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HEAD
riscv64: Add RISC-V target
[platform/upstream/openblas.git]
/
Makefile.riscv64
1
ifeq ($(CORE), C910V)
2
CCOMMON_OPT += -march=rv64imafdcv0p7_zfh_xtheadc -mabi=lp64d -mtune=c920
3
FCOMMON_OPT += -march=rv64imafdcv0p7_zfh_xtheadc -mabi=lp64d -mtune=c920 -static
4
endif