i965_DeriveImage() support JPEG color formats

Signed-off-by: Zhong Li <zhong.li@intel.com>
(cherry picked from commit 9f9c505ed5212ae0704f71f45532b9716ac0bd51)

1.3.2.pre1 for development

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Intel driver 1.3.1

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Update NEWS

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Return error when trying to decoding an interlaced VC-1 video

https://bugs.freedesktop.org/show_bug.cgi?id=77386

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>

Make it buildable against libva 1.3.0

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>

Fix over assigned callback "QueryConfigEntrypoints".

VPP: Enable Skin tone detection and enhancement - Added STDE coefficients.

In this commit, I added the optimized STDE coefficients to the vebox state table.
(cherry picked from commit 150f67c67bd92cd201b75a92388fe3a63b00cd8a)

VPP: Enable Skin Tone Detection and Enhancement feature in the driver.

The VPP-STDE feature is enabled in the driver code for gen75 and gen8.
In this commit, I added the filter and made appropriate changes to the
hw_codec_info and the supporting methods.
(cherry picked from commit 691b149b7afe578889a423841a29db3ac56aad83)

vp8: fix support for segmentation-enabled streams.

If segmentation is enabled, then the segmentation map shall be live
across frames until the current frame updates the segment ids. This
means that the driver needs to maintain the segmentation map buffer
allocation and enable writes (resp. reads) whenever necessary.

This fixes decoding of 00-comprehensive-010.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

VPP: Set the alpha channel when doing the conversion from NV12 to RGBA on Ivy/Haswell/BDW

Currently zero is written to alpha channel when doing the conversion
from NV12 to RGBA(BGRA), which affects the following the rendering operation.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 4082c9db1eef45bc117fc151d60a178926ab9f73)

Fix bound checking

Otherwise it might result in buffer overflow.

Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 782b8afdda14f000874d8acf51c3e8c490d55773)

Rendering/BDW:Follow the hardware spec to update the 3DSTATE_URB_VS command

This is to fix the GPU hang when doing the color-space conversion from
NV12 to RGB on BDW GT3 machine.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 4a3f17ae44bae58daf65dcc706332b28a6d478ac)

vp8: fix loop filter for bitexact reconstruction.

Each loop filter delta update value shall be encoded within 7 bits,
including the sign bit and 6-bit magnitude in 2's complement. So,
don't propagate the sign bit while packing the filter level values.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit 36ccd9c3e47766edc70ecbdf82acc89ed67e26c4)

BDW: Fix one error in shader binaray for media encoding

The commit 7ac4263ff2dae5c877b92356d04df4ccfe10d7c9 updates
the shader binary more than it required. So it is removed.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit b1319c7f7cb9d20179b20dac2308330bd0e51ffe)

V3: Add 422H support.

Changes between V3 to V2:
1. Add 422H support into gen8_post_processing.c, according to
   yakui's comments.

changes between V2 and V1:
1. Rebase on staging branch.
2. Add 422H support for pp.
3. Reword the commit title.
Signed-off-by: Alex wu <zhiwen.wu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 347dd731d31dd37b242bbace744125554f2c09e7)

Use the VA_FOURCC_ABCD constant to replace the VA_FOURCC(A,B,C,D)

This is helpful to avoid the typo error when using VA_FOURCC(A, B, C, D).

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit acea969011bceee36a57fe2c0e4ee96c0c5e79c7)

VEBOX: Use the VA_FOURCC_ABCD constant to replace the VA_FOURCC(A,B,C,D)

This is helpful to avoid the typo error when using VA_FOURCC(A, B, C, D).

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
--
 src/gen75_vpp_vebox.c |   83 ++++++++++++++++++++++++--------------------------
 1 file changed, 41 insertions(+), 42 deletions(-)

(cherry picked from commit 2a31ad7e200cfb5df95b11875ee33795cdc7e343)

VPP: Use the VA_FOURCC_ABCD constant to replace the VA_FOURCC(A,B,C,D)

This is helpful to avoid the typo error when using VA_FOURCC(A, B, C, D).

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 0b9ed6ad9fbe46812d566fa31bf6d60739757a17)

Conflicts:
src/i965_post_processing.c

Use the VA_FOURCC_XXXX to replace the VA_FOURCC(X,X,X,X) in i965_drv_video

This is helpful to avoid the typo error when using VA_FOURCC(A, B, C, D).

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit ab3e02d63fe672e3f81631f2beb5bc2b7ab17af0)

Fix for check i965_check_alloc_surface_bo ret

Signed-off-by: Zhao Halley <halley.zhao@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 41da810decbb2d64843b95384fc87f7a29152c88)

clean up some assert in i965_drv_video.c

a return value is expected when assert is disabled.

Signed-off-by: Zhao Halley <halley.zhao@intel.com>
(cherry picked from commit 12c81227fd92fe028100af0cb32cc17b7f698b3d)

va: User specified tiling and stride support.

It is done by two VASurfaceAttrib:
 * one is buffer attribute described by VASurfaceAttribExternalBufferDescriptor.
   it covers strides and tiling or not.
 * another is buffer type to indicate that the buffer is allocated by va driver.
   VASurfaceAttribMemoryType:VA_SURFACE_ATTRIB_MEM_TYPE_VA

Signed-off-by: Zhao Halley <halley.zhao@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 55e63685dc040e3855868b4d7ccb0ac8e1f66690)

VPP: Fix the typo error of "VV16"

It should be "YV16" instead of "VV16".
Thank Gwenole for capturing this typo error which is caused by
the commit 2b5fad11a5c12d3c6ffbef15c02449a3b4e90b98.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit abd77ff2014322d152d723a3e8b1cba1e41b0a5f)

Add the csc conversion from YV16 to NV12

V1->V2: Follow Zhiwen's comment to handle the scenario of CSC conversion from
YV16 to NV12  when the source is YV16 image instead of YV16 surface.

Reviewed-by: Wind Yuan <feng.yuan@intel.com>
Tested-by: Wind Yuan <feng.yuan@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 2b5fad11a5c12d3c6ffbef15c02449a3b4e90b98)

Add the support of derive image from YV16 surface

Reviewed-by: Wind Yuan <feng.yuan@intel.com>
Tested-by: Wind Yuan <feng.yuan@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 7d5172de91336db2e627c0011404231b6b64b211)

Export the surface attribute based on YV16 for VPP on Gen7+

Reviewed-by: Wind Yuan <feng.yuan@intel.com>
Tested-by: Wind Yuan <feng.yuan@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 94f415b29ee197f66281370801a9c3bd4240c928)

Add the support of create surface based on YV16 format

Reviewed-by: Wind Yuan <feng.yuan@intel.com>
Tested-by: Wind Yuan <feng.yuan@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 12e7421ce1ed2627270dcb281af4d760afeb7209)

Add the seperated file for Video post-processing on BDW

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 6e1baecded9d23b32daa8e34828b6a5d32a27c46)

Conflicts:
src/i965_post_processing.c

Use the XXX_post_processing as callback function for post-processing

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit b7da102c3d237ac5553f8c8ada1bb155e5b8ea75)

Add the seperated file for rendering on BDW

This is to avoid the interference between the new platform and previous
platform.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit fbd6b7ff33ed5beb15f0122ec70668ed0c8479d2)

Use the XXX_render_put_surface/put_subpicture as callback function for rendering

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 9db92268b7b7bf6763ae76df0021608effe260ec)

Define i965_DestroySurfaces in header file explicitly to avoid multiple declaration

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit af0687252bfc6f81ff5361feedba7ec8989b3555)

BDW: Follow the spec to add the MEDIA_STATE_FLUSH before MEDIA_INTERFACE_LOAD

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit a90acbe7f08d66084e70113859198c3975f63b80)

bdw: Follow the spec to update the PIPE_CONTROL command

This is the hardware requirement.

Signed-off-by: Zhao Yakui <Yakui.zhao@intel.com>
(cherry picked from commit fc4d39f3b849366ed04223620fa371d76cf813b0)

bdw: Fix the FENCE message in GPU shader for H264 encoding

Use the real register as write_back register instead of NULL register
although the Fence Message doesn't touch it.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 7ac4263ff2dae5c877b92356d04df4ccfe10d7c9)

1.3.1.pre1 for development

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Intel driver 1.3.0

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Fix the broken package made by 'make dist'

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Fix broken make dist

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Bump version to 1.3.0.pre1

To build the code, a new version of VA-API is needed, so
update the dependency on VA-API as well

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Update NEWS

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

configure.ac: update the dependency on intel-gen4asm

The new version of intel-gen4asm is required to build shaders
for BDW

Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

intel-vaapi: Add more checks for H264 decoding parameter to filter the unsupported clip

Signed-off-by: Yuan Feng <feng.yuan@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Remove the redundant if () from gen8_pp_upload_constants

This fixed the issue reported by Klockwork

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Warning fixes

gen8_mfd.c: In function ‘gen8_mfd_vp8_decode_init’:
gen8_mfd.c:2773:5: warning: implicit declaration of function ‘intel_update_vp8_frame_store_index’ [-Wimplicit-function-declaration]

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Don't use assert() in case getting wrong parameters from user

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Fix the wrong setting in MI_BATCH_BATCH_START command on Snb/Ivy/Haswell

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Use the right parameters to initialize bit rate context

Reported-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Don't advertise CBR for MPEG-2 encoding

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Fix vp8 partition offset set error

Signed-off-by: Zhong Li <zhong.li@intel.com>

Fix vp8 p frame decode error issue.

Signed-off-by: Zhong Li <zhong.li@intel.com>

vp8 dec: fix when bool_coder_ctx.count is 0

bool_coder_ctx.count is remaining bits,
hw requires used-bits-count: 8-bool_coder_ctx.count, range [0,7]
update offset and partition_size[0] as well

Signed-off-by: Zhao Halley <halley.zhao@intel.com>

vp8 dec: follows va_dec_vp8.h update

    key_frame:0 means an intra frame
    bool_coder_ctx.count is the remaining bits in bool_coder_ctx.value, range[0,7)
    slice_data_offset/macroblock_offset update

Signed-off-by: Zhao Halley <halley.zhao@intel.com>

Remove the unnecessary sorting to simplify the DPB buffer management

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Complain the warning instead of assert fault when slice picture is not found in DPB for decoder

This is to fix the bug https://bugs.freedesktop.org/show_bug.cgi?id=72660

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

VPP: Correct return value of vpp gpe functions

Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>

Remove the whitespace following trailing backslash in a Makefile.am

src/shaders/post_processing/gen8/Makefile.am:31: whitespace following trailing backslash
src/shaders/post_processing/gen8/Makefile.am:32: whitespace following trailing backslash

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Enable sharpening feature on BDW

Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>

VPP: Refine code for sharpening on Haswell

Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>

VEBOX/bdw: set downsample method

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VEBOX/bdw: DW0-DW8 are used for dndi parameters in VEBOX_DNDI_STATE

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Add one environment variable to check the benchmark of decoding/vaPutsurface

The swap_buffer callback will wait for the completion of buffer swap, which
will affect the benchmark test of decoding/vaPutSurface.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Render/BDW: Align each offset with 64 bytes

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Render/BDW: Initialize the blend_state for rendering

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Render/HSW: Fix the bug caused by merging code

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Update the MFX_AVC_IMAGE_STATE to follow the spec

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Fix the incorrect MV upper bound setting of MFC_IND_OBJ_BASE_ADDRESS_STAE for encoding on gen8

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Fix the wrong VPP initialization function for Dn/DI on Ivybridge

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Add the VPP shader of conversion between YUY2 and YUY2 on BDW

Signed-off-by: Zhao Yakui <yakui.zhao2intel.com>

Use the pp_null_initialize function for the unsupported VPP on BDW

The Dn/DI will be implemented by using VEBOX and doesn't use the VPP shader any more.
So the corresponding VPP shader should use the pp_null_initialize hook function.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Fix the error for the VPP conversion of NV12->NV12 on BDW

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Use the correct sub-context for VPP on BDW to avoid the NULL pointer

The structure of sub-context is updated for VPP in the commit of
4faf6bf47f8e4e2fe587e3bb6a004340edd59c4c. So BDW should update the correct
sub-context.Otherwise the segment fault will be triggered.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Add the support of querying the surface attributes on BDW

Otherwise the user-space application doesn't query which surfaceformat is
supported by the libva-vappi driver on BDW.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Fix the wrong pitch of surface for Video post-processing on BDW

Now the object surface already contains the pitch after the object surface
structure is reworked in the commit f886f24eaaacba9544fa5f6405b7382c686f3a1f.
So it is unnecessary to calculate the pitch based on the width.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Follow the spec to make the VPP media pipeline work in 48-bit addressing mode

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Fix the error of offset calculation for encoding on BDW

Currently although the encoding can work well, the offset in the internal
object is calculated incorrectly. So fix it to avoid the potential issue.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

VPP/bdw: Fix the initialize function used for NV12 to NV12

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Add the ring supported for bdw vpp filters

Signed-off-by: Zhong Li <zhong.li@intel.com>

Fix a bug of vp8 quant index calculation error

Signed-off-by: Zhong Li <zhong.li@intel.com>

Remove the unused function of gen7_pp_rgbx_avs_initialize

This is not used any more after it uses the same gen7_pp_plx_avs_initialize
function for RGBX input on Ivy/Haswell.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Configure VPP parameter for RGBX input so that Haswell/Ivy uses the same gen7_pp_plx_avs_initialize

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Update the supported render target format and pixel format for JPEG on BDW

This is picked up from the commit a90e80fb7fde114535ab5e9be74d973117def138
on Ivy/Haswell. Otherwise the JPEG on BDW can't work as expected.

Signed-off-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Add the support of color BT709/SMPTE240M for color-space conversion on BDW

This is picked up from that on Haswell/Ivybridge.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Add the support of brightness/contrast/hue/saturation for BDW rendering

This is picked up from the commit 04ecb6e79f4382d96eb5d4b51733049d420f592a

Signed-off-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Fix the error in render shader for subpicture

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Fix the error in render shader for BDW

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Explicitly declare the color blend operation for subpicture on BDW

Without this it still can work. This is only human-readable.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Fix the incorrect setting for subpicture on BDW

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

BDW encoding reuses aux_batchbuffer instead of allocating another new buffer

This is picked up from that on Haswell/Ivybridge.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Calculate required space of batch buffer to avoid buffer overflow in encoding on BDW

The required size is based on the number of macroblocks and slice parameter.
Then it can avoid that too large buffer is allocated or possible overflow.
This is picked up from that on Haswell/Ivybridge.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Handle the aux_batchbuffer correctly for H264 encoding on Haswell

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Follow spec to update the URB entry/size setting for encoding on Haswell/BDW

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Rendering/bdw: fix push constant buffer for PS

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

BDW doesn't support H.264 Baseline profile

The similar fix to f765987

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Follow the spec to make the 3D pipeline work in 48-bit addressing mode

Signed-off-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

follow the spec to fill the Vertex URB entry on BDW

Signed-off-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Add the missing 3D pipeline command for rendering on BDW

Signed-off-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Follow the spec to restrict the max number of PS thread

Signed-off-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Enable the Intra-prediction for MPEG2 P-B frame on BDW

This is picked up from the implementation on Haswell/Ivybridge.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>