batch->intel = intel;
batch->flag = flag;
batch->run = drm_intel_bo_mrb_exec;
+
+ if (IS_GEN6(intel->device_id) &&
+ flag == I915_EXEC_RENDER)
+ batch->wa_render_bo = dri_bo_alloc(intel->bufmgr,
+ "wa scratch",
+ 4096,
+ 4096);
+ else
+ batch->wa_render_bo = NULL;
+
intel_batchbuffer_reset(batch, buffer_size);
return batch;
}
dri_bo_unreference(batch->buffer);
+ dri_bo_unreference(batch->wa_render_bo);
free(batch);
}
if (IS_GEN6(intel->device_id) ||
IS_GEN7(intel->device_id)) {
if (batch->flag == I915_EXEC_RENDER) {
- BEGIN_BATCH(batch, 4);
- OUT_BATCH(batch, CMD_PIPE_CONTROL | 0x2);
-
- if (IS_GEN6(intel->device_id))
- OUT_BATCH(batch,
+ if (IS_GEN6(intel->device_id)) {
+ assert(batch->wa_render_bo);
+
+ BEGIN_BATCH(batch, 4 * 3);
+
+ OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2));
+ OUT_BATCH(batch,
+ CMD_PIPE_CONTROL_CS_STALL |
+ CMD_PIPE_CONTROL_STALL_AT_SCOREBOARD);
+ OUT_BATCH(batch, 0); /* address */
+ OUT_BATCH(batch, 0); /* write data */
+
+ OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2));
+ OUT_BATCH(batch, CMD_PIPE_CONTROL_WRITE_QWORD);
+ OUT_RELOC(batch,
+ batch->wa_render_bo,
+ I915_GEM_DOMAIN_INSTRUCTION,
+ I915_GEM_DOMAIN_INSTRUCTION,
+ 0);
+ OUT_BATCH(batch, 0); /* write data */
+
+ /* now finally the _real flush */
+ OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2));
+ OUT_BATCH(batch,
CMD_PIPE_CONTROL_WC_FLUSH |
CMD_PIPE_CONTROL_TC_FLUSH |
CMD_PIPE_CONTROL_NOWRITE);
- else
+ } else {
+ BEGIN_BATCH(batch, 4);
+ OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2));
+
OUT_BATCH(batch,
CMD_PIPE_CONTROL_WC_FLUSH |
CMD_PIPE_CONTROL_TC_FLUSH |
CMD_PIPE_CONTROL_DC_FLUSH |
CMD_PIPE_CONTROL_NOWRITE);
+ }
- OUT_BATCH(batch, 0);
- OUT_BATCH(batch, 0);
+ OUT_BATCH(batch, 0); /* write address */
+ OUT_BATCH(batch, 0); /* write data */
ADVANCE_BATCH(batch);
} else {
if (batch->flag == I915_EXEC_BLT) {
#define BR13_8888 (0x3 << 24)
#define CMD_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24) | (0 << 16))
+#define CMD_PIPE_CONTROL_CS_STALL (1 << 20)
#define CMD_PIPE_CONTROL_NOWRITE (0 << 14)
#define CMD_PIPE_CONTROL_WRITE_QWORD (1 << 14)
#define CMD_PIPE_CONTROL_WRITE_DEPTH (2 << 14)
#define CMD_PIPE_CONTROL_DC_FLUSH (1 << 5)
#define CMD_PIPE_CONTROL_GLOBAL_GTT (1 << 2)
#define CMD_PIPE_CONTROL_LOCAL_PGTT (0 << 2)
+#define CMD_PIPE_CONTROL_STALL_AT_SCOREBOARD (1 << 1)
#define CMD_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0)