src/intel_driver.h

   1 #ifndef _INTEL_DRIVER_H_
   2 #define _INTEL_DRIVER_H_
   3
   4 #include <stddef.h>
   5 #include <pthread.h>
   6 #include <signal.h>
   7 #include <stdbool.h>
   8
   9 #include <drm.h>
  10 #include <i915_drm.h>
  11 #include <intel_bufmgr.h>
  12
  13 #include <va/va_backend.h>
  14 #include "va_backend_compat.h"
  15
  16 #include "intel_compiler.h"
  17
  18 #define BATCH_SIZE      0x80000
  19 #define BATCH_RESERVED  0x10
  20
  21 #define CMD_MI                                  (0x0 << 29)
  22 #define CMD_2D                                  (0x2 << 29)
  23 #define CMD_3D                                  (0x3 << 29)
  24
  25 #define MI_NOOP                                 (CMD_MI | 0)
  26
  27 #define MI_BATCH_BUFFER_END                     (CMD_MI | (0xA << 23))
  28 #define MI_BATCH_BUFFER_START                   (CMD_MI | (0x31 << 23))
  29
  30 #define MI_FLUSH                                (CMD_MI | (0x4 << 23))
  31 #define   MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE   (0x1 << 0)
  32
  33 #define MI_FLUSH_DW                             (CMD_MI | (0x26 << 23) | 0x2)
  34 #define   MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE   (0x1 << 7)
  35
  36 #define XY_COLOR_BLT_CMD                        (CMD_2D | (0x50 << 22) | 0x04)
  37 #define XY_COLOR_BLT_WRITE_ALPHA                (1 << 21)
  38 #define XY_COLOR_BLT_WRITE_RGB                  (1 << 20)
  39 #define XY_COLOR_BLT_DST_TILED                  (1 << 11)
  40
  41 #define GEN8_XY_COLOR_BLT_CMD                   (CMD_2D | (0x50 << 22) | 0x05)
  42
  43 /* BR13 */
  44 #define BR13_8                                  (0x0 << 24)
  45 #define BR13_565                                (0x1 << 24)
  46 #define BR13_1555                               (0x2 << 24)
  47 #define BR13_8888                               (0x3 << 24)
  48
  49 #define CMD_PIPE_CONTROL                        (CMD_3D | (3 << 27) | (2 << 24) | (0 << 16))
  50 #define CMD_PIPE_CONTROL_CS_STALL               (1 << 20)
  51 #define CMD_PIPE_CONTROL_NOWRITE                (0 << 14)
  52 #define CMD_PIPE_CONTROL_WRITE_QWORD            (1 << 14)
  53 #define CMD_PIPE_CONTROL_WRITE_DEPTH            (2 << 14)
  54 #define CMD_PIPE_CONTROL_WRITE_TIME             (3 << 14)
  55 #define CMD_PIPE_CONTROL_DEPTH_STALL            (1 << 13)
  56 #define CMD_PIPE_CONTROL_WC_FLUSH               (1 << 12)
  57 #define CMD_PIPE_CONTROL_IS_FLUSH               (1 << 11)
  58 #define CMD_PIPE_CONTROL_TC_FLUSH               (1 << 10)
  59 #define CMD_PIPE_CONTROL_NOTIFY_ENABLE          (1 << 8)
  60 #define CMD_PIPE_CONTROL_DC_FLUSH               (1 << 5)
  61 #define CMD_PIPE_CONTROL_GLOBAL_GTT             (1 << 2)
  62 #define CMD_PIPE_CONTROL_LOCAL_PGTT             (0 << 2)
  63 #define CMD_PIPE_CONTROL_STALL_AT_SCOREBOARD    (1 << 1)
  64 #define CMD_PIPE_CONTROL_DEPTH_CACHE_FLUSH      (1 << 0)
  65
  66
  67 struct intel_batchbuffer;
  68
  69 #define ALIGN(i, n)    (((i) + (n) - 1) & ~((n) - 1))
  70 #define IS_ALIGNED(i, n) (((i) & ((n)-1)) == 0)
  71 #define MIN(a, b) ((a) < (b) ? (a) : (b))
  72 #define MAX(a, b) ((a) > (b) ? (a) : (b))
  73 #define ARRAY_ELEMS(a) (sizeof(a) / sizeof((a)[0]))
  74
  75 #define Bool int
  76 #define True 1
  77 #define False 0
  78
  79 #define ASSERT_RET(value, fail_ret) do {    \
  80         if (!(value)) {                 \
  81             assert(0);                      \
  82             return fail_ret;                \
  83         }                                   \
  84     } while (0)
  85
  86 #define SET_BLOCKED_SIGSET()   do {     \
  87         sigset_t bl_mask;               \
  88         sigfillset(&bl_mask);           \
  89         sigdelset(&bl_mask, SIGFPE);    \
  90         sigdelset(&bl_mask, SIGILL);    \
  91         sigdelset(&bl_mask, SIGSEGV);   \
  92         sigdelset(&bl_mask, SIGBUS);    \
  93         sigdelset(&bl_mask, SIGKILL);   \
  94         pthread_sigmask(SIG_SETMASK, &bl_mask, &intel->sa_mask); \
  95     } while (0)
  96
  97 #define RESTORE_BLOCKED_SIGSET() do {    \
  98         pthread_sigmask(SIG_SETMASK, &intel->sa_mask, NULL); \
  99     } while (0)
 100
 101 #define PPTHREAD_MUTEX_LOCK() do {             \
 102         SET_BLOCKED_SIGSET();                  \
 103         pthread_mutex_lock(&intel->ctxmutex);       \
 104     } while (0)
 105
 106 #define PPTHREAD_MUTEX_UNLOCK() do {           \
 107         pthread_mutex_unlock(&intel->ctxmutex);     \
 108         RESTORE_BLOCKED_SIGSET();              \
 109     } while (0)
 110
 111 #define WARN_ONCE(...) do {                     \
 112         static int g_once = 1;                  \
 113         if (g_once) {                           \
 114             g_once = 0;                         \
 115             printf("WARNING: " __VA_ARGS__);    \
 116         }                                       \
 117     } while (0)
 118
 119 struct intel_device_info
 120 {
 121     int gen;
 122     int gt;
 123
 124     unsigned int urb_size;
 125     unsigned int max_wm_threads;
 126
 127     unsigned int is_g4x         : 1; /* gen4 */
 128     unsigned int is_ivybridge   : 1; /* gen7 */
 129     unsigned int is_baytrail    : 1; /* gen7 */
 130     unsigned int is_haswell     : 1; /* gen7 */
 131 };
 132
 133 struct intel_driver_data
 134 {
 135     int fd;
 136     int device_id;
 137     int revision;
 138
 139     int dri2Enabled;
 140
 141     sigset_t sa_mask;
 142     pthread_mutex_t ctxmutex;
 143     int locked;
 144
 145     dri_bufmgr *bufmgr;
 146
 147     unsigned int has_exec2  : 1; /* Flag: has execbuffer2? */
 148     unsigned int has_bsd    : 1; /* Flag: has bitstream decoder for H.264? */
 149     unsigned int has_blt    : 1; /* Flag: has BLT unit? */
 150     unsigned int has_vebox  : 1; /* Flag: has VEBOX unit */
 151
 152     const struct intel_device_info *device_info;
 153 };
 154
 155 bool intel_driver_init(VADriverContextP ctx);
 156 void intel_driver_terminate(VADriverContextP ctx);
 157
 158 static INLINE struct intel_driver_data *
 159 intel_driver_data(VADriverContextP ctx)
 160 {
 161     return (struct intel_driver_data *)ctx->pDriverData;
 162 }
 163
 164 struct intel_region
 165 {
 166     int x;
 167     int y;
 168     unsigned int width;
 169     unsigned int height;
 170     unsigned int cpp;
 171     unsigned int pitch;
 172     unsigned int tiling;
 173     unsigned int swizzle;
 174     dri_bo *bo;
 175 };
 176
 177 #define PCI_CHIP_GM45_GM                0x2A42
 178 #define PCI_CHIP_IGD_E_G                0x2E02
 179 #define PCI_CHIP_Q45_G                  0x2E12
 180 #define PCI_CHIP_G45_G                  0x2E22
 181 #define PCI_CHIP_G41_G                  0x2E32
 182 #define PCI_CHIP_B43_G                  0x2E42
 183 #define PCI_CHIP_B43_G1                 0x2E92
 184
 185 #define PCI_CHIP_IRONLAKE_D_G           0x0042
 186 #define PCI_CHIP_IRONLAKE_M_G           0x0046
 187
 188 #ifndef PCI_CHIP_SANDYBRIDGE_GT1
 189 #define PCI_CHIP_SANDYBRIDGE_GT1        0x0102  /* Desktop */
 190 #define PCI_CHIP_SANDYBRIDGE_GT2        0x0112
 191 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS   0x0122
 192 #define PCI_CHIP_SANDYBRIDGE_M_GT1      0x0106  /* Mobile */
 193 #define PCI_CHIP_SANDYBRIDGE_M_GT2      0x0116
 194 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
 195 #define PCI_CHIP_SANDYBRIDGE_S_GT       0x010A  /* Server */
 196 #endif
 197
 198 #define PCI_CHIP_IVYBRIDGE_GT1          0x0152  /* Desktop */
 199 #define PCI_CHIP_IVYBRIDGE_GT2          0x0162
 200 #define PCI_CHIP_IVYBRIDGE_M_GT1        0x0156  /* Mobile */
 201 #define PCI_CHIP_IVYBRIDGE_M_GT2        0x0166
 202 #define PCI_CHIP_IVYBRIDGE_S_GT1        0x015a  /* Server */
 203 #define PCI_CHIP_IVYBRIDGE_S_GT2        0x016a
 204
 205 #define PCI_CHIP_HASWELL_GT1            0x0402 /* Desktop */
 206 #define PCI_CHIP_HASWELL_GT2            0x0412
 207 #define PCI_CHIP_HASWELL_GT3            0x0422
 208 #define PCI_CHIP_HASWELL_M_GT1          0x0406 /* Mobile */
 209 #define PCI_CHIP_HASWELL_M_GT2          0x0416
 210 #define PCI_CHIP_HASWELL_M_GT3          0x0426
 211 #define PCI_CHIP_HASWELL_S_GT1          0x040a /* Server */
 212 #define PCI_CHIP_HASWELL_S_GT2          0x041a
 213 #define PCI_CHIP_HASWELL_S_GT3          0x042a
 214 #define PCI_CHIP_HASWELL_B_GT1          0x040b /* Reserved */
 215 #define PCI_CHIP_HASWELL_B_GT2          0x041b
 216 #define PCI_CHIP_HASWELL_B_GT3          0x042b
 217 #define PCI_CHIP_HASWELL_E_GT1          0x040e /* Reserved */
 218 #define PCI_CHIP_HASWELL_E_GT2          0x041e
 219 #define PCI_CHIP_HASWELL_E_GT3          0x042e
 220
 221 #define PCI_CHIP_HASWELL_SDV_GT1                0x0c02 /* Desktop */
 222 #define PCI_CHIP_HASWELL_SDV_GT2                0x0c12
 223 #define PCI_CHIP_HASWELL_SDV_GT3                0x0c22
 224 #define PCI_CHIP_HASWELL_SDV_M_GT1              0x0c06 /* Mobile */
 225 #define PCI_CHIP_HASWELL_SDV_M_GT2              0x0c16
 226 #define PCI_CHIP_HASWELL_SDV_M_GT3              0x0c26
 227 #define PCI_CHIP_HASWELL_SDV_S_GT1              0x0c0a /* Server */
 228 #define PCI_CHIP_HASWELL_SDV_S_GT2              0x0c1a
 229 #define PCI_CHIP_HASWELL_SDV_S_GT3              0x0c2a
 230 #define PCI_CHIP_HASWELL_SDV_B_GT1              0x0c0b /* Reserved */
 231 #define PCI_CHIP_HASWELL_SDV_B_GT2              0x0c1b
 232 #define PCI_CHIP_HASWELL_SDV_B_GT3              0x0c2b
 233 #define PCI_CHIP_HASWELL_SDV_E_GT1              0x0c0e /* Reserved */
 234 #define PCI_CHIP_HASWELL_SDV_E_GT2              0x0c1e
 235 #define PCI_CHIP_HASWELL_SDV_E_GT3              0x0c2e
 236
 237 #define PCI_CHIP_HASWELL_ULT_GT1                0x0A02 /* Desktop */
 238 #define PCI_CHIP_HASWELL_ULT_GT2                0x0A12
 239 #define PCI_CHIP_HASWELL_ULT_GT3                0x0A22
 240 #define PCI_CHIP_HASWELL_ULT_M_GT1              0x0A06 /* Mobile */
 241 #define PCI_CHIP_HASWELL_ULT_M_GT2              0x0A16
 242 #define PCI_CHIP_HASWELL_ULT_M_GT3              0x0A26
 243 #define PCI_CHIP_HASWELL_ULT_S_GT1              0x0A0A /* Server */
 244 #define PCI_CHIP_HASWELL_ULT_S_GT2              0x0A1A
 245 #define PCI_CHIP_HASWELL_ULT_S_GT3              0x0A2A
 246 #define PCI_CHIP_HASWELL_ULT_B_GT1              0x0A0B /* Reserved */
 247 #define PCI_CHIP_HASWELL_ULT_B_GT2              0x0A1B
 248 #define PCI_CHIP_HASWELL_ULT_B_GT3              0x0A2B
 249 #define PCI_CHIP_HASWELL_ULT_E_GT1              0x0A0E /* Reserved */
 250 #define PCI_CHIP_HASWELL_ULT_E_GT2              0x0A1E
 251 #define PCI_CHIP_HASWELL_ULT_E_GT3              0x0A2E
 252
 253 #define PCI_CHIP_HASWELL_CRW_GT1                0x0D02 /* Desktop */
 254 #define PCI_CHIP_HASWELL_CRW_GT2                0x0D12
 255 #define PCI_CHIP_HASWELL_CRW_GT3                0x0D22
 256 #define PCI_CHIP_HASWELL_CRW_M_GT1              0x0D06 /* Mobile */
 257 #define PCI_CHIP_HASWELL_CRW_M_GT2              0x0D16
 258 #define PCI_CHIP_HASWELL_CRW_M_GT3              0x0D26
 259 #define PCI_CHIP_HASWELL_CRW_S_GT1              0x0D0A /* Server */
 260 #define PCI_CHIP_HASWELL_CRW_S_GT2              0x0D1A
 261 #define PCI_CHIP_HASWELL_CRW_S_GT3              0x0D2A
 262 #define PCI_CHIP_HASWELL_CRW_B_GT1              0x0D0B /* Reserved */
 263 #define PCI_CHIP_HASWELL_CRW_B_GT2              0x0D1B
 264 #define PCI_CHIP_HASWELL_CRW_B_GT3              0x0D2B
 265 #define PCI_CHIP_HASWELL_CRW_E_GT1              0x0D0E /* Reserved */
 266 #define PCI_CHIP_HASWELL_CRW_E_GT2              0x0D1E
 267 #define PCI_CHIP_HASWELL_CRW_E_GT3              0x0D2E
 268
 269 #define PCI_CHIP_BAYTRAIL_M_1           0x0F31
 270 #define PCI_CHIP_BAYTRAIL_M_2           0x0F32
 271 #define PCI_CHIP_BAYTRAIL_M_3           0x0F33
 272 #define PCI_CHIP_BAYTRAIL_M_4           0x0157
 273 #define PCI_CHIP_BAYTRAIL_D             0x0155
 274
 275 #define PCI_CHIP_BROADWELL_MS_GT1       0x1602
 276 #define PCI_CHIP_BROADWELL_MS_GT2       0x1612
 277 #define PCI_CHIP_BROADWELL_MS_GT2PLUS   0x1622
 278
 279 #define PCI_CHIP_BROADWELL_M_GT1_1      0x1606
 280 #define PCI_CHIP_BROADWELL_M_GT2_1      0x1616
 281 #define PCI_CHIP_BROADWELL_M_GT2PLUS_1  0x1626
 282
 283 #define PCI_CHIP_BROADWELL_M_GT1_2      0x160B
 284 #define PCI_CHIP_BROADWELL_M_GT2_2      0x161B
 285 #define PCI_CHIP_BROADWELL_M_GT2PLUS_2  0x162B
 286
 287 #define PCI_CHIP_BROADWELL_M_GT1_3      0x160E
 288 #define PCI_CHIP_BROADWELL_M_GT2_3      0x161E
 289 #define PCI_CHIP_BROADWELL_M_GT2PLUS_3  0x162E
 290
 291 #define PCI_CHIP_BROADWELL_D_GT1_1      0x160A
 292 #define PCI_CHIP_BROADWELL_D_GT2_1      0x161A
 293 #define PCI_CHIP_BROADWELL_D_GT2PLUS_1  0x162A
 294
 295 #define PCI_CHIP_BROADWELL_D_GT1_2      0x160D
 296 #define PCI_CHIP_BROADWELL_D_GT2_2      0x161D
 297 #define PCI_CHIP_BROADWELL_D_GT2PLUS_2  0x162D
 298
 299 #define IS_G45(devid)           (devid == PCI_CHIP_IGD_E_G ||   \
 300                                  devid == PCI_CHIP_Q45_G ||     \
 301                                  devid == PCI_CHIP_G45_G ||     \
 302                                  devid == PCI_CHIP_G41_G ||     \
 303                                  devid == PCI_CHIP_B43_G ||     \
 304                                  devid == PCI_CHIP_B43_G1)
 305
 306 #define IS_GM45(devid)          (devid == PCI_CHIP_GM45_GM)
 307 #define IS_G4X(devid)           (IS_G45(devid) || IS_GM45(devid))
 308
 309 #define IS_IRONLAKE_D(devid)    (devid == PCI_CHIP_IRONLAKE_D_G)
 310 #define IS_IRONLAKE_M(devid)    (devid == PCI_CHIP_IRONLAKE_M_G)
 311 #define IS_IRONLAKE(devid)      (IS_IRONLAKE_D(devid) || IS_IRONLAKE_M(devid))
 312
 313 #define IS_SNB_GT1(devid)       (devid == PCI_CHIP_SANDYBRIDGE_GT1 ||   \
 314                                  devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
 315                                  devid == PCI_CHIP_SANDYBRIDGE_S_GT)
 316
 317 #define IS_SNB_GT2(devid)       (devid == PCI_CHIP_SANDYBRIDGE_GT2 ||   \
 318                                  devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
 319                                  devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
 320                                  devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS)
 321
 322 #define IS_GEN6(devid)          (IS_SNB_GT1(devid) ||   \
 323                                  IS_SNB_GT2(devid))
 324
 325 #define IS_BAYTRAIL_M1(devid)    (devid == PCI_CHIP_BAYTRAIL_M_1)
 326 #define IS_BAYTRAIL_M2(devid)    (devid == PCI_CHIP_BAYTRAIL_M_2)
 327 #define IS_BAYTRAIL_M3(devid)    (devid == PCI_CHIP_BAYTRAIL_M_3)
 328 #define IS_BAYTRAIL_D(devid)     (devid == PCI_CHIP_BAYTRAIL_D)
 329 #define IS_BAYTRAIL(devid)       (IS_BAYTRAIL_M1(devid) || \
 330                                   IS_BAYTRAIL_M2(devid) || \
 331                                   IS_BAYTRAIL_M3(devid) || \
 332                                   IS_BAYTRAIL_D(devid) )
 333
 334 #define IS_IVB_GT1(devid)       (devid == PCI_CHIP_IVYBRIDGE_GT1 ||     \
 335                                  devid == PCI_CHIP_IVYBRIDGE_M_GT1 ||   \
 336                                  devid == PCI_CHIP_IVYBRIDGE_S_GT1)
 337
 338 #define IS_IVB_GT2(devid)       (devid == PCI_CHIP_IVYBRIDGE_GT2 ||     \
 339                                  devid == PCI_CHIP_IVYBRIDGE_M_GT2 ||   \
 340                                  devid == PCI_CHIP_IVYBRIDGE_S_GT2)
 341
 342 #define IS_IVYBRIDGE(devid)     (IS_IVB_GT1(devid) ||   \
 343                                  IS_IVB_GT2(devid) ||   \
 344                                  IS_BAYTRAIL(devid) )
 345
 346 #define IS_HSW_GT1(devid)       (devid == PCI_CHIP_HASWELL_GT1          || \
 347                                  devid == PCI_CHIP_HASWELL_M_GT1        || \
 348                                  devid == PCI_CHIP_HASWELL_S_GT1        || \
 349                                  devid == PCI_CHIP_HASWELL_B_GT1        || \
 350                                  devid == PCI_CHIP_HASWELL_E_GT1        || \
 351                                  devid == PCI_CHIP_HASWELL_SDV_GT1      || \
 352                                  devid == PCI_CHIP_HASWELL_SDV_M_GT1    || \
 353                                  devid == PCI_CHIP_HASWELL_SDV_S_GT1    || \
 354                                  devid == PCI_CHIP_HASWELL_SDV_B_GT1    || \
 355                                  devid == PCI_CHIP_HASWELL_SDV_E_GT1    || \
 356                                  devid == PCI_CHIP_HASWELL_CRW_GT1      || \
 357                                  devid == PCI_CHIP_HASWELL_CRW_M_GT1    || \
 358                                  devid == PCI_CHIP_HASWELL_CRW_S_GT1    || \
 359                                  devid == PCI_CHIP_HASWELL_CRW_B_GT1    || \
 360                                  devid == PCI_CHIP_HASWELL_CRW_E_GT1    || \
 361                                  devid == PCI_CHIP_HASWELL_ULT_GT1      || \
 362                                  devid == PCI_CHIP_HASWELL_ULT_M_GT1    || \
 363                                  devid == PCI_CHIP_HASWELL_ULT_S_GT1    || \
 364                                  devid == PCI_CHIP_HASWELL_ULT_B_GT1    || \
 365                                  devid == PCI_CHIP_HASWELL_ULT_E_GT1)
 366
 367
 368 #define IS_HSW_GT2(devid)       (devid == PCI_CHIP_HASWELL_GT2||        \
 369                                  devid == PCI_CHIP_HASWELL_M_GT2||      \
 370                                  devid == PCI_CHIP_HASWELL_S_GT2||      \
 371                                  devid == PCI_CHIP_HASWELL_B_GT2 || \
 372                                  devid == PCI_CHIP_HASWELL_E_GT2 || \
 373                                  devid == PCI_CHIP_HASWELL_SDV_GT2||    \
 374                                  devid == PCI_CHIP_HASWELL_SDV_M_GT2||  \
 375                                  devid == PCI_CHIP_HASWELL_SDV_S_GT2||  \
 376                                  devid == PCI_CHIP_HASWELL_SDV_B_GT2 || \
 377                                  devid == PCI_CHIP_HASWELL_SDV_E_GT2 || \
 378                                  devid == PCI_CHIP_HASWELL_CRW_GT2||    \
 379                                  devid == PCI_CHIP_HASWELL_CRW_M_GT2||  \
 380                                  devid == PCI_CHIP_HASWELL_CRW_S_GT2||  \
 381                                  devid == PCI_CHIP_HASWELL_CRW_B_GT2|| \
 382                                  devid == PCI_CHIP_HASWELL_CRW_E_GT2|| \
 383                                  devid == PCI_CHIP_HASWELL_ULT_GT2||    \
 384                                  devid == PCI_CHIP_HASWELL_ULT_M_GT2||  \
 385                                  devid == PCI_CHIP_HASWELL_ULT_S_GT2||  \
 386                                  devid == PCI_CHIP_HASWELL_ULT_B_GT2 || \
 387                                  devid == PCI_CHIP_HASWELL_ULT_E_GT2)
 388
 389
 390 #define IS_HSW_GT3(devid)       (devid == PCI_CHIP_HASWELL_GT3          || \
 391                                  devid == PCI_CHIP_HASWELL_M_GT3        || \
 392                                  devid == PCI_CHIP_HASWELL_S_GT3        || \
 393                                  devid == PCI_CHIP_HASWELL_B_GT3        || \
 394                                  devid == PCI_CHIP_HASWELL_E_GT3        || \
 395                                  devid == PCI_CHIP_HASWELL_SDV_GT3      || \
 396                                  devid == PCI_CHIP_HASWELL_SDV_M_GT3    || \
 397                                  devid == PCI_CHIP_HASWELL_SDV_S_GT3    || \
 398                                  devid == PCI_CHIP_HASWELL_SDV_B_GT3    || \
 399                                  devid == PCI_CHIP_HASWELL_SDV_E_GT3    || \
 400                                  devid == PCI_CHIP_HASWELL_CRW_GT3      || \
 401                                  devid == PCI_CHIP_HASWELL_CRW_M_GT3    || \
 402                                  devid == PCI_CHIP_HASWELL_CRW_S_GT3    || \
 403                                  devid == PCI_CHIP_HASWELL_CRW_B_GT3    || \
 404                                  devid == PCI_CHIP_HASWELL_CRW_E_GT3    || \
 405                                  devid == PCI_CHIP_HASWELL_ULT_GT3      || \
 406                                  devid == PCI_CHIP_HASWELL_ULT_M_GT3    || \
 407                                  devid == PCI_CHIP_HASWELL_ULT_S_GT3    || \
 408                                  devid == PCI_CHIP_HASWELL_ULT_B_GT3    || \
 409                                  devid == PCI_CHIP_HASWELL_ULT_E_GT3)
 410
 411 #define IS_HASWELL(devid)       (IS_HSW_GT1(devid) || \
 412                                  IS_HSW_GT2(devid) || \
 413                                  IS_HSW_GT3(devid))
 414
 415 #define IS_GEN7(devid)          (IS_IVYBRIDGE(devid) || \
 416                                  IS_HASWELL(devid))
 417
 418
 419 #define IS_BDW_GT1(devid)       (devid == PCI_CHIP_BROADWELL_M_GT1_1 || \
 420                                  devid == PCI_CHIP_BROADWELL_M_GT1_2 || \
 421                                  devid == PCI_CHIP_BROADWELL_M_GT1_3 || \
 422                                  devid == PCI_CHIP_BROADWELL_D_GT1_1 || \
 423                                  devid == PCI_CHIP_BROADWELL_D_GT1_2 || \
 424                                  devid == PCI_CHIP_BROADWELL_MS_GT1)
 425
 426 #define IS_BDW_GT2(devid)       (devid == PCI_CHIP_BROADWELL_M_GT2_1 || \
 427                                  devid == PCI_CHIP_BROADWELL_M_GT2_2 || \
 428                                  devid == PCI_CHIP_BROADWELL_M_GT2_3 || \
 429                                  devid == PCI_CHIP_BROADWELL_D_GT2_1 || \
 430                                  devid == PCI_CHIP_BROADWELL_D_GT2_2 || \
 431                                  devid == PCI_CHIP_BROADWELL_MS_GT2)
 432
 433 #define IS_BDW_GT2PLUS(devid)   (devid == PCI_CHIP_BROADWELL_M_GT2PLUS_1 || \
 434                                  devid == PCI_CHIP_BROADWELL_M_GT2PLUS_2 || \
 435                                  devid == PCI_CHIP_BROADWELL_M_GT2PLUS_3 || \
 436                                  devid == PCI_CHIP_BROADWELL_D_GT2PLUS_1 || \
 437                                  devid == PCI_CHIP_BROADWELL_D_GT2PLUS_2 || \
 438                                  devid == PCI_CHIP_BROADWELL_MS_GT2PLUS)
 439
 440 #define IS_GEN8(devid)          (IS_BDW_GT1(devid) ||   \
 441                                  IS_BDW_GT2(devid) ||   \
 442                                  IS_BDW_GT2PLUS(devid))
 443
 444 #endif /* _INTEL_DRIVER_H_ */