src/gen75_vme.c

   1 /*
   2  * Copyright © 2010-2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhao Yakui <yakui.zhao@intel.com>
  26  *    Xiang Haihao <haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include "sysdeps.h"
  31
  32 #include "intel_batchbuffer.h"
  33 #include "intel_driver.h"
  34
  35 #include "i965_defines.h"
  36 #include "i965_drv_video.h"
  37 #include "i965_encoder.h"
  38 #include "gen6_vme.h"
  39 #include "gen6_mfc.h"
  40
  41 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  42 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  43 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  44
  45 #define SURFACE_STATE_PADDED_SIZE_0_GEN6        ALIGN(sizeof(struct i965_surface_state), 32)
  46 #define SURFACE_STATE_PADDED_SIZE_1_GEN6        ALIGN(sizeof(struct i965_surface_state2), 32)
  47 #define SURFACE_STATE_PADDED_SIZE_GEN6          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN6, SURFACE_STATE_PADDED_SIZE_1_GEN6)
  48
  49 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
  50 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  51 #define BINDING_TABLE_OFFSET(index)             (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
  52
  53 #define VME_INTRA_SHADER        0
  54 #define VME_INTER_SHADER        1
  55 #define VME_BINTER_SHADER       3
  56 #define VME_BATCHBUFFER         2
  57
  58 #define CURBE_ALLOCATION_SIZE   37              /* in 256-bit */
  59 #define CURBE_TOTAL_DATA_LENGTH (4 * 32)        /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */
  60 #define CURBE_URB_ENTRY_LENGTH  4               /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */
  61
  62 #define VME_MSG_LENGTH          32
  63
  64 static const uint32_t gen75_vme_intra_frame[][4] = {
  65 #include "shaders/vme/intra_frame_haswell.g75b"
  66 };
  67
  68 static const uint32_t gen75_vme_inter_frame[][4] = {
  69 #include "shaders/vme/inter_frame_haswell.g75b"
  70 };
  71
  72 static const uint32_t gen75_vme_inter_bframe[][4] = {
  73 #include "shaders/vme/inter_bframe_haswell.g75b"
  74 };
  75
  76 static const uint32_t gen75_vme_batchbuffer[][4] = {
  77 #include "shaders/vme/batchbuffer.g75b"
  78 };
  79
  80 static struct i965_kernel gen75_vme_kernels[] = {
  81     {
  82         "VME Intra Frame",
  83         VME_INTRA_SHADER, /*index*/
  84         gen75_vme_intra_frame,
  85         sizeof(gen75_vme_intra_frame),
  86         NULL
  87     },
  88     {
  89         "VME inter Frame",
  90         VME_INTER_SHADER,
  91         gen75_vme_inter_frame,
  92         sizeof(gen75_vme_inter_frame),
  93         NULL
  94     },
  95     {
  96         "VME BATCHBUFFER",
  97         VME_BATCHBUFFER,
  98         gen75_vme_batchbuffer,
  99         sizeof(gen75_vme_batchbuffer),
 100         NULL
 101     },
 102     {
 103         "VME inter BFrame",
 104         VME_BINTER_SHADER,
 105         gen75_vme_inter_bframe,
 106         sizeof(gen75_vme_inter_bframe),
 107         NULL
 108     }
 109 };
 110
 111 static const uint32_t gen75_vme_mpeg2_intra_frame[][4] = {
 112 #include "shaders/vme/intra_frame_haswell.g75b"
 113 };
 114
 115 static const uint32_t gen75_vme_mpeg2_inter_frame[][4] = {
 116 #include "shaders/vme/mpeg2_inter_haswell.g75b"
 117 };
 118
 119 static const uint32_t gen75_vme_mpeg2_batchbuffer[][4] = {
 120 #include "shaders/vme/batchbuffer.g75b"
 121 };
 122
 123 static struct i965_kernel gen75_vme_mpeg2_kernels[] = {
 124     {
 125         "VME Intra Frame",
 126         VME_INTRA_SHADER, /*index*/
 127         gen75_vme_mpeg2_intra_frame,
 128         sizeof(gen75_vme_mpeg2_intra_frame),
 129         NULL
 130     },
 131     {
 132         "VME inter Frame",
 133         VME_INTER_SHADER,
 134         gen75_vme_mpeg2_inter_frame,
 135         sizeof(gen75_vme_mpeg2_inter_frame),
 136         NULL
 137     },
 138     {
 139         "VME BATCHBUFFER",
 140         VME_BATCHBUFFER,
 141         gen75_vme_mpeg2_batchbuffer,
 142         sizeof(gen75_vme_mpeg2_batchbuffer),
 143         NULL
 144     },
 145 };
 146
 147 /* only used for VME source surface state */
 148 static void
 149 gen75_vme_source_surface_state(VADriverContextP ctx,
 150                                int index,
 151                                struct object_surface *obj_surface,
 152                                struct intel_encoder_context *encoder_context)
 153 {
 154     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 155
 156     vme_context->vme_surface2_setup(ctx,
 157                                     &vme_context->gpe_context,
 158                                     obj_surface,
 159                                     BINDING_TABLE_OFFSET(index),
 160                                     SURFACE_STATE_OFFSET(index));
 161 }
 162
 163 static void
 164 gen75_vme_media_source_surface_state(VADriverContextP ctx,
 165                                      int index,
 166                                      struct object_surface *obj_surface,
 167                                      struct intel_encoder_context *encoder_context)
 168 {
 169     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 170
 171     vme_context->vme_media_rw_surface_setup(ctx,
 172                                             &vme_context->gpe_context,
 173                                             obj_surface,
 174                                             BINDING_TABLE_OFFSET(index),
 175                                             SURFACE_STATE_OFFSET(index));
 176 }
 177
 178 static void
 179 gen75_vme_media_chroma_source_surface_state(VADriverContextP ctx,
 180                                             int index,
 181                                             struct object_surface *obj_surface,
 182                                             struct intel_encoder_context *encoder_context)
 183 {
 184     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 185
 186     vme_context->vme_media_chroma_surface_setup(ctx,
 187                                                 &vme_context->gpe_context,
 188                                                 obj_surface,
 189                                                 BINDING_TABLE_OFFSET(index),
 190                                                 SURFACE_STATE_OFFSET(index));
 191 }
 192
 193 static void
 194 gen75_vme_output_buffer_setup(VADriverContextP ctx,
 195                               struct encode_state *encode_state,
 196                               int index,
 197                               struct intel_encoder_context *encoder_context)
 198
 199 {
 200     struct i965_driver_data *i965 = i965_driver_data(ctx);
 201     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 202     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 203     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 204     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 205     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 206     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 207
 208     vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
 209     vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
 210
 211     if (is_intra)
 212         vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 2;
 213     else
 214         vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 24;
 215     /*
 216      * Inter MV . 32-byte Intra search + 16 IME info + 128 IME MV + 32 IME Ref
 217      * + 16 FBR Info + 128 FBR MV + 32 FBR Ref.
 218      * 16 * (2 + 2 * (1 + 8 + 2))= 16 * 24.
 219      */
 220
 221     vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
 222                                               "VME output buffer",
 223                                               vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
 224                                               0x1000);
 225     assert(vme_context->vme_output.bo);
 226     vme_context->vme_buffer_suface_setup(ctx,
 227                                          &vme_context->gpe_context,
 228                                          &vme_context->vme_output,
 229                                          BINDING_TABLE_OFFSET(index),
 230                                          SURFACE_STATE_OFFSET(index));
 231 }
 232
 233 static void
 234 gen75_vme_output_vme_batchbuffer_setup(VADriverContextP ctx,
 235                                        struct encode_state *encode_state,
 236                                        int index,
 237                                        struct intel_encoder_context *encoder_context)
 238
 239 {
 240     struct i965_driver_data *i965 = i965_driver_data(ctx);
 241     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 242     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 243     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 244     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 245
 246     vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
 247     vme_context->vme_batchbuffer.size_block = 64; /* 4 OWORDs */
 248     vme_context->vme_batchbuffer.pitch = 16;
 249     vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
 250                                                    "VME batchbuffer",
 251                                                    vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
 252                                                    0x1000);
 253     vme_context->vme_buffer_suface_setup(ctx,
 254                                          &vme_context->gpe_context,
 255                                          &vme_context->vme_batchbuffer,
 256                                          BINDING_TABLE_OFFSET(index),
 257                                          SURFACE_STATE_OFFSET(index));
 258 }
 259
 260 static VAStatus
 261 gen75_vme_surface_setup(VADriverContextP ctx,
 262                         struct encode_state *encode_state,
 263                         int is_intra,
 264                         struct intel_encoder_context *encoder_context)
 265 {
 266     struct object_surface *obj_surface;
 267     struct i965_driver_data *i965 = i965_driver_data(ctx);
 268
 269     /*Setup surfaces state*/
 270     /* current picture for encoding */
 271     obj_surface = encode_state->input_yuv_object;
 272     gen75_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
 273     gen75_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
 274     gen75_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context);
 275
 276     if (!is_intra) {
 277         VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 278         int slice_type;
 279         struct object_surface *slice_obj_surface;
 280         int ref_surface_id;
 281
 282         slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
 283
 284         if (slice_type == SLICE_TYPE_P || slice_type == SLICE_TYPE_B) {
 285             slice_obj_surface = NULL;
 286             ref_surface_id = slice_param->RefPicList0[0].picture_id;
 287             if (ref_surface_id != VA_INVALID_SURFACE) {
 288                 slice_obj_surface = SURFACE(ref_surface_id);
 289             }
 290             if (slice_obj_surface && slice_obj_surface->bo) {
 291                 obj_surface = slice_obj_surface;
 292             } else {
 293                 obj_surface = encode_state->reference_objects[0];
 294             }
 295             /* reference 0 */
 296             if (obj_surface && obj_surface->bo)
 297                 gen75_vme_source_surface_state(ctx, 1, obj_surface, encoder_context);
 298         }
 299         if (slice_type == SLICE_TYPE_B) {
 300             /* reference 1 */
 301             slice_obj_surface = NULL;
 302             ref_surface_id = slice_param->RefPicList1[0].picture_id;
 303             if (ref_surface_id != VA_INVALID_SURFACE) {
 304                 slice_obj_surface = SURFACE(ref_surface_id);
 305             }
 306             if (slice_obj_surface && slice_obj_surface->bo) {
 307                 obj_surface = slice_obj_surface;
 308             } else {
 309                 obj_surface = encode_state->reference_objects[1];
 310             }
 311
 312             if (obj_surface && obj_surface->bo)
 313                 gen75_vme_source_surface_state(ctx, 2, obj_surface, encoder_context);
 314         }
 315     }
 316
 317     /* VME output */
 318     gen75_vme_output_buffer_setup(ctx, encode_state, 3, encoder_context);
 319     gen75_vme_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
 320
 321     return VA_STATUS_SUCCESS;
 322 }
 323
 324 static VAStatus gen75_vme_interface_setup(VADriverContextP ctx,
 325                                           struct encode_state *encode_state,
 326                                           struct intel_encoder_context *encoder_context)
 327 {
 328     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 329     struct gen6_interface_descriptor_data *desc;
 330     int i;
 331     dri_bo *bo;
 332
 333     bo = vme_context->gpe_context.idrt.bo;
 334     dri_bo_map(bo, 1);
 335     assert(bo->virtual);
 336     desc = bo->virtual;
 337
 338     for (i = 0; i < vme_context->vme_kernel_sum; i++) {
 339         struct i965_kernel *kernel;
 340         kernel = &vme_context->gpe_context.kernels[i];
 341         assert(sizeof(*desc) == 32);
 342         /*Setup the descritor table*/
 343         memset(desc, 0, sizeof(*desc));
 344         desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
 345         desc->desc2.sampler_count = 0; /* FIXME: */
 346         desc->desc2.sampler_state_pointer = 0;
 347         desc->desc3.binding_table_entry_count = 1; /* FIXME: */
 348         desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
 349         desc->desc4.constant_urb_entry_read_offset = 0;
 350         desc->desc4.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH;
 351
 352         /*kernel start*/
 353         dri_bo_emit_reloc(bo,
 354                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 355                           0,
 356                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
 357                           kernel->bo);
 358         desc++;
 359     }
 360     dri_bo_unmap(bo);
 361
 362     return VA_STATUS_SUCCESS;
 363 }
 364
 365 static VAStatus gen75_vme_constant_setup(VADriverContextP ctx,
 366                                          struct encode_state *encode_state,
 367                                          struct intel_encoder_context *encoder_context)
 368 {
 369     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 370     unsigned char *constant_buffer;
 371     unsigned int *vme_state_message;
 372     int mv_num = 32;
 373
 374     vme_state_message = (unsigned int *)vme_context->vme_state_message;
 375
 376     if (encoder_context->codec == CODEC_H264) {
 377         if (vme_context->h264_level >= 30) {
 378             mv_num = 16;
 379
 380             if (vme_context->h264_level >= 31)
 381                 mv_num = 8;
 382         }
 383     } else if (encoder_context->codec == CODEC_MPEG2) {
 384         mv_num = 2;
 385     }
 386
 387     vme_state_message[31] = mv_num;
 388
 389     dri_bo_map(vme_context->gpe_context.curbe.bo, 1);
 390     assert(vme_context->gpe_context.curbe.bo->virtual);
 391     constant_buffer = vme_context->gpe_context.curbe.bo->virtual;
 392
 393     /* VME MV/Mb cost table is passed by using const buffer */
 394     /* Now it uses the fixed search path. So it is constructed directly
 395      * in the GPU shader.
 396      */
 397     memcpy(constant_buffer, (char *)vme_context->vme_state_message, 128);
 398
 399     dri_bo_unmap(vme_context->gpe_context.curbe.bo);
 400
 401     return VA_STATUS_SUCCESS;
 402 }
 403
 404 static const unsigned int intra_mb_mode_cost_table[] = {
 405     0x31110001, // for qp0
 406     0x09110001, // for qp1
 407     0x15030001, // for qp2
 408     0x0b030001, // for qp3
 409     0x0d030011, // for qp4
 410     0x17210011, // for qp5
 411     0x41210011, // for qp6
 412     0x19210011, // for qp7
 413     0x25050003, // for qp8
 414     0x1b130003, // for qp9
 415     0x1d130003, // for qp10
 416     0x27070021, // for qp11
 417     0x51310021, // for qp12
 418     0x29090021, // for qp13
 419     0x35150005, // for qp14
 420     0x2b0b0013, // for qp15
 421     0x2d0d0013, // for qp16
 422     0x37170007, // for qp17
 423     0x61410031, // for qp18
 424     0x39190009, // for qp19
 425     0x45250015, // for qp20
 426     0x3b1b000b, // for qp21
 427     0x3d1d000d, // for qp22
 428     0x47270017, // for qp23
 429     0x71510041, // for qp24 ! center for qp=0..30
 430     0x49290019, // for qp25
 431     0x55350025, // for qp26
 432     0x4b2b001b, // for qp27
 433     0x4d2d001d, // for qp28
 434     0x57370027, // for qp29
 435     0x81610051, // for qp30
 436     0x57270017, // for qp31
 437     0x81510041, // for qp32 ! center for qp=31..51
 438     0x59290019, // for qp33
 439     0x65350025, // for qp34
 440     0x5b2b001b, // for qp35
 441     0x5d2d001d, // for qp36
 442     0x67370027, // for qp37
 443     0x91610051, // for qp38
 444     0x69390029, // for qp39
 445     0x75450035, // for qp40
 446     0x6b3b002b, // for qp41
 447     0x6d3d002d, // for qp42
 448     0x77470037, // for qp43
 449     0xa1710061, // for qp44
 450     0x79490039, // for qp45
 451     0x85550045, // for qp46
 452     0x7b4b003b, // for qp47
 453     0x7d4d003d, // for qp48
 454     0x87570047, // for qp49
 455     0xb1810071, // for qp50
 456     0x89590049  // for qp51
 457 };
 458
 459 static void gen75_vme_state_setup_fixup(VADriverContextP ctx,
 460                                         struct encode_state *encode_state,
 461                                         struct intel_encoder_context *encoder_context,
 462                                         unsigned int *vme_state_message)
 463 {
 464     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 465     VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 466     VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 467
 468     if (slice_param->slice_type != SLICE_TYPE_I &&
 469         slice_param->slice_type != SLICE_TYPE_SI)
 470         return;
 471     if (encoder_context->rate_control_mode == VA_RC_CQP)
 472         vme_state_message[0] = intra_mb_mode_cost_table[pic_param->pic_init_qp + slice_param->slice_qp_delta];
 473     else
 474         vme_state_message[0] = intra_mb_mode_cost_table[mfc_context->bit_rate_control_context[SLICE_TYPE_I].QpPrimeY];
 475 }
 476
 477 static VAStatus gen75_vme_vme_state_setup(VADriverContextP ctx,
 478                                           struct encode_state *encode_state,
 479                                           int is_intra,
 480                                           struct intel_encoder_context *encoder_context)
 481 {
 482     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 483     unsigned int *vme_state_message;
 484     int i;
 485
 486     //pass the MV/Mb cost into VME message on HASWell
 487     assert(vme_context->vme_state_message);
 488     vme_state_message = (unsigned int *)vme_context->vme_state_message;
 489
 490     vme_state_message[0] = 0x4a4a4a4a;
 491     vme_state_message[1] = 0x4a4a4a4a;
 492     vme_state_message[2] = 0x4a4a4a4a;
 493     vme_state_message[3] = 0x22120200;
 494     vme_state_message[4] = 0x62524232;
 495
 496     for (i=5; i < 8; i++) {
 497         vme_state_message[i] = 0;
 498     }
 499
 500     switch (encoder_context->codec) {
 501     case CODEC_H264:
 502         gen75_vme_state_setup_fixup(ctx, encode_state, encoder_context, vme_state_message);
 503
 504         break;
 505
 506     default:
 507         /* no fixup */
 508         break;
 509     }
 510
 511     return VA_STATUS_SUCCESS;
 512 }
 513
 514 static void
 515 gen75_vme_fill_vme_batchbuffer(VADriverContextP ctx,
 516                                struct encode_state *encode_state,
 517                                int mb_width, int mb_height,
 518                                int kernel,
 519                                int transform_8x8_mode_flag,
 520                                struct intel_encoder_context *encoder_context)
 521 {
 522     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 523     int mb_x = 0, mb_y = 0;
 524     int i, s;
 525     unsigned int *command_ptr;
 526
 527     dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
 528     command_ptr = vme_context->vme_batchbuffer.bo->virtual;
 529
 530     for (s = 0; s < encode_state->num_slice_params_ext; s++) {
 531         VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
 532         int slice_mb_begin = pSliceParameter->macroblock_address;
 533         int slice_mb_number = pSliceParameter->num_macroblocks;
 534         unsigned int mb_intra_ub;
 535         int slice_mb_x = pSliceParameter->macroblock_address % mb_width;
 536         for (i = 0; i < slice_mb_number;  ) {
 537             int mb_count = i + slice_mb_begin;
 538             mb_x = mb_count % mb_width;
 539             mb_y = mb_count / mb_width;
 540             mb_intra_ub = 0;
 541             if (mb_x != 0) {
 542                 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
 543             }
 544             if (mb_y != 0) {
 545                 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
 546                 if (mb_x != 0)
 547                     mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
 548                 if (mb_x != (mb_width -1))
 549                     mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
 550             }
 551             if (i < mb_width) {
 552                 if (i == 0)
 553                     mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_AE);
 554                 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_BCD_MASK);
 555                 if ((i == (mb_width - 1)) && slice_mb_x) {
 556                     mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
 557                 }
 558             }
 559
 560             if ((i == mb_width) && slice_mb_x) {
 561                 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_D);
 562             }
 563             *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
 564             *command_ptr++ = kernel;
 565             *command_ptr++ = 0;
 566             *command_ptr++ = 0;
 567             *command_ptr++ = 0;
 568             *command_ptr++ = 0;
 569
 570             /*inline data */
 571             *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
 572             *command_ptr++ = ( (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
 573
 574             i += 1;
 575         }
 576     }
 577
 578     *command_ptr++ = 0;
 579     *command_ptr++ = MI_BATCH_BUFFER_END;
 580
 581     dri_bo_unmap(vme_context->vme_batchbuffer.bo);
 582 }
 583
 584 static void gen75_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 585 {
 586     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 587
 588     i965_gpe_context_init(ctx, &vme_context->gpe_context);
 589
 590     /* VME output buffer */
 591     dri_bo_unreference(vme_context->vme_output.bo);
 592     vme_context->vme_output.bo = NULL;
 593
 594     dri_bo_unreference(vme_context->vme_batchbuffer.bo);
 595     vme_context->vme_batchbuffer.bo = NULL;
 596
 597     /* VME state */
 598     dri_bo_unreference(vme_context->vme_state.bo);
 599     vme_context->vme_state.bo = NULL;
 600 }
 601
 602 static void gen75_vme_pipeline_programing(VADriverContextP ctx,
 603                                           struct encode_state *encode_state,
 604                                           struct intel_encoder_context *encoder_context)
 605 {
 606     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 607     struct intel_batchbuffer *batch = encoder_context->base.batch;
 608     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 609     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 610     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 611     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 612     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 613     int kernel_shader;
 614     bool allow_hwscore = true;
 615     int s;
 616
 617     for (s = 0; s < encode_state->num_slice_params_ext; s++) {
 618         pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
 619         if ((pSliceParameter->macroblock_address % width_in_mbs)) {
 620             allow_hwscore = false;
 621             break;
 622         }
 623     }
 624     if ((pSliceParameter->slice_type == SLICE_TYPE_I) ||
 625         (pSliceParameter->slice_type == SLICE_TYPE_I)) {
 626         kernel_shader = VME_INTRA_SHADER;
 627     } else if ((pSliceParameter->slice_type == SLICE_TYPE_P) ||
 628                (pSliceParameter->slice_type == SLICE_TYPE_SP)) {
 629         kernel_shader = VME_INTER_SHADER;
 630     } else {
 631         kernel_shader = VME_BINTER_SHADER;
 632         if (!allow_hwscore)
 633             kernel_shader = VME_INTER_SHADER;
 634     }
 635     if (allow_hwscore)
 636         gen7_vme_walker_fill_vme_batchbuffer(ctx,
 637                                              encode_state,
 638                                              width_in_mbs, height_in_mbs,
 639                                              kernel_shader,
 640                                              pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
 641                                              encoder_context);
 642     else
 643         gen75_vme_fill_vme_batchbuffer(ctx,
 644                                        encode_state,
 645                                        width_in_mbs, height_in_mbs,
 646                                        kernel_shader,
 647                                        pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
 648                                        encoder_context);
 649
 650     intel_batchbuffer_start_atomic(batch, 0x1000);
 651     gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
 652     BEGIN_BATCH(batch, 2);
 653     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
 654     OUT_RELOC(batch,
 655               vme_context->vme_batchbuffer.bo,
 656               I915_GEM_DOMAIN_COMMAND, 0,
 657               0);
 658     ADVANCE_BATCH(batch);
 659
 660     intel_batchbuffer_end_atomic(batch);
 661 }
 662
 663 static VAStatus gen75_vme_prepare(VADriverContextP ctx,
 664                                   struct encode_state *encode_state,
 665                                   struct intel_encoder_context *encoder_context)
 666 {
 667     VAStatus vaStatus = VA_STATUS_SUCCESS;
 668     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 669     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 670     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 671     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 672
 673     if (!vme_context->h264_level ||
 674         (vme_context->h264_level != pSequenceParameter->level_idc)) {
 675         vme_context->h264_level = pSequenceParameter->level_idc;
 676     }
 677
 678     intel_vme_update_mbmv_cost(ctx, encode_state, encoder_context);
 679
 680     /*Setup all the memory object*/
 681     gen75_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
 682     gen75_vme_interface_setup(ctx, encode_state, encoder_context);
 683     //gen75_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context);
 684     gen75_vme_constant_setup(ctx, encode_state, encoder_context);
 685
 686     /*Programing media pipeline*/
 687     gen75_vme_pipeline_programing(ctx, encode_state, encoder_context);
 688
 689     return vaStatus;
 690 }
 691
 692 static VAStatus gen75_vme_run(VADriverContextP ctx,
 693                               struct encode_state *encode_state,
 694                               struct intel_encoder_context *encoder_context)
 695 {
 696     struct intel_batchbuffer *batch = encoder_context->base.batch;
 697
 698     intel_batchbuffer_flush(batch);
 699
 700     return VA_STATUS_SUCCESS;
 701 }
 702
 703 static VAStatus gen75_vme_stop(VADriverContextP ctx,
 704                                struct encode_state *encode_state,
 705                                struct intel_encoder_context *encoder_context)
 706 {
 707     return VA_STATUS_SUCCESS;
 708 }
 709
 710 static VAStatus
 711 gen75_vme_pipeline(VADriverContextP ctx,
 712                    VAProfile profile,
 713                    struct encode_state *encode_state,
 714                    struct intel_encoder_context *encoder_context)
 715 {
 716     gen75_vme_media_init(ctx, encoder_context);
 717     gen75_vme_prepare(ctx, encode_state, encoder_context);
 718     gen75_vme_run(ctx, encode_state, encoder_context);
 719     gen75_vme_stop(ctx, encode_state, encoder_context);
 720
 721     return VA_STATUS_SUCCESS;
 722 }
 723
 724 static void
 725 gen75_vme_mpeg2_output_buffer_setup(VADriverContextP ctx,
 726                                     struct encode_state *encode_state,
 727                                     int index,
 728                                     int is_intra,
 729                                     struct intel_encoder_context *encoder_context)
 730
 731 {
 732     struct i965_driver_data *i965 = i965_driver_data(ctx);
 733     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 734     VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
 735     int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
 736     int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
 737
 738     vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
 739     vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
 740
 741     if (is_intra)
 742         vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 2;
 743     else
 744         vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 24;
 745     /*
 746      * Inter MV . 32-byte Intra search + 16 IME info + 128 IME MV + 32 IME Ref
 747      * + 16 FBR Info + 128 FBR MV + 32 FBR Ref.
 748      * 16 * (2 + 2 * (1 + 8 + 2))= 16 * 24.
 749      */
 750
 751     vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
 752                                               "VME output buffer",
 753                                               vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
 754                                               0x1000);
 755     assert(vme_context->vme_output.bo);
 756     vme_context->vme_buffer_suface_setup(ctx,
 757                                          &vme_context->gpe_context,
 758                                          &vme_context->vme_output,
 759                                          BINDING_TABLE_OFFSET(index),
 760                                          SURFACE_STATE_OFFSET(index));
 761 }
 762
 763 static void
 764 gen75_vme_mpeg2_output_vme_batchbuffer_setup(VADriverContextP ctx,
 765                                              struct encode_state *encode_state,
 766                                              int index,
 767                                              struct intel_encoder_context *encoder_context)
 768
 769 {
 770     struct i965_driver_data *i965 = i965_driver_data(ctx);
 771     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 772     VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
 773     int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
 774     int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
 775
 776     vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
 777     vme_context->vme_batchbuffer.size_block = 64; /* 4 OWORDs */
 778     vme_context->vme_batchbuffer.pitch = 16;
 779     vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
 780                                                    "VME batchbuffer",
 781                                                    vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
 782                                                    0x1000);
 783     vme_context->vme_buffer_suface_setup(ctx,
 784                                          &vme_context->gpe_context,
 785                                          &vme_context->vme_batchbuffer,
 786                                          BINDING_TABLE_OFFSET(index),
 787                                          SURFACE_STATE_OFFSET(index));
 788 }
 789
 790 static VAStatus
 791 gen75_vme_mpeg2_surface_setup(VADriverContextP ctx,
 792                               struct encode_state *encode_state,
 793                               int is_intra,
 794                               struct intel_encoder_context *encoder_context)
 795 {
 796     struct object_surface *obj_surface;
 797
 798     /*Setup surfaces state*/
 799     /* current picture for encoding */
 800     obj_surface = encode_state->input_yuv_object;
 801     gen75_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
 802     gen75_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
 803     gen75_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context);
 804
 805     if (!is_intra) {
 806         /* reference 0 */
 807         obj_surface = encode_state->reference_objects[0];
 808         if (obj_surface->bo != NULL)
 809             gen75_vme_source_surface_state(ctx, 1, obj_surface, encoder_context);
 810
 811         /* reference 1 */
 812         obj_surface = encode_state->reference_objects[1];
 813         if (obj_surface && obj_surface->bo != NULL)
 814             gen75_vme_source_surface_state(ctx, 2, obj_surface, encoder_context);
 815     }
 816
 817     /* VME output */
 818     gen75_vme_mpeg2_output_buffer_setup(ctx, encode_state, 3, is_intra, encoder_context);
 819     gen75_vme_mpeg2_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
 820
 821     return VA_STATUS_SUCCESS;
 822 }
 823
 824 static void
 825 gen75_vme_mpeg2_fill_vme_batchbuffer(VADriverContextP ctx,
 826                                      struct encode_state *encode_state,
 827                                      int mb_width, int mb_height,
 828                                      int kernel,
 829                                      int transform_8x8_mode_flag,
 830                                      struct intel_encoder_context *encoder_context)
 831 {
 832     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 833     int mb_x = 0, mb_y = 0;
 834     int i, s, j;
 835     unsigned int *command_ptr;
 836
 837
 838     dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
 839     command_ptr = vme_context->vme_batchbuffer.bo->virtual;
 840
 841     for (s = 0; s < encode_state->num_slice_params_ext; s++) {
 842         VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer;
 843
 844         for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) {
 845             int slice_mb_begin = slice_param->macroblock_address;
 846             int slice_mb_number = slice_param->num_macroblocks;
 847             unsigned int mb_intra_ub;
 848             int slice_mb_x = slice_param->macroblock_address % mb_width;
 849
 850             for (i = 0; i < slice_mb_number;) {
 851                 int mb_count = i + slice_mb_begin;
 852
 853                 mb_x = mb_count % mb_width;
 854                 mb_y = mb_count / mb_width;
 855                 mb_intra_ub = 0;
 856
 857                 if (mb_x != 0) {
 858                     mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
 859                 }
 860
 861                 if (mb_y != 0) {
 862                     mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
 863
 864                     if (mb_x != 0)
 865                         mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
 866
 867                     if (mb_x != (mb_width -1))
 868                         mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
 869                 }
 870
 871                 if (i < mb_width) {
 872                     if (i == 0)
 873                         mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_AE);
 874
 875                     mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_BCD_MASK);
 876
 877                     if ((i == (mb_width - 1)) && slice_mb_x) {
 878                         mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
 879                     }
 880                 }
 881
 882                 if ((i == mb_width) && slice_mb_x) {
 883                     mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_D);
 884                 }
 885
 886                 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
 887                 *command_ptr++ = kernel;
 888                 *command_ptr++ = 0;
 889                 *command_ptr++ = 0;
 890                 *command_ptr++ = 0;
 891                 *command_ptr++ = 0;
 892
 893                 /*inline data */
 894                 *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
 895                 *command_ptr++ = ( (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
 896
 897                 i += 1;
 898             }
 899
 900             slice_param++;
 901         }
 902     }
 903
 904     *command_ptr++ = 0;
 905     *command_ptr++ = MI_BATCH_BUFFER_END;
 906
 907     dri_bo_unmap(vme_context->vme_batchbuffer.bo);
 908 }
 909
 910 static void
 911 gen75_vme_mpeg2_pipeline_programing(VADriverContextP ctx,
 912                                     struct encode_state *encode_state,
 913                                     int is_intra,
 914                                     struct intel_encoder_context *encoder_context)
 915 {
 916     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 917     struct intel_batchbuffer *batch = encoder_context->base.batch;
 918     VAEncPictureParameterBufferMPEG2 *pic_param = NULL;
 919     VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
 920     int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
 921     int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
 922     bool allow_hwscore = true;
 923     int s;
 924     int kernel_shader;
 925
 926     pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer;
 927
 928     for (s = 0; s < encode_state->num_slice_params_ext; s++) {
 929         int j;
 930         VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer;
 931
 932         for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) {
 933             if (slice_param->macroblock_address % width_in_mbs) {
 934                 allow_hwscore = false;
 935                 break;
 936             }
 937         }
 938     }
 939
 940     pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer;
 941     if (pic_param->picture_type == VAEncPictureTypeIntra) {
 942         allow_hwscore = false;
 943         kernel_shader = VME_INTRA_SHADER;
 944     } else {
 945         kernel_shader = VME_INTER_SHADER;
 946     }
 947
 948     if (allow_hwscore)
 949         gen7_vme_mpeg2_walker_fill_vme_batchbuffer(ctx,
 950                                                    encode_state,
 951                                                    width_in_mbs, height_in_mbs,
 952                                                    kernel_shader,
 953                                                    encoder_context);
 954     else
 955         gen75_vme_mpeg2_fill_vme_batchbuffer(ctx,
 956                                              encode_state,
 957                                              width_in_mbs, height_in_mbs,
 958                                              kernel_shader,
 959                                              0,
 960                                              encoder_context);
 961
 962     intel_batchbuffer_start_atomic(batch, 0x1000);
 963     gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
 964     BEGIN_BATCH(batch, 2);
 965     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
 966     OUT_RELOC(batch,
 967               vme_context->vme_batchbuffer.bo,
 968               I915_GEM_DOMAIN_COMMAND, 0,
 969               0);
 970     ADVANCE_BATCH(batch);
 971
 972     intel_batchbuffer_end_atomic(batch);
 973 }
 974
 975 static VAStatus
 976 gen75_vme_mpeg2_prepare(VADriverContextP ctx,
 977                         struct encode_state *encode_state,
 978                         struct intel_encoder_context *encoder_context)
 979 {
 980     VAStatus vaStatus = VA_STATUS_SUCCESS;
 981     VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[0]->buffer;
 982
 983     VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
 984     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 985
 986     if ((!vme_context->mpeg2_level) ||
 987         (vme_context->mpeg2_level != (seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK))) {
 988         vme_context->mpeg2_level = seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK;
 989     }
 990
 991     /*Setup all the memory object*/
 992     gen75_vme_mpeg2_surface_setup(ctx, encode_state, slice_param->is_intra_slice, encoder_context);
 993     gen75_vme_interface_setup(ctx, encode_state, encoder_context);
 994     gen75_vme_vme_state_setup(ctx, encode_state, slice_param->is_intra_slice, encoder_context);
 995     intel_vme_mpeg2_state_setup(ctx, encode_state, encoder_context);
 996     gen75_vme_constant_setup(ctx, encode_state, encoder_context);
 997
 998     /*Programing media pipeline*/
 999     gen75_vme_mpeg2_pipeline_programing(ctx, encode_state, slice_param->is_intra_slice, encoder_context);
1000
1001     return vaStatus;
1002 }
1003
1004 static VAStatus
1005 gen75_vme_mpeg2_pipeline(VADriverContextP ctx,
1006                          VAProfile profile,
1007                          struct encode_state *encode_state,
1008                          struct intel_encoder_context *encoder_context)
1009 {
1010     gen75_vme_media_init(ctx, encoder_context);
1011     gen75_vme_mpeg2_prepare(ctx, encode_state, encoder_context);
1012     gen75_vme_run(ctx, encode_state, encoder_context);
1013     gen75_vme_stop(ctx, encode_state, encoder_context);
1014
1015     return VA_STATUS_SUCCESS;
1016 }
1017
1018 static void
1019 gen75_vme_context_destroy(void *context)
1020 {
1021     struct gen6_vme_context *vme_context = context;
1022
1023     i965_gpe_context_destroy(&vme_context->gpe_context);
1024
1025     dri_bo_unreference(vme_context->vme_output.bo);
1026     vme_context->vme_output.bo = NULL;
1027
1028     dri_bo_unreference(vme_context->vme_state.bo);
1029     vme_context->vme_state.bo = NULL;
1030
1031     dri_bo_unreference(vme_context->vme_batchbuffer.bo);
1032     vme_context->vme_batchbuffer.bo = NULL;
1033
1034     if (vme_context->vme_state_message) {
1035         free(vme_context->vme_state_message);
1036         vme_context->vme_state_message = NULL;
1037     }
1038
1039     free(vme_context);
1040 }
1041
1042 Bool gen75_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1043 {
1044     struct gen6_vme_context *vme_context = calloc(1, sizeof(struct gen6_vme_context));
1045     struct i965_kernel *vme_kernel_list = NULL;
1046     int i965_kernel_num;
1047
1048     switch (encoder_context->codec) {
1049     case CODEC_H264:
1050         vme_kernel_list = gen75_vme_kernels;
1051         encoder_context->vme_pipeline = gen75_vme_pipeline;
1052         i965_kernel_num = sizeof(gen75_vme_kernels) / sizeof(struct i965_kernel);
1053         break;
1054
1055     case CODEC_MPEG2:
1056         vme_kernel_list = gen75_vme_mpeg2_kernels;
1057         encoder_context->vme_pipeline = gen75_vme_mpeg2_pipeline;
1058         i965_kernel_num = sizeof(gen75_vme_mpeg2_kernels) / sizeof(struct i965_kernel);
1059
1060         break;
1061
1062     default:
1063         /* never get here */
1064         assert(0);
1065
1066         break;
1067     }
1068     vme_context->vme_kernel_sum = i965_kernel_num;
1069     vme_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
1070
1071     vme_context->gpe_context.idrt.max_entries = MAX_INTERFACE_DESC_GEN6;
1072     vme_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
1073
1074     vme_context->gpe_context.curbe.length = CURBE_TOTAL_DATA_LENGTH;
1075
1076     vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
1077     vme_context->gpe_context.vfe_state.num_urb_entries = 16;
1078     vme_context->gpe_context.vfe_state.gpgpu_mode = 0;
1079     vme_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
1080     vme_context->gpe_context.vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1;
1081
1082     gen7_vme_scoreboard_init(ctx, vme_context);
1083
1084     i965_gpe_load_kernels(ctx,
1085                           &vme_context->gpe_context,
1086                           vme_kernel_list,
1087                           i965_kernel_num);
1088     vme_context->vme_surface2_setup = gen7_gpe_surface2_setup;
1089     vme_context->vme_media_rw_surface_setup = gen7_gpe_media_rw_surface_setup;
1090     vme_context->vme_buffer_suface_setup = gen7_gpe_buffer_suface_setup;
1091     vme_context->vme_media_chroma_surface_setup = gen75_gpe_media_chroma_surface_setup;
1092
1093     encoder_context->vme_context = vme_context;
1094     encoder_context->vme_context_destroy = gen75_vme_context_destroy;
1095
1096     vme_context->vme_state_message = malloc(VME_MSG_LENGTH * sizeof(int));
1097
1098     return True;
1099 }