src/gen6_mfd.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include "sysdeps.h"
  30 #include "intel_batchbuffer.h"
  31 #include "intel_driver.h"
  32 #include "i965_defines.h"
  33 #include "i965_drv_video.h"
  34 #include "i965_decoder_utils.h"
  35
  36 #include "gen6_mfd.h"
  37 #include "intel_media.h"
  38
  39 static const uint32_t zigzag_direct[64] = {
  40     0,   1,  8, 16,  9,  2,  3, 10,
  41     17, 24, 32, 25, 18, 11,  4,  5,
  42     12, 19, 26, 33, 40, 48, 41, 34,
  43     27, 20, 13,  6,  7, 14, 21, 28,
  44     35, 42, 49, 56, 57, 50, 43, 36,
  45     29, 22, 15, 23, 30, 37, 44, 51,
  46     58, 59, 52, 45, 38, 31, 39, 46,
  47     53, 60, 61, 54, 47, 55, 62, 63
  48 };
  49
  50 static void
  51 gen6_mfd_init_avc_surface(VADriverContextP ctx,
  52                           VAPictureParameterBufferH264 *pic_param,
  53                           struct object_surface *obj_surface)
  54 {
  55     struct i965_driver_data *i965 = i965_driver_data(ctx);
  56     GenAvcSurface *gen6_avc_surface = obj_surface->private_data;
  57     int height_in_mbs;
  58
  59     obj_surface->free_private_data = gen_free_avc_surface;
  60     height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */
  61
  62     if (!gen6_avc_surface) {
  63         gen6_avc_surface = calloc(sizeof(GenAvcSurface), 1);
  64         assert((obj_surface->size & 0x3f) == 0);
  65         obj_surface->private_data = gen6_avc_surface;
  66     }
  67
  68     gen6_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
  69                                          !pic_param->seq_fields.bits.direct_8x8_inference_flag);
  70
  71     if (gen6_avc_surface->dmv_top == NULL) {
  72         gen6_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
  73                                                  "direct mv w/r buffer",
  74                                                  128 * height_in_mbs * 64,      /* scalable with frame height */
  75                                                  0x1000);
  76     }
  77
  78     if (gen6_avc_surface->dmv_bottom_flag &&
  79         gen6_avc_surface->dmv_bottom == NULL) {
  80         gen6_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
  81                                                     "direct mv w/r buffer",
  82                                                     128 * height_in_mbs * 64,   /* scalable with frame height */
  83                                                     0x1000);
  84     }
  85 }
  86
  87 static void
  88 gen6_mfd_pipe_mode_select(VADriverContextP ctx,
  89                           struct decode_state *decode_state,
  90                           int standard_select,
  91                           struct gen6_mfd_context *gen6_mfd_context)
  92 {
  93     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
  94
  95     assert(standard_select == MFX_FORMAT_MPEG2 ||
  96            standard_select == MFX_FORMAT_AVC ||
  97            standard_select == MFX_FORMAT_VC1);
  98
  99     BEGIN_BCS_BATCH(batch, 4);
 100     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
 101     OUT_BCS_BATCH(batch,
 102                   (MFD_MODE_VLD << 16) | /* VLD mode */
 103                   (0 << 10) | /* disable Stream-Out */
 104                   (gen6_mfd_context->post_deblocking_output.valid << 9)  | /* Post Deblocking Output */
 105                   (gen6_mfd_context->pre_deblocking_output.valid << 8)  | /* Pre Deblocking Output */
 106                   (0 << 7)  | /* disable TLB prefectch */
 107                   (0 << 5)  | /* not in stitch mode */
 108                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
 109                   (standard_select << 0));
 110     OUT_BCS_BATCH(batch,
 111                   (0 << 20) | /* round flag in PB slice */
 112                   (0 << 19) | /* round flag in Intra8x8 */
 113                   (0 << 7)  | /* expand NOA bus flag */
 114                   (1 << 6)  | /* must be 1 */
 115                   (0 << 5)  | /* disable clock gating for NOA */
 116                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
 117                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 118                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 119                   (0 << 1)  | /* AVC long field motion vector */
 120                   (1 << 0));  /* always calculate AVC ILDB boundary strength */
 121     OUT_BCS_BATCH(batch, 0);
 122     ADVANCE_BCS_BATCH(batch);
 123 }
 124
 125 static void
 126 gen6_mfd_surface_state(VADriverContextP ctx,
 127                        struct decode_state *decode_state,
 128                        int standard_select,
 129                        struct gen6_mfd_context *gen6_mfd_context)
 130 {
 131     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 132     struct object_surface *obj_surface = decode_state->render_object;
 133     unsigned int surface_format;
 134
 135     surface_format = obj_surface->fourcc == VA_FOURCC_Y800 ?
 136         MFX_SURFACE_MONOCHROME : MFX_SURFACE_PLANAR_420_8;
 137
 138     BEGIN_BCS_BATCH(batch, 6);
 139     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 140     OUT_BCS_BATCH(batch, 0);
 141     OUT_BCS_BATCH(batch,
 142                   ((obj_surface->orig_height - 1) << 19) |
 143                   ((obj_surface->orig_width - 1) << 6));
 144     OUT_BCS_BATCH(batch,
 145                   (surface_format << 28) | /* 420 planar YUV surface */
 146                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
 147                   (0 << 22) | /* surface object control state, FIXME??? */
 148                   ((obj_surface->width - 1) << 3) | /* pitch */
 149                   (0 << 2)  | /* must be 0 for interleave U/V */
 150                   (1 << 1)  | /* must be y-tiled */
 151                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, FIXME: must be 1 ??? */
 152     OUT_BCS_BATCH(batch,
 153                   (0 << 16) | /* must be 0 for interleave U/V */
 154                   (obj_surface->height)); /* y offset for U(cb) */
 155     OUT_BCS_BATCH(batch, 0);
 156     ADVANCE_BCS_BATCH(batch);
 157 }
 158
 159 static void
 160 gen6_mfd_pipe_buf_addr_state(VADriverContextP ctx,
 161                              struct decode_state *decode_state,
 162                              int standard_select,
 163                              struct gen6_mfd_context *gen6_mfd_context)
 164 {
 165     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 166     int i;
 167
 168     BEGIN_BCS_BATCH(batch, 24);
 169     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 170     if (gen6_mfd_context->pre_deblocking_output.valid)
 171         OUT_BCS_RELOC(batch, gen6_mfd_context->pre_deblocking_output.bo,
 172                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 173                       0);
 174     else
 175         OUT_BCS_BATCH(batch, 0);
 176
 177     if (gen6_mfd_context->post_deblocking_output.valid)
 178         OUT_BCS_RELOC(batch, gen6_mfd_context->post_deblocking_output.bo,
 179                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 180                       0);
 181     else
 182         OUT_BCS_BATCH(batch, 0);
 183
 184     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 185     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 186
 187     if (gen6_mfd_context->intra_row_store_scratch_buffer.valid)
 188         OUT_BCS_RELOC(batch, gen6_mfd_context->intra_row_store_scratch_buffer.bo,
 189                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 190                       0);
 191     else
 192         OUT_BCS_BATCH(batch, 0);
 193
 194     if (gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
 195         OUT_BCS_RELOC(batch, gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
 196                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 197                       0);
 198     else
 199         OUT_BCS_BATCH(batch, 0);
 200
 201     /* DW 7..22 */
 202     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
 203         struct object_surface *obj_surface;
 204
 205         if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 206             gen6_mfd_context->reference_surface[i].obj_surface &&
 207             gen6_mfd_context->reference_surface[i].obj_surface->bo) {
 208             obj_surface = gen6_mfd_context->reference_surface[i].obj_surface;
 209
 210             OUT_BCS_RELOC(batch, obj_surface->bo,
 211                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 212                           0);
 213         } else {
 214             OUT_BCS_BATCH(batch, 0);
 215         }
 216     }
 217
 218     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
 219     ADVANCE_BCS_BATCH(batch);
 220 }
 221
 222 static void
 223 gen6_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
 224                                  dri_bo *slice_data_bo,
 225                                  int standard_select,
 226                                  struct gen6_mfd_context *gen6_mfd_context)
 227 {
 228     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 229
 230     BEGIN_BCS_BATCH(batch, 11);
 231     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 232     OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
 233     OUT_BCS_BATCH(batch, 0);
 234     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 235     OUT_BCS_BATCH(batch, 0);
 236     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 237     OUT_BCS_BATCH(batch, 0);
 238     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 239     OUT_BCS_BATCH(batch, 0);
 240     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 241     OUT_BCS_BATCH(batch, 0);
 242     ADVANCE_BCS_BATCH(batch);
 243 }
 244
 245 static void
 246 gen6_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
 247                                  struct decode_state *decode_state,
 248                                  int standard_select,
 249                                  struct gen6_mfd_context *gen6_mfd_context)
 250 {
 251     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 252
 253     BEGIN_BCS_BATCH(batch, 4);
 254     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 255
 256     if (gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
 257         OUT_BCS_RELOC(batch, gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
 258                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 259                       0);
 260     else
 261         OUT_BCS_BATCH(batch, 0);
 262
 263     if (gen6_mfd_context->mpr_row_store_scratch_buffer.valid)
 264         OUT_BCS_RELOC(batch, gen6_mfd_context->mpr_row_store_scratch_buffer.bo,
 265                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 266                       0);
 267     else
 268         OUT_BCS_BATCH(batch, 0);
 269
 270     if (gen6_mfd_context->bitplane_read_buffer.valid)
 271         OUT_BCS_RELOC(batch, gen6_mfd_context->bitplane_read_buffer.bo,
 272                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 273                       0);
 274     else
 275         OUT_BCS_BATCH(batch, 0);
 276
 277     ADVANCE_BCS_BATCH(batch);
 278 }
 279
 280 static void
 281 gen6_mfd_avc_img_state(VADriverContextP ctx,
 282                        struct decode_state *decode_state,
 283                        struct gen6_mfd_context *gen6_mfd_context)
 284 {
 285     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 286     int qm_present_flag;
 287     int img_struct;
 288     int mbaff_frame_flag;
 289     unsigned int width_in_mbs, height_in_mbs;
 290     VAPictureParameterBufferH264 *pic_param;
 291
 292     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 293     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 294
 295     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
 296         qm_present_flag = 1;
 297     else
 298         qm_present_flag = 0; /* built-in QM matrices */
 299
 300     if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
 301         img_struct = 1;
 302     else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
 303         img_struct = 3;
 304     else
 305         img_struct = 0;
 306
 307     if ((img_struct & 0x1) == 0x1) {
 308         assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
 309     } else {
 310         assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
 311     }
 312
 313     if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
 314         assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
 315         assert(pic_param->pic_fields.bits.field_pic_flag == 0);
 316     } else {
 317         assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
 318     }
 319
 320     mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
 321                         !pic_param->pic_fields.bits.field_pic_flag);
 322
 323     width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
 324     height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */
 325     assert(!((width_in_mbs * height_in_mbs) & 0x8000)); /* hardware requirement */
 326
 327     /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
 328     assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
 329            pic_param->seq_fields.bits.chroma_format_idc == 1);  /* 4:2:0 */
 330     assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
 331
 332     BEGIN_BCS_BATCH(batch, 13);
 333     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
 334     OUT_BCS_BATCH(batch,
 335                   ((width_in_mbs * height_in_mbs) & 0x7fff));
 336     OUT_BCS_BATCH(batch,
 337                   (height_in_mbs << 16) |
 338                   (width_in_mbs << 0));
 339     OUT_BCS_BATCH(batch,
 340                   ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
 341                   ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
 342                   (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
 343                   (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
 344                   (1 << 12) | /* always 1, hardware requirement */
 345                   (qm_present_flag << 10) |
 346                   (img_struct << 8) |
 347                   (16 << 0));
 348     OUT_BCS_BATCH(batch,
 349                   (pic_param->seq_fields.bits.chroma_format_idc << 10) |
 350                   (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
 351                   ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
 352                   (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
 353                   (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
 354                   (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
 355                   (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
 356                   (mbaff_frame_flag << 1) |
 357                   (pic_param->pic_fields.bits.field_pic_flag << 0));
 358     OUT_BCS_BATCH(batch, 0);
 359     OUT_BCS_BATCH(batch, 0);
 360     OUT_BCS_BATCH(batch, 0);
 361     OUT_BCS_BATCH(batch, 0);
 362     OUT_BCS_BATCH(batch, 0);
 363     OUT_BCS_BATCH(batch, 0);
 364     OUT_BCS_BATCH(batch, 0);
 365     OUT_BCS_BATCH(batch, 0);
 366     ADVANCE_BCS_BATCH(batch);
 367 }
 368
 369 static void
 370 gen6_mfd_avc_qm_state(VADriverContextP ctx,
 371                       struct decode_state *decode_state,
 372                       struct gen6_mfd_context *gen6_mfd_context)
 373 {
 374     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 375     int cmd_len;
 376     VAIQMatrixBufferH264 *iq_matrix;
 377     VAPictureParameterBufferH264 *pic_param;
 378
 379     if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
 380         return;
 381
 382     iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
 383
 384     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 385     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 386
 387     cmd_len = 2 + 6 * 4; /* always load six 4x4 scaling matrices */
 388
 389     if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
 390         cmd_len += 2 * 16; /* load two 8x8 scaling matrices */
 391
 392     BEGIN_BCS_BATCH(batch, cmd_len);
 393     OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | (cmd_len - 2));
 394
 395     if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
 396         OUT_BCS_BATCH(batch,
 397                       (0x0  << 8) | /* don't use default built-in matrices */
 398                       (0xff << 0)); /* six 4x4 and two 8x8 scaling matrices */
 399     else
 400         OUT_BCS_BATCH(batch,
 401                       (0x0  << 8) | /* don't use default built-in matrices */
 402                       (0x3f << 0)); /* six 4x4 scaling matrices */
 403
 404     intel_batchbuffer_data(batch, &iq_matrix->ScalingList4x4[0][0], 6 * 4 * 4);
 405
 406     if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
 407         intel_batchbuffer_data(batch, &iq_matrix->ScalingList8x8[0][0], 2 * 16 * 4);
 408
 409     ADVANCE_BCS_BATCH(batch);
 410 }
 411
 412 static void
 413 gen6_mfd_avc_directmode_state(VADriverContextP ctx,
 414                               struct decode_state *decode_state,
 415                               VAPictureParameterBufferH264 *pic_param,
 416                               VASliceParameterBufferH264 *slice_param,
 417                               struct gen6_mfd_context *gen6_mfd_context)
 418 {
 419     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 420     struct object_surface *obj_surface;
 421     GenAvcSurface *gen6_avc_surface;
 422     VAPictureH264 *va_pic;
 423     int i, j;
 424
 425     BEGIN_BCS_BATCH(batch, 69);
 426     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 427
 428     /* reference surfaces 0..15 */
 429     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
 430         if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 431             gen6_mfd_context->reference_surface[i].obj_surface &&
 432             gen6_mfd_context->reference_surface[i].obj_surface->private_data) {
 433
 434             obj_surface = gen6_mfd_context->reference_surface[i].obj_surface;
 435             gen6_avc_surface = obj_surface->private_data;
 436             OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 437                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 438                           0);
 439
 440             if (gen6_avc_surface->dmv_bottom_flag == 1)
 441                 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_bottom,
 442                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 443                               0);
 444             else
 445                 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 446                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 447                               0);
 448         } else {
 449             OUT_BCS_BATCH(batch, 0);
 450             OUT_BCS_BATCH(batch, 0);
 451         }
 452     }
 453
 454     /* the current decoding frame/field */
 455     va_pic = &pic_param->CurrPic;
 456     obj_surface = decode_state->render_object;
 457     assert(obj_surface->bo && obj_surface->private_data);
 458     gen6_avc_surface = obj_surface->private_data;
 459
 460     OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 461                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 462                   0);
 463
 464     if (gen6_avc_surface->dmv_bottom_flag == 1)
 465         OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_bottom,
 466                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 467                       0);
 468     else
 469         OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 470                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 471                       0);
 472
 473     /* POC List */
 474     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
 475         if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 476             int found = 0;
 477
 478             assert(gen6_mfd_context->reference_surface[i].obj_surface != NULL);
 479
 480             for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
 481                 va_pic = &pic_param->ReferenceFrames[j];
 482
 483                 if (va_pic->flags & VA_PICTURE_H264_INVALID)
 484                     continue;
 485
 486                 if (va_pic->picture_id == gen6_mfd_context->reference_surface[i].surface_id) {
 487                     found = 1;
 488                     break;
 489                 }
 490             }
 491
 492             assert(found == 1);
 493             assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 494
 495             OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 496             OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 497         } else {
 498             OUT_BCS_BATCH(batch, 0);
 499             OUT_BCS_BATCH(batch, 0);
 500         }
 501     }
 502
 503     va_pic = &pic_param->CurrPic;
 504     OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 505     OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 506
 507     ADVANCE_BCS_BATCH(batch);
 508 }
 509
 510 static void
 511 gen6_mfd_avc_slice_state(VADriverContextP ctx,
 512                          VAPictureParameterBufferH264 *pic_param,
 513                          VASliceParameterBufferH264 *slice_param,
 514                          VASliceParameterBufferH264 *next_slice_param,
 515                          struct gen6_mfd_context *gen6_mfd_context)
 516 {
 517     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 518     int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 519     int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
 520     int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
 521     int num_ref_idx_l0, num_ref_idx_l1;
 522     int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
 523                          pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
 524     int weighted_pred_idc = 0;
 525     int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
 526     unsigned int chroma_log2_weight_denom, luma_log2_weight_denom;
 527     int slice_type;
 528
 529     if (slice_param->slice_type == SLICE_TYPE_I ||
 530         slice_param->slice_type == SLICE_TYPE_SI) {
 531         slice_type = SLICE_TYPE_I;
 532     } else if (slice_param->slice_type == SLICE_TYPE_P ||
 533                slice_param->slice_type == SLICE_TYPE_SP) {
 534         slice_type = SLICE_TYPE_P;
 535     } else {
 536         assert(slice_param->slice_type == SLICE_TYPE_B);
 537         slice_type = SLICE_TYPE_B;
 538     }
 539
 540     luma_log2_weight_denom   = slice_param->luma_log2_weight_denom;
 541     chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
 542
 543     if (slice_type == SLICE_TYPE_I) {
 544         assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
 545         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 546         num_ref_idx_l0 = 0;
 547         num_ref_idx_l1 = 0;
 548     } else if (slice_type == SLICE_TYPE_P) {
 549         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 550         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 551         num_ref_idx_l1 = 0;
 552         weighted_pred_idc = (pic_param->pic_fields.bits.weighted_pred_flag == 1);
 553     } else {
 554         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 555         num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
 556         weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
 557
 558         if (weighted_pred_idc == 2) {
 559             /* 8.4.3 - Derivation process for prediction weights (8-279) */
 560             luma_log2_weight_denom   = 5;
 561             chroma_log2_weight_denom = 5;
 562         }
 563     }
 564
 565     first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture;
 566     slice_hor_pos = first_mb_in_slice % width_in_mbs;
 567     slice_ver_pos = first_mb_in_slice / width_in_mbs;
 568
 569     if (next_slice_param) {
 570         first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture;
 571         next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
 572         next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
 573     } else {
 574         next_slice_hor_pos = 0;
 575         next_slice_ver_pos = height_in_mbs;
 576     }
 577
 578     BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
 579     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
 580     OUT_BCS_BATCH(batch, slice_type);
 581     OUT_BCS_BATCH(batch,
 582                   (num_ref_idx_l1 << 24) |
 583                   (num_ref_idx_l0 << 16) |
 584                   (chroma_log2_weight_denom << 8) |
 585                   (luma_log2_weight_denom << 0));
 586     OUT_BCS_BATCH(batch,
 587                   (weighted_pred_idc << 30) |
 588                   (slice_param->direct_spatial_mv_pred_flag << 29) |
 589                   (slice_param->disable_deblocking_filter_idc << 27) |
 590                   (slice_param->cabac_init_idc << 24) |
 591                   ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
 592                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 593                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 594     OUT_BCS_BATCH(batch,
 595                   (slice_ver_pos << 24) |
 596                   (slice_hor_pos << 16) |
 597                   (first_mb_in_slice << 0));
 598     OUT_BCS_BATCH(batch,
 599                   (next_slice_ver_pos << 16) |
 600                   (next_slice_hor_pos << 0));
 601     OUT_BCS_BATCH(batch,
 602                   (next_slice_param == NULL) << 19); /* last slice flag */
 603     OUT_BCS_BATCH(batch, 0);
 604     OUT_BCS_BATCH(batch, 0);
 605     OUT_BCS_BATCH(batch, 0);
 606     OUT_BCS_BATCH(batch, 0);
 607     ADVANCE_BCS_BATCH(batch);
 608 }
 609
 610 static void
 611 gen6_mfd_avc_phantom_slice_state(VADriverContextP ctx,
 612                                  VAPictureParameterBufferH264 *pic_param,
 613                                  VASliceParameterBufferH264 *next_slice_param,
 614                                  struct gen6_mfd_context *gen6_mfd_context)
 615 {
 616     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 617     int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 618     int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
 619     int slice_hor_pos, slice_ver_pos, slice_start_mb_num, next_slice_hor_pos, next_slice_ver_pos;
 620     int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
 621                          pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
 622
 623     if (next_slice_param) {
 624         int first_mb_in_next_slice;
 625
 626         slice_hor_pos = 0;
 627         slice_ver_pos = 0;
 628         slice_start_mb_num = 0;
 629         first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture;
 630         next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
 631         next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
 632     } else {
 633         slice_hor_pos = 0;
 634         slice_ver_pos = height_in_mbs;
 635         slice_start_mb_num = width_in_mbs * height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag);
 636         next_slice_hor_pos = 0;
 637         next_slice_ver_pos = 0;
 638     }
 639
 640     BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
 641     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
 642     OUT_BCS_BATCH(batch, 0);
 643     OUT_BCS_BATCH(batch, 0);
 644     OUT_BCS_BATCH(batch, 0);
 645     OUT_BCS_BATCH(batch,
 646                   slice_ver_pos << 24 |
 647                   slice_hor_pos << 16 |
 648                   slice_start_mb_num << 0);
 649     OUT_BCS_BATCH(batch,
 650                   next_slice_ver_pos << 16 |
 651                   next_slice_hor_pos << 0);
 652     OUT_BCS_BATCH(batch, 0);
 653     OUT_BCS_BATCH(batch, 0);
 654     OUT_BCS_BATCH(batch, 0);
 655     OUT_BCS_BATCH(batch, 0);
 656     OUT_BCS_BATCH(batch, 0);
 657     ADVANCE_BCS_BATCH(batch);
 658 }
 659
 660 static inline void
 661 gen6_mfd_avc_ref_idx_state(VADriverContextP ctx,
 662                            VAPictureParameterBufferH264 *pic_param,
 663                            VASliceParameterBufferH264 *slice_param,
 664                            struct gen6_mfd_context *gen6_mfd_context)
 665 {
 666     gen6_send_avc_ref_idx_state(
 667         gen6_mfd_context->base.batch,
 668         slice_param,
 669         gen6_mfd_context->reference_surface
 670     );
 671 }
 672
 673 static void
 674 gen6_mfd_avc_weightoffset_state(VADriverContextP ctx,
 675                                 VAPictureParameterBufferH264 *pic_param,
 676                                 VASliceParameterBufferH264 *slice_param,
 677                                 struct gen6_mfd_context *gen6_mfd_context)
 678 {
 679     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 680     int i, j, num_weight_offset_table = 0;
 681     short weightoffsets[32 * 6];
 682
 683     if ((slice_param->slice_type == SLICE_TYPE_P ||
 684          slice_param->slice_type == SLICE_TYPE_SP) &&
 685         (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
 686         num_weight_offset_table = 1;
 687     }
 688
 689     if ((slice_param->slice_type == SLICE_TYPE_B) &&
 690         (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
 691         num_weight_offset_table = 2;
 692     }
 693
 694     for (i = 0; i < num_weight_offset_table; i++) {
 695         BEGIN_BCS_BATCH(batch, 98);
 696         OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
 697         OUT_BCS_BATCH(batch, i);
 698
 699         if (i == 0) {
 700             for (j = 0; j < 32; j++) {
 701                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
 702                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
 703                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
 704                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
 705                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
 706                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
 707             }
 708         } else {
 709             for (j = 0; j < 32; j++) {
 710                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
 711                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
 712                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
 713                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
 714                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
 715                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
 716             }
 717         }
 718
 719         intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
 720         ADVANCE_BCS_BATCH(batch);
 721     }
 722 }
 723
 724 static void
 725 gen6_mfd_avc_bsd_object(VADriverContextP ctx,
 726                         VAPictureParameterBufferH264 *pic_param,
 727                         VASliceParameterBufferH264 *slice_param,
 728                         dri_bo *slice_data_bo,
 729                         struct gen6_mfd_context *gen6_mfd_context)
 730 {
 731     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 732     unsigned int slice_data_bit_offset;
 733
 734     slice_data_bit_offset = avc_get_first_mb_bit_offset(
 735         slice_data_bo,
 736         slice_param,
 737         pic_param->pic_fields.bits.entropy_coding_mode_flag
 738     );
 739
 740     BEGIN_BCS_BATCH(batch, 6);
 741     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
 742     OUT_BCS_BATCH(batch,
 743                   (slice_param->slice_data_size - slice_param->slice_data_offset));
 744     OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
 745     OUT_BCS_BATCH(batch,
 746                   (0 << 31) |
 747                   (0 << 14) |
 748                   (0 << 12) |
 749                   (0 << 10) |
 750                   (0 << 8));
 751     OUT_BCS_BATCH(batch,
 752                   ((slice_data_bit_offset >> 3) << 16) |
 753                   (1 << 7)  |
 754                   (1 << 6)  |
 755                   ((0x7 - (slice_data_bit_offset & 0x7)) << 0));
 756     OUT_BCS_BATCH(batch, 0);
 757     ADVANCE_BCS_BATCH(batch);
 758 }
 759
 760 static void
 761 gen6_mfd_avc_phantom_slice_bsd_object(VADriverContextP ctx,
 762                                       VAPictureParameterBufferH264 *pic_param,
 763                                       struct gen6_mfd_context *gen6_mfd_context)
 764 {
 765     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 766
 767     BEGIN_BCS_BATCH(batch, 6);
 768     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
 769     OUT_BCS_BATCH(batch, 0);
 770     OUT_BCS_BATCH(batch, 0);
 771     OUT_BCS_BATCH(batch, 0);
 772     OUT_BCS_BATCH(batch, 0);
 773     OUT_BCS_BATCH(batch, 0);
 774     ADVANCE_BCS_BATCH(batch);
 775 }
 776
 777 static void
 778 gen6_mfd_avc_phantom_slice(VADriverContextP ctx,
 779                            VAPictureParameterBufferH264 *pic_param,
 780                            VASliceParameterBufferH264 *next_slice_param,
 781                            struct gen6_mfd_context *gen6_mfd_context)
 782 {
 783     gen6_mfd_avc_phantom_slice_state(ctx, pic_param, next_slice_param, gen6_mfd_context);
 784     gen6_mfd_avc_phantom_slice_bsd_object(ctx, pic_param, gen6_mfd_context);
 785 }
 786
 787 static void
 788 gen6_mfd_avc_phantom_slice_first(VADriverContextP ctx,
 789                                  VAPictureParameterBufferH264 *pic_param,
 790                                  VASliceParameterBufferH264 *next_slice_param,
 791                                  struct gen6_mfd_context *gen6_mfd_context)
 792 {
 793     gen6_mfd_avc_phantom_slice(ctx, pic_param, next_slice_param, gen6_mfd_context);
 794 }
 795
 796 static void
 797 gen6_mfd_avc_phantom_slice_last(VADriverContextP ctx,
 798                                 VAPictureParameterBufferH264 *pic_param,
 799                                 struct gen6_mfd_context *gen6_mfd_context)
 800 {
 801     gen6_mfd_avc_phantom_slice(ctx, pic_param, NULL, gen6_mfd_context);
 802 }
 803
 804 static void
 805 gen6_mfd_avc_decode_init(VADriverContextP ctx,
 806                          struct decode_state *decode_state,
 807                          struct gen6_mfd_context *gen6_mfd_context)
 808 {
 809     VAPictureParameterBufferH264 *pic_param;
 810     VASliceParameterBufferH264 *slice_param;
 811     struct i965_driver_data *i965 = i965_driver_data(ctx);
 812     struct object_surface *obj_surface;
 813     dri_bo *bo;
 814     int i, j, enable_avc_ildb = 0;
 815     int width_in_mbs;
 816
 817     for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
 818         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 819         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 820
 821         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 822             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 823             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 824                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 825                    (slice_param->slice_type == SLICE_TYPE_P) ||
 826                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 827                    (slice_param->slice_type == SLICE_TYPE_B));
 828
 829             if (slice_param->disable_deblocking_filter_idc != 1) {
 830                 enable_avc_ildb = 1;
 831                 break;
 832             }
 833
 834             slice_param++;
 835         }
 836     }
 837
 838     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 839     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 840     intel_update_avc_frame_store_index(ctx, decode_state, pic_param, gen6_mfd_context->reference_surface);
 841     width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
 842
 843     /* Current decoded picture */
 844     obj_surface = decode_state->render_object;
 845     obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
 846     obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0);
 847
 848     avc_ensure_surface_bo(ctx, decode_state, obj_surface, pic_param);
 849     gen6_mfd_init_avc_surface(ctx, pic_param, obj_surface);
 850
 851     dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
 852     gen6_mfd_context->post_deblocking_output.bo = obj_surface->bo;
 853     dri_bo_reference(gen6_mfd_context->post_deblocking_output.bo);
 854     gen6_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
 855
 856     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
 857     gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 858     dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
 859     gen6_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
 860
 861     dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
 862     bo = dri_bo_alloc(i965->intel.bufmgr,
 863                       "intra row store",
 864                       width_in_mbs * 64,
 865                       0x1000);
 866     assert(bo);
 867     gen6_mfd_context->intra_row_store_scratch_buffer.bo = bo;
 868     gen6_mfd_context->intra_row_store_scratch_buffer.valid = 1;
 869
 870     dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
 871     bo = dri_bo_alloc(i965->intel.bufmgr,
 872                       "deblocking filter row store",
 873                       width_in_mbs * 64 * 4,
 874                       0x1000);
 875     assert(bo);
 876     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 877     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
 878
 879     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 880     bo = dri_bo_alloc(i965->intel.bufmgr,
 881                       "bsd mpc row store",
 882                       width_in_mbs * 96,
 883                       0x1000);
 884     assert(bo);
 885     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 886     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
 887
 888     dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo);
 889     bo = dri_bo_alloc(i965->intel.bufmgr,
 890                       "mpr row store",
 891                       width_in_mbs * 64,
 892                       0x1000);
 893     assert(bo);
 894     gen6_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
 895     gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
 896
 897     gen6_mfd_context->bitplane_read_buffer.valid = 0;
 898 }
 899
 900 static void
 901 gen6_mfd_avc_decode_picture(VADriverContextP ctx,
 902                             struct decode_state *decode_state,
 903                             struct gen6_mfd_context *gen6_mfd_context)
 904 {
 905     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 906     VAPictureParameterBufferH264 *pic_param;
 907     VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
 908     dri_bo *slice_data_bo;
 909     int i, j;
 910
 911     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 912     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 913     gen6_mfd_avc_decode_init(ctx, decode_state, gen6_mfd_context);
 914
 915     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
 916     intel_batchbuffer_emit_mi_flush(batch);
 917     gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
 918     gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
 919     gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
 920     gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
 921     gen6_mfd_avc_img_state(ctx, decode_state, gen6_mfd_context);
 922     gen6_mfd_avc_qm_state(ctx, decode_state, gen6_mfd_context);
 923
 924     for (j = 0; j < decode_state->num_slice_params; j++) {
 925         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 926         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 927         slice_data_bo = decode_state->slice_datas[j]->bo;
 928         gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen6_mfd_context);
 929
 930         if (j == decode_state->num_slice_params - 1)
 931             next_slice_group_param = NULL;
 932         else
 933             next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
 934
 935             if (j == 0 &&
 936                 slice_param->first_mb_in_slice)
 937                 gen6_mfd_avc_phantom_slice_first(ctx, pic_param, slice_param, gen6_mfd_context);
 938
 939         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 940             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 941             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 942                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 943                    (slice_param->slice_type == SLICE_TYPE_P) ||
 944                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 945                    (slice_param->slice_type == SLICE_TYPE_B));
 946
 947             if (i < decode_state->slice_params[j]->num_elements - 1)
 948                 next_slice_param = slice_param + 1;
 949             else
 950                 next_slice_param = next_slice_group_param;
 951
 952             gen6_mfd_avc_directmode_state(ctx, decode_state, pic_param, slice_param, gen6_mfd_context);
 953             gen6_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen6_mfd_context);
 954             gen6_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen6_mfd_context);
 955             gen6_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen6_mfd_context);
 956             gen6_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, gen6_mfd_context);
 957             slice_param++;
 958         }
 959     }
 960
 961     gen6_mfd_avc_phantom_slice_last(ctx, pic_param, gen6_mfd_context);
 962     intel_batchbuffer_end_atomic(batch);
 963     intel_batchbuffer_flush(batch);
 964 }
 965
 966 static void
 967 gen6_mfd_mpeg2_decode_init(VADriverContextP ctx,
 968                            struct decode_state *decode_state,
 969                            struct gen6_mfd_context *gen6_mfd_context)
 970 {
 971     VAPictureParameterBufferMPEG2 *pic_param;
 972     struct i965_driver_data *i965 = i965_driver_data(ctx);
 973     struct object_surface *obj_surface;
 974     dri_bo *bo;
 975     unsigned int width_in_mbs;
 976
 977     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 978     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
 979     width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
 980
 981     mpeg2_set_reference_surfaces(
 982         ctx,
 983         gen6_mfd_context->reference_surface,
 984         decode_state,
 985         pic_param
 986     );
 987
 988     /* Current decoded picture */
 989     obj_surface = decode_state->render_object;
 990     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
 991
 992     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
 993     gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 994     dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
 995     gen6_mfd_context->pre_deblocking_output.valid = 1;
 996
 997     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 998     bo = dri_bo_alloc(i965->intel.bufmgr,
 999                       "bsd mpc row store",
1000                       width_in_mbs * 96,
1001                       0x1000);
1002     assert(bo);
1003     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1004     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1005
1006     gen6_mfd_context->post_deblocking_output.valid = 0;
1007     gen6_mfd_context->intra_row_store_scratch_buffer.valid = 0;
1008     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
1009     gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1010     gen6_mfd_context->bitplane_read_buffer.valid = 0;
1011 }
1012
1013 static void
1014 gen6_mfd_mpeg2_pic_state(VADriverContextP ctx,
1015                          struct decode_state *decode_state,
1016                          struct gen6_mfd_context *gen6_mfd_context)
1017 {
1018     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1019     VAPictureParameterBufferMPEG2 *pic_param;
1020     unsigned int tff, pic_structure;
1021
1022     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1023     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1024
1025     pic_structure = pic_param->picture_coding_extension.bits.picture_structure;
1026     if (pic_structure == MPEG_FRAME)
1027         tff = pic_param->picture_coding_extension.bits.top_field_first;
1028     else
1029         tff = !(pic_param->picture_coding_extension.bits.is_first_field ^
1030                 (pic_structure & MPEG_TOP_FIELD));
1031
1032     BEGIN_BCS_BATCH(batch, 4);
1033     OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (4 - 2));
1034     OUT_BCS_BATCH(batch,
1035                   (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
1036                   ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
1037                   ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
1038                   ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
1039                   pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
1040                   pic_param->picture_coding_extension.bits.picture_structure << 12 |
1041                   tff << 11 |
1042                   pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
1043                   pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
1044                   pic_param->picture_coding_extension.bits.q_scale_type << 8 |
1045                   pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
1046                   pic_param->picture_coding_extension.bits.alternate_scan << 6);
1047     OUT_BCS_BATCH(batch,
1048                   pic_param->picture_coding_type << 9);
1049     OUT_BCS_BATCH(batch,
1050                   (ALIGN(pic_param->vertical_size, 16) / 16) << 16 |
1051                   (ALIGN(pic_param->horizontal_size, 16) / 16));
1052     ADVANCE_BCS_BATCH(batch);
1053 }
1054
1055 static void
1056 gen6_mfd_mpeg2_qm_state(VADriverContextP ctx,
1057                         struct decode_state *decode_state,
1058                         struct gen6_mfd_context *gen6_mfd_context)
1059 {
1060     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1061     VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen6_mfd_context->iq_matrix.mpeg2;
1062     int i, j;
1063
1064     /* Update internal QM state */
1065     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
1066         VAIQMatrixBufferMPEG2 * const iq_matrix =
1067             (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
1068
1069         gen_iq_matrix->load_intra_quantiser_matrix =
1070             iq_matrix->load_intra_quantiser_matrix;
1071         if (iq_matrix->load_intra_quantiser_matrix) {
1072             for (j = 0; j < 64; j++)
1073                 gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
1074                     iq_matrix->intra_quantiser_matrix[j];
1075         }
1076
1077         gen_iq_matrix->load_non_intra_quantiser_matrix =
1078             iq_matrix->load_non_intra_quantiser_matrix;
1079         if (iq_matrix->load_non_intra_quantiser_matrix) {
1080             for (j = 0; j < 64; j++)
1081                 gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1082                     iq_matrix->non_intra_quantiser_matrix[j];
1083         }
1084     }
1085
1086     /* Commit QM state to HW */
1087     for (i = 0; i < 2; i++) {
1088         unsigned char *qm = NULL;
1089
1090         if (i == 0) {
1091             if (gen_iq_matrix->load_intra_quantiser_matrix)
1092                 qm = gen_iq_matrix->intra_quantiser_matrix;
1093         } else {
1094             if (gen_iq_matrix->load_non_intra_quantiser_matrix)
1095                 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1096         }
1097
1098         if (!qm)
1099             continue;
1100
1101         BEGIN_BCS_BATCH(batch, 18);
1102         OUT_BCS_BATCH(batch, MFX_MPEG2_QM_STATE | (18 - 2));
1103         OUT_BCS_BATCH(batch, i);
1104         intel_batchbuffer_data(batch, qm, 64);
1105         ADVANCE_BCS_BATCH(batch);
1106     }
1107 }
1108
1109 static void
1110 gen6_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1111                           VAPictureParameterBufferMPEG2 *pic_param,
1112                           VASliceParameterBufferMPEG2 *slice_param,
1113                           VASliceParameterBufferMPEG2 *next_slice_param,
1114                           struct gen6_mfd_context *gen6_mfd_context)
1115 {
1116     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1117     unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1118     int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1119
1120     if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1121         pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1122         is_field_pic = 1;
1123     is_field_pic_wa = is_field_pic &&
1124         gen6_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1125
1126     vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1127     hpos0 = slice_param->slice_horizontal_position;
1128
1129     if (next_slice_param == NULL) {
1130         vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1131         hpos1 = 0;
1132     } else {
1133         vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1134         hpos1 = next_slice_param->slice_horizontal_position;
1135     }
1136
1137     mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1138
1139     BEGIN_BCS_BATCH(batch, 5);
1140     OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1141     OUT_BCS_BATCH(batch,
1142                   slice_param->slice_data_size - (slice_param->macroblock_offset >> 3));
1143     OUT_BCS_BATCH(batch,
1144                   slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1145     OUT_BCS_BATCH(batch,
1146                   hpos0 << 24 |
1147                   vpos0 << 16 |
1148                   mb_count << 8 |
1149                   (next_slice_param == NULL) << 5 |
1150                   (next_slice_param == NULL) << 3 |
1151                   (slice_param->macroblock_offset & 0x7));
1152     OUT_BCS_BATCH(batch,
1153                   slice_param->quantiser_scale_code << 24);
1154     ADVANCE_BCS_BATCH(batch);
1155 }
1156
1157 static void
1158 gen6_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1159                               struct decode_state *decode_state,
1160                               struct gen6_mfd_context *gen6_mfd_context)
1161 {
1162     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1163     VAPictureParameterBufferMPEG2 *pic_param;
1164     VASliceParameterBufferMPEG2 *slice_param, *next_slice_param;
1165     dri_bo *slice_data_bo;
1166     int group_idx = 0, pre_group_idx = -1, element_idx = 0;
1167
1168     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1169     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1170
1171     gen6_mfd_mpeg2_decode_init(ctx, decode_state, gen6_mfd_context);
1172     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1173     intel_batchbuffer_emit_mi_flush(batch);
1174     gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1175     gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1176     gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1177     gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1178     gen6_mfd_mpeg2_pic_state(ctx, decode_state, gen6_mfd_context);
1179     gen6_mfd_mpeg2_qm_state(ctx, decode_state, gen6_mfd_context);
1180
1181     if (gen6_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1182         gen6_mfd_context->wa_mpeg2_slice_vertical_position =
1183             mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1184
1185     slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[group_idx]->buffer;
1186
1187     for (; slice_param;) {
1188         if (pre_group_idx != group_idx) {
1189             slice_data_bo = decode_state->slice_datas[group_idx]->bo;
1190             gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen6_mfd_context);
1191             pre_group_idx = group_idx;
1192         }
1193
1194         next_slice_param = intel_mpeg2_find_next_slice(decode_state, pic_param, slice_param, &group_idx, &element_idx);
1195         gen6_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, next_slice_param, gen6_mfd_context);
1196         slice_param = next_slice_param;
1197     }
1198
1199     intel_batchbuffer_end_atomic(batch);
1200     intel_batchbuffer_flush(batch);
1201 }
1202
1203 static const int va_to_gen6_vc1_pic_type[5] = {
1204     GEN6_VC1_I_PICTURE,
1205     GEN6_VC1_P_PICTURE,
1206     GEN6_VC1_B_PICTURE,
1207     GEN6_VC1_BI_PICTURE,
1208     GEN6_VC1_P_PICTURE,
1209 };
1210
1211 static const int va_to_gen6_vc1_mv[4] = {
1212     1, /* 1-MV */
1213     2, /* 1-MV half-pel */
1214     3, /* 1-MV half-pef bilinear */
1215     0, /* Mixed MV */
1216 };
1217
1218 static const int b_picture_scale_factor[21] = {
1219     128, 85,  170, 64,  192,
1220     51,  102, 153, 204, 43,
1221     215, 37,  74,  111, 148,
1222     185, 222, 32,  96,  160,
1223     224,
1224 };
1225
1226 static const int va_to_gen6_vc1_condover[3] = {
1227     0,
1228     2,
1229     3
1230 };
1231
1232 static const int va_to_gen6_vc1_profile[4] = {
1233     GEN6_VC1_SIMPLE_PROFILE,
1234     GEN6_VC1_MAIN_PROFILE,
1235     GEN6_VC1_RESERVED_PROFILE,
1236     GEN6_VC1_ADVANCED_PROFILE
1237 };
1238
1239 static void
1240 gen6_mfd_free_vc1_surface(void **data)
1241 {
1242     struct gen6_vc1_surface *gen6_vc1_surface = *data;
1243
1244     if (!gen6_vc1_surface)
1245         return;
1246
1247     dri_bo_unreference(gen6_vc1_surface->dmv);
1248     free(gen6_vc1_surface);
1249     *data = NULL;
1250 }
1251
1252 static void
1253 gen6_mfd_init_vc1_surface(VADriverContextP ctx,
1254                           VAPictureParameterBufferVC1 *pic_param,
1255                           struct object_surface *obj_surface)
1256 {
1257     struct i965_driver_data *i965 = i965_driver_data(ctx);
1258     struct gen6_vc1_surface *gen6_vc1_surface = obj_surface->private_data;
1259     int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1260
1261     obj_surface->free_private_data = gen6_mfd_free_vc1_surface;
1262
1263     if (!gen6_vc1_surface) {
1264         gen6_vc1_surface = calloc(sizeof(struct gen6_vc1_surface), 1);
1265         assert((obj_surface->size & 0x3f) == 0);
1266         obj_surface->private_data = gen6_vc1_surface;
1267     }
1268
1269     gen6_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
1270
1271     if (gen6_vc1_surface->dmv == NULL) {
1272         gen6_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
1273                                              "direct mv w/r buffer",
1274                                              128 * height_in_mbs * 64,  /* scalable with frame height */
1275                                              0x1000);
1276     }
1277 }
1278
1279 static void
1280 gen6_mfd_vc1_decode_init(VADriverContextP ctx,
1281                          struct decode_state *decode_state,
1282                          struct gen6_mfd_context *gen6_mfd_context)
1283 {
1284     VAPictureParameterBufferVC1 *pic_param;
1285     struct i965_driver_data *i965 = i965_driver_data(ctx);
1286     struct object_surface *obj_surface;
1287     dri_bo *bo;
1288     int width_in_mbs;
1289     int picture_type;
1290
1291     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1292     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1293     width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1294     picture_type = pic_param->picture_fields.bits.picture_type;
1295
1296     intel_update_vc1_frame_store_index(ctx,
1297                                        decode_state,
1298                                        pic_param,
1299                                        gen6_mfd_context->reference_surface);
1300
1301     /* Current decoded picture */
1302     obj_surface = decode_state->render_object;
1303     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
1304     gen6_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1305
1306     dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
1307     gen6_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1308     dri_bo_reference(gen6_mfd_context->post_deblocking_output.bo);
1309     gen6_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1310
1311     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
1312     gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1313     dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
1314     gen6_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1315
1316     dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
1317     bo = dri_bo_alloc(i965->intel.bufmgr,
1318                       "intra row store",
1319                       width_in_mbs * 64,
1320                       0x1000);
1321     assert(bo);
1322     gen6_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1323     gen6_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1324
1325     dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1326     bo = dri_bo_alloc(i965->intel.bufmgr,
1327                       "deblocking filter row store",
1328                       width_in_mbs * 7 * 64,
1329                       0x1000);
1330     assert(bo);
1331     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1332     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1333
1334     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1335     bo = dri_bo_alloc(i965->intel.bufmgr,
1336                       "bsd mpc row store",
1337                       width_in_mbs * 96,
1338                       0x1000);
1339     assert(bo);
1340     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1341     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1342
1343     gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1344
1345     gen6_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value;
1346     dri_bo_unreference(gen6_mfd_context->bitplane_read_buffer.bo);
1347
1348     if (gen6_mfd_context->bitplane_read_buffer.valid) {
1349         int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1350         int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1351         int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1352         int src_w, src_h;
1353         uint8_t *src = NULL, *dst = NULL;
1354
1355         assert(decode_state->bit_plane->buffer);
1356         src = decode_state->bit_plane->buffer;
1357
1358         bo = dri_bo_alloc(i965->intel.bufmgr,
1359                           "VC-1 Bitplane",
1360                           bitplane_width * height_in_mbs,
1361                           0x1000);
1362         assert(bo);
1363         gen6_mfd_context->bitplane_read_buffer.bo = bo;
1364
1365         dri_bo_map(bo, True);
1366         assert(bo->virtual);
1367         dst = bo->virtual;
1368
1369         for (src_h = 0; src_h < height_in_mbs; src_h++) {
1370             for(src_w = 0; src_w < width_in_mbs; src_w++) {
1371                 int src_index, dst_index;
1372                 int src_shift;
1373                 uint8_t src_value;
1374
1375                 src_index = (src_h * width_in_mbs + src_w) / 2;
1376                 src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1377                 src_value = ((src[src_index] >> src_shift) & 0xf);
1378
1379                 if (picture_type == GEN6_VC1_SKIPPED_PICTURE){
1380                     src_value |= 0x2;
1381                 }
1382
1383                 dst_index = src_w / 2;
1384                 dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1385             }
1386
1387             if (src_w & 1)
1388                 dst[src_w / 2] >>= 4;
1389
1390             dst += bitplane_width;
1391         }
1392
1393         dri_bo_unmap(bo);
1394     } else
1395         gen6_mfd_context->bitplane_read_buffer.bo = NULL;
1396 }
1397
1398 static void
1399 gen6_mfd_vc1_pic_state(VADriverContextP ctx,
1400                        struct decode_state *decode_state,
1401                        struct gen6_mfd_context *gen6_mfd_context)
1402 {
1403     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1404     VAPictureParameterBufferVC1 *pic_param;
1405     struct object_surface *obj_surface;
1406     int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1407     int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1408     int unified_mv_mode;
1409     int ref_field_pic_polarity = 0;
1410     int scale_factor = 0;
1411     int trans_ac_y = 0;
1412     int dmv_surface_valid = 0;
1413     int brfd = 0;
1414     int fcm = 0;
1415     int picture_type;
1416     int profile;
1417     int overlap;
1418
1419     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1420     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1421
1422     profile = va_to_gen6_vc1_profile[pic_param->sequence_fields.bits.profile];
1423     dquant = pic_param->pic_quantizer_fields.bits.dquant;
1424     dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1425     dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1426     dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1427     dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1428     dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1429     alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1430
1431     if (dquant == 0) {
1432         alt_pquant_config = 0;
1433         alt_pquant_edge_mask = 0;
1434     } else if (dquant == 2) {
1435         alt_pquant_config = 1;
1436         alt_pquant_edge_mask = 0xf;
1437     } else {
1438         assert(dquant == 1);
1439         if (dquantfrm == 0) {
1440             alt_pquant_config = 0;
1441             alt_pquant_edge_mask = 0;
1442             alt_pq = 0;
1443         } else {
1444             assert(dquantfrm == 1);
1445             alt_pquant_config = 1;
1446
1447             switch (dqprofile) {
1448             case 3:
1449                 if (dqbilevel == 0) {
1450                     alt_pquant_config = 2;
1451                     alt_pquant_edge_mask = 0;
1452                 } else {
1453                     assert(dqbilevel == 1);
1454                     alt_pquant_config = 3;
1455                     alt_pquant_edge_mask = 0;
1456                 }
1457                 break;
1458
1459             case 0:
1460                 alt_pquant_edge_mask = 0xf;
1461                 break;
1462
1463             case 1:
1464                 if (dqdbedge == 3)
1465                     alt_pquant_edge_mask = 0x9;
1466                 else
1467                     alt_pquant_edge_mask = (0x3 << dqdbedge);
1468
1469                 break;
1470
1471             case 2:
1472                 alt_pquant_edge_mask = (0x1 << dqsbedge);
1473                 break;
1474
1475             default:
1476                 assert(0);
1477             }
1478         }
1479     }
1480
1481     if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1482         assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1483         unified_mv_mode = va_to_gen6_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1484     } else {
1485         assert(pic_param->mv_fields.bits.mv_mode < 4);
1486         unified_mv_mode = va_to_gen6_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1487     }
1488
1489     if (pic_param->sequence_fields.bits.interlace == 1 &&
1490         pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
1491         /* FIXME: calculate reference field picture polarity */
1492         assert(0);
1493         ref_field_pic_polarity = 0;
1494     }
1495
1496     if (pic_param->b_picture_fraction < 21)
1497         scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1498
1499     picture_type = va_to_gen6_vc1_pic_type[pic_param->picture_fields.bits.picture_type];
1500
1501     if (profile == GEN6_VC1_ADVANCED_PROFILE &&
1502         picture_type == GEN6_VC1_I_PICTURE)
1503         picture_type = GEN6_VC1_BI_PICTURE;
1504
1505     if (picture_type == GEN6_VC1_I_PICTURE || picture_type == GEN6_VC1_BI_PICTURE) /* I picture */
1506         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1507     else {
1508         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1509         /*
1510          * 8.3.6.2.1 Transform Type Selection
1511          * If variable-sized transform coding is not enabled,
1512          * then the 8x8 transform shall be used for all blocks.
1513          * it is also MFX_VC1_PIC_STATE requirement.
1514          */
1515         if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) {
1516             pic_param->transform_fields.bits.mb_level_transform_type_flag   = 1;
1517             pic_param->transform_fields.bits.frame_level_transform_type     = 0;
1518         }
1519     }
1520
1521     if (picture_type == GEN6_VC1_B_PICTURE) {
1522         struct gen6_vc1_surface *gen6_vc1_surface = NULL;
1523
1524         obj_surface = decode_state->reference_objects[1];
1525
1526         if (obj_surface)
1527             gen6_vc1_surface = obj_surface->private_data;
1528
1529         if (!gen6_vc1_surface ||
1530             (va_to_gen6_vc1_pic_type[gen6_vc1_surface->picture_type] == GEN6_VC1_I_PICTURE ||
1531              va_to_gen6_vc1_pic_type[gen6_vc1_surface->picture_type] == GEN6_VC1_BI_PICTURE))
1532             dmv_surface_valid = 0;
1533         else
1534             dmv_surface_valid = 1;
1535     }
1536
1537     assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1538
1539     if (pic_param->picture_fields.bits.frame_coding_mode < 2)
1540         fcm = pic_param->picture_fields.bits.frame_coding_mode;
1541     else {
1542         if (pic_param->picture_fields.bits.top_field_first)
1543             fcm = 2;
1544         else
1545             fcm = 3;
1546     }
1547
1548     if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_B_PICTURE) { /* B picture */
1549         brfd = pic_param->reference_fields.bits.reference_distance;
1550         brfd = (scale_factor * brfd) >> 8;
1551         brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
1552
1553         if (brfd < 0)
1554             brfd = 0;
1555     }
1556
1557     overlap = 0;
1558     if (profile != GEN6_VC1_ADVANCED_PROFILE){
1559         if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 &&
1560             pic_param->picture_fields.bits.picture_type != GEN6_VC1_B_PICTURE) {
1561             overlap = 1;
1562         }
1563     }else {
1564         if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_P_PICTURE &&
1565              pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
1566               overlap = 1;
1567         }
1568         if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_I_PICTURE ||
1569             pic_param->picture_fields.bits.picture_type == GEN6_VC1_BI_PICTURE){
1570              if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
1571                 overlap = 1;
1572              } else if (va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] == 2 ||
1573                         va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] == 3) {
1574                  overlap = 1;
1575              }
1576         }
1577     }
1578
1579     assert(pic_param->conditional_overlap_flag < 3);
1580     assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
1581
1582     BEGIN_BCS_BATCH(batch, 6);
1583     OUT_BCS_BATCH(batch, MFX_VC1_PIC_STATE | (6 - 2));
1584     OUT_BCS_BATCH(batch,
1585                   (ALIGN(pic_param->coded_height, 16) / 16) << 16 |
1586                   (ALIGN(pic_param->coded_width, 16) / 16));
1587     OUT_BCS_BATCH(batch,
1588                   pic_param->sequence_fields.bits.syncmarker << 31 |
1589                   1 << 29 | /* concealment */
1590                   alt_pq << 24 |
1591                   pic_param->entrypoint_fields.bits.loopfilter << 23 |
1592                   overlap << 22 |
1593                   (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 21 | /* implicit quantizer */
1594                   pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 16 |
1595                   alt_pquant_edge_mask << 12 |
1596                   alt_pquant_config << 10 |
1597                   pic_param->pic_quantizer_fields.bits.half_qp << 9 |
1598                   pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 8 |
1599                   va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] << 6 |
1600                   !pic_param->picture_fields.bits.is_first_field << 5 |
1601                   picture_type << 2 |
1602                   fcm << 0);
1603     OUT_BCS_BATCH(batch,
1604                   !!pic_param->bitplane_present.value << 23 |
1605                   !pic_param->bitplane_present.flags.bp_forward_mb << 22 |
1606                   !pic_param->bitplane_present.flags.bp_mv_type_mb << 21 |
1607                   !pic_param->bitplane_present.flags.bp_skip_mb << 20 |
1608                   !pic_param->bitplane_present.flags.bp_direct_mb << 19 |
1609                   !pic_param->bitplane_present.flags.bp_overflags << 18 |
1610                   !pic_param->bitplane_present.flags.bp_ac_pred << 17 |
1611                   !pic_param->bitplane_present.flags.bp_field_tx << 16 |
1612                   pic_param->mv_fields.bits.extended_dmv_range << 14 |
1613                   pic_param->mv_fields.bits.extended_mv_range << 12 |
1614                   pic_param->mv_fields.bits.four_mv_switch << 11 |
1615                   pic_param->fast_uvmc_flag << 10 |
1616                   unified_mv_mode << 8 |
1617                   ref_field_pic_polarity << 6 |
1618                   pic_param->reference_fields.bits.num_reference_pictures << 5 |
1619                   pic_param->reference_fields.bits.reference_distance << 0);
1620     OUT_BCS_BATCH(batch,
1621                   scale_factor << 24 |
1622                   pic_param->mv_fields.bits.mv_table << 20 |
1623                   pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
1624                   pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
1625                   pic_param->transform_fields.bits.frame_level_transform_type << 12 |
1626                   pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
1627                   pic_param->mb_mode_table << 8 |
1628                   trans_ac_y << 6 |
1629                   pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
1630                   pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
1631                   pic_param->cbp_table << 0);
1632     OUT_BCS_BATCH(batch,
1633                   dmv_surface_valid << 13 |
1634                   brfd << 8 |
1635                   ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1));
1636     ADVANCE_BCS_BATCH(batch);
1637 }
1638
1639 static void
1640 gen6_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
1641                              struct decode_state *decode_state,
1642                              struct gen6_mfd_context *gen6_mfd_context)
1643 {
1644     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1645     VAPictureParameterBufferVC1 *pic_param;
1646     int interpolation_mode = 0;
1647     int intensitycomp_single;
1648
1649     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1650     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1651
1652     if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
1653         (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1654          pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
1655         interpolation_mode = 2; /* Half-pel bilinear */
1656     else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
1657              (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1658               pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
1659         interpolation_mode = 0; /* Half-pel bicubic */
1660     else
1661         interpolation_mode = 1; /* Quarter-pel bicubic */
1662
1663     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1664     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1665     intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
1666
1667     BEGIN_BCS_BATCH(batch, 7);
1668     OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (7 - 2));
1669     OUT_BCS_BATCH(batch,
1670                   0 << 8 | /* FIXME: interlace mode */
1671                   pic_param->rounding_control << 4 |
1672                   va_to_gen6_vc1_profile[pic_param->sequence_fields.bits.profile] << 2);
1673     OUT_BCS_BATCH(batch,
1674                   pic_param->luma_shift << 16 |
1675                   pic_param->luma_scale << 0); /* FIXME: Luma Scaling */
1676     OUT_BCS_BATCH(batch, 0);
1677     OUT_BCS_BATCH(batch, 0);
1678     OUT_BCS_BATCH(batch, 0);
1679     OUT_BCS_BATCH(batch,
1680                   interpolation_mode << 19 |
1681                   pic_param->fast_uvmc_flag << 18 |
1682                   0 << 17 | /* FIXME: scale up or down ??? */
1683                   pic_param->range_reduction_frame << 16 |
1684                   0 << 6 | /* FIXME: double ??? */
1685                   0 << 4 |
1686                   intensitycomp_single << 2 |
1687                   intensitycomp_single << 0);
1688     ADVANCE_BCS_BATCH(batch);
1689 }
1690
1691
1692 static void
1693 gen6_mfd_vc1_directmode_state(VADriverContextP ctx,
1694                               struct decode_state *decode_state,
1695                               struct gen6_mfd_context *gen6_mfd_context)
1696 {
1697     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1698     struct object_surface *obj_surface;
1699     dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
1700
1701     obj_surface = decode_state->render_object;
1702
1703     if (obj_surface && obj_surface->private_data) {
1704         dmv_write_buffer = ((struct gen6_vc1_surface *)(obj_surface->private_data))->dmv;
1705     }
1706
1707     obj_surface = decode_state->reference_objects[1];
1708
1709     if (obj_surface && obj_surface->private_data) {
1710         dmv_read_buffer = ((struct gen6_vc1_surface *)(obj_surface->private_data))->dmv;
1711     }
1712
1713     BEGIN_BCS_BATCH(batch, 3);
1714     OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
1715
1716     if (dmv_write_buffer)
1717         OUT_BCS_RELOC(batch, dmv_write_buffer,
1718                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
1719                       0);
1720     else
1721         OUT_BCS_BATCH(batch, 0);
1722
1723     if (dmv_read_buffer)
1724         OUT_BCS_RELOC(batch, dmv_read_buffer,
1725                       I915_GEM_DOMAIN_INSTRUCTION, 0,
1726                       0);
1727     else
1728         OUT_BCS_BATCH(batch, 0);
1729
1730     ADVANCE_BCS_BATCH(batch);
1731 }
1732
1733 static int
1734 gen6_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
1735 {
1736     int out_slice_data_bit_offset;
1737     int slice_header_size = in_slice_data_bit_offset / 8;
1738     int i, j;
1739
1740     if (profile != 3)
1741         out_slice_data_bit_offset = in_slice_data_bit_offset;
1742     else {
1743         for (i = 0, j = 0; i < slice_header_size; i++, j++) {
1744             if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
1745                 i++, j += 2;
1746             }
1747         }
1748
1749         out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
1750     }
1751
1752     return out_slice_data_bit_offset;
1753 }
1754
1755 static void
1756 gen6_mfd_vc1_bsd_object(VADriverContextP ctx,
1757                         VAPictureParameterBufferVC1 *pic_param,
1758                         VASliceParameterBufferVC1 *slice_param,
1759                         VASliceParameterBufferVC1 *next_slice_param,
1760                         dri_bo *slice_data_bo,
1761                         struct gen6_mfd_context *gen6_mfd_context)
1762 {
1763     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1764     int next_slice_start_vert_pos;
1765     int macroblock_offset;
1766     uint8_t *slice_data = NULL;
1767
1768     dri_bo_map(slice_data_bo, 0);
1769     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
1770     macroblock_offset = gen6_mfd_vc1_get_macroblock_bit_offset(slice_data,
1771                                                                slice_param->macroblock_offset,
1772                                                                pic_param->sequence_fields.bits.profile);
1773     dri_bo_unmap(slice_data_bo);
1774
1775     if (next_slice_param)
1776         next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
1777     else
1778         next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
1779
1780     BEGIN_BCS_BATCH(batch, 4);
1781     OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (4 - 2));
1782     OUT_BCS_BATCH(batch,
1783                   slice_param->slice_data_size - (macroblock_offset >> 3));
1784     OUT_BCS_BATCH(batch,
1785                   slice_param->slice_data_offset + (macroblock_offset >> 3));
1786     OUT_BCS_BATCH(batch,
1787                   slice_param->slice_vertical_position << 24 |
1788                   next_slice_start_vert_pos << 16 |
1789                   (macroblock_offset & 0x7));
1790     ADVANCE_BCS_BATCH(batch);
1791 }
1792
1793 static void
1794 gen6_mfd_vc1_decode_picture(VADriverContextP ctx,
1795                             struct decode_state *decode_state,
1796                             struct gen6_mfd_context *gen6_mfd_context)
1797 {
1798     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1799     VAPictureParameterBufferVC1 *pic_param;
1800     VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
1801     dri_bo *slice_data_bo;
1802     int i, j;
1803
1804     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1805     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1806
1807     gen6_mfd_vc1_decode_init(ctx, decode_state, gen6_mfd_context);
1808     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1809     intel_batchbuffer_emit_mi_flush(batch);
1810     gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1811     gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1812     gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1813     gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1814     gen6_mfd_vc1_pic_state(ctx, decode_state, gen6_mfd_context);
1815     gen6_mfd_vc1_pred_pipe_state(ctx, decode_state, gen6_mfd_context);
1816     gen6_mfd_vc1_directmode_state(ctx, decode_state, gen6_mfd_context);
1817
1818     for (j = 0; j < decode_state->num_slice_params; j++) {
1819         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1820         slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
1821         slice_data_bo = decode_state->slice_datas[j]->bo;
1822         gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen6_mfd_context);
1823
1824         if (j == decode_state->num_slice_params - 1)
1825             next_slice_group_param = NULL;
1826         else
1827             next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
1828
1829         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1830             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1831
1832             if (i < decode_state->slice_params[j]->num_elements - 1)
1833                 next_slice_param = slice_param + 1;
1834             else
1835                 next_slice_param = next_slice_group_param;
1836
1837             gen6_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen6_mfd_context);
1838             slice_param++;
1839         }
1840     }
1841
1842     intel_batchbuffer_end_atomic(batch);
1843     intel_batchbuffer_flush(batch);
1844 }
1845
1846 static VAStatus
1847 gen6_mfd_decode_picture(VADriverContextP ctx,
1848                         VAProfile profile,
1849                         union codec_state *codec_state,
1850                         struct hw_context *hw_context)
1851
1852 {
1853     struct gen6_mfd_context *gen6_mfd_context = (struct gen6_mfd_context *)hw_context;
1854     struct decode_state *decode_state = &codec_state->decode;
1855     VAStatus vaStatus;
1856
1857     assert(gen6_mfd_context);
1858
1859     vaStatus = intel_decoder_sanity_check_input(ctx, profile, decode_state);
1860
1861     if (vaStatus != VA_STATUS_SUCCESS)
1862         goto out;
1863
1864     switch (profile) {
1865     case VAProfileMPEG2Simple:
1866     case VAProfileMPEG2Main:
1867         gen6_mfd_mpeg2_decode_picture(ctx, decode_state, gen6_mfd_context);
1868         break;
1869
1870     case VAProfileH264ConstrainedBaseline:
1871     case VAProfileH264Main:
1872     case VAProfileH264High:
1873         gen6_mfd_avc_decode_picture(ctx, decode_state, gen6_mfd_context);
1874         break;
1875
1876     case VAProfileVC1Simple:
1877     case VAProfileVC1Main:
1878     case VAProfileVC1Advanced:
1879         gen6_mfd_vc1_decode_picture(ctx, decode_state, gen6_mfd_context);
1880         break;
1881
1882     default:
1883         assert(0);
1884         break;
1885     }
1886
1887     vaStatus = VA_STATUS_SUCCESS;
1888
1889 out:
1890     return vaStatus;
1891 }
1892
1893 static void
1894 gen6_mfd_context_destroy(void *hw_context)
1895 {
1896     struct gen6_mfd_context *gen6_mfd_context = (struct gen6_mfd_context *)hw_context;
1897
1898     dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
1899     gen6_mfd_context->post_deblocking_output.bo = NULL;
1900
1901     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
1902     gen6_mfd_context->pre_deblocking_output.bo = NULL;
1903
1904     dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
1905     gen6_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
1906
1907     dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1908     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1909
1910     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1911     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1912
1913     dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo);
1914     gen6_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
1915
1916     dri_bo_unreference(gen6_mfd_context->bitplane_read_buffer.bo);
1917     gen6_mfd_context->bitplane_read_buffer.bo = NULL;
1918
1919     intel_batchbuffer_free(gen6_mfd_context->base.batch);
1920     free(gen6_mfd_context);
1921 }
1922
1923 struct hw_context *
1924 gen6_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
1925 {
1926     struct intel_driver_data *intel = intel_driver_data(ctx);
1927     struct gen6_mfd_context *gen6_mfd_context = calloc(1, sizeof(struct gen6_mfd_context));
1928     int i;
1929
1930     gen6_mfd_context->base.destroy = gen6_mfd_context_destroy;
1931     gen6_mfd_context->base.run = gen6_mfd_decode_picture;
1932     gen6_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
1933
1934     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
1935         gen6_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
1936         gen6_mfd_context->reference_surface[i].frame_store_id = -1;
1937         gen6_mfd_context->reference_surface[i].obj_surface = NULL;
1938     }
1939
1940     gen6_mfd_context->wa_mpeg2_slice_vertical_position = -1;
1941
1942     return (struct hw_context *)gen6_mfd_context;
1943 }