src/gen6_mfd.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include "sysdeps.h"
  30 #include "intel_batchbuffer.h"
  31 #include "intel_driver.h"
  32 #include "i965_defines.h"
  33 #include "i965_drv_video.h"
  34 #include "i965_decoder_utils.h"
  35
  36 #include "gen6_mfd.h"
  37 #include "intel_media.h"
  38
  39 static const uint32_t zigzag_direct[64] = {
  40     0,   1,  8, 16,  9,  2,  3, 10,
  41     17, 24, 32, 25, 18, 11,  4,  5,
  42     12, 19, 26, 33, 40, 48, 41, 34,
  43     27, 20, 13,  6,  7, 14, 21, 28,
  44     35, 42, 49, 56, 57, 50, 43, 36,
  45     29, 22, 15, 23, 30, 37, 44, 51,
  46     58, 59, 52, 45, 38, 31, 39, 46,
  47     53, 60, 61, 54, 47, 55, 62, 63
  48 };
  49
  50 static void
  51 gen6_mfd_init_avc_surface(VADriverContextP ctx,
  52                           VAPictureParameterBufferH264 *pic_param,
  53                           struct object_surface *obj_surface)
  54 {
  55     struct i965_driver_data *i965 = i965_driver_data(ctx);
  56     GenAvcSurface *gen6_avc_surface = obj_surface->private_data;
  57     int height_in_mbs;
  58
  59     obj_surface->free_private_data = gen_free_avc_surface;
  60     height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */
  61
  62     if (!gen6_avc_surface) {
  63         gen6_avc_surface = calloc(sizeof(GenAvcSurface), 1);
  64         gen6_avc_surface->frame_store_id = -1;
  65         assert((obj_surface->size & 0x3f) == 0);
  66         obj_surface->private_data = gen6_avc_surface;
  67     }
  68
  69     gen6_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
  70                                          !pic_param->seq_fields.bits.direct_8x8_inference_flag);
  71
  72     if (gen6_avc_surface->dmv_top == NULL) {
  73         gen6_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
  74                                                  "direct mv w/r buffer",
  75                                                  128 * height_in_mbs * 64,      /* scalable with frame height */
  76                                                  0x1000);
  77     }
  78
  79     if (gen6_avc_surface->dmv_bottom_flag &&
  80         gen6_avc_surface->dmv_bottom == NULL) {
  81         gen6_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
  82                                                     "direct mv w/r buffer",
  83                                                     128 * height_in_mbs * 64,   /* scalable with frame height */
  84                                                     0x1000);
  85     }
  86 }
  87
  88 static void
  89 gen6_mfd_pipe_mode_select(VADriverContextP ctx,
  90                           struct decode_state *decode_state,
  91                           int standard_select,
  92                           struct gen6_mfd_context *gen6_mfd_context)
  93 {
  94     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
  95
  96     assert(standard_select == MFX_FORMAT_MPEG2 ||
  97            standard_select == MFX_FORMAT_AVC ||
  98            standard_select == MFX_FORMAT_VC1);
  99
 100     BEGIN_BCS_BATCH(batch, 4);
 101     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
 102     OUT_BCS_BATCH(batch,
 103                   (MFD_MODE_VLD << 16) | /* VLD mode */
 104                   (0 << 10) | /* disable Stream-Out */
 105                   (gen6_mfd_context->post_deblocking_output.valid << 9)  | /* Post Deblocking Output */
 106                   (gen6_mfd_context->pre_deblocking_output.valid << 8)  | /* Pre Deblocking Output */
 107                   (0 << 7)  | /* disable TLB prefectch */
 108                   (0 << 5)  | /* not in stitch mode */
 109                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
 110                   (standard_select << 0));
 111     OUT_BCS_BATCH(batch,
 112                   (0 << 20) | /* round flag in PB slice */
 113                   (0 << 19) | /* round flag in Intra8x8 */
 114                   (0 << 7)  | /* expand NOA bus flag */
 115                   (1 << 6)  | /* must be 1 */
 116                   (0 << 5)  | /* disable clock gating for NOA */
 117                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
 118                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 119                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 120                   (0 << 1)  | /* AVC long field motion vector */
 121                   (1 << 0));  /* always calculate AVC ILDB boundary strength */
 122     OUT_BCS_BATCH(batch, 0);
 123     ADVANCE_BCS_BATCH(batch);
 124 }
 125
 126 static void
 127 gen6_mfd_surface_state(VADriverContextP ctx,
 128                        struct decode_state *decode_state,
 129                        int standard_select,
 130                        struct gen6_mfd_context *gen6_mfd_context)
 131 {
 132     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 133     struct object_surface *obj_surface = decode_state->render_object;
 134     unsigned int surface_format;
 135
 136     surface_format = obj_surface->fourcc == VA_FOURCC_Y800 ?
 137         MFX_SURFACE_MONOCHROME : MFX_SURFACE_PLANAR_420_8;
 138
 139     BEGIN_BCS_BATCH(batch, 6);
 140     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 141     OUT_BCS_BATCH(batch, 0);
 142     OUT_BCS_BATCH(batch,
 143                   ((obj_surface->orig_height - 1) << 19) |
 144                   ((obj_surface->orig_width - 1) << 6));
 145     OUT_BCS_BATCH(batch,
 146                   (surface_format << 28) | /* 420 planar YUV surface */
 147                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
 148                   (0 << 22) | /* surface object control state, FIXME??? */
 149                   ((obj_surface->width - 1) << 3) | /* pitch */
 150                   (0 << 2)  | /* must be 0 for interleave U/V */
 151                   (1 << 1)  | /* must be y-tiled */
 152                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, FIXME: must be 1 ??? */
 153     OUT_BCS_BATCH(batch,
 154                   (0 << 16) | /* must be 0 for interleave U/V */
 155                   (obj_surface->height)); /* y offset for U(cb) */
 156     OUT_BCS_BATCH(batch, 0);
 157     ADVANCE_BCS_BATCH(batch);
 158 }
 159
 160 static void
 161 gen6_mfd_pipe_buf_addr_state(VADriverContextP ctx,
 162                              struct decode_state *decode_state,
 163                              int standard_select,
 164                              struct gen6_mfd_context *gen6_mfd_context)
 165 {
 166     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 167     int i;
 168
 169     BEGIN_BCS_BATCH(batch, 24);
 170     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 171     if (gen6_mfd_context->pre_deblocking_output.valid)
 172         OUT_BCS_RELOC(batch, gen6_mfd_context->pre_deblocking_output.bo,
 173                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 174                       0);
 175     else
 176         OUT_BCS_BATCH(batch, 0);
 177
 178     if (gen6_mfd_context->post_deblocking_output.valid)
 179         OUT_BCS_RELOC(batch, gen6_mfd_context->post_deblocking_output.bo,
 180                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 181                       0);
 182     else
 183         OUT_BCS_BATCH(batch, 0);
 184
 185     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 186     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 187
 188     if (gen6_mfd_context->intra_row_store_scratch_buffer.valid)
 189         OUT_BCS_RELOC(batch, gen6_mfd_context->intra_row_store_scratch_buffer.bo,
 190                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 191                       0);
 192     else
 193         OUT_BCS_BATCH(batch, 0);
 194
 195     if (gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
 196         OUT_BCS_RELOC(batch, gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
 197                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 198                       0);
 199     else
 200         OUT_BCS_BATCH(batch, 0);
 201
 202     /* DW 7..22 */
 203     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
 204         struct object_surface *obj_surface;
 205
 206         if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 207             gen6_mfd_context->reference_surface[i].obj_surface &&
 208             gen6_mfd_context->reference_surface[i].obj_surface->bo) {
 209             obj_surface = gen6_mfd_context->reference_surface[i].obj_surface;
 210
 211             OUT_BCS_RELOC(batch, obj_surface->bo,
 212                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 213                           0);
 214         } else {
 215             OUT_BCS_BATCH(batch, 0);
 216         }
 217     }
 218
 219     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
 220     ADVANCE_BCS_BATCH(batch);
 221 }
 222
 223 static void
 224 gen6_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
 225                                  dri_bo *slice_data_bo,
 226                                  int standard_select,
 227                                  struct gen6_mfd_context *gen6_mfd_context)
 228 {
 229     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 230
 231     BEGIN_BCS_BATCH(batch, 11);
 232     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 233     OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
 234     OUT_BCS_BATCH(batch, 0);
 235     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 236     OUT_BCS_BATCH(batch, 0);
 237     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 238     OUT_BCS_BATCH(batch, 0);
 239     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 240     OUT_BCS_BATCH(batch, 0);
 241     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 242     OUT_BCS_BATCH(batch, 0);
 243     ADVANCE_BCS_BATCH(batch);
 244 }
 245
 246 static void
 247 gen6_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
 248                                  struct decode_state *decode_state,
 249                                  int standard_select,
 250                                  struct gen6_mfd_context *gen6_mfd_context)
 251 {
 252     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 253
 254     BEGIN_BCS_BATCH(batch, 4);
 255     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 256
 257     if (gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
 258         OUT_BCS_RELOC(batch, gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
 259                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 260                       0);
 261     else
 262         OUT_BCS_BATCH(batch, 0);
 263
 264     if (gen6_mfd_context->mpr_row_store_scratch_buffer.valid)
 265         OUT_BCS_RELOC(batch, gen6_mfd_context->mpr_row_store_scratch_buffer.bo,
 266                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 267                       0);
 268     else
 269         OUT_BCS_BATCH(batch, 0);
 270
 271     if (gen6_mfd_context->bitplane_read_buffer.valid)
 272         OUT_BCS_RELOC(batch, gen6_mfd_context->bitplane_read_buffer.bo,
 273                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 274                       0);
 275     else
 276         OUT_BCS_BATCH(batch, 0);
 277
 278     ADVANCE_BCS_BATCH(batch);
 279 }
 280
 281 static void
 282 gen6_mfd_avc_img_state(VADriverContextP ctx,
 283                        struct decode_state *decode_state,
 284                        struct gen6_mfd_context *gen6_mfd_context)
 285 {
 286     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 287     int qm_present_flag;
 288     int img_struct;
 289     int mbaff_frame_flag;
 290     unsigned int width_in_mbs, height_in_mbs;
 291     VAPictureParameterBufferH264 *pic_param;
 292
 293     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 294     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 295
 296     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
 297         qm_present_flag = 1;
 298     else
 299         qm_present_flag = 0; /* built-in QM matrices */
 300
 301     if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
 302         img_struct = 1;
 303     else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
 304         img_struct = 3;
 305     else
 306         img_struct = 0;
 307
 308     if ((img_struct & 0x1) == 0x1) {
 309         assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
 310     } else {
 311         assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
 312     }
 313
 314     if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
 315         assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
 316         assert(pic_param->pic_fields.bits.field_pic_flag == 0);
 317     } else {
 318         assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
 319     }
 320
 321     mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
 322                         !pic_param->pic_fields.bits.field_pic_flag);
 323
 324     width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
 325     height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */
 326     assert(!((width_in_mbs * height_in_mbs) & 0x8000)); /* hardware requirement */
 327
 328     /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
 329     assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
 330            pic_param->seq_fields.bits.chroma_format_idc == 1);  /* 4:2:0 */
 331     assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
 332
 333     BEGIN_BCS_BATCH(batch, 13);
 334     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
 335     OUT_BCS_BATCH(batch,
 336                   ((width_in_mbs * height_in_mbs) & 0x7fff));
 337     OUT_BCS_BATCH(batch,
 338                   (height_in_mbs << 16) |
 339                   (width_in_mbs << 0));
 340     OUT_BCS_BATCH(batch,
 341                   ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
 342                   ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
 343                   (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
 344                   (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
 345                   (1 << 12) | /* always 1, hardware requirement */
 346                   (qm_present_flag << 10) |
 347                   (img_struct << 8) |
 348                   (16 << 0));
 349     OUT_BCS_BATCH(batch,
 350                   (pic_param->seq_fields.bits.chroma_format_idc << 10) |
 351                   (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
 352                   ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
 353                   (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
 354                   (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
 355                   (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
 356                   (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
 357                   (mbaff_frame_flag << 1) |
 358                   (pic_param->pic_fields.bits.field_pic_flag << 0));
 359     OUT_BCS_BATCH(batch, 0);
 360     OUT_BCS_BATCH(batch, 0);
 361     OUT_BCS_BATCH(batch, 0);
 362     OUT_BCS_BATCH(batch, 0);
 363     OUT_BCS_BATCH(batch, 0);
 364     OUT_BCS_BATCH(batch, 0);
 365     OUT_BCS_BATCH(batch, 0);
 366     OUT_BCS_BATCH(batch, 0);
 367     ADVANCE_BCS_BATCH(batch);
 368 }
 369
 370 static void
 371 gen6_mfd_avc_qm_state(VADriverContextP ctx,
 372                       struct decode_state *decode_state,
 373                       struct gen6_mfd_context *gen6_mfd_context)
 374 {
 375     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 376     int cmd_len;
 377     VAIQMatrixBufferH264 *iq_matrix;
 378     VAPictureParameterBufferH264 *pic_param;
 379
 380     if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
 381         return;
 382
 383     iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
 384
 385     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 386     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 387
 388     cmd_len = 2 + 6 * 4; /* always load six 4x4 scaling matrices */
 389
 390     if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
 391         cmd_len += 2 * 16; /* load two 8x8 scaling matrices */
 392
 393     BEGIN_BCS_BATCH(batch, cmd_len);
 394     OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | (cmd_len - 2));
 395
 396     if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
 397         OUT_BCS_BATCH(batch,
 398                       (0x0  << 8) | /* don't use default built-in matrices */
 399                       (0xff << 0)); /* six 4x4 and two 8x8 scaling matrices */
 400     else
 401         OUT_BCS_BATCH(batch,
 402                       (0x0  << 8) | /* don't use default built-in matrices */
 403                       (0x3f << 0)); /* six 4x4 scaling matrices */
 404
 405     intel_batchbuffer_data(batch, &iq_matrix->ScalingList4x4[0][0], 6 * 4 * 4);
 406
 407     if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
 408         intel_batchbuffer_data(batch, &iq_matrix->ScalingList8x8[0][0], 2 * 16 * 4);
 409
 410     ADVANCE_BCS_BATCH(batch);
 411 }
 412
 413 static void
 414 gen6_mfd_avc_directmode_state(VADriverContextP ctx,
 415                               struct decode_state *decode_state,
 416                               VAPictureParameterBufferH264 *pic_param,
 417                               VASliceParameterBufferH264 *slice_param,
 418                               struct gen6_mfd_context *gen6_mfd_context)
 419 {
 420     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 421     struct object_surface *obj_surface;
 422     GenAvcSurface *gen6_avc_surface;
 423     VAPictureH264 *va_pic;
 424     int i;
 425
 426     BEGIN_BCS_BATCH(batch, 69);
 427     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 428
 429     /* reference surfaces 0..15 */
 430     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
 431         if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 432             gen6_mfd_context->reference_surface[i].obj_surface &&
 433             gen6_mfd_context->reference_surface[i].obj_surface->private_data) {
 434
 435             obj_surface = gen6_mfd_context->reference_surface[i].obj_surface;
 436             gen6_avc_surface = obj_surface->private_data;
 437             OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 438                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 439                           0);
 440
 441             if (gen6_avc_surface->dmv_bottom_flag == 1)
 442                 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_bottom,
 443                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 444                               0);
 445             else
 446                 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 447                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 448                               0);
 449         } else {
 450             OUT_BCS_BATCH(batch, 0);
 451             OUT_BCS_BATCH(batch, 0);
 452         }
 453     }
 454
 455     /* the current decoding frame/field */
 456     va_pic = &pic_param->CurrPic;
 457     obj_surface = decode_state->render_object;
 458     assert(obj_surface->bo && obj_surface->private_data);
 459     gen6_avc_surface = obj_surface->private_data;
 460
 461     OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 462                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 463                   0);
 464
 465     if (gen6_avc_surface->dmv_bottom_flag == 1)
 466         OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_bottom,
 467                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 468                       0);
 469     else
 470         OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 471                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 472                       0);
 473
 474     /* POC List */
 475     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
 476         obj_surface = gen6_mfd_context->reference_surface[i].obj_surface;
 477
 478         if (obj_surface) {
 479             const VAPictureH264 * const va_pic = avc_find_picture(
 480                 obj_surface->base.id, pic_param->ReferenceFrames,
 481                 ARRAY_ELEMS(pic_param->ReferenceFrames));
 482
 483             assert(va_pic != NULL);
 484             OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 485             OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 486         } else {
 487             OUT_BCS_BATCH(batch, 0);
 488             OUT_BCS_BATCH(batch, 0);
 489         }
 490     }
 491
 492     va_pic = &pic_param->CurrPic;
 493     OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 494     OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 495
 496     ADVANCE_BCS_BATCH(batch);
 497 }
 498
 499 static void
 500 gen6_mfd_avc_slice_state(VADriverContextP ctx,
 501                          VAPictureParameterBufferH264 *pic_param,
 502                          VASliceParameterBufferH264 *slice_param,
 503                          VASliceParameterBufferH264 *next_slice_param,
 504                          struct gen6_mfd_context *gen6_mfd_context)
 505 {
 506     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 507     int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 508     int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
 509     int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
 510     int num_ref_idx_l0, num_ref_idx_l1;
 511     int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
 512                          pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
 513     int weighted_pred_idc = 0;
 514     int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
 515     unsigned int chroma_log2_weight_denom, luma_log2_weight_denom;
 516     int slice_type;
 517
 518     if (slice_param->slice_type == SLICE_TYPE_I ||
 519         slice_param->slice_type == SLICE_TYPE_SI) {
 520         slice_type = SLICE_TYPE_I;
 521     } else if (slice_param->slice_type == SLICE_TYPE_P ||
 522                slice_param->slice_type == SLICE_TYPE_SP) {
 523         slice_type = SLICE_TYPE_P;
 524     } else {
 525         assert(slice_param->slice_type == SLICE_TYPE_B);
 526         slice_type = SLICE_TYPE_B;
 527     }
 528
 529     luma_log2_weight_denom   = slice_param->luma_log2_weight_denom;
 530     chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
 531
 532     if (slice_type == SLICE_TYPE_I) {
 533         assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
 534         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 535         num_ref_idx_l0 = 0;
 536         num_ref_idx_l1 = 0;
 537     } else if (slice_type == SLICE_TYPE_P) {
 538         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 539         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 540         num_ref_idx_l1 = 0;
 541         weighted_pred_idc = (pic_param->pic_fields.bits.weighted_pred_flag == 1);
 542     } else {
 543         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 544         num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
 545         weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
 546
 547         if (weighted_pred_idc == 2) {
 548             /* 8.4.3 - Derivation process for prediction weights (8-279) */
 549             luma_log2_weight_denom   = 5;
 550             chroma_log2_weight_denom = 5;
 551         }
 552     }
 553
 554     first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture;
 555     slice_hor_pos = first_mb_in_slice % width_in_mbs;
 556     slice_ver_pos = first_mb_in_slice / width_in_mbs;
 557
 558     if (next_slice_param) {
 559         first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture;
 560         next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
 561         next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
 562     } else {
 563         next_slice_hor_pos = 0;
 564         next_slice_ver_pos = height_in_mbs;
 565     }
 566
 567     BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
 568     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
 569     OUT_BCS_BATCH(batch, slice_type);
 570     OUT_BCS_BATCH(batch,
 571                   (num_ref_idx_l1 << 24) |
 572                   (num_ref_idx_l0 << 16) |
 573                   (chroma_log2_weight_denom << 8) |
 574                   (luma_log2_weight_denom << 0));
 575     OUT_BCS_BATCH(batch,
 576                   (weighted_pred_idc << 30) |
 577                   (slice_param->direct_spatial_mv_pred_flag << 29) |
 578                   (slice_param->disable_deblocking_filter_idc << 27) |
 579                   (slice_param->cabac_init_idc << 24) |
 580                   ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
 581                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 582                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 583     OUT_BCS_BATCH(batch,
 584                   (slice_ver_pos << 24) |
 585                   (slice_hor_pos << 16) |
 586                   (first_mb_in_slice << 0));
 587     OUT_BCS_BATCH(batch,
 588                   (next_slice_ver_pos << 16) |
 589                   (next_slice_hor_pos << 0));
 590     OUT_BCS_BATCH(batch,
 591                   (next_slice_param == NULL) << 19); /* last slice flag */
 592     OUT_BCS_BATCH(batch, 0);
 593     OUT_BCS_BATCH(batch, 0);
 594     OUT_BCS_BATCH(batch, 0);
 595     OUT_BCS_BATCH(batch, 0);
 596     ADVANCE_BCS_BATCH(batch);
 597 }
 598
 599 static void
 600 gen6_mfd_avc_phantom_slice_state(VADriverContextP ctx,
 601                                  VAPictureParameterBufferH264 *pic_param,
 602                                  VASliceParameterBufferH264 *next_slice_param,
 603                                  struct gen6_mfd_context *gen6_mfd_context)
 604 {
 605     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 606     int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 607     int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
 608     int slice_hor_pos, slice_ver_pos, slice_start_mb_num, next_slice_hor_pos, next_slice_ver_pos;
 609     int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
 610                          pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
 611
 612     if (next_slice_param) {
 613         int first_mb_in_next_slice;
 614
 615         slice_hor_pos = 0;
 616         slice_ver_pos = 0;
 617         slice_start_mb_num = 0;
 618         first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture;
 619         next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
 620         next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
 621     } else {
 622         slice_hor_pos = 0;
 623         slice_ver_pos = height_in_mbs;
 624         slice_start_mb_num = width_in_mbs * height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag);
 625         next_slice_hor_pos = 0;
 626         next_slice_ver_pos = 0;
 627     }
 628
 629     BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
 630     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
 631     OUT_BCS_BATCH(batch, 0);
 632     OUT_BCS_BATCH(batch, 0);
 633     OUT_BCS_BATCH(batch, 0);
 634     OUT_BCS_BATCH(batch,
 635                   slice_ver_pos << 24 |
 636                   slice_hor_pos << 16 |
 637                   slice_start_mb_num << 0);
 638     OUT_BCS_BATCH(batch,
 639                   next_slice_ver_pos << 16 |
 640                   next_slice_hor_pos << 0);
 641     OUT_BCS_BATCH(batch, 0);
 642     OUT_BCS_BATCH(batch, 0);
 643     OUT_BCS_BATCH(batch, 0);
 644     OUT_BCS_BATCH(batch, 0);
 645     OUT_BCS_BATCH(batch, 0);
 646     ADVANCE_BCS_BATCH(batch);
 647 }
 648
 649 static inline void
 650 gen6_mfd_avc_ref_idx_state(VADriverContextP ctx,
 651                            VAPictureParameterBufferH264 *pic_param,
 652                            VASliceParameterBufferH264 *slice_param,
 653                            struct gen6_mfd_context *gen6_mfd_context)
 654 {
 655     gen6_send_avc_ref_idx_state(
 656         gen6_mfd_context->base.batch,
 657         slice_param,
 658         gen6_mfd_context->reference_surface
 659     );
 660 }
 661
 662 static void
 663 gen6_mfd_avc_weightoffset_state(VADriverContextP ctx,
 664                                 VAPictureParameterBufferH264 *pic_param,
 665                                 VASliceParameterBufferH264 *slice_param,
 666                                 struct gen6_mfd_context *gen6_mfd_context)
 667 {
 668     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 669     int i, j, num_weight_offset_table = 0;
 670     short weightoffsets[32 * 6];
 671
 672     if ((slice_param->slice_type == SLICE_TYPE_P ||
 673          slice_param->slice_type == SLICE_TYPE_SP) &&
 674         (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
 675         num_weight_offset_table = 1;
 676     }
 677
 678     if ((slice_param->slice_type == SLICE_TYPE_B) &&
 679         (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
 680         num_weight_offset_table = 2;
 681     }
 682
 683     for (i = 0; i < num_weight_offset_table; i++) {
 684         BEGIN_BCS_BATCH(batch, 98);
 685         OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
 686         OUT_BCS_BATCH(batch, i);
 687
 688         if (i == 0) {
 689             for (j = 0; j < 32; j++) {
 690                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
 691                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
 692                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
 693                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
 694                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
 695                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
 696             }
 697         } else {
 698             for (j = 0; j < 32; j++) {
 699                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
 700                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
 701                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
 702                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
 703                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
 704                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
 705             }
 706         }
 707
 708         intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
 709         ADVANCE_BCS_BATCH(batch);
 710     }
 711 }
 712
 713 static void
 714 gen6_mfd_avc_bsd_object(VADriverContextP ctx,
 715                         VAPictureParameterBufferH264 *pic_param,
 716                         VASliceParameterBufferH264 *slice_param,
 717                         dri_bo *slice_data_bo,
 718                         struct gen6_mfd_context *gen6_mfd_context)
 719 {
 720     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 721     unsigned int slice_data_bit_offset;
 722
 723     slice_data_bit_offset = avc_get_first_mb_bit_offset(
 724         slice_data_bo,
 725         slice_param,
 726         pic_param->pic_fields.bits.entropy_coding_mode_flag
 727     );
 728
 729     BEGIN_BCS_BATCH(batch, 6);
 730     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
 731     OUT_BCS_BATCH(batch,
 732                   (slice_param->slice_data_size - slice_param->slice_data_offset));
 733     OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
 734     OUT_BCS_BATCH(batch,
 735                   (0 << 31) |
 736                   (0 << 14) |
 737                   (0 << 12) |
 738                   (0 << 10) |
 739                   (0 << 8));
 740     OUT_BCS_BATCH(batch,
 741                   ((slice_data_bit_offset >> 3) << 16) |
 742                   (1 << 7)  |
 743                   (1 << 6)  |
 744                   ((0x7 - (slice_data_bit_offset & 0x7)) << 0));
 745     OUT_BCS_BATCH(batch, 0);
 746     ADVANCE_BCS_BATCH(batch);
 747 }
 748
 749 static void
 750 gen6_mfd_avc_phantom_slice_bsd_object(VADriverContextP ctx,
 751                                       VAPictureParameterBufferH264 *pic_param,
 752                                       struct gen6_mfd_context *gen6_mfd_context)
 753 {
 754     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 755
 756     BEGIN_BCS_BATCH(batch, 6);
 757     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
 758     OUT_BCS_BATCH(batch, 0);
 759     OUT_BCS_BATCH(batch, 0);
 760     OUT_BCS_BATCH(batch, 0);
 761     OUT_BCS_BATCH(batch, 0);
 762     OUT_BCS_BATCH(batch, 0);
 763     ADVANCE_BCS_BATCH(batch);
 764 }
 765
 766 static void
 767 gen6_mfd_avc_phantom_slice(VADriverContextP ctx,
 768                            VAPictureParameterBufferH264 *pic_param,
 769                            VASliceParameterBufferH264 *next_slice_param,
 770                            struct gen6_mfd_context *gen6_mfd_context)
 771 {
 772     gen6_mfd_avc_phantom_slice_state(ctx, pic_param, next_slice_param, gen6_mfd_context);
 773     gen6_mfd_avc_phantom_slice_bsd_object(ctx, pic_param, gen6_mfd_context);
 774 }
 775
 776 static void
 777 gen6_mfd_avc_phantom_slice_first(VADriverContextP ctx,
 778                                  VAPictureParameterBufferH264 *pic_param,
 779                                  VASliceParameterBufferH264 *next_slice_param,
 780                                  struct gen6_mfd_context *gen6_mfd_context)
 781 {
 782     gen6_mfd_avc_phantom_slice(ctx, pic_param, next_slice_param, gen6_mfd_context);
 783 }
 784
 785 static void
 786 gen6_mfd_avc_phantom_slice_last(VADriverContextP ctx,
 787                                 VAPictureParameterBufferH264 *pic_param,
 788                                 struct gen6_mfd_context *gen6_mfd_context)
 789 {
 790     gen6_mfd_avc_phantom_slice(ctx, pic_param, NULL, gen6_mfd_context);
 791 }
 792
 793 static void
 794 gen6_mfd_avc_decode_init(VADriverContextP ctx,
 795                          struct decode_state *decode_state,
 796                          struct gen6_mfd_context *gen6_mfd_context)
 797 {
 798     VAPictureParameterBufferH264 *pic_param;
 799     VASliceParameterBufferH264 *slice_param;
 800     struct i965_driver_data *i965 = i965_driver_data(ctx);
 801     struct object_surface *obj_surface;
 802     dri_bo *bo;
 803     int i, j, enable_avc_ildb = 0;
 804     int width_in_mbs;
 805
 806     for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
 807         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 808         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 809
 810         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 811             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 812             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 813                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 814                    (slice_param->slice_type == SLICE_TYPE_P) ||
 815                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 816                    (slice_param->slice_type == SLICE_TYPE_B));
 817
 818             if (slice_param->disable_deblocking_filter_idc != 1) {
 819                 enable_avc_ildb = 1;
 820                 break;
 821             }
 822
 823             slice_param++;
 824         }
 825     }
 826
 827     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 828     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 829     intel_update_avc_frame_store_index(ctx, decode_state, pic_param,
 830         gen6_mfd_context->reference_surface, &gen6_mfd_context->fs_ctx);
 831     width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
 832
 833     /* Current decoded picture */
 834     obj_surface = decode_state->render_object;
 835     if (pic_param->pic_fields.bits.reference_pic_flag)
 836         obj_surface->flags |= SURFACE_REFERENCED;
 837     else
 838         obj_surface->flags &= ~SURFACE_REFERENCED;
 839
 840     avc_ensure_surface_bo(ctx, decode_state, obj_surface, pic_param);
 841     gen6_mfd_init_avc_surface(ctx, pic_param, obj_surface);
 842
 843     dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
 844     gen6_mfd_context->post_deblocking_output.bo = obj_surface->bo;
 845     dri_bo_reference(gen6_mfd_context->post_deblocking_output.bo);
 846     gen6_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
 847
 848     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
 849     gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 850     dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
 851     gen6_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
 852
 853     dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
 854     bo = dri_bo_alloc(i965->intel.bufmgr,
 855                       "intra row store",
 856                       width_in_mbs * 64,
 857                       0x1000);
 858     assert(bo);
 859     gen6_mfd_context->intra_row_store_scratch_buffer.bo = bo;
 860     gen6_mfd_context->intra_row_store_scratch_buffer.valid = 1;
 861
 862     dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
 863     bo = dri_bo_alloc(i965->intel.bufmgr,
 864                       "deblocking filter row store",
 865                       width_in_mbs * 64 * 4,
 866                       0x1000);
 867     assert(bo);
 868     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 869     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
 870
 871     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 872     bo = dri_bo_alloc(i965->intel.bufmgr,
 873                       "bsd mpc row store",
 874                       width_in_mbs * 96,
 875                       0x1000);
 876     assert(bo);
 877     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 878     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
 879
 880     dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo);
 881     bo = dri_bo_alloc(i965->intel.bufmgr,
 882                       "mpr row store",
 883                       width_in_mbs * 64,
 884                       0x1000);
 885     assert(bo);
 886     gen6_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
 887     gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
 888
 889     gen6_mfd_context->bitplane_read_buffer.valid = 0;
 890 }
 891
 892 static void
 893 gen6_mfd_avc_decode_picture(VADriverContextP ctx,
 894                             struct decode_state *decode_state,
 895                             struct gen6_mfd_context *gen6_mfd_context)
 896 {
 897     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 898     VAPictureParameterBufferH264 *pic_param;
 899     VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
 900     dri_bo *slice_data_bo;
 901     int i, j;
 902
 903     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 904     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 905     gen6_mfd_avc_decode_init(ctx, decode_state, gen6_mfd_context);
 906
 907     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
 908     intel_batchbuffer_emit_mi_flush(batch);
 909     gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
 910     gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
 911     gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
 912     gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
 913     gen6_mfd_avc_img_state(ctx, decode_state, gen6_mfd_context);
 914     gen6_mfd_avc_qm_state(ctx, decode_state, gen6_mfd_context);
 915
 916     for (j = 0; j < decode_state->num_slice_params; j++) {
 917         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 918         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 919         slice_data_bo = decode_state->slice_datas[j]->bo;
 920         gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen6_mfd_context);
 921
 922         if (j == decode_state->num_slice_params - 1)
 923             next_slice_group_param = NULL;
 924         else
 925             next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
 926
 927             if (j == 0 &&
 928                 slice_param->first_mb_in_slice)
 929                 gen6_mfd_avc_phantom_slice_first(ctx, pic_param, slice_param, gen6_mfd_context);
 930
 931         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 932             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 933             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 934                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 935                    (slice_param->slice_type == SLICE_TYPE_P) ||
 936                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 937                    (slice_param->slice_type == SLICE_TYPE_B));
 938
 939             if (i < decode_state->slice_params[j]->num_elements - 1)
 940                 next_slice_param = slice_param + 1;
 941             else
 942                 next_slice_param = next_slice_group_param;
 943
 944             gen6_mfd_avc_directmode_state(ctx, decode_state, pic_param, slice_param, gen6_mfd_context);
 945             gen6_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen6_mfd_context);
 946             gen6_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen6_mfd_context);
 947             gen6_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen6_mfd_context);
 948             gen6_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, gen6_mfd_context);
 949             slice_param++;
 950         }
 951     }
 952
 953     gen6_mfd_avc_phantom_slice_last(ctx, pic_param, gen6_mfd_context);
 954     intel_batchbuffer_end_atomic(batch);
 955     intel_batchbuffer_flush(batch);
 956 }
 957
 958 static void
 959 gen6_mfd_mpeg2_decode_init(VADriverContextP ctx,
 960                            struct decode_state *decode_state,
 961                            struct gen6_mfd_context *gen6_mfd_context)
 962 {
 963     VAPictureParameterBufferMPEG2 *pic_param;
 964     struct i965_driver_data *i965 = i965_driver_data(ctx);
 965     struct object_surface *obj_surface;
 966     dri_bo *bo;
 967     unsigned int width_in_mbs;
 968
 969     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 970     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
 971     width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
 972
 973     mpeg2_set_reference_surfaces(
 974         ctx,
 975         gen6_mfd_context->reference_surface,
 976         decode_state,
 977         pic_param
 978     );
 979
 980     /* Current decoded picture */
 981     obj_surface = decode_state->render_object;
 982     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
 983
 984     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
 985     gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 986     dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
 987     gen6_mfd_context->pre_deblocking_output.valid = 1;
 988
 989     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 990     bo = dri_bo_alloc(i965->intel.bufmgr,
 991                       "bsd mpc row store",
 992                       width_in_mbs * 96,
 993                       0x1000);
 994     assert(bo);
 995     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 996     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
 997
 998     gen6_mfd_context->post_deblocking_output.valid = 0;
 999     gen6_mfd_context->intra_row_store_scratch_buffer.valid = 0;
1000     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
1001     gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1002     gen6_mfd_context->bitplane_read_buffer.valid = 0;
1003 }
1004
1005 static void
1006 gen6_mfd_mpeg2_pic_state(VADriverContextP ctx,
1007                          struct decode_state *decode_state,
1008                          struct gen6_mfd_context *gen6_mfd_context)
1009 {
1010     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1011     VAPictureParameterBufferMPEG2 *pic_param;
1012     unsigned int tff, pic_structure;
1013
1014     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1015     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1016
1017     pic_structure = pic_param->picture_coding_extension.bits.picture_structure;
1018     if (pic_structure == MPEG_FRAME)
1019         tff = pic_param->picture_coding_extension.bits.top_field_first;
1020     else
1021         tff = !(pic_param->picture_coding_extension.bits.is_first_field ^
1022                 (pic_structure & MPEG_TOP_FIELD));
1023
1024     BEGIN_BCS_BATCH(batch, 4);
1025     OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (4 - 2));
1026     OUT_BCS_BATCH(batch,
1027                   (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
1028                   ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
1029                   ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
1030                   ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
1031                   pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
1032                   pic_param->picture_coding_extension.bits.picture_structure << 12 |
1033                   tff << 11 |
1034                   pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
1035                   pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
1036                   pic_param->picture_coding_extension.bits.q_scale_type << 8 |
1037                   pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
1038                   pic_param->picture_coding_extension.bits.alternate_scan << 6);
1039     OUT_BCS_BATCH(batch,
1040                   pic_param->picture_coding_type << 9);
1041     OUT_BCS_BATCH(batch,
1042                   (ALIGN(pic_param->vertical_size, 16) / 16) << 16 |
1043                   (ALIGN(pic_param->horizontal_size, 16) / 16));
1044     ADVANCE_BCS_BATCH(batch);
1045 }
1046
1047 static void
1048 gen6_mfd_mpeg2_qm_state(VADriverContextP ctx,
1049                         struct decode_state *decode_state,
1050                         struct gen6_mfd_context *gen6_mfd_context)
1051 {
1052     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1053     VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen6_mfd_context->iq_matrix.mpeg2;
1054     int i, j;
1055
1056     /* Update internal QM state */
1057     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
1058         VAIQMatrixBufferMPEG2 * const iq_matrix =
1059             (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
1060
1061         gen_iq_matrix->load_intra_quantiser_matrix =
1062             iq_matrix->load_intra_quantiser_matrix;
1063         if (iq_matrix->load_intra_quantiser_matrix) {
1064             for (j = 0; j < 64; j++)
1065                 gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
1066                     iq_matrix->intra_quantiser_matrix[j];
1067         }
1068
1069         gen_iq_matrix->load_non_intra_quantiser_matrix =
1070             iq_matrix->load_non_intra_quantiser_matrix;
1071         if (iq_matrix->load_non_intra_quantiser_matrix) {
1072             for (j = 0; j < 64; j++)
1073                 gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1074                     iq_matrix->non_intra_quantiser_matrix[j];
1075         }
1076     }
1077
1078     /* Commit QM state to HW */
1079     for (i = 0; i < 2; i++) {
1080         unsigned char *qm = NULL;
1081
1082         if (i == 0) {
1083             if (gen_iq_matrix->load_intra_quantiser_matrix)
1084                 qm = gen_iq_matrix->intra_quantiser_matrix;
1085         } else {
1086             if (gen_iq_matrix->load_non_intra_quantiser_matrix)
1087                 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1088         }
1089
1090         if (!qm)
1091             continue;
1092
1093         BEGIN_BCS_BATCH(batch, 18);
1094         OUT_BCS_BATCH(batch, MFX_MPEG2_QM_STATE | (18 - 2));
1095         OUT_BCS_BATCH(batch, i);
1096         intel_batchbuffer_data(batch, qm, 64);
1097         ADVANCE_BCS_BATCH(batch);
1098     }
1099 }
1100
1101 static void
1102 gen6_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1103                           VAPictureParameterBufferMPEG2 *pic_param,
1104                           VASliceParameterBufferMPEG2 *slice_param,
1105                           VASliceParameterBufferMPEG2 *next_slice_param,
1106                           struct gen6_mfd_context *gen6_mfd_context)
1107 {
1108     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1109     unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1110     int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1111
1112     if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1113         pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1114         is_field_pic = 1;
1115     is_field_pic_wa = is_field_pic &&
1116         gen6_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1117
1118     vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1119     hpos0 = slice_param->slice_horizontal_position;
1120
1121     if (next_slice_param == NULL) {
1122         vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1123         hpos1 = 0;
1124     } else {
1125         vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1126         hpos1 = next_slice_param->slice_horizontal_position;
1127     }
1128
1129     mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1130
1131     BEGIN_BCS_BATCH(batch, 5);
1132     OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1133     OUT_BCS_BATCH(batch,
1134                   slice_param->slice_data_size - (slice_param->macroblock_offset >> 3));
1135     OUT_BCS_BATCH(batch,
1136                   slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1137     OUT_BCS_BATCH(batch,
1138                   hpos0 << 24 |
1139                   vpos0 << 16 |
1140                   mb_count << 8 |
1141                   (next_slice_param == NULL) << 5 |
1142                   (next_slice_param == NULL) << 3 |
1143                   (slice_param->macroblock_offset & 0x7));
1144     OUT_BCS_BATCH(batch,
1145                   slice_param->quantiser_scale_code << 24);
1146     ADVANCE_BCS_BATCH(batch);
1147 }
1148
1149 static void
1150 gen6_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1151                               struct decode_state *decode_state,
1152                               struct gen6_mfd_context *gen6_mfd_context)
1153 {
1154     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1155     VAPictureParameterBufferMPEG2 *pic_param;
1156     VASliceParameterBufferMPEG2 *slice_param, *next_slice_param;
1157     dri_bo *slice_data_bo;
1158     int group_idx = 0, pre_group_idx = -1, element_idx = 0;
1159
1160     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1161     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1162
1163     gen6_mfd_mpeg2_decode_init(ctx, decode_state, gen6_mfd_context);
1164     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1165     intel_batchbuffer_emit_mi_flush(batch);
1166     gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1167     gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1168     gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1169     gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1170     gen6_mfd_mpeg2_pic_state(ctx, decode_state, gen6_mfd_context);
1171     gen6_mfd_mpeg2_qm_state(ctx, decode_state, gen6_mfd_context);
1172
1173     if (gen6_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1174         gen6_mfd_context->wa_mpeg2_slice_vertical_position =
1175             mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1176
1177     slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[group_idx]->buffer;
1178
1179     for (; slice_param;) {
1180         if (pre_group_idx != group_idx) {
1181             slice_data_bo = decode_state->slice_datas[group_idx]->bo;
1182             gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen6_mfd_context);
1183             pre_group_idx = group_idx;
1184         }
1185
1186         next_slice_param = intel_mpeg2_find_next_slice(decode_state, pic_param, slice_param, &group_idx, &element_idx);
1187         gen6_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, next_slice_param, gen6_mfd_context);
1188         slice_param = next_slice_param;
1189     }
1190
1191     intel_batchbuffer_end_atomic(batch);
1192     intel_batchbuffer_flush(batch);
1193 }
1194
1195 static const int va_to_gen6_vc1_pic_type[5] = {
1196     GEN6_VC1_I_PICTURE,
1197     GEN6_VC1_P_PICTURE,
1198     GEN6_VC1_B_PICTURE,
1199     GEN6_VC1_BI_PICTURE,
1200     GEN6_VC1_P_PICTURE,
1201 };
1202
1203 static const int va_to_gen6_vc1_mv[4] = {
1204     1, /* 1-MV */
1205     2, /* 1-MV half-pel */
1206     3, /* 1-MV half-pef bilinear */
1207     0, /* Mixed MV */
1208 };
1209
1210 static const int b_picture_scale_factor[21] = {
1211     128, 85,  170, 64,  192,
1212     51,  102, 153, 204, 43,
1213     215, 37,  74,  111, 148,
1214     185, 222, 32,  96,  160,
1215     224,
1216 };
1217
1218 static const int va_to_gen6_vc1_condover[3] = {
1219     0,
1220     2,
1221     3
1222 };
1223
1224 static const int va_to_gen6_vc1_profile[4] = {
1225     GEN6_VC1_SIMPLE_PROFILE,
1226     GEN6_VC1_MAIN_PROFILE,
1227     GEN6_VC1_RESERVED_PROFILE,
1228     GEN6_VC1_ADVANCED_PROFILE
1229 };
1230
1231 static void
1232 gen6_mfd_free_vc1_surface(void **data)
1233 {
1234     struct gen6_vc1_surface *gen6_vc1_surface = *data;
1235
1236     if (!gen6_vc1_surface)
1237         return;
1238
1239     dri_bo_unreference(gen6_vc1_surface->dmv);
1240     free(gen6_vc1_surface);
1241     *data = NULL;
1242 }
1243
1244 static void
1245 gen6_mfd_init_vc1_surface(VADriverContextP ctx,
1246                           VAPictureParameterBufferVC1 *pic_param,
1247                           struct object_surface *obj_surface)
1248 {
1249     struct i965_driver_data *i965 = i965_driver_data(ctx);
1250     struct gen6_vc1_surface *gen6_vc1_surface = obj_surface->private_data;
1251     int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1252
1253     obj_surface->free_private_data = gen6_mfd_free_vc1_surface;
1254
1255     if (!gen6_vc1_surface) {
1256         gen6_vc1_surface = calloc(sizeof(struct gen6_vc1_surface), 1);
1257         assert((obj_surface->size & 0x3f) == 0);
1258         obj_surface->private_data = gen6_vc1_surface;
1259     }
1260
1261     gen6_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
1262
1263     if (gen6_vc1_surface->dmv == NULL) {
1264         gen6_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
1265                                              "direct mv w/r buffer",
1266                                              128 * height_in_mbs * 64,  /* scalable with frame height */
1267                                              0x1000);
1268     }
1269 }
1270
1271 static void
1272 gen6_mfd_vc1_decode_init(VADriverContextP ctx,
1273                          struct decode_state *decode_state,
1274                          struct gen6_mfd_context *gen6_mfd_context)
1275 {
1276     VAPictureParameterBufferVC1 *pic_param;
1277     struct i965_driver_data *i965 = i965_driver_data(ctx);
1278     struct object_surface *obj_surface;
1279     dri_bo *bo;
1280     int width_in_mbs;
1281     int picture_type;
1282
1283     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1284     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1285     width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1286     picture_type = pic_param->picture_fields.bits.picture_type;
1287
1288     intel_update_vc1_frame_store_index(ctx,
1289                                        decode_state,
1290                                        pic_param,
1291                                        gen6_mfd_context->reference_surface);
1292
1293     /* Current decoded picture */
1294     obj_surface = decode_state->render_object;
1295     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
1296     gen6_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1297
1298     dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
1299     gen6_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1300     dri_bo_reference(gen6_mfd_context->post_deblocking_output.bo);
1301     gen6_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1302
1303     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
1304     gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1305     dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
1306     gen6_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1307
1308     dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
1309     bo = dri_bo_alloc(i965->intel.bufmgr,
1310                       "intra row store",
1311                       width_in_mbs * 64,
1312                       0x1000);
1313     assert(bo);
1314     gen6_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1315     gen6_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1316
1317     dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1318     bo = dri_bo_alloc(i965->intel.bufmgr,
1319                       "deblocking filter row store",
1320                       width_in_mbs * 7 * 64,
1321                       0x1000);
1322     assert(bo);
1323     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1324     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1325
1326     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1327     bo = dri_bo_alloc(i965->intel.bufmgr,
1328                       "bsd mpc row store",
1329                       width_in_mbs * 96,
1330                       0x1000);
1331     assert(bo);
1332     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1333     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1334
1335     gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1336
1337     gen6_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value;
1338     dri_bo_unreference(gen6_mfd_context->bitplane_read_buffer.bo);
1339
1340     if (gen6_mfd_context->bitplane_read_buffer.valid) {
1341         int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1342         int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1343         int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1344         int src_w, src_h;
1345         uint8_t *src = NULL, *dst = NULL;
1346
1347         assert(decode_state->bit_plane->buffer);
1348         src = decode_state->bit_plane->buffer;
1349
1350         bo = dri_bo_alloc(i965->intel.bufmgr,
1351                           "VC-1 Bitplane",
1352                           bitplane_width * height_in_mbs,
1353                           0x1000);
1354         assert(bo);
1355         gen6_mfd_context->bitplane_read_buffer.bo = bo;
1356
1357         dri_bo_map(bo, True);
1358         assert(bo->virtual);
1359         dst = bo->virtual;
1360
1361         for (src_h = 0; src_h < height_in_mbs; src_h++) {
1362             for(src_w = 0; src_w < width_in_mbs; src_w++) {
1363                 int src_index, dst_index;
1364                 int src_shift;
1365                 uint8_t src_value;
1366
1367                 src_index = (src_h * width_in_mbs + src_w) / 2;
1368                 src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1369                 src_value = ((src[src_index] >> src_shift) & 0xf);
1370
1371                 if (picture_type == GEN6_VC1_SKIPPED_PICTURE){
1372                     src_value |= 0x2;
1373                 }
1374
1375                 dst_index = src_w / 2;
1376                 dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1377             }
1378
1379             if (src_w & 1)
1380                 dst[src_w / 2] >>= 4;
1381
1382             dst += bitplane_width;
1383         }
1384
1385         dri_bo_unmap(bo);
1386     } else
1387         gen6_mfd_context->bitplane_read_buffer.bo = NULL;
1388 }
1389
1390 static void
1391 gen6_mfd_vc1_pic_state(VADriverContextP ctx,
1392                        struct decode_state *decode_state,
1393                        struct gen6_mfd_context *gen6_mfd_context)
1394 {
1395     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1396     VAPictureParameterBufferVC1 *pic_param;
1397     struct object_surface *obj_surface;
1398     int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1399     int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1400     int unified_mv_mode;
1401     int ref_field_pic_polarity = 0;
1402     int scale_factor = 0;
1403     int trans_ac_y = 0;
1404     int dmv_surface_valid = 0;
1405     int brfd = 0;
1406     int fcm = 0;
1407     int picture_type;
1408     int profile;
1409     int overlap;
1410
1411     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1412     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1413
1414     profile = va_to_gen6_vc1_profile[pic_param->sequence_fields.bits.profile];
1415     dquant = pic_param->pic_quantizer_fields.bits.dquant;
1416     dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1417     dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1418     dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1419     dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1420     dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1421     alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1422
1423     if (dquant == 0) {
1424         alt_pquant_config = 0;
1425         alt_pquant_edge_mask = 0;
1426     } else if (dquant == 2) {
1427         alt_pquant_config = 1;
1428         alt_pquant_edge_mask = 0xf;
1429     } else {
1430         assert(dquant == 1);
1431         if (dquantfrm == 0) {
1432             alt_pquant_config = 0;
1433             alt_pquant_edge_mask = 0;
1434             alt_pq = 0;
1435         } else {
1436             assert(dquantfrm == 1);
1437             alt_pquant_config = 1;
1438
1439             switch (dqprofile) {
1440             case 3:
1441                 if (dqbilevel == 0) {
1442                     alt_pquant_config = 2;
1443                     alt_pquant_edge_mask = 0;
1444                 } else {
1445                     assert(dqbilevel == 1);
1446                     alt_pquant_config = 3;
1447                     alt_pquant_edge_mask = 0;
1448                 }
1449                 break;
1450
1451             case 0:
1452                 alt_pquant_edge_mask = 0xf;
1453                 break;
1454
1455             case 1:
1456                 if (dqdbedge == 3)
1457                     alt_pquant_edge_mask = 0x9;
1458                 else
1459                     alt_pquant_edge_mask = (0x3 << dqdbedge);
1460
1461                 break;
1462
1463             case 2:
1464                 alt_pquant_edge_mask = (0x1 << dqsbedge);
1465                 break;
1466
1467             default:
1468                 assert(0);
1469             }
1470         }
1471     }
1472
1473     if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1474         assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1475         unified_mv_mode = va_to_gen6_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1476     } else {
1477         assert(pic_param->mv_fields.bits.mv_mode < 4);
1478         unified_mv_mode = va_to_gen6_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1479     }
1480
1481     if (pic_param->sequence_fields.bits.interlace == 1 &&
1482         pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
1483         /* FIXME: calculate reference field picture polarity */
1484         assert(0);
1485         ref_field_pic_polarity = 0;
1486     }
1487
1488     if (pic_param->b_picture_fraction < 21)
1489         scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1490
1491     picture_type = va_to_gen6_vc1_pic_type[pic_param->picture_fields.bits.picture_type];
1492
1493     if (profile == GEN6_VC1_ADVANCED_PROFILE &&
1494         picture_type == GEN6_VC1_I_PICTURE)
1495         picture_type = GEN6_VC1_BI_PICTURE;
1496
1497     if (picture_type == GEN6_VC1_I_PICTURE || picture_type == GEN6_VC1_BI_PICTURE) /* I picture */
1498         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1499     else {
1500         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1501         /*
1502          * 8.3.6.2.1 Transform Type Selection
1503          * If variable-sized transform coding is not enabled,
1504          * then the 8x8 transform shall be used for all blocks.
1505          * it is also MFX_VC1_PIC_STATE requirement.
1506          */
1507         if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) {
1508             pic_param->transform_fields.bits.mb_level_transform_type_flag   = 1;
1509             pic_param->transform_fields.bits.frame_level_transform_type     = 0;
1510         }
1511     }
1512
1513     if (picture_type == GEN6_VC1_B_PICTURE) {
1514         struct gen6_vc1_surface *gen6_vc1_surface = NULL;
1515
1516         obj_surface = decode_state->reference_objects[1];
1517
1518         if (obj_surface)
1519             gen6_vc1_surface = obj_surface->private_data;
1520
1521         if (!gen6_vc1_surface ||
1522             (va_to_gen6_vc1_pic_type[gen6_vc1_surface->picture_type] == GEN6_VC1_I_PICTURE ||
1523              va_to_gen6_vc1_pic_type[gen6_vc1_surface->picture_type] == GEN6_VC1_BI_PICTURE))
1524             dmv_surface_valid = 0;
1525         else
1526             dmv_surface_valid = 1;
1527     }
1528
1529     assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1530
1531     if (pic_param->picture_fields.bits.frame_coding_mode < 2)
1532         fcm = pic_param->picture_fields.bits.frame_coding_mode;
1533     else {
1534         if (pic_param->picture_fields.bits.top_field_first)
1535             fcm = 2;
1536         else
1537             fcm = 3;
1538     }
1539
1540     if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_B_PICTURE) { /* B picture */
1541         brfd = pic_param->reference_fields.bits.reference_distance;
1542         brfd = (scale_factor * brfd) >> 8;
1543         brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
1544
1545         if (brfd < 0)
1546             brfd = 0;
1547     }
1548
1549     overlap = 0;
1550     if (profile != GEN6_VC1_ADVANCED_PROFILE){
1551         if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 &&
1552             pic_param->picture_fields.bits.picture_type != GEN6_VC1_B_PICTURE) {
1553             overlap = 1;
1554         }
1555     }else {
1556         if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_P_PICTURE &&
1557              pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
1558               overlap = 1;
1559         }
1560         if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_I_PICTURE ||
1561             pic_param->picture_fields.bits.picture_type == GEN6_VC1_BI_PICTURE){
1562              if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
1563                 overlap = 1;
1564              } else if (va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] == 2 ||
1565                         va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] == 3) {
1566                  overlap = 1;
1567              }
1568         }
1569     }
1570
1571     assert(pic_param->conditional_overlap_flag < 3);
1572     assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
1573
1574     BEGIN_BCS_BATCH(batch, 6);
1575     OUT_BCS_BATCH(batch, MFX_VC1_PIC_STATE | (6 - 2));
1576     OUT_BCS_BATCH(batch,
1577                   (ALIGN(pic_param->coded_height, 16) / 16) << 16 |
1578                   (ALIGN(pic_param->coded_width, 16) / 16));
1579     OUT_BCS_BATCH(batch,
1580                   pic_param->sequence_fields.bits.syncmarker << 31 |
1581                   1 << 29 | /* concealment */
1582                   alt_pq << 24 |
1583                   pic_param->entrypoint_fields.bits.loopfilter << 23 |
1584                   overlap << 22 |
1585                   (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 21 | /* implicit quantizer */
1586                   pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 16 |
1587                   alt_pquant_edge_mask << 12 |
1588                   alt_pquant_config << 10 |
1589                   pic_param->pic_quantizer_fields.bits.half_qp << 9 |
1590                   pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 8 |
1591                   va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] << 6 |
1592                   !pic_param->picture_fields.bits.is_first_field << 5 |
1593                   picture_type << 2 |
1594                   fcm << 0);
1595     OUT_BCS_BATCH(batch,
1596                   !!pic_param->bitplane_present.value << 23 |
1597                   !pic_param->bitplane_present.flags.bp_forward_mb << 22 |
1598                   !pic_param->bitplane_present.flags.bp_mv_type_mb << 21 |
1599                   !pic_param->bitplane_present.flags.bp_skip_mb << 20 |
1600                   !pic_param->bitplane_present.flags.bp_direct_mb << 19 |
1601                   !pic_param->bitplane_present.flags.bp_overflags << 18 |
1602                   !pic_param->bitplane_present.flags.bp_ac_pred << 17 |
1603                   !pic_param->bitplane_present.flags.bp_field_tx << 16 |
1604                   pic_param->mv_fields.bits.extended_dmv_range << 14 |
1605                   pic_param->mv_fields.bits.extended_mv_range << 12 |
1606                   pic_param->mv_fields.bits.four_mv_switch << 11 |
1607                   pic_param->fast_uvmc_flag << 10 |
1608                   unified_mv_mode << 8 |
1609                   ref_field_pic_polarity << 6 |
1610                   pic_param->reference_fields.bits.num_reference_pictures << 5 |
1611                   pic_param->reference_fields.bits.reference_distance << 0);
1612     OUT_BCS_BATCH(batch,
1613                   scale_factor << 24 |
1614                   pic_param->mv_fields.bits.mv_table << 20 |
1615                   pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
1616                   pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
1617                   pic_param->transform_fields.bits.frame_level_transform_type << 12 |
1618                   pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
1619                   pic_param->mb_mode_table << 8 |
1620                   trans_ac_y << 6 |
1621                   pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
1622                   pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
1623                   pic_param->cbp_table << 0);
1624     OUT_BCS_BATCH(batch,
1625                   dmv_surface_valid << 13 |
1626                   brfd << 8 |
1627                   ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1));
1628     ADVANCE_BCS_BATCH(batch);
1629 }
1630
1631 static void
1632 gen6_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
1633                              struct decode_state *decode_state,
1634                              struct gen6_mfd_context *gen6_mfd_context)
1635 {
1636     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1637     VAPictureParameterBufferVC1 *pic_param;
1638     int interpolation_mode = 0;
1639     int intensitycomp_single;
1640
1641     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1642     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1643
1644     if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
1645         (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1646          pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
1647         interpolation_mode = 2; /* Half-pel bilinear */
1648     else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
1649              (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1650               pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
1651         interpolation_mode = 0; /* Half-pel bicubic */
1652     else
1653         interpolation_mode = 1; /* Quarter-pel bicubic */
1654
1655     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1656     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1657     intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
1658
1659     BEGIN_BCS_BATCH(batch, 7);
1660     OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (7 - 2));
1661     OUT_BCS_BATCH(batch,
1662                   0 << 8 | /* FIXME: interlace mode */
1663                   pic_param->rounding_control << 4 |
1664                   va_to_gen6_vc1_profile[pic_param->sequence_fields.bits.profile] << 2);
1665     OUT_BCS_BATCH(batch,
1666                   pic_param->luma_shift << 16 |
1667                   pic_param->luma_scale << 0); /* FIXME: Luma Scaling */
1668     OUT_BCS_BATCH(batch, 0);
1669     OUT_BCS_BATCH(batch, 0);
1670     OUT_BCS_BATCH(batch, 0);
1671     OUT_BCS_BATCH(batch,
1672                   interpolation_mode << 19 |
1673                   pic_param->fast_uvmc_flag << 18 |
1674                   0 << 17 | /* FIXME: scale up or down ??? */
1675                   pic_param->range_reduction_frame << 16 |
1676                   0 << 6 | /* FIXME: double ??? */
1677                   0 << 4 |
1678                   intensitycomp_single << 2 |
1679                   intensitycomp_single << 0);
1680     ADVANCE_BCS_BATCH(batch);
1681 }
1682
1683
1684 static void
1685 gen6_mfd_vc1_directmode_state(VADriverContextP ctx,
1686                               struct decode_state *decode_state,
1687                               struct gen6_mfd_context *gen6_mfd_context)
1688 {
1689     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1690     struct object_surface *obj_surface;
1691     dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
1692
1693     obj_surface = decode_state->render_object;
1694
1695     if (obj_surface && obj_surface->private_data) {
1696         dmv_write_buffer = ((struct gen6_vc1_surface *)(obj_surface->private_data))->dmv;
1697     }
1698
1699     obj_surface = decode_state->reference_objects[1];
1700
1701     if (obj_surface && obj_surface->private_data) {
1702         dmv_read_buffer = ((struct gen6_vc1_surface *)(obj_surface->private_data))->dmv;
1703     }
1704
1705     BEGIN_BCS_BATCH(batch, 3);
1706     OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
1707
1708     if (dmv_write_buffer)
1709         OUT_BCS_RELOC(batch, dmv_write_buffer,
1710                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
1711                       0);
1712     else
1713         OUT_BCS_BATCH(batch, 0);
1714
1715     if (dmv_read_buffer)
1716         OUT_BCS_RELOC(batch, dmv_read_buffer,
1717                       I915_GEM_DOMAIN_INSTRUCTION, 0,
1718                       0);
1719     else
1720         OUT_BCS_BATCH(batch, 0);
1721
1722     ADVANCE_BCS_BATCH(batch);
1723 }
1724
1725 static int
1726 gen6_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
1727 {
1728     int out_slice_data_bit_offset;
1729     int slice_header_size = in_slice_data_bit_offset / 8;
1730     int i, j;
1731
1732     if (profile != 3)
1733         out_slice_data_bit_offset = in_slice_data_bit_offset;
1734     else {
1735         for (i = 0, j = 0; i < slice_header_size; i++, j++) {
1736             if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
1737                 i++, j += 2;
1738             }
1739         }
1740
1741         out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
1742     }
1743
1744     return out_slice_data_bit_offset;
1745 }
1746
1747 static void
1748 gen6_mfd_vc1_bsd_object(VADriverContextP ctx,
1749                         VAPictureParameterBufferVC1 *pic_param,
1750                         VASliceParameterBufferVC1 *slice_param,
1751                         VASliceParameterBufferVC1 *next_slice_param,
1752                         dri_bo *slice_data_bo,
1753                         struct gen6_mfd_context *gen6_mfd_context)
1754 {
1755     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1756     int next_slice_start_vert_pos;
1757     int macroblock_offset;
1758     uint8_t *slice_data = NULL;
1759
1760     dri_bo_map(slice_data_bo, 0);
1761     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
1762     macroblock_offset = gen6_mfd_vc1_get_macroblock_bit_offset(slice_data,
1763                                                                slice_param->macroblock_offset,
1764                                                                pic_param->sequence_fields.bits.profile);
1765     dri_bo_unmap(slice_data_bo);
1766
1767     if (next_slice_param)
1768         next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
1769     else
1770         next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
1771
1772     BEGIN_BCS_BATCH(batch, 4);
1773     OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (4 - 2));
1774     OUT_BCS_BATCH(batch,
1775                   slice_param->slice_data_size - (macroblock_offset >> 3));
1776     OUT_BCS_BATCH(batch,
1777                   slice_param->slice_data_offset + (macroblock_offset >> 3));
1778     OUT_BCS_BATCH(batch,
1779                   slice_param->slice_vertical_position << 24 |
1780                   next_slice_start_vert_pos << 16 |
1781                   (macroblock_offset & 0x7));
1782     ADVANCE_BCS_BATCH(batch);
1783 }
1784
1785 static void
1786 gen6_mfd_vc1_decode_picture(VADriverContextP ctx,
1787                             struct decode_state *decode_state,
1788                             struct gen6_mfd_context *gen6_mfd_context)
1789 {
1790     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1791     VAPictureParameterBufferVC1 *pic_param;
1792     VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
1793     dri_bo *slice_data_bo;
1794     int i, j;
1795
1796     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1797     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1798
1799     gen6_mfd_vc1_decode_init(ctx, decode_state, gen6_mfd_context);
1800     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1801     intel_batchbuffer_emit_mi_flush(batch);
1802     gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1803     gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1804     gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1805     gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1806     gen6_mfd_vc1_pic_state(ctx, decode_state, gen6_mfd_context);
1807     gen6_mfd_vc1_pred_pipe_state(ctx, decode_state, gen6_mfd_context);
1808     gen6_mfd_vc1_directmode_state(ctx, decode_state, gen6_mfd_context);
1809
1810     for (j = 0; j < decode_state->num_slice_params; j++) {
1811         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1812         slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
1813         slice_data_bo = decode_state->slice_datas[j]->bo;
1814         gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen6_mfd_context);
1815
1816         if (j == decode_state->num_slice_params - 1)
1817             next_slice_group_param = NULL;
1818         else
1819             next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
1820
1821         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1822             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1823
1824             if (i < decode_state->slice_params[j]->num_elements - 1)
1825                 next_slice_param = slice_param + 1;
1826             else
1827                 next_slice_param = next_slice_group_param;
1828
1829             gen6_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen6_mfd_context);
1830             slice_param++;
1831         }
1832     }
1833
1834     intel_batchbuffer_end_atomic(batch);
1835     intel_batchbuffer_flush(batch);
1836 }
1837
1838 static VAStatus
1839 gen6_mfd_decode_picture(VADriverContextP ctx,
1840                         VAProfile profile,
1841                         union codec_state *codec_state,
1842                         struct hw_context *hw_context)
1843
1844 {
1845     struct gen6_mfd_context *gen6_mfd_context = (struct gen6_mfd_context *)hw_context;
1846     struct decode_state *decode_state = &codec_state->decode;
1847     VAStatus vaStatus;
1848
1849     assert(gen6_mfd_context);
1850
1851     vaStatus = intel_decoder_sanity_check_input(ctx, profile, decode_state);
1852
1853     if (vaStatus != VA_STATUS_SUCCESS)
1854         goto out;
1855
1856     switch (profile) {
1857     case VAProfileMPEG2Simple:
1858     case VAProfileMPEG2Main:
1859         gen6_mfd_mpeg2_decode_picture(ctx, decode_state, gen6_mfd_context);
1860         break;
1861
1862     case VAProfileH264ConstrainedBaseline:
1863     case VAProfileH264Main:
1864     case VAProfileH264High:
1865     case VAProfileH264StereoHigh:
1866         gen6_mfd_avc_decode_picture(ctx, decode_state, gen6_mfd_context);
1867         break;
1868
1869     case VAProfileVC1Simple:
1870     case VAProfileVC1Main:
1871     case VAProfileVC1Advanced:
1872         gen6_mfd_vc1_decode_picture(ctx, decode_state, gen6_mfd_context);
1873         break;
1874
1875     default:
1876         assert(0);
1877         break;
1878     }
1879
1880     vaStatus = VA_STATUS_SUCCESS;
1881
1882 out:
1883     return vaStatus;
1884 }
1885
1886 static void
1887 gen6_mfd_context_destroy(void *hw_context)
1888 {
1889     struct gen6_mfd_context *gen6_mfd_context = (struct gen6_mfd_context *)hw_context;
1890
1891     dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
1892     gen6_mfd_context->post_deblocking_output.bo = NULL;
1893
1894     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
1895     gen6_mfd_context->pre_deblocking_output.bo = NULL;
1896
1897     dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
1898     gen6_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
1899
1900     dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1901     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1902
1903     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1904     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1905
1906     dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo);
1907     gen6_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
1908
1909     dri_bo_unreference(gen6_mfd_context->bitplane_read_buffer.bo);
1910     gen6_mfd_context->bitplane_read_buffer.bo = NULL;
1911
1912     intel_batchbuffer_free(gen6_mfd_context->base.batch);
1913     free(gen6_mfd_context);
1914 }
1915
1916 struct hw_context *
1917 gen6_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
1918 {
1919     struct intel_driver_data *intel = intel_driver_data(ctx);
1920     struct gen6_mfd_context *gen6_mfd_context = calloc(1, sizeof(struct gen6_mfd_context));
1921     int i;
1922
1923     gen6_mfd_context->base.destroy = gen6_mfd_context_destroy;
1924     gen6_mfd_context->base.run = gen6_mfd_decode_picture;
1925     gen6_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
1926
1927     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
1928         gen6_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
1929         gen6_mfd_context->reference_surface[i].frame_store_id = -1;
1930         gen6_mfd_context->reference_surface[i].obj_surface = NULL;
1931     }
1932
1933     gen6_mfd_context->wa_mpeg2_slice_vertical_position = -1;
1934
1935     return (struct hw_context *)gen6_mfd_context;
1936 }