radeon: add comment to clarify bus mastering on PCIE chips

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index f897820..86fb6db 100644 (file)
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -432,20 +432,30 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #      define RADEON_SCISSOR_1_ENABLE          (1 << 29)
 #      define RADEON_SCISSOR_2_ENABLE          (1 << 30)
 
+/*
+ * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx)
+ * don't have an explicit bus mastering disable bit.  It's handled
+ * by the PCI D-states.  PMI_BM_DIS disables D-state bus master
+ * handling, not bus mastering itself.
+ */
 #define RADEON_BUS_CNTL                        0x0030
-/* r1xx, r2xx, r300, r(v)350, r420, rs480 */
+/* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */
 #      define RADEON_BUS_MASTER_DIS            (1 << 6)
-/* rs400, rs690, rs740 */
+/* rs400, rs690/rs740 */
 #      define RS400_BUS_MASTER_DIS             (1 << 14)
 #      define RS400_MSI_REARM                  (1 << 20)
+/* see RS480_MSI_REARM in AIC_CNTL for rs480 */
+
+#define RADEON_BUS_CNTL1               0x0034
+#      define RADEON_PMI_BM_DIS                (1 << 2)
+#      define RADEON_PMI_INT_DIS               (1 << 3)
 
 #define RV370_BUS_CNTL                 0x004c
-/* rv370, rv380, rv410, r423, r430, r480, r5xx */
 #      define RV370_PMI_BM_DIS                 (1 << 5)
 #      define RV370_PMI_INT_DIS                (1 << 6)
 
 #define RADEON_MSI_REARM_EN            0x0160
-/* rv370, rv380, rv410, r423, r430, r480, r5xx */
+/* rv370/rv380, rv410, r423/r430/r480, r5xx */
 #      define RV370_MSI_REARM_EN               (1 << 0)
 
 #define RADEON_CLOCK_CNTL_DATA         0x000c