intel: Add support for GPU reset status query ioctl
authorIan Romanick <ian.d.romanick@intel.com>
Mon, 10 Sep 2012 11:15:02 +0000 (14:15 +0300)
committerIan Romanick <ian.d.romanick@intel.com>
Fri, 8 Nov 2013 03:14:31 +0000 (19:14 -0800)
I would have just used the drmIoctl interface directly in Mesa, but the
ioctl needs some data from the drm_intel_context that is not exposed
outside libdrm.

v2: Update based on Mika's kernel work.

v3: Fix compile failures from last-minute typos.  Sigh.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
include/drm/i915_drm.h
intel/intel_bufmgr.h
intel/intel_bufmgr_gem.c

index aa983f3..2703ded 100644 (file)
@@ -198,6 +198,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_GEM_SET_CACHEING      0x2f
 #define DRM_I915_GEM_GET_CACHEING      0x30
 #define DRM_I915_REG_READ              0x31
+#define DRM_I915_GET_RESET_STATS       0x32
 
 #define DRM_IOCTL_I915_INIT            DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH           DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -247,6 +248,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE      DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY     DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
 #define DRM_IOCTL_I915_REG_READ                        DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
+#define DRM_IOCTL_I915_GET_RESET_STATS         DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
@@ -943,4 +945,19 @@ struct drm_i915_reg_read {
        __u64 offset;
        __u64 val; /* Return value */
 };
+
+struct drm_i915_reset_stats {
+       __u32 ctx_id;
+       __u32 flags;
+
+       /* For all contexts */
+       __u32 reset_count;
+
+       /* For this context */
+       __u32 batch_active;
+       __u32 batch_pending;
+
+       __u32 pad;
+};
+
 #endif                         /* _I915_DRM_H_ */
index 15f818e..2eb9742 100644 (file)
@@ -248,6 +248,11 @@ int drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
                       uint32_t offset,
                       uint64_t *result);
 
+int drm_intel_get_reset_stats(drm_intel_context *ctx,
+                             uint32_t *reset_count,
+                             uint32_t *active,
+                             uint32_t *pending);
+
 /** @{ Compatibility defines to keep old code building despite the symbol rename
  * from dri_* to drm_intel_*
  */
index 029ca5d..df6fcec 100644 (file)
@@ -3021,6 +3021,40 @@ drm_intel_gem_context_destroy(drm_intel_context *ctx)
 }
 
 int
+drm_intel_get_reset_stats(drm_intel_context *ctx,
+                         uint32_t *reset_count,
+                         uint32_t *active,
+                         uint32_t *pending)
+{
+       drm_intel_bufmgr_gem *bufmgr_gem;
+       struct drm_i915_reset_stats stats;
+       int ret;
+
+       if (ctx == NULL)
+               return -EINVAL;
+
+       VG_CLEAR(stats);
+
+       bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
+       stats.ctx_id = ctx->ctx_id;
+       ret = drmIoctl(bufmgr_gem->fd,
+                      DRM_IOCTL_I915_GET_RESET_STATS,
+                      &stats);
+       if (ret == 0) {
+               if (reset_count != NULL)
+                       *reset_count = stats.reset_count;
+
+               if (active != NULL)
+                       *active = stats.batch_active;
+
+               if (pending != NULL)
+                       *pending = stats.batch_pending;
+       }
+
+       return ret;
+}
+
+int
 drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
                   uint32_t offset,
                   uint64_t *result)