3 * Header for the Direct Rendering Manager
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
39 * The Direct Rendering Manager (DRM) is a device-independent kernel-level
40 * device driver that provides support for the XFree86 Direct Rendering
41 * Infrastructure (DRI).
43 * The DRM supports the Direct Rendering Infrastructure (DRI) in four major
45 * -# The DRM provides synchronized access to the graphics hardware via
46 * the use of an optimized two-tiered lock.
47 * -# The DRM enforces the DRI security policy for access to the graphics
48 * hardware by only allowing authenticated X11 clients access to
49 * restricted regions of memory.
50 * -# The DRM provides a generic DMA engine, complete with multiple
51 * queues and the ability to detect the need for an OpenGL context
53 * -# The DRM is extensible via the use of small device-specific modules
54 * that rely extensively on the API exported by the DRM module.
69 # define DEPRECATED __attribute__ ((deprecated))
74 #if defined(__linux__)
75 #include <asm/ioctl.h> /* For _IO* macros */
76 #define DRM_IOCTL_NR(n) _IOC_NR(n)
77 #define DRM_IOC_VOID _IOC_NONE
78 #define DRM_IOC_READ _IOC_READ
79 #define DRM_IOC_WRITE _IOC_WRITE
80 #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
81 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
82 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__)
83 #include <sys/ioccom.h>
84 #define DRM_IOCTL_NR(n) ((n) & 0xff)
85 #define DRM_IOC_VOID IOC_VOID
86 #define DRM_IOC_READ IOC_OUT
87 #define DRM_IOC_WRITE IOC_IN
88 #define DRM_IOC_READWRITE IOC_INOUT
89 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
92 #define XFREE86_VERSION(major,minor,patch,snap) \
93 ((major << 16) | (minor << 8) | patch)
95 #ifndef CONFIG_XFREE86_VERSION
96 #define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
99 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
100 #define DRM_PROC_DEVICES "/proc/devices"
101 #define DRM_PROC_MISC "/proc/misc"
102 #define DRM_PROC_DRM "/proc/drm"
103 #define DRM_DEV_DRM "/dev/drm"
104 #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
105 #define DRM_DEV_UID 0
106 #define DRM_DEV_GID 0
109 #if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
113 #if defined(__linux__) || defined(__NetBSD__)
114 #define DRM_MAJOR 226
116 #define DRM_MAX_MINOR 15
118 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
119 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
120 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
121 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
123 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
124 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
125 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
126 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
127 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
129 #if defined(__linux__)
130 #if defined(__KERNEL__)
131 typedef __u64 drm_u64_t;
133 typedef unsigned long long drm_u64_t;
136 typedef unsigned int drm_handle_t;
138 #include <sys/types.h>
139 typedef u_int64_t drm_u64_t;
140 typedef unsigned long drm_handle_t; /**< To mapped regions */
142 typedef unsigned int drm_context_t; /**< GLXContext handle */
143 typedef unsigned int drm_drawable_t;
144 typedef unsigned int drm_magic_t; /**< Magic for authentication */
149 * \warning If you change this structure, make sure you change
150 * XF86DRIClipRectRec in the server as well
152 * \note KW: Actually it's illegal to change either for
153 * backwards-compatibility reasons.
155 typedef struct drm_clip_rect {
163 * Drawable information.
165 typedef struct drm_drawable_info {
166 unsigned int num_rects;
167 drm_clip_rect_t *rects;
168 } drm_drawable_info_t;
173 typedef struct drm_tex_region {
176 unsigned char in_use;
177 unsigned char padding;
184 * The lock structure is a simple cache-line aligned integer. To avoid
185 * processor bus contention on a multiprocessor system, there should not be any
186 * other data stored in the same cache line.
188 typedef struct drm_hw_lock {
189 __volatile__ unsigned int lock; /**< lock variable */
190 char padding[60]; /**< Pad to cache line */
193 /* This is beyond ugly, and only works on GCC. However, it allows me to use
194 * drm.h in places (i.e., in the X-server) where I can't use size_t. The real
195 * fix is to use uint32_t instead of size_t, but that fix will break existing
196 * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That *will*
197 * eventually happen, though. I chose 'unsigned long' to be the fallback type
198 * because that works on all the platforms I know about. Hopefully, the
199 * real fix will happen before that bites us.
203 # define DRM_SIZE_T __SIZE_TYPE__
205 # warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!"
206 # define DRM_SIZE_T unsigned long
210 * DRM_IOCTL_VERSION ioctl argument type.
212 * \sa drmGetVersion().
214 typedef struct drm_version {
215 int version_major; /**< Major version */
216 int version_minor; /**< Minor version */
217 int version_patchlevel; /**< Patch level */
218 DRM_SIZE_T name_len; /**< Length of name buffer */
219 char __user *name; /**< Name of driver */
220 DRM_SIZE_T date_len; /**< Length of date buffer */
221 char __user *date; /**< User-space buffer to hold date */
222 DRM_SIZE_T desc_len; /**< Length of desc buffer */
223 char __user *desc; /**< User-space buffer to hold desc */
227 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
229 * \sa drmGetBusid() and drmSetBusId().
231 typedef struct drm_unique {
232 DRM_SIZE_T unique_len; /**< Length of unique */
233 char __user *unique; /**< Unique name for driver instantiation */
238 typedef struct drm_list {
239 int count; /**< Length of user-space structures */
240 drm_version_t __user *version;
243 typedef struct drm_block {
248 * DRM_IOCTL_CONTROL ioctl argument type.
250 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
252 typedef struct drm_control {
263 * Type of memory to map.
265 typedef enum drm_map_type {
266 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
267 _DRM_REGISTERS = 1, /**< no caching, no core dump */
268 _DRM_SHM = 2, /**< shared, cached */
269 _DRM_AGP = 3, /**< AGP/GART */
270 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
271 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
276 * Memory mapping flags.
278 typedef enum drm_map_flags {
279 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
280 _DRM_READ_ONLY = 0x02,
281 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
282 _DRM_KERNEL = 0x08, /**< kernel requires access */
283 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
284 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
285 _DRM_REMOVABLE = 0x40 /**< Removable mapping */
288 typedef struct drm_ctx_priv_map {
289 unsigned int ctx_id; /**< Context requesting private mapping */
290 void *handle; /**< Handle of map */
291 } drm_ctx_priv_map_t;
294 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
299 typedef struct drm_map {
300 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
301 unsigned long size; /**< Requested physical size (bytes) */
302 drm_map_type_t type; /**< Type of memory to map */
303 drm_map_flags_t flags; /**< Flags */
304 void *handle; /**< User-space: "Handle" to pass to mmap() */
305 /**< Kernel-space: kernel-virtual address */
306 int mtrr; /**< MTRR slot used */
311 * DRM_IOCTL_GET_CLIENT ioctl argument type.
313 typedef struct drm_client {
314 int idx; /**< Which client desired? */
315 int auth; /**< Is client authenticated? */
316 unsigned long pid; /**< Process ID */
317 unsigned long uid; /**< User ID */
318 unsigned long magic; /**< Magic */
319 unsigned long iocs; /**< Ioctl count */
329 _DRM_STAT_VALUE, /**< Generic value */
330 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
331 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
333 _DRM_STAT_IRQ, /**< IRQ */
334 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
335 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
336 _DRM_STAT_DMA, /**< DMA */
337 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
338 _DRM_STAT_MISSED /**< Missed DMA opportunity */
339 /* Add to the *END* of the list */
343 * DRM_IOCTL_GET_STATS ioctl argument type.
345 typedef struct drm_stats {
349 drm_stat_type_t type;
354 * Hardware locking flags.
356 typedef enum drm_lock_flags {
357 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
358 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
359 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
360 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
361 /* These *HALT* flags aren't supported yet
362 -- they will be used to support the
363 full-screen DGA-like mode. */
364 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
365 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
369 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
371 * \sa drmGetLock() and drmUnlock().
373 typedef struct drm_lock {
375 drm_lock_flags_t flags;
382 * These values \e must match xf86drm.h.
386 typedef enum drm_dma_flags {
387 /* Flags for DMA buffer dispatch */
388 _DRM_DMA_BLOCK = 0x01, /**<
389 * Block until buffer dispatched.
391 * \note The buffer may not yet have
392 * been processed by the hardware --
393 * getting a hardware lock with the
394 * hardware quiescent will ensure
395 * that the buffer has been
398 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
399 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
401 /* Flags for DMA buffer request */
402 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
403 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
404 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
408 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
412 typedef struct drm_buf_desc {
413 int count; /**< Number of buffers of this size */
414 int size; /**< Size in bytes */
415 int low_mark; /**< Low water mark */
416 int high_mark; /**< High water mark */
418 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
419 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
420 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
421 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
422 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
424 unsigned long agp_start; /**<
425 * Start address of where the AGP buffers are
426 * in the AGP aperture
431 * DRM_IOCTL_INFO_BUFS ioctl argument type.
433 typedef struct drm_buf_info {
434 int count; /**< Number of buffers described in list */
435 drm_buf_desc_t __user *list; /**< List of buffer descriptions */
439 * DRM_IOCTL_FREE_BUFS ioctl argument type.
441 typedef struct drm_buf_free {
451 typedef struct drm_buf_pub {
452 int idx; /**< Index into the master buffer list */
453 int total; /**< Buffer size */
454 int used; /**< Amount of buffer in use (for DMA) */
455 void __user *address; /**< Address of buffer */
459 * DRM_IOCTL_MAP_BUFS ioctl argument type.
461 typedef struct drm_buf_map {
462 int count; /**< Length of the buffer list */
463 #if defined(__cplusplus)
464 void __user *c_virtual;
466 void __user *virtual; /**< Mmap'd area in user-virtual */
468 drm_buf_pub_t __user *list; /**< Buffer information */
472 * DRM_IOCTL_DMA ioctl argument type.
474 * Indices here refer to the offset into the buffer list in drm_buf_get.
478 typedef struct drm_dma {
479 int context; /**< Context handle */
480 int send_count; /**< Number of buffers to send */
481 int __user *send_indices; /**< List of handles to buffers */
482 int __user *send_sizes; /**< Lengths of data to send */
483 drm_dma_flags_t flags; /**< Flags */
484 int request_count; /**< Number of buffers requested */
485 int request_size; /**< Desired size for buffers */
486 int __user *request_indices; /**< Buffer information */
487 int __user *request_sizes;
488 int granted_count; /**< Number of buffers granted */
492 _DRM_CONTEXT_PRESERVED = 0x01,
493 _DRM_CONTEXT_2DONLY = 0x02
497 * DRM_IOCTL_ADD_CTX ioctl argument type.
499 * \sa drmCreateContext() and drmDestroyContext().
501 typedef struct drm_ctx {
502 drm_context_t handle;
503 drm_ctx_flags_t flags;
507 * DRM_IOCTL_RES_CTX ioctl argument type.
509 typedef struct drm_ctx_res {
511 drm_ctx_t __user *contexts;
515 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
517 typedef struct drm_draw {
518 drm_drawable_t handle;
522 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
525 DRM_DRAWABLE_CLIPRECTS,
526 } drm_drawable_info_type_t;
528 typedef struct drm_update_draw {
529 drm_drawable_t handle;
532 unsigned long long data;
536 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
538 typedef struct drm_auth {
543 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
545 * \sa drmGetInterruptFromBusID().
547 typedef struct drm_irq_busid {
548 int irq; /**< IRQ number */
549 int busnum; /**< bus number */
550 int devnum; /**< device number */
551 int funcnum; /**< function number */
555 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
556 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
557 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
558 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
559 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
560 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
561 } drm_vblank_seq_type_t;
563 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
564 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \
565 _DRM_VBLANK_NEXTONMISS)
567 struct drm_wait_vblank_request {
568 drm_vblank_seq_type_t type;
569 unsigned int sequence;
570 unsigned long signal;
573 struct drm_wait_vblank_reply {
574 drm_vblank_seq_type_t type;
575 unsigned int sequence;
581 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
583 * \sa drmWaitVBlank().
585 typedef union drm_wait_vblank {
586 struct drm_wait_vblank_request request;
587 struct drm_wait_vblank_reply reply;
591 _DRM_PRE_MODESET = 1,
592 _DRM_POST_MODESET = 2,
593 } drm_modeset_ctl_cmd_t;
596 * DRM_IOCTL_MODESET_CTL ioctl argument type
598 * \sa drmModesetCtl().
600 typedef struct drm_modeset_ctl {
602 drm_modeset_ctl_cmd_t cmd;
606 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
608 * \sa drmAgpEnable().
610 typedef struct drm_agp_mode {
611 unsigned long mode; /**< AGP mode */
615 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
617 * \sa drmAgpAlloc() and drmAgpFree().
619 typedef struct drm_agp_buffer {
620 unsigned long size; /**< In bytes -- will round to page boundary */
621 unsigned long handle; /**< Used for binding / unbinding */
622 unsigned long type; /**< Type of memory to allocate */
623 unsigned long physical; /**< Physical used by i810 */
627 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
629 * \sa drmAgpBind() and drmAgpUnbind().
631 typedef struct drm_agp_binding {
632 unsigned long handle; /**< From drm_agp_buffer */
633 unsigned long offset; /**< In bytes -- will round to page boundary */
637 * DRM_IOCTL_AGP_INFO ioctl argument type.
639 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
640 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
641 * drmAgpVendorId() and drmAgpDeviceId().
643 typedef struct drm_agp_info {
644 int agp_version_major;
645 int agp_version_minor;
647 unsigned long aperture_base; /**< physical address */
648 unsigned long aperture_size; /**< bytes */
649 unsigned long memory_allowed; /**< bytes */
650 unsigned long memory_used;
652 /** \name PCI information */
654 unsigned short id_vendor;
655 unsigned short id_device;
660 * DRM_IOCTL_SG_ALLOC ioctl argument type.
662 typedef struct drm_scatter_gather {
663 unsigned long size; /**< In bytes -- will round to page boundary */
664 unsigned long handle; /**< Used for mapping / unmapping */
665 } drm_scatter_gather_t;
668 * DRM_IOCTL_SET_VERSION ioctl argument type.
670 typedef struct drm_set_version {
678 #define DRM_FENCE_FLAG_EMIT 0x00000001
679 #define DRM_FENCE_FLAG_SHAREABLE 0x00000002
680 #define DRM_FENCE_FLAG_WAIT_LAZY 0x00000004
681 #define DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS 0x00000008
683 /* Reserved for driver use */
684 #define DRM_FENCE_MASK_DRIVER 0xFF000000
686 #define DRM_FENCE_TYPE_EXE 0x00000001
688 typedef struct drm_fence_arg {
694 unsigned expand_pad[4]; /*Future expansion */
699 drm_fence_unreference,
708 /* Buffer permissions, referring to how the GPU uses the buffers.
709 * these translate to fence types used for the buffers.
710 * Typically a texture buffer is read, A destination buffer is write and
711 * a command (batch-) buffer is exe. Can be or-ed together.
714 #define DRM_BO_FLAG_READ 0x00000001
715 #define DRM_BO_FLAG_WRITE 0x00000002
716 #define DRM_BO_FLAG_EXE 0x00000004
719 * Status flags. Can be read to determine the actual state of a buffer.
720 * Can also be set in the buffer mask before validation.
724 * Mask: Never evict this buffer. Not even with force. This type of buffer is only
725 * available to root and must be manually removed before buffer manager shutdown
729 #define DRM_BO_FLAG_NO_EVICT 0x00000010
732 * Mask: Require that the buffer is placed in mappable memory when validated.
733 * If not set the buffer may or may not be in mappable memory when validated.
734 * Flags: If set, the buffer is in mappable memory.
736 #define DRM_BO_FLAG_MAPPABLE 0x00000020
738 /* Mask: The buffer should be shareable with other processes.
739 * Flags: The buffer is shareable with other processes.
741 #define DRM_BO_FLAG_SHAREABLE 0x00000040
743 /* Mask: If set, place the buffer in cache-coherent memory if available.
744 * If clear, never place the buffer in cache coherent memory if validated.
745 * Flags: The buffer is currently in cache-coherent memory.
747 #define DRM_BO_FLAG_CACHED 0x00000080
749 /* Mask: Make sure that every time this buffer is validated,
750 * it ends up on the same location provided that the memory mask is the same.
751 * The buffer will also not be evicted when claiming space for
752 * other buffers. Basically a pinned buffer but it may be thrown out as
753 * part of buffer manager shutdown or locking.
754 * Flags: Acknowledge.
756 #define DRM_BO_FLAG_NO_MOVE 0x00000100
758 /* Mask: Make sure the buffer is in cached memory when mapped for reading.
759 * Flags: Acknowledge.
761 #define DRM_BO_FLAG_READ_CACHED 0x00080000
763 /* Mask: Force DRM_BO_FLAG_CACHED flag strictly also if it is set.
764 * Flags: Acknowledge.
766 #define DRM_BO_FLAG_FORCE_CACHING 0x00002000
769 * Mask: Force DRM_BO_FLAG_MAPPABLE flag strictly also if it is clear.
770 * Flags: Acknowledge.
772 #define DRM_BO_FLAG_FORCE_MAPPABLE 0x00004000
775 * Memory type flags that can be or'ed together in the mask, but only
776 * one appears in flags.
780 #define DRM_BO_FLAG_MEM_LOCAL 0x01000000
781 /* Translation table memory */
782 #define DRM_BO_FLAG_MEM_TT 0x02000000
784 #define DRM_BO_FLAG_MEM_VRAM 0x04000000
785 /* Up to the driver to define. */
786 #define DRM_BO_FLAG_MEM_PRIV0 0x08000000
787 #define DRM_BO_FLAG_MEM_PRIV1 0x10000000
788 #define DRM_BO_FLAG_MEM_PRIV2 0x20000000
789 #define DRM_BO_FLAG_MEM_PRIV3 0x40000000
790 #define DRM_BO_FLAG_MEM_PRIV4 0x80000000
792 /* Memory flag mask */
793 #define DRM_BO_MASK_MEM 0xFF000000
794 #define DRM_BO_MASK_MEMTYPE 0xFF0000A0
796 /* Don't block on validate and map */
797 #define DRM_BO_HINT_DONT_BLOCK 0x00000002
798 /* Don't place this buffer on the unfenced list.*/
799 #define DRM_BO_HINT_DONT_FENCE 0x00000004
800 #define DRM_BO_HINT_WAIT_LAZY 0x00000008
801 #define DRM_BO_HINT_ALLOW_UNFENCED_MAP 0x00000010
808 drm_bo_type_kernel, /* for initial kernel allocations */
812 typedef struct drm_bo_arg_request {
813 unsigned handle; /* User space handle */
819 drm_u64_t buffer_start;
820 unsigned page_alignment;
821 unsigned expand_pad[4]; /*Future expansion */
835 } drm_bo_arg_request_t;
842 #define DRM_BO_REP_BUSY 0x00000001
844 typedef struct drm_bo_arg_reply {
850 drm_u64_t arg_handle;
852 drm_u64_t buffer_start;
853 unsigned fence_flags;
855 unsigned page_alignment;
856 unsigned expand_pad[4]; /*Future expansion */
860 typedef struct drm_bo_arg{
864 drm_bo_arg_request_t req;
865 drm_bo_arg_reply_t rep;
869 #define DRM_BO_MEM_LOCAL 0
870 #define DRM_BO_MEM_TT 1
871 #define DRM_BO_MEM_VRAM 2
872 #define DRM_BO_MEM_PRIV0 3
873 #define DRM_BO_MEM_PRIV1 4
874 #define DRM_BO_MEM_PRIV2 5
875 #define DRM_BO_MEM_PRIV3 6
876 #define DRM_BO_MEM_PRIV4 7
878 #define DRM_BO_MEM_TYPES 8 /* For now. */
880 typedef union drm_mm_init_arg{
892 unsigned expand_pad[8]; /*Future expansion */
895 drm_handle_t mm_sarea;
896 unsigned expand_pad[8]; /*Future expansion */
901 * \name Ioctls Definitions
905 #define DRM_IOCTL_BASE 'd'
906 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
907 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
908 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
909 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
911 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
912 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
913 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
914 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
915 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t)
916 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t)
917 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t)
918 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t)
920 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
921 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
922 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
923 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
924 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
925 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
926 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
927 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
928 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
929 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
930 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
932 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t)
934 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t)
935 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t)
937 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
938 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
939 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
940 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
941 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
942 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
943 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
944 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
945 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
946 #define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
947 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
948 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
949 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
951 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
952 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
953 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
954 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
955 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
956 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
957 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
958 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
960 #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t)
961 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t)
963 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t)
965 #define DRM_IOCTL_FENCE DRM_IOWR(0x3b, drm_fence_arg_t)
966 #define DRM_IOCTL_BUFOBJ DRM_IOWR(0x3d, drm_bo_arg_t)
967 #define DRM_IOCTL_MM_INIT DRM_IOWR(0x3e, drm_mm_init_arg_t)
969 #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, drm_update_draw_t)
971 #define DRM_IOCTL_MODESET_CTL DRM_IOW(0xa0, drm_modeset_ctl_t)
976 * Device specific ioctls should only be in their respective headers
977 * The device specific ioctl range is from 0x40 to 0x99.
978 * Generic IOCTLS restart at 0xA0.
980 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
981 * drmCommandReadWrite().
983 #define DRM_COMMAND_BASE 0x40
984 #define DRM_COMMAND_END 0xA0