linux-core/radeon_buffer.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2007 Dave Airlie
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  18  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  19  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  *
  26  *
  27  **************************************************************************/
  28 /*
  29  * Authors: Dave Airlie <airlied@linux.ie>
  30  */
  31
  32 #include "drmP.h"
  33 #include "radeon_drm.h"
  34 #include "radeon_drv.h"
  35
  36 struct drm_ttm_backend *radeon_create_ttm_backend_entry(struct drm_device * dev)
  37 {
  38         drm_radeon_private_t *dev_priv = dev->dev_private;
  39
  40         if(dev_priv->flags & RADEON_IS_AGP)
  41                 return drm_agp_init_ttm(dev);
  42         else
  43                 return ati_pcigart_init_ttm(dev, &dev_priv->gart_info, radeon_gart_flush);
  44 }
  45
  46 int radeon_fence_types(struct drm_buffer_object *bo, uint32_t * class, uint32_t * type)
  47 {
  48         *class = 0;
  49         if (bo->mem.flags & (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE))
  50                 *type = 3;
  51         else
  52                 *type = 1;
  53         return 0;
  54 }
  55
  56 int radeon_invalidate_caches(struct drm_device * dev, uint64_t flags)
  57 {
  58         drm_radeon_private_t *dev_priv = dev->dev_private;
  59         RING_LOCALS;
  60
  61         BEGIN_RING(4);
  62         RADEON_FLUSH_CACHE();
  63         RADEON_FLUSH_ZCACHE();
  64         ADVANCE_RING();
  65         return 0;
  66 }
  67
  68 uint32_t radeon_evict_mask(struct drm_buffer_object *bo)
  69 {
  70         switch (bo->mem.mem_type) {
  71         case DRM_BO_MEM_LOCAL:
  72         case DRM_BO_MEM_TT:
  73                 return DRM_BO_FLAG_MEM_LOCAL;
  74         case DRM_BO_MEM_VRAM:
  75                 if (bo->mem.num_pages > 128)
  76                         return DRM_BO_MEM_TT;
  77                 else
  78                         return DRM_BO_MEM_LOCAL;
  79         default:
  80                 return DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_CACHED;
  81         }
  82 }
  83
  84 int radeon_init_mem_type(struct drm_device * dev, uint32_t type,
  85                          struct drm_mem_type_manager * man)
  86 {
  87         drm_radeon_private_t *dev_priv = dev->dev_private;
  88
  89         switch (type) {
  90         case DRM_BO_MEM_LOCAL:
  91                 man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
  92                     _DRM_FLAG_MEMTYPE_CACHED;
  93                 man->drm_bus_maptype = 0;
  94                 break;
  95         case DRM_BO_MEM_VRAM:
  96                 man->flags =  _DRM_FLAG_MEMTYPE_FIXED | _DRM_FLAG_MEMTYPE_MAPPABLE | _DRM_FLAG_NEEDS_IOREMAP;
  97                 man->io_addr = NULL;
  98                 man->drm_bus_maptype = _DRM_FRAME_BUFFER;
  99                 man->io_offset = drm_get_resource_start(dev, 0);
 100                 man->io_size = drm_get_resource_len(dev, 0);
 101                 break;
 102         case DRM_BO_MEM_TT:
 103                 if (dev_priv->flags & RADEON_IS_AGP) {
 104                         if (!(drm_core_has_AGP(dev) && dev->agp)) {
 105                                 DRM_ERROR("AGP is not enabled for memory type %u\n",
 106                                           (unsigned)type);
 107                                 return -EINVAL;
 108                         }
 109                         man->io_offset = dev->agp->agp_info.aper_base;
 110                         man->io_size = dev->agp->agp_info.aper_size * 1024 * 1024;
 111                         man->io_addr = NULL;
 112                         man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
 113                                 _DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_NEEDS_IOREMAP;
 114                         man->drm_bus_maptype = _DRM_AGP;
 115                 } else {
 116                         man->io_offset = dev_priv->gart_vm_start;
 117                         man->io_size = dev_priv->gart_size;
 118                         man->io_addr = NULL;
 119                         man->flags = _DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_MEMTYPE_MAPPABLE | _DRM_FLAG_MEMTYPE_CMA;
 120                         man->drm_bus_maptype = _DRM_SCATTER_GATHER;
 121                 }
 122                 break;
 123         default:
 124                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 125                 return -EINVAL;
 126         }
 127         return 0;
 128 }
 129
 130 static void radeon_emit_copy_blit(struct drm_device * dev,
 131                                   uint32_t src_offset,
 132                                   uint32_t dst_offset,
 133                                   uint32_t pages, int direction)
 134 {
 135         uint32_t cur_pages;
 136         uint32_t stride = PAGE_SIZE;
 137         drm_radeon_private_t *dev_priv = dev->dev_private;
 138         uint32_t format, height;
 139         RING_LOCALS;
 140
 141         if (!dev_priv)
 142                 return;
 143
 144         /* 32-bit copy format */
 145         format = RADEON_COLOR_FORMAT_ARGB8888;
 146
 147         /* radeon limited to 16k stride */
 148         stride &= 0x3fff;
 149         while(pages > 0) {
 150                 cur_pages = pages;
 151                 if (cur_pages > 2048)
 152                         cur_pages = 2048;
 153                 pages -= cur_pages;
 154
 155                 /* needs verification */
 156                 BEGIN_RING(7);
 157                 OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5));
 158                 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 159                          RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 160                          RADEON_GMC_BRUSH_NONE |
 161                          (format << 8) |
 162                          RADEON_GMC_SRC_DATATYPE_COLOR |
 163                          RADEON_ROP3_S |
 164                          RADEON_DP_SRC_SOURCE_MEMORY |
 165                          RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
 166                 if (direction) {
 167                         OUT_RING((stride << 22) | (src_offset >> 10));
 168                         OUT_RING((stride << 22) | (dst_offset >> 10));
 169                 } else {
 170                         OUT_RING((stride << 22) | (dst_offset >> 10));
 171                         OUT_RING((stride << 22) | (src_offset >> 10));
 172                 }
 173                 OUT_RING(0);
 174                 OUT_RING(pages); /* x - y */
 175                 OUT_RING((stride << 16) | cur_pages);
 176                 ADVANCE_RING();
 177         }
 178
 179         BEGIN_RING(2);
 180         RADEON_WAIT_UNTIL_2D_IDLE();
 181         ADVANCE_RING();
 182
 183         return;
 184 }
 185
 186 static int radeon_move_blit(struct drm_buffer_object * bo,
 187                             int evict, int no_wait, struct drm_bo_mem_reg *new_mem)
 188 {
 189         struct drm_bo_mem_reg *old_mem = &bo->mem;
 190         int dir = 0;
 191
 192         if ((old_mem->mem_type == new_mem->mem_type) &&
 193             (new_mem->mm_node->start <
 194              old_mem->mm_node->start + old_mem->mm_node->size)) {
 195                 dir = 1;
 196         }
 197
 198         radeon_emit_copy_blit(bo->dev,
 199                               old_mem->mm_node->start << PAGE_SHIFT,
 200                               new_mem->mm_node->start << PAGE_SHIFT,
 201                               new_mem->num_pages, dir);
 202
 203
 204         return drm_bo_move_accel_cleanup(bo, evict, no_wait, 0,
 205                                          DRM_FENCE_TYPE_EXE |
 206                                          DRM_RADEON_FENCE_TYPE_RW,
 207                                          DRM_RADEON_FENCE_FLAG_FLUSHED, new_mem);
 208 }
 209
 210 static int radeon_move_flip(struct drm_buffer_object * bo,
 211                             int evict, int no_wait, struct drm_bo_mem_reg * new_mem)
 212 {
 213         struct drm_device *dev = bo->dev;
 214         struct drm_bo_mem_reg tmp_mem;
 215         int ret;
 216
 217         tmp_mem = *new_mem;
 218         tmp_mem.mm_node = NULL;
 219         tmp_mem.mask = DRM_BO_FLAG_MEM_TT |
 220             DRM_BO_FLAG_CACHED | DRM_BO_FLAG_FORCE_CACHING;
 221
 222         ret = drm_bo_mem_space(bo, &tmp_mem, no_wait);
 223         if (ret)
 224                 return ret;
 225
 226         ret = drm_bind_ttm(bo->ttm, &tmp_mem);
 227         if (ret)
 228                 goto out_cleanup;
 229
 230         ret = radeon_move_blit(bo, 1, no_wait, &tmp_mem);
 231         if (ret)
 232                 goto out_cleanup;
 233
 234         ret = drm_bo_move_ttm(bo, evict, no_wait, new_mem);
 235 out_cleanup:
 236         if (tmp_mem.mm_node) {
 237                 mutex_lock(&dev->struct_mutex);
 238                 if (tmp_mem.mm_node != bo->pinned_node)
 239                         drm_mm_put_block(tmp_mem.mm_node);
 240                 tmp_mem.mm_node = NULL;
 241                 mutex_unlock(&dev->struct_mutex);
 242         }
 243         return ret;
 244 }
 245
 246 int radeon_move(struct drm_buffer_object * bo,
 247                 int evict, int no_wait, struct drm_bo_mem_reg * new_mem)
 248 {
 249         struct drm_bo_mem_reg *old_mem = &bo->mem;
 250
 251         DRM_DEBUG("\n");
 252         if (old_mem->mem_type == DRM_BO_MEM_LOCAL) {
 253                 return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
 254         } else if (new_mem->mem_type == DRM_BO_MEM_LOCAL) {
 255                 if (radeon_move_flip(bo, evict, no_wait, new_mem))
 256                         return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
 257         } else {
 258                 if (radeon_move_blit(bo, evict, no_wait, new_mem))
 259                         return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
 260         }
 261         return 0;
 262 }
 263