1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007-2012 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
58 #define ETIME ETIMEDOUT
61 #include "libdrm_lists.h"
62 #include "intel_bufmgr.h"
63 #include "intel_bufmgr_priv.h"
64 #include "intel_chipset.h"
65 #include "intel_aub.h"
78 #define VG_CLEAR(s) VG(memset(&s, 0, sizeof(s)))
80 #define DBG(...) do { \
81 if (bufmgr_gem->bufmgr.debug) \
82 fprintf(stderr, __VA_ARGS__); \
85 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
87 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
89 struct drm_intel_gem_bo_bucket {
94 typedef struct _drm_intel_bufmgr_gem {
95 drm_intel_bufmgr bufmgr;
103 pthread_mutex_t lock;
105 struct drm_i915_gem_exec_object *exec_objects;
106 struct drm_i915_gem_exec_object2 *exec2_objects;
107 drm_intel_bo **exec_bos;
111 /** Array of lists of cached gem objects of power-of-two sizes */
112 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
116 drmMMListHead managers;
119 drmMMListHead vma_cache;
120 int vma_count, vma_open, vma_max;
123 int available_fences;
126 unsigned int has_bsd : 1;
127 unsigned int has_blt : 1;
128 unsigned int has_relaxed_fencing : 1;
129 unsigned int has_llc : 1;
130 unsigned int has_wait_timeout : 1;
131 unsigned int bo_reuse : 1;
132 unsigned int no_exec : 1;
133 unsigned int has_vebox : 1;
139 } drm_intel_bufmgr_gem;
141 #define DRM_INTEL_RELOC_FENCE (1<<0)
143 typedef struct _drm_intel_reloc_target_info {
146 } drm_intel_reloc_target;
148 struct _drm_intel_bo_gem {
156 * Kenel-assigned global name for this object
158 * List contains both flink named and prime fd'd objects
160 unsigned int global_name;
161 drmMMListHead name_list;
164 * Index of the buffer within the validation list while preparing a
165 * batchbuffer execution.
170 * Current tiling mode
172 uint32_t tiling_mode;
173 uint32_t swizzle_mode;
174 unsigned long stride;
178 /** Array passed to the DRM containing relocation information. */
179 struct drm_i915_gem_relocation_entry *relocs;
181 * Array of info structs corresponding to relocs[i].target_handle etc
183 drm_intel_reloc_target *reloc_target_info;
184 /** Number of entries in relocs */
186 /** Mapped address for the buffer, saved across map/unmap cycles */
188 /** GTT virtual address for the buffer, saved across map/unmap cycles */
191 * Virtual address of the buffer allocated by user, used for userptr
196 drmMMListHead vma_list;
202 * Boolean of whether this BO and its children have been included in
203 * the current drm_intel_bufmgr_check_aperture_space() total.
205 bool included_in_check_aperture;
208 * Boolean of whether this buffer has been used as a relocation
209 * target and had its size accounted for, and thus can't have any
210 * further relocations added to it.
212 bool used_as_reloc_target;
215 * Boolean of whether we have encountered an error whilst building the relocation tree.
220 * Boolean of whether this buffer can be re-used
225 * Boolean of whether the GPU is definitely not accessing the buffer.
227 * This is only valid when reusable, since non-reusable
228 * buffers are those that have been shared wth other
229 * processes, so we don't know their state.
234 * Boolean of whether this buffer was allocated with userptr
239 * Size in bytes of this buffer and its relocation descendents.
241 * Used to avoid costly tree walking in
242 * drm_intel_bufmgr_check_aperture in the common case.
247 * Number of potential fence registers required by this buffer and its
250 int reloc_tree_fences;
252 /** Flags that we may need to do the SW_FINSIH ioctl on unmap. */
253 bool mapped_cpu_write;
257 drm_intel_aub_annotation *aub_annotations;
258 unsigned aub_annotation_count;
262 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
265 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
268 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
269 uint32_t * swizzle_mode);
272 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
273 uint32_t tiling_mode,
276 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
279 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
281 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
284 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
285 uint32_t *tiling_mode)
287 unsigned long min_size, max_size;
290 if (*tiling_mode == I915_TILING_NONE)
293 /* 965+ just need multiples of page size for tiling */
294 if (bufmgr_gem->gen >= 4)
295 return ROUND_UP_TO(size, 4096);
297 /* Older chips need powers of two, of at least 512k or 1M */
298 if (bufmgr_gem->gen == 3) {
299 min_size = 1024*1024;
300 max_size = 128*1024*1024;
303 max_size = 64*1024*1024;
306 if (size > max_size) {
307 *tiling_mode = I915_TILING_NONE;
311 /* Do we need to allocate every page for the fence? */
312 if (bufmgr_gem->has_relaxed_fencing)
313 return ROUND_UP_TO(size, 4096);
315 for (i = min_size; i < size; i <<= 1)
322 * Round a given pitch up to the minimum required for X tiling on a
323 * given chip. We use 512 as the minimum to allow for a later tiling
327 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
328 unsigned long pitch, uint32_t *tiling_mode)
330 unsigned long tile_width;
333 /* If untiled, then just align it so that we can do rendering
334 * to it with the 3D engine.
336 if (*tiling_mode == I915_TILING_NONE)
337 return ALIGN(pitch, 64);
339 if (*tiling_mode == I915_TILING_X
340 || (IS_915(bufmgr_gem->pci_device)
341 && *tiling_mode == I915_TILING_Y))
346 /* 965 is flexible */
347 if (bufmgr_gem->gen >= 4)
348 return ROUND_UP_TO(pitch, tile_width);
350 /* The older hardware has a maximum pitch of 8192 with tiled
351 * surfaces, so fallback to untiled if it's too large.
354 *tiling_mode = I915_TILING_NONE;
355 return ALIGN(pitch, 64);
358 /* Pre-965 needs power of two tile width */
359 for (i = tile_width; i < pitch; i <<= 1)
365 static struct drm_intel_gem_bo_bucket *
366 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
371 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
372 struct drm_intel_gem_bo_bucket *bucket =
373 &bufmgr_gem->cache_bucket[i];
374 if (bucket->size >= size) {
383 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
387 for (i = 0; i < bufmgr_gem->exec_count; i++) {
388 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
389 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
391 if (bo_gem->relocs == NULL) {
392 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
397 for (j = 0; j < bo_gem->reloc_count; j++) {
398 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
399 drm_intel_bo_gem *target_gem =
400 (drm_intel_bo_gem *) target_bo;
402 DBG("%2d: %d (%s)@0x%08llx -> "
403 "%d (%s)@0x%08lx + 0x%08x\n",
405 bo_gem->gem_handle, bo_gem->name,
406 (unsigned long long)bo_gem->relocs[j].offset,
407 target_gem->gem_handle,
410 bo_gem->relocs[j].delta);
416 drm_intel_gem_bo_reference(drm_intel_bo *bo)
418 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
420 atomic_inc(&bo_gem->refcount);
424 * Adds the given buffer to the list of buffers to be validated (moved into the
425 * appropriate memory type) with the next batch submission.
427 * If a buffer is validated multiple times in a batch submission, it ends up
428 * with the intersection of the memory type flags and the union of the
432 drm_intel_add_validate_buffer(drm_intel_bo *bo)
434 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
435 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
438 if (bo_gem->validate_index != -1)
441 /* Extend the array of validation entries as necessary. */
442 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
443 int new_size = bufmgr_gem->exec_size * 2;
448 bufmgr_gem->exec_objects =
449 realloc(bufmgr_gem->exec_objects,
450 sizeof(*bufmgr_gem->exec_objects) * new_size);
451 bufmgr_gem->exec_bos =
452 realloc(bufmgr_gem->exec_bos,
453 sizeof(*bufmgr_gem->exec_bos) * new_size);
454 bufmgr_gem->exec_size = new_size;
457 index = bufmgr_gem->exec_count;
458 bo_gem->validate_index = index;
459 /* Fill in array entry */
460 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
461 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
462 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
463 bufmgr_gem->exec_objects[index].alignment = 0;
464 bufmgr_gem->exec_objects[index].offset = 0;
465 bufmgr_gem->exec_bos[index] = bo;
466 bufmgr_gem->exec_count++;
470 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
472 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
473 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
476 if (bo_gem->validate_index != -1) {
478 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
479 EXEC_OBJECT_NEEDS_FENCE;
483 /* Extend the array of validation entries as necessary. */
484 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
485 int new_size = bufmgr_gem->exec_size * 2;
490 bufmgr_gem->exec2_objects =
491 realloc(bufmgr_gem->exec2_objects,
492 sizeof(*bufmgr_gem->exec2_objects) * new_size);
493 bufmgr_gem->exec_bos =
494 realloc(bufmgr_gem->exec_bos,
495 sizeof(*bufmgr_gem->exec_bos) * new_size);
496 bufmgr_gem->exec_size = new_size;
499 index = bufmgr_gem->exec_count;
500 bo_gem->validate_index = index;
501 /* Fill in array entry */
502 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
503 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
504 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
505 bufmgr_gem->exec2_objects[index].alignment = 0;
506 bufmgr_gem->exec2_objects[index].offset = 0;
507 bufmgr_gem->exec_bos[index] = bo;
508 bufmgr_gem->exec2_objects[index].flags = 0;
509 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
510 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
512 bufmgr_gem->exec2_objects[index].flags |=
513 EXEC_OBJECT_NEEDS_FENCE;
515 bufmgr_gem->exec_count++;
518 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
522 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
523 drm_intel_bo_gem *bo_gem)
527 assert(!bo_gem->used_as_reloc_target);
529 /* The older chipsets are far-less flexible in terms of tiling,
530 * and require tiled buffer to be size aligned in the aperture.
531 * This means that in the worst possible case we will need a hole
532 * twice as large as the object in order for it to fit into the
533 * aperture. Optimal packing is for wimps.
535 size = bo_gem->bo.size;
536 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
539 if (bufmgr_gem->has_relaxed_fencing) {
540 if (bufmgr_gem->gen == 3)
541 min_size = 1024*1024;
545 while (min_size < size)
550 /* Account for worst-case alignment. */
554 bo_gem->reloc_tree_size = size;
558 drm_intel_setup_reloc_list(drm_intel_bo *bo)
560 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
561 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
562 unsigned int max_relocs = bufmgr_gem->max_relocs;
564 if (bo->size / 4 < max_relocs)
565 max_relocs = bo->size / 4;
567 bo_gem->relocs = malloc(max_relocs *
568 sizeof(struct drm_i915_gem_relocation_entry));
569 bo_gem->reloc_target_info = malloc(max_relocs *
570 sizeof(drm_intel_reloc_target));
571 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
572 bo_gem->has_error = true;
574 free (bo_gem->relocs);
575 bo_gem->relocs = NULL;
577 free (bo_gem->reloc_target_info);
578 bo_gem->reloc_target_info = NULL;
587 drm_intel_gem_bo_busy(drm_intel_bo *bo)
589 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
590 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
591 struct drm_i915_gem_busy busy;
594 if (bo_gem->reusable && bo_gem->idle)
598 busy.handle = bo_gem->gem_handle;
600 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
602 bo_gem->idle = !busy.busy;
607 return (ret == 0 && busy.busy);
611 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
612 drm_intel_bo_gem *bo_gem, int state)
614 struct drm_i915_gem_madvise madv;
617 madv.handle = bo_gem->gem_handle;
620 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
622 return madv.retained;
626 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
628 return drm_intel_gem_bo_madvise_internal
629 ((drm_intel_bufmgr_gem *) bo->bufmgr,
630 (drm_intel_bo_gem *) bo,
634 /* drop the oldest entries that have been purged by the kernel */
636 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
637 struct drm_intel_gem_bo_bucket *bucket)
639 while (!DRMLISTEMPTY(&bucket->head)) {
640 drm_intel_bo_gem *bo_gem;
642 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
643 bucket->head.next, head);
644 if (drm_intel_gem_bo_madvise_internal
645 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
648 DRMLISTDEL(&bo_gem->head);
649 drm_intel_gem_bo_free(&bo_gem->bo);
653 static drm_intel_bo *
654 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
658 uint32_t tiling_mode,
659 unsigned long stride)
661 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
662 drm_intel_bo_gem *bo_gem;
663 unsigned int page_size = getpagesize();
665 struct drm_intel_gem_bo_bucket *bucket;
666 bool alloc_from_cache;
667 unsigned long bo_size;
668 bool for_render = false;
670 if (flags & BO_ALLOC_FOR_RENDER)
673 /* Round the allocated size up to a power of two number of pages. */
674 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
676 /* If we don't have caching at this size, don't actually round the
679 if (bucket == NULL) {
681 if (bo_size < page_size)
684 bo_size = bucket->size;
687 pthread_mutex_lock(&bufmgr_gem->lock);
688 /* Get a buffer out of the cache if available */
690 alloc_from_cache = false;
691 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
693 /* Allocate new render-target BOs from the tail (MRU)
694 * of the list, as it will likely be hot in the GPU
695 * cache and in the aperture for us.
697 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
698 bucket->head.prev, head);
699 DRMLISTDEL(&bo_gem->head);
700 alloc_from_cache = true;
702 /* For non-render-target BOs (where we're probably
703 * going to map it first thing in order to fill it
704 * with data), check if the last BO in the cache is
705 * unbusy, and only reuse in that case. Otherwise,
706 * allocating a new buffer is probably faster than
707 * waiting for the GPU to finish.
709 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
710 bucket->head.next, head);
711 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
712 alloc_from_cache = true;
713 DRMLISTDEL(&bo_gem->head);
717 if (alloc_from_cache) {
718 if (!drm_intel_gem_bo_madvise_internal
719 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
720 drm_intel_gem_bo_free(&bo_gem->bo);
721 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
726 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
729 drm_intel_gem_bo_free(&bo_gem->bo);
734 pthread_mutex_unlock(&bufmgr_gem->lock);
736 if (!alloc_from_cache) {
737 struct drm_i915_gem_create create;
739 bo_gem = calloc(1, sizeof(*bo_gem));
743 bo_gem->bo.size = bo_size;
746 create.size = bo_size;
748 ret = drmIoctl(bufmgr_gem->fd,
749 DRM_IOCTL_I915_GEM_CREATE,
751 bo_gem->gem_handle = create.handle;
752 bo_gem->bo.handle = bo_gem->gem_handle;
757 bo_gem->bo.bufmgr = bufmgr;
759 bo_gem->tiling_mode = I915_TILING_NONE;
760 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
763 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
766 drm_intel_gem_bo_free(&bo_gem->bo);
770 DRMINITLISTHEAD(&bo_gem->name_list);
771 DRMINITLISTHEAD(&bo_gem->vma_list);
775 atomic_set(&bo_gem->refcount, 1);
776 bo_gem->validate_index = -1;
777 bo_gem->reloc_tree_fences = 0;
778 bo_gem->used_as_reloc_target = false;
779 bo_gem->has_error = false;
780 bo_gem->reusable = true;
781 bo_gem->aub_annotations = NULL;
782 bo_gem->aub_annotation_count = 0;
784 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
786 DBG("bo_create: buf %d (%s) %ldb\n",
787 bo_gem->gem_handle, bo_gem->name, size);
792 static drm_intel_bo *
793 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
796 unsigned int alignment)
798 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
800 I915_TILING_NONE, 0);
803 static drm_intel_bo *
804 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
807 unsigned int alignment)
809 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
810 I915_TILING_NONE, 0);
813 static drm_intel_bo *
814 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
815 int x, int y, int cpp, uint32_t *tiling_mode,
816 unsigned long *pitch, unsigned long flags)
818 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
819 unsigned long size, stride;
823 unsigned long aligned_y, height_alignment;
825 tiling = *tiling_mode;
827 /* If we're tiled, our allocations are in 8 or 32-row blocks,
828 * so failure to align our height means that we won't allocate
831 * If we're untiled, we still have to align to 2 rows high
832 * because the data port accesses 2x2 blocks even if the
833 * bottom row isn't to be rendered, so failure to align means
834 * we could walk off the end of the GTT and fault. This is
835 * documented on 965, and may be the case on older chipsets
836 * too so we try to be careful.
839 height_alignment = 2;
841 if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE)
842 height_alignment = 16;
843 else if (tiling == I915_TILING_X
844 || (IS_915(bufmgr_gem->pci_device)
845 && tiling == I915_TILING_Y))
846 height_alignment = 8;
847 else if (tiling == I915_TILING_Y)
848 height_alignment = 32;
849 aligned_y = ALIGN(y, height_alignment);
852 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
853 size = stride * aligned_y;
854 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
855 } while (*tiling_mode != tiling);
858 if (tiling == I915_TILING_NONE)
861 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
865 static drm_intel_bo *
866 drm_intel_gem_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
869 uint32_t tiling_mode,
874 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
875 drm_intel_bo_gem *bo_gem;
877 struct drm_i915_gem_userptr userptr;
879 /* Tiling with userptr surfaces is not supported
880 * on all hardware so refuse it for time being.
882 if (tiling_mode != I915_TILING_NONE)
885 bo_gem = calloc(1, sizeof(*bo_gem));
889 bo_gem->bo.size = size;
892 userptr.user_ptr = (__u64)((unsigned long)addr);
893 userptr.user_size = size;
894 userptr.flags = flags;
896 ret = drmIoctl(bufmgr_gem->fd,
897 DRM_IOCTL_I915_GEM_USERPTR,
900 DBG("bo_create_userptr: "
901 "ioctl failed with user ptr %p size 0x%lx, "
902 "user flags 0x%lx\n", addr, size, flags);
907 bo_gem->gem_handle = userptr.handle;
908 bo_gem->bo.handle = bo_gem->gem_handle;
909 bo_gem->bo.bufmgr = bufmgr;
910 bo_gem->is_userptr = true;
911 bo_gem->bo.virtual = addr;
912 /* Save the address provided by user */
913 bo_gem->user_virtual = addr;
914 bo_gem->tiling_mode = I915_TILING_NONE;
915 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
918 DRMINITLISTHEAD(&bo_gem->name_list);
919 DRMINITLISTHEAD(&bo_gem->vma_list);
922 atomic_set(&bo_gem->refcount, 1);
923 bo_gem->validate_index = -1;
924 bo_gem->reloc_tree_fences = 0;
925 bo_gem->used_as_reloc_target = false;
926 bo_gem->has_error = false;
927 bo_gem->reusable = false;
929 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
931 DBG("bo_create_userptr: "
932 "ptr %p buf %d (%s) size %ldb, stride 0x%x, tile mode %d\n",
933 addr, bo_gem->gem_handle, bo_gem->name,
934 size, stride, tiling_mode);
940 * Returns a drm_intel_bo wrapping the given buffer object handle.
942 * This can be used when one application needs to pass a buffer object
945 drm_public drm_intel_bo *
946 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
950 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
951 drm_intel_bo_gem *bo_gem;
953 struct drm_gem_open open_arg;
954 struct drm_i915_gem_get_tiling get_tiling;
957 /* At the moment most applications only have a few named bo.
958 * For instance, in a DRI client only the render buffers passed
959 * between X and the client are named. And since X returns the
960 * alternating names for the front/back buffer a linear search
961 * provides a sufficiently fast match.
963 for (list = bufmgr_gem->named.next;
964 list != &bufmgr_gem->named;
966 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
967 if (bo_gem->global_name == handle) {
968 drm_intel_gem_bo_reference(&bo_gem->bo);
974 open_arg.name = handle;
975 ret = drmIoctl(bufmgr_gem->fd,
979 DBG("Couldn't reference %s handle 0x%08x: %s\n",
980 name, handle, strerror(errno));
983 /* Now see if someone has used a prime handle to get this
984 * object from the kernel before by looking through the list
985 * again for a matching gem_handle
987 for (list = bufmgr_gem->named.next;
988 list != &bufmgr_gem->named;
990 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
991 if (bo_gem->gem_handle == open_arg.handle) {
992 drm_intel_gem_bo_reference(&bo_gem->bo);
997 bo_gem = calloc(1, sizeof(*bo_gem));
1001 bo_gem->bo.size = open_arg.size;
1002 bo_gem->bo.offset = 0;
1003 bo_gem->bo.offset64 = 0;
1004 bo_gem->bo.virtual = NULL;
1005 bo_gem->bo.bufmgr = bufmgr;
1006 bo_gem->name = name;
1007 atomic_set(&bo_gem->refcount, 1);
1008 bo_gem->validate_index = -1;
1009 bo_gem->gem_handle = open_arg.handle;
1010 bo_gem->bo.handle = open_arg.handle;
1011 bo_gem->global_name = handle;
1012 bo_gem->reusable = false;
1014 VG_CLEAR(get_tiling);
1015 get_tiling.handle = bo_gem->gem_handle;
1016 ret = drmIoctl(bufmgr_gem->fd,
1017 DRM_IOCTL_I915_GEM_GET_TILING,
1020 drm_intel_gem_bo_unreference(&bo_gem->bo);
1023 bo_gem->tiling_mode = get_tiling.tiling_mode;
1024 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
1025 /* XXX stride is unknown */
1026 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1028 DRMINITLISTHEAD(&bo_gem->vma_list);
1029 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
1030 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
1036 drm_intel_gem_bo_free(drm_intel_bo *bo)
1038 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1039 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1040 struct drm_gem_close close;
1043 DRMLISTDEL(&bo_gem->vma_list);
1044 if (bo_gem->mem_virtual) {
1045 VG(VALGRIND_FREELIKE_BLOCK(bo_gem->mem_virtual, 0));
1046 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
1047 bufmgr_gem->vma_count--;
1049 if (bo_gem->gtt_virtual) {
1050 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
1051 bufmgr_gem->vma_count--;
1054 /* Close this object */
1056 close.handle = bo_gem->gem_handle;
1057 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
1059 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
1060 bo_gem->gem_handle, bo_gem->name, strerror(errno));
1062 free(bo_gem->aub_annotations);
1067 drm_intel_gem_bo_mark_mmaps_incoherent(drm_intel_bo *bo)
1070 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1072 if (bo_gem->mem_virtual)
1073 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->mem_virtual, bo->size);
1075 if (bo_gem->gtt_virtual)
1076 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->gtt_virtual, bo->size);
1080 /** Frees all cached buffers significantly older than @time. */
1082 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
1086 if (bufmgr_gem->time == time)
1089 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1090 struct drm_intel_gem_bo_bucket *bucket =
1091 &bufmgr_gem->cache_bucket[i];
1093 while (!DRMLISTEMPTY(&bucket->head)) {
1094 drm_intel_bo_gem *bo_gem;
1096 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1097 bucket->head.next, head);
1098 if (time - bo_gem->free_time <= 1)
1101 DRMLISTDEL(&bo_gem->head);
1103 drm_intel_gem_bo_free(&bo_gem->bo);
1107 bufmgr_gem->time = time;
1110 static void drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem)
1114 DBG("%s: cached=%d, open=%d, limit=%d\n", __FUNCTION__,
1115 bufmgr_gem->vma_count, bufmgr_gem->vma_open, bufmgr_gem->vma_max);
1117 if (bufmgr_gem->vma_max < 0)
1120 /* We may need to evict a few entries in order to create new mmaps */
1121 limit = bufmgr_gem->vma_max - 2*bufmgr_gem->vma_open;
1125 while (bufmgr_gem->vma_count > limit) {
1126 drm_intel_bo_gem *bo_gem;
1128 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1129 bufmgr_gem->vma_cache.next,
1131 assert(bo_gem->map_count == 0);
1132 DRMLISTDELINIT(&bo_gem->vma_list);
1134 if (bo_gem->mem_virtual) {
1135 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
1136 bo_gem->mem_virtual = NULL;
1137 bufmgr_gem->vma_count--;
1139 if (bo_gem->gtt_virtual) {
1140 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
1141 bo_gem->gtt_virtual = NULL;
1142 bufmgr_gem->vma_count--;
1147 static void drm_intel_gem_bo_close_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1148 drm_intel_bo_gem *bo_gem)
1150 bufmgr_gem->vma_open--;
1151 DRMLISTADDTAIL(&bo_gem->vma_list, &bufmgr_gem->vma_cache);
1152 if (bo_gem->mem_virtual)
1153 bufmgr_gem->vma_count++;
1154 if (bo_gem->gtt_virtual)
1155 bufmgr_gem->vma_count++;
1156 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1159 static void drm_intel_gem_bo_open_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1160 drm_intel_bo_gem *bo_gem)
1162 bufmgr_gem->vma_open++;
1163 DRMLISTDEL(&bo_gem->vma_list);
1164 if (bo_gem->mem_virtual)
1165 bufmgr_gem->vma_count--;
1166 if (bo_gem->gtt_virtual)
1167 bufmgr_gem->vma_count--;
1168 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1172 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
1174 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1175 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1176 struct drm_intel_gem_bo_bucket *bucket;
1179 /* Unreference all the target buffers */
1180 for (i = 0; i < bo_gem->reloc_count; i++) {
1181 if (bo_gem->reloc_target_info[i].bo != bo) {
1182 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
1183 reloc_target_info[i].bo,
1187 bo_gem->reloc_count = 0;
1188 bo_gem->used_as_reloc_target = false;
1190 DBG("bo_unreference final: %d (%s)\n",
1191 bo_gem->gem_handle, bo_gem->name);
1193 /* release memory associated with this object */
1194 if (bo_gem->reloc_target_info) {
1195 free(bo_gem->reloc_target_info);
1196 bo_gem->reloc_target_info = NULL;
1198 if (bo_gem->relocs) {
1199 free(bo_gem->relocs);
1200 bo_gem->relocs = NULL;
1203 /* Clear any left-over mappings */
1204 if (bo_gem->map_count) {
1205 DBG("bo freed with non-zero map-count %d\n", bo_gem->map_count);
1206 bo_gem->map_count = 0;
1207 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1208 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1211 DRMLISTDEL(&bo_gem->name_list);
1213 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
1214 /* Put the buffer into our internal cache for reuse if we can. */
1215 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
1216 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
1217 I915_MADV_DONTNEED)) {
1218 bo_gem->free_time = time;
1220 bo_gem->name = NULL;
1221 bo_gem->validate_index = -1;
1223 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
1225 drm_intel_gem_bo_free(bo);
1229 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
1232 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1234 assert(atomic_read(&bo_gem->refcount) > 0);
1235 if (atomic_dec_and_test(&bo_gem->refcount))
1236 drm_intel_gem_bo_unreference_final(bo, time);
1239 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
1241 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1243 assert(atomic_read(&bo_gem->refcount) > 0);
1245 if (atomic_add_unless(&bo_gem->refcount, -1, 1)) {
1246 drm_intel_bufmgr_gem *bufmgr_gem =
1247 (drm_intel_bufmgr_gem *) bo->bufmgr;
1248 struct timespec time;
1250 clock_gettime(CLOCK_MONOTONIC, &time);
1252 pthread_mutex_lock(&bufmgr_gem->lock);
1254 if (atomic_dec_and_test(&bo_gem->refcount)) {
1255 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
1256 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
1259 pthread_mutex_unlock(&bufmgr_gem->lock);
1263 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1265 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1266 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1267 struct drm_i915_gem_set_domain set_domain;
1270 if (bo_gem->is_userptr) {
1271 /* Return the same user ptr */
1272 bo->virtual = bo_gem->user_virtual;
1276 pthread_mutex_lock(&bufmgr_gem->lock);
1278 if (bo_gem->map_count++ == 0)
1279 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1281 if (!bo_gem->mem_virtual) {
1282 struct drm_i915_gem_mmap mmap_arg;
1284 DBG("bo_map: %d (%s), map_count=%d\n",
1285 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1288 mmap_arg.handle = bo_gem->gem_handle;
1289 mmap_arg.offset = 0;
1290 mmap_arg.size = bo->size;
1291 ret = drmIoctl(bufmgr_gem->fd,
1292 DRM_IOCTL_I915_GEM_MMAP,
1296 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1297 __FILE__, __LINE__, bo_gem->gem_handle,
1298 bo_gem->name, strerror(errno));
1299 if (--bo_gem->map_count == 0)
1300 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1301 pthread_mutex_unlock(&bufmgr_gem->lock);
1304 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
1305 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1307 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1308 bo_gem->mem_virtual);
1309 bo->virtual = bo_gem->mem_virtual;
1311 VG_CLEAR(set_domain);
1312 set_domain.handle = bo_gem->gem_handle;
1313 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1315 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1317 set_domain.write_domain = 0;
1318 ret = drmIoctl(bufmgr_gem->fd,
1319 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1322 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1323 __FILE__, __LINE__, bo_gem->gem_handle,
1328 bo_gem->mapped_cpu_write = true;
1330 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1331 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->mem_virtual, bo->size));
1332 pthread_mutex_unlock(&bufmgr_gem->lock);
1338 map_gtt(drm_intel_bo *bo)
1340 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1341 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1344 if (bo_gem->is_userptr)
1347 if (bo_gem->map_count++ == 0)
1348 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1350 /* Get a mapping of the buffer if we haven't before. */
1351 if (bo_gem->gtt_virtual == NULL) {
1352 struct drm_i915_gem_mmap_gtt mmap_arg;
1354 DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n",
1355 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1358 mmap_arg.handle = bo_gem->gem_handle;
1360 /* Get the fake offset back... */
1361 ret = drmIoctl(bufmgr_gem->fd,
1362 DRM_IOCTL_I915_GEM_MMAP_GTT,
1366 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1368 bo_gem->gem_handle, bo_gem->name,
1370 if (--bo_gem->map_count == 0)
1371 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1376 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1377 MAP_SHARED, bufmgr_gem->fd,
1379 if (bo_gem->gtt_virtual == MAP_FAILED) {
1380 bo_gem->gtt_virtual = NULL;
1382 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1384 bo_gem->gem_handle, bo_gem->name,
1386 if (--bo_gem->map_count == 0)
1387 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1392 bo->virtual = bo_gem->gtt_virtual;
1394 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1395 bo_gem->gtt_virtual);
1401 drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1403 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1404 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1405 struct drm_i915_gem_set_domain set_domain;
1408 pthread_mutex_lock(&bufmgr_gem->lock);
1412 pthread_mutex_unlock(&bufmgr_gem->lock);
1416 /* Now move it to the GTT domain so that the GPU and CPU
1417 * caches are flushed and the GPU isn't actively using the
1420 * The pagefault handler does this domain change for us when
1421 * it has unbound the BO from the GTT, but it's up to us to
1422 * tell it when we're about to use things if we had done
1423 * rendering and it still happens to be bound to the GTT.
1425 VG_CLEAR(set_domain);
1426 set_domain.handle = bo_gem->gem_handle;
1427 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1428 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1429 ret = drmIoctl(bufmgr_gem->fd,
1430 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1433 DBG("%s:%d: Error setting domain %d: %s\n",
1434 __FILE__, __LINE__, bo_gem->gem_handle,
1438 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1439 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1440 pthread_mutex_unlock(&bufmgr_gem->lock);
1446 * Performs a mapping of the buffer object like the normal GTT
1447 * mapping, but avoids waiting for the GPU to be done reading from or
1448 * rendering to the buffer.
1450 * This is used in the implementation of GL_ARB_map_buffer_range: The
1451 * user asks to create a buffer, then does a mapping, fills some
1452 * space, runs a drawing command, then asks to map it again without
1453 * synchronizing because it guarantees that it won't write over the
1454 * data that the GPU is busy using (or, more specifically, that if it
1455 * does write over the data, it acknowledges that rendering is
1460 drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
1462 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1463 #ifdef HAVE_VALGRIND
1464 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1468 /* If the CPU cache isn't coherent with the GTT, then use a
1469 * regular synchronized mapping. The problem is that we don't
1470 * track where the buffer was last used on the CPU side in
1471 * terms of drm_intel_bo_map vs drm_intel_gem_bo_map_gtt, so
1472 * we would potentially corrupt the buffer even when the user
1473 * does reasonable things.
1475 if (!bufmgr_gem->has_llc)
1476 return drm_intel_gem_bo_map_gtt(bo);
1478 pthread_mutex_lock(&bufmgr_gem->lock);
1482 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1483 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1486 pthread_mutex_unlock(&bufmgr_gem->lock);
1491 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1493 drm_intel_bufmgr_gem *bufmgr_gem;
1494 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1500 if (bo_gem->is_userptr)
1503 bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1505 pthread_mutex_lock(&bufmgr_gem->lock);
1507 if (bo_gem->map_count <= 0) {
1508 DBG("attempted to unmap an unmapped bo\n");
1509 pthread_mutex_unlock(&bufmgr_gem->lock);
1510 /* Preserve the old behaviour of just treating this as a
1511 * no-op rather than reporting the error.
1516 if (bo_gem->mapped_cpu_write) {
1517 struct drm_i915_gem_sw_finish sw_finish;
1519 /* Cause a flush to happen if the buffer's pinned for
1520 * scanout, so the results show up in a timely manner.
1521 * Unlike GTT set domains, this only does work if the
1522 * buffer should be scanout-related.
1524 VG_CLEAR(sw_finish);
1525 sw_finish.handle = bo_gem->gem_handle;
1526 ret = drmIoctl(bufmgr_gem->fd,
1527 DRM_IOCTL_I915_GEM_SW_FINISH,
1529 ret = ret == -1 ? -errno : 0;
1531 bo_gem->mapped_cpu_write = false;
1534 /* We need to unmap after every innovation as we cannot track
1535 * an open vma for every bo as that will exhaasut the system
1536 * limits and cause later failures.
1538 if (--bo_gem->map_count == 0) {
1539 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1540 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1543 pthread_mutex_unlock(&bufmgr_gem->lock);
1549 drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1551 return drm_intel_gem_bo_unmap(bo);
1555 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1556 unsigned long size, const void *data)
1558 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1559 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1560 struct drm_i915_gem_pwrite pwrite;
1563 if (bo_gem->is_userptr)
1567 pwrite.handle = bo_gem->gem_handle;
1568 pwrite.offset = offset;
1570 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1571 ret = drmIoctl(bufmgr_gem->fd,
1572 DRM_IOCTL_I915_GEM_PWRITE,
1576 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1577 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1578 (int)size, strerror(errno));
1585 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1587 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1588 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1591 VG_CLEAR(get_pipe_from_crtc_id);
1592 get_pipe_from_crtc_id.crtc_id = crtc_id;
1593 ret = drmIoctl(bufmgr_gem->fd,
1594 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1595 &get_pipe_from_crtc_id);
1597 /* We return -1 here to signal that we don't
1598 * know which pipe is associated with this crtc.
1599 * This lets the caller know that this information
1600 * isn't available; using the wrong pipe for
1601 * vblank waiting can cause the chipset to lock up
1606 return get_pipe_from_crtc_id.pipe;
1610 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1611 unsigned long size, void *data)
1613 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1614 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1615 struct drm_i915_gem_pread pread;
1618 if (bo_gem->is_userptr)
1622 pread.handle = bo_gem->gem_handle;
1623 pread.offset = offset;
1625 pread.data_ptr = (uint64_t) (uintptr_t) data;
1626 ret = drmIoctl(bufmgr_gem->fd,
1627 DRM_IOCTL_I915_GEM_PREAD,
1631 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1632 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1633 (int)size, strerror(errno));
1639 /** Waits for all GPU rendering with the object to have completed. */
1641 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1643 drm_intel_gem_bo_start_gtt_access(bo, 1);
1647 * Waits on a BO for the given amount of time.
1649 * @bo: buffer object to wait for
1650 * @timeout_ns: amount of time to wait in nanoseconds.
1651 * If value is less than 0, an infinite wait will occur.
1653 * Returns 0 if the wait was successful ie. the last batch referencing the
1654 * object has completed within the allotted time. Otherwise some negative return
1655 * value describes the error. Of particular interest is -ETIME when the wait has
1656 * failed to yield the desired result.
1658 * Similar to drm_intel_gem_bo_wait_rendering except a timeout parameter allows
1659 * the operation to give up after a certain amount of time. Another subtle
1660 * difference is the internal locking semantics are different (this variant does
1661 * not hold the lock for the duration of the wait). This makes the wait subject
1662 * to a larger userspace race window.
1664 * The implementation shall wait until the object is no longer actively
1665 * referenced within a batch buffer at the time of the call. The wait will
1666 * not guarantee that the buffer is re-issued via another thread, or an flinked
1667 * handle. Userspace must make sure this race does not occur if such precision
1671 drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
1673 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1674 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1675 struct drm_i915_gem_wait wait;
1678 if (!bufmgr_gem->has_wait_timeout) {
1679 DBG("%s:%d: Timed wait is not supported. Falling back to "
1680 "infinite wait\n", __FILE__, __LINE__);
1682 drm_intel_gem_bo_wait_rendering(bo);
1685 return drm_intel_gem_bo_busy(bo) ? -ETIME : 0;
1689 wait.bo_handle = bo_gem->gem_handle;
1690 wait.timeout_ns = timeout_ns;
1692 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_WAIT, &wait);
1700 * Sets the object to the GTT read and possibly write domain, used by the X
1701 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1703 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1704 * can do tiled pixmaps this way.
1707 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1709 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1710 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1711 struct drm_i915_gem_set_domain set_domain;
1714 VG_CLEAR(set_domain);
1715 set_domain.handle = bo_gem->gem_handle;
1716 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1717 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1718 ret = drmIoctl(bufmgr_gem->fd,
1719 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1722 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1723 __FILE__, __LINE__, bo_gem->gem_handle,
1724 set_domain.read_domains, set_domain.write_domain,
1730 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1732 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1735 free(bufmgr_gem->exec2_objects);
1736 free(bufmgr_gem->exec_objects);
1737 free(bufmgr_gem->exec_bos);
1738 free(bufmgr_gem->aub_filename);
1740 pthread_mutex_destroy(&bufmgr_gem->lock);
1742 /* Free any cached buffer objects we were going to reuse */
1743 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1744 struct drm_intel_gem_bo_bucket *bucket =
1745 &bufmgr_gem->cache_bucket[i];
1746 drm_intel_bo_gem *bo_gem;
1748 while (!DRMLISTEMPTY(&bucket->head)) {
1749 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1750 bucket->head.next, head);
1751 DRMLISTDEL(&bo_gem->head);
1753 drm_intel_gem_bo_free(&bo_gem->bo);
1761 * Adds the target buffer to the validation list and adds the relocation
1762 * to the reloc_buffer's relocation list.
1764 * The relocation entry at the given offset must already contain the
1765 * precomputed relocation value, because the kernel will optimize out
1766 * the relocation entry write when the buffer hasn't moved from the
1767 * last known offset in target_bo.
1770 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1771 drm_intel_bo *target_bo, uint32_t target_offset,
1772 uint32_t read_domains, uint32_t write_domain,
1775 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1776 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1777 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1778 bool fenced_command;
1780 if (bo_gem->has_error)
1783 if (target_bo_gem->has_error) {
1784 bo_gem->has_error = true;
1788 /* We never use HW fences for rendering on 965+ */
1789 if (bufmgr_gem->gen >= 4)
1792 fenced_command = need_fence;
1793 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1796 /* Create a new relocation list if needed */
1797 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1800 /* Check overflow */
1801 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1804 assert(offset <= bo->size - 4);
1805 assert((write_domain & (write_domain - 1)) == 0);
1807 /* Make sure that we're not adding a reloc to something whose size has
1808 * already been accounted for.
1810 assert(!bo_gem->used_as_reloc_target);
1811 if (target_bo_gem != bo_gem) {
1812 target_bo_gem->used_as_reloc_target = true;
1813 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1815 /* An object needing a fence is a tiled buffer, so it won't have
1816 * relocs to other buffers.
1819 target_bo_gem->reloc_tree_fences = 1;
1820 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1822 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1823 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1824 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1825 target_bo_gem->gem_handle;
1826 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1827 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1828 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset64;
1830 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1831 if (target_bo != bo)
1832 drm_intel_gem_bo_reference(target_bo);
1834 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1835 DRM_INTEL_RELOC_FENCE;
1837 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1839 bo_gem->reloc_count++;
1845 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1846 drm_intel_bo *target_bo, uint32_t target_offset,
1847 uint32_t read_domains, uint32_t write_domain)
1849 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1851 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1852 read_domains, write_domain,
1853 !bufmgr_gem->fenced_relocs);
1857 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1858 drm_intel_bo *target_bo,
1859 uint32_t target_offset,
1860 uint32_t read_domains, uint32_t write_domain)
1862 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1863 read_domains, write_domain, true);
1867 drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
1869 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1871 return bo_gem->reloc_count;
1875 * Removes existing relocation entries in the BO after "start".
1877 * This allows a user to avoid a two-step process for state setup with
1878 * counting up all the buffer objects and doing a
1879 * drm_intel_bufmgr_check_aperture_space() before emitting any of the
1880 * relocations for the state setup. Instead, save the state of the
1881 * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the
1882 * state, and then check if it still fits in the aperture.
1884 * Any further drm_intel_bufmgr_check_aperture_space() queries
1885 * involving this buffer in the tree are undefined after this call.
1888 drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
1890 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1891 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1893 struct timespec time;
1895 clock_gettime(CLOCK_MONOTONIC, &time);
1897 assert(bo_gem->reloc_count >= start);
1899 /* Unreference the cleared target buffers */
1900 pthread_mutex_lock(&bufmgr_gem->lock);
1902 for (i = start; i < bo_gem->reloc_count; i++) {
1903 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) bo_gem->reloc_target_info[i].bo;
1904 if (&target_bo_gem->bo != bo) {
1905 bo_gem->reloc_tree_fences -= target_bo_gem->reloc_tree_fences;
1906 drm_intel_gem_bo_unreference_locked_timed(&target_bo_gem->bo,
1910 bo_gem->reloc_count = start;
1912 pthread_mutex_unlock(&bufmgr_gem->lock);
1917 * Walk the tree of relocations rooted at BO and accumulate the list of
1918 * validations to be performed and update the relocation buffers with
1919 * index values into the validation list.
1922 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1924 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1927 if (bo_gem->relocs == NULL)
1930 for (i = 0; i < bo_gem->reloc_count; i++) {
1931 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1933 if (target_bo == bo)
1936 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1938 /* Continue walking the tree depth-first. */
1939 drm_intel_gem_bo_process_reloc(target_bo);
1941 /* Add the target to the validate list */
1942 drm_intel_add_validate_buffer(target_bo);
1947 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1949 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1952 if (bo_gem->relocs == NULL)
1955 for (i = 0; i < bo_gem->reloc_count; i++) {
1956 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1959 if (target_bo == bo)
1962 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1964 /* Continue walking the tree depth-first. */
1965 drm_intel_gem_bo_process_reloc2(target_bo);
1967 need_fence = (bo_gem->reloc_target_info[i].flags &
1968 DRM_INTEL_RELOC_FENCE);
1970 /* Add the target to the validate list */
1971 drm_intel_add_validate_buffer2(target_bo, need_fence);
1977 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1981 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1982 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1983 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1985 /* Update the buffer offset */
1986 if (bufmgr_gem->exec_objects[i].offset != bo->offset64) {
1987 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1988 bo_gem->gem_handle, bo_gem->name, bo->offset64,
1989 (unsigned long long)bufmgr_gem->exec_objects[i].
1991 bo->offset64 = bufmgr_gem->exec_objects[i].offset;
1992 bo->offset = bufmgr_gem->exec_objects[i].offset;
1998 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
2002 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2003 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2004 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2006 /* Update the buffer offset */
2007 if (bufmgr_gem->exec2_objects[i].offset != bo->offset64) {
2008 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
2009 bo_gem->gem_handle, bo_gem->name, bo->offset64,
2010 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
2011 bo->offset64 = bufmgr_gem->exec2_objects[i].offset;
2012 bo->offset = bufmgr_gem->exec2_objects[i].offset;
2018 aub_out(drm_intel_bufmgr_gem *bufmgr_gem, uint32_t data)
2020 fwrite(&data, 1, 4, bufmgr_gem->aub_file);
2024 aub_out_data(drm_intel_bufmgr_gem *bufmgr_gem, void *data, size_t size)
2026 fwrite(data, 1, size, bufmgr_gem->aub_file);
2030 aub_write_bo_data(drm_intel_bo *bo, uint32_t offset, uint32_t size)
2032 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2033 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2037 data = malloc(bo->size);
2038 drm_intel_bo_get_subdata(bo, offset, size, data);
2040 /* Easy mode: write out bo with no relocations */
2041 if (!bo_gem->reloc_count) {
2042 aub_out_data(bufmgr_gem, data, size);
2047 /* Otherwise, handle the relocations while writing. */
2048 for (i = 0; i < size / 4; i++) {
2050 for (r = 0; r < bo_gem->reloc_count; r++) {
2051 struct drm_i915_gem_relocation_entry *reloc;
2052 drm_intel_reloc_target *info;
2054 reloc = &bo_gem->relocs[r];
2055 info = &bo_gem->reloc_target_info[r];
2057 if (reloc->offset == offset + i * 4) {
2058 drm_intel_bo_gem *target_gem;
2061 target_gem = (drm_intel_bo_gem *)info->bo;
2064 val += target_gem->aub_offset;
2066 aub_out(bufmgr_gem, val);
2071 if (r == bo_gem->reloc_count) {
2072 /* no relocation, just the data */
2073 aub_out(bufmgr_gem, data[i]);
2081 aub_bo_get_address(drm_intel_bo *bo)
2083 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2084 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2086 /* Give the object a graphics address in the AUB file. We
2087 * don't just use the GEM object address because we do AUB
2088 * dumping before execution -- we want to successfully log
2089 * when the hardware might hang, and we might even want to aub
2090 * capture for a driver trying to execute on a different
2091 * generation of hardware by disabling the actual kernel exec
2094 bo_gem->aub_offset = bufmgr_gem->aub_offset;
2095 bufmgr_gem->aub_offset += bo->size;
2096 /* XXX: Handle aperture overflow. */
2097 assert(bufmgr_gem->aub_offset < 256 * 1024 * 1024);
2101 aub_write_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype,
2102 uint32_t offset, uint32_t size)
2104 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2105 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2108 CMD_AUB_TRACE_HEADER_BLOCK |
2109 ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
2111 AUB_TRACE_MEMTYPE_GTT | type | AUB_TRACE_OP_DATA_WRITE);
2112 aub_out(bufmgr_gem, subtype);
2113 aub_out(bufmgr_gem, bo_gem->aub_offset + offset);
2114 aub_out(bufmgr_gem, size);
2115 if (bufmgr_gem->gen >= 8)
2116 aub_out(bufmgr_gem, 0);
2117 aub_write_bo_data(bo, offset, size);
2121 * Break up large objects into multiple writes. Otherwise a 128kb VBO
2122 * would overflow the 16 bits of size field in the packet header and
2123 * everything goes badly after that.
2126 aub_write_large_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype,
2127 uint32_t offset, uint32_t size)
2129 uint32_t block_size;
2130 uint32_t sub_offset;
2132 for (sub_offset = 0; sub_offset < size; sub_offset += block_size) {
2133 block_size = size - sub_offset;
2135 if (block_size > 8 * 4096)
2136 block_size = 8 * 4096;
2138 aub_write_trace_block(bo, type, subtype, offset + sub_offset,
2144 aub_write_bo(drm_intel_bo *bo)
2146 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2147 uint32_t offset = 0;
2150 aub_bo_get_address(bo);
2152 /* Write out each annotated section separately. */
2153 for (i = 0; i < bo_gem->aub_annotation_count; ++i) {
2154 drm_intel_aub_annotation *annotation =
2155 &bo_gem->aub_annotations[i];
2156 uint32_t ending_offset = annotation->ending_offset;
2157 if (ending_offset > bo->size)
2158 ending_offset = bo->size;
2159 if (ending_offset > offset) {
2160 aub_write_large_trace_block(bo, annotation->type,
2161 annotation->subtype,
2163 ending_offset - offset);
2164 offset = ending_offset;
2168 /* Write out any remaining unannotated data */
2169 if (offset < bo->size) {
2170 aub_write_large_trace_block(bo, AUB_TRACE_TYPE_NOTYPE, 0,
2171 offset, bo->size - offset);
2176 * Make a ringbuffer on fly and dump it
2179 aub_build_dump_ringbuffer(drm_intel_bufmgr_gem *bufmgr_gem,
2180 uint32_t batch_buffer, int ring_flag)
2182 uint32_t ringbuffer[4096];
2183 int ring = AUB_TRACE_TYPE_RING_PRB0; /* The default ring */
2186 if (ring_flag == I915_EXEC_BSD)
2187 ring = AUB_TRACE_TYPE_RING_PRB1;
2188 else if (ring_flag == I915_EXEC_BLT)
2189 ring = AUB_TRACE_TYPE_RING_PRB2;
2191 /* Make a ring buffer to execute our batchbuffer. */
2192 memset(ringbuffer, 0, sizeof(ringbuffer));
2193 if (bufmgr_gem->gen >= 8) {
2194 ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START | (3 - 2);
2195 ringbuffer[ring_count++] = batch_buffer;
2196 ringbuffer[ring_count++] = 0;
2198 ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START;
2199 ringbuffer[ring_count++] = batch_buffer;
2202 /* Write out the ring. This appears to trigger execution of
2203 * the ring in the simulator.
2206 CMD_AUB_TRACE_HEADER_BLOCK |
2207 ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
2209 AUB_TRACE_MEMTYPE_GTT | ring | AUB_TRACE_OP_COMMAND_WRITE);
2210 aub_out(bufmgr_gem, 0); /* general/surface subtype */
2211 aub_out(bufmgr_gem, bufmgr_gem->aub_offset);
2212 aub_out(bufmgr_gem, ring_count * 4);
2213 if (bufmgr_gem->gen >= 8)
2214 aub_out(bufmgr_gem, 0);
2216 /* FIXME: Need some flush operations here? */
2217 aub_out_data(bufmgr_gem, ringbuffer, ring_count * 4);
2219 /* Update offset pointer */
2220 bufmgr_gem->aub_offset += 4096;
2224 drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
2225 int x1, int y1, int width, int height,
2226 enum aub_dump_bmp_format format,
2227 int pitch, int offset)
2229 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2230 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2234 case AUB_DUMP_BMP_FORMAT_8BIT:
2237 case AUB_DUMP_BMP_FORMAT_ARGB_4444:
2240 case AUB_DUMP_BMP_FORMAT_ARGB_0888:
2241 case AUB_DUMP_BMP_FORMAT_ARGB_8888:
2245 printf("Unknown AUB dump format %d\n", format);
2249 if (!bufmgr_gem->aub_file)
2252 aub_out(bufmgr_gem, CMD_AUB_DUMP_BMP | 4);
2253 aub_out(bufmgr_gem, (y1 << 16) | x1);
2258 aub_out(bufmgr_gem, (height << 16) | width);
2259 aub_out(bufmgr_gem, bo_gem->aub_offset + offset);
2261 ((bo_gem->tiling_mode != I915_TILING_NONE) ? (1 << 2) : 0) |
2262 ((bo_gem->tiling_mode == I915_TILING_Y) ? (1 << 3) : 0));
2266 aub_exec(drm_intel_bo *bo, int ring_flag, int used)
2268 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2269 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2271 bool batch_buffer_needs_annotations;
2273 if (!bufmgr_gem->aub_file)
2276 /* If batch buffer is not annotated, annotate it the best we
2279 batch_buffer_needs_annotations = bo_gem->aub_annotation_count == 0;
2280 if (batch_buffer_needs_annotations) {
2281 drm_intel_aub_annotation annotations[2] = {
2282 { AUB_TRACE_TYPE_BATCH, 0, used },
2283 { AUB_TRACE_TYPE_NOTYPE, 0, bo->size }
2285 drm_intel_bufmgr_gem_set_aub_annotations(bo, annotations, 2);
2288 /* Write out all buffers to AUB memory */
2289 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2290 aub_write_bo(bufmgr_gem->exec_bos[i]);
2293 /* Remove any annotations we added */
2294 if (batch_buffer_needs_annotations)
2295 drm_intel_bufmgr_gem_set_aub_annotations(bo, NULL, 0);
2297 /* Dump ring buffer */
2298 aub_build_dump_ringbuffer(bufmgr_gem, bo_gem->aub_offset, ring_flag);
2300 fflush(bufmgr_gem->aub_file);
2303 * One frame has been dumped. So reset the aub_offset for the next frame.
2305 * FIXME: Can we do this?
2307 bufmgr_gem->aub_offset = 0x10000;
2311 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
2312 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
2314 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2315 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2316 struct drm_i915_gem_execbuffer execbuf;
2319 if (bo_gem->has_error)
2322 pthread_mutex_lock(&bufmgr_gem->lock);
2323 /* Update indices and set up the validate list. */
2324 drm_intel_gem_bo_process_reloc(bo);
2326 /* Add the batch buffer to the validation list. There are no
2327 * relocations pointing to it.
2329 drm_intel_add_validate_buffer(bo);
2332 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
2333 execbuf.buffer_count = bufmgr_gem->exec_count;
2334 execbuf.batch_start_offset = 0;
2335 execbuf.batch_len = used;
2336 execbuf.cliprects_ptr = (uintptr_t) cliprects;
2337 execbuf.num_cliprects = num_cliprects;
2341 ret = drmIoctl(bufmgr_gem->fd,
2342 DRM_IOCTL_I915_GEM_EXECBUFFER,
2346 if (errno == ENOSPC) {
2347 DBG("Execbuffer fails to pin. "
2348 "Estimate: %u. Actual: %u. Available: %u\n",
2349 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2352 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2355 (unsigned int)bufmgr_gem->gtt_size);
2358 drm_intel_update_buffer_offsets(bufmgr_gem);
2360 if (bufmgr_gem->bufmgr.debug)
2361 drm_intel_gem_dump_validation_list(bufmgr_gem);
2363 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2364 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2365 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2367 bo_gem->idle = false;
2369 /* Disconnect the buffer from the validate list */
2370 bo_gem->validate_index = -1;
2371 bufmgr_gem->exec_bos[i] = NULL;
2373 bufmgr_gem->exec_count = 0;
2374 pthread_mutex_unlock(&bufmgr_gem->lock);
2380 do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
2381 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2384 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
2385 struct drm_i915_gem_execbuffer2 execbuf;
2389 switch (flags & 0x7) {
2393 if (!bufmgr_gem->has_blt)
2397 if (!bufmgr_gem->has_bsd)
2400 case I915_EXEC_VEBOX:
2401 if (!bufmgr_gem->has_vebox)
2404 case I915_EXEC_RENDER:
2405 case I915_EXEC_DEFAULT:
2409 pthread_mutex_lock(&bufmgr_gem->lock);
2410 /* Update indices and set up the validate list. */
2411 drm_intel_gem_bo_process_reloc2(bo);
2413 /* Add the batch buffer to the validation list. There are no relocations
2416 drm_intel_add_validate_buffer2(bo, 0);
2419 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
2420 execbuf.buffer_count = bufmgr_gem->exec_count;
2421 execbuf.batch_start_offset = 0;
2422 execbuf.batch_len = used;
2423 execbuf.cliprects_ptr = (uintptr_t)cliprects;
2424 execbuf.num_cliprects = num_cliprects;
2427 execbuf.flags = flags;
2429 i915_execbuffer2_set_context_id(execbuf, 0);
2431 i915_execbuffer2_set_context_id(execbuf, ctx->ctx_id);
2434 aub_exec(bo, flags, used);
2436 if (bufmgr_gem->no_exec)
2437 goto skip_execution;
2439 ret = drmIoctl(bufmgr_gem->fd,
2440 DRM_IOCTL_I915_GEM_EXECBUFFER2,
2444 if (ret == -ENOSPC) {
2445 DBG("Execbuffer fails to pin. "
2446 "Estimate: %u. Actual: %u. Available: %u\n",
2447 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2448 bufmgr_gem->exec_count),
2449 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2450 bufmgr_gem->exec_count),
2451 (unsigned int) bufmgr_gem->gtt_size);
2454 drm_intel_update_buffer_offsets2(bufmgr_gem);
2457 if (bufmgr_gem->bufmgr.debug)
2458 drm_intel_gem_dump_validation_list(bufmgr_gem);
2460 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2461 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2462 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2464 bo_gem->idle = false;
2466 /* Disconnect the buffer from the validate list */
2467 bo_gem->validate_index = -1;
2468 bufmgr_gem->exec_bos[i] = NULL;
2470 bufmgr_gem->exec_count = 0;
2471 pthread_mutex_unlock(&bufmgr_gem->lock);
2477 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
2478 drm_clip_rect_t *cliprects, int num_cliprects,
2481 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2486 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
2487 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2490 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2495 drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
2496 int used, unsigned int flags)
2498 return do_exec2(bo, used, ctx, NULL, 0, 0, flags);
2502 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
2504 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2505 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2506 struct drm_i915_gem_pin pin;
2510 pin.handle = bo_gem->gem_handle;
2511 pin.alignment = alignment;
2513 ret = drmIoctl(bufmgr_gem->fd,
2514 DRM_IOCTL_I915_GEM_PIN,
2519 bo->offset64 = pin.offset;
2520 bo->offset = pin.offset;
2525 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
2527 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2528 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2529 struct drm_i915_gem_unpin unpin;
2533 unpin.handle = bo_gem->gem_handle;
2535 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
2543 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
2544 uint32_t tiling_mode,
2547 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2548 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2549 struct drm_i915_gem_set_tiling set_tiling;
2552 if (bo_gem->global_name == 0 &&
2553 tiling_mode == bo_gem->tiling_mode &&
2554 stride == bo_gem->stride)
2557 memset(&set_tiling, 0, sizeof(set_tiling));
2559 /* set_tiling is slightly broken and overwrites the
2560 * input on the error path, so we have to open code
2563 set_tiling.handle = bo_gem->gem_handle;
2564 set_tiling.tiling_mode = tiling_mode;
2565 set_tiling.stride = stride;
2567 ret = ioctl(bufmgr_gem->fd,
2568 DRM_IOCTL_I915_GEM_SET_TILING,
2570 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
2574 bo_gem->tiling_mode = set_tiling.tiling_mode;
2575 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
2576 bo_gem->stride = set_tiling.stride;
2581 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2584 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2585 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2588 /* Tiling with userptr surfaces is not supported
2589 * on all hardware so refuse it for time being.
2591 if (bo_gem->is_userptr)
2594 /* Linear buffers have no stride. By ensuring that we only ever use
2595 * stride 0 with linear buffers, we simplify our code.
2597 if (*tiling_mode == I915_TILING_NONE)
2600 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
2602 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
2604 *tiling_mode = bo_gem->tiling_mode;
2609 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2610 uint32_t * swizzle_mode)
2612 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2614 *tiling_mode = bo_gem->tiling_mode;
2615 *swizzle_mode = bo_gem->swizzle_mode;
2619 drm_public drm_intel_bo *
2620 drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int size)
2622 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2625 drm_intel_bo_gem *bo_gem;
2626 struct drm_i915_gem_get_tiling get_tiling;
2627 drmMMListHead *list;
2629 ret = drmPrimeFDToHandle(bufmgr_gem->fd, prime_fd, &handle);
2632 * See if the kernel has already returned this buffer to us. Just as
2633 * for named buffers, we must not create two bo's pointing at the same
2636 for (list = bufmgr_gem->named.next;
2637 list != &bufmgr_gem->named;
2638 list = list->next) {
2639 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
2640 if (bo_gem->gem_handle == handle) {
2641 drm_intel_gem_bo_reference(&bo_gem->bo);
2647 fprintf(stderr,"ret is %d %d\n", ret, errno);
2651 bo_gem = calloc(1, sizeof(*bo_gem));
2655 /* Determine size of bo. The fd-to-handle ioctl really should
2656 * return the size, but it doesn't. If we have kernel 3.12 or
2657 * later, we can lseek on the prime fd to get the size. Older
2658 * kernels will just fail, in which case we fall back to the
2659 * provided (estimated or guess size). */
2660 ret = lseek(prime_fd, 0, SEEK_END);
2662 bo_gem->bo.size = ret;
2664 bo_gem->bo.size = size;
2666 bo_gem->bo.handle = handle;
2667 bo_gem->bo.bufmgr = bufmgr;
2669 bo_gem->gem_handle = handle;
2671 atomic_set(&bo_gem->refcount, 1);
2673 bo_gem->name = "prime";
2674 bo_gem->validate_index = -1;
2675 bo_gem->reloc_tree_fences = 0;
2676 bo_gem->used_as_reloc_target = false;
2677 bo_gem->has_error = false;
2678 bo_gem->reusable = false;
2680 DRMINITLISTHEAD(&bo_gem->vma_list);
2681 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2683 VG_CLEAR(get_tiling);
2684 get_tiling.handle = bo_gem->gem_handle;
2685 ret = drmIoctl(bufmgr_gem->fd,
2686 DRM_IOCTL_I915_GEM_GET_TILING,
2689 drm_intel_gem_bo_unreference(&bo_gem->bo);
2692 bo_gem->tiling_mode = get_tiling.tiling_mode;
2693 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
2694 /* XXX stride is unknown */
2695 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
2701 drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd)
2703 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2704 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2706 if (DRMLISTEMPTY(&bo_gem->name_list))
2707 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2709 if (drmPrimeHandleToFD(bufmgr_gem->fd, bo_gem->gem_handle,
2710 DRM_CLOEXEC, prime_fd) != 0)
2713 bo_gem->reusable = false;
2719 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
2721 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2722 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2725 if (!bo_gem->global_name) {
2726 struct drm_gem_flink flink;
2729 flink.handle = bo_gem->gem_handle;
2731 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
2735 bo_gem->global_name = flink.name;
2736 bo_gem->reusable = false;
2738 if (DRMLISTEMPTY(&bo_gem->name_list))
2739 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2742 *name = bo_gem->global_name;
2747 * Enables unlimited caching of buffer objects for reuse.
2749 * This is potentially very memory expensive, as the cache at each bucket
2750 * size is only bounded by how many buffers of that size we've managed to have
2751 * in flight at once.
2754 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
2756 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2758 bufmgr_gem->bo_reuse = true;
2762 * Enable use of fenced reloc type.
2764 * New code should enable this to avoid unnecessary fence register
2765 * allocation. If this option is not enabled, all relocs will have fence
2766 * register allocated.
2769 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
2771 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2773 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
2774 bufmgr_gem->fenced_relocs = true;
2778 * Return the additional aperture space required by the tree of buffer objects
2782 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
2784 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2788 if (bo == NULL || bo_gem->included_in_check_aperture)
2792 bo_gem->included_in_check_aperture = true;
2794 for (i = 0; i < bo_gem->reloc_count; i++)
2796 drm_intel_gem_bo_get_aperture_space(bo_gem->
2797 reloc_target_info[i].bo);
2803 * Count the number of buffers in this list that need a fence reg
2805 * If the count is greater than the number of available regs, we'll have
2806 * to ask the caller to resubmit a batch with fewer tiled buffers.
2808 * This function over-counts if the same buffer is used multiple times.
2811 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
2814 unsigned int total = 0;
2816 for (i = 0; i < count; i++) {
2817 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2822 total += bo_gem->reloc_tree_fences;
2828 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
2829 * for the next drm_intel_bufmgr_check_aperture_space() call.
2832 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
2834 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2837 if (bo == NULL || !bo_gem->included_in_check_aperture)
2840 bo_gem->included_in_check_aperture = false;
2842 for (i = 0; i < bo_gem->reloc_count; i++)
2843 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
2844 reloc_target_info[i].bo);
2848 * Return a conservative estimate for the amount of aperture required
2849 * for a collection of buffers. This may double-count some buffers.
2852 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
2855 unsigned int total = 0;
2857 for (i = 0; i < count; i++) {
2858 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2860 total += bo_gem->reloc_tree_size;
2866 * Return the amount of aperture needed for a collection of buffers.
2867 * This avoids double counting any buffers, at the cost of looking
2868 * at every buffer in the set.
2871 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
2874 unsigned int total = 0;
2876 for (i = 0; i < count; i++) {
2877 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
2878 /* For the first buffer object in the array, we get an
2879 * accurate count back for its reloc_tree size (since nothing
2880 * had been flagged as being counted yet). We can save that
2881 * value out as a more conservative reloc_tree_size that
2882 * avoids double-counting target buffers. Since the first
2883 * buffer happens to usually be the batch buffer in our
2884 * callers, this can pull us back from doing the tree
2885 * walk on every new batch emit.
2888 drm_intel_bo_gem *bo_gem =
2889 (drm_intel_bo_gem *) bo_array[i];
2890 bo_gem->reloc_tree_size = total;
2894 for (i = 0; i < count; i++)
2895 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
2900 * Return -1 if the batchbuffer should be flushed before attempting to
2901 * emit rendering referencing the buffers pointed to by bo_array.
2903 * This is required because if we try to emit a batchbuffer with relocations
2904 * to a tree of buffers that won't simultaneously fit in the aperture,
2905 * the rendering will return an error at a point where the software is not
2906 * prepared to recover from it.
2908 * However, we also want to emit the batchbuffer significantly before we reach
2909 * the limit, as a series of batchbuffers each of which references buffers
2910 * covering almost all of the aperture means that at each emit we end up
2911 * waiting to evict a buffer from the last rendering, and we get synchronous
2912 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
2913 * get better parallelism.
2916 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
2918 drm_intel_bufmgr_gem *bufmgr_gem =
2919 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
2920 unsigned int total = 0;
2921 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
2924 /* Check for fence reg constraints if necessary */
2925 if (bufmgr_gem->available_fences) {
2926 total_fences = drm_intel_gem_total_fences(bo_array, count);
2927 if (total_fences > bufmgr_gem->available_fences)
2931 total = drm_intel_gem_estimate_batch_space(bo_array, count);
2933 if (total > threshold)
2934 total = drm_intel_gem_compute_batch_space(bo_array, count);
2936 if (total > threshold) {
2937 DBG("check_space: overflowed available aperture, "
2939 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
2942 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
2943 (int)bufmgr_gem->gtt_size / 1024);
2949 * Disable buffer reuse for objects which are shared with the kernel
2950 * as scanout buffers
2953 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
2955 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2957 bo_gem->reusable = false;
2962 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
2964 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2966 return bo_gem->reusable;
2970 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2972 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2975 for (i = 0; i < bo_gem->reloc_count; i++) {
2976 if (bo_gem->reloc_target_info[i].bo == target_bo)
2978 if (bo == bo_gem->reloc_target_info[i].bo)
2980 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2988 /** Return true if target_bo is referenced by bo's relocation tree. */
2990 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2992 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2994 if (bo == NULL || target_bo == NULL)
2996 if (target_bo_gem->used_as_reloc_target)
2997 return _drm_intel_gem_bo_references(bo, target_bo);
3002 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
3004 unsigned int i = bufmgr_gem->num_buckets;
3006 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
3008 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
3009 bufmgr_gem->cache_bucket[i].size = size;
3010 bufmgr_gem->num_buckets++;
3014 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
3016 unsigned long size, cache_max_size = 64 * 1024 * 1024;
3018 /* OK, so power of two buckets was too wasteful of memory.
3019 * Give 3 other sizes between each power of two, to hopefully
3020 * cover things accurately enough. (The alternative is
3021 * probably to just go for exact matching of sizes, and assume
3022 * that for things like composited window resize the tiled
3023 * width/height alignment and rounding of sizes to pages will
3024 * get us useful cache hit rates anyway)
3026 add_bucket(bufmgr_gem, 4096);
3027 add_bucket(bufmgr_gem, 4096 * 2);
3028 add_bucket(bufmgr_gem, 4096 * 3);
3030 /* Initialize the linked lists for BO reuse cache. */
3031 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
3032 add_bucket(bufmgr_gem, size);
3034 add_bucket(bufmgr_gem, size + size * 1 / 4);
3035 add_bucket(bufmgr_gem, size + size * 2 / 4);
3036 add_bucket(bufmgr_gem, size + size * 3 / 4);
3041 drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit)
3043 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3045 bufmgr_gem->vma_max = limit;
3047 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
3051 * Get the PCI ID for the device. This can be overridden by setting the
3052 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
3055 get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem)
3057 char *devid_override;
3060 drm_i915_getparam_t gp;
3062 if (geteuid() == getuid()) {
3063 devid_override = getenv("INTEL_DEVID_OVERRIDE");
3064 if (devid_override) {
3065 bufmgr_gem->no_exec = true;
3066 return strtod(devid_override, NULL);
3072 gp.param = I915_PARAM_CHIPSET_ID;
3074 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3076 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
3077 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
3083 drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
3085 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3087 return bufmgr_gem->pci_device;
3091 * Sets the AUB filename.
3093 * This function has to be called before drm_intel_bufmgr_gem_set_aub_dump()
3094 * for it to have any effect.
3097 drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
3098 const char *filename)
3100 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3102 free(bufmgr_gem->aub_filename);
3104 bufmgr_gem->aub_filename = strdup(filename);
3108 * Sets up AUB dumping.
3110 * This is a trace file format that can be used with the simulator.
3111 * Packets are emitted in a format somewhat like GPU command packets.
3112 * You can set up a GTT and upload your objects into the referenced
3113 * space, then send off batchbuffers and get BMPs out the other end.
3116 drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
3118 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3119 int entry = 0x200003;
3121 int gtt_size = 0x10000;
3122 const char *filename;
3125 if (bufmgr_gem->aub_file) {
3126 fclose(bufmgr_gem->aub_file);
3127 bufmgr_gem->aub_file = NULL;
3132 if (geteuid() != getuid())
3135 if (bufmgr_gem->aub_filename)
3136 filename = bufmgr_gem->aub_filename;
3138 filename = "intel.aub";
3139 bufmgr_gem->aub_file = fopen(filename, "w+");
3140 if (!bufmgr_gem->aub_file)
3143 /* Start allocating objects from just after the GTT. */
3144 bufmgr_gem->aub_offset = gtt_size;
3146 /* Start with a (required) version packet. */
3147 aub_out(bufmgr_gem, CMD_AUB_HEADER | (13 - 2));
3149 (4 << AUB_HEADER_MAJOR_SHIFT) |
3150 (0 << AUB_HEADER_MINOR_SHIFT));
3151 for (i = 0; i < 8; i++) {
3152 aub_out(bufmgr_gem, 0); /* app name */
3154 aub_out(bufmgr_gem, 0); /* timestamp */
3155 aub_out(bufmgr_gem, 0); /* timestamp */
3156 aub_out(bufmgr_gem, 0); /* comment len */
3158 /* Set up the GTT. The max we can handle is 256M */
3159 aub_out(bufmgr_gem, CMD_AUB_TRACE_HEADER_BLOCK | ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
3160 aub_out(bufmgr_gem, AUB_TRACE_MEMTYPE_NONLOCAL | 0 | AUB_TRACE_OP_DATA_WRITE);
3161 aub_out(bufmgr_gem, 0); /* subtype */
3162 aub_out(bufmgr_gem, 0); /* offset */
3163 aub_out(bufmgr_gem, gtt_size); /* size */
3164 if (bufmgr_gem->gen >= 8)
3165 aub_out(bufmgr_gem, 0);
3166 for (i = 0x000; i < gtt_size; i += 4, entry += 0x1000) {
3167 aub_out(bufmgr_gem, entry);
3171 drm_public drm_intel_context *
3172 drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
3174 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3175 struct drm_i915_gem_context_create create;
3176 drm_intel_context *context = NULL;
3179 context = calloc(1, sizeof(*context));
3184 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &create);
3186 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n",
3192 context->ctx_id = create.ctx_id;
3193 context->bufmgr = bufmgr;
3199 drm_intel_gem_context_destroy(drm_intel_context *ctx)
3201 drm_intel_bufmgr_gem *bufmgr_gem;
3202 struct drm_i915_gem_context_destroy destroy;
3210 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3211 destroy.ctx_id = ctx->ctx_id;
3212 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY,
3215 fprintf(stderr, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
3222 drm_intel_get_reset_stats(drm_intel_context *ctx,
3223 uint32_t *reset_count,
3227 drm_intel_bufmgr_gem *bufmgr_gem;
3228 struct drm_i915_reset_stats stats;
3234 memset(&stats, 0, sizeof(stats));
3236 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3237 stats.ctx_id = ctx->ctx_id;
3238 ret = drmIoctl(bufmgr_gem->fd,
3239 DRM_IOCTL_I915_GET_RESET_STATS,
3242 if (reset_count != NULL)
3243 *reset_count = stats.reset_count;
3246 *active = stats.batch_active;
3248 if (pending != NULL)
3249 *pending = stats.batch_pending;
3256 drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
3260 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3261 struct drm_i915_reg_read reg_read;
3265 reg_read.offset = offset;
3267 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_REG_READ, ®_read);
3269 *result = reg_read.val;
3275 * Annotate the given bo for use in aub dumping.
3277 * \param annotations is an array of drm_intel_aub_annotation objects
3278 * describing the type of data in various sections of the bo. Each
3279 * element of the array specifies the type and subtype of a section of
3280 * the bo, and the past-the-end offset of that section. The elements
3281 * of \c annotations must be sorted so that ending_offset is
3284 * \param count is the number of elements in the \c annotations array.
3285 * If \c count is zero, then \c annotations will not be dereferenced.
3287 * Annotations are copied into a private data structure, so caller may
3288 * re-use the memory pointed to by \c annotations after the call
3291 * Annotations are stored for the lifetime of the bo; to reset to the
3292 * default state (no annotations), call this function with a \c count
3296 drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
3297 drm_intel_aub_annotation *annotations,
3300 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3301 unsigned size = sizeof(*annotations) * count;
3302 drm_intel_aub_annotation *new_annotations =
3303 count > 0 ? realloc(bo_gem->aub_annotations, size) : NULL;
3304 if (new_annotations == NULL) {
3305 free(bo_gem->aub_annotations);
3306 bo_gem->aub_annotations = NULL;
3307 bo_gem->aub_annotation_count = 0;
3310 memcpy(new_annotations, annotations, size);
3311 bo_gem->aub_annotations = new_annotations;
3312 bo_gem->aub_annotation_count = count;
3315 static pthread_mutex_t bufmgr_list_mutex = PTHREAD_MUTEX_INITIALIZER;
3316 static drmMMListHead bufmgr_list = { &bufmgr_list, &bufmgr_list };
3318 static drm_intel_bufmgr_gem *
3319 drm_intel_bufmgr_gem_find(int fd)
3321 drm_intel_bufmgr_gem *bufmgr_gem;
3323 DRMLISTFOREACHENTRY(bufmgr_gem, &bufmgr_list, managers) {
3324 if (bufmgr_gem->fd == fd) {
3325 atomic_inc(&bufmgr_gem->refcount);
3334 drm_intel_bufmgr_gem_unref(drm_intel_bufmgr *bufmgr)
3336 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3338 if (atomic_add_unless(&bufmgr_gem->refcount, -1, 1)) {
3339 pthread_mutex_lock(&bufmgr_list_mutex);
3341 if (atomic_dec_and_test(&bufmgr_gem->refcount)) {
3342 DRMLISTDEL(&bufmgr_gem->managers);
3343 drm_intel_bufmgr_gem_destroy(bufmgr);
3346 pthread_mutex_unlock(&bufmgr_list_mutex);
3351 has_userptr(drm_intel_bufmgr_gem *bufmgr_gem)
3356 struct drm_i915_gem_userptr userptr;
3357 struct drm_gem_close close_bo;
3359 pgsz = sysconf(_SC_PAGESIZE);
3362 ret = posix_memalign(&ptr, pgsz, pgsz);
3364 DBG("Failed to get a page (%ld) for userptr detection!\n",
3369 memset(&userptr, 0, sizeof(userptr));
3370 userptr.user_ptr = (__u64)(unsigned long)ptr;
3371 userptr.user_size = pgsz;
3374 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_USERPTR, &userptr);
3376 if (errno == ENODEV && userptr.flags == 0) {
3377 userptr.flags = I915_USERPTR_UNSYNCHRONIZED;
3384 close_bo.handle = userptr.handle;
3385 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close_bo);
3389 fprintf(stderr, "Failed to release test userptr object! (%d) "
3390 "i915 kernel driver may not be sane!\n", errno);
3398 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
3399 * and manage map buffer objections.
3401 * \param fd File descriptor of the opened DRM device.
3403 drm_public drm_intel_bufmgr *
3404 drm_intel_bufmgr_gem_init(int fd, int batch_size)
3406 drm_intel_bufmgr_gem *bufmgr_gem;
3407 struct drm_i915_gem_get_aperture aperture;
3408 drm_i915_getparam_t gp;
3412 pthread_mutex_lock(&bufmgr_list_mutex);
3414 bufmgr_gem = drm_intel_bufmgr_gem_find(fd);
3418 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
3419 if (bufmgr_gem == NULL)
3422 bufmgr_gem->fd = fd;
3423 atomic_set(&bufmgr_gem->refcount, 1);
3425 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
3431 ret = drmIoctl(bufmgr_gem->fd,
3432 DRM_IOCTL_I915_GEM_GET_APERTURE,
3436 bufmgr_gem->gtt_size = aperture.aper_available_size;
3438 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
3440 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
3441 fprintf(stderr, "Assuming %dkB available aperture size.\n"
3442 "May lead to reduced performance or incorrect "
3444 (int)bufmgr_gem->gtt_size / 1024);
3447 bufmgr_gem->pci_device = get_pci_device_id(bufmgr_gem);
3449 if (IS_GEN2(bufmgr_gem->pci_device))
3450 bufmgr_gem->gen = 2;
3451 else if (IS_GEN3(bufmgr_gem->pci_device))
3452 bufmgr_gem->gen = 3;
3453 else if (IS_GEN4(bufmgr_gem->pci_device))
3454 bufmgr_gem->gen = 4;
3455 else if (IS_GEN5(bufmgr_gem->pci_device))
3456 bufmgr_gem->gen = 5;
3457 else if (IS_GEN6(bufmgr_gem->pci_device))
3458 bufmgr_gem->gen = 6;
3459 else if (IS_GEN7(bufmgr_gem->pci_device))
3460 bufmgr_gem->gen = 7;
3461 else if (IS_GEN8(bufmgr_gem->pci_device))
3462 bufmgr_gem->gen = 8;
3469 if (IS_GEN3(bufmgr_gem->pci_device) &&
3470 bufmgr_gem->gtt_size > 256*1024*1024) {
3471 /* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
3472 * be used for tiled blits. To simplify the accounting, just
3473 * substract the unmappable part (fixed to 256MB on all known
3474 * gen3 devices) if the kernel advertises it. */
3475 bufmgr_gem->gtt_size -= 256*1024*1024;
3481 gp.param = I915_PARAM_HAS_EXECBUF2;
3482 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3486 gp.param = I915_PARAM_HAS_BSD;
3487 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3488 bufmgr_gem->has_bsd = ret == 0;
3490 gp.param = I915_PARAM_HAS_BLT;
3491 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3492 bufmgr_gem->has_blt = ret == 0;
3494 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
3495 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3496 bufmgr_gem->has_relaxed_fencing = ret == 0;
3498 if (has_userptr(bufmgr_gem))
3499 bufmgr_gem->bufmgr.bo_alloc_userptr =
3500 drm_intel_gem_bo_alloc_userptr;
3502 gp.param = I915_PARAM_HAS_WAIT_TIMEOUT;
3503 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3504 bufmgr_gem->has_wait_timeout = ret == 0;
3506 gp.param = I915_PARAM_HAS_LLC;
3507 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3509 /* Kernel does not supports HAS_LLC query, fallback to GPU
3510 * generation detection and assume that we have LLC on GEN6/7
3512 bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) |
3513 IS_GEN7(bufmgr_gem->pci_device));
3515 bufmgr_gem->has_llc = *gp.value;
3517 gp.param = I915_PARAM_HAS_VEBOX;
3518 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3519 bufmgr_gem->has_vebox = (ret == 0) & (*gp.value > 0);
3521 if (bufmgr_gem->gen < 4) {
3522 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
3523 gp.value = &bufmgr_gem->available_fences;
3524 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3526 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
3528 fprintf(stderr, "param: %d, val: %d\n", gp.param,
3530 bufmgr_gem->available_fences = 0;
3532 /* XXX The kernel reports the total number of fences,
3533 * including any that may be pinned.
3535 * We presume that there will be at least one pinned
3536 * fence for the scanout buffer, but there may be more
3537 * than one scanout and the user may be manually
3538 * pinning buffers. Let's move to execbuffer2 and
3539 * thereby forget the insanity of using fences...
3541 bufmgr_gem->available_fences -= 2;
3542 if (bufmgr_gem->available_fences < 0)
3543 bufmgr_gem->available_fences = 0;
3547 /* Let's go with one relocation per every 2 dwords (but round down a bit
3548 * since a power of two will mean an extra page allocation for the reloc
3551 * Every 4 was too few for the blender benchmark.
3553 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
3555 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
3556 bufmgr_gem->bufmgr.bo_alloc_for_render =
3557 drm_intel_gem_bo_alloc_for_render;
3558 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
3559 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
3560 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
3561 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
3562 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
3563 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
3564 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
3565 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
3566 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
3567 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
3568 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
3569 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
3570 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
3571 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
3572 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
3573 /* Use the new one if available */
3575 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
3576 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
3578 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
3579 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
3580 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
3581 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_unref;
3582 bufmgr_gem->bufmgr.debug = 0;
3583 bufmgr_gem->bufmgr.check_aperture_space =
3584 drm_intel_gem_check_aperture_space;
3585 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
3586 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
3587 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
3588 drm_intel_gem_get_pipe_from_crtc_id;
3589 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
3591 DRMINITLISTHEAD(&bufmgr_gem->named);
3592 init_cache_buckets(bufmgr_gem);
3594 DRMINITLISTHEAD(&bufmgr_gem->vma_cache);
3595 bufmgr_gem->vma_max = -1; /* unlimited by default */
3597 DRMLISTADD(&bufmgr_gem->managers, &bufmgr_list);
3600 pthread_mutex_unlock(&bufmgr_list_mutex);
3602 return bufmgr_gem != NULL ? &bufmgr_gem->bufmgr : NULL;