2 * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
4 * Copyright (c) 2008 Red Hat Inc.
5 * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
6 * Copyright (c) 2007-2008 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #define DRM_DISPLAY_INFO_LEN 32
31 #define DRM_CONNECTOR_NAME_LEN 32
32 #define DRM_DISPLAY_MODE_LEN 32
33 #define DRM_PROP_NAME_LEN 32
35 #define DRM_MODE_TYPE_BUILTIN (1<<0)
36 #define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN)
37 #define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN)
38 #define DRM_MODE_TYPE_PREFERRED (1<<3)
39 #define DRM_MODE_TYPE_DEFAULT (1<<4)
40 #define DRM_MODE_TYPE_USERDEF (1<<5)
41 #define DRM_MODE_TYPE_DRIVER (1<<6)
43 /* Video mode flags */
44 /* bit compatible with the xorg definitions. */
45 #define DRM_MODE_FLAG_PHSYNC (1<<0)
46 #define DRM_MODE_FLAG_NHSYNC (1<<1)
47 #define DRM_MODE_FLAG_PVSYNC (1<<2)
48 #define DRM_MODE_FLAG_NVSYNC (1<<3)
49 #define DRM_MODE_FLAG_INTERLACE (1<<4)
50 #define DRM_MODE_FLAG_DBLSCAN (1<<5)
51 #define DRM_MODE_FLAG_CSYNC (1<<6)
52 #define DRM_MODE_FLAG_PCSYNC (1<<7)
53 #define DRM_MODE_FLAG_NCSYNC (1<<8)
54 #define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */
55 #define DRM_MODE_FLAG_BCAST (1<<10)
56 #define DRM_MODE_FLAG_PIXMUX (1<<11)
57 #define DRM_MODE_FLAG_DBLCLK (1<<12)
58 #define DRM_MODE_FLAG_CLKDIV2 (1<<13)
59 #define DRM_MODE_FLAG_3D_MASK (0x1f<<14)
60 #define DRM_MODE_FLAG_3D_NONE (0<<14)
61 #define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14)
62 #define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14)
63 #define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14)
64 #define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14)
65 #define DRM_MODE_FLAG_3D_L_DEPTH (5<<14)
66 #define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14)
67 #define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14)
68 #define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14)
72 /* bit compatible with the xorg definitions. */
73 #define DRM_MODE_DPMS_ON 0
74 #define DRM_MODE_DPMS_STANDBY 1
75 #define DRM_MODE_DPMS_SUSPEND 2
76 #define DRM_MODE_DPMS_OFF 3
78 /* Scaling mode options */
79 #define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or
80 software can still scale) */
81 #define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */
82 #define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */
83 #define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */
85 /* Dithering mode options */
86 #define DRM_MODE_DITHERING_OFF 0
87 #define DRM_MODE_DITHERING_ON 1
88 #define DRM_MODE_DITHERING_AUTO 2
90 /* Dirty info options */
91 #define DRM_MODE_DIRTY_OFF 0
92 #define DRM_MODE_DIRTY_ON 1
93 #define DRM_MODE_DIRTY_ANNOTATE 2
95 struct drm_mode_modeinfo {
97 __u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
98 __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
104 char name[DRM_DISPLAY_MODE_LEN];
107 struct drm_mode_card_res {
110 __u64 connector_id_ptr;
111 __u64 encoder_id_ptr;
114 __u32 count_connectors;
115 __u32 count_encoders;
116 __u32 min_width, max_width;
117 __u32 min_height, max_height;
120 struct drm_mode_crtc {
121 __u64 set_connectors_ptr;
122 __u32 count_connectors;
124 __u32 crtc_id; /**< Id */
125 __u32 fb_id; /**< Id of framebuffer */
127 __u32 x, y; /**< Position on the frameuffer */
131 struct drm_mode_modeinfo mode;
134 #define DRM_MODE_PRESENT_TOP_FIELD (1<<0)
135 #define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1)
137 /* Planes blend with or override other bits on the CRTC */
138 struct drm_mode_set_plane {
141 __u32 fb_id; /* fb object contains surface format type */
144 /* Signed dest location allows it to be partially off screen */
145 __s32 crtc_x, crtc_y;
146 __u32 crtc_w, crtc_h;
148 /* Source values are 16.16 fixed point */
153 struct drm_mode_get_plane {
159 __u32 possible_crtcs;
162 __u32 count_format_types;
163 __u64 format_type_ptr;
166 struct drm_mode_get_plane_res {
171 #define DRM_MODE_ENCODER_NONE 0
172 #define DRM_MODE_ENCODER_DAC 1
173 #define DRM_MODE_ENCODER_TMDS 2
174 #define DRM_MODE_ENCODER_LVDS 3
175 #define DRM_MODE_ENCODER_TVDAC 4
176 #define DRM_MODE_ENCODER_VIRTUAL 5
178 struct drm_mode_get_encoder {
182 __u32 crtc_id; /**< Id of crtc */
184 __u32 possible_crtcs;
185 __u32 possible_clones;
188 /* This is for connectors with multiple signal types. */
189 /* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
190 #define DRM_MODE_SUBCONNECTOR_Automatic 0
191 #define DRM_MODE_SUBCONNECTOR_Unknown 0
192 #define DRM_MODE_SUBCONNECTOR_DVID 3
193 #define DRM_MODE_SUBCONNECTOR_DVIA 4
194 #define DRM_MODE_SUBCONNECTOR_Composite 5
195 #define DRM_MODE_SUBCONNECTOR_SVIDEO 6
196 #define DRM_MODE_SUBCONNECTOR_Component 8
197 #define DRM_MODE_SUBCONNECTOR_SCART 9
199 #define DRM_MODE_CONNECTOR_Unknown 0
200 #define DRM_MODE_CONNECTOR_VGA 1
201 #define DRM_MODE_CONNECTOR_DVII 2
202 #define DRM_MODE_CONNECTOR_DVID 3
203 #define DRM_MODE_CONNECTOR_DVIA 4
204 #define DRM_MODE_CONNECTOR_Composite 5
205 #define DRM_MODE_CONNECTOR_SVIDEO 6
206 #define DRM_MODE_CONNECTOR_LVDS 7
207 #define DRM_MODE_CONNECTOR_Component 8
208 #define DRM_MODE_CONNECTOR_9PinDIN 9
209 #define DRM_MODE_CONNECTOR_DisplayPort 10
210 #define DRM_MODE_CONNECTOR_HDMIA 11
211 #define DRM_MODE_CONNECTOR_HDMIB 12
212 #define DRM_MODE_CONNECTOR_TV 13
213 #define DRM_MODE_CONNECTOR_eDP 14
214 #define DRM_MODE_CONNECTOR_VIRTUAL 15
216 struct drm_mode_get_connector {
221 __u64 prop_values_ptr;
225 __u32 count_encoders;
227 __u32 encoder_id; /**< Current Encoder */
228 __u32 connector_id; /**< Id */
229 __u32 connector_type;
230 __u32 connector_type_id;
233 __u32 mm_width, mm_height; /**< HxW in millimeters */
237 #define DRM_MODE_PROP_PENDING (1<<0)
238 #define DRM_MODE_PROP_RANGE (1<<1)
239 #define DRM_MODE_PROP_IMMUTABLE (1<<2)
240 #define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */
241 #define DRM_MODE_PROP_BLOB (1<<4)
242 #define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */
244 struct drm_mode_property_enum {
246 char name[DRM_PROP_NAME_LEN];
249 struct drm_mode_get_property {
250 __u64 values_ptr; /* values and blob lengths */
251 __u64 enum_blob_ptr; /* enum and blob id ptrs */
255 char name[DRM_PROP_NAME_LEN];
258 __u32 count_enum_blobs;
261 struct drm_mode_connector_set_property {
267 #define DRM_MODE_OBJECT_CRTC 0xcccccccc
268 #define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
269 #define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0
270 #define DRM_MODE_OBJECT_MODE 0xdededede
271 #define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0
272 #define DRM_MODE_OBJECT_FB 0xfbfbfbfb
273 #define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
274 #define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
276 struct drm_mode_obj_get_properties {
278 __u64 prop_values_ptr;
284 struct drm_mode_obj_set_property {
291 struct drm_mode_get_blob {
297 struct drm_mode_fb_cmd {
303 /* driver specific handle */
307 #define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
309 struct drm_mode_fb_cmd2 {
312 __u32 pixel_format; /* fourcc code from drm_fourcc.h */
316 * In case of planar formats, this ioctl allows up to 4
317 * buffer objects with offsets and pitches per plane.
318 * The pitch and offset order is dictated by the fourcc,
319 * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
321 * YUV 4:2:0 image with a plane of 8 bit Y samples
322 * followed by an interleaved U/V plane containing
323 * 8 bit 2x2 subsampled colour difference samples.
325 * So it would consist of Y as offset[0] and UV as
326 * offset[1]. Note that offset[0] will generally
330 __u32 pitches[4]; /* pitch for each plane */
331 __u32 offsets[4]; /* offset of each plane */
334 #define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
335 #define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
336 #define DRM_MODE_FB_DIRTY_FLAGS 0x03
339 * Mark a region of a framebuffer as dirty.
341 * Some hardware does not automatically update display contents
342 * as a hardware or software draw to a framebuffer. This ioctl
343 * allows userspace to tell the kernel and the hardware what
344 * regions of the framebuffer have changed.
346 * The kernel or hardware is free to update more then just the
347 * region specified by the clip rects. The kernel or hardware
348 * may also delay and/or coalesce several calls to dirty into a
351 * Userspace may annotate the updates, the annotates are a
352 * promise made by the caller that the change is either a copy
353 * of pixels or a fill of a single color in the region specified.
355 * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
356 * the number of updated regions are half of num_clips given,
357 * where the clip rects are paired in src and dst. The width and
358 * height of each one of the pairs must match.
360 * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
361 * promises that the region specified of the clip rects is filled
362 * completely with a single color as given in the color argument.
365 struct drm_mode_fb_dirty_cmd {
373 struct drm_mode_mode_cmd {
375 struct drm_mode_modeinfo mode;
378 #define DRM_MODE_CURSOR_BO (1<<0)
379 #define DRM_MODE_CURSOR_MOVE (1<<1)
382 * depending on the value in flags diffrent members are used.
388 * handle - if 0 turns the cursor of
395 struct drm_mode_cursor {
402 /* driver specific handle */
406 struct drm_mode_cursor2 {
413 /* driver specific handle */
419 struct drm_mode_crtc_lut {
423 /* pointers to arrays */
429 #define DRM_MODE_PAGE_FLIP_EVENT 0x01
430 #define DRM_MODE_PAGE_FLIP_ASYNC 0x02
431 #define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT|DRM_MODE_PAGE_FLIP_ASYNC)
434 * Request a page flip on the specified crtc.
436 * This ioctl will ask KMS to schedule a page flip for the specified
437 * crtc. Once any pending rendering targeting the specified fb (as of
438 * ioctl time) has completed, the crtc will be reprogrammed to display
439 * that fb after the next vertical refresh. The ioctl returns
440 * immediately, but subsequent rendering to the current fb will block
441 * in the execbuffer ioctl until the page flip happens. If a page
442 * flip is already pending as the ioctl is called, EBUSY will be
445 * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will
446 * request that drm sends back a vblank event (see drm.h: struct
447 * drm_event_vblank) when the page flip is done. The user_data field
448 * passed in with this ioctl will be returned as the user_data field
449 * in the vblank event struct.
451 * The reserved field must be zero until we figure out something
452 * clever to use it for.
455 struct drm_mode_crtc_page_flip {
463 /* create a dumb scanout buffer */
464 struct drm_mode_create_dumb {
469 /* handle, pitch, size will be returned */
475 /* set up for mmap of a dumb scanout buffer */
476 struct drm_mode_map_dumb {
477 /** Handle for the object being mapped. */
481 * Fake offset to use for subsequent mmap call
483 * This is a fixed-size type for 32/64 compatibility.
488 struct drm_mode_destroy_dumb {