3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
7 * Seung-Woo Kim <sw0312.kim@samsung.com>
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
26 * OTHER DEALINGS IN THE SOFTWARE.
29 #ifndef _EXYNOS_DRM_H_
30 #define _EXYNOS_DRM_H_
35 * User-desired buffer creation information structure.
37 * @size: user-desired memory allocation size.
38 * - this size value would be page-aligned internally.
39 * @flags: user request for setting memory type or cache attributes.
40 * @handle: returned a handle to created gem object.
41 * - this handle will be set by gem module of kernel side.
43 struct drm_exynos_gem_create {
50 * A structure for getting a fake-offset that can be used with mmap.
52 * @handle: handle of gem object.
53 * @reserved: just padding to be 64-bit aligned.
54 * @offset: a fake-offset of gem object.
56 struct drm_exynos_gem_map {
63 * A structure to gem information.
65 * @handle: a handle to gem object created.
66 * @flags: flag value including memory type and cache attribute and
67 * this value would be set by driver.
68 * @size: size to memory region allocated by gem and this size would
71 struct drm_exynos_gem_info {
78 * A structure for user connection request of virtual display.
80 * @connection: indicate whether doing connetion or not by user.
81 * @extensions: if this value is 1 then the vidi driver would need additional
83 * @edid: the edid data pointer from user side.
85 struct drm_exynos_vidi_connection {
86 unsigned int connection;
87 unsigned int extensions;
91 /* memory type definitions. */
92 enum e_drm_exynos_gem_mem_type {
93 /* Physically Continuous memory and used as default. */
94 EXYNOS_BO_CONTIG = 0 << 0,
95 /* Physically Non-Continuous memory. */
96 EXYNOS_BO_NONCONTIG = 1 << 0,
97 /* non-cachable mapping and used as default. */
98 EXYNOS_BO_NONCACHABLE = 0 << 1,
99 /* cachable mapping. */
100 EXYNOS_BO_CACHABLE = 1 << 1,
101 /* write-combine mapping. */
102 EXYNOS_BO_WC = 1 << 2,
103 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
107 struct drm_exynos_g2d_get_ver {
112 struct drm_exynos_g2d_cmd {
117 enum drm_exynos_g2d_buf_type {
118 G2D_BUF_USERPTR = 1 << 31,
121 enum drm_exynos_g2d_event_type {
124 G2D_EVENT_STOP, /* not yet */
127 struct drm_exynos_g2d_userptr {
128 unsigned long userptr;
132 struct drm_exynos_g2d_set_cmdlist {
143 struct drm_exynos_g2d_exec {
147 /* definition of operations types */
148 enum drm_exynos_ops_id {
154 /* definition of size */
155 struct drm_exynos_sz {
160 /* definition of position */
161 struct drm_exynos_pos {
168 /* definition of flip */
169 enum drm_exynos_flip {
170 EXYNOS_DRM_FLIP_NONE = (0 << 0),
171 EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
172 EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
173 EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL |
174 EXYNOS_DRM_FLIP_HORIZONTAL,
177 /* definition of rotation degree */
178 enum drm_exynos_degree {
180 EXYNOS_DRM_DEGREE_90,
181 EXYNOS_DRM_DEGREE_180,
182 EXYNOS_DRM_DEGREE_270,
185 /* definition of planar */
186 enum drm_exynos_planer {
188 EXYNOS_DRM_PLANAR_CB,
189 EXYNOS_DRM_PLANAR_CR,
190 EXYNOS_DRM_PLANAR_MAX,
193 /* define of blending operation */
194 enum drm_exynos_ipp_blending {
202 /* [Sa + (1 - Sa)*Da, Rc = Sc + (1 - Sa)*Dc] */
203 IPP_BLENDING_SRC_OVER,
204 /* [Sa + (1 - Sa)*Da, Rc = Dc + (1 - Da)*Sc] */
205 IPP_BLENDING_DST_OVER,
206 /* [Sa * Da, Sc * Da] */
208 /* [Sa * Da, Sa * Dc] */
210 /* [Sa * (1 - Da), Sc * (1 - Da)] */
211 IPP_BLENDING_SRC_OUT,
212 /* [Da * (1 - Sa), Dc * (1 - Sa)] */
213 IPP_BLENDING_DST_OUT,
214 /* [Da, Sc * Da + (1 - Sa) * Dc] */
215 IPP_BLENDING_SRC_ATOP,
216 /* [Sa, Sc * (1 - Da) + Sa * Dc ] */
217 IPP_BLENDING_DST_ATOP,
218 /* [-(Sa * Da), Sc * (1 - Da) + (1 - Sa) * Dc] */
220 /* [Sa + Da - Sa*Da, Sc*(1 - Da) + Dc*(1 - Sa) + min(Sc, Dc)] */
222 /* [Sa + Da - Sa*Da, Sc*(1 - Da) + Dc*(1 - Sa) + max(Sc, Dc)] */
223 IPP_BLENDING_LIGHTEN,
224 /* [Sa * Da, Sc * Dc] */
225 IPP_BLENDING_MULTIPLY,
226 /* [Sa + Da - Sa * Da, Sc + Dc - Sc * Dc] */
228 /* Saturate(S + D) */
234 /* define of dithering operation */
235 enum drm_exynos_ipp_dithering {
245 * A structure for ipp supported property list.
247 * @version: version of this structure.
248 * @ipp_id: id of ipp driver.
249 * @count: count of ipp driver.
250 * @writeback: flag of writeback supporting.
251 * @flip: flag of flip supporting.
252 * @degree: flag of degree information.
253 * @csc: flag of csc supporting.
254 * @crop: flag of crop supporting.
255 * @scale: flag of scale supporting.
256 * @blending: flag of blending supporting.
257 * @dithering: flag of dithering supporting.
258 * @colorfill: flag of colorfill supporting.
259 * @refresh_min: min hz of refresh.
260 * @refresh_max: max hz of refresh.
261 * @crop_min: crop min resolution.
262 * @crop_max: crop max resolution.
263 * @scale_min: scale min resolution.
264 * @scale_max: scale max resolution.
266 struct drm_exynos_ipp_prop_list {
281 struct drm_exynos_sz crop_min;
282 struct drm_exynos_sz crop_max;
283 struct drm_exynos_sz scale_min;
284 struct drm_exynos_sz scale_max;
288 * A structure for ipp config.
290 * @ops_id: property of operation directions.
291 * @flip: property of mirror, flip.
292 * @degree: property of rotation degree.
293 * @fmt: property of image format.
294 * @sz: property of image size.
295 * @pos: property of image position(src-cropped,dst-scaler).
297 struct drm_exynos_ipp_config {
298 enum drm_exynos_ops_id ops_id;
299 enum drm_exynos_flip flip;
300 enum drm_exynos_degree degree;
302 struct drm_exynos_sz sz;
303 struct drm_exynos_pos pos;
306 /* definition of command */
307 enum drm_exynos_ipp_cmd {
315 /* define of color range */
316 enum drm_exynos_color_range {
317 COLOR_RANGE_LIMITED, /* Narrow: Y(16 to 235), Cb/Cr(16 to 240) */
318 COLOR_RANGE_FULL, /* Wide: Y/Cb/Cr(0 to 255), Wide default */
322 * A structure for ipp property.
324 * @config: source, destination config.
325 * @cmd: definition of command.
326 * @ipp_id: id of ipp driver.
327 * @prop_id: id of property.
328 * @refresh_rate: refresh rate.
329 * @range: dynamic range for csc.
330 * @blending: blending opeation config.
331 * @dithering: dithering opeation config.
332 * @color_fill: color fill value.
334 struct drm_exynos_ipp_property {
335 struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
336 enum drm_exynos_ipp_cmd cmd;
346 /* definition of buffer */
347 enum drm_exynos_ipp_buf_type {
353 * A structure for ipp buffer operations.
355 * @ops_id: operation directions.
356 * @buf_type: definition of buffer.
357 * @prop_id: id of property.
358 * @buf_id: id of buffer.
359 * @handle: Y, Cb, Cr each planar handle.
360 * @user_data: user data.
362 struct drm_exynos_ipp_queue_buf {
363 enum drm_exynos_ops_id ops_id;
364 enum drm_exynos_ipp_buf_type buf_type;
367 __u32 handle[EXYNOS_DRM_PLANAR_MAX];
372 /* definition of control */
373 enum drm_exynos_ipp_ctrl {
382 * A structure for ipp start/stop operations.
384 * @prop_id: id of property.
385 * @ctrl: definition of control.
387 struct drm_exynos_ipp_cmd_ctrl {
389 enum drm_exynos_ipp_ctrl ctrl;
392 #define DRM_EXYNOS_GEM_CREATE 0x00
393 #define DRM_EXYNOS_GEM_MAP 0x01
394 /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
395 #define DRM_EXYNOS_GEM_GET 0x04
396 #define DRM_EXYNOS_VIDI_CONNECTION 0x07
399 #define DRM_EXYNOS_G2D_GET_VER 0x20
400 #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
401 #define DRM_EXYNOS_G2D_EXEC 0x22
403 /* IPP - Image Post Processing */
404 #define DRM_EXYNOS_IPP_GET_PROPERTY 0x30
405 #define DRM_EXYNOS_IPP_SET_PROPERTY 0x31
406 #define DRM_EXYNOS_IPP_QUEUE_BUF 0x32
407 #define DRM_EXYNOS_IPP_CMD_CTRL 0x33
409 #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
410 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
411 #define DRM_IOCTL_EXYNOS_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + \
412 DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map)
413 #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \
414 DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
416 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \
417 DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
419 #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
420 DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
421 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
422 DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
423 #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
424 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
426 #define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
427 DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
428 #define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
429 DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
430 #define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \
431 DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
432 #define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \
433 DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
435 /* EXYNOS specific events */
436 #define DRM_EXYNOS_G2D_EVENT 0x80000000
437 #define DRM_EXYNOS_IPP_EVENT 0x80000001
439 struct drm_exynos_g2d_event {
440 struct drm_event base;
448 struct drm_exynos_ipp_event {
449 struct drm_event base;
455 __u32 buf_id[EXYNOS_DRM_OPS_MAX];