2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Chris Wilson <chris@chris-wilson.co.uk>
31 #include <sys/ioctl.h>
40 #include "ioctl_wrappers.h"
42 #include "intel_chipset.h"
48 #define OBJECT_SIZE (4*WIDTH*HEIGHT)
50 #define BATCH_SIZE 4096
55 * Testcase: execbuf fence accounting
57 * We had a bug where we were falsely accounting upon reservation already
58 * fenced buffers as occupying a fence register even if they did not require
61 * We aim to exercise this by performing a sequence of fenced BLT
62 * with 2*num_avail_fence buffers, but alternating which half are fenced in
66 static drm_intel_bufmgr *bufmgr;
67 struct intel_batchbuffer *batch;
70 static void emit_dummy_load(void)
73 uint32_t tile_flags = 0;
74 uint32_t tiling_mode = I915_TILING_X;
76 drm_intel_bo *dummy_bo;
78 dummy_bo = drm_intel_bo_alloc_tiled(bufmgr, "tiled dummy_bo", 2048, 2048,
79 4, &tiling_mode, &pitch, 0);
83 tile_flags = XY_SRC_COPY_BLT_SRC_TILED |
84 XY_SRC_COPY_BLT_DST_TILED;
87 for (i = 0; i < 5; i++) {
88 BLIT_COPY_BATCH_START(devid, tile_flags);
89 OUT_BATCH((3 << 24) | /* 32 bits */
90 (0xcc << 16) | /* copy ROP */
92 OUT_BATCH(0 << 16 | 1024);
93 OUT_BATCH((2048) << 16 | (2048));
94 OUT_RELOC_FENCED(dummy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
95 OUT_BATCH(0 << 16 | 0);
97 OUT_RELOC_FENCED(dummy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
100 if (IS_GEN6(devid) || IS_GEN7(devid)) {
102 OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
108 intel_batchbuffer_flush(batch);
110 drm_intel_bo_unreference(dummy_bo);
114 tiled_bo_create (int fd)
118 handle = gem_create(fd, OBJECT_SIZE);
120 gem_set_tiling(fd, handle, I915_TILING_X, WIDTH*4);
126 batch_create (int fd)
128 uint32_t buf[] = { MI_BATCH_BUFFER_END, 0 };
129 uint32_t batch_handle;
131 batch_handle = gem_create(fd, BATCH_SIZE);
133 gem_write(fd, batch_handle, 0, buf, sizeof(buf));
138 static void fill_reloc(struct drm_i915_gem_relocation_entry *reloc, uint32_t handle)
140 reloc->offset = 2 * sizeof(uint32_t);
141 reloc->target_handle = handle;
142 reloc->read_domains = I915_GEM_DOMAIN_RENDER;
143 reloc->write_domain = 0;
146 #define BUSY_LOAD (1 << 0)
147 #define INTERRUPTIBLE (1 << 1)
149 static void run_test(int fd, int num_fences, int expected_errno,
152 struct drm_i915_gem_execbuffer2 execbuf[2];
153 struct drm_i915_gem_exec_object2 exec[2][2*MAX_FENCES+3];
154 struct drm_i915_gem_relocation_entry reloc[2*MAX_FENCES+2];
159 if (flags & BUSY_LOAD) {
160 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
161 batch = intel_batchbuffer_alloc(bufmgr, devid);
163 /* Takes forever otherwise. */
167 if (flags & INTERRUPTIBLE)
168 igt_fork_signal_helper();
170 memset(execbuf, 0, sizeof(execbuf));
171 memset(exec, 0, sizeof(exec));
172 memset(reloc, 0, sizeof(reloc));
174 for (n = 0; n < 2*num_fences; n++) {
175 uint32_t handle = tiled_bo_create(fd);
176 exec[1][2*num_fences - n-1].handle = exec[0][n].handle = handle;
177 fill_reloc(&reloc[n], handle);
180 for (i = 0; i < 2; i++) {
181 for (n = 0; n < num_fences; n++)
182 exec[i][n].flags = EXEC_OBJECT_NEEDS_FENCE;
184 exec[i][2*num_fences].handle = batch_create(fd);
185 exec[i][2*num_fences].relocs_ptr = (uintptr_t)reloc;
186 exec[i][2*num_fences].relocation_count = 2*num_fences;
188 execbuf[i].buffers_ptr = (uintptr_t)exec[i];
189 execbuf[i].buffer_count = 2*num_fences+1;
190 execbuf[i].batch_len = 2*sizeof(uint32_t);
196 if (flags & BUSY_LOAD)
200 DRM_IOCTL_I915_GEM_EXECBUFFER2,
202 igt_assert(expected_errno ?
203 ret < 0 && errno == expected_errno :
207 DRM_IOCTL_I915_GEM_EXECBUFFER2,
209 igt_assert(expected_errno ?
210 ret < 0 && errno == expected_errno :
214 if (flags & INTERRUPTIBLE)
215 igt_stop_signal_helper();
223 igt_skip_on_simulation();
227 num_fences = gem_available_fences(fd);
228 igt_assert(num_fences > 4);
229 devid = intel_get_drm_devid(fd);
231 igt_assert(num_fences <= MAX_FENCES);
234 igt_subtest("2-spare-fences")
235 run_test(fd, num_fences - 2, 0, 0);
236 for (unsigned flags = 0; flags < 4; flags++) {
237 igt_subtest_f("no-spare-fences%s%s",
238 flags & BUSY_LOAD ? "-busy" : "",
239 flags & INTERRUPTIBLE ? "-interruptible" : "")
240 run_test(fd, num_fences, 0, flags);
242 igt_subtest("too-many-fences")
243 run_test(fd, num_fences + 1, intel_gen(devid) >= 4 ? 0 : EDEADLK, 0);