tests/gem_caching.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  25  *    Chris Wilson <chris@chris-wilson.co.uk>
  26  *
  27  */
  28
  29 #include <stdlib.h>
  30 #include <stdio.h>
  31 #include <string.h>
  32 #include <fcntl.h>
  33 #include <inttypes.h>
  34 #include <errno.h>
  35 #include <sys/stat.h>
  36 #include <sys/time.h>
  37
  38 #include <drm.h>
  39
  40 #include "ioctl_wrappers.h"
  41 #include "drmtest.h"
  42 #include "intel_bufmgr.h"
  43 #include "intel_batchbuffer.h"
  44 #include "intel_io.h"
  45 #include "intel_chipset.h"
  46 #include "igt_aux.h"
  47
  48 /*
  49  * Testcase: snoop consistency when touching partial cachelines
  50  *
  51  */
  52
  53 static drm_intel_bufmgr *bufmgr;
  54 struct intel_batchbuffer *batch;
  55
  56 drm_intel_bo *scratch_bo;
  57 drm_intel_bo *staging_bo;
  58 #define BO_SIZE (4*4096)
  59 uint32_t devid;
  60 uint64_t mappable_gtt_limit;
  61 int fd;
  62
  63 static void
  64 copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
  65 {
  66         BLIT_COPY_BATCH_START(devid, 0);
  67         OUT_BATCH((3 << 24) | /* 32 bits */
  68                   (0xcc << 16) | /* copy ROP */
  69                   4096);
  70         OUT_BATCH(0 << 16 | 0);
  71         OUT_BATCH((BO_SIZE/4096) << 16 | 1024);
  72         OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
  73         OUT_BATCH(0 << 16 | 0);
  74         OUT_BATCH(4096);
  75         OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
  76         ADVANCE_BATCH();
  77
  78         intel_batchbuffer_flush(batch);
  79 }
  80
  81 static void
  82 blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, uint8_t val)
  83 {
  84         uint8_t *gtt_ptr;
  85         int i;
  86
  87         do_or_die(drm_intel_gem_bo_map_gtt(tmp_bo));
  88         gtt_ptr = tmp_bo->virtual;
  89
  90         for (i = 0; i < BO_SIZE; i++)
  91                 gtt_ptr[i] = val;
  92
  93         drm_intel_gem_bo_unmap_gtt(tmp_bo);
  94
  95         if (bo->offset < mappable_gtt_limit &&
  96             (IS_G33(devid) || intel_gen(devid) >= 4))
  97                 igt_trash_aperture();
  98
  99         copy_bo(tmp_bo, bo);
 100 }
 101
 102 #define MAX_BLT_SIZE 128
 103 #define ROUNDS 1000
 104 #define TEST_READ 0x1
 105 #define TEST_WRITE 0x2
 106 #define TEST_BOTH (TEST_READ | TEST_WRITE)
 107 igt_main
 108 {
 109         unsigned flags = TEST_BOTH;
 110         int i, j;
 111         uint8_t *cpu_ptr;
 112         uint8_t *gtt_ptr;
 113
 114         igt_skip_on_simulation();
 115
 116         igt_fixture {
 117                 srandom(0xdeadbeef);
 118
 119                 fd = drm_open_any();
 120
 121                 gem_require_caching(fd);
 122
 123                 devid = intel_get_drm_devid(fd);
 124                 if (IS_GEN2(devid)) /* chipset only handles cached -> uncached */
 125                         flags &= ~TEST_READ;
 126                 if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
 127                         /* chipset is completely fubar */
 128                         igt_info("coherency broken on i965g/gm\n");
 129                         flags = 0;
 130                 }
 131
 132                 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
 133                 batch = intel_batchbuffer_alloc(bufmgr, devid);
 134
 135                 /* overallocate the buffers we're actually using because */
 136                 scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096);
 137                 gem_set_caching(fd, scratch_bo->handle, 1);
 138
 139                 staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
 140
 141                 igt_init_aperture_trashers(bufmgr);
 142                 mappable_gtt_limit = gem_mappable_aperture_size();
 143         }
 144
 145         igt_subtest("reads") {
 146                 igt_require(flags & TEST_READ);
 147
 148                 igt_info("checking partial reads\n");
 149
 150                 for (i = 0; i < ROUNDS; i++) {
 151                         uint8_t val0 = i;
 152                         int start, len;
 153
 154                         blt_bo_fill(staging_bo, scratch_bo, i);
 155
 156                         start = random() % BO_SIZE;
 157                         len = random() % (BO_SIZE-start) + 1;
 158
 159                         drm_intel_bo_map(scratch_bo, false);
 160                         cpu_ptr = scratch_bo->virtual;
 161                         for (j = 0; j < len; j++) {
 162                                 igt_assert_f(cpu_ptr[j] == val0,
 163                                              "mismatch at %i, got: %i, expected: %i\n",
 164                                              j, cpu_ptr[j], val0);
 165                         }
 166                         drm_intel_bo_unmap(scratch_bo);
 167
 168                         igt_progress("partial reads test: ", i, ROUNDS);
 169                 }
 170         }
 171
 172         igt_subtest("writes") {
 173                 igt_require(flags & TEST_WRITE);
 174
 175                 igt_info("checking partial writes\n");
 176
 177                 for (i = 0; i < ROUNDS; i++) {
 178                         uint8_t val0 = i, val1;
 179                         int start, len;
 180
 181                         blt_bo_fill(staging_bo, scratch_bo, val0);
 182
 183                         start = random() % BO_SIZE;
 184                         len = random() % (BO_SIZE-start) + 1;
 185
 186                         val1 = val0 + 63;
 187                         drm_intel_bo_map(scratch_bo, true);
 188                         cpu_ptr = scratch_bo->virtual;
 189                         memset(cpu_ptr + start, val1, len);
 190                         drm_intel_bo_unmap(scratch_bo);
 191
 192                         copy_bo(scratch_bo, staging_bo);
 193                         do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
 194                         gtt_ptr = staging_bo->virtual;
 195
 196                         for (j = 0; j < start; j++) {
 197                                 igt_assert_f(gtt_ptr[j] == val0,
 198                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 199                                              j, start, len, gtt_ptr[j], val0);
 200                         }
 201                         for (; j < start + len; j++) {
 202                                 igt_assert_f(gtt_ptr[j] == val1,
 203                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 204                                              j, start, len, gtt_ptr[j], val1);
 205                         }
 206                         for (; j < BO_SIZE; j++) {
 207                                 igt_assert_f(gtt_ptr[j] == val0,
 208                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 209                                              j, start, len, gtt_ptr[j], val0);
 210                         }
 211                         drm_intel_gem_bo_unmap_gtt(staging_bo);
 212
 213                         igt_progress("partial writes test: ", i, ROUNDS);
 214                 }
 215         }
 216
 217         igt_subtest("read-writes") {
 218                 igt_require((flags & TEST_BOTH) == TEST_BOTH);
 219
 220                 igt_info("checking partial writes after partial reads\n");
 221
 222                 for (i = 0; i < ROUNDS; i++) {
 223                         uint8_t val0 = i, val1, val2;
 224                         int start, len;
 225
 226                         blt_bo_fill(staging_bo, scratch_bo, val0);
 227
 228                         /* partial read */
 229                         start = random() % BO_SIZE;
 230                         len = random() % (BO_SIZE-start) + 1;
 231
 232                         do_or_die(drm_intel_bo_map(scratch_bo, false));
 233                         cpu_ptr = scratch_bo->virtual;
 234                         for (j = 0; j < len; j++) {
 235                                 igt_assert_f(cpu_ptr[j] == val0,
 236                                              "mismatch in read at %i, got: %i, expected: %i\n",
 237                                              j, cpu_ptr[j], val0);
 238                         }
 239                         drm_intel_bo_unmap(scratch_bo);
 240
 241                         /* Change contents through gtt to make the pread cachelines
 242                          * stale. */
 243                         val1 = i + 17;
 244                         blt_bo_fill(staging_bo, scratch_bo, val1);
 245
 246                         /* partial write */
 247                         start = random() % BO_SIZE;
 248                         len = random() % (BO_SIZE-start) + 1;
 249
 250                         val2 = i + 63;
 251                         do_or_die(drm_intel_bo_map(scratch_bo, false));
 252                         cpu_ptr = scratch_bo->virtual;
 253                         memset(cpu_ptr + start, val2, len);
 254
 255                         copy_bo(scratch_bo, staging_bo);
 256                         do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
 257                         gtt_ptr = staging_bo->virtual;
 258
 259                         for (j = 0; j < start; j++) {
 260                                 igt_assert_f(gtt_ptr[j] == val1,
 261                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 262                                              j, start, len, gtt_ptr[j], val1);
 263                         }
 264                         for (; j < start + len; j++) {
 265                                 igt_assert_f(gtt_ptr[j] == val2,
 266                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 267                                              j, start, len, gtt_ptr[j], val2);
 268                         }
 269                         for (; j < BO_SIZE; j++) {
 270                                 igt_assert_f(gtt_ptr[j] == val1,
 271                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 272                                              j, start, len, gtt_ptr[j], val1);
 273                         }
 274                         drm_intel_gem_bo_unmap_gtt(staging_bo);
 275                         drm_intel_bo_unmap(scratch_bo);
 276
 277                         igt_progress("partial read/writes test: ", i, ROUNDS);
 278                 }
 279         }
 280
 281         igt_fixture {
 282                 igt_cleanup_aperture_trashers();
 283                 drm_intel_bufmgr_destroy(bufmgr);
 284
 285                 close(fd);
 286         }
 287 }