1 /* Target-dependent code for Lattice Mico32 processor, for GDB.
2 Contributed by Jon Beniston <jon@beniston.com>
4 Copyright (C) 2009-2023 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "frame-unwind.h"
24 #include "frame-base.h"
30 #include "gdb/sim-lm32.h"
31 #include "arch-utils.h"
33 #include "trad-frame.h"
34 #include "reggroups.h"
35 #include "opcodes/lm32-desc.h"
39 /* Macros to extract fields from an instruction. */
40 #define LM32_OPCODE(insn) ((insn >> 26) & 0x3f)
41 #define LM32_REG0(insn) ((insn >> 21) & 0x1f)
42 #define LM32_REG1(insn) ((insn >> 16) & 0x1f)
43 #define LM32_REG2(insn) ((insn >> 11) & 0x1f)
44 #define LM32_IMM16(insn) ((((long)insn & 0xffff) << 16) >> 16)
46 struct lm32_gdbarch_tdep : gdbarch_tdep_base
48 /* gdbarch target dependent data here. Currently unused for LM32. */
51 struct lm32_frame_cache
53 /* The frame's base. Used when constructing a frame ID. */
58 /* Table indicating the location of each and every register. */
59 trad_frame_saved_reg *saved_regs;
62 /* Return whether a given register is in a given group. */
65 lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
66 const struct reggroup *group)
68 if (group == general_reggroup)
69 return ((regnum >= SIM_LM32_R0_REGNUM) && (regnum <= SIM_LM32_RA_REGNUM))
70 || (regnum == SIM_LM32_PC_REGNUM);
71 else if (group == system_reggroup)
72 return ((regnum >= SIM_LM32_BA_REGNUM) && (regnum <= SIM_LM32_EA_REGNUM))
73 || ((regnum >= SIM_LM32_EID_REGNUM) && (regnum <= SIM_LM32_IP_REGNUM));
74 return default_register_reggroup_p (gdbarch, regnum, group);
77 /* Return a name that corresponds to the given register number. */
80 lm32_register_name (struct gdbarch *gdbarch, int reg_nr)
82 static const char *register_names[] = {
83 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
84 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
85 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
86 "r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba",
87 "PC", "EID", "EBA", "DEBA", "IE", "IM", "IP"
90 gdb_static_assert (ARRAY_SIZE (register_names) == SIM_LM32_NUM_REGS);
91 return register_names[reg_nr];
94 /* Return type of register. */
97 lm32_register_type (struct gdbarch *gdbarch, int reg_nr)
99 return builtin_type (gdbarch)->builtin_int32;
102 /* Return non-zero if a register can't be written. */
105 lm32_cannot_store_register (struct gdbarch *gdbarch, int regno)
107 return (regno == SIM_LM32_R0_REGNUM) || (regno == SIM_LM32_EID_REGNUM);
110 /* Analyze a function's prologue. */
113 lm32_analyze_prologue (struct gdbarch *gdbarch,
114 CORE_ADDR pc, CORE_ADDR limit,
115 struct lm32_frame_cache *info)
117 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
118 unsigned long instruction;
120 /* Keep reading though instructions, until we come across an instruction
121 that isn't likely to be part of the prologue. */
123 for (; pc < limit; pc += 4)
126 /* Read an instruction. */
127 instruction = read_memory_integer (pc, 4, byte_order);
129 if ((LM32_OPCODE (instruction) == OP_SW)
130 && (LM32_REG0 (instruction) == SIM_LM32_SP_REGNUM))
132 /* Any stack displaced store is likely part of the prologue.
133 Record that the register is being saved, and the offset
135 info->saved_regs[LM32_REG1 (instruction)].set_addr (LM32_IMM16 (instruction));
137 else if ((LM32_OPCODE (instruction) == OP_ADDI)
138 && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
140 /* An add to the SP is likely to be part of the prologue.
141 Adjust stack size by whatever the instruction adds to the sp. */
142 info->size -= LM32_IMM16 (instruction);
144 else if ( /* add fp,fp,sp */
145 ((LM32_OPCODE (instruction) == OP_ADD)
146 && (LM32_REG2 (instruction) == SIM_LM32_FP_REGNUM)
147 && (LM32_REG0 (instruction) == SIM_LM32_FP_REGNUM)
148 && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
150 || ((LM32_OPCODE (instruction) == OP_ADDI)
151 && (LM32_REG1 (instruction) == SIM_LM32_FP_REGNUM)
152 && (LM32_REG0 (instruction) == SIM_LM32_R0_REGNUM)))
154 /* Likely to be in the prologue for functions that require
159 /* Any other instruction is likely not to be part of the
168 /* Return PC of first non prologue instruction, for the function at the
169 specified address. */
172 lm32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
174 CORE_ADDR func_addr, limit_pc;
175 struct lm32_frame_cache frame_info;
176 trad_frame_saved_reg saved_regs[SIM_LM32_NUM_REGS];
178 /* See if we can determine the end of the prologue via the symbol table.
179 If so, then return either PC, or the PC after the prologue, whichever
181 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
183 CORE_ADDR post_prologue_pc
184 = skip_prologue_using_sal (gdbarch, func_addr);
185 if (post_prologue_pc != 0)
186 return std::max (pc, post_prologue_pc);
189 /* Can't determine prologue from the symbol table, need to examine
192 /* Find an upper limit on the function prologue using the debug
193 information. If the debug information could not be used to provide
194 that bound, then use an arbitrary large number as the upper bound. */
195 limit_pc = skip_prologue_using_sal (gdbarch, pc);
197 limit_pc = pc + 100; /* Magic. */
199 frame_info.saved_regs = saved_regs;
200 return lm32_analyze_prologue (gdbarch, pc, limit_pc, &frame_info);
203 /* Create a breakpoint instruction. */
204 constexpr gdb_byte lm32_break_insn[4] = { OP_RAISE << 2, 0, 0, 2 };
206 typedef BP_MANIPULATION (lm32_break_insn) lm32_breakpoint;
209 /* Setup registers and stack for faking a call to a function in the
213 lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
214 struct regcache *regcache, CORE_ADDR bp_addr,
215 int nargs, struct value **args, CORE_ADDR sp,
216 function_call_return_method return_method,
217 CORE_ADDR struct_addr)
219 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
220 int first_arg_reg = SIM_LM32_R1_REGNUM;
221 int num_arg_regs = 8;
224 /* Set the return address. */
225 regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr);
227 /* If we're returning a large struct, a pointer to the address to
228 store it at is passed as a first hidden parameter. */
229 if (return_method == return_method_struct)
231 regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr);
237 /* Setup parameters. */
238 for (i = 0; i < nargs; i++)
240 struct value *arg = args[i];
241 struct type *arg_type = check_typedef (value_type (arg));
245 /* Promote small integer types to int. */
246 switch (arg_type->code ())
251 case TYPE_CODE_RANGE:
253 if (arg_type->length () < 4)
255 arg_type = builtin_type (gdbarch)->builtin_int32;
256 arg = value_cast (arg_type, arg);
261 /* FIXME: Handle structures. */
263 contents = (gdb_byte *) value_contents (arg).data ();
264 val = extract_unsigned_integer (contents, arg_type->length (),
267 /* First num_arg_regs parameters are passed by registers,
268 and the rest are passed on the stack. */
269 if (i < num_arg_regs)
270 regcache_cooked_write_unsigned (regcache, first_arg_reg + i, val);
273 write_memory_unsigned_integer (sp, arg_type->length (), byte_order,
279 /* Update stack pointer. */
280 regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp);
282 /* Return adjusted stack pointer. */
286 /* Extract return value after calling a function in the inferior. */
289 lm32_extract_return_value (struct type *type, struct regcache *regcache,
292 struct gdbarch *gdbarch = regcache->arch ();
293 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
295 CORE_ADDR return_buffer;
297 if (type->code () != TYPE_CODE_STRUCT
298 && type->code () != TYPE_CODE_UNION
299 && type->code () != TYPE_CODE_ARRAY && type->length () <= 4)
301 /* Return value is returned in a single register. */
302 regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
303 store_unsigned_integer (valbuf, type->length (), byte_order, l);
305 else if ((type->code () == TYPE_CODE_INT) && (type->length () == 8))
307 /* 64-bit values are returned in a register pair. */
308 regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
309 memcpy (valbuf, &l, 4);
310 regcache_cooked_read_unsigned (regcache, SIM_LM32_R2_REGNUM, &l);
311 memcpy (valbuf + 4, &l, 4);
315 /* Aggregate types greater than a single register are returned
316 in memory. FIXME: Unless they are only 2 regs?. */
317 regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
319 read_memory (return_buffer, valbuf, type->length ());
323 /* Write into appropriate registers a function return value of type
324 TYPE, given in virtual format. */
326 lm32_store_return_value (struct type *type, struct regcache *regcache,
327 const gdb_byte *valbuf)
329 struct gdbarch *gdbarch = regcache->arch ();
330 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
332 int len = type->length ();
336 val = extract_unsigned_integer (valbuf, len, byte_order);
337 regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
341 val = extract_unsigned_integer (valbuf, 4, byte_order);
342 regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
343 val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order);
344 regcache_cooked_write_unsigned (regcache, SIM_LM32_R2_REGNUM, val);
347 error (_("lm32_store_return_value: type length too large."));
350 /* Determine whether a functions return value is in a register or memory. */
351 static enum return_value_convention
352 lm32_return_value (struct gdbarch *gdbarch, struct value *function,
353 struct type *valtype, struct regcache *regcache,
354 gdb_byte *readbuf, const gdb_byte *writebuf)
356 enum type_code code = valtype->code ();
358 if (code == TYPE_CODE_STRUCT
359 || code == TYPE_CODE_UNION
360 || code == TYPE_CODE_ARRAY || valtype->length () > 8)
361 return RETURN_VALUE_STRUCT_CONVENTION;
364 lm32_extract_return_value (valtype, regcache, readbuf);
366 lm32_store_return_value (valtype, regcache, writebuf);
368 return RETURN_VALUE_REGISTER_CONVENTION;
371 /* Put here the code to store, into fi->saved_regs, the addresses of
372 the saved registers of frame described by FRAME_INFO. This
373 includes special registers such as pc and fp saved in special ways
374 in the stack frame. sp is even more special: the address we return
375 for it IS the sp for the next frame. */
377 static struct lm32_frame_cache *
378 lm32_frame_cache (frame_info_ptr this_frame, void **this_prologue_cache)
380 CORE_ADDR current_pc;
383 struct lm32_frame_cache *info;
386 if ((*this_prologue_cache))
387 return (struct lm32_frame_cache *) (*this_prologue_cache);
389 info = FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache);
390 (*this_prologue_cache) = info;
391 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
393 info->pc = get_frame_func (this_frame);
394 current_pc = get_frame_pc (this_frame);
395 lm32_analyze_prologue (get_frame_arch (this_frame),
396 info->pc, current_pc, info);
398 /* Compute the frame's base, and the previous frame's SP. */
399 this_base = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
400 prev_sp = this_base + info->size;
401 info->base = this_base;
403 /* Convert callee save offsets into addresses. */
404 for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++)
406 if (info->saved_regs[i].is_addr ())
407 info->saved_regs[i].set_addr (this_base + info->saved_regs[i].addr ());
410 /* The call instruction moves the caller's PC in the callee's RA register.
411 Since this is an unwind, do the reverse. Copy the location of RA register
412 into PC (the address / regnum) so that a request for PC will be
413 converted into a request for the RA register. */
414 info->saved_regs[SIM_LM32_PC_REGNUM] = info->saved_regs[SIM_LM32_RA_REGNUM];
416 /* The previous frame's SP needed to be computed. Save the computed
418 info->saved_regs[SIM_LM32_SP_REGNUM].set_value (prev_sp);
424 lm32_frame_this_id (frame_info_ptr this_frame, void **this_cache,
425 struct frame_id *this_id)
427 struct lm32_frame_cache *cache = lm32_frame_cache (this_frame, this_cache);
429 /* This marks the outermost frame. */
430 if (cache->base == 0)
433 (*this_id) = frame_id_build (cache->base, cache->pc);
436 static struct value *
437 lm32_frame_prev_register (frame_info_ptr this_frame,
438 void **this_prologue_cache, int regnum)
440 struct lm32_frame_cache *info;
442 info = lm32_frame_cache (this_frame, this_prologue_cache);
443 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
446 static const struct frame_unwind lm32_frame_unwind = {
449 default_frame_unwind_stop_reason,
451 lm32_frame_prev_register,
453 default_frame_sniffer
457 lm32_frame_base_address (frame_info_ptr this_frame, void **this_cache)
459 struct lm32_frame_cache *info = lm32_frame_cache (this_frame, this_cache);
464 static const struct frame_base lm32_frame_base = {
466 lm32_frame_base_address,
467 lm32_frame_base_address,
468 lm32_frame_base_address
472 lm32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
474 /* Align to the size of an instruction (so that they can safely be
475 pushed onto the stack. */
479 static struct gdbarch *
480 lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
482 struct gdbarch *gdbarch;
484 /* If there is already a candidate, use it. */
485 arches = gdbarch_list_lookup_by_info (arches, &info);
487 return arches->gdbarch;
489 /* None found, create a new architecture from the information provided. */
490 lm32_gdbarch_tdep *tdep = new lm32_gdbarch_tdep;
491 gdbarch = gdbarch_alloc (&info, tdep);
494 set_gdbarch_short_bit (gdbarch, 16);
495 set_gdbarch_int_bit (gdbarch, 32);
496 set_gdbarch_long_bit (gdbarch, 32);
497 set_gdbarch_long_long_bit (gdbarch, 64);
498 set_gdbarch_float_bit (gdbarch, 32);
499 set_gdbarch_double_bit (gdbarch, 64);
500 set_gdbarch_long_double_bit (gdbarch, 64);
501 set_gdbarch_ptr_bit (gdbarch, 32);
504 set_gdbarch_num_regs (gdbarch, SIM_LM32_NUM_REGS);
505 set_gdbarch_sp_regnum (gdbarch, SIM_LM32_SP_REGNUM);
506 set_gdbarch_pc_regnum (gdbarch, SIM_LM32_PC_REGNUM);
507 set_gdbarch_register_name (gdbarch, lm32_register_name);
508 set_gdbarch_register_type (gdbarch, lm32_register_type);
509 set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register);
512 set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue);
513 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
514 set_gdbarch_decr_pc_after_break (gdbarch, 0);
515 set_gdbarch_frame_args_skip (gdbarch, 0);
517 /* Frame unwinding. */
518 set_gdbarch_frame_align (gdbarch, lm32_frame_align);
519 frame_base_set_default (gdbarch, &lm32_frame_base);
520 frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind);
523 set_gdbarch_breakpoint_kind_from_pc (gdbarch, lm32_breakpoint::kind_from_pc);
524 set_gdbarch_sw_breakpoint_from_kind (gdbarch, lm32_breakpoint::bp_from_kind);
525 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
527 /* Calling functions in the inferior. */
528 set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call);
529 set_gdbarch_return_value (gdbarch, lm32_return_value);
531 set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p);
536 void _initialize_lm32_tdep ();
538 _initialize_lm32_tdep ()
540 gdbarch_register (bfd_arch_lm32, lm32_gdbarch_init);