libavcodec/arm/rdft_neon.S

   1 /*
   2  * ARM NEON optimised RDFT
   3  * Copyright (c) 2009 Mans Rullgard <mans@mansr.com>
   4  *
   5  * This file is part of FFmpeg.
   6  *
   7  * FFmpeg is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * FFmpeg is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with FFmpeg; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
  20  */
  21
  22 #include "libavutil/arm/asm.S"
  23
  24 function ff_rdft_calc_neon, export=1
  25         push            {r4-r8,lr}
  26
  27         ldr             r6,  [r0, #4]           @ inverse
  28         mov             r4,  r0
  29         mov             r5,  r1
  30
  31         lsls            r6,  r6,  #31
  32         bne             1f
  33         add             r0,  r4,  #24
  34         bl              X(ff_fft_permute_neon)
  35         add             r0,  r4,  #24
  36         mov             r1,  r5
  37         bl              X(ff_fft_calc_neon)
  38 1:
  39         ldr             r12, [r4, #0]           @ nbits
  40         mov             r2,  #1
  41         ldr             r8,  [r4, #20]          @ negative_sin
  42         lsl             r12, r2,  r12
  43         add             r0,  r5,  #8
  44         lsl             r8,  r8,  #31
  45         add             r1,  r5,  r12, lsl #2
  46         lsr             r12, r12, #2
  47         vdup.32         d26, r8
  48         ldr             r2,  [r4, #12]          @ tcos
  49         sub             r12, r12, #2
  50         ldr             r3,  [r4, #16]          @ tsin
  51         mov             r7,  r0
  52         sub             r1,  r1,  #8
  53         mov             lr,  r1
  54         mov             r8,  #-8
  55         vld1.32         {d0},     [r0,:64]!     @ d1[0,1]
  56         vld1.32         {d1},     [r1,:64], r8  @ d2[0,1]
  57         vld1.32         {d4},     [r2,:64]!     @ tcos[i]
  58         vld1.32         {d5},     [r3,:64]!     @ tsin[i]
  59         vmov.f32        d18, #0.5               @ k1
  60         vdup.32         d19, r6
  61         veor            d5,  d26, d5
  62         pld             [r0, #32]
  63         veor            d19, d18, d19           @ k2
  64         vmov.i32        d16, #0
  65         vmov.i32        d17, #1<<31
  66         pld             [r1, #-32]
  67         vtrn.32         d16, d17
  68         pld             [r2, #32]
  69         vrev64.32       d16, d16                @ d16=1,0 d17=0,1
  70         pld             [r3, #32]
  71 2:
  72         veor            q1,  q0,  q8            @ -d1[0],d1[1], d2[0],-d2[1]
  73         vld1.32         {d24},    [r0,:64]!     @  d1[0,1]
  74         vadd.f32        d0,  d0,  d3            @  d1[0]+d2[0], d1[1]-d2[1]
  75         vld1.32         {d25},    [r1,:64], r8  @  d2[0,1]
  76         vadd.f32        d1,  d2,  d1            @ -d1[0]+d2[0], d1[1]+d2[1]
  77         veor            q3,  q12, q8            @ -d1[0],d1[1], d2[0],-d2[1]
  78         pld             [r0, #32]
  79         vmul.f32        q10, q0,  q9            @  ev.re, ev.im, od.im, od.re
  80         pld             [r1, #-32]
  81         vadd.f32        d0,  d24, d7            @  d1[0]+d2[0], d1[1]-d2[1]
  82         vadd.f32        d1,  d6,  d25           @ -d1[0]+d2[0], d1[1]+d2[1]
  83         vmul.f32        q11, q0,  q9            @  ev.re, ev.im, od.im, od.re
  84         veor            d7,  d21, d16           @ -od.im, od.re
  85         vrev64.32       d3,  d21                @  od.re, od.im
  86         veor            d6,  d20, d17           @  ev.re,-ev.im
  87         veor            d2,  d3,  d16           @ -od.re, od.im
  88         vmla.f32        d20, d3,  d4[1]
  89         vmla.f32        d20, d7,  d5[1]
  90         vmla.f32        d6,  d2,  d4[1]
  91         vmla.f32        d6,  d21, d5[1]
  92         vld1.32         {d4},     [r2,:64]!     @  tcos[i]
  93         veor            d7,  d23, d16           @ -od.im, od.re
  94         vld1.32         {d5},     [r3,:64]!     @  tsin[i]
  95         veor            d24, d22, d17           @  ev.re,-ev.im
  96         vrev64.32       d3,  d23                @  od.re, od.im
  97         veor            d5, d26, d5
  98         pld             [r2, #32]
  99         veor            d2,  d3,  d16           @ -od.re, od.im
 100         pld             [r3, #32]
 101         vmla.f32        d22, d3,  d4[0]
 102         vmla.f32        d22, d7,  d5[0]
 103         vmla.f32        d24, d2,  d4[0]
 104         vmla.f32        d24, d23, d5[0]
 105         vld1.32         {d0},     [r0,:64]!     @  d1[0,1]
 106         vld1.32         {d1},     [r1,:64], r8  @  d2[0,1]
 107         vst1.32         {d20},    [r7,:64]!
 108         vst1.32         {d6},     [lr,:64], r8
 109         vst1.32         {d22},    [r7,:64]!
 110         vst1.32         {d24},    [lr,:64], r8
 111         subs            r12, r12, #2
 112         bgt             2b
 113
 114         veor            q1,  q0,  q8            @ -d1[0],d1[1], d2[0],-d2[1]
 115         vadd.f32        d0,  d0,  d3            @  d1[0]+d2[0], d1[1]-d2[1]
 116         vadd.f32        d1,  d2,  d1            @ -d1[0]+d2[0], d1[1]+d2[1]
 117         ldr             r2,  [r4, #8]           @  sign_convention
 118         vmul.f32        q10, q0,  q9            @  ev.re, ev.im, od.im, od.re
 119         add             r0,  r0,  #4
 120         bfc             r2,  #0,  #31
 121         vld1.32         {d0[0]},  [r0,:32]
 122         veor            d7,  d21, d16           @ -od.im, od.re
 123         vrev64.32       d3,  d21                @  od.re, od.im
 124         veor            d6,  d20, d17           @  ev.re,-ev.im
 125         vld1.32         {d22},    [r5,:64]
 126         vdup.32         d1,  r2
 127         vmov            d23, d22
 128         veor            d2,  d3,  d16           @ -od.re, od.im
 129         vtrn.32         d22, d23
 130         veor            d0,  d0,  d1
 131         veor            d23, d23, d17
 132         vmla.f32        d20, d3,  d4[1]
 133         vmla.f32        d20, d7,  d5[1]
 134         vmla.f32        d6,  d2,  d4[1]
 135         vmla.f32        d6,  d21, d5[1]
 136         vadd.f32        d22, d22, d23
 137         vst1.32         {d20},    [r7,:64]
 138         vst1.32         {d6},     [lr,:64]
 139         vst1.32         {d0[0]},  [r0,:32]
 140         vst1.32         {d22},    [r5,:64]
 141
 142         cmp             r6,  #0
 143         it              eq
 144         popeq           {r4-r8,pc}
 145
 146         vmul.f32        d22, d22, d18
 147         vst1.32         {d22},    [r5,:64]
 148         add             r0,  r4,  #24
 149         mov             r1,  r5
 150         bl              X(ff_fft_permute_neon)
 151         add             r0,  r4,  #24
 152         mov             r1,  r5
 153         pop             {r4-r8,lr}
 154         b               X(ff_fft_calc_neon)
 155 endfunc