Fix for UBSan build
[platform/upstream/doxygen.git] / src / vhdlparser.y
1
2 /*********************************************************************************************
3  * The original was a VHDL parser description to be used with GMD Compiler
4  * Tool Box
5  * written from:
6  * Jan den Ouden, Jaap Hofstede
7  * Department of Computer Science (INF/SPA)
8  * University of Twente
9  * PB 217, 7500 AE ENSCHEDE, The Netherlands
10  * Tel: +31 53 893788
11  * Email: hofstede@cs.utwente.nl
12  * avail at: ftp.cs.utwente.nl in pub/src/VHDL/Grammar
13  *
14  * author of YACC transformation:
15  * Thomas Dettmer
16  * Dortmund University
17  * Dept. of Computer Scienc, LS1
18  * PB 500 500
19  * D-44221 Dortmund (Germany)
20  * Phone: +49-231-755-6464
21  * e-mail: dettmer@ls1.informatik.uni-dortmund.de
22  *****************************************************************
23  *
24  * This file is intended not to be used for commercial purposes
25  * without permission of the University of Twente and permission
26  * of the University of Dortmund
27  *
28  * NOTE THAT THERE IS NO WARRANTY FOR CORRECTNES, COMPLETENESS, SUPPORT
29  * OR ANYTHING ELSE.
30  *
31  *******************************************************/
32 /******************************************************************************
33  * modified for doxygen by M. Kreis
34  * extended to VHDL 93/2002/2008
35  ******************************************************************************/
36
37
38 %{
39 #include <stdio.h>
40 #include <qcstring.h>
41 #include <qstringlist.h>
42
43 #ifndef YYSTYPE
44 typedef int YYSTYPE;
45 #endif
46
47 struct  YYMM
48 {
49   int itype;
50   QCString qstr;
51 };
52
53 // define struct instead of union
54 #define YYSTYPE YYMM
55
56 #include "membergroup.h"
57 #include "vhdldocgen.h"
58 #include "doxygen.h"
59 #include "searchindex.h"
60 #include "vhdlscanner.h"
61 #include "commentscan.h"
62 #include "entry.h"
63 #include "arguments.h"
64
65 //-----------------------------variables ---------------------------------------------------------------------------
66 //static VhdlParser* myconv=0;
67
68 static VhdlContainer s_str;
69 static QList<Entry>instFiles;
70 static int yyLineNr;
71 static Entry* lastCompound;
72 static Entry* currentCompound;
73 static Entry* lastEntity;
74 static Entry* current;
75 static Entry* tempEntry;
76 static Entry* current_root;
77 static QCString compSpec;
78 static QCString currName;
79 static int levelCounter;
80 static QCString confName;
81 static QCString genLabels;
82
83 static QList<VhdlConfNode> configL;
84 static VhdlConfNode* currNode;
85
86 static int currP=0;
87
88 enum  { GEN_SEC=0x1, PARAM_SEC,CONTEXT_SEC,PROTECTED_SEC } ;
89
90 static int param_sec = 0;
91 static int parse_sec=0;
92
93
94 //---------------------------- function --------------------------------------------------------------------------------
95
96 int vhdlScanYYlex ();
97 void vhdlScanYYerror (char const *);
98
99 static void addVhdlType(const QCString &name,int startLine,
100                         int section,int spec,
101                         const char* args,const char* type,
102                         Protection prot=Public);
103 static void addCompInst(char *n, char* instName,char* comp,int line);
104
105 static void newEntry();
106 static void initEntry(Entry *e);
107 static bool isFuncProcProced();
108 static void popConfig();
109 static void pushLabel(const QCString &label);
110 static void popLabel();
111 static void addConfigureNode(const char* a,const char*b,
112                          bool isRoot,bool isLeave,bool inlineConf=FALSE);
113 //static bool addLibUseClause(const QCString &type);
114 static bool isFuncProcProced();
115 static void initEntry(Entry *e);
116 static void addProto(const char *s1,const char *s2,const char *s3,
117                      const char *s4,const char *s5,const char *s6);
118 static void createFunction(const QCString &impure,int spec,
119                            const QCString &fname);
120
121 void newVhdlEntry()
122 {
123   newEntry();
124 }
125
126 Entry* getCurrentVhdlEntry()
127 {
128   return current;
129 }
130
131 void initVhdlParser()
132 {
133   lastCompound=0;
134   lastEntity=0;
135   currentCompound=0;
136   lastEntity=0;
137   current_root=s_str.root;
138   current=new Entry();
139   initEntry(current);
140 }
141
142 QList<Entry> & getVhdlInstList()
143 {
144   return instFiles;
145 }
146
147
148 %}
149
150 %token
151 t_ABSTRLIST
152 t_CHARLIST
153 t_DIGIT
154 t_STRING
155 t_LETTER
156 t_ACCESS
157 t_AFTER
158 t_ALIAS
159 t_ALL
160 t_AND
161 t_ARCHITECTURE
162 t_ARRAY
163 t_ASSERT
164 t_ATTRIBUTE
165 t_BEGIN
166 t_BLOCK
167 t_BODY
168 t_BUFFER
169 t_BUS
170 t_CASE
171 t_COMPONENT
172 t_CONFIGURATION
173 t_CONSTANT
174 t_DISCONNECT
175 t_DOWNTO
176 t_ELSE
177 t_ELSIF
178 t_END
179 t_ENTITY
180 t_EXIT
181 t_FILE
182 t_FOR
183 t_FUNCTION
184 t_GENERATE
185 t_GENERIC
186 t_GUARDED
187 t_IF
188 t_IN
189 t_INOUT
190 t_IS
191 t_LABEL
192 t_LIBRARY
193 t_LINKAGE
194 t_LOOP
195 t_MAP
196 t_NAND
197 t_NEW
198 t_NEXT
199 t_NOR
200 t_NULL
201 t_OF
202 t_ON
203 t_OPEN
204 t_OR
205 t_OTHERS
206 t_OUT
207 t_PACKAGE
208 t_PORT
209 t_PROCEDURE
210 t_PROCESS
211 t_RANGE
212 t_RECORD
213 t_REGISTER
214 t_REPORT
215 t_RETURN
216 t_SELECT
217 t_SEVERITY
218 t_SIGNAL
219 t_SUBTYPE
220 t_THEN
221 t_TO
222 t_TRANSPORT
223 t_TYPE
224 t_UNITS
225 t_UNTIL
226 t_USE
227 t_VARIABLE
228 t_WAIT
229 t_WHEN
230 t_WHILE
231 t_WITH
232 t_XOR
233
234 /* new keywords */
235 t_IMPURE
236 t_PURE
237 t_GROUP
238 t_POSTPONED
239 t_SHARED
240 t_XNOR
241 t_SLL
242 t_SRA
243 t_SLA
244 t_SRL
245 t_ROR
246 t_ROL
247 t_UNAFFECTED
248 /*============== VHDL 2008 keywords   ======================= */
249
250 t_ASSUME_GUARANTEE
251 t_ASSUME
252 t_CONTEXT
253 t_COVER
254 t_DEFAULT
255 t_FAIRNESS
256 t_FORCE
257 t_INERTIAL
258 t_LITERAL
259 t_PARAMETER
260 t_PROTECTED
261 t_PROPERTY
262 t_REJECT
263 t_RELEASE
264 t_RESTRICT
265 t_RESTRICT_GUARANTEE
266 t_SEQUENCE
267 t_STRONG
268 t_VMODE
269 t_VPROP
270 t_VUNIT
271
272
273 /*============== VHDL binary operators 2008   ======================= */
274
275 t_SLSL
276 t_SRSR
277 t_QQ
278 t_QGT
279 t_QLT
280 t_QG
281 t_QL
282 t_QEQU
283 t_QNEQU
284
285 %nonassoc t_EQSym t_NESym t_LTSym t_LESym t_GTSym t_GESym t_QNEQU t_QEQU t_QL t_QG t_QLT  t_QGT
286 %left t_Plus t_Minus t_Ampersand
287 %left MED_PRECEDENCE
288 %left t_Star t_Slash t_MOD t_REM
289 %nonassoc t_DoubleStar t_ABS t_NOT MAX_PRECEDENCE
290
291 /* misc syms */
292 /*t_Space */
293
294 %token
295 t_Apostrophe
296 t_LeftParen
297 t_RightParen
298 t_Comma
299 t_VarAsgn
300 t_Colon
301 t_Semicolon
302 t_Arrow
303 t_Box
304 t_Bar
305 t_Dot
306 t_Q
307 t_At
308 t_Neg
309 t_LEFTBR
310 t_RIGHTBR
311 t_ToolDir
312
313 %type<qstr> designator literal enumeration_literal physical_literal physical_literal_no_default physical_literal_1
314 %type<qstr> lib_clause use_clause sel_list entity_decl entity_start entity_decl_2 entity_decl_1 arch_body arch_start arch_body_1
315 %type<qstr> config_decl config_start config_decl_2 config_decl_1 config_decl_3 package_decl package_start package_body pack_body_start package_body_2 package_body_1 common_decltve_item
316 %type<qstr> config_decltve_item subprog_decl subprog_body interf_list interf_element interf_element_4 interf_element_3 interf_element_2 interf_element_1 mode
317 %type<qstr> association_list association_list_1 association_list_2 gen_association_list gen_association_list_1 gen_association_list_2 association_element gen_association_element formal_part actual_part mark expr and_relation relation primary name name2 sel_name suffix ifts_name
318 %type<qstr> attribute_name aggregate element_association_list2 qualified_expr element_association choices choices_1 choices_2 choice type_decl type_decl_1 type_definition enumeration_type_definition enumeration_type_definition_1 enumeration_type_definition_2 physical_type_definition physical_type_definition_1 physical_type_definition_2 base_unit_decl secondary_unit_decl unconstrained_array_definition unconstrained_array_definition_1 unconstrained_array_definition_2 index_subtype_definition constrained_array_definition record_type_definition record_type_definition_1 record_type_definition_2 element_decl
319 %type<qstr> access_type_definition file_type_definition subtype_decl subtype_indic subtype_indic_1 subtype_indic1 subtype_indic1_1 range_constraint index_constraint index_constraint_1 index_constraint_2 discrete_range discrete_range1 range_spec direction constant_decl constant_decl_1 signal_decl signal_decl_2 signal_decl_1 variable_decl variable_decl_1 object_class signal_kind alias_decl file_decl file_decl_1 attribute_decl attribute_spec entity_spec entity_name_list entity_name_list_1
320 %type<qstr> entity_name_list_2 entity_class block_stat
321 %type<qstr> generate_stat generate_stat_1 procs_stat procs_stat1 procs_stat1_1 sensitivity_list sensitivity_list_1 sensitivity_list_2
322 %type<qstr> procedure_call_stat comp_decl comp_decl_2 comp_decl_1 block_config block_config_2 block_config_3 block_config_1 block_config_4 block_spec config_item comp_config comp_config_2 comp_config_1 config_spec binding_indic comp_spec
323 %type<qstr> inst_list entity_aspect idf_list procs_stat1_6
324 %type<qstr> t_Identifier t_StringLit t_BitStringLit t_AbstractLit t_CharacterLit tbox group_name record_type_simple_name
325 %type<qstr> entity_class_entry_list entity_class_entry group_constituent_list group_constituent group_declaration group_template_declaration
326 %type<qstr> procs_stat1_5 comp_1 mark_comp dot_name fi_dec multiplying_operator factor term adding_op
327 %type<qstr> simple_exp alias_spec sigma signature1 mark_stats mark_stats_1 signature
328 %type<qstr> protected_type_body protected_type_declaration alias_name_stat vcomp_stat comp_spec_stat
329 %type<qstr> sig_stat external_name absolute_pathname relative_pathname package_path_name external_pathname pathname_element_list neg_list pathname_element
330
331 %type<qstr> func_name return_is param func_prec iproc ifunc interface_subprogram_decl interface_package_decl package_instantiation_decl
332 %type<qstr> subprogram_instantiation_decl
333 %type<qstr>  context_ref  libustcont_stats   libustcont_stat  context_decl
334
335
336 %debug
337
338 // for debugging set yydebug=1
339 %initial-action { yydebug=0; }
340
341 %expect 2
342
343 // minimum bison version
344 //%require "2.2"
345
346 %%
347 start: design_file
348
349
350 design_file     : design_unit_list
351
352 design_unit_list: design_unit
353                 | design_unit_list design_unit
354                 ;
355
356 designator      : t_Identifier                      { $$=$1; }
357                 | t_StringLit                       { $$=$1; }
358                 ;
359
360 literal         : t_AbstractLit                     { $$=$1; }
361                 | t_CharacterLit                    { $$=$1; }
362                 | t_BitStringLit                    { $$=$1; }
363                 | physical_literal_no_default       { $$=$1; }
364                 | t_NULL                            { $$="null"; }
365                 ;
366
367 enumeration_literal  : t_CharacterLit               { $$=$1; }
368                      | t_Identifier                 { $$=$1; }
369
370 physical_literal     : physical_literal_1 t_Identifier  { $$=$1+" "+$2; }
371
372 physical_literal_1   : /* empty */        { $$=""; }
373                      | t_AbstractLit      { $$=$1; }
374
375 physical_literal_no_default : t_AbstractLit t_Identifier   { $$=$1+" "+$2; }
376
377 idf_list : t_Identifier { $$=$1; }
378          | idf_list t_Comma t_Identifier { $$=$1+","+$3}
379          ;
380
381 /*------------------------------------------
382 --  Desing Unit
383 --------------------------------------------*/
384
385 design_unit      : context_list lib_unit
386
387 context_list     :  /* empty */
388                  | context_list context_item
389
390 lib_unit         : entity_decl
391                  | config_decl
392                  | package_decl
393                  | arch_body
394                  | package_body
395                  | context_decl
396                  | package_instantiation_decl
397                  ;
398
399 context_item     : lib_clause
400                  | use_clause
401                  ;
402
403 lib_clause       : t_LIBRARY idf_list t_Semicolon
404                  {
405                    if ( parse_sec == 0)
406                    {
407                     addVhdlType($2,getParsedLine(t_LIBRARY),Entry::VARIABLE_SEC,VhdlDocGen::LIBRARY,$2.data(),"_library_");
408                    }
409                    $$="library "+$2;
410                  }
411
412 use_clause : t_USE sel_list t_Semicolon
413                  {
414                    QStringList ql1=QStringList::split(",",$2,FALSE);
415                    for (uint j=0;j<ql1.count();j++)
416                    {
417                      QStringList ql=QStringList::split(".",ql1[j],FALSE);
418                      QCString it=ql[1].utf8();
419                      if ( parse_sec == 0 )
420                      {
421                        addVhdlType(it,getParsedLine(t_USE),Entry::VARIABLE_SEC,VhdlDocGen::USE,it.data(),"_use_");
422                      }
423                    }
424                    $$="use "+$2;
425                  }
426
427 sel_list    : sel_name { $$=$1; }
428             | sel_list t_Comma sel_name { $$=$1+","+$3; }
429             ;
430 /*------------------------------------------
431 --  Library Units
432 --------------------------------------------*/
433
434 entity_decl : entity_start error comp_end_dec  t_Semicolon
435
436 entity_decl : entity_start entity_decl_1 entity_decl_2
437                      entity_decl_3 entity_decl_4   comp_end_dec  t_Semicolon
438
439 entity_start: t_ENTITY t_Identifier t_IS
440               {
441                 $$=$2;
442                 lastEntity=current;
443                 lastCompound=0;
444                 /*int k=*/ getParsedLine(t_ENTITY);
445                 addVhdlType($$,getParsedLine(t_ENTITY),Entry::CLASS_SEC,VhdlDocGen::ENTITY,0,0,Public);
446                 //fprintf(stderr,"\n entiy %s : at line %d",$$.data(),s_str.yyLineNr);
447               }
448               ;
449
450 entity_decl_5 :   /* empty */
451               |  t_Identifier
452               ;
453 entity_decl_4 :  /* empty */
454               | t_BEGIN concurrent_stats
455               ;
456 entity_decl_3 :  /* empty */
457               | entity_decl_3 entity_decl_6
458               ;
459
460 entity_decl_6 : entity_decltve_item
461
462 entity_decl_2 : /* empty */  { $$=""; }
463               | t_PORT { currP=VhdlDocGen::PORT; }  interf_list t_Semicolon  { currP=0; }
464               ;
465 entity_decl_1 :  /* empty */  { $$=""; }
466               | t_GENERIC { currP=VhdlDocGen::GENERIC;parse_sec=GEN_SEC} interf_list t_Semicolon{ currP=0;parse_sec=0; }
467               | t_GENERIC error t_Semicolon{ currP=0; }
468               ;
469
470
471 arch_body     : arch_start arch_body_1 t_BEGIN concurrent_stats t_END arch_body_2 t_Semicolon
472 arch_body     : arch_start error t_END arch_body_2 t_Semicolon
473
474 arch_start    : t_ARCHITECTURE t_Identifier t_OF t_Identifier t_IS
475                 {
476                   $$=$4;
477                   $$+="::";
478                   $$+=$2;
479                   pushLabel($2);
480                   lastCompound=current;
481                   addVhdlType($$,getParsedLine(t_ARCHITECTURE),Entry::CLASS_SEC,VhdlDocGen::ARCHITECTURE,0,0,Private);
482                 }
483 arch_body_2   : /* empty */
484 arch_body_2   : t_Identifier
485 arch_body_2   : t_ARCHITECTURE  t_Identifier
486 arch_body_2   : t_ARCHITECTURE
487
488 arch_body_1   : /* empty */  { $$=""; }
489 arch_body_1   : arch_body_1 arch_body_3
490
491 arch_body_3   :  block_decltve_item
492
493 config_decl   : config_start error  t_END config_decl_2 t_Semicolon { genLabels.resize(0); }
494 config_decl   : config_start config_decl_1 block_config t_END config_decl_2 t_Semicolon { genLabels.resize(0); }
495                 {
496                   confName="";
497                 }
498
499
500 config_start  : t_CONFIGURATION t_Identifier t_OF t_Identifier t_IS
501                 {
502                   confName=$2+"::"+$4;
503                   addVhdlType($2.data(),getParsedLine(t_CONFIGURATION),Entry::VARIABLE_SEC,VhdlDocGen::CONFIG,"configuration",$4.data());
504                 }
505
506 config_decl_2 : /* empty */     { $$=""; }
507 config_decl_2 : t_Identifier    { $$=$1; }
508 config_decl_2 : t_CONFIGURATION { $$="configuration"; }
509 config_decl_2 : t_CONFIGURATION t_Identifier  { $$=$2; }
510 config_decl_1 :  /* empty */    { $$=""; }
511 config_decl_1 : config_decl_1 config_decl_3   { $$=$1+" "+$2; }
512 config_decl_3 : config_decltve_item           { $$=$1; }
513
514 package_decl  : package_start error t_END package_decl_2 t_Semicolon
515 package_decl  : package_start package_decl_1 t_END package_decl_2 t_Semicolon
516 package_start : t_PACKAGE t_Identifier t_IS
517                            {
518                           lastCompound=current;
519
520
521          Entry *clone=new Entry(*current);
522          clone->section=Entry::NAMESPACE_SEC;
523          clone->spec=VhdlDocGen::PACKAGE;
524            clone->name=$2;
525            int line=s_str.iLine;
526          clone->startLine=line;
527            clone->bodyLine=line;
528
529          clone->protection=Package;
530              current_root->addSubEntry(clone);
531
532
533                         addVhdlType($2,line,Entry::CLASS_SEC,VhdlDocGen::PACKAGE,0,0,Package);
534                         //fprintf(stderr,"\n entiy %s : at line %d",$$.data(),s_str.yyLineNr);
535                        }
536
537 package_decl_2     :  /* empty */
538 package_decl_2     : t_Identifier  { lastCompound=0; }
539 package_decl_2     : t_PACKAGE t_Identifier { lastCompound=0; }
540 package_decl_2     : t_PACKAGE { lastCompound=0; }
541
542 package_decl_1     :  /* empty */
543 package_decl_1    : package_decl_22
544 package_decl_1     : package_decl_1 package_decl_3
545 package_decl_3     : package_decltve_item
546
547 package_decl_22: gen_interface_list t_Semicolon
548 package_decl_22: gen_interface_list
549 package_decl_22: gen_interface_list gen_assoc_list
550 package_decl_22: gen_interface_list gen_assoc_list t_Semicolon
551
552 package_body    : pack_body_start error t_END package_body_2 t_Semicolon
553 package_body    : pack_body_start package_body_1 t_END package_body_2 t_Semicolon
554 pack_body_start : t_PACKAGE t_BODY t_Identifier t_IS
555                       {
556                         $$=$3;
557                         lastCompound=current;
558                         $$.prepend("_");
559                         addVhdlType($$,getParsedLine(t_PACKAGE) ,Entry::CLASS_SEC,VhdlDocGen::PACKAGE_BODY,0,0,Protected);
560                       }
561 package_body_2  :  /* empty */  { $$="";lastCompound=0; }
562 package_body_2  : t_Identifier                                            { lastCompound=0; }
563 package_body_2  : t_PACKAGE t_BODY                         { lastCompound=0; }
564 package_body_2  : t_PACKAGE t_BODY t_Identifier      { lastCompound=0; }
565
566
567 package_body_1  :  /* empty */  { $$=""; }
568 package_body_1  : package_body_1 package_body_3
569 package_body_3  : package_body_decltve_item
570
571
572
573 /*------------------------------------------
574 --  Declarative Item
575 --------------------------------------------*/
576
577 common_decltve_item_1: package_decl
578 common_decltve_item_1: package_instantiation_decl
579 common_decltve_item_1: package_body
580 common_decltve_item_1: subprogram_instantiation_decl
581
582
583 common_decltve_item: type_decl
584 common_decltve_item: subtype_decl
585 common_decltve_item: constant_decl
586 common_decltve_item: file_decl
587 common_decltve_item: alias_decl
588 common_decltve_item: subprog_decl
589 common_decltve_item: use_clause
590
591 entity_decltve_item: common_decltve_item
592 entity_decltve_item: subprog_body
593 entity_decltve_item: attribute_decl
594 entity_decltve_item: attribute_spec
595 entity_decltve_item: disconnection_spec
596 entity_decltve_item: signal_decl
597 entity_decltve_item: variable_decl
598 entity_decltve_item: group_template_declaration
599 entity_decltve_item: group_declaration
600 entity_decltve_item: common_decltve_item_1
601
602
603 block_decltve_item: common_decltve_item
604 block_decltve_item: subprog_body
605 block_decltve_item: comp_decl
606 block_decltve_item: attribute_decl
607 block_decltve_item: attribute_spec
608 block_decltve_item: config_spec
609 block_decltve_item: disconnection_spec
610 block_decltve_item: signal_decl
611 block_decltve_item: variable_decl
612 block_decltve_item: group_template_declaration
613 block_decltve_item: group_declaration
614 block_decltve_item: common_decltve_item_1
615 block_decltve_item: tool_directive
616
617 block_declarative_part: block_decltve_item
618                       | block_declarative_part  block_decltve_item
619
620
621 package_decltve_item: common_decltve_item
622 package_decltve_item: comp_decl
623 package_decltve_item: attribute_decl
624 package_decltve_item: attribute_spec
625 package_decltve_item: disconnection_spec
626 package_decltve_item: signal_decl
627 package_decltve_item: variable_decl
628 package_decltve_item: group_template_declaration
629 package_decltve_item: group_declaration
630 package_decltve_item: package_decl
631 package_decltve_item: package_instantiation_decl
632 package_decltve_item: subprogram_instantiation_decl
633
634 package_body_decltve_item: common_decltve_item
635 package_body_decltve_item: subprog_body
636 package_body_decltve_item: variable_decl
637 package_body_decltve_item: group_template_declaration
638 package_body_decltve_item: group_declaration
639 package_body_decltve_item: attribute_decl
640 package_body_decltve_item: attribute_spec
641 package_body_decltve_item: common_decltve_item_1
642
643 subprog_decltve_item: common_decltve_item
644 subprog_decltve_item: subprog_body
645 subprog_decltve_item: attribute_decl
646 subprog_decltve_item: attribute_spec
647 subprog_decltve_item: variable_decl
648 subprog_decltve_item: group_template_declaration
649 subprog_decltve_item: group_declaration
650 subprog_decltve_item: common_decltve_item_1
651
652 procs_decltve_item: common_decltve_item
653 procs_decltve_item: subprog_body
654 procs_decltve_item: attribute_decl
655 procs_decltve_item: attribute_spec
656 procs_decltve_item: variable_decl
657 procs_decltve_item: group_template_declaration
658 procs_decltve_item: group_declaration
659 procs_decltve_item: common_decltve_item_1
660
661 config_decltve_item: attribute_spec    { $$=$1; }
662 config_decltve_item: use_clause        { $$=$1; }
663 config_decltve_item: group_declaration { $$=$1; }
664 config_decltve_item: t_USE t_VUNIT idf_list t_Semicolon { $$=$3; }
665
666 /*------------------------------------------
667 --  Subprograms
668 --------------------------------------------*/
669 func_prec: t_PURE { $$="pure"; }
670 func_prec: t_IMPURE { $$="impure"; }
671
672 subprog_decl: subprog_spec t_Semicolon { currP=0; }
673
674 subprog_spec: t_PROCEDURE t_Identifier
675               { currP=VhdlDocGen::PROCEDURE; createFunction($2,currP,0); }
676               subprog_spec_1 {  newEntry(); }
677 subprog_spec: func_prec t_FUNCTION designator
678               {
679                 currP=VhdlDocGen::FUNCTION;
680                 createFunction($1,currP,$3.data());
681               }
682               subprog_spec_2 t_RETURN mark
683               {
684                 tempEntry=current;
685                 current->type=$7;
686                 newEntry();
687               }
688
689 subprog_spec  :  t_FUNCTION designator
690               {
691                 currP=VhdlDocGen::FUNCTION;
692                 createFunction(0,currP,$2.data());
693               }
694               subprog_spec_2 t_RETURN mark
695               {
696                 tempEntry=current;
697                 current->type=$6;
698                 newEntry();
699               }
700
701 subprog_spec_22: gen_interface_list
702 subprog_spec_22: gen_interface_list gen_assoc_list
703
704 subprog_spec_33: t_PARAMETER
705                  { param_sec=PARAM_SEC; }
706                  interf_list
707                  { param_sec= 0; }
708 subprog_spec_33: { param_sec=PARAM_SEC; }
709                  interf_list
710                  { param_sec= 0; }
711
712 subprog_spec_2:  /* empty */
713 subprog_spec_2: subprog_spec_22 subprog_spec_33
714 subprog_spec_2: subprog_spec_33
715 subprog_spec_2: subprog_spec_22
716
717 subprog_spec_1: subprog_spec_2
718
719 subprog_body: subprog_spec t_IS  subprog_body_1 t_BEGIN   seq_stats t_END subprog_body_2 t_Semicolon
720     {
721       currP=0;
722     }
723 subprog_body: subprog_spec t_IS error  t_END subprog_body_2 t_Semicolon
724     {
725       currP=0;
726     }
727 subprog_body_2:  /* empty */
728 subprog_body_2: designator
729 subprog_body_2: t_FUNCTION
730 subprog_body_2: t_PROCEDURE
731 subprog_body_2: t_PROCEDURE t_Identifier
732 subprog_body_2: t_FUNCTION t_Identifier
733 subprog_body_2: t_FUNCTION t_STRING
734
735
736 subprog_body_1:  /* empty */
737 //subprog_body_1    :  subprogram_instantiation_decl
738 subprog_body_1: subprog_body_1 subprog_body_3
739 subprog_body_3: subprog_decltve_item
740
741 /*--------------------------------------------------
742 --  Interface Lists and Associaton Lists
743 ----------------------------------------------------*/
744
745 interf_list:   t_LeftParen interf_element interf_list_1 t_RightParen   { $$=""; }
746 interf_list:   t_LeftParen error t_RightParen   { $$=""; }
747 interf_list_1:  /* empty */
748 interf_list_1: interf_list_1 interf_list_2
749 interf_list_2: t_Semicolon interf_element
750
751 interf_element: interface_package_decl
752                   {
753                     // adding generic :  [ package foo  is new bar]
754                     if (parse_sec==GEN_SEC)
755                     {
756                       QCString n=current->name;
757                       addVhdlType(n.data(),getParsedLine(t_PACKAGE),Entry::VARIABLE_SEC,VhdlDocGen::GENERIC,$1.data(),0);
758                     }
759                   }
760 interf_element: interface_subprogram_decl
761                   {
762                     if (parse_sec==GEN_SEC)
763                     {
764                       int a=getParsedLine(t_FUNCTION);
765                       int b=getParsedLine(t_PROCEDURE);
766
767                       if (a>b) b=a;
768
769                       QCString n=current->name;
770                       addVhdlType(n.data(),b,Entry::VARIABLE_SEC,VhdlDocGen::GENERIC,$1.data(),0);
771                     }
772                   }
773 interf_element: interf_element_1 t_Identifier
774                   {
775                     if (parse_sec==GEN_SEC)
776                     {
777                       QCString v= $1;
778                       addVhdlType($2,s_str.iLine,Entry::VARIABLE_SEC,currP,$1.data(),0);
779                     }
780                   }
781 interf_element: interf_element_1 idf_list t_Colon interf_element_2 subtype_indic interf_element_3 interf_element_4
782                   {
783                     QCString b=$2;
784                     $$=$2+":"+$4+$5+$6+$7;
785                     if (currP!=VhdlDocGen::COMPONENT)
786                     {
787                       if (currP==VhdlDocGen::FUNCTION || currP==VhdlDocGen::PROCEDURE)
788                       {
789                         addProto($1.data(),$2.data(),$4.data(),$5.data(),$6.data(),$7.data());
790                       }
791                       else
792                       {
793                         QCString i=$5+$6+$7;
794                         if (currP==VhdlDocGen::GENERIC)
795                           addVhdlType($2,s_str.iLine,Entry::VARIABLE_SEC,currP,i.data(),$4.data());
796                         else if(parse_sec != GEN_SEC)
797                           addVhdlType($2,s_str.iLine,Entry::VARIABLE_SEC,currP,i.data(),$4.data());
798                       }
799                       //   fprintf(stderr,"\n\n <<port  %s  >>\n",$$.data());
800                     } // if component
801                   }
802 interf_element_4: /* empty :=*/   { $$=""; }
803 interf_element_4: t_VarAsgn expr  { $$=":="+$2; }
804 interf_element_3: /* empty */     { $$=""; }
805 interf_element_3: t_BUFFER        { $$="buffer"; }
806 interf_element_3: t_BUS           { $$="bus"; }
807 interf_element_2: /* empty */     { $$=""; }
808 interf_element_2: mode            { $$=$1; }
809 interf_element_1: /* empty */     { $$=""; }
810 interf_element_1: object_class    { $$=$1; }
811
812 mode: t_IN                        { $$="in"; }
813 mode: t_OUT                       { $$="out"; }
814 mode: t_INOUT                     { $$="inout"; }
815 mode: t_BUFFER                    { $$="buffer"; }
816 mode: t_LINKAGE                   { $$="link"; }
817
818 association_list:   t_LeftParen association_element association_list_1 t_RightParen  { $$="("+$2+")"; }
819 association_list_1:  /* empty */                           { $$=""; }
820 association_list_1: association_list_1 association_list_2  { $$=$1+" "+$2; }
821 association_list_2: t_Comma association_element            { $$=", "+$2; }
822
823 gen_association_list : t_LeftParen gen_association_element gen_association_list_1 t_RightParen
824     {
825       QCString str="( "+$2;
826       str.append(" )");
827       $$=str;
828     }
829 gen_association_list: t_LeftParen  error t_RightParen { $$=""; }
830 gen_association_list: t_LeftParen t_OPEN t_RightParen { $$=" ( open ) "; }
831
832 gen_association_list_1:  /* empty */  { $$=""; }
833 gen_association_list_1: gen_association_list_1   gen_association_list_2  { $$=$1+"?? "+$2; }
834 gen_association_list_2: t_Comma gen_association_element { $$=","+$2; }
835
836 association_element: formal_part t_Arrow actual_part { $$=$1+"=>"+$3; }
837 association_element: actual_part { $$=$1; }
838 association_element: t_Box       { $$="<>"; }
839 association_element: t_DEFAULT   { $$="default"; }
840
841 /* changed ;gen_association_element   : association_element  */
842 gen_association_element: expr            { $$=$1; }
843 gen_association_element: choice t_Arrow expr
844 gen_association_element: discrete_range1 {  $$=$1 ; }
845
846 formal_part: name  { $$=$1; }
847
848 actual_part: expr      { $$=$1; }
849 actual_part: t_OPEN    { $$="open"; }
850 actual_part: t_INERTIAL expr    { $$="inertial"; }
851
852 /*--------------------------------------------------
853 --  Names and Expressions
854 ----------------------------------------------------*/
855
856
857
858 expr: and_relation  { $$=$1; }
859 expr: relation  { $$=$1; }
860
861 shift_op: t_SLL
862         | t_SRA
863         | t_SLA
864         | t_SRL
865         | t_ROR
866         | t_ROL
867         ;
868 and_relation: relation shift_op relation
869 and_relation: relation t_AND    relation
870 and_relation: relation t_XOR    relation
871 and_relation: relation t_OR     relation
872 and_relation: relation t_NOR    relation
873 and_relation: relation t_XNOR   relation
874 and_relation: relation t_NAND   relation
875 and_relation: and_relation t_NAND relation
876 and_relation: and_relation t_NOR  relation
877 and_relation: and_relation t_XNOR relation
878 and_relation: and_relation t_AND  relation
879 and_relation: and_relation t_OR   relation
880 and_relation: and_relation t_XOR  relation
881
882 /* ;relation   : unary_operator primary   */
883
884 relation: t_QQ primary                         { $$=" ?? "+$2; }
885 relation: primary                              { $$=$1; }
886 relation: t_Plus primary  %prec MED_PRECEDENCE { $$="+"+$2; }
887 relation: t_Minus primary %prec MED_PRECEDENCE { $$="-"+$2; }
888 relation: t_ABS primary                        { $$="abs"+$2; }
889 relation: t_NOT primary                        { $$="not "+$2; }
890 relation: primary t_DoubleStar primary         { $$=$1+" ** "+$3; }
891 relation: t_Minus primary t_DoubleStar primary { $$=$2+" ** "+$4; }
892
893 /* ;    relation : relation binary_operator primary */
894
895 relation: relation t_MOD   relation       { $$=$1+" mod  "+$3; }
896 relation: relation t_REM   relation       { $$=$1+" rem "+$3;  }
897 relation: relation t_Ampersand relation   { $$=$1+" & "+$3;    }
898 relation: relation t_Star  relation       { $$=$1+" * "+$3;    }
899 relation: relation t_Plus  relation       { $$=$1+" + "+$3;    }
900 relation: relation t_Minus relation       { $$=$1+" -  "+$3;   }
901 relation: relation t_LESym relation       { $$=$1+" <= "+$3;   }
902 relation: relation t_GESym relation       { $$=$1+" >= "+$3;   }
903 relation: relation t_LTSym relation       { $$=$1+" <  "+$3;   }
904 relation: relation t_GTSym relation       { $$=$1+" >  "+$3;   }
905 relation: relation t_EQSym relation       { $$=$1+" ==  "+$3;  }
906 relation: relation t_NESym relation       { $$=$1+" != "+$3;   }
907 relation: relation t_Slash relation       { $$=$1+" /"+$3;     }
908 relation: relation t_QNEQU relation       { $$=$1+" ?/="+$3;   }
909 relation: relation t_QEQU  relation       { $$=$1+" ?="+$3;    }
910 relation: relation t_QL    relation       { $$=$1+" ?<"+$3;    }
911 relation: relation t_QG    relation       { $$=$1+" ?>"+$3;    }
912 relation: relation t_QLT   relation       { $$=$1+" ?<="+$3;   }
913 relation: relation t_QGT   relation       { $$=$1+" ?>="+$3;   }
914
915 simple_exp: t_Minus  term  { $$ = "-"+$2; }
916           | t_Plus term    { $$ = "+"+$2; }
917           | term           { $$ = $1; }
918           | simple_exp
919             adding_op term { $$ = $1+" "+$2+" "+$3; }
920
921 adding_op: t_Ampersand { $$ = "&"; }
922          | t_Minus     { $$ = "-"; }
923          | t_Plus      { $$ = "+"; }
924          ;
925
926 term: factor { $$=$1; }
927     | factor multiplying_operator factor { $$ = $1+" "+$2+" "+$3; }
928     ;
929
930 multiplying_operator: t_Star  { $$ = "*";   }
931                     | t_REM   { $$ = "rem"; }
932                     | t_MOD   { $$ = "mod"; }
933                     | t_Slash { $$ = "/";   }
934
935 factor: primary                        { $$=$1; }
936       | t_ABS  primary                 { $$="abs "+$2; }
937       | t_NOT  primary                 { $$="not  "+$2; }
938       |  primary t_DoubleStar  primary { $$ = $1+" ** "+$3; }
939
940 primary: name                          { $$=$1; }
941 primary: literal                       { $$=$1; }
942 primary: aggregate                     { $$=$1; }
943 primary: qualified_expr                { $$=$1; }
944 primary: allocator                     { $$=""; }
945 primary: t_LeftParen expr t_RightParen { $$="("+$2+")"; }
946
947 name:  mark           { $$=$1; }
948 name:  name2          { $$=$1; }
949 name:  external_name  { $$=$1; }
950 name2: t_StringLit    { $$=$1; }
951 name2: attribute_name { $$=$1; }
952 name2: ifts_name      { $$=$1; }
953
954 mark: t_Identifier    { $$=$1; }
955 mark: sel_name        { $$=$1; }
956
957 sel_name: name t_Dot suffix   { $$=$1+"."+$3; }
958
959 suffix: designator     { $$=$1; }
960 suffix: t_CharacterLit { $$=$1; }
961 suffix: t_ALL          { $$="all"; }
962
963 ifts_name: mark  gen_association_list { $$=$1+" "+$2; }
964 ifts_name: name2 gen_association_list { $$=$1+" "+$2; }
965
966 sigma:  t_Apostrophe { $$="'"; }
967 //sigma :  t_LEFTBR signature1 t_RIGHTBR  t_Apostrophe { $$="("+$2;;$$.append(")");$$.append("'"); }
968
969 attribute_name: mark  sigma t_Identifier   { $$=$1+"' "+$3; }
970 attribute_name: attribute_name t_LeftParen expr t_RightParen
971 attribute_name: name2 sigma t_Identifier   { $$=$1+" '"+$3; }
972 attribute_name: mark  sigma t_RANGE        { $$=$1+"' range "; }
973 attribute_name: name2 sigma t_RANGE        { $$=$1+"' range "; }
974
975 aggregate  : element_association_list2 t_RightParen  { $$=$1+" ) "; }
976 aggregate  : t_LeftParen choices t_Arrow expr t_RightParen  { $$="( "+$2+ "=>"+$4+" ) "; }
977
978 element_association_list2 : t_LeftParen element_association t_Comma element_association  { $$=" ( "+$2+","+$4; }
979 element_association_list2 : element_association_list2 t_Comma element_association   { $$=$1+","+$3; }
980
981 qualified_expr : mark t_Apostrophe t_LeftParen expr  t_RightParen { $$=$1+"'("+$4+" ) "; }
982 qualified_expr : mark t_Apostrophe aggregate  { $$=$1+"'"+$3; }
983
984 allocator: t_NEW mark mark allocator_1
985 allocator: t_NEW mark allocator_2
986 allocator: t_NEW qualified_expr
987 allocator_2:  /* empty */
988 allocator_2: gen_association_list
989 allocator_1:  /* empty */
990 allocator_1: gen_association_list
991
992
993 /*--------------------------------------------------
994 --  Element Association and Choices
995 ----------------------------------------------------*/
996
997 element_association: choices t_Arrow expr { $$=$1+"=> "+$3; }
998 element_association: expr                 { $$=$1; }
999
1000 choices: choice choices_1      { $$=$1+" "+$2; }
1001 choices_1:  /* empty */        { $$="";        }
1002 choices_1: choices_1 choices_2 { $$=$1+" "+$2; }
1003 choices_2: t_Bar choice        { $$=" | "+$2;  }
1004
1005 choice: expr                   { $$=$1; }
1006 choice: discrete_range1        { $$=$1; }
1007 choice: t_OTHERS               { $$="others"; }
1008
1009 /*--------------------------------------------------
1010 --      Type Declarations
1011 ----------------------------------------------------*/
1012 type_decl: t_TYPE t_Identifier error t_Semicolon  { $$=""; }
1013 type_decl: t_TYPE t_Identifier type_decl_1 t_Semicolon
1014            {
1015              addVhdlType($2,getParsedLine(t_TYPE),Entry::VARIABLE_SEC,VhdlDocGen::TYPE,0,$3.data());
1016            }
1017 type_decl: t_TYPE error t_Semicolon { $$=""; }
1018
1019 type_decl_1:  /* empty */           { $$=""; }
1020 type_decl_1: t_IS type_definition   { $$="is "+$2; }
1021
1022 type_definition: enumeration_type_definition    { $$=$1; }
1023 type_definition: range_constraint               { $$=$1; }
1024 type_definition: physical_type_definition       { $$=$1; }
1025 type_definition: unconstrained_array_definition { $$=$1; }
1026 type_definition: constrained_array_definition   { $$=$1; }
1027 type_definition: record_type_definition         { $$=$1; }
1028 type_definition: access_type_definition         { $$=$1; }
1029 type_definition: file_type_definition           { $$=$1; }
1030 type_definition: protected_type_declaration     { $$=$1; }
1031 type_definition: protected_type_body            { $$=$1; }
1032
1033
1034 enumeration_type_definition:   t_LeftParen enumeration_literal enumeration_type_definition_1 t_RightParen { $$="( "+$2+" "+$3+" )"; }
1035 enumeration_type_definition_1: { $$=""; }
1036 enumeration_type_definition_1: enumeration_type_definition_1 enumeration_type_definition_2 { $$=$1+" "+$2; }
1037 enumeration_type_definition_2: t_Comma enumeration_literal { $$=","+$2; }
1038
1039 physical_type_definition : range_constraint  t_UNITS base_unit_decl
1040                            physical_type_definition_1 t_END unit_stat
1041                            {
1042                              $$=$1;
1043                              current->args=$3+"#"+$4;
1044                              current->args.prepend("units");
1045                              current->spec=VhdlDocGen::UNITS;
1046                            }
1047
1048 unit_stat: t_UNITS t_Identifier
1049 unit_stat: t_UNITS
1050
1051 physical_type_definition_1: /* empty */ { $$=""; }
1052 physical_type_definition_1: physical_type_definition_1 physical_type_definition_2 { $$=$1+" "+$2; }
1053 physical_type_definition_2: secondary_unit_decl  { $$=$1+"#"; }
1054
1055 base_unit_decl: t_Identifier t_Semicolon { $$=$1; }
1056
1057 secondary_unit_decl: t_Identifier t_EQSym physical_literal t_Semicolon { $$=$1+"="+$3 }
1058
1059 unconstrained_array_definition: t_ARRAY t_LeftParen
1060                                 index_subtype_definition unconstrained_array_definition_1 t_RightParen t_OF
1061                                 subtype_indic
1062     {
1063       QCString sr1=" array ( "+$3+" "+$4;
1064       QCString sr2=" ) of "+$7;
1065       $$=sr1+sr2;
1066     }
1067
1068 unconstrained_array_definition_1: { $$=""; }
1069 unconstrained_array_definition_1: unconstrained_array_definition_1 unconstrained_array_definition_2 { $$=$1+"  "+$2 }
1070 unconstrained_array_definition_2: t_Comma index_subtype_definition { $$=", "+$2 }
1071
1072 index_subtype_definition: mark t_RANGE t_Box { $$=$1+" range<> "; }
1073
1074 constrained_array_definition: t_ARRAY index_constraint t_OF subtype_indic { $$=" array "+$2+" of "+$4; }
1075
1076 record_type_simple_name:/*empty*/     { $$=""; }
1077                        | t_Identifier { $$=$1; }
1078
1079 record_type_definition: t_RECORD element_decl record_type_definition_1 t_END
1080                         t_RECORD record_type_simple_name
1081     {
1082       QRegExp reg("[\\s]");
1083       QCString oo=$2+" "+$3;
1084       current->spec=VhdlDocGen::RECORD;
1085       current->args=oo;
1086       current->args.replace(reg,"%");
1087       current->args.prepend("record");
1088       $$=$2+" "+$3;
1089     }
1090
1091 record_type_definition_1: /*empty*/ { $$=""; }
1092 record_type_definition_1: record_type_definition_1 record_type_definition_2
1093     {
1094       $$=$1+" "+$2;
1095     }
1096 record_type_definition_2: element_decl { $$=$1; }
1097
1098 element_decl: idf_list t_Colon subtype_indic t_Semicolon { $$=$1+":"+$3+"#"; }
1099
1100 access_type_definition: t_ACCESS subtype_indic { $$="access "+$2; }
1101
1102 file_type_definition: t_FILE t_OF mark  { $$="file of "+$3; }
1103
1104 /*--------------------------------------------------
1105 --  Subtypes and Constraints
1106 ----------------------------------------------------*/
1107
1108 subtype_decl: t_SUBTYPE t_Identifier t_IS subtype_indic t_Semicolon
1109     {
1110       addVhdlType($2,getParsedLine(t_SUBTYPE),Entry::VARIABLE_SEC,VhdlDocGen::SUBTYPE,0,$4.data());
1111     }
1112 subtype_decl:     t_SUBTYPE error  t_Semicolon  { $$=""; }
1113 subtype_indic:    mark subtype_indic_1          { $$=$1+" "+$2; }
1114 subtype_indic:    subtype_indic1                { $$=$1; }
1115 subtype_indic_1:  /* empty */                   { $$=""; }
1116 subtype_indic_1:  gen_association_list          { $$=$1; }
1117
1118 subtype_indic1:   mark mark range_constraint    { $$=$1+" "+$2+" "+$3; }
1119 subtype_indic1:   mark range_constraint         { $$=$1+" "+$2; }
1120 subtype_indic1:   mark mark subtype_indic1_1    { $$=$1+" "+$2+" "+$3; }
1121 subtype_indic1_1:  /* empty */                  { $$=""; }
1122 subtype_indic1_1: gen_association_list          { $$=$1; }
1123
1124 range_constraint: t_RANGE range_spec            { $$="range "+$2; }
1125 //range_constraint        : array_constraint
1126
1127 index_constraint: t_LeftParen discrete_range
1128                   index_constraint_1
1129                   t_RightParen                  { $$="("+$2+" "+$3+")"; }
1130 index_constraint_1:  /* empty */                { $$=""; }
1131 index_constraint_1: index_constraint_1
1132                     index_constraint_2          { $$=$1+" "+$2; }
1133 index_constraint_2: t_Comma discrete_range      { $$=","+$2; }
1134
1135 discrete_range: subtype_indic                   { $$=$1; }
1136 discrete_range: range_spec                      { $$=$1; }
1137
1138 discrete_range1 : subtype_indic1                { $$=$1; }
1139 discrete_range1 : expr direction expr           { $$=$1+"  "+$2+"  "+$3; }
1140
1141 range_spec  : attribute_name                    { $$=$1; }
1142 range_spec  : simple_exp direction simple_exp   { $$=$1+"  "+$2+"  "+$3; }
1143
1144 direction  : t_TO     { $$=" to "; }
1145 direction  : t_DOWNTO { $$=" downto "; }
1146
1147 /*--------------------------------------------------
1148 --  Objects, Aliases, Files, Disconnections
1149 ----------------------------------------------------*/
1150
1151 constant_decl: t_CONSTANT idf_list t_Colon subtype_indic constant_decl_1 t_Semicolon
1152                                   {
1153                                     QCString it=$4+" "+$5;
1154                                     //  fprintf(stderr,"\n currP %d \n",currP);
1155                                     addVhdlType($2,getParsedLine(t_CONSTANT),Entry::VARIABLE_SEC,VhdlDocGen::CONSTANT,0,it.data());
1156                                   }
1157 constant_decl_1:  /* empty */     { $$="";      }
1158 constant_decl_1: t_VarAsgn expr   { $$=":="+$2; }
1159
1160 signal_decl: t_SIGNAL idf_list t_Colon subtype_indic signal_decl_1 signal_decl_2 t_Semicolon
1161                                   {
1162                                     QCString s=$4+" "+$6;
1163                                     addVhdlType($2,getParsedLine(t_SIGNAL),Entry::VARIABLE_SEC,VhdlDocGen::SIGNAL,0,s.data());
1164                                   }
1165 signal_decl_2:  /* empty */       { $$=""; }
1166 signal_decl_2: t_VarAsgn expr     { $$=":="+$2; }
1167 signal_decl_1:  /* empty */       { $$=""; }
1168 signal_decl_1: signal_kind        { $$=$1; }
1169
1170 variable_decl: t_VARIABLE idf_list t_Colon subtype_indic variable_decl_1 t_Semicolon
1171                                   {
1172                                     $$=$2+":"+$4+" "+$5;
1173                                   }
1174 variable_decl: t_SHARED t_VARIABLE idf_list t_Colon subtype_indic variable_decl_1 t_Semicolon
1175                                   {
1176                                     $$=$5+" "+$6;
1177                                     addVhdlType($3,getParsedLine(t_VARIABLE),Entry::VARIABLE_SEC,VhdlDocGen::SHAREDVARIABLE,0,$$.data());
1178                                   }
1179 variable_decl_1:  /* empty */     { $$=""; }
1180 variable_decl_1: t_VarAsgn expr   { $$=":="+$2; }
1181
1182 object_class: t_CONSTANT          { $$="constant"; }
1183 object_class: t_SIGNAL            { $$="signal"; }
1184 object_class: t_VARIABLE          { $$="variable"; }
1185 object_class: t_SHARED t_VARIABLE { $$="shared"; }
1186 object_class: t_FILE              { $$="file"; }
1187 object_class: t_TYPE              { $$="type"; }
1188
1189 signal_kind: t_BUS                { $$="bus"; }
1190 signal_kind: t_REGISTER           { $$="register"; }
1191
1192 alias_decl: t_ALIAS alias_name_stat alias_spec t_IS name signature t_Semicolon
1193                                   {
1194                                     QCString s=$3+" is "+$5+$6;
1195                                     addVhdlType($2,getParsedLine(t_ALIAS),Entry::VARIABLE_SEC,VhdlDocGen::ALIAS,0,s.data());
1196                                   }
1197 alias_decl: t_ALIAS alias_name_stat alias_spec t_IS error t_Semicolon { $$=""; }
1198
1199 alias_name_stat: t_Identifier     { $$=$1; }
1200 alias_name_stat: t_StringLit      { $$=$1; }
1201
1202 alias_spec :/*empty*/              { $$=""; }
1203            | t_Colon subtype_indic { $$=","+$2; }
1204            ;
1205
1206 file_decl: t_FILE idf_list t_Colon subtype_indic t_IS file_decl_1 expr t_Semicolon
1207            {
1208              addVhdlType($2,getParsedLine(t_FILE),Entry::VARIABLE_SEC,VhdlDocGen::VFILE,0,$4.data());
1209            }
1210
1211 file_decl: t_FILE idf_list t_Colon t_Identifier fi_dec t_Semicolon
1212            {
1213              QCString s=$4+" "+$5;
1214              addVhdlType($2,getParsedLine(t_FILE),Entry::VARIABLE_SEC,VhdlDocGen::VFILE,0,s.data());
1215            }
1216
1217 fi_dec: /*empty*/              { $$=""; }
1218       |  t_OPEN expr t_IS expr { $$="open "+$2+" is "+s_str.qstr; }
1219
1220
1221 file_decl_1:  /* empty */   { $$=""; }
1222 file_decl_1: mode           { $$=$1; }
1223
1224 disconnection_spec: t_DISCONNECT signal_list t_Colon mark t_AFTER expr t_Semicolon
1225
1226 signal_list:   name signal_list_1
1227 signal_list:   t_OTHERS
1228 signal_list:   t_ALL
1229 signal_list_1:  /* empty */
1230 signal_list_1: signal_list_1 signal_list_2
1231 signal_list_2: t_Comma name
1232
1233 /*--------------------------------------------------
1234 --  Attribute Declarations and Specifications
1235 ----------------------------------------------------*/
1236
1237 attribute_decl: t_ATTRIBUTE t_Identifier t_Colon mark t_Semicolon
1238                 {
1239                   addVhdlType($2,getParsedLine(t_ATTRIBUTE),Entry::VARIABLE_SEC,VhdlDocGen::ATTRIBUTE,0,$4.data());
1240                 }
1241
1242 attribute_spec: t_ATTRIBUTE t_Identifier t_OF entity_spec t_IS expr t_Semicolon
1243                 {
1244                   QCString oo=$4+" is "+$6;
1245                   addVhdlType($2,getParsedLine(t_ATTRIBUTE),Entry::VARIABLE_SEC,VhdlDocGen::ATTRIBUTE,0,oo.data());
1246                 }
1247
1248 entity_spec : entity_name_list signature  t_Colon entity_class { $$=$1+$2+":"+$4;}      
1249
1250 entity_name_list:   designator entity_name_list_1         { $$=$1+" "+$2; }
1251 entity_name_list:   t_OTHERS                              { $$="others";  }
1252 entity_name_list:   t_ALL                                 { $$="all";     }
1253 entity_name_list_1: /* empty */                           { $$="";        }
1254 entity_name_list_1: entity_name_list_1 entity_name_list_2 { $$=$1+" "+$2; }
1255 entity_name_list_2: t_Comma designator                    { $$=","+$2;    }
1256
1257 entity_class: t_ENTITY        { $$="entity";        }
1258 entity_class: t_ARCHITECTURE  { $$="architecture";  }
1259 entity_class: t_PACKAGE       { $$="package";       }
1260 entity_class: t_CONFIGURATION { $$="configuration"; }
1261 entity_class: t_COMPONENT     { $$="component";     }
1262 entity_class: t_LABEL         { $$="label";         }
1263 entity_class: t_TYPE          { $$="type";          }
1264 entity_class: t_SUBTYPE       { $$="subtype";       }
1265 entity_class: t_PROCEDURE     { $$="procedure";     }
1266 entity_class: t_FUNCTION      { $$="function";      }
1267 entity_class: t_SIGNAL        { $$="signal";        }
1268 entity_class: t_VARIABLE      { $$="variable";      }
1269 entity_class: t_CONSTANT      { $$="constant";      }
1270 entity_class: t_GROUP         { $$="group";         }
1271 entity_class: t_FILE          { $$="file";          }
1272 entity_class: t_UNITS         { $$="units";         }
1273 entity_class: t_LITERAL       { $$="literal";       }
1274 entity_class: t_SEQUENCE      { $$="sequence";      }
1275 entity_class: t_PROPERTY      { $$="property";      }
1276
1277
1278 /*--------------------------------------------------
1279 --  Schemes
1280
1281 --------------------------------------------------------------------------*/
1282
1283 if_generation_scheme: if_scheme
1284
1285 if_scheme: t_IF expr t_GENERATE  generate_statement_body  if_scheme_1 if_scheme_2
1286 if_scheme: t_IF lable expr t_GENERATE  generate_statement_body  if_scheme_1 if_scheme_2
1287
1288 if_scheme_2: /* empty */
1289 if_scheme_2: t_ELSE t_GENERATE  generate_statement_body
1290 if_scheme_2: t_ELSE lable t_GENERATE  generate_statement_body
1291 if_scheme_1: /* empty */
1292 if_scheme_1: if_scheme_1 if_scheme_3
1293 if_scheme_3: t_ELSIF expr t_GENERATE generate_statement_body
1294 if_scheme_3: t_ELSIF lable expr t_GENERATE generate_statement_body
1295
1296 generation_scheme: for_scheme
1297
1298 iteration_scheme: for_scheme
1299 iteration_scheme: while_scheme
1300
1301 for_scheme: t_FOR t_Identifier t_IN discrete_range
1302 for_scheme: t_FOR lable t_Identifier t_IN discrete_range
1303
1304 while_scheme: t_WHILE expr
1305
1306 /*--------------------------------------------------
1307 --  Concurrent Statements
1308 ----------------------------------------------------*/
1309
1310 concurrent_stats:   concurrent_stats_1
1311 concurrent_stats_1: /* empty */
1312 concurrent_stats_1: concurrent_stats_1 concurrent_stats_2
1313 concurrent_stats_2: concurrent_stat
1314
1315 concurrent_stat : block_stat
1316                 | concurrent_assertion_stat
1317                 | concurrent_procedure_call
1318                 | concurrent_signal_assign_stat
1319                 | comp_inst_stat
1320                 | generate_stat
1321                 | procs_stat
1322
1323 block_stat: t_Identifier t_Colon t_BLOCK block_stat_0 block_stat_1 block_stat_2
1324             block_stat_3 block_stat_4 t_BEGIN concurrent_stats t_END t_BLOCK block_stat_5
1325             t_Semicolon
1326 block_stat_5: /* empty */
1327 block_stat_5: t_Identifier
1328 block_stat_4: /* empty */
1329 block_stat_4: block_stat_4 block_stat_6
1330 block_stat_6: block_decltve_item
1331 block_stat_3: /* empty */
1332 block_stat_3: t_PORT interf_list t_Semicolon block_stat_7
1333 //block_sta_7:  /* empty */
1334 block_stat_7: t_PORT t_MAP association_list t_Semicolon
1335 block_stat_2: /* empty */
1336 block_stat_2: t_GENERIC interf_list t_Semicolon block_stat_8
1337 block_stat_8: /* empty */
1338 block_stat_8: t_GENERIC t_MAP association_list t_Semicolon
1339 block_stat_1: /* empty */
1340 block_stat_1: t_LeftParen expr t_RightParen  block_stat_0
1341 block_stat_0: /* empty */
1342 block_stat_0: t_IS
1343
1344 dot_name: t_Identifier                 { $$=$1; }
1345         | dot_name  t_Dot t_Identifier { $$=$1+"."+$3; }
1346         ;
1347
1348 mark_comp: dot_name  comp_1      { $$=$1+" "+$2; }
1349 mark_comp: dot_name              { $$=$1; }
1350
1351 comp_1: t_LeftParen t_Identifier  t_RightParen  { $$="("+$2+")"; }
1352
1353 vcomp_stat: t_CONFIGURATION      { $$="configurátion";yyLineNr=s_str.iLine; }
1354 vcomp_stat: t_ENTITY             { $$="entity";yyLineNr=s_str.iLine; }
1355 vcomp_stat: t_COMPONENT          { $$="component";yyLineNr=s_str.iLine; }
1356
1357 comp_inst_stat:  t_Identifier   t_Colon  name   { yyLineNr=s_str.iLine; }     t_GENERIC t_MAP association_list comp_inst_stat_1 t_Semicolon
1358                              {
1359                                 addCompInst($1.data(),$3.data(),0,yyLineNr);
1360                                }
1361 comp_inst_stat:  t_Identifier   t_Colon     name   { yyLineNr=s_str.iLine; }    t_PORT t_MAP association_list t_Semicolon
1362                               {
1363                                addCompInst($1.data(),$3.data(),0,yyLineNr);
1364                              }
1365
1366 comp_inst_stat:  t_Identifier  t_Colon   vcomp_stat  mark_comp    t_PORT t_MAP association_list t_Semicolon
1367                              {
1368                                   addCompInst($1.data(),$4.data(),$3.data(),yyLineNr);
1369                               }
1370 comp_inst_stat:  t_Identifier  t_Colon  vcomp_stat   mark_comp        t_GENERIC t_MAP association_list comp_inst_stat_1 t_Semicolon
1371                               {
1372                                 addCompInst($1.data(),$4.data(),$3.data(),yyLineNr);
1373                               }
1374 comp_inst_stat_1:  /* empty */
1375 comp_inst_stat_1: t_PORT t_MAP association_list
1376
1377 concurrent_assertion_stat:  t_Identifier t_Colon  assertion_stat
1378 concurrent_assertion_stat:  assertion_stat
1379
1380 concurrent_assertion_stat:  t_Identifier t_Colon  t_POSTPONED  assertion_stat
1381 concurrent_assertion_stat:   t_POSTPONED assertion_stat
1382
1383 concurrent_procedure_call: t_Identifier t_Colon procedure_call_stat
1384 concurrent_procedure_call: procedure_call_stat
1385
1386 concurrent_procedure_call: t_Identifier t_Colon t_POSTPONED procedure_call_stat
1387 concurrent_procedure_call: t_POSTPONED procedure_call_stat
1388
1389 concurrent_signal_assign_stat: t_Identifier t_Colon condal_signal_assign
1390 concurrent_signal_assign_stat: condal_signal_assign
1391
1392 concurrent_signal_assign_stat: t_Identifier t_Colon  t_POSTPONED  condal_signal_assign
1393 concurrent_signal_assign_stat: t_POSTPONED  condal_signal_assign
1394
1395 concurrent_signal_assign_stat: t_Identifier t_Colon t_POSTPONED sel_signal_assign
1396 concurrent_signal_assign_stat: t_POSTPONED sel_signal_assign
1397
1398 concurrent_signal_assign_stat: t_Identifier t_Colon sel_signal_assign
1399 concurrent_signal_assign_stat: sel_signal_assign
1400
1401 condal_signal_assign: target t_LESym opts   condal_wavefrms t_Semicolon
1402
1403 condal_wavefrms: wavefrm
1404 condal_wavefrms: wavefrm t_WHEN expr
1405 condal_wavefrms: wavefrm t_WHEN expr t_ELSE condal_wavefrms
1406
1407 wavefrm:   wavefrm_element wavefrm_1
1408 wavefrm:   t_UNAFFECTED
1409 wavefrm_1: /* empty */
1410 wavefrm_1: wavefrm_1 wavefrm_2
1411 wavefrm_2: t_Comma wavefrm_element
1412
1413 wavefrm_element:   expr wavefrm_element_1
1414 wavefrm_element_1: /* empty */
1415 wavefrm_element_1: t_AFTER expr
1416 wavefrm_element_1: t_NULL wavefrm_element_2
1417 wavefrm_element_1: t_NULL
1418 wavefrm_element_2: t_AFTER expr
1419
1420 target: name
1421 target: aggregate
1422
1423 opts: opts_1 opts_2
1424
1425 opts_2: /* empty */
1426 opts_2: t_TRANSPORT
1427 opts_2: t_REJECT expr t_INERTIAL
1428 opts_2: t_INERTIAL
1429
1430 opts_1: /* empty */
1431 opts_1: t_GUARDED
1432
1433 sel_signal_assign: t_WITH expr t_SELECT target t_LESym opts sel_wavefrms t_Semicolon
1434
1435 sel_wavefrms:   sel_wavefrms_1 wavefrm t_WHEN choices
1436 sel_wavefrms_1: /* empty */
1437 sel_wavefrms_1: sel_wavefrms_1 sel_wavefrms_2
1438 sel_wavefrms_2: wavefrm t_WHEN choices t_Comma
1439
1440 gen_stat1: /* empty */
1441         |  block_declarative_part  t_BEGIN
1442         | t_BEGIN
1443
1444  // problem with double end
1445  // end;
1446  // end generate;
1447
1448 generate_statement_body:  gen_stat1 concurrent_stats
1449
1450 generate_stat : t_Identifier  t_Colon
1451                 { pushLabel($1); }
1452                 generation_scheme t_GENERATE
1453                 gen_stat1 concurrent_stats  opstat
1454
1455 // stems from VHDL 2008 generate_statement_body
1456 opstat: end_stats t_END generate_stat_1 t_Semicolon { popLabel(); }
1457 opstat: t_END generate_stat_1 t_Semicolon           { popLabel(); }
1458
1459 generate_stat: t_Identifier  t_Colon
1460                { pushLabel($1); }
1461                if_generation_scheme opstat //    t_END   generate_stat_1 t_Semicolon { popLabel(); }
1462 generate_stat: t_Identifier  t_Colon case_scheme
1463
1464 generate_stat_1: t_GENERATE              { $$=""; }
1465 generate_stat_1: t_GENERATE t_Identifier { $$=$2; }
1466
1467 //end_stats :
1468 end_stats: t_END t_Semicolon
1469 end_stats: t_END t_Identifier t_Semicolon
1470
1471 procs_stat: t_Identifier t_Colon procs_stat1
1472                {
1473                  current->name=$1;
1474                  current->endBodyLine=s_str.yyLineNr;
1475                  newEntry();
1476                }
1477
1478 procs_stat: procs_stat1
1479                {
1480                  current->name=VhdlDocGen::getProcessNumber();
1481                  current->endBodyLine=s_str.yyLineNr;
1482                  newEntry();
1483                }
1484
1485 procs_stat1: procs_stat1_5
1486                { currP=VhdlDocGen::PROCESS; }
1487                t_PROCESS procs_stat1_1 procs_stat1_2 t_BEGIN seq_stats t_END
1488                procs_stat1_3 t_Semicolon
1489                { currP=0;
1490                  createFunction(currName,VhdlDocGen::PROCESS,$4.data());
1491                }
1492 procs_stat1: error t_END procs_stat1_3  t_Semicolon { currP=0; }
1493
1494 procs_stat1_3:  /* empty */
1495 procs_stat1_3: procs_stat1_5  t_PROCESS  procs_stat1_6
1496
1497 procs_stat1_5:  /* empty */ { $$=""; }
1498 procs_stat1_5: t_POSTPONED  { $$="postponed"; }
1499
1500 procs_stat1_6:  /* empty */ { $$=""; }
1501 procs_stat1_6: t_Identifier { $$=$1; }
1502
1503 procs_stat1_2:  /* empty */
1504 procs_stat1_2:  t_IS
1505 procs_stat1_2: procs_stat1_2 procs_stat1_4
1506 procs_stat1_4: procs_decltve_item
1507 procs_stat1_1:  /* empty */                                    { $$=""; }
1508 procs_stat1_1: t_LeftParen t_ALL t_RightParen                  { $$="all"; }
1509 procs_stat1_1: t_LeftParen sensitivity_list t_RightParen       { $$=$2; }
1510
1511 sensitivity_list:   name sensitivity_list_1                    { $$=$1+" "+$2; }
1512 sensitivity_list_1: /* empty */                                { $$=""; }
1513 sensitivity_list_1: sensitivity_list_1 sensitivity_list_2      { $$=$1+" "+$2; }
1514 sensitivity_list_2: t_Comma name                               { $$=","+$2; }
1515
1516 /*--------------------------------------------------
1517 --  Sequential Statements
1518 ----------------------------------------------------*/
1519
1520 seq_stats:   seq_stats_1
1521 seq_stats_1: /* empty */
1522 seq_stats_1: seq_stats_1 seq_stats_2
1523 seq_stats_2: seq_stat
1524
1525 seq_stat: assertion_stat
1526 seq_stat: lable assertion_stat
1527 seq_stat: case_stat
1528 seq_stat: exit_stat
1529 seq_stat: if_stat
1530 seq_stat: loop_stat
1531 seq_stat: next_stat
1532 seq_stat: null_stat
1533 seq_stat: procedure_call_stat
1534 seq_stat: return_stat
1535 seq_stat: lable signal_assign_stat
1536 seq_stat: signal_assign_stat
1537 seq_stat: variable_assign_stat
1538 seq_stat: wait_stat
1539 seq_stat: lable wait_stat
1540 seq_stat: report_statement
1541
1542 report_statement: loop_stat_1 t_REPORT expr assertion_stat_2  t_Semicolon
1543
1544 assertion_stat: t_ASSERT expr assertion_stat_1 assertion_stat_2 t_Semicolon
1545 assertion_stat_2:  /* empty */
1546 assertion_stat_2     : t_SEVERITY expr
1547 assertion_stat_1     :  /* empty */
1548 assertion_stat_1     : t_REPORT expr
1549
1550 choice_stat :  /* empty */
1551 choice_stat :  t_Q
1552
1553 choice_stat_1:  /* empty */
1554 choice_stat_1 :  t_Q
1555 choice_stat_1 : t_Identifier
1556
1557 case_stat  : t_CASE choice_stat expr t_IS case_stat_alternative case_stat_1 t_END t_CASE choice_stat_1  t_Semicolon
1558 case_stat  : lable t_CASE choice_stat expr t_IS case_stat_alternative case_stat_1 t_END t_CASE choice_stat_1  t_Semicolon
1559
1560 case_stat  : t_CASE error t_END t_CASE choice_stat_1  t_Semicolon
1561 case_stat_1     :  /* empty */
1562 case_stat_1     : case_stat_1 case_stat_2
1563 case_stat_2     : case_stat_alternative
1564
1565 case_stat_alternative     : t_WHEN choices t_Arrow seq_stats
1566
1567 exit_stat  : t_EXIT exit_stat_1 exit_stat_2 t_Semicolon
1568 exit_stat_2     :  /* empty */
1569 exit_stat_2     : t_WHEN expr
1570 exit_stat_1     :  /* empty */
1571 exit_stat_1     : t_Identifier
1572
1573 if_stat    : t_IF expr t_THEN seq_stats if_stat_1 if_stat_2 t_END t_IF t_Semicolon
1574 if_stat  :  t_IF expr t_THEN  error  t_END t_IF  t_Semicolon
1575 if_stat_2  :  /* empty */
1576 if_stat_2  : t_ELSE seq_stats
1577 if_stat_1  :  /* empty */
1578 if_stat_1  : if_stat_1 if_stat_3
1579 if_stat_3  : t_ELSIF expr t_THEN seq_stats
1580
1581 loop_stat:   loop_stat_1 loop_stat_2 t_LOOP seq_stats t_END t_LOOP loop_stat_3 t_Semicolon
1582 loop_stat_3: /* empty */
1583 loop_stat_3: t_Identifier
1584 loop_stat_2: /* epty */
1585 loop_stat_2: iteration_scheme
1586 loop_stat_1: /* empty */
1587 loop_stat_1: t_Identifier t_Colon
1588
1589 next_stat:   t_NEXT next_stat_1 next_stat_2 t_Semicolon
1590 next_stat_2:  /* empty */
1591 next_stat_2: t_WHEN expr
1592 next_stat_1:  /* empty */
1593 next_stat_1: t_Identifier
1594
1595 null_stat: t_NULL t_Semicolon
1596
1597 procedure_call_stat: name t_Semicolon
1598
1599 return_stat:   t_RETURN return_stat_1 t_Semicolon
1600 return_stat_1: /* empty */
1601 return_stat_1: expr
1602
1603 signal_assign_stat: target t_LESym wavefrm t_Semicolon
1604                   | target t_LESym delay_mechanism wavefrm t_Semicolon
1605                   | target t_LESym t_FORCE inout_stat  expr t_Semicolon
1606                   | target t_LESym t_RELEASE inout_stat t_Semicolon
1607                   | selected_signal_assignment
1608                   | conditional_signal_assignment
1609                   ;
1610
1611 variable_assign_stat: variable_assign_stat_1 t_Semicolon
1612                     | conditional_variable_assignment
1613                     | lable selected_variable_assignment
1614                     | selected_variable_assignment
1615
1616 lable: t_Identifier t_Colon
1617 variable_assign_stat_1: target t_VarAsgn expr
1618 variable_assign_stat_1: lable target t_VarAsgn expr
1619
1620 wait_stat:   t_WAIT wait_stat_1 wait_stat_2 wait_stat_3 t_Semicolon
1621 wait_stat_3: /* empty */
1622 wait_stat_3: t_FOR expr
1623 wait_stat_2: /* empty */
1624 wait_stat_2: t_UNTIL expr
1625 wait_stat_1: /* empty */
1626 wait_stat_1: t_ON sensitivity_list
1627
1628
1629 /*--------------------------------------------------
1630 --  Components and Configurations
1631 ----------------------------------------------------*/
1632 comp_end_dec : t_END                              { lastEntity=0; lastCompound=0; genLabels.resize(0); }
1633              | t_END t_COMPONENT entity_decl_5
1634              | t_END t_ARCHITECTURE entity_decl_5 { lastCompound=0; genLabels.resize(0); }
1635              | t_END t_ENTITY entity_decl_5       { lastEntity=0; genLabels.resize(0); }
1636              | t_END t_Identifier                 { lastEntity=0; lastCompound=0; genLabels.resize(0); }
1637
1638 iss :/*empty*/ { currP=VhdlDocGen::COMPONENT; }
1639     |  t_IS    { currP=VhdlDocGen::COMPONENT; }
1640
1641 comp_decl: t_COMPONENT t_Identifier iss comp_decl_1 comp_decl_2 comp_end_dec  t_Semicolon
1642            {
1643              addVhdlType($2,getParsedLine(t_COMPONENT),Entry::VARIABLE_SEC,VhdlDocGen::COMPONENT,0,0);
1644              currP=0;
1645            }
1646 comp_decl_2:  /* empty */                      { $$=""; }
1647 comp_decl_2: t_PORT interf_list t_Semicolon    { $$=$2; }
1648 comp_decl_1:  /* empty */                      { $$=""; }
1649 comp_decl_1: t_GENERIC interf_list t_Semicolon { $$=$2; }
1650
1651 block_config: t_FOR block_spec block_config_1 block_config_2 t_END t_FOR t_Semicolon
1652           {
1653            popConfig();
1654           }
1655
1656 block_config:   t_FOR error t_END t_FOR t_Semicolon { $$=""; }
1657 block_config_2: /* empty */                         { $$=""; }
1658 block_config_2: block_config_2 block_config_3       { $$=$1+"  "; }
1659 block_config_3: config_item                         { $$=$1; }
1660 block_config_1: /* empty */                         { $$=""; }
1661 block_config_1: block_config_1 block_config_4       { $$=$1; }
1662 block_config_4: use_clause                          { $$=$1; }
1663
1664 block_spec: name
1665     {
1666       $$=$1;
1667
1668       if (levelCounter==0)
1669         addConfigureNode($1.data(),NULL,TRUE,FALSE);
1670       else
1671         addConfigureNode($1.data(),NULL,FALSE,FALSE);
1672     }
1673
1674 config_item: block_config { $$=$1; }
1675 config_item: comp_config  { $$=$1; }
1676
1677 comp_config: t_FOR comp_spec comp_config_1 comp_config_2 t_END t_FOR t_Semicolon
1678              {
1679                $$=$2+" "+$3+" "+$4;
1680                popConfig();
1681              }
1682 comp_config_2:  /* empty */   { $$=""; }
1683 comp_config_2: block_config   { $$=$1; }
1684 comp_config_1:  /*empty*/     { $$=""; }
1685
1686 comp_config_1: binding_indic_1  binding_indic_2  t_Semicolon   { $$=""; }
1687 comp_config_1: t_USE t_VUNIT idf_list  t_Semicolon             { $$=""; }
1688 comp_config_1: t_USE binding_indic t_Semicolon
1689              {
1690                addConfigureNode(compSpec.data(),$2.data(),FALSE,FALSE);
1691              }
1692
1693 config_spec: t_FOR comp_spec comp_spec_stat t_Semicolon                         
1694              { 
1695                addConfigureNode($2.data(),$3.data(),TRUE,FALSE,TRUE);currNode->confVhdl=lastCompound->name; 
1696              }
1697 config_spec: t_FOR comp_spec comp_spec_stat t_Semicolon t_END t_FOR t_Semicolon 
1698              { 
1699                addConfigureNode($2.data(),$3.data(),TRUE,FALSE,TRUE);currNode->confVhdl=lastCompound->name; 
1700              }
1701
1702 comp_spec_stat: t_USE  binding_indic               { $$=$2; }
1703 comp_spec_stat: t_USE t_VUNIT idf_list t_Semicolon { $$=""; }
1704 comp_spec_stat: binding_indic_1  binding_indic_2   { $$=""; }
1705
1706 comp_spec: inst_list t_Colon expr
1707              {
1708                $$=$1+":"+$3;
1709                compSpec=$$;
1710              }
1711
1712 inst_list: idf_list  { $$=$1; }
1713 inst_list: t_ALL     { $$="all"; }
1714 inst_list: t_OTHERS  { $$="others"; }
1715
1716 binding_indic   : entity_aspect binding_indic_1 binding_indic_2 { $$=$1; }
1717
1718 binding_indic_2:
1719 binding_indic_2: t_PORT t_MAP association_list
1720
1721 binding_indic_1:
1722 binding_indic_1: t_GENERIC t_MAP association_list
1723
1724
1725 entity_aspect: t_ENTITY name { $$="entity "+$2; }
1726 entity_aspect: t_CONFIGURATION mark { $$="configuration "+ $2; }
1727 entity_aspect: t_OPEN { $$="open "; }
1728              ;
1729
1730 group_constituent: t_Identifier    { $$=$1; }
1731                  | t_CharacterLit { $$=$1; }
1732                  ;
1733
1734 group_constituent_list: group_constituent                                { $$=$1; }
1735                       | group_constituent_list t_Comma group_constituent { $$=$1+","+$3; }
1736                       ;
1737
1738 group_declaration : t_GROUP t_Identifier t_Colon group_name   t_LeftParen  group_constituent_list  t_RightParen t_Semicolon
1739                     {
1740                       // $$=$2+":"+$4+$6;
1741                       $$="("+$4+$6+")";
1742                       addVhdlType($2,getParsedLine(t_GROUP),Entry::VARIABLE_SEC,VhdlDocGen::GROUP,$$.data(),0);
1743                     }
1744
1745 group_template_declaration :  t_GROUP  t_Identifier t_IS  t_LeftParen  entity_class_entry_list  t_RightParen t_Semicolon
1746                     {
1747                       $$=$2+":"+$5;
1748                       addVhdlType($2,getParsedLine(t_GROUP),Entry::VARIABLE_SEC,VhdlDocGen::GROUP,$5.data(),0);
1749                     }
1750
1751 group_template_declaration: t_GROUP  t_Identifier t_IS  t_LeftParen error t_Semicolon  t_RightParen { $$=""; }
1752
1753 entity_class_entry : entity_class tbox
1754
1755 tbox :  /* empty */ { $$="";   }
1756 tbox :  t_Box       { $$="<>"; }
1757
1758 entity_class_entry_list: entity_class_entry         { $$=$1; }
1759                        | entity_class_entry_list
1760                          t_Comma entity_class_entry { $$=$1+","+$3; }
1761                        ;
1762
1763 group_name: t_Identifier { $$=$1; }
1764 group_name: t_StringLit  { $$=$1; }
1765
1766 t_Identifier: t_LETTER
1767     {
1768       $$=s_str.qstr;
1769     }
1770
1771 t_BitStringLit: t_DIGIT
1772     {
1773       $$=s_str.qstr;
1774     }
1775
1776 t_StringLit: t_STRING
1777     {
1778       $$=s_str.qstr;
1779     }
1780
1781 t_AbstractLit: t_ABSTRLIST
1782     {
1783       $$=s_str.qstr;
1784     }
1785
1786 t_CharacterLit: t_CHARLIST
1787     {
1788       $$=s_str.qstr;
1789     }
1790
1791
1792 /*--------------------------------------------------
1793 --  VHDL 2002 extensions
1794 -- to do: must be added
1795 -----------------------------------------------------*/
1796 protected_type_declaration:t_PROTECTED protected_stats t_END protected_stat_1 { $$=""; }
1797 protected_type_declaration:t_PROTECTED error  t_END protected_stat_1 { $$=""; }
1798
1799 protected_stats:       /* empty */
1800 protected_stats:       protected_stats   protected_stat_decl_1
1801 protected_stat_decl_1: protected_type_declaration_item
1802 protected_stat_1:      t_PROTECTED
1803 protected_stat_1:      t_PROTECTED t_Identifier
1804
1805 protected_type_declaration_item: use_clause
1806 protected_type_declaration_item: attribute_spec
1807 protected_type_declaration_item: subprog_decl
1808 protected_type_declaration_item:  subprogram_instantiation_decl
1809
1810 protected_type_body: t_PROTECTED t_BODY protected_body_stats t_END protected_body_stat_1 { $$=""; }
1811 protected_type_body: t_PROTECTED t_BODY error t_END protected_body_stat_1 { $$=""; }
1812
1813 protected_body_stats: /* empty */
1814 protected_body_stats:  protected_body_stats   protected_body_stat_decl_1
1815 protected_body_stat_decl_1: protected_type_body_declaration_item
1816
1817 protected_body_stat_1: t_PROTECTED t_BODY
1818 protected_body_stat_1: t_PROTECTED t_BODY t_Identifier
1819
1820 protected_type_body_declaration_item: subprog_decltve_item // same as subprog
1821
1822 /*--------------------------------------------------
1823 --  VHDL 2008 extensions
1824 -- to do: must be added
1825 -----------------------------------------------------*/
1826 context_ref: t_CONTEXT  sel_list t_Semicolon { $$="context "+$2; }
1827
1828 context_decl: t_CONTEXT t_Identifier t_IS { parse_sec=CONTEXT_SEC; }  libustcont_stats t_END context_stat_1 t_Semicolon
1829                         {
1830                           parse_sec=0;
1831                           QCString v=$5;
1832                           addVhdlType($2,getParsedLine(t_LIBRARY),Entry::VARIABLE_SEC,VhdlDocGen::LIBRARY,"context",$5.data());
1833                         }
1834 context_decl: t_CONTEXT t_Identifier t_IS  t_END context_stat_1 t_Semicolon
1835                         {
1836                           addVhdlType($2,getParsedLine(t_LIBRARY),Entry::VARIABLE_SEC,VhdlDocGen::LIBRARY,"context",0);
1837                         }
1838
1839 context_stat_1: t_CONTEXT
1840 context_stat_1: t_CONTEXT t_Identifier
1841
1842 libustcont_stats: libustcont_stat                     { $$ = $1; }
1843 libustcont_stats: libustcont_stats  libustcont_stat   { $$ = $1+"#"+$2; }
1844
1845 libustcont_stat: use_clause  { $$ = $1; }
1846 libustcont_stat: lib_clause  { $$ = $1; }
1847 libustcont_stat: context_ref { $$ = $1; }
1848
1849 package_instantiation_decl: t_PACKAGE t_Identifier t_IS t_NEW dot_name signature t_Semicolon
1850     {
1851       $$=" is new "+$5+$6;
1852       //Entry * pp=lastCompound;
1853       //Entry * pps=lastEntity  ;
1854       //assert(false);
1855       addVhdlType($2,getParsedLine(t_PACKAGE),Entry::VARIABLE_SEC,VhdlDocGen::INSTANTIATION,"package",$$.data());
1856     }
1857 package_instantiation_decl: t_PACKAGE t_Identifier t_IS t_NEW dot_name signature  gen_assoc_list t_Semicolon
1858     {
1859       $$=" is new "+$5+$6;
1860       addVhdlType($2,getParsedLine(t_PACKAGE),Entry::VARIABLE_SEC,VhdlDocGen::INSTANTIATION,"package",$$.data());
1861     }
1862 package_instantiation_decl: t_PACKAGE error  t_Identifier t_IS t_NEW t_Semicolon  { $$=""; }
1863
1864 subprogram_instantiation_decl: t_FUNCTION  t_Identifier t_IS   t_NEW dot_name  signature  t_Semicolon
1865     {
1866       $$= " is new "+$5+$6;
1867       addVhdlType($2,getParsedLine(t_FUNCTION),Entry::VARIABLE_SEC,VhdlDocGen::INSTANTIATION,"function ",$$.data());
1868     }
1869 subprogram_instantiation_decl: t_FUNCTION  t_Identifier t_IS t_NEW dot_name  signature gen_assoc_list t_Semicolon
1870     {
1871       $$=" is new "+$5+$6;
1872       addVhdlType($2,getParsedLine(t_FUNCTION),Entry::VARIABLE_SEC,VhdlDocGen::INSTANTIATION,"function ",$$.data());
1873     }
1874 subprogram_instantiation_decl: t_FUNCTION   t_Identifier t_IS   t_NEW error t_Semicolon { $$=""; }
1875
1876 signature:/*empty*/                  { $$=""; }
1877 signature: t_LEFTBR signature1 
1878            t_RIGHTBR                 { $$="["+$2+" ]"; }
1879 signature: t_LEFTBR t_RIGHTBR        { $$="[ ]"; }
1880
1881 signature1: t_RETURN mark            { $$="return "+$2; }
1882 signature1: mark_stats               { $$=$1; }
1883 signature1: mark_stats t_RETURN mark { $$=$1+" return "+$3; }
1884
1885 mark_stats: mark                     { $$=$1; }
1886 mark_stats: mark_stats mark_stats_1  { $$=$1+" "+$2; }
1887 mark_stats_1: t_Comma mark           { $$=" , "+$2; }
1888
1889 case_scheme:  t_CASE expr   t_GENERATE when_stats ttend  t_END t_GENERATE generate_stat_1  t_Semicolon
1890 case_scheme:  t_CASE expr   t_GENERATE when_stats        t_END t_GENERATE generate_stat_1  t_Semicolon
1891 case_scheme:  t_CASE error  t_GENERATE error             t_END t_GENERATE generate_stat_1  t_Semicolon
1892
1893 when_stats_1: t_WHEN lable choices t_Arrow generate_statement_body
1894 when_stats_1: t_WHEN choices t_Arrow generate_statement_body
1895 when_stats:   when_stats  when_stats_1
1896 when_stats:   when_stats_1
1897
1898 ttend: t_END t_Semicolon
1899 ttend: t_END t_Identifier t_Semicolon
1900
1901 conditional_signal_assignment: conditional_waveform_assignment
1902 conditional_signal_assignment: conditional_force_assignment
1903
1904 conditional_waveform_assignment: target t_LESym wavefrm_element t_WHEN expr else_wave_list t_Semicolon
1905 conditional_waveform_assignment: target t_LESym delay_mechanism wavefrm_element t_WHEN expr else_wave_list t_Semicolon
1906 conditional_waveform_assignment: target t_LESym wavefrm_element t_WHEN expr t_Semicolon
1907 conditional_waveform_assignment: target t_LESym delay_mechanism wavefrm_element t_WHEN expr t_Semicolon
1908 conditional_waveform_assignment: target t_LESym error t_Semicolon
1909
1910 else_wave_list: t_ELSE expr t_WHEN expr
1911 else_wave_list: t_ELSE expr
1912
1913 conditional_force_assignment:  target t_LESym t_FORCE  inout_stat expr t_WHEN expr else_stat t_Semicolon
1914 conditional_force_assignment:  target t_LESym t_FORCE  inout_stat expr t_WHEN expr t_Semicolon
1915
1916 selected_signal_assignment : selected_waveform_assignment
1917 selected_signal_assignment : selected_force_assignment
1918
1919 selected_waveform_assignment: t_WITH expr t_SELECT choice_stat
1920                               target t_LESym delay_stat sel_wave_list
1921
1922 delay_stat:
1923 delay_stat: delay_mechanism
1924
1925 sel_wave_list: wavefrm_element t_WHEN choices t_Comma  sel_wave_list
1926 sel_wave_list: sel_wave_list_1
1927
1928 sel_wave_list_1: wavefrm_element  t_WHEN choices t_Semicolon
1929
1930 selected_force_assignment: t_WITH expr t_SELECT choice_stat target t_LESym t_FORCE
1931                                                   inout_stat sel_var_list
1932
1933 inout_stat:
1934 inout_stat: t_IN
1935 inout_stat: t_OUT
1936
1937 delay_mechanism : t_TRANSPORT
1938                 | t_REJECT expr t_INERTIAL
1939                 |  t_INERTIAL
1940
1941 conditional_variable_assignment : variable_assign_stat_1 t_WHEN expr else_stat t_Semicolon
1942 conditional_variable_assignment : variable_assign_stat_1 t_WHEN expr t_Semicolon
1943
1944 else_stat: t_ELSE expr t_WHEN expr
1945 else_stat: else_stat t_ELSE expr t_WHEN expr
1946 else_stat: t_ELSE expr
1947
1948 selected_variable_assignment: t_WITH expr t_SELECT choice_stat select_name t_VarAsgn sel_var_list
1949
1950 sel_var_list: expr t_WHEN choices t_Comma  sel_var_list
1951 sel_var_list: sel_var_list_1
1952
1953 sel_var_list_1: expr t_WHEN choices t_Semicolon
1954
1955 select_name: name
1956            | aggregate
1957
1958 interface_subprogram_decl: iproc { $$ = $1; }
1959                          | ifunc { $$=$1; }
1960                          ;
1961 iproc: t_PROCEDURE t_Identifier param { $$ = "procedure "+$2+$3; current->name=$2; }
1962
1963 ifunc: t_FUNCTION   func_name param   t_RETURN mark return_is
1964     {
1965       QCString s=$6;
1966       if (!s.isEmpty())
1967       {
1968         s.prepend(" is ");
1969       }
1970       $$=" function "+$2+$3+$5+s;
1971       current->name=$2;
1972     }
1973 ifunc: func_prec t_FUNCTION  func_name param t_RETURN mark return_is
1974     {
1975       QCString s=$7;
1976       if (!s.isEmpty())
1977       {
1978         s.prepend(" is ");
1979       }
1980       $$=$1+" function "+$3+$4+" return "+$6+s;
1981       current->name=$3;
1982     }
1983
1984 func_name: t_Identifier   { $$=$1; }
1985          | t_StringLit    { $$=$1; }  // "?<"
1986          ;
1987
1988 return_is:  /* empty */       { $$="";   }
1989          | t_IS  t_Identifier { $$=$2;   }
1990          | t_IS t_Box         { $$="<>"; }
1991
1992 param: /* empty */ { $$=""; }
1993 param: t_PARAMETER { $$="parameter "; }
1994 param: t_PARAMETER { parse_sec=PARAM_SEC; }
1995                    t_LeftParen interf_element interf_list_1 t_RightParen
1996                    { parse_sec=0; }
1997
1998 param: t_LeftParen  interf_element interf_list_1 t_RightParen { $$="("+$2+")"; }
1999
2000 interface_package_decl: t_PACKAGE t_Identifier t_IS t_NEW dot_name
2001                         {
2002                           $$="package "+$2+" is new "+$5;
2003                           current->name=$2;
2004                         }
2005 interface_package_decl: t_PACKAGE t_Identifier t_IS t_NEW dot_name gen_assoc_list 
2006                         { 
2007                           $$="package "+$2+" is new "+$5+"( ... )" ; 
2008                           current->name=$2; 
2009                         }
2010
2011 gen_assoc_list:         t_GENERIC t_MAP   association_list
2012
2013 gen_interface_list :    t_GENERIC
2014                         {
2015                           //int u=s_str.iLine;
2016                           parse_sec=GEN_SEC;
2017                         }
2018                         interf_list
2019                         {
2020                           QCString vo=$3;
2021                           parse_sec=0;
2022                         }
2023
2024 external_name: t_SLSL sig_stat external_pathname t_Colon  subtype_indic  t_SRSR
2025                         {
2026                           QCString s="<<"+$2;
2027                           QCString s1=$3+":"+$5+">>";
2028                           $$=s+s1;
2029                         }
2030
2031 sig_stat:  t_CONSTANT   { $$="constant "; }
2032 sig_stat:  t_SIGNAL     { $$="signal ";   }
2033 sig_stat:  t_VARIABLE   { $$="variable "; }
2034
2035 external_pathname: absolute_pathname  { $$=$1; }
2036                  | relative_pathname  { $$=$1; }
2037                  | package_path_name  { $$=$1; }
2038                  ;
2039
2040 absolute_pathname:  t_Dot  pathname_element_list t_Identifier  { $$="."+$2+$3; }
2041 absolute_pathname:  t_Dot  t_Identifier  { $$="."+$2; }
2042
2043 relative_pathname: neg_list pathname_element_list t_Identifier { $$=$1+$2+$3; }
2044 relative_pathname: neg_list t_Identifier { $$=$1+$2; }
2045
2046 neg_list:  t_Neg t_Dot          { $$="^."; }
2047 neg_list: neg_list  t_Neg t_Dot { $$=$1+"^."; }
2048
2049 pathname_element: t_Identifier  { $$=$1; }
2050                 | t_Identifier t_LeftParen expr  t_RightParen  { $$=$1+"("+$3+")"; }
2051                 ;
2052
2053 pathname_element_list: pathname_element t_Dot     { $$=$1+"."; }
2054                      | pathname_element_list pathname_element t_Dot   { $$=$1+$2+"."; }
2055
2056 package_path_name: t_At dot_name { $$="@"+$2; }
2057
2058 tool_directive: t_ToolDir
2059 {
2060 // fprintf(stderr,"\n  tooldir %s",s_str.qstr.data() );
2061 }
2062
2063
2064 %%
2065 extern FILE* yyout;
2066 extern YYSTYPE vhdlScanYYlval;
2067
2068 void vhdlScanYYerror(const char* /*str*/)
2069 {
2070 //  fprintf(stderr,"\n<---error at line %d  : [ %s]   in file : %s ---->",s_str.yyLineNr,s_str.qstr.data(),s_str.fileName);
2071  // exit(0);
2072 }
2073
2074 void vhdlParse()
2075 {
2076 //  //myconv=conv;
2077   vhdlScanYYparse();
2078 }
2079
2080 //int lex(void)
2081 //{
2082 //  return myconv->doLex();
2083 //}
2084
2085 VhdlContainer*  getVhdlCont()
2086 {
2087   return &s_str;
2088 }
2089
2090 Entry* getVhdlCompound()
2091 {
2092   if (lastEntity) return lastEntity;
2093   if (lastCompound) return lastCompound;
2094   return NULL;
2095 }
2096
2097 QList<VhdlConfNode>& getVhdlConfiguration() { return  configL; }
2098
2099 static void addCompInst(char *n, char* instName, char* comp,int iLine)
2100 {
2101
2102   current->spec=VhdlDocGen::INSTANTIATION;
2103   current->section=Entry::VARIABLE_SEC;
2104   current->startLine=iLine;
2105   current->bodyLine=iLine;
2106   current->type=instName;                       // foo:instname e.g proto or work. proto(ttt)
2107   current->exception=genLabels;                 // |arch|label1:label2...
2108   current->name=n;                              // foo
2109   current->args=lastCompound->name;             // architecture name
2110   current->includeName=comp;                    // component/enity/configuration
2111
2112   //printf(" \n genlable: [%s]  inst: [%s]  name: [%s] \n",genLabels.data(),instName,n);
2113
2114   if (lastCompound)
2115   {
2116     current->args=lastCompound->name;
2117     if (true) // !findInstant(current->type))
2118     {
2119       initEntry(current);
2120       instFiles.append(new Entry(*current));
2121     }
2122   
2123     Entry *temp=current;  // hold  current pointer  (temp=oldEntry)
2124     current=new Entry;     // (oldEntry != current)
2125     delete  temp;
2126    
2127   }
2128   else
2129   {
2130     newEntry();
2131   }
2132 }
2133
2134 static void pushLabel(const QCString &label)
2135 {
2136   genLabels+="|"+label;
2137 }
2138
2139 static void popLabel()
2140 {
2141   int u=genLabels.findRev("|");
2142   if (u<0) return;
2143   genLabels=genLabels.left(u);
2144 }
2145
2146 static void popConfig()
2147 {
2148   assert(currNode);
2149   currNode=currNode->prevNode;
2150   // printf("\n pop arch %s ",currNode->arch.data());
2151 }
2152
2153 static void addConfigureNode(const char* a,const char*b, bool isRoot,bool isLeave,bool inlineConf)
2154 {
2155   VhdlConfNode* co;
2156   QCString ent,arch,lab;
2157   ent=a;
2158   lab =  VhdlDocGen::parseForConfig(ent,arch);
2159
2160   if (b)
2161   {
2162     ent=b;
2163     lab=VhdlDocGen::parseForBinding(ent,arch);
2164   }
2165
2166   co=new VhdlConfNode(a,b,confName.data());
2167   if (inlineConf)
2168   {
2169     co->isInlineConf=TRUE;
2170   }
2171
2172   if (isRoot)
2173   {
2174     co->isRoot=TRUE;
2175     configL.append(co);
2176     currNode=co;
2177     currNode->prevNode=currNode;
2178   }
2179   else if (!isLeave)
2180   {
2181     currNode->addNode(co);
2182     co->prevNode=currNode;
2183     currNode=co;
2184   }
2185   else
2186   {
2187     assert(0);
2188     co=new VhdlConfNode(a,b,confName.data());
2189     currNode->addNode(co);
2190   }
2191 }// addConfigure
2192
2193 //------------------------------------------------------------------------------------------------------------
2194
2195 static bool isFuncProcProced()
2196 {
2197   if (currP==VhdlDocGen::FUNCTION ||
2198       currP==VhdlDocGen::PROCEDURE ||
2199       currP==VhdlDocGen::PROCESS
2200      )
2201   {
2202     return TRUE;
2203   }
2204   return FALSE;
2205 }
2206
2207 static void initEntry(Entry *e)
2208 {
2209   e->fileName = s_str.fileName;
2210   e->lang=SrcLangExt_VHDL;
2211   isVhdlDocPending();
2212   initGroupInfo(e);
2213 }
2214
2215 static void addProto(const char *s1,const char *s2,const char *s3,
2216                      const char *s4,const char *s5,const char *s6)
2217 {
2218  // (void)s3; // avoid unused warning
2219   (void)s5; // avoid unused warning
2220   static QRegExp reg("[\\s]");
2221   QCString name=s2;
2222   QStringList ql=QStringList::split(",",name,FALSE);
2223
2224   for (uint u=0;u<ql.count();u++)
2225   {
2226     Argument *arg=new Argument;
2227     arg->name=ql[u].utf8();
2228     if (s3)
2229     {
2230       arg->type=s3;
2231     }
2232     arg->type+=" ";
2233     arg->type+=s4;
2234     if (s6)
2235     {
2236       arg->type+=s6;
2237     }
2238     if (parse_sec==GEN_SEC && param_sec==0)
2239     {
2240       arg->defval="gen!";
2241     }
2242
2243     if (parse_sec==PARAM_SEC)
2244     {
2245       assert(false);
2246     }
2247
2248     arg->defval+=s1;
2249     arg->attrib="";//s6;
2250
2251     current->argList->append(arg);
2252     current->args+=s2;
2253     current->args+=",";
2254   }
2255 }
2256
2257 static void createFunction(const QCString &impure,int spec,
2258                            const QCString &fname)
2259 {
2260   int it=0;
2261   current->bodyLine=getParsedLine(spec);
2262   current->spec=spec;
2263   current->section=Entry::FUNCTION_SEC;
2264   current->exception=impure;
2265
2266   if (parse_sec==GEN_SEC)
2267   {
2268     current->spec= VhdlDocGen::GENERIC;
2269     current->section=Entry::FUNCTION_SEC;
2270   }
2271
2272   if (currP==VhdlDocGen::PROCEDURE)
2273   {
2274     current->name=impure;
2275     current->exception="";
2276     it=t_PROCEDURE;
2277   }
2278   else
2279   {
2280     current->name=fname;
2281     it=t_FUNCTION;
2282   }
2283
2284   if (spec==VhdlDocGen::PROCESS)
2285   {
2286     it=t_PROCESS;
2287     current->args=fname;
2288     current->name=impure;
2289     if (!fname.isEmpty())
2290     {
2291       QStringList q1=QStringList::split(',',fname);
2292       for (uint ii=0;ii<q1.count();ii++)
2293       {
2294         Argument *arg=new Argument;
2295         arg->name=q1[ii].utf8();
2296         current->argList->append(arg);
2297       }
2298     }
2299   }
2300
2301   current->startLine=getParsedLine(it);
2302   current->bodyLine=getParsedLine(it);
2303 }
2304
2305 static void addVhdlType(const QCString &name,int startLine,int section,int spec,
2306                         const char* args,const char* type,Protection prot)
2307 {
2308   static QRegExp reg("[\\s]");
2309
2310   //int startLine=getParsedLine(spec);
2311
2312   if (isFuncProcProced())
2313   {
2314     return;
2315   }
2316
2317   if (parse_sec==GEN_SEC)
2318   {
2319     spec= VhdlDocGen::GENERIC;
2320   }
2321
2322   // more than one name   ?
2323   QStringList ql=QStringList::split(",",name,FALSE);
2324
2325   for (uint u=0;u<ql.count();u++)
2326   {
2327     current->name=ql[u].utf8();
2328  //   if (section==Entry::VARIABLE_SEC &&  !(spec == VhdlDocGen::USE || spec == VhdlDocGen::LIBRARY) )
2329  //   {
2330  //     current->name.prepend(VhdlDocGen::getRecordNumber());
2331  //   }
2332    
2333     current->startLine=startLine;
2334     current->bodyLine=startLine;
2335     current->section=section;
2336     current->spec=spec;
2337     current->fileName=s_str.fileName;
2338     if (current->args.isEmpty())
2339     {
2340       current->args=args;
2341       current->args.replace(reg,"%"); // insert dummy chars because wihte spaces are removed
2342     }
2343     current->type=type;
2344     current->type.replace(reg,"%"); // insert dummy chars because white spaces are removed
2345     current->protection=prot;
2346     newEntry();
2347   }
2348 }
2349
2350 static void newEntry()
2351 {
2352   if (current->spec==VhdlDocGen::ENTITY       ||
2353       current->spec==VhdlDocGen::PACKAGE      ||
2354       current->spec==VhdlDocGen::ARCHITECTURE ||
2355       current->spec==VhdlDocGen::PACKAGE_BODY
2356      )
2357   {
2358     current_root->addSubEntry(current);
2359   }
2360   else
2361   {
2362     if (lastCompound)
2363     {
2364       lastCompound->addSubEntry(current);
2365     }
2366     else
2367     {
2368       if (lastEntity)
2369       {
2370         lastEntity->addSubEntry(current);
2371       }
2372       else
2373       {
2374         current_root->addSubEntry(current);
2375       }
2376     }
2377   }
2378   current = new Entry ;
2379   initEntry(current);
2380 }
2381