[MIPS] Rename COPROC related macros

gas/

	* config/tc-mips.c: Rename INSN_LOAD_COPROC_DELAY to INSN_LOAD_COPROC
	and INSN_COPROC_MOVE_DELAY to INSN_COPROC_MOVE throughout.

include/opcode/

	* mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
	(INSN_LOAD_COPROC): New define.
	(INSN_COPROC_MOVE_DELAY): Rename to...
	(INSN_COPROC_MOVE): New define.

opcodes/

	* micromips-opc.c (COD): Rename throughout to...
	(CM): New define, update to use INSN_COPROC_MOVE.
	(LCD): Rename throughout to...
	(LC): New define, update to use INSN_LOAD_COPROC.
	* mips-opc.c: Likewise.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 487b0c7..72d54db 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,10 @@
 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 
+       * config/tc-mips.c: Rename INSN_LOAD_COPROC_DELAY to INSN_LOAD_COPROC
+       and INSN_COPROC_MOVE_DELAY to INSN_COPROC_MOVE throughout.
+
+2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
+
        * config/tc-mips.c (mips_flags_frag): New static global.
        (struct mips_set_options): Add oddspreg field.
        (file_mips_opts, mips_opts): Initialize oddspreg.

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 2340afc..03f2b13 100644 (file)
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -533,8 +533,8 @@ static int mips_32bitmode = 0;
 /* Whether the processor uses hardware interlocks to avoid delays
    required by coprocessor instructions, and thus does not require
    nops to be inserted.  This applies to instructions marked
-   INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
-   between instructions marked INSN_WRITE_COND_CODE and ones marked
+   INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
+   instructions marked INSN_WRITE_COND_CODE and ones marked
    INSN_READ_COND_CODE.  These nops are only required at MIPS ISA
    levels I, II, and III and microMIPS mode instructions are always
    interlocked.  */
@@ -4509,7 +4509,7 @@ mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
      otherwise it depends on oddspreg.  */
   if ((insn->pinfo & FP_S)
       && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY
-                        | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
+                        | INSN_LOAD_COPROC | INSN_COPROC_MOVE)))
     return FPR_SIZE == 32 || oddspreg;
 
   /* Allow odd registers for single-precision ops and double-precision if the
@@ -4688,9 +4688,9 @@ convert_reg_type (const struct mips_opcode *opcode,
         FPR load, store or move (including moves to and from GPRs).  */
       if ((mips_opts.ase & ASE_MDMX)
          && (opcode->pinfo & FP_D)
-         && (opcode->pinfo & (INSN_COPROC_MOVE_DELAY
+         && (opcode->pinfo & (INSN_COPROC_MOVE
                               | INSN_COPROC_MEMORY_DELAY
-                              | INSN_LOAD_COPROC_DELAY
+                              | INSN_LOAD_COPROC
                               | INSN_LOAD_MEMORY
                               | INSN_STORE_MEMORY)))
        return RTYPE_FPU | RTYPE_VEC;
@@ -5842,7 +5842,7 @@ reg_needs_delay (unsigned int reg)
   prev_pinfo = history[0].insn_mo->pinfo;
   if (!mips_opts.noreorder
       && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks)
-         || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) && !cop_interlocks))
+         || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks))
       && (gpr_write_mask (&history[0]) & (1 << reg)))
     return TRUE;
 
@@ -5960,7 +5960,7 @@ insns_between (const struct mips_cl_insn *insn1,
         are on the RT register.  */
       /* Itbl support may require additional care here.  */
       if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY))
-         || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
+         || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC)))
        {
          if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
            return 1;
@@ -5974,7 +5974,7 @@ insns_between (const struct mips_cl_insn *insn1,
       /* Itbl support may require additional care here. FIXME!
         Need to modify this to include knowledge about
         user specified delays!  */
-      else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
+      else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE))
               || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
        {
          /* Handle cases where INSN1 writes to a known general coprocessor

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 3ddc36c..95532b1 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,10 @@
+2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
+       (INSN_LOAD_COPROC): New define.
+       (INSN_COPROC_MOVE_DELAY): Rename to...
+       (INSN_COPROC_MOVE): New define.
+
 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 6ae1f3a..846cc0f 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -973,16 +973,16 @@ struct mips_opcode
 #define INSN_COP                    0x00000400
 /* Instruction loads value from memory.  */
 #define INSN_LOAD_MEMORY           0x00000800
-/* Instruction loads value from coprocessor, requiring delay.  */
-#define INSN_LOAD_COPROC_DELAY     0x00001000
+/* Instruction loads value from coprocessor, (may require delay).  */
+#define INSN_LOAD_COPROC           0x00001000
 /* Instruction has unconditional branch delay slot.  */
 #define INSN_UNCOND_BRANCH_DELAY    0x00002000
 /* Instruction has conditional branch delay slot.  */
 #define INSN_COND_BRANCH_DELAY      0x00004000
 /* Conditional branch likely: if branch not taken, insn nullified.  */
 #define INSN_COND_BRANCH_LIKELY            0x00008000
-/* Moves to coprocessor register, requiring delay.  */
-#define INSN_COPROC_MOVE_DELAY      0x00010000
+/* Moves to coprocessor register, (may require delay).  */
+#define INSN_COPROC_MOVE            0x00010000
 /* Loads coprocessor register from memory, requiring delay.  */
 #define INSN_COPROC_MEMORY_DELAY    0x00020000
 /* Reads the HI register.  */

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 50876fc..79c42a2 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,13 @@
 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 
+       * micromips-opc.c (COD): Rename throughout to...
+       (CM): New define, update to use INSN_COPROC_MOVE.
+       (LCD): Rename throughout to...
+       (LC): New define, update to use INSN_LOAD_COPROC.
+       * mips-opc.c: Likewise.
+
+2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
+
        * micromips-opc.c (COD, LCD) New macros.
        (cfc1, ctc1): Remove FP_S attribute.
        (dmfc1, mfc1, mfhc1): Add LCD attribute.

diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index 4b1cdd7..7571c6b 100644 (file)
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -202,8 +202,8 @@ decode_micromips_operand (const char *p)
 #define TRAP   INSN_NO_DELAY_SLOT
 #define LM     INSN_LOAD_MEMORY
 #define SM     INSN_STORE_MEMORY
-#define COD    INSN_COPROC_MOVE_DELAY
-#define LCD    INSN_LOAD_COPROC_DELAY
+#define CM     INSN_COPROC_MOVE
+#define LC     INSN_LOAD_COPROC
 #define BD16   INSN2_BRANCH_DELAY_16BIT        /* Used in pinfo2.  */
 #define BD32   INSN2_BRANCH_DELAY_32BIT        /* Used in pinfo2.  */
 
@@ -625,10 +625,10 @@ const struct mips_opcode micromips_opcodes[] =
 {"dmtc0",              "t,G,H",        0x580002fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC,       0,              I3,             0,      0 },
 {"dmtgc0",             "t,G",          0x580006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC,       0,              0,              IVIRT64, 0 },
 {"dmtgc0",             "t,G,H",        0x580006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC,       0,              0,              IVIRT64, 0 },
-{"dmfc1",              "t,S",          0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LCD,     0,              I3,             0,      0 },
-{"dmfc1",              "t,G",          0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LCD,     0,              I3,             0,      0 },
-{"dmtc1",              "t,G",          0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|COD,     0,              I3,             0,      0 },
-{"dmtc1",              "t,S",          0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|COD,     0,              I3,             0,      0 },
+{"dmfc1",              "t,S",          0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LC,      0,              I3,             0,      0 },
+{"dmfc1",              "t,G",          0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LC,      0,              I3,             0,      0 },
+{"dmtc1",              "t,G",          0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM,      0,              I3,             0,      0 },
+{"dmtc1",              "t,S",          0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM,      0,              I3,             0,      0 },
 {"dmfc2",              "t,G",          0x00006d3c, 0xfc00ffff, WR_1|RD_C2,             0,              I3,             0,      0 },
 /*{"dmfc2",            "t,G,H",        0x58000283, 0xfc001fff, WR_1|RD_C2,             0,              I3,             0,      0 },*/
 {"dmtc2",              "t,G",          0x00007d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC,       0,              I3,             0,      0 },
@@ -825,13 +825,13 @@ const struct mips_opcode micromips_opcodes[] =
 {"maddu",              "7,s,t",        0x00001abc, 0xfc003fff, RD_2|RD_3|MOD_a,        0,              0,              D32,    0 },
 {"mfc0",               "t,G",          0x000000fc, 0xfc00ffff, WR_1|RD_C0,             0,              I1,             0,      0 },
 {"mfc0",               "t,G,H",        0x000000fc, 0xfc00c7ff, WR_1|RD_C0,             0,              I1,             0,      0 },
-{"mfc1",               "t,S",          0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|LCD,     0,              I1,             0,      0 },
-{"mfc1",               "t,G",          0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|LCD,     0,              I1,             0,      0 },
+{"mfc1",               "t,S",          0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|LC,      0,              I1,             0,      0 },
+{"mfc1",               "t,G",          0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|LC,      0,              I1,             0,      0 },
 {"mfc2",               "t,G",          0x00004d3c, 0xfc00ffff, WR_1|RD_C2,             0,              I1,             0,      0 },
 {"mfgc0",              "t,G",          0x000004fc, 0xfc00ffff, WR_1|RD_C0,             0,              0,              IVIRT,  0 },
 {"mfgc0",              "t,G,H",        0x000004fc, 0xfc00c7ff, WR_1|RD_C0,             0,              0,              IVIRT,  0 },
-{"mfhc1",              "t,S",          0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LCD,     0,              I1,             0,      0 },
-{"mfhc1",              "t,G",          0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LCD,     0,              I1,             0,      0 },
+{"mfhc1",              "t,S",          0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC,      0,              I1,             0,      0 },
+{"mfhc1",              "t,G",          0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC,      0,              I1,             0,      0 },
 {"mfhc2",              "t,G",          0x00008d3c, 0xfc00ffff, WR_1|RD_C2,             0,              I1,             0,      0 },
 {"mfhi",               "mj",               0x4600,     0xffe0, WR_1|RD_HI,             0,              I1,             0,      0 },
 {"mfhi",               "s",            0x00000d7c, 0xffe0ffff, WR_1|RD_HI,             0,              I1,             0,      0 },
@@ -871,13 +871,13 @@ const struct mips_opcode micromips_opcodes[] =
 {"msubu",              "7,s,t",        0x00003abc, 0xfc003fff, RD_2|RD_3|MOD_a,        0,              0,              D32,    0 },
 {"mtc0",               "t,G",          0x000002fc, 0xfc00ffff, RD_1|WR_C0|WR_CC,       0,              I1,             0,      0 },
 {"mtc0",               "t,G,H",        0x000002fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC,       0,              I1,             0,      0 },
-{"mtc1",               "t,S",          0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|COD,     0,              I1,             0,      0 },
-{"mtc1",               "t,G",          0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|COD,     0,              I1,             0,      0 },
+{"mtc1",               "t,S",          0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM,      0,              I1,             0,      0 },
+{"mtc1",               "t,G",          0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM,      0,              I1,             0,      0 },
 {"mtc2",               "t,G",          0x00005d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC,       0,              I1,             0,      0 },
 {"mtgc0",              "t,G",          0x000006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC,       0,              0,              IVIRT,  0 },
 {"mtgc0",              "t,G,H",        0x000006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC,       0,              0,              IVIRT,  0 },
-{"mthc1",              "t,S",          0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|COD,     0,              I1,             0,      0 },
-{"mthc1",              "t,G",          0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|COD,     0,              I1,             0,      0 },
+{"mthc1",              "t,S",          0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM,      0,              I1,             0,      0 },
+{"mthc1",              "t,G",          0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM,      0,              I1,             0,      0 },
 {"mthc2",              "t,G",          0x00009d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC,       0,              I1,             0,      0 },
 {"mthi",               "s",            0x00002d7c, 0xffe0ffff, RD_1|WR_HI,             0,              I1,             0,      0 },
 {"mthi",               "s,7",          0x0000207c, 0xffe03fff, RD_1|WR_HI,             0,              0,              D32,    0 },

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index ed74f90..6e3167f 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -190,10 +190,10 @@ decode_mips_operand (const char *p)
 
 /* Short hand so the lines aren't too long.  */
 
-#define LCD    INSN_LOAD_COPROC_DELAY
+#define LC     INSN_LOAD_COPROC
 #define UBD     INSN_UNCOND_BRANCH_DELAY
 #define CBD    INSN_COND_BRANCH_DELAY
-#define COD     INSN_COPROC_MOVE_DELAY
+#define CM     INSN_COPROC_MOVE
 #define CLD    (INSN_LOAD_MEMORY|INSN_COPROC_MEMORY_DELAY)
 #define CBL    INSN_COND_BRANCH_LIKELY
 #define NODS   INSN_NO_DELAY_SLOT
@@ -901,26 +901,26 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ceil.w.d",           "D,S",          0x4620000e, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              I2,             0,      SF },
 {"ceil.w.s",           "D,S",          0x4600000e, 0xffff003f, WR_1|RD_2|FP_S,         0,              I2,             0,      EE },
 /* cfc0 is at the bottom of the table.  */
-{"cfc1",               "t,G",          0x44400000, 0xffe007ff, WR_1|RD_C1|LCD,         0,              I1,             0,      0 },
-{"cfc1",               "t,S",          0x44400000, 0xffe007ff, WR_1|RD_C1|LCD,         0,              I1,             0,      0 },
+{"cfc1",               "t,G",          0x44400000, 0xffe007ff, WR_1|RD_C1|LC,          0,              I1,             0,      0 },
+{"cfc1",               "t,S",          0x44400000, 0xffe007ff, WR_1|RD_C1|LC,          0,              I1,             0,      0 },
 /* cfc2 is at the bottom of the table.  */
 /* cfc3 is at the bottom of the table.  */
-{"cftc1",              "d,E",          0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LCD,    0,              0,              MT32,   0 },
-{"cftc1",              "d,T",          0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LCD,    0,              0,              MT32,   0 },
-{"cftc2",              "d,E",          0x41000025, 0xffe007ff, WR_1|RD_C2|TRAP|LCD,    0,              0,              MT32,   IOCT|IOCTP|IOCT2 },
+{"cftc1",              "d,E",          0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC,     0,              0,              MT32,   0 },
+{"cftc1",              "d,T",          0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC,     0,              0,              MT32,   0 },
+{"cftc2",              "d,E",          0x41000025, 0xffe007ff, WR_1|RD_C2|TRAP|LC,     0,              0,              MT32,   IOCT|IOCTP|IOCT2 },
 {"cins32",             "t,r,+p,+s",    0x70000033, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 },
 {"cins",               "t,r,+P,+S",    0x70000033, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 }, /* cins32 */
 {"cins",               "t,r,+p,+S",    0x70000032, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 },
 {"clo",                        "U,s",          0x70000021, 0xfc0007ff, WR_1|RD_2,      0,              I32|N55,        0,      0 },
 {"clz",                        "U,s",          0x70000020, 0xfc0007ff, WR_1|RD_2,      0,              I32|N55,        0,      0 },
 /* ctc0 is at the bottom of the table.  */
-{"ctc1",               "t,G",          0x44c00000, 0xffe007ff, RD_1|WR_CC|COD,         0,              I1,             0,      0 },
-{"ctc1",               "t,S",          0x44c00000, 0xffe007ff, RD_1|WR_CC|COD,         0,              I1,             0,      0 },
+{"ctc1",               "t,G",          0x44c00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              I1,             0,      0 },
+{"ctc1",               "t,S",          0x44c00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              I1,             0,      0 },
 /* ctc2 is at the bottom of the table.  */
 /* ctc3 is at the bottom of the table.  */
-{"cttc1",              "t,G",          0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|COD,    0,              0,              MT32,   0 },
-{"cttc1",              "t,S",          0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|COD,    0,              0,              MT32,   0 },
-{"cttc2",              "t,g",          0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|COD,    0,              0,              MT32,   IOCT|IOCTP|IOCT2 },
+{"cttc1",              "t,G",          0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM,     0,              0,              MT32,   0 },
+{"cttc1",              "t,S",          0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM,     0,              0,              MT32,   0 },
+{"cttc2",              "t,g",          0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|CM,     0,              0,              MT32,   IOCT|IOCTP|IOCT2 },
 {"cvt.d.l",            "D,S",          0x46a00021, 0xffff003f, WR_1|RD_2|FP_D,         0,              I3_33,          0,      0 },
 {"cvt.d.s",            "D,S",          0x46000021, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              I1,             0,      SF },
 {"cvt.d.w",            "D,S",          0x46800021, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              I1,             0,      SF },
@@ -1008,20 +1008,20 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dmaccu",             "d,s,t",        0x00000069, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO,   0,              N412,           0,      0 },
 {"dmaccus",            "d,s,t",        0x00000469, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO,   0,              N412,           0,      0 },
 {"dmadd16",            "s,t",          0x00000029, 0xfc00ffff, RD_1|RD_2|MOD_LO,       0,              N411,           0,      0 },
-{"dmfc0",              "t,G",          0x40200000, 0xffe007ff, WR_1|RD_C0|LCD,         0,              I3,             0,      EE },
-{"dmfc0",              "t,G,H",        0x40200000, 0xffe007f8, WR_1|RD_C0|LCD,         0,              I64,            0,      0 },
-{"dmfgc0",             "t,G",          0x40600100, 0xffe007ff, WR_1|RD_C0|LCD,         0,              0,              IVIRT64, 0 },
-{"dmfgc0",             "t,G,H",        0x40600100, 0xffe007f8, WR_1|RD_C0|LCD,         0,              0,              IVIRT64, 0 },
+{"dmfc0",              "t,G",          0x40200000, 0xffe007ff, WR_1|RD_C0|LC,          0,              I3,             0,      EE },
+{"dmfc0",              "t,G,H",        0x40200000, 0xffe007f8, WR_1|RD_C0|LC,          0,              I64,            0,      0 },
+{"dmfgc0",             "t,G",          0x40600100, 0xffe007ff, WR_1|RD_C0|LC,          0,              0,              IVIRT64, 0 },
+{"dmfgc0",             "t,G,H",        0x40600100, 0xffe007f8, WR_1|RD_C0|LC,          0,              0,              IVIRT64, 0 },
 {"dmt",                        "",             0x41600bc1, 0xffffffff, TRAP,                   0,              0,              MT32,   0 },
 {"dmt",                        "t",            0x41600bc1, 0xffe0ffff, WR_1|TRAP,              0,              0,              MT32,   0 },
-{"dmtc0",              "t,G",          0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|COD,   0,              I3,             0,      EE },
-{"dmtc0",              "t,G,H",        0x40a00000, 0xffe007f8, RD_1|WR_C0|WR_CC|COD,   0,              I64,            0,      0 },
-{"dmtgc0",             "t,G",          0x40600300, 0xffe007ff, RD_1|WR_C0|WR_CC|COD,   0,              0,              IVIRT64, 0 },
-{"dmtgc0",             "t,G,H",        0x40600300, 0xffe007f8, RD_1|WR_C0|WR_CC|COD,   0,              0,              IVIRT64, 0 },
-{"dmfc1",              "t,S",          0x44200000, 0xffe007ff, WR_1|RD_2|LCD|FP_D,     0,              I3,             0,      SF },
-{"dmfc1",              "t,G",          0x44200000, 0xffe007ff, WR_1|RD_2|LCD|FP_D,     0,              I3,             0,      SF },
-{"dmtc1",              "t,S",          0x44a00000, 0xffe007ff, RD_1|WR_2|COD|FP_D,     0,              I3,             0,      SF },
-{"dmtc1",              "t,G",          0x44a00000, 0xffe007ff, RD_1|WR_2|COD|FP_D,     0,              I3,             0,      SF },
+{"dmtc0",              "t,G",          0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              I3,             0,      EE },
+{"dmtc0",              "t,G,H",        0x40a00000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,    0,              I64,            0,      0 },
+{"dmtgc0",             "t,G",          0x40600300, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              0,              IVIRT64, 0 },
+{"dmtgc0",             "t,G,H",        0x40600300, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,   0,               0,              IVIRT64, 0 },
+{"dmfc1",              "t,S",          0x44200000, 0xffe007ff, WR_1|RD_2|LC|FP_D,      0,              I3,             0,      SF },
+{"dmfc1",              "t,G",          0x44200000, 0xffe007ff, WR_1|RD_2|LC|FP_D,     0,               I3,             0,      SF },
+{"dmtc1",              "t,S",          0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D,      0,              I3,             0,      SF },
+{"dmtc1",              "t,G",          0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D,     0,               I3,             0,      SF },
 /* dmfc2 is at the bottom of the table.  */
 /* dmtc2 is at the bottom of the table.  */
 /* dmfc3 is at the bottom of the table.  */
@@ -1276,48 +1276,48 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"max.ob",             "D,S,Q",        0x48000007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"max.qh",             "X,Y,Q",        0x78200007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"max.s",              "D,S,T",        0x46000028, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              EE,             0,      0 },
-{"mfbpc",              "t",            0x4000c000, 0xffe0ffff, WR_1|RD_C0|LCD,         0,              EE,             0,      0 },
-{"mfdab",              "t",            0x4000c004, 0xffe0ffff, WR_1|RD_C0|LCD,         0,              EE,             0,      0 },
-{"mfdabm",             "t",            0x4000c005, 0xffe0ffff, WR_1|RD_C0|LCD,         0,              EE,             0,      0 },
-{"mfdvb",              "t",            0x4000c006, 0xffe0ffff, WR_1|RD_C0|LCD,         0,              EE,             0,      0 },
-{"mfdvbm",             "t",            0x4000c007, 0xffe0ffff, WR_1|RD_C0|LCD,         0,              EE,             0,      0 },
-{"mfiab",              "t",            0x4000c002, 0xffe0ffff, WR_1|RD_C0|LCD,         0,              EE,             0,      0 },
-{"mfiabm",             "t",            0x4000c003, 0xffe0ffff, WR_1|RD_C0|LCD,         0,              EE,             0,      0 },
-{"mfpc",               "t,P",          0x4000c801, 0xffe0ffc1, WR_1|RD_C0|LCD,         0,              M1|N5|EE,       0,      0 },
-{"mfps",               "t,P",          0x4000c800, 0xffe0ffc1, WR_1|RD_C0|LCD,         0,              M1|N5|EE,       0,      0 },
+{"mfbpc",              "t",            0x4000c000, 0xffe0ffff, WR_1|RD_C0|LC,          0,              EE,             0,      0 },
+{"mfdab",              "t",            0x4000c004, 0xffe0ffff, WR_1|RD_C0|LC,          0,              EE,             0,      0 },
+{"mfdabm",             "t",            0x4000c005, 0xffe0ffff, WR_1|RD_C0|LC,          0,              EE,             0,      0 },
+{"mfdvb",              "t",            0x4000c006, 0xffe0ffff, WR_1|RD_C0|LC,          0,              EE,             0,      0 },
+{"mfdvbm",             "t",            0x4000c007, 0xffe0ffff, WR_1|RD_C0|LC,          0,              EE,             0,      0 },
+{"mfiab",              "t",            0x4000c002, 0xffe0ffff, WR_1|RD_C0|LC,          0,              EE,             0,      0 },
+{"mfiabm",             "t",            0x4000c003, 0xffe0ffff, WR_1|RD_C0|LC,          0,              EE,             0,      0 },
+{"mfpc",               "t,P",          0x4000c801, 0xffe0ffc1, WR_1|RD_C0|LC,          0,              M1|N5|EE,       0,      0 },
+{"mfps",               "t,P",          0x4000c800, 0xffe0ffc1, WR_1|RD_C0|LC,          0,              M1|N5|EE,       0,      0 },
 {"mftacx",             "d",            0x41020021, 0xffff07ff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
 {"mftacx",             "d,*",          0x41020021, 0xfff307ff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
-{"mftc0",              "d,+t",         0x41000000, 0xffe007ff, WR_1|RD_C0|TRAP|LCD,    0,              0,              MT32,   0 },
-{"mftc0",              "d,E,H",        0x41000000, 0xffe007f8, WR_1|RD_C0|TRAP|LCD,    0,              0,              MT32,   0 },
-{"mftc1",              "d,T",          0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LCD|FP_S, 0,             0,              MT32,   0 },
-{"mftc1",              "d,E",          0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LCD|FP_S, 0,             0,              MT32,   0 },
-{"mftc2",              "d,E",          0x41000024, 0xffe007ff, WR_1|RD_C2|TRAP|LCD,    0,              0,              MT32,   IOCT|IOCTP|IOCT2 },
+{"mftc0",              "d,+t",         0x41000000, 0xffe007ff, WR_1|RD_C0|TRAP|LC,     0,              0,              MT32,   0 },
+{"mftc0",              "d,E,H",        0x41000000, 0xffe007f8, WR_1|RD_C0|TRAP|LC,     0,              0,              MT32,   0 },
+{"mftc1",              "d,T",          0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_S, 0,              0,              MT32,   0 },
+{"mftc1",              "d,E",          0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_S, 0,              0,              MT32,   0 },
+{"mftc2",              "d,E",          0x41000024, 0xffe007ff, WR_1|RD_C2|TRAP|LC,     0,              0,              MT32,   IOCT|IOCTP|IOCT2 },
 {"mftdsp",             "d",            0x41100021, 0xffff07ff, WR_1|TRAP,              0,              0,              MT32,   0 },
 {"mftgpr",             "d,t",          0x41000020, 0xffe007ff, WR_1|RD_2|TRAP,         0,              0,              MT32,   0 },
-{"mfthc1",             "d,T",          0x41000032, 0xffe007ff, WR_1|RD_2|TRAP|LCD|FP_D, 0,             0,              MT32,   0 },
-{"mfthc1",             "d,E",          0x41000032, 0xffe007ff, WR_1|RD_2|TRAP|LCD|FP_D, 0,             0,              MT32,   0 },
-{"mfthc2",             "d,E",          0x41000034, 0xffe007ff, WR_1|RD_C2|TRAP|LCD,    0,              0,              MT32,   IOCT|IOCTP|IOCT2 },
+{"mfthc1",             "d,T",          0x41000032, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_D, 0,              0,              MT32,   0 },
+{"mfthc1",             "d,E",          0x41000032, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_D, 0,              0,              MT32,   0 },
+{"mfthc2",             "d,E",          0x41000034, 0xffe007ff, WR_1|RD_C2|TRAP|LC,     0,              0,              MT32,   IOCT|IOCTP|IOCT2 },
 {"mfthi",              "d",            0x41010021, 0xffff07ff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
 {"mfthi",              "d,*",          0x41010021, 0xfff307ff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
 {"mftlo",              "d",            0x41000021, 0xffff07ff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
 {"mftlo",              "d,*",          0x41000021, 0xfff307ff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
 {"mftr",               "d,t,!,H,$",    0x41000000, 0xffe007c8, WR_1|TRAP,              0,              0,              MT32,   0 },
-{"mfc0",               "t,G",          0x40000000, 0xffe007ff, WR_1|RD_C0|LCD,         0,              I1,             0,      0 },
-{"mfc0",               "t,G,H",        0x40000000, 0xffe007f8, WR_1|RD_C0|LCD,         0,              I32,            0,      0 },
-{"mfgc0",              "t,G",          0x40600000, 0xffe007ff, WR_1|RD_C0|LCD,         0,              0,              IVIRT,  0 },
-{"mfgc0",              "t,G,H",        0x40600000, 0xffe007f8, WR_1|RD_C0|LCD,         0,              0,              IVIRT,  0 },
-{"mfhc0",              "t,G",          0x40400000, 0xffe007ff, WR_1|RD_C0|LCD,         0,              I33,            XPA,    0 },
-{"mfhc0",              "t,G,H",        0x40400000, 0xffe007f8, WR_1|RD_C0|LCD,         0,              I33,            XPA,    0 },
-{"mfhgc0",             "t,G",          0x40600400, 0xffe007ff, WR_1|RD_C0|LCD,         0,              I33,            IVIRT|XPA,      0 },
-{"mfhgc0",             "t,G,H",        0x40600400, 0xffe007f8, WR_1|RD_C0|LCD,         0,              I33,            IVIRT|XPA,      0 },
-{"mfc1",               "t,S",          0x44000000, 0xffe007ff, WR_1|RD_2|LCD|FP_S,     0,              I1,             0,      0 },
-{"mfc1",               "t,G",          0x44000000, 0xffe007ff, WR_1|RD_2|LCD|FP_S,     0,              I1,             0,      0 },
-{"mfhc1",              "t,S",          0x44600000, 0xffe007ff, WR_1|RD_2|LCD|FP_D,     0,              I33,            0,      0 },
-{"mfhc1",              "t,G",          0x44600000, 0xffe007ff, WR_1|RD_2|LCD|FP_D,     0,              I33,            0,      0 },
+{"mfc0",               "t,G",          0x40000000, 0xffe007ff, WR_1|RD_C0|LC,          0,              I1,             0,      0 },
+{"mfc0",               "t,G,H",        0x40000000, 0xffe007f8, WR_1|RD_C0|LC,          0,              I32,            0,      0 },
+{"mfgc0",              "t,G",          0x40600000, 0xffe007ff, WR_1|RD_C0|LC,          0,              0,              IVIRT,  0 },
+{"mfgc0",              "t,G,H",        0x40600000, 0xffe007f8, WR_1|RD_C0|LC,          0,              0,              IVIRT,  0 },
+{"mfhc0",              "t,G",          0x40400000, 0xffe007ff, WR_1|RD_C0|LC,          0,              I33,            XPA,    0 },
+{"mfhc0",              "t,G,H",        0x40400000, 0xffe007f8, WR_1|RD_C0|LC,          0,              I33,            XPA,    0 },
+{"mfhgc0",             "t,G",          0x40600400, 0xffe007ff, WR_1|RD_C0|LC,          0,              I33,            IVIRT|XPA,      0 },
+{"mfhgc0",             "t,G,H",        0x40600400, 0xffe007f8, WR_1|RD_C0|LC,          0,              I33,            IVIRT|XPA,      0 },
+{"mfc1",               "t,S",          0x44000000, 0xffe007ff, WR_1|RD_2|LC|FP_S,      0,              I1,             0,      0 },
+{"mfc1",               "t,G",          0x44000000, 0xffe007ff, WR_1|RD_2|LC|FP_S,      0,              I1,             0,      0 },
+{"mfhc1",              "t,S",          0x44600000, 0xffe007ff, WR_1|RD_2|LC|FP_D,      0,              I33,            0,      0 },
+{"mfhc1",              "t,G",          0x44600000, 0xffe007ff, WR_1|RD_2|LC|FP_D,      0,              I33,            0,      0 },
 /* mfc2 is at the bottom of the table.  */
 /* mfhc2 is at the bottom of the table.  */
 /* mfc3 is at the bottom of the table.  */
-{"mfdr",               "t,G",          0x7000003d, 0xffe007ff, WR_1|RD_C0|LCD,         0,              N5,             0,      0 },
+{"mfdr",               "t,G",          0x7000003d, 0xffe007ff, WR_1|RD_C0|LC,          0,              N5,             0,      0 },
 {"mfhi",               "d",            0x00000010, 0xffff07ff, WR_1|RD_HI,             0,              I1,             0,      0 },
 {"mfhi",               "d,9",          0x00000010, 0xff9f07ff, WR_1|RD_HI,             0,              0,              D32,    0 },
 {"mfhi1",              "d",            0x70000010, 0xffff07ff, WR_1|RD_HI,             0,              EE,             0,      0 },
@@ -1390,31 +1390,31 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msubu",              "s,t",          0x0000001f, 0xfc00ffff, RD_1|RD_2|WR_HILO,      0,              L1,             0,      0 },
 {"msubu",              "s,t",          0x70000005, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,              I32|N55,        0,      0 },
 {"msubu",              "7,s,t",        0x70000005, 0xfc00e7ff, RD_2|RD_3|MOD_a,        0,              0,              D32,    0 },
-{"mtbpc",              "t",            0x4080c000, 0xffe0ffff, RD_1|WR_C0|COD,         0,              EE,             0,      0 },
-{"mtdab",              "t",            0x4080c004, 0xffe0ffff, RD_1|WR_C0|COD,         0,              EE,             0,      0 },
-{"mtdabm",             "t",            0x4080c005, 0xffe0ffff, RD_1|WR_C0|COD,         0,              EE,             0,      0 },
-{"mtdvb",              "t",            0x4080c006, 0xffe0ffff, RD_1|WR_C0|COD,         0,              EE,             0,      0 },
-{"mtdvbm",             "t",            0x4080c007, 0xffe0ffff, RD_1|WR_C0|COD,         0,              EE,             0,      0 },
-{"mtiab",              "t",            0x4080c002, 0xffe0ffff, RD_1|WR_C0|COD,         0,              EE,             0,      0 },
-{"mtiabm",             "t",            0x4080c003, 0xffe0ffff, RD_1|WR_C0|COD,         0,              EE,             0,      0 },
-{"mtpc",               "t,P",          0x4080c801, 0xffe0ffc1, RD_1|WR_C0|COD,         0,              M1|N5|EE,       0,      0 },
-{"mtps",               "t,P",          0x4080c800, 0xffe0ffc1, RD_1|WR_C0|COD,         0,              M1|N5|EE,       0,      0 },
-{"mtc0",               "t,G",          0x40800000, 0xffe007ff, RD_1|WR_C0|WR_CC|COD,   0,              I1,             0,      0 },
-{"mtc0",               "t,G,H",        0x40800000, 0xffe007f8, RD_1|WR_C0|WR_CC|COD,   0,              I32,            0,      0 },
-{"mtgc0",              "t,G",          0x40600200, 0xffe007ff, RD_1|WR_C0|WR_CC|COD,   0,              0,              IVIRT,  0 },
-{"mtgc0",              "t,G,H",        0x40600200, 0xffe007f8, RD_1|WR_C0|WR_CC|COD,   0,              0,              IVIRT,  0 },
-{"mthc0",              "t,G",          0x40c00000, 0xffe007ff, RD_1|WR_C0|WR_CC|COD,   0,              I33,            XPA,    0 },
-{"mthc0",              "t,G,H",        0x40c00000, 0xffe007f8, RD_1|WR_C0|WR_CC|COD,   0,              I33,            XPA,    0 },
-{"mthgc0",             "t,G",          0x40600600, 0xffe007ff, RD_1|WR_C0|WR_CC|COD,   0,              I33,            IVIRT|XPA,      0 },
-{"mthgc0",             "t,G,H",        0x40600600, 0xffe007f8, RD_1|WR_C0|WR_CC|COD,   0,              I33,            IVIRT|XPA,      0 },
-{"mtc1",               "t,S",          0x44800000, 0xffe007ff, RD_1|WR_2|COD|FP_S,     0,              I1,             0,      0 },
-{"mtc1",               "t,G",          0x44800000, 0xffe007ff, RD_1|WR_2|COD|FP_S,     0,              I1,             0,      0 },
-{"mthc1",              "t,S",          0x44e00000, 0xffe007ff, RD_1|WR_2|COD|FP_D,     0,              I33,            0,      0 },
-{"mthc1",              "t,G",          0x44e00000, 0xffe007ff, RD_1|WR_2|COD|FP_D,     0,              I33,            0,      0 },
+{"mtbpc",              "t",            0x4080c000, 0xffe0ffff, RD_1|WR_C0|CM,          0,              EE,             0,      0 },
+{"mtdab",              "t",            0x4080c004, 0xffe0ffff, RD_1|WR_C0|CM,          0,              EE,             0,      0 },
+{"mtdabm",             "t",            0x4080c005, 0xffe0ffff, RD_1|WR_C0|CM,          0,              EE,             0,      0 },
+{"mtdvb",              "t",            0x4080c006, 0xffe0ffff, RD_1|WR_C0|CM,          0,              EE,             0,      0 },
+{"mtdvbm",             "t",            0x4080c007, 0xffe0ffff, RD_1|WR_C0|CM,          0,              EE,             0,      0 },
+{"mtiab",              "t",            0x4080c002, 0xffe0ffff, RD_1|WR_C0|CM,          0,              EE,             0,      0 },
+{"mtiabm",             "t",            0x4080c003, 0xffe0ffff, RD_1|WR_C0|CM,          0,              EE,             0,      0 },
+{"mtpc",               "t,P",          0x4080c801, 0xffe0ffc1, RD_1|WR_C0|CM,          0,              M1|N5|EE,       0,      0 },
+{"mtps",               "t,P",          0x4080c800, 0xffe0ffc1, RD_1|WR_C0|CM,          0,              M1|N5|EE,       0,      0 },
+{"mtc0",               "t,G",          0x40800000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              I1,             0,      0 },
+{"mtc0",               "t,G,H",        0x40800000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,    0,              I32,            0,      0 },
+{"mtgc0",              "t,G",          0x40600200, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              0,              IVIRT,  0 },
+{"mtgc0",              "t,G,H",        0x40600200, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,   0,               0,              IVIRT,  0 },
+{"mthc0",              "t,G",          0x40c00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              I33,            XPA,    0 },
+{"mthc0",              "t,G,H",        0x40c00000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,    0,              I33,            XPA,    0 },
+{"mthgc0",             "t,G",          0x40600600, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              I33,            IVIRT|XPA,      0 },
+{"mthgc0",             "t,G,H",        0x40600600, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,    0,              I33,            IVIRT|XPA,      0 },
+{"mtc1",               "t,S",          0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S,      0,              I1,             0,      0 },
+{"mtc1",               "t,G",          0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S,      0,              I1,             0,      0 },
+{"mthc1",              "t,S",          0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D,      0,              I33,            0,      0 },
+{"mthc1",              "t,G",          0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D,      0,              I33,            0,      0 },
 /* mtc2 is at the bottom of the table.  */
 /* mthc2 is at the bottom of the table.  */
 /* mtc3 is at the bottom of the table.  */
-{"mtdr",               "t,G",          0x7080003d, 0xffe007ff, RD_1|WR_C0|COD,         0,              N5,             0,      0 },
+{"mtdr",               "t,G",          0x7080003d, 0xffe007ff, RD_1|WR_C0|CM,          0,              N5,             0,      0 },
 {"mthi",               "s",            0x00000011, 0xfc1fffff, RD_1|WR_HI,             0,              I1,             0,      0 },
 {"mthi",               "s,7",          0x00000011, 0xfc1fe7ff, RD_1|WR_HI,             0,              0,              D32,    0 },
 {"mthi1",              "s",            0x70000011, 0xfc1fffff, RD_1|WR_HI,             0,              EE,             0,      0 },
@@ -1432,18 +1432,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtsa",               "s",            0x00000029, 0xfc1fffff, RD_1,                   0,              EE,             0,      0 },
 {"mtsab",              "s,j",          0x04180000, 0xfc1f0000, RD_1,                   0,              EE,             0,      0 },
 {"mtsah",              "s,j",          0x04190000, 0xfc1f0000, RD_1,                   0,              EE,             0,      0 },
-{"mttc0",              "t,G",          0x41800000, 0xffe007ff, RD_1|WR_C0|WR_CC|TRAP|COD, 0,           0,              MT32,   0 },
-{"mttc0",              "t,G,H",        0x41800000, 0xffe007f8, RD_1|WR_C0|WR_CC|TRAP|COD, 0,           0,              MT32,   0 },
-{"mttc1",              "t,S",          0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|COD|FP_S, 0,             0,              MT32,   0 },
-{"mttc1",              "t,G",          0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|COD|FP_S, 0,             0,              MT32,   0 },
-{"mttc2",              "t,g",          0x41800024, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|COD, 0,           0,              MT32,   IOCT|IOCTP|IOCT2 },
+{"mttc0",              "t,G",          0x41800000, 0xffe007ff, RD_1|WR_C0|WR_CC|TRAP|CM, 0,            0,              MT32,   0 },
+{"mttc0",              "t,G,H",        0x41800000, 0xffe007f8, RD_1|WR_C0|WR_CC|TRAP|CM, 0,            0,              MT32,   0 },
+{"mttc1",              "t,S",          0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_S, 0,              0,              MT32,   0 },
+{"mttc1",              "t,G",          0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_S, 0,              0,              MT32,   0 },
+{"mttc2",              "t,g",          0x41800024, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0,            0,              MT32,   IOCT|IOCTP|IOCT2 },
 {"mttacx",             "t",            0x41801021, 0xffe0ffff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
 {"mttacx",             "t,&",          0x41801021, 0xffe09fff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
 {"mttdsp",             "t",            0x41808021, 0xffe0ffff, RD_1|TRAP,              0,              0,              MT32,   0 },
 {"mttgpr",             "t,d",          0x41800020, 0xffe007ff, RD_1|WR_2|TRAP,         0,              0,              MT32,   0 },
-{"mtthc1",             "t,S",          0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|COD|FP_D, 0,             0,              MT32,   0 },
-{"mtthc1",             "t,G",          0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|COD|FP_D, 0,             0,              MT32,   0 },
-{"mtthc2",             "t,g",          0x41800034, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|COD, 0,           0,              MT32,   IOCT|IOCTP|IOCT2 },
+{"mtthc1",             "t,S",          0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_D, 0,              0,              MT32,   0 },
+{"mtthc1",             "t,G",          0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_D, 0,              0,              MT32,   0 },
+{"mtthc2",             "t,g",          0x41800034, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0,            0,              MT32,   IOCT|IOCTP|IOCT2 },
 {"mtthi",              "t",            0x41800821, 0xffe0ffff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
 {"mtthi",              "t,&",          0x41800821, 0xffe09fff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
 {"mttlo",              "t",            0x41800021, 0xffe0ffff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
@@ -1971,8 +1971,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the 
    mfhc0 and mthc0 XPA instructions, so they have been placed here 
    to allow the XPA instructions to take precedence.  */
-{"ctc0",               "t,G",          0x40c00000, 0xffe007ff, RD_1|WR_CC|COD,         0,              I1,             0,      IOCT|IOCTP|IOCT2 },
-{"cfc0",               "t,G",          0x40400000, 0xffe007ff, WR_1|RD_C0|LCD,         0,              I1,             0,      IOCT|IOCTP|IOCT2 },
+{"ctc0",               "t,G",          0x40c00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              I1,             0,      IOCT|IOCTP|IOCT2 },
+{"cfc0",               "t,G",          0x40400000, 0xffe007ff, WR_1|RD_C0|LC,          0,              I1,             0,      IOCT|IOCTP|IOCT2 },
 
 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
    instructions so they are here for the latters to take precedence.  */
@@ -1984,30 +1984,30 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"bc2t",               "N,p",          0x49010000, 0xffe30000, RD_CC|CBD,              0,              I32,            0,      IOCT|IOCTP|IOCT2 },
 {"bc2tl",              "p",            0x49030000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      IOCT|IOCTP|IOCT2 },
 {"bc2tl",              "N,p",          0x49030000, 0xffe30000, RD_CC|CBL,              0,              I32,            0,      IOCT|IOCTP|IOCT2 },
-{"cfc2",               "t,G",          0x48400000, 0xffe007ff, WR_1|RD_C2|LCD,         0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"cfc2",               "t,+9",         0x48400000, 0xffe007ff, WR_1|RD_C2|LCD,         0,              EE,             0,      0 },
-{"cfc2.i",             "t,+9",         0x48400001, 0xffe007ff, WR_1|RD_C2|LCD,         0,              EE,             0,      0 },
-{"cfc2.ni",            "t,+9",         0x48400000, 0xffe007ff, WR_1|RD_C2|LCD,         0,              EE,             0,      0 },
-{"ctc2",               "t,G",          0x48c00000, 0xffe007ff, RD_1|WR_CC|COD,         0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"ctc2",               "t,+9",         0x48c00000, 0xffe007ff, RD_1|WR_CC|COD,         0,              EE,             0,      0 },
-{"ctc2.i",             "t,+9",         0x48c00001, 0xffe007ff, RD_1|WR_CC|COD,         0,              EE,             0,      0 },
-{"ctc2.ni",            "t,+9",         0x48c00000, 0xffe007ff, RD_1|WR_CC|COD,         0,              EE,             0,      0 },
-{"dmfc2",              "t,i",          0x48200000, 0xffe00000, WR_1|RD_C2|LCD,         0,              IOCT,           0,      0 },
-{"dmfc2",              "t,G",          0x48200000, 0xffe007ff, WR_1|RD_C2|LCD,         0,              I3,             0,      IOCT|IOCTP|IOCT2|EE },
-{"dmfc2",              "t,G,H",        0x48200000, 0xffe007f8, WR_1|RD_C2|LCD,         0,              I64,            0,      IOCT|IOCTP|IOCT2 },
-{"dmtc2",              "t,i",          0x48a00000, 0xffe00000, RD_1|WR_C2|WR_CC|COD,   0,              IOCT,           0,      0 },
-{"dmtc2",              "t,G",          0x48a00000, 0xffe007ff, RD_1|WR_C2|WR_CC|COD,   0,              I3,             0,      IOCT|IOCTP|IOCT2|EE },
-{"dmtc2",              "t,G,H",        0x48a00000, 0xffe007f8, RD_1|WR_C2|WR_CC|COD,   0,              I64,            0,      IOCT|IOCTP|IOCT2 },
-{"mfc2",               "t,G",          0x48000000, 0xffe007ff, WR_1|RD_C2|LCD,         0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"mfc2",               "t,G,H",        0x48000000, 0xffe007f8, WR_1|RD_C2|LCD,         0,              I32,            0,      IOCT|IOCTP|IOCT2 },
-{"mfhc2",              "t,G",          0x48600000, 0xffe007ff, WR_1|RD_C2|LCD,         0,              I33,            0,      IOCT|IOCTP|IOCT2 },
-{"mfhc2",              "t,G,H",        0x48600000, 0xffe007f8, WR_1|RD_C2|LCD,         0,              I33,            0,      IOCT|IOCTP|IOCT2 },
-{"mfhc2",              "t,i",          0x48600000, 0xffe00000, WR_1|RD_C2|LCD,         0,              I33,            0,      IOCT|IOCTP|IOCT2 },
-{"mtc2",               "t,G",          0x48800000, 0xffe007ff, RD_1|WR_C2|WR_CC|COD,   0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"mtc2",               "t,G,H",        0x48800000, 0xffe007f8, RD_1|WR_C2|WR_CC|COD,   0,              I32,            0,      IOCT|IOCTP|IOCT2 },
-{"mthc2",              "t,G",          0x48e00000, 0xffe007ff, RD_1|WR_C2|WR_CC|COD,   0,              I33,            0,      IOCT|IOCTP|IOCT2 },
-{"mthc2",              "t,G,H",        0x48e00000, 0xffe007f8, RD_1|WR_C2|WR_CC|COD,   0,              I33,            0,      IOCT|IOCTP|IOCT2 },
-{"mthc2",              "t,i",          0x48e00000, 0xffe00000, RD_1|WR_C2|WR_CC|COD,   0,              I33,            0,      IOCT|IOCTP|IOCT2 },
+{"cfc2",               "t,G",          0x48400000, 0xffe007ff, WR_1|RD_C2|LC,          0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
+{"cfc2",               "t,+9",         0x48400000, 0xffe007ff, WR_1|RD_C2|LC,          0,              EE,             0,      0 },
+{"cfc2.i",             "t,+9",         0x48400001, 0xffe007ff, WR_1|RD_C2|LC,          0,              EE,             0,      0 },
+{"cfc2.ni",            "t,+9",         0x48400000, 0xffe007ff, WR_1|RD_C2|LC,          0,              EE,             0,      0 },
+{"ctc2",               "t,G",          0x48c00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
+{"ctc2",               "t,+9",         0x48c00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              EE,             0,      0 },
+{"ctc2.i",             "t,+9",         0x48c00001, 0xffe007ff, RD_1|WR_CC|CM,          0,              EE,             0,      0 },
+{"ctc2.ni",            "t,+9",         0x48c00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              EE,             0,      0 },
+{"dmfc2",              "t,i",          0x48200000, 0xffe00000, WR_1|RD_C2|LC,          0,              IOCT,           0,      0 },
+{"dmfc2",              "t,G",          0x48200000, 0xffe007ff, WR_1|RD_C2|LC,          0,              I3,             0,      IOCT|IOCTP|IOCT2|EE },
+{"dmfc2",              "t,G,H",        0x48200000, 0xffe007f8, WR_1|RD_C2|LC,          0,              I64,            0,      IOCT|IOCTP|IOCT2 },
+{"dmtc2",              "t,i",          0x48a00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM,    0,              IOCT,           0,      0 },
+{"dmtc2",              "t,G",          0x48a00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM,    0,              I3,             0,      IOCT|IOCTP|IOCT2|EE },
+{"dmtc2",              "t,G,H",        0x48a00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM,    0,              I64,            0,      IOCT|IOCTP|IOCT2 },
+{"mfc2",               "t,G",          0x48000000, 0xffe007ff, WR_1|RD_C2|LC,          0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
+{"mfc2",               "t,G,H",        0x48000000, 0xffe007f8, WR_1|RD_C2|LC,          0,              I32,            0,      IOCT|IOCTP|IOCT2 },
+{"mfhc2",              "t,G",          0x48600000, 0xffe007ff, WR_1|RD_C2|LC,          0,              I33,            0,      IOCT|IOCTP|IOCT2 },
+{"mfhc2",              "t,G,H",        0x48600000, 0xffe007f8, WR_1|RD_C2|LC,          0,              I33,            0,      IOCT|IOCTP|IOCT2 },
+{"mfhc2",              "t,i",          0x48600000, 0xffe00000, WR_1|RD_C2|LC,          0,              I33,            0,      IOCT|IOCTP|IOCT2 },
+{"mtc2",               "t,G",          0x48800000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM,    0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
+{"mtc2",               "t,G,H",        0x48800000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM,    0,              I32,            0,      IOCT|IOCTP|IOCT2 },
+{"mthc2",              "t,G",          0x48e00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM,    0,              I33,            0,      IOCT|IOCTP|IOCT2 },
+{"mthc2",              "t,G,H",        0x48e00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM,    0,              I33,            0,      IOCT|IOCTP|IOCT2 },
+{"mthc2",              "t,i",          0x48e00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM,    0,              I33,            0,      IOCT|IOCTP|IOCT2 },
 {"qmfc2",              "t,+6",         0x48200000, 0xffe007ff, WR_1|RD_C2,             0,              EE,             0,      0 },
 {"qmfc2.i",            "t,+6",         0x48200001, 0xffe007ff, WR_1|RD_C2,             0,              EE,             0,      0 },
 {"qmfc2.ni",           "t,+6",         0x48200000, 0xffe007ff, WR_1|RD_C2,             0,              EE,             0,      0 },
@@ -2020,14 +2020,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"bc3fl",              "p",            0x4d020000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      IOCT|IOCTP|IOCT2|EE },
 {"bc3t",               "p",            0x4d010000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
 {"bc3tl",              "p",            0x4d030000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      IOCT|IOCTP|IOCT2|EE },
-{"cfc3",               "t,G",          0x4c400000, 0xffe007ff, WR_1|RD_C3|LCD,         0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"ctc3",               "t,G",          0x4cc00000, 0xffe007ff, RD_1|WR_CC|COD,         0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"dmfc3",              "t,G",          0x4c200000, 0xffe007ff, WR_1|RD_C3|LCD,         0,              I3,             0,      IOCT|IOCTP|IOCT2|EE },
-{"dmtc3",              "t,G",          0x4ca00000, 0xffe007ff, RD_1|WR_C3|WR_CC|COD,   0,              I3,             0,      IOCT|IOCTP|IOCT2|EE },
-{"mfc3",               "t,G",          0x4c000000, 0xffe007ff, WR_1|RD_C3|LCD,         0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"mfc3",               "t,G,H",        0x4c000000, 0xffe007f8, WR_1|RD_C3|LCD,         0,              I32,            0,      IOCT|IOCTP|IOCT2|EE },
-{"mtc3",               "t,G",          0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|COD,   0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"mtc3",               "t,G,H",        0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|COD,   0,              I32,            0,      IOCT|IOCTP|IOCT2|EE },
+{"cfc3",               "t,G",          0x4c400000, 0xffe007ff, WR_1|RD_C3|LC,          0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
+{"ctc3",               "t,G",          0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
+{"dmfc3",              "t,G",          0x4c200000, 0xffe007ff, WR_1|RD_C3|LC,          0,              I3,             0,      IOCT|IOCTP|IOCT2|EE },
+{"dmtc3",              "t,G",          0x4ca00000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM,    0,              I3,             0,      IOCT|IOCTP|IOCT2|EE },
+{"mfc3",               "t,G",          0x4c000000, 0xffe007ff, WR_1|RD_C3|LC,          0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
+{"mfc3",               "t,G,H",        0x4c000000, 0xffe007f8, WR_1|RD_C3|LC,          0,              I32,            0,      IOCT|IOCTP|IOCT2|EE },
+{"mtc3",               "t,G",          0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM,    0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
+{"mtc3",               "t,G,H",        0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|CM,    0,              I32,            0,      IOCT|IOCTP|IOCT2|EE },
 
   /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
      4010 any more, so move this insn out of the way.  If the object
@@ -3050,8 +3050,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ffint_s.d",          "+d,+e",        0x7b3d001e, 0xffff003f, WR_1|RD_2,              0,              0,              MSA,    0 },
 {"ffint_u.w",          "+d,+e",        0x7b3e001e, 0xffff003f, WR_1|RD_2,              0,              0,              MSA,    0 },
 {"ffint_u.d",          "+d,+e",        0x7b3f001e, 0xffff003f, WR_1|RD_2,              0,              0,              MSA,    0 },
-{"ctcmsa",             "+l,d",         0x783e0019, 0xffff003f, RD_2|COD,               0,              0,              MSA,    0 },
-{"cfcmsa",             "+k,+n",        0x787e0019, 0xffff003f, WR_1|COD,               0,              0,              MSA,    0 },
+{"ctcmsa",             "+l,d",         0x783e0019, 0xffff003f, RD_2|CM,                0,              0,              MSA,    0 },
+{"cfcmsa",             "+k,+n",        0x787e0019, 0xffff003f, WR_1|CM,                0,              0,              MSA,    0 },
 {"move.v",             "+d,+e",        0x78be0019, 0xffff003f, WR_1|RD_2,              0,              0,              MSA,    0 },
 {"lsa",                        "d,v,t,+~",     0x00000005, 0xfc00073f, WR_1|RD_2|RD_3,         0,              0,              MSA,    0 },
 {"dlsa",               "d,v,t,+~",     0x00000015, 0xfc00073f, WR_1|RD_2|RD_3,         0,              0,              MSA64,  0 },