ppc: enable msgclr and msgsnd on Power8

According to my reading of the spec it was an oversight for them to
not having got enabled when Power8 support got added.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 1e9d7ef..b391709 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,6 +1,10 @@
 2014-10-28  Alan Modra  <amodra@gmail.com>
 
        Apply truck patches
+       2014-10-21  Jan Beulich  <jbeulich@suse.com>
+       * gas/ppc/power8.s: Test msgclr and msgsnd.
+       * gas/ppc/power8.d: Adjust accordingly.
+
        2014-10-18  Alan Modra  <amodra@gmail.com>
        * gas/i386/inval-equ-2.l: Adjust.
 

diff --git a/gas/testsuite/gas/ppc/power8.d b/gas/testsuite/gas/ppc/power8.d
index 2d576e6..e66951e 100644 (file)
--- a/gas/testsuite/gas/ppc/power8.d
+++ b/gas/testsuite/gas/ppc/power8.d
@@ -150,4 +150,6 @@ Disassembly of section \.text:
  230:  (f3 60 d5 2d|2d d5 60 f3)       xscvspdpn vs59,vs26
  234:  (ff 0e 16 8c|8c 16 0e ff)       fmrgow  f24,f14,f2
  238:  (fe c7 2f 8c|8c 2f c7 fe)       fmrgew  f22,f7,f5
+ 23c:  (7c 00 71 9c|9c 71 00 7c)       msgsnd  r14
+ 240:  (7c 00 b9 dc|dc b9 00 7c)       msgclr  r23
 #pass

diff --git a/gas/testsuite/gas/ppc/power8.s b/gas/testsuite/gas/ppc/power8.s
index 8df4f6b..09dbe43 100644 (file)
--- a/gas/testsuite/gas/ppc/power8.s
+++ b/gas/testsuite/gas/ppc/power8.s
@@ -142,3 +142,5 @@ power8:
        xscvspdpn    59,26
        fmrgow       24,14,2
        fmrgew       22,7,5
+       msgsnd       14
+       msgclr       23

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a8fa342..cdb3a99 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2014-10-28  Alan Modra  <amodra@gmail.com>
+
+       Apply trunk patches
+       2014-10-21  Jan Beulich  <jbeulich@suse.com>
+       * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
+
 2014-10-15  Tristan Gingold  <gingold@adacore.com>
 
        * configure: Regenerate.

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index a5cfe1a..bcc0ca0 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4653,7 +4653,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"addze.",     XO(31,202,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
 {"aze.",       XO(31,202,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
 
-{"msgsnd",     XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}},
+{"msgsnd",     XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}},
 
 {"mtsr",       X(31,210), XRB_MASK|(1<<20), COM,       NON32,          {SR, RS}},
 
@@ -4700,7 +4700,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"muls.",      XO(31,235,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
 
 {"icblce",     X(31,238),      X_MASK,      PPCCHLK,   E500MC|PPCA2,   {CT, RA, RB}},
-{"msgclr",     XRTRA(31,238,0,0),XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}},
+{"msgclr",     XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}},
 {"mtsrin",     X(31,242),      XRA_MASK,    PPC,       NON32,          {RS, RB}},
 {"mtsri",      X(31,242),      XRA_MASK,    POWER,     NON32,          {RS, RB}},