1 2014-12-16 Matthew Fortune <matthew.fortune@imgtec.com>
3 * mips-opc.c (mips_builtin_opcodes): Add JALRC alias for
4 JIALC. Remove the operand from NAL.
6 2014-11-30 Alan Modra <amodra@gmail.com>
8 * ppc-opc.c (powerpc_opcodes): Make mftb* generate mfspr for
11 2014-11-28 Alan Modra <amodra@gmail.com>
13 * ppc-opc.c (powerpc_opcodes <mftb>): Don't deprecate for power7.
15 (insert_tbr, extract_tbr): Validate tbr number.
17 2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
19 * i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb,
21 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2.
22 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS.
23 (cpu_flags): Add CpuAVX512VBMI.
24 * i386-opc.h (enum): Add CpuAVX512VBMI.
25 (i386_cpu_flags): Add cpuavx512vbmi.
26 * i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b,
28 * i386-init.h: Regenerated.
29 * i386-tbl.h: Likewise.
31 2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
33 * i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
34 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4,
36 * i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS.
37 (cpu_flags): Add CpuAVX512IFMA.
38 * i386-opc.h (enum): Add CpuAVX512IFMA.
39 (i386_cpu_flags): Add cpuavx512ifma.
40 * i386-opc.tbl: Add vpmadd52huq, vpmadd52luq.
41 * i386-init.h: Regenerated.
42 * i386-tbl.h: Likewise.
44 2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
46 * i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7.
47 (prefix_table): Add pcommit.
48 * i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS.
49 (cpu_flags): Add CpuPCOMMIT.
50 * i386-opc.h (enum): Add CpuPCOMMIT.
51 (i386_cpu_flags): Add cpupcommit.
52 * i386-opc.tbl: Add pcommit.
53 * i386-init.h: Regenerated.
54 * i386-tbl.h: Likewise.
56 2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
58 * i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
59 (prefix_table): Add clwb.
60 * i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
61 (cpu_flags): Add CpuCLWB.
62 * i386-opc.h (enum): Add CpuCLWB.
63 (i386_cpu_flags): Add cpuclwb.
64 * i386-opc.tbl: Add clwb.
65 * i386-init.h: Regenerated.
66 * i386-tbl.h: Likewise.
68 2014-11-03 Nick Clifton <nickc@redhat.com>
70 * po/fi.po: Updated Finnish translation.
72 2014-10-29 Nick Clifton <nickc@redhat.com>
74 * po/de.po: Updated German translation.
76 2014-10-28 Alan Modra <amodra@gmail.com>
79 2014-10-21 Jan Beulich <jbeulich@suse.com>
80 * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
82 2014-10-15 Tristan Gingold <gingold@adacore.com>
84 * configure: Regenerate.
86 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
88 * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
89 `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
90 Annotate table with HWCAP2 bits.
91 Add instructions xmontmul, xmontsqr, xmpmul.
92 (sparc-opcodes): Add the `mwait', `wr r,r,%mwait', `wr
93 r,i,%mwait' and `rd %mwait,r' instructions.
94 Add rd/wr instructions for accessing the %mcdper ancillary state
96 (sparc-opcodes): Add sparc5/vis4.0 instructions:
97 subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
98 fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
99 fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
100 fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
101 fpsubus16, and faligndatai.
102 * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
103 ancillary state register to the table.
104 (print_insn_sparc): Handle the %mcdper ancillary state register.
105 (print_insn_sparc): Handle new operand type '}'.
107 2014-09-22 H.J. Lu <hongjiu.lu@intel.com>
109 * i386-dis.c (MOD_0F20): Removed.
110 (MOD_0F21): Likewise.
111 (MOD_0F22): Likewise.
112 (MOD_0F23): Likewise.
113 (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
114 MOD_0F23 with "movZ".
115 (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
116 (OP_R): Check mod/rm byte and call OP_E_register.
118 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
120 * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
121 keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
122 keyword_aridxi): Add audio ISA extension.
123 (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
124 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
125 keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
126 for nds32-dis.c using.
127 (build_opcode_syntax): Remove dead code.
128 (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
129 parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
130 parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
132 * nds32-asm.h: Declare.
133 * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
136 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
137 Matthew Fortune <matthew.fortune@imgtec.com>
139 * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
141 (parse_mips_dis_option): Allow MSA and virtualization support for
143 (mips_print_arg_state): Add fields dest_regno and seen_dest.
144 (mips_seen_register): New function.
145 (print_insn_arg): Refactored code to use mips_seen_register
146 function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
147 OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
148 the register rather than aborting.
149 (print_insn_args): Add length argument. Add code to correctly
150 calculate the instruction address for pc relative instructions.
151 (validate_insn_args): New static function.
152 (print_insn_mips): Prevent jalx disassembling for r6. Use
154 (print_insn_micromips): Use validate_insn_args.
155 all the arguments are valid.
156 * mips-formats.h (PREV_CHECK): New define.
157 * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
158 -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
163 (mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
164 MIPS R6 instructions from MIPS R2 instructions.
166 2014-09-10 H.J. Lu <hongjiu.lu@intel.com>
168 * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
169 (putop): Handle "%LP".
171 2014-09-03 Jiong Wang <jiong.wang@arm.com>
173 * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
174 * aarch64-dis-2.c: Update auto-generated file.
176 2014-09-03 Jiong Wang <jiong.wang@arm.com>
178 * aarch64-tbl.h (QL_R4NIL): New qualifiers.
179 (aarch64_feature_lse): New feature added.
181 (aarch64_opcode_table): New LSE instructions added. Improve
182 descriptions for ldarb/ldarh/ldar.
183 (aarch64_opcode_table): Describe PAIRREG.
184 * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
185 * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
186 (aarch64_print_operand): Recognize PAIRREG.
187 (operand_general_constraint_met_p): Check reg pair constraints for CASP
189 * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
190 (do_special_decoding): Recognize F_LSE_SZ.
191 * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
193 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
195 * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
196 (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
197 "sdbbp", "syscall" and "wait".
199 2014-08-21 Nathan Sidwell <nathan@codesourcery.com>
200 Maciej W. Rozycki <macro@codesourcery.com>
202 * arm-dis.c (print_arm_address): Negate the GPR-relative offset
203 returned if the U bit is set.
205 2014-08-21 Maciej W. Rozycki <macro@codesourcery.com>
207 * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
208 48-bit "li" encoding.
210 2014-08-19 Andreas Arnez <arnez@linux.vnet.ibm.com>
212 * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
213 (s390_print_insn_with_opcode, opcode_mask_more_specific): New
214 static functions, code was moved from...
215 (print_insn_s390): ...here.
216 (s390_extract_operand): Adjust comment. Change type of first
217 parameter from 'unsigned char *' to 'const bfd_byte *'.
218 (union operand_value): New.
219 (s390_extract_operand): Change return type to union operand_value.
220 Also avoid integer overflow in sign-extension.
221 (s390_print_insn_with_opcode): Adjust to changed return value from
222 s390_extract_operand(). Change "%i" printf format to "%u" for
224 (init_disasm): Simplify initialization of opc_index[]. This also
225 fixes an access after the last element of s390_opcodes[].
226 (print_insn_s390): Simplify the opcode search loop.
227 Check architecture mask against all searched opcodes, not just the
229 (s390_print_insn_with_opcode): Drop function pointer dereferences
231 (print_insn_s390): Likewise.
232 (s390_insn_length): Simplify formula for return value.
233 (s390_print_insn_with_opcode): Avoid special handling for the
234 separator before the first operand. Use new local variable
235 'flags' in place of 'operand->flags'.
237 2014-08-14 Mike Frysinger <vapier@gentoo.org>
239 * bfin-dis.c (struct private): Change int's to bfd_boolean's.
240 (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
241 decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
242 Change assignment of 1 to priv->comment to TRUE.
243 (print_insn_bfin): Change legal to a bfd_boolean. Change
244 assignment of 0/1 with priv comment and parallel and legal
247 2014-08-14 Mike Frysinger <vapier@gentoo.org>
249 * bfin-dis.c (OUT): Define.
250 (decode_CC2stat_0): Declare new op_names array.
251 Replace multiple if statements with a single one.
253 2014-08-14 Mike Frysinger <vapier@gentoo.org>
255 * bfin-dis.c (struct private): Add iw0.
256 (_print_insn_bfin): Assign iw0 to priv.iw0.
257 (print_insn_bfin): Drop ifetch and use priv.iw0.
259 2014-08-13 Mike Frysinger <vapier@gentoo.org>
261 * bfin-dis.c (comment, parallel): Move from global scope ...
262 (struct private): ... to this new struct.
263 (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
264 decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
265 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
266 decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
267 decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
268 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
269 decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
270 print_insn_bfin): Declare private struct. Use priv's comment and
273 2014-08-13 Mike Frysinger <vapier@gentoo.org>
275 * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
276 (_print_insn_bfin): Add check for unaligned pc.
278 2014-08-13 Mike Frysinger <vapier@gentoo.org>
280 * bfin-dis.c (ifetch): New function.
281 (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
284 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
286 * micromips-opc.c (COD): Rename throughout to...
287 (CM): New define, update to use INSN_COPROC_MOVE.
288 (LCD): Rename throughout to...
289 (LC): New define, update to use INSN_LOAD_COPROC.
290 * mips-opc.c: Likewise.
292 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
294 * micromips-opc.c (COD, LCD) New macros.
295 (cfc1, ctc1): Remove FP_S attribute.
296 (dmfc1, mfc1, mfhc1): Add LCD attribute.
297 (dmtc1, mtc1, mthc1): Add COD attribute.
298 * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
300 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
301 Alexander Ivchenko <alexander.ivchenko@intel.com>
302 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
303 Sergey Lega <sergey.s.lega@intel.com>
304 Anna Tikhonova <anna.tikhonova@intel.com>
305 Ilya Tocar <ilya.tocar@intel.com>
306 Andrey Turetskiy <andrey.turetskiy@intel.com>
307 Ilya Verbin <ilya.verbin@intel.com>
308 Kirill Yukhin <kirill.yukhin@intel.com>
309 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
311 * i386-dis-evex.h: Updated.
312 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
313 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
314 PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
315 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
317 (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
318 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
319 (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
320 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
321 EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
322 EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
323 EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
324 EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
325 EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
326 (prefix_table): Add entries for new instructions.
327 (vex_len_table): Ditto.
328 (vex_w_table): Ditto.
329 (OP_E_memory): Update xmmq_mode handling.
330 * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
331 (cpu_flags): Add CpuAVX512DQ.
332 * i386-init.h: Regenerared.
333 * i386-opc.h (CpuAVX512DQ): New.
334 (i386_cpu_flags): Add cpuavx512dq.
335 * i386-opc.tbl: Add AVX512DQ instructions.
336 * i386-tbl.h: Regenerate.
338 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
339 Alexander Ivchenko <alexander.ivchenko@intel.com>
340 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
341 Sergey Lega <sergey.s.lega@intel.com>
342 Anna Tikhonova <anna.tikhonova@intel.com>
343 Ilya Tocar <ilya.tocar@intel.com>
344 Andrey Turetskiy <andrey.turetskiy@intel.com>
345 Ilya Verbin <ilya.verbin@intel.com>
346 Kirill Yukhin <kirill.yukhin@intel.com>
347 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
349 * i386-dis-evex.h: Add new instructions (prefixes bellow).
350 * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
351 (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
352 (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
353 PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
354 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
355 PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
356 PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
357 PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
358 PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
359 PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
360 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
361 PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
362 PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
363 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
364 PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
365 PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
366 PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
367 PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
368 PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
369 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
370 PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
371 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
372 (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
373 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
374 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
375 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
376 VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
377 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
378 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
379 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
380 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
381 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
382 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
383 (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
384 EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
385 EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
386 EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
387 EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
388 EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
389 EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
390 (prefix_table): Add entries for new instructions.
392 (vex_len_table): Ditto.
393 (vex_w_table): Ditto.
394 (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
395 mask_bd_mode handling.
396 (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
398 (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
400 (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
401 (OP_EX): Add dqw_swap_mode handling.
402 (OP_VEX): Add mask_bd_mode handling.
403 (OP_Mask): Add mask_bd_mode handling.
404 * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
405 (cpu_flags): Add CpuAVX512BW.
406 * i386-init.h: Regenerated.
407 * i386-opc.h (CpuAVX512BW): New.
408 (i386_cpu_flags): Add cpuavx512bw.
409 * i386-opc.tbl: Add AVX512BW instructions.
410 * i386-tbl.h: Regenerate.
412 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
413 Alexander Ivchenko <alexander.ivchenko@intel.com>
414 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
415 Sergey Lega <sergey.s.lega@intel.com>
416 Anna Tikhonova <anna.tikhonova@intel.com>
417 Ilya Tocar <ilya.tocar@intel.com>
418 Andrey Turetskiy <andrey.turetskiy@intel.com>
419 Ilya Verbin <ilya.verbin@intel.com>
420 Kirill Yukhin <kirill.yukhin@intel.com>
421 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
423 * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
424 * i386-tbl.h: Regenerate.
426 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
427 Alexander Ivchenko <alexander.ivchenko@intel.com>
428 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
429 Sergey Lega <sergey.s.lega@intel.com>
430 Anna Tikhonova <anna.tikhonova@intel.com>
431 Ilya Tocar <ilya.tocar@intel.com>
432 Andrey Turetskiy <andrey.turetskiy@intel.com>
433 Ilya Verbin <ilya.verbin@intel.com>
434 Kirill Yukhin <kirill.yukhin@intel.com>
435 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
437 * i386-dis.c (intel_operand_size): Support 128/256 length in
438 vex_vsib_q_w_dq_mode.
439 (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
440 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
441 (cpu_flags): Add CpuAVX512VL.
442 * i386-init.h: Regenerated.
443 * i386-opc.h (CpuAVX512VL): New.
444 (i386_cpu_flags): Add cpuavx512vl.
445 (BROADCAST_1TO4, BROADCAST_1TO2): Define.
446 * i386-opc.tbl: Add AVX512VL instructions.
447 * i386-tbl.h: Regenerate.
449 2014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
451 * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
452 * or1k-opinst.c: Regenerate.
454 2014-07-08 Ilya Tocar <ilya.tocar@intel.com>
456 * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
457 (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
459 2014-07-04 Alan Modra <amodra@gmail.com>
461 * configure.ac: Rename from configure.in.
462 * Makefile.in: Regenerate.
463 * config.in: Regenerate.
465 2014-07-04 Alan Modra <amodra@gmail.com>
467 * configure.in: Include bfd/version.m4.
468 (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
469 (BFD_VERSION): Delete.
470 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
471 * configure: Regenerate.
472 * Makefile.in: Regenerate.
474 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
475 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
476 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
477 Soundararajan <Sounderarajan.D@atmel.com>
479 * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
480 (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
481 machine is not avrtiny.
483 2014-06-26 Philippe De Muyter <phdm@macqel.be>
485 * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
488 2014-06-12 Alan Modra <amodra@gmail.com>
490 * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
491 * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
493 2014-06-10 H.J. Lu <hongjiu.lu@intel.com>
495 * i386-dis.c (fwait_prefix): New.
496 (ckprefix): Set fwait_prefix.
497 (print_insn): Properly print prefixes before fwait.
499 2014-06-07 Alan Modra <amodra@gmail.com>
501 * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
503 2014-06-05 Joel Brobecker <brobecker@adacore.com>
505 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
506 bfd's development.sh.
507 * Makefile.in, configure: Regenerate.
509 2014-06-03 Nick Clifton <nickc@redhat.com>
511 * msp430-dis.c (msp430_doubleoperand): Use extension_word to
512 decide when extended addressing is being used.
514 2014-06-02 Eric Botcazou <ebotcazou@adacore.com>
516 * sparc-opc.c (cas): Disable for LEON.
519 2014-05-20 Alan Modra <amodra@gmail.com>
521 * m68k-dis.c: Don't include setjmp.h.
523 2014-05-09 H.J. Lu <hongjiu.lu@intel.com>
525 * i386-dis.c (ADDR16_PREFIX): Removed.
526 (ADDR32_PREFIX): Likewise.
527 (DATA16_PREFIX): Likewise.
528 (DATA32_PREFIX): Likewise.
529 (prefix_name): Updated.
530 (print_insn): Simplify data and address size prefixes processing.
532 2014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
534 * or1k-desc.c: Regenerated.
535 * or1k-desc.h: Likewise.
536 * or1k-opc.c: Likewise.
537 * or1k-opc.h: Likewise.
538 * or1k-opinst.c: Likewise.
540 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
542 * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
547 * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
549 (parse_mips_dis_option): Update MSA and virtualization support to
550 allow mips64r3 and mips64r5.
552 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
554 * mips-opc.c (G3): Remove I4.
556 2014-05-05 H.J. Lu <hongjiu.lu@intel.com>
559 * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
560 (end_codep): Likewise.
561 (mandatory_prefix): Likewise.
562 (active_seg_prefix): Likewise.
563 (ckprefix): Set active_seg_prefix to the active segment register
565 (seg_prefix): Removed.
566 (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
567 for prefix index. Ignore the index if it is invalid and the
568 mandatory prefix isn't required.
569 (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
570 mandatory. Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
571 in used_prefixes here. Don't print unused prefixes. Check
572 active_seg_prefix for the active segment register prefix.
573 Restore the DFLAG bit in sizeflag if the data size prefix is
574 unused. Check the unused mandatory PREFIX_XXX prefixes
575 (append_seg): Only print the segment register which gets used.
576 (OP_E_memory): Check active_seg_prefix for the segment register
579 (OP_OFF64): Likewise.
580 (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
582 2014-05-02 H.J. Lu <hongjiu.lu@intel.com>
585 * config.in: Regenerated.
586 * configure: Likewise.
587 * configure.in: Check if sigsetjmp is available.
588 * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
589 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
590 (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
591 * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
592 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
593 (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
594 * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
595 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
596 (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
597 * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
598 (OPCODES_SIGSETJMP): Likewise.
599 (OPCODES_SIGLONGJMP): Likewise.
600 * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
601 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
602 (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
603 * xtensa-dis.c (dis_private): Replace jmp_buf with
605 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
606 (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
607 * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
608 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
609 (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
611 2014-05-01 H.J. Lu <hongjiu.lu@intel.com>
614 * i386-dis.c (print_insn): Handle prefixes before fwait.
616 2014-04-26 Alan Modra <amodra@gmail.com>
618 * po/POTFILES.in: Regenerate.
620 2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
622 * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
623 to allow the MIPS XPA ASE.
624 (parse_mips_dis_option): Process the -Mxpa option.
625 * mips-opc.c (XPA): New define.
626 (mips_builtin_opcodes): Add MIPS XPA instructions and move the
627 locations of the ctc0 and cfc0 instructions.
629 2014-04-22 Christian Svensson <blue@cmd.nu>
631 * Makefile.am: Remove openrisc and or32 support. Add support for or1k.
632 * configure.in: Likewise.
633 * disassemble.c: Likewise.
634 * or1k-asm.c: New file.
635 * or1k-desc.c: New file.
636 * or1k-desc.h: New file.
637 * or1k-dis.c: New file.
638 * or1k-ibld.c: New file.
639 * or1k-opc.c: New file.
640 * or1k-opc.h: New file.
641 * or1k-opinst.c: New file.
642 * Makefile.in: Regenerate.
643 * configure: Regenerate.
644 * openrisc-asm.c: Delete.
645 * openrisc-desc.c: Delete.
646 * openrisc-desc.h: Delete.
647 * openrisc-dis.c: Delete.
648 * openrisc-ibld.c: Delete.
649 * openrisc-opc.c: Delete.
650 * openrisc-opc.h: Delete.
651 * or32-dis.c: Delete.
652 * or32-opc.c: Delete.
654 2014-04-04 Ilya Tocar <ilya.tocar@intel.com>
656 * i386-dis.c (rm_table): Add encls, enclu.
657 * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
658 (cpu_flags): Add CpuSE1.
659 * i386-opc.h (enum): Add CpuSE1.
660 (i386_cpu_flags): Add cpuse1.
661 * i386-opc.tbl: Add encls, enclu.
662 * i386-init.h: Regenerated.
663 * i386-tbl.h: Likewise.
665 2014-04-02 Anthony Green <green@moxielogic.com>
667 * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
668 instructions, sex.b and sex.s.
670 2014-03-26 Jiong Wang <jiong.wang@arm.com>
672 * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
675 2014-03-20 Ilya Tocar <ilya.tocar@intel.com>
677 * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
678 vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
680 * i386-tbl.h: Regenerate.
682 2014-03-19 Jose E. Marchesi <jose.marchesi@oracle.com>
684 * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
685 %hstick_enable added.
687 2014-03-19 Nick Clifton <nickc@redhat.com>
689 * rx-decode.opc (bwl): Allow for bogus instructions with a size
691 (sbwl, ubwl, SCALE): Likewise.
692 * rx-decode.c: Regenerate.
694 2014-03-12 Alan Modra <amodra@gmail.com>
696 * Makefile.in: Regenerate.
698 2014-03-05 Alan Modra <amodra@gmail.com>
700 Update copyright years.
702 2014-03-04 Heiher <r@hev.cc>
704 * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
706 2014-03-04 Richard Sandiford <rdsandiford@googlemail.com>
708 * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
709 so that they come after the Loongson extensions.
711 2014-03-03 Alan Modra <amodra@gmail.com>
713 * i386-gen.c (process_copyright): Emit copyright notice on one line.
715 2014-02-28 Alan Modra <amodra@gmail.com>
717 * msp430-decode.c: Regenerate.
719 2014-02-27 Jiong Wang <jiong.wang@arm.com>
721 * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
722 FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
724 2014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
726 * aarch64-opc.c (print_register_offset_address): Call
727 get_int_reg_name to prepare the register name.
729 2014-02-25 Ilya Tocar <ilya.tocar@intel.com>
731 * i386-opc.tbl: Remove wrong variant of vcvtps2ph
732 * i386-tbl.h: Regenerate.
734 2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
736 * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
737 (cpu_flags): Add CpuPREFETCHWT1.
738 * i386-init.h: Regenerate.
739 * i386-opc.h (CpuPREFETCHWT1): New.
740 (i386_cpu_flags): Add cpuprefetchwt1.
741 * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
742 * i386-tbl.h: Regenerate.
744 2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
746 * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
748 * i386-tbl.h: Regenerate.
750 2014-02-19 H.J. Lu <hongjiu.lu@intel.com>
752 * i386-gen.c (output_cpu_flags): Don't output trailing space.
753 (output_opcode_modifier): Likewise.
754 (output_operand_type): Likewise.
755 * i386-init.h: Regenerated.
756 * i386-tbl.h: Likewise.
758 2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
760 * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
762 (PREFIX enum): Add PREFIX_0FAE_REG_7.
763 (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
764 (prefix_table): Add clflusopt.
765 (mod_table): Add xrstors, xsavec, xsaves.
766 * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
767 CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
768 (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
769 * i386-init.h: Regenerate.
770 * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
771 xsaves64, xsavec, xsavec64.
772 * i386-tbl.h: Regenerate.
774 2014-02-10 Alan Modra <amodra@gmail.com>
776 * po/POTFILES.in: Regenerate.
777 * po/opcodes.pot: Regenerate.
779 2014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
780 Jan Beulich <jbeulich@suse.com>
783 * i386-dis.c (OP_E_memory): Fix shift computation for
784 vex_vsib_q_w_dq_mode.
786 2014-01-09 Bradley Nelson <bradnelson@google.com>
787 Roland McGrath <mcgrathr@google.com>
789 * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
790 last_rex_prefix is -1.
792 2014-01-08 H.J. Lu <hongjiu.lu@intel.com>
794 * i386-gen.c (process_copyright): Update copyright year to 2014.
796 2014-01-03 Maciej W. Rozycki <macro@codesourcery.com>
798 * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
800 For older changes see ChangeLog-2013
802 Copyright (C) 2014 Free Software Foundation, Inc.
804 Copying and distribution of this file, with or without modification,
805 are permitted in any medium without royalty provided the copyright
806 notice and this notice are preserved.
812 version-control: never