1 This is as.info, produced by makeinfo version 4.8 from as.texinfo.
3 INFO-DIR-SECTION Software development
5 * As: (as). The GNU assembler.
6 * Gas: (as). The GNU assembler.
9 This file documents the GNU Assembler "as".
11 Copyright (C) 1991-2014 Free Software Foundation, Inc.
13 Permission is granted to copy, distribute and/or modify this document
14 under the terms of the GNU Free Documentation License, Version 1.3 or
15 any later version published by the Free Software Foundation; with no
16 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
17 Texts. A copy of the license is included in the section entitled "GNU
18 Free Documentation License".
21 File: as.info, Node: Top, Next: Overview, Up: (dir)
26 This file is a user guide to the GNU assembler `as' (GNU Binutils)
29 This document is distributed under the terms of the GNU Free
30 Documentation License. A copy of the license is included in the
31 section entitled "GNU Free Documentation License".
36 * Invoking:: Command-Line Options
38 * Sections:: Sections and Relocation
40 * Expressions:: Expressions
41 * Pseudo Ops:: Assembler Directives
43 * Object Attributes:: Object Attributes
44 * Machine Dependencies:: Machine Dependent Features
45 * Reporting Bugs:: Reporting Bugs
46 * Acknowledgements:: Who Did What
47 * GNU Free Documentation License:: GNU Free Documentation License
51 File: as.info, Node: Overview, Next: Invoking, Prev: Top, Up: Top
56 Here is a brief summary of how to invoke `as'. For details, see *Note
57 Command-Line Options: Invoking.
59 as [-a[cdghlns][=FILE]] [-alternate] [-D]
60 [-compress-debug-sections] [-nocompress-debug-sections]
61 [-debug-prefix-map OLD=NEW]
62 [-defsym SYM=VAL] [-f] [-g] [-gstabs]
63 [-gstabs+] [-gdwarf-2] [-gdwarf-sections]
65 [-K] [-L] [-listing-lhs-width=NUM]
66 [-listing-lhs-width2=NUM] [-listing-rhs-width=NUM]
67 [-listing-cont-lines=NUM] [-keep-locals] [-o
68 OBJFILE] [-R] [-reduce-memory-overheads] [-statistics]
69 [-v] [-version] [-version] [-W] [-warn]
70 [-fatal-warnings] [-w] [-x] [-Z] [@FILE]
71 [-size-check=[error|warning]]
72 [-target-help] [TARGET-OPTIONS]
75 _Target AArch64 options:_
79 _Target Alpha options:_
81 [-mdebug | -no-mdebug]
82 [-replace | -noreplace]
83 [-relax] [-g] [-GSIZE]
91 [-mcpu=PROCESSOR[+EXTENSION...]]
92 [-march=ARCHITECTURE[+EXTENSION...]]
93 [-mfpu=FLOATING-POINT-FORMAT]
98 [-mapcs-32|-mapcs-26|-mapcs-float|
100 [-mthumb-interwork] [-k]
102 _Target Blackfin options:_
103 [-mcpu=PROCESSOR[-SIREVISION]]
108 _Target CRIS options:_
109 [-underscore | -no-underscore]
111 [-emulation=criself | -emulation=crisaout]
112 [-march=v0_v10 | -march=v10 | -march=v32 | -march=common_v10_v32]
114 _Target D10V options:_
117 _Target D30V options:_
120 _Target EPIPHANY options:_
121 [-mepiphany|-mepiphany16]
123 _Target H8/300 options:_
126 _Target i386 options:_
128 [-march=CPU[+EXTENSION...]] [-mtune=CPU]
130 _Target i960 options:_
131 [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB|
135 _Target IA-64 options:_
136 [-mconstant-gp|-mauto-pic]
137 [-milp32|-milp64|-mlp64|-mp64]
139 [-mtune=itanium1|-mtune=itanium2]
140 [-munwind-check=warning|-munwind-check=error]
141 [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
142 [-x|-xexplicit] [-xauto] [-xdebug]
144 _Target IP2K options:_
145 [-mip2022|-mip2022ext]
147 _Target M32C options:_
148 [-m32c|-m16c] [-relax] [-h-tick-hex]
150 _Target M32R options:_
151 [-m32rx|-[no-]warn-explicit-parallel-conflicts|
154 _Target M680X0 options:_
155 [-l] [-m68000|-m68010|-m68020|...]
157 _Target M68HC11 options:_
158 [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
160 [-mshort-double|-mlong-double]
161 [-force-long-branches] [-short-branches]
162 [-strict-direct-mode] [-print-insn-syntax]
163 [-print-opcodes] [-generate-example]
165 _Target MCORE options:_
166 [-jsri2bsr] [-sifilter] [-relax]
169 _Target Meta options:_
170 [-mcpu=CPU] [-mfpu=CPU] [-mdsp=CPU]
171 _Target MICROBLAZE options:_
173 _Target MIPS options:_
174 [-nocpp] [-EL] [-EB] [-O[OPTIMIZATION LEVEL]]
175 [-g[DEBUG LEVEL]] [-G NUM] [-KPIC] [-call_shared]
176 [-non_shared] [-xgot [-mvxworks-pic]
177 [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
178 [-mfp64] [-mgp64] [-mfpxx]
179 [-modd-spreg] [-mno-odd-spreg]
180 [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
181 [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
182 [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
183 [-mips64r3] [-mips64r5] [-mips64r6]
184 [-construct-floats] [-no-construct-floats]
186 [-trap] [-no-break] [-break] [-no-trap]
187 [-mips16] [-no-mips16]
188 [-mmicromips] [-mno-micromips]
189 [-msmartmips] [-mno-smartmips]
190 [-mips3d] [-no-mips3d]
193 [-mdspr2] [-mno-dspr2]
198 [-minsn32] [-mno-insn32]
199 [-mfix7000] [-mno-fix7000]
200 [-mfix-rm7000] [-mno-fix-rm7000]
201 [-mfix-vr4120] [-mno-fix-vr4120]
202 [-mfix-vr4130] [-mno-fix-vr4130]
203 [-mdebug] [-no-mdebug]
206 _Target MMIX options:_
207 [-fixed-special-register-names] [-globalize-symbols]
208 [-gnu-syntax] [-relax] [-no-predefined-symbols]
209 [-no-expand] [-no-merge-gregs] [-x]
210 [-linker-allocated-gregs]
212 _Target Nios II options:_
213 [-relax-all] [-relax-section] [-no-relax]
216 _Target NDS32 options:_
217 [-EL] [-EB] [-O] [-Os] [-mcpu=CPU]
218 [-misa=ISA] [-mabi=ABI] [-mall-ext]
219 [-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext]
220 [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
221 [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
222 [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
223 [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
226 _Target PDP11 options:_
227 [-mpic|-mno-pic] [-mall] [-mno-extensions]
228 [-mEXTENSION|-mno-EXTENSION]
231 _Target picoJava options:_
234 _Target PowerPC options:_
236 [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
237 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mppc64|
238 -m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|-me6500|-mppc64bridge|
239 -mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|-mpower6|-mpwr6|
240 -mpower7|-mpwr7|-mpower8|-mpwr8|-ma2|-mcell|-mspe|-mtitan|-me300|-mcom]
241 [-many] [-maltivec|-mvsx|-mhtm|-mvle]
242 [-mregnames|-mno-regnames]
243 [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
244 [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
245 [-msolaris|-mno-solaris]
248 _Target RL78 options:_
250 [-m32bit-doubles|-m64bit-doubles]
253 [-mlittle-endian|-mbig-endian]
254 [-m32bit-doubles|-m64bit-doubles]
255 [-muse-conventional-section-names]
259 [-mint-register=NUMBER]
262 _Target s390 options:_
263 [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
264 [-mregnames|-mno-regnames]
267 _Target SCORE options:_
268 [-EB][-EL][-FIXDD][-NWARN]
269 [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
270 [-march=score7][-march=score3]
271 [-USE_R1][-KPIC][-O0][-G NUM][-V]
273 _Target SPARC options:_
274 [-Av6|-Av7|-Av8|-Asparclet|-Asparclite
275 -Av8plus|-Av8plusa|-Av9|-Av9a]
276 [-xarch=v8plus|-xarch=v8plusa] [-bump]
279 _Target TIC54X options:_
280 [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
281 [-merrors-to-file <FILENAME>|-me <FILENAME>]
284 _Target TIC6X options:_
285 [-march=ARCH] [-mbig-endian|-mlittle-endian]
286 [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
289 _Target TILE-Gx options:_
290 [-m32|-m64][-EB][-EL]
293 _Target Xtensa options:_
294 [-[no-]text-section-literals] [-[no-]absolute-literals]
295 [-[no-]target-align] [-[no-]longcalls]
297 [-rename-section OLDNAME=NEWNAME]
301 _Target Z80 options:_
303 [ -ignore-undocumented-instructions] [-Wnud]
304 [ -ignore-unportable-instructions] [-Wnup]
305 [ -warn-undocumented-instructions] [-Wud]
306 [ -warn-unportable-instructions] [-Wup]
307 [ -forbid-undocumented-instructions] [-Fud]
308 [ -forbid-unportable-instructions] [-Fup]
311 Read command-line options from FILE. The options read are
312 inserted in place of the original @FILE option. If FILE does not
313 exist, or cannot be read, then the option will be treated
314 literally, and not removed.
316 Options in FILE are separated by whitespace. A whitespace
317 character may be included in an option by surrounding the entire
318 option in either single or double quotes. Any character
319 (including a backslash) may be included by prefixing the character
320 to be included with a backslash. The FILE may itself contain
321 additional @FILE options; any such options will be processed
325 Turn on listings, in any of a variety of ways:
328 omit false conditionals
331 omit debugging directives
334 include general information, like as version and options
338 include high-level source
344 include macro expansions
347 omit forms processing
353 set the name of the listing file
355 You may combine these options; for example, use `-aln' for assembly
356 listing without forms processing. The `=file' option, if used,
357 must be the last one. By itself, `-a' defaults to `-ahls'.
360 Begin in alternate macro mode. *Note `.altmacro': Altmacro.
362 `--compress-debug-sections'
363 Compress DWARF debug sections using zlib. The debug sections are
364 renamed to begin with `.zdebug', and the resulting object file may
365 not be compatible with older linkers and object file utilities.
367 `--nocompress-debug-sections'
368 Do not compress DWARF debug sections. This is the default.
371 Ignored. This option is accepted for script compatibility with
372 calls to other assemblers.
374 `--debug-prefix-map OLD=NEW'
375 When assembling files in directory `OLD', record debugging
376 information describing them as in `NEW' instead.
379 Define the symbol SYM to be VALUE before assembling the input file.
380 VALUE must be an integer constant. As in C, a leading `0x'
381 indicates a hexadecimal value, and a leading `0' indicates an octal
382 value. The value of the symbol can be overridden inside a source
383 file via the use of a `.set' pseudo-op.
386 "fast"--skip whitespace and comment preprocessing (assume source is
391 Generate debugging information for each assembler source line
392 using whichever debug format is preferred by the target. This
393 currently means either STABS, ECOFF or DWARF2.
396 Generate stabs debugging information for each assembler line. This
397 may help debugging assembler code, if the debugger can handle it.
400 Generate stabs debugging information for each assembler line, with
401 GNU extensions that probably only gdb can handle, and that could
402 make other debuggers crash or refuse to read your program. This
403 may help debugging assembler code. Currently the only GNU
404 extension is the location of the current working directory at
408 Generate DWARF2 debugging information for each assembler line.
409 This may help debugging assembler code, if the debugger can handle
410 it. Note--this option is only supported by some targets, not all
414 Instead of creating a .debug_line section, create a series of
415 .debug_line.FOO sections where FOO is the name of the
416 corresponding code section. For example a code section called
417 .TEXT.FUNC will have its dwarf line number information placed into
418 a section called .DEBUG_LINE.TEXT.FUNC. If the code section is
419 just called .TEXT then debug line section will still be called
420 just .DEBUG_LINE without any suffix.
423 `--size-check=warning'
424 Issue an error or warning for invalid ELF .size directive.
427 Print a summary of the command line options and exit.
430 Print a summary of all target specific options and exit.
433 Add directory DIR to the search list for `.include' directives.
436 Don't warn about signed overflow.
439 Issue warnings when difference tables altered for long
444 Keep (in the symbol table) local symbols. These symbols start with
445 system-specific local label prefixes, typically `.L' for ELF
446 systems or `L' for traditional a.out systems. *Note Symbol
449 `--listing-lhs-width=NUMBER'
450 Set the maximum width, in words, of the output data column for an
451 assembler listing to NUMBER.
453 `--listing-lhs-width2=NUMBER'
454 Set the maximum width, in words, of the output data column for
455 continuation lines in an assembler listing to NUMBER.
457 `--listing-rhs-width=NUMBER'
458 Set the maximum width of an input source line, as displayed in a
459 listing, to NUMBER bytes.
461 `--listing-cont-lines=NUMBER'
462 Set the maximum number of lines printed in a listing for a single
463 line of input to NUMBER + 1.
466 Name the object-file output from `as' OBJFILE.
469 Fold the data section into the text section.
471 Set the default size of GAS's hash tables to a prime number close
472 to NUMBER. Increasing this value can reduce the length of time it
473 takes the assembler to perform its tasks, at the expense of
474 increasing the assembler's memory requirements. Similarly
475 reducing this value can reduce the memory requirements at the
478 `--reduce-memory-overheads'
479 This option reduces GAS's memory requirements, at the expense of
480 making the assembly processes slower. Currently this switch is a
481 synonym for `--hash-size=4051', but in the future it may have
482 other effects as well.
485 Print the maximum space (in bytes) and total time (in seconds)
488 `--strip-local-absolute'
489 Remove local absolute symbols from the outgoing symbol table.
493 Print the `as' version.
496 Print the `as' version and exit.
500 Suppress warning messages.
503 Treat warnings as errors.
506 Don't suppress warning messages or treat them as errors.
515 Generate an object file even after errors.
518 Standard input, or source files to assemble.
521 *Note AArch64 Options::, for the options available when as is
522 configured for the 64-bit mode of the ARM Architecture (AArch64).
524 *Note Alpha Options::, for the options available when as is
525 configured for an Alpha processor.
527 The following options are available when as is configured for an ARC
531 This option selects the core processor variant.
534 Select either big-endian (-EB) or little-endian (-EL) output.
536 The following options are available when as is configured for the ARM
539 `-mcpu=PROCESSOR[+EXTENSION...]'
540 Specify which ARM processor variant is the target.
542 `-march=ARCHITECTURE[+EXTENSION...]'
543 Specify which ARM architecture variant is used by the target.
545 `-mfpu=FLOATING-POINT-FORMAT'
546 Select which Floating Point architecture is the target.
549 Select which floating point ABI is in use.
552 Enable Thumb only instruction decoding.
554 `-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant'
555 Select which procedure calling convention is in use.
558 Select either big-endian (-EB) or little-endian (-EL) output.
561 Specify that the code has been generated with interworking between
562 Thumb and ARM code in mind.
565 Turns on CodeComposer Studio assembly syntax compatibility mode.
568 Specify that PIC code has been generated.
570 *Note Blackfin Options::, for the options available when as is
571 configured for the Blackfin processor family.
573 See the info pages for documentation of the CRIS-specific options.
575 The following options are available when as is configured for a D10V
578 Optimize output by parallelizing instructions.
580 The following options are available when as is configured for a D30V
583 Optimize output by parallelizing instructions.
586 Warn when nops are generated.
589 Warn when a nop after a 32-bit multiply instruction is generated.
591 The following options are available when as is configured for the
592 Adapteva EPIPHANY series.
594 *Note Epiphany Options::, for the options available when as is
595 configured for an Epiphany processor.
597 *Note i386-Options::, for the options available when as is
598 configured for an i386 processor.
600 The following options are available when as is configured for the
601 Intel 80960 processor.
603 `-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC'
604 Specify which variant of the 960 architecture is the target.
607 Add code to collect statistics about branches taken.
610 Do not alter compare-and-branch instructions for long
611 displacements; error if necessary.
614 The following options are available when as is configured for the
618 Specifies that the extended IP2022 instructions are allowed.
621 Restores the default behaviour, which restricts the permitted
622 instructions to just the basic IP2022 ones.
625 The following options are available when as is configured for the
626 Renesas M32C and M16C processors.
629 Assemble M32C instructions.
632 Assemble M16C instructions (the default).
635 Enable support for link-time relaxations.
638 Support H'00 style hex constants in addition to 0x00 style.
641 The following options are available when as is configured for the
642 Renesas M32R (formerly Mitsubishi M32R) series.
645 Specify which processor in the M32R family is the target. The
646 default is normally the M32R, but this option changes it to the
649 `--warn-explicit-parallel-conflicts or --Wp'
650 Produce warning messages when questionable parallel constructs are
653 `--no-warn-explicit-parallel-conflicts or --Wnp'
654 Do not produce warning messages when questionable parallel
655 constructs are encountered.
658 The following options are available when as is configured for the
659 Motorola 68000 series.
662 Shorten references to undefined symbols, to one word instead of
665 `-m68000 | -m68008 | -m68010 | -m68020 | -m68030'
666 `| -m68040 | -m68060 | -m68302 | -m68331 | -m68332'
667 `| -m68333 | -m68340 | -mcpu32 | -m5200'
668 Specify what processor in the 68000 family is the target. The
669 default is normally the 68020, but this can be changed at
672 `-m68881 | -m68882 | -mno-68881 | -mno-68882'
673 The target machine does (or does not) have a floating-point
674 coprocessor. The default is to assume a coprocessor for 68020,
675 68030, and cpu32. Although the basic 68000 is not compatible with
676 the 68881, a combination of the two can be specified, since it's
677 possible to do emulation of the coprocessor instructions with the
680 `-m68851 | -mno-68851'
681 The target machine does (or does not) have a memory-management
682 unit coprocessor. The default is to assume an MMU for 68020 and
686 *Note Nios II Options::, for the options available when as is
687 configured for an Altera Nios II processor.
689 For details about the PDP-11 machine dependent features options, see
690 *Note PDP-11-Options::.
693 Generate position-independent (or position-dependent) code. The
698 Enable all instruction set extensions. This is the default.
701 Disable all instruction set extensions.
703 `-mEXTENSION | -mno-EXTENSION'
704 Enable (or disable) a particular instruction set extension.
707 Enable the instruction set extensions supported by a particular
708 CPU, and disable all other extensions.
711 Enable the instruction set extensions supported by a particular
712 machine model, and disable all other extensions.
714 The following options are available when as is configured for a
718 Generate "big endian" format output.
721 Generate "little endian" format output.
724 The following options are available when as is configured for the
725 Motorola 68HC11 or 68HC12 series.
727 `-m68hc11 | -m68hc12 | -m68hcs12 | -mm9s12x | -mm9s12xg'
728 Specify what processor is the target. The default is defined by
729 the configuration option when building the assembler.
732 Instruct the linker to offset RAM addresses from S12X address
733 space into XGATE address space.
736 Specify to use the 16-bit integer ABI.
739 Specify to use the 32-bit integer ABI.
742 Specify to use the 32-bit double ABI.
745 Specify to use the 64-bit double ABI.
747 `--force-long-branches'
748 Relative branches are turned into absolute ones. This concerns
749 conditional branches, unconditional branches and branches to a sub
752 `-S | --short-branches'
753 Do not turn relative branches into absolute ones when the offset
756 `--strict-direct-mode'
757 Do not turn the direct addressing mode into extended addressing
758 mode when the instruction does not support direct addressing mode.
760 `--print-insn-syntax'
761 Print the syntax of instruction in case of error.
764 Print the list of instructions with syntax and then exit.
767 Print an example of instruction for each possible instruction and
768 then exit. This option is only useful for testing `as'.
771 The following options are available when `as' is configured for the
774 `-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite'
775 `-Av8plus | -Av8plusa | -Av9 | -Av9a'
776 Explicitly select a variant of the SPARC architecture.
778 `-Av8plus' and `-Av8plusa' select a 32 bit environment. `-Av9'
779 and `-Av9a' select a 64 bit environment.
781 `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with
782 UltraSPARC extensions.
784 `-xarch=v8plus | -xarch=v8plusa'
785 For compatibility with the Solaris v9 assembler. These options are
786 equivalent to -Av8plus and -Av8plusa, respectively.
789 Warn when the assembler switches to another architecture.
791 The following options are available when as is configured for the
795 Enable extended addressing mode. All addresses and relocations
796 will assume extended addressing (usually 23 bits).
799 Sets the CPU version being compiled for.
801 `-merrors-to-file FILENAME'
802 Redirect error output to a file, for broken systems which don't
803 support such behaviour in the shell.
805 The following options are available when as is configured for a MIPS
809 This option sets the largest size of an object that can be
810 referenced implicitly with the `gp' register. It is only accepted
811 for targets that use ECOFF format, such as a DECstation running
812 Ultrix. The default value is 8.
815 Generate "big endian" format output.
818 Generate "little endian" format output.
835 Generate code for a particular MIPS Instruction Set Architecture
836 level. `-mips1' is an alias for `-march=r3000', `-mips2' is an
837 alias for `-march=r6000', `-mips3' is an alias for `-march=r4000'
838 and `-mips4' is an alias for `-march=r8000'. `-mips5', `-mips32',
839 `-mips32r2', `-mips32r3', `-mips32r5', `-mips32r6', `-mips64',
840 `-mips64r2', `-mips64r3', `-mips64r5', and `-mips64r6' correspond
841 to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3,
842 MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2,
843 MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA
844 processors, respectively.
847 Generate code for a particular MIPS CPU.
850 Schedule and tune for a particular MIPS CPU.
854 Cause nops to be inserted if the read of the destination register
855 of an mfhi or mflo instruction occurs in the following two
860 Cause nops to be inserted if a dmult or dmultu instruction is
861 followed by a load instruction.
865 Cause stabs-style debugging output to go into an ECOFF-style
866 .mdebug section instead of the standard ELF .stabs sections.
870 Control generation of `.pdr' sections.
874 The register sizes are normally inferred from the ISA and ABI, but
875 these flags force a certain group of registers to be treated as 32
876 bits wide at all times. `-mgp32' controls the size of
877 general-purpose registers and `-mfp32' controls the size of
878 floating-point registers.
882 The register sizes are normally inferred from the ISA and ABI, but
883 these flags force a certain group of registers to be treated as 64
884 bits wide at all times. `-mgp64' controls the size of
885 general-purpose registers and `-mfp64' controls the size of
886 floating-point registers.
889 The register sizes are normally inferred from the ISA and ABI, but
890 using this flag in combination with `-mabi=32' enables an ABI
891 variant which will operate correctly with floating-point registers
892 which are 32 or 64 bits wide.
896 Enable use of floating-point operations on odd-numbered
897 single-precision registers when supported by the ISA. `-mfpxx'
898 implies `-mno-odd-spreg', otherwise the default is `-modd-spreg'.
902 Generate code for the MIPS 16 processor. This is equivalent to
903 putting `.set mips16' at the start of the assembly file.
904 `-no-mips16' turns off this option.
908 Generate code for the microMIPS processor. This is equivalent to
909 putting `.set micromips' at the start of the assembly file.
910 `-mno-micromips' turns off this option. This is equivalent to
911 putting `.set nomicromips' at the start of the assembly file.
915 Enables the SmartMIPS extension to the MIPS32 instruction set.
916 This is equivalent to putting `.set smartmips' at the start of the
917 assembly file. `-mno-smartmips' turns off this option.
921 Generate code for the MIPS-3D Application Specific Extension.
922 This tells the assembler to accept MIPS-3D instructions.
923 `-no-mips3d' turns off this option.
927 Generate code for the MDMX Application Specific Extension. This
928 tells the assembler to accept MDMX instructions. `-no-mdmx' turns
933 Generate code for the DSP Release 1 Application Specific Extension.
934 This tells the assembler to accept DSP Release 1 instructions.
935 `-mno-dsp' turns off this option.
939 Generate code for the DSP Release 2 Application Specific Extension.
940 This option implies -mdsp. This tells the assembler to accept DSP
941 Release 2 instructions. `-mno-dspr2' turns off this option.
945 Generate code for the MIPS SIMD Architecture Extension. This
946 tells the assembler to accept MSA instructions. `-mno-msa' turns
951 Generate code for the MIPS eXtended Physical Address (XPA)
952 Extension. This tells the assembler to accept XPA instructions.
953 `-mno-xpa' turns off this option.
957 Generate code for the MT Application Specific Extension. This
958 tells the assembler to accept MT instructions. `-mno-mt' turns
963 Generate code for the MCU Application Specific Extension. This
964 tells the assembler to accept MCU instructions. `-mno-mcu' turns
969 Only use 32-bit instruction encodings when generating code for the
970 microMIPS processor. This option inhibits the use of any 16-bit
971 instructions. This is equivalent to putting `.set insn32' at the
972 start of the assembly file. `-mno-insn32' turns off this option.
973 This is equivalent to putting `.set noinsn32' at the start of the
974 assembly file. By default `-mno-insn32' is selected, allowing all
975 instructions to be used.
978 `--no-construct-floats'
979 The `--no-construct-floats' option disables the construction of
980 double width floating point constants by loading the two halves of
981 the value into the two single width floating point registers that
982 make up the double width register. By default
983 `--construct-floats' is selected, allowing construction of these
984 floating point constants.
988 The `--relax-branch' option enables the relaxation of out-of-range
989 branches. By default `--no-relax-branch' is selected, causing any
990 out-of-range branches to produce an error.
993 Select between the IEEE 754-2008 (`-mnan=2008') or the legacy
994 (`-mnan=legacy') NaN encoding format. The latter is the default.
997 This option was formerly used to switch between ELF and ECOFF
998 output on targets like IRIX 5 that supported both. MIPS ECOFF
999 support was removed in GAS 2.24, so the option now serves little
1000 purpose. It is retained for backwards compatibility.
1002 The available configuration names are: `mipself', `mipslelf' and
1003 `mipsbelf'. Choosing `mipself' now has no effect, since the output
1004 is always ELF. `mipslelf' and `mipsbelf' select little- and
1005 big-endian output respectively, but `-EL' and `-EB' are now the
1006 preferred options instead.
1009 `as' ignores this option. It is accepted for compatibility with
1016 Control how to deal with multiplication overflow and division by
1017 zero. `--trap' or `--no-break' (which are synonyms) take a trap
1018 exception (and only work for Instruction Set Architecture level 2
1019 and higher); `--break' or `--no-trap' (also synonyms, and the
1020 default) take a break exception.
1023 When this option is used, `as' will issue a warning every time it
1024 generates a nop instruction from a macro.
1026 The following options are available when as is configured for an
1031 Enable or disable the JSRI to BSR transformation. By default this
1032 is enabled. The command line option `-nojsri2bsr' can be used to
1037 Enable or disable the silicon filter behaviour. By default this
1038 is disabled. The default can be overridden by the `-sifilter'
1039 command line option.
1042 Alter jump instructions for long displacements.
1045 Select the cpu type on the target hardware. This controls which
1046 instructions can be assembled.
1049 Assemble for a big endian target.
1052 Assemble for a little endian target.
1055 *Note Meta Options::, for the options available when as is configured
1056 for a Meta processor.
1058 See the info pages for documentation of the MMIX-specific options.
1060 *Note NDS32 Options::, for the options available when as is
1061 configured for a NDS32 processor.
1063 *Note PowerPC-Opts::, for the options available when as is configured
1064 for a PowerPC processor.
1066 See the info pages for documentation of the RX-specific options.
1068 The following options are available when as is configured for the
1069 s390 processor family.
1073 Select the word size, either 31/32 bits or 64 bits.
1078 Select the architecture mode, either the Enterprise System
1079 Architecture (esa) or the z/Architecture mode (zarch).
1082 Specify which s390 processor variant is the target, `g6', `g6',
1083 `z900', `z990', `z9-109', `z9-ec', `z10', `z196', or `zEC12'.
1087 Allow or disallow symbolic names for registers.
1090 Warn whenever the operand for a base or index register has been
1091 specified but evaluates to zero.
1093 *Note TIC6X Options::, for the options available when as is
1094 configured for a TMS320C6000 processor.
1096 *Note TILE-Gx Options::, for the options available when as is
1097 configured for a TILE-Gx processor.
1099 *Note Xtensa Options::, for the options available when as is
1100 configured for an Xtensa processor.
1102 The following options are available when as is configured for a Z80
1105 Assemble for Z80 processor.
1108 Assemble for R800 processor.
1110 `-ignore-undocumented-instructions'
1112 Assemble undocumented Z80 instructions that also work on R800
1115 `-ignore-unportable-instructions'
1117 Assemble all undocumented Z80 instructions without warning.
1119 `-warn-undocumented-instructions'
1121 Issue a warning for undocumented Z80 instructions that also work
1124 `-warn-unportable-instructions'
1126 Issue a warning for undocumented Z80 instructions that do not work
1129 `-forbid-undocumented-instructions'
1131 Treat all undocumented instructions as errors.
1133 `-forbid-unportable-instructions'
1135 Treat undocumented Z80 instructions that do not work on R800 as
1140 * Manual:: Structure of this Manual
1141 * GNU Assembler:: The GNU Assembler
1142 * Object Formats:: Object File Formats
1143 * Command Line:: Command Line
1144 * Input Files:: Input Files
1145 * Object:: Output (Object) File
1146 * Errors:: Error and Warning Messages
1149 File: as.info, Node: Manual, Next: GNU Assembler, Up: Overview
1151 1.1 Structure of this Manual
1152 ============================
1154 This manual is intended to describe what you need to know to use GNU
1155 `as'. We cover the syntax expected in source files, including notation
1156 for symbols, constants, and expressions; the directives that `as'
1157 understands; and of course how to invoke `as'.
1159 This manual also describes some of the machine-dependent features of
1160 various flavors of the assembler.
1162 On the other hand, this manual is _not_ intended as an introduction
1163 to programming in assembly language--let alone programming in general!
1164 In a similar vein, we make no attempt to introduce the machine
1165 architecture; we do _not_ describe the instruction set, standard
1166 mnemonics, registers or addressing modes that are standard to a
1167 particular architecture. You may want to consult the manufacturer's
1168 machine architecture manual for this information.
1171 File: as.info, Node: GNU Assembler, Next: Object Formats, Prev: Manual, Up: Overview
1173 1.2 The GNU Assembler
1174 =====================
1176 GNU `as' is really a family of assemblers. If you use (or have used)
1177 the GNU assembler on one architecture, you should find a fairly similar
1178 environment when you use it on another architecture. Each version has
1179 much in common with the others, including object file formats, most
1180 assembler directives (often called "pseudo-ops") and assembler syntax.
1182 `as' is primarily intended to assemble the output of the GNU C
1183 compiler `gcc' for use by the linker `ld'. Nevertheless, we've tried
1184 to make `as' assemble correctly everything that other assemblers for
1185 the same machine would assemble. Any exceptions are documented
1186 explicitly (*note Machine Dependencies::). This doesn't mean `as'
1187 always uses the same syntax as another assembler for the same
1188 architecture; for example, we know of several incompatible versions of
1189 680x0 assembly language syntax.
1191 Unlike older assemblers, `as' is designed to assemble a source
1192 program in one pass of the source file. This has a subtle impact on the
1193 `.org' directive (*note `.org': Org.).
1196 File: as.info, Node: Object Formats, Next: Command Line, Prev: GNU Assembler, Up: Overview
1198 1.3 Object File Formats
1199 =======================
1201 The GNU assembler can be configured to produce several alternative
1202 object file formats. For the most part, this does not affect how you
1203 write assembly language programs; but directives for debugging symbols
1204 are typically different in different file formats. *Note Symbol
1205 Attributes: Symbol Attributes.
1208 File: as.info, Node: Command Line, Next: Input Files, Prev: Object Formats, Up: Overview
1213 After the program name `as', the command line may contain options and
1214 file names. Options may appear in any order, and may be before, after,
1215 or between file names. The order of file names is significant.
1217 `--' (two hyphens) by itself names the standard input file
1218 explicitly, as one of the files for `as' to assemble.
1220 Except for `--' any command line argument that begins with a hyphen
1221 (`-') is an option. Each option changes the behavior of `as'. No
1222 option changes the way another option works. An option is a `-'
1223 followed by one or more letters; the case of the letter is important.
1224 All options are optional.
1226 Some options expect exactly one file name to follow them. The file
1227 name may either immediately follow the option's letter (compatible with
1228 older assemblers) or it may be the next command argument (GNU
1229 standard). These two command lines are equivalent:
1231 as -o my-object-file.o mumble.s
1232 as -omy-object-file.o mumble.s
1235 File: as.info, Node: Input Files, Next: Object, Prev: Command Line, Up: Overview
1240 We use the phrase "source program", abbreviated "source", to describe
1241 the program input to one run of `as'. The program may be in one or
1242 more files; how the source is partitioned into files doesn't change the
1243 meaning of the source.
1245 The source program is a concatenation of the text in all the files,
1246 in the order specified.
1248 Each time you run `as' it assembles exactly one source program. The
1249 source program is made up of one or more files. (The standard input is
1252 You give `as' a command line that has zero or more input file names.
1253 The input files are read (from left file name to right). A command
1254 line argument (in any position) that has no special meaning is taken to
1255 be an input file name.
1257 If you give `as' no file names it attempts to read one input file
1258 from the `as' standard input, which is normally your terminal. You may
1259 have to type <ctl-D> to tell `as' there is no more program to assemble.
1261 Use `--' if you need to explicitly name the standard input file in
1264 If the source is empty, `as' produces a small, empty object file.
1266 Filenames and Line-numbers
1267 --------------------------
1269 There are two ways of locating a line in the input file (or files) and
1270 either may be used in reporting error messages. One way refers to a
1271 line number in a physical file; the other refers to a line number in a
1272 "logical" file. *Note Error and Warning Messages: Errors.
1274 "Physical files" are those files named in the command line given to
1277 "Logical files" are simply names declared explicitly by assembler
1278 directives; they bear no relation to physical files. Logical file
1279 names help error messages reflect the original source file, when `as'
1280 source is itself synthesized from other files. `as' understands the
1281 `#' directives emitted by the `gcc' preprocessor. See also *Note
1285 File: as.info, Node: Object, Next: Errors, Prev: Input Files, Up: Overview
1287 1.6 Output (Object) File
1288 ========================
1290 Every time you run `as' it produces an output file, which is your
1291 assembly language program translated into numbers. This file is the
1292 object file. Its default name is `a.out'. You can give it another
1293 name by using the `-o' option. Conventionally, object file names end
1294 with `.o'. The default name is used for historical reasons: older
1295 assemblers were capable of assembling self-contained programs directly
1296 into a runnable program. (For some formats, this isn't currently
1297 possible, but it can be done for the `a.out' format.)
1299 The object file is meant for input to the linker `ld'. It contains
1300 assembled program code, information to help `ld' integrate the
1301 assembled program into a runnable file, and (optionally) symbolic
1302 information for the debugger.
1305 File: as.info, Node: Errors, Prev: Object, Up: Overview
1307 1.7 Error and Warning Messages
1308 ==============================
1310 `as' may write warnings and error messages to the standard error file
1311 (usually your terminal). This should not happen when a compiler runs
1312 `as' automatically. Warnings report an assumption made so that `as'
1313 could keep assembling a flawed program; errors report a grave problem
1314 that stops the assembly.
1316 Warning messages have the format
1318 file_name:NNN:Warning Message Text
1320 (where NNN is a line number). If a logical file name has been given
1321 (*note `.file': File.) it is used for the filename, otherwise the name
1322 of the current input file is used. If a logical line number was given
1323 (*note `.line': Line.) then it is used to calculate the number printed,
1324 otherwise the actual line in the current source file is printed. The
1325 message text is intended to be self explanatory (in the grand Unix
1328 Error messages have the format
1329 file_name:NNN:FATAL:Error Message Text
1330 The file name and line number are derived as for warning messages.
1331 The actual message text may be rather less explanatory because many of
1332 them aren't supposed to happen.
1335 File: as.info, Node: Invoking, Next: Syntax, Prev: Overview, Up: Top
1337 2 Command-Line Options
1338 **********************
1340 This chapter describes command-line options available in _all_ versions
1341 of the GNU assembler; see *Note Machine Dependencies::, for options
1342 specific to particular machine architectures.
1344 If you are invoking `as' via the GNU C compiler, you can use the
1345 `-Wa' option to pass arguments through to the assembler. The assembler
1346 arguments must be separated from each other (and the `-Wa') by commas.
1349 gcc -c -g -O -Wa,-alh,-L file.c
1351 This passes two options to the assembler: `-alh' (emit a listing to
1352 standard output with high-level and assembly source) and `-L' (retain
1353 local symbols in the symbol table).
1355 Usually you do not need to use this `-Wa' mechanism, since many
1356 compiler command-line options are automatically passed to the assembler
1357 by the compiler. (You can call the GNU compiler driver with the `-v'
1358 option to see precisely what options it passes to each compilation
1359 pass, including the assembler.)
1363 * a:: -a[cdghlns] enable listings
1364 * alternate:: --alternate enable alternate macro syntax
1365 * D:: -D for compatibility
1366 * f:: -f to work faster
1367 * I:: -I for .include search path
1369 * K:: -K for difference tables
1371 * L:: -L to retain local symbols
1372 * listing:: --listing-XXX to configure listing output
1373 * M:: -M or --mri to assemble in MRI compatibility mode
1374 * MD:: --MD for dependency tracking
1375 * o:: -o to name the object file
1376 * R:: -R to join data and text sections
1377 * statistics:: --statistics to see statistics about assembly
1378 * traditional-format:: --traditional-format for compatible output
1379 * v:: -v to announce version
1380 * W:: -W, --no-warn, --warn, --fatal-warnings to control warnings
1381 * Z:: -Z to make object file even after errors
1384 File: as.info, Node: a, Next: alternate, Up: Invoking
1386 2.1 Enable Listings: `-a[cdghlns]'
1387 ==================================
1389 These options enable listing output from the assembler. By itself,
1390 `-a' requests high-level, assembly, and symbols listing. You can use
1391 other letters to select specific options for the list: `-ah' requests a
1392 high-level language listing, `-al' requests an output-program assembly
1393 listing, and `-as' requests a symbol table listing. High-level
1394 listings require that a compiler debugging option like `-g' be used,
1395 and that assembly listings (`-al') be requested also.
1397 Use the `-ag' option to print a first section with general assembly
1398 information, like as version, switches passed, or time stamp.
1400 Use the `-ac' option to omit false conditionals from a listing. Any
1401 lines which are not assembled because of a false `.if' (or `.ifdef', or
1402 any other conditional), or a true `.if' followed by an `.else', will be
1403 omitted from the listing.
1405 Use the `-ad' option to omit debugging directives from the listing.
1407 Once you have specified one of these options, you can further control
1408 listing output and its appearance using the directives `.list',
1409 `.nolist', `.psize', `.eject', `.title', and `.sbttl'. The `-an'
1410 option turns off all forms processing. If you do not request listing
1411 output with one of the `-a' options, the listing-control directives
1414 The letters after `-a' may be combined into one option, _e.g._,
1417 Note if the assembler source is coming from the standard input (e.g.,
1418 because it is being created by `gcc' and the `-pipe' command line switch
1419 is being used) then the listing will not contain any comments or
1420 preprocessor directives. This is because the listing code buffers
1421 input source lines from stdin only after they have been preprocessed by
1422 the assembler. This reduces memory usage and makes the code more
1426 File: as.info, Node: alternate, Next: D, Prev: a, Up: Invoking
1431 Begin in alternate macro mode, see *Note `.altmacro': Altmacro.
1434 File: as.info, Node: D, Next: f, Prev: alternate, Up: Invoking
1439 This option has no effect whatsoever, but it is accepted to make it more
1440 likely that scripts written for other assemblers also work with `as'.
1443 File: as.info, Node: f, Next: I, Prev: D, Up: Invoking
1445 2.4 Work Faster: `-f'
1446 =====================
1448 `-f' should only be used when assembling programs written by a
1449 (trusted) compiler. `-f' stops the assembler from doing whitespace and
1450 comment preprocessing on the input file(s) before assembling them.
1451 *Note Preprocessing: Preprocessing.
1453 _Warning:_ if you use `-f' when the files actually need to be
1454 preprocessed (if they contain comments, for example), `as' does
1458 File: as.info, Node: I, Next: K, Prev: f, Up: Invoking
1460 2.5 `.include' Search Path: `-I' PATH
1461 =====================================
1463 Use this option to add a PATH to the list of directories `as' searches
1464 for files specified in `.include' directives (*note `.include':
1465 Include.). You may use `-I' as many times as necessary to include a
1466 variety of paths. The current working directory is always searched
1467 first; after that, `as' searches any `-I' directories in the same order
1468 as they were specified (left to right) on the command line.
1471 File: as.info, Node: K, Next: L, Prev: I, Up: Invoking
1473 2.6 Difference Tables: `-K'
1474 ===========================
1476 `as' sometimes alters the code emitted for directives of the form
1477 `.word SYM1-SYM2'. *Note `.word': Word. You can use the `-K' option
1478 if you want a warning issued when this is done.
1481 File: as.info, Node: L, Next: listing, Prev: K, Up: Invoking
1483 2.7 Include Local Symbols: `-L'
1484 ===============================
1486 Symbols beginning with system-specific local label prefixes, typically
1487 `.L' for ELF systems or `L' for traditional a.out systems, are called
1488 "local symbols". *Note Symbol Names::. Normally you do not see such
1489 symbols when debugging, because they are intended for the use of
1490 programs (like compilers) that compose assembler programs, not for your
1491 notice. Normally both `as' and `ld' discard such symbols, so you do
1492 not normally debug with them.
1494 This option tells `as' to retain those local symbols in the object
1495 file. Usually if you do this you also tell the linker `ld' to preserve
1499 File: as.info, Node: listing, Next: M, Prev: L, Up: Invoking
1501 2.8 Configuring listing output: `--listing'
1502 ===========================================
1504 The listing feature of the assembler can be enabled via the command
1505 line switch `-a' (*note a::). This feature combines the input source
1506 file(s) with a hex dump of the corresponding locations in the output
1507 object file, and displays them as a listing file. The format of this
1508 listing can be controlled by directives inside the assembler source
1509 (i.e., `.list' (*note List::), `.title' (*note Title::), `.sbttl'
1510 (*note Sbttl::), `.psize' (*note Psize::), and `.eject' (*note Eject::)
1511 and also by the following switches:
1513 `--listing-lhs-width=`number''
1514 Sets the maximum width, in words, of the first line of the hex
1515 byte dump. This dump appears on the left hand side of the listing
1518 `--listing-lhs-width2=`number''
1519 Sets the maximum width, in words, of any further lines of the hex
1520 byte dump for a given input source line. If this value is not
1521 specified, it defaults to being the same as the value specified
1522 for `--listing-lhs-width'. If neither switch is used the default
1525 `--listing-rhs-width=`number''
1526 Sets the maximum width, in characters, of the source line that is
1527 displayed alongside the hex dump. The default value for this
1528 parameter is 100. The source line is displayed on the right hand
1529 side of the listing output.
1531 `--listing-cont-lines=`number''
1532 Sets the maximum number of continuation lines of hex dump that
1533 will be displayed for a given single line of source input. The
1537 File: as.info, Node: M, Next: MD, Prev: listing, Up: Invoking
1539 2.9 Assemble in MRI Compatibility Mode: `-M'
1540 ============================================
1542 The `-M' or `--mri' option selects MRI compatibility mode. This
1543 changes the syntax and pseudo-op handling of `as' to make it compatible
1544 with the `ASM68K' or the `ASM960' (depending upon the configured
1545 target) assembler from Microtec Research. The exact nature of the MRI
1546 syntax will not be documented here; see the MRI manuals for more
1547 information. Note in particular that the handling of macros and macro
1548 arguments is somewhat different. The purpose of this option is to
1549 permit assembling existing MRI assembler code using `as'.
1551 The MRI compatibility is not complete. Certain operations of the
1552 MRI assembler depend upon its object file format, and can not be
1553 supported using other object file formats. Supporting these would
1554 require enhancing each object file format individually. These are:
1556 * global symbols in common section
1558 The m68k MRI assembler supports common sections which are merged
1559 by the linker. Other object file formats do not support this.
1560 `as' handles common sections by treating them as a single common
1561 symbol. It permits local symbols to be defined within a common
1562 section, but it can not support global symbols, since it has no
1563 way to describe them.
1565 * complex relocations
1567 The MRI assemblers support relocations against a negated section
1568 address, and relocations which combine the start addresses of two
1569 or more sections. These are not support by other object file
1572 * `END' pseudo-op specifying start address
1574 The MRI `END' pseudo-op permits the specification of a start
1575 address. This is not supported by other object file formats. The
1576 start address may instead be specified using the `-e' option to
1577 the linker, or in a linker script.
1579 * `IDNT', `.ident' and `NAME' pseudo-ops
1581 The MRI `IDNT', `.ident' and `NAME' pseudo-ops assign a module
1582 name to the output file. This is not supported by other object
1587 The m68k MRI `ORG' pseudo-op begins an absolute section at a given
1588 address. This differs from the usual `as' `.org' pseudo-op, which
1589 changes the location within the current section. Absolute
1590 sections are not supported by other object file formats. The
1591 address of a section may be assigned within a linker script.
1593 There are some other features of the MRI assembler which are not
1594 supported by `as', typically either because they are difficult or
1595 because they seem of little consequence. Some of these may be
1596 supported in future releases.
1600 EBCDIC strings are not supported.
1602 * packed binary coded decimal
1604 Packed binary coded decimal is not supported. This means that the
1605 `DC.P' and `DCB.P' pseudo-ops are not supported.
1609 The m68k `FEQU' pseudo-op is not supported.
1613 The m68k `NOOBJ' pseudo-op is not supported.
1615 * `OPT' branch control options
1617 The m68k `OPT' branch control options--`B', `BRS', `BRB', `BRL',
1618 and `BRW'--are ignored. `as' automatically relaxes all branches,
1619 whether forward or backward, to an appropriate size, so these
1620 options serve no purpose.
1622 * `OPT' list control options
1624 The following m68k `OPT' list control options are ignored: `C',
1625 `CEX', `CL', `CRE', `E', `G', `I', `M', `MEX', `MC', `MD', `X'.
1627 * other `OPT' options
1629 The following m68k `OPT' options are ignored: `NEST', `O', `OLD',
1630 `OP', `P', `PCO', `PCR', `PCS', `R'.
1632 * `OPT' `D' option is default
1634 The m68k `OPT' `D' option is the default, unlike the MRI assembler.
1635 `OPT NOD' may be used to turn it off.
1639 The m68k `XREF' pseudo-op is ignored.
1641 * `.debug' pseudo-op
1643 The i960 `.debug' pseudo-op is not supported.
1645 * `.extended' pseudo-op
1647 The i960 `.extended' pseudo-op is not supported.
1649 * `.list' pseudo-op.
1651 The various options of the i960 `.list' pseudo-op are not
1654 * `.optimize' pseudo-op
1656 The i960 `.optimize' pseudo-op is not supported.
1658 * `.output' pseudo-op
1660 The i960 `.output' pseudo-op is not supported.
1662 * `.setreal' pseudo-op
1664 The i960 `.setreal' pseudo-op is not supported.
1668 File: as.info, Node: MD, Next: o, Prev: M, Up: Invoking
1670 2.10 Dependency Tracking: `--MD'
1671 ================================
1673 `as' can generate a dependency file for the file it creates. This file
1674 consists of a single rule suitable for `make' describing the
1675 dependencies of the main source file.
1677 The rule is written to the file named in its argument.
1679 This feature is used in the automatic updating of makefiles.
1682 File: as.info, Node: o, Next: R, Prev: MD, Up: Invoking
1684 2.11 Name the Object File: `-o'
1685 ===============================
1687 There is always one object file output when you run `as'. By default
1688 it has the name `a.out' (or `b.out', for Intel 960 targets only). You
1689 use this option (which takes exactly one filename) to give the object
1690 file a different name.
1692 Whatever the object file is called, `as' overwrites any existing
1693 file of the same name.
1696 File: as.info, Node: R, Next: statistics, Prev: o, Up: Invoking
1698 2.12 Join Data and Text Sections: `-R'
1699 ======================================
1701 `-R' tells `as' to write the object file as if all data-section data
1702 lives in the text section. This is only done at the very last moment:
1703 your binary data are the same, but data section parts are relocated
1704 differently. The data section part of your object file is zero bytes
1705 long because all its bytes are appended to the text section. (*Note
1706 Sections and Relocation: Sections.)
1708 When you specify `-R' it would be possible to generate shorter
1709 address displacements (because we do not have to cross between text and
1710 data section). We refrain from doing this simply for compatibility with
1711 older versions of `as'. In future, `-R' may work this way.
1713 When `as' is configured for COFF or ELF output, this option is only
1714 useful if you use sections named `.text' and `.data'.
1716 `-R' is not supported for any of the HPPA targets. Using `-R'
1717 generates a warning from `as'.
1720 File: as.info, Node: statistics, Next: traditional-format, Prev: R, Up: Invoking
1722 2.13 Display Assembly Statistics: `--statistics'
1723 ================================================
1725 Use `--statistics' to display two statistics about the resources used by
1726 `as': the maximum amount of space allocated during the assembly (in
1727 bytes), and the total execution time taken for the assembly (in CPU
1731 File: as.info, Node: traditional-format, Next: v, Prev: statistics, Up: Invoking
1733 2.14 Compatible Output: `--traditional-format'
1734 ==============================================
1736 For some targets, the output of `as' is different in some ways from the
1737 output of some existing assembler. This switch requests `as' to use
1738 the traditional format instead.
1740 For example, it disables the exception frame optimizations which
1741 `as' normally does by default on `gcc' output.
1744 File: as.info, Node: v, Next: W, Prev: traditional-format, Up: Invoking
1746 2.15 Announce Version: `-v'
1747 ===========================
1749 You can find out what version of as is running by including the option
1750 `-v' (which you can also spell as `-version') on the command line.
1753 File: as.info, Node: W, Next: Z, Prev: v, Up: Invoking
1755 2.16 Control Warnings: `-W', `--warn', `--no-warn', `--fatal-warnings'
1756 ======================================================================
1758 `as' should never give a warning or error message when assembling
1759 compiler output. But programs written by people often cause `as' to
1760 give a warning that a particular assumption was made. All such
1761 warnings are directed to the standard error file.
1763 If you use the `-W' and `--no-warn' options, no warnings are issued.
1764 This only affects the warning messages: it does not change any
1765 particular of how `as' assembles your file. Errors, which stop the
1766 assembly, are still reported.
1768 If you use the `--fatal-warnings' option, `as' considers files that
1769 generate warnings to be in error.
1771 You can switch these options off again by specifying `--warn', which
1772 causes warnings to be output as usual.
1775 File: as.info, Node: Z, Prev: W, Up: Invoking
1777 2.17 Generate Object File in Spite of Errors: `-Z'
1778 ==================================================
1780 After an error message, `as' normally produces no output. If for some
1781 reason you are interested in object file output even after `as' gives
1782 an error message on your program, use the `-Z' option. If there are
1783 any errors, `as' continues anyways, and writes an object file after a
1784 final warning message of the form `N errors, M warnings, generating bad
1788 File: as.info, Node: Syntax, Next: Sections, Prev: Invoking, Up: Top
1793 This chapter describes the machine-independent syntax allowed in a
1794 source file. `as' syntax is similar to what many other assemblers use;
1795 it is inspired by the BSD 4.2 assembler, except that `as' does not
1796 assemble Vax bit-fields.
1800 * Preprocessing:: Preprocessing
1801 * Whitespace:: Whitespace
1802 * Comments:: Comments
1803 * Symbol Intro:: Symbols
1804 * Statements:: Statements
1805 * Constants:: Constants
1808 File: as.info, Node: Preprocessing, Next: Whitespace, Up: Syntax
1813 The `as' internal preprocessor:
1814 * adjusts and removes extra whitespace. It leaves one space or tab
1815 before the keywords on a line, and turns any other whitespace on
1816 the line into a single space.
1818 * removes all comments, replacing them with a single space, or an
1819 appropriate number of newlines.
1821 * converts character constants into the appropriate numeric values.
1823 It does not do macro processing, include file handling, or anything
1824 else you may get from your C compiler's preprocessor. You can do
1825 include file processing with the `.include' directive (*note
1826 `.include': Include.). You can use the GNU C compiler driver to get
1827 other "CPP" style preprocessing by giving the input file a `.S' suffix.
1828 *Note Options Controlling the Kind of Output: (gcc.info)Overall
1831 Excess whitespace, comments, and character constants cannot be used
1832 in the portions of the input text that are not preprocessed.
1834 If the first line of an input file is `#NO_APP' or if you use the
1835 `-f' option, whitespace and comments are not removed from the input
1836 file. Within an input file, you can ask for whitespace and comment
1837 removal in specific portions of the by putting a line that says `#APP'
1838 before the text that may contain whitespace or comments, and putting a
1839 line that says `#NO_APP' after this text. This feature is mainly
1840 intend to support `asm' statements in compilers whose output is
1841 otherwise free of comments and whitespace.
1844 File: as.info, Node: Whitespace, Next: Comments, Prev: Preprocessing, Up: Syntax
1849 "Whitespace" is one or more blanks or tabs, in any order. Whitespace
1850 is used to separate symbols, and to make programs neater for people to
1851 read. Unless within character constants (*note Character Constants:
1852 Characters.), any whitespace means the same as exactly one space.
1855 File: as.info, Node: Comments, Next: Symbol Intro, Prev: Whitespace, Up: Syntax
1860 There are two ways of rendering comments to `as'. In both cases the
1861 comment is equivalent to one space.
1863 Anything from `/*' through the next `*/' is a comment. This means
1864 you may not nest these comments.
1867 The only way to include a newline ('\n') in a comment
1868 is to use this sort of comment.
1871 /* This sort of comment does not nest. */
1873 Anything from a "line comment" character up to the next newline is
1874 considered a comment and is ignored. The line comment character is
1875 target specific, and some targets multiple comment characters. Some
1876 targets also have line comment characters that only work if they are
1877 the first character on a line. Some targets use a sequence of two
1878 characters to introduce a line comment. Some targets can also change
1879 their line comment characters depending upon command line options that
1880 have been used. For more details see the _Syntax_ section in the
1881 documentation for individual targets.
1883 If the line comment character is the hash sign (`#') then it still
1884 has the special ability to enable and disable preprocessing (*note
1885 Preprocessing::) and to specify logical line numbers:
1887 To be compatible with past assemblers, lines that begin with `#'
1888 have a special interpretation. Following the `#' should be an absolute
1889 expression (*note Expressions::): the logical line number of the _next_
1890 line. Then a string (*note Strings: Strings.) is allowed: if present
1891 it is a new logical file name. The rest of the line, if any, should be
1894 If the first non-whitespace characters on the line are not numeric,
1895 the line is ignored. (Just like a comment.)
1897 # This is an ordinary comment.
1898 # 42-6 "new_file_name" # New logical file name
1899 # This is logical line # 36.
1900 This feature is deprecated, and may disappear from future versions
1904 File: as.info, Node: Symbol Intro, Next: Statements, Prev: Comments, Up: Syntax
1909 A "symbol" is one or more characters chosen from the set of all letters
1910 (both upper and lower case), digits and the three characters `_.$'. On
1911 most machines, you can also use `$' in symbol names; exceptions are
1912 noted in *Note Machine Dependencies::. No symbol may begin with a
1913 digit. Case is significant. There is no length limit: all characters
1914 are significant. Multibyte characters are supported. Symbols are
1915 delimited by characters not in that set, or by the beginning of a file
1916 (since the source program must end with a newline, the end of a file is
1917 not a possible symbol delimiter). *Note Symbols::.
1920 File: as.info, Node: Statements, Next: Constants, Prev: Symbol Intro, Up: Syntax
1925 A "statement" ends at a newline character (`\n') or a "line separator
1926 character". The line separator character is target specific and
1927 described in the _Syntax_ section of each target's documentation. Not
1928 all targets support a line separator character. The newline or line
1929 separator character is considered to be part of the preceding
1930 statement. Newlines and separators within character constants are an
1931 exception: they do not end statements.
1933 It is an error to end any statement with end-of-file: the last
1934 character of any input file should be a newline.
1936 An empty statement is allowed, and may include whitespace. It is
1939 A statement begins with zero or more labels, optionally followed by a
1940 key symbol which determines what kind of statement it is. The key
1941 symbol determines the syntax of the rest of the statement. If the
1942 symbol begins with a dot `.' then the statement is an assembler
1943 directive: typically valid for any computer. If the symbol begins with
1944 a letter the statement is an assembly language "instruction": it
1945 assembles into a machine language instruction. Different versions of
1946 `as' for different computers recognize different instructions. In
1947 fact, the same symbol may represent a different instruction in a
1948 different computer's assembly language.
1950 A label is a symbol immediately followed by a colon (`:').
1951 Whitespace before a label or after a colon is permitted, but you may not
1952 have whitespace between a label's symbol and its colon. *Note Labels::.
1954 For HPPA targets, labels need not be immediately followed by a
1955 colon, but the definition of a label must begin in column zero. This
1956 also implies that only one label may be defined on each line.
1958 label: .directive followed by something
1959 another_label: # This is an empty statement.
1960 instruction operand_1, operand_2, ...
1963 File: as.info, Node: Constants, Prev: Statements, Up: Syntax
1968 A constant is a number, written so that its value is known by
1969 inspection, without knowing any context. Like this:
1970 .byte 74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value.
1971 .ascii "Ring the bell\7" # A string constant.
1972 .octa 0x123456789abcdef0123456789ABCDEF0 # A bignum.
1973 .float 0f-314159265358979323846264338327\
1974 95028841971.693993751E-40 # - pi, a flonum.
1978 * Characters:: Character Constants
1979 * Numbers:: Number Constants
1982 File: as.info, Node: Characters, Next: Numbers, Up: Constants
1984 3.6.1 Character Constants
1985 -------------------------
1987 There are two kinds of character constants. A "character" stands for
1988 one character in one byte and its value may be used in numeric
1989 expressions. String constants (properly called string _literals_) are
1990 potentially many bytes and their values may not be used in arithmetic
1996 * Chars:: Characters
1999 File: as.info, Node: Strings, Next: Chars, Up: Characters
2004 A "string" is written between double-quotes. It may contain
2005 double-quotes or null characters. The way to get special characters
2006 into a string is to "escape" these characters: precede them with a
2007 backslash `\' character. For example `\\' represents one backslash:
2008 the first `\' is an escape which tells `as' to interpret the second
2009 character literally as a backslash (which prevents `as' from
2010 recognizing the second `\' as an escape character). The complete list
2014 Mnemonic for backspace; for ASCII this is octal code 010.
2017 Mnemonic for FormFeed; for ASCII this is octal code 014.
2020 Mnemonic for newline; for ASCII this is octal code 012.
2023 Mnemonic for carriage-Return; for ASCII this is octal code 015.
2026 Mnemonic for horizontal Tab; for ASCII this is octal code 011.
2028 `\ DIGIT DIGIT DIGIT'
2029 An octal character code. The numeric code is 3 octal digits. For
2030 compatibility with other Unix systems, 8 and 9 are accepted as
2031 digits: for example, `\008' has the value 010, and `\009' the
2034 `\`x' HEX-DIGITS...'
2035 A hex character code. All trailing hex digits are combined.
2036 Either upper or lower case `x' works.
2039 Represents one `\' character.
2042 Represents one `"' character. Needed in strings to represent this
2043 character, because an unescaped `"' would end the string.
2046 Any other character when escaped by `\' gives a warning, but
2047 assembles as if the `\' was not present. The idea is that if you
2048 used an escape sequence you clearly didn't want the literal
2049 interpretation of the following character. However `as' has no
2050 other interpretation, so `as' knows it is giving you the wrong
2051 code and warns you of the fact.
2053 Which characters are escapable, and what those escapes represent,
2054 varies widely among assemblers. The current set is what we think the
2055 BSD 4.2 assembler recognizes, and is a subset of what most C compilers
2056 recognize. If you are in doubt, do not use an escape sequence.
2059 File: as.info, Node: Chars, Prev: Strings, Up: Characters
2064 A single character may be written as a single quote immediately
2065 followed by that character. The same escapes apply to characters as to
2066 strings. So if you want to write the character backslash, you must
2067 write `'\\' where the first `\' escapes the second `\'. As you can
2068 see, the quote is an acute accent, not a grave accent. A newline
2069 immediately following an acute accent is taken as a literal character
2070 and does not count as the end of a statement. The value of a character
2071 constant in a numeric expression is the machine's byte-wide code for
2072 that character. `as' assumes your character code is ASCII: `'A' means
2073 65, `'B' means 66, and so on.
2076 File: as.info, Node: Numbers, Prev: Characters, Up: Constants
2078 3.6.2 Number Constants
2079 ----------------------
2081 `as' distinguishes three kinds of numbers according to how they are
2082 stored in the target machine. _Integers_ are numbers that would fit
2083 into an `int' in the C language. _Bignums_ are integers, but they are
2084 stored in more than 32 bits. _Flonums_ are floating point numbers,
2089 * Integers:: Integers
2094 File: as.info, Node: Integers, Next: Bignums, Up: Numbers
2099 A binary integer is `0b' or `0B' followed by zero or more of the binary
2102 An octal integer is `0' followed by zero or more of the octal digits
2105 A decimal integer starts with a non-zero digit followed by zero or
2106 more digits (`0123456789').
2108 A hexadecimal integer is `0x' or `0X' followed by one or more
2109 hexadecimal digits chosen from `0123456789abcdefABCDEF'.
2111 Integers have the usual values. To denote a negative integer, use
2112 the prefix operator `-' discussed under expressions (*note Prefix
2113 Operators: Prefix Ops.).
2116 File: as.info, Node: Bignums, Next: Flonums, Prev: Integers, Up: Numbers
2121 A "bignum" has the same syntax and semantics as an integer except that
2122 the number (or its negative) takes more than 32 bits to represent in
2123 binary. The distinction is made because in some places integers are
2124 permitted while bignums are not.
2127 File: as.info, Node: Flonums, Prev: Bignums, Up: Numbers
2132 A "flonum" represents a floating point number. The translation is
2133 indirect: a decimal floating point number from the text is converted by
2134 `as' to a generic binary floating point number of more than sufficient
2135 precision. This generic floating point number is converted to a
2136 particular computer's floating point format (or formats) by a portion
2137 of `as' specialized to that computer.
2139 A flonum is written by writing (in order)
2140 * The digit `0'. (`0' is optional on the HPPA.)
2142 * A letter, to tell `as' the rest of the number is a flonum. `e' is
2143 recommended. Case is not important.
2145 On the H8/300, Renesas / SuperH SH, and AMD 29K architectures, the
2146 letter must be one of the letters `DFPRSX' (in upper or lower
2149 On the ARC, the letter must be one of the letters `DFRS' (in upper
2152 On the Intel 960 architecture, the letter must be one of the
2153 letters `DFT' (in upper or lower case).
2155 On the HPPA architecture, the letter must be `E' (upper case only).
2157 * An optional sign: either `+' or `-'.
2159 * An optional "integer part": zero or more decimal digits.
2161 * An optional "fractional part": `.' followed by zero or more
2164 * An optional exponent, consisting of:
2168 * Optional sign: either `+' or `-'.
2170 * One or more decimal digits.
2173 At least one of the integer part or the fractional part must be
2174 present. The floating point number has the usual base-10 value.
2176 `as' does all processing using integers. Flonums are computed
2177 independently of any floating point hardware in the computer running
2181 File: as.info, Node: Sections, Next: Symbols, Prev: Syntax, Up: Top
2183 4 Sections and Relocation
2184 *************************
2188 * Secs Background:: Background
2189 * Ld Sections:: Linker Sections
2190 * As Sections:: Assembler Internal Sections
2191 * Sub-Sections:: Sub-Sections
2195 File: as.info, Node: Secs Background, Next: Ld Sections, Up: Sections
2200 Roughly, a section is a range of addresses, with no gaps; all data "in"
2201 those addresses is treated the same for some particular purpose. For
2202 example there may be a "read only" section.
2204 The linker `ld' reads many object files (partial programs) and
2205 combines their contents to form a runnable program. When `as' emits an
2206 object file, the partial program is assumed to start at address 0.
2207 `ld' assigns the final addresses for the partial program, so that
2208 different partial programs do not overlap. This is actually an
2209 oversimplification, but it suffices to explain how `as' uses sections.
2211 `ld' moves blocks of bytes of your program to their run-time
2212 addresses. These blocks slide to their run-time addresses as rigid
2213 units; their length does not change and neither does the order of bytes
2214 within them. Such a rigid unit is called a _section_. Assigning
2215 run-time addresses to sections is called "relocation". It includes the
2216 task of adjusting mentions of object-file addresses so they refer to
2217 the proper run-time addresses. For the H8/300, and for the Renesas /
2218 SuperH SH, `as' pads sections if needed to ensure they end on a word
2219 (sixteen bit) boundary.
2221 An object file written by `as' has at least three sections, any of
2222 which may be empty. These are named "text", "data" and "bss" sections.
2224 When it generates COFF or ELF output, `as' can also generate
2225 whatever other named sections you specify using the `.section'
2226 directive (*note `.section': Section.). If you do not use any
2227 directives that place output in the `.text' or `.data' sections, these
2228 sections still exist, but are empty.
2230 When `as' generates SOM or ELF output for the HPPA, `as' can also
2231 generate whatever other named sections you specify using the `.space'
2232 and `.subspace' directives. See `HP9000 Series 800 Assembly Language
2233 Reference Manual' (HP 92432-90001) for details on the `.space' and
2234 `.subspace' assembler directives.
2236 Additionally, `as' uses different names for the standard text, data,
2237 and bss sections when generating SOM output. Program text is placed
2238 into the `$CODE$' section, data into `$DATA$', and BSS into `$BSS$'.
2240 Within the object file, the text section starts at address `0', the
2241 data section follows, and the bss section follows the data section.
2243 When generating either SOM or ELF output files on the HPPA, the text
2244 section starts at address `0', the data section at address `0x4000000',
2245 and the bss section follows the data section.
2247 To let `ld' know which data changes when the sections are relocated,
2248 and how to change that data, `as' also writes to the object file
2249 details of the relocation needed. To perform relocation `ld' must
2250 know, each time an address in the object file is mentioned:
2251 * Where in the object file is the beginning of this reference to an
2254 * How long (in bytes) is this reference?
2256 * Which section does the address refer to? What is the numeric
2258 (ADDRESS) - (START-ADDRESS OF SECTION)?
2260 * Is the reference to an address "Program-Counter relative"?
2262 In fact, every address `as' ever uses is expressed as
2263 (SECTION) + (OFFSET INTO SECTION)
2264 Further, most expressions `as' computes have this section-relative
2265 nature. (For some object formats, such as SOM for the HPPA, some
2266 expressions are symbol-relative instead.)
2268 In this manual we use the notation {SECNAME N} to mean "offset N
2269 into section SECNAME."
2271 Apart from text, data and bss sections you need to know about the
2272 "absolute" section. When `ld' mixes partial programs, addresses in the
2273 absolute section remain unchanged. For example, address `{absolute 0}'
2274 is "relocated" to run-time address 0 by `ld'. Although the linker
2275 never arranges two partial programs' data sections with overlapping
2276 addresses after linking, _by definition_ their absolute sections must
2277 overlap. Address `{absolute 239}' in one part of a program is always
2278 the same address when the program is running as address `{absolute
2279 239}' in any other part of the program.
2281 The idea of sections is extended to the "undefined" section. Any
2282 address whose section is unknown at assembly time is by definition
2283 rendered {undefined U}--where U is filled in later. Since numbers are
2284 always defined, the only way to generate an undefined address is to
2285 mention an undefined symbol. A reference to a named common block would
2286 be such a symbol: its value is unknown at assembly time so it has
2287 section _undefined_.
2289 By analogy the word _section_ is used to describe groups of sections
2290 in the linked program. `ld' puts all partial programs' text sections
2291 in contiguous addresses in the linked program. It is customary to
2292 refer to the _text section_ of a program, meaning all the addresses of
2293 all partial programs' text sections. Likewise for data and bss
2296 Some sections are manipulated by `ld'; others are invented for use
2297 of `as' and have no meaning except during assembly.
2300 File: as.info, Node: Ld Sections, Next: As Sections, Prev: Secs Background, Up: Sections
2305 `ld' deals with just four kinds of sections, summarized below.
2310 These sections hold your program. `as' and `ld' treat them as
2311 separate but equal sections. Anything you can say of one section
2312 is true of another. When the program is running, however, it is
2313 customary for the text section to be unalterable. The text
2314 section is often shared among processes: it contains instructions,
2315 constants and the like. The data section of a running program is
2316 usually alterable: for example, C variables would be stored in the
2320 This section contains zeroed bytes when your program begins
2321 running. It is used to hold uninitialized variables or common
2322 storage. The length of each partial program's bss section is
2323 important, but because it starts out containing zeroed bytes there
2324 is no need to store explicit zero bytes in the object file. The
2325 bss section was invented to eliminate those explicit zeros from
2329 Address 0 of this section is always "relocated" to runtime address
2330 0. This is useful if you want to refer to an address that `ld'
2331 must not change when relocating. In this sense we speak of
2332 absolute addresses being "unrelocatable": they do not change
2336 This "section" is a catch-all for address references to objects
2337 not in the preceding sections.
2339 An idealized example of three relocatable sections follows. The
2340 example uses the traditional section names `.text' and `.data'. Memory
2341 addresses are on the horizontal axis.
2344 partial program # 1: |ttttt|dddd|00|
2351 partial program # 2: |TTT|DDD|000|
2354 +--+---+-----+--+----+---+-----+~~
2355 linked program: | |TTT|ttttt| |dddd|DDD|00000|
2356 +--+---+-----+--+----+---+-----+~~
2361 File: as.info, Node: As Sections, Next: Sub-Sections, Prev: Ld Sections, Up: Sections
2363 4.3 Assembler Internal Sections
2364 ===============================
2366 These sections are meant only for the internal use of `as'. They have
2367 no meaning at run-time. You do not really need to know about these
2368 sections for most purposes; but they can be mentioned in `as' warning
2369 messages, so it might be helpful to have an idea of their meanings to
2370 `as'. These sections are used to permit the value of every expression
2371 in your assembly language program to be a section-relative address.
2373 ASSEMBLER-INTERNAL-LOGIC-ERROR!
2374 An internal assembler logic error has been found. This means
2375 there is a bug in the assembler.
2378 The assembler stores complex expression internally as combinations
2379 of symbols. When it needs to represent an expression as a symbol,
2380 it puts it in the expr section.
2383 File: as.info, Node: Sub-Sections, Next: bss, Prev: As Sections, Up: Sections
2388 Assembled bytes conventionally fall into two sections: text and data.
2389 You may have separate groups of data in named sections that you want to
2390 end up near to each other in the object file, even though they are not
2391 contiguous in the assembler source. `as' allows you to use
2392 "subsections" for this purpose. Within each section, there can be
2393 numbered subsections with values from 0 to 8192. Objects assembled
2394 into the same subsection go into the object file together with other
2395 objects in the same subsection. For example, a compiler might want to
2396 store constants in the text section, but might not want to have them
2397 interspersed with the program being assembled. In this case, the
2398 compiler could issue a `.text 0' before each section of code being
2399 output, and a `.text 1' before each group of constants being output.
2401 Subsections are optional. If you do not use subsections, everything
2402 goes in subsection number zero.
2404 Each subsection is zero-padded up to a multiple of four bytes.
2405 (Subsections may be padded a different amount on different flavors of
2408 Subsections appear in your object file in numeric order, lowest
2409 numbered to highest. (All this to be compatible with other people's
2410 assemblers.) The object file contains no representation of
2411 subsections; `ld' and other programs that manipulate object files see
2412 no trace of them. They just see all your text subsections as a text
2413 section, and all your data subsections as a data section.
2415 To specify which subsection you want subsequent statements assembled
2416 into, use a numeric argument to specify it, in a `.text EXPRESSION' or
2417 a `.data EXPRESSION' statement. When generating COFF output, you can
2418 also use an extra subsection argument with arbitrary named sections:
2419 `.section NAME, EXPRESSION'. When generating ELF output, you can also
2420 use the `.subsection' directive (*note SubSection::) to specify a
2421 subsection: `.subsection EXPRESSION'. EXPRESSION should be an absolute
2422 expression (*note Expressions::). If you just say `.text' then `.text
2423 0' is assumed. Likewise `.data' means `.data 0'. Assembly begins in
2424 `text 0'. For instance:
2425 .text 0 # The default subsection is text 0 anyway.
2426 .ascii "This lives in the first text subsection. *"
2428 .ascii "But this lives in the second text subsection."
2430 .ascii "This lives in the data section,"
2431 .ascii "in the first data subsection."
2433 .ascii "This lives in the first text section,"
2434 .ascii "immediately following the asterisk (*)."
2436 Each section has a "location counter" incremented by one for every
2437 byte assembled into that section. Because subsections are merely a
2438 convenience restricted to `as' there is no concept of a subsection
2439 location counter. There is no way to directly manipulate a location
2440 counter--but the `.align' directive changes it, and any label
2441 definition captures its current value. The location counter of the
2442 section where statements are being assembled is said to be the "active"
2446 File: as.info, Node: bss, Prev: Sub-Sections, Up: Sections
2451 The bss section is used for local common variable storage. You may
2452 allocate address space in the bss section, but you may not dictate data
2453 to load into it before your program executes. When your program starts
2454 running, all the contents of the bss section are zeroed bytes.
2456 The `.lcomm' pseudo-op defines a symbol in the bss section; see
2457 *Note `.lcomm': Lcomm.
2459 The `.comm' pseudo-op may be used to declare a common symbol, which
2460 is another form of uninitialized symbol; see *Note `.comm': Comm.
2462 When assembling for a target which supports multiple sections, such
2463 as ELF or COFF, you may switch into the `.bss' section and define
2464 symbols as usual; see *Note `.section': Section. You may only assemble
2465 zero values into the section. Typically the section will only contain
2466 symbol definitions and `.skip' directives (*note `.skip': Skip.).
2469 File: as.info, Node: Symbols, Next: Expressions, Prev: Sections, Up: Top
2474 Symbols are a central concept: the programmer uses symbols to name
2475 things, the linker uses symbols to link, and the debugger uses symbols
2478 _Warning:_ `as' does not place symbols in the object file in the
2479 same order they were declared. This may break some debuggers.
2484 * Setting Symbols:: Giving Symbols Other Values
2485 * Symbol Names:: Symbol Names
2486 * Dot:: The Special Dot Symbol
2487 * Symbol Attributes:: Symbol Attributes
2490 File: as.info, Node: Labels, Next: Setting Symbols, Up: Symbols
2495 A "label" is written as a symbol immediately followed by a colon `:'.
2496 The symbol then represents the current value of the active location
2497 counter, and is, for example, a suitable instruction operand. You are
2498 warned if you use the same symbol to represent two different locations:
2499 the first definition overrides any other definitions.
2501 On the HPPA, the usual form for a label need not be immediately
2502 followed by a colon, but instead must start in column zero. Only one
2503 label may be defined on a single line. To work around this, the HPPA
2504 version of `as' also provides a special directive `.label' for defining
2505 labels more flexibly.
2508 File: as.info, Node: Setting Symbols, Next: Symbol Names, Prev: Labels, Up: Symbols
2510 5.2 Giving Symbols Other Values
2511 ===============================
2513 A symbol can be given an arbitrary value by writing a symbol, followed
2514 by an equals sign `=', followed by an expression (*note Expressions::).
2515 This is equivalent to using the `.set' directive. *Note `.set': Set.
2516 In the same way, using a double equals sign `='`=' here represents an
2517 equivalent of the `.eqv' directive. *Note `.eqv': Eqv.
2519 Blackfin does not support symbol assignment with `='.
2522 File: as.info, Node: Symbol Names, Next: Dot, Prev: Setting Symbols, Up: Symbols
2527 Symbol names begin with a letter or with one of `._'. On most
2528 machines, you can also use `$' in symbol names; exceptions are noted in
2529 *Note Machine Dependencies::. That character may be followed by any
2530 string of digits, letters, dollar signs (unless otherwise noted for a
2531 particular target machine), and underscores.
2533 Case of letters is significant: `foo' is a different symbol name than
2536 Multibyte characters are supported. To generate a symbol name
2537 containing multibyte characters enclose it within double quotes and use
2538 escape codes. cf *Note Strings::. Generating a multibyte symbol name
2539 from a label is not currently supported.
2541 Each symbol has exactly one name. Each name in an assembly language
2542 program refers to exactly one symbol. You may use that symbol name any
2543 number of times in a program.
2548 A local symbol is any symbol beginning with certain local label
2549 prefixes. By default, the local label prefix is `.L' for ELF systems or
2550 `L' for traditional a.out systems, but each target may have its own set
2551 of local label prefixes. On the HPPA local symbols begin with `L$'.
2553 Local symbols are defined and used within the assembler, but they are
2554 normally not saved in object files. Thus, they are not visible when
2555 debugging. You may use the `-L' option (*note Include Local Symbols:
2556 `-L': L.) to retain the local symbols in the object files.
2561 Local labels help compilers and programmers use names temporarily.
2562 They create symbols which are guaranteed to be unique over the entire
2563 scope of the input source code and which can be referred to by a simple
2564 notation. To define a local label, write a label of the form `N:'
2565 (where N represents any positive integer). To refer to the most recent
2566 previous definition of that label write `Nb', using the same number as
2567 when you defined the label. To refer to the next definition of a local
2568 label, write `Nf'--the `b' stands for "backwards" and the `f' stands
2571 There is no restriction on how you can use these labels, and you can
2572 reuse them too. So that it is possible to repeatedly define the same
2573 local label (using the same number `N'), although you can only refer to
2574 the most recently defined local label of that number (for a backwards
2575 reference) or the next definition of a specific local label for a
2576 forward reference. It is also worth noting that the first 10 local
2577 labels (`0:'...`9:') are implemented in a slightly more efficient
2578 manner than the others.
2587 Which is the equivalent of:
2589 label_1: branch label_3
2590 label_2: branch label_1
2591 label_3: branch label_4
2592 label_4: branch label_3
2594 Local label names are only a notational device. They are immediately
2595 transformed into more conventional symbol names before the assembler
2596 uses them. The symbol names are stored in the symbol table, appear in
2597 error messages, and are optionally emitted to the object file. The
2598 names are constructed using these parts:
2600 `_local label prefix_'
2601 All local symbols begin with the system-specific local label
2602 prefix. Normally both `as' and `ld' forget symbols that start
2603 with the local label prefix. These labels are used for symbols
2604 you are never intended to see. If you use the `-L' option then
2605 `as' retains these symbols in the object file. If you also
2606 instruct `ld' to retain these symbols, you may use them in
2610 This is the number that was used in the local label definition.
2611 So if the label is written `55:' then the number is `55'.
2614 This unusual character is included so you do not accidentally
2615 invent a symbol of the same name. The character has ASCII value
2616 of `\002' (control-B).
2619 This is a serial number to keep the labels distinct. The first
2620 definition of `0:' gets the number `1'. The 15th definition of
2621 `0:' gets the number `15', and so on. Likewise the first
2622 definition of `1:' gets the number `1' and its 15th definition
2625 So for example, the first `1:' may be named `.L1C-B1', and the 44th
2626 `3:' may be named `.L3C-B44'.
2631 `as' also supports an even more local form of local labels called
2632 dollar labels. These labels go out of scope (i.e., they become
2633 undefined) as soon as a non-local label is defined. Thus they remain
2634 valid for only a small region of the input source code. Normal local
2635 labels, by contrast, remain in scope for the entire file, or until they
2636 are redefined by another occurrence of the same local label.
2638 Dollar labels are defined in exactly the same way as ordinary local
2639 labels, except that they have a dollar sign suffix to their numeric
2640 value, e.g., `55$:'.
2642 They can also be distinguished from ordinary local labels by their
2643 transformed names which use ASCII character `\001' (control-A) as the
2644 magic character to distinguish them from ordinary labels. For example,
2645 the fifth definition of `6$' may be named `.L6C-A5'.
2648 File: as.info, Node: Dot, Next: Symbol Attributes, Prev: Symbol Names, Up: Symbols
2650 5.4 The Special Dot Symbol
2651 ==========================
2653 The special symbol `.' refers to the current address that `as' is
2654 assembling into. Thus, the expression `melvin: .long .' defines
2655 `melvin' to contain its own address. Assigning a value to `.' is
2656 treated the same as a `.org' directive. Thus, the expression `.=.+4'
2657 is the same as saying `.space 4'.
2660 File: as.info, Node: Symbol Attributes, Prev: Dot, Up: Symbols
2662 5.5 Symbol Attributes
2663 =====================
2665 Every symbol has, as well as its name, the attributes "Value" and
2666 "Type". Depending on output format, symbols can also have auxiliary
2669 If you use a symbol without defining it, `as' assumes zero for all
2670 these attributes, and probably won't warn you. This makes the symbol
2671 an externally defined symbol, which is generally what you would want.
2675 * Symbol Value:: Value
2676 * Symbol Type:: Type
2679 * a.out Symbols:: Symbol Attributes: `a.out'
2681 * COFF Symbols:: Symbol Attributes for COFF
2683 * SOM Symbols:: Symbol Attributes for SOM
2686 File: as.info, Node: Symbol Value, Next: Symbol Type, Up: Symbol Attributes
2691 The value of a symbol is (usually) 32 bits. For a symbol which labels a
2692 location in the text, data, bss or absolute sections the value is the
2693 number of addresses from the start of that section to the label.
2694 Naturally for text, data and bss sections the value of a symbol changes
2695 as `ld' changes section base addresses during linking. Absolute
2696 symbols' values do not change during linking: that is why they are
2699 The value of an undefined symbol is treated in a special way. If it
2700 is 0 then the symbol is not defined in this assembler source file, and
2701 `ld' tries to determine its value from other files linked into the same
2702 program. You make this kind of symbol simply by mentioning a symbol
2703 name without defining it. A non-zero value represents a `.comm' common
2704 declaration. The value is how much common storage to reserve, in bytes
2705 (addresses). The symbol refers to the first address of the allocated
2709 File: as.info, Node: Symbol Type, Next: a.out Symbols, Prev: Symbol Value, Up: Symbol Attributes
2714 The type attribute of a symbol contains relocation (section)
2715 information, any flag settings indicating that a symbol is external, and
2716 (optionally), other information for linkers and debuggers. The exact
2717 format depends on the object-code output format in use.
2720 File: as.info, Node: a.out Symbols, Next: COFF Symbols, Prev: Symbol Type, Up: Symbol Attributes
2722 5.5.3 Symbol Attributes: `a.out'
2723 --------------------------------
2727 * Symbol Desc:: Descriptor
2728 * Symbol Other:: Other
2731 File: as.info, Node: Symbol Desc, Next: Symbol Other, Up: a.out Symbols
2736 This is an arbitrary 16-bit value. You may establish a symbol's
2737 descriptor value by using a `.desc' statement (*note `.desc': Desc.).
2738 A descriptor value means nothing to `as'.
2741 File: as.info, Node: Symbol Other, Prev: Symbol Desc, Up: a.out Symbols
2746 This is an arbitrary 8-bit value. It means nothing to `as'.
2749 File: as.info, Node: COFF Symbols, Next: SOM Symbols, Prev: a.out Symbols, Up: Symbol Attributes
2751 5.5.4 Symbol Attributes for COFF
2752 --------------------------------
2754 The COFF format supports a multitude of auxiliary symbol attributes;
2755 like the primary symbol attributes, they are set between `.def' and
2756 `.endef' directives.
2758 5.5.4.1 Primary Attributes
2759 ..........................
2761 The symbol name is set with `.def'; the value and type, respectively,
2762 with `.val' and `.type'.
2764 5.5.4.2 Auxiliary Attributes
2765 ............................
2767 The `as' directives `.dim', `.line', `.scl', `.size', `.tag', and
2768 `.weak' can generate auxiliary symbol table information for COFF.
2771 File: as.info, Node: SOM Symbols, Prev: COFF Symbols, Up: Symbol Attributes
2773 5.5.5 Symbol Attributes for SOM
2774 -------------------------------
2776 The SOM format for the HPPA supports a multitude of symbol attributes
2777 set with the `.EXPORT' and `.IMPORT' directives.
2779 The attributes are described in `HP9000 Series 800 Assembly Language
2780 Reference Manual' (HP 92432-90001) under the `IMPORT' and `EXPORT'
2781 assembler directive documentation.
2784 File: as.info, Node: Expressions, Next: Pseudo Ops, Prev: Symbols, Up: Top
2789 An "expression" specifies an address or numeric value. Whitespace may
2790 precede and/or follow an expression.
2792 The result of an expression must be an absolute number, or else an
2793 offset into a particular section. If an expression is not absolute,
2794 and there is not enough information when `as' sees the expression to
2795 know its section, a second pass over the source program might be
2796 necessary to interpret the expression--but the second pass is currently
2797 not implemented. `as' aborts with an error message in this situation.
2801 * Empty Exprs:: Empty Expressions
2802 * Integer Exprs:: Integer Expressions
2805 File: as.info, Node: Empty Exprs, Next: Integer Exprs, Up: Expressions
2807 6.1 Empty Expressions
2808 =====================
2810 An empty expression has no value: it is just whitespace or null.
2811 Wherever an absolute expression is required, you may omit the
2812 expression, and `as' assumes a value of (absolute) 0. This is
2813 compatible with other assemblers.
2816 File: as.info, Node: Integer Exprs, Prev: Empty Exprs, Up: Expressions
2818 6.2 Integer Expressions
2819 =======================
2821 An "integer expression" is one or more _arguments_ delimited by
2826 * Arguments:: Arguments
2827 * Operators:: Operators
2828 * Prefix Ops:: Prefix Operators
2829 * Infix Ops:: Infix Operators
2832 File: as.info, Node: Arguments, Next: Operators, Up: Integer Exprs
2837 "Arguments" are symbols, numbers or subexpressions. In other contexts
2838 arguments are sometimes called "arithmetic operands". In this manual,
2839 to avoid confusing them with the "instruction operands" of the machine
2840 language, we use the term "argument" to refer to parts of expressions
2841 only, reserving the word "operand" to refer only to machine instruction
2844 Symbols are evaluated to yield {SECTION NNN} where SECTION is one of
2845 text, data, bss, absolute, or undefined. NNN is a signed, 2's
2846 complement 32 bit integer.
2848 Numbers are usually integers.
2850 A number can be a flonum or bignum. In this case, you are warned
2851 that only the low order 32 bits are used, and `as' pretends these 32
2852 bits are an integer. You may write integer-manipulating instructions
2853 that act on exotic constants, compatible with other assemblers.
2855 Subexpressions are a left parenthesis `(' followed by an integer
2856 expression, followed by a right parenthesis `)'; or a prefix operator
2857 followed by an argument.
2860 File: as.info, Node: Operators, Next: Prefix Ops, Prev: Arguments, Up: Integer Exprs
2865 "Operators" are arithmetic functions, like `+' or `%'. Prefix
2866 operators are followed by an argument. Infix operators appear between
2867 their arguments. Operators may be preceded and/or followed by
2871 File: as.info, Node: Prefix Ops, Next: Infix Ops, Prev: Operators, Up: Integer Exprs
2873 6.2.3 Prefix Operator
2874 ---------------------
2876 `as' has the following "prefix operators". They each take one
2877 argument, which must be absolute.
2880 "Negation". Two's complement negation.
2883 "Complementation". Bitwise not.
2886 File: as.info, Node: Infix Ops, Prev: Prefix Ops, Up: Integer Exprs
2888 6.2.4 Infix Operators
2889 ---------------------
2891 "Infix operators" take two arguments, one on either side. Operators
2892 have precedence, but operations with equal precedence are performed left
2893 to right. Apart from `+' or `-', both arguments must be absolute, and
2894 the result is absolute.
2896 1. Highest Precedence
2902 "Division". Truncation is the same as the C operator `/'
2908 "Shift Left". Same as the C operator `<<'.
2911 "Shift Right". Same as the C operator `>>'.
2913 2. Intermediate precedence
2916 "Bitwise Inclusive Or".
2922 "Bitwise Exclusive Or".
2930 "Addition". If either argument is absolute, the result has
2931 the section of the other argument. You may not add together
2932 arguments from different sections.
2935 "Subtraction". If the right argument is absolute, the result
2936 has the section of the left argument. If both arguments are
2937 in the same section, the result is absolute. You may not
2938 subtract arguments from different sections.
2954 "Is Greater Than Or Equal To"
2957 "Is Less Than Or Equal To"
2959 The comparison operators can be used as infix operators. A
2960 true results has a value of -1 whereas a false result has a
2961 value of 0. Note, these operators perform signed
2964 4. Lowest Precedence
2972 These two logical operations can be used to combine the
2973 results of sub expressions. Note, unlike the comparison
2974 operators a true result returns a value of 1 but a false
2975 results does still return 0. Also note that the logical or
2976 operator has a slightly lower precedence than logical and.
2979 In short, it's only meaningful to add or subtract the _offsets_ in an
2980 address; you can only have a defined section in one of the two
2984 File: as.info, Node: Pseudo Ops, Next: Object Attributes, Prev: Expressions, Up: Top
2986 7 Assembler Directives
2987 **********************
2989 All assembler directives have names that begin with a period (`.').
2990 The rest of the name is letters, usually in lower case.
2992 This chapter discusses directives that are available regardless of
2993 the target machine configuration for the GNU assembler. Some machine
2994 configurations provide additional directives. *Note Machine
3001 * ABORT (COFF):: `.ABORT'
3003 * Align:: `.align ABS-EXPR , ABS-EXPR'
3004 * Altmacro:: `.altmacro'
3005 * Ascii:: `.ascii "STRING"'...
3006 * Asciz:: `.asciz "STRING"'...
3007 * Balign:: `.balign ABS-EXPR , ABS-EXPR'
3008 * Bundle directives:: `.bundle_align_mode ABS-EXPR', `.bundle_lock', `.bundle_unlock'
3009 * Byte:: `.byte EXPRESSIONS'
3010 * CFI directives:: `.cfi_startproc [simple]', `.cfi_endproc', etc.
3011 * Comm:: `.comm SYMBOL , LENGTH '
3012 * Data:: `.data SUBSECTION'
3016 * Desc:: `.desc SYMBOL, ABS-EXPRESSION'
3020 * Double:: `.double FLONUMS'
3023 * Elseif:: `.elseif'
3028 * Endfunc:: `.endfunc'
3030 * Equ:: `.equ SYMBOL, EXPRESSION'
3031 * Equiv:: `.equiv SYMBOL, EXPRESSION'
3032 * Eqv:: `.eqv SYMBOL, EXPRESSION'
3034 * Error:: `.error STRING'
3036 * Extern:: `.extern'
3039 * Fill:: `.fill REPEAT , SIZE , VALUE'
3040 * Float:: `.float FLONUMS'
3042 * Global:: `.global SYMBOL', `.globl SYMBOL'
3044 * Gnu_attribute:: `.gnu_attribute TAG,VALUE'
3045 * Hidden:: `.hidden NAMES'
3047 * hword:: `.hword EXPRESSIONS'
3049 * If:: `.if ABSOLUTE EXPRESSION'
3050 * Incbin:: `.incbin "FILE"[,SKIP[,COUNT]]'
3051 * Include:: `.include "FILE"'
3052 * Int:: `.int EXPRESSIONS'
3054 * Internal:: `.internal NAMES'
3056 * Irp:: `.irp SYMBOL,VALUES'...
3057 * Irpc:: `.irpc SYMBOL,VALUES'...
3058 * Lcomm:: `.lcomm SYMBOL , LENGTH'
3059 * Lflags:: `.lflags'
3061 * Line:: `.line LINE-NUMBER'
3063 * Linkonce:: `.linkonce [TYPE]'
3065 * Ln:: `.ln LINE-NUMBER'
3066 * Loc:: `.loc FILENO LINENO'
3067 * Loc_mark_labels:: `.loc_mark_labels ENABLE'
3069 * Local:: `.local NAMES'
3071 * Long:: `.long EXPRESSIONS'
3073 * Macro:: `.macro NAME ARGS'...
3075 * Noaltmacro:: `.noaltmacro'
3076 * Nolist:: `.nolist'
3077 * Octa:: `.octa BIGNUMS'
3078 * Offset:: `.offset LOC'
3079 * Org:: `.org NEW-LC, FILL'
3080 * P2align:: `.p2align ABS-EXPR, ABS-EXPR, ABS-EXPR'
3082 * PopSection:: `.popsection'
3083 * Previous:: `.previous'
3085 * Print:: `.print STRING'
3087 * Protected:: `.protected NAMES'
3089 * Psize:: `.psize LINES, COLUMNS'
3090 * Purgem:: `.purgem NAME'
3092 * PushSection:: `.pushsection NAME'
3094 * Quad:: `.quad BIGNUMS'
3095 * Reloc:: `.reloc OFFSET, RELOC_NAME[, EXPRESSION]'
3096 * Rept:: `.rept COUNT'
3097 * Sbttl:: `.sbttl "SUBHEADING"'
3099 * Scl:: `.scl CLASS'
3101 * Section:: `.section NAME[, FLAGS]'
3103 * Set:: `.set SYMBOL, EXPRESSION'
3104 * Short:: `.short EXPRESSIONS'
3105 * Single:: `.single FLONUMS'
3107 * Size:: `.size [NAME , EXPRESSION]'
3109 * Skip:: `.skip SIZE , FILL'
3111 * Sleb128:: `.sleb128 EXPRESSIONS'
3113 * Space:: `.space SIZE , FILL'
3115 * Stab:: `.stabd, .stabn, .stabs'
3117 * String:: `.string "STR"', `.string8 "STR"', `.string16 "STR"', `.string32 "STR"', `.string64 "STR"'
3118 * Struct:: `.struct EXPRESSION'
3120 * SubSection:: `.subsection'
3121 * Symver:: `.symver NAME,NAME2@NODENAME'
3124 * Tag:: `.tag STRUCTNAME'
3126 * Text:: `.text SUBSECTION'
3127 * Title:: `.title "HEADING"'
3129 * Type:: `.type <INT | NAME , TYPE DESCRIPTION>'
3131 * Uleb128:: `.uleb128 EXPRESSIONS'
3136 * Version:: `.version "STRING"'
3137 * VTableEntry:: `.vtable_entry TABLE, OFFSET'
3138 * VTableInherit:: `.vtable_inherit CHILD, PARENT'
3140 * Warning:: `.warning STRING'
3141 * Weak:: `.weak NAMES'
3142 * Weakref:: `.weakref ALIAS, SYMBOL'
3143 * Word:: `.word EXPRESSIONS'
3144 * Deprecated:: Deprecated Directives
3147 File: as.info, Node: Abort, Next: ABORT (COFF), Up: Pseudo Ops
3152 This directive stops the assembly immediately. It is for compatibility
3153 with other assemblers. The original idea was that the assembly
3154 language source would be piped into the assembler. If the sender of
3155 the source quit, it could use this directive tells `as' to quit also.
3156 One day `.abort' will not be supported.
3159 File: as.info, Node: ABORT (COFF), Next: Align, Prev: Abort, Up: Pseudo Ops
3164 When producing COFF output, `as' accepts this directive as a synonym
3168 File: as.info, Node: Align, Next: Altmacro, Prev: ABORT (COFF), Up: Pseudo Ops
3170 7.3 `.align ABS-EXPR, ABS-EXPR, ABS-EXPR'
3171 =========================================
3173 Pad the location counter (in the current subsection) to a particular
3174 storage boundary. The first expression (which must be absolute) is the
3175 alignment required, as described below.
3177 The second expression (also absolute) gives the fill value to be
3178 stored in the padding bytes. It (and the comma) may be omitted. If it
3179 is omitted, the padding bytes are normally zero. However, on some
3180 systems, if the section is marked as containing code and the fill value
3181 is omitted, the space is filled with no-op instructions.
3183 The third expression is also absolute, and is also optional. If it
3184 is present, it is the maximum number of bytes that should be skipped by
3185 this alignment directive. If doing the alignment would require
3186 skipping more bytes than the specified maximum, then the alignment is
3187 not done at all. You can omit the fill value (the second argument)
3188 entirely by simply using two commas after the required alignment; this
3189 can be useful if you want the alignment to be filled with no-op
3190 instructions when appropriate.
3192 The way the required alignment is specified varies from system to
3193 system. For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or1k,
3194 s390, sparc, tic4x, tic80 and xtensa, the first expression is the
3195 alignment request in bytes. For example `.align 8' advances the
3196 location counter until it is a multiple of 8. If the location counter
3197 is already a multiple of 8, no change is needed. For the tic54x, the
3198 first expression is the alignment request in words.
3200 For other systems, including ppc, i386 using a.out format, arm and
3201 strongarm, it is the number of low-order zero bits the location counter
3202 must have after advancement. For example `.align 3' advances the
3203 location counter until it a multiple of 8. If the location counter is
3204 already a multiple of 8, no change is needed.
3206 This inconsistency is due to the different behaviors of the various
3207 native assemblers for these systems which GAS must emulate. GAS also
3208 provides `.balign' and `.p2align' directives, described later, which
3209 have a consistent behavior across all architectures (but are specific
3213 File: as.info, Node: Altmacro, Next: Ascii, Prev: Align, Up: Pseudo Ops
3218 Enable alternate macro mode, enabling:
3220 `LOCAL NAME [ , ... ]'
3221 One additional directive, `LOCAL', is available. It is used to
3222 generate a string replacement for each of the NAME arguments, and
3223 replace any instances of NAME in each macro expansion. The
3224 replacement string is unique in the assembly, and different for
3225 each separate macro expansion. `LOCAL' allows you to write macros
3226 that define symbols, without fear of conflict between separate
3230 You can write strings delimited in these other ways besides
3234 You can delimit strings with single-quote characters.
3237 You can delimit strings with matching angle brackets.
3239 `single-character string escape'
3240 To include any single character literally in a string (even if the
3241 character would otherwise have some special meaning), you can
3242 prefix the character with `!' (an exclamation mark). For example,
3243 you can write `<4.3 !> 5.4!!>' to get the literal text `4.3 >
3246 `Expression results as strings'
3247 You can write `%EXPR' to evaluate the expression EXPR and use the
3251 File: as.info, Node: Ascii, Next: Asciz, Prev: Altmacro, Up: Pseudo Ops
3253 7.5 `.ascii "STRING"'...
3254 ========================
3256 `.ascii' expects zero or more string literals (*note Strings::)
3257 separated by commas. It assembles each string (with no automatic
3258 trailing zero byte) into consecutive addresses.
3261 File: as.info, Node: Asciz, Next: Balign, Prev: Ascii, Up: Pseudo Ops
3263 7.6 `.asciz "STRING"'...
3264 ========================
3266 `.asciz' is just like `.ascii', but each string is followed by a zero
3267 byte. The "z" in `.asciz' stands for "zero".
3270 File: as.info, Node: Balign, Next: Bundle directives, Prev: Asciz, Up: Pseudo Ops
3272 7.7 `.balign[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR'
3273 ==============================================
3275 Pad the location counter (in the current subsection) to a particular
3276 storage boundary. The first expression (which must be absolute) is the
3277 alignment request in bytes. For example `.balign 8' advances the
3278 location counter until it is a multiple of 8. If the location counter
3279 is already a multiple of 8, no change is needed.
3281 The second expression (also absolute) gives the fill value to be
3282 stored in the padding bytes. It (and the comma) may be omitted. If it
3283 is omitted, the padding bytes are normally zero. However, on some
3284 systems, if the section is marked as containing code and the fill value
3285 is omitted, the space is filled with no-op instructions.
3287 The third expression is also absolute, and is also optional. If it
3288 is present, it is the maximum number of bytes that should be skipped by
3289 this alignment directive. If doing the alignment would require
3290 skipping more bytes than the specified maximum, then the alignment is
3291 not done at all. You can omit the fill value (the second argument)
3292 entirely by simply using two commas after the required alignment; this
3293 can be useful if you want the alignment to be filled with no-op
3294 instructions when appropriate.
3296 The `.balignw' and `.balignl' directives are variants of the
3297 `.balign' directive. The `.balignw' directive treats the fill pattern
3298 as a two byte word value. The `.balignl' directives treats the fill
3299 pattern as a four byte longword value. For example, `.balignw
3300 4,0x368d' will align to a multiple of 4. If it skips two bytes, they
3301 will be filled in with the value 0x368d (the exact placement of the
3302 bytes depends upon the endianness of the processor). If it skips 1 or
3303 3 bytes, the fill value is undefined.
3306 File: as.info, Node: Bundle directives, Next: Byte, Prev: Balign, Up: Pseudo Ops
3308 7.8 `.bundle_align_mode ABS-EXPR'
3309 =================================
3311 `.bundle_align_mode' enables or disables "aligned instruction bundle"
3312 mode. In this mode, sequences of adjacent instructions are grouped
3313 into fixed-sized "bundles". If the argument is zero, this mode is
3314 disabled (which is the default state). If the argument it not zero, it
3315 gives the size of an instruction bundle as a power of two (as for the
3316 `.p2align' directive, *note P2align::).
3318 For some targets, it's an ABI requirement that no instruction may
3319 span a certain aligned boundary. A "bundle" is simply a sequence of
3320 instructions that starts on an aligned boundary. For example, if
3321 ABS-EXPR is `5' then the bundle size is 32, so each aligned chunk of 32
3322 bytes is a bundle. When aligned instruction bundle mode is in effect,
3323 no single instruction may span a boundary between bundles. If an
3324 instruction would start too close to the end of a bundle for the length
3325 of that particular instruction to fit within the bundle, then the space
3326 at the end of that bundle is filled with no-op instructions so the
3327 instruction starts in the next bundle. As a corollary, it's an error
3328 if any single instruction's encoding is longer than the bundle size.
3330 7.9 `.bundle_lock' and `.bundle_unlock'
3331 =======================================
3333 The `.bundle_lock' and directive `.bundle_unlock' directives allow
3334 explicit control over instruction bundle padding. These directives are
3335 only valid when `.bundle_align_mode' has been used to enable aligned
3336 instruction bundle mode. It's an error if they appear when
3337 `.bundle_align_mode' has not been used at all, or when the last
3338 directive was `.bundle_align_mode 0'.
3340 For some targets, it's an ABI requirement that certain instructions
3341 may appear only as part of specified permissible sequences of multiple
3342 instructions, all within the same bundle. A pair of `.bundle_lock' and
3343 `.bundle_unlock' directives define a "bundle-locked" instruction
3344 sequence. For purposes of aligned instruction bundle mode, a sequence
3345 starting with `.bundle_lock' and ending with `.bundle_unlock' is
3346 treated as a single instruction. That is, the entire sequence must fit
3347 into a single bundle and may not span a bundle boundary. If necessary,
3348 no-op instructions will be inserted before the first instruction of the
3349 sequence so that the whole sequence starts on an aligned bundle
3350 boundary. It's an error if the sequence is longer than the bundle size.
3352 For convenience when using `.bundle_lock' and `.bundle_unlock'
3353 inside assembler macros (*note Macro::), bundle-locked sequences may be
3354 nested. That is, a second `.bundle_lock' directive before the next
3355 `.bundle_unlock' directive has no effect except that it must be matched
3356 by another closing `.bundle_unlock' so that there is the same number of
3357 `.bundle_lock' and `.bundle_unlock' directives.
3360 File: as.info, Node: Byte, Next: CFI directives, Prev: Bundle directives, Up: Pseudo Ops
3362 7.10 `.byte EXPRESSIONS'
3363 ========================
3365 `.byte' expects zero or more expressions, separated by commas. Each
3366 expression is assembled into the next byte.
3369 File: as.info, Node: CFI directives, Next: Comm, Prev: Byte, Up: Pseudo Ops
3371 7.11 `.cfi_sections SECTION_LIST'
3372 =================================
3374 `.cfi_sections' may be used to specify whether CFI directives should
3375 emit `.eh_frame' section and/or `.debug_frame' section. If
3376 SECTION_LIST is `.eh_frame', `.eh_frame' is emitted, if SECTION_LIST is
3377 `.debug_frame', `.debug_frame' is emitted. To emit both use
3378 `.eh_frame, .debug_frame'. The default if this directive is not used
3379 is `.cfi_sections .eh_frame'.
3381 7.12 `.cfi_startproc [simple]'
3382 ==============================
3384 `.cfi_startproc' is used at the beginning of each function that should
3385 have an entry in `.eh_frame'. It initializes some internal data
3386 structures. Don't forget to close the function by `.cfi_endproc'.
3388 Unless `.cfi_startproc' is used along with parameter `simple' it
3389 also emits some architecture dependent initial CFI instructions.
3394 `.cfi_endproc' is used at the end of a function where it closes its
3395 unwind entry previously opened by `.cfi_startproc', and emits it to
3398 7.14 `.cfi_personality ENCODING [, EXP]'
3399 ========================================
3401 `.cfi_personality' defines personality routine and its encoding.
3402 ENCODING must be a constant determining how the personality should be
3403 encoded. If it is 255 (`DW_EH_PE_omit'), second argument is not
3404 present, otherwise second argument should be a constant or a symbol
3405 name. When using indirect encodings, the symbol provided should be the
3406 location where personality can be loaded from, not the personality
3407 routine itself. The default after `.cfi_startproc' is
3408 `.cfi_personality 0xff', no personality routine.
3410 7.15 `.cfi_lsda ENCODING [, EXP]'
3411 =================================
3413 `.cfi_lsda' defines LSDA and its encoding. ENCODING must be a constant
3414 determining how the LSDA should be encoded. If it is 255
3415 (`DW_EH_PE_omit'), second argument is not present, otherwise second
3416 argument should be a constant or a symbol name. The default after
3417 `.cfi_startproc' is `.cfi_lsda 0xff', no LSDA.
3419 7.16 `.cfi_def_cfa REGISTER, OFFSET'
3420 ====================================
3422 `.cfi_def_cfa' defines a rule for computing CFA as: take address from
3423 REGISTER and add OFFSET to it.
3425 7.17 `.cfi_def_cfa_register REGISTER'
3426 =====================================
3428 `.cfi_def_cfa_register' modifies a rule for computing CFA. From now on
3429 REGISTER will be used instead of the old one. Offset remains the same.
3431 7.18 `.cfi_def_cfa_offset OFFSET'
3432 =================================
3434 `.cfi_def_cfa_offset' modifies a rule for computing CFA. Register
3435 remains the same, but OFFSET is new. Note that it is the absolute
3436 offset that will be added to a defined register to compute CFA address.
3438 7.19 `.cfi_adjust_cfa_offset OFFSET'
3439 ====================================
3441 Same as `.cfi_def_cfa_offset' but OFFSET is a relative value that is
3442 added/substracted from the previous offset.
3444 7.20 `.cfi_offset REGISTER, OFFSET'
3445 ===================================
3447 Previous value of REGISTER is saved at offset OFFSET from CFA.
3449 7.21 `.cfi_rel_offset REGISTER, OFFSET'
3450 =======================================
3452 Previous value of REGISTER is saved at offset OFFSET from the current
3453 CFA register. This is transformed to `.cfi_offset' using the known
3454 displacement of the CFA register from the CFA. This is often easier to
3455 use, because the number will match the code it's annotating.
3457 7.22 `.cfi_register REGISTER1, REGISTER2'
3458 =========================================
3460 Previous value of REGISTER1 is saved in register REGISTER2.
3462 7.23 `.cfi_restore REGISTER'
3463 ============================
3465 `.cfi_restore' says that the rule for REGISTER is now the same as it
3466 was at the beginning of the function, after all initial instruction
3467 added by `.cfi_startproc' were executed.
3469 7.24 `.cfi_undefined REGISTER'
3470 ==============================
3472 From now on the previous value of REGISTER can't be restored anymore.
3474 7.25 `.cfi_same_value REGISTER'
3475 ===============================
3477 Current value of REGISTER is the same like in the previous frame, i.e.
3478 no restoration needed.
3480 7.26 `.cfi_remember_state',
3481 ===========================
3483 First save all current rules for all registers by `.cfi_remember_state',
3484 then totally screw them up by subsequent `.cfi_*' directives and when
3485 everything is hopelessly bad, use `.cfi_restore_state' to restore the
3486 previous saved state.
3488 7.27 `.cfi_return_column REGISTER'
3489 ==================================
3491 Change return column REGISTER, i.e. the return address is either
3492 directly in REGISTER or can be accessed by rules for REGISTER.
3494 7.28 `.cfi_signal_frame'
3495 ========================
3497 Mark current function as signal trampoline.
3499 7.29 `.cfi_window_save'
3500 =======================
3502 SPARC register window has been saved.
3504 7.30 `.cfi_escape' EXPRESSION[, ...]
3505 ====================================
3507 Allows the user to add arbitrary bytes to the unwind info. One might
3508 use this to add OS-specific CFI opcodes, or generic CFI opcodes that
3509 GAS does not yet support.
3511 7.31 `.cfi_val_encoded_addr REGISTER, ENCODING, LABEL'
3512 ======================================================
3514 The current value of REGISTER is LABEL. The value of LABEL will be
3515 encoded in the output file according to ENCODING; see the description
3516 of `.cfi_personality' for details on this encoding.
3518 The usefulness of equating a register to a fixed label is probably
3519 limited to the return address register. Here, it can be useful to mark
3520 a code segment that has only one return address which is reached by a
3521 direct branch and no copy of the return address exists in memory or
3525 File: as.info, Node: Comm, Next: Data, Prev: CFI directives, Up: Pseudo Ops
3527 7.32 `.comm SYMBOL , LENGTH '
3528 =============================
3530 `.comm' declares a common symbol named SYMBOL. When linking, a common
3531 symbol in one object file may be merged with a defined or common symbol
3532 of the same name in another object file. If `ld' does not see a
3533 definition for the symbol-just one or more common symbols-then it will
3534 allocate LENGTH bytes of uninitialized memory. LENGTH must be an
3535 absolute expression. If `ld' sees multiple common symbols with the
3536 same name, and they do not all have the same size, it will allocate
3537 space using the largest size.
3539 When using ELF or (as a GNU extension) PE, the `.comm' directive
3540 takes an optional third argument. This is the desired alignment of the
3541 symbol, specified for ELF as a byte boundary (for example, an alignment
3542 of 16 means that the least significant 4 bits of the address should be
3543 zero), and for PE as a power of two (for example, an alignment of 5
3544 means aligned to a 32-byte boundary). The alignment must be an
3545 absolute expression, and it must be a power of two. If `ld' allocates
3546 uninitialized memory for the common symbol, it will use the alignment
3547 when placing the symbol. If no alignment is specified, `as' will set
3548 the alignment to the largest power of two less than or equal to the
3549 size of the symbol, up to a maximum of 16 on ELF, or the default
3550 section alignment of 4 on PE(1).
3552 The syntax for `.comm' differs slightly on the HPPA. The syntax is
3553 `SYMBOL .comm, LENGTH'; SYMBOL is optional.
3555 ---------- Footnotes ----------
3557 (1) This is not the same as the executable image file alignment
3558 controlled by `ld''s `--section-alignment' option; image file sections
3559 in PE are aligned to multiples of 4096, which is far too large an
3560 alignment for ordinary variables. It is rather the default alignment
3561 for (non-debug) sections within object (`*.o') files, which are less
3565 File: as.info, Node: Data, Next: Def, Prev: Comm, Up: Pseudo Ops
3567 7.33 `.data SUBSECTION'
3568 =======================
3570 `.data' tells `as' to assemble the following statements onto the end of
3571 the data subsection numbered SUBSECTION (which is an absolute
3572 expression). If SUBSECTION is omitted, it defaults to zero.
3575 File: as.info, Node: Def, Next: Desc, Prev: Data, Up: Pseudo Ops
3580 Begin defining debugging information for a symbol NAME; the definition
3581 extends until the `.endef' directive is encountered.
3584 File: as.info, Node: Desc, Next: Dim, Prev: Def, Up: Pseudo Ops
3586 7.35 `.desc SYMBOL, ABS-EXPRESSION'
3587 ===================================
3589 This directive sets the descriptor of the symbol (*note Symbol
3590 Attributes::) to the low 16 bits of an absolute expression.
3592 The `.desc' directive is not available when `as' is configured for
3593 COFF output; it is only for `a.out' or `b.out' object format. For the
3594 sake of compatibility, `as' accepts it, but produces no output, when
3595 configured for COFF.
3598 File: as.info, Node: Dim, Next: Double, Prev: Desc, Up: Pseudo Ops
3603 This directive is generated by compilers to include auxiliary debugging
3604 information in the symbol table. It is only permitted inside
3605 `.def'/`.endef' pairs.
3608 File: as.info, Node: Double, Next: Eject, Prev: Dim, Up: Pseudo Ops
3610 7.37 `.double FLONUMS'
3611 ======================
3613 `.double' expects zero or more flonums, separated by commas. It
3614 assembles floating point numbers. The exact kind of floating point
3615 numbers emitted depends on how `as' is configured. *Note Machine
3619 File: as.info, Node: Eject, Next: Else, Prev: Double, Up: Pseudo Ops
3624 Force a page break at this point, when generating assembly listings.
3627 File: as.info, Node: Else, Next: Elseif, Prev: Eject, Up: Pseudo Ops
3632 `.else' is part of the `as' support for conditional assembly; see *Note
3633 `.if': If. It marks the beginning of a section of code to be assembled
3634 if the condition for the preceding `.if' was false.
3637 File: as.info, Node: Elseif, Next: End, Prev: Else, Up: Pseudo Ops
3642 `.elseif' is part of the `as' support for conditional assembly; see
3643 *Note `.if': If. It is shorthand for beginning a new `.if' block that
3644 would otherwise fill the entire `.else' section.
3647 File: as.info, Node: End, Next: Endef, Prev: Elseif, Up: Pseudo Ops
3652 `.end' marks the end of the assembly file. `as' does not process
3653 anything in the file past the `.end' directive.
3656 File: as.info, Node: Endef, Next: Endfunc, Prev: End, Up: Pseudo Ops
3661 This directive flags the end of a symbol definition begun with `.def'.
3664 File: as.info, Node: Endfunc, Next: Endif, Prev: Endef, Up: Pseudo Ops
3669 `.endfunc' marks the end of a function specified with `.func'.
3672 File: as.info, Node: Endif, Next: Equ, Prev: Endfunc, Up: Pseudo Ops
3677 `.endif' is part of the `as' support for conditional assembly; it marks
3678 the end of a block of code that is only assembled conditionally. *Note
3682 File: as.info, Node: Equ, Next: Equiv, Prev: Endif, Up: Pseudo Ops
3684 7.45 `.equ SYMBOL, EXPRESSION'
3685 ==============================
3687 This directive sets the value of SYMBOL to EXPRESSION. It is
3688 synonymous with `.set'; see *Note `.set': Set.
3690 The syntax for `equ' on the HPPA is `SYMBOL .equ EXPRESSION'.
3692 The syntax for `equ' on the Z80 is `SYMBOL equ EXPRESSION'. On the
3693 Z80 it is an eror if SYMBOL is already defined, but the symbol is not
3694 protected from later redefinition. Compare *Note Equiv::.
3697 File: as.info, Node: Equiv, Next: Eqv, Prev: Equ, Up: Pseudo Ops
3699 7.46 `.equiv SYMBOL, EXPRESSION'
3700 ================================
3702 The `.equiv' directive is like `.equ' and `.set', except that the
3703 assembler will signal an error if SYMBOL is already defined. Note a
3704 symbol which has been referenced but not actually defined is considered
3707 Except for the contents of the error message, this is roughly
3713 plus it protects the symbol from later redefinition.
3716 File: as.info, Node: Eqv, Next: Err, Prev: Equiv, Up: Pseudo Ops
3718 7.47 `.eqv SYMBOL, EXPRESSION'
3719 ==============================
3721 The `.eqv' directive is like `.equiv', but no attempt is made to
3722 evaluate the expression or any part of it immediately. Instead each
3723 time the resulting symbol is used in an expression, a snapshot of its
3724 current value is taken.
3727 File: as.info, Node: Err, Next: Error, Prev: Eqv, Up: Pseudo Ops
3732 If `as' assembles a `.err' directive, it will print an error message
3733 and, unless the `-Z' option was used, it will not generate an object
3734 file. This can be used to signal an error in conditionally compiled
3738 File: as.info, Node: Error, Next: Exitm, Prev: Err, Up: Pseudo Ops
3740 7.49 `.error "STRING"'
3741 ======================
3743 Similarly to `.err', this directive emits an error, but you can specify
3744 a string that will be emitted as the error message. If you don't
3745 specify the message, it defaults to `".error directive invoked in
3746 source file"'. *Note Error and Warning Messages: Errors.
3748 .error "This code has not been assembled and tested."
3751 File: as.info, Node: Exitm, Next: Extern, Prev: Error, Up: Pseudo Ops
3756 Exit early from the current macro definition. *Note Macro::.
3759 File: as.info, Node: Extern, Next: Fail, Prev: Exitm, Up: Pseudo Ops
3764 `.extern' is accepted in the source program--for compatibility with
3765 other assemblers--but it is ignored. `as' treats all undefined symbols
3769 File: as.info, Node: Fail, Next: File, Prev: Extern, Up: Pseudo Ops
3771 7.52 `.fail EXPRESSION'
3772 =======================
3774 Generates an error or a warning. If the value of the EXPRESSION is 500
3775 or more, `as' will print a warning message. If the value is less than
3776 500, `as' will print an error message. The message will include the
3777 value of EXPRESSION. This can occasionally be useful inside complex
3778 nested macros or conditional assembly.
3781 File: as.info, Node: File, Next: Fill, Prev: Fail, Up: Pseudo Ops
3786 There are two different versions of the `.file' directive. Targets
3787 that support DWARF2 line number information use the DWARF2 version of
3788 `.file'. Other targets use the default version.
3793 This version of the `.file' directive tells `as' that we are about to
3794 start a new logical file. The syntax is:
3798 STRING is the new file name. In general, the filename is recognized
3799 whether or not it is surrounded by quotes `"'; but if you wish to
3800 specify an empty file name, you must give the quotes-`""'. This
3801 statement may go away in future: it is only recognized to be compatible
3802 with old `as' programs.
3807 When emitting DWARF2 line number information, `.file' assigns filenames
3808 to the `.debug_line' file name table. The syntax is:
3810 .file FILENO FILENAME
3812 The FILENO operand should be a unique positive integer to use as the
3813 index of the entry in the table. The FILENAME operand is a C string
3816 The detail of filename indices is exposed to the user because the
3817 filename table is shared with the `.debug_info' section of the DWARF2
3818 debugging information, and thus the user must know the exact indices
3819 that table entries will have.
3822 File: as.info, Node: Fill, Next: Float, Prev: File, Up: Pseudo Ops
3824 7.54 `.fill REPEAT , SIZE , VALUE'
3825 ==================================
3827 REPEAT, SIZE and VALUE are absolute expressions. This emits REPEAT
3828 copies of SIZE bytes. REPEAT may be zero or more. SIZE may be zero or
3829 more, but if it is more than 8, then it is deemed to have the value 8,
3830 compatible with other people's assemblers. The contents of each REPEAT
3831 bytes is taken from an 8-byte number. The highest order 4 bytes are
3832 zero. The lowest order 4 bytes are VALUE rendered in the byte-order of
3833 an integer on the computer `as' is assembling for. Each SIZE bytes in
3834 a repetition is taken from the lowest order SIZE bytes of this number.
3835 Again, this bizarre behavior is compatible with other people's
3838 SIZE and VALUE are optional. If the second comma and VALUE are
3839 absent, VALUE is assumed zero. If the first comma and following tokens
3840 are absent, SIZE is assumed to be 1.
3843 File: as.info, Node: Float, Next: Func, Prev: Fill, Up: Pseudo Ops
3845 7.55 `.float FLONUMS'
3846 =====================
3848 This directive assembles zero or more flonums, separated by commas. It
3849 has the same effect as `.single'. The exact kind of floating point
3850 numbers emitted depends on how `as' is configured. *Note Machine
3854 File: as.info, Node: Func, Next: Global, Prev: Float, Up: Pseudo Ops
3856 7.56 `.func NAME[,LABEL]'
3857 =========================
3859 `.func' emits debugging information to denote function NAME, and is
3860 ignored unless the file is assembled with debugging enabled. Only
3861 `--gstabs[+]' is currently supported. LABEL is the entry point of the
3862 function and if omitted NAME prepended with the `leading char' is used.
3863 `leading char' is usually `_' or nothing, depending on the target. All
3864 functions are currently defined to have `void' return type. The
3865 function must be terminated with `.endfunc'.
3868 File: as.info, Node: Global, Next: Gnu_attribute, Prev: Func, Up: Pseudo Ops
3870 7.57 `.global SYMBOL', `.globl SYMBOL'
3871 ======================================
3873 `.global' makes the symbol visible to `ld'. If you define SYMBOL in
3874 your partial program, its value is made available to other partial
3875 programs that are linked with it. Otherwise, SYMBOL takes its
3876 attributes from a symbol of the same name from another file linked into
3879 Both spellings (`.globl' and `.global') are accepted, for
3880 compatibility with other assemblers.
3882 On the HPPA, `.global' is not always enough to make it accessible to
3883 other partial programs. You may need the HPPA-only `.EXPORT' directive
3884 as well. *Note HPPA Assembler Directives: HPPA Directives.
3887 File: as.info, Node: Gnu_attribute, Next: Hidden, Prev: Global, Up: Pseudo Ops
3889 7.58 `.gnu_attribute TAG,VALUE'
3890 ===============================
3892 Record a GNU object attribute for this file. *Note Object Attributes::.
3895 File: as.info, Node: Hidden, Next: hword, Prev: Gnu_attribute, Up: Pseudo Ops
3897 7.59 `.hidden NAMES'
3898 ====================
3900 This is one of the ELF visibility directives. The other two are
3901 `.internal' (*note `.internal': Internal.) and `.protected' (*note
3902 `.protected': Protected.).
3904 This directive overrides the named symbols default visibility (which
3905 is set by their binding: local, global or weak). The directive sets
3906 the visibility to `hidden' which means that the symbols are not visible
3907 to other components. Such symbols are always considered to be
3908 `protected' as well.
3911 File: as.info, Node: hword, Next: Ident, Prev: Hidden, Up: Pseudo Ops
3913 7.60 `.hword EXPRESSIONS'
3914 =========================
3916 This expects zero or more EXPRESSIONS, and emits a 16 bit number for
3919 This directive is a synonym for `.short'; depending on the target
3920 architecture, it may also be a synonym for `.word'.
3923 File: as.info, Node: Ident, Next: If, Prev: hword, Up: Pseudo Ops
3928 This directive is used by some assemblers to place tags in object
3929 files. The behavior of this directive varies depending on the target.
3930 When using the a.out object file format, `as' simply accepts the
3931 directive for source-file compatibility with existing assemblers, but
3932 does not emit anything for it. When using COFF, comments are emitted
3933 to the `.comment' or `.rdata' section, depending on the target. When
3934 using ELF, comments are emitted to the `.comment' section.
3937 File: as.info, Node: If, Next: Incbin, Prev: Ident, Up: Pseudo Ops
3939 7.62 `.if ABSOLUTE EXPRESSION'
3940 ==============================
3942 `.if' marks the beginning of a section of code which is only considered
3943 part of the source program being assembled if the argument (which must
3944 be an ABSOLUTE EXPRESSION) is non-zero. The end of the conditional
3945 section of code must be marked by `.endif' (*note `.endif': Endif.);
3946 optionally, you may include code for the alternative condition, flagged
3947 by `.else' (*note `.else': Else.). If you have several conditions to
3948 check, `.elseif' may be used to avoid nesting blocks if/else within
3949 each subsequent `.else' block.
3951 The following variants of `.if' are also supported:
3953 Assembles the following section of code if the specified SYMBOL
3954 has been defined. Note a symbol which has been referenced but not
3955 yet defined is considered to be undefined.
3958 Assembles the following section of code if the operand is blank
3961 `.ifc STRING1,STRING2'
3962 Assembles the following section of code if the two strings are the
3963 same. The strings may be optionally quoted with single quotes.
3964 If they are not quoted, the first string stops at the first comma,
3965 and the second string stops at the end of the line. Strings which
3966 contain whitespace should be quoted. The string comparison is
3969 `.ifeq ABSOLUTE EXPRESSION'
3970 Assembles the following section of code if the argument is zero.
3972 `.ifeqs STRING1,STRING2'
3973 Another form of `.ifc'. The strings must be quoted using double
3976 `.ifge ABSOLUTE EXPRESSION'
3977 Assembles the following section of code if the argument is greater
3978 than or equal to zero.
3980 `.ifgt ABSOLUTE EXPRESSION'
3981 Assembles the following section of code if the argument is greater
3984 `.ifle ABSOLUTE EXPRESSION'
3985 Assembles the following section of code if the argument is less
3986 than or equal to zero.
3988 `.iflt ABSOLUTE EXPRESSION'
3989 Assembles the following section of code if the argument is less
3993 Like `.ifb', but the sense of the test is reversed: this assembles
3994 the following section of code if the operand is non-blank
3997 `.ifnc STRING1,STRING2.'
3998 Like `.ifc', but the sense of the test is reversed: this assembles
3999 the following section of code if the two strings are not the same.
4003 Assembles the following section of code if the specified SYMBOL
4004 has not been defined. Both spelling variants are equivalent.
4005 Note a symbol which has been referenced but not yet defined is
4006 considered to be undefined.
4008 `.ifne ABSOLUTE EXPRESSION'
4009 Assembles the following section of code if the argument is not
4010 equal to zero (in other words, this is equivalent to `.if').
4012 `.ifnes STRING1,STRING2'
4013 Like `.ifeqs', but the sense of the test is reversed: this
4014 assembles the following section of code if the two strings are not
4018 File: as.info, Node: Incbin, Next: Include, Prev: If, Up: Pseudo Ops
4020 7.63 `.incbin "FILE"[,SKIP[,COUNT]]'
4021 ====================================
4023 The `incbin' directive includes FILE verbatim at the current location.
4024 You can control the search paths used with the `-I' command-line option
4025 (*note Command-Line Options: Invoking.). Quotation marks are required
4028 The SKIP argument skips a number of bytes from the start of the
4029 FILE. The COUNT argument indicates the maximum number of bytes to
4030 read. Note that the data is not aligned in any way, so it is the user's
4031 responsibility to make sure that proper alignment is provided both
4032 before and after the `incbin' directive.
4035 File: as.info, Node: Include, Next: Int, Prev: Incbin, Up: Pseudo Ops
4037 7.64 `.include "FILE"'
4038 ======================
4040 This directive provides a way to include supporting files at specified
4041 points in your source program. The code from FILE is assembled as if
4042 it followed the point of the `.include'; when the end of the included
4043 file is reached, assembly of the original file continues. You can
4044 control the search paths used with the `-I' command-line option (*note
4045 Command-Line Options: Invoking.). Quotation marks are required around
4049 File: as.info, Node: Int, Next: Internal, Prev: Include, Up: Pseudo Ops
4051 7.65 `.int EXPRESSIONS'
4052 =======================
4054 Expect zero or more EXPRESSIONS, of any section, separated by commas.
4055 For each expression, emit a number that, at run time, is the value of
4056 that expression. The byte order and bit size of the number depends on
4057 what kind of target the assembly is for.
4060 File: as.info, Node: Internal, Next: Irp, Prev: Int, Up: Pseudo Ops
4062 7.66 `.internal NAMES'
4063 ======================
4065 This is one of the ELF visibility directives. The other two are
4066 `.hidden' (*note `.hidden': Hidden.) and `.protected' (*note
4067 `.protected': Protected.).
4069 This directive overrides the named symbols default visibility (which
4070 is set by their binding: local, global or weak). The directive sets
4071 the visibility to `internal' which means that the symbols are
4072 considered to be `hidden' (i.e., not visible to other components), and
4073 that some extra, processor specific processing must also be performed
4074 upon the symbols as well.
4077 File: as.info, Node: Irp, Next: Irpc, Prev: Internal, Up: Pseudo Ops
4079 7.67 `.irp SYMBOL,VALUES'...
4080 ============================
4082 Evaluate a sequence of statements assigning different values to SYMBOL.
4083 The sequence of statements starts at the `.irp' directive, and is
4084 terminated by an `.endr' directive. For each VALUE, SYMBOL is set to
4085 VALUE, and the sequence of statements is assembled. If no VALUE is
4086 listed, the sequence of statements is assembled once, with SYMBOL set
4087 to the null string. To refer to SYMBOL within the sequence of
4088 statements, use \SYMBOL.
4090 For example, assembling
4096 is equivalent to assembling
4102 For some caveats with the spelling of SYMBOL, see also *Note Macro::.
4105 File: as.info, Node: Irpc, Next: Lcomm, Prev: Irp, Up: Pseudo Ops
4107 7.68 `.irpc SYMBOL,VALUES'...
4108 =============================
4110 Evaluate a sequence of statements assigning different values to SYMBOL.
4111 The sequence of statements starts at the `.irpc' directive, and is
4112 terminated by an `.endr' directive. For each character in VALUE,
4113 SYMBOL is set to the character, and the sequence of statements is
4114 assembled. If no VALUE is listed, the sequence of statements is
4115 assembled once, with SYMBOL set to the null string. To refer to SYMBOL
4116 within the sequence of statements, use \SYMBOL.
4118 For example, assembling
4124 is equivalent to assembling
4130 For some caveats with the spelling of SYMBOL, see also the discussion
4134 File: as.info, Node: Lcomm, Next: Lflags, Prev: Irpc, Up: Pseudo Ops
4136 7.69 `.lcomm SYMBOL , LENGTH'
4137 =============================
4139 Reserve LENGTH (an absolute expression) bytes for a local common
4140 denoted by SYMBOL. The section and value of SYMBOL are those of the
4141 new local common. The addresses are allocated in the bss section, so
4142 that at run-time the bytes start off zeroed. SYMBOL is not declared
4143 global (*note `.global': Global.), so is normally not visible to `ld'.
4145 Some targets permit a third argument to be used with `.lcomm'. This
4146 argument specifies the desired alignment of the symbol in the bss
4149 The syntax for `.lcomm' differs slightly on the HPPA. The syntax is
4150 `SYMBOL .lcomm, LENGTH'; SYMBOL is optional.
4153 File: as.info, Node: Lflags, Next: Line, Prev: Lcomm, Up: Pseudo Ops
4158 `as' accepts this directive, for compatibility with other assemblers,
4162 File: as.info, Node: Line, Next: Linkonce, Prev: Lflags, Up: Pseudo Ops
4164 7.71 `.line LINE-NUMBER'
4165 ========================
4167 Change the logical line number. LINE-NUMBER must be an absolute
4168 expression. The next line has that logical line number. Therefore any
4169 other statements on the current line (after a statement separator
4170 character) are reported as on logical line number LINE-NUMBER - 1. One
4171 day `as' will no longer support this directive: it is recognized only
4172 for compatibility with existing assembler programs.
4174 Even though this is a directive associated with the `a.out' or `b.out'
4175 object-code formats, `as' still recognizes it when producing COFF
4176 output, and treats `.line' as though it were the COFF `.ln' _if_ it is
4177 found outside a `.def'/`.endef' pair.
4179 Inside a `.def', `.line' is, instead, one of the directives used by
4180 compilers to generate auxiliary symbol information for debugging.
4183 File: as.info, Node: Linkonce, Next: List, Prev: Line, Up: Pseudo Ops
4185 7.72 `.linkonce [TYPE]'
4186 =======================
4188 Mark the current section so that the linker only includes a single copy
4189 of it. This may be used to include the same section in several
4190 different object files, but ensure that the linker will only include it
4191 once in the final output file. The `.linkonce' pseudo-op must be used
4192 for each instance of the section. Duplicate sections are detected
4193 based on the section name, so it should be unique.
4195 This directive is only supported by a few object file formats; as of
4196 this writing, the only object file format which supports it is the
4197 Portable Executable format used on Windows NT.
4199 The TYPE argument is optional. If specified, it must be one of the
4200 following strings. For example:
4202 Not all types may be supported on all object file formats.
4205 Silently discard duplicate sections. This is the default.
4208 Warn if there are duplicate sections, but still keep only one copy.
4211 Warn if any of the duplicates have different sizes.
4214 Warn if any of the duplicates do not have exactly the same
4218 File: as.info, Node: List, Next: Ln, Prev: Linkonce, Up: Pseudo Ops
4223 Control (in conjunction with the `.nolist' directive) whether or not
4224 assembly listings are generated. These two directives maintain an
4225 internal counter (which is zero initially). `.list' increments the
4226 counter, and `.nolist' decrements it. Assembly listings are generated
4227 whenever the counter is greater than zero.
4229 By default, listings are disabled. When you enable them (with the
4230 `-a' command line option; *note Command-Line Options: Invoking.), the
4231 initial value of the listing counter is one.
4234 File: as.info, Node: Ln, Next: Loc, Prev: List, Up: Pseudo Ops
4236 7.74 `.ln LINE-NUMBER'
4237 ======================
4239 `.ln' is a synonym for `.line'.
4242 File: as.info, Node: Loc, Next: Loc_mark_labels, Prev: Ln, Up: Pseudo Ops
4244 7.75 `.loc FILENO LINENO [COLUMN] [OPTIONS]'
4245 ============================================
4247 When emitting DWARF2 line number information, the `.loc' directive will
4248 add a row to the `.debug_line' line number matrix corresponding to the
4249 immediately following assembly instruction. The FILENO, LINENO, and
4250 optional COLUMN arguments will be applied to the `.debug_line' state
4251 machine before the row is added.
4253 The OPTIONS are a sequence of the following tokens in any order:
4256 This option will set the `basic_block' register in the
4257 `.debug_line' state machine to `true'.
4260 This option will set the `prologue_end' register in the
4261 `.debug_line' state machine to `true'.
4264 This option will set the `epilogue_begin' register in the
4265 `.debug_line' state machine to `true'.
4268 This option will set the `is_stmt' register in the `.debug_line'
4269 state machine to `value', which must be either 0 or 1.
4272 This directive will set the `isa' register in the `.debug_line'
4273 state machine to VALUE, which must be an unsigned integer.
4275 `discriminator VALUE'
4276 This directive will set the `discriminator' register in the
4277 `.debug_line' state machine to VALUE, which must be an unsigned
4282 File: as.info, Node: Loc_mark_labels, Next: Local, Prev: Loc, Up: Pseudo Ops
4284 7.76 `.loc_mark_labels ENABLE'
4285 ==============================
4287 When emitting DWARF2 line number information, the `.loc_mark_labels'
4288 directive makes the assembler emit an entry to the `.debug_line' line
4289 number matrix with the `basic_block' register in the state machine set
4290 whenever a code label is seen. The ENABLE argument should be either 1
4291 or 0, to enable or disable this function respectively.
4294 File: as.info, Node: Local, Next: Long, Prev: Loc_mark_labels, Up: Pseudo Ops
4299 This directive, which is available for ELF targets, marks each symbol in
4300 the comma-separated list of `names' as a local symbol so that it will
4301 not be externally visible. If the symbols do not already exist, they
4304 For targets where the `.lcomm' directive (*note Lcomm::) does not
4305 accept an alignment argument, which is the case for most ELF targets,
4306 the `.local' directive can be used in combination with `.comm' (*note
4307 Comm::) to define aligned local common data.
4310 File: as.info, Node: Long, Next: Macro, Prev: Local, Up: Pseudo Ops
4312 7.78 `.long EXPRESSIONS'
4313 ========================
4315 `.long' is the same as `.int'. *Note `.int': Int.
4318 File: as.info, Node: Macro, Next: MRI, Prev: Long, Up: Pseudo Ops
4323 The commands `.macro' and `.endm' allow you to define macros that
4324 generate assembly output. For example, this definition specifies a
4325 macro `sum' that puts a sequence of numbers into memory:
4327 .macro sum from=0, to=5
4334 With that definition, `SUM 0,5' is equivalent to this assembly input:
4344 `.macro MACNAME MACARGS ...'
4345 Begin the definition of a macro called MACNAME. If your macro
4346 definition requires arguments, specify their names after the macro
4347 name, separated by commas or spaces. You can qualify the macro
4348 argument to indicate whether all invocations must specify a
4349 non-blank value (through `:`req''), or whether it takes all of the
4350 remaining arguments (through `:`vararg''). You can supply a
4351 default value for any macro argument by following the name with
4352 `=DEFLT'. You cannot define two macros with the same MACNAME
4353 unless it has been subject to the `.purgem' directive (*note
4354 Purgem::) between the two definitions. For example, these are all
4355 valid `.macro' statements:
4358 Begin the definition of a macro called `comm', which takes no
4361 `.macro plus1 p, p1'
4363 Either statement begins the definition of a macro called
4364 `plus1', which takes two arguments; within the macro
4365 definition, write `\p' or `\p1' to evaluate the arguments.
4367 `.macro reserve_str p1=0 p2'
4368 Begin the definition of a macro called `reserve_str', with two
4369 arguments. The first argument has a default value, but not
4370 the second. After the definition is complete, you can call
4371 the macro either as `reserve_str A,B' (with `\p1' evaluating
4372 to A and `\p2' evaluating to B), or as `reserve_str ,B' (with
4373 `\p1' evaluating as the default, in this case `0', and `\p2'
4376 `.macro m p1:req, p2=0, p3:vararg'
4377 Begin the definition of a macro called `m', with at least
4378 three arguments. The first argument must always have a value
4379 specified, but not the second, which instead has a default
4380 value. The third formal will get assigned all remaining
4381 arguments specified at invocation time.
4383 When you call a macro, you can specify the argument values
4384 either by position, or by keyword. For example, `sum 9,17'
4385 is equivalent to `sum to=17, from=9'.
4388 Note that since each of the MACARGS can be an identifier exactly
4389 as any other one permitted by the target architecture, there may be
4390 occasional problems if the target hand-crafts special meanings to
4391 certain characters when they occur in a special position. For
4392 example, if the colon (`:') is generally permitted to be part of a
4393 symbol name, but the architecture specific code special-cases it
4394 when occurring as the final character of a symbol (to denote a
4395 label), then the macro parameter replacement code will have no way
4396 of knowing that and consider the whole construct (including the
4397 colon) an identifier, and check only this identifier for being the
4398 subject to parameter substitution. So for example this macro
4405 might not work as expected. Invoking `label foo' might not create
4406 a label called `foo' but instead just insert the text `\l:' into
4407 the assembler source, probably generating an error about an
4408 unrecognised identifier.
4410 Similarly problems might occur with the period character (`.')
4411 which is often allowed inside opcode names (and hence identifier
4412 names). So for example constructing a macro to build an opcode
4413 from a base name and a length specifier like this:
4415 .macro opcode base length
4419 and invoking it as `opcode store l' will not create a `store.l'
4420 instruction but instead generate some kind of error as the
4421 assembler tries to interpret the text `\base.\length'.
4423 There are several possible ways around this problem:
4425 `Insert white space'
4426 If it is possible to use white space characters then this is
4427 the simplest solution. eg:
4434 The string `\()' can be used to separate the end of a macro
4435 argument from the following text. eg:
4437 .macro opcode base length
4441 `Use the alternate macro syntax mode'
4442 In the alternative macro syntax mode the ampersand character
4443 (`&') can be used as a separator. eg:
4450 Note: this problem of correctly identifying string parameters to
4451 pseudo ops also applies to the identifiers used in `.irp' (*note
4452 Irp::) and `.irpc' (*note Irpc::) as well.
4455 Mark the end of a macro definition.
4458 Exit early from the current macro definition.
4461 `as' maintains a counter of how many macros it has executed in
4462 this pseudo-variable; you can copy that number to your output with
4463 `\@', but _only within a macro definition_.
4465 `LOCAL NAME [ , ... ]'
4466 _Warning: `LOCAL' is only available if you select "alternate macro
4467 syntax" with `--alternate' or `.altmacro'._ *Note `.altmacro':
4471 File: as.info, Node: MRI, Next: Noaltmacro, Prev: Macro, Up: Pseudo Ops
4476 If VAL is non-zero, this tells `as' to enter MRI mode. If VAL is zero,
4477 this tells `as' to exit MRI mode. This change affects code assembled
4478 until the next `.mri' directive, or until the end of the file. *Note
4482 File: as.info, Node: Noaltmacro, Next: Nolist, Prev: MRI, Up: Pseudo Ops
4487 Disable alternate macro mode. *Note Altmacro::.
4490 File: as.info, Node: Nolist, Next: Octa, Prev: Noaltmacro, Up: Pseudo Ops
4495 Control (in conjunction with the `.list' directive) whether or not
4496 assembly listings are generated. These two directives maintain an
4497 internal counter (which is zero initially). `.list' increments the
4498 counter, and `.nolist' decrements it. Assembly listings are generated
4499 whenever the counter is greater than zero.
4502 File: as.info, Node: Octa, Next: Offset, Prev: Nolist, Up: Pseudo Ops
4504 7.83 `.octa BIGNUMS'
4505 ====================
4507 This directive expects zero or more bignums, separated by commas. For
4508 each bignum, it emits a 16-byte integer.
4510 The term "octa" comes from contexts in which a "word" is two bytes;
4511 hence _octa_-word for 16 bytes.
4514 File: as.info, Node: Offset, Next: Org, Prev: Octa, Up: Pseudo Ops
4519 Set the location counter to LOC in the absolute section. LOC must be
4520 an absolute expression. This directive may be useful for defining
4521 symbols with absolute values. Do not confuse it with the `.org'
4525 File: as.info, Node: Org, Next: P2align, Prev: Offset, Up: Pseudo Ops
4527 7.85 `.org NEW-LC , FILL'
4528 =========================
4530 Advance the location counter of the current section to NEW-LC. NEW-LC
4531 is either an absolute expression or an expression with the same section
4532 as the current subsection. That is, you can't use `.org' to cross
4533 sections: if NEW-LC has the wrong section, the `.org' directive is
4534 ignored. To be compatible with former assemblers, if the section of
4535 NEW-LC is absolute, `as' issues a warning, then pretends the section of
4536 NEW-LC is the same as the current subsection.
4538 `.org' may only increase the location counter, or leave it
4539 unchanged; you cannot use `.org' to move the location counter backwards.
4541 Because `as' tries to assemble programs in one pass, NEW-LC may not
4542 be undefined. If you really detest this restriction we eagerly await a
4543 chance to share your improved assembler.
4545 Beware that the origin is relative to the start of the section, not
4546 to the start of the subsection. This is compatible with other people's
4549 When the location counter (of the current subsection) is advanced,
4550 the intervening bytes are filled with FILL which should be an absolute
4551 expression. If the comma and FILL are omitted, FILL defaults to zero.
4554 File: as.info, Node: P2align, Next: PopSection, Prev: Org, Up: Pseudo Ops
4556 7.86 `.p2align[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR'
4557 ================================================
4559 Pad the location counter (in the current subsection) to a particular
4560 storage boundary. The first expression (which must be absolute) is the
4561 number of low-order zero bits the location counter must have after
4562 advancement. For example `.p2align 3' advances the location counter
4563 until it a multiple of 8. If the location counter is already a
4564 multiple of 8, no change is needed.
4566 The second expression (also absolute) gives the fill value to be
4567 stored in the padding bytes. It (and the comma) may be omitted. If it
4568 is omitted, the padding bytes are normally zero. However, on some
4569 systems, if the section is marked as containing code and the fill value
4570 is omitted, the space is filled with no-op instructions.
4572 The third expression is also absolute, and is also optional. If it
4573 is present, it is the maximum number of bytes that should be skipped by
4574 this alignment directive. If doing the alignment would require
4575 skipping more bytes than the specified maximum, then the alignment is
4576 not done at all. You can omit the fill value (the second argument)
4577 entirely by simply using two commas after the required alignment; this
4578 can be useful if you want the alignment to be filled with no-op
4579 instructions when appropriate.
4581 The `.p2alignw' and `.p2alignl' directives are variants of the
4582 `.p2align' directive. The `.p2alignw' directive treats the fill
4583 pattern as a two byte word value. The `.p2alignl' directives treats the
4584 fill pattern as a four byte longword value. For example, `.p2alignw
4585 2,0x368d' will align to a multiple of 4. If it skips two bytes, they
4586 will be filled in with the value 0x368d (the exact placement of the
4587 bytes depends upon the endianness of the processor). If it skips 1 or
4588 3 bytes, the fill value is undefined.
4591 File: as.info, Node: PopSection, Next: Previous, Prev: P2align, Up: Pseudo Ops
4596 This is one of the ELF section stack manipulation directives. The
4597 others are `.section' (*note Section::), `.subsection' (*note
4598 SubSection::), `.pushsection' (*note PushSection::), and `.previous'
4601 This directive replaces the current section (and subsection) with
4602 the top section (and subsection) on the section stack. This section is
4603 popped off the stack.
4606 File: as.info, Node: Previous, Next: Print, Prev: PopSection, Up: Pseudo Ops
4611 This is one of the ELF section stack manipulation directives. The
4612 others are `.section' (*note Section::), `.subsection' (*note
4613 SubSection::), `.pushsection' (*note PushSection::), and `.popsection'
4614 (*note PopSection::).
4616 This directive swaps the current section (and subsection) with most
4617 recently referenced section/subsection pair prior to this one. Multiple
4618 `.previous' directives in a row will flip between two sections (and
4619 their subsections). For example:
4629 Will place 0x1234 and 0x9abc into subsection 1 and 0x5678 into
4630 subsection 2 of section A. Whilst:
4634 # Now in section A subsection 1
4638 # Now in section B subsection 0
4641 # Now in section B subsection 1
4644 # Now in section B subsection 0
4647 Will place 0x1234 into section A, 0x5678 and 0xdef0 into subsection
4648 0 of section B and 0x9abc into subsection 1 of section B.
4650 In terms of the section stack, this directive swaps the current
4651 section with the top section on the section stack.
4654 File: as.info, Node: Print, Next: Protected, Prev: Previous, Up: Pseudo Ops
4656 7.89 `.print STRING'
4657 ====================
4659 `as' will print STRING on the standard output during assembly. You
4660 must put STRING in double quotes.
4663 File: as.info, Node: Protected, Next: Psize, Prev: Print, Up: Pseudo Ops
4665 7.90 `.protected NAMES'
4666 =======================
4668 This is one of the ELF visibility directives. The other two are
4669 `.hidden' (*note Hidden::) and `.internal' (*note Internal::).
4671 This directive overrides the named symbols default visibility (which
4672 is set by their binding: local, global or weak). The directive sets
4673 the visibility to `protected' which means that any references to the
4674 symbols from within the components that defines them must be resolved
4675 to the definition in that component, even if a definition in another
4676 component would normally preempt this.
4679 File: as.info, Node: Psize, Next: Purgem, Prev: Protected, Up: Pseudo Ops
4681 7.91 `.psize LINES , COLUMNS'
4682 =============================
4684 Use this directive to declare the number of lines--and, optionally, the
4685 number of columns--to use for each page, when generating listings.
4687 If you do not use `.psize', listings use a default line-count of 60.
4688 You may omit the comma and COLUMNS specification; the default width is
4691 `as' generates formfeeds whenever the specified number of lines is
4692 exceeded (or whenever you explicitly request one, using `.eject').
4694 If you specify LINES as `0', no formfeeds are generated save those
4695 explicitly specified with `.eject'.
4698 File: as.info, Node: Purgem, Next: PushSection, Prev: Psize, Up: Pseudo Ops
4703 Undefine the macro NAME, so that later uses of the string will not be
4704 expanded. *Note Macro::.
4707 File: as.info, Node: PushSection, Next: Quad, Prev: Purgem, Up: Pseudo Ops
4709 7.93 `.pushsection NAME [, SUBSECTION] [, "FLAGS"[, @TYPE[,ARGUMENTS]]]'
4710 ========================================================================
4712 This is one of the ELF section stack manipulation directives. The
4713 others are `.section' (*note Section::), `.subsection' (*note
4714 SubSection::), `.popsection' (*note PopSection::), and `.previous'
4717 This directive pushes the current section (and subsection) onto the
4718 top of the section stack, and then replaces the current section and
4719 subsection with `name' and `subsection'. The optional `flags', `type'
4720 and `arguments' are treated the same as in the `.section' (*note
4721 Section::) directive.
4724 File: as.info, Node: Quad, Next: Reloc, Prev: PushSection, Up: Pseudo Ops
4726 7.94 `.quad BIGNUMS'
4727 ====================
4729 `.quad' expects zero or more bignums, separated by commas. For each
4730 bignum, it emits an 8-byte integer. If the bignum won't fit in 8
4731 bytes, it prints a warning message; and just takes the lowest order 8
4732 bytes of the bignum.
4734 The term "quad" comes from contexts in which a "word" is two bytes;
4735 hence _quad_-word for 8 bytes.
4738 File: as.info, Node: Reloc, Next: Rept, Prev: Quad, Up: Pseudo Ops
4740 7.95 `.reloc OFFSET, RELOC_NAME[, EXPRESSION]'
4741 ==============================================
4743 Generate a relocation at OFFSET of type RELOC_NAME with value
4744 EXPRESSION. If OFFSET is a number, the relocation is generated in the
4745 current section. If OFFSET is an expression that resolves to a symbol
4746 plus offset, the relocation is generated in the given symbol's section.
4747 EXPRESSION, if present, must resolve to a symbol plus addend or to an
4748 absolute value, but note that not all targets support an addend. e.g.
4749 ELF REL targets such as i386 store an addend in the section contents
4750 rather than in the relocation. This low level interface does not
4751 support addends stored in the section.
4754 File: as.info, Node: Rept, Next: Sbttl, Prev: Reloc, Up: Pseudo Ops
4759 Repeat the sequence of lines between the `.rept' directive and the next
4760 `.endr' directive COUNT times.
4762 For example, assembling
4768 is equivalent to assembling
4775 File: as.info, Node: Sbttl, Next: Scl, Prev: Rept, Up: Pseudo Ops
4777 7.97 `.sbttl "SUBHEADING"'
4778 ==========================
4780 Use SUBHEADING as the title (third line, immediately after the title
4781 line) when generating assembly listings.
4783 This directive affects subsequent pages, as well as the current page
4784 if it appears within ten lines of the top of a page.
4787 File: as.info, Node: Scl, Next: Section, Prev: Sbttl, Up: Pseudo Ops
4792 Set the storage-class value for a symbol. This directive may only be
4793 used inside a `.def'/`.endef' pair. Storage class may flag whether a
4794 symbol is static or external, or it may record further symbolic
4795 debugging information.
4798 File: as.info, Node: Section, Next: Set, Prev: Scl, Up: Pseudo Ops
4800 7.99 `.section NAME'
4801 ====================
4803 Use the `.section' directive to assemble the following code into a
4806 This directive is only supported for targets that actually support
4807 arbitrarily named sections; on `a.out' targets, for example, it is not
4808 accepted, even with a standard `a.out' section name.
4813 For COFF targets, the `.section' directive is used in one of the
4816 .section NAME[, "FLAGS"]
4817 .section NAME[, SUBSECTION]
4819 If the optional argument is quoted, it is taken as flags to use for
4820 the section. Each flag is a single character. The following flags are
4823 bss section (uninitialized data)
4826 section is not loaded
4835 exclude section from linking
4844 shared section (meaningful for PE targets)
4847 ignored. (For compatibility with the ELF version)
4850 section is not readable (meaningful for PE targets)
4853 single-digit power-of-two section alignment (GNU extension)
4855 If no flags are specified, the default flags depend upon the section
4856 name. If the section name is not recognized, the default will be for
4857 the section to be loaded and writable. Note the `n' and `w' flags
4858 remove attributes from the section, rather than adding them, so if they
4859 are used on their own it will be as if no flags had been specified at
4862 If the optional argument to the `.section' directive is not quoted,
4863 it is taken as a subsection number (*note Sub-Sections::).
4868 This is one of the ELF section stack manipulation directives. The
4869 others are `.subsection' (*note SubSection::), `.pushsection' (*note
4870 PushSection::), `.popsection' (*note PopSection::), and `.previous'
4873 For ELF targets, the `.section' directive is used like this:
4875 .section NAME [, "FLAGS"[, @TYPE[,FLAG_SPECIFIC_ARGUMENTS]]]
4877 The optional FLAGS argument is a quoted string which may contain any
4878 combination of the following characters:
4880 section is allocatable
4883 section is excluded from executable and shared library.
4889 section is executable
4892 section is mergeable
4895 section contains zero terminated strings
4898 section is a member of a section group
4901 section is used for thread-local-storage
4904 section is a member of the previously-current section's group, if
4907 The optional TYPE argument may contain one of the following
4910 section contains data
4913 section does not contain data (i.e., section only occupies space)
4916 section contains data which is used by things other than the
4920 section contains an array of pointers to init functions
4923 section contains an array of pointers to finish functions
4926 section contains an array of pointers to pre-init functions
4928 Many targets only support the first three section types.
4930 Note on targets where the `@' character is the start of a comment (eg
4931 ARM) then another character is used instead. For example the ARM port
4932 uses the `%' character.
4934 If FLAGS contains the `M' symbol then the TYPE argument must be
4935 specified as well as an extra argument--ENTSIZE--like this:
4937 .section NAME , "FLAGS"M, @TYPE, ENTSIZE
4939 Sections with the `M' flag but not `S' flag must contain fixed size
4940 constants, each ENTSIZE octets long. Sections with both `M' and `S'
4941 must contain zero terminated strings where each character is ENTSIZE
4942 bytes long. The linker may remove duplicates within sections with the
4943 same name, same entity size and same flags. ENTSIZE must be an
4944 absolute expression. For sections with both `M' and `S', a string
4945 which is a suffix of a larger string is considered a duplicate. Thus
4946 `"def"' will be merged with `"abcdef"'; A reference to the first
4947 `"def"' will be changed to a reference to `"abcdef"+3'.
4949 If FLAGS contains the `G' symbol then the TYPE argument must be
4950 present along with an additional field like this:
4952 .section NAME , "FLAGS"G, @TYPE, GROUPNAME[, LINKAGE]
4954 The GROUPNAME field specifies the name of the section group to which
4955 this particular section belongs. The optional linkage field can
4958 indicates that only one copy of this section should be retained
4963 Note: if both the M and G flags are present then the fields for the
4964 Merge flag should come first, like this:
4966 .section NAME , "FLAGS"MG, @TYPE, ENTSIZE, GROUPNAME[, LINKAGE]
4968 If FLAGS contains the `?' symbol then it may not also contain the
4969 `G' symbol and the GROUPNAME or LINKAGE fields should not be present.
4970 Instead, `?' says to consider the section that's current before this
4971 directive. If that section used `G', then the new section will use `G'
4972 with those same GROUPNAME and LINKAGE fields implicitly. If not, then
4973 the `?' symbol has no effect.
4975 If no flags are specified, the default flags depend upon the section
4976 name. If the section name is not recognized, the default will be for
4977 the section to have none of the above flags: it will not be allocated
4978 in memory, nor writable, nor executable. The section will contain data.
4980 For ELF targets, the assembler supports another type of `.section'
4981 directive for compatibility with the Solaris assembler:
4983 .section "NAME"[, FLAGS...]
4985 Note that the section name is quoted. There may be a sequence of
4986 comma separated flags:
4988 section is allocatable
4994 section is executable
4997 section is excluded from executable and shared library.
5000 section is used for thread local storage
5002 This directive replaces the current section and subsection. See the
5003 contents of the gas testsuite directory `gas/testsuite/gas/elf' for
5004 some examples of how this directive and the other section stack
5008 File: as.info, Node: Set, Next: Short, Prev: Section, Up: Pseudo Ops
5010 7.100 `.set SYMBOL, EXPRESSION'
5011 ===============================
5013 Set the value of SYMBOL to EXPRESSION. This changes SYMBOL's value and
5014 type to conform to EXPRESSION. If SYMBOL was flagged as external, it
5015 remains flagged (*note Symbol Attributes::).
5017 You may `.set' a symbol many times in the same assembly.
5019 If you `.set' a global symbol, the value stored in the object file
5020 is the last value stored into it.
5022 On Z80 `set' is a real instruction, use `SYMBOL defl EXPRESSION'
5026 File: as.info, Node: Short, Next: Single, Prev: Set, Up: Pseudo Ops
5028 7.101 `.short EXPRESSIONS'
5029 ==========================
5031 `.short' is normally the same as `.word'. *Note `.word': Word.
5033 In some configurations, however, `.short' and `.word' generate
5034 numbers of different lengths. *Note Machine Dependencies::.
5037 File: as.info, Node: Single, Next: Size, Prev: Short, Up: Pseudo Ops
5039 7.102 `.single FLONUMS'
5040 =======================
5042 This directive assembles zero or more flonums, separated by commas. It
5043 has the same effect as `.float'. The exact kind of floating point
5044 numbers emitted depends on how `as' is configured. *Note Machine
5048 File: as.info, Node: Size, Next: Skip, Prev: Single, Up: Pseudo Ops
5053 This directive is used to set the size associated with a symbol.
5058 For COFF targets, the `.size' directive is only permitted inside
5059 `.def'/`.endef' pairs. It is used like this:
5066 For ELF targets, the `.size' directive is used like this:
5068 .size NAME , EXPRESSION
5070 This directive sets the size associated with a symbol NAME. The
5071 size in bytes is computed from EXPRESSION which can make use of label
5072 arithmetic. This directive is typically used to set the size of
5076 File: as.info, Node: Skip, Next: Sleb128, Prev: Size, Up: Pseudo Ops
5078 7.104 `.skip SIZE , FILL'
5079 =========================
5081 This directive emits SIZE bytes, each of value FILL. Both SIZE and
5082 FILL are absolute expressions. If the comma and FILL are omitted, FILL
5083 is assumed to be zero. This is the same as `.space'.
5086 File: as.info, Node: Sleb128, Next: Space, Prev: Skip, Up: Pseudo Ops
5088 7.105 `.sleb128 EXPRESSIONS'
5089 ============================
5091 SLEB128 stands for "signed little endian base 128." This is a compact,
5092 variable length representation of numbers used by the DWARF symbolic
5093 debugging format. *Note `.uleb128': Uleb128.
5096 File: as.info, Node: Space, Next: Stab, Prev: Sleb128, Up: Pseudo Ops
5098 7.106 `.space SIZE , FILL'
5099 ==========================
5101 This directive emits SIZE bytes, each of value FILL. Both SIZE and
5102 FILL are absolute expressions. If the comma and FILL are omitted, FILL
5103 is assumed to be zero. This is the same as `.skip'.
5105 _Warning:_ `.space' has a completely different meaning for HPPA
5106 targets; use `.block' as a substitute. See `HP9000 Series 800
5107 Assembly Language Reference Manual' (HP 92432-90001) for the
5108 meaning of the `.space' directive. *Note HPPA Assembler
5109 Directives: HPPA Directives, for a summary.
5112 File: as.info, Node: Stab, Next: String, Prev: Space, Up: Pseudo Ops
5114 7.107 `.stabd, .stabn, .stabs'
5115 ==============================
5117 There are three directives that begin `.stab'. All emit symbols (*note
5118 Symbols::), for use by symbolic debuggers. The symbols are not entered
5119 in the `as' hash table: they cannot be referenced elsewhere in the
5120 source file. Up to five fields are required:
5123 This is the symbol's name. It may contain any character except
5124 `\000', so is more general than ordinary symbol names. Some
5125 debuggers used to code arbitrarily complex structures into symbol
5126 names using this field.
5129 An absolute expression. The symbol's type is set to the low 8
5130 bits of this expression. Any bit pattern is permitted, but `ld'
5131 and debuggers choke on silly bit patterns.
5134 An absolute expression. The symbol's "other" attribute is set to
5135 the low 8 bits of this expression.
5138 An absolute expression. The symbol's descriptor is set to the low
5139 16 bits of this expression.
5142 An absolute expression which becomes the symbol's value.
5144 If a warning is detected while reading a `.stabd', `.stabn', or
5145 `.stabs' statement, the symbol has probably already been created; you
5146 get a half-formed symbol in your object file. This is compatible with
5149 `.stabd TYPE , OTHER , DESC'
5150 The "name" of the symbol generated is not even an empty string.
5151 It is a null pointer, for compatibility. Older assemblers used a
5152 null pointer so they didn't waste space in object files with empty
5155 The symbol's value is set to the location counter, relocatably.
5156 When your program is linked, the value of this symbol is the
5157 address of the location counter when the `.stabd' was assembled.
5159 `.stabn TYPE , OTHER , DESC , VALUE'
5160 The name of the symbol is set to the empty string `""'.
5162 `.stabs STRING , TYPE , OTHER , DESC , VALUE'
5163 All five fields are specified.
5166 File: as.info, Node: String, Next: Struct, Prev: Stab, Up: Pseudo Ops
5168 7.108 `.string' "STR", `.string8' "STR", `.string16'
5169 ====================================================
5171 "STR", `.string32' "STR", `.string64' "STR"
5173 Copy the characters in STR to the object file. You may specify more
5174 than one string to copy, separated by commas. Unless otherwise
5175 specified for a particular machine, the assembler marks the end of each
5176 string with a 0 byte. You can use any of the escape sequences
5177 described in *Note Strings: Strings.
5179 The variants `string16', `string32' and `string64' differ from the
5180 `string' pseudo opcode in that each 8-bit character from STR is copied
5181 and expanded to 16, 32 or 64 bits respectively. The expanded characters
5182 are stored in target endianness byte order.
5187 .string "B\0\0\0Y\0\0\0E\0\0\0" /* On little endian targets. */
5188 .string "\0\0\0B\0\0\0Y\0\0\0E" /* On big endian targets. */
5191 File: as.info, Node: Struct, Next: SubSection, Prev: String, Up: Pseudo Ops
5193 7.109 `.struct EXPRESSION'
5194 ==========================
5196 Switch to the absolute section, and set the section offset to
5197 EXPRESSION, which must be an absolute expression. You might use this
5205 This would define the symbol `field1' to have the value 0, the symbol
5206 `field2' to have the value 4, and the symbol `field3' to have the value
5207 8. Assembly would be left in the absolute section, and you would need
5208 to use a `.section' directive of some sort to change to some other
5209 section before further assembly.
5212 File: as.info, Node: SubSection, Next: Symver, Prev: Struct, Up: Pseudo Ops
5214 7.110 `.subsection NAME'
5215 ========================
5217 This is one of the ELF section stack manipulation directives. The
5218 others are `.section' (*note Section::), `.pushsection' (*note
5219 PushSection::), `.popsection' (*note PopSection::), and `.previous'
5222 This directive replaces the current subsection with `name'. The
5223 current section is not changed. The replaced subsection is put onto
5224 the section stack in place of the then current top of stack subsection.
5227 File: as.info, Node: Symver, Next: Tag, Prev: SubSection, Up: Pseudo Ops
5232 Use the `.symver' directive to bind symbols to specific version nodes
5233 within a source file. This is only supported on ELF platforms, and is
5234 typically used when assembling files to be linked into a shared library.
5235 There are cases where it may make sense to use this in objects to be
5236 bound into an application itself so as to override a versioned symbol
5237 from a shared library.
5239 For ELF targets, the `.symver' directive can be used like this:
5240 .symver NAME, NAME2@NODENAME
5241 If the symbol NAME is defined within the file being assembled, the
5242 `.symver' directive effectively creates a symbol alias with the name
5243 NAME2@NODENAME, and in fact the main reason that we just don't try and
5244 create a regular alias is that the @ character isn't permitted in
5245 symbol names. The NAME2 part of the name is the actual name of the
5246 symbol by which it will be externally referenced. The name NAME itself
5247 is merely a name of convenience that is used so that it is possible to
5248 have definitions for multiple versions of a function within a single
5249 source file, and so that the compiler can unambiguously know which
5250 version of a function is being mentioned. The NODENAME portion of the
5251 alias should be the name of a node specified in the version script
5252 supplied to the linker when building a shared library. If you are
5253 attempting to override a versioned symbol from a shared library, then
5254 NODENAME should correspond to the nodename of the symbol you are trying
5257 If the symbol NAME is not defined within the file being assembled,
5258 all references to NAME will be changed to NAME2@NODENAME. If no
5259 reference to NAME is made, NAME2@NODENAME will be removed from the
5262 Another usage of the `.symver' directive is:
5263 .symver NAME, NAME2@@NODENAME
5264 In this case, the symbol NAME must exist and be defined within the
5265 file being assembled. It is similar to NAME2@NODENAME. The difference
5266 is NAME2@@NODENAME will also be used to resolve references to NAME2 by
5269 The third usage of the `.symver' directive is:
5270 .symver NAME, NAME2@@@NODENAME
5271 When NAME is not defined within the file being assembled, it is
5272 treated as NAME2@NODENAME. When NAME is defined within the file being
5273 assembled, the symbol name, NAME, will be changed to NAME2@@NODENAME.
5276 File: as.info, Node: Tag, Next: Text, Prev: Symver, Up: Pseudo Ops
5278 7.112 `.tag STRUCTNAME'
5279 =======================
5281 This directive is generated by compilers to include auxiliary debugging
5282 information in the symbol table. It is only permitted inside
5283 `.def'/`.endef' pairs. Tags are used to link structure definitions in
5284 the symbol table with instances of those structures.
5287 File: as.info, Node: Text, Next: Title, Prev: Tag, Up: Pseudo Ops
5289 7.113 `.text SUBSECTION'
5290 ========================
5292 Tells `as' to assemble the following statements onto the end of the
5293 text subsection numbered SUBSECTION, which is an absolute expression.
5294 If SUBSECTION is omitted, subsection number zero is used.
5297 File: as.info, Node: Title, Next: Type, Prev: Text, Up: Pseudo Ops
5299 7.114 `.title "HEADING"'
5300 ========================
5302 Use HEADING as the title (second line, immediately after the source
5303 file name and pagenumber) when generating assembly listings.
5305 This directive affects subsequent pages, as well as the current page
5306 if it appears within ten lines of the top of a page.
5309 File: as.info, Node: Type, Next: Uleb128, Prev: Title, Up: Pseudo Ops
5314 This directive is used to set the type of a symbol.
5319 For COFF targets, this directive is permitted only within
5320 `.def'/`.endef' pairs. It is used like this:
5324 This records the integer INT as the type attribute of a symbol table
5330 For ELF targets, the `.type' directive is used like this:
5332 .type NAME , TYPE DESCRIPTION
5334 This sets the type of symbol NAME to be either a function symbol or
5335 an object symbol. There are five different syntaxes supported for the
5336 TYPE DESCRIPTION field, in order to provide compatibility with various
5339 Because some of the characters used in these syntaxes (such as `@'
5340 and `#') are comment characters for some architectures, some of the
5341 syntaxes below do not work on all architectures. The first variant
5342 will be accepted by the GNU assembler on all architectures so that
5343 variant should be used for maximum portability, if you do not need to
5344 assemble your code with other assemblers.
5346 The syntaxes supported are:
5348 .type <name> STT_<TYPE_IN_UPPER_CASE>
5349 .type <name>,#<type>
5350 .type <name>,@<type>
5351 .type <name>,%<type>
5352 .type <name>,"<type>"
5354 The types supported are:
5358 Mark the symbol as being a function name.
5361 `gnu_indirect_function'
5362 Mark the symbol as an indirect function when evaluated during reloc
5363 processing. (This is only supported on assemblers targeting GNU
5368 Mark the symbol as being a data object.
5372 Mark the symbol as being a thead-local data object.
5376 Mark the symbol as being a common data object.
5380 Does not mark the symbol in any way. It is supported just for
5384 Marks the symbol as being a globally unique data object. The
5385 dynamic linker will make sure that in the entire process there is
5386 just one symbol with this name and type in use. (This is only
5387 supported on assemblers targeting GNU systems).
5390 Note: Some targets support extra types in addition to those listed
5394 File: as.info, Node: Uleb128, Next: Val, Prev: Type, Up: Pseudo Ops
5396 7.116 `.uleb128 EXPRESSIONS'
5397 ============================
5399 ULEB128 stands for "unsigned little endian base 128." This is a
5400 compact, variable length representation of numbers used by the DWARF
5401 symbolic debugging format. *Note `.sleb128': Sleb128.
5404 File: as.info, Node: Val, Next: Version, Prev: Uleb128, Up: Pseudo Ops
5409 This directive, permitted only within `.def'/`.endef' pairs, records
5410 the address ADDR as the value attribute of a symbol table entry.
5413 File: as.info, Node: Version, Next: VTableEntry, Prev: Val, Up: Pseudo Ops
5415 7.118 `.version "STRING"'
5416 =========================
5418 This directive creates a `.note' section and places into it an ELF
5419 formatted note of type NT_VERSION. The note's name is set to `string'.
5422 File: as.info, Node: VTableEntry, Next: VTableInherit, Prev: Version, Up: Pseudo Ops
5424 7.119 `.vtable_entry TABLE, OFFSET'
5425 ===================================
5427 This directive finds or creates a symbol `table' and creates a
5428 `VTABLE_ENTRY' relocation for it with an addend of `offset'.
5431 File: as.info, Node: VTableInherit, Next: Warning, Prev: VTableEntry, Up: Pseudo Ops
5433 7.120 `.vtable_inherit CHILD, PARENT'
5434 =====================================
5436 This directive finds the symbol `child' and finds or creates the symbol
5437 `parent' and then creates a `VTABLE_INHERIT' relocation for the parent
5438 whose addend is the value of the child symbol. As a special case the
5439 parent name of `0' is treated as referring to the `*ABS*' section.
5442 File: as.info, Node: Warning, Next: Weak, Prev: VTableInherit, Up: Pseudo Ops
5444 7.121 `.warning "STRING"'
5445 =========================
5447 Similar to the directive `.error' (*note `.error "STRING"': Error.),
5448 but just emits a warning.
5451 File: as.info, Node: Weak, Next: Weakref, Prev: Warning, Up: Pseudo Ops
5456 This directive sets the weak attribute on the comma separated list of
5457 symbol `names'. If the symbols do not already exist, they will be
5460 On COFF targets other than PE, weak symbols are a GNU extension.
5461 This directive sets the weak attribute on the comma separated list of
5462 symbol `names'. If the symbols do not already exist, they will be
5465 On the PE target, weak symbols are supported natively as weak
5466 aliases. When a weak symbol is created that is not an alias, GAS
5467 creates an alternate symbol to hold the default value.
5470 File: as.info, Node: Weakref, Next: Word, Prev: Weak, Up: Pseudo Ops
5472 7.123 `.weakref ALIAS, TARGET'
5473 ==============================
5475 This directive creates an alias to the target symbol that enables the
5476 symbol to be referenced with weak-symbol semantics, but without
5477 actually making it weak. If direct references or definitions of the
5478 symbol are present, then the symbol will not be weak, but if all
5479 references to it are through weak references, the symbol will be marked
5480 as weak in the symbol table.
5482 The effect is equivalent to moving all references to the alias to a
5483 separate assembly source file, renaming the alias to the symbol in it,
5484 declaring the symbol as weak there, and running a reloadable link to
5485 merge the object files resulting from the assembly of the new source
5486 file and the old source file that had the references to the alias
5489 The alias itself never makes to the symbol table, and is entirely
5490 handled within the assembler.
5493 File: as.info, Node: Word, Next: Deprecated, Prev: Weakref, Up: Pseudo Ops
5495 7.124 `.word EXPRESSIONS'
5496 =========================
5498 This directive expects zero or more EXPRESSIONS, of any section,
5499 separated by commas.
5501 The size of the number emitted, and its byte order, depend on what
5502 target computer the assembly is for.
5504 _Warning: Special Treatment to support Compilers_
5506 Machines with a 32-bit address space, but that do less than 32-bit
5507 addressing, require the following special treatment. If the machine of
5508 interest to you does 32-bit addressing (or doesn't require it; *note
5509 Machine Dependencies::), you can ignore this issue.
5511 In order to assemble compiler output into something that works, `as'
5512 occasionally does strange things to `.word' directives. Directives of
5513 the form `.word sym1-sym2' are often emitted by compilers as part of
5514 jump tables. Therefore, when `as' assembles a directive of the form
5515 `.word sym1-sym2', and the difference between `sym1' and `sym2' does
5516 not fit in 16 bits, `as' creates a "secondary jump table", immediately
5517 before the next label. This secondary jump table is preceded by a
5518 short-jump to the first byte after the secondary table. This
5519 short-jump prevents the flow of control from accidentally falling into
5520 the new table. Inside the table is a long-jump to `sym2'. The
5521 original `.word' contains `sym1' minus the address of the long-jump to
5524 If there were several occurrences of `.word sym1-sym2' before the
5525 secondary jump table, all of them are adjusted. If there was a `.word
5526 sym3-sym4', that also did not fit in sixteen bits, a long-jump to
5527 `sym4' is included in the secondary jump table, and the `.word'
5528 directives are adjusted to contain `sym3' minus the address of the
5529 long-jump to `sym4'; and so on, for as many entries in the original
5530 jump table as necessary.
5533 File: as.info, Node: Deprecated, Prev: Word, Up: Pseudo Ops
5535 7.125 Deprecated Directives
5536 ===========================
5538 One day these directives won't work. They are included for
5539 compatibility with older assemblers.
5545 File: as.info, Node: Object Attributes, Next: Machine Dependencies, Prev: Pseudo Ops, Up: Top
5550 `as' assembles source files written for a specific architecture into
5551 object files for that architecture. But not all object files are alike.
5552 Many architectures support incompatible variations. For instance,
5553 floating point arguments might be passed in floating point registers if
5554 the object file requires hardware floating point support--or floating
5555 point arguments might be passed in integer registers if the object file
5556 supports processors with no hardware floating point unit. Or, if two
5557 objects are built for different generations of the same architecture,
5558 the combination may require the newer generation at run-time.
5560 This information is useful during and after linking. At link time,
5561 `ld' can warn about incompatible object files. After link time, tools
5562 like `gdb' can use it to process the linked file correctly.
5564 Compatibility information is recorded as a series of object
5565 attributes. Each attribute has a "vendor", "tag", and "value". The
5566 vendor is a string, and indicates who sets the meaning of the tag. The
5567 tag is an integer, and indicates what property the attribute describes.
5568 The value may be a string or an integer, and indicates how the
5569 property affects this object. Missing attributes are the same as
5570 attributes with a zero value or empty string value.
5572 Object attributes were developed as part of the ABI for the ARM
5573 Architecture. The file format is documented in `ELF for the ARM
5578 * GNU Object Attributes:: GNU Object Attributes
5579 * Defining New Object Attributes:: Defining New Object Attributes
5582 File: as.info, Node: GNU Object Attributes, Next: Defining New Object Attributes, Up: Object Attributes
5584 8.1 GNU Object Attributes
5585 =========================
5587 The `.gnu_attribute' directive records an object attribute with vendor
5590 Except for `Tag_compatibility', which has both an integer and a
5591 string for its value, GNU attributes have a string value if the tag
5592 number is odd and an integer value if the tag number is even. The
5593 second bit (`TAG & 2' is set for architecture-independent attributes
5594 and clear for architecture-dependent ones.
5596 8.1.1 Common GNU attributes
5597 ---------------------------
5599 These attributes are valid on all architectures.
5601 Tag_compatibility (32)
5602 The compatibility attribute takes an integer flag value and a
5603 vendor name. If the flag value is 0, the file is compatible with
5604 other toolchains. If it is 1, then the file is only compatible
5605 with the named toolchain. If it is greater than 1, the file can
5606 only be processed by other toolchains under some private
5607 arrangement indicated by the flag value and the vendor name.
5609 8.1.2 MIPS Attributes
5610 ---------------------
5612 Tag_GNU_MIPS_ABI_FP (4)
5613 The floating-point ABI used by this object file. The value will
5616 * 0 for files not affected by the floating-point ABI.
5618 * 1 for files using the hardware floating-point ABI with a
5619 standard double-precision FPU.
5621 * 2 for files using the hardware floating-point ABI with a
5622 single-precision FPU.
5624 * 3 for files using the software floating-point ABI.
5626 * 4 for files using the deprecated hardware floating-point ABI
5627 which used 64-bit floating-point registers, 32-bit
5628 general-purpose registers and increased the number of
5629 callee-saved floating-point registers.
5631 * 5 for files using the hardware floating-point ABI with a
5632 double-precision FPU with either 32-bit or 64-bit
5633 floating-point registers and 32-bit general-purpose registers.
5635 * 6 for files using the hardware floating-point ABI with 64-bit
5636 floating-point registers and 32-bit general-purpose registers.
5638 * 7 for files using the hardware floating-point ABI with 64-bit
5639 floating-point registers, 32-bit general-purpose registers
5640 and a rule that forbids the direct use of odd-numbered
5641 single-precision floating-point registers.
5643 8.1.3 PowerPC Attributes
5644 ------------------------
5646 Tag_GNU_Power_ABI_FP (4)
5647 The floating-point ABI used by this object file. The value will
5650 * 0 for files not affected by the floating-point ABI.
5652 * 1 for files using double-precision hardware floating-point
5655 * 2 for files using the software floating-point ABI.
5657 * 3 for files using single-precision hardware floating-point
5660 Tag_GNU_Power_ABI_Vector (8)
5661 The vector ABI used by this object file. The value will be:
5663 * 0 for files not affected by the vector ABI.
5665 * 1 for files using general purpose registers to pass vectors.
5667 * 2 for files using AltiVec registers to pass vectors.
5669 * 3 for files using SPE registers to pass vectors.
5672 File: as.info, Node: Defining New Object Attributes, Prev: GNU Object Attributes, Up: Object Attributes
5674 8.2 Defining New Object Attributes
5675 ==================================
5677 If you want to define a new GNU object attribute, here are the places
5678 you will need to modify. New attributes should be discussed on the
5679 `binutils' mailing list.
5681 * This manual, which is the official register of attributes.
5683 * The header for your architecture `include/elf', to define the tag.
5685 * The `bfd' support file for your architecture, to merge the
5686 attribute and issue any appropriate link warnings.
5688 * Test cases in `ld/testsuite' for merging and link warnings.
5690 * `binutils/readelf.c' to display your attribute.
5692 * GCC, if you want the compiler to mark the attribute automatically.
5695 File: as.info, Node: Machine Dependencies, Next: Reporting Bugs, Prev: Object Attributes, Up: Top
5697 9 Machine Dependent Features
5698 ****************************
5700 The machine instruction sets are (almost by definition) different on
5701 each machine where `as' runs. Floating point representations vary as
5702 well, and `as' often supports a few additional directives or
5703 command-line options for compatibility with other assemblers on a
5704 particular platform. Finally, some versions of `as' support special
5705 pseudo-instructions for branch optimization.
5707 This chapter discusses most of these differences, though it does not
5708 include details on any machine's instruction set. For details on that
5709 subject, see the hardware manufacturer's manual.
5714 * AArch64-Dependent:: AArch64 Dependent Features
5716 * Alpha-Dependent:: Alpha Dependent Features
5718 * ARC-Dependent:: ARC Dependent Features
5720 * ARM-Dependent:: ARM Dependent Features
5722 * AVR-Dependent:: AVR Dependent Features
5724 * Blackfin-Dependent:: Blackfin Dependent Features
5726 * CR16-Dependent:: CR16 Dependent Features
5728 * CRIS-Dependent:: CRIS Dependent Features
5730 * D10V-Dependent:: D10V Dependent Features
5732 * D30V-Dependent:: D30V Dependent Features
5734 * Epiphany-Dependent:: EPIPHANY Dependent Features
5736 * H8/300-Dependent:: Renesas H8/300 Dependent Features
5738 * HPPA-Dependent:: HPPA Dependent Features
5740 * ESA/390-Dependent:: IBM ESA/390 Dependent Features
5742 * i386-Dependent:: Intel 80386 and AMD x86-64 Dependent Features
5744 * i860-Dependent:: Intel 80860 Dependent Features
5746 * i960-Dependent:: Intel 80960 Dependent Features
5748 * IA-64-Dependent:: Intel IA-64 Dependent Features
5750 * IP2K-Dependent:: IP2K Dependent Features
5752 * LM32-Dependent:: LM32 Dependent Features
5754 * M32C-Dependent:: M32C Dependent Features
5756 * M32R-Dependent:: M32R Dependent Features
5758 * M68K-Dependent:: M680x0 Dependent Features
5760 * M68HC11-Dependent:: M68HC11 and 68HC12 Dependent Features
5762 * Meta-Dependent :: Meta Dependent Features
5764 * MicroBlaze-Dependent:: MICROBLAZE Dependent Features
5766 * MIPS-Dependent:: MIPS Dependent Features
5768 * MMIX-Dependent:: MMIX Dependent Features
5770 * MSP430-Dependent:: MSP430 Dependent Features
5772 * NDS32-Dependent:: Andes NDS32 Dependent Features
5774 * NiosII-Dependent:: Altera Nios II Dependent Features
5776 * NS32K-Dependent:: NS32K Dependent Features
5778 * SH-Dependent:: Renesas / SuperH SH Dependent Features
5779 * SH64-Dependent:: SuperH SH64 Dependent Features
5781 * PDP-11-Dependent:: PDP-11 Dependent Features
5783 * PJ-Dependent:: picoJava Dependent Features
5785 * PPC-Dependent:: PowerPC Dependent Features
5787 * RL78-Dependent:: RL78 Dependent Features
5789 * RX-Dependent:: RX Dependent Features
5791 * S/390-Dependent:: IBM S/390 Dependent Features
5793 * SCORE-Dependent:: SCORE Dependent Features
5795 * Sparc-Dependent:: SPARC Dependent Features
5797 * TIC54X-Dependent:: TI TMS320C54x Dependent Features
5799 * TIC6X-Dependent :: TI TMS320C6x Dependent Features
5801 * TILE-Gx-Dependent :: Tilera TILE-Gx Dependent Features
5803 * TILEPro-Dependent :: Tilera TILEPro Dependent Features
5805 * V850-Dependent:: V850 Dependent Features
5807 * XGATE-Dependent:: XGATE Features
5809 * XSTORMY16-Dependent:: XStormy16 Dependent Features
5811 * Xtensa-Dependent:: Xtensa Dependent Features
5813 * Z80-Dependent:: Z80 Dependent Features
5815 * Z8000-Dependent:: Z8000 Dependent Features
5817 * Vax-Dependent:: VAX Dependent Features
5820 File: as.info, Node: AArch64-Dependent, Next: Alpha-Dependent, Up: Machine Dependencies
5822 9.1 AArch64 Dependent Features
5823 ==============================
5827 * AArch64 Options:: Options
5828 * AArch64 Extensions:: Extensions
5829 * AArch64 Syntax:: Syntax
5830 * AArch64 Floating Point:: Floating Point
5831 * AArch64 Directives:: AArch64 Machine Directives
5832 * AArch64 Opcodes:: Opcodes
5833 * AArch64 Mapping Symbols:: Mapping Symbols
5836 File: as.info, Node: AArch64 Options, Next: AArch64 Extensions, Up: AArch64-Dependent
5842 This option specifies that the output generated by the assembler
5843 should be marked as being encoded for a big-endian processor.
5846 This option specifies that the output generated by the assembler
5847 should be marked as being encoded for a little-endian processor.
5850 Specify which ABI the source code uses. The recognized arguments
5851 are: `ilp32' and `lp64', which decides the generated object file
5852 in ELF32 and ELF64 format respectively. The default is `lp64'.
5854 `-mcpu=PROCESSOR[+EXTENSION...]'
5855 This option specifies the target processor. The assembler will
5856 issue an error message if an attempt is made to assemble an
5857 instruction which will not execute on the target processor. The
5858 following processor names are recognized: `cortex-a53',
5859 `cortex-a57', `xgene1', and `xgene2'. The special name `all' may
5860 be used to allow the assembler to accept instructions valid for
5861 any supported processor, including all optional extensions.
5863 In addition to the basic instruction set, the assembler can be
5864 told to accept, or restrict, various extension mnemonics that
5865 extend the processor. *Note AArch64 Extensions::.
5867 If some implementations of a particular processor can have an
5868 extension, then then those extensions are automatically enabled.
5869 Consequently, you will not normally have to specify any additional
5872 `-march=ARCHITECTURE[+EXTENSION...]'
5873 This option specifies the target architecture. The assembler will
5874 issue an error message if an attempt is made to assemble an
5875 instruction which will not execute on the target architecture. The
5876 only value for ARCHITECTURE is `armv8-a'.
5878 If both `-mcpu' and `-march' are specified, the assembler will use
5879 the setting for `-mcpu'. If neither are specified, the assembler
5880 will default to `-mcpu=all'.
5882 The architecture option can be extended with the same instruction
5883 set extension options as the `-mcpu' option. Unlike `-mcpu',
5884 extensions are not always enabled by default, *Note AArch64
5888 This option enables verbose error messages for AArch64 gas. This
5889 option is enabled by default.
5891 `-mno-verbose-error'
5892 This option disables verbose error messages in AArch64 gas.
5896 File: as.info, Node: AArch64 Extensions, Next: AArch64 Syntax, Prev: AArch64 Options, Up: AArch64-Dependent
5898 9.1.2 Architecture Extensions
5899 -----------------------------
5901 The table below lists the permitted architecture extensions that are
5902 supported by the assembler and the conditions under which they are
5903 automatically enabled.
5905 Multiple extensions may be specified, separated by a `+'. Extension
5906 mnemonics may also be removed from those the assembler accepts. This
5907 is done by prepending `no' to the option that adds the extension.
5908 Extensions that are removed must be listed after all extensions that
5911 Enabling an extension that requires other extensions will
5912 automatically cause those extensions to be enabled. Similarly,
5913 disabling an extension that is required by other extensions will
5914 automatically cause those extensions to be disabled.
5916 Extension Minimum Enabled by Description
5917 Architecture default
5918 ----------------------------------------------------------------------------
5919 `crc' ARMv8-A No Enable CRC instructions.
5920 `crypto' ARMv8-A No Enable cryptographic extensions. This
5921 implies `fp' and `simd'.
5922 `fp' ARMv8-A ARMv8-A or Enable floating-point extensions.
5924 `simd' ARMv8-A ARMv8-A or Enable Advanced SIMD extensions. This
5928 File: as.info, Node: AArch64 Syntax, Next: AArch64 Floating Point, Prev: AArch64 Extensions, Up: AArch64-Dependent
5935 * AArch64-Chars:: Special Characters
5936 * AArch64-Regs:: Register Names
5937 * AArch64-Relocations:: Relocations
5940 File: as.info, Node: AArch64-Chars, Next: AArch64-Regs, Up: AArch64 Syntax
5942 9.1.3.1 Special Characters
5943 ..........................
5945 The presence of a `//' on a line indicates the start of a comment that
5946 extends to the end of the current line. If a `#' appears as the first
5947 character of a line, the whole line is treated as a comment.
5949 The `;' character can be used instead of a newline to separate
5952 The `#' can be optionally used to indicate immediate operands.
5955 File: as.info, Node: AArch64-Regs, Next: AArch64-Relocations, Prev: AArch64-Chars, Up: AArch64 Syntax
5957 9.1.3.2 Register Names
5958 ......................
5960 Please refer to the section `4.4 Register Names' of `ARMv8 Instruction
5961 Set Overview', which is available at `http://infocenter.arm.com'.
5964 File: as.info, Node: AArch64-Relocations, Prev: AArch64-Regs, Up: AArch64 Syntax
5969 Relocations for `MOVZ' and `MOVK' instructions can be generated by
5970 prefixing the label with `#:abs_g2:' etc. For example to load the
5971 48-bit absolute address of FOO into x0:
5973 movz x0, #:abs_g2:foo // bits 32-47, overflow check
5974 movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
5975 movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
5977 Relocations for `ADRP', and `ADD', `LDR' or `STR' instructions can
5978 be generated by prefixing the label with `:pg_hi21:' and `#:lo12:'
5981 For example to use 33-bit (+/-4GB) pc-relative addressing to load
5982 the address of FOO into x0:
5984 adrp x0, :pg_hi21:foo
5985 add x0, x0, #:lo12:foo
5987 Or to load the value of FOO into x0:
5989 adrp x0, :pg_hi21:foo
5990 ldr x0, [x0, #:lo12:foo]
5992 Note that `:pg_hi21:' is optional.
5998 adrp x0, :pg_hi21:foo
6001 File: as.info, Node: AArch64 Floating Point, Next: AArch64 Directives, Prev: AArch64 Syntax, Up: AArch64-Dependent
6003 9.1.4 Floating Point
6004 --------------------
6006 The AArch64 architecture uses IEEE floating-point numbers.
6009 File: as.info, Node: AArch64 Directives, Next: AArch64 Opcodes, Prev: AArch64 Floating Point, Up: AArch64-Dependent
6011 9.1.5 AArch64 Machine Directives
6012 --------------------------------
6015 This directive switches to the `.bss' section.
6018 This directive causes the current contents of the literal pool to
6019 be dumped into the current section (which is assumed to be the
6020 .text section) at the current location (aligned to a word
6021 boundary). GAS maintains a separate literal pool for each section
6022 and each sub-section. The `.ltorg' directive will only affect the
6023 literal pool of the current section and sub-section. At the end
6024 of assembly all remaining, un-empty literal pools will
6025 automatically be dumped.
6027 Note - older versions of GAS would dump the current literal pool
6028 any time a section change occurred. This is no longer done, since
6029 it prevents accurate control of the placement of literal pools.
6032 This is a synonym for .ltorg.
6034 `NAME .req REGISTER NAME'
6035 This creates an alias for REGISTER NAME called NAME. For example:
6040 This undefines a register alias which was previously defined using
6041 the `req' directive. For example:
6046 An error occurs if the name is undefined. Note - this pseudo op
6047 can be used to delete builtin in register name aliases (eg 'w0').
6048 This should only be done if it is really necessary.
6052 File: as.info, Node: AArch64 Opcodes, Next: AArch64 Mapping Symbols, Prev: AArch64 Directives, Up: AArch64-Dependent
6057 GAS implements all the standard AArch64 opcodes. It also implements
6058 several pseudo opcodes, including several synthetic load instructions.
6061 ldr <register> , =<expression>
6063 The constant expression will be placed into the nearest literal
6064 pool (if it not already there) and a PC-relative LDR instruction
6068 For more information on the AArch64 instruction set and assembly
6069 language notation, see `ARMv8 Instruction Set Overview' available at
6070 `http://infocenter.arm.com'.
6073 File: as.info, Node: AArch64 Mapping Symbols, Prev: AArch64 Opcodes, Up: AArch64-Dependent
6075 9.1.7 Mapping Symbols
6076 ---------------------
6078 The AArch64 ELF specification requires that special symbols be inserted
6079 into object files to mark certain features:
6082 At the start of a region of code containing AArch64 instructions.
6085 At the start of a region of data.
6089 File: as.info, Node: Alpha-Dependent, Next: ARC-Dependent, Prev: AArch64-Dependent, Up: Machine Dependencies
6091 9.2 Alpha Dependent Features
6092 ============================
6096 * Alpha Notes:: Notes
6097 * Alpha Options:: Options
6098 * Alpha Syntax:: Syntax
6099 * Alpha Floating Point:: Floating Point
6100 * Alpha Directives:: Alpha Machine Directives
6101 * Alpha Opcodes:: Opcodes
6104 File: as.info, Node: Alpha Notes, Next: Alpha Options, Up: Alpha-Dependent
6109 The documentation here is primarily for the ELF object format. `as'
6110 also supports the ECOFF and EVAX formats, but features specific to
6111 these formats are not yet documented.
6114 File: as.info, Node: Alpha Options, Next: Alpha Syntax, Prev: Alpha Notes, Up: Alpha-Dependent
6120 This option specifies the target processor. If an attempt is made
6121 to assemble an instruction which will not execute on the target
6122 processor, the assembler may either expand the instruction as a
6123 macro or issue an error message. This option is equivalent to the
6126 The following processor names are recognized: `21064', `21064a',
6127 `21066', `21068', `21164', `21164a', `21164pc', `21264', `21264a',
6128 `21264b', `ev4', `ev5', `lca45', `ev5', `ev56', `pca56', `ev6',
6129 `ev67', `ev68'. The special name `all' may be used to allow the
6130 assembler to accept instructions valid for any Alpha processor.
6132 In order to support existing practice in OSF/1 with respect to
6133 `.arch', and existing practice within `MILO' (the Linux ARC
6134 bootloader), the numbered processor names (e.g. 21064) enable the
6135 processor-specific PALcode instructions, while the
6136 "electro-vlasic" names (e.g. `ev4') do not.
6140 Enables or disables the generation of `.mdebug' encapsulation for
6141 stabs directives and procedure descriptors. The default is to
6142 automatically enable `.mdebug' when the first stabs directive is
6146 This option forces all relocations to be put into the object file,
6147 instead of saving space and resolving some relocations at assembly
6148 time. Note that this option does not propagate all symbol
6149 arithmetic into the object file, because not all symbol arithmetic
6150 can be represented. However, the option can still be useful in
6151 specific applications.
6155 Enables or disables the optimization of procedure calls, both at
6156 assemblage and at link time. These options are only available for
6157 VMS targets and `-replace' is the default. See section 1.4.1 of
6158 the OpenVMS Linker Utility Manual.
6161 This option is used when the compiler generates debug information.
6162 When `gcc' is using `mips-tfile' to generate debug information
6163 for ECOFF, local labels must be passed through to the object file.
6164 Otherwise this option has no effect.
6167 A local common symbol larger than SIZE is placed in `.bss', while
6168 smaller symbols are placed in `.sbss'.
6172 These options are ignored for backward compatibility.
6175 File: as.info, Node: Alpha Syntax, Next: Alpha Floating Point, Prev: Alpha Options, Up: Alpha-Dependent
6180 The assembler syntax closely follow the Alpha Reference Manual;
6181 assembler directives and general syntax closely follow the OSF/1 and
6182 OpenVMS syntax, with a few differences for ELF.
6186 * Alpha-Chars:: Special Characters
6187 * Alpha-Regs:: Register Names
6188 * Alpha-Relocs:: Relocations
6191 File: as.info, Node: Alpha-Chars, Next: Alpha-Regs, Up: Alpha Syntax
6193 9.2.3.1 Special Characters
6194 ..........................
6196 `#' is the line comment character. Note that if `#' is the first
6197 character on a line then it can also be a logical line number directive
6198 (*note Comments::) or a preprocessor control command (*note
6201 `;' can be used instead of a newline to separate statements.
6204 File: as.info, Node: Alpha-Regs, Next: Alpha-Relocs, Prev: Alpha-Chars, Up: Alpha Syntax
6206 9.2.3.2 Register Names
6207 ......................
6209 The 32 integer registers are referred to as `$N' or `$rN'. In
6210 addition, registers 15, 28, 29, and 30 may be referred to by the
6211 symbols `$fp', `$at', `$gp', and `$sp' respectively.
6213 The 32 floating-point registers are referred to as `$fN'.
6216 File: as.info, Node: Alpha-Relocs, Prev: Alpha-Regs, Up: Alpha Syntax
6221 Some of these relocations are available for ECOFF, but mostly only for
6222 ELF. They are modeled after the relocation format introduced in
6223 Digital Unix 4.0, but there are additions.
6225 The format is `!TAG' or `!TAG!NUMBER' where TAG is the name of the
6226 relocation. In some cases NUMBER is used to relate specific
6229 The relocation is placed at the end of the instruction like so:
6231 ldah $0,a($29) !gprelhigh
6232 lda $0,a($0) !gprellow
6233 ldq $1,b($29) !literal!100
6234 ldl $2,0($1) !lituse_base!100
6238 Used with an `ldq' instruction to load the address of a symbol
6241 A sequence number N is optional, and if present is used to pair
6242 `lituse' relocations with this `literal' relocation. The `lituse'
6243 relocations are used by the linker to optimize the code based on
6244 the final location of the symbol.
6246 Note that these optimizations are dependent on the data flow of the
6247 program. Therefore, if _any_ `lituse' is paired with a `literal'
6248 relocation, then _all_ uses of the register set by the `literal'
6249 instruction must also be marked with `lituse' relocations. This
6250 is because the original `literal' instruction may be deleted or
6251 transformed into another instruction.
6253 Also note that there may be a one-to-many relationship between
6254 `literal' and `lituse', but not a many-to-one. That is, if there
6255 are two code paths that load up the same address and feed the
6256 value to a single use, then the use may not use a `lituse'
6260 Used with any memory format instruction (e.g. `ldl') to indicate
6261 that the literal is used for an address load. The offset field of
6262 the instruction must be zero. During relaxation, the code may be
6263 altered to use a gp-relative load.
6266 Used with a register branch format instruction (e.g. `jsr') to
6267 indicate that the literal is used for a call. During relaxation,
6268 the code may be altered to use a direct branch (e.g. `bsr').
6270 `!lituse_jsrdirect!N'
6271 Similar to `lituse_jsr', but also that this call cannot be vectored
6272 through a PLT entry. This is useful for functions with special
6273 calling conventions which do not allow the normal call-clobbered
6274 registers to be clobbered.
6277 Used with a byte mask instruction (e.g. `extbl') to indicate that
6278 only the low 3 bits of the address are relevant. During
6279 relaxation, the code may be altered to use an immediate instead of
6283 Used with any other instruction to indicate that the original
6284 address is in fact used, and the original `ldq' instruction may
6285 not be altered or deleted. This is useful in conjunction with
6286 `lituse_jsr' to test whether a weak symbol is defined.
6288 ldq $27,foo($29) !literal!1
6289 beq $27,is_undef !lituse_addr!1
6290 jsr $26,($27),foo !lituse_jsr!1
6293 Used with a register branch format instruction to indicate that the
6294 literal is the call to `__tls_get_addr' used to compute the
6295 address of the thread-local storage variable whose descriptor was
6296 loaded with `!tlsgd!N'.
6299 Used with a register branch format instruction to indicate that the
6300 literal is the call to `__tls_get_addr' used to compute the
6301 address of the base of the thread-local storage block for the
6302 current module. The descriptor for the module must have been
6303 loaded with `!tlsldm!N'.
6306 Used with `ldah' and `lda' to load the GP from the current
6307 address, a-la the `ldgp' macro. The source register for the
6308 `ldah' instruction must contain the address of the `ldah'
6309 instruction. There must be exactly one `lda' instruction paired
6310 with the `ldah' instruction, though it may appear anywhere in the
6311 instruction stream. The immediate operands must be zero.
6314 ldah $29,0($26) !gpdisp!1
6315 lda $29,0($29) !gpdisp!1
6318 Used with an `ldah' instruction to add the high 16 bits of a
6319 32-bit displacement from the GP.
6322 Used with any memory format instruction to add the low 16 bits of a
6323 32-bit displacement from the GP.
6326 Used with any memory format instruction to add a 16-bit
6327 displacement from the GP.
6330 Used with any branch format instruction to skip the GP load at the
6331 target address. The referenced symbol must have the same GP as the
6332 source object file, and it must be declared to either not use `$27'
6333 or perform a standard GP load in the first two instructions via the
6334 `.prologue' directive.
6338 Used with an `lda' instruction to load the address of a TLS
6339 descriptor for a symbol in the GOT.
6341 The sequence number N is optional, and if present it used to pair
6342 the descriptor load with both the `literal' loading the address of
6343 the `__tls_get_addr' function and the `lituse_tlsgd' marking the
6344 call to that function.
6346 For proper relaxation, both the `tlsgd', `literal' and `lituse'
6347 relocations must be in the same extended basic block. That is,
6348 the relocation with the lowest address must be executed first at
6353 Used with an `lda' instruction to load the address of a TLS
6354 descriptor for the current module in the GOT.
6356 Similar in other respects to `tlsgd'.
6359 Used with an `ldq' instruction to load the offset of the TLS
6360 symbol within its module's thread-local storage block. Also known
6361 as the dynamic thread pointer offset or dtp-relative offset.
6366 Like `gprel' relocations except they compute dtp-relative offsets.
6369 Used with an `ldq' instruction to load the offset of the TLS
6370 symbol from the thread pointer. Also known as the tp-relative
6376 Like `gprel' relocations except they compute tp-relative offsets.
6379 File: as.info, Node: Alpha Floating Point, Next: Alpha Directives, Prev: Alpha Syntax, Up: Alpha-Dependent
6381 9.2.4 Floating Point
6382 --------------------
6384 The Alpha family uses both IEEE and VAX floating-point numbers.
6387 File: as.info, Node: Alpha Directives, Next: Alpha Opcodes, Prev: Alpha Floating Point, Up: Alpha-Dependent
6389 9.2.5 Alpha Assembler Directives
6390 --------------------------------
6392 `as' for the Alpha supports many additional directives for
6393 compatibility with the native assembler. This section describes them
6396 These are the additional directives in `as' for the Alpha:
6399 Specifies the target processor. This is equivalent to the `-mCPU'
6400 command-line option. *Note Options: Alpha Options, for a list of
6403 `.ent FUNCTION[, N]'
6404 Mark the beginning of FUNCTION. An optional number may follow for
6405 compatibility with the OSF/1 assembler, but is ignored. When
6406 generating `.mdebug' information, this will create a procedure
6407 descriptor for the function. In ELF, it will mark the symbol as a
6408 function a-la the generic `.type' directive.
6411 Mark the end of FUNCTION. In ELF, it will set the size of the
6412 symbol a-la the generic `.size' directive.
6414 `.mask MASK, OFFSET'
6415 Indicate which of the integer registers are saved in the current
6416 function's stack frame. MASK is interpreted a bit mask in which
6417 bit N set indicates that register N is saved. The registers are
6418 saved in a block located OFFSET bytes from the "canonical frame
6419 address" (CFA) which is the value of the stack pointer on entry to
6420 the function. The registers are saved sequentially, except that
6421 the return address register (normally `$26') is saved first.
6423 This and the other directives that describe the stack frame are
6424 currently only used when generating `.mdebug' information. They
6425 may in the future be used to generate DWARF2 `.debug_frame' unwind
6426 information for hand written assembly.
6428 `.fmask MASK, OFFSET'
6429 Indicate which of the floating-point registers are saved in the
6430 current stack frame. The MASK and OFFSET parameters are
6431 interpreted as with `.mask'.
6433 `.frame FRAMEREG, FRAMEOFFSET, RETREG[, ARGOFFSET]'
6434 Describes the shape of the stack frame. The frame pointer in use
6435 is FRAMEREG; normally this is either `$fp' or `$sp'. The frame
6436 pointer is FRAMEOFFSET bytes below the CFA. The return address is
6437 initially located in RETREG until it is saved as indicated in
6438 `.mask'. For compatibility with OSF/1 an optional ARGOFFSET
6439 parameter is accepted and ignored. It is believed to indicate the
6440 offset from the CFA to the saved argument registers.
6443 Indicate that the stack frame is set up and all registers have been
6444 spilled. The argument N indicates whether and how the function
6445 uses the incoming "procedure vector" (the address of the called
6446 function) in `$27'. 0 indicates that `$27' is not used; 1
6447 indicates that the first two instructions of the function use `$27'
6448 to perform a load of the GP register; 2 indicates that `$27' is
6449 used in some non-standard way and so the linker cannot elide the
6450 load of the procedure vector during relaxation.
6452 `.usepv FUNCTION, WHICH'
6453 Used to indicate the use of the `$27' register, similar to
6454 `.prologue', but without the other semantics of needing to be
6455 inside an open `.ent'/`.end' block.
6457 The WHICH argument should be either `no', indicating that `$27' is
6458 not used, or `std', indicating that the first two instructions of
6459 the function perform a GP load.
6461 One might use this directive instead of `.prologue' if you are
6462 also using dwarf2 CFI directives.
6464 `.gprel32 EXPRESSION'
6465 Computes the difference between the address in EXPRESSION and the
6466 GP for the current object file, and stores it in 4 bytes. In
6467 addition to being smaller than a full 8 byte address, this also
6468 does not require a dynamic relocation when used in a shared
6471 `.t_floating EXPRESSION'
6472 Stores EXPRESSION as an IEEE double precision value.
6474 `.s_floating EXPRESSION'
6475 Stores EXPRESSION as an IEEE single precision value.
6477 `.f_floating EXPRESSION'
6478 Stores EXPRESSION as a VAX F format value.
6480 `.g_floating EXPRESSION'
6481 Stores EXPRESSION as a VAX G format value.
6483 `.d_floating EXPRESSION'
6484 Stores EXPRESSION as a VAX D format value.
6487 Enables or disables various assembler features. Using the positive
6488 name of the feature enables while using `noFEATURE' disables.
6491 Indicates that macro expansions may clobber the "assembler
6492 temporary" (`$at' or `$28') register. Some macros may not be
6493 expanded without this and will generate an error message if
6494 `noat' is in effect. When `at' is in effect, a warning will
6495 be generated if `$at' is used by the programmer.
6498 Enables the expansion of macro instructions. Note that
6499 variants of real instructions, such as `br label' vs `br
6500 $31,label' are considered alternate forms and not macros.
6505 These control whether and how the assembler may re-order
6506 instructions. Accepted for compatibility with the OSF/1
6507 assembler, but `as' does not do instruction scheduling, so
6508 these features are ignored.
6510 The following directives are recognized for compatibility with the
6511 OSF/1 assembler but are ignored.
6520 File: as.info, Node: Alpha Opcodes, Prev: Alpha Directives, Up: Alpha-Dependent
6525 For detailed information on the Alpha machine instruction set, see the
6526 Alpha Architecture Handbook
6527 (ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdf).
6530 File: as.info, Node: ARC-Dependent, Next: ARM-Dependent, Prev: Alpha-Dependent, Up: Machine Dependencies
6532 9.3 ARC Dependent Features
6533 ==========================
6537 * ARC Options:: Options
6538 * ARC Syntax:: Syntax
6539 * ARC Floating Point:: Floating Point
6540 * ARC Directives:: ARC Machine Directives
6541 * ARC Opcodes:: Opcodes
6544 File: as.info, Node: ARC Options, Next: ARC Syntax, Up: ARC-Dependent
6550 This option selects the core processor variant. Using `-marc' is
6551 the same as `-marc6', which is also the default.
6554 Base instruction set.
6557 Jump-and-link (jl) instruction. No requirement of an
6558 instruction between setting flags and conditional jump. For
6565 Break (brk) and sleep (sleep) instructions.
6568 Software interrupt (swi) instruction.
6571 Note: the `.option' directive can to be used to select a core
6572 variant from within assembly code.
6575 This option specifies that the output generated by the assembler
6576 should be marked as being encoded for a big-endian processor.
6579 This option specifies that the output generated by the assembler
6580 should be marked as being encoded for a little-endian processor -
6581 this is the default.
6585 File: as.info, Node: ARC Syntax, Next: ARC Floating Point, Prev: ARC Options, Up: ARC-Dependent
6592 * ARC-Chars:: Special Characters
6593 * ARC-Regs:: Register Names
6596 File: as.info, Node: ARC-Chars, Next: ARC-Regs, Up: ARC Syntax
6598 9.3.2.1 Special Characters
6599 ..........................
6601 The presence of a `#' on a line indicates the start of a comment that
6602 extends to the end of the current line. Note that if a line starts
6603 with a `#' character then it can also be a logical line number
6604 directive (*note Comments::) or a preprocessor control command (*note
6607 The ARC assembler does not support a line separator character.
6610 File: as.info, Node: ARC-Regs, Prev: ARC-Chars, Up: ARC Syntax
6612 9.3.2.2 Register Names
6613 ......................
6618 File: as.info, Node: ARC Floating Point, Next: ARC Directives, Prev: ARC Syntax, Up: ARC-Dependent
6620 9.3.3 Floating Point
6621 --------------------
6623 The ARC core does not currently have hardware floating point support.
6624 Software floating point support is provided by `GCC' and uses IEEE
6625 floating-point numbers.
6628 File: as.info, Node: ARC Directives, Next: ARC Opcodes, Prev: ARC Floating Point, Up: ARC-Dependent
6630 9.3.4 ARC Machine Directives
6631 ----------------------------
6633 The ARC version of `as' supports the following additional machine
6636 `.2byte EXPRESSIONS'
6639 `.3byte EXPRESSIONS'
6642 `.4byte EXPRESSIONS'
6645 `.extAuxRegister NAME,ADDRESS,MODE'
6646 The ARCtangent A4 has extensible auxiliary register space. The
6647 auxiliary registers can be defined in the assembler source code by
6648 using this directive. The first parameter is the NAME of the new
6649 auxiallry register. The second parameter is the ADDRESS of the
6650 register in the auxiliary register memory map for the variant of
6651 the ARC. The third parameter specifies the MODE in which the
6652 register can be operated is and it can be one of:
6658 `r|w (read or write)'
6662 .extAuxRegister mulhi,0x12,w
6664 This specifies an extension auxiliary register called _mulhi_
6665 which is at address 0x12 in the memory space and which is only
6668 `.extCondCode SUFFIX,VALUE'
6669 The condition codes on the ARCtangent A4 are extensible and can be
6670 specified by means of this assembler directive. They are specified
6671 by the suffix and the value for the condition code. They can be
6672 used to specify extra condition codes with any values. For
6675 .extCondCode is_busy,0x14
6677 add.is_busy r1,r2,r3
6680 `.extCoreRegister NAME,REGNUM,MODE,SHORTCUT'
6681 Specifies an extension core register NAME for the application.
6682 This allows a register NAME with a valid REGNUM between 0 and 60,
6683 with the following as valid values for MODE
6689 `_r|w_ (read or write)'
6691 The other parameter gives a description of the register having a
6692 SHORTCUT in the pipeline. The valid values are:
6700 .extCoreRegister mlo,57,r,can_shortcut
6702 This defines an extension core register mlo with the value 57 which
6703 can shortcut the pipeline.
6705 `.extInstruction NAME,OPCODE,SUBOPCODE,SUFFIXCLASS,SYNTAXCLASS'
6706 The ARCtangent A4 allows the user to specify extension
6707 instructions. The extension instructions are not macros. The
6708 assembler creates encodings for use of these instructions
6709 according to the specification by the user. The parameters are:
6711 * NAME Name of the extension instruction
6713 * OPCODE Opcode to be used. (Bits 27:31 in the encoding).
6714 Valid values 0x10-0x1f or 0x03
6716 * SUBOPCODE Subopcode to be used. Valid values are from
6717 0x09-0x3f. However the correct value also depends on
6720 * SUFFIXCLASS Determines the kinds of suffixes to be allowed.
6721 Valid values are `SUFFIX_NONE', `SUFFIX_COND', `SUFFIX_FLAG'
6722 which indicates the absence or presence of conditional
6723 suffixes and flag setting by the extension instruction. It
6724 is also possible to specify that an instruction sets the
6725 flags and is conditional by using `SUFFIX_CODE' |
6728 * SYNTAXCLASS Determines the syntax class for the instruction.
6729 It can have the following values:
6732 2 Operand Instruction
6735 3 Operand Instruction
6737 In addition there could be modifiers for the syntax class as
6740 Syntax Class Modifiers are:
6742 - `OP1_MUST_BE_IMM': Modifies syntax class SYNTAX_3OP,
6743 specifying that the first operand of a three-operand
6744 instruction must be an immediate (i.e., the result is
6745 discarded). OP1_MUST_BE_IMM is used by bitwise ORing it
6746 with SYNTAX_3OP as given in the example below. This
6747 could usually be used to set the flags using specific
6748 instructions and not retain results.
6750 - `OP1_IMM_IMPLIED': Modifies syntax class SYNTAX_20P, it
6751 specifies that there is an implied immediate destination
6752 operand which does not appear in the syntax. For
6753 example, if the source code contains an instruction like:
6757 it really means that the first argument is an implied
6758 immediate (that is, the result is discarded). This is
6759 the same as though the source code were: inst 0,r1,r2.
6760 You use OP1_IMM_IMPLIED by bitwise ORing it with
6764 For example, defining 64-bit multiplier with immediate operands:
6766 .extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG ,
6767 SYNTAX_3OP|OP1_MUST_BE_IMM
6769 The above specifies an extension instruction called mp64 which has
6770 3 operands, sets the flags, can be used with a condition code, for
6771 which the first operand is an immediate. (Equivalent to
6772 discarding the result of the operation).
6774 .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED
6776 This describes a 2 operand instruction with an implicit first
6777 immediate operand. The result of this operation would be
6786 `.option ARC|ARC5|ARC6|ARC7|ARC8'
6787 The `.option' directive must be followed by the desired core
6788 version. Again `arc' is an alias for `arc6'.
6790 Note: the `.option' directive overrides the command line option
6791 `-marc'; a warning is emitted when the version is not consistent
6792 between the two - even for the implicit default core version
6795 `.short EXPRESSIONS'
6803 File: as.info, Node: ARC Opcodes, Prev: ARC Directives, Up: ARC-Dependent
6808 For information on the ARC instruction set, see `ARC Programmers
6809 Reference Manual', ARC International (www.arc.com)
6812 File: as.info, Node: ARM-Dependent, Next: AVR-Dependent, Prev: ARC-Dependent, Up: Machine Dependencies
6814 9.4 ARM Dependent Features
6815 ==========================
6819 * ARM Options:: Options
6820 * ARM Syntax:: Syntax
6821 * ARM Floating Point:: Floating Point
6822 * ARM Directives:: ARM Machine Directives
6823 * ARM Opcodes:: Opcodes
6824 * ARM Mapping Symbols:: Mapping Symbols
6825 * ARM Unwinding Tutorial:: Unwinding
6828 File: as.info, Node: ARM Options, Next: ARM Syntax, Up: ARM-Dependent
6833 `-mcpu=PROCESSOR[+EXTENSION...]'
6834 This option specifies the target processor. The assembler will
6835 issue an error message if an attempt is made to assemble an
6836 instruction which will not execute on the target processor. The
6837 following processor names are recognized: `arm1', `arm2', `arm250',
6838 `arm3', `arm6', `arm60', `arm600', `arm610', `arm620', `arm7',
6839 `arm7m', `arm7d', `arm7dm', `arm7di', `arm7dmi', `arm70', `arm700',
6840 `arm700i', `arm710', `arm710t', `arm720', `arm720t', `arm740t',
6841 `arm710c', `arm7100', `arm7500', `arm7500fe', `arm7t', `arm7tdmi',
6842 `arm7tdmi-s', `arm8', `arm810', `strongarm', `strongarm1',
6843 `strongarm110', `strongarm1100', `strongarm1110', `arm9', `arm920',
6844 `arm920t', `arm922t', `arm940t', `arm9tdmi', `fa526' (Faraday
6845 FA526 processor), `fa626' (Faraday FA626 processor), `arm9e',
6846 `arm926e', `arm926ej-s', `arm946e-r0', `arm946e', `arm946e-s',
6847 `arm966e-r0', `arm966e', `arm966e-s', `arm968e-s', `arm10t',
6848 `arm10tdmi', `arm10e', `arm1020', `arm1020t', `arm1020e',
6849 `arm1022e', `arm1026ej-s', `fa606te' (Faraday FA606TE processor),
6850 `fa616te' (Faraday FA616TE processor), `fa626te' (Faraday FA626TE
6851 processor), `fmp626' (Faraday FMP626 processor), `fa726te'
6852 (Faraday FA726TE processor), `arm1136j-s', `arm1136jf-s',
6853 `arm1156t2-s', `arm1156t2f-s', `arm1176jz-s', `arm1176jzf-s',
6854 `mpcore', `mpcorenovfp', `cortex-a5', `cortex-a7', `cortex-a8',
6855 `cortex-a9', `cortex-a15', `cortex-r4', `cortex-r4f', `cortex-r5',
6856 `cortex-r7', `cortex-m4', `cortex-m3', `cortex-m1', `cortex-m0',
6857 `cortex-m0plus', `ep9312' (ARM920 with Cirrus Maverick
6858 coprocessor), `i80200' (Intel XScale processor) `iwmmxt' (Intel(r)
6859 XScale processor with Wireless MMX(tm) technology coprocessor) and
6860 `xscale'. The special name `all' may be used to allow the
6861 assembler to accept instructions valid for any ARM processor.
6863 In addition to the basic instruction set, the assembler can be
6864 told to accept various extension mnemonics that extend the
6865 processor using the co-processor instruction space. For example,
6866 `-mcpu=arm920+maverick' is equivalent to specifying `-mcpu=ep9312'.
6868 Multiple extensions may be specified, separated by a `+'. The
6869 extensions should be specified in ascending alphabetical order.
6871 Some extensions may be restricted to particular architectures;
6872 this is documented in the list of extensions below.
6874 Extension mnemonics may also be removed from those the assembler
6875 accepts. This is done be prepending `no' to the option that adds
6876 the extension. Extensions that are removed should be listed after
6877 all extensions which have been added, again in ascending
6878 alphabetical order. For example, `-mcpu=ep9312+nomaverick' is
6879 equivalent to specifying `-mcpu=arm920'.
6881 The following extensions are currently supported: `crypto'
6882 (Cryptography Extensions for v8-A architecture, implies `fp+simd'),
6883 `fp' (Floating Point Extensions for v8-A architecture), `idiv'
6884 (Integer Divide Extensions for v7-A and v7-R architectures),
6885 `iwmmxt', `iwmmxt2', `maverick', `mp' (Multiprocessing Extensions
6886 for v7-A and v7-R architectures), `os' (Operating System for v6M
6887 architecture), `sec' (Security Extensions for v6K and v7-A
6888 architectures), `simd' (Advanced SIMD Extensions for v8-A
6889 architecture, implies `fp'), `virt' (Virtualization Extensions for
6890 v7-A architecture, implies `idiv'), and `xscale'.
6892 `-march=ARCHITECTURE[+EXTENSION...]'
6893 This option specifies the target architecture. The assembler will
6894 issue an error message if an attempt is made to assemble an
6895 instruction which will not execute on the target architecture.
6896 The following architecture names are recognized: `armv1', `armv2',
6897 `armv2a', `armv2s', `armv3', `armv3m', `armv4', `armv4xm',
6898 `armv4t', `armv4txm', `armv5', `armv5t', `armv5txm', `armv5te',
6899 `armv5texp', `armv6', `armv6j', `armv6k', `armv6z', `armv6zk',
6900 `armv6-m', `armv6s-m', `armv7', `armv7-a', `armv7ve', `armv7-r',
6901 `armv7-m', `armv7e-m', `armv8-a', `iwmmxt' and `xscale'. If both
6902 `-mcpu' and `-march' are specified, the assembler will use the
6903 setting for `-mcpu'.
6905 The architecture option can be extended with the same instruction
6906 set extension options as the `-mcpu' option.
6908 `-mfpu=FLOATING-POINT-FORMAT'
6909 This option specifies the floating point format to assemble for.
6910 The assembler will issue an error message if an attempt is made to
6911 assemble an instruction which will not execute on the target
6912 floating point unit. The following format options are recognized:
6913 `softfpa', `fpe', `fpe2', `fpe3', `fpa', `fpa10', `fpa11',
6914 `arm7500fe', `softvfp', `softvfp+vfp', `vfp', `vfp10', `vfp10-r0',
6915 `vfp9', `vfpxd', `vfpv2', `vfpv3', `vfpv3-fp16', `vfpv3-d16',
6916 `vfpv3-d16-fp16', `vfpv3xd', `vfpv3xd-d16', `vfpv4', `vfpv4-d16',
6917 `fpv4-sp-d16', `fp-armv8', `arm1020t', `arm1020e', `arm1136jf-s',
6918 `maverick', `neon', `neon-vfpv4', `neon-fp-armv8', and
6919 `crypto-neon-fp-armv8'.
6921 In addition to determining which instructions are assembled, this
6922 option also affects the way in which the `.double' assembler
6923 directive behaves when assembling little-endian code.
6925 The default is dependent on the processor selected. For
6926 Architecture 5 or later, the default is to assembler for VFP
6927 instructions; for earlier architectures the default is to assemble
6928 for FPA instructions.
6931 This option specifies that the assembler should start assembling
6932 Thumb instructions; that is, it should behave as though the file
6933 starts with a `.code 16' directive.
6936 This option specifies that the output generated by the assembler
6937 should be marked as supporting interworking.
6939 `-mimplicit-it=never'
6940 `-mimplicit-it=always'
6942 `-mimplicit-it=thumb'
6943 The `-mimplicit-it' option controls the behavior of the assembler
6944 when conditional instructions are not enclosed in IT blocks.
6945 There are four possible behaviors. If `never' is specified, such
6946 constructs cause a warning in ARM code and an error in Thumb-2
6947 code. If `always' is specified, such constructs are accepted in
6948 both ARM and Thumb-2 code, where the IT instruction is added
6949 implicitly. If `arm' is specified, such constructs are accepted
6950 in ARM code and cause an error in Thumb-2 code. If `thumb' is
6951 specified, such constructs cause a warning in ARM code and are
6952 accepted in Thumb-2 code. If you omit this option, the behavior
6953 is equivalent to `-mimplicit-it=arm'.
6957 These options specify that the output generated by the assembler
6958 should be marked as supporting the indicated version of the Arm
6959 Procedure. Calling Standard.
6962 This option specifies that the output generated by the assembler
6963 should be marked as supporting the Arm/Thumb Procedure Calling
6964 Standard. If enabled this option will cause the assembler to
6965 create an empty debugging section in the object file called
6966 .arm.atpcs. Debuggers can use this to determine the ABI being
6970 This indicates the floating point variant of the APCS should be
6971 used. In this variant floating point arguments are passed in FP
6972 registers rather than integer registers.
6975 This indicates that the reentrant variant of the APCS should be
6976 used. This variant supports position independent code.
6979 This option specifies that the output generated by the assembler
6980 should be marked as using specified floating point ABI. The
6981 following values are recognized: `soft', `softfp' and `hard'.
6984 This option specifies which EABI version the produced object files
6985 should conform to. The following values are recognized: `gnu', `4'
6989 This option specifies that the output generated by the assembler
6990 should be marked as being encoded for a big-endian processor.
6993 This option specifies that the output generated by the assembler
6994 should be marked as being encoded for a little-endian processor.
6997 This option specifies that the output of the assembler should be
6998 marked as position-independent code (PIC).
7001 Allow `BX' instructions in ARMv4 code. This is intended for use
7002 with the linker option of the same name.
7005 `-mno-warn-deprecated'
7006 Enable or disable warnings about using deprecated options or
7007 features. The default is to warn.
7010 Turns on CodeComposer Studio assembly syntax compatibility mode.
7014 File: as.info, Node: ARM Syntax, Next: ARM Floating Point, Prev: ARM Options, Up: ARM-Dependent
7021 * ARM-Instruction-Set:: Instruction Set
7022 * ARM-Chars:: Special Characters
7023 * ARM-Regs:: Register Names
7024 * ARM-Relocations:: Relocations
7025 * ARM-Neon-Alignment:: NEON Alignment Specifiers
7028 File: as.info, Node: ARM-Instruction-Set, Next: ARM-Chars, Up: ARM Syntax
7030 9.4.2.1 Instruction Set Syntax
7031 ..............................
7033 Two slightly different syntaxes are support for ARM and THUMB
7034 instructions. The default, `divided', uses the old style where ARM and
7035 THUMB instructions had their own, separate syntaxes. The new,
7036 `unified' syntax, which can be selected via the `.syntax' directive,
7037 and has the following main features:
7039 * Immediate operands do not require a `#' prefix.
7041 * The `IT' instruction may appear, and if it does it is validated
7042 against subsequent conditional affixes. In ARM mode it does not
7043 generate machine code, in THUMB mode it does.
7045 * For ARM instructions the conditional affixes always appear at the
7046 end of the instruction. For THUMB instructions conditional
7047 affixes can be used, but only inside the scope of an `IT'
7050 * All of the instructions new to the V6T2 architecture (and later)
7051 are available. (Only a few such instructions can be written in the
7054 * The `.N' and `.W' suffixes are recognized and honored.
7056 * All instructions set the flags if and only if they have an `s'
7060 File: as.info, Node: ARM-Chars, Next: ARM-Regs, Prev: ARM-Instruction-Set, Up: ARM Syntax
7062 9.4.2.2 Special Characters
7063 ..........................
7065 The presence of a `@' anywhere on a line indicates the start of a
7066 comment that extends to the end of that line.
7068 If a `#' appears as the first character of a line then the whole
7069 line is treated as a comment, but in this case the line could also be a
7070 logical line number directive (*note Comments::) or a preprocessor
7071 control command (*note Preprocessing::).
7073 The `;' character can be used instead of a newline to separate
7076 Either `#' or `$' can be used to indicate immediate operands.
7078 *TODO* Explain about /data modifier on symbols.
7081 File: as.info, Node: ARM-Regs, Next: ARM-Relocations, Prev: ARM-Chars, Up: ARM Syntax
7083 9.4.2.3 Register Names
7084 ......................
7086 *TODO* Explain about ARM register naming, and the predefined names.
7089 File: as.info, Node: ARM-Relocations, Next: ARM-Neon-Alignment, Prev: ARM-Regs, Up: ARM Syntax
7091 9.4.2.4 ARM relocation generation
7092 .................................
7094 Specific data relocations can be generated by putting the relocation
7095 name in parentheses after the symbol name. For example:
7099 This will generate an `R_ARM_TARGET1' relocation against the symbol
7100 FOO. The following relocations are supported: `GOT', `GOTOFF',
7101 `TARGET1', `TARGET2', `SBREL', `TLSGD', `TLSLDM', `TLSLDO', `TLSDESC',
7102 `TLSCALL', `GOTTPOFF', `GOT_PREL' and `TPOFF'.
7104 For compatibility with older toolchains the assembler also accepts
7105 `(PLT)' after branch targets. On legacy targets this will generate the
7106 deprecated `R_ARM_PLT32' relocation. On EABI targets it will encode
7107 either the `R_ARM_CALL' or `R_ARM_JUMP24' relocation, as appropriate.
7109 Relocations for `MOVW' and `MOVT' instructions can be generated by
7110 prefixing the value with `#:lower16:' and `#:upper16' respectively.
7111 For example to load the 32-bit address of foo into r0:
7113 MOVW r0, #:lower16:foo
7114 MOVT r0, #:upper16:foo
7117 File: as.info, Node: ARM-Neon-Alignment, Prev: ARM-Relocations, Up: ARM Syntax
7119 9.4.2.5 NEON Alignment Specifiers
7120 .................................
7122 Some NEON load/store instructions allow an optional address alignment
7123 qualifier. The ARM documentation specifies that this is indicated by
7124 `@ ALIGN'. However GAS already interprets the `@' character as a "line
7125 comment" start, so `: ALIGN' is used instead. For example:
7127 vld1.8 {q0}, [r0, :128]
7130 File: as.info, Node: ARM Floating Point, Next: ARM Directives, Prev: ARM Syntax, Up: ARM-Dependent
7132 9.4.3 Floating Point
7133 --------------------
7135 The ARM family uses IEEE floating-point numbers.
7138 File: as.info, Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Point, Up: ARM-Dependent
7140 9.4.4 ARM Machine Directives
7141 ----------------------------
7143 `.2byte EXPRESSION [, EXPRESSION]*'
7144 `.4byte EXPRESSION [, EXPRESSION]*'
7145 `.8byte EXPRESSION [, EXPRESSION]*'
7146 These directives write 2, 4 or 8 byte values to the output section.
7148 `.align EXPRESSION [, EXPRESSION]'
7149 This is the generic .ALIGN directive. For the ARM however if the
7150 first argument is zero (ie no alignment is needed) the assembler
7151 will behave as if the argument had been 2 (ie pad to the next four
7152 byte boundary). This is for compatibility with ARM's own
7156 Select the target architecture. Valid values for NAME are the
7157 same as for the `-march' commandline option.
7159 Specifying `.arch' clears any previously selected architecture
7162 `.arch_extension NAME'
7163 Add or remove an architecture extension to the target
7164 architecture. Valid values for NAME are the same as those
7165 accepted as architectural extensions by the `-mcpu' commandline
7168 `.arch_extension' may be used multiple times to add or remove
7169 extensions incrementally to the architecture being compiled for.
7172 This performs the same action as .CODE 32.
7175 This directive switches to the `.bss' section.
7178 Prevents unwinding through the current function. No personality
7179 routine or exception table data is required or permitted.
7182 This directive selects the instruction set being generated. The
7183 value 16 selects Thumb, with the value 32 selecting ARM.
7186 Select the target processor. Valid values for NAME are the same as
7187 for the `-mcpu' commandline option.
7189 Specifying `.cpu' clears any previously selected architecture
7192 `NAME .dn REGISTER NAME [.TYPE] [[INDEX]]'
7193 `NAME .qn REGISTER NAME [.TYPE] [[INDEX]]'
7194 The `dn' and `qn' directives are used to create typed and/or
7195 indexed register aliases for use in Advanced SIMD Extension (Neon)
7196 instructions. The former should be used to create aliases of
7197 double-precision registers, and the latter to create aliases of
7198 quad-precision registers.
7200 If these directives are used to create typed aliases, those
7201 aliases can be used in Neon instructions instead of writing types
7202 after the mnemonic or after each operand. For example:
7209 This is equivalent to writing the following:
7211 vmul.f32 d2,d3,d4[1]
7213 Aliases created using `dn' or `qn' can be destroyed using `unreq'.
7215 `.eabi_attribute TAG, VALUE'
7216 Set the EABI object attribute TAG to VALUE.
7218 The TAG is either an attribute number, or one of the following:
7219 `Tag_CPU_raw_name', `Tag_CPU_name', `Tag_CPU_arch',
7220 `Tag_CPU_arch_profile', `Tag_ARM_ISA_use', `Tag_THUMB_ISA_use',
7221 `Tag_FP_arch', `Tag_WMMX_arch', `Tag_Advanced_SIMD_arch',
7222 `Tag_PCS_config', `Tag_ABI_PCS_R9_use', `Tag_ABI_PCS_RW_data',
7223 `Tag_ABI_PCS_RO_data', `Tag_ABI_PCS_GOT_use',
7224 `Tag_ABI_PCS_wchar_t', `Tag_ABI_FP_rounding',
7225 `Tag_ABI_FP_denormal', `Tag_ABI_FP_exceptions',
7226 `Tag_ABI_FP_user_exceptions', `Tag_ABI_FP_number_model',
7227 `Tag_ABI_align_needed', `Tag_ABI_align_preserved',
7228 `Tag_ABI_enum_size', `Tag_ABI_HardFP_use', `Tag_ABI_VFP_args',
7229 `Tag_ABI_WMMX_args', `Tag_ABI_optimization_goals',
7230 `Tag_ABI_FP_optimization_goals', `Tag_compatibility',
7231 `Tag_CPU_unaligned_access', `Tag_FP_HP_extension',
7232 `Tag_ABI_FP_16bit_format', `Tag_MPextension_use', `Tag_DIV_use',
7233 `Tag_nodefaults', `Tag_also_compatible_with', `Tag_conformance',
7234 `Tag_T2EE_use', `Tag_Virtualization_use'
7236 The VALUE is either a `number', `"string"', or `number, "string"'
7237 depending on the tag.
7239 Note - the following legacy values are also accepted by TAG:
7240 `Tag_VFP_arch', `Tag_ABI_align8_needed',
7241 `Tag_ABI_align8_preserved', `Tag_VFP_HP_extension',
7244 This directive aligns to an even-numbered address.
7246 `.extend EXPRESSION [, EXPRESSION]*'
7247 `.ldouble EXPRESSION [, EXPRESSION]*'
7248 These directives write 12byte long double floating-point values to
7249 the output section. These are not compatible with current ARM
7253 Marks the end of a function with an unwind table entry. The
7254 unwind index table entry is created when this directive is
7257 If no personality routine has been specified then standard
7258 personality routine 0 or 1 will be used, depending on the number
7259 of unwind opcodes required.
7262 Marks the start of a function with an unwind table entry.
7265 This directive forces the selection of Thumb instructions, even if
7266 the target processor does not support those instructions
7269 Select the floating-point unit to assemble for. Valid values for
7270 NAME are the same as for the `-mfpu' commandline option.
7273 Marks the end of the current function, and the start of the
7274 exception table entry for that function. Anything between this
7275 directive and the `.fnend' directive will be added to the
7276 exception table entry.
7278 Must be preceded by a `.personality' or `.personalityindex'
7281 `.inst OPCODE [ , ... ]'
7282 `.inst.n OPCODE [ , ... ]'
7283 `.inst.w OPCODE [ , ... ]'
7284 Generates the instruction corresponding to the numerical value
7285 OPCODE. `.inst.n' and `.inst.w' allow the Thumb instruction size
7286 to be specified explicitly, overriding the normal encoding rules.
7288 `.ldouble EXPRESSION [, EXPRESSION]*'
7292 This directive causes the current contents of the literal pool to
7293 be dumped into the current section (which is assumed to be the
7294 .text section) at the current location (aligned to a word
7295 boundary). `GAS' maintains a separate literal pool for each
7296 section and each sub-section. The `.ltorg' directive will only
7297 affect the literal pool of the current section and sub-section.
7298 At the end of assembly all remaining, un-empty literal pools will
7299 automatically be dumped.
7301 Note - older versions of `GAS' would dump the current literal pool
7302 any time a section change occurred. This is no longer done, since
7303 it prevents accurate control of the placement of literal pools.
7305 `.movsp REG [, #OFFSET]'
7306 Tell the unwinder that REG contains an offset from the current
7307 stack pointer. If OFFSET is not specified then it is assumed to be
7311 Override the architecture recorded in the EABI object attribute
7312 section. Valid values for NAME are the same as for the `.arch'
7313 directive. Typically this is useful when code uses runtime
7314 detection of CPU features.
7316 `.packed EXPRESSION [, EXPRESSION]*'
7317 This directive writes 12-byte packed floating-point values to the
7318 output section. These are not compatible with current ARM
7322 Generate unwinder annotations for a stack adjustment of COUNT
7323 bytes. A positive value indicates the function prologue allocated
7324 stack space by decrementing the stack pointer.
7327 Sets the personality routine for the current function to NAME.
7329 `.personalityindex INDEX'
7330 Sets the personality routine for the current function to the EABI
7331 standard routine number INDEX
7334 This is a synonym for .ltorg.
7336 `NAME .req REGISTER NAME'
7337 This creates an alias for REGISTER NAME called NAME. For example:
7342 Generate unwinder annotations to restore the registers in REGLIST.
7343 The format of REGLIST is the same as the corresponding
7344 store-multiple instruction.
7347 .save {r4, r5, r6, lr}
7348 stmfd sp!, {r4, r5, r6, lr}
7354 fstmdx sp!, {d8, d9, d10}
7357 wstrd wr11, [sp, #-8]!
7358 wstrd wr10, [sp, #-8]!
7361 wstrd wr11, [sp, #-8]!
7363 wstrd wr10, [sp, #-8]!
7365 `.setfp FPREG, SPREG [, #OFFSET]'
7366 Make all unwinder annotations relative to a frame pointer.
7367 Without this the unwinder will use offsets from the stack pointer.
7369 The syntax of this directive is the same as the `add' or `mov'
7370 instruction used to set the frame pointer. SPREG must be either
7371 `sp' or mentioned in a previous `.movsp' directive.
7379 `.secrel32 EXPRESSION [, EXPRESSION]*'
7380 This directive emits relocations that evaluate to the
7381 section-relative offset of each expression's symbol. This
7382 directive is only supported for PE targets.
7384 `.syntax [`unified' | `divided']'
7385 This directive sets the Instruction Set Syntax as described in the
7386 *Note ARM-Instruction-Set:: section.
7389 This performs the same action as .CODE 16.
7392 This directive specifies that the following symbol is the name of a
7393 Thumb encoded function. This information is necessary in order to
7394 allow the assembler and linker to generate correct code for
7395 interworking between Arm and Thumb instructions and should be used
7396 even if interworking is not going to be performed. The presence
7397 of this directive also implies `.thumb'
7399 This directive is not neccessary when generating EABI objects. On
7400 these targets the encoding is implicit when generating Thumb code.
7403 This performs the equivalent of a `.set' directive in that it
7404 creates a symbol which is an alias for another symbol (possibly
7405 not yet defined). This directive also has the added property in
7406 that it marks the aliased symbol as being a thumb function entry
7407 point, in the same way that the `.thumb_func' directive does.
7409 `.tlsdescseq TLS-VARIABLE'
7410 This directive is used to annotate parts of an inlined TLS
7411 descriptor trampoline. Normally the trampoline is provided by the
7412 linker, and this directive is not needed.
7415 This undefines a register alias which was previously defined using
7416 the `req', `dn' or `qn' directives. For example:
7421 An error occurs if the name is undefined. Note - this pseudo op
7422 can be used to delete builtin in register name aliases (eg 'r0').
7423 This should only be done if it is really necessary.
7425 `.unwind_raw OFFSET, BYTE1, ...'
7426 Insert one of more arbitary unwind opcode bytes, which are known
7427 to adjust the stack pointer by OFFSET bytes.
7429 For example `.unwind_raw 4, 0xb1, 0x01' is equivalent to `.save
7432 `.vsave VFP-REGLIST'
7433 Generate unwinder annotations to restore the VFP registers in
7434 VFP-REGLIST using FLDMD. Also works for VFPv3 registers that are
7435 to be restored using VLDM. The format of VFP-REGLIST is the same
7436 as the corresponding store-multiple instruction.
7439 .vsave {d8, d9, d10}
7440 fstmdd sp!, {d8, d9, d10}
7442 .vsave {d15, d16, d17}
7443 vstm sp!, {d15, d16, d17}
7445 Since FLDMX and FSTMX are now deprecated, this directive should be
7446 used in favour of `.save' for saving VFP registers for ARMv6 and
7451 File: as.info, Node: ARM Opcodes, Next: ARM Mapping Symbols, Prev: ARM Directives, Up: ARM-Dependent
7456 `as' implements all the standard ARM opcodes. It also implements
7457 several pseudo opcodes, including several synthetic load instructions.
7462 This pseudo op will always evaluate to a legal ARM instruction
7463 that does nothing. Currently it will evaluate to MOV r0, r0.
7466 ldr <register> , = <expression>
7468 If expression evaluates to a numeric constant then a MOV or MVN
7469 instruction will be used in place of the LDR instruction, if the
7470 constant can be generated by either of these instructions.
7471 Otherwise the constant will be placed into the nearest literal
7472 pool (if it not already there) and a PC relative LDR instruction
7476 adr <register> <label>
7478 This instruction will load the address of LABEL into the indicated
7479 register. The instruction will evaluate to a PC relative ADD or
7480 SUB instruction depending upon where the label is located. If the
7481 label is out of range, or if it is not defined in the same file
7482 (and section) as the ADR instruction, then an error will be
7483 generated. This instruction will not make use of the literal pool.
7486 adrl <register> <label>
7488 This instruction will load the address of LABEL into the indicated
7489 register. The instruction will evaluate to one or two PC relative
7490 ADD or SUB instructions depending upon where the label is located.
7491 If a second instruction is not needed a NOP instruction will be
7492 generated in its place, so that this instruction is always 8 bytes
7495 If the label is out of range, or if it is not defined in the same
7496 file (and section) as the ADRL instruction, then an error will be
7497 generated. This instruction will not make use of the literal pool.
7500 For information on the ARM or Thumb instruction sets, see `ARM
7501 Software Development Toolkit Reference Manual', Advanced RISC Machines
7505 File: as.info, Node: ARM Mapping Symbols, Next: ARM Unwinding Tutorial, Prev: ARM Opcodes, Up: ARM-Dependent
7507 9.4.6 Mapping Symbols
7508 ---------------------
7510 The ARM ELF specification requires that special symbols be inserted
7511 into object files to mark certain features:
7514 At the start of a region of code containing ARM instructions.
7517 At the start of a region of code containing THUMB instructions.
7520 At the start of a region of data.
7523 The assembler will automatically insert these symbols for you - there
7524 is no need to code them yourself. Support for tagging symbols ($b, $f,
7525 $p and $m) which is also mentioned in the current ARM ELF specification
7526 is not implemented. This is because they have been dropped from the
7527 new EABI and so tools cannot rely upon their presence.
7530 File: as.info, Node: ARM Unwinding Tutorial, Prev: ARM Mapping Symbols, Up: ARM-Dependent
7535 The ABI for the ARM Architecture specifies a standard format for
7536 exception unwind information. This information is used when an
7537 exception is thrown to determine where control should be transferred.
7538 In particular, the unwind information is used to determine which
7539 function called the function that threw the exception, and which
7540 function called that one, and so forth. This information is also used
7541 to restore the values of callee-saved registers in the function
7542 catching the exception.
7544 If you are writing functions in assembly code, and those functions
7545 call other functions that throw exceptions, you must use assembly
7546 pseudo ops to ensure that appropriate exception unwind information is
7547 generated. Otherwise, if one of the functions called by your assembly
7548 code throws an exception, the run-time library will be unable to unwind
7549 the stack through your assembly code and your program will not behave
7552 To illustrate the use of these pseudo ops, we will examine the code
7553 that G++ generates for the following C++ input:
7556 void callee (int *);
7566 This example does not show how to throw or catch an exception from
7567 assembly code. That is a much more complex operation and should always
7568 be done in a high-level language, such as C++, that directly supports
7571 The code generated by one particular version of G++ when compiling
7572 the example above is:
7578 @ Function supports interworking.
7579 @ args = 0, pretend = 0, frame = 8
7580 @ frame_needed = 1, uses_anonymous_args = 0
7601 Of course, the sequence of instructions varies based on the options
7602 you pass to GCC and on the version of GCC in use. The exact
7603 instructions are not important since we are focusing on the pseudo ops
7604 that are used to generate unwind information.
7606 An important assumption made by the unwinder is that the stack frame
7607 does not change during the body of the function. In particular, since
7608 we assume that the assembly code does not itself throw an exception,
7609 the only point where an exception can be thrown is from a call, such as
7610 the `bl' instruction above. At each call site, the same saved
7611 registers (including `lr', which indicates the return address) must be
7612 located in the same locations relative to the frame pointer.
7614 The `.fnstart' (*note .fnstart pseudo op: arm_fnstart.) pseudo op
7615 appears immediately before the first instruction of the function while
7616 the `.fnend' (*note .fnend pseudo op: arm_fnend.) pseudo op appears
7617 immediately after the last instruction of the function. These pseudo
7618 ops specify the range of the function.
7620 Only the order of the other pseudos ops (e.g., `.setfp' or `.pad')
7621 matters; their exact locations are irrelevant. In the example above,
7622 the compiler emits the pseudo ops with particular instructions. That
7623 makes it easier to understand the code, but it is not required for
7624 correctness. It would work just as well to emit all of the pseudo ops
7625 other than `.fnend' in the same order, but immediately after `.fnstart'.
7627 The `.save' (*note .save pseudo op: arm_save.) pseudo op indicates
7628 registers that have been saved to the stack so that they can be
7629 restored before the function returns. The argument to the `.save'
7630 pseudo op is a list of registers to save. If a register is
7631 "callee-saved" (as specified by the ABI) and is modified by the
7632 function you are writing, then your code must save the value before it
7633 is modified and restore the original value before the function returns.
7634 If an exception is thrown, the run-time library restores the values of
7635 these registers from their locations on the stack before returning
7636 control to the exception handler. (Of course, if an exception is not
7637 thrown, the function that contains the `.save' pseudo op restores these
7638 registers in the function epilogue, as is done with the `ldmfd'
7641 You do not have to save callee-saved registers at the very beginning
7642 of the function and you do not need to use the `.save' pseudo op
7643 immediately following the point at which the registers are saved.
7644 However, if you modify a callee-saved register, you must save it on the
7645 stack before modifying it and before calling any functions which might
7646 throw an exception. And, you must use the `.save' pseudo op to
7647 indicate that you have done so.
7649 The `.pad' (*note .pad: arm_pad.) pseudo op indicates a modification
7650 of the stack pointer that does not save any registers. The argument is
7651 the number of bytes (in decimal) that are subtracted from the stack
7652 pointer. (On ARM CPUs, the stack grows downwards, so subtracting from
7653 the stack pointer increases the size of the stack.)
7655 The `.setfp' (*note .setfp pseudo op: arm_setfp.) pseudo op
7656 indicates the register that contains the frame pointer. The first
7657 argument is the register that is set, which is typically `fp'. The
7658 second argument indicates the register from which the frame pointer
7659 takes its value. The third argument, if present, is the value (in
7660 decimal) added to the register specified by the second argument to
7661 compute the value of the frame pointer. You should not modify the
7662 frame pointer in the body of the function.
7664 If you do not use a frame pointer, then you should not use the
7665 `.setfp' pseudo op. If you do not use a frame pointer, then you should
7666 avoid modifying the stack pointer outside of the function prologue.
7667 Otherwise, the run-time library will be unable to find saved registers
7668 when it is unwinding the stack.
7670 The pseudo ops described above are sufficient for writing assembly
7671 code that calls functions which may throw exceptions. If you need to
7672 know more about the object-file format used to represent unwind
7673 information, you may consult the `Exception Handling ABI for the ARM
7674 Architecture' available from `http://infocenter.arm.com'.
7677 File: as.info, Node: AVR-Dependent, Next: Blackfin-Dependent, Prev: ARM-Dependent, Up: Machine Dependencies
7679 9.5 AVR Dependent Features
7680 ==========================
7684 * AVR Options:: Options
7685 * AVR Syntax:: Syntax
7686 * AVR Opcodes:: Opcodes
7689 File: as.info, Node: AVR Options, Next: AVR Syntax, Up: AVR-Dependent
7695 Specify ATMEL AVR instruction set or MCU type.
7697 Instruction set avr1 is for the minimal AVR core, not supported by
7698 the C compiler, only for assembler programs (MCU types: at90s1200,
7699 attiny11, attiny12, attiny15, attiny28).
7701 Instruction set avr2 (default) is for the classic AVR core with up
7702 to 8K program memory space (MCU types: at90s2313, at90s2323,
7703 at90s2333, at90s2343, attiny22, attiny26, at90s4414, at90s4433,
7704 at90s4434, at90s8515, at90c8534, at90s8535).
7706 Instruction set avr25 is for the classic AVR core with up to 8K
7707 program memory space plus the MOVW instruction (MCU types:
7708 attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a,
7709 attiny4313, attiny44, attiny44a, attiny84, attiny84a, attiny25,
7710 attiny45, attiny85, attiny261, attiny261a, attiny461, attiny461a,
7711 attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88,
7712 attiny828, at86rf401, ata6289, ata5272).
7714 Instruction set avr3 is for the classic AVR core with up to 128K
7715 program memory space (MCU types: at43usb355, at76c711).
7717 Instruction set avr31 is for the classic AVR core with exactly
7718 128K program memory space (MCU types: atmega103, at43usb320).
7720 Instruction set avr35 is for classic AVR core plus MOVW, CALL, and
7721 JMP instructions (MCU types: attiny167, attiny1634, at90usb82,
7722 at90usb162, atmega8u2, atmega16u2, atmega32u2, ata5505).
7724 Instruction set avr4 is for the enhanced AVR core with up to 8K
7725 program memory space (MCU types: atmega48, atmega48a, atmega48pa,
7726 atmega48p, atmega8, atmega8a, atmega88, atmega88a, atmega88p,
7727 atmega88pa, atmega8515, atmega8535, atmega8hva, at90pwm1,
7728 at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, ata6285,
7731 Instruction set avr5 is for the enhanced AVR core with up to 128K
7732 program memory space (MCU types: at90pwm161, atmega16, atmega16a,
7733 atmega161, atmega162, atmega163, atmega164a, atmega164p,
7734 atmega164pa, atmega165, atmega165a, atmega165p, atmega165pa,
7735 atmega168, atmega168a, atmega168p, atmega168pa, atmega169,
7736 atmega169a, atmega169p, atmega169pa, atmega32, atmega323,
7737 atmega324a, atmega324p, atmega324pa, atmega325, atmega325a,
7738 atmega32, atmega32a, atmega323, atmega324a, atmega324p,
7739 atmega324pa, atmega325, atmega325a, atmega325p, atmega325p,
7740 atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa,
7741 atmega328, atmega328p, atmega329, atmega329a, atmega329p,
7742 atmega329pa, atmega3290a, atmega3290p, atmega3290pa, atmega406,
7743 atmega64, atmega64a, atmega64rfr2, atmega644rfr2, atmega640,
7744 atmega644, atmega644a, atmega644p, atmega644pa, atmega645,
7745 atmega645a, atmega645p, atmega6450, atmega6450a, atmega6450p,
7746 atmega649, atmega649a, atmega649p, atmega6490, atmega6490a,
7747 atmega6490p, atmega16hva, atmega16hva2, atmega16hvb,
7748 atmega16hvbrevb, atmega32hvb, atmega32hvbrevb, atmega64hve,
7749 at90can32, at90can64, at90pwm161, at90pwm216, at90pwm316,
7750 atmega32c1, atmega64c1, atmega16m1, atmega32m1, atmega64m1,
7751 atmega16u4, atmega32u4, atmega32u6, at90usb646, at90usb647, at94k,
7752 at90scr100, ata5790, ata5795).
7754 Instruction set avr51 is for the enhanced AVR core with exactly
7755 128K program memory space (MCU types: atmega128, atmega128a,
7756 atmega1280, atmega1281, atmega1284, atmega1284p, atmega128rfa1,
7757 atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286,
7758 at90usb1287, m3000).
7760 Instruction set avr6 is for the enhanced AVR core with a 3-byte PC
7761 (MCU types: atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2).
7763 Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K
7764 program memory space and less than 64K data space (MCU types:
7765 atxmega16a4, atxmega16a4u, atxmega16c4, atxmega16d4, atxmega16x1,
7766 atxmega32a4, atxmega32a4u, atxmega32c4, atxmega32d4, atxmega16e5,
7767 atxmega8e5, atxmega32e5, atxmega32x1).
7769 Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K
7770 program memory space and greater than 64K data space (MCU types:
7773 Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K
7774 program memory space and less than 64K data space (MCU types:
7775 atxmega64a3, atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3,
7776 atxmega64c3, atxmega64d3, atxmega64d4).
7778 Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K
7779 program memory space and greater than 64K data space (MCU types:
7780 atxmega64a1, atxmega64a1u).
7782 Instruction set avrxmega6 is for the XMEGA AVR core with larger
7783 than 64K program memory space and less than 64K data space (MCU
7784 types: atxmega128a3, atxmega128a3u, atxmega128c3, atxmega128d3,
7785 atxmega128d4, atxmega192a3, atxmega192a3u, atxmega128b1,
7786 atxmega128b3, atxmega192c3, atxmega192d3, atxmega256a3,
7787 atxmega256a3u, atxmega256a3b, atxmega256a3bu, atxmega256c3,
7788 atxmega256d3, atxmega384c3, atxmega256d3).
7790 Instruction set avrxmega7 is for the XMEGA AVR core with larger
7791 than 64K program memory space and greater than 64K data space (MCU
7792 types: atxmega128a1, atxmega128a1u, atxmega128a4u).
7794 Instruction set avrtiny is for the ATtiny4/5/9/10/20/40
7798 Accept all AVR opcodes, even if not supported by `-mmcu'.
7801 This option disable warnings for skipping two-word instructions.
7804 This option reject `rjmp/rcall' instructions with 8K wrap-around.
7807 Accept Read-Modify-Write (`XCH,LAC,LAS,LAT') instructions.
7811 File: as.info, Node: AVR Syntax, Next: AVR Opcodes, Prev: AVR Options, Up: AVR-Dependent
7818 * AVR-Chars:: Special Characters
7819 * AVR-Regs:: Register Names
7820 * AVR-Modifiers:: Relocatable Expression Modifiers
7823 File: as.info, Node: AVR-Chars, Next: AVR-Regs, Up: AVR Syntax
7825 9.5.2.1 Special Characters
7826 ..........................
7828 The presence of a `;' anywhere on a line indicates the start of a
7829 comment that extends to the end of that line.
7831 If a `#' appears as the first character of a line, the whole line is
7832 treated as a comment, but in this case the line can also be a logical
7833 line number directive (*note Comments::) or a preprocessor control
7834 command (*note Preprocessing::).
7836 The `$' character can be used instead of a newline to separate
7840 File: as.info, Node: AVR-Regs, Next: AVR-Modifiers, Prev: AVR-Chars, Up: AVR Syntax
7842 9.5.2.2 Register Names
7843 ......................
7845 The AVR has 32 x 8-bit general purpose working registers `r0', `r1',
7846 ... `r31'. Six of the 32 registers can be used as three 16-bit
7847 indirect address register pointers for Data Space addressing. One of
7848 the these address pointers can also be used as an address pointer for
7849 look up tables in Flash program memory. These added function registers
7850 are the 16-bit `X', `Y' and `Z' - registers.
7857 File: as.info, Node: AVR-Modifiers, Prev: AVR-Regs, Up: AVR Syntax
7859 9.5.2.3 Relocatable Expression Modifiers
7860 ........................................
7862 The assembler supports several modifiers when using relocatable
7863 addresses in AVR instruction operands. The general syntax is the
7866 modifier(relocatable-expression)
7869 This modifier allows you to use bits 0 through 7 of an address
7870 expression as 8 bit relocatable expression.
7873 This modifier allows you to use bits 7 through 15 of an address
7874 expression as 8 bit relocatable expression. This is useful with,
7875 for example, the AVR `ldi' instruction and `lo8' modifier.
7879 ldi r26, lo8(sym+10)
7880 ldi r27, hi8(sym+10)
7883 This modifier allows you to use bits 16 through 23 of an address
7884 expression as 8 bit relocatable expression. Also, can be useful
7885 for loading 32 bit constants.
7891 This modifier allows you to use bits 24 through 31 of an
7892 expression as 8 bit expression. This is useful with, for example,
7893 the AVR `ldi' instruction and `lo8', `hi8', `hlo8', `hhi8',
7898 ldi r26, lo8(285774925)
7899 ldi r27, hi8(285774925)
7900 ldi r28, hlo8(285774925)
7901 ldi r29, hhi8(285774925)
7902 ; r29,r28,r27,r26 = 285774925
7905 This modifier allows you to use bits 0 through 7 of an address
7906 expression as 8 bit relocatable expression. This modifier useful
7907 for addressing data or code from Flash/Program memory. The using
7908 of `pm_lo8' similar to `lo8'.
7911 This modifier allows you to use bits 8 through 15 of an address
7912 expression as 8 bit relocatable expression. This modifier useful
7913 for addressing data or code from Flash/Program memory.
7916 This modifier allows you to use bits 15 through 23 of an address
7917 expression as 8 bit relocatable expression. This modifier useful
7918 for addressing data or code from Flash/Program memory.
7922 File: as.info, Node: AVR Opcodes, Prev: AVR Syntax, Up: AVR-Dependent
7927 For detailed information on the AVR machine instruction set, see
7928 `www.atmel.com/products/AVR'.
7930 `as' implements all the standard AVR opcodes. The following table
7931 summarizes the AVR opcodes, and their arguments.
7935 d `ldi' register (r16-r31)
7936 v `movw' even register (r0, r2, ..., r28, r30)
7937 a `fmul' register (r16-r23)
7938 w `adiw' register (r24,r26,r28,r30)
7939 e pointer registers (X,Y,Z)
7940 b base pointer register and displacement ([YZ]+disp)
7941 z Z pointer register (for [e]lpm Rd,Z[+])
7942 M immediate value from 0 to 255
7943 n immediate value from 0 to 255 ( n = ~M ). Relocation impossible
7944 s immediate value from 0 to 7
7945 P Port address value from 0 to 63. (in, out)
7946 p Port address value from 0 to 31. (cbi, sbi, sbic, sbis)
7947 K immediate value from 0 to 63 (used in `adiw', `sbiw')
7949 l signed pc relative offset from -64 to 63
7950 L signed pc relative offset from -2048 to 2047
7951 h absolute code address (call, jmp)
7952 S immediate value from 0 to 7 (S = s << 4)
7953 ? use this opcode entry if no parameters, else use next opcode entry
7955 1001010010001000 clc
7956 1001010011011000 clh
7957 1001010011111000 cli
7958 1001010010101000 cln
7959 1001010011001000 cls
7960 1001010011101000 clt
7961 1001010010111000 clv
7962 1001010010011000 clz
7963 1001010000001000 sec
7964 1001010001011000 seh
7965 1001010001111000 sei
7966 1001010000101000 sen
7967 1001010001001000 ses
7968 1001010001101000 set
7969 1001010000111000 sev
7970 1001010000011000 sez
7971 100101001SSS1000 bclr S
7972 100101000SSS1000 bset S
7973 1001010100001001 icall
7974 1001010000001001 ijmp
7975 1001010111001000 lpm ?
7976 1001000ddddd010+ lpm r,z
7977 1001010111011000 elpm ?
7978 1001000ddddd011+ elpm r,z
7979 0000000000000000 nop
7980 1001010100001000 ret
7981 1001010100011000 reti
7982 1001010110001000 sleep
7983 1001010110011000 break
7984 1001010110101000 wdr
7985 1001010111101000 spm
7986 000111rdddddrrrr adc r,r
7987 000011rdddddrrrr add r,r
7988 001000rdddddrrrr and r,r
7989 000101rdddddrrrr cp r,r
7990 000001rdddddrrrr cpc r,r
7991 000100rdddddrrrr cpse r,r
7992 001001rdddddrrrr eor r,r
7993 001011rdddddrrrr mov r,r
7994 100111rdddddrrrr mul r,r
7995 001010rdddddrrrr or r,r
7996 000010rdddddrrrr sbc r,r
7997 000110rdddddrrrr sub r,r
7998 001001rdddddrrrr clr r
7999 000011rdddddrrrr lsl r
8000 000111rdddddrrrr rol r
8001 001000rdddddrrrr tst r
8002 0111KKKKddddKKKK andi d,M
8003 0111KKKKddddKKKK cbr d,n
8004 1110KKKKddddKKKK ldi d,M
8005 11101111dddd1111 ser d
8006 0110KKKKddddKKKK ori d,M
8007 0110KKKKddddKKKK sbr d,M
8008 0011KKKKddddKKKK cpi d,M
8009 0100KKKKddddKKKK sbci d,M
8010 0101KKKKddddKKKK subi d,M
8011 1111110rrrrr0sss sbrc r,s
8012 1111111rrrrr0sss sbrs r,s
8013 1111100ddddd0sss bld r,s
8014 1111101ddddd0sss bst r,s
8015 10110PPdddddPPPP in r,P
8016 10111PPrrrrrPPPP out P,r
8017 10010110KKddKKKK adiw w,K
8018 10010111KKddKKKK sbiw w,K
8019 10011000pppppsss cbi p,s
8020 10011010pppppsss sbi p,s
8021 10011001pppppsss sbic p,s
8022 10011011pppppsss sbis p,s
8023 111101lllllll000 brcc l
8024 111100lllllll000 brcs l
8025 111100lllllll001 breq l
8026 111101lllllll100 brge l
8027 111101lllllll101 brhc l
8028 111100lllllll101 brhs l
8029 111101lllllll111 brid l
8030 111100lllllll111 brie l
8031 111100lllllll000 brlo l
8032 111100lllllll100 brlt l
8033 111100lllllll010 brmi l
8034 111101lllllll001 brne l
8035 111101lllllll010 brpl l
8036 111101lllllll000 brsh l
8037 111101lllllll110 brtc l
8038 111100lllllll110 brts l
8039 111101lllllll011 brvc l
8040 111100lllllll011 brvs l
8041 111101lllllllsss brbc s,l
8042 111100lllllllsss brbs s,l
8043 1101LLLLLLLLLLLL rcall L
8044 1100LLLLLLLLLLLL rjmp L
8045 1001010hhhhh111h call h
8046 1001010hhhhh110h jmp h
8047 1001010rrrrr0101 asr r
8048 1001010rrrrr0000 com r
8049 1001010rrrrr1010 dec r
8050 1001010rrrrr0011 inc r
8051 1001010rrrrr0110 lsr r
8052 1001010rrrrr0001 neg r
8053 1001000rrrrr1111 pop r
8054 1001001rrrrr1111 push r
8055 1001010rrrrr0111 ror r
8056 1001010rrrrr0010 swap r
8057 00000001ddddrrrr movw v,v
8058 00000010ddddrrrr muls d,d
8059 000000110ddd0rrr mulsu a,a
8060 000000110ddd1rrr fmul a,a
8061 000000111ddd0rrr fmuls a,a
8062 000000111ddd1rrr fmulsu a,a
8063 1001001ddddd0000 sts i,r
8064 1001000ddddd0000 lds r,i
8065 10o0oo0dddddbooo ldd r,b
8066 100!000dddddee-+ ld r,e
8067 10o0oo1rrrrrbooo std b,r
8068 100!001rrrrree-+ st e,r
8069 1001010100011001 eicall
8070 1001010000011001 eijmp
8073 File: as.info, Node: Blackfin-Dependent, Next: CR16-Dependent, Prev: AVR-Dependent, Up: Machine Dependencies
8075 9.6 Blackfin Dependent Features
8076 ===============================
8080 * Blackfin Options:: Blackfin Options
8081 * Blackfin Syntax:: Blackfin Syntax
8082 * Blackfin Directives:: Blackfin Directives
8085 File: as.info, Node: Blackfin Options, Next: Blackfin Syntax, Up: Blackfin-Dependent
8090 `-mcpu=PROCESSOR[-SIREVISION]'
8091 This option specifies the target processor. The optional
8092 SIREVISION is not used in assembler. It's here such that GCC can
8093 easily pass down its `-mcpu=' option. The assembler will issue an
8094 error message if an attempt is made to assemble an instruction
8095 which will not execute on the target processor. The following
8096 processor names are recognized: `bf504', `bf506', `bf512', `bf514',
8097 `bf516', `bf518', `bf522', `bf523', `bf524', `bf525', `bf526',
8098 `bf527', `bf531', `bf532', `bf533', `bf534', `bf535' (not
8099 implemented yet), `bf536', `bf537', `bf538', `bf539', `bf542',
8100 `bf542m', `bf544', `bf544m', `bf547', `bf547m', `bf548', `bf548m',
8101 `bf549', `bf549m', `bf561', and `bf592'.
8104 Assemble for the FDPIC ABI.
8111 File: as.info, Node: Blackfin Syntax, Next: Blackfin Directives, Prev: Blackfin Options, Up: Blackfin-Dependent
8116 `Special Characters'
8117 Assembler input is free format and may appear anywhere on the line.
8118 One instruction may extend across multiple lines or more than one
8119 instruction may appear on the same line. White space (space, tab,
8120 comments or newline) may appear anywhere between tokens. A token
8121 must not have embedded spaces. Tokens include numbers, register
8122 names, keywords, user identifiers, and also some multicharacter
8123 special symbols like "+=", "/*" or "||".
8125 Comments are introduced by the `#' character and extend to the end
8126 of the current line. If the `#' appears as the first character of
8127 a line, the whole line is treated as a comment, but in this case
8128 the line can also be a logical line number directive (*note
8129 Comments::) or a preprocessor control command (*note
8132 `Instruction Delimiting'
8133 A semicolon must terminate every instruction. Sometimes a complete
8134 instruction will consist of more than one operation. There are two
8135 cases where this occurs. The first is when two general operations
8136 are combined. Normally a comma separates the different parts, as
8139 a0= r3.h * r2.l, a1 = r3.l * r2.h ;
8141 The second case occurs when a general instruction is combined with
8142 one or two memory references for joint issue. The latter portions
8143 are set off by a "||" token.
8145 a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
8147 Multiple instructions can occur on the same line. Each must be
8148 terminated by a semicolon character.
8151 The assembler treats register names and instruction keywords in a
8152 case insensitive manner. User identifiers are case sensitive.
8153 Thus, R3.l, R3.L, r3.l and r3.L are all equivalent input to the
8156 Register names are reserved and may not be used as program
8159 Some operations (such as "Move Register") require a register pair.
8160 Register pairs are always data registers and are denoted using a
8161 colon, eg., R3:2. The larger number must be written firsts. Note
8162 that the hardware only supports odd-even pairs, eg., R7:6, R5:4,
8165 Some instructions (such as -SP (Push Multiple)) require a group of
8166 adjacent registers. Adjacent registers are denoted in the syntax
8167 by the range enclosed in parentheses and separated by a colon,
8168 eg., (R7:3). Again, the larger number appears first.
8170 Portions of a particular register may be individually specified.
8171 This is written with a dot (".") following the register name and
8172 then a letter denoting the desired portion. For 32-bit registers,
8173 ".H" denotes the most significant ("High") portion. ".L" denotes
8174 the least-significant portion. The subdivisions of the 40-bit
8175 registers are described later.
8178 The set of 40-bit registers A1 and A0 that normally contain data
8179 that is being manipulated. Each accumulator can be accessed in
8182 `one 40-bit register'
8183 The register will be referred to as A1 or A0.
8185 `one 32-bit register'
8186 The registers are designated as A1.W or A0.W.
8188 `two 16-bit registers'
8189 The registers are designated as A1.H, A1.L, A0.H or A0.L.
8191 `one 8-bit register'
8192 The registers are designated as A1.X or A0.X for the bits that
8193 extend beyond bit 31.
8196 The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7)
8197 that normally contain data for manipulation. These are
8198 abbreviated as D-register or Dreg. Data registers can be accessed
8199 as 32-bit registers or as two independent 16-bit registers. The
8200 least significant 16 bits of each register is called the "low"
8201 half and is designated with ".L" following the register name. The
8202 most significant 16 bits are called the "high" half and is
8203 designated with ".H" following the name.
8205 R7.L, r2.h, r4.L, R0.H
8208 The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP)
8209 that normally contain byte addresses of data structures. These are
8210 abbreviated as P-register or Preg.
8215 The stack pointer contains the 32-bit address of the last occupied
8216 byte location in the stack. The stack grows by decrementing the
8220 The frame pointer contains the 32-bit address of the previous frame
8221 pointer in the stack. It is located at the top of a frame.
8224 LT0 and LT1. These registers contain the 32-bit address of the
8225 top of a zero overhead loop.
8228 LC0 and LC1. These registers contain the 32-bit counter of the
8229 zero overhead loop executions.
8232 LB0 and LB1. These registers contain the 32-bit address of the
8233 bottom of a zero overhead loop.
8236 The set of 32-bit registers (I0, I1, I2, I3) that normally contain
8237 byte addresses of data structures. Abbreviated I-register or Ireg.
8240 The set of 32-bit registers (M0, M1, M2, M3) that normally contain
8241 offset values that are added and subtracted to one of the index
8242 registers. Abbreviated as Mreg.
8245 The set of 32-bit registers (L0, L1, L2, L3) that normally contain
8246 the length in bytes of the circular buffer. Abbreviated as Lreg.
8247 Clear the Lreg to disable circular addressing for the
8251 The set of 32-bit registers (B0, B1, B2, B3) that normally contain
8252 the base address in bytes of the circular buffer. Abbreviated as
8256 The Blackfin family has no hardware floating point but the .float
8257 directive generates ieee floating point numbers for use with
8258 software floating point libraries.
8261 For detailed information on the Blackfin machine instruction set,
8262 see the Blackfin(r) Processor Instruction Set Reference.
8266 File: as.info, Node: Blackfin Directives, Prev: Blackfin Syntax, Up: Blackfin-Dependent
8271 The following directives are provided for compatibility with the VDSP
8275 Initializes a two byte data object.
8277 This maps to the `.short' directive.
8280 Initializes a four byte data object.
8282 This maps to the `.int' directive.
8285 Initializes a single byte data object.
8287 This directive is a synonym for `.byte'.
8290 Initializes a two byte data object.
8292 This directive is a synonym for `.byte2'.
8295 Initializes a four byte data object.
8297 This directive is a synonym for `.byte4'.
8300 Define and initialize a 32 bit data object.
8303 File: as.info, Node: CR16-Dependent, Next: CRIS-Dependent, Prev: Blackfin-Dependent, Up: Machine Dependencies
8305 9.7 CR16 Dependent Features
8306 ===========================
8310 * CR16 Operand Qualifiers:: CR16 Machine Operand Qualifiers
8311 * CR16 Syntax:: Syntax for the CR16
8314 File: as.info, Node: CR16 Operand Qualifiers, Next: CR16 Syntax, Up: CR16-Dependent
8316 9.7.1 CR16 Operand Qualifiers
8317 -----------------------------
8319 The National Semiconductor CR16 target of `as' has a few machine
8320 dependent operand qualifiers.
8322 Operand expression type qualifier is an optional field in the
8323 instruction operand, to determines the type of the expression field of
8324 an operand. The `@' is required. CR16 architecture uses one of the
8325 following expression qualifiers:
8328 - `Specifies expression operand type as small'
8331 - `Specifies expression operand type as medium'
8334 - `Specifies expression operand type as large'
8337 - `Specifies the CR16 Assembler generates a relocation entry for
8338 the operand, where pc has implied bit, the expression is adjusted
8339 accordingly. The linker uses the relocation entry to update the
8340 operand address at link time.'
8343 - `Specifies the CR16 Assembler generates a relocation entry for
8344 the operand, offset from Global Offset Table. The linker uses this
8345 relocation entry to update the operand address at link time'
8348 - `Specifies the CompactRISC Assembler generates a relocation
8349 entry for the operand, where pc has implied bit, the expression is
8350 adjusted accordingly. The linker uses the relocation entry to
8351 update the operand address at link time.'
8353 CR16 target operand qualifiers and its size (in bits):
8355 `Immediate Operand: s'
8358 `Immediate Operand: m'
8359 16 bits, for movb and movw instructions.
8361 `Immediate Operand: m'
8362 20 bits, movd instructions.
8364 `Immediate Operand: l'
8367 `Absolute Operand: s'
8368 Illegal specifier for this operand.
8370 `Absolute Operand: m'
8371 20 bits, movd instructions.
8373 `Displacement Operand: s'
8376 `Displacement Operand: m'
8379 `Displacement Operand: l'
8384 1 `movw $_myfun@c,r1'
8386 This loads the address of _myfun, shifted right by 1, into r1.
8388 2 `movd $_myfun@c,(r2,r1)'
8390 This loads the address of _myfun, shifted right by 1, into register-pair r2-r1.
8394 `loadd _myfun_ptr, (r1,r0)'
8397 This .long directive, the address of _myfunc, shifted right by 1 at link time.
8399 4 `loadd _data1@GOT(r12), (r1,r0)'
8401 This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1.
8403 5 `loadd _myfunc@cGOT(r12), (r1,r0)'
8405 This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0.
8408 File: as.info, Node: CR16 Syntax, Prev: CR16 Operand Qualifiers, Up: CR16-Dependent
8415 * CR16-Chars:: Special Characters
8418 File: as.info, Node: CR16-Chars, Up: CR16 Syntax
8420 9.7.2.1 Special Characters
8421 ..........................
8423 The presence of a `#' on a line indicates the start of a comment that
8424 extends to the end of the current line. If the `#' appears as the
8425 first character of a line, the whole line is treated as a comment, but
8426 in this case the line can also be a logical line number directive
8427 (*note Comments::) or a preprocessor control command (*note
8430 The `;' character can be used to separate statements on the same
8434 File: as.info, Node: CRIS-Dependent, Next: D10V-Dependent, Prev: CR16-Dependent, Up: Machine Dependencies
8436 9.8 CRIS Dependent Features
8437 ===========================
8441 * CRIS-Opts:: Command-line Options
8442 * CRIS-Expand:: Instruction expansion
8443 * CRIS-Symbols:: Symbols
8444 * CRIS-Syntax:: Syntax
8447 File: as.info, Node: CRIS-Opts, Next: CRIS-Expand, Up: CRIS-Dependent
8449 9.8.1 Command-line Options
8450 --------------------------
8452 The CRIS version of `as' has these machine-dependent command-line
8455 The format of the generated object files can be either ELF or a.out,
8456 specified by the command-line options `--emulation=crisaout' and
8457 `--emulation=criself'. The default is ELF (criself), unless `as' has
8458 been configured specifically for a.out by using the configuration name
8461 There are two different link-incompatible ELF object file variants
8462 for CRIS, for use in environments where symbols are expected to be
8463 prefixed by a leading `_' character and for environments without such a
8464 symbol prefix. The variant used for GNU/Linux port has no symbol
8465 prefix. Which variant to produce is specified by either of the options
8466 `--underscore' and `--no-underscore'. The default is `--underscore'.
8467 Since symbols in CRIS a.out objects are expected to have a `_' prefix,
8468 specifying `--no-underscore' when generating a.out objects is an error.
8469 Besides the object format difference, the effect of this option is to
8470 parse register names differently (*note crisnous::). The
8471 `--no-underscore' option makes a `$' register prefix mandatory.
8473 The option `--pic' must be passed to `as' in order to recognize the
8474 symbol syntax used for ELF (SVR4 PIC) position-independent-code (*note
8475 crispic::). This will also affect expansion of instructions. The
8476 expansion with `--pic' will use PC-relative rather than (slightly
8477 faster) absolute addresses in those expansions. This option is only
8478 valid when generating ELF format object files.
8480 The option `--march=ARCHITECTURE' specifies the recognized
8481 instruction set and recognized register names. It also controls the
8482 architecture type of the object file. Valid values for ARCHITECTURE
8485 All instructions and register names for any architecture variant
8486 in the set v0...v10 are recognized. This is the default if the
8487 target is configured as cris-*.
8490 Only instructions and register names for CRIS v10 (as found in
8491 ETRAX 100 LX) are recognized. This is the default if the target
8492 is configured as crisv10-*.
8495 Only instructions and register names for CRIS v32 (code name
8496 Guinness) are recognized. This is the default if the target is
8497 configured as crisv32-*. This value implies `--no-mul-bug-abort'.
8498 (A subsequent `--mul-bug-abort' will turn it back on.)
8501 Only instructions with register names and addressing modes with
8502 opcodes common to the v10 and v32 are recognized.
8504 When `-N' is specified, `as' will emit a warning when a 16-bit
8505 branch instruction is expanded into a 32-bit multiple-instruction
8506 construct (*note CRIS-Expand::).
8508 Some versions of the CRIS v10, for example in the Etrax 100 LX,
8509 contain a bug that causes destabilizing memory accesses when a multiply
8510 instruction is executed with certain values in the first operand just
8511 before a cache-miss. When the `--mul-bug-abort' command line option is
8512 active (the default value), `as' will refuse to assemble a file
8513 containing a multiply instruction at a dangerous offset, one that could
8514 be the last on a cache-line, or is in a section with insufficient
8515 alignment. This placement checking does not catch any case where the
8516 multiply instruction is dangerously placed because it is located in a
8517 delay-slot. The `--mul-bug-abort' command line option turns off the
8521 File: as.info, Node: CRIS-Expand, Next: CRIS-Symbols, Prev: CRIS-Opts, Up: CRIS-Dependent
8523 9.8.2 Instruction expansion
8524 ---------------------------
8526 `as' will silently choose an instruction that fits the operand size for
8527 `[register+constant]' operands. For example, the offset `127' in
8528 `move.d [r3+127],r4' fits in an instruction using a signed-byte offset.
8529 Similarly, `move.d [r2+32767],r1' will generate an instruction using a
8530 16-bit offset. For symbolic expressions and constants that do not fit
8531 in 16 bits including the sign bit, a 32-bit offset is generated.
8533 For branches, `as' will expand from a 16-bit branch instruction into
8534 a sequence of instructions that can reach a full 32-bit address. Since
8535 this does not correspond to a single instruction, such expansions can
8536 optionally be warned about. *Note CRIS-Opts::.
8538 If the operand is found to fit the range, a `lapc' mnemonic will
8539 translate to a `lapcq' instruction. Use `lapc.d' to force the 32-bit
8542 Similarly, the `addo' mnemonic will translate to the shortest
8543 fitting instruction of `addoq', `addo.w' and `addo.d', when used with a
8544 operand that is a constant known at assembly time.
8547 File: as.info, Node: CRIS-Symbols, Next: CRIS-Syntax, Prev: CRIS-Expand, Up: CRIS-Dependent
8552 Some symbols are defined by the assembler. They're intended to be used
8553 in conditional assembly, for example:
8554 .if ..asm.arch.cris.v32
8556 .elseif ..asm.arch.cris.common_v10_v32
8557 CODE COMMON TO CRIS V32 AND CRIS V10
8558 .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10
8561 .error "Code needs to be added here."
8564 These symbols are defined in the assembler, reflecting command-line
8565 options, either when specified or the default. They are always
8567 `..asm.arch.cris.any_v0_v10'
8568 This symbol is non-zero when `--march=v0_v10' is specified or the
8571 `..asm.arch.cris.common_v10_v32'
8572 Set according to the option `--march=common_v10_v32'.
8574 `..asm.arch.cris.v10'
8575 Reflects the option `--march=v10'.
8577 `..asm.arch.cris.v32'
8578 Corresponds to `--march=v10'.
8580 Speaking of symbols, when a symbol is used in code, it can have a
8581 suffix modifying its value for use in position-independent code. *Note
8585 File: as.info, Node: CRIS-Syntax, Prev: CRIS-Symbols, Up: CRIS-Dependent
8590 There are different aspects of the CRIS assembly syntax.
8594 * CRIS-Chars:: Special Characters
8595 * CRIS-Pic:: Position-Independent Code Symbols
8596 * CRIS-Regs:: Register Names
8597 * CRIS-Pseudos:: Assembler Directives
8600 File: as.info, Node: CRIS-Chars, Next: CRIS-Pic, Up: CRIS-Syntax
8602 9.8.4.1 Special Characters
8603 ..........................
8605 The character `#' is a line comment character. It starts a comment if
8606 and only if it is placed at the beginning of a line.
8608 A `;' character starts a comment anywhere on the line, causing all
8609 characters up to the end of the line to be ignored.
8611 A `@' character is handled as a line separator equivalent to a
8612 logical new-line character (except in a comment), so separate
8613 instructions can be specified on a single line.
8616 File: as.info, Node: CRIS-Pic, Next: CRIS-Regs, Prev: CRIS-Chars, Up: CRIS-Syntax
8618 9.8.4.2 Symbols in position-independent code
8619 ............................................
8621 When generating position-independent code (SVR4 PIC) for use in
8622 cris-axis-linux-gnu or crisv32-axis-linux-gnu shared libraries, symbol
8623 suffixes are used to specify what kind of run-time symbol lookup will
8624 be used, expressed in the object as different _relocation types_.
8625 Usually, all absolute symbol values must be located in a table, the
8626 _global offset table_, leaving the code position-independent;
8627 independent of values of global symbols and independent of the address
8628 of the code. The suffix modifies the value of the symbol, into for
8629 example an index into the global offset table where the real symbol
8630 value is entered, or a PC-relative value, or a value relative to the
8631 start of the global offset table. All symbol suffixes start with the
8632 character `:' (omitted in the list below). Every symbol use in code or
8633 a read-only section must therefore have a PIC suffix to enable a useful
8634 shared library to be created. Usually, these constructs must not be
8635 used with an additive constant offset as is usually allowed, i.e. no 4
8636 as in `symbol + 4' is allowed. This restriction is checked at
8637 link-time, not at assembly-time.
8640 Attaching this suffix to a symbol in an instruction causes the
8641 symbol to be entered into the global offset table. The value is a
8642 32-bit index for that symbol into the global offset table. The
8643 name of the corresponding relocation is `R_CRIS_32_GOT'. Example:
8644 `move.d [$r0+extsym:GOT],$r9'
8647 Same as for `GOT', but the value is a 16-bit index into the global
8648 offset table. The corresponding relocation is `R_CRIS_16_GOT'.
8649 Example: `move.d [$r0+asymbol:GOT16],$r10'
8652 This suffix is used for function symbols. It causes a _procedure
8653 linkage table_, an array of code stubs, to be created at the time
8654 the shared object is created or linked against, together with a
8655 global offset table entry. The value is a pc-relative offset to
8656 the corresponding stub code in the procedure linkage table. This
8657 arrangement causes the run-time symbol resolver to be called to
8658 look up and set the value of the symbol the first time the
8659 function is called (at latest; depending environment variables).
8660 It is only safe to leave the symbol unresolved this way if all
8661 references are function calls. The name of the relocation is
8662 `R_CRIS_32_PLT_PCREL'. Example: `add.d fnname:PLT,$pc'
8665 Like PLT, but the value is relative to the beginning of the global
8666 offset table. The relocation is `R_CRIS_32_PLT_GOTREL'. Example:
8667 `move.d fnname:PLTG,$r3'
8670 Similar to `PLT', but the value of the symbol is a 32-bit index
8671 into the global offset table. This is somewhat of a mix between
8672 the effect of the `GOT' and the `PLT' suffix; the difference to
8673 `GOT' is that there will be a procedure linkage table entry
8674 created, and that the symbol is assumed to be a function entry and
8675 will be resolved by the run-time resolver as with `PLT'. The
8676 relocation is `R_CRIS_32_GOTPLT'. Example: `jsr
8677 [$r0+fnname:GOTPLT]'
8680 A variant of `GOTPLT' giving a 16-bit value. Its relocation name
8681 is `R_CRIS_16_GOTPLT'. Example: `jsr [$r0+fnname:GOTPLT16]'
8684 This suffix must only be attached to a local symbol, but may be
8685 used in an expression adding an offset. The value is the address
8686 of the symbol relative to the start of the global offset table.
8687 The relocation name is `R_CRIS_32_GOTREL'. Example: `move.d
8688 [$r0+localsym:GOTOFF],r3'
8691 File: as.info, Node: CRIS-Regs, Next: CRIS-Pseudos, Prev: CRIS-Pic, Up: CRIS-Syntax
8693 9.8.4.3 Register names
8694 ......................
8696 A `$' character may always prefix a general or special register name in
8697 an instruction operand but is mandatory when the option
8698 `--no-underscore' is specified or when the `.syntax register_prefix'
8699 directive is in effect (*note crisnous::). Register names are
8703 File: as.info, Node: CRIS-Pseudos, Prev: CRIS-Regs, Up: CRIS-Syntax
8705 9.8.4.4 Assembler Directives
8706 ............................
8708 There are a few CRIS-specific pseudo-directives in addition to the
8709 generic ones. *Note Pseudo Ops::. Constants emitted by
8710 pseudo-directives are in little-endian order for CRIS. There is no
8711 support for floating-point-specific directives for CRIS.
8713 `.dword EXPRESSIONS'
8714 The `.dword' directive is a synonym for `.int', expecting zero or
8715 more EXPRESSIONS, separated by commas. For each expression, a
8716 32-bit little-endian constant is emitted.
8719 The `.syntax' directive takes as ARGUMENT one of the following
8720 case-sensitive choices.
8722 `no_register_prefix'
8723 The `.syntax no_register_prefix' directive makes a `$'
8724 character prefix on all registers optional. It overrides a
8725 previous setting, including the corresponding effect of the
8726 option `--no-underscore'. If this directive is used when
8727 ordinary symbols do not have a `_' character prefix, care
8728 must be taken to avoid ambiguities whether an operand is a
8729 register or a symbol; using symbols with names the same as
8730 general or special registers then invoke undefined behavior.
8733 This directive makes a `$' character prefix on all registers
8734 mandatory. It overrides a previous setting, including the
8735 corresponding effect of the option `--underscore'.
8737 `leading_underscore'
8738 This is an assertion directive, emitting an error if the
8739 `--no-underscore' option is in effect.
8741 `no_leading_underscore'
8742 This is the opposite of the `.syntax leading_underscore'
8743 directive and emits an error if the option `--underscore' is
8747 This is an assertion directive, giving an error if the specified
8748 ARGUMENT is not the same as the specified or default value for the
8749 `--march=ARCHITECTURE' option (*note march-option::).
8753 File: as.info, Node: D10V-Dependent, Next: D30V-Dependent, Prev: CRIS-Dependent, Up: Machine Dependencies
8755 9.9 D10V Dependent Features
8756 ===========================
8760 * D10V-Opts:: D10V Options
8761 * D10V-Syntax:: Syntax
8762 * D10V-Float:: Floating Point
8763 * D10V-Opcodes:: Opcodes
8766 File: as.info, Node: D10V-Opts, Next: D10V-Syntax, Up: D10V-Dependent
8771 The Mitsubishi D10V version of `as' has a few machine dependent options.
8774 The D10V can often execute two sub-instructions in parallel. When
8775 this option is used, `as' will attempt to optimize its output by
8776 detecting when instructions can be executed in parallel.
8779 To optimize execution performance, `as' will sometimes swap the
8780 order of instructions. Normally this generates a warning. When
8781 this option is used, no warning will be generated when
8782 instructions are swapped.
8785 `--no-gstabs-packing'
8786 `as' packs adjacent short instructions into a single packed
8787 instruction. `--no-gstabs-packing' turns instruction packing off if
8788 `--gstabs' is specified as well; `--gstabs-packing' (the default)
8789 turns instruction packing on even when `--gstabs' is specified.
8792 File: as.info, Node: D10V-Syntax, Next: D10V-Float, Prev: D10V-Opts, Up: D10V-Dependent
8797 The D10V syntax is based on the syntax in Mitsubishi's D10V
8798 architecture manual. The differences are detailed below.
8802 * D10V-Size:: Size Modifiers
8803 * D10V-Subs:: Sub-Instructions
8804 * D10V-Chars:: Special Characters
8805 * D10V-Regs:: Register Names
8806 * D10V-Addressing:: Addressing Modes
8807 * D10V-Word:: @WORD Modifier
8810 File: as.info, Node: D10V-Size, Next: D10V-Subs, Up: D10V-Syntax
8812 9.9.2.1 Size Modifiers
8813 ......................
8815 The D10V version of `as' uses the instruction names in the D10V
8816 Architecture Manual. However, the names in the manual are sometimes
8817 ambiguous. There are instruction names that can assemble to a short or
8818 long form opcode. How does the assembler pick the correct form? `as'
8819 will always pick the smallest form if it can. When dealing with a
8820 symbol that is not defined yet when a line is being assembled, it will
8821 always use the long form. If you need to force the assembler to use
8822 either the short or long form of the instruction, you can append either
8823 `.s' (short) or `.l' (long) to it. For example, if you are writing an
8824 assembly program and you want to do a branch to a symbol that is
8825 defined later in your program, you can write `bra.s foo'. Objdump
8826 and GDB will always append `.s' or `.l' to instructions which have both
8827 short and long forms.
8830 File: as.info, Node: D10V-Subs, Next: D10V-Chars, Prev: D10V-Size, Up: D10V-Syntax
8832 9.9.2.2 Sub-Instructions
8833 ........................
8835 The D10V assembler takes as input a series of instructions, either
8836 one-per-line, or in the special two-per-line format described in the
8837 next section. Some of these instructions will be short-form or
8838 sub-instructions. These sub-instructions can be packed into a single
8839 instruction. The assembler will do this automatically. It will also
8840 detect when it should not pack instructions. For example, when a label
8841 is defined, the next instruction will never be packaged with the
8842 previous one. Whenever a branch and link instruction is called, it
8843 will not be packaged with the next instruction so the return address
8844 will be valid. Nops are automatically inserted when necessary.
8846 If you do not want the assembler automatically making these
8847 decisions, you can control the packaging and execution type (parallel
8848 or sequential) with the special execution symbols described in the next
8852 File: as.info, Node: D10V-Chars, Next: D10V-Regs, Prev: D10V-Subs, Up: D10V-Syntax
8854 9.9.2.3 Special Characters
8855 ..........................
8857 A semicolon (`;') can be used anywhere on a line to start a comment
8858 that extends to the end of the line.
8860 If a `#' appears as the first character of a line, the whole line is
8861 treated as a comment, but in this case the line could also be a logical
8862 line number directive (*note Comments::) or a preprocessor control
8863 command (*note Preprocessing::).
8865 Sub-instructions may be executed in order, in reverse-order, or in
8866 parallel. Instructions listed in the standard one-per-line format will
8867 be executed sequentially. To specify the executing order, use the
8870 Sequential with instruction on the left first.
8873 Sequential with instruction on the right first.
8877 The D10V syntax allows either one instruction per line, one
8878 instruction per line with the execution symbol, or two instructions per
8881 Execute these sequentially. The instruction on the right is in
8882 the right container and is executed second.
8885 Execute these reverse-sequentially. The instruction on the right
8886 is in the right container, and is executed first.
8888 `ld2w r2,@r8+ || mac a0,r0,r7'
8889 Execute these in parallel.
8893 Two-line format. Execute these in parallel.
8897 Two-line format. Execute these sequentially. Assembler will put
8898 them in the proper containers.
8902 Two-line format. Execute these sequentially. Same as above but
8903 second instruction will always go into right container.
8904 Since `$' has no special meaning, you may use it in symbol names.
8907 File: as.info, Node: D10V-Regs, Next: D10V-Addressing, Prev: D10V-Chars, Up: D10V-Syntax
8909 9.9.2.4 Register Names
8910 ......................
8912 You can use the predefined symbols `r0' through `r15' to refer to the
8913 D10V registers. You can also use `sp' as an alias for `r15'. The
8914 accumulators are `a0' and `a1'. There are special register-pair names
8915 that may optionally be used in opcodes that require even-numbered
8916 registers. Register names are not case sensitive.
8935 The D10V also has predefined symbols for these control registers and
8938 Processor Status Word
8941 Backup Processor Status Word
8947 Backup Program Counter
8953 Repeat Start address
8959 Modulo Start address
8965 Instruction Break Address
8977 File: as.info, Node: D10V-Addressing, Next: D10V-Word, Prev: D10V-Regs, Up: D10V-Syntax
8979 9.9.2.5 Addressing Modes
8980 ........................
8982 `as' understands the following addressing modes for the D10V. `RN' in
8983 the following refers to any of the numbered registers, but _not_ the
8992 Register indirect with post-increment
8995 Register indirect with post-decrement
8998 Register indirect with pre-decrement
9001 Register indirect with displacement
9004 PC relative address (for branch or rep).
9007 Immediate data (the `#' is optional and ignored)
9010 File: as.info, Node: D10V-Word, Prev: D10V-Addressing, Up: D10V-Syntax
9012 9.9.2.6 @WORD Modifier
9013 ......................
9015 Any symbol followed by `@word' will be replaced by the symbol's value
9016 shifted right by 2. This is used in situations such as loading a
9017 register with the address of a function (or any other code fragment).
9018 For example, if you want to load a register with the location of the
9019 function `main' then jump to that function, you could do it as follows:
9024 File: as.info, Node: D10V-Float, Next: D10V-Opcodes, Prev: D10V-Syntax, Up: D10V-Dependent
9026 9.9.3 Floating Point
9027 --------------------
9029 The D10V has no hardware floating point, but the `.float' and `.double'
9030 directives generates IEEE floating-point numbers for compatibility with
9031 other development tools.
9034 File: as.info, Node: D10V-Opcodes, Prev: D10V-Float, Up: D10V-Dependent
9039 For detailed information on the D10V machine instruction set, see `D10V
9040 Architecture: A VLIW Microprocessor for Multimedia Applications'
9041 (Mitsubishi Electric Corp.). `as' implements all the standard D10V
9042 opcodes. The only changes are those described in the section on size
9046 File: as.info, Node: D30V-Dependent, Next: Epiphany-Dependent, Prev: D10V-Dependent, Up: Machine Dependencies
9048 9.10 D30V Dependent Features
9049 ============================
9053 * D30V-Opts:: D30V Options
9054 * D30V-Syntax:: Syntax
9055 * D30V-Float:: Floating Point
9056 * D30V-Opcodes:: Opcodes
9059 File: as.info, Node: D30V-Opts, Next: D30V-Syntax, Up: D30V-Dependent
9064 The Mitsubishi D30V version of `as' has a few machine dependent options.
9067 The D30V can often execute two sub-instructions in parallel. When
9068 this option is used, `as' will attempt to optimize its output by
9069 detecting when instructions can be executed in parallel.
9072 When this option is used, `as' will issue a warning every time it
9073 adds a nop instruction.
9076 When this option is used, `as' will issue a warning if it needs to
9077 insert a nop after a 32-bit multiply before a load or 16-bit
9078 multiply instruction.
9081 File: as.info, Node: D30V-Syntax, Next: D30V-Float, Prev: D30V-Opts, Up: D30V-Dependent
9086 The D30V syntax is based on the syntax in Mitsubishi's D30V
9087 architecture manual. The differences are detailed below.
9091 * D30V-Size:: Size Modifiers
9092 * D30V-Subs:: Sub-Instructions
9093 * D30V-Chars:: Special Characters
9094 * D30V-Guarded:: Guarded Execution
9095 * D30V-Regs:: Register Names
9096 * D30V-Addressing:: Addressing Modes
9099 File: as.info, Node: D30V-Size, Next: D30V-Subs, Up: D30V-Syntax
9101 9.10.2.1 Size Modifiers
9102 .......................
9104 The D30V version of `as' uses the instruction names in the D30V
9105 Architecture Manual. However, the names in the manual are sometimes
9106 ambiguous. There are instruction names that can assemble to a short or
9107 long form opcode. How does the assembler pick the correct form? `as'
9108 will always pick the smallest form if it can. When dealing with a
9109 symbol that is not defined yet when a line is being assembled, it will
9110 always use the long form. If you need to force the assembler to use
9111 either the short or long form of the instruction, you can append either
9112 `.s' (short) or `.l' (long) to it. For example, if you are writing an
9113 assembly program and you want to do a branch to a symbol that is
9114 defined later in your program, you can write `bra.s foo'. Objdump and
9115 GDB will always append `.s' or `.l' to instructions which have both
9116 short and long forms.
9119 File: as.info, Node: D30V-Subs, Next: D30V-Chars, Prev: D30V-Size, Up: D30V-Syntax
9121 9.10.2.2 Sub-Instructions
9122 .........................
9124 The D30V assembler takes as input a series of instructions, either
9125 one-per-line, or in the special two-per-line format described in the
9126 next section. Some of these instructions will be short-form or
9127 sub-instructions. These sub-instructions can be packed into a single
9128 instruction. The assembler will do this automatically. It will also
9129 detect when it should not pack instructions. For example, when a label
9130 is defined, the next instruction will never be packaged with the
9131 previous one. Whenever a branch and link instruction is called, it
9132 will not be packaged with the next instruction so the return address
9133 will be valid. Nops are automatically inserted when necessary.
9135 If you do not want the assembler automatically making these
9136 decisions, you can control the packaging and execution type (parallel
9137 or sequential) with the special execution symbols described in the next
9141 File: as.info, Node: D30V-Chars, Next: D30V-Guarded, Prev: D30V-Subs, Up: D30V-Syntax
9143 9.10.2.3 Special Characters
9144 ...........................
9146 A semicolon (`;') can be used anywhere on a line to start a comment
9147 that extends to the end of the line.
9149 If a `#' appears as the first character of a line, the whole line is
9150 treated as a comment, but in this case the line could also be a logical
9151 line number directive (*note Comments::) or a preprocessor control
9152 command (*note Preprocessing::).
9154 Sub-instructions may be executed in order, in reverse-order, or in
9155 parallel. Instructions listed in the standard one-per-line format will
9156 be executed sequentially unless you use the `-O' option.
9158 To specify the executing order, use the following symbols:
9160 Sequential with instruction on the left first.
9163 Sequential with instruction on the right first.
9168 The D30V syntax allows either one instruction per line, one
9169 instruction per line with the execution symbol, or two instructions per
9171 `abs r2,r3 -> abs r4,r5'
9172 Execute these sequentially. The instruction on the right is in
9173 the right container and is executed second.
9175 `abs r2,r3 <- abs r4,r5'
9176 Execute these reverse-sequentially. The instruction on the right
9177 is in the right container, and is executed first.
9179 `abs r2,r3 || abs r4,r5'
9180 Execute these in parallel.
9182 `ldw r2,@(r3,r4) ||'
9184 Two-line format. Execute these in parallel.
9188 Two-line format. Execute these sequentially unless `-O' option is
9189 used. If the `-O' option is used, the assembler will determine if
9190 the instructions could be done in parallel (the above two
9191 instructions can be done in parallel), and if so, emit them as
9192 parallel instructions. The assembler will put them in the proper
9193 containers. In the above example, the assembler will put the
9194 `stw' instruction in left container and the `mulx' instruction in
9195 the right container.
9197 `stw r2,@(r3,r4) ->'
9199 Two-line format. Execute the `stw' instruction followed by the
9200 `mulx' instruction sequentially. The first instruction goes in the
9201 left container and the second instruction goes into right
9202 container. The assembler will give an error if the machine
9203 ordering constraints are violated.
9205 `stw r2,@(r3,r4) <-'
9207 Same as previous example, except that the `mulx' instruction is
9208 executed before the `stw' instruction.
9210 Since `$' has no special meaning, you may use it in symbol names.
9213 File: as.info, Node: D30V-Guarded, Next: D30V-Regs, Prev: D30V-Chars, Up: D30V-Syntax
9215 9.10.2.4 Guarded Execution
9216 ..........................
9218 `as' supports the full range of guarded execution directives for each
9219 instruction. Just append the directive after the instruction proper.
9223 Execute the instruction if flag f0 is true.
9226 Execute the instruction if flag f0 is false.
9229 Execute the instruction if flag f1 is true.
9232 Execute the instruction if flag f1 is false.
9235 Execute the instruction if both flags f0 and f1 are true.
9238 Execute the instruction if flag f0 is true and flag f1 is false.
9241 File: as.info, Node: D30V-Regs, Next: D30V-Addressing, Prev: D30V-Guarded, Up: D30V-Syntax
9243 9.10.2.5 Register Names
9244 .......................
9246 You can use the predefined symbols `r0' through `r63' to refer to the
9247 D30V registers. You can also use `sp' as an alias for `r63' and `link'
9248 as an alias for `r62'. The accumulators are `a0' and `a1'.
9250 The D30V also has predefined symbols for these control registers and
9253 Processor Status Word
9256 Backup Processor Status Word
9262 Backup Program Counter
9268 Repeat Start address
9274 Modulo Start address
9280 Instruction Break Address
9307 Same as flag 4 (saturation flag)
9310 Same as flag 5 (overflow flag)
9313 Same as flag 6 (sticky overflow flag)
9316 Same as flag 7 (carry/borrow flag)
9319 Same as flag 7 (carry/borrow flag)
9322 File: as.info, Node: D30V-Addressing, Prev: D30V-Regs, Up: D30V-Syntax
9324 9.10.2.6 Addressing Modes
9325 .........................
9327 `as' understands the following addressing modes for the D30V. `RN' in
9328 the following refers to any of the numbered registers, but _not_ the
9337 Register indirect with post-increment
9340 Register indirect with post-decrement
9343 Register indirect with pre-decrement
9346 Register indirect with displacement
9349 PC relative address (for branch or rep).
9352 Immediate data (the `#' is optional and ignored)
9355 File: as.info, Node: D30V-Float, Next: D30V-Opcodes, Prev: D30V-Syntax, Up: D30V-Dependent
9357 9.10.3 Floating Point
9358 ---------------------
9360 The D30V has no hardware floating point, but the `.float' and `.double'
9361 directives generates IEEE floating-point numbers for compatibility with
9362 other development tools.
9365 File: as.info, Node: D30V-Opcodes, Prev: D30V-Float, Up: D30V-Dependent
9370 For detailed information on the D30V machine instruction set, see `D30V
9371 Architecture: A VLIW Microprocessor for Multimedia Applications'
9372 (Mitsubishi Electric Corp.). `as' implements all the standard D30V
9373 opcodes. The only changes are those described in the section on size
9377 File: as.info, Node: Epiphany-Dependent, Next: H8/300-Dependent, Prev: D30V-Dependent, Up: Machine Dependencies
9379 9.11 Epiphany Dependent Features
9380 ================================
9384 * Epiphany Options:: Options
9385 * Epiphany Syntax:: Epiphany Syntax
9388 File: as.info, Node: Epiphany Options, Next: Epiphany Syntax, Up: Epiphany-Dependent
9393 `as' has two additional command-line options for the Epiphany
9397 Specifies that the both 32 and 16 bit instructions are allowed.
9398 This is the default behavior.
9401 Restricts the permitted instructions to just the 16 bit set.
9404 File: as.info, Node: Epiphany Syntax, Prev: Epiphany Options, Up: Epiphany-Dependent
9406 9.11.2 Epiphany Syntax
9407 ----------------------
9411 * Epiphany-Chars:: Special Characters
9414 File: as.info, Node: Epiphany-Chars, Up: Epiphany Syntax
9416 9.11.2.1 Special Characters
9417 ...........................
9419 The presence of a `;' on a line indicates the start of a comment that
9420 extends to the end of the current line.
9422 If a `#' appears as the first character of a line then the whole
9423 line is treated as a comment, but in this case the line could also be a
9424 logical line number directive (*note Comments::) or a preprocessor
9425 control command (*note Preprocessing::).
9427 The ``' character can be used to separate statements on the same
9431 File: as.info, Node: H8/300-Dependent, Next: HPPA-Dependent, Prev: Epiphany-Dependent, Up: Machine Dependencies
9433 9.12 H8/300 Dependent Features
9434 ==============================
9438 * H8/300 Options:: Options
9439 * H8/300 Syntax:: Syntax
9440 * H8/300 Floating Point:: Floating Point
9441 * H8/300 Directives:: H8/300 Machine Directives
9442 * H8/300 Opcodes:: Opcodes
9445 File: as.info, Node: H8/300 Options, Next: H8/300 Syntax, Up: H8/300-Dependent
9450 The Renesas H8/300 version of `as' has one machine-dependent option:
9453 Support H'00 style hex constants in addition to 0x00 style.
9457 File: as.info, Node: H8/300 Syntax, Next: H8/300 Floating Point, Prev: H8/300 Options, Up: H8/300-Dependent
9464 * H8/300-Chars:: Special Characters
9465 * H8/300-Regs:: Register Names
9466 * H8/300-Addressing:: Addressing Modes
9469 File: as.info, Node: H8/300-Chars, Next: H8/300-Regs, Up: H8/300 Syntax
9471 9.12.2.1 Special Characters
9472 ...........................
9474 `;' is the line comment character.
9476 `$' can be used instead of a newline to separate statements.
9477 Therefore _you may not use `$' in symbol names_ on the H8/300.
9480 File: as.info, Node: H8/300-Regs, Next: H8/300-Addressing, Prev: H8/300-Chars, Up: H8/300 Syntax
9482 9.12.2.2 Register Names
9483 .......................
9485 You can use predefined symbols of the form `rNh' and `rNl' to refer to
9486 the H8/300 registers as sixteen 8-bit general-purpose registers. N is
9487 a digit from `0' to `7'); for instance, both `r0h' and `r7l' are valid
9490 You can also use the eight predefined symbols `rN' to refer to the
9491 H8/300 registers as 16-bit registers (you must use this form for
9494 On the H8/300H, you can also use the eight predefined symbols `erN'
9495 (`er0' ... `er7') to refer to the 32-bit general purpose registers.
9497 The two control registers are called `pc' (program counter; a 16-bit
9498 register, except on the H8/300H where it is 24 bits) and `ccr'
9499 (condition code register; an 8-bit register). `r7' is used as the
9500 stack pointer, and can also be called `sp'.
9503 File: as.info, Node: H8/300-Addressing, Prev: H8/300-Regs, Up: H8/300 Syntax
9505 9.12.2.3 Addressing Modes
9506 .........................
9508 as understands the following addressing modes for the H8/300:
9518 Register indirect: 16-bit or 24-bit displacement D from register
9519 N. (24-bit displacements are only meaningful on the H8/300H.)
9522 Register indirect with post-increment
9525 Register indirect with pre-decrement
9531 Absolute address `aa'. (The address size `:24' only makes sense
9538 Immediate data XX. You may specify the `:8', `:16', or `:32' for
9539 clarity, if you wish; but `as' neither requires this nor uses
9540 it--the data size required is taken from context.
9544 Memory indirect. You may specify the `:8' for clarity, if you
9545 wish; but `as' neither requires this nor uses it.
9548 File: as.info, Node: H8/300 Floating Point, Next: H8/300 Directives, Prev: H8/300 Syntax, Up: H8/300-Dependent
9550 9.12.3 Floating Point
9551 ---------------------
9553 The H8/300 family has no hardware floating point, but the `.float'
9554 directive generates IEEE floating-point numbers for compatibility with
9555 other development tools.
9558 File: as.info, Node: H8/300 Directives, Next: H8/300 Opcodes, Prev: H8/300 Floating Point, Up: H8/300-Dependent
9560 9.12.4 H8/300 Machine Directives
9561 --------------------------------
9563 `as' has the following machine-dependent directives for the H8/300:
9566 Recognize and emit additional instructions for the H8/300H
9567 variant, and also make `.int' emit 32-bit numbers rather than the
9568 usual (16-bit) for the H8/300 family.
9571 Recognize and emit additional instructions for the H8S variant, and
9572 also make `.int' emit 32-bit numbers rather than the usual (16-bit)
9573 for the H8/300 family.
9576 Recognize and emit additional instructions for the H8/300H variant
9577 in normal mode, and also make `.int' emit 32-bit numbers rather
9578 than the usual (16-bit) for the H8/300 family.
9581 Recognize and emit additional instructions for the H8S variant in
9582 normal mode, and also make `.int' emit 32-bit numbers rather than
9583 the usual (16-bit) for the H8/300 family.
9585 On the H8/300 family (including the H8/300H) `.word' directives
9586 generate 16-bit numbers.
9589 File: as.info, Node: H8/300 Opcodes, Prev: H8/300 Directives, Up: H8/300-Dependent
9594 For detailed information on the H8/300 machine instruction set, see
9595 `H8/300 Series Programming Manual'. For information specific to the
9596 H8/300H, see `H8/300H Series Programming Manual' (Renesas).
9598 `as' implements all the standard H8/300 opcodes. No additional
9599 pseudo-instructions are needed on this family.
9601 The following table summarizes the H8/300 opcodes, and their
9602 arguments. Entries marked `*' are opcodes used only on the H8/300H.
9606 Rd destination register
9607 abs absolute address
9609 disp:N N-bit displacement from a register
9610 pcrel:N N-bit displacement relative to program counter
9612 add.b #imm,rd * andc #imm,ccr
9613 add.b rs,rd band #imm,rd
9614 add.w rs,rd band #imm,@rd
9615 * add.w #imm,rd band #imm,@abs:8
9616 * add.l rs,rd bra pcrel:8
9617 * add.l #imm,rd * bra pcrel:16
9618 adds #imm,rd bt pcrel:8
9619 addx #imm,rd * bt pcrel:16
9620 addx rs,rd brn pcrel:8
9621 and.b #imm,rd * brn pcrel:16
9622 and.b rs,rd bf pcrel:8
9623 * and.w rs,rd * bf pcrel:16
9624 * and.w #imm,rd bhi pcrel:8
9625 * and.l #imm,rd * bhi pcrel:16
9626 * and.l rs,rd bls pcrel:8
9628 * bls pcrel:16 bld #imm,rd
9629 bcc pcrel:8 bld #imm,@rd
9630 * bcc pcrel:16 bld #imm,@abs:8
9631 bhs pcrel:8 bnot #imm,rd
9632 * bhs pcrel:16 bnot #imm,@rd
9633 bcs pcrel:8 bnot #imm,@abs:8
9634 * bcs pcrel:16 bnot rs,rd
9635 blo pcrel:8 bnot rs,@rd
9636 * blo pcrel:16 bnot rs,@abs:8
9637 bne pcrel:8 bor #imm,rd
9638 * bne pcrel:16 bor #imm,@rd
9639 beq pcrel:8 bor #imm,@abs:8
9640 * beq pcrel:16 bset #imm,rd
9641 bvc pcrel:8 bset #imm,@rd
9642 * bvc pcrel:16 bset #imm,@abs:8
9643 bvs pcrel:8 bset rs,rd
9644 * bvs pcrel:16 bset rs,@rd
9645 bpl pcrel:8 bset rs,@abs:8
9646 * bpl pcrel:16 bsr pcrel:8
9647 bmi pcrel:8 bsr pcrel:16
9648 * bmi pcrel:16 bst #imm,rd
9649 bge pcrel:8 bst #imm,@rd
9650 * bge pcrel:16 bst #imm,@abs:8
9651 blt pcrel:8 btst #imm,rd
9652 * blt pcrel:16 btst #imm,@rd
9653 bgt pcrel:8 btst #imm,@abs:8
9654 * bgt pcrel:16 btst rs,rd
9655 ble pcrel:8 btst rs,@rd
9656 * ble pcrel:16 btst rs,@abs:8
9657 bclr #imm,rd bxor #imm,rd
9658 bclr #imm,@rd bxor #imm,@rd
9659 bclr #imm,@abs:8 bxor #imm,@abs:8
9660 bclr rs,rd cmp.b #imm,rd
9661 bclr rs,@rd cmp.b rs,rd
9662 bclr rs,@abs:8 cmp.w rs,rd
9663 biand #imm,rd cmp.w rs,rd
9664 biand #imm,@rd * cmp.w #imm,rd
9665 biand #imm,@abs:8 * cmp.l #imm,rd
9666 bild #imm,rd * cmp.l rs,rd
9667 bild #imm,@rd daa rs
9668 bild #imm,@abs:8 das rs
9669 bior #imm,rd dec.b rs
9670 bior #imm,@rd * dec.w #imm,rd
9671 bior #imm,@abs:8 * dec.l #imm,rd
9672 bist #imm,rd divxu.b rs,rd
9673 bist #imm,@rd * divxu.w rs,rd
9674 bist #imm,@abs:8 * divxs.b rs,rd
9675 bixor #imm,rd * divxs.w rs,rd
9676 bixor #imm,@rd eepmov
9677 bixor #imm,@abs:8 * eepmovw
9679 * exts.w rd mov.w rs,@abs:16
9680 * exts.l rd * mov.l #imm,rd
9681 * extu.w rd * mov.l rs,rd
9682 * extu.l rd * mov.l @rs,rd
9683 inc rs * mov.l @(disp:16,rs),rd
9684 * inc.w #imm,rd * mov.l @(disp:24,rs),rd
9685 * inc.l #imm,rd * mov.l @rs+,rd
9686 jmp @rs * mov.l @abs:16,rd
9687 jmp abs * mov.l @abs:24,rd
9688 jmp @@abs:8 * mov.l rs,@rd
9689 jsr @rs * mov.l rs,@(disp:16,rd)
9690 jsr abs * mov.l rs,@(disp:24,rd)
9691 jsr @@abs:8 * mov.l rs,@-rd
9692 ldc #imm,ccr * mov.l rs,@abs:16
9693 ldc rs,ccr * mov.l rs,@abs:24
9694 * ldc @abs:16,ccr movfpe @abs:16,rd
9695 * ldc @abs:24,ccr movtpe rs,@abs:16
9696 * ldc @(disp:16,rs),ccr mulxu.b rs,rd
9697 * ldc @(disp:24,rs),ccr * mulxu.w rs,rd
9698 * ldc @rs+,ccr * mulxs.b rs,rd
9699 * ldc @rs,ccr * mulxs.w rs,rd
9700 * mov.b @(disp:24,rs),rd neg.b rs
9701 * mov.b rs,@(disp:24,rd) * neg.w rs
9702 mov.b @abs:16,rd * neg.l rs
9704 mov.b @abs:8,rd not.b rs
9705 mov.b rs,@abs:8 * not.w rs
9706 mov.b rs,rd * not.l rs
9707 mov.b #imm,rd or.b #imm,rd
9708 mov.b @rs,rd or.b rs,rd
9709 mov.b @(disp:16,rs),rd * or.w #imm,rd
9710 mov.b @rs+,rd * or.w rs,rd
9711 mov.b @abs:8,rd * or.l #imm,rd
9712 mov.b rs,@rd * or.l rs,rd
9713 mov.b rs,@(disp:16,rd) orc #imm,ccr
9714 mov.b rs,@-rd pop.w rs
9715 mov.b rs,@abs:8 * pop.l rs
9716 mov.w rs,@rd push.w rs
9717 * mov.w @(disp:24,rs),rd * push.l rs
9718 * mov.w rs,@(disp:24,rd) rotl.b rs
9719 * mov.w @abs:24,rd * rotl.w rs
9720 * mov.w rs,@abs:24 * rotl.l rs
9721 mov.w rs,rd rotr.b rs
9722 mov.w #imm,rd * rotr.w rs
9723 mov.w @rs,rd * rotr.l rs
9724 mov.w @(disp:16,rs),rd rotxl.b rs
9725 mov.w @rs+,rd * rotxl.w rs
9726 mov.w @abs:16,rd * rotxl.l rs
9727 mov.w rs,@(disp:16,rd) rotxr.b rs
9728 mov.w rs,@-rd * rotxr.w rs
9730 * rotxr.l rs * stc ccr,@(disp:24,rd)
9732 rte * stc ccr,@abs:16
9733 rts * stc ccr,@abs:24
9734 shal.b rs sub.b rs,rd
9735 * shal.w rs sub.w rs,rd
9736 * shal.l rs * sub.w #imm,rd
9737 shar.b rs * sub.l rs,rd
9738 * shar.w rs * sub.l #imm,rd
9739 * shar.l rs subs #imm,rd
9740 shll.b rs subx #imm,rd
9741 * shll.w rs subx rs,rd
9742 * shll.l rs * trapa #imm
9743 shlr.b rs xor #imm,rd
9744 * shlr.w rs xor rs,rd
9745 * shlr.l rs * xor.w #imm,rd
9747 stc ccr,rd * xor.l #imm,rd
9748 * stc ccr,@rs * xor.l rs,rd
9749 * stc ccr,@(disp:16,rd) xorc #imm,ccr
9751 Four H8/300 instructions (`add', `cmp', `mov', `sub') are defined
9752 with variants using the suffixes `.b', `.w', and `.l' to specify the
9753 size of a memory operand. `as' supports these suffixes, but does not
9754 require them; since one of the operands is always a register, `as' can
9755 deduce the correct size.
9757 For example, since `r0' refers to a 16-bit register,
9762 If you use the size suffixes, `as' issues a warning when the suffix
9763 and the register size do not match.
9766 File: as.info, Node: HPPA-Dependent, Next: ESA/390-Dependent, Prev: H8/300-Dependent, Up: Machine Dependencies
9768 9.13 HPPA Dependent Features
9769 ============================
9773 * HPPA Notes:: Notes
9774 * HPPA Options:: Options
9775 * HPPA Syntax:: Syntax
9776 * HPPA Floating Point:: Floating Point
9777 * HPPA Directives:: HPPA Machine Directives
9778 * HPPA Opcodes:: Opcodes
9781 File: as.info, Node: HPPA Notes, Next: HPPA Options, Up: HPPA-Dependent
9786 As a back end for GNU CC `as' has been throughly tested and should work
9787 extremely well. We have tested it only minimally on hand written
9788 assembly code and no one has tested it much on the assembly output from
9791 The format of the debugging sections has changed since the original
9792 `as' port (version 1.3X) was released; therefore, you must rebuild all
9793 HPPA objects and libraries with the new assembler so that you can debug
9794 the final executable.
9796 The HPPA `as' port generates a small subset of the relocations
9797 available in the SOM and ELF object file formats. Additional relocation
9798 support will be added as it becomes necessary.
9801 File: as.info, Node: HPPA Options, Next: HPPA Syntax, Prev: HPPA Notes, Up: HPPA-Dependent
9806 `as' has no machine-dependent command-line options for the HPPA.
9809 File: as.info, Node: HPPA Syntax, Next: HPPA Floating Point, Prev: HPPA Options, Up: HPPA-Dependent
9814 The assembler syntax closely follows the HPPA instruction set reference
9815 manual; assembler directives and general syntax closely follow the HPPA
9816 assembly language reference manual, with a few noteworthy differences.
9818 First, a colon may immediately follow a label definition. This is
9819 simply for compatibility with how most assembly language programmers
9822 Some obscure expression parsing problems may affect hand written
9823 code which uses the `spop' instructions, or code which makes significant
9824 use of the `!' line separator.
9826 `as' is much less forgiving about missing arguments and other
9827 similar oversights than the HP assembler. `as' notifies you of missing
9828 arguments as syntax errors; this is regarded as a feature, not a bug.
9830 Finally, `as' allows you to use an external symbol without
9831 explicitly importing the symbol. _Warning:_ in the future this will be
9832 an error for HPPA targets.
9834 Special characters for HPPA targets include:
9836 `;' is the line comment character.
9838 `!' can be used instead of a newline to separate statements.
9840 Since `$' has no special meaning, you may use it in symbol names.
9843 File: as.info, Node: HPPA Floating Point, Next: HPPA Directives, Prev: HPPA Syntax, Up: HPPA-Dependent
9845 9.13.4 Floating Point
9846 ---------------------
9848 The HPPA family uses IEEE floating-point numbers.
9851 File: as.info, Node: HPPA Directives, Next: HPPA Opcodes, Prev: HPPA Floating Point, Up: HPPA-Dependent
9853 9.13.5 HPPA Assembler Directives
9854 --------------------------------
9856 `as' for the HPPA supports many additional directives for compatibility
9857 with the native assembler. This section describes them only briefly.
9858 For detailed information on HPPA-specific assembler directives, see
9859 `HP9000 Series 800 Assembly Language Reference Manual' (HP 92432-90001).
9861 `as' does _not_ support the following assembler directives described
9869 Beyond those implemented for compatibility, `as' supports one
9870 additional assembler directive for the HPPA: `.param'. It conveys
9871 register argument locations for static functions. Its syntax closely
9872 follows the `.export' directive.
9874 These are the additional directives in `as' for the HPPA:
9878 Reserve N bytes of storage, and initialize them to zero.
9881 Mark the beginning of a procedure call. Only the special case
9882 with _no arguments_ is allowed.
9884 `.callinfo [ PARAM=VALUE, ... ] [ FLAG, ... ]'
9885 Specify a number of parameters and flags that define the
9886 environment for a procedure.
9888 PARAM may be any of `frame' (frame size), `entry_gr' (end of
9889 general register range), `entry_fr' (end of float register range),
9890 `entry_sr' (end of space register range).
9892 The values for FLAG are `calls' or `caller' (proc has
9893 subroutines), `no_calls' (proc does not call subroutines),
9894 `save_rp' (preserve return pointer), `save_sp' (proc preserves
9895 stack pointer), `no_unwind' (do not unwind this proc), `hpux_int'
9896 (proc is interrupt routine).
9899 Assemble into the standard section called `$TEXT$', subsection
9902 `.copyright "STRING"'
9903 In the SOM object format, insert STRING into the object code,
9904 marked as a copyright string.
9906 `.copyright "STRING"'
9907 In the ELF object format, insert STRING into the object code,
9908 marked as a version string.
9911 Not yet supported; the assembler rejects programs containing this
9915 Mark the beginning of a procedure.
9918 Mark the end of a procedure.
9920 `.export NAME [ ,TYP ] [ ,PARAM=R ]'
9921 Make a procedure NAME available to callers. TYP, if present, must
9922 be one of `absolute', `code' (ELF only, not SOM), `data', `entry',
9923 `data', `entry', `millicode', `plabel', `pri_prog', or `sec_prog'.
9925 PARAM, if present, provides either relocation information for the
9926 procedure arguments and result, or a privilege level. PARAM may be
9927 `argwN' (where N ranges from `0' to `3', and indicates one of four
9928 one-word arguments); `rtnval' (the procedure's result); or
9929 `priv_lev' (privilege level). For arguments or the result, R
9930 specifies how to relocate, and must be one of `no' (not
9931 relocatable), `gr' (argument is in general register), `fr' (in
9932 floating point register), or `fu' (upper half of float register).
9933 For `priv_lev', R is an integer.
9936 Define a two-byte integer constant N; synonym for the portable
9937 `as' directive `.short'.
9939 `.import NAME [ ,TYP ]'
9940 Converse of `.export'; make a procedure available to call. The
9941 arguments use the same conventions as the first two arguments for
9945 Define NAME as a label for the current assembly location.
9948 Not yet supported; the assembler rejects programs containing this
9952 Advance location counter to LC. Synonym for the `as' portable
9955 `.param NAME [ ,TYP ] [ ,PARAM=R ]'
9956 Similar to `.export', but used for static procedures.
9959 Use preceding the first statement of a procedure.
9962 Use following the last statement of a procedure.
9965 Synonym for `.equ'; define LABEL with the absolute expression EXPR
9968 `.space SECNAME [ ,PARAMS ]'
9969 Switch to section SECNAME, creating a new section by that name if
9970 necessary. You may only use PARAMS when creating a new section,
9971 not when switching to an existing one. SECNAME may identify a
9972 section by number rather than by name.
9974 If specified, the list PARAMS declares attributes of the section,
9975 identified by keywords. The keywords recognized are `spnum=EXP'
9976 (identify this section by the number EXP, an absolute expression),
9977 `sort=EXP' (order sections according to this sort key when linking;
9978 EXP is an absolute expression), `unloadable' (section contains no
9979 loadable data), `notdefined' (this section defined elsewhere), and
9980 `private' (data in this section not available to other programs).
9983 Allocate four bytes of storage, and initialize them with the
9984 section number of the section named SECNAM. (You can define the
9985 section number with the HPPA `.space' directive.)
9988 Copy the characters in the string STR to the object file. *Note
9989 Strings: Strings, for information on escape sequences you can use
9992 _Warning!_ The HPPA version of `.string' differs from the usual
9993 `as' definition: it does _not_ write a zero byte after copying STR.
9996 Like `.string', but appends a zero byte after copying STR to object
9999 `.subspa NAME [ ,PARAMS ]'
10000 `.nsubspa NAME [ ,PARAMS ]'
10001 Similar to `.space', but selects a subsection NAME within the
10002 current section. You may only specify PARAMS when you create a
10003 subsection (in the first instance of `.subspa' for this NAME).
10005 If specified, the list PARAMS declares attributes of the
10006 subsection, identified by keywords. The keywords recognized are
10007 `quad=EXPR' ("quadrant" for this subsection), `align=EXPR'
10008 (alignment for beginning of this subsection; a power of two),
10009 `access=EXPR' (value for "access rights" field), `sort=EXPR'
10010 (sorting order for this subspace in link), `code_only' (subsection
10011 contains only code), `unloadable' (subsection cannot be loaded
10012 into memory), `comdat' (subsection is comdat), `common'
10013 (subsection is common block), `dup_comm' (subsection may have
10014 duplicate names), or `zero' (subsection is all zeros, do not write
10017 `.nsubspa' always creates a new subspace with the given name, even
10018 if one with the same name already exists.
10020 `comdat', `common' and `dup_comm' can be used to implement various
10021 flavors of one-only support when using the SOM linker. The SOM
10022 linker only supports specific combinations of these flags. The
10023 details are not documented. A brief description is provided here.
10025 `comdat' provides a form of linkonce support. It is useful for
10026 both code and data subspaces. A `comdat' subspace has a key symbol
10027 marked by the `is_comdat' flag or `ST_COMDAT'. Only the first
10028 subspace for any given key is selected. The key symbol becomes
10029 universal in shared links. This is similar to the behavior of
10030 `secondary_def' symbols.
10032 `common' provides Fortran named common support. It is only useful
10033 for data subspaces. Symbols with the flag `is_common' retain this
10034 flag in shared links. Referencing a `is_common' symbol in a shared
10035 library from outside the library doesn't work. Thus, `is_common'
10036 symbols must be output whenever they are needed.
10038 `common' and `dup_comm' together provide Cobol common support.
10039 The subspaces in this case must all be the same length.
10040 Otherwise, this support is similar to the Fortran common support.
10042 `dup_comm' by itself provides a type of one-only support for code.
10043 Only the first `dup_comm' subspace is selected. There is a rather
10044 complex algorithm to compare subspaces. Code symbols marked with
10045 the `dup_common' flag are hidden. This support was intended for
10046 "C++ duplicate inlines".
10048 A simplified technique is used to mark the flags of symbols based
10049 on the flags of their subspace. A symbol with the scope
10050 SS_UNIVERSAL and type ST_ENTRY, ST_CODE or ST_DATA is marked with
10051 the corresponding settings of `comdat', `common' and `dup_comm'
10052 from the subspace, respectively. This avoids having to introduce
10053 additional directives to mark these symbols. The HP assembler
10054 sets `is_common' from `common'. However, it doesn't set the
10055 `dup_common' from `dup_comm'. It doesn't have `comdat' support.
10058 Write STR as version identifier in object code.
10061 File: as.info, Node: HPPA Opcodes, Prev: HPPA Directives, Up: HPPA-Dependent
10066 For detailed information on the HPPA machine instruction set, see
10067 `PA-RISC Architecture and Instruction Set Reference Manual' (HP
10071 File: as.info, Node: ESA/390-Dependent, Next: i386-Dependent, Prev: HPPA-Dependent, Up: Machine Dependencies
10073 9.14 ESA/390 Dependent Features
10074 ===============================
10078 * ESA/390 Notes:: Notes
10079 * ESA/390 Options:: Options
10080 * ESA/390 Syntax:: Syntax
10081 * ESA/390 Floating Point:: Floating Point
10082 * ESA/390 Directives:: ESA/390 Machine Directives
10083 * ESA/390 Opcodes:: Opcodes
10086 File: as.info, Node: ESA/390 Notes, Next: ESA/390 Options, Up: ESA/390-Dependent
10091 The ESA/390 `as' port is currently intended to be a back-end for the
10092 GNU CC compiler. It is not HLASM compatible, although it does support
10093 a subset of some of the HLASM directives. The only supported binary
10094 file format is ELF; none of the usual MVS/VM/OE/USS object file
10095 formats, such as ESD or XSD, are supported.
10097 When used with the GNU CC compiler, the ESA/390 `as' will produce
10098 correct, fully relocated, functional binaries, and has been used to
10099 compile and execute large projects. However, many aspects should still
10100 be considered experimental; these include shared library support,
10101 dynamically loadable objects, and any relocation other than the 31-bit
10105 File: as.info, Node: ESA/390 Options, Next: ESA/390 Syntax, Prev: ESA/390 Notes, Up: ESA/390-Dependent
10110 `as' has no machine-dependent command-line options for the ESA/390.
10113 File: as.info, Node: ESA/390 Syntax, Next: ESA/390 Floating Point, Prev: ESA/390 Options, Up: ESA/390-Dependent
10118 The opcode/operand syntax follows the ESA/390 Principles of Operation
10119 manual; assembler directives and general syntax are loosely based on the
10120 prevailing AT&T/SVR4/ELF/Solaris style notation. HLASM-style directives
10121 are _not_ supported for the most part, with the exception of those
10124 A leading dot in front of directives is optional, and the case of
10125 directives is ignored; thus for example, .using and USING have the same
10128 A colon may immediately follow a label definition. This is simply
10129 for compatibility with how most assembly language programmers write
10132 `#' is the line comment character.
10134 `;' can be used instead of a newline to separate statements.
10136 Since `$' has no special meaning, you may use it in symbol names.
10138 Registers can be given the symbolic names r0..r15, fp0, fp2, fp4,
10139 fp6. By using thesse symbolic names, `as' can detect simple syntax
10140 errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for
10141 r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base
10142 for r3 and rpgt or r.pgt for r4.
10144 `*' is the current location counter. Unlike `.' it is always
10145 relative to the last USING directive. Note that this means that
10146 expressions cannot use multiplication, as any occurrence of `*' will be
10147 interpreted as a location counter.
10149 All labels are relative to the last USING. Thus, branches to a label
10150 always imply the use of base+displacement.
10152 Many of the usual forms of address constants / address literals are
10155 L r15,=A(some_routine)
10156 LM r6,r7,=V(some_longlong_extern)
10160 MD r6,=D'3.14159265358979'
10161 O r6,=XL4'cacad0d0'
10163 should all behave as expected: that is, an entry in the literal pool
10164 will be created (or reused if it already exists), and the instruction
10165 operands will be the displacement into the literal pool using the
10166 current base register (as last declared with the `.using' directive).
10169 File: as.info, Node: ESA/390 Floating Point, Next: ESA/390 Directives, Prev: ESA/390 Syntax, Up: ESA/390-Dependent
10171 9.14.4 Floating Point
10172 ---------------------
10174 The assembler generates only IEEE floating-point numbers. The older
10175 floating point formats are not supported.
10178 File: as.info, Node: ESA/390 Directives, Next: ESA/390 Opcodes, Prev: ESA/390 Floating Point, Up: ESA/390-Dependent
10180 9.14.5 ESA/390 Assembler Directives
10181 -----------------------------------
10183 `as' for the ESA/390 supports all of the standard ELF/SVR4 assembler
10184 directives that are documented in the main part of this documentation.
10185 Several additional directives are supported in order to implement the
10186 ESA/390 addressing model. The most important of these are `.using' and
10189 These are the additional directives in `as' for the ESA/390:
10192 A small subset of the usual DC directive is supported.
10195 Stop using REGNO as the base register. The REGNO must have been
10196 previously declared with a `.using' directive in the same section
10197 as the current section.
10200 Emit the EBCDIC equivalent of the indicated string. The emitted
10201 string will be null terminated. Note that the directives
10202 `.string' etc. emit ascii strings by default.
10205 The standard HLASM-style EQU directive is not supported; however,
10206 the standard `as' directive .equ can be used to the same effect.
10209 Dump the literal pool accumulated so far; begin a new literal pool.
10210 The literal pool will be written in the current section; in order
10211 to generate correct assembly, a `.using' must have been previously
10212 specified in the same section.
10214 `.using EXPR,REGNO'
10215 Use REGNO as the base register for all subsequent RX, RS, and SS
10216 form instructions. The EXPR will be evaluated to obtain the base
10217 address; usually, EXPR will merely be `*'.
10219 This assembler allows two `.using' directives to be simultaneously
10220 outstanding, one in the `.text' section, and one in another section
10221 (typically, the `.data' section). This feature allows dynamically
10222 loaded objects to be implemented in a relatively straightforward
10223 way. A `.using' directive must always be specified in the `.text'
10224 section; this will specify the base register that will be used for
10225 branches in the `.text' section. A second `.using' may be
10226 specified in another section; this will specify the base register
10227 that is used for non-label address literals. When a second
10228 `.using' is specified, then the subsequent `.ltorg' must be put in
10229 the same section; otherwise an error will result.
10231 Thus, for example, the following code uses `r3' to address branch
10232 targets and `r4' to address the literal pool, which has been
10233 written to the `.data' section. The is, the constants
10234 `=A(some_routine)', `=H'42'' and `=E'3.1416'' will all appear in
10235 the `.data' section.
10246 L r15,=A(some_routine)
10256 Note that this dual-`.using' directive semantics extends and is
10257 not compatible with HLASM semantics. Note that this assembler
10258 directive does not support the full range of HLASM semantics.
10262 File: as.info, Node: ESA/390 Opcodes, Prev: ESA/390 Directives, Up: ESA/390-Dependent
10267 For detailed information on the ESA/390 machine instruction set, see
10268 `ESA/390 Principles of Operation' (IBM Publication Number DZ9AR004).
10271 File: as.info, Node: i386-Dependent, Next: i860-Dependent, Prev: ESA/390-Dependent, Up: Machine Dependencies
10273 9.15 80386 Dependent Features
10274 =============================
10276 The i386 version `as' supports both the original Intel 386
10277 architecture in both 16 and 32-bit mode as well as AMD x86-64
10278 architecture extending the Intel architecture to 64-bits.
10282 * i386-Options:: Options
10283 * i386-Directives:: X86 specific directives
10284 * i386-Syntax:: Syntactical considerations
10285 * i386-Mnemonics:: Instruction Naming
10286 * i386-Regs:: Register Naming
10287 * i386-Prefixes:: Instruction Prefixes
10288 * i386-Memory:: Memory References
10289 * i386-Jumps:: Handling of Jump Instructions
10290 * i386-Float:: Floating Point
10291 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
10292 * i386-LWP:: AMD's Lightweight Profiling Instructions
10293 * i386-BMI:: Bit Manipulation Instruction
10294 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
10295 * i386-16bit:: Writing 16-bit Code
10296 * i386-Arch:: Specifying an x86 CPU architecture
10297 * i386-Bugs:: AT&T Syntax bugs
10298 * i386-Notes:: Notes
10301 File: as.info, Node: i386-Options, Next: i386-Directives, Up: i386-Dependent
10306 The i386 version of `as' has a few machine dependent options:
10308 `--32 | --x32 | --64'
10309 Select the word size, either 32 bits or 64 bits. `--32' implies
10310 Intel i386 architecture, while `--x32' and `--64' imply AMD x86-64
10311 architecture with 32-bit or 64-bit word-size respectively.
10313 These options are only available with the ELF object file format,
10314 and require that the necessary BFD support has been included (on a
10315 32-bit platform you have to add -enable-64-bit-bfd to configure
10316 enable 64-bit usage and use x86-64 as target platform).
10319 By default, x86 GAS replaces multiple nop instructions used for
10320 alignment within code sections with multi-byte nop instructions
10321 such as leal 0(%esi,1),%esi. This switch disables the
10325 On SVR4-derived platforms, the character `/' is treated as a
10326 comment character, which means that it cannot be used in
10327 expressions. The `--divide' option turns `/' into a normal
10328 character. This does not disable `/' at the beginning of a line
10329 starting a comment, or affect using `#' for starting a comment.
10331 `-march=CPU[+EXTENSION...]'
10332 This option specifies the target processor. The assembler will
10333 issue an error message if an attempt is made to assemble an
10334 instruction which will not execute on the target processor. The
10335 following processor names are recognized: `i8086', `i186', `i286',
10336 `i386', `i486', `i586', `i686', `pentium', `pentiumpro',
10337 `pentiumii', `pentiumiii', `pentium4', `prescott', `nocona',
10338 `core', `core2', `corei7', `l1om', `k1om', `k6', `k6_2', `athlon',
10339 `opteron', `k8', `amdfam10', `bdver1', `bdver2', `bdver3',
10340 `bdver4', `btver1', `btver2', `generic32' and `generic64'.
10342 In addition to the basic instruction set, the assembler can be
10343 told to accept various extension mnemonics. For example,
10344 `-march=i686+sse4+vmx' extends I686 with SSE4 and VMX. The
10345 following extensions are currently supported: `8087', `287', `387',
10346 `no87', `mmx', `nommx', `sse', `sse2', `sse3', `ssse3', `sse4.1',
10347 `sse4.2', `sse4', `nosse', `avx', `avx2', `adx', `rdseed',
10348 `prfchw', `smap', `mpx', `sha', `prefetchwt1', `clflushopt', `se1',
10349 `clwb', `pcommit', `avx512f', `avx512cd', `avx512er', `avx512pf',
10350 `avx512vl', `avx512bw', `avx512dq', `avx512ifma', `avx512vbmi',
10351 `noavx', `vmx', `vmfunc', `smx', `xsave', `xsaveopt', `xsavec',
10352 `xsaves', `aes', `pclmul', `fsgsbase', `rdrnd', `f16c', `bmi2',
10353 `fma', `movbe', `ept', `lzcnt', `hle', `rtm', `invpcid', `clflush',
10354 `lwp', `fma4', `xop', `cx16', `syscall', `rdtscp', `3dnow',
10355 `3dnowa', `sse4a', `sse5', `svme', `abm' and `padlock'. Note that
10356 rather than extending a basic instruction set, the extension
10357 mnemonics starting with `no' revoke the respective functionality.
10359 When the `.arch' directive is used with `-march', the `.arch'
10360 directive will take precedent.
10363 This option specifies a processor to optimize for. When used in
10364 conjunction with the `-march' option, only instructions of the
10365 processor specified by the `-march' option will be generated.
10367 Valid CPU values are identical to the processor list of
10371 This option specifies that the assembler should encode SSE
10372 instructions with VEX prefix.
10375 `-msse-check=WARNING'
10376 `-msse-check=ERROR'
10377 These options control if the assembler should check SSE
10378 instructions. `-msse-check=NONE' will make the assembler not to
10379 check SSE instructions, which is the default.
10380 `-msse-check=WARNING' will make the assembler issue a warning for
10381 any SSE instruction. `-msse-check=ERROR' will make the assembler
10382 issue an error for any SSE instruction.
10386 These options control how the assembler should encode scalar AVX
10387 instructions. `-mavxscalar=128' will encode scalar AVX
10388 instructions with 128bit vector length, which is the default.
10389 `-mavxscalar=256' will encode scalar AVX instructions with 256bit
10395 These options control how the assembler should encode
10396 length-ignored (LIG) EVEX instructions. `-mevexlig=128' will
10397 encode LIG EVEX instructions with 128bit vector length, which is
10398 the default. `-mevexlig=256' and `-mevexlig=512' will encode LIG
10399 EVEX instructions with 256bit and 512bit vector length,
10404 These options control how the assembler should encode w-ignored
10405 (WIG) EVEX instructions. `-mevexwig=0' will encode WIG EVEX
10406 instructions with evex.w = 0, which is the default. `-mevexwig=1'
10407 will encode WIG EVEX instructions with evex.w = 1.
10411 This option specifies instruction mnemonic for matching
10412 instructions. The `.att_mnemonic' and `.intel_mnemonic'
10413 directives will take precedent.
10417 This option specifies instruction syntax when processing
10418 instructions. The `.att_syntax' and `.intel_syntax' directives
10419 will take precedent.
10422 This opetion specifies that registers don't require a `%' prefix.
10423 The `.att_syntax' and `.intel_syntax' directives will take
10427 This option forces the assembler to add BND prefix to all
10428 branches, even if such prefix was not explicitly specified in the
10432 On x86-64 PE/COFF target this option forces the use of big object
10433 file format, which allows more than 32768 sections.
10435 `-momit-lock-prefix=NO'
10436 `-momit-lock-prefix=YES'
10437 These options control how the assembler should encode lock prefix.
10438 This option is intended as a workaround for processors, that fail
10439 on lock prefix. This option can only be safely used with
10440 single-core, single-thread computers `-momit-lock-prefix=YES' will
10441 omit all lock prefixes. `-momit-lock-prefix=NO' will encode lock
10442 prefix as usual, which is the default.
10448 These options control how the assembler should encode SAE-only
10449 EVEX instructions. `-mevexrcig=RNE' will encode RC bits of EVEX
10450 instruction with 00, which is the default. `-mevexrcig=RD',
10451 `-mevexrcig=RU' and `-mevexrcig=RZ' will encode SAE-only EVEX
10452 instructions with 01, 10 and 11 RC bits, respectively.
10456 File: as.info, Node: i386-Directives, Next: i386-Syntax, Prev: i386-Options, Up: i386-Dependent
10458 9.15.2 x86 specific Directives
10459 ------------------------------
10461 `.lcomm SYMBOL , LENGTH[, ALIGNMENT]'
10462 Reserve LENGTH (an absolute expression) bytes for a local common
10463 denoted by SYMBOL. The section and value of SYMBOL are those of
10464 the new local common. The addresses are allocated in the bss
10465 section, so that at run-time the bytes start off zeroed. Since
10466 SYMBOL is not declared global, it is normally not visible to `ld'.
10467 The optional third parameter, ALIGNMENT, specifies the desired
10468 alignment of the symbol in the bss section.
10470 This directive is only available for COFF based x86 targets.
10474 File: as.info, Node: i386-Syntax, Next: i386-Mnemonics, Prev: i386-Directives, Up: i386-Dependent
10476 9.15.3 i386 Syntactical Considerations
10477 --------------------------------------
10481 * i386-Variations:: AT&T Syntax versus Intel Syntax
10482 * i386-Chars:: Special Characters
10485 File: as.info, Node: i386-Variations, Next: i386-Chars, Up: i386-Syntax
10487 9.15.3.1 AT&T Syntax versus Intel Syntax
10488 ........................................
10490 `as' now supports assembly using Intel assembler syntax.
10491 `.intel_syntax' selects Intel mode, and `.att_syntax' switches back to
10492 the usual AT&T mode for compatibility with the output of `gcc'. Either
10493 of these directives may have an optional argument, `prefix', or
10494 `noprefix' specifying whether registers require a `%' prefix. AT&T
10495 System V/386 assembler syntax is quite different from Intel syntax. We
10496 mention these differences because almost all 80386 documents use Intel
10497 syntax. Notable differences between the two syntaxes are:
10499 * AT&T immediate operands are preceded by `$'; Intel immediate
10500 operands are undelimited (Intel `push 4' is AT&T `pushl $4').
10501 AT&T register operands are preceded by `%'; Intel register operands
10502 are undelimited. AT&T absolute (as opposed to PC relative)
10503 jump/call operands are prefixed by `*'; they are undelimited in
10506 * AT&T and Intel syntax use the opposite order for source and
10507 destination operands. Intel `add eax, 4' is `addl $4, %eax'. The
10508 `source, dest' convention is maintained for compatibility with
10509 previous Unix assemblers. Note that `bound', `invlpga', and
10510 instructions with 2 immediate operands, such as the `enter'
10511 instruction, do _not_ have reversed order. *Note i386-Bugs::.
10513 * In AT&T syntax the size of memory operands is determined from the
10514 last character of the instruction mnemonic. Mnemonic suffixes of
10515 `b', `w', `l' and `q' specify byte (8-bit), word (16-bit), long
10516 (32-bit) and quadruple word (64-bit) memory references. Intel
10517 syntax accomplishes this by prefixing memory operands (_not_ the
10518 instruction mnemonics) with `byte ptr', `word ptr', `dword ptr'
10519 and `qword ptr'. Thus, Intel `mov al, byte ptr FOO' is `movb FOO,
10520 %al' in AT&T syntax.
10522 In 64-bit code, `movabs' can be used to encode the `mov'
10523 instruction with the 64-bit displacement or immediate operand.
10525 * Immediate form long jumps and calls are `lcall/ljmp $SECTION,
10526 $OFFSET' in AT&T syntax; the Intel syntax is `call/jmp far
10527 SECTION:OFFSET'. Also, the far return instruction is `lret
10528 $STACK-ADJUST' in AT&T syntax; Intel syntax is `ret far
10531 * The AT&T assembler does not provide support for multiple section
10532 programs. Unix style systems expect all programs to be single
10536 File: as.info, Node: i386-Chars, Prev: i386-Variations, Up: i386-Syntax
10538 9.15.3.2 Special Characters
10539 ...........................
10541 The presence of a `#' appearing anywhere on a line indicates the start
10542 of a comment that extends to the end of that line.
10544 If a `#' appears as the first character of a line then the whole
10545 line is treated as a comment, but in this case the line can also be a
10546 logical line number directive (*note Comments::) or a preprocessor
10547 control command (*note Preprocessing::).
10549 If the `--divide' command line option has not been specified then
10550 the `/' character appearing anywhere on a line also introduces a line
10553 The `;' character can be used to separate statements on the same
10557 File: as.info, Node: i386-Mnemonics, Next: i386-Regs, Prev: i386-Syntax, Up: i386-Dependent
10559 9.15.4 Instruction Naming
10560 -------------------------
10562 Instruction mnemonics are suffixed with one character modifiers which
10563 specify the size of operands. The letters `b', `w', `l' and `q'
10564 specify byte, word, long and quadruple word operands. If no suffix is
10565 specified by an instruction then `as' tries to fill in the missing
10566 suffix based on the destination register operand (the last one by
10567 convention). Thus, `mov %ax, %bx' is equivalent to `movw %ax, %bx';
10568 also, `mov $1, %bx' is equivalent to `movw $1, bx'. Note that this is
10569 incompatible with the AT&T Unix assembler which assumes that a missing
10570 mnemonic suffix implies long operand size. (This incompatibility does
10571 not affect compiler output since compilers always explicitly specify
10572 the mnemonic suffix.)
10574 Almost all instructions have the same names in AT&T and Intel format.
10575 There are a few exceptions. The sign extend and zero extend
10576 instructions need two sizes to specify them. They need a size to
10577 sign/zero extend _from_ and a size to zero extend _to_. This is
10578 accomplished by using two instruction mnemonic suffixes in AT&T syntax.
10579 Base names for sign extend and zero extend are `movs...' and `movz...'
10580 in AT&T syntax (`movsx' and `movzx' in Intel syntax). The instruction
10581 mnemonic suffixes are tacked on to this base name, the _from_ suffix
10582 before the _to_ suffix. Thus, `movsbl %al, %edx' is AT&T syntax for
10583 "move sign extend _from_ %al _to_ %edx." Possible suffixes, thus, are
10584 `bl' (from byte to long), `bw' (from byte to word), `wl' (from word to
10585 long), `bq' (from byte to quadruple word), `wq' (from word to quadruple
10586 word), and `lq' (from long to quadruple word).
10588 Different encoding options can be specified via optional mnemonic
10589 suffix. `.s' suffix swaps 2 register operands in encoding when moving
10590 from one register to another. `.d8' or `.d32' suffix prefers 8bit or
10591 32bit displacement in encoding.
10593 The Intel-syntax conversion instructions
10595 * `cbw' -- sign-extend byte in `%al' to word in `%ax',
10597 * `cwde' -- sign-extend word in `%ax' to long in `%eax',
10599 * `cwd' -- sign-extend word in `%ax' to long in `%dx:%ax',
10601 * `cdq' -- sign-extend dword in `%eax' to quad in `%edx:%eax',
10603 * `cdqe' -- sign-extend dword in `%eax' to quad in `%rax' (x86-64
10606 * `cqo' -- sign-extend quad in `%rax' to octuple in `%rdx:%rax'
10609 are called `cbtw', `cwtl', `cwtd', `cltd', `cltq', and `cqto' in AT&T
10610 naming. `as' accepts either naming for these instructions.
10612 Far call/jump instructions are `lcall' and `ljmp' in AT&T syntax,
10613 but are `call far' and `jump far' in Intel convention.
10615 9.15.5 AT&T Mnemonic versus Intel Mnemonic
10616 ------------------------------------------
10618 `as' supports assembly using Intel mnemonic. `.intel_mnemonic' selects
10619 Intel mnemonic with Intel syntax, and `.att_mnemonic' switches back to
10620 the usual AT&T mnemonic with AT&T syntax for compatibility with the
10621 output of `gcc'. Several x87 instructions, `fadd', `fdiv', `fdivp',
10622 `fdivr', `fdivrp', `fmul', `fsub', `fsubp', `fsubr' and `fsubrp', are
10623 implemented in AT&T System V/386 assembler with different mnemonics
10624 from those in Intel IA32 specification. `gcc' generates those
10625 instructions with AT&T mnemonic.
10628 File: as.info, Node: i386-Regs, Next: i386-Prefixes, Prev: i386-Mnemonics, Up: i386-Dependent
10630 9.15.6 Register Naming
10631 ----------------------
10633 Register operands are always prefixed with `%'. The 80386 registers
10636 * the 8 32-bit registers `%eax' (the accumulator), `%ebx', `%ecx',
10637 `%edx', `%edi', `%esi', `%ebp' (the frame pointer), and `%esp'
10638 (the stack pointer).
10640 * the 8 16-bit low-ends of these: `%ax', `%bx', `%cx', `%dx', `%di',
10641 `%si', `%bp', and `%sp'.
10643 * the 8 8-bit registers: `%ah', `%al', `%bh', `%bl', `%ch', `%cl',
10644 `%dh', and `%dl' (These are the high-bytes and low-bytes of `%ax',
10645 `%bx', `%cx', and `%dx')
10647 * the 6 section registers `%cs' (code section), `%ds' (data
10648 section), `%ss' (stack section), `%es', `%fs', and `%gs'.
10650 * the 3 processor control registers `%cr0', `%cr2', and `%cr3'.
10652 * the 6 debug registers `%db0', `%db1', `%db2', `%db3', `%db6', and
10655 * the 2 test registers `%tr6' and `%tr7'.
10657 * the 8 floating point register stack `%st' or equivalently
10658 `%st(0)', `%st(1)', `%st(2)', `%st(3)', `%st(4)', `%st(5)',
10659 `%st(6)', and `%st(7)'. These registers are overloaded by 8 MMX
10660 registers `%mm0', `%mm1', `%mm2', `%mm3', `%mm4', `%mm5', `%mm6'
10663 * the 8 SSE registers registers `%xmm0', `%xmm1', `%xmm2', `%xmm3',
10664 `%xmm4', `%xmm5', `%xmm6' and `%xmm7'.
10666 The AMD x86-64 architecture extends the register set by:
10668 * enhancing the 8 32-bit registers to 64-bit: `%rax' (the
10669 accumulator), `%rbx', `%rcx', `%rdx', `%rdi', `%rsi', `%rbp' (the
10670 frame pointer), `%rsp' (the stack pointer)
10672 * the 8 extended registers `%r8'-`%r15'.
10674 * the 8 32-bit low ends of the extended registers: `%r8d'-`%r15d'
10676 * the 8 16-bit low ends of the extended registers: `%r8w'-`%r15w'
10678 * the 8 8-bit low ends of the extended registers: `%r8b'-`%r15b'
10680 * the 4 8-bit registers: `%sil', `%dil', `%bpl', `%spl'.
10682 * the 8 debug registers: `%db8'-`%db15'.
10684 * the 8 SSE registers: `%xmm8'-`%xmm15'.
10687 File: as.info, Node: i386-Prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent
10689 9.15.7 Instruction Prefixes
10690 ---------------------------
10692 Instruction prefixes are used to modify the following instruction. They
10693 are used to repeat string instructions, to provide section overrides, to
10694 perform bus lock operations, and to change operand and address sizes.
10695 (Most instructions that normally operate on 32-bit operands will use
10696 16-bit operands if the instruction has an "operand size" prefix.)
10697 Instruction prefixes are best written on the same line as the
10698 instruction they act upon. For example, the `scas' (scan string)
10699 instruction is repeated with:
10701 repne scas %es:(%edi),%al
10703 You may also place prefixes on the lines immediately preceding the
10704 instruction, but this circumvents checks that `as' does with prefixes,
10705 and will not work with all prefixes.
10707 Here is a list of instruction prefixes:
10709 * Section override prefixes `cs', `ds', `ss', `es', `fs', `gs'.
10710 These are automatically added by specifying using the
10711 SECTION:MEMORY-OPERAND form for memory references.
10713 * Operand/Address size prefixes `data16' and `addr16' change 32-bit
10714 operands/addresses into 16-bit operands/addresses, while `data32'
10715 and `addr32' change 16-bit ones (in a `.code16' section) into
10716 32-bit operands/addresses. These prefixes _must_ appear on the
10717 same line of code as the instruction they modify. For example, in
10718 a 16-bit `.code16' section, you might write:
10720 addr32 jmpl *(%ebx)
10722 * The bus lock prefix `lock' inhibits interrupts during execution of
10723 the instruction it precedes. (This is only valid with certain
10724 instructions; see a 80386 manual for details).
10726 * The wait for coprocessor prefix `wait' waits for the coprocessor to
10727 complete the current instruction. This should never be needed for
10728 the 80386/80387 combination.
10730 * The `rep', `repe', and `repne' prefixes are added to string
10731 instructions to make them repeat `%ecx' times (`%cx' times if the
10732 current address size is 16-bits).
10734 * The `rex' family of prefixes is used by x86-64 to encode
10735 extensions to i386 instruction set. The `rex' prefix has four
10736 bits -- an operand size overwrite (`64') used to change operand
10737 size from 32-bit to 64-bit and X, Y and Z extensions bits used to
10738 extend the register set.
10740 You may write the `rex' prefixes directly. The `rex64xyz'
10741 instruction emits `rex' prefix with all the bits set. By omitting
10742 the `64', `x', `y' or `z' you may write other prefixes as well.
10743 Normally, there is no need to write the prefixes explicitly, since
10744 gas will automatically generate them based on the instruction
10748 File: as.info, Node: i386-Memory, Next: i386-Jumps, Prev: i386-Prefixes, Up: i386-Dependent
10750 9.15.8 Memory References
10751 ------------------------
10753 An Intel syntax indirect memory reference of the form
10755 SECTION:[BASE + INDEX*SCALE + DISP]
10757 is translated into the AT&T syntax
10759 SECTION:DISP(BASE, INDEX, SCALE)
10761 where BASE and INDEX are the optional 32-bit base and index registers,
10762 DISP is the optional displacement, and SCALE, taking the values 1, 2,
10763 4, and 8, multiplies INDEX to calculate the address of the operand. If
10764 no SCALE is specified, SCALE is taken to be 1. SECTION specifies the
10765 optional section register for the memory operand, and may override the
10766 default section register (see a 80386 manual for section register
10767 defaults). Note that section overrides in AT&T syntax _must_ be
10768 preceded by a `%'. If you specify a section override which coincides
10769 with the default section register, `as' does _not_ output any section
10770 register override prefixes to assemble the given instruction. Thus,
10771 section overrides can be specified to emphasize which section register
10772 is used for a given memory operand.
10774 Here are some examples of Intel and AT&T style memory references:
10776 AT&T: `-4(%ebp)', Intel: `[ebp - 4]'
10777 BASE is `%ebp'; DISP is `-4'. SECTION is missing, and the default
10778 section is used (`%ss' for addressing with `%ebp' as the base
10779 register). INDEX, SCALE are both missing.
10781 AT&T: `foo(,%eax,4)', Intel: `[foo + eax*4]'
10782 INDEX is `%eax' (scaled by a SCALE 4); DISP is `foo'. All other
10783 fields are missing. The section register here defaults to `%ds'.
10785 AT&T: `foo(,1)'; Intel `[foo]'
10786 This uses the value pointed to by `foo' as a memory operand. Note
10787 that BASE and INDEX are both missing, but there is only _one_ `,'.
10788 This is a syntactic exception.
10790 AT&T: `%gs:foo'; Intel `gs:foo'
10791 This selects the contents of the variable `foo' with section
10792 register SECTION being `%gs'.
10794 Absolute (as opposed to PC relative) call and jump operands must be
10795 prefixed with `*'. If no `*' is specified, `as' always chooses PC
10796 relative addressing for jump/call labels.
10798 Any instruction that has a memory operand, but no register operand,
10799 _must_ specify its size (byte, word, long, or quadruple) with an
10800 instruction mnemonic suffix (`b', `w', `l' or `q', respectively).
10802 The x86-64 architecture adds an RIP (instruction pointer relative)
10803 addressing. This addressing mode is specified by using `rip' as a base
10804 register. Only constant offsets are valid. For example:
10806 AT&T: `1234(%rip)', Intel: `[rip + 1234]'
10807 Points to the address 1234 bytes past the end of the current
10810 AT&T: `symbol(%rip)', Intel: `[rip + symbol]'
10811 Points to the `symbol' in RIP relative way, this is shorter than
10812 the default absolute addressing.
10814 Other addressing modes remain unchanged in x86-64 architecture,
10815 except registers used are 64-bit instead of 32-bit.
10818 File: as.info, Node: i386-Jumps, Next: i386-Float, Prev: i386-Memory, Up: i386-Dependent
10820 9.15.9 Handling of Jump Instructions
10821 ------------------------------------
10823 Jump instructions are always optimized to use the smallest possible
10824 displacements. This is accomplished by using byte (8-bit) displacement
10825 jumps whenever the target is sufficiently close. If a byte displacement
10826 is insufficient a long displacement is used. We do not support word
10827 (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
10828 instruction with the `data16' instruction prefix), since the 80386
10829 insists upon masking `%eip' to 16 bits after the word displacement is
10830 added. (See also *note i386-Arch::)
10832 Note that the `jcxz', `jecxz', `loop', `loopz', `loope', `loopnz'
10833 and `loopne' instructions only come in byte displacements, so that if
10834 you use these instructions (`gcc' does not use them) you may get an
10835 error message (and incorrect code). The AT&T 80386 assembler tries to
10836 get around this problem by expanding `jcxz foo' to
10844 File: as.info, Node: i386-Float, Next: i386-SIMD, Prev: i386-Jumps, Up: i386-Dependent
10846 9.15.10 Floating Point
10847 ----------------------
10849 All 80387 floating point types except packed BCD are supported. (BCD
10850 support may be added without much difficulty). These data types are
10851 16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit),
10852 and extended (80-bit) precision floating point. Each supported type
10853 has an instruction mnemonic suffix and a constructor associated with
10854 it. Instruction mnemonic suffixes specify the operand's data type.
10855 Constructors build these data types into memory.
10857 * Floating point constructors are `.float' or `.single', `.double',
10858 and `.tfloat' for 32-, 64-, and 80-bit formats. These correspond
10859 to instruction mnemonic suffixes `s', `l', and `t'. `t' stands for
10860 80-bit (ten byte) real. The 80387 only supports this format via
10861 the `fldt' (load 80-bit real to stack top) and `fstpt' (store
10862 80-bit real and pop stack) instructions.
10864 * Integer constructors are `.word', `.long' or `.int', and `.quad'
10865 for the 16-, 32-, and 64-bit integer formats. The corresponding
10866 instruction mnemonic suffixes are `s' (single), `l' (long), and
10867 `q' (quad). As with the 80-bit real format, the 64-bit `q' format
10868 is only present in the `fildq' (load quad integer to stack top)
10869 and `fistpq' (store quad integer and pop stack) instructions.
10871 Register to register operations should not use instruction mnemonic
10872 suffixes. `fstl %st, %st(1)' will give a warning, and be assembled as
10873 if you wrote `fst %st, %st(1)', since all register to register
10874 operations use 80-bit floating point operands. (Contrast this with
10875 `fstl %st, mem', which converts `%st' from 80-bit to 64-bit floating
10876 point format, then stores the result in the 4 byte location `mem')
10879 File: as.info, Node: i386-SIMD, Next: i386-LWP, Prev: i386-Float, Up: i386-Dependent
10881 9.15.11 Intel's MMX and AMD's 3DNow! SIMD Operations
10882 ----------------------------------------------------
10884 `as' supports Intel's MMX instruction set (SIMD instructions for
10885 integer data), available on Intel's Pentium MMX processors and Pentium
10886 II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and
10887 probably others. It also supports AMD's 3DNow! instruction set (SIMD
10888 instructions for 32-bit floating point data) available on AMD's K6-2
10889 processor and possibly others in the future.
10891 Currently, `as' does not support Intel's floating point SIMD, Katmai
10894 The eight 64-bit MMX operands, also used by 3DNow!, are called
10895 `%mm0', `%mm1', ... `%mm7'. They contain eight 8-bit integers, four
10896 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
10897 floating point values. The MMX registers cannot be used at the same
10898 time as the floating point stack.
10900 See Intel and AMD documentation, keeping in mind that the operand
10901 order in instructions is reversed from the Intel syntax.
10904 File: as.info, Node: i386-LWP, Next: i386-BMI, Prev: i386-SIMD, Up: i386-Dependent
10906 9.15.12 AMD's Lightweight Profiling Instructions
10907 ------------------------------------------------
10909 `as' supports AMD's Lightweight Profiling (LWP) instruction set,
10910 available on AMD's Family 15h (Orochi) processors.
10912 LWP enables applications to collect and manage performance data, and
10913 react to performance events. The collection of performance data
10914 requires no context switches. LWP runs in the context of a thread and
10915 so several counters can be used independently across multiple threads.
10916 LWP can be used in both 64-bit and legacy 32-bit modes.
10918 For detailed information on the LWP instruction set, see the `AMD
10919 Lightweight Profiling Specification' available at Lightweight Profiling
10920 Specification (http://developer.amd.com/cpu/LWP).
10923 File: as.info, Node: i386-BMI, Next: i386-TBM, Prev: i386-LWP, Up: i386-Dependent
10925 9.15.13 Bit Manipulation Instructions
10926 -------------------------------------
10928 `as' supports the Bit Manipulation (BMI) instruction set.
10930 BMI instructions provide several instructions implementing individual
10931 bit manipulation operations such as isolation, masking, setting, or
10935 File: as.info, Node: i386-TBM, Next: i386-16bit, Prev: i386-BMI, Up: i386-Dependent
10937 9.15.14 AMD's Trailing Bit Manipulation Instructions
10938 ----------------------------------------------------
10940 `as' supports AMD's Trailing Bit Manipulation (TBM) instruction set,
10941 available on AMD's BDVER2 processors (Trinity and Viperfish).
10943 TBM instructions provide instructions implementing individual bit
10944 manipulation operations such as isolating, masking, setting, resetting,
10945 complementing, and operations on trailing zeros and ones.
10948 File: as.info, Node: i386-16bit, Next: i386-Arch, Prev: i386-TBM, Up: i386-Dependent
10950 9.15.15 Writing 16-bit Code
10951 ---------------------------
10953 While `as' normally writes only "pure" 32-bit i386 code or 64-bit
10954 x86-64 code depending on the default configuration, it also supports
10955 writing code to run in real mode or in 16-bit protected mode code
10956 segments. To do this, put a `.code16' or `.code16gcc' directive before
10957 the assembly language instructions to be run in 16-bit mode. You can
10958 switch `as' to writing 32-bit code with the `.code32' directive or
10959 64-bit code with the `.code64' directive.
10961 `.code16gcc' provides experimental support for generating 16-bit
10962 code from gcc, and differs from `.code16' in that `call', `ret',
10963 `enter', `leave', `push', `pop', `pusha', `popa', `pushf', and `popf'
10964 instructions default to 32-bit size. This is so that the stack pointer
10965 is manipulated in the same way over function calls, allowing access to
10966 function parameters at the same stack offsets as in 32-bit mode.
10967 `.code16gcc' also automatically adds address size prefixes where
10968 necessary to use the 32-bit addressing modes that gcc generates.
10970 The code which `as' generates in 16-bit mode will not necessarily
10971 run on a 16-bit pre-80386 processor. To write code that runs on such a
10972 processor, you must refrain from using _any_ 32-bit constructs which
10973 require `as' to output address or operand size prefixes.
10975 Note that writing 16-bit code instructions by explicitly specifying a
10976 prefix or an instruction mnemonic suffix within a 32-bit code section
10977 generates different machine instructions than those generated for a
10978 16-bit code segment. In a 32-bit code section, the following code
10979 generates the machine opcode bytes `66 6a 04', which pushes the value
10980 `4' onto the stack, decrementing `%esp' by 2.
10984 The same code in a 16-bit code section would generate the machine
10985 opcode bytes `6a 04' (i.e., without the operand size prefix), which is
10986 correct since the processor default operand size is assumed to be 16
10987 bits in a 16-bit code section.
10990 File: as.info, Node: i386-Bugs, Next: i386-Notes, Prev: i386-Arch, Up: i386-Dependent
10992 9.15.16 AT&T Syntax bugs
10993 ------------------------
10995 The UnixWare assembler, and probably other AT&T derived ix86 Unix
10996 assemblers, generate floating point instructions with reversed source
10997 and destination registers in certain cases. Unfortunately, gcc and
10998 possibly many other programs use this reversed syntax, so we're stuck
11004 results in `%st(3)' being updated to `%st - %st(3)' rather than the
11005 expected `%st(3) - %st'. This happens with all the non-commutative
11006 arithmetic floating point operations with two register operands where
11007 the source register is `%st' and the destination register is `%st(i)'.
11010 File: as.info, Node: i386-Arch, Next: i386-Bugs, Prev: i386-16bit, Up: i386-Dependent
11012 9.15.17 Specifying CPU Architecture
11013 -----------------------------------
11015 `as' may be told to assemble for a particular CPU (sub-)architecture
11016 with the `.arch CPU_TYPE' directive. This directive enables a warning
11017 when gas detects an instruction that is not supported on the CPU
11018 specified. The choices for CPU_TYPE are:
11020 `i8086' `i186' `i286' `i386'
11021 `i486' `i586' `i686' `pentium'
11022 `pentiumpro' `pentiumii' `pentiumiii' `pentium4'
11023 `prescott' `nocona' `core' `core2'
11024 `corei7' `l1om' `k1om'
11025 `k6' `k6_2' `athlon' `k8'
11026 `amdfam10' `bdver1' `bdver2' `bdver3'
11027 `bdver4' `btver1' `btver2'
11028 `generic32' `generic64'
11029 `.mmx' `.sse' `.sse2' `.sse3'
11030 `.ssse3' `.sse4.1' `.sse4.2' `.sse4'
11031 `.avx' `.vmx' `.smx' `.ept'
11032 `.clflush' `.movbe' `.xsave' `.xsaveopt'
11033 `.aes' `.pclmul' `.fma' `.fsgsbase'
11034 `.rdrnd' `.f16c' `.avx2' `.bmi2'
11035 `.lzcnt' `.invpcid' `.vmfunc' `.hle'
11036 `.rtm' `.adx' `.rdseed' `.prfchw'
11037 `.smap' `.mpx' `.sha' `.prefetchwt1'
11038 `.clflushopt' `.xsavec' `.xsaves' `.se1'
11039 `.avx512f' `.avx512cd' `.avx512er' `.avx512pf'
11040 `.avx512vl' `.avx512bw' `.avx512dq' `.avx512ifma'
11041 `.avx512vbmi' `.clwb' `.pcommit'
11042 `.3dnow' `.3dnowa' `.sse4a' `.sse5'
11043 `.syscall' `.rdtscp' `.svme' `.abm'
11044 `.lwp' `.fma4' `.xop' `.cx16'
11047 Apart from the warning, there are only two other effects on `as'
11048 operation; Firstly, if you specify a CPU other than `i486', then shift
11049 by one instructions such as `sarl $1, %eax' will automatically use a
11050 two byte opcode sequence. The larger three byte opcode sequence is
11051 used on the 486 (and when no architecture is specified) because it
11052 executes faster on the 486. Note that you can explicitly request the
11053 two byte opcode by writing `sarl %eax'. Secondly, if you specify
11054 `i8086', `i186', or `i286', _and_ `.code16' or `.code16gcc' then byte
11055 offset conditional jumps will be promoted when necessary to a two
11056 instruction sequence consisting of a conditional jump of the opposite
11057 sense around an unconditional jump to the target.
11059 Following the CPU architecture (but not a sub-architecture, which
11060 are those starting with a dot), you may specify `jumps' or `nojumps' to
11061 control automatic promotion of conditional jumps. `jumps' is the
11062 default, and enables jump promotion; All external jumps will be of the
11063 long variety, and file-local jumps will be promoted as necessary.
11064 (*note i386-Jumps::) `nojumps' leaves external conditional jumps as
11065 byte offset jumps, and warns about file-local conditional jumps that
11066 `as' promotes. Unconditional jumps are treated as for `jumps'.
11070 .arch i8086,nojumps
11073 File: as.info, Node: i386-Notes, Prev: i386-Bugs, Up: i386-Dependent
11078 There is some trickery concerning the `mul' and `imul' instructions
11079 that deserves mention. The 16-, 32-, 64- and 128-bit expanding
11080 multiplies (base opcode `0xf6'; extension 4 for `mul' and 5 for `imul')
11081 can be output only in the one operand form. Thus, `imul %ebx, %eax'
11082 does _not_ select the expanding multiply; the expanding multiply would
11083 clobber the `%edx' register, and this would confuse `gcc' output. Use
11084 `imul %ebx' to get the 64-bit product in `%edx:%eax'.
11086 We have added a two operand form of `imul' when the first operand is
11087 an immediate mode expression and the second operand is a register.
11088 This is just a shorthand, so that, multiplying `%eax' by 69, for
11089 example, can be done with `imul $69, %eax' rather than `imul $69, %eax,
11093 File: as.info, Node: i860-Dependent, Next: i960-Dependent, Prev: i386-Dependent, Up: Machine Dependencies
11095 9.16 Intel i860 Dependent Features
11096 ==================================
11100 * Notes-i860:: i860 Notes
11101 * Options-i860:: i860 Command-line Options
11102 * Directives-i860:: i860 Machine Directives
11103 * Opcodes for i860:: i860 Opcodes
11104 * Syntax of i860:: i860 Syntax
11107 File: as.info, Node: Notes-i860, Next: Options-i860, Up: i860-Dependent
11112 This is a fairly complete i860 assembler which is compatible with the
11113 UNIX System V/860 Release 4 assembler. However, it does not currently
11114 support SVR4 PIC (i.e., `@GOT, @GOTOFF, @PLT').
11116 Like the SVR4/860 assembler, the output object format is ELF32.
11117 Currently, this is the only supported object format. If there is
11118 sufficient interest, other formats such as COFF may be implemented.
11120 Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter
11121 being the default. One difference is that AT&T syntax requires the '%'
11122 prefix on register names while Intel syntax does not. Another
11123 difference is in the specification of relocatable expressions. The
11124 Intel syntax is `ha%expression' whereas the SVR4 syntax is
11125 `[expression]@ha' (and similarly for the "l" and "h" selectors).
11128 File: as.info, Node: Options-i860, Next: Directives-i860, Prev: Notes-i860, Up: i860-Dependent
11130 9.16.2 i860 Command-line Options
11131 --------------------------------
11133 9.16.2.1 SVR4 compatibility options
11134 ...................................
11137 Print assembler version.
11145 9.16.2.2 Other options
11146 ......................
11149 Select little endian output (this is the default).
11152 Select big endian output. Note that the i860 always reads
11153 instructions as little endian data, so this option only effects
11154 data and not instructions.
11157 Emit a warning message if any pseudo-instruction expansions
11158 occurred. For example, a `or' instruction with an immediate
11159 larger than 16-bits will be expanded into two instructions. This
11160 is a very undesirable feature to rely on, so this flag can help
11161 detect any code where it happens. One use of it, for instance, has
11162 been to find and eliminate any place where `gcc' may emit these
11163 pseudo-instructions.
11166 Enable support for the i860XP instructions and control registers.
11167 By default, this option is disabled so that only the base
11168 instruction set (i.e., i860XR) is supported.
11171 The i860 assembler defaults to AT&T/SVR4 syntax. This option
11172 enables the Intel syntax.
11175 File: as.info, Node: Directives-i860, Next: Opcodes for i860, Prev: Options-i860, Up: i860-Dependent
11177 9.16.3 i860 Machine Directives
11178 ------------------------------
11181 Enter dual instruction mode. While this directive is supported, the
11182 preferred way to use dual instruction mode is to explicitly code
11183 the dual bit with the `d.' prefix.
11186 Exit dual instruction mode. While this directive is supported, the
11187 preferred way to use dual instruction mode is to explicitly code
11188 the dual bit with the `d.' prefix.
11191 Change the temporary register used when expanding pseudo
11192 operations. The default register is `r31'.
11194 The `.dual', `.enddual', and `.atmp' directives are available only
11195 in the Intel syntax mode.
11197 Both syntaxes allow for the standard `.align' directive. However,
11198 the Intel syntax additionally allows keywords for the alignment
11199 parameter: "`.align type'", where `type' is one of `.short', `.long',
11200 `.quad', `.single', `.double' representing alignments of 2, 4, 16, 4,
11201 and 8, respectively.
11204 File: as.info, Node: Opcodes for i860, Next: Syntax of i860, Prev: Directives-i860, Up: i860-Dependent
11206 9.16.4 i860 Opcodes
11207 -------------------
11209 All of the Intel i860XR and i860XP machine instructions are supported.
11210 Please see either _i860 Microprocessor Programmer's Reference Manual_
11211 or _i860 Microprocessor Architecture_ for more information.
11213 9.16.4.1 Other instruction support (pseudo-instructions)
11214 ........................................................
11216 For compatibility with some other i860 assemblers, a number of
11217 pseudo-instructions are supported. While these are supported, they are
11218 a very undesirable feature that should be avoided - in particular, when
11219 they result in an expansion to multiple actual i860 instructions. Below
11220 are the pseudo-instructions that result in expansions.
11221 * Load large immediate into general register:
11223 The pseudo-instruction `mov imm,%rn' (where the immediate does not
11224 fit within a signed 16-bit field) will be expanded into:
11225 orh large_imm@h,%r0,%rn
11226 or large_imm@l,%rn,%rn
11228 * Load/store with relocatable address expression:
11230 For example, the pseudo-instruction `ld.b addr_exp(%rx),%rn' will
11232 orh addr_exp@ha,%rx,%r31
11233 ld.l addr_exp@l(%r31),%rn
11235 The analogous expansions apply to `ld.x, st.x, fld.x, pfld.x,
11236 fst.x', and `pst.x' as well.
11238 * Signed large immediate with add/subtract:
11240 If any of the arithmetic operations `adds, addu, subs, subu' are
11241 used with an immediate larger than 16-bits (signed), then they
11242 will be expanded. For instance, the pseudo-instruction `adds
11243 large_imm,%rx,%rn' expands to:
11244 orh large_imm@h,%r0,%r31
11245 or large_imm@l,%r31,%r31
11248 * Unsigned large immediate with logical operations:
11250 Logical operations (`or, andnot, or, xor') also result in
11251 expansions. The pseudo-instruction `or large_imm,%rx,%rn' results
11253 orh large_imm@h,%rx,%r31
11254 or large_imm@l,%r31,%rn
11256 Similarly for the others, except for `and' which expands to:
11257 andnot (-1 - large_imm)@h,%rx,%r31
11258 andnot (-1 - large_imm)@l,%r31,%rn
11261 File: as.info, Node: Syntax of i860, Prev: Opcodes for i860, Up: i860-Dependent
11268 * i860-Chars:: Special Characters
11271 File: as.info, Node: i860-Chars, Up: Syntax of i860
11273 9.16.5.1 Special Characters
11274 ...........................
11276 The presence of a `#' appearing anywhere on a line indicates the start
11277 of a comment that extends to the end of that line.
11279 If a `#' appears as the first character of a line then the whole
11280 line is treated as a comment, but in this case the line can also be a
11281 logical line number directive (*note Comments::) or a preprocessor
11282 control command (*note Preprocessing::).
11284 The `;' character can be used to separate statements on the same
11288 File: as.info, Node: i960-Dependent, Next: IA-64-Dependent, Prev: i860-Dependent, Up: Machine Dependencies
11290 9.17 Intel 80960 Dependent Features
11291 ===================================
11295 * Options-i960:: i960 Command-line Options
11296 * Floating Point-i960:: Floating Point
11297 * Directives-i960:: i960 Machine Directives
11298 * Opcodes for i960:: i960 Opcodes
11299 * Syntax of i960:: i960 Syntax
11302 File: as.info, Node: Options-i960, Next: Floating Point-i960, Up: i960-Dependent
11304 9.17.1 i960 Command-line Options
11305 --------------------------------
11307 `-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC'
11308 Select the 80960 architecture. Instructions or features not
11309 supported by the selected architecture cause fatal errors.
11311 `-ACA' is equivalent to `-ACA_A'; `-AKC' is equivalent to `-AMC'.
11312 Synonyms are provided for compatibility with other tools.
11314 If you do not specify any of these options, `as' generates code
11315 for any instruction or feature that is supported by _some_ version
11316 of the 960 (even if this means mixing architectures!). In
11317 principle, `as' attempts to deduce the minimal sufficient
11318 processor type if none is specified; depending on the object code
11319 format, the processor type may be recorded in the object file. If
11320 it is critical that the `as' output match a specific architecture,
11321 specify that architecture explicitly.
11324 Add code to collect information about conditional branches taken,
11325 for later optimization using branch prediction bits. (The
11326 conditional branch instructions have branch prediction bits in the
11327 CA, CB, and CC architectures.) If BR represents a conditional
11328 branch instruction, the following represents the code generated by
11329 the assembler when `-b' is specified:
11331 call INCREMENT ROUTINE
11332 .word 0 # pre-counter
11334 call INCREMENT ROUTINE
11335 .word 0 # post-counter
11337 The counter following a branch records the number of times that
11338 branch was _not_ taken; the difference between the two counters is
11339 the number of times the branch _was_ taken.
11341 A table of every such `Label' is also generated, so that the
11342 external postprocessor `gbr960' (supplied by Intel) can locate all
11343 the counters. This table is always labeled `__BRANCH_TABLE__';
11344 this is a local symbol to permit collecting statistics for many
11345 separate object files. The table is word aligned, and begins with
11346 a two-word header. The first word, initialized to 0, is used in
11347 maintaining linked lists of branch tables. The second word is a
11348 count of the number of entries in the table, which follow
11349 immediately: each is a word, pointing to one of the labels
11352 +------------+------------+------------+ ... +------------+
11354 | *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N |
11356 +------------+------------+------------+ ... +------------+
11358 __BRANCH_TABLE__ layout
11360 The first word of the header is used to locate multiple branch
11361 tables, since each object file may contain one. Normally the links
11362 are maintained with a call to an initialization routine, placed at
11363 the beginning of each function in the file. The GNU C compiler
11364 generates these calls automatically when you give it a `-b' option.
11365 For further details, see the documentation of `gbr960'.
11368 Normally, Compare-and-Branch instructions with targets that require
11369 displacements greater than 13 bits (or that have external targets)
11370 are replaced with the corresponding compare (or `chkbit') and
11371 branch instructions. You can use the `-no-relax' option to
11372 specify that `as' should generate errors instead, if the target
11373 displacement is larger than 13 bits.
11375 This option does not affect the Compare-and-Jump instructions; the
11376 code emitted for them is _always_ adjusted when necessary
11377 (depending on displacement size), regardless of whether you use
11381 File: as.info, Node: Floating Point-i960, Next: Directives-i960, Prev: Options-i960, Up: i960-Dependent
11383 9.17.2 Floating Point
11384 ---------------------
11386 `as' generates IEEE floating-point numbers for the directives `.float',
11387 `.double', `.extended', and `.single'.
11390 File: as.info, Node: Directives-i960, Next: Opcodes for i960, Prev: Floating Point-i960, Up: i960-Dependent
11392 9.17.3 i960 Machine Directives
11393 ------------------------------
11395 `.bss SYMBOL, LENGTH, ALIGN'
11396 Reserve LENGTH bytes in the bss section for a local SYMBOL,
11397 aligned to the power of two specified by ALIGN. LENGTH and ALIGN
11398 must be positive absolute expressions. This directive differs
11399 from `.lcomm' only in that it permits you to specify an alignment.
11400 *Note `.lcomm': Lcomm.
11402 `.extended FLONUMS'
11403 `.extended' expects zero or more flonums, separated by commas; for
11404 each flonum, `.extended' emits an IEEE extended-format (80-bit)
11405 floating-point number.
11407 `.leafproc CALL-LAB, BAL-LAB'
11408 You can use the `.leafproc' directive in conjunction with the
11409 optimized `callj' instruction to enable faster calls of leaf
11410 procedures. If a procedure is known to call no other procedures,
11411 you may define an entry point that skips procedure prolog code
11412 (and that does not depend on system-supplied saved context), and
11413 declare it as the BAL-LAB using `.leafproc'. If the procedure
11414 also has an entry point that goes through the normal prolog, you
11415 can specify that entry point as CALL-LAB.
11417 A `.leafproc' declaration is meant for use in conjunction with the
11418 optimized call instruction `callj'; the directive records the data
11419 needed later to choose between converting the `callj' into a `bal'
11422 CALL-LAB is optional; if only one argument is present, or if the
11423 two arguments are identical, the single argument is assumed to be
11424 the `bal' entry point.
11426 `.sysproc NAME, INDEX'
11427 The `.sysproc' directive defines a name for a system procedure.
11428 After you define it using `.sysproc', you can use NAME to refer to
11429 the system procedure identified by INDEX when calling procedures
11430 with the optimized call instruction `callj'.
11432 Both arguments are required; INDEX must be between 0 and 31
11436 File: as.info, Node: Opcodes for i960, Next: Syntax of i960, Prev: Directives-i960, Up: i960-Dependent
11438 9.17.4 i960 Opcodes
11439 -------------------
11441 All Intel 960 machine instructions are supported; *note i960
11442 Command-line Options: Options-i960. for a discussion of selecting the
11443 instruction subset for a particular 960 architecture.
11445 Some opcodes are processed beyond simply emitting a single
11446 corresponding instruction: `callj', and Compare-and-Branch or
11447 Compare-and-Jump instructions with target displacements larger than 13
11452 * callj-i960:: `callj'
11453 * Compare-and-branch-i960:: Compare-and-Branch
11456 File: as.info, Node: callj-i960, Next: Compare-and-branch-i960, Up: Opcodes for i960
11461 You can write `callj' to have the assembler or the linker determine the
11462 most appropriate form of subroutine call: `call', `bal', or `calls'.
11463 If the assembly source contains enough information--a `.leafproc' or
11464 `.sysproc' directive defining the operand--then `as' translates the
11465 `callj'; if not, it simply emits the `callj', leaving it for the linker
11469 File: as.info, Node: Compare-and-branch-i960, Prev: callj-i960, Up: Opcodes for i960
11471 9.17.4.2 Compare-and-Branch
11472 ...........................
11474 The 960 architectures provide combined Compare-and-Branch instructions
11475 that permit you to store the branch target in the lower 13 bits of the
11476 instruction word itself. However, if you specify a branch target far
11477 enough away that its address won't fit in 13 bits, the assembler can
11478 either issue an error, or convert your Compare-and-Branch instruction
11479 into separate instructions to do the compare and the branch.
11481 Whether `as' gives an error or expands the instruction depends on
11482 two choices you can make: whether you use the `-no-relax' option, and
11483 whether you use a "Compare and Branch" instruction or a "Compare and
11484 Jump" instruction. The "Jump" instructions are _always_ expanded if
11485 necessary; the "Branch" instructions are expanded when necessary
11486 _unless_ you specify `-no-relax'--in which case `as' gives an error
11489 These are the Compare-and-Branch instructions, their "Jump" variants,
11490 and the instruction pairs they may expand into:
11493 Branch Jump Expanded to
11494 ------ ------ ------------
11497 cmpibe cmpije cmpi; be
11498 cmpibg cmpijg cmpi; bg
11499 cmpibge cmpijge cmpi; bge
11500 cmpibl cmpijl cmpi; bl
11501 cmpible cmpijle cmpi; ble
11502 cmpibno cmpijno cmpi; bno
11503 cmpibne cmpijne cmpi; bne
11504 cmpibo cmpijo cmpi; bo
11505 cmpobe cmpoje cmpo; be
11506 cmpobg cmpojg cmpo; bg
11507 cmpobge cmpojge cmpo; bge
11508 cmpobl cmpojl cmpo; bl
11509 cmpoble cmpojle cmpo; ble
11510 cmpobne cmpojne cmpo; bne
11513 File: as.info, Node: Syntax of i960, Prev: Opcodes for i960, Up: i960-Dependent
11515 9.17.5 Syntax for the i960
11516 --------------------------
11520 * i960-Chars:: Special Characters
11523 File: as.info, Node: i960-Chars, Up: Syntax of i960
11525 9.17.5.1 Special Characters
11526 ...........................
11528 The presence of a `#' on a line indicates the start of a comment that
11529 extends to the end of the current line.
11531 If a `#' appears as the first character of a line, the whole line is
11532 treated as a comment, but in this case the line can also be a logical
11533 line number directive (*note Comments::) or a preprocessor control
11534 command (*note Preprocessing::).
11536 The `;' character can be used to separate statements on the same
11540 File: as.info, Node: IA-64-Dependent, Next: IP2K-Dependent, Prev: i960-Dependent, Up: Machine Dependencies
11542 9.18 IA-64 Dependent Features
11543 =============================
11547 * IA-64 Options:: Options
11548 * IA-64 Syntax:: Syntax
11549 * IA-64 Opcodes:: Opcodes
11552 File: as.info, Node: IA-64 Options, Next: IA-64 Syntax, Up: IA-64-Dependent
11558 This option instructs the assembler to mark the resulting object
11559 file as using the "constant GP" model. With this model, it is
11560 assumed that the entire program uses a single global pointer (GP)
11561 value. Note that this option does not in any fashion affect the
11562 machine code emitted by the assembler. All it does is turn on the
11563 EF_IA_64_CONS_GP flag in the ELF file header.
11566 This option instructs the assembler to mark the resulting object
11567 file as using the "constant GP without function descriptor" data
11568 model. This model is like the "constant GP" model, except that it
11569 additionally does away with function descriptors. What this means
11570 is that the address of a function refers directly to the
11571 function's code entry-point. Normally, such an address would
11572 refer to a function descriptor, which contains both the code
11573 entry-point and the GP-value needed by the function. Note that
11574 this option does not in any fashion affect the machine code
11575 emitted by the assembler. All it does is turn on the
11576 EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header.
11582 These options select the data model. The assembler defaults to
11583 `-mlp64' (LP64 data model).
11587 These options select the byte order. The `-mle' option selects
11588 little-endian byte order (default) and `-mbe' selects big-endian
11589 byte order. Note that IA-64 machine code always uses
11590 little-endian byte order.
11594 Tune for a particular IA-64 CPU, ITANIUM1 or ITANIUM2. The default
11597 `-munwind-check=warning'
11598 `-munwind-check=error'
11599 These options control what the assembler will do when performing
11600 consistency checks on unwind directives. `-munwind-check=warning'
11601 will make the assembler issue a warning when an unwind directive
11602 check fails. This is the default. `-munwind-check=error' will
11603 make the assembler issue an error when an unwind directive check
11609 These options control what the assembler will do when the `hint.b'
11610 instruction is used. `-mhint.b=ok' will make the assembler accept
11611 `hint.b'. `-mint.b=warning' will make the assembler issue a
11612 warning when `hint.b' is used. `-mhint.b=error' will make the
11613 assembler treat `hint.b' as an error, which is the default.
11617 These options turn on dependency violation checking.
11620 This option instructs the assembler to automatically insert stop
11621 bits where necessary to remove dependency violations. This is the
11625 This option turns off dependency violation checking.
11628 This turns on debug output intended to help tracking down bugs in
11629 the dependency violation checker.
11632 This is a shortcut for -xnone -xdebug.
11635 This is a shortcut for -xexplicit -xdebug.
11639 File: as.info, Node: IA-64 Syntax, Next: IA-64 Opcodes, Prev: IA-64 Options, Up: IA-64-Dependent
11644 The assembler syntax closely follows the IA-64 Assembly Language
11649 * IA-64-Chars:: Special Characters
11650 * IA-64-Regs:: Register Names
11651 * IA-64-Bits:: Bit Names
11652 * IA-64-Relocs:: Relocations
11655 File: as.info, Node: IA-64-Chars, Next: IA-64-Regs, Up: IA-64 Syntax
11657 9.18.2.1 Special Characters
11658 ...........................
11660 `//' is the line comment token.
11662 `;' can be used instead of a newline to separate statements.
11665 File: as.info, Node: IA-64-Regs, Next: IA-64-Bits, Prev: IA-64-Chars, Up: IA-64 Syntax
11667 9.18.2.2 Register Names
11668 .......................
11670 The 128 integer registers are referred to as `rN'. The 128
11671 floating-point registers are referred to as `fN'. The 128 application
11672 registers are referred to as `arN'. The 128 control registers are
11673 referred to as `crN'. The 64 one-bit predicate registers are referred
11674 to as `pN'. The 8 branch registers are referred to as `bN'. In
11675 addition, the assembler defines a number of aliases: `gp' (`r1'), `sp'
11676 (`r12'), `rp' (`b0'), `ret0' (`r8'), `ret1' (`r9'), `ret2' (`r10'),
11677 `ret3' (`r9'), `fargN' (`f8+N'), and `fretN' (`f8+N').
11679 For convenience, the assembler also defines aliases for all named
11680 application and control registers. For example, `ar.bsp' refers to the
11681 register backing store pointer (`ar17'). Similarly, `cr.eoi' refers to
11682 the end-of-interrupt register (`cr67').
11685 File: as.info, Node: IA-64-Bits, Next: IA-64-Relocs, Prev: IA-64-Regs, Up: IA-64 Syntax
11687 9.18.2.3 IA-64 Processor-Status-Register (PSR) Bit Names
11688 ........................................................
11690 The assembler defines bit masks for each of the bits in the IA-64
11691 processor status register. For example, `psr.ic' corresponds to a
11692 value of 0x2000. These masks are primarily intended for use with the
11693 `ssm'/`sum' and `rsm'/`rum' instructions, but they can be used anywhere
11694 else where an integer constant is expected.
11697 File: as.info, Node: IA-64-Relocs, Prev: IA-64-Bits, Up: IA-64 Syntax
11699 9.18.2.4 Relocations
11700 ....................
11702 In addition to the standard IA-64 relocations, the following
11703 relocations are implemented by `as':
11706 Convert the address offset V into a slot count. This pseudo
11707 function is available only on VMS. The expression V must be known
11708 at assembly time: it can't reference undefined symbols or symbols
11709 in different sections.
11712 File: as.info, Node: IA-64 Opcodes, Prev: IA-64 Syntax, Up: IA-64-Dependent
11717 For detailed information on the IA-64 machine instruction set, see the
11718 IA-64 Architecture Handbook
11719 (http://developer.intel.com/design/itanium/arch_spec.htm).
11722 File: as.info, Node: IP2K-Dependent, Next: LM32-Dependent, Prev: IA-64-Dependent, Up: Machine Dependencies
11724 9.19 IP2K Dependent Features
11725 ============================
11729 * IP2K-Opts:: IP2K Options
11730 * IP2K-Syntax:: IP2K Syntax
11733 File: as.info, Node: IP2K-Opts, Next: IP2K-Syntax, Up: IP2K-Dependent
11735 9.19.1 IP2K Options
11736 -------------------
11738 The Ubicom IP2K version of `as' has a few machine dependent options:
11741 `as' can assemble the extended IP2022 instructions, but it will
11742 only do so if this is specifically allowed via this command line
11746 This option restores the assembler's default behaviour of not
11747 permitting the extended IP2022 instructions to be assembled.
11751 File: as.info, Node: IP2K-Syntax, Prev: IP2K-Opts, Up: IP2K-Dependent
11758 * IP2K-Chars:: Special Characters
11761 File: as.info, Node: IP2K-Chars, Up: IP2K-Syntax
11763 9.19.2.1 Special Characters
11764 ...........................
11766 The presence of a `;' on a line indicates the start of a comment that
11767 extends to the end of the current line.
11769 If a `#' appears as the first character of a line, the whole line is
11770 treated as a comment, but in this case the line can also be a logical
11771 line number directive (*note Comments::) or a preprocessor control
11772 command (*note Preprocessing::).
11774 The IP2K assembler does not currently support a line separator
11778 File: as.info, Node: LM32-Dependent, Next: M32C-Dependent, Prev: IP2K-Dependent, Up: Machine Dependencies
11780 9.20 LM32 Dependent Features
11781 ============================
11785 * LM32 Options:: Options
11786 * LM32 Syntax:: Syntax
11787 * LM32 Opcodes:: Opcodes
11790 File: as.info, Node: LM32 Options, Next: LM32 Syntax, Up: LM32-Dependent
11795 `-mmultiply-enabled'
11796 Enable multiply instructions.
11799 Enable divide instructions.
11801 `-mbarrel-shift-enabled'
11802 Enable barrel-shift instructions.
11804 `-msign-extend-enabled'
11805 Enable sign extend instructions.
11808 Enable user defined instructions.
11811 Enable instruction cache related CSRs.
11814 Enable data cache related CSRs.
11817 Enable break instructions.
11820 Enable all instructions and CSRs.
11824 File: as.info, Node: LM32 Syntax, Next: LM32 Opcodes, Prev: LM32 Options, Up: LM32-Dependent
11831 * LM32-Regs:: Register Names
11832 * LM32-Modifiers:: Relocatable Expression Modifiers
11833 * LM32-Chars:: Special Characters
11836 File: as.info, Node: LM32-Regs, Next: LM32-Modifiers, Up: LM32 Syntax
11838 9.20.2.1 Register Names
11839 .......................
11841 LM32 has 32 x 32-bit general purpose registers `r0', `r1', ... `r31'.
11843 The following aliases are defined: `gp' - `r26', `fp' - `r27', `sp'
11844 - `r28', `ra' - `r29', `ea' - `r30', `ba' - `r31'.
11846 LM32 has the following Control and Status Registers (CSRs).
11858 Instruction cache control.
11861 Data cache control.
11870 Exception base address.
11876 Debug exception base address.
11909 File: as.info, Node: LM32-Modifiers, Next: LM32-Chars, Prev: LM32-Regs, Up: LM32 Syntax
11911 9.20.2.2 Relocatable Expression Modifiers
11912 .........................................
11914 The assembler supports several modifiers when using relocatable
11915 addresses in LM32 instruction operands. The general syntax is the
11918 modifier(relocatable-expression)
11921 This modifier allows you to use bits 0 through 15 of an address
11922 expression as 16 bit relocatable expression.
11925 This modifier allows you to use bits 16 through 23 of an address
11926 expression as 16 bit relocatable expression.
11930 ori r4, r4, lo(sym+10)
11931 orhi r4, r4, hi(sym+10)
11934 This modified creates a 16-bit relocatable expression that is the
11935 offset of the symbol from the global pointer.
11940 This modifier places a symbol in the GOT and creates a 16-bit
11941 relocatable expression that is the offset into the GOT of this
11944 lw r4, (gp+got(sym))
11947 This modifier allows you to use the bits 0 through 15 of an
11948 address which is an offset from the GOT.
11951 This modifier allows you to use the bits 16 through 31 of an
11952 address which is an offset from the GOT.
11954 orhi r4, r4, gotoffhi16(lsym)
11955 addi r4, r4, gotofflo16(lsym)
11959 File: as.info, Node: LM32-Chars, Prev: LM32-Modifiers, Up: LM32 Syntax
11961 9.20.2.3 Special Characters
11962 ...........................
11964 The presence of a `#' on a line indicates the start of a comment that
11965 extends to the end of the current line. Note that if a line starts
11966 with a `#' character then it can also be a logical line number
11967 directive (*note Comments::) or a preprocessor control command (*note
11970 A semicolon (`;') can be used to separate multiple statements on the
11974 File: as.info, Node: LM32 Opcodes, Prev: LM32 Syntax, Up: LM32-Dependent
11979 For detailed information on the LM32 machine instruction set, see
11980 `http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/'.
11982 `as' implements all the standard LM32 opcodes.
11985 File: as.info, Node: M32C-Dependent, Next: M32R-Dependent, Prev: LM32-Dependent, Up: Machine Dependencies
11987 9.21 M32C Dependent Features
11988 ============================
11990 `as' can assemble code for several different members of the Renesas
11991 M32C family. Normally the default is to assemble code for the M16C
11992 microprocessor. The `-m32c' option may be used to change the default
11993 to the M32C microprocessor.
11997 * M32C-Opts:: M32C Options
11998 * M32C-Syntax:: M32C Syntax
12001 File: as.info, Node: M32C-Opts, Next: M32C-Syntax, Up: M32C-Dependent
12003 9.21.1 M32C Options
12004 -------------------
12006 The Renesas M32C version of `as' has these machine-dependent options:
12009 Assemble M32C instructions.
12012 Assemble M16C instructions (default).
12015 Enable support for link-time relaxations.
12018 Support H'00 style hex constants in addition to 0x00 style.
12022 File: as.info, Node: M32C-Syntax, Prev: M32C-Opts, Up: M32C-Dependent
12029 * M32C-Modifiers:: Symbolic Operand Modifiers
12030 * M32C-Chars:: Special Characters
12033 File: as.info, Node: M32C-Modifiers, Next: M32C-Chars, Up: M32C-Syntax
12035 9.21.2.1 Symbolic Operand Modifiers
12036 ...................................
12038 The assembler supports several modifiers when using symbol addresses in
12039 M32C instruction operands. The general syntax is the following:
12045 These modifiers override the assembler's assumptions about how big
12046 a symbol's address is. Normally, when it sees an operand like
12047 `sym[a0]' it assumes `sym' may require the widest displacement
12048 field (16 bits for `-m16c', 24 bits for `-m32c'). These modifiers
12049 tell it to assume the address will fit in an 8 or 16 bit
12050 (respectively) unsigned displacement. Note that, of course, if it
12051 doesn't actually fit you will get linker errors. Example:
12053 mov.w %dsp8(sym)[a0],r1
12054 mov.b #0,%dsp8(sym)[a0]
12057 This modifier allows you to load bits 16 through 23 of a 24 bit
12058 address into an 8 bit register. This is useful with, for example,
12059 the M16C `smovf' instruction, which expects a 20 bit address in
12060 `r1h' and `a0'. Example:
12062 mov.b #%hi8(sym),r1h
12063 mov.w #%lo16(sym),a0
12067 Likewise, this modifier allows you to load bits 0 through 15 of a
12068 24 bit address into a 16 bit register.
12071 This modifier allows you to load bits 16 through 31 of a 32 bit
12072 address into a 16 bit register. While the M32C family only has 24
12073 bits of address space, it does support addresses in pairs of 16 bit
12074 registers (like `a1a0' for the `lde' instruction). This modifier
12075 is for loading the upper half in such cases. Example:
12077 mov.w #%hi16(sym),a1
12078 mov.w #%lo16(sym),a0
12084 File: as.info, Node: M32C-Chars, Prev: M32C-Modifiers, Up: M32C-Syntax
12086 9.21.2.2 Special Characters
12087 ...........................
12089 The presence of a `;' character on a line indicates the start of a
12090 comment that extends to the end of that line.
12092 If a `#' appears as the first character of a line, the whole line is
12093 treated as a comment, but in this case the line can also be a logical
12094 line number directive (*note Comments::) or a preprocessor control
12095 command (*note Preprocessing::).
12097 The `|' character can be used to separate statements on the same
12101 File: as.info, Node: M32R-Dependent, Next: M68K-Dependent, Prev: M32C-Dependent, Up: Machine Dependencies
12103 9.22 M32R Dependent Features
12104 ============================
12108 * M32R-Opts:: M32R Options
12109 * M32R-Directives:: M32R Directives
12110 * M32R-Warnings:: M32R Warnings
12113 File: as.info, Node: M32R-Opts, Next: M32R-Directives, Up: M32R-Dependent
12115 9.22.1 M32R Options
12116 -------------------
12118 The Renease M32R version of `as' has a few machine dependent options:
12121 `as' can assemble code for several different members of the
12122 Renesas M32R family. Normally the default is to assemble code for
12123 the M32R microprocessor. This option may be used to change the
12124 default to the M32RX microprocessor, which adds some more
12125 instructions to the basic M32R instruction set, and some
12126 additional parameters to some of the original instructions.
12129 This option changes the target processor to the M32R2
12133 This option can be used to restore the assembler's default
12134 behaviour of assembling for the M32R microprocessor. This can be
12135 useful if the default has been changed by a previous command line
12139 This option tells the assembler to produce little-endian code and
12140 data. The default is dependent upon how the toolchain was
12144 This is a synonym for _-little_.
12147 This option tells the assembler to produce big-endian code and
12151 This is a synonum for _-big_.
12154 This option specifies that the output of the assembler should be
12155 marked as position-independent code (PIC).
12158 This option tells the assembler to attempts to combine two
12159 sequential instructions into a single, parallel instruction, where
12160 it is legal to do so.
12163 This option disables a previously enabled _-parallel_ option.
12166 This option disables the support for the extended bit-field
12167 instructions provided by the M32R2. If this support needs to be
12168 re-enabled the _-bitinst_ switch can be used to restore it.
12171 This option tells the assembler to attempt to optimize the
12172 instructions that it produces. This includes filling delay slots
12173 and converting sequential instructions into parallel ones. This
12174 option implies _-parallel_.
12176 `-warn-explicit-parallel-conflicts'
12177 Instructs `as' to produce warning messages when questionable
12178 parallel instructions are encountered. This option is enabled by
12179 default, but `gcc' disables it when it invokes `as' directly.
12180 Questionable instructions are those whose behaviour would be
12181 different if they were executed sequentially. For example the
12182 code fragment `mv r1, r2 || mv r3, r1' produces a different result
12183 from `mv r1, r2 \n mv r3, r1' since the former moves r1 into r3
12184 and then r2 into r1, whereas the later moves r2 into r1 and r3.
12187 This is a shorter synonym for the
12188 _-warn-explicit-parallel-conflicts_ option.
12190 `-no-warn-explicit-parallel-conflicts'
12191 Instructs `as' not to produce warning messages when questionable
12192 parallel instructions are encountered.
12195 This is a shorter synonym for the
12196 _-no-warn-explicit-parallel-conflicts_ option.
12198 `-ignore-parallel-conflicts'
12199 This option tells the assembler's to stop checking parallel
12200 instructions for constraint violations. This ability is provided
12201 for hardware vendors testing chip designs and should not be used
12202 under normal circumstances.
12204 `-no-ignore-parallel-conflicts'
12205 This option restores the assembler's default behaviour of checking
12206 parallel instructions to detect constraint violations.
12209 This is a shorter synonym for the _-ignore-parallel-conflicts_
12213 This is a shorter synonym for the _-no-ignore-parallel-conflicts_
12216 `-warn-unmatched-high'
12217 This option tells the assembler to produce a warning message if a
12218 `.high' pseudo op is encountered without a matching `.low' pseudo
12219 op. The presence of such an unmatched pseudo op usually indicates
12220 a programming error.
12222 `-no-warn-unmatched-high'
12223 Disables a previously enabled _-warn-unmatched-high_ option.
12226 This is a shorter synonym for the _-warn-unmatched-high_ option.
12229 This is a shorter synonym for the _-no-warn-unmatched-high_ option.
12233 File: as.info, Node: M32R-Directives, Next: M32R-Warnings, Prev: M32R-Opts, Up: M32R-Dependent
12235 9.22.2 M32R Directives
12236 ----------------------
12238 The Renease M32R version of `as' has a few architecture specific
12242 The `low' directive computes the value of its expression and
12243 places the lower 16-bits of the result into the immediate-field of
12244 the instruction. For example:
12246 or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678
12247 add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred
12250 The `high' directive computes the value of its expression and
12251 places the upper 16-bits of the result into the immediate-field of
12252 the instruction. For example:
12254 seth r0, #high(0x12345678) ; compute r0 = 0x12340000
12255 seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred
12258 The `shigh' directive is very similar to the `high' directive. It
12259 also computes the value of its expression and places the upper
12260 16-bits of the result into the immediate-field of the instruction.
12261 The difference is that `shigh' also checks to see if the lower
12262 16-bits could be interpreted as a signed number, and if so it
12263 assumes that a borrow will occur from the upper-16 bits. To
12264 compensate for this the `shigh' directive pre-biases the upper 16
12265 bit value by adding one to it. For example:
12269 seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000
12270 seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000
12272 In the second example the lower 16-bits are 0x8000. If these are
12273 treated as a signed value and sign extended to 32-bits then the
12274 value becomes 0xffff8000. If this value is then added to
12275 0x00010000 then the result is 0x00008000.
12277 This behaviour is to allow for the different semantics of the
12278 `or3' and `add3' instructions. The `or3' instruction treats its
12279 16-bit immediate argument as unsigned whereas the `add3' treats
12280 its 16-bit immediate as a signed value. So for example:
12282 seth r0, #shigh(0x00008000)
12283 add3 r0, r0, #low(0x00008000)
12285 Produces the correct result in r0, whereas:
12287 seth r0, #shigh(0x00008000)
12288 or3 r0, r0, #low(0x00008000)
12290 Stores 0xffff8000 into r0.
12292 Note - the `shigh' directive does not know where in the assembly
12293 source code the lower 16-bits of the value are going set, so it
12294 cannot check to make sure that an `or3' instruction is being used
12295 rather than an `add3' instruction. It is up to the programmer to
12296 make sure that correct directives are used.
12299 The directive performs a similar thing as the _-m32r_ command line
12300 option. It tells the assembler to only accept M32R instructions
12301 from now on. An instructions from later M32R architectures are
12305 The directive performs a similar thing as the _-m32rx_ command
12306 line option. It tells the assembler to start accepting the extra
12307 instructions in the M32RX ISA as well as the ordinary M32R ISA.
12310 The directive performs a similar thing as the _-m32r2_ command
12311 line option. It tells the assembler to start accepting the extra
12312 instructions in the M32R2 ISA as well as the ordinary M32R ISA.
12315 The directive performs a similar thing as the _-little_ command
12316 line option. It tells the assembler to start producing
12317 little-endian code and data. This option should be used with care
12318 as producing mixed-endian binary files is fraught with danger.
12321 The directive performs a similar thing as the _-big_ command line
12322 option. It tells the assembler to start producing big-endian code
12323 and data. This option should be used with care as producing
12324 mixed-endian binary files is fraught with danger.
12328 File: as.info, Node: M32R-Warnings, Prev: M32R-Directives, Up: M32R-Dependent
12330 9.22.3 M32R Warnings
12331 --------------------
12333 There are several warning and error messages that can be produced by
12334 `as' which are specific to the M32R:
12336 `output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?'
12337 This message is only produced if warnings for explicit parallel
12338 conflicts have been enabled. It indicates that the assembler has
12339 encountered a parallel instruction in which the destination
12340 register of the left hand instruction is used as an input register
12341 in the right hand instruction. For example in this code fragment
12342 `mv r1, r2 || neg r3, r1' register r1 is the destination of the
12343 move instruction and the input to the neg instruction.
12345 `output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?'
12346 This message is only produced if warnings for explicit parallel
12347 conflicts have been enabled. It indicates that the assembler has
12348 encountered a parallel instruction in which the destination
12349 register of the right hand instruction is used as an input
12350 register in the left hand instruction. For example in this code
12351 fragment `mv r1, r2 || neg r2, r3' register r2 is the destination
12352 of the neg instruction and the input to the move instruction.
12354 `instruction `...' is for the M32RX only'
12355 This message is produced when the assembler encounters an
12356 instruction which is only supported by the M32Rx processor, and
12357 the `-m32rx' command line flag has not been specified to allow
12358 assembly of such instructions.
12360 `unknown instruction `...''
12361 This message is produced when the assembler encounters an
12362 instruction which it does not recognize.
12364 `only the NOP instruction can be issued in parallel on the m32r'
12365 This message is produced when the assembler encounters a parallel
12366 instruction which does not involve a NOP instruction and the
12367 `-m32rx' command line flag has not been specified. Only the M32Rx
12368 processor is able to execute two instructions in parallel.
12370 `instruction `...' cannot be executed in parallel.'
12371 This message is produced when the assembler encounters a parallel
12372 instruction which is made up of one or two instructions which
12373 cannot be executed in parallel.
12375 `Instructions share the same execution pipeline'
12376 This message is produced when the assembler encounters a parallel
12377 instruction whoes components both use the same execution pipeline.
12379 `Instructions write to the same destination register.'
12380 This message is produced when the assembler encounters a parallel
12381 instruction where both components attempt to modify the same
12382 register. For example these code fragments will produce this
12383 message: `mv r1, r2 || neg r1, r3' `jl r0 || mv r14, r1' `st r2,
12384 @-r1 || mv r1, r3' `mv r1, r2 || ld r0, @r1+' `cmp r1, r2 || addx
12385 r3, r4' (Both write to the condition bit)
12389 File: as.info, Node: M68K-Dependent, Next: M68HC11-Dependent, Prev: M32R-Dependent, Up: Machine Dependencies
12391 9.23 M680x0 Dependent Features
12392 ==============================
12396 * M68K-Opts:: M680x0 Options
12397 * M68K-Syntax:: Syntax
12398 * M68K-Moto-Syntax:: Motorola Syntax
12399 * M68K-Float:: Floating Point
12400 * M68K-Directives:: 680x0 Machine Directives
12401 * M68K-opcodes:: Opcodes
12404 File: as.info, Node: M68K-Opts, Next: M68K-Syntax, Up: M68K-Dependent
12406 9.23.1 M680x0 Options
12407 ---------------------
12409 The Motorola 680x0 version of `as' has a few machine dependent options:
12411 `-march=ARCHITECTURE'
12412 This option specifies a target architecture. The following
12413 architectures are recognized: `68000', `68010', `68020', `68030',
12414 `68040', `68060', `cpu32', `isaa', `isaaplus', `isab', `isac' and
12418 This option specifies a target cpu. When used in conjunction with
12419 the `-march' option, the cpu must be within the specified
12420 architecture. Also, the generic features of the architecture are
12421 used for instruction generation, rather than those of the specific
12431 Enable or disable various architecture specific features. If a
12432 chip or architecture by default supports an option (for instance
12433 `-march=isaaplus' includes the `-mdiv' option), explicitly
12434 disabling the option will override the default.
12437 You can use the `-l' option to shorten the size of references to
12438 undefined symbols. If you do not use the `-l' option, references
12439 to undefined symbols are wide enough for a full `long' (32 bits).
12440 (Since `as' cannot know where these symbols end up, `as' can only
12441 allocate space for the linker to fill in later. Since `as' does
12442 not know how far away these symbols are, it allocates as much
12443 space as it can.) If you use this option, the references are only
12444 one word wide (16 bits). This may be useful if you want the
12445 object file to be as small as possible, and you know that the
12446 relevant symbols are always less than 17 bits away.
12448 `--register-prefix-optional'
12449 For some configurations, especially those where the compiler
12450 normally does not prepend an underscore to the names of user
12451 variables, the assembler requires a `%' before any use of a
12452 register name. This is intended to let the assembler distinguish
12453 between C variables and functions named `a0' through `a7', and so
12454 on. The `%' is always accepted, but is not required for certain
12455 configurations, notably `sun3'. The `--register-prefix-optional'
12456 option may be used to permit omitting the `%' even for
12457 configurations for which it is normally required. If this is
12458 done, it will generally be impossible to refer to C variables and
12459 functions with the same names as register names.
12462 Normally the character `|' is treated as a comment character, which
12463 means that it can not be used in expressions. The `--bitwise-or'
12464 option turns `|' into a normal character. In this mode, you must
12465 either use C style comments, or start comments with a `#' character
12466 at the beginning of a line.
12468 `--base-size-default-16 --base-size-default-32'
12469 If you use an addressing mode with a base register without
12470 specifying the size, `as' will normally use the full 32 bit value.
12471 For example, the addressing mode `%a0@(%d0)' is equivalent to
12472 `%a0@(%d0:l)'. You may use the `--base-size-default-16' option to
12473 tell `as' to default to using the 16 bit value. In this case,
12474 `%a0@(%d0)' is equivalent to `%a0@(%d0:w)'. You may use the
12475 `--base-size-default-32' option to restore the default behaviour.
12477 `--disp-size-default-16 --disp-size-default-32'
12478 If you use an addressing mode with a displacement, and the value
12479 of the displacement is not known, `as' will normally assume that
12480 the value is 32 bits. For example, if the symbol `disp' has not
12481 been defined, `as' will assemble the addressing mode
12482 `%a0@(disp,%d0)' as though `disp' is a 32 bit value. You may use
12483 the `--disp-size-default-16' option to tell `as' to instead assume
12484 that the displacement is 16 bits. In this case, `as' will
12485 assemble `%a0@(disp,%d0)' as though `disp' is a 16 bit value. You
12486 may use the `--disp-size-default-32' option to restore the default
12490 Always keep branches PC-relative. In the M680x0 architecture all
12491 branches are defined as PC-relative. However, on some processors
12492 they are limited to word displacements maximum. When `as' needs a
12493 long branch that is not available, it normally emits an absolute
12494 jump instead. This option disables this substitution. When this
12495 option is given and no long branches are available, only word
12496 branches will be emitted. An error message will be generated if a
12497 word branch cannot reach its target. This option has no effect on
12498 68020 and other processors that have long branches. *note Branch
12499 Improvement: M68K-Branch.
12502 `as' can assemble code for several different members of the
12503 Motorola 680x0 family. The default depends upon how `as' was
12504 configured when it was built; normally, the default is to assemble
12505 code for the 68020 microprocessor. The following options may be
12506 used to change the default. These options control which
12507 instructions and addressing modes are permitted. The members of
12508 the 680x0 family are very similar. For detailed information about
12509 the differences, see the Motorola manuals.
12521 Assemble for the 68000. `-m68008', `-m68302', and so on are
12522 synonyms for `-m68000', since the chips are the same from the
12523 point of view of the assembler.
12526 Assemble for the 68010.
12530 Assemble for the 68020. This is normally the default.
12534 Assemble for the 68030.
12538 Assemble for the 68040.
12542 Assemble for the 68060.
12555 Assemble for the CPU32 family of chips.
12571 Assemble for the ColdFire family of chips.
12575 Assemble 68881 floating point instructions. This is the
12576 default for the 68020, 68030, and the CPU32. The 68040 and
12577 68060 always support floating point instructions.
12580 Do not assemble 68881 floating point instructions. This is
12581 the default for 68000 and the 68010. The 68040 and 68060
12582 always support floating point instructions, even if this
12586 Assemble 68851 MMU instructions. This is the default for the
12587 68020, 68030, and 68060. The 68040 accepts a somewhat
12588 different set of MMU instructions; `-m68851' and `-m68040'
12589 should not be used together.
12592 Do not assemble 68851 MMU instructions. This is the default
12593 for the 68000, 68010, and the CPU32. The 68040 accepts a
12594 somewhat different set of MMU instructions.
12597 File: as.info, Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, Up: M68K-Dependent
12602 This syntax for the Motorola 680x0 was developed at MIT.
12604 The 680x0 version of `as' uses instructions names and syntax
12605 compatible with the Sun assembler. Intervening periods are ignored;
12606 for example, `movl' is equivalent to `mov.l'.
12608 In the following table APC stands for any of the address registers
12609 (`%a0' through `%a7'), the program counter (`%pc'), the zero-address
12610 relative to the program counter (`%zpc'), a suppressed address register
12611 (`%za0' through `%za7'), or it may be omitted entirely. The use of
12612 SIZE means one of `w' or `l', and it may be omitted, along with the
12613 leading colon, unless a scale is also specified. The use of SCALE
12614 means one of `1', `2', `4', or `8', and it may always be omitted along
12615 with the leading colon.
12617 The following addressing modes are understood:
12622 `%d0' through `%d7'
12625 `%a0' through `%a7'
12626 `%a7' is also known as `%sp', i.e., the Stack Pointer. `%a6' is
12627 also known as `%fp', the Frame Pointer.
12629 "Address Register Indirect"
12630 `%a0@' through `%a7@'
12632 "Address Register Postincrement"
12633 `%a0@+' through `%a7@+'
12635 "Address Register Predecrement"
12636 `%a0@-' through `%a7@-'
12638 "Indirect Plus Offset"
12642 `APC@(NUMBER,REGISTER:SIZE:SCALE)'
12644 The NUMBER may be omitted.
12647 `APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)'
12649 The ONUMBER or the REGISTER, but not both, may be omitted.
12652 `APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)'
12654 The NUMBER may be omitted. Omitting the REGISTER produces the
12655 Postindex addressing mode.
12658 `SYMBOL', or `DIGITS', optionally followed by `:b', `:w', or `:l'.
12661 File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent
12663 9.23.3 Motorola Syntax
12664 ----------------------
12666 The standard Motorola syntax for this chip differs from the syntax
12667 already discussed (*note Syntax: M68K-Syntax.). `as' can accept
12668 Motorola syntax for operands, even if MIT syntax is used for other
12669 operands in the same instruction. The two kinds of syntax are fully
12672 In the following table APC stands for any of the address registers
12673 (`%a0' through `%a7'), the program counter (`%pc'), the zero-address
12674 relative to the program counter (`%zpc'), or a suppressed address
12675 register (`%za0' through `%za7'). The use of SIZE means one of `w' or
12676 `l', and it may always be omitted along with the leading dot. The use
12677 of SCALE means one of `1', `2', `4', or `8', and it may always be
12678 omitted along with the leading asterisk.
12680 The following additional addressing modes are understood:
12682 "Address Register Indirect"
12683 `(%a0)' through `(%a7)'
12684 `%a7' is also known as `%sp', i.e., the Stack Pointer. `%a6' is
12685 also known as `%fp', the Frame Pointer.
12687 "Address Register Postincrement"
12688 `(%a0)+' through `(%a7)+'
12690 "Address Register Predecrement"
12691 `-(%a0)' through `-(%a7)'
12693 "Indirect Plus Offset"
12694 `NUMBER(%A0)' through `NUMBER(%A7)', or `NUMBER(%PC)'.
12696 The NUMBER may also appear within the parentheses, as in
12697 `(NUMBER,%A0)'. When used with the PC, the NUMBER may be omitted
12698 (with an address register, omitting the NUMBER produces Address
12699 Register Indirect mode).
12702 `NUMBER(APC,REGISTER.SIZE*SCALE)'
12704 The NUMBER may be omitted, or it may appear within the
12705 parentheses. The APC may be omitted. The REGISTER and the APC
12706 may appear in either order. If both APC and REGISTER are address
12707 registers, and the SIZE and SCALE are omitted, then the first
12708 register is taken as the base register, and the second as the
12712 `([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)'
12714 The ONUMBER, or the REGISTER, or both, may be omitted. Either the
12715 NUMBER or the APC may be omitted, but not both.
12718 `([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)'
12720 The NUMBER, or the APC, or the REGISTER, or any two of them, may
12721 be omitted. The ONUMBER may be omitted. The REGISTER and the APC
12722 may appear in either order. If both APC and REGISTER are address
12723 registers, and the SIZE and SCALE are omitted, then the first
12724 register is taken as the base register, and the second as the
12728 File: as.info, Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent
12730 9.23.4 Floating Point
12731 ---------------------
12733 Packed decimal (P) format floating literals are not supported. Feel
12734 free to add the code!
12736 The floating point formats generated by directives are these.
12739 `Single' precision floating point constants.
12742 `Double' precision floating point constants.
12746 `Extended' precision (`long double') floating point constants.
12749 File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent
12751 9.23.5 680x0 Machine Directives
12752 -------------------------------
12754 In order to be compatible with the Sun assembler the 680x0 assembler
12755 understands the following directives.
12758 This directive is identical to a `.data 1' directive.
12761 This directive is identical to a `.data 2' directive.
12764 This directive is a special case of the `.align' directive; it
12765 aligns the output to an even byte boundary.
12768 This directive is identical to a `.space' directive.
12771 Select the target architecture and extension features. Valid
12772 values for NAME are the same as for the `-march' command line
12773 option. This directive cannot be specified after any instructions
12774 have been assembled. If it is given multiple times, or in
12775 conjunction with the `-march' option, all uses must be for the
12776 same architecture and extension set.
12779 Select the target cpu. Valid valuse for NAME are the same as for
12780 the `-mcpu' command line option. This directive cannot be
12781 specified after any instructions have been assembled. If it is
12782 given multiple times, or in conjunction with the `-mopt' option,
12783 all uses must be for the same cpu.
12787 File: as.info, Node: M68K-opcodes, Prev: M68K-Directives, Up: M68K-Dependent
12794 * M68K-Branch:: Branch Improvement
12795 * M68K-Chars:: Special Characters
12798 File: as.info, Node: M68K-Branch, Next: M68K-Chars, Up: M68K-opcodes
12800 9.23.6.1 Branch Improvement
12801 ...........................
12803 Certain pseudo opcodes are permitted for branch instructions. They
12804 expand to the shortest branch instruction that reach the target.
12805 Generally these mnemonics are made by substituting `j' for `b' at the
12806 start of a Motorola mnemonic.
12808 The following table summarizes the pseudo-operations. A `*' flags
12809 cases that are more fully described after the table:
12812 +------------------------------------------------------------
12813 | 68020 68000/10, not PC-relative OK
12814 Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP **
12815 +------------------------------------------------------------
12816 jbsr |bsrs bsrw bsrl jsr
12817 jra |bras braw bral jmp
12818 * jXX |bXXs bXXw bXXl bNXs;jmp
12819 * dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp
12820 fjXX | N/A fbXXw fbXXl N/A
12823 NX: negative of condition XX
12824 `*'--see full description below
12825 `**'--this expansion mode is disallowed by `--pcrel'
12829 These are the simplest jump pseudo-operations; they always map to
12830 one particular machine instruction, depending on the displacement
12831 to the branch target. This instruction will be a byte or word
12832 branch is that is sufficient. Otherwise, a long branch will be
12833 emitted if available. If no long branches are available and the
12834 `--pcrel' option is not given, an absolute long jump will be
12835 emitted instead. If no long branches are available, the `--pcrel'
12836 option is given, and a word branch cannot reach the target, an
12837 error message is generated.
12839 In addition to standard branch operands, `as' allows these
12840 pseudo-operations to have all operands that are allowed for jsr
12841 and jmp, substituting these instructions if the operand given is
12842 not valid for a branch instruction.
12845 Here, `jXX' stands for an entire family of pseudo-operations,
12846 where XX is a conditional branch or condition-code test. The full
12847 list of pseudo-ops in this family is:
12848 jhi jls jcc jcs jne jeq jvc
12849 jvs jpl jmi jge jlt jgt jle
12851 Usually, each of these pseudo-operations expands to a single branch
12852 instruction. However, if a word branch is not sufficient, no long
12853 branches are available, and the `--pcrel' option is not given, `as'
12854 issues a longer code fragment in terms of NX, the opposite
12855 condition to XX. For example, under these conditions:
12863 The full family of pseudo-operations covered here is
12864 dbhi dbls dbcc dbcs dbne dbeq dbvc
12865 dbvs dbpl dbmi dbge dblt dbgt dble
12868 Motorola `dbXX' instructions allow word displacements only. When
12869 a word displacement is sufficient, each of these pseudo-operations
12870 expands to the corresponding Motorola instruction. When a word
12871 displacement is not sufficient and long branches are available,
12872 when the source reads `dbXX foo', `as' emits
12878 If, however, long branches are not available and the `--pcrel'
12879 option is not given, `as' emits
12886 This family includes
12887 fjne fjeq fjge fjlt fjgt fjle fjf
12888 fjt fjgl fjgle fjnge fjngl fjngle fjngt
12889 fjnle fjnlt fjoge fjogl fjogt fjole fjolt
12890 fjor fjseq fjsf fjsne fjst fjueq fjuge
12891 fjugt fjule fjult fjun
12893 Each of these pseudo-operations always expands to a single Motorola
12894 coprocessor branch instruction, word or long. All Motorola
12895 coprocessor branch instructions allow both word and long
12900 File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes
12902 9.23.6.2 Special Characters
12903 ...........................
12905 Line comments are introduced by the `|' character appearing anywhere on
12906 a line, unless the `--bitwise-or' command line option has been
12909 An asterisk (`*') as the first character on a line marks the start
12910 of a line comment as well.
12912 A hash character (`#') as the first character on a line also marks
12913 the start of a line comment, but in this case it could also be a
12914 logical line number directive (*note Comments::) or a preprocessor
12915 control command (*note Preprocessing::). If the hash character appears
12916 elsewhere on a line it is used to introduce an immediate value. (This
12917 is for compatibility with Sun's assembler).
12919 Multiple statements on the same line can appear if they are separated
12920 by the `;' character.
12923 File: as.info, Node: M68HC11-Dependent, Next: Meta-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies
12925 9.24 M68HC11 and M68HC12 Dependent Features
12926 ===========================================
12930 * M68HC11-Opts:: M68HC11 and M68HC12 Options
12931 * M68HC11-Syntax:: Syntax
12932 * M68HC11-Modifiers:: Symbolic Operand Modifiers
12933 * M68HC11-Directives:: Assembler Directives
12934 * M68HC11-Float:: Floating Point
12935 * M68HC11-opcodes:: Opcodes
12938 File: as.info, Node: M68HC11-Opts, Next: M68HC11-Syntax, Up: M68HC11-Dependent
12940 9.24.1 M68HC11 and M68HC12 Options
12941 ----------------------------------
12943 The Motorola 68HC11 and 68HC12 version of `as' have a few machine
12947 This option switches the assembler into the M68HC11 mode. In this
12948 mode, the assembler only accepts 68HC11 operands and mnemonics. It
12949 produces code for the 68HC11.
12952 This option switches the assembler into the M68HC12 mode. In this
12953 mode, the assembler also accepts 68HC12 operands and mnemonics. It
12954 produces code for the 68HC12. A few 68HC11 instructions are
12955 replaced by some 68HC12 instructions as recommended by Motorola
12959 This option switches the assembler into the M68HCS12 mode. This
12960 mode is similar to `-m68hc12' but specifies to assemble for the
12961 68HCS12 series. The only difference is on the assembling of the
12962 `movb' and `movw' instruction when a PC-relative operand is used.
12965 This option switches the assembler into the M9S12X mode. This
12966 mode is similar to `-m68hc12' but specifies to assemble for the
12967 S12X series which is a superset of the HCS12.
12970 This option switches the assembler into the XGATE mode for the RISC
12971 co-processor featured on some S12X-family chips.
12973 `--xgate-ramoffset'
12974 This option instructs the linker to offset RAM addresses from S12X
12975 address space into XGATE address space.
12978 This option controls the ABI and indicates to use a 16-bit integer
12979 ABI. It has no effect on the assembled instructions. This is the
12983 This option controls the ABI and indicates to use a 32-bit integer
12987 This option controls the ABI and indicates to use a 32-bit float
12988 ABI. This is the default.
12991 This option controls the ABI and indicates to use a 64-bit float
12994 `--strict-direct-mode'
12995 You can use the `--strict-direct-mode' option to disable the
12996 automatic translation of direct page mode addressing into extended
12997 mode when the instruction does not support direct mode. For
12998 example, the `clr' instruction does not support direct page mode
12999 addressing. When it is used with the direct page mode, `as' will
13000 ignore it and generate an absolute addressing. This option
13001 prevents `as' from doing this, and the wrong usage of the direct
13002 page mode will raise an error.
13005 The `--short-branches' option turns off the translation of
13006 relative branches into absolute branches when the branch offset is
13007 out of range. By default `as' transforms the relative branch
13008 (`bsr', `bgt', `bge', `beq', `bne', `ble', `blt', `bhi', `bcc',
13009 `bls', `bcs', `bmi', `bvs', `bvs', `bra') into an absolute branch
13010 when the offset is out of the -128 .. 127 range. In that case,
13011 the `bsr' instruction is translated into a `jsr', the `bra'
13012 instruction is translated into a `jmp' and the conditional
13013 branches instructions are inverted and followed by a `jmp'. This
13014 option disables these translations and `as' will generate an error
13015 if a relative branch is out of range. This option does not affect
13016 the optimization associated to the `jbra', `jbsr' and `jbXX'
13019 `--force-long-branches'
13020 The `--force-long-branches' option forces the translation of
13021 relative branches into absolute branches. This option does not
13022 affect the optimization associated to the `jbra', `jbsr' and
13023 `jbXX' pseudo opcodes.
13025 `--print-insn-syntax'
13026 You can use the `--print-insn-syntax' option to obtain the syntax
13027 description of the instruction when an error is detected.
13030 The `--print-opcodes' option prints the list of all the
13031 instructions with their syntax. The first item of each line
13032 represents the instruction name and the rest of the line indicates
13033 the possible operands for that instruction. The list is printed in
13034 alphabetical order. Once the list is printed `as' exits.
13036 `--generate-example'
13037 The `--generate-example' option is similar to `--print-opcodes'
13038 but it generates an example for each instruction instead.
13041 File: as.info, Node: M68HC11-Syntax, Next: M68HC11-Modifiers, Prev: M68HC11-Opts, Up: M68HC11-Dependent
13046 In the M68HC11 syntax, the instruction name comes first and it may be
13047 followed by one or several operands (up to three). Operands are
13048 separated by comma (`,'). In the normal mode, `as' will complain if too
13049 many operands are specified for a given instruction. In the MRI mode
13050 (turned on with `-M' option), it will treat them as comments. Example:
13057 The presence of a `;' character or a `!' character anywhere on a
13058 line indicates the start of a comment that extends to the end of that
13061 A `*' or a `#' character at the start of a line also introduces a
13062 line comment, but these characters do not work elsewhere on the line.
13063 If the first character of the line is a `#' then as well as starting a
13064 comment, the line could also be logical line number directive (*note
13065 Comments::) or a preprocessor control command (*note Preprocessing::).
13067 The M68HC11 assembler does not currently support a line separator
13070 The following addressing modes are understood for 68HC11 and 68HC12:
13075 `NUMBER,X', `NUMBER,Y'
13077 The NUMBER may be omitted in which case 0 is assumed.
13079 "Direct Addressing mode"
13080 `*SYMBOL', or `*DIGITS'
13083 `SYMBOL', or `DIGITS'
13085 The M68HC12 has other more complex addressing modes. All of them are
13086 supported and they are represented below:
13088 "Constant Offset Indexed Addressing Mode"
13091 The NUMBER may be omitted in which case 0 is assumed. The
13092 register can be either `X', `Y', `SP' or `PC'. The assembler will
13093 use the smaller post-byte definition according to the constant
13094 value (5-bit constant offset, 9-bit constant offset or 16-bit
13095 constant offset). If the constant is not known by the assembler
13096 it will use the 16-bit constant offset post-byte and the value
13097 will be resolved at link time.
13099 "Offset Indexed Indirect"
13102 The register can be either `X', `Y', `SP' or `PC'.
13104 "Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement"
13105 `NUMBER,-REG' `NUMBER,+REG' `NUMBER,REG-' `NUMBER,REG+'
13107 The number must be in the range `-8'..`+8' and must not be 0. The
13108 register can be either `X', `Y', `SP' or `PC'.
13110 "Accumulator Offset"
13113 The accumulator register can be either `A', `B' or `D'. The
13114 register can be either `X', `Y', `SP' or `PC'.
13116 "Accumulator D offset indexed-indirect"
13119 The register can be either `X', `Y', `SP' or `PC'.
13132 File: as.info, Node: M68HC11-Modifiers, Next: M68HC11-Directives, Prev: M68HC11-Syntax, Up: M68HC11-Dependent
13134 9.24.3 Symbolic Operand Modifiers
13135 ---------------------------------
13137 The assembler supports several modifiers when using symbol addresses in
13138 68HC11 and 68HC12 instruction operands. The general syntax is the
13144 This modifier indicates to the assembler and linker to use the
13145 16-bit physical address corresponding to the symbol. This is
13146 intended to be used on memory window systems to map a symbol in
13147 the memory bank window. If the symbol is in a memory expansion
13148 part, the physical address corresponds to the symbol address
13149 within the memory bank window. If the symbol is not in a memory
13150 expansion part, this is the symbol address (using or not using the
13151 %addr modifier has no effect in that case).
13154 This modifier indicates to use the memory page number corresponding
13155 to the symbol. If the symbol is in a memory expansion part, its
13156 page number is computed by the linker as a number used to map the
13157 page containing the symbol in the memory bank window. If the
13158 symbol is not in a memory expansion part, the page number is 0.
13161 This modifier indicates to use the 8-bit high part of the physical
13162 address of the symbol.
13165 This modifier indicates to use the 8-bit low part of the physical
13166 address of the symbol.
13169 For example a 68HC12 call to a function `foo_example' stored in
13170 memory expansion part could be written as follows:
13172 call %addr(foo_example),%page(foo_example)
13174 and this is equivalent to
13178 And for 68HC11 it could be written as follows:
13180 ldab #%page(foo_example)
13182 jsr %addr(foo_example)
13185 File: as.info, Node: M68HC11-Directives, Next: M68HC11-Float, Prev: M68HC11-Modifiers, Up: M68HC11-Dependent
13187 9.24.4 Assembler Directives
13188 ---------------------------
13190 The 68HC11 and 68HC12 version of `as' have the following specific
13191 assembler directives:
13194 The relax directive is used by the `GNU Compiler' to emit a
13195 specific relocation to mark a group of instructions for linker
13196 relaxation. The sequence of instructions within the group must be
13197 known to the linker so that relaxation can be performed.
13199 `.mode [mshort|mlong|mshort-double|mlong-double]'
13200 This directive specifies the ABI. It overrides the `-mshort',
13201 `-mlong', `-mshort-double' and `-mlong-double' options.
13204 This directive marks the symbol as a `far' symbol meaning that it
13205 uses a `call/rtc' calling convention as opposed to `jsr/rts'.
13206 During a final link, the linker will identify references to the
13207 `far' symbol and will verify the proper calling convention.
13209 `.interrupt SYMBOL'
13210 This directive marks the symbol as an interrupt entry point. This
13211 information is then used by the debugger to correctly unwind the
13212 frame across interrupts.
13215 This directive is defined for compatibility with the
13216 `Specification for Motorola 8 and 16-Bit Assembly Language Input
13217 Standard' and is ignored.
13221 File: as.info, Node: M68HC11-Float, Next: M68HC11-opcodes, Prev: M68HC11-Directives, Up: M68HC11-Dependent
13223 9.24.5 Floating Point
13224 ---------------------
13226 Packed decimal (P) format floating literals are not supported. Feel
13227 free to add the code!
13229 The floating point formats generated by directives are these.
13232 `Single' precision floating point constants.
13235 `Double' precision floating point constants.
13239 `Extended' precision (`long double') floating point constants.
13242 File: as.info, Node: M68HC11-opcodes, Prev: M68HC11-Float, Up: M68HC11-Dependent
13249 * M68HC11-Branch:: Branch Improvement
13252 File: as.info, Node: M68HC11-Branch, Up: M68HC11-opcodes
13254 9.24.6.1 Branch Improvement
13255 ...........................
13257 Certain pseudo opcodes are permitted for branch instructions. They
13258 expand to the shortest branch instruction that reach the target.
13259 Generally these mnemonics are made by prepending `j' to the start of
13260 Motorola mnemonic. These pseudo opcodes are not affected by the
13261 `--short-branches' or `--force-long-branches' options.
13263 The following table summarizes the pseudo-operations.
13266 +-------------------------------------------------------------+
13268 | --short-branches --force-long-branches |
13269 +--------------------------+----------------------------------+
13270 Op |BYTE WORD | BYTE WORD |
13271 +--------------------------+----------------------------------+
13272 bsr | bsr <pc-rel> <error> | jsr <abs> |
13273 bra | bra <pc-rel> <error> | jmp <abs> |
13274 jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> |
13275 jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> |
13276 bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> |
13277 jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> |
13279 +--------------------------+----------------------------------+
13281 NX: negative of condition XX
13285 These are the simplest jump pseudo-operations; they always map to
13286 one particular machine instruction, depending on the displacement
13287 to the branch target.
13290 Here, `jbXX' stands for an entire family of pseudo-operations,
13291 where XX is a conditional branch or condition-code test. The full
13292 list of pseudo-ops in this family is:
13293 jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo
13294 jbcs jbne jblt jble jbls jbvc jbmi
13296 For the cases of non-PC relative displacements and long
13297 displacements, `as' issues a longer code fragment in terms of NX,
13298 the opposite condition to XX. For example, for the non-PC
13308 File: as.info, Node: Meta-Dependent, Next: MicroBlaze-Dependent, Prev: M68HC11-Dependent, Up: Machine Dependencies
13310 9.25 Meta Dependent Features
13311 ============================
13315 * Meta Options:: Options
13316 * Meta Syntax:: Meta Assembler Syntax
13319 File: as.info, Node: Meta Options, Next: Meta Syntax, Up: Meta-Dependent
13324 The Imagination Technologies Meta architecture is implemented in a
13325 number of versions, with each new version adding new features such as
13326 instructions and registers. For precise details of what instructions
13327 each core supports, please see the chip's technical reference manual.
13329 The following table lists all available Meta options.
13332 Generate code for Meta 1.1.
13335 Generate code for Meta 1.2.
13338 Generate code for Meta 2.1.
13341 Allow code to use FPU hardware of Meta 2.1.
13345 File: as.info, Node: Meta Syntax, Prev: Meta Options, Up: Meta-Dependent
13352 * Meta-Chars:: Special Characters
13353 * Meta-Regs:: Register Names
13356 File: as.info, Node: Meta-Chars, Next: Meta-Regs, Up: Meta Syntax
13358 9.25.2.1 Special Characters
13359 ...........................
13361 `!' is the line comment character.
13363 You can use `;' instead of a newline to separate statements.
13365 Since `$' has no special meaning, you may use it in symbol names.
13368 File: as.info, Node: Meta-Regs, Prev: Meta-Chars, Up: Meta Syntax
13370 9.25.2.2 Register Names
13371 .......................
13373 Registers can be specified either using their mnemonic names, such as
13374 `D0Re0', or using the unit plus register number separated by a `.',
13378 File: as.info, Node: MicroBlaze-Dependent, Next: MIPS-Dependent, Prev: Meta-Dependent, Up: Machine Dependencies
13380 9.26 MicroBlaze Dependent Features
13381 ==================================
13383 The Xilinx MicroBlaze processor family includes several variants,
13384 all using the same core instruction set. This chapter covers features
13385 of the GNU assembler that are specific to the MicroBlaze architecture.
13386 For details about the MicroBlaze instruction set, please see the
13387 `MicroBlaze Processor Reference Guide (UG081)' available at
13392 * MicroBlaze Directives:: Directives for MicroBlaze Processors.
13393 * MicroBlaze Syntax:: Syntax for the MicroBlaze
13396 File: as.info, Node: MicroBlaze Directives, Next: MicroBlaze Syntax, Up: MicroBlaze-Dependent
13401 A number of assembler directives are available for MicroBlaze.
13403 `.data8 EXPRESSION,...'
13404 This directive is an alias for `.byte'. Each expression is
13405 assembled into an eight-bit value.
13407 `.data16 EXPRESSION,...'
13408 This directive is an alias for `.hword'. Each expression is
13409 assembled into an 16-bit value.
13411 `.data32 EXPRESSION,...'
13412 This directive is an alias for `.word'. Each expression is
13413 assembled into an 32-bit value.
13415 `.ent NAME[,LABEL]'
13416 This directive is an alias for `.func' denoting the start of
13417 function NAME at (optional) LABEL.
13419 `.end NAME[,LABEL]'
13420 This directive is an alias for `.endfunc' denoting the end of
13423 `.gpword LABEL,...'
13424 This directive is an alias for `.rva'. The resolved address of
13425 LABEL is stored in the data section.
13428 Declare that LABEL is a weak external symbol.
13431 Switch to .rodata section. Equivalent to `.section .rodata'
13434 Switch to .sdata2 section. Equivalent to `.section .sdata2'
13437 Switch to .sdata section. Equivalent to `.section .sdata'
13440 Switch to .bss section. Equivalent to `.section .bss'
13443 Switch to .sbss section. Equivalent to `.section .sbss'
13446 File: as.info, Node: MicroBlaze Syntax, Prev: MicroBlaze Directives, Up: MicroBlaze-Dependent
13448 9.26.2 Syntax for the MicroBlaze
13449 --------------------------------
13453 * MicroBlaze-Chars:: Special Characters
13456 File: as.info, Node: MicroBlaze-Chars, Up: MicroBlaze Syntax
13458 9.26.2.1 Special Characters
13459 ...........................
13461 The presence of a `#' on a line indicates the start of a comment that
13462 extends to the end of the current line.
13464 If a `#' appears as the first character of a line, the whole line is
13465 treated as a comment, but in this case the line can also be a logical
13466 line number directive (*note Comments::) or a preprocessor control
13467 command (*note Preprocessing::).
13469 The `;' character can be used to separate statements on the same
13473 File: as.info, Node: MIPS-Dependent, Next: MMIX-Dependent, Prev: MicroBlaze-Dependent, Up: Machine Dependencies
13475 9.27 MIPS Dependent Features
13476 ============================
13478 GNU `as' for MIPS architectures supports several different MIPS
13479 processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For
13480 information about the MIPS instruction set, see `MIPS RISC
13481 Architecture', by Kane and Heindrich (Prentice-Hall). For an overview
13482 of MIPS assembly conventions, see "Appendix D: Assembly Language
13483 Programming" in the same work.
13487 * MIPS Options:: Assembler options
13488 * MIPS Macros:: High-level assembly macros
13489 * MIPS Symbol Sizes:: Directives to override the size of symbols
13490 * MIPS Small Data:: Controlling the use of small data accesses
13491 * MIPS ISA:: Directives to override the ISA level
13492 * MIPS assembly options:: Directives to control code generation
13493 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
13494 * MIPS insn:: Directive to mark data as an instruction
13495 * MIPS FP ABIs:: Marking which FP ABI is in use
13496 * MIPS NaN Encodings:: Directives to record which NaN encoding is being used
13497 * MIPS Option Stack:: Directives to save and restore options
13498 * MIPS ASE Instruction Generation Overrides:: Directives to control
13499 generation of MIPS ASE instructions
13500 * MIPS Floating-Point:: Directives to override floating-point options
13501 * MIPS Syntax:: MIPS specific syntactical considerations
13504 File: as.info, Node: MIPS Options, Next: MIPS Macros, Up: MIPS-Dependent
13506 9.27.1 Assembler options
13507 ------------------------
13509 The MIPS configurations of GNU `as' support these special options:
13512 Set the "small data" limit to N bytes. The default limit is 8
13513 bytes. *Note Controlling the use of small data accesses: MIPS
13518 Any MIPS configuration of `as' can select big-endian or
13519 little-endian output at run time (unlike the other GNU development
13520 tools, which must be configured for one or the other). Use `-EB'
13521 to select big-endian output, and `-EL' for little-endian.
13524 Generate SVR4-style PIC. This option tells the assembler to
13525 generate SVR4-style position-independent macro expansions. It
13526 also tells the assembler to mark the output file as PIC.
13529 Generate VxWorks PIC. This option tells the assembler to generate
13530 VxWorks-style position-independent macro expansions.
13547 Generate code for a particular MIPS Instruction Set Architecture
13548 level. `-mips1' corresponds to the R2000 and R3000 processors,
13549 `-mips2' to the R6000 processor, `-mips3' to the R4000 processor,
13550 and `-mips4' to the R8000 and R10000 processors. `-mips5',
13551 `-mips32', `-mips32r2', `-mips32r3', `-mips32r5', `-mips32r6',
13552 `-mips64', `-mips64r2', `-mips64r3', `-mips64r5', and `-mips64r6'
13553 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32
13554 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, and MIPS64
13555 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release
13556 6 ISA processors, respectively. You can also switch instruction
13557 sets during the assembly; see *Note Directives to override the ISA
13562 Some macros have different expansions for 32-bit and 64-bit
13563 registers. The register sizes are normally inferred from the ISA
13564 and ABI, but these flags force a certain group of registers to be
13565 treated as 32 bits wide at all times. `-mgp32' controls the size
13566 of general-purpose registers and `-mfp32' controls the size of
13567 floating-point registers.
13569 The `.set gp=32' and `.set fp=32' directives allow the size of
13570 registers to be changed for parts of an object. The default value
13571 is restored by `.set gp=default' and `.set fp=default'.
13573 On some MIPS variants there is a 32-bit mode flag; when this flag
13574 is set, 64-bit instructions generate a trap. Also, some 32-bit
13575 OSes only save the 32-bit registers on a context switch, so it is
13576 essential never to use the 64-bit registers.
13580 Assume that 64-bit registers are available. This is provided in
13581 the interests of symmetry with `-mgp32' and `-mfp32'.
13583 The `.set gp=64' and `.set fp=64' directives allow the size of
13584 registers to be changed for parts of an object. The default value
13585 is restored by `.set gp=default' and `.set fp=default'.
13588 Make no assumptions about whether 32-bit or 64-bit floating-point
13589 registers are available. This is provided to support having modules
13590 compatible with either `-mfp32' or `-mfp64'. This option can only
13591 be used with MIPS II and above.
13593 The `.set fp=xx' directive allows a part of an object to be marked
13594 as not making assumptions about 32-bit or 64-bit FP registers. The
13595 default value is restored by `.set fp=default'.
13599 Enable use of floating-point operations on odd-numbered
13600 single-precision registers when supported by the ISA. `-mfpxx'
13601 implies `-mno-odd-spreg', otherwise the default is `-modd-spreg'
13605 Generate code for the MIPS 16 processor. This is equivalent to
13606 putting `.set mips16' at the start of the assembly file.
13607 `-no-mips16' turns off this option.
13611 Generate code for the microMIPS processor. This is equivalent to
13612 putting `.set micromips' at the start of the assembly file.
13613 `-mno-micromips' turns off this option. This is equivalent to
13614 putting `.set nomicromips' at the start of the assembly file.
13618 Enables the SmartMIPS extensions to the MIPS32 instruction set,
13619 which provides a number of new instructions which target smartcard
13620 and cryptographic applications. This is equivalent to putting
13621 `.set smartmips' at the start of the assembly file.
13622 `-mno-smartmips' turns off this option.
13626 Generate code for the MIPS-3D Application Specific Extension.
13627 This tells the assembler to accept MIPS-3D instructions.
13628 `-no-mips3d' turns off this option.
13632 Generate code for the MDMX Application Specific Extension. This
13633 tells the assembler to accept MDMX instructions. `-no-mdmx' turns
13638 Generate code for the DSP Release 1 Application Specific Extension.
13639 This tells the assembler to accept DSP Release 1 instructions.
13640 `-mno-dsp' turns off this option.
13644 Generate code for the DSP Release 2 Application Specific Extension.
13645 This option implies -mdsp. This tells the assembler to accept DSP
13646 Release 2 instructions. `-mno-dspr2' turns off this option.
13650 Generate code for the MT Application Specific Extension. This
13651 tells the assembler to accept MT instructions. `-mno-mt' turns
13656 Generate code for the MCU Application Specific Extension. This
13657 tells the assembler to accept MCU instructions. `-mno-mcu' turns
13662 Generate code for the MIPS SIMD Architecture Extension. This
13663 tells the assembler to accept MSA instructions. `-mno-msa' turns
13668 Generate code for the MIPS eXtended Physical Address (XPA)
13669 Extension. This tells the assembler to accept XPA instructions.
13670 `-mno-xpa' turns off this option.
13674 Generate code for the Virtualization Application Specific
13675 Extension. This tells the assembler to accept Virtualization
13676 instructions. `-mno-virt' turns off this option.
13680 Only use 32-bit instruction encodings when generating code for the
13681 microMIPS processor. This option inhibits the use of any 16-bit
13682 instructions. This is equivalent to putting `.set insn32' at the
13683 start of the assembly file. `-mno-insn32' turns off this option.
13684 This is equivalent to putting `.set noinsn32' at the start of the
13685 assembly file. By default `-mno-insn32' is selected, allowing all
13686 instructions to be used.
13690 Cause nops to be inserted if the read of the destination register
13691 of an mfhi or mflo instruction occurs in the following two
13696 Cause nops to be inserted if a dmult or dmultu instruction is
13697 followed by a load instruction.
13699 `-mfix-loongson2f-jump'
13700 `-mno-fix-loongson2f-jump'
13701 Eliminate instruction fetch from outside 256M region to work
13702 around the Loongson2F `jump' instructions. Without it, under
13703 extreme cases, the kernel may crash. The issue has been solved in
13704 latest processor batches, but this fix has no side effect to them.
13706 `-mfix-loongson2f-nop'
13707 `-mno-fix-loongson2f-nop'
13708 Replace nops by `or at,at,zero' to work around the Loongson2F
13709 `nop' errata. Without it, under extreme cases, the CPU might
13710 deadlock. The issue has been solved in later Loongson2F batches,
13711 but this fix has no side effect to them.
13715 Insert nops to work around certain VR4120 errata. This option is
13716 intended to be used on GCC-generated code: it is not designed to
13717 catch all problems in hand-written assembler code.
13721 Insert nops to work around the VR4130 `mflo'/`mfhi' errata.
13725 Insert nops to work around the 24K `eret'/`deret' errata.
13728 `-mno-fix-cn63xxp1'
13729 Replace `pref' hints 0 - 4 and 6 - 24 with hint 28 to work around
13730 certain CN63XXP1 errata.
13734 Generate code for the LSI R4010 chip. This tells the assembler to
13735 accept the R4010-specific instructions (`addciu', `ffc', etc.),
13736 and to not schedule `nop' instructions around accesses to the `HI'
13737 and `LO' registers. `-no-m4010' turns off this option.
13741 Generate code for the MIPS R4650 chip. This tells the assembler
13742 to accept the `mad' and `madu' instruction, and to not schedule
13743 `nop' instructions around accesses to the `HI' and `LO' registers.
13744 `-no-m4650' turns off this option.
13750 For each option `-mNNNN', generate code for the MIPS RNNNN chip.
13751 This tells the assembler to accept instructions specific to that
13752 chip, and to schedule for that chip's hazards.
13755 Generate code for a particular MIPS CPU. It is exactly equivalent
13756 to `-mCPU', except that there are more value of CPU understood.
13757 Valid CPU value are:
13759 2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130,
13760 vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231,
13761 rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000,
13762 10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem,
13763 4kep, 4ksd, m4k, m4kp, m14k, m14kc, m14ke, m14kec, 24kc,
13764 24kf2_1, 24kf, 24kf1_1, 24kec, 24kef2_1, 24kef, 24kef1_1,
13765 34kc, 34kf2_1, 34kf, 34kf1_1, 34kn, 74kc, 74kf2_1, 74kf,
13766 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf, 1004kf1_1, p5600,
13767 5kc, 5kf, 20kc, 25kf, sb1, sb1a, loongson2e, loongson2f,
13768 loongson3a, octeon, octeon+, octeon2, xlr, xlp
13770 For compatibility reasons, `Nx' and `Bfx' are accepted as synonyms
13771 for `Nf1_1'. These values are deprecated.
13774 Schedule and tune for a particular MIPS CPU. Valid CPU values are
13775 identical to `-march=CPU'.
13778 Record which ABI the source code uses. The recognized arguments
13779 are: `32', `n32', `o64', `64' and `eabi'.
13783 Equivalent to adding `.set sym32' or `.set nosym32' to the
13784 beginning of the assembler input. *Note MIPS Symbol Sizes::.
13787 This option is ignored. It is accepted for command-line
13788 compatibility with other assemblers, which use it to turn off C
13789 style preprocessing. With GNU `as', there is no need for
13790 `-nocpp', because the GNU assembler itself never runs the C
13795 Disable or enable floating-point instructions. Note that by
13796 default floating-point instructions are always allowed even with
13797 CPU targets that don't have support for these instructions.
13801 Disable or enable double-precision floating-point operations. Note
13802 that by default double-precision floating-point operations are
13803 always allowed even with CPU targets that don't have support for
13806 `--construct-floats'
13807 `--no-construct-floats'
13808 The `--no-construct-floats' option disables the construction of
13809 double width floating point constants by loading the two halves of
13810 the value into the two single width floating point registers that
13811 make up the double width register. This feature is useful if the
13812 processor support the FR bit in its status register, and this bit
13813 is known (by the programmer) to be set. This bit prevents the
13814 aliasing of the double width register by the single width
13817 By default `--construct-floats' is selected, allowing construction
13818 of these floating point constants.
13821 `--no-relax-branch'
13822 The `--relax-branch' option enables the relaxation of out-of-range
13823 branches. Any branches whose target cannot be reached directly are
13824 converted to a small instruction sequence including an
13825 inverse-condition branch to the physically next instruction, and a
13826 jump to the original target is inserted between the two
13827 instructions. In PIC code the jump will involve further
13828 instructions for address calculation.
13830 The `BC1ANY2F', `BC1ANY2T', `BC1ANY4F', `BC1ANY4T', `BPOSGE32' and
13831 `BPOSGE64' instructions are excluded from relaxation, because they
13832 have no complementing counterparts. They could be relaxed with
13833 the use of a longer sequence involving another branch, however
13834 this has not been implemented and if their target turns out of
13835 reach, they produce an error even if branch relaxation is enabled.
13837 Also no MIPS16 branches are ever relaxed.
13839 By default `--no-relax-branch' is selected, causing any
13840 out-of-range branches to produce an error.
13843 This option indicates whether the source code uses the IEEE 2008
13844 NaN encoding (`-mnan=2008') or the original MIPS encoding
13845 (`-mnan=legacy'). It is equivalent to adding a `.nan' directive
13846 to the beginning of the source file. *Note MIPS NaN Encodings::.
13848 `-mnan=legacy' is the default if no `-mnan' option or `.nan'
13853 `as' automatically macro expands certain division and
13854 multiplication instructions to check for overflow and division by
13855 zero. This option causes `as' to generate code to take a trap
13856 exception rather than a break exception when an error is detected.
13857 The trap instructions are only supported at Instruction Set
13858 Architecture level 2 and higher.
13862 Generate code to take a break exception rather than a trap
13863 exception when an error is detected. This is the default.
13867 Control generation of `.pdr' sections. Off by default on IRIX, on
13872 When generating code using the Unix calling conventions (selected
13873 by `-KPIC' or `-mcall_shared'), gas will normally generate code
13874 which can go into a shared library. The `-mno-shared' option
13875 tells gas to generate code which uses the calling convention, but
13876 can not go into a shared library. The resulting code is slightly
13877 more efficient. This option only affects the handling of the
13878 `.cpload' and `.cpsetup' pseudo-ops.
13881 File: as.info, Node: MIPS Macros, Next: MIPS Symbol Sizes, Prev: MIPS Options, Up: MIPS-Dependent
13883 9.27.2 High-level assembly macros
13884 ---------------------------------
13886 MIPS assemblers have traditionally provided a wider range of
13887 instructions than the MIPS architecture itself. These extra
13888 instructions are usually referred to as "macro" instructions (1).
13890 Some MIPS macro instructions extend an underlying architectural
13891 instruction while others are entirely new. An example of the former
13892 type is `and', which allows the third operand to be either a register
13893 or an arbitrary immediate value. Examples of the latter type include
13894 `bgt', which branches to the third operand when the first operand is
13895 greater than the second operand, and `ulh', which implements an
13896 unaligned 2-byte load.
13898 One of the most common extensions provided by macros is to expand
13899 memory offsets to the full address range (32 or 64 bits) and to allow
13900 symbolic offsets such as `my_data + 4' to be used in place of integer
13901 constants. For example, the architectural instruction `lbu' allows
13902 only a signed 16-bit offset, whereas the macro `lbu' allows code such
13903 as `lbu $4,array+32769($5)'. The implementation of these symbolic
13904 offsets depends on several factors, such as whether the assembler is
13905 generating SVR4-style PIC (selected by `-KPIC', *note Assembler
13906 options: MIPS Options.), the size of symbols (*note Directives to
13907 override the size of symbols: MIPS Symbol Sizes.), and the small data
13908 limit (*note Controlling the use of small data accesses: MIPS Small
13911 Sometimes it is undesirable to have one assembly instruction expand
13912 to several machine instructions. The directive `.set nomacro' tells
13913 the assembler to warn when this happens. `.set macro' restores the
13916 Some macro instructions need a temporary register to store
13917 intermediate results. This register is usually `$1', also known as
13918 `$at', but it can be changed to any core register REG using `.set
13919 at=REG'. Note that `$at' always refers to `$1' regardless of which
13920 register is being used as the temporary register.
13922 Implicit uses of the temporary register in macros could interfere
13923 with explicit uses in the assembly code. The assembler therefore warns
13924 whenever it sees an explicit use of the temporary register. The
13925 directive `.set noat' silences this warning while `.set at' restores
13926 the default behavior. It is safe to use `.set noat' while `.set
13927 nomacro' is in effect since single-instruction macros never need a
13928 temporary register.
13930 Note that while the GNU assembler provides these macros for
13931 compatibility, it does not make any attempt to optimize them with the
13934 ---------- Footnotes ----------
13936 (1) The term "macro" is somewhat overloaded here, since these macros
13937 have no relation to those defined by `.macro', *note `.macro': Macro.
13940 File: as.info, Node: MIPS Symbol Sizes, Next: MIPS Small Data, Prev: MIPS Macros, Up: MIPS-Dependent
13942 9.27.3 Directives to override the size of symbols
13943 -------------------------------------------------
13945 The n64 ABI allows symbols to have any 64-bit value. Although this
13946 provides a great deal of flexibility, it means that some macros have
13947 much longer expansions than their 32-bit counterparts. For example,
13948 the non-PIC expansion of `dla $4,sym' is usually:
13950 lui $4,%highest(sym)
13952 daddiu $4,$4,%higher(sym)
13953 daddiu $1,$1,%lo(sym)
13957 whereas the 32-bit expansion is simply:
13960 daddiu $4,$4,%lo(sym)
13962 n64 code is sometimes constructed in such a way that all symbolic
13963 constants are known to have 32-bit values, and in such cases, it's
13964 preferable to use the 32-bit expansion instead of the 64-bit expansion.
13966 You can use the `.set sym32' directive to tell the assembler that,
13967 from this point on, all expressions of the form `SYMBOL' or `SYMBOL +
13968 OFFSET' have 32-bit values. For example:
13973 sw $4,sym+0x8000($4)
13975 will cause the assembler to treat `sym', `sym+16' and `sym+0x8000'
13976 as 32-bit values. The handling of non-symbolic addresses is not
13979 The directive `.set nosym32' ends a `.set sym32' block and reverts
13980 to the normal behavior. It is also possible to change the symbol size
13981 using the command-line options `-msym32' and `-mno-sym32'.
13983 These options and directives are always accepted, but at present,
13984 they have no effect for anything other than n64.
13987 File: as.info, Node: MIPS Small Data, Next: MIPS ISA, Prev: MIPS Symbol Sizes, Up: MIPS-Dependent
13989 9.27.4 Controlling the use of small data accesses
13990 -------------------------------------------------
13992 It often takes several instructions to load the address of a symbol.
13993 For example, when `addr' is a 32-bit symbol, the non-PIC expansion of
13994 `dla $4,addr' is usually:
13997 daddiu $4,$4,%lo(addr)
13999 The sequence is much longer when `addr' is a 64-bit symbol. *Note
14000 Directives to override the size of symbols: MIPS Symbol Sizes.
14002 In order to cut down on this overhead, most embedded MIPS systems
14003 set aside a 64-kilobyte "small data" area and guarantee that all data
14004 of size N and smaller will be placed in that area. The limit N is
14005 passed to both the assembler and the linker using the command-line
14006 option `-G N', *note Assembler options: MIPS Options. Note that the
14007 same value of N must be used when linking and when assembling all input
14008 files to the link; any inconsistency could cause a relocation overflow
14011 The size of an object in the `.bss' section is set by the `.comm' or
14012 `.lcomm' directive that defines it. The size of an external object may
14013 be set with the `.extern' directive. For example, `.extern sym,4'
14014 declares that the object at `sym' is 4 bytes in length, while leaving
14015 `sym' otherwise undefined.
14017 When no `-G' option is given, the default limit is 8 bytes. The
14018 option `-G 0' prevents any data from being automatically classified as
14021 It is also possible to mark specific objects as small by putting them
14022 in the special sections `.sdata' and `.sbss', which are "small"
14023 counterparts of `.data' and `.bss' respectively. The toolchain will
14024 treat such data as small regardless of the `-G' setting.
14026 On startup, systems that support a small data area are expected to
14027 initialize register `$28', also known as `$gp', in such a way that
14028 small data can be accessed using a 16-bit offset from that register.
14029 For example, when `addr' is small data, the `dla $4,addr' instruction
14030 above is equivalent to:
14032 daddiu $4,$28,%gp_rel(addr)
14034 Small data is not supported for SVR4-style PIC.
14037 File: as.info, Node: MIPS ISA, Next: MIPS assembly options, Prev: MIPS Small Data, Up: MIPS-Dependent
14039 9.27.5 Directives to override the ISA level
14040 -------------------------------------------
14042 GNU `as' supports an additional directive to change the MIPS
14043 Instruction Set Architecture level on the fly: `.set mipsN'. N should
14044 be a number from 0 to 5, or 32, 32r2, 32r3, 32r5, 32r6, 64, 64r2, 64r3,
14045 64r5 or 64r6. The values other than 0 make the assembler accept
14046 instructions for the corresponding ISA level, from that point on in the
14047 assembly. `.set mipsN' affects not only which instructions are
14048 permitted, but also how certain macros are expanded. `.set mips0'
14049 restores the ISA level to its original level: either the level you
14050 selected with command line options, or the default for your
14051 configuration. You can use this feature to permit specific MIPS III
14052 instructions while assembling in 32 bit mode. Use this directive with
14055 The `.set arch=CPU' directive provides even finer control. It
14056 changes the effective CPU target and allows the assembler to use
14057 instructions specific to a particular CPU. All CPUs supported by the
14058 `-march' command line option are also selectable by this directive.
14059 The original value is restored by `.set arch=default'.
14061 The directive `.set mips16' puts the assembler into MIPS 16 mode, in
14062 which it will assemble instructions for the MIPS 16 processor. Use
14063 `.set nomips16' to return to normal 32 bit mode.
14065 Traditional MIPS assemblers do not support this directive.
14067 The directive `.set micromips' puts the assembler into microMIPS
14068 mode, in which it will assemble instructions for the microMIPS
14069 processor. Use `.set nomicromips' to return to normal 32 bit mode.
14071 Traditional MIPS assemblers do not support this directive.
14074 File: as.info, Node: MIPS assembly options, Next: MIPS autoextend, Prev: MIPS ISA, Up: MIPS-Dependent
14076 9.27.6 Directives to control code generation
14077 --------------------------------------------
14079 The `.module' directive allows command line options to be set directly
14080 from assembly. The format of the directive matches the `.set'
14081 directive but only those options which are relevant to a whole module
14082 are supported. The effect of a `.module' directive is the same as the
14083 corresponding command line option. Where `.set' directives support
14084 returning to a default then the `.module' directives do not as they
14085 define the defaults.
14087 These module-level directives must appear first in assembly.
14089 Traditional MIPS assemblers do not support this directive.
14091 The directive `.set insn32' makes the assembler only use 32-bit
14092 instruction encodings when generating code for the microMIPS processor.
14093 This directive inhibits the use of any 16-bit instructions from that
14094 point on in the assembly. The `.set noinsn32' directive allows 16-bit
14095 instructions to be accepted.
14097 Traditional MIPS assemblers do not support this directive.
14100 File: as.info, Node: MIPS autoextend, Next: MIPS insn, Prev: MIPS assembly options, Up: MIPS-Dependent
14102 9.27.7 Directives for extending MIPS 16 bit instructions
14103 --------------------------------------------------------
14105 By default, MIPS 16 instructions are automatically extended to 32 bits
14106 when necessary. The directive `.set noautoextend' will turn this off.
14107 When `.set noautoextend' is in effect, any 32 bit instruction must be
14108 explicitly extended with the `.e' modifier (e.g., `li.e $4,1000'). The
14109 directive `.set autoextend' may be used to once again automatically
14110 extend instructions when necessary.
14112 This directive is only meaningful when in MIPS 16 mode. Traditional
14113 MIPS assemblers do not support this directive.
14116 File: as.info, Node: MIPS insn, Next: MIPS FP ABIs, Prev: MIPS autoextend, Up: MIPS-Dependent
14118 9.27.8 Directive to mark data as an instruction
14119 -----------------------------------------------
14121 The `.insn' directive tells `as' that the following data is actually
14122 instructions. This makes a difference in MIPS 16 and microMIPS modes:
14123 when loading the address of a label which precedes instructions, `as'
14124 automatically adds 1 to the value, so that jumping to the loaded
14125 address will do the right thing.
14127 The `.global' and `.globl' directives supported by `as' will by
14128 default mark the symbol as pointing to a region of data not code. This
14129 means that, for example, any instructions following such a symbol will
14130 not be disassembled by `objdump' as it will regard them as data. To
14131 change this behavior an optional section name can be placed after the
14132 symbol name in the `.global' directive. If this section exists and is
14133 known to be a code section, then the symbol will be marked as pointing
14134 at code not data. Ie the syntax for the directive is:
14136 `.global SYMBOL[ SECTION][, SYMBOL[ SECTION]] ...',
14138 Here is a short example:
14140 .global foo .text, bar, baz .data
14149 File: as.info, Node: MIPS FP ABIs, Next: MIPS NaN Encodings, Prev: MIPS insn, Up: MIPS-Dependent
14151 9.27.9 Directives to control the FP ABI
14152 ---------------------------------------
14156 * MIPS FP ABI History:: History of FP ABIs
14157 * MIPS FP ABI Variants:: Supported FP ABIs
14158 * MIPS FP ABI Selection:: Automatic selection of FP ABI
14159 * MIPS FP ABI Compatibility:: Linking different FP ABI variants
14162 File: as.info, Node: MIPS FP ABI History, Next: MIPS FP ABI Variants, Up: MIPS FP ABIs
14164 9.27.9.1 History of FP ABIs
14165 ...........................
14167 The MIPS ABIs support a variety of different floating-point extensions
14168 where calling-convention and register sizes vary for floating-point
14169 data. The extensions exist to support a wide variety of optional
14170 architecture features. The resulting ABI variants are generally
14171 incompatible with each other and must be tracked carefully.
14173 Traditionally the use of an explicit `.gnu_attribute 4, N' directive
14174 is used to indicate which ABI is in use by a specific module. It was
14175 then left to the user to ensure that command line options and the
14176 selected ABI were compatible with some potential for inconsistencies.
14179 File: as.info, Node: MIPS FP ABI Variants, Next: MIPS FP ABI Selection, Prev: MIPS FP ABI History, Up: MIPS FP ABIs
14181 9.27.9.2 Supported FP ABIs
14182 ..........................
14184 The supported floating-point ABI variants are:
14186 `0 - No floating-point'
14187 This variant is used to indicate that floating-point is not used
14188 within the module at all and therefore has no impact on the ABI.
14189 This is the default.
14191 `1 - Double-precision'
14192 This variant indicates that double-precision support is used. For
14193 64-bit ABIs this means that 64-bit wide floating-point registers
14194 are required. For 32-bit ABIs this means that 32-bit wide
14195 floating-point registers are required and double-precision
14196 operations use pairs of registers.
14198 `2 - Single-precision'
14199 This variant indicates that single-precision support is used.
14200 Double precision operations will be supported via soft-float
14204 This variant indicates that although floating-point support is
14205 used all operations are emulated in software. This means the ABI
14206 is modified to pass all floating-point data in general-purpose
14210 This variant existed as an initial attempt at supporting 64-bit
14211 wide floating-point registers for O32 ABI on a MIPS32r2 CPU. This
14212 has been superseded by 5, 6 and 7.
14214 `5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU'
14215 This variant is used by 32-bit ABIs to indicate that the
14216 floating-point code in the module has been designed to operate
14217 correctly with either 32-bit wide or 64-bit wide floating-point
14218 registers. Double-precision support is used. Only O32 currently
14219 supports this variant and requires a minimum architecture of MIPS
14222 `6 - Double-precision 32-bit FPU, 64-bit FPU'
14223 This variant is used by 32-bit ABIs to indicate that the
14224 floating-point code in the module requires 64-bit wide
14225 floating-point registers. Double-precision support is used. Only
14226 O32 currently supports this variant and requires a minimum
14227 architecture of MIPS32r2.
14229 `7 - Double-precision compat 32-bit FPU, 64-bit FPU'
14230 This variant is used by 32-bit ABIs to indicate that the
14231 floating-point code in the module requires 64-bit wide
14232 floating-point registers. Double-precision support is used. This
14233 differs from the previous ABI as it restricts use of odd-numbered
14234 single-precision registers. Only O32 currently supports this
14235 variant and requires a minimum architecture of MIPS32r2.
14238 File: as.info, Node: MIPS FP ABI Selection, Next: MIPS FP ABI Compatibility, Prev: MIPS FP ABI Variants, Up: MIPS FP ABIs
14240 9.27.9.3 Automatic selection of FP ABI
14241 ......................................
14243 In order to simplify and add safety to the process of selecting the
14244 correct floating-point ABI, the assembler will automatically infer the
14245 correct `.gnu_attribute 4, N' directive based on command line options
14246 and `.module' overrides. Where an explicit `.gnu_attribute 4, N'
14247 directive has been seen then a warning will be raised if it does not
14248 match an inferred setting.
14250 The floating-point ABI is inferred as follows. If `-msoft-float'
14251 has been used the module will be marked as soft-float. If
14252 `-msingle-float' has been used then the module will be marked as
14253 single-precision. The remaining ABIs are then selected based on the FP
14254 register width. Double-precision is selected if the width of GP and FP
14255 registers match and the special double-precision variants for 32-bit
14256 ABIs are then selected depending on `-mfpxx', `-mfp64' and
14260 File: as.info, Node: MIPS FP ABI Compatibility, Prev: MIPS FP ABI Selection, Up: MIPS FP ABIs
14262 9.27.9.4 Linking different FP ABI variants
14263 ..........................................
14265 Modules using the default FP ABI (no floating-point) can be linked with
14266 any other (singular) FP ABI variant.
14268 Special compatibility support exists for O32 with the four
14269 double-precision FP ABI variants. The `-mfpxx' FP ABI is specifically
14270 designed to be compatible with the standard double-precision ABI and the
14271 `-mfp64' FP ABIs. This makes it desirable for O32 modules to be built
14272 as `-mfpxx' to ensure the maximum compatibility with other modules
14273 produced for more specific needs. The only FP ABIs which cannot be
14274 linked together are the standard double-precision ABI and the full
14275 `-mfp64' ABI with `-modd-spreg'.
14278 File: as.info, Node: MIPS NaN Encodings, Next: MIPS Option Stack, Prev: MIPS FP ABIs, Up: MIPS-Dependent
14280 9.27.10 Directives to record which NaN encoding is being used
14281 -------------------------------------------------------------
14283 The IEEE 754 floating-point standard defines two types of not-a-number
14284 (NaN) data: "signalling" NaNs and "quiet" NaNs. The original version
14285 of the standard did not specify how these two types should be
14286 distinguished. Most implementations followed the i387 model, in which
14287 the first bit of the significand is set for quiet NaNs and clear for
14288 signalling NaNs. However, the original MIPS implementation assigned the
14289 opposite meaning to the bit, so that it was set for signalling NaNs and
14290 clear for quiet NaNs.
14292 The 2008 revision of the standard formally suggested the i387 choice
14293 and as from Sep 2012 the current release of the MIPS architecture
14294 therefore optionally supports that form. Code that uses one NaN
14295 encoding would usually be incompatible with code that uses the other
14296 NaN encoding, so MIPS ELF objects have a flag (`EF_MIPS_NAN2008') to
14297 record which encoding is being used.
14299 Assembly files can use the `.nan' directive to select between the
14300 two encodings. `.nan 2008' says that the assembly file uses the IEEE
14301 754-2008 encoding while `.nan legacy' says that the file uses the
14302 original MIPS encoding. If several `.nan' directives are given, the
14303 final setting is the one that is used.
14305 The command-line options `-mnan=legacy' and `-mnan=2008' can be used
14306 instead of `.nan legacy' and `.nan 2008' respectively. However, any
14307 `.nan' directive overrides the command-line setting.
14309 `.nan legacy' is the default if no `.nan' directive or `-mnan'
14312 Note that GNU `as' does not produce NaNs itself and therefore these
14313 directives do not affect code generation. They simply control the
14314 setting of the `EF_MIPS_NAN2008' flag.
14316 Traditional MIPS assemblers do not support these directives.
14319 File: as.info, Node: MIPS Option Stack, Next: MIPS ASE Instruction Generation Overrides, Prev: MIPS NaN Encodings, Up: MIPS-Dependent
14321 9.27.11 Directives to save and restore options
14322 ----------------------------------------------
14324 The directives `.set push' and `.set pop' may be used to save and
14325 restore the current settings for all the options which are controlled
14326 by `.set'. The `.set push' directive saves the current settings on a
14327 stack. The `.set pop' directive pops the stack and restores the
14330 These directives can be useful inside an macro which must change an
14331 option such as the ISA level or instruction reordering but does not want
14332 to change the state of the code which invoked the macro.
14334 Traditional MIPS assemblers do not support these directives.
14337 File: as.info, Node: MIPS ASE Instruction Generation Overrides, Next: MIPS Floating-Point, Prev: MIPS Option Stack, Up: MIPS-Dependent
14339 9.27.12 Directives to control generation of MIPS ASE instructions
14340 -----------------------------------------------------------------
14342 The directive `.set mips3d' makes the assembler accept instructions
14343 from the MIPS-3D Application Specific Extension from that point on in
14344 the assembly. The `.set nomips3d' directive prevents MIPS-3D
14345 instructions from being accepted.
14347 The directive `.set smartmips' makes the assembler accept
14348 instructions from the SmartMIPS Application Specific Extension to the
14349 MIPS32 ISA from that point on in the assembly. The `.set nosmartmips'
14350 directive prevents SmartMIPS instructions from being accepted.
14352 The directive `.set mdmx' makes the assembler accept instructions
14353 from the MDMX Application Specific Extension from that point on in the
14354 assembly. The `.set nomdmx' directive prevents MDMX instructions from
14357 The directive `.set dsp' makes the assembler accept instructions
14358 from the DSP Release 1 Application Specific Extension from that point
14359 on in the assembly. The `.set nodsp' directive prevents DSP Release 1
14360 instructions from being accepted.
14362 The directive `.set dspr2' makes the assembler accept instructions
14363 from the DSP Release 2 Application Specific Extension from that point
14364 on in the assembly. This directive implies `.set dsp'. The `.set
14365 nodspr2' directive prevents DSP Release 2 instructions from being
14368 The directive `.set mt' makes the assembler accept instructions from
14369 the MT Application Specific Extension from that point on in the
14370 assembly. The `.set nomt' directive prevents MT instructions from
14373 The directive `.set mcu' makes the assembler accept instructions
14374 from the MCU Application Specific Extension from that point on in the
14375 assembly. The `.set nomcu' directive prevents MCU instructions from
14378 The directive `.set msa' makes the assembler accept instructions
14379 from the MIPS SIMD Architecture Extension from that point on in the
14380 assembly. The `.set nomsa' directive prevents MSA instructions from
14383 The directive `.set virt' makes the assembler accept instructions
14384 from the Virtualization Application Specific Extension from that point
14385 on in the assembly. The `.set novirt' directive prevents Virtualization
14386 instructions from being accepted.
14388 The directive `.set xpa' makes the assembler accept instructions
14389 from the XPA Extension from that point on in the assembly. The `.set
14390 noxpa' directive prevents XPA instructions from being accepted.
14392 Traditional MIPS assemblers do not support these directives.
14395 File: as.info, Node: MIPS Floating-Point, Next: MIPS Syntax, Prev: MIPS ASE Instruction Generation Overrides, Up: MIPS-Dependent
14397 9.27.13 Directives to override floating-point options
14398 -----------------------------------------------------
14400 The directives `.set softfloat' and `.set hardfloat' provide finer
14401 control of disabling and enabling float-point instructions. These
14402 directives always override the default (that hard-float instructions
14403 are accepted) or the command-line options (`-msoft-float' and
14406 The directives `.set singlefloat' and `.set doublefloat' provide
14407 finer control of disabling and enabling double-precision float-point
14408 operations. These directives always override the default (that
14409 double-precision operations are accepted) or the command-line options
14410 (`-msingle-float' and `-mdouble-float').
14412 Traditional MIPS assemblers do not support these directives.
14415 File: as.info, Node: MIPS Syntax, Prev: MIPS Floating-Point, Up: MIPS-Dependent
14417 9.27.14 Syntactical considerations for the MIPS assembler
14418 ---------------------------------------------------------
14422 * MIPS-Chars:: Special Characters
14425 File: as.info, Node: MIPS-Chars, Up: MIPS Syntax
14427 9.27.14.1 Special Characters
14428 ............................
14430 The presence of a `#' on a line indicates the start of a comment that
14431 extends to the end of the current line.
14433 If a `#' appears as the first character of a line, the whole line is
14434 treated as a comment, but in this case the line can also be a logical
14435 line number directive (*note Comments::) or a preprocessor control
14436 command (*note Preprocessing::).
14438 The `;' character can be used to separate statements on the same
14442 File: as.info, Node: MMIX-Dependent, Next: MSP430-Dependent, Prev: MIPS-Dependent, Up: Machine Dependencies
14444 9.28 MMIX Dependent Features
14445 ============================
14449 * MMIX-Opts:: Command-line Options
14450 * MMIX-Expand:: Instruction expansion
14451 * MMIX-Syntax:: Syntax
14452 * MMIX-mmixal:: Differences to `mmixal' syntax and semantics
14455 File: as.info, Node: MMIX-Opts, Next: MMIX-Expand, Up: MMIX-Dependent
14457 9.28.1 Command-line Options
14458 ---------------------------
14460 The MMIX version of `as' has some machine-dependent options.
14462 When `--fixed-special-register-names' is specified, only the register
14463 names specified in *Note MMIX-Regs:: are recognized in the instructions
14466 You can use the `--globalize-symbols' to make all symbols global.
14467 This option is useful when splitting up a `mmixal' program into several
14470 The `--gnu-syntax' turns off most syntax compatibility with
14471 `mmixal'. Its usability is currently doubtful.
14473 The `--relax' option is not fully supported, but will eventually make
14474 the object file prepared for linker relaxation.
14476 If you want to avoid inadvertently calling a predefined symbol and
14477 would rather get an error, for example when using `as' with a compiler
14478 or other machine-generated code, specify `--no-predefined-syms'. This
14479 turns off built-in predefined definitions of all such symbols,
14480 including rounding-mode symbols, segment symbols, `BIT' symbols, and
14481 `TRAP' symbols used in `mmix' "system calls". It also turns off
14482 predefined special-register names, except when used in `PUT' and `GET'
14485 By default, some instructions are expanded to fit the size of the
14486 operand or an external symbol (*note MMIX-Expand::). By passing
14487 `--no-expand', no such expansion will be done, instead causing errors
14488 at link time if the operand does not fit.
14490 The `mmixal' documentation (*note mmixsite::) specifies that global
14491 registers allocated with the `GREG' directive (*note MMIX-greg::) and
14492 initialized to the same non-zero value, will refer to the same global
14493 register. This isn't strictly enforceable in `as' since the final
14494 addresses aren't known until link-time, but it will do an effort unless
14495 the `--no-merge-gregs' option is specified. (Register merging isn't
14496 yet implemented in `ld'.)
14498 `as' will warn every time it expands an instruction to fit an
14499 operand unless the option `-x' is specified. It is believed that this
14500 behaviour is more useful than just mimicking `mmixal''s behaviour, in
14501 which instructions are only expanded if the `-x' option is specified,
14502 and assembly fails otherwise, when an instruction needs to be expanded.
14503 It needs to be kept in mind that `mmixal' is both an assembler and
14504 linker, while `as' will expand instructions that at link stage can be
14505 contracted. (Though linker relaxation isn't yet implemented in `ld'.)
14506 The option `-x' also imples `--linker-allocated-gregs'.
14508 If instruction expansion is enabled, `as' can expand a `PUSHJ'
14509 instruction into a series of instructions. The shortest expansion is
14510 to not expand it, but just mark the call as redirectable to a stub,
14511 which `ld' creates at link-time, but only if the original `PUSHJ'
14512 instruction is found not to reach the target. The stub consists of the
14513 necessary instructions to form a jump to the target. This happens if
14514 `as' can assert that the `PUSHJ' instruction can reach such a stub.
14515 The option `--no-pushj-stubs' disables this shorter expansion, and the
14516 longer series of instructions is then created at assembly-time. The
14517 option `--no-stubs' is a synonym, intended for compatibility with
14518 future releases, where generation of stubs for other instructions may
14521 Usually a two-operand-expression (*note GREG-base::) without a
14522 matching `GREG' directive is treated as an error by `as'. When the
14523 option `--linker-allocated-gregs' is in effect, they are instead passed
14524 through to the linker, which will allocate as many global registers as
14528 File: as.info, Node: MMIX-Expand, Next: MMIX-Syntax, Prev: MMIX-Opts, Up: MMIX-Dependent
14530 9.28.2 Instruction expansion
14531 ----------------------------
14533 When `as' encounters an instruction with an operand that is either not
14534 known or does not fit the operand size of the instruction, `as' (and
14535 `ld') will expand the instruction into a sequence of instructions
14536 semantically equivalent to the operand fitting the instruction.
14537 Expansion will take place for the following instructions:
14540 Expands to a sequence of four instructions: `SETL', `INCML',
14541 `INCMH' and `INCH'. The operand must be a multiple of four.
14543 Conditional branches
14544 A branch instruction is turned into a branch with the complemented
14545 condition and prediction bit over five instructions; four
14546 instructions setting `$255' to the operand value, which like with
14547 `GETA' must be a multiple of four, and a final `GO $255,$255,0'.
14550 Similar to expansion for conditional branches; four instructions
14551 set `$255' to the operand value, followed by a `PUSHGO
14555 Similar to conditional branches and `PUSHJ'. The final instruction
14556 is `GO $255,$255,0'.
14558 The linker `ld' is expected to shrink these expansions for code
14559 assembled with `--relax' (though not currently implemented).
14562 File: as.info, Node: MMIX-Syntax, Next: MMIX-mmixal, Prev: MMIX-Expand, Up: MMIX-Dependent
14567 The assembly syntax is supposed to be upward compatible with that
14568 described in Sections 1.3 and 1.4 of `The Art of Computer Programming,
14569 Volume 1'. Draft versions of those chapters as well as other MMIX
14570 information is located at
14571 `http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html'. Most code
14572 examples from the mmixal package located there should work unmodified
14573 when assembled and linked as single files, with a few noteworthy
14574 exceptions (*note MMIX-mmixal::).
14576 Before an instruction is emitted, the current location is aligned to
14577 the next four-byte boundary. If a label is defined at the beginning of
14578 the line, its value will be the aligned value.
14580 In addition to the traditional hex-prefix `0x', a hexadecimal number
14581 can also be specified by the prefix character `#'.
14583 After all operands to an MMIX instruction or directive have been
14584 specified, the rest of the line is ignored, treated as a comment.
14588 * MMIX-Chars:: Special Characters
14589 * MMIX-Symbols:: Symbols
14590 * MMIX-Regs:: Register Names
14591 * MMIX-Pseudos:: Assembler Directives
14594 File: as.info, Node: MMIX-Chars, Next: MMIX-Symbols, Up: MMIX-Syntax
14596 9.28.3.1 Special Characters
14597 ...........................
14599 The characters `*' and `#' are line comment characters; each start a
14600 comment at the beginning of a line, but only at the beginning of a
14601 line. A `#' prefixes a hexadecimal number if found elsewhere on a
14602 line. If a `#' appears at the start of a line the whole line is
14603 treated as a comment, but the line can also act as a logical line
14604 number directive (*note Comments::) or a preprocessor control command
14605 (*note Preprocessing::).
14607 Two other characters, `%' and `!', each start a comment anywhere on
14608 the line. Thus you can't use the `modulus' and `not' operators in
14609 expressions normally associated with these two characters.
14611 A `;' is a line separator, treated as a new-line, so separate
14612 instructions can be specified on a single line.
14615 File: as.info, Node: MMIX-Symbols, Next: MMIX-Regs, Prev: MMIX-Chars, Up: MMIX-Syntax
14620 The character `:' is permitted in identifiers. There are two
14621 exceptions to it being treated as any other symbol character: if a
14622 symbol begins with `:', it means that the symbol is in the global
14623 namespace and that the current prefix should not be prepended to that
14624 symbol (*note MMIX-prefix::). The `:' is then not considered part of
14625 the symbol. For a symbol in the label position (first on a line), a `:'
14626 at the end of a symbol is silently stripped off. A label is permitted,
14627 but not required, to be followed by a `:', as with many other assembly
14630 The character `@' in an expression, is a synonym for `.', the
14633 In addition to the common forward and backward local symbol formats
14634 (*note Symbol Names::), they can be specified with upper-case `B' and
14635 `F', as in `8B' and `9F'. A local label defined for the current
14636 position is written with a `H' appended to the number:
14638 This and traditional local-label formats cannot be mixed: a label
14639 must be defined and referred to using the same format.
14641 There's a minor caveat: just as for the ordinary local symbols, the
14642 local symbols are translated into ordinary symbols using control
14643 characters are to hide the ordinal number of the symbol.
14644 Unfortunately, these symbols are not translated back in error messages.
14645 Thus you may see confusing error messages when local symbols are used.
14646 Control characters `\003' (control-C) and `\004' (control-D) are used
14647 for the MMIX-specific local-symbol syntax.
14649 The symbol `Main' is handled specially; it is always global.
14651 By defining the symbols `__.MMIX.start..text' and
14652 `__.MMIX.start..data', the address of respectively the `.text' and
14653 `.data' segments of the final program can be defined, though when
14654 linking more than one object file, the code or data in the object file
14655 containing the symbol is not guaranteed to be start at that position;
14656 just the final executable. *Note MMIX-loc::.
14659 File: as.info, Node: MMIX-Regs, Next: MMIX-Pseudos, Prev: MMIX-Symbols, Up: MMIX-Syntax
14661 9.28.3.3 Register names
14662 .......................
14664 Local and global registers are specified as `$0' to `$255'. The
14665 recognized special register names are `rJ', `rA', `rB', `rC', `rD',
14666 `rE', `rF', `rG', `rH', `rI', `rK', `rL', `rM', `rN', `rO', `rP', `rQ',
14667 `rR', `rS', `rT', `rU', `rV', `rW', `rX', `rY', `rZ', `rBB', `rTT',
14668 `rWW', `rXX', `rYY' and `rZZ'. A leading `:' is optional for special
14671 Local and global symbols can be equated to register names and used in
14672 place of ordinary registers.
14674 Similarly for special registers, local and global symbols can be
14675 used. Also, symbols equated from numbers and constant expressions are
14676 allowed in place of a special register, except when either of the
14677 options `--no-predefined-syms' and `--fixed-special-register-names' are
14678 specified. Then only the special register names above are allowed for
14679 the instructions having a special register operand; `GET' and `PUT'.
14682 File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax
14684 9.28.3.4 Assembler Directives
14685 .............................
14688 The `LOC' directive sets the current location to the value of the
14689 operand field, which may include changing sections. If the
14690 operand is a constant, the section is set to either `.data' if the
14691 value is `0x2000000000000000' or larger, else it is set to `.text'.
14692 Within a section, the current location may only be changed to
14693 monotonically higher addresses. A LOC expression must be a
14694 previously defined symbol or a "pure" constant.
14696 An example, which sets the label PREV to the current location, and
14697 updates the current location to eight bytes forward:
14700 When a LOC has a constant as its operand, a symbol
14701 `__.MMIX.start..text' or `__.MMIX.start..data' is defined
14702 depending on the address as mentioned above. Each such symbol is
14703 interpreted as special by the linker, locating the section at that
14704 address. Note that if multiple files are linked, the first object
14705 file with that section will be mapped to that address (not
14706 necessarily the file with the LOC definition).
14710 LOCAL external_symbol
14714 This directive-operation generates a link-time assertion that the
14715 operand does not correspond to a global register. The operand is
14716 an expression that at link-time resolves to a register symbol or a
14717 number. A number is treated as the register having that number.
14718 There is one restriction on the use of this directive: the
14719 pseudo-directive must be placed in a section with contents, code
14723 The `IS' directive:
14724 asymbol IS an_expression
14725 sets the symbol `asymbol' to `an_expression'. A symbol may not be
14726 set more than once using this directive. Local labels may be set
14727 using this directive, for example:
14731 This directive reserves a global register, gives it an initial
14732 value and optionally gives it a symbolic name. Some examples:
14735 breg GREG data_value
14737 .greg creg, another_data_value
14739 The symbolic register name can be used in place of a (non-special)
14740 register. If a value isn't provided, it defaults to zero. Unless
14741 the option `--no-merge-gregs' is specified, non-zero registers
14742 allocated with this directive may be eliminated by `as'; another
14743 register with the same value used in its place. Any of the
14744 instructions `CSWAP', `GO', `LDA', `LDBU', `LDB', `LDHT', `LDOU',
14745 `LDO', `LDSF', `LDTU', `LDT', `LDUNC', `LDVTS', `LDWU', `LDW',
14746 `PREGO', `PRELD', `PREST', `PUSHGO', `STBU', `STB', `STCO', `STHT',
14747 `STOU', `STSF', `STTU', `STT', `STUNC', `SYNCD', `SYNCID', can
14748 have a value nearby an initial value in place of its second and
14749 third operands. Here, "nearby" is defined as within the range
14750 0...255 from the initial value of such an allocated register.
14752 buffer1 BYTE 0,0,0,0,0
14753 buffer2 BYTE 0,0,0,0,0
14757 In the example above, the `Y' field of the `LDOUI' instruction
14758 (LDOU with a constant Z) will be replaced with the global register
14759 allocated for `buffer1', and the `Z' field will have the value 5,
14760 the offset from `buffer1' to `buffer2'. The result is equivalent
14762 buffer1 BYTE 0,0,0,0,0
14763 buffer2 BYTE 0,0,0,0,0
14765 tmpreg GREG buffer1
14766 LDOU $42,tmpreg,(buffer2-buffer1)
14768 Global registers allocated with this directive are allocated in
14769 order higher-to-lower within a file. Other than that, the exact
14770 order of register allocation and elimination is undefined. For
14771 example, the order is undefined when more than one file with such
14772 directives are linked together. With the options `-x' and
14773 `--linker-allocated-gregs', `GREG' directives for two-operand
14774 cases like the one mentioned above can be omitted. Sufficient
14775 global registers will then be allocated by the linker.
14778 The `BYTE' directive takes a series of operands separated by a
14779 comma. If an operand is a string (*note Strings::), each
14780 character of that string is emitted as a byte. Other operands
14781 must be constant expressions without forward references, in the
14782 range 0...255. If you need operands having expressions with
14783 forward references, use `.byte' (*note Byte::). An operand can be
14784 omitted, defaulting to a zero value.
14789 The directives `WYDE', `TETRA' and `OCTA' emit constants of two,
14790 four and eight bytes size respectively. Before anything else
14791 happens for the directive, the current location is aligned to the
14792 respective constant-size boundary. If a label is defined at the
14793 beginning of the line, its value will be that after the alignment.
14794 A single operand can be omitted, defaulting to a zero value
14795 emitted for the directive. Operands can be expressed as strings
14796 (*note Strings::), in which case each character in the string is
14797 emitted as a separate constant of the size indicated by the
14801 The `PREFIX' directive sets a symbol name prefix to be prepended to
14802 all symbols (except local symbols, *note MMIX-Symbols::), that are
14803 not prefixed with `:', until the next `PREFIX' directive. Such
14804 prefixes accumulate. For example,
14808 defines a symbol `abc' with the value 0.
14812 A pair of `BSPEC' and `ESPEC' directives delimit a section of
14813 special contents (without specified semantics). Example:
14817 The single operand to `BSPEC' must be number in the range 0...255.
14818 The `BSPEC' number 80 is used by the GNU binutils implementation.
14821 File: as.info, Node: MMIX-mmixal, Prev: MMIX-Syntax, Up: MMIX-Dependent
14823 9.28.4 Differences to `mmixal'
14824 ------------------------------
14826 The binutils `as' and `ld' combination has a few differences in
14827 function compared to `mmixal' (*note mmixsite::).
14829 The replacement of a symbol with a GREG-allocated register (*note
14830 GREG-base::) is not handled the exactly same way in `as' as in
14831 `mmixal'. This is apparent in the `mmixal' example file `inout.mms',
14832 where different registers with different offsets, eventually yielding
14833 the same address, are used in the first instruction. This type of
14834 difference should however not affect the function of any program unless
14835 it has specific assumptions about the allocated register number.
14837 Line numbers (in the `mmo' object format) are currently not
14840 Expression operator precedence is not that of mmixal: operator
14841 precedence is that of the C programming language. It's recommended to
14842 use parentheses to explicitly specify wanted operator precedence
14843 whenever more than one type of operators are used.
14845 The serialize unary operator `&', the fractional division operator
14846 `//', the logical not operator `!' and the modulus operator `%' are not
14849 Symbols are not global by default, unless the option
14850 `--globalize-symbols' is passed. Use the `.global' directive to
14851 globalize symbols (*note Global::).
14853 Operand syntax is a bit stricter with `as' than `mmixal'. For
14854 example, you can't say `addu 1,2,3', instead you must write `addu
14857 You can't LOC to a lower address than those already visited (i.e.,
14860 A LOC directive must come before any emitted code.
14862 Predefined symbols are visible as file-local symbols after use. (In
14863 the ELF file, that is--the linked mmo file has no notion of a file-local
14866 Some mapping of constant expressions to sections in LOC expressions
14867 is attempted, but that functionality is easily confused and should be
14868 avoided unless compatibility with `mmixal' is required. A LOC
14869 expression to `0x2000000000000000' or higher, maps to the `.data'
14870 section and lower addresses map to the `.text' section (*note
14873 The code and data areas are each contiguous. Sparse programs with
14874 far-away LOC directives will take up the same amount of space as a
14875 contiguous program with zeros filled in the gaps between the LOC
14876 directives. If you need sparse programs, you might try and get the
14877 wanted effect with a linker script and splitting up the code parts into
14878 sections (*note Section::). Assembly code for this, to be compatible
14879 with `mmixal', would look something like:
14881 LOC away_expression
14885 `as' will not execute the LOC directive and `mmixal' ignores the
14886 lines with `.'. This construct can be used generally to help
14889 Symbols can't be defined twice-not even to the same value.
14891 Instruction mnemonics are recognized case-insensitive, though the
14892 `IS' and `GREG' pseudo-operations must be specified in upper-case
14895 There's no unicode support.
14897 The following is a list of programs in `mmix.tar.gz', available at
14898 `http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html', last
14899 checked with the version dated 2001-08-25 (md5sum
14900 c393470cfc86fac040487d22d2bf0172) that assemble with `mmixal' but do
14901 not assemble with `as':
14904 LOC to a previous address.
14907 Redefines symbol `Done'.
14910 Uses the serial operator `&'.
14913 File: as.info, Node: MSP430-Dependent, Next: NDS32-Dependent, Prev: MMIX-Dependent, Up: Machine Dependencies
14915 9.29 MSP 430 Dependent Features
14916 ===============================
14920 * MSP430 Options:: Options
14921 * MSP430 Syntax:: Syntax
14922 * MSP430 Floating Point:: Floating Point
14923 * MSP430 Directives:: MSP 430 Machine Directives
14924 * MSP430 Opcodes:: Opcodes
14925 * MSP430 Profiling Capability:: Profiling Capability
14928 File: as.info, Node: MSP430 Options, Next: MSP430 Syntax, Up: MSP430-Dependent
14934 selects the mcu architecture. If the architecture is 430Xv2 then
14935 this also enables NOP generation unless the `-mN' is also
14939 selects the cpu architecture. If the architecture is 430Xv2 then
14940 this also enables NOP generation unless the `-mN' is also
14944 enables polymorph instructions handler.
14947 enables relaxation at assembly time. DANGEROUS!
14950 indicates that the input uses the large code model.
14953 enables the generation of a NOP instruction following any
14954 instruction that might change the interrupts enabled/disabled
14955 state. The pipelined nature of the MSP430 core means that any
14956 instruction that changes the interrupt state (`EINT', `DINT', `BIC
14957 #8, SR', `BIS #8, SR' or `MOV.W <>, SR') must be followed by a NOP
14958 instruction in order to ensure the correct processing of
14959 interrupts. By default it is up to the programmer to supply these
14960 NOP instructions, but this command line option enables the
14961 automatic insertion by the assembler, if they are missing.
14964 disables the generation of a NOP instruction following any
14965 instruction that might change the interrupts enabled/disabled
14966 state. This is the default behaviour.
14969 tells the assembler to generate a warning message if a NOP does not
14970 immediately forllow an instruction that enables or disables
14971 interrupts. This is the default.
14973 Note that this option can be stacked with the `-mn' option so that
14974 the assembler will both warn about missing NOP instructions and
14975 then insert them automatically.
14978 disables warnings about missing NOP instructions.
14981 mark the object file as one that requires data to copied from ROM
14982 to RAM at execution startup. Disabled by default.
14986 File: as.info, Node: MSP430 Syntax, Next: MSP430 Floating Point, Prev: MSP430 Options, Up: MSP430-Dependent
14993 * MSP430-Macros:: Macros
14994 * MSP430-Chars:: Special Characters
14995 * MSP430-Regs:: Register Names
14996 * MSP430-Ext:: Assembler Extensions
14999 File: as.info, Node: MSP430-Macros, Next: MSP430-Chars, Up: MSP430 Syntax
15004 The macro syntax used on the MSP 430 is like that described in the MSP
15005 430 Family Assembler Specification. Normal `as' macros should still
15008 Additional built-in macros are:
15011 Extracts least significant word from 32-bit expression 'exp'.
15014 Extracts most significant word from 32-bit expression 'exp'.
15017 Extracts 3rd word from 64-bit expression 'exp'.
15020 Extracts 4rd word from 64-bit expression 'exp'.
15023 They normally being used as an immediate source operand.
15024 mov #llo(1), r10 ; == mov #1, r10
15025 mov #lhi(1), r10 ; == mov #0, r10
15028 File: as.info, Node: MSP430-Chars, Next: MSP430-Regs, Prev: MSP430-Macros, Up: MSP430 Syntax
15030 9.29.2.2 Special Characters
15031 ...........................
15033 A semicolon (`;') appearing anywhere on a line starts a comment that
15034 extends to the end of that line.
15036 If a `#' appears as the first character of a line then the whole
15037 line is treated as a comment, but it can also be a logical line number
15038 directive (*note Comments::) or a preprocessor control command (*note
15041 Multiple statements can appear on the same line provided that they
15042 are separated by the `{' character.
15044 The character `$' in jump instructions indicates current location and
15045 implemented only for TI syntax compatibility.
15048 File: as.info, Node: MSP430-Regs, Next: MSP430-Ext, Prev: MSP430-Chars, Up: MSP430 Syntax
15050 9.29.2.3 Register Names
15051 .......................
15053 General-purpose registers are represented by predefined symbols of the
15054 form `rN' (for global registers), where N represents a number between
15055 `0' and `15'. The leading letters may be in either upper or lower
15056 case; for example, `r13' and `R7' are both valid register names.
15058 Register names `PC', `SP' and `SR' cannot be used as register names
15059 and will be treated as variables. Use `r0', `r1', and `r2' instead.
15062 File: as.info, Node: MSP430-Ext, Prev: MSP430-Regs, Up: MSP430 Syntax
15064 9.29.2.4 Assembler Extensions
15065 .............................
15068 As destination operand being treated as `0(rn)'
15071 As source operand being treated as `@rn'
15074 Skips next N bytes followed by jump instruction and equivalent to
15078 Also, there are some instructions, which cannot be found in other
15079 assemblers. These are branch instructions, which has different opcodes
15080 upon jump distance. They all got PC relative addressing mode.
15083 A polymorph instruction which is `jeq label' in case if jump
15084 distance within allowed range for cpu's jump instruction. If not,
15085 this unrolls into a sequence of
15090 A polymorph instruction which is `jne label' or `jeq +4; br label'
15093 A polymorph instruction which is `jl label' or `jge +4; br label'
15096 A polymorph instruction which is `jn label' or `jn +2; jmp +4; br
15100 A polymorph instruction which is `jlo label' or `jhs +2; br label'
15103 A polymorph instruction which is `jge label' or `jl +4; br label'
15106 A polymorph instruction which is `jhs label' or `jlo +4; br label'
15109 A polymorph instruction which is `jeq +2; jge label' or `jeq +6;
15113 A polymorph instruction which is `jeq +2; jhs label' or `jeq +6;
15117 A polymorph instruction which is `jeq label; jlo label' or `jeq
15118 +2; jhs +4; br label'
15121 A polymorph instruction which is `jeq label; jl label' or `jeq
15122 +2; jge +4; br label'
15125 A polymorph instruction which is `jmp label' or `br label'
15128 File: as.info, Node: MSP430 Floating Point, Next: MSP430 Directives, Prev: MSP430 Syntax, Up: MSP430-Dependent
15130 9.29.3 Floating Point
15131 ---------------------
15133 The MSP 430 family uses IEEE 32-bit floating-point numbers.
15136 File: as.info, Node: MSP430 Directives, Next: MSP430 Opcodes, Prev: MSP430 Floating Point, Up: MSP430-Dependent
15138 9.29.4 MSP 430 Machine Directives
15139 ---------------------------------
15142 This directive is ignored; it is accepted for compatibility with
15143 other MSP 430 assemblers.
15145 _Warning:_ in other versions of the GNU assembler, `.file' is
15146 used for the directive called `.app-file' in the MSP 430
15150 This directive is ignored; it is accepted for compatibility with
15151 other MSP 430 assemblers.
15154 Sets the target microcontroller in the same way as the `-mmcu'
15155 command line option.
15158 Sets the target architecture in the same way as the `-mcpu'
15159 command line option.
15162 This directive instructs assembler to add new profile entry to the
15166 This directive instructs assembler to add an undefined reference to
15167 the symbol following the directive. The maximum symbol name
15168 length is 1023 characters. No relocation is created for this
15169 symbol; it will exist purely for pulling in object files from
15170 archives. Note that this reloc is not sufficient to prevent
15171 garbage collection; use a KEEP() directive in the linker file to
15172 preserve such objects.
15176 File: as.info, Node: MSP430 Opcodes, Next: MSP430 Profiling Capability, Prev: MSP430 Directives, Up: MSP430-Dependent
15181 `as' implements all the standard MSP 430 opcodes. No additional
15182 pseudo-instructions are needed on this family.
15184 For information on the 430 machine instruction set, see `MSP430
15185 User's Manual, document slau049d', Texas Instrument, Inc.
15188 File: as.info, Node: MSP430 Profiling Capability, Prev: MSP430 Opcodes, Up: MSP430-Dependent
15190 9.29.6 Profiling Capability
15191 ---------------------------
15193 It is a performance hit to use gcc's profiling approach for this tiny
15194 target. Even more - jtag hardware facility does not perform any
15195 profiling functions. However we've got gdb's built-in simulator where
15196 we can do anything.
15198 We define new section `.profiler' which holds all profiling
15199 information. We define new pseudo operation `.profiler' which will
15200 instruct assembler to add new profile entry to the object file. Profile
15201 should take place at the present address.
15203 Pseudo operation format:
15205 `.profiler flags,function_to_profile [, cycle_corrector, extra]'
15209 `flags' is a combination of the following characters:
15218 function is in init section
15221 function is in fini section
15233 interrupt service routine
15248 long jump / sjlj unwind
15251 an arbitrary code fragment
15254 extra parameter saved (a constant value like frame size)
15256 `function_to_profile'
15260 a value which should be added to the cycle counter, zero if
15264 any extra parameter, zero if omitted.
15269 .type fxx,@function
15271 .LFrameOffset_fxx=0x08
15272 .profiler "scdP", fxx ; function entry.
15273 ; we also demand stack value to be saved
15278 .profiler "cdpt",fxx,0, .LFrameOffset_fxx ; check stack value at this point
15279 ; (this is a prologue end)
15280 ; note, that spare var filled with
15284 .profiler cdE,fxx ; check stack
15289 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter
15290 ret ; cause 'ret' insn takes 3 cycles
15293 File: as.info, Node: NDS32-Dependent, Next: NiosII-Dependent, Prev: MSP430-Dependent, Up: Machine Dependencies
15295 9.30 NDS32 Dependent Features
15296 =============================
15298 The NDS32 processors family includes high-performance and low-power
15299 32-bit processors for high-end to low-end. GNU `as' for NDS32
15300 architectures supports NDS32 ISA version 3. For detail about NDS32
15301 instruction set, please see the AndeStar ISA User Manual which is
15302 availible at http://www.andestech.com/en/index/index.htm
15306 * NDS32 Options:: Assembler options
15307 * NDS32 Syntax:: High-level assembly macros
15310 File: as.info, Node: NDS32 Options, Next: NDS32 Syntax, Up: NDS32-Dependent
15312 9.30.1 NDS32 Options
15313 --------------------
15315 The NDS32 configurations of GNU `as' support these special options:
15318 Optimize for performance.
15321 Optimize for space.
15324 Produce little endian data output.
15327 Produce little endian data output.
15332 `-mno-fp-as-gp-relax'
15333 Suppress fp-as-gp relaxation for this file.
15336 Back-to-back branch optimization.
15339 Suppress all relaxation for this file.
15341 `-march=<arch name>'
15342 Assemble for architecture <arch name> which could be v3, v3j, v3m,
15343 v3f, v3s, v2, v2j, v2f, v2s.
15345 `-mbaseline=<baseline>'
15346 Assemble for baseline <baseline> which could be v2, v3, v3m.
15349 Specify a FPU configuration.
15350 `0 8 SP / 4 DP registers'
15352 `1 16 SP / 8 DP registers'
15354 `2 32 SP / 16 DP registers'
15356 `3 32 SP / 32 DP registers'
15359 Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
15362 Enable/Disable Multiply instructions support.
15365 Enable/Disable Divide instructions support.
15368 Enable/Disable 16-bit extension
15371 Enable/Disable d0/d1 registers
15374 Enable/Disable Performance extension
15377 Enable/Disable Performance extension 2
15379 `-m[no-]string-ext'
15380 Enable/Disable String extension
15382 `-m[no-]reduced-regs'
15383 Enable/Disable Reduced Register configuration (GPR16) option
15385 `-m[no-]audio-isa-ext'
15386 Enable/Disable AUDIO ISA extension
15388 `-m[no-]fpu-sp-ext'
15389 Enable/Disable FPU SP extension
15391 `-m[no-]fpu-dp-ext'
15392 Enable/Disable FPU DP extension
15395 Enable/Disable FPU fused-multiply-add instructions
15398 Turn on all extensions and instructions support
15401 File: as.info, Node: NDS32 Syntax, Prev: NDS32 Options, Up: NDS32-Dependent
15408 * NDS32-Chars:: Special Characters
15409 * NDS32-Regs:: Register Names
15410 * NDS32-Ops:: Pseudo Instructions
15413 File: as.info, Node: NDS32-Chars, Next: NDS32-Regs, Up: NDS32 Syntax
15415 9.30.2.1 Special Characters
15416 ...........................
15418 Use `#' at column 1 and `!' anywhere in the line except inside quotes.
15420 Multiple instructions in a line are allowed though not recommended
15421 and should be separated by `;'.
15423 Assembler is not case-sensitive in general except user defined label.
15424 For example, `jral F1' is different from `jral f1' while it is the same
15428 File: as.info, Node: NDS32-Regs, Next: NDS32-Ops, Prev: NDS32-Chars, Up: NDS32 Syntax
15430 9.30.2.2 Register Names
15431 .......................
15433 `General purpose registers (GPR)'
15434 There are 32 32-bit general purpose registers $r0 to $r31.
15436 `Accumulators d0 and d1'
15437 64-bit accumulators: $d0.hi, $d0.lo, $d1.hi, and $d1.lo.
15439 `Assembler reserved register $ta'
15440 Register $ta ($r15) is reserved for assembler using.
15442 `Operating system reserved registers $p0 and $p1'
15443 Registers $p0 ($r26) and $p1 ($r27) are used by operating system
15444 as scratch registers.
15446 `Frame pointer $fp'
15447 Register $r28 is regarded as the frame pointer.
15450 Register $r29 is regarded as the global pointer.
15453 Register $r30 is regarded as the link pointer.
15456 Register $r31 is regarded as the stack pointer.
15459 File: as.info, Node: NDS32-Ops, Prev: NDS32-Regs, Up: NDS32 Syntax
15461 9.30.2.3 Pseudo Instructions
15462 ............................
15465 load 32-bit integer into register rt5. `sethi rt5,hi20(imm32)'
15466 and then `ori rt5,reg,lo12(imm32)'.
15469 Load 32-bit address of var into register rt5. `sethi
15470 rt5,hi20(var)' and then `ori reg,rt5,lo12(var)'
15473 Load value of var into register rt5. `sethi $ta,hi20(var)' and
15474 then `l[bhw]i rt5,[$ta+lo12(var)]'
15477 Load value of var into register rt5. `sethi $ta,hi20(var)' and
15478 then `l[bh]si rt5,[$ta+lo12(var)]'
15480 `l.[bhw]p rt5,var,inc'
15481 Load value of var into register rt5 and increment $ta by amount
15482 inc. `la $ta,var' and then `l[bhw]i.bi rt5,[$ta],inc'
15484 `l.[bhw]pc rt5,inc'
15485 Continue loading value of var into register rt5 and increment $ta
15486 by amount inc. `l[bhw]i.bi rt5,[$ta],inc.'
15488 `l.[bh]sp rt5,var,inc'
15489 Load value of var into register rt5 and increment $ta by amount
15490 inc. `la $ta,var' and then `l[bh]si.bi rt5,[$ta],inc'
15492 `l.[bh]spc rt5,inc'
15493 Continue loading value of var into register rt5 and increment $ta
15494 by amount inc. `l[bh]si.bi rt5,[$ta],inc.'
15497 Store register rt5 to var. `sethi $ta,hi20(var)' and then
15498 `s[bhw]i rt5,[$ta+lo12(var)]'
15500 `s.[bhw]p rt5,var,inc'
15501 Store register rt5 to var and increment $ta by amount inc. `la
15502 $ta,var' and then `s[bhw]i.bi rt5,[$ta],inc'
15504 `s.[bhw]pc rt5,inc'
15505 Continue storing register rt5 to var and increment $ta by amount
15506 inc. `s[bhw]i.bi rt5,[$ta],inc.'
15509 Alias of `nor rt5,ra5,ra5'.
15512 Alias of `subri rt5,ra5,0'.
15515 Depending on how it is assembled, it is translated into `r5 rb5'
15519 Branch to label depending on how it is assembled, it is translated
15520 into `j8 label', `j label', or "`la $ta,label' `br $ta'".
15523 Alias of jral br5 depending on how it is assembled, it is
15524 translated into `jral5 rb5' or `jral rb5'.
15527 Alias of jal fname depending on how it is assembled, it is
15528 translated into `jal fname' or "`la $ta,fname' `bral $ta'".
15531 Call function fname same as `jal fname'.
15534 For 16-bit, this is `mov55 rt5,ra5'. For no 16-bit, this is `ori
15538 This is the same as `l.w rt5,var'.
15541 This is the same as `li rt5,imm32'.
15544 Push contents of registers from ra5 to rb5 into stack.
15547 Push content of register ra5 into stack. (same `pushm ra5,ra5').
15550 Push value of double-word variable var into stack.
15553 Push value of word variable var into stack.
15556 Push value of half-word variable var into stack.
15559 Push value of byte variable var into stack.
15562 Push 32-bit address of variable var into stack.
15565 Push 32-bit immediate value into stack.
15568 Pop top of stack values into registers ra5 to rb5.
15571 Pop top of stack value into register. (same as `popm rt5,rt5'.)
15574 Pop value of double-word variable var from stack using register ra5
15575 as 2nd scratch register. (1st is $ta)
15578 Pop value of word variable var from stack using register ra5.
15581 Pop value of half-word variable var from stack using register ra5.
15584 Pop value of byte variable var from stack using register ra5.
15588 File: as.info, Node: NiosII-Dependent, Next: NS32K-Dependent, Prev: NDS32-Dependent, Up: Machine Dependencies
15590 9.31 Nios II Dependent Features
15591 ===============================
15595 * Nios II Options:: Options
15596 * Nios II Syntax:: Syntax
15597 * Nios II Relocations:: Relocations
15598 * Nios II Directives:: Nios II Machine Directives
15599 * Nios II Opcodes:: Opcodes
15602 File: as.info, Node: Nios II Options, Next: Nios II Syntax, Up: NiosII-Dependent
15608 Replace identified out-of-range branches with PC-relative `jmp'
15609 sequences when possible. The generated code sequences are suitable
15610 for use in position-independent code, but there is a practical
15611 limit on the extended branch range because of the length of the
15612 sequences. This option is the default.
15615 Replace branch instructions not determinable to be in range and
15616 all call instructions with `jmp' and `callr' sequences
15617 (respectively). This option generates absolute relocations
15618 against the target symbols and is not appropriate for
15619 position-independent code.
15622 Do not replace any branches or calls.
15625 Generate big-endian output.
15628 Generate little-endian output. This is the default.
15632 File: as.info, Node: Nios II Syntax, Next: Nios II Relocations, Prev: Nios II Options, Up: NiosII-Dependent
15639 * Nios II Chars:: Special Characters
15642 File: as.info, Node: Nios II Chars, Up: Nios II Syntax
15644 9.31.2.1 Special Characters
15645 ...........................
15647 `#' is the line comment character. `;' is the line separator character.
15650 File: as.info, Node: Nios II Relocations, Next: Nios II Directives, Prev: Nios II Syntax, Up: NiosII-Dependent
15652 9.31.3 Nios II Machine Relocations
15653 ----------------------------------
15655 `%hiadj(EXPRESSION)'
15656 Extract the upper 16 bits of EXPRESSION and add one if the 15th
15659 The value of `%hiadj(EXPRESSION)' is:
15660 ((EXPRESSION >> 16) & 0xffff) + ((EXPRESSION >> 15) & 0x01)
15662 The `%hiadj' relocation is intended to be used with the `addi',
15663 `ld' or `st' instructions along with a `%lo', in order to load a
15666 movhi r2, %hiadj(symbol)
15667 addi r2, r2, %lo(symbol)
15670 Extract the upper 16 bits of EXPRESSION.
15673 Extract the lower 16 bits of EXPRESSION.
15675 `%gprel(EXPRESSION)'
15676 Subtract the value of the symbol `_gp' from EXPRESSION.
15678 The intention of the `%gprel' relocation is to have a fast small
15679 area of memory which only takes a 16-bit immediate to access.
15685 ldw r4, %gprel(fastint)(gp)
15687 `%call(EXPRESSION)'
15689 `%call_lo(EXPRESSION)'
15691 `%call_hiadj(EXPRESSION)'
15693 `%got_lo(EXPRESSION)'
15694 `%got_hiadj(EXPRESSION)'
15695 `%gotoff(EXPRESSION)'
15696 `%gotoff_lo(EXPRESSION)'
15697 `%gotoff_hiadj(EXPRESSION)'
15698 `%tls_gd(EXPRESSION)'
15699 `%tls_ie(EXPRESSION)'
15700 `%tls_le(EXPRESSION)'
15701 `%tls_ldm(EXPRESSION)'
15702 `%tls_ldo(EXPRESSION)'
15703 These relocations support the ABI for Linux Systems documented in
15704 the `Nios II Processor Reference Handbook'.
15707 File: as.info, Node: Nios II Directives, Next: Nios II Opcodes, Prev: Nios II Relocations, Up: NiosII-Dependent
15709 9.31.4 Nios II Machine Directives
15710 ---------------------------------
15712 `.align EXPRESSION [, EXPRESSION]'
15713 This is the generic `.align' directive, however this aligns to a
15717 Create an aligned constant 2 bytes in size.
15720 Create an aligned constant 4 bytes in size.
15722 `.dword EXPRESSION'
15723 Create an aligned constant 8 bytes in size.
15725 `.2byte EXPRESSION'
15726 Create an unaligned constant 2 bytes in size.
15728 `.4byte EXPRESSION'
15729 Create an unaligned constant 4 bytes in size.
15731 `.8byte EXPRESSION'
15732 Create an unaligned constant 8 bytes in size.
15734 `.16byte EXPRESSION'
15735 Create an unaligned constant 16 bytes in size.
15738 Allows assembly code to use `at' register without warning. Macro
15739 or relaxation expansions generate warnings.
15742 Assembly code using `at' register generates warnings, and macro
15743 expansion and relaxation are enabled.
15746 Allows assembly code to use `ba' and `bt' registers without
15750 Turns warnings back on for using `ba' and `bt' registers.
15753 Do not replace any branches or calls.
15755 `.set relaxsection'
15756 Replace identified out-of-range branches with `jmp' sequences
15759 `.set relaxsection'
15760 Replace all branch and call instructions with `jmp' and `callr'
15764 All other `.set' are the normal use.
15768 File: as.info, Node: Nios II Opcodes, Prev: Nios II Directives, Up: NiosII-Dependent
15773 `as' implements all the standard Nios II opcodes documented in the
15774 `Nios II Processor Reference Handbook', including the assembler
15775 pseudo-instructions.
15778 File: as.info, Node: NS32K-Dependent, Next: SH-Dependent, Prev: NiosII-Dependent, Up: Machine Dependencies
15780 9.32 NS32K Dependent Features
15781 =============================
15785 * NS32K Syntax:: Syntax
15788 File: as.info, Node: NS32K Syntax, Up: NS32K-Dependent
15795 * NS32K-Chars:: Special Characters
15798 File: as.info, Node: NS32K-Chars, Up: NS32K Syntax
15800 9.32.1.1 Special Characters
15801 ...........................
15803 The presence of a `#' appearing anywhere on a line indicates the start
15804 of a comment that extends to the end of that line.
15806 If a `#' appears as the first character of a line then the whole
15807 line is treated as a comment, but in this case the line can also be a
15808 logical line number directive (*note Comments::) or a preprocessor
15809 control command (*note Preprocessing::).
15811 If Sequent compatibility has been configured into the assembler then
15812 the `|' character appearing as the first character on a line will also
15813 indicate the start of a line comment.
15815 The `;' character can be used to separate statements on the same
15819 File: as.info, Node: PDP-11-Dependent, Next: PJ-Dependent, Prev: SH64-Dependent, Up: Machine Dependencies
15821 9.33 PDP-11 Dependent Features
15822 ==============================
15826 * PDP-11-Options:: Options
15827 * PDP-11-Pseudos:: Assembler Directives
15828 * PDP-11-Syntax:: DEC Syntax versus BSD Syntax
15829 * PDP-11-Mnemonics:: Instruction Naming
15830 * PDP-11-Synthetic:: Synthetic Instructions
15833 File: as.info, Node: PDP-11-Options, Next: PDP-11-Pseudos, Up: PDP-11-Dependent
15838 The PDP-11 version of `as' has a rich set of machine dependent options.
15840 9.33.1.1 Code Generation Options
15841 ................................
15844 Generate position-independent (or position-dependent) code.
15846 The default is to generate position-independent code.
15848 9.33.1.2 Instruction Set Extension Options
15849 ..........................................
15851 These options enables or disables the use of extensions over the base
15852 line instruction set as introduced by the first PDP-11 CPU: the KA11.
15853 Most options come in two variants: a `-m'EXTENSION that enables
15854 EXTENSION, and a `-mno-'EXTENSION that disables EXTENSION.
15856 The default is to enable all extensions.
15858 `-mall | -mall-extensions'
15859 Enable all instruction set extensions.
15862 Disable all instruction set extensions.
15865 Enable (or disable) the use of the commercial instruction set,
15866 which consists of these instructions: `ADDNI', `ADDN', `ADDPI',
15867 `ADDP', `ASHNI', `ASHN', `ASHPI', `ASHP', `CMPCI', `CMPC',
15868 `CMPNI', `CMPN', `CMPPI', `CMPP', `CVTLNI', `CVTLN', `CVTLPI',
15869 `CVTLP', `CVTNLI', `CVTNL', `CVTNPI', `CVTNP', `CVTPLI', `CVTPL',
15870 `CVTPNI', `CVTPN', `DIVPI', `DIVP', `L2DR', `L3DR', `LOCCI',
15871 `LOCC', `MATCI', `MATC', `MOVCI', `MOVC', `MOVRCI', `MOVRC',
15872 `MOVTCI', `MOVTC', `MULPI', `MULP', `SCANCI', `SCANC', `SKPCI',
15873 `SKPC', `SPANCI', `SPANC', `SUBNI', `SUBN', `SUBPI', and `SUBP'.
15876 Enable (or disable) the use of the `CSM' instruction.
15879 Enable (or disable) the use of the extended instruction set, which
15880 consists of these instructions: `ASHC', `ASH', `DIV', `MARK',
15881 `MUL', `RTT', `SOB' `SXT', and `XOR'.
15884 `-mno-fis | -mno-kev11'
15885 Enable (or disable) the use of the KEV11 floating-point
15886 instructions: `FADD', `FDIV', `FMUL', and `FSUB'.
15888 `-mfpp | -mfpu | -mfp-11'
15889 `-mno-fpp | -mno-fpu | -mno-fp-11'
15890 Enable (or disable) the use of FP-11 floating-point instructions:
15891 `ABSF', `ADDF', `CFCC', `CLRF', `CMPF', `DIVF', `LDCFF', `LDCIF',
15892 `LDEXP', `LDF', `LDFPS', `MODF', `MULF', `NEGF', `SETD', `SETF',
15893 `SETI', `SETL', `STCFF', `STCFI', `STEXP', `STF', `STFPS', `STST',
15894 `SUBF', and `TSTF'.
15896 `-mlimited-eis | -mno-limited-eis'
15897 Enable (or disable) the use of the limited extended instruction
15898 set: `MARK', `RTT', `SOB', `SXT', and `XOR'.
15900 The -mno-limited-eis options also implies -mno-eis.
15902 `-mmfpt | -mno-mfpt'
15903 Enable (or disable) the use of the `MFPT' instruction.
15905 `-mmultiproc | -mno-multiproc'
15906 Enable (or disable) the use of multiprocessor instructions:
15907 `TSTSET' and `WRTLCK'.
15909 `-mmxps | -mno-mxps'
15910 Enable (or disable) the use of the `MFPS' and `MTPS' instructions.
15913 Enable (or disable) the use of the `SPL' instruction.
15915 Enable (or disable) the use of the microcode instructions: `LDUB',
15918 9.33.1.3 CPU Model Options
15919 ..........................
15921 These options enable the instruction set extensions supported by a
15922 particular CPU, and disables all other extensions.
15925 KA11 CPU. Base line instruction set only.
15928 KB11 CPU. Enable extended instruction set and `SPL'.
15931 KD11-A CPU. Enable limited extended instruction set.
15934 KD11-B CPU. Base line instruction set only.
15937 KD11-D CPU. Base line instruction set only.
15940 KD11-E CPU. Enable extended instruction set, `MFPS', and `MTPS'.
15942 `-mkd11f | -mkd11h | -mkd11q'
15943 KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended
15944 instruction set, `MFPS', and `MTPS'.
15947 KD11-K CPU. Enable extended instruction set, `LDUB', `MED',
15948 `MFPS', `MFPT', `MTPS', and `XFC'.
15951 KD11-Z CPU. Enable extended instruction set, `CSM', `MFPS',
15952 `MFPT', `MTPS', and `SPL'.
15955 F11 CPU. Enable extended instruction set, `MFPS', `MFPT', and
15959 J11 CPU. Enable extended instruction set, `CSM', `MFPS', `MFPT',
15960 `MTPS', `SPL', `TSTSET', and `WRTLCK'.
15963 T11 CPU. Enable limited extended instruction set, `MFPS', and
15966 9.33.1.4 Machine Model Options
15967 ..............................
15969 These options enable the instruction set extensions supported by a
15970 particular machine model, and disables all other extensions.
15978 `-m11/05 | -m11/10'
15981 `-m11/15 | -m11/20'
15987 `-m11/23 | -m11/24'
15994 Ame as `-mkd11e' `-mfpp'.
15996 `-m11/35 | -m11/40'
16002 `-m11/45 | -m11/50 | -m11/55 | -m11/70'
16005 `-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94'
16012 File: as.info, Node: PDP-11-Pseudos, Next: PDP-11-Syntax, Prev: PDP-11-Options, Up: PDP-11-Dependent
16014 9.33.2 Assembler Directives
16015 ---------------------------
16017 The PDP-11 version of `as' has a few machine dependent assembler
16021 Switch to the `bss' section.
16024 Align the location counter to an even number.
16027 File: as.info, Node: PDP-11-Syntax, Next: PDP-11-Mnemonics, Prev: PDP-11-Pseudos, Up: PDP-11-Dependent
16029 9.33.3 PDP-11 Assembly Language Syntax
16030 --------------------------------------
16032 `as' supports both DEC syntax and BSD syntax. The only difference is
16033 that in DEC syntax, a `#' character is used to denote an immediate
16034 constants, while in BSD syntax the character for this purpose is `$'.
16036 general-purpose registers are named `r0' through `r7'. Mnemonic
16037 alternatives for `r6' and `r7' are `sp' and `pc', respectively.
16039 Floating-point registers are named `ac0' through `ac3', or
16040 alternatively `fr0' through `fr3'.
16042 Comments are started with a `#' or a `/' character, and extend to
16043 the end of the line. (FIXME: clash with immediates?)
16045 Multiple statements on the same line can be separated by the `;'
16049 File: as.info, Node: PDP-11-Mnemonics, Next: PDP-11-Synthetic, Prev: PDP-11-Syntax, Up: PDP-11-Dependent
16051 9.33.4 Instruction Naming
16052 -------------------------
16054 Some instructions have alternative names.
16072 File: as.info, Node: PDP-11-Synthetic, Prev: PDP-11-Mnemonics, Up: PDP-11-Dependent
16074 9.33.5 Synthetic Instructions
16075 -----------------------------
16077 The `JBR' and `J'CC synthetic instructions are not supported yet.
16080 File: as.info, Node: PJ-Dependent, Next: PPC-Dependent, Prev: PDP-11-Dependent, Up: Machine Dependencies
16082 9.34 picoJava Dependent Features
16083 ================================
16087 * PJ Options:: Options
16088 * PJ Syntax:: PJ Syntax
16091 File: as.info, Node: PJ Options, Next: PJ Syntax, Up: PJ-Dependent
16096 `as' has two additional command-line options for the picoJava
16099 This option selects little endian data output.
16102 This option selects big endian data output.
16105 File: as.info, Node: PJ Syntax, Prev: PJ Options, Up: PJ-Dependent
16112 * PJ-Chars:: Special Characters
16115 File: as.info, Node: PJ-Chars, Up: PJ Syntax
16117 9.34.2.1 Special Characters
16118 ...........................
16120 The presence of a `!' or `/' on a line indicates the start of a comment
16121 that extends to the end of the current line.
16123 If a `#' appears as the first character of a line then the whole
16124 line is treated as a comment, but in this case the line could also be a
16125 logical line number directive (*note Comments::) or a preprocessor
16126 control command (*note Preprocessing::).
16128 The `;' character can be used to separate statements on the same
16132 File: as.info, Node: PPC-Dependent, Next: RL78-Dependent, Prev: PJ-Dependent, Up: Machine Dependencies
16134 9.35 PowerPC Dependent Features
16135 ===============================
16139 * PowerPC-Opts:: Options
16140 * PowerPC-Pseudo:: PowerPC Assembler Directives
16141 * PowerPC-Syntax:: PowerPC Syntax
16144 File: as.info, Node: PowerPC-Opts, Next: PowerPC-Pseudo, Up: PPC-Dependent
16149 The PowerPC chip family includes several successive levels, using the
16150 same core instruction set, but including a few additional instructions
16151 at each level. There are exceptions to this however. For details on
16152 what instructions each variant supports, please see the chip's
16153 architecture reference manual.
16155 The following table lists all available PowerPC options.
16158 Generate ELF32 or XCOFF32.
16161 Generate ELF64 or XCOFF64.
16164 Set EF_PPC_RELOCATABLE_LIB in ELF flags.
16167 Generate code for POWER/2 (RIOS2).
16170 Generate code for POWER (RIOS1)
16173 Generate code for PowerPC 601.
16175 `-mppc, -mppc32, -m603, -m604'
16176 Generate code for PowerPC 603/604.
16179 Generate code for PowerPC 403/405.
16182 Generate code for PowerPC 440. BookE and some 405 instructions.
16185 Generate code for PowerPC 464.
16188 Generate code for PowerPC 476.
16190 `-m7400, -m7410, -m7450, -m7455'
16191 Generate code for PowerPC 7400/7410/7450/7455.
16194 Generate code for PowerPC 750CL.
16197 Generate code for PowerPC 620/625/630.
16200 Generate code for Motorola e500 core complex.
16203 Generate code for Freescale e500mc core complex.
16206 Generate code for Freescale e500mc64 core complex.
16209 Generate code for Freescale e5500 core complex.
16212 Generate code for Freescale e6500 core complex.
16215 Generate code for Motorola SPE instructions.
16218 Generate code for AppliedMicro Titan core complex.
16221 Generate code for PowerPC 64, including bridge insns.
16224 Generate code for 32-bit BookE.
16227 Generate code for A2 architecture.
16230 Generate code for PowerPC e300 family.
16233 Generate code for processors with AltiVec instructions.
16236 Generate code for Freescale PowerPC VLE instructions.
16239 Generate code for processors with Vector-Scalar (VSX) instructions.
16242 Generate code for processors with Hardware Transactional Memory
16246 Generate code for Power4 architecture.
16248 `-mpower5, -mpwr5, -mpwr5x'
16249 Generate code for Power5 architecture.
16252 Generate code for Power6 architecture.
16255 Generate code for Power7 architecture.
16258 Generate code for Power8 architecture.
16263 Generate code for Cell Broadband Engine architecture.
16266 Generate code Power/PowerPC common instructions.
16269 Generate code for any architecture (PWR/PWRX/PPC).
16272 Allow symbolic names for registers.
16275 Do not allow symbolic names for registers.
16278 Support for GCC's -mrelocatable option.
16280 `-mrelocatable-lib'
16281 Support for GCC's -mrelocatable-lib option.
16284 Set PPC_EMB bit in ELF flags.
16286 `-mlittle, -mlittle-endian, -le'
16287 Generate code for a little endian machine.
16289 `-mbig, -mbig-endian, -be'
16290 Generate code for a big endian machine.
16293 Generate code for Solaris.
16296 Do not generate code for Solaris.
16299 If an alignment directive inserts more than COUNT nops, put a
16300 branch at the beginning to skip execution of the nops.
16303 File: as.info, Node: PowerPC-Pseudo, Next: PowerPC-Syntax, Prev: PowerPC-Opts, Up: PPC-Dependent
16305 9.35.2 PowerPC Assembler Directives
16306 -----------------------------------
16308 A number of assembler directives are available for PowerPC. The
16309 following table is far from complete.
16311 `.machine "string"'
16312 This directive allows you to change the machine for which code is
16313 generated. `"string"' may be any of the -m cpu selection options
16314 (without the -m) enclosed in double quotes, `"push"', or `"pop"'.
16315 `.machine "push"' saves the currently selected cpu, which may be
16316 restored with `.machine "pop"'.
16319 File: as.info, Node: PowerPC-Syntax, Prev: PowerPC-Pseudo, Up: PPC-Dependent
16321 9.35.3 PowerPC Syntax
16322 ---------------------
16326 * PowerPC-Chars:: Special Characters
16329 File: as.info, Node: PowerPC-Chars, Up: PowerPC-Syntax
16331 9.35.3.1 Special Characters
16332 ...........................
16334 The presence of a `#' on a line indicates the start of a comment that
16335 extends to the end of the current line.
16337 If a `#' appears as the first character of a line then the whole
16338 line is treated as a comment, but in this case the line could also be a
16339 logical line number directive (*note Comments::) or a preprocessor
16340 control command (*note Preprocessing::).
16342 If the assembler has been configured for the ppc-*-solaris* target
16343 then the `!' character also acts as a line comment character. This can
16344 be disabled via the `-mno-solaris' command line option.
16346 The `;' character can be used to separate statements on the same
16350 File: as.info, Node: RL78-Dependent, Next: RX-Dependent, Prev: PPC-Dependent, Up: Machine Dependencies
16352 9.36 RL78 Dependent Features
16353 ============================
16357 * RL78-Opts:: RL78 Assembler Command Line Options
16358 * RL78-Modifiers:: Symbolic Operand Modifiers
16359 * RL78-Directives:: Assembler Directives
16360 * RL78-Syntax:: Syntax
16363 File: as.info, Node: RL78-Opts, Next: RL78-Modifiers, Up: RL78-Dependent
16365 9.36.1 RL78 Options
16366 -------------------
16369 Enable support for link-time relaxation.
16372 Mark the generated binary as targeting the G10 variant of the RL78
16376 Mark the generated binary as one that uses 32-bits to hold the
16377 `double' floating point type. This is the default.
16380 Mark the generated binary as one that uses 64-bits to hold the
16381 `double' floating point type.
16385 File: as.info, Node: RL78-Modifiers, Next: RL78-Directives, Prev: RL78-Opts, Up: RL78-Dependent
16387 9.36.2 Symbolic Operand Modifiers
16388 ---------------------------------
16390 The RL78 has three modifiers that adjust the relocations used by the
16394 When loading a 20-bit (or wider) address into registers, this
16395 modifier selects the 16 least significant bits.
16397 movw ax,#%lo16(_sym)
16400 When loading a 20-bit (or wider) address into registers, this
16401 modifier selects the 16 most significant bits.
16403 movw ax,#%hi16(_sym)
16406 When loading a 20-bit (or wider) address into registers, this
16407 modifier selects the 8 bits that would go into CS or ES (i.e. bits
16410 mov es, #%hi8(_sym)
16414 File: as.info, Node: RL78-Directives, Next: RL78-Syntax, Prev: RL78-Modifiers, Up: RL78-Dependent
16416 9.36.3 Assembler Directives
16417 ---------------------------
16419 In addition to the common directives, the RL78 adds these:
16422 Output a constant in "double" format, which is either a 32-bit or
16423 a 64-bit floating point value, depending upon the setting of the
16424 `-m32bit-doubles'|`-m64bit-doubles' command line option.
16427 Select the BSS section.
16430 Output a constant value in a three byte format.
16434 Output a constant value in a four byte format.
16438 File: as.info, Node: RL78-Syntax, Prev: RL78-Directives, Up: RL78-Dependent
16440 9.36.4 Syntax for the RL78
16441 --------------------------
16445 * RL78-Chars:: Special Characters
16448 File: as.info, Node: RL78-Chars, Up: RL78-Syntax
16450 9.36.4.1 Special Characters
16451 ...........................
16453 The presence of a `;' appearing anywhere on a line indicates the start
16454 of a comment that extends to the end of that line.
16456 If a `#' appears as the first character of a line then the whole
16457 line is treated as a comment, but in this case the line can also be a
16458 logical line number directive (*note Comments::) or a preprocessor
16459 control command (*note Preprocessing::).
16461 The `|' character can be used to separate statements on the same
16465 File: as.info, Node: RX-Dependent, Next: S/390-Dependent, Prev: RL78-Dependent, Up: Machine Dependencies
16467 9.37 RX Dependent Features
16468 ==========================
16472 * RX-Opts:: RX Assembler Command Line Options
16473 * RX-Modifiers:: Symbolic Operand Modifiers
16474 * RX-Directives:: Assembler Directives
16475 * RX-Float:: Floating Point
16476 * RX-Syntax:: Syntax
16479 File: as.info, Node: RX-Opts, Next: RX-Modifiers, Up: RX-Dependent
16484 The Renesas RX port of `as' has a few target specfic command line
16488 This option controls the ABI and indicates to use a 32-bit float
16489 ABI. It has no effect on the assembled instructions, but it does
16490 influence the behaviour of the `.double' pseudo-op. This is the
16494 This option controls the ABI and indicates to use a 64-bit float
16495 ABI. It has no effect on the assembled instructions, but it does
16496 influence the behaviour of the `.double' pseudo-op.
16499 This option controls the ABI and indicates to use a big-endian data
16500 ABI. It has no effect on the assembled instructions, but it does
16501 influence the behaviour of the `.short', `.hword', `.int',
16502 `.word', `.long', `.quad' and `.octa' pseudo-ops.
16505 This option controls the ABI and indicates to use a little-endian
16506 data ABI. It has no effect on the assembled instructions, but it
16507 does influence the behaviour of the `.short', `.hword', `.int',
16508 `.word', `.long', `.quad' and `.octa' pseudo-ops. This is the
16511 `-muse-conventional-section-names'
16512 This option controls the default names given to the code (.text),
16513 initialised data (.data) and uninitialised data sections (.bss).
16515 `-muse-renesas-section-names'
16516 This option controls the default names given to the code (.P),
16517 initialised data (.D_1) and uninitialised data sections (.B_1).
16518 This is the default.
16520 `-msmall-data-limit'
16521 This option tells the assembler that the small data limit feature
16522 of the RX port of GCC is being used. This results in the assembler
16523 generating an undefined reference to a symbol called `__gp' for
16524 use by the relocations that are needed to support the small data
16525 limit feature. This option is not enabled by default as it would
16526 otherwise pollute the symbol table.
16529 This option tells the assembler that the position independent data
16530 of the RX port of GCC is being used. This results in the assembler
16531 generating an undefined reference to a symbol called `__pid_base',
16532 and also setting the RX_PID flag bit in the e_flags field of the
16533 ELF header of the object file.
16535 `-mint-register=NUM'
16536 This option tells the assembler how many registers have been
16537 reserved for use by interrupt handlers. This is needed in order
16538 to compute the correct values for the `%gpreg' and `%pidreg' meta
16542 This option tells the assembler that the old GCC ABI is being used
16543 by the assembled code. With this version of the ABI function
16544 arguments that are passed on the stack are aligned to a 32-bit
16548 This option tells the assembler that the official RX ABI is being
16549 used by the assembled code. With this version of the ABI function
16550 arguments that are passed on the stack are aligned to their natural
16551 alignments. This option is the default.
16554 This option tells the assembler the target CPU type. Currently the
16555 `rx200', `rx600' and `rx610' are recognised as valid cpu names.
16556 Attempting to assemble an instruction not supported by the
16557 indicated cpu type will result in an error message being generated.
16561 File: as.info, Node: RX-Modifiers, Next: RX-Directives, Prev: RX-Opts, Up: RX-Dependent
16563 9.37.2 Symbolic Operand Modifiers
16564 ---------------------------------
16566 The assembler supports one modifier when using symbol addresses in RX
16567 instruction operands. The general syntax is the following:
16571 The modifier returns the offset from the __GP symbol to the
16572 specified symbol as a 16-bit value. The intent is that this offset
16573 should be used in a register+offset move instruction when generating
16574 references to small data. Ie, like this:
16576 mov.W %gp(_foo)[%gpreg], r1
16578 The assembler also supports two meta register names which can be used
16579 to refer to registers whose values may not be known to the programmer.
16580 These meta register names are:
16583 The small data address register.
16586 The PID base address register.
16589 Both registers normally have the value r13, but this can change if
16590 some registers have been reserved for use by interrupt handlers or if
16591 both the small data limit and position independent data features are
16592 being used at the same time.
16595 File: as.info, Node: RX-Directives, Next: RX-Float, Prev: RX-Modifiers, Up: RX-Dependent
16597 9.37.3 Assembler Directives
16598 ---------------------------
16600 The RX version of `as' has the following specific assembler directives:
16603 Inserts a 3-byte value into the output file at the current
16607 If the next opcode following this directive spans a fetch line
16608 boundary (8 byte boundary), the opcode is aligned to that boundary.
16609 If the next opcode does not span a fetch line, this directive has
16610 no effect. Note that one or more labels may be between this
16611 directive and the opcode; those labels are aligned as well. Any
16612 inserted bytes due to alignment will form a NOP opcode.
16616 File: as.info, Node: RX-Float, Next: RX-Syntax, Prev: RX-Directives, Up: RX-Dependent
16618 9.37.4 Floating Point
16619 ---------------------
16621 The floating point formats generated by directives are these.
16624 `Single' precision (32-bit) floating point constants.
16627 If the `-m64bit-doubles' command line option has been specified
16628 then then `double' directive generates `double' precision (64-bit)
16629 floating point constants, otherwise it generates `single'
16630 precision (32-bit) floating point constants. To force the
16631 generation of 64-bit floating point constants used the `dc.d'
16636 File: as.info, Node: RX-Syntax, Prev: RX-Float, Up: RX-Dependent
16638 9.37.5 Syntax for the RX
16639 ------------------------
16643 * RX-Chars:: Special Characters
16646 File: as.info, Node: RX-Chars, Up: RX-Syntax
16648 9.37.5.1 Special Characters
16649 ...........................
16651 The presence of a `;' appearing anywhere on a line indicates the start
16652 of a comment that extends to the end of that line.
16654 If a `#' appears as the first character of a line then the whole
16655 line is treated as a comment, but in this case the line can also be a
16656 logical line number directive (*note Comments::) or a preprocessor
16657 control command (*note Preprocessing::).
16659 The `!' character can be used to separate statements on the same
16663 File: as.info, Node: S/390-Dependent, Next: SCORE-Dependent, Prev: RX-Dependent, Up: Machine Dependencies
16665 9.38 IBM S/390 Dependent Features
16666 =================================
16668 The s390 version of `as' supports two architectures modes and seven
16669 chip levels. The architecture modes are the Enterprise System
16670 Architecture (ESA) and the newer z/Architecture mode. The chip levels
16671 are g5, g6, z900, z990, z9-109, z9-ec, z10, z196, and zEC12.
16675 * s390 Options:: Command-line Options.
16676 * s390 Characters:: Special Characters.
16677 * s390 Syntax:: Assembler Instruction syntax.
16678 * s390 Directives:: Assembler Directives.
16679 * s390 Floating Point:: Floating Point.
16682 File: as.info, Node: s390 Options, Next: s390 Characters, Up: S/390-Dependent
16687 The following table lists all available s390 specific options:
16690 Select 31- or 64-bit ABI implying a word size of 32- or 64-bit.
16692 These options are only available with the ELF object file format,
16693 and require that the necessary BFD support has been included (on a
16694 31-bit platform you must add -enable-64-bit-bfd on the call to the
16695 configure script to enable 64-bit usage and use s390x as target
16699 Select the architecture mode, either the Enterprise System
16700 Architecture (esa) mode or the z/Architecture mode (zarch).
16702 The 64-bit instructions are only available with the z/Architecture
16703 mode. The combination of `-m64' and `-mesa' results in a warning
16707 This option specifies the target processor. The following
16708 processor names are recognized: `g5', `g6', `z900', `z990',
16709 `z9-109', `z9-ec', `z10' and `z196'. Assembling an instruction
16710 that is not supported on the target processor results in an error
16711 message. Do not specify `g5' or `g6' with `-mzarch'.
16714 Allow symbolic names for registers.
16717 Do not allow symbolic names for registers.
16720 Warn whenever the operand for a base or index register has been
16721 specified but evaluates to zero. This can indicate the misuse of
16722 general purpose register 0 as an address register.
16726 File: as.info, Node: s390 Characters, Next: s390 Syntax, Prev: s390 Options, Up: S/390-Dependent
16728 9.38.2 Special Characters
16729 -------------------------
16731 `#' is the line comment character.
16733 If a `#' appears as the first character of a line then the whole
16734 line is treated as a comment, but in this case the line could also be a
16735 logical line number directive (*note Comments::) or a preprocessor
16736 control command (*note Preprocessing::).
16738 The `;' character can be used instead of a newline to separate
16742 File: as.info, Node: s390 Syntax, Next: s390 Directives, Prev: s390 Characters, Up: S/390-Dependent
16744 9.38.3 Instruction syntax
16745 -------------------------
16747 The assembler syntax closely follows the syntax outlined in Enterprise
16748 Systems Architecture/390 Principles of Operation (SA22-7201) and the
16749 z/Architecture Principles of Operation (SA22-7832).
16751 Each instruction has two major parts, the instruction mnemonic and
16752 the instruction operands. The instruction format varies.
16756 * s390 Register:: Register Naming
16757 * s390 Mnemonics:: Instruction Mnemonics
16758 * s390 Operands:: Instruction Operands
16759 * s390 Formats:: Instruction Formats
16760 * s390 Aliases:: Instruction Aliases
16761 * s390 Operand Modifier:: Instruction Operand Modifier
16762 * s390 Instruction Marker:: Instruction Marker
16763 * s390 Literal Pool Entries:: Literal Pool Entries
16766 File: as.info, Node: s390 Register, Next: s390 Mnemonics, Up: s390 Syntax
16768 9.38.3.1 Register naming
16769 ........................
16771 The `as' recognizes a number of predefined symbols for the various
16772 processor registers. A register specification in one of the instruction
16773 formats is an unsigned integer between 0 and 15. The specific
16774 instruction and the position of the register in the instruction format
16775 denotes the type of the register. The register symbols are prefixed with
16778 %rN the 16 general purpose registers, 0 <= N <= 15
16779 %fN the 16 floating point registers, 0 <= N <= 15
16780 %aN the 16 access registers, 0 <= N <= 15
16781 %cN the 16 control registers, 0 <= N <= 15
16782 %lit an alias for the general purpose register %r13
16783 %sp an alias for the general purpose register %r15
16786 File: as.info, Node: s390 Mnemonics, Next: s390 Operands, Prev: s390 Register, Up: s390 Syntax
16788 9.38.3.2 Instruction Mnemonics
16789 ..............................
16791 All instructions documented in the Principles of Operation are supported
16792 with the mnemonic and order of operands as described. The instruction
16793 mnemonic identifies the instruction format (*Note s390 Formats::) and
16794 the specific operation code for the instruction. For example, the `lr'
16795 mnemonic denotes the instruction format `RR' with the operation code
16798 The definition of the various mnemonics follows a scheme, where the
16799 first character usually hint at the type of the instruction:
16801 a add instruction, for example `al' for add logical 32-bit
16802 b branch instruction, for example `bc' for branch on condition
16803 c compare or convert instruction, for example `cr' for compare
16805 d divide instruction, for example `dlr' devide logical register
16807 i insert instruction, for example `ic' insert character
16808 l load instruction, for example `ltr' load and test register
16809 mv move instruction, for example `mvc' move character
16810 m multiply instruction, for example `mh' multiply halfword
16811 n and instruction, for example `ni' and immediate
16812 o or instruction, for example `oc' or character
16813 sla, sll shift left single instruction
16814 sra, srl shift right single instruction
16815 st store instruction, for example `stm' store multiple
16816 s subtract instruction, for example `slr' subtract
16818 t test or translate instruction, of example `tm' test under mask
16819 x exclusive or instruction, for example `xc' exclusive or
16822 Certain characters at the end of the mnemonic may describe a property
16823 of the instruction:
16825 c the instruction uses a 8-bit character operand
16826 f the instruction extends a 32-bit operand to 64 bit
16827 g the operands are treated as 64-bit values
16828 h the operand uses a 16-bit halfword operand
16829 i the instruction uses an immediate operand
16830 l the instruction uses unsigned, logical operands
16831 m the instruction uses a mask or operates on multiple values
16832 r if r is the last character, the instruction operates on registers
16833 y the instruction uses 20-bit displacements
16835 There are many exceptions to the scheme outlined in the above lists,
16836 in particular for the priviledged instructions. For non-priviledged
16837 instruction it works quite well, for example the instruction `clgfr' c:
16838 compare instruction, l: unsigned operands, g: 64-bit operands, f: 32-
16839 to 64-bit extension, r: register operands. The instruction compares an
16840 64-bit value in a register with the zero extended 32-bit value from a
16841 second register. For a complete list of all mnemonics see appendix B
16842 in the Principles of Operation.
16845 File: as.info, Node: s390 Operands, Next: s390 Formats, Prev: s390 Mnemonics, Up: s390 Syntax
16847 9.38.3.3 Instruction Operands
16848 .............................
16850 Instruction operands can be grouped into three classes, operands located
16851 in registers, immediate operands, and operands in storage.
16853 A register operand can be located in general, floating-point, access,
16854 or control register. The register is identified by a four-bit field.
16855 The field containing the register operand is called the R field.
16857 Immediate operands are contained within the instruction and can have
16858 8, 16 or 32 bits. The field containing the immediate operand is called
16859 the I field. Dependent on the instruction the I field is either signed
16862 A storage operand consists of an address and a length. The address
16863 of a storage operands can be specified in any of these ways:
16865 * The content of a single general R
16867 * The sum of the content of a general register called the base
16868 register B plus the content of a displacement field D
16870 * The sum of the contents of two general registers called the index
16871 register X and the base register B plus the content of a
16874 * The sum of the current instruction address and a 32-bit signed
16875 immediate field multiplied by two.
16877 The length of a storage operand can be:
16879 * Implied by the instruction
16881 * Specified by a bitmask
16883 * Specified by a four-bit or eight-bit length field L
16885 * Specified by the content of a general register
16887 The notation for storage operand addresses formed from multiple
16888 fields is as follows:
16891 the address for operand number n is formed from the content of
16892 general register Bn called the base register and the displacement
16896 the address for operand number n is formed from the content of
16897 general register Xn called the index register, general register Bn
16898 called the base register and the displacement field Dn.
16901 the address for operand number n is formed from the content of
16902 general regiser Bn called the base register and the displacement
16903 field Dn. The length of the operand n is specified by the field
16906 The base registers Bn and the index registers Xn of a storage
16907 operand can be skipped. If Bn and Xn are skipped, a zero will be stored
16908 to the operand field. The notation changes as follows:
16910 full notation short notation
16911 ------------------------------------------
16918 File: as.info, Node: s390 Formats, Next: s390 Aliases, Prev: s390 Operands, Up: s390 Syntax
16920 9.38.3.4 Instruction Formats
16921 ............................
16923 The Principles of Operation manuals lists 26 instruction formats where
16924 some of the formats have multiple variants. For the `.insn' pseudo
16925 directive the assembler recognizes some of the formats. Typically, the
16926 most general variant of the instruction format is used by the `.insn'
16929 The following table lists the abbreviations used in the table of
16930 instruction formats:
16932 OpCode / OpCd Part of the op code.
16933 Bx Base register number for operand x.
16934 Dx Displacement for operand x.
16935 DLx Displacement lower 12 bits for operand x.
16936 DHx Displacement higher 8-bits for operand x.
16937 Rx Register number for operand x.
16938 Xx Index register number for operand x.
16939 Ix Signed immediate for operand x.
16940 Ux Unsigned immediate for operand x.
16942 An instruction is two, four, or six bytes in length and must be
16943 aligned on a 2 byte boundary. The first two bits of the instruction
16944 specify the length of the instruction, 00 indicates a two byte
16945 instruction, 01 and 10 indicates a four byte instruction, and 11
16946 indicates a six byte instruction.
16948 The following table lists the s390 instruction formats that are
16949 available with the `.insn' pseudo directive:
16958 `RI format: <insn> R1,I2'
16960 +--------+----+----+------------------+
16961 | OpCode | R1 |OpCd| I2 |
16962 +--------+----+----+------------------+
16965 `RIE format: <insn> R1,R3,I2'
16967 +--------+----+----+------------------+--------+--------+
16968 | OpCode | R1 | R3 | I2 |////////| OpCode |
16969 +--------+----+----+------------------+--------+--------+
16972 `RIL format: <insn> R1,I2'
16974 +--------+----+----+------------------------------------+
16975 | OpCode | R1 |OpCd| I2 |
16976 +--------+----+----+------------------------------------+
16979 `RILU format: <insn> R1,U2'
16981 +--------+----+----+------------------------------------+
16982 | OpCode | R1 |OpCd| U2 |
16983 +--------+----+----+------------------------------------+
16986 `RIS format: <insn> R1,I2,M3,D4(B4)'
16988 +--------+----+----+----+-------------+--------+--------+
16989 | OpCode | R1 | M3 | B4 | D4 | I2 | Opcode |
16990 +--------+----+----+----+-------------+--------+--------+
16991 0 8 12 16 20 32 36 47
16993 `RR format: <insn> R1,R2'
16995 +--------+----+----+
16996 | OpCode | R1 | R2 |
16997 +--------+----+----+
17000 `RRE format: <insn> R1,R2'
17002 +------------------+--------+----+----+
17003 | OpCode |////////| R1 | R2 |
17004 +------------------+--------+----+----+
17007 `RRF format: <insn> R1,R2,R3,M4'
17009 +------------------+----+----+----+----+
17010 | OpCode | R3 | M4 | R1 | R2 |
17011 +------------------+----+----+----+----+
17014 `RRS format: <insn> R1,R2,M3,D4(B4)'
17016 +--------+----+----+----+-------------+----+----+--------+
17017 | OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode |
17018 +--------+----+----+----+-------------+----+----+--------+
17019 0 8 12 16 20 32 36 40 47
17021 `RS format: <insn> R1,R3,D2(B2)'
17023 +--------+----+----+----+-------------+
17024 | OpCode | R1 | R3 | B2 | D2 |
17025 +--------+----+----+----+-------------+
17028 `RSE format: <insn> R1,R3,D2(B2)'
17030 +--------+----+----+----+-------------+--------+--------+
17031 | OpCode | R1 | R3 | B2 | D2 |////////| OpCode |
17032 +--------+----+----+----+-------------+--------+--------+
17033 0 8 12 16 20 32 40 47
17035 `RSI format: <insn> R1,R3,I2'
17037 +--------+----+----+------------------------------------+
17038 | OpCode | R1 | R3 | I2 |
17039 +--------+----+----+------------------------------------+
17042 `RSY format: <insn> R1,R3,D2(B2)'
17044 +--------+----+----+----+-------------+--------+--------+
17045 | OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode |
17046 +--------+----+----+----+-------------+--------+--------+
17047 0 8 12 16 20 32 40 47
17049 `RX format: <insn> R1,D2(X2,B2)'
17051 +--------+----+----+----+-------------+
17052 | OpCode | R1 | X2 | B2 | D2 |
17053 +--------+----+----+----+-------------+
17056 `RXE format: <insn> R1,D2(X2,B2)'
17058 +--------+----+----+----+-------------+--------+--------+
17059 | OpCode | R1 | X2 | B2 | D2 |////////| OpCode |
17060 +--------+----+----+----+-------------+--------+--------+
17061 0 8 12 16 20 32 40 47
17063 `RXF format: <insn> R1,R3,D2(X2,B2)'
17065 +--------+----+----+----+-------------+----+---+--------+
17066 | OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode |
17067 +--------+----+----+----+-------------+----+---+--------+
17068 0 8 12 16 20 32 36 40 47
17070 `RXY format: <insn> R1,D2(X2,B2)'
17072 +--------+----+----+----+-------------+--------+--------+
17073 | OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode |
17074 +--------+----+----+----+-------------+--------+--------+
17075 0 8 12 16 20 32 36 40 47
17077 `S format: <insn> D2(B2)'
17079 +------------------+----+-------------+
17080 | OpCode | B2 | D2 |
17081 +------------------+----+-------------+
17084 `SI format: <insn> D1(B1),I2'
17086 +--------+---------+----+-------------+
17087 | OpCode | I2 | B1 | D1 |
17088 +--------+---------+----+-------------+
17091 `SIY format: <insn> D1(B1),U2'
17093 +--------+---------+----+-------------+--------+--------+
17094 | OpCode | I2 | B1 | DL1 | DH1 | OpCode |
17095 +--------+---------+----+-------------+--------+--------+
17096 0 8 16 20 32 36 40 47
17098 `SIL format: <insn> D1(B1),I2'
17100 +------------------+----+-------------+-----------------+
17101 | OpCode | B1 | D1 | I2 |
17102 +------------------+----+-------------+-----------------+
17105 `SS format: <insn> D1(R1,B1),D2(B3),R3'
17107 +--------+----+----+----+-------------+----+------------+
17108 | OpCode | R1 | R3 | B1 | D1 | B2 | D2 |
17109 +--------+----+----+----+-------------+----+------------+
17110 0 8 12 16 20 32 36 47
17112 `SSE format: <insn> D1(B1),D2(B2)'
17114 +------------------+----+-------------+----+------------+
17115 | OpCode | B1 | D1 | B2 | D2 |
17116 +------------------+----+-------------+----+------------+
17117 0 8 12 16 20 32 36 47
17119 `SSF format: <insn> D1(B1),D2(B2),R3'
17121 +--------+----+----+----+-------------+----+------------+
17122 | OpCode | R3 |OpCd| B1 | D1 | B2 | D2 |
17123 +--------+----+----+----+-------------+----+------------+
17124 0 8 12 16 20 32 36 47
17127 For the complete list of all instruction format variants see the
17128 Principles of Operation manuals.
17131 File: as.info, Node: s390 Aliases, Next: s390 Operand Modifier, Prev: s390 Formats, Up: s390 Syntax
17133 9.38.3.5 Instruction Aliases
17134 ............................
17136 A specific bit pattern can have multiple mnemonics, for example the bit
17137 pattern `0xa7000000' has the mnemonics `tmh' and `tmlh'. In addition,
17138 there are a number of mnemonics recognized by `as' that are not present
17139 in the Principles of Operation. These are the short forms of the
17140 branch instructions, where the condition code mask operand is encoded
17141 in the mnemonic. This is relevant for the branch instructions, the
17142 compare and branch instructions, and the compare and trap instructions.
17144 For the branch instructions there are 20 condition code strings that
17145 can be used as part of the mnemonic in place of a mask operand in the
17146 instruction format:
17148 instruction short form
17149 ------------------------------------------
17151 bc M1,D2(X2,B2) b<m> D2(X2,B2)
17153 brcl M1,I2 jg<m> I2
17155 In the mnemonic for a branch instruction the condition code string
17156 <m> can be any of the following:
17158 o jump on overflow / if ones
17161 nle jump on not low or equal
17164 nhe jump on not high or equal
17165 lh jump on low or high
17166 ne jump on A not equal B
17167 nz jump on not zero / if not zeros
17168 e jump on A equal B
17169 z jump on zero / if zeroes
17170 nlh jump on not low or high
17171 he jump on high or equal
17172 nl jump on A not low
17173 nm jump on not minus / if not mixed
17174 le jump on low or equal
17175 nh jump on A not high
17176 np jump on not plus
17177 no jump on not overflow / if not ones
17179 For the compare and branch, and compare and trap instructions there
17180 are 12 condition code strings that can be used as part of the mnemonic
17181 in place of a mask operand in the instruction format:
17183 instruction short form
17184 --------------------------------------------------------
17185 crb R1,R2,M3,D4(B4) crb<m> R1,R2,D4(B4)
17186 cgrb R1,R2,M3,D4(B4) cgrb<m> R1,R2,D4(B4)
17187 crj R1,R2,M3,I4 crj<m> R1,R2,I4
17188 cgrj R1,R2,M3,I4 cgrj<m> R1,R2,I4
17189 cib R1,I2,M3,D4(B4) cib<m> R1,I2,D4(B4)
17190 cgib R1,I2,M3,D4(B4) cgib<m> R1,I2,D4(B4)
17191 cij R1,I2,M3,I4 cij<m> R1,I2,I4
17192 cgij R1,I2,M3,I4 cgij<m> R1,I2,I4
17193 crt R1,R2,M3 crt<m> R1,R2
17194 cgrt R1,R2,M3 cgrt<m> R1,R2
17195 cit R1,I2,M3 cit<m> R1,I2
17196 cgit R1,I2,M3 cgit<m> R1,I2
17197 clrb R1,R2,M3,D4(B4) clrb<m> R1,R2,D4(B4)
17198 clgrb R1,R2,M3,D4(B4) clgrb<m> R1,R2,D4(B4)
17199 clrj R1,R2,M3,I4 clrj<m> R1,R2,I4
17200 clgrj R1,R2,M3,I4 clgrj<m> R1,R2,I4
17201 clib R1,I2,M3,D4(B4) clib<m> R1,I2,D4(B4)
17202 clgib R1,I2,M3,D4(B4) clgib<m> R1,I2,D4(B4)
17203 clij R1,I2,M3,I4 clij<m> R1,I2,I4
17204 clgij R1,I2,M3,I4 clgij<m> R1,I2,I4
17205 clrt R1,R2,M3 clrt<m> R1,R2
17206 clgrt R1,R2,M3 clgrt<m> R1,R2
17207 clfit R1,I2,M3 clfit<m> R1,I2
17208 clgit R1,I2,M3 clgit<m> R1,I2
17210 In the mnemonic for a compare and branch and compare and trap
17211 instruction the condition code string <m> can be any of the following:
17214 nle jump on not low or equal
17216 nhe jump on not high or equal
17217 ne jump on A not equal B
17218 lh jump on low or high
17219 e jump on A equal B
17220 nlh jump on not low or high
17221 nl jump on A not low
17222 he jump on high or equal
17223 nh jump on A not high
17224 le jump on low or equal
17227 File: as.info, Node: s390 Operand Modifier, Next: s390 Instruction Marker, Prev: s390 Aliases, Up: s390 Syntax
17229 9.38.3.6 Instruction Operand Modifier
17230 .....................................
17232 If a symbol modifier is attached to a symbol in an expression for an
17233 instruction operand field, the symbol term is replaced with a reference
17234 to an object in the global offset table (GOT) or the procedure linkage
17235 table (PLT). The following expressions are allowed: `symbol@modifier +
17236 constant', `symbol@modifier + label + constant', and `symbol@modifier -
17237 label + constant'. The term `symbol' is the symbol that will be
17238 entered into the GOT or PLT, `label' is a local label, and `constant'
17239 is an arbitrary expression that the assembler can evaluate to a
17242 The term `(symbol + constant1)@modifier +/- label + constant2' is
17243 also accepted but a warning message is printed and the term is
17244 converted to `symbol@modifier +/- label + constant1 + constant2'.
17248 The @got modifier can be used for displacement fields, 16-bit
17249 immediate fields and 32-bit pc-relative immediate fields. The
17250 @got12 modifier is synonym to @got. The symbol is added to the
17251 GOT. For displacement fields and 16-bit immediate fields the
17252 symbol term is replaced with the offset from the start of the GOT
17253 to the GOT slot for the symbol. For a 32-bit pc-relative field
17254 the pc-relative offset to the GOT slot from the current
17255 instruction address is used.
17258 The @gotent modifier can be used for 32-bit pc-relative immediate
17259 fields. The symbol is added to the GOT and the symbol term is
17260 replaced with the pc-relative offset from the current instruction
17261 to the GOT slot for the symbol.
17264 The @gotoff modifier can be used for 16-bit immediate fields. The
17265 symbol term is replaced with the offset from the start of the GOT
17266 to the address of the symbol.
17269 The @gotplt modifier can be used for displacement fields, 16-bit
17270 immediate fields, and 32-bit pc-relative immediate fields. A
17271 procedure linkage table entry is generated for the symbol and a
17272 jump slot for the symbol is added to the GOT. For displacement
17273 fields and 16-bit immediate fields the symbol term is replaced
17274 with the offset from the start of the GOT to the jump slot for the
17275 symbol. For a 32-bit pc-relative field the pc-relative offset to
17276 the jump slot from the current instruction address is used.
17279 The @plt modifier can be used for 16-bit and 32-bit pc-relative
17280 immediate fields. A procedure linkage table entry is generated for
17281 the symbol. The symbol term is replaced with the relative offset
17282 from the current instruction to the PLT entry for the symbol.
17285 The @pltoff modifier can be used for 16-bit immediate fields. The
17286 symbol term is replaced with the offset from the start of the PLT
17287 to the address of the symbol.
17290 The @gotntpoff modifier can be used for displacement fields. The
17291 symbol is added to the static TLS block and the negated offset to
17292 the symbol in the static TLS block is added to the GOT. The symbol
17293 term is replaced with the offset to the GOT slot from the start of
17297 The @indntpoff modifier can be used for 32-bit pc-relative
17298 immediate fields. The symbol is added to the static TLS block and
17299 the negated offset to the symbol in the static TLS block is added
17300 to the GOT. The symbol term is replaced with the pc-relative
17301 offset to the GOT slot from the current instruction address.
17303 For more information about the thread local storage modifiers
17304 `gotntpoff' and `indntpoff' see the ELF extension documentation `ELF
17305 Handling For Thread-Local Storage'.
17308 File: as.info, Node: s390 Instruction Marker, Next: s390 Literal Pool Entries, Prev: s390 Operand Modifier, Up: s390 Syntax
17310 9.38.3.7 Instruction Marker
17311 ...........................
17313 The thread local storage instruction markers are used by the linker to
17314 perform code optimization.
17317 The :tls_load marker is used to flag the load instruction in the
17318 initial exec TLS model that retrieves the offset from the thread
17319 pointer to a thread local storage variable from the GOT.
17322 The :tls_gdcall marker is used to flag the branch-and-save
17323 instruction to the __tls_get_offset function in the global dynamic
17327 The :tls_ldcall marker is used to flag the branch-and-save
17328 instruction to the __tls_get_offset function in the local dynamic
17331 For more information about the thread local storage instruction
17332 marker and the linker optimizations see the ELF extension documentation
17333 `ELF Handling For Thread-Local Storage'.
17336 File: as.info, Node: s390 Literal Pool Entries, Prev: s390 Instruction Marker, Up: s390 Syntax
17338 9.38.3.8 Literal Pool Entries
17339 .............................
17341 A literal pool is a collection of values. To access the values a pointer
17342 to the literal pool is loaded to a register, the literal pool register.
17343 Usually, register %r13 is used as the literal pool register (*Note s390
17344 Register::). Literal pool entries are created by adding the suffix
17345 :lit1, :lit2, :lit4, or :lit8 to the end of an expression for an
17346 instruction operand. The expression is added to the literal pool and the
17347 operand is replaced with the offset to the literal in the literal pool.
17350 The literal pool entry is created as an 8-bit value. An operand
17351 modifier must not be used for the original expression.
17354 The literal pool entry is created as a 16 bit value. The operand
17355 modifier @got may be used in the original expression. The term
17356 `x@got:lit2' will put the got offset for the global symbol x to
17357 the literal pool as 16 bit value.
17360 The literal pool entry is created as a 32-bit value. The operand
17361 modifier @got and @plt may be used in the original expression. The
17362 term `x@got:lit4' will put the got offset for the global symbol x
17363 to the literal pool as a 32-bit value. The term `x@plt:lit4' will
17364 put the plt offset for the global symbol x to the literal pool as
17368 The literal pool entry is created as a 64-bit value. The operand
17369 modifier @got and @plt may be used in the original expression. The
17370 term `x@got:lit8' will put the got offset for the global symbol x
17371 to the literal pool as a 64-bit value. The term `x@plt:lit8' will
17372 put the plt offset for the global symbol x to the literal pool as
17375 The assembler directive `.ltorg' is used to emit all literal pool
17376 entries to the current position.
17379 File: as.info, Node: s390 Directives, Next: s390 Floating Point, Prev: s390 Syntax, Up: S/390-Dependent
17381 9.38.4 Assembler Directives
17382 ---------------------------
17384 `as' for s390 supports all of the standard ELF assembler directives as
17385 outlined in the main part of this document. Some directives have been
17386 extended and there are some additional directives, which are only
17387 available for the s390 `as'.
17390 This directive permits the numeric representation of an
17391 instructions and makes the assembler insert the operands according
17392 to one of the instructions formats for `.insn' (*Note s390
17393 Formats::). For example, the instruction `l %r1,24(%r15)' could
17394 be written as `.insn rx,0x58000000,%r1,24(%r15)'.
17399 This directive places one or more 16-bit (.short), 32-bit (.long),
17400 or 64-bit (.quad) values into the current section. If an ELF or
17401 TLS modifier is used only the following expressions are allowed:
17402 `symbol@modifier + constant', `symbol@modifier + label +
17403 constant', and `symbol@modifier - label + constant'. The
17404 following modifiers are available:
17407 The @got modifier can be used for .short, .long and .quad.
17408 The @got12 modifier is synonym to @got. The symbol is added
17409 to the GOT. The symbol term is replaced with offset from the
17410 start of the GOT to the GOT slot for the symbol.
17413 The @gotoff modifier can be used for .short, .long and .quad.
17414 The symbol term is replaced with the offset from the start of
17415 the GOT to the address of the symbol.
17418 The @gotplt modifier can be used for .long and .quad. A
17419 procedure linkage table entry is generated for the symbol and
17420 a jump slot for the symbol is added to the GOT. The symbol
17421 term is replaced with the offset from the start of the GOT to
17422 the jump slot for the symbol.
17425 The @plt modifier can be used for .long and .quad. A
17426 procedure linkage table entry us generated for the symbol.
17427 The symbol term is replaced with the address of the PLT entry
17431 The @pltoff modifier can be used for .short, .long and .quad.
17432 The symbol term is replaced with the offset from the start of
17433 the PLT to the address of the symbol.
17437 The @tlsgd and @tlsldm modifier can be used for .long and
17438 .quad. A tls_index structure for the symbol is added to the
17439 GOT. The symbol term is replaced with the offset from the
17440 start of the GOT to the tls_index structure.
17444 The @gotntpoff and @indntpoff modifier can be used for .long
17445 and .quad. The symbol is added to the static TLS block and
17446 the negated offset to the symbol in the static TLS block is
17447 added to the GOT. For @gotntpoff the symbol term is replaced
17448 with the offset from the start of the GOT to the GOT slot,
17449 for @indntpoff the symbol term is replaced with the address
17453 The @dtpoff modifier can be used for .long and .quad. The
17454 symbol term is replaced with the offset of the symbol
17455 relative to the start of the TLS block it is contained in.
17458 The @ntpoff modifier can be used for .long and .quad. The
17459 symbol term is replaced with the offset of the symbol
17460 relative to the TCB pointer.
17462 For more information about the thread local storage modifiers see
17463 the ELF extension documentation `ELF Handling For Thread-Local
17467 This directive causes the current contents of the literal pool to
17468 be dumped to the current location (*Note s390 Literal Pool
17472 This directive allows you to change the machine for which code is
17473 generated. `string' may be any of the `-march=' selection options
17474 (without the -march=), `push', or `pop'. `.machine push' saves
17475 the currently selected cpu, which may be restored with `.machine
17476 pop'. Be aware that the cpu string has to be put into double
17477 quotes in case it contains characters not appropriate for
17478 identifiers. So you have to write `"z9-109"' instead of just
17481 `.machinemode string'
17482 This directive allows to change the architecture mode for which
17483 code is being generated. `string' may be `esa', `zarch',
17484 `zarch_nohighgprs', `push', or `pop'. `.machinemode
17485 zarch_nohighgprs' can be used to prevent the `highgprs' flag from
17486 being set in the ELF header of the output file. This is useful in
17487 situations where the code is gated with a runtime check which
17488 makes sure that the code is only executed on kernels providing the
17489 `highgprs' feature. `.machinemode push' saves the currently
17490 selected mode, which may be restored with `.machinemode pop'.
17493 File: as.info, Node: s390 Floating Point, Prev: s390 Directives, Up: S/390-Dependent
17495 9.38.5 Floating Point
17496 ---------------------
17498 The assembler recognizes both the IEEE floating-point instruction and
17499 the hexadecimal floating-point instructions. The floating-point
17500 constructors `.float', `.single', and `.double' always emit the IEEE
17501 format. To assemble hexadecimal floating-point constants the `.long'
17502 and `.quad' directives must be used.
17505 File: as.info, Node: SCORE-Dependent, Next: Sparc-Dependent, Prev: S/390-Dependent, Up: Machine Dependencies
17507 9.39 SCORE Dependent Features
17508 =============================
17512 * SCORE-Opts:: Assembler options
17513 * SCORE-Pseudo:: SCORE Assembler Directives
17514 * SCORE-Syntax:: Syntax
17517 File: as.info, Node: SCORE-Opts, Next: SCORE-Pseudo, Up: SCORE-Dependent
17522 The following table lists all available SCORE options.
17525 This option sets the largest size of an object that can be
17526 referenced implicitly with the `gp' register. The default value is
17530 Assemble code for a big-endian cpu
17533 Assemble code for a little-endian cpu
17536 Assemble code for fix data dependency
17539 Assemble code for no warning message for fix data dependency
17542 Assemble code for target is SCORE5
17545 Assemble code for target is SCORE5U
17548 Assemble code for target is SCORE7, this is default setting
17551 Assemble code for target is SCORE3
17554 Assemble code for target is SCORE7, this is default setting
17557 Assemble code for target is SCORE3
17560 Assemble code for no warning message when using temp register r1
17563 Generate code for PIC. This option tells the assembler to generate
17564 score position-independent macro expansions. It also tells the
17565 assembler to mark the output file as PIC.
17568 Assembler will not perform any optimizations
17571 Sunplus release version
17575 File: as.info, Node: SCORE-Pseudo, Next: SCORE-Syntax, Prev: SCORE-Opts, Up: SCORE-Dependent
17577 9.39.2 SCORE Assembler Directives
17578 ---------------------------------
17580 A number of assembler directives are available for SCORE. The
17581 following table is far from complete.
17584 Let the assembler not to generate warnings if the source machine
17585 language instructions happen data dependency.
17588 Let the assembler to insert bubbles (32 bit nop instruction / 16
17589 bit nop! Instruction) if the source machine language instructions
17590 happen data dependency.
17593 Let the assembler to generate warnings if the source machine
17594 language instructions happen data dependency. (Default)
17597 Let the assembler not to generate warnings if the source program
17598 uses r1. allow user to use r1
17601 Let the assembler to generate warnings if the source program uses
17605 Tell the assembler to add subsequent data into the sdata section
17608 Tell the assembler to add subsequent data into the rdata section
17610 `.frame "frame-register", "offset", "return-pc-register"'
17611 Describe a stack frame. "frame-register" is the frame register,
17612 "offset" is the distance from the frame register to the virtual
17613 frame pointer, "return-pc-register" is the return program register.
17614 You must use ".ent" before ".frame" and only one ".frame" can be
17617 `.mask "bitmask", "frameoffset"'
17618 Indicate which of the integer registers are saved in the current
17619 function's stack frame, this is for the debugger to explain the
17623 Set the beginning of the procedure "proc_name". Use this directive
17624 when you want to generate information for the debugger.
17627 Set the end of a procedure. Use this directive to generate
17628 information for the debugger.
17631 Switch the destination of following statements into the bss
17632 section, which is used for data that is uninitialized anywhere.
17636 File: as.info, Node: SCORE-Syntax, Prev: SCORE-Pseudo, Up: SCORE-Dependent
17638 9.39.3 SCORE Syntax
17639 -------------------
17643 * SCORE-Chars:: Special Characters
17646 File: as.info, Node: SCORE-Chars, Up: SCORE-Syntax
17648 9.39.3.1 Special Characters
17649 ...........................
17651 The presence of a `#' appearing anywhere on a line indicates the start
17652 of a comment that extends to the end of that line.
17654 If a `#' appears as the first character of a line then the whole
17655 line is treated as a comment, but in this case the line can also be a
17656 logical line number directive (*note Comments::) or a preprocessor
17657 control command (*note Preprocessing::).
17659 The `;' character can be used to separate statements on the same
17663 File: as.info, Node: SH-Dependent, Next: SH64-Dependent, Prev: NS32K-Dependent, Up: Machine Dependencies
17665 9.40 Renesas / SuperH SH Dependent Features
17666 ===========================================
17670 * SH Options:: Options
17671 * SH Syntax:: Syntax
17672 * SH Floating Point:: Floating Point
17673 * SH Directives:: SH Machine Directives
17674 * SH Opcodes:: Opcodes
17677 File: as.info, Node: SH Options, Next: SH Syntax, Up: SH-Dependent
17682 `as' has following command-line options for the Renesas (formerly
17683 Hitachi) / SuperH SH family.
17686 Generate little endian code.
17689 Generate big endian code.
17692 Alter jump instructions for long displacements.
17695 Align sections to 4 byte boundaries, not 16.
17698 Enable sh-dsp insns, and disable sh3e / sh4 insns.
17701 Disable optimization with section symbol for compatibility with
17704 `--allow-reg-prefix'
17705 Allow '$' as a register name prefix.
17708 Generate an FDPIC object file.
17711 Specify the sh4 or sh4a instruction set.
17714 Enable sh-dsp insns, and disable sh3e / sh4 insns.
17717 Enable sh2e, sh3e, sh4, and sh4a insn sets.
17720 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
17723 Support H'00 style hex constants in addition to 0x00 style.
17727 File: as.info, Node: SH Syntax, Next: SH Floating Point, Prev: SH Options, Up: SH-Dependent
17734 * SH-Chars:: Special Characters
17735 * SH-Regs:: Register Names
17736 * SH-Addressing:: Addressing Modes
17739 File: as.info, Node: SH-Chars, Next: SH-Regs, Up: SH Syntax
17741 9.40.2.1 Special Characters
17742 ...........................
17744 `!' is the line comment character.
17746 You can use `;' instead of a newline to separate statements.
17748 If a `#' appears as the first character of a line then the whole
17749 line is treated as a comment, but in this case the line could also be a
17750 logical line number directive (*note Comments::) or a preprocessor
17751 control command (*note Preprocessing::).
17753 Since `$' has no special meaning, you may use it in symbol names.
17756 File: as.info, Node: SH-Regs, Next: SH-Addressing, Prev: SH-Chars, Up: SH Syntax
17758 9.40.2.2 Register Names
17759 .......................
17761 You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5',
17762 `r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and `r15' to
17763 refer to the SH registers.
17765 The SH also has these control registers:
17768 procedure register (holds return address)
17775 high and low multiply accumulator registers
17781 global base register
17784 vector base register (for interrupt vectors)
17787 File: as.info, Node: SH-Addressing, Prev: SH-Regs, Up: SH Syntax
17789 9.40.2.3 Addressing Modes
17790 .........................
17792 `as' understands the following addressing modes for the SH. `RN' in
17793 the following refers to any of the numbered registers, but _not_ the
17803 Register indirect with pre-decrement
17806 Register indirect with post-increment
17809 Register indirect with displacement
17822 PC relative address (for branch or for addressing memory). The
17823 `as' implementation allows you to use the simpler form ADDR
17824 anywhere a PC relative address is called for; the alternate form
17825 is supported for compatibility with other assemblers.
17831 File: as.info, Node: SH Floating Point, Next: SH Directives, Prev: SH Syntax, Up: SH-Dependent
17833 9.40.3 Floating Point
17834 ---------------------
17836 SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
17837 SH groups can use `.float' directive to generate IEEE floating-point
17840 SH2E and SH3E support single-precision floating point calculations as
17841 well as entirely PCAPI compatible emulation of double-precision
17842 floating point calculations. SH2E and SH3E instructions are a subset of
17843 the floating point calculations conforming to the IEEE754 standard.
17845 In addition to single-precision and double-precision floating-point
17846 operation capability, the on-chip FPU of SH4 has a 128-bit graphic
17847 engine that enables 32-bit floating-point data to be processed 128 bits
17848 at a time. It also supports 4 * 4 array operations and inner product
17849 operations. Also, a superscalar architecture is employed that enables
17850 simultaneous execution of two instructions (including FPU
17851 instructions), providing performance of up to twice that of
17852 conventional architectures at the same frequency.
17855 File: as.info, Node: SH Directives, Next: SH Opcodes, Prev: SH Floating Point, Up: SH-Dependent
17857 9.40.4 SH Machine Directives
17858 ----------------------------
17863 `as' will issue a warning when a misaligned `.word', `.long', or
17864 `.quad' directive is used. You may use `.uaword', `.ualong', or
17865 `.uaquad' to indicate that the value is intentionally misaligned.
17868 File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent
17873 For detailed information on the SH machine instruction set, see
17874 `SH-Microcomputer User's Manual' (Renesas) or `SH-4 32-bit CPU Core
17875 Architecture' (SuperH) and `SuperH (SH) 64-Bit RISC Series' (SuperH).
17877 `as' implements all the standard SH opcodes. No additional
17878 pseudo-instructions are needed on this family. Note, however, that
17879 because `as' supports a simpler form of PC-relative addressing, you may
17880 simply write (for example)
17884 where other assemblers might require an explicit displacement to `bar'
17885 from the program counter:
17889 Here is a summary of SH opcodes:
17892 Rn a numbered register
17893 Rm another numbered register
17894 #imm immediate data
17896 disp8 8-bit displacement
17897 disp12 12-bit displacement
17899 add #imm,Rn lds.l @Rn+,PR
17900 add Rm,Rn mac.w @Rm+,@Rn+
17901 addc Rm,Rn mov #imm,Rn
17902 addv Rm,Rn mov Rm,Rn
17903 and #imm,R0 mov.b Rm,@(R0,Rn)
17904 and Rm,Rn mov.b Rm,@-Rn
17905 and.b #imm,@(R0,GBR) mov.b Rm,@Rn
17906 bf disp8 mov.b @(disp,Rm),R0
17907 bra disp12 mov.b @(disp,GBR),R0
17908 bsr disp12 mov.b @(R0,Rm),Rn
17909 bt disp8 mov.b @Rm+,Rn
17910 clrmac mov.b @Rm,Rn
17911 clrt mov.b R0,@(disp,Rm)
17912 cmp/eq #imm,R0 mov.b R0,@(disp,GBR)
17913 cmp/eq Rm,Rn mov.l Rm,@(disp,Rn)
17914 cmp/ge Rm,Rn mov.l Rm,@(R0,Rn)
17915 cmp/gt Rm,Rn mov.l Rm,@-Rn
17916 cmp/hi Rm,Rn mov.l Rm,@Rn
17917 cmp/hs Rm,Rn mov.l @(disp,Rn),Rm
17918 cmp/pl Rn mov.l @(disp,GBR),R0
17919 cmp/pz Rn mov.l @(disp,PC),Rn
17920 cmp/str Rm,Rn mov.l @(R0,Rm),Rn
17921 div0s Rm,Rn mov.l @Rm+,Rn
17923 div1 Rm,Rn mov.l R0,@(disp,GBR)
17924 exts.b Rm,Rn mov.w Rm,@(R0,Rn)
17925 exts.w Rm,Rn mov.w Rm,@-Rn
17926 extu.b Rm,Rn mov.w Rm,@Rn
17927 extu.w Rm,Rn mov.w @(disp,Rm),R0
17928 jmp @Rn mov.w @(disp,GBR),R0
17929 jsr @Rn mov.w @(disp,PC),Rn
17930 ldc Rn,GBR mov.w @(R0,Rm),Rn
17931 ldc Rn,SR mov.w @Rm+,Rn
17932 ldc Rn,VBR mov.w @Rm,Rn
17933 ldc.l @Rn+,GBR mov.w R0,@(disp,Rm)
17934 ldc.l @Rn+,SR mov.w R0,@(disp,GBR)
17935 ldc.l @Rn+,VBR mova @(disp,PC),R0
17936 lds Rn,MACH movt Rn
17937 lds Rn,MACL muls Rm,Rn
17938 lds Rn,PR mulu Rm,Rn
17939 lds.l @Rn+,MACH neg Rm,Rn
17940 lds.l @Rn+,MACL negc Rm,Rn
17943 not Rm,Rn stc.l GBR,@-Rn
17944 or #imm,R0 stc.l SR,@-Rn
17945 or Rm,Rn stc.l VBR,@-Rn
17946 or.b #imm,@(R0,GBR) sts MACH,Rn
17947 rotcl Rn sts MACL,Rn
17949 rotl Rn sts.l MACH,@-Rn
17950 rotr Rn sts.l MACL,@-Rn
17955 shar Rn swap.b Rm,Rn
17956 shll Rn swap.w Rm,Rn
17957 shll16 Rn tas.b @Rn
17958 shll2 Rn trapa #imm
17959 shll8 Rn tst #imm,R0
17961 shlr16 Rn tst.b #imm,@(R0,GBR)
17962 shlr2 Rn xor #imm,R0
17964 sleep xor.b #imm,@(R0,GBR)
17965 stc GBR,Rn xtrct Rm,Rn
17969 File: as.info, Node: SH64-Dependent, Next: PDP-11-Dependent, Prev: SH-Dependent, Up: Machine Dependencies
17971 9.41 SuperH SH64 Dependent Features
17972 ===================================
17976 * SH64 Options:: Options
17977 * SH64 Syntax:: Syntax
17978 * SH64 Directives:: SH64 Machine Directives
17979 * SH64 Opcodes:: Opcodes
17982 File: as.info, Node: SH64 Options, Next: SH64 Syntax, Up: SH64-Dependent
17988 Specify the sh4 or sh4a instruction set.
17991 Enable sh-dsp insns, and disable sh3e / sh4 insns.
17994 Enable sh2e, sh3e, sh4, and sh4a insn sets.
17997 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
17999 `-isa=shmedia | -isa=shcompact'
18000 Specify the default instruction set. `SHmedia' specifies the
18001 32-bit opcodes, and `SHcompact' specifies the 16-bit opcodes
18002 compatible with previous SH families. The default depends on the
18003 ABI selected; the default for the 64-bit ABI is SHmedia, and the
18004 default for the 32-bit ABI is SHcompact. If neither the ABI nor
18005 the ISA is specified, the default is 32-bit SHcompact.
18007 Note that the `.mode' pseudo-op is not permitted if the ISA is not
18008 specified on the command line.
18010 `-abi=32 | -abi=64'
18011 Specify the default ABI. If the ISA is specified and the ABI is
18012 not, the default ABI depends on the ISA, with SHmedia defaulting
18013 to 64-bit and SHcompact defaulting to 32-bit.
18015 Note that the `.abi' pseudo-op is not permitted if the ABI is not
18016 specified on the command line. When the ABI is specified on the
18017 command line, any `.abi' pseudo-ops in the source must match it.
18019 `-shcompact-const-crange'
18020 Emit code-range descriptors for constants in SHcompact code
18024 Disallow SHmedia code in the same section as constants and
18028 Do not expand MOVI, PT, PTA or PTB instructions.
18031 With -abi=64, expand PT, PTA and PTB instructions to 32 bits only.
18034 Support H'00 style hex constants in addition to 0x00 style.
18038 File: as.info, Node: SH64 Syntax, Next: SH64 Directives, Prev: SH64 Options, Up: SH64-Dependent
18045 * SH64-Chars:: Special Characters
18046 * SH64-Regs:: Register Names
18047 * SH64-Addressing:: Addressing Modes
18050 File: as.info, Node: SH64-Chars, Next: SH64-Regs, Up: SH64 Syntax
18052 9.41.2.1 Special Characters
18053 ...........................
18055 `!' is the line comment character.
18057 If a `#' appears as the first character of a line then the whole
18058 line is treated as a comment, but in this case the line could also be a
18059 logical line number directive (*note Comments::) or a preprocessor
18060 control command (*note Preprocessing::).
18062 You can use `;' instead of a newline to separate statements.
18064 Since `$' has no special meaning, you may use it in symbol names.
18067 File: as.info, Node: SH64-Regs, Next: SH64-Addressing, Prev: SH64-Chars, Up: SH64 Syntax
18069 9.41.2.2 Register Names
18070 .......................
18072 You can use the predefined symbols `r0' through `r63' to refer to the
18073 SH64 general registers, `cr0' through `cr63' for control registers,
18074 `tr0' through `tr7' for target address registers, `fr0' through `fr63'
18075 for single-precision floating point registers, `dr0' through `dr62'
18076 (even numbered registers only) for double-precision floating point
18077 registers, `fv0' through `fv60' (multiples of four only) for
18078 single-precision floating point vectors, `fp0' through `fp62' (even
18079 numbered registers only) for single-precision floating point pairs,
18080 `mtrx0' through `mtrx48' (multiples of 16 only) for 4x4 matrices of
18081 single-precision floating point registers, `pc' for the program
18082 counter, and `fpscr' for the floating point status and control register.
18084 You can also refer to the control registers by the mnemonics `sr',
18085 `ssr', `pssr', `intevt', `expevt', `pexpevt', `tra', `spc', `pspc',
18086 `resvec', `vbr', `tea', `dcr', `kcr0', `kcr1', `ctc', and `usr'.
18089 File: as.info, Node: SH64-Addressing, Prev: SH64-Regs, Up: SH64 Syntax
18091 9.41.2.3 Addressing Modes
18092 .........................
18094 SH64 operands consist of either a register or immediate value. The
18095 immediate value can be a constant or label reference (or portion of a
18096 label reference), as in this example:
18100 movi (function >> 16) & 65535,r0
18101 shori function & 65535, r0
18104 Instruction label references can reference labels in either SHmedia
18105 or SHcompact. To differentiate between the two, labels in SHmedia
18106 sections will always have the least significant bit set (i.e. they will
18107 be odd), which SHcompact labels will have the least significant bit
18108 reset (i.e. they will be even). If you need to reference the actual
18109 address of a label, you can use the `datalabel' modifier, as in this
18113 .long datalabel function
18115 In that example, the first longword may or may not have the least
18116 significant bit set depending on whether the label is an SHmedia label
18117 or an SHcompact label. The second longword will be the actual address
18118 of the label, regardless of what type of label it is.
18121 File: as.info, Node: SH64 Directives, Next: SH64 Opcodes, Prev: SH64 Syntax, Up: SH64-Dependent
18123 9.41.3 SH64 Machine Directives
18124 ------------------------------
18126 In addition to the SH directives, the SH64 provides the following
18129 `.mode [shmedia|shcompact]'
18130 `.isa [shmedia|shcompact]'
18131 Specify the ISA for the following instructions (the two directives
18132 are equivalent). Note that programs such as `objdump' rely on
18133 symbolic labels to determine when such mode switches occur (by
18134 checking the least significant bit of the label's address), so
18135 such mode/isa changes should always be followed by a label (in
18136 practice, this is true anyway). Note that you cannot use these
18137 directives if you didn't specify an ISA on the command line.
18140 Specify the ABI for the following instructions. Note that you
18141 cannot use this directive unless you specified an ABI on the
18142 command line, and the ABIs specified must match.
18146 File: as.info, Node: SH64 Opcodes, Prev: SH64 Directives, Up: SH64-Dependent
18151 For detailed information on the SH64 machine instruction set, see
18152 `SuperH 64 bit RISC Series Architecture Manual' (SuperH, Inc.).
18154 `as' implements all the standard SH64 opcodes. In addition, the
18155 following pseudo-opcodes may be expanded into one or more alternate
18159 If the value doesn't fit into a standard `movi' opcode, `as' will
18160 replace the `movi' with a sequence of `movi' and `shori' opcodes.
18163 This expands to a sequence of `movi' and `shori' opcode, followed
18164 by a `ptrel' opcode, or to a `pta' or `ptb' opcode, depending on
18165 the label referenced.
18169 File: as.info, Node: Sparc-Dependent, Next: TIC54X-Dependent, Prev: SCORE-Dependent, Up: Machine Dependencies
18171 9.42 SPARC Dependent Features
18172 =============================
18176 * Sparc-Opts:: Options
18177 * Sparc-Aligned-Data:: Option to enforce aligned data
18178 * Sparc-Syntax:: Syntax
18179 * Sparc-Float:: Floating Point
18180 * Sparc-Directives:: Sparc Machine Directives
18183 File: as.info, Node: Sparc-Opts, Next: Sparc-Aligned-Data, Up: Sparc-Dependent
18188 The SPARC chip family includes several successive versions, using the
18189 same core instruction set, but including a few additional instructions
18190 at each version. There are exceptions to this however. For details on
18191 what instructions each variant supports, please see the chip's
18192 architecture reference manual.
18194 By default, `as' assumes the core instruction set (SPARC v6), but
18195 "bumps" the architecture level as needed: it switches to successively
18196 higher architectures as it encounters instructions that only exist in
18199 If not configured for SPARC v9 (`sparc64-*-*') GAS will not bump
18200 past sparclite by default, an option must be passed to enable the v9
18203 GAS treats sparclite as being compatible with v8, unless an
18204 architecture is explicitly requested. SPARC v9 is always incompatible
18207 `-Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite'
18208 `-Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv'
18209 `-Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m'
18210 `-Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima'
18211 `-Asparcvis3 | -Asparcvis3r'
18212 Use one of the `-A' options to select one of the SPARC
18213 architectures explicitly. If you select an architecture
18214 explicitly, `as' reports a fatal error if it encounters an
18215 instruction or feature requiring an incompatible or higher level.
18217 `-Av8plus', `-Av8plusa', `-Av8plusb', `-Av8plusc', `-Av8plusd',
18218 and `-Av8plusv' select a 32 bit environment.
18220 `-Av9', `-Av9a', `-Av9b', `-Av9c', `-Av9d', `-Av9e', `-Av9v' and
18221 `-Av9m' select a 64 bit environment and are not available unless
18222 GAS is explicitly configured with 64 bit environment support.
18224 `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with
18225 UltraSPARC VIS 1.0 extensions.
18227 `-Av8plusb' and `-Av9b' enable the UltraSPARC VIS 2.0 instructions,
18228 as well as the instructions enabled by `-Av8plusa' and `-Av9a'.
18230 `-Av8plusc' and `-Av9c' enable the UltraSPARC Niagara instructions,
18231 as well as the instructions enabled by `-Av8plusb' and `-Av9b'.
18233 `-Av8plusd' and `-Av9d' enable the floating point fused
18234 multiply-add, VIS 3.0, and HPC extension instructions, as well as
18235 the instructions enabled by `-Av8plusc' and `-Av9c'.
18237 `-Av8pluse' and `-Av9e' enable the cryptographic instructions, as
18238 well as the instructions enabled by `-Av8plusd' and `-Av9d'.
18240 `-Av8plusv' and `-Av9v' enable floating point unfused
18241 multiply-add, and integer multiply-add, as well as the instructions
18242 enabled by `-Av8pluse' and `-Av9e'.
18244 `-Av8plusm' and `-Av9m' enable the VIS 4.0, subtract extended,
18245 xmpmul, xmontmul and xmontsqr instructions, as well as the
18246 instructions enabled by `-Av8plusv' and `-Av9v'.
18248 `-Asparc' specifies a v9 environment. It is equivalent to `-Av9'
18249 if the word size is 64-bit, and `-Av8plus' otherwise.
18251 `-Asparcvis' specifies a v9a environment. It is equivalent to
18252 `-Av9a' if the word size is 64-bit, and `-Av8plusa' otherwise.
18254 `-Asparcvis2' specifies a v9b environment. It is equivalent to
18255 `-Av9b' if the word size is 64-bit, and `-Av8plusb' otherwise.
18257 `-Asparcfmaf' specifies a v9b environment with the floating point
18258 fused multiply-add instructions enabled.
18260 `-Asparcima' specifies a v9b environment with the integer
18261 multiply-add instructions enabled.
18263 `-Asparcvis3' specifies a v9b environment with the VIS 3.0, HPC ,
18264 and floating point fused multiply-add instructions enabled.
18266 `-Asparcvis3r' specifies a v9b environment with the VIS 3.0, HPC,
18267 and floating point unfused multiply-add instructions enabled.
18269 `-Asparc5' is equivalent to `-Av9m'.
18271 `-xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc'
18272 `-xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a'
18273 `-xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v | -xarch=v9m'
18274 `-xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2'
18275 `-xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3'
18276 `-xarch=sparcvis3r | -xarch=sparc5'
18277 For compatibility with the SunOS v9 assembler. These options are
18278 equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd,
18279 -Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9e, -Av9v, -Av9m,
18280 -Asparc, -Asparcvis, -Asparcvis2, -Asparcfmaf, -Asparcima,
18281 -Asparcvis3, and -Asparcvis3r, respectively.
18284 Warn whenever it is necessary to switch to another level. If an
18285 architecture level is explicitly requested, GAS will not issue
18286 warnings until that level is reached, and will then bump the level
18287 as required (except between incompatible levels).
18290 Select the word size, either 32 bits or 64 bits. These options
18291 are only available with the ELF object file format, and require
18292 that the necessary BFD support has been included.
18295 File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Syntax, Prev: Sparc-Opts, Up: Sparc-Dependent
18297 9.42.2 Enforcing aligned data
18298 -----------------------------
18300 SPARC GAS normally permits data to be misaligned. For example, it
18301 permits the `.long' pseudo-op to be used on a byte boundary. However,
18302 the native SunOS assemblers issue an error when they see misaligned
18305 You can use the `--enforce-aligned-data' option to make SPARC GAS
18306 also issue an error about misaligned data, just as the SunOS assemblers
18309 The `--enforce-aligned-data' option is not the default because gcc
18310 issues misaligned data pseudo-ops when it initializes certain packed
18311 data structures (structures defined using the `packed' attribute). You
18312 may have to assemble with GAS in order to initialize packed data
18313 structures in your own code.
18316 File: as.info, Node: Sparc-Syntax, Next: Sparc-Float, Prev: Sparc-Aligned-Data, Up: Sparc-Dependent
18318 9.42.3 Sparc Syntax
18319 -------------------
18321 The assembler syntax closely follows The Sparc Architecture Manual,
18322 versions 8 and 9, as well as most extensions defined by Sun for their
18323 UltraSPARC and Niagara line of processors.
18327 * Sparc-Chars:: Special Characters
18328 * Sparc-Regs:: Register Names
18329 * Sparc-Constants:: Constant Names
18330 * Sparc-Relocs:: Relocations
18331 * Sparc-Size-Translations:: Size Translations
18334 File: as.info, Node: Sparc-Chars, Next: Sparc-Regs, Up: Sparc-Syntax
18336 9.42.3.1 Special Characters
18337 ...........................
18339 A `!' character appearing anywhere on a line indicates the start of a
18340 comment that extends to the end of that line.
18342 If a `#' appears as the first character of a line then the whole
18343 line is treated as a comment, but in this case the line could also be a
18344 logical line number directive (*note Comments::) or a preprocessor
18345 control command (*note Preprocessing::).
18347 `;' can be used instead of a newline to separate statements.
18350 File: as.info, Node: Sparc-Regs, Next: Sparc-Constants, Prev: Sparc-Chars, Up: Sparc-Syntax
18352 9.42.3.2 Register Names
18353 .......................
18355 The Sparc integer register file is broken down into global, outgoing,
18356 local, and incoming.
18358 * The 8 global registers are referred to as `%gN'.
18360 * The 8 outgoing registers are referred to as `%oN'.
18362 * The 8 local registers are referred to as `%lN'.
18364 * The 8 incoming registers are referred to as `%iN'.
18366 * The frame pointer register `%i6' can be referenced using the alias
18369 * The stack pointer register `%o6' can be referenced using the alias
18372 Floating point registers are simply referred to as `%fN'. When
18373 assembling for pre-V9, only 32 floating point registers are available.
18374 For V9 and later there are 64, but there are restrictions when
18375 referencing the upper 32 registers. They can only be accessed as
18376 double or quad, and thus only even or quad numbered accesses are
18377 allowed. For example, `%f34' is a legal floating point register, but
18380 Certain V9 instructions allow access to ancillary state registers.
18381 Most simply they can be referred to as `%asrN' where N can be from 16
18382 to 31. However, there are some aliases defined to reference ASR
18383 registers defined for various UltraSPARC processors:
18385 * The tick compare register is referred to as `%tick_cmpr'.
18387 * The system tick register is referred to as `%stick'. An alias,
18388 `%sys_tick', exists but is deprecated and should not be used by
18391 * The system tick compare register is referred to as `%stick_cmpr'.
18392 An alias, `%sys_tick_cmpr', exists but is deprecated and should
18393 not be used by new software.
18395 * The software interrupt register is referred to as `%softint'.
18397 * The set software interrupt register is referred to as
18398 `%set_softint'. The mnemonic `%softint_set' is provided as an
18401 * The clear software interrupt register is referred to as
18402 `%clear_softint'. The mnemonic `%softint_clear' is provided as an
18405 * The performance instrumentation counters register is referred to as
18408 * The performance control register is referred to as `%pcr'.
18410 * The graphics status register is referred to as `%gsr'.
18412 * The V9 dispatch control register is referred to as `%dcr'.
18414 Various V9 branch and conditional move instructions allow
18415 specification of which set of integer condition codes to test. These
18416 are referred to as `%xcc' and `%icc'.
18418 In V9, there are 4 sets of floating point condition codes which are
18419 referred to as `%fccN'.
18421 Several special privileged and non-privileged registers exist:
18423 * The V9 address space identifier register is referred to as `%asi'.
18425 * The V9 restorable windows register is referred to as `%canrestore'.
18427 * The V9 savable windows register is referred to as `%cansave'.
18429 * The V9 clean windows register is referred to as `%cleanwin'.
18431 * The V9 current window pointer register is referred to as `%cwp'.
18433 * The floating-point queue register is referred to as `%fq'.
18435 * The V8 co-processor queue register is referred to as `%cq'.
18437 * The floating point status register is referred to as `%fsr'.
18439 * The other windows register is referred to as `%otherwin'.
18441 * The V9 program counter register is referred to as `%pc'.
18443 * The V9 next program counter register is referred to as `%npc'.
18445 * The V9 processor interrupt level register is referred to as `%pil'.
18447 * The V9 processor state register is referred to as `%pstate'.
18449 * The trap base address register is referred to as `%tba'.
18451 * The V9 tick register is referred to as `%tick'.
18453 * The V9 trap level is referred to as `%tl'.
18455 * The V9 trap program counter is referred to as `%tpc'.
18457 * The V9 trap next program counter is referred to as `%tnpc'.
18459 * The V9 trap state is referred to as `%tstate'.
18461 * The V9 trap type is referred to as `%tt'.
18463 * The V9 condition codes is referred to as `%ccr'.
18465 * The V9 floating-point registers state is referred to as `%fprs'.
18467 * The V9 version register is referred to as `%ver'.
18469 * The V9 window state register is referred to as `%wstate'.
18471 * The Y register is referred to as `%y'.
18473 * The V8 window invalid mask register is referred to as `%wim'.
18475 * The V8 processor state register is referred to as `%psr'.
18477 * The V9 global register level register is referred to as `%gl'.
18479 Several special register names exist for hypervisor mode code:
18481 * The hyperprivileged processor state register is referred to as
18484 * The hyperprivileged trap state register is referred to as
18487 * The hyperprivileged interrupt pending register is referred to as
18490 * The hyperprivileged trap base address register is referred to as
18493 * The hyperprivileged implementation version register is referred to
18496 * The hyperprivileged system tick offset register is referred to as
18497 `%hstick_offset'. Note that there is no `%hstick' register, the
18498 normal `%stick' is used.
18500 * The hyperprivileged system tick enable register is referred to as
18503 * The hyperprivileged system tick compare register is referred to as
18507 File: as.info, Node: Sparc-Constants, Next: Sparc-Relocs, Prev: Sparc-Regs, Up: Sparc-Syntax
18512 Several Sparc instructions take an immediate operand field for which
18513 mnemonic names exist. Two such examples are `membar' and `prefetch'.
18514 Another example are the set of V9 memory access instruction that allow
18515 specification of an address space identifier.
18517 The `membar' instruction specifies a memory barrier that is the
18518 defined by the operand which is a bitmask. The supported mask
18521 * `#Sync' requests that all operations (including nonmemory
18522 reference operations) appearing prior to the `membar' must have
18523 been performed and the effects of any exceptions become visible
18524 before any instructions after the `membar' may be initiated. This
18525 corresponds to `membar' cmask field bit 2.
18527 * `#MemIssue' requests that all memory reference operations
18528 appearing prior to the `membar' must have been performed before
18529 any memory operation after the `membar' may be initiated. This
18530 corresponds to `membar' cmask field bit 1.
18532 * `#Lookaside' requests that a store appearing prior to the `membar'
18533 must complete before any load following the `membar' referencing
18534 the same address can be initiated. This corresponds to `membar'
18537 * `#StoreStore' defines that the effects of all stores appearing
18538 prior to the `membar' instruction must be visible to all
18539 processors before the effect of any stores following the `membar'.
18540 Equivalent to the deprecated `stbar' instruction. This
18541 corresponds to `membar' mmask field bit 3.
18543 * `#LoadStore' defines all loads appearing prior to the `membar'
18544 instruction must have been performed before the effect of any
18545 stores following the `membar' is visible to any other processor.
18546 This corresponds to `membar' mmask field bit 2.
18548 * `#StoreLoad' defines that the effects of all stores appearing
18549 prior to the `membar' instruction must be visible to all
18550 processors before loads following the `membar' may be performed.
18551 This corresponds to `membar' mmask field bit 1.
18553 * `#LoadLoad' defines that all loads appearing prior to the `membar'
18554 instruction must have been performed before any loads following
18555 the `membar' may be performed. This corresponds to `membar' mmask
18559 These values can be ored together, for example:
18562 membar #StoreLoad | #LoadLoad
18563 membar #StoreLoad | #StoreStore
18565 The `prefetch' and `prefetcha' instructions take a prefetch function
18566 code. The following prefetch function code constant mnemonics are
18569 * `#n_reads' requests a prefetch for several reads, and corresponds
18570 to a prefetch function code of 0.
18572 `#one_read' requests a prefetch for one read, and corresponds to a
18573 prefetch function code of 1.
18575 `#n_writes' requests a prefetch for several writes (and possibly
18576 reads), and corresponds to a prefetch function code of 2.
18578 `#one_write' requests a prefetch for one write, and corresponds to
18579 a prefetch function code of 3.
18581 `#page' requests a prefetch page, and corresponds to a prefetch
18582 function code of 4.
18584 `#invalidate' requests a prefetch invalidate, and corresponds to a
18585 prefetch function code of 16.
18587 `#unified' requests a prefetch to the nearest unified cache, and
18588 corresponds to a prefetch function code of 17.
18590 `#n_reads_strong' requests a strong prefetch for several reads,
18591 and corresponds to a prefetch function code of 20.
18593 `#one_read_strong' requests a strong prefetch for one read, and
18594 corresponds to a prefetch function code of 21.
18596 `#n_writes_strong' requests a strong prefetch for several writes,
18597 and corresponds to a prefetch function code of 22.
18599 `#one_write_strong' requests a strong prefetch for one write, and
18600 corresponds to a prefetch function code of 23.
18602 Onle one prefetch code may be specified. Here are some examples:
18604 prefetch [%l0 + %l2], #one_read
18605 prefetch [%g2 + 8], #n_writes
18606 prefetcha [%g1] 0x8, #unified
18607 prefetcha [%o0 + 0x10] %asi, #n_reads
18609 The actual behavior of a given prefetch function code is processor
18610 specific. If a processor does not implement a given prefetch
18611 function code, it will treat the prefetch instruction as a nop.
18613 For instructions that accept an immediate address space identifier,
18614 `as' provides many mnemonics corresponding to V9 defined as well
18615 as UltraSPARC and Niagara extended values. For example, `#ASI_P'
18616 and `#ASI_BLK_INIT_QUAD_LDD_AIUS'. See the V9 and processor
18617 specific manuals for details.
18621 File: as.info, Node: Sparc-Relocs, Next: Sparc-Size-Translations, Prev: Sparc-Constants, Up: Sparc-Syntax
18623 9.42.3.4 Relocations
18624 ....................
18626 ELF relocations are available as defined in the 32-bit and 64-bit Sparc
18627 ELF specifications.
18629 `R_SPARC_HI22' is obtained using `%hi' and `R_SPARC_LO10' is
18630 obtained using `%lo'. Likewise `R_SPARC_HIX22' is obtained from `%hix'
18631 and `R_SPARC_LOX10' is obtained using `%lox'. For example:
18633 sethi %hi(symbol), %g1
18634 or %g1, %lo(symbol), %g1
18636 sethi %hix(symbol), %g1
18637 xor %g1, %lox(symbol), %g1
18639 These "high" mnemonics extract bits 31:10 of their operand, and the
18640 "low" mnemonics extract bits 9:0 of their operand.
18642 V9 code model relocations can be requested as follows:
18644 * `R_SPARC_HH22' is requested using `%hh'. It can also be generated
18647 * `R_SPARC_HM10' is requested using `%hm'. It can also be generated
18650 * `R_SPARC_LM22' is requested using `%lm'.
18652 * `R_SPARC_H44' is requested using `%h44'.
18654 * `R_SPARC_M44' is requested using `%m44'.
18656 * `R_SPARC_L44' is requested using `%l44' or `%l34'.
18658 * `R_SPARC_H34' is requested using `%h34'.
18660 The `%l34' generates a `R_SPARC_L44' relocation because it
18661 calculates the necessary value, and therefore no explicit `R_SPARC_L34'
18662 relocation needed to be created for this purpose.
18664 The `%h34' and `%l34' relocations are used for the abs34 code model.
18665 Here is an example abs34 address generation sequence:
18667 sethi %h34(symbol), %g1
18669 or %g1, %l34(symbol), %g1
18671 The PC relative relocation `R_SPARC_PC22' can be obtained by
18672 enclosing an operand inside of `%pc22'. Likewise, the `R_SPARC_PC10'
18673 relocation can be obtained using `%pc10'. These are mostly used when
18674 assembling PIC code. For example, the standard PIC sequence on Sparc
18675 to get the base of the global offset table, PC relative, into a
18676 register, can be performed as:
18678 sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7
18679 add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7
18681 Several relocations exist to allow the link editor to potentially
18682 optimize GOT data references. The `R_SPARC_GOTDATA_OP_HIX22'
18683 relocation can obtained by enclosing an operand inside of
18684 `%gdop_hix22'. The `R_SPARC_GOTDATA_OP_LOX10' relocation can obtained
18685 by enclosing an operand inside of `%gdop_lox10'. Likewise,
18686 `R_SPARC_GOTDATA_OP' can be obtained by enclosing an operand inside of
18687 `%gdop'. For example, assuming the GOT base is in register `%l7':
18689 sethi %gdop_hix22(symbol), %l1
18690 xor %l1, %gdop_lox10(symbol), %l1
18691 ld [%l7 + %l1], %l2, %gdop(symbol)
18693 There are many relocations that can be requested for access to
18694 thread local storage variables. All of the Sparc TLS mnemonics are
18697 * `R_SPARC_TLS_GD_HI22' is requested using `%tgd_hi22'.
18699 * `R_SPARC_TLS_GD_LO10' is requested using `%tgd_lo10'.
18701 * `R_SPARC_TLS_GD_ADD' is requested using `%tgd_add'.
18703 * `R_SPARC_TLS_GD_CALL' is requested using `%tgd_call'.
18705 * `R_SPARC_TLS_LDM_HI22' is requested using `%tldm_hi22'.
18707 * `R_SPARC_TLS_LDM_LO10' is requested using `%tldm_lo10'.
18709 * `R_SPARC_TLS_LDM_ADD' is requested using `%tldm_add'.
18711 * `R_SPARC_TLS_LDM_CALL' is requested using `%tldm_call'.
18713 * `R_SPARC_TLS_LDO_HIX22' is requested using `%tldo_hix22'.
18715 * `R_SPARC_TLS_LDO_LOX10' is requested using `%tldo_lox10'.
18717 * `R_SPARC_TLS_LDO_ADD' is requested using `%tldo_add'.
18719 * `R_SPARC_TLS_IE_HI22' is requested using `%tie_hi22'.
18721 * `R_SPARC_TLS_IE_LO10' is requested using `%tie_lo10'.
18723 * `R_SPARC_TLS_IE_LD' is requested using `%tie_ld'.
18725 * `R_SPARC_TLS_IE_LDX' is requested using `%tie_ldx'.
18727 * `R_SPARC_TLS_IE_ADD' is requested using `%tie_add'.
18729 * `R_SPARC_TLS_LE_HIX22' is requested using `%tle_hix22'.
18731 * `R_SPARC_TLS_LE_LOX10' is requested using `%tle_lox10'.
18733 Here are some example TLS model sequences.
18735 First, General Dynamic:
18737 sethi %tgd_hi22(symbol), %l1
18738 add %l1, %tgd_lo10(symbol), %l1
18739 add %l7, %l1, %o0, %tgd_add(symbol)
18740 call __tls_get_addr, %tgd_call(symbol)
18745 sethi %tldm_hi22(symbol), %l1
18746 add %l1, %tldm_lo10(symbol), %l1
18747 add %l7, %l1, %o0, %tldm_add(symbol)
18748 call __tls_get_addr, %tldm_call(symbol)
18751 sethi %tldo_hix22(symbol), %l1
18752 xor %l1, %tldo_lox10(symbol), %l1
18753 add %o0, %l1, %l1, %tldo_add(symbol)
18757 sethi %tie_hi22(symbol), %l1
18758 add %l1, %tie_lo10(symbol), %l1
18759 ld [%l7 + %l1], %o0, %tie_ld(symbol)
18760 add %g7, %o0, %o0, %tie_add(symbol)
18762 sethi %tie_hi22(symbol), %l1
18763 add %l1, %tie_lo10(symbol), %l1
18764 ldx [%l7 + %l1], %o0, %tie_ldx(symbol)
18765 add %g7, %o0, %o0, %tie_add(symbol)
18767 And finally, Local Exec:
18769 sethi %tle_hix22(symbol), %l1
18770 add %l1, %tle_lox10(symbol), %l1
18773 When assembling for 64-bit, and a secondary constant addend is
18774 specified in an address expression that would normally generate an
18775 `R_SPARC_LO10' relocation, the assembler will emit an `R_SPARC_OLO10'
18779 File: as.info, Node: Sparc-Size-Translations, Prev: Sparc-Relocs, Up: Sparc-Syntax
18781 9.42.3.5 Size Translations
18782 ..........................
18784 Often it is desirable to write code in an operand size agnostic manner.
18785 `as' provides support for this via operand size opcode translations.
18786 Translations are supported for loads, stores, shifts, compare-and-swap
18787 atomics, and the `clr' synthetic instruction.
18789 If generating 32-bit code, `as' will generate the 32-bit opcode.
18790 Whereas if 64-bit code is being generated, the 64-bit opcode will be
18791 emitted. For example `ldn' will be transformed into `ld' for 32-bit
18792 code and `ldx' for 64-bit code.
18794 Here is an example meant to demonstrate all the supported opcode
18798 ldna [%o0] %asi, %o2
18800 stna %o2, [%o0] %asi
18804 casn [%o0], %o1, %o2
18805 casna [%o0] %asi, %o1, %o2
18808 In 32-bit mode `as' will emit:
18811 lda [%o0] %asi, %o2
18813 sta %o2, [%o0] %asi
18817 cas [%o0], %o1, %o2
18818 casa [%o0] %asi, %o1, %o2
18821 And in 64-bit mode `as' will emit:
18824 ldxa [%o0] %asi, %o2
18826 stxa %o2, [%o0] %asi
18830 casx [%o0], %o1, %o2
18831 casxa [%o0] %asi, %o1, %o2
18834 Finally, the `.nword' translating directive is supported as well.
18835 It is documented in the section on Sparc machine directives.
18838 File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Syntax, Up: Sparc-Dependent
18840 9.42.4 Floating Point
18841 ---------------------
18843 The Sparc uses IEEE floating-point numbers.
18846 File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent
18848 9.42.5 Sparc Machine Directives
18849 -------------------------------
18851 The Sparc version of `as' supports the following additional machine
18855 This must be followed by the desired alignment in bytes.
18858 This must be followed by a symbol name, a positive number, and
18859 `"bss"'. This behaves somewhat like `.comm', but the syntax is
18863 This is functionally identical to `.short'.
18866 On the Sparc, the `.nword' directive produces native word sized
18867 value, ie. if assembling with -32 it is equivalent to `.word', if
18868 assembling with -64 it is equivalent to `.xword'.
18871 This directive is ignored. Any text following it on the same line
18875 This directive declares use of a global application or system
18876 register. It must be followed by a register name %g2, %g3, %g6 or
18877 %g7, comma and the symbol name for that register. If symbol name
18878 is `#scratch', it is a scratch register, if it is `#ignore', it
18879 just suppresses any errors about using undeclared global register,
18880 but does not emit any information about it into the object file.
18881 This can be useful e.g. if you save the register before use and
18885 This must be followed by a symbol name, a positive number, and
18886 `"bss"'. This behaves somewhat like `.lcomm', but the syntax is
18890 This must be followed by `"text"', `"data"', or `"data1"'. It
18891 behaves like `.text', `.data', or `.data 1'.
18894 This is functionally identical to the `.space' directive.
18897 On the Sparc, the `.word' directive produces 32 bit values,
18898 instead of the 16 bit values it produces on many other machines.
18901 On the Sparc V9 processor, the `.xword' directive produces 64 bit
18905 File: as.info, Node: TIC54X-Dependent, Next: TIC6X-Dependent, Prev: Sparc-Dependent, Up: Machine Dependencies
18907 9.43 TIC54X Dependent Features
18908 ==============================
18912 * TIC54X-Opts:: Command-line Options
18913 * TIC54X-Block:: Blocking
18914 * TIC54X-Env:: Environment Settings
18915 * TIC54X-Constants:: Constants Syntax
18916 * TIC54X-Subsyms:: String Substitution
18917 * TIC54X-Locals:: Local Label Syntax
18918 * TIC54X-Builtins:: Builtin Assembler Math Functions
18919 * TIC54X-Ext:: Extended Addressing Support
18920 * TIC54X-Directives:: Directives
18921 * TIC54X-Macros:: Macro Features
18922 * TIC54X-MMRegs:: Memory-mapped Registers
18923 * TIC54X-Syntax:: Syntax
18926 File: as.info, Node: TIC54X-Opts, Next: TIC54X-Block, Up: TIC54X-Dependent
18931 The TMS320C54X version of `as' has a few machine-dependent options.
18933 You can use the `-mfar-mode' option to enable extended addressing
18934 mode. All addresses will be assumed to be > 16 bits, and the
18935 appropriate relocation types will be used. This option is equivalent
18936 to using the `.far_mode' directive in the assembly code. If you do not
18937 use the `-mfar-mode' option, all references will be assumed to be 16
18938 bits. This option may be abbreviated to `-mf'.
18940 You can use the `-mcpu' option to specify a particular CPU. This
18941 option is equivalent to using the `.version' directive in the assembly
18942 code. For recognized CPU codes, see *Note `.version':
18943 TIC54X-Directives. The default CPU version is `542'.
18945 You can use the `-merrors-to-file' option to redirect error output
18946 to a file (this provided for those deficient environments which don't
18947 provide adequate output redirection). This option may be abbreviated to
18951 File: as.info, Node: TIC54X-Block, Next: TIC54X-Env, Prev: TIC54X-Opts, Up: TIC54X-Dependent
18956 A blocked section or memory block is guaranteed not to cross the
18957 blocking boundary (usually a page, or 128 words) if it is smaller than
18958 the blocking size, or to start on a page boundary if it is larger than
18962 File: as.info, Node: TIC54X-Env, Next: TIC54X-Constants, Prev: TIC54X-Block, Up: TIC54X-Dependent
18964 9.43.3 Environment Settings
18965 ---------------------------
18967 `C54XDSP_DIR' and `A_DIR' are semicolon-separated paths which are added
18968 to the list of directories normally searched for source and include
18969 files. `C54XDSP_DIR' will override `A_DIR'.
18972 File: as.info, Node: TIC54X-Constants, Next: TIC54X-Subsyms, Prev: TIC54X-Env, Up: TIC54X-Dependent
18974 9.43.4 Constants Syntax
18975 -----------------------
18977 The TIC54X version of `as' allows the following additional constant
18978 formats, using a suffix to indicate the radix:
18980 Binary `000000B, 011000b'
18982 Hexadecimal `45h, 0FH'
18985 File: as.info, Node: TIC54X-Subsyms, Next: TIC54X-Locals, Prev: TIC54X-Constants, Up: TIC54X-Dependent
18987 9.43.5 String Substitution
18988 --------------------------
18990 A subset of allowable symbols (which we'll call subsyms) may be assigned
18991 arbitrary string values. This is roughly equivalent to C preprocessor
18992 #define macros. When `as' encounters one of these symbols, the symbol
18993 is replaced in the input stream by its string value. Subsym names
18994 *must* begin with a letter.
18996 Subsyms may be defined using the `.asg' and `.eval' directives
18997 (*Note `.asg': TIC54X-Directives, *Note `.eval': TIC54X-Directives.
18999 Expansion is recursive until a previously encountered symbol is
19000 seen, at which point substitution stops.
19002 In this example, x is replaced with SYM2; SYM2 is replaced with
19003 SYM1, and SYM1 is replaced with x. At this point, x has already been
19004 encountered and the substitution stops.
19009 add x,a ; final code assembled is "add x, a"
19011 Macro parameters are converted to subsyms; a side effect of this is
19012 the normal `as' '\ARG' dereferencing syntax is unnecessary. Subsyms
19013 defined within a macro will have global scope, unless the `.var'
19014 directive is used to identify the subsym as a local macro variable
19015 *note `.var': TIC54X-Directives.
19017 Substitution may be forced in situations where replacement might be
19018 ambiguous by placing colons on either side of the subsym. The following
19024 When assembled becomes:
19028 Smaller parts of the string assigned to a subsym may be accessed with
19029 the following syntax:
19031 ``:SYMBOL(CHAR_INDEX):''
19032 Evaluates to a single-character string, the character at
19035 ``:SYMBOL(START,LENGTH):''
19036 Evaluates to a substring of SYMBOL beginning at START with length
19040 File: as.info, Node: TIC54X-Locals, Next: TIC54X-Builtins, Prev: TIC54X-Subsyms, Up: TIC54X-Dependent
19042 9.43.6 Local Labels
19043 -------------------
19045 Local labels may be defined in two ways:
19047 * $N, where N is a decimal number between 0 and 9
19049 * LABEL?, where LABEL is any legal symbol name.
19051 Local labels thus defined may be redefined or automatically
19052 generated. The scope of a local label is based on when it may be
19053 undefined or reset. This happens when one of the following situations
19056 * .newblock directive *note `.newblock': TIC54X-Directives.
19058 * The current section is changed (.sect, .text, or .data)
19060 * Entering or leaving an included file
19062 * The macro scope where the label was defined is exited
19065 File: as.info, Node: TIC54X-Builtins, Next: TIC54X-Ext, Prev: TIC54X-Locals, Up: TIC54X-Dependent
19067 9.43.7 Math Builtins
19068 --------------------
19070 The following built-in functions may be used to generate a
19071 floating-point value. All return a floating-point value except `$cvi',
19072 `$int', and `$sgn', which return an integer value.
19075 Returns the floating point arccosine of EXPR.
19078 Returns the floating point arcsine of EXPR.
19081 Returns the floating point arctangent of EXPR.
19083 ``$atan2(EXPR1,EXPR2)''
19084 Returns the floating point arctangent of EXPR1 / EXPR2.
19087 Returns the smallest integer not less than EXPR as floating point.
19090 Returns the floating point hyperbolic cosine of EXPR.
19093 Returns the floating point cosine of EXPR.
19096 Returns the integer value EXPR converted to floating-point.
19099 Returns the floating point value EXPR converted to integer.
19102 Returns the floating point value e ^ EXPR.
19105 Returns the floating point absolute value of EXPR.
19108 Returns the largest integer that is not greater than EXPR as
19111 ``$fmod(EXPR1,EXPR2)''
19112 Returns the floating point remainder of EXPR1 / EXPR2.
19115 Returns 1 if EXPR evaluates to an integer, zero otherwise.
19117 ``$ldexp(EXPR1,EXPR2)''
19118 Returns the floating point value EXPR1 * 2 ^ EXPR2.
19121 Returns the base 10 logarithm of EXPR.
19124 Returns the natural logarithm of EXPR.
19126 ``$max(EXPR1,EXPR2)''
19127 Returns the floating point maximum of EXPR1 and EXPR2.
19129 ``$min(EXPR1,EXPR2)''
19130 Returns the floating point minimum of EXPR1 and EXPR2.
19132 ``$pow(EXPR1,EXPR2)''
19133 Returns the floating point value EXPR1 ^ EXPR2.
19136 Returns the nearest integer to EXPR as a floating point number.
19139 Returns -1, 0, or 1 based on the sign of EXPR.
19142 Returns the floating point sine of EXPR.
19145 Returns the floating point hyperbolic sine of EXPR.
19148 Returns the floating point square root of EXPR.
19151 Returns the floating point tangent of EXPR.
19154 Returns the floating point hyperbolic tangent of EXPR.
19157 Returns the integer value of EXPR truncated towards zero as
19162 File: as.info, Node: TIC54X-Ext, Next: TIC54X-Directives, Prev: TIC54X-Builtins, Up: TIC54X-Dependent
19164 9.43.8 Extended Addressing
19165 --------------------------
19167 The `LDX' pseudo-op is provided for loading the extended addressing bits
19168 of a label or address. For example, if an address `_label' resides in
19169 extended program memory, the value of `_label' may be loaded as follows:
19170 ldx #_label,16,a ; loads extended bits of _label
19171 or #_label,a ; loads lower 16 bits of _label
19172 bacc a ; full address is in accumulator A
19175 File: as.info, Node: TIC54X-Directives, Next: TIC54X-Macros, Prev: TIC54X-Ext, Up: TIC54X-Dependent
19182 Align the section program counter on the next boundary, based on
19183 SIZE. SIZE may be any power of 2. `.even' is equivalent to
19184 `.align' with a SIZE of 2.
19186 Align SPC to word boundary
19189 Align SPC to longword boundary (same as .even)
19192 Align SPC to page boundary
19194 `.asg STRING, NAME'
19195 Assign NAME the string STRING. String replacement is performed on
19196 STRING before assignment.
19198 `.eval STRING, NAME'
19199 Evaluate the contents of string STRING and assign the result as a
19200 string to the subsym NAME. String replacement is performed on
19201 STRING before assignment.
19203 `.bss SYMBOL, SIZE [, [BLOCKING_FLAG] [,ALIGNMENT_FLAG]]'
19204 Reserve space for SYMBOL in the .bss section. SIZE is in words.
19205 If present, BLOCKING_FLAG indicates the allocated space should be
19206 aligned on a page boundary if it would otherwise cross a page
19207 boundary. If present, ALIGNMENT_FLAG causes the assembler to
19208 allocate SIZE on a long word boundary.
19210 `.byte VALUE [,...,VALUE_N]'
19211 `.ubyte VALUE [,...,VALUE_N]'
19212 `.char VALUE [,...,VALUE_N]'
19213 `.uchar VALUE [,...,VALUE_N]'
19214 Place one or more bytes into consecutive words of the current
19215 section. The upper 8 bits of each word is zero-filled. If a
19216 label is used, it points to the word allocated for the first byte
19219 `.clink ["SECTION_NAME"]'
19220 Set STYP_CLINK flag for this section, which indicates to the
19221 linker that if no symbols from this section are referenced, the
19222 section should not be included in the link. If SECTION_NAME is
19223 omitted, the current section is used.
19228 `.copy "FILENAME" | FILENAME'
19229 `.include "FILENAME" | FILENAME'
19230 Read source statements from FILENAME. The normal include search
19231 path is used. Normally .copy will cause statements from the
19232 included file to be printed in the assembly listing and .include
19233 will not, but this distinction is not currently implemented.
19236 Begin assembling code into the .data section.
19238 `.double VALUE [,...,VALUE_N]'
19239 `.ldouble VALUE [,...,VALUE_N]'
19240 `.float VALUE [,...,VALUE_N]'
19241 `.xfloat VALUE [,...,VALUE_N]'
19242 Place an IEEE single-precision floating-point representation of
19243 one or more floating-point values into the current section. All
19244 but `.xfloat' align the result on a longword boundary. Values are
19245 stored most-significant word first.
19249 Control printing of directives to the listing file. Ignored.
19254 Emit a user-defined error, message, or warning, respectively.
19257 Use extended addressing when assembling statements. This should
19258 appear only once per file, and is equivalent to the -mfar-mode
19259 option *note `-mfar-mode': TIC54X-Opts.
19263 Control printing of false conditional blocks to the listing file.
19265 `.field VALUE [,SIZE]'
19266 Initialize a bitfield of SIZE bits in the current section. If
19267 VALUE is relocatable, then SIZE must be 16. SIZE defaults to 16
19268 bits. If VALUE does not fit into SIZE bits, the value will be
19269 truncated. Successive `.field' directives will pack starting at
19270 the current word, filling the most significant bits first, and
19271 aligning to the start of the next word if the field size does not
19272 fit into the space remaining in the current word. A `.align'
19273 directive with an operand of 1 will force the next `.field'
19274 directive to begin packing into a new word. If a label is used, it
19275 points to the word that contains the specified field.
19277 `.global SYMBOL [,...,SYMBOL_N]'
19278 `.def SYMBOL [,...,SYMBOL_N]'
19279 `.ref SYMBOL [,...,SYMBOL_N]'
19280 `.def' nominally identifies a symbol defined in the current file
19281 and available to other files. `.ref' identifies a symbol used in
19282 the current file but defined elsewhere. Both map to the standard
19283 `.global' directive.
19285 `.half VALUE [,...,VALUE_N]'
19286 `.uhalf VALUE [,...,VALUE_N]'
19287 `.short VALUE [,...,VALUE_N]'
19288 `.ushort VALUE [,...,VALUE_N]'
19289 `.int VALUE [,...,VALUE_N]'
19290 `.uint VALUE [,...,VALUE_N]'
19291 `.word VALUE [,...,VALUE_N]'
19292 `.uword VALUE [,...,VALUE_N]'
19293 Place one or more values into consecutive words of the current
19294 section. If a label is used, it points to the word allocated for
19295 the first value encountered.
19298 Define a special SYMBOL to refer to the load time address of the
19299 current section program counter.
19303 Set the page length and width of the output listing file. Ignored.
19307 Control whether the source listing is printed. Ignored.
19309 `.long VALUE [,...,VALUE_N]'
19310 `.ulong VALUE [,...,VALUE_N]'
19311 `.xlong VALUE [,...,VALUE_N]'
19312 Place one or more 32-bit values into consecutive words in the
19313 current section. The most significant word is stored first.
19314 `.long' and `.ulong' align the result on a longword boundary;
19318 `.break [CONDITION]'
19320 Repeatedly assemble a block of code. `.loop' begins the block, and
19321 `.endloop' marks its termination. COUNT defaults to 1024, and
19322 indicates the number of times the block should be repeated.
19323 `.break' terminates the loop so that assembly begins after the
19324 `.endloop' directive. The optional CONDITION will cause the loop
19325 to terminate only if it evaluates to zero.
19327 `MACRO_NAME .macro [PARAM1][,...PARAM_N]'
19330 See the section on macros for more explanation (*Note
19333 `.mlib "FILENAME" | FILENAME'
19334 Load the macro library FILENAME. FILENAME must be an archived
19335 library (BFD ar-compatible) of text files, expected to contain
19336 only macro definitions. The standard include search path is used.
19340 Control whether to include macro and loop block expansions in the
19341 listing output. Ignored.
19344 Define global symbolic names for the 'c54x registers. Supposedly
19345 equivalent to executing `.set' directives for each register with
19346 its memory-mapped value, but in reality is provided only for
19347 compatibility and does nothing.
19350 This directive resets any TIC54X local labels currently defined.
19351 Normal `as' local labels are unaffected.
19353 `.option OPTION_LIST'
19354 Set listing options. Ignored.
19356 `.sblock "SECTION_NAME" | SECTION_NAME [,"NAME_N" | NAME_N]'
19357 Designate SECTION_NAME for blocking. Blocking guarantees that a
19358 section will start on a page boundary (128 words) if it would
19359 otherwise cross a page boundary. Only initialized sections may be
19360 designated with this directive. See also *Note TIC54X-Block::.
19362 `.sect "SECTION_NAME"'
19363 Define a named initialized section and make it the current section.
19365 `SYMBOL .set "VALUE"'
19366 `SYMBOL .equ "VALUE"'
19367 Equate a constant VALUE to a SYMBOL, which is placed in the symbol
19368 table. SYMBOL may not be previously defined.
19370 `.space SIZE_IN_BITS'
19371 `.bes SIZE_IN_BITS'
19372 Reserve the given number of bits in the current section and
19373 zero-fill them. If a label is used with `.space', it points to the
19374 *first* word reserved. With `.bes', the label points to the
19375 *last* word reserved.
19379 Controls the inclusion of subsym replacement in the listing
19382 `.string "STRING" [,...,"STRING_N"]'
19383 `.pstring "STRING" [,...,"STRING_N"]'
19384 Place 8-bit characters from STRING into the current section.
19385 `.string' zero-fills the upper 8 bits of each word, while
19386 `.pstring' puts two characters into each word, filling the
19387 most-significant bits first. Unused space is zero-filled. If a
19388 label is used, it points to the first word initialized.
19390 `[STAG] .struct [OFFSET]'
19391 `[NAME_1] element [COUNT_1]'
19392 `[NAME_2] element [COUNT_2]'
19393 `[TNAME] .tag STAGX [TCOUNT]'
19395 `[NAME_N] element [COUNT_N]'
19396 `[SSIZE] .endstruct'
19397 `LABEL .tag [STAG]'
19398 Assign symbolic offsets to the elements of a structure. STAG
19399 defines a symbol to use to reference the structure. OFFSET
19400 indicates a starting value to use for the first element
19401 encountered; otherwise it defaults to zero. Each element can have
19402 a named offset, NAME, which is a symbol assigned the value of the
19403 element's offset into the structure. If STAG is missing, these
19404 become global symbols. COUNT adjusts the offset that many times,
19405 as if `element' were an array. `element' may be one of `.byte',
19406 `.word', `.long', `.float', or any equivalent of those, and the
19407 structure offset is adjusted accordingly. `.field' and `.string'
19408 are also allowed; the size of `.field' is one bit, and `.string'
19409 is considered to be one word in size. Only element descriptors,
19410 structure/union tags, `.align' and conditional assembly directives
19411 are allowed within `.struct'/`.endstruct'. `.align' aligns member
19412 offsets to word boundaries only. SSIZE, if provided, will always
19413 be assigned the size of the structure.
19415 The `.tag' directive, in addition to being used to define a
19416 structure/union element within a structure, may be used to apply a
19417 structure to a symbol. Once applied to LABEL, the individual
19418 structure elements may be applied to LABEL to produce the desired
19419 offsets using LABEL as the structure base.
19422 Set the tab size in the output listing. Ignored.
19425 `[NAME_1] element [COUNT_1]'
19426 `[NAME_2] element [COUNT_2]'
19427 `[TNAME] .tag UTAGX[,TCOUNT]'
19429 `[NAME_N] element [COUNT_N]'
19430 `[USIZE] .endstruct'
19431 `LABEL .tag [UTAG]'
19432 Similar to `.struct', but the offset after each element is reset to
19433 zero, and the USIZE is set to the maximum of all defined elements.
19434 Starting offset for the union is always zero.
19436 `[SYMBOL] .usect "SECTION_NAME", SIZE, [,[BLOCKING_FLAG] [,ALIGNMENT_FLAG]]'
19437 Reserve space for variables in a named, uninitialized section
19438 (similar to .bss). `.usect' allows definitions sections
19439 independent of .bss. SYMBOL points to the first location reserved
19440 by this allocation. The symbol may be used as a variable name.
19441 SIZE is the allocated size in words. BLOCKING_FLAG indicates
19442 whether to block this section on a page boundary (128 words)
19443 (*note TIC54X-Block::). ALIGNMENT FLAG indicates whether the
19444 section should be longword-aligned.
19446 `.var SYM[,..., SYM_N]'
19447 Define a subsym to be a local variable within a macro. See *Note
19451 Set which processor to build instructions for. Though the
19452 following values are accepted, the op is ignored.
19463 File: as.info, Node: TIC54X-Macros, Next: TIC54X-MMRegs, Prev: TIC54X-Directives, Up: TIC54X-Dependent
19468 Macros do not require explicit dereferencing of arguments (i.e., \ARG).
19470 During macro expansion, the macro parameters are converted to
19471 subsyms. If the number of arguments passed the macro invocation
19472 exceeds the number of parameters defined, the last parameter is
19473 assigned the string equivalent of all remaining arguments. If fewer
19474 arguments are given than parameters, the missing parameters are
19475 assigned empty strings. To include a comma in an argument, you must
19476 enclose the argument in quotes.
19478 The following built-in subsym functions allow examination of the
19479 string value of subsyms (or ordinary strings). The arguments are
19480 strings unless otherwise indicated (subsyms passed as args will be
19481 replaced by the strings they represent).
19483 Returns the length of STR.
19485 ``$symcmp(STR1,STR2)''
19486 Returns 0 if STR1 == STR2, non-zero otherwise.
19488 ``$firstch(STR,CH)''
19489 Returns index of the first occurrence of character constant CH in
19492 ``$lastch(STR,CH)''
19493 Returns index of the last occurrence of character constant CH in
19496 ``$isdefed(SYMBOL)''
19497 Returns zero if the symbol SYMBOL is not in the symbol table,
19498 non-zero otherwise.
19500 ``$ismember(SYMBOL,LIST)''
19501 Assign the first member of comma-separated string LIST to SYMBOL;
19502 LIST is reassigned the remainder of the list. Returns zero if
19503 LIST is a null string. Both arguments must be subsyms.
19506 Returns 1 if string EXPR is binary, 2 if octal, 3 if hexadecimal,
19507 4 if a character, 5 if decimal, and zero if not an integer.
19510 Returns 1 if NAME is a valid symbol name, zero otherwise.
19513 Returns 1 if REG is a valid predefined register name (AR0-AR7
19516 ``$structsz(STAG)''
19517 Returns the size of the structure or union represented by STAG.
19519 ``$structacc(STAG)''
19520 Returns the reference point of the structure or union represented
19521 by STAG. Always returns zero.
19525 File: as.info, Node: TIC54X-MMRegs, Next: TIC54X-Syntax, Prev: TIC54X-Macros, Up: TIC54X-Dependent
19527 9.43.11 Memory-mapped Registers
19528 -------------------------------
19530 The following symbols are recognized as memory-mapped registers:
19534 File: as.info, Node: TIC54X-Syntax, Prev: TIC54X-MMRegs, Up: TIC54X-Dependent
19536 9.43.12 TIC54X Syntax
19537 ---------------------
19541 * TIC54X-Chars:: Special Characters
19544 File: as.info, Node: TIC54X-Chars, Up: TIC54X-Syntax
19546 9.43.12.1 Special Characters
19547 ............................
19549 The presence of a `;' appearing anywhere on a line indicates the start
19550 of a comment that extends to the end of that line.
19552 If a `#' appears as the first character of a line then the whole
19553 line is treated as a comment, but in this case the line can also be a
19554 logical line number directive (*note Comments::) or a preprocessor
19555 control command (*note Preprocessing::).
19557 The presence of an asterisk (`*') at the start of a line also
19558 indicates a comment that extends to the end of that line.
19560 The TIC54X assembler does not currently support a line separator
19564 File: as.info, Node: TIC6X-Dependent, Next: TILE-Gx-Dependent, Prev: TIC54X-Dependent, Up: Machine Dependencies
19566 9.44 TIC6X Dependent Features
19567 =============================
19571 * TIC6X Options:: Options
19572 * TIC6X Syntax:: Syntax
19573 * TIC6X Directives:: Directives
19576 File: as.info, Node: TIC6X Options, Next: TIC6X Syntax, Up: TIC6X-Dependent
19578 9.44.1 TIC6X Options
19579 --------------------
19582 Enable (only) instructions from architecture ARCH. By default,
19583 all instructions are permitted.
19585 The following values of ARCH are accepted: `c62x', `c64x',
19586 `c64x+', `c67x', `c67x+', `c674x'.
19590 The `-mdsbt' option causes the assembler to generate the
19591 `Tag_ABI_DSBT' attribute with a value of 1, indicating that the
19592 code is using DSBT addressing. The `-mno-dsbt' option, the
19593 default, causes the tag to have a value of 0, indicating that the
19594 code does not use DSBT addressing. The linker will emit a warning
19595 if objects of different type (DSBT and non-DSBT) are linked
19601 The `-mpid=' option causes the assembler to generate the
19602 `Tag_ABI_PID' attribute with a value indicating the form of data
19603 addressing used by the code. `-mpid=no', the default, indicates
19604 position-dependent data addressing, `-mpid=near' indicates
19605 position-independent addressing with GOT accesses using near DP
19606 addressing, and `-mpid=far' indicates position-independent
19607 addressing with GOT accesses using far DP addressing. The linker
19608 will emit a warning if objects built with different settings of
19609 this option are linked together.
19613 The `-mpic' option causes the assembler to generate the
19614 `Tag_ABI_PIC' attribute with a value of 1, indicating that the
19615 code is using position-independent code addressing, The
19616 `-mno-pic' option, the default, causes the tag to have a value of
19617 0, indicating position-dependent code addressing. The linker will
19618 emit a warning if objects of different type (position-dependent and
19619 position-independent) are linked together.
19623 Generate code for the specified endianness. The default is
19628 File: as.info, Node: TIC6X Syntax, Next: TIC6X Directives, Prev: TIC6X Options, Up: TIC6X-Dependent
19630 9.44.2 TIC6X Syntax
19631 -------------------
19633 The presence of a `;' on a line indicates the start of a comment that
19634 extends to the end of the current line. If a `#' or `*' appears as the
19635 first character of a line, the whole line is treated as a comment.
19636 Note that if a line starts with a `#' character then it can also be a
19637 logical line number directive (*note Comments::) or a preprocessor
19638 control command (*note Preprocessing::).
19640 The `@' character can be used instead of a newline to separate
19643 Instruction, register and functional unit names are case-insensitive.
19644 `as' requires fully-specified functional unit names, such as `.S1',
19645 `.L1X' or `.D1T2', on all instructions using a functional unit.
19647 For some instructions, there may be syntactic ambiguity between
19648 register or functional unit names and the names of labels or other
19649 symbols. To avoid this, enclose the ambiguous symbol name in
19650 parentheses; register and functional unit names may not be enclosed in
19654 File: as.info, Node: TIC6X Directives, Prev: TIC6X Syntax, Up: TIC6X-Dependent
19656 9.44.3 TIC6X Directives
19657 -----------------------
19659 Directives controlling the set of instructions accepted by the
19660 assembler have effect for instructions between the directive and any
19661 subsequent directive overriding it.
19664 This has the same effect as `-march=ARCH'.
19667 Prevents unwinding through the current function. No personality
19668 routine or exception table data is required or permitted.
19670 If this is not specified then frame unwinding information will be
19671 constructed from CFI directives. *note CFI directives::.
19673 `.c6xabi_attribute TAG, VALUE'
19674 Set the C6000 EABI build attribute TAG to VALUE.
19676 The TAG is either an attribute number or one of `Tag_ISA',
19677 `Tag_ABI_wchar_t', `Tag_ABI_stack_align_needed',
19678 `Tag_ABI_stack_align_preserved', `Tag_ABI_DSBT', `Tag_ABI_PID',
19679 `Tag_ABI_PIC', `TAG_ABI_array_object_alignment',
19680 `TAG_ABI_array_object_align_expected', `Tag_ABI_compatibility' and
19681 `Tag_ABI_conformance'. The VALUE is either a `number',
19682 `"string"', or `number, "string"' depending on the tag.
19685 Output an exception type table reference to SYMBOL.
19688 Marks the end of and exception table or function. If preceeded by
19689 a `.handlerdata' directive then this also switched back to the
19690 previous text section.
19693 Marks the end of the current function, and the start of the
19694 exception table entry for that function. Anything between this
19695 directive and the `.endp' directive will be added to the exception
19698 Must be preceded by a CFI block containing a `.cfi_lsda' directive.
19701 Disallow use of C64x+ compact instructions in the current text
19704 `.personalityindex INDEX'
19705 Sets the personality routine for the current function to the ABI
19706 specified compact routine number INDEX
19708 `.personality NAME'
19709 Sets the personality routine for the current function to NAME.
19711 `.scomm SYMBOL, SIZE, ALIGN'
19712 Like `.comm', creating a common symbol SYMBOL with size SIZE and
19713 alignment ALIGN, but unlike when using `.comm', this symbol will
19714 be placed into the small BSS section by the linker.
19718 File: as.info, Node: TILE-Gx-Dependent, Next: TILEPro-Dependent, Prev: TIC6X-Dependent, Up: Machine Dependencies
19720 9.45 TILE-Gx Dependent Features
19721 ===============================
19725 * TILE-Gx Options:: TILE-Gx Options
19726 * TILE-Gx Syntax:: TILE-Gx Syntax
19727 * TILE-Gx Directives:: TILE-Gx Directives
19730 File: as.info, Node: TILE-Gx Options, Next: TILE-Gx Syntax, Up: TILE-Gx-Dependent
19735 The following table lists all available TILE-Gx specific options:
19738 Select the word size, either 32 bits or 64 bits.
19741 Select the endianness, either big-endian (-EB) or little-endian
19746 File: as.info, Node: TILE-Gx Syntax, Next: TILE-Gx Directives, Prev: TILE-Gx Options, Up: TILE-Gx-Dependent
19751 Block comments are delimited by `/*' and `*/'. End of line comments
19752 may be introduced by `#'.
19754 Instructions consist of a leading opcode or macro name followed by
19755 whitespace and an optional comma-separated list of operands:
19757 OPCODE [OPERAND, ...]
19759 Instructions must be separated by a newline or semicolon.
19761 There are two ways to write code: either write naked instructions,
19762 which the assembler is free to combine into VLIW bundles, or specify
19763 the VLIW bundles explicitly.
19765 Bundles are specified using curly braces:
19767 { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 }
19769 A bundle can span multiple lines. If you want to put multiple
19770 instructions on a line, whether in a bundle or not, you need to
19771 separate them with semicolons as in this example.
19773 A bundle may contain one or more instructions, up to the limit
19774 specified by the ISA (currently three). If fewer instructions are
19775 specified than the hardware supports in a bundle, the assembler inserts
19776 `fnop' instructions automatically.
19778 The assembler will prefer to preserve the ordering of instructions
19779 within the bundle, putting the first instruction in a lower-numbered
19780 pipeline than the next one, etc. This fact, combined with the optional
19781 use of explicit `fnop' or `nop' instructions, allows precise control
19782 over which pipeline executes each instruction.
19784 If the instructions cannot be bundled in the listed order, the
19785 assembler will automatically try to find a valid pipeline assignment.
19786 If there is no way to bundle the instructions together, the assembler
19789 The assembler does not yet auto-bundle (automatically combine
19790 multiple instructions into one bundle), but it reserves the right to do
19791 so in the future. If you want to force an instruction to run by
19792 itself, put it in a bundle explicitly with curly braces and use `nop'
19793 instructions (not `fnop') to fill the remaining pipeline slots in that
19798 * TILE-Gx Opcodes:: Opcode Naming Conventions.
19799 * TILE-Gx Registers:: Register Naming.
19800 * TILE-Gx Modifiers:: Symbolic Operand Modifiers.
19803 File: as.info, Node: TILE-Gx Opcodes, Next: TILE-Gx Registers, Up: TILE-Gx Syntax
19805 9.45.2.1 Opcode Names
19806 .....................
19808 For a complete list of opcodes and descriptions of their semantics, see
19809 `TILE-Gx Instruction Set Architecture', available upon request at
19813 File: as.info, Node: TILE-Gx Registers, Next: TILE-Gx Modifiers, Prev: TILE-Gx Opcodes, Up: TILE-Gx Syntax
19815 9.45.2.2 Register Names
19816 .......................
19818 General-purpose registers are represented by predefined symbols of the
19819 form `rN', where N represents a number between `0' and `63'. However,
19820 the following registers have canonical names that must be used instead:
19853 The assembler will emit a warning if a numeric name is used instead
19854 of the non-numeric name. The `.no_require_canonical_reg_names'
19855 assembler pseudo-op turns off this warning.
19856 `.require_canonical_reg_names' turns it back on.
19859 File: as.info, Node: TILE-Gx Modifiers, Prev: TILE-Gx Registers, Up: TILE-Gx Syntax
19861 9.45.2.3 Symbolic Operand Modifiers
19862 ...................................
19864 The assembler supports several modifiers when using symbol addresses in
19865 TILE-Gx instruction operands. The general syntax is the following:
19869 The following modifiers are supported:
19872 This modifier is used to load bits 0-15 of the symbol's address.
19875 This modifier is used to load bits 16-31 of the symbol's address.
19878 This modifier is used to load bits 32-47 of the symbol's address.
19881 This modifier is used to load bits 48-63 of the symbol's address.
19884 This modifier yields the same value as `hw0', but it also checks
19885 that the value does not overflow.
19888 This modifier yields the same value as `hw1', but it also checks
19889 that the value does not overflow.
19892 This modifier yields the same value as `hw2', but it also checks
19893 that the value does not overflow.
19895 A 48-bit symbolic value is constructed by using the following
19898 moveli r0, hw2_last(sym)
19899 shl16insli r0, r0, hw1(sym)
19900 shl16insli r0, r0, hw0(sym)
19903 This modifier is used to load bits 0-15 of the symbol's offset in
19904 the GOT entry corresponding to the symbol.
19907 This modifier yields the same value as `hw0_got', but it also
19908 checks that the value does not overflow.
19911 This modifier is used to load bits 16-31 of the symbol's offset in
19912 the GOT entry corresponding to the symbol, and it also checks that
19913 the value does not overflow.
19916 This modifier is used for function symbols. It causes a
19917 _procedure linkage table_, an array of code stubs, to be created
19918 at the time the shared object is created or linked against,
19919 together with a global offset table entry. The value is a
19920 pc-relative offset to the corresponding stub code in the procedure
19921 linkage table. This arrangement causes the run-time symbol
19922 resolver to be called to look up and set the value of the symbol
19923 the first time the function is called (at latest; depending
19924 environment variables). It is only safe to leave the symbol
19925 unresolved this way if all references are function calls.
19928 This modifier is used to load bits 0-15 of the pc-relative address
19932 This modifier is used to load bits 16-31 of the pc-relative
19933 address of a plt entry.
19936 This modifier yields the same value as `hw1_plt', but it also
19937 checks that the value does not overflow.
19940 This modifier is used to load bits 32-47 of the pc-relative
19941 address of a plt entry, and it also checks that the value does not
19945 This modifier is used to load bits 0-15 of the offset of the GOT
19946 entry of the symbol's TLS descriptor, to be used for
19947 general-dynamic TLS accesses.
19950 This modifier yields the same value as `hw0_tls_gd', but it also
19951 checks that the value does not overflow.
19954 This modifier is used to load bits 16-31 of the offset of the GOT
19955 entry of the symbol's TLS descriptor, to be used for
19956 general-dynamic TLS accesses. It also checks that the value does
19960 This modifier is used to load bits 0-15 of the offset of the GOT
19961 entry containing the offset of the symbol's address from the TCB,
19962 to be used for initial-exec TLS accesses.
19965 This modifier yields the same value as `hw0_tls_ie', but it also
19966 checks that the value does not overflow.
19969 This modifier is used to load bits 16-31 of the offset of the GOT
19970 entry containing the offset of the symbol's address from the TCB,
19971 to be used for initial-exec TLS accesses. It also checks that the
19972 value does not overflow.
19975 This modifier is used to load bits 0-15 of the offset of the
19976 symbol's address from the TCB, to be used for local-exec TLS
19980 This modifier yields the same value as `hw0_tls_le', but it also
19981 checks that the value does not overflow.
19984 This modifier is used to load bits 16-31 of the offset of the
19985 symbol's address from the TCB, to be used for local-exec TLS
19986 accesses. It also checks that the value does not overflow.
19989 This modifier is used to tag an instrution as the "call" part of a
19990 calling sequence for a TLS GD reference of its operand.
19993 This modifier is used to tag an instruction as the "add" part of a
19994 calling sequence for a TLS GD reference of its operand.
19997 This modifier is used to tag an instruction as the "load" part of a
19998 calling sequence for a TLS IE reference of its operand.
20002 File: as.info, Node: TILE-Gx Directives, Prev: TILE-Gx Syntax, Up: TILE-Gx-Dependent
20004 9.45.3 TILE-Gx Directives
20005 -------------------------
20007 `.align EXPRESSION [, EXPRESSION]'
20008 This is the generic .ALIGN directive. The first argument is the
20009 requested alignment in bytes.
20011 `.allow_suspicious_bundles'
20012 Turns on error checking for combinations of instructions in a
20013 bundle that probably indicate a programming error. This is on by
20016 `.no_allow_suspicious_bundles'
20017 Turns off error checking for combinations of instructions in a
20018 bundle that probably indicate a programming error.
20020 `.require_canonical_reg_names'
20021 Require that canonical register names be used, and emit a warning
20022 if the numeric names are used. This is on by default.
20024 `.no_require_canonical_reg_names'
20025 Permit the use of numeric names for registers that have canonical
20030 File: as.info, Node: TILEPro-Dependent, Next: V850-Dependent, Prev: TILE-Gx-Dependent, Up: Machine Dependencies
20032 9.46 TILEPro Dependent Features
20033 ===============================
20037 * TILEPro Options:: TILEPro Options
20038 * TILEPro Syntax:: TILEPro Syntax
20039 * TILEPro Directives:: TILEPro Directives
20042 File: as.info, Node: TILEPro Options, Next: TILEPro Syntax, Up: TILEPro-Dependent
20047 `as' has no machine-dependent command-line options for TILEPro.
20050 File: as.info, Node: TILEPro Syntax, Next: TILEPro Directives, Prev: TILEPro Options, Up: TILEPro-Dependent
20055 Block comments are delimited by `/*' and `*/'. End of line comments
20056 may be introduced by `#'.
20058 Instructions consist of a leading opcode or macro name followed by
20059 whitespace and an optional comma-separated list of operands:
20061 OPCODE [OPERAND, ...]
20063 Instructions must be separated by a newline or semicolon.
20065 There are two ways to write code: either write naked instructions,
20066 which the assembler is free to combine into VLIW bundles, or specify
20067 the VLIW bundles explicitly.
20069 Bundles are specified using curly braces:
20071 { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 }
20073 A bundle can span multiple lines. If you want to put multiple
20074 instructions on a line, whether in a bundle or not, you need to
20075 separate them with semicolons as in this example.
20077 A bundle may contain one or more instructions, up to the limit
20078 specified by the ISA (currently three). If fewer instructions are
20079 specified than the hardware supports in a bundle, the assembler inserts
20080 `fnop' instructions automatically.
20082 The assembler will prefer to preserve the ordering of instructions
20083 within the bundle, putting the first instruction in a lower-numbered
20084 pipeline than the next one, etc. This fact, combined with the optional
20085 use of explicit `fnop' or `nop' instructions, allows precise control
20086 over which pipeline executes each instruction.
20088 If the instructions cannot be bundled in the listed order, the
20089 assembler will automatically try to find a valid pipeline assignment.
20090 If there is no way to bundle the instructions together, the assembler
20093 The assembler does not yet auto-bundle (automatically combine
20094 multiple instructions into one bundle), but it reserves the right to do
20095 so in the future. If you want to force an instruction to run by
20096 itself, put it in a bundle explicitly with curly braces and use `nop'
20097 instructions (not `fnop') to fill the remaining pipeline slots in that
20102 * TILEPro Opcodes:: Opcode Naming Conventions.
20103 * TILEPro Registers:: Register Naming.
20104 * TILEPro Modifiers:: Symbolic Operand Modifiers.
20107 File: as.info, Node: TILEPro Opcodes, Next: TILEPro Registers, Up: TILEPro Syntax
20109 9.46.2.1 Opcode Names
20110 .....................
20112 For a complete list of opcodes and descriptions of their semantics, see
20113 `TILE Processor User Architecture Manual', available upon request at
20117 File: as.info, Node: TILEPro Registers, Next: TILEPro Modifiers, Prev: TILEPro Opcodes, Up: TILEPro Syntax
20119 9.46.2.2 Register Names
20120 .......................
20122 General-purpose registers are represented by predefined symbols of the
20123 form `rN', where N represents a number between `0' and `63'. However,
20124 the following registers have canonical names that must be used instead:
20157 The assembler will emit a warning if a numeric name is used instead
20158 of the canonical name. The `.no_require_canonical_reg_names' assembler
20159 pseudo-op turns off this warning. `.require_canonical_reg_names' turns
20163 File: as.info, Node: TILEPro Modifiers, Prev: TILEPro Registers, Up: TILEPro Syntax
20165 9.46.2.3 Symbolic Operand Modifiers
20166 ...................................
20168 The assembler supports several modifiers when using symbol addresses in
20169 TILEPro instruction operands. The general syntax is the following:
20173 The following modifiers are supported:
20176 This modifier is used to load the low 16 bits of the symbol's
20177 address, sign-extended to a 32-bit value (sign-extension allows it
20178 to be range-checked against signed 16 bit immediate operands
20179 without complaint).
20182 This modifier is used to load the high 16 bits of the symbol's
20183 address, also sign-extended to a 32-bit value.
20186 `ha16(N)' is identical to `hi16(N)', except if `lo16(N)' is
20187 negative it adds one to the `hi16(N)' value. This way `lo16' and
20188 `ha16' can be added to create any 32-bit value using `auli'. For
20189 example, here is how you move an arbitrary 32-bit address into r3:
20191 moveli r3, lo16(sym)
20192 auli r3, r3, ha16(sym)
20195 This modifier is used to load the offset of the GOT entry
20196 corresponding to the symbol.
20199 This modifier is used to load the sign-extended low 16 bits of the
20200 offset of the GOT entry corresponding to the symbol.
20203 This modifier is used to load the sign-extended high 16 bits of the
20204 offset of the GOT entry corresponding to the symbol.
20207 This modifier is like `got_hi16', but it adds one if `got_lo16' of
20208 the input value is negative.
20211 This modifier is used for function symbols. It causes a
20212 _procedure linkage table_, an array of code stubs, to be created
20213 at the time the shared object is created or linked against,
20214 together with a global offset table entry. The value is a
20215 pc-relative offset to the corresponding stub code in the procedure
20216 linkage table. This arrangement causes the run-time symbol
20217 resolver to be called to look up and set the value of the symbol
20218 the first time the function is called (at latest; depending
20219 environment variables). It is only safe to leave the symbol
20220 unresolved this way if all references are function calls.
20223 This modifier is used to load the offset of the GOT entry of the
20224 symbol's TLS descriptor, to be used for general-dynamic TLS
20228 This modifier is used to load the sign-extended low 16 bits of the
20229 offset of the GOT entry of the symbol's TLS descriptor, to be used
20230 for general dynamic TLS accesses.
20233 This modifier is used to load the sign-extended high 16 bits of the
20234 offset of the GOT entry of the symbol's TLS descriptor, to be used
20235 for general dynamic TLS accesses.
20238 This modifier is like `tls_gd_hi16', but it adds one to the value
20239 if `tls_gd_lo16' of the input value is negative.
20242 This modifier is used to load the offset of the GOT entry
20243 containing the offset of the symbol's address from the TCB, to be
20244 used for initial-exec TLS accesses.
20247 This modifier is used to load the low 16 bits of the offset of the
20248 GOT entry containing the offset of the symbol's address from the
20249 TCB, to be used for initial-exec TLS accesses.
20252 This modifier is used to load the high 16 bits of the offset of the
20253 GOT entry containing the offset of the symbol's address from the
20254 TCB, to be used for initial-exec TLS accesses.
20257 This modifier is like `tls_ie_hi16', but it adds one to the value
20258 if `tls_ie_lo16' of the input value is negative.
20261 This modifier is used to load the offset of the symbol's address
20262 from the TCB, to be used for local-exec TLS accesses.
20265 This modifier is used to load the low 16 bits of the offset of the
20266 symbol's address from the TCB, to be used for local-exec TLS
20270 This modifier is used to load the high 16 bits of the offset of the
20271 symbol's address from the TCB, to be used for local-exec TLS
20275 This modifier is like `tls_le_hi16', but it adds one to the value
20276 if `tls_le_lo16' of the input value is negative.
20279 This modifier is used to tag an instrution as the "call" part of a
20280 calling sequence for a TLS GD reference of its operand.
20283 This modifier is used to tag an instruction as the "add" part of a
20284 calling sequence for a TLS GD reference of its operand.
20287 This modifier is used to tag an instruction as the "load" part of a
20288 calling sequence for a TLS IE reference of its operand.
20292 File: as.info, Node: TILEPro Directives, Prev: TILEPro Syntax, Up: TILEPro-Dependent
20294 9.46.3 TILEPro Directives
20295 -------------------------
20297 `.align EXPRESSION [, EXPRESSION]'
20298 This is the generic .ALIGN directive. The first argument is the
20299 requested alignment in bytes.
20301 `.allow_suspicious_bundles'
20302 Turns on error checking for combinations of instructions in a
20303 bundle that probably indicate a programming error. This is on by
20306 `.no_allow_suspicious_bundles'
20307 Turns off error checking for combinations of instructions in a
20308 bundle that probably indicate a programming error.
20310 `.require_canonical_reg_names'
20311 Require that canonical register names be used, and emit a warning
20312 if the numeric names are used. This is on by default.
20314 `.no_require_canonical_reg_names'
20315 Permit the use of numeric names for registers that have canonical
20320 File: as.info, Node: Z80-Dependent, Next: Z8000-Dependent, Prev: Xtensa-Dependent, Up: Machine Dependencies
20322 9.47 Z80 Dependent Features
20323 ===========================
20327 * Z80 Options:: Options
20328 * Z80 Syntax:: Syntax
20329 * Z80 Floating Point:: Floating Point
20330 * Z80 Directives:: Z80 Machine Directives
20331 * Z80 Opcodes:: Opcodes
20334 File: as.info, Node: Z80 Options, Next: Z80 Syntax, Up: Z80-Dependent
20339 The Zilog Z80 and Ascii R800 version of `as' have a few machine
20342 Produce code for the Z80 processor. There are additional options to
20343 request warnings and error messages for undocumented instructions.
20345 `-ignore-undocumented-instructions'
20347 Silently assemble undocumented Z80-instructions that have been
20348 adopted as documented R800-instructions.
20350 `-ignore-unportable-instructions'
20352 Silently assemble all undocumented Z80-instructions.
20354 `-warn-undocumented-instructions'
20356 Issue warnings for undocumented Z80-instructions that work on
20357 R800, do not assemble other undocumented instructions without
20360 `-warn-unportable-instructions'
20362 Issue warnings for other undocumented Z80-instructions, do not
20363 treat any undocumented instructions as errors.
20365 `-forbid-undocumented-instructions'
20367 Treat all undocumented z80-instructions as errors.
20369 `-forbid-unportable-instructions'
20371 Treat undocumented z80-instructions that do not work on R800 as
20375 Produce code for the R800 processor. The assembler does not support
20376 undocumented instructions for the R800. In line with common
20377 practice, `as' uses Z80 instruction names for the R800 processor,
20378 as far as they exist.
20381 File: as.info, Node: Z80 Syntax, Next: Z80 Floating Point, Prev: Z80 Options, Up: Z80-Dependent
20386 The assembler syntax closely follows the 'Z80 family CPU User Manual' by
20387 Zilog. In expressions a single `=' may be used as "is equal to"
20388 comparison operator.
20390 Suffices can be used to indicate the radix of integer constants; `H'
20391 or `h' for hexadecimal, `D' or `d' for decimal, `Q', `O', `q' or `o'
20392 for octal, and `B' for binary.
20394 The suffix `b' denotes a backreference to local label.
20398 * Z80-Chars:: Special Characters
20399 * Z80-Regs:: Register Names
20400 * Z80-Case:: Case Sensitivity
20403 File: as.info, Node: Z80-Chars, Next: Z80-Regs, Up: Z80 Syntax
20405 9.47.2.1 Special Characters
20406 ...........................
20408 The semicolon `;' is the line comment character;
20410 If a `#' appears as the first character of a line then the whole
20411 line is treated as a comment, but in this case the line could also be a
20412 logical line number directive (*note Comments::) or a preprocessor
20413 control command (*note Preprocessing::).
20415 The Z80 assembler does not support a line separator character.
20417 The dollar sign `$' can be used as a prefix for hexadecimal numbers
20418 and as a symbol denoting the current location counter.
20420 A backslash `\' is an ordinary character for the Z80 assembler.
20422 The single quote `'' must be followed by a closing quote. If there
20423 is one character in between, it is a character constant, otherwise it is
20427 File: as.info, Node: Z80-Regs, Next: Z80-Case, Prev: Z80-Chars, Up: Z80 Syntax
20429 9.47.2.2 Register Names
20430 .......................
20432 The registers are referred to with the letters assigned to them by
20433 Zilog. In addition `as' recognizes `ixl' and `ixh' as the least and
20434 most significant octet in `ix', and similarly `iyl' and `iyh' as parts
20438 File: as.info, Node: Z80-Case, Prev: Z80-Regs, Up: Z80 Syntax
20440 9.47.2.3 Case Sensitivity
20441 .........................
20443 Upper and lower case are equivalent in register names, opcodes,
20444 condition codes and assembler directives. The case of letters is
20445 significant in labels and symbol names. The case is also important to
20446 distinguish the suffix `b' for a backward reference to a local label
20447 from the suffix `B' for a number in binary notation.
20450 File: as.info, Node: Z80 Floating Point, Next: Z80 Directives, Prev: Z80 Syntax, Up: Z80-Dependent
20452 9.47.3 Floating Point
20453 ---------------------
20455 Floating-point numbers are not supported.
20458 File: as.info, Node: Z80 Directives, Next: Z80 Opcodes, Prev: Z80 Floating Point, Up: Z80-Dependent
20460 9.47.4 Z80 Assembler Directives
20461 -------------------------------
20463 `as' for the Z80 supports some additional directives for compatibility
20464 with other assemblers.
20466 These are the additional directives in `as' for the Z80:
20468 `db EXPRESSION|STRING[,EXPRESSION|STRING...]'
20469 `defb EXPRESSION|STRING[,EXPRESSION|STRING...]'
20470 For each STRING the characters are copied to the object file, for
20471 each other EXPRESSION the value is stored in one byte. A warning
20472 is issued in case of an overflow.
20474 `dw EXPRESSION[,EXPRESSION...]'
20475 `defw EXPRESSION[,EXPRESSION...]'
20476 For each EXPRESSION the value is stored in two bytes, ignoring
20479 `d24 EXPRESSION[,EXPRESSION...]'
20480 `def24 EXPRESSION[,EXPRESSION...]'
20481 For each EXPRESSION the value is stored in three bytes, ignoring
20484 `d32 EXPRESSION[,EXPRESSION...]'
20485 `def32 EXPRESSION[,EXPRESSION...]'
20486 For each EXPRESSION the value is stored in four bytes, ignoring
20489 `ds COUNT[, VALUE]'
20490 `defs COUNT[, VALUE]'
20491 Fill COUNT bytes in the object file with VALUE, if VALUE is
20492 omitted it defaults to zero.
20494 `SYMBOL equ EXPRESSION'
20495 `SYMBOL defl EXPRESSION'
20496 These directives set the value of SYMBOL to EXPRESSION. If `equ'
20497 is used, it is an error if SYMBOL is already defined. Symbols
20498 defined with `equ' are not protected from redefinition.
20501 This is a normal instruction on Z80, and not an assembler
20505 A synonym for *Note Section::, no second argument should be given.
20509 File: as.info, Node: Z80 Opcodes, Prev: Z80 Directives, Up: Z80-Dependent
20514 In line with common practice, Z80 mnemonics are used for both the Z80
20517 In many instructions it is possible to use one of the half index
20518 registers (`ixl',`ixh',`iyl',`iyh') in stead of an 8-bit general
20519 purpose register. This yields instructions that are documented on the
20520 R800 and undocumented on the Z80. Similarly `in f,(c)' is documented
20521 on the R800 and undocumented on the Z80.
20523 The assembler also supports the following undocumented
20524 Z80-instructions, that have not been adopted in the R800 instruction
20527 Sends zero to the port pointed to by register c.
20530 Equivalent to `M = (M<<1)+1', the operand M can be any operand
20531 that is valid for `sla'. One can use `sll' as a synonym for `sli'.
20534 This is equivalent to
20540 The operation `OPC' may be any of `res B,', `set B,', `rl', `rlc',
20541 `rr', `rrc', `sla', `sli', `sra' and `srl', and the register `R'
20542 may be any of `a', `b', `c', `d', `e', `h' and `l'.
20545 As above, but with `iy' instead of `ix'.
20547 The web site at `http://www.z80.info' is a good starting place to
20548 find more information on programming the Z80.
20551 File: as.info, Node: Z8000-Dependent, Next: Vax-Dependent, Prev: Z80-Dependent, Up: Machine Dependencies
20553 9.48 Z8000 Dependent Features
20554 =============================
20556 The Z8000 as supports both members of the Z8000 family: the
20557 unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with
20560 When the assembler is in unsegmented mode (specified with the
20561 `unsegm' directive), an address takes up one word (16 bit) sized
20562 register. When the assembler is in segmented mode (specified with the
20563 `segm' directive), a 24-bit address takes up a long (32 bit) register.
20564 *Note Assembler Directives for the Z8000: Z8000 Directives, for a list
20565 of other Z8000 specific assembler directives.
20569 * Z8000 Options:: Command-line options for the Z8000
20570 * Z8000 Syntax:: Assembler syntax for the Z8000
20571 * Z8000 Directives:: Special directives for the Z8000
20572 * Z8000 Opcodes:: Opcodes
20575 File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent
20581 Generate segmented code by default.
20584 Generate unsegmented code by default.
20587 File: as.info, Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent
20594 * Z8000-Chars:: Special Characters
20595 * Z8000-Regs:: Register Names
20596 * Z8000-Addressing:: Addressing Modes
20599 File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax
20601 9.48.2.1 Special Characters
20602 ...........................
20604 `!' is the line comment character.
20606 If a `#' appears as the first character of a line then the whole
20607 line is treated as a comment, but in this case the line could also be a
20608 logical line number directive (*note Comments::) or a preprocessor
20609 control command (*note Preprocessing::).
20611 You can use `;' instead of a newline to separate statements.
20614 File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax
20616 9.48.2.2 Register Names
20617 .......................
20619 The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer
20620 to different sized groups of registers by register number, with the
20621 prefix `r' for 16 bit registers, `rr' for 32 bit registers and `rq' for
20622 64 bit registers. You can also refer to the contents of the first
20623 eight (of the sixteen 16 bit registers) by bytes. They are named `rlN'
20627 rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3
20628 rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7
20631 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
20633 _long word registers_
20634 rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14
20636 _quad word registers_
20640 File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax
20642 9.48.2.3 Addressing Modes
20643 .........................
20645 as understands the following addressing modes for the Z8000:
20652 Register direct: 8bit, 16bit, 32bit, and 64bit registers.
20656 Indirect register: @rrN in segmented mode, @rN in unsegmented
20660 Direct: the 16 bit or 24 bit address (depending on whether the
20661 assembler is in segmented or unsegmented mode) of the operand is
20662 in the instruction.
20665 Indexed: the 16 or 24 bit address is added to the 16 bit register
20666 to produce the final address in memory of the operand.
20670 Base Address: the 16 or 24 bit register is added to the 16 bit sign
20671 extended immediate displacement to produce the final address in
20672 memory of the operand.
20676 Base Index: the 16 or 24 bit register rN or rrN is added to the
20677 sign extended 16 bit index register rM to produce the final
20678 address in memory of the operand.
20684 File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent
20686 9.48.3 Assembler Directives for the Z8000
20687 -----------------------------------------
20689 The Z8000 port of as includes additional assembler directives, for
20690 compatibility with other Z8000 assemblers. These do not begin with `.'
20691 (unlike the ordinary as directives).
20695 Generate code for the segmented Z8001.
20699 Generate code for the unsegmented Z8002.
20702 Synonym for `.file'
20705 Synonym for `.global'
20708 Synonym for `.word'
20711 Synonym for `.long'
20714 Synonym for `.byte'
20717 Assemble a string. `sval' expects one string literal, delimited by
20718 single quotes. It assembles each byte of the string into
20719 consecutive addresses. You can use the escape sequence `%XX'
20720 (where XX represents a two-digit hexadecimal number) to represent
20721 the character whose ASCII value is XX. Use this feature to
20722 describe single quote and other characters that may not appear in
20723 string literals as themselves. For example, the C statement
20724 `char *a = "he said \"it's 50% off\"";' is represented in Z8000
20725 assembly language (shown with the assembler output in hex at the
20728 68652073 sval 'he said %22it%27s 50%25 off%22%00'
20736 synonym for `.section'
20739 synonym for `.space'
20742 special case of `.align'; aligns output to even byte boundary.
20745 File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent
20750 For detailed information on the Z8000 machine instruction set, see
20751 `Z8000 Technical Manual'.
20753 The following table summarizes the opcodes and their arguments:
20755 rs 16 bit source register
20756 rd 16 bit destination register
20757 rbs 8 bit source register
20758 rbd 8 bit destination register
20759 rrs 32 bit source register
20760 rrd 32 bit destination register
20761 rqs 64 bit source register
20762 rqd 64 bit destination register
20763 addr 16/24 bit address
20766 adc rd,rs clrb addr cpsir @rd,@rs,rr,cc
20767 adcb rbd,rbs clrb addr(rd) cpsirb @rd,@rs,rr,cc
20768 add rd,@rs clrb rbd dab rbd
20769 add rd,addr com @rd dbjnz rbd,disp7
20770 add rd,addr(rs) com addr dec @rd,imm4m1
20771 add rd,imm16 com addr(rd) dec addr(rd),imm4m1
20772 add rd,rs com rd dec addr,imm4m1
20773 addb rbd,@rs comb @rd dec rd,imm4m1
20774 addb rbd,addr comb addr decb @rd,imm4m1
20775 addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1
20776 addb rbd,imm8 comb rbd decb addr,imm4m1
20777 addb rbd,rbs comflg flags decb rbd,imm4m1
20778 addl rrd,@rs cp @rd,imm16 di i2
20779 addl rrd,addr cp addr(rd),imm16 div rrd,@rs
20780 addl rrd,addr(rs) cp addr,imm16 div rrd,addr
20781 addl rrd,imm32 cp rd,@rs div rrd,addr(rs)
20782 addl rrd,rrs cp rd,addr div rrd,imm16
20783 and rd,@rs cp rd,addr(rs) div rrd,rs
20784 and rd,addr cp rd,imm16 divl rqd,@rs
20785 and rd,addr(rs) cp rd,rs divl rqd,addr
20786 and rd,imm16 cpb @rd,imm8 divl rqd,addr(rs)
20787 and rd,rs cpb addr(rd),imm8 divl rqd,imm32
20788 andb rbd,@rs cpb addr,imm8 divl rqd,rrs
20789 andb rbd,addr cpb rbd,@rs djnz rd,disp7
20790 andb rbd,addr(rs) cpb rbd,addr ei i2
20791 andb rbd,imm8 cpb rbd,addr(rs) ex rd,@rs
20792 andb rbd,rbs cpb rbd,imm8 ex rd,addr
20793 bit @rd,imm4 cpb rbd,rbs ex rd,addr(rs)
20794 bit addr(rd),imm4 cpd rd,@rs,rr,cc ex rd,rs
20795 bit addr,imm4 cpdb rbd,@rs,rr,cc exb rbd,@rs
20796 bit rd,imm4 cpdr rd,@rs,rr,cc exb rbd,addr
20797 bit rd,rs cpdrb rbd,@rs,rr,cc exb rbd,addr(rs)
20798 bitb @rd,imm4 cpi rd,@rs,rr,cc exb rbd,rbs
20799 bitb addr(rd),imm4 cpib rbd,@rs,rr,cc ext0e imm8
20800 bitb addr,imm4 cpir rd,@rs,rr,cc ext0f imm8
20801 bitb rbd,imm4 cpirb rbd,@rs,rr,cc ext8e imm8
20802 bitb rbd,rs cpl rrd,@rs ext8f imm8
20803 bpt cpl rrd,addr exts rrd
20804 call @rd cpl rrd,addr(rs) extsb rd
20805 call addr cpl rrd,imm32 extsl rqd
20806 call addr(rd) cpl rrd,rrs halt
20807 calr disp12 cpsd @rd,@rs,rr,cc in rd,@rs
20808 clr @rd cpsdb @rd,@rs,rr,cc in rd,imm16
20809 clr addr cpsdr @rd,@rs,rr,cc inb rbd,@rs
20810 clr addr(rd) cpsdrb @rd,@rs,rr,cc inb rbd,imm16
20811 clr rd cpsi @rd,@rs,rr,cc inc @rd,imm4m1
20812 clrb @rd cpsib @rd,@rs,rr,cc inc addr(rd),imm4m1
20813 inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs)
20814 inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16
20815 incb @rd,imm4m1 ldb rd(rx),rbs mult rrd,rs
20816 incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@rs
20817 incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr
20818 incb rbd,imm4m1 ldd @rs,@rd,rr multl rqd,addr(rs)
20819 ind @rd,@rs,ra lddb @rs,@rd,rr multl rqd,imm32
20820 indb @rd,@rs,rba lddr @rs,@rd,rr multl rqd,rrs
20821 inib @rd,@rs,ra lddrb @rs,@rd,rr neg @rd
20822 inibr @rd,@rs,ra ldi @rd,@rs,rr neg addr
20823 iret ldib @rd,@rs,rr neg addr(rd)
20824 jp cc,@rd ldir @rd,@rs,rr neg rd
20825 jp cc,addr ldirb @rd,@rs,rr negb @rd
20826 jp cc,addr(rd) ldk rd,imm4 negb addr
20827 jr cc,disp8 ldl @rd,rrs negb addr(rd)
20828 ld @rd,imm16 ldl addr(rd),rrs negb rbd
20829 ld @rd,rs ldl addr,rrs nop
20830 ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@rs
20831 ld addr(rd),rs ldl rd(rx),rrs or rd,addr
20832 ld addr,imm16 ldl rrd,@rs or rd,addr(rs)
20833 ld addr,rs ldl rrd,addr or rd,imm16
20834 ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs
20835 ld rd(rx),rs ldl rrd,imm32 orb rbd,@rs
20836 ld rd,@rs ldl rrd,rrs orb rbd,addr
20837 ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs)
20838 ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8
20839 ld rd,imm16 ldm @rd,rs,n orb rbd,rbs
20840 ld rd,rs ldm addr(rd),rs,n out @rd,rs
20841 ld rd,rs(imm16) ldm addr,rs,n out imm16,rs
20842 ld rd,rs(rx) ldm rd,@rs,n outb @rd,rbs
20843 lda rd,addr ldm rd,addr(rs),n outb imm16,rbs
20844 lda rd,addr(rs) ldm rd,addr,n outd @rd,@rs,ra
20845 lda rd,rs(imm16) ldps @rs outdb @rd,@rs,rba
20846 lda rd,rs(rx) ldps addr outib @rd,@rs,ra
20847 ldar rd,disp16 ldps addr(rs) outibr @rd,@rs,ra
20848 ldb @rd,imm8 ldr disp16,rs pop @rd,@rs
20849 ldb @rd,rbs ldr rd,disp16 pop addr(rd),@rs
20850 ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@rs
20851 ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@rs
20852 ldb addr,imm8 ldrl disp16,rrs popl @rd,@rs
20853 ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@rs
20854 ldb rbd,@rs mbit popl addr,@rs
20855 ldb rbd,addr mreq rd popl rrd,@rs
20856 ldb rbd,addr(rs) mres push @rd,@rs
20857 ldb rbd,imm8 mset push @rd,addr
20858 ldb rbd,rbs mult rrd,@rs push @rd,addr(rs)
20859 ldb rbd,rs(imm16) mult rrd,addr push @rd,imm16
20860 push @rd,rs set addr,imm4 subl rrd,imm32
20861 pushl @rd,@rs set rd,imm4 subl rrd,rrs
20862 pushl @rd,addr set rd,rs tcc cc,rd
20863 pushl @rd,addr(rs) setb @rd,imm4 tccb cc,rbd
20864 pushl @rd,rrs setb addr(rd),imm4 test @rd
20865 res @rd,imm4 setb addr,imm4 test addr
20866 res addr(rd),imm4 setb rbd,imm4 test addr(rd)
20867 res addr,imm4 setb rbd,rs test rd
20868 res rd,imm4 setflg imm4 testb @rd
20869 res rd,rs sinb rbd,imm16 testb addr
20870 resb @rd,imm4 sinb rd,imm16 testb addr(rd)
20871 resb addr(rd),imm4 sind @rd,@rs,ra testb rbd
20872 resb addr,imm4 sindb @rd,@rs,rba testl @rd
20873 resb rbd,imm4 sinib @rd,@rs,ra testl addr
20874 resb rbd,rs sinibr @rd,@rs,ra testl addr(rd)
20875 resflg imm4 sla rd,imm8 testl rrd
20876 ret cc slab rbd,imm8 trdb @rd,@rs,rba
20877 rl rd,imm1or2 slal rrd,imm8 trdrb @rd,@rs,rba
20878 rlb rbd,imm1or2 sll rd,imm8 trib @rd,@rs,rbr
20879 rlc rd,imm1or2 sllb rbd,imm8 trirb @rd,@rs,rbr
20880 rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @ra,@rb,rbr
20881 rldb rbb,rba sout imm16,rs trtib @ra,@rb,rr
20882 rr rd,imm1or2 soutb imm16,rbs trtirb @ra,@rb,rbr
20883 rrb rbd,imm1or2 soutd @rd,@rs,ra trtrb @ra,@rb,rbr
20884 rrc rd,imm1or2 soutdb @rd,@rs,rba tset @rd
20885 rrcb rbd,imm1or2 soutib @rd,@rs,ra tset addr
20886 rrdb rbb,rba soutibr @rd,@rs,ra tset addr(rd)
20887 rsvd36 sra rd,imm8 tset rd
20888 rsvd38 srab rbd,imm8 tsetb @rd
20889 rsvd78 sral rrd,imm8 tsetb addr
20890 rsvd7e srl rd,imm8 tsetb addr(rd)
20891 rsvd9d srlb rbd,imm8 tsetb rbd
20892 rsvd9f srll rrd,imm8 xor rd,@rs
20893 rsvdb9 sub rd,@rs xor rd,addr
20894 rsvdbf sub rd,addr xor rd,addr(rs)
20895 sbc rd,rs sub rd,addr(rs) xor rd,imm16
20896 sbcb rbd,rbs sub rd,imm16 xor rd,rs
20897 sc imm8 sub rd,rs xorb rbd,@rs
20898 sda rd,rs subb rbd,@rs xorb rbd,addr
20899 sdab rbd,rs subb rbd,addr xorb rbd,addr(rs)
20900 sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8
20901 sdl rd,rs subb rbd,imm8 xorb rbd,rbs
20902 sdlb rbd,rs subb rbd,rbs xorb rbd,rbs
20903 sdll rrd,rs subl rrd,@rs
20904 set @rd,imm4 subl rrd,addr
20905 set addr(rd),imm4 subl rrd,addr(rs)
20908 File: as.info, Node: Vax-Dependent, Prev: Z8000-Dependent, Up: Machine Dependencies
20910 9.49 VAX Dependent Features
20911 ===========================
20915 * VAX-Opts:: VAX Command-Line Options
20916 * VAX-float:: VAX Floating Point
20917 * VAX-directives:: Vax Machine Directives
20918 * VAX-opcodes:: VAX Opcodes
20919 * VAX-branch:: VAX Branch Improvement
20920 * VAX-operands:: VAX Operands
20921 * VAX-no:: Not Supported on VAX
20922 * VAX-Syntax:: VAX Syntax
20925 File: as.info, Node: VAX-Opts, Next: VAX-float, Up: Vax-Dependent
20927 9.49.1 VAX Command-Line Options
20928 -------------------------------
20930 The Vax version of `as' accepts any of the following options, gives a
20931 warning message that the option was ignored and proceeds. These
20932 options are for compatibility with scripts designed for other people's
20936 ``-S' (Symbol Table)'
20937 ``-T' (Token Trace)'
20938 These are obsolete options used to debug old assemblers.
20940 ``-d' (Displacement size for JUMPs)'
20941 This option expects a number following the `-d'. Like options
20942 that expect filenames, the number may immediately follow the `-d'
20943 (old standard) or constitute the whole of the command line
20944 argument that follows `-d' (GNU standard).
20946 ``-V' (Virtualize Interpass Temporary File)'
20947 Some other assemblers use a temporary file. This option commanded
20948 them to keep the information in active memory rather than in a
20949 disk file. `as' always does this, so this option is redundant.
20951 ``-J' (JUMPify Longer Branches)'
20952 Many 32-bit computers permit a variety of branch instructions to
20953 do the same job. Some of these instructions are short (and fast)
20954 but have a limited range; others are long (and slow) but can
20955 branch anywhere in virtual memory. Often there are 3 flavors of
20956 branch: short, medium and long. Some other assemblers would emit
20957 short and medium branches, unless told by this option to emit
20958 short and long branches.
20960 ``-t' (Temporary File Directory)'
20961 Some other assemblers may use a temporary file, and this option
20962 takes a filename being the directory to site the temporary file.
20963 Since `as' does not use a temporary disk file, this option makes
20964 no difference. `-t' needs exactly one filename.
20966 The Vax version of the assembler accepts additional options when
20970 External symbol or section (used for global variables) names are
20971 not case sensitive on VAX/VMS and always mapped to upper case.
20972 This is contrary to the C language definition which explicitly
20973 distinguishes upper and lower case. To implement a standard
20974 conforming C compiler, names must be changed (mapped) to preserve
20975 the case information. The default mapping is to convert all lower
20976 case characters to uppercase and adding an underscore followed by
20977 a 6 digit hex value, representing a 24 digit binary value. The
20978 one digits in the binary value represent which characters are
20979 uppercase in the original symbol name.
20981 The `-h N' option determines how we map names. This takes several
20982 values. No `-h' switch at all allows case hacking as described
20983 above. A value of zero (`-h0') implies names should be upper
20984 case, and inhibits the case hack. A value of 2 (`-h2') implies
20985 names should be all lower case, with no case hack. A value of 3
20986 (`-h3') implies that case should be preserved. The value 1 is
20987 unused. The `-H' option directs `as' to display every mapped
20988 symbol during assembly.
20990 Symbols whose names include a dollar sign `$' are exceptions to the
20991 general name mapping. These symbols are normally only used to
20992 reference VMS library names. Such symbols are always mapped to
20996 The `-+' option causes `as' to truncate any symbol name larger
20997 than 31 characters. The `-+' option also prevents some code
20998 following the `_main' symbol normally added to make the object
20999 file compatible with Vax-11 "C".
21002 This option is ignored for backward compatibility with `as'
21006 The `-H' option causes `as' to print every symbol which was
21007 changed by case mapping.
21010 File: as.info, Node: VAX-float, Next: VAX-directives, Prev: VAX-Opts, Up: Vax-Dependent
21012 9.49.2 VAX Floating Point
21013 -------------------------
21015 Conversion of flonums to floating point is correct, and compatible with
21016 previous assemblers. Rounding is towards zero if the remainder is
21017 exactly half the least significant bit.
21019 `D', `F', `G' and `H' floating point formats are understood.
21021 Immediate floating literals (_e.g._ `S`$6.9') are rendered
21022 correctly. Again, rounding is towards zero in the boundary case.
21024 The `.float' directive produces `f' format numbers. The `.double'
21025 directive produces `d' format numbers.
21028 File: as.info, Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: Vax-Dependent
21030 9.49.3 Vax Machine Directives
21031 -----------------------------
21033 The Vax version of the assembler supports four directives for
21034 generating Vax floating point constants. They are described in the
21038 This expects zero or more flonums, separated by commas, and
21039 assembles Vax `d' format 64-bit floating point constants.
21042 This expects zero or more flonums, separated by commas, and
21043 assembles Vax `f' format 32-bit floating point constants.
21046 This expects zero or more flonums, separated by commas, and
21047 assembles Vax `g' format 64-bit floating point constants.
21050 This expects zero or more flonums, separated by commas, and
21051 assembles Vax `h' format 128-bit floating point constants.
21055 File: as.info, Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up: Vax-Dependent
21060 All DEC mnemonics are supported. Beware that `case...' instructions
21061 have exactly 3 operands. The dispatch table that follows the `case...'
21062 instruction should be made with `.word' statements. This is compatible
21063 with all unix assemblers we know of.
21066 File: as.info, Node: VAX-branch, Next: VAX-operands, Prev: VAX-opcodes, Up: Vax-Dependent
21068 9.49.5 VAX Branch Improvement
21069 -----------------------------
21071 Certain pseudo opcodes are permitted. They are for branch
21072 instructions. They expand to the shortest branch instruction that
21073 reaches the target. Generally these mnemonics are made by substituting
21074 `j' for `b' at the start of a DEC mnemonic. This feature is included
21075 both for compatibility and to help compilers. If you do not need this
21076 feature, avoid these opcodes. Here are the mnemonics, and the code
21077 they can expand into.
21080 `Jsb' is already an instruction mnemonic, so we chose `jbsb'.
21081 (byte displacement)
21084 (word displacement)
21087 (long displacement)
21092 Unconditional branch.
21093 (byte displacement)
21096 (word displacement)
21099 (long displacement)
21103 COND may be any one of the conditional branches `neq', `nequ',
21104 `eql', `eqlu', `gtr', `geq', `lss', `gtru', `lequ', `vc', `vs',
21105 `gequ', `cc', `lssu', `cs'. COND may also be one of the bit tests
21106 `bs', `bc', `bss', `bcs', `bsc', `bcc', `bssi', `bcci', `lbs',
21107 `lbc'. NOTCOND is the opposite condition to COND.
21108 (byte displacement)
21111 (word displacement)
21112 `bNOTCOND foo ; brw ... ; foo:'
21114 (long displacement)
21115 `bNOTCOND foo ; jmp ... ; foo:'
21118 X may be one of `b d f g h l w'.
21119 (word displacement)
21122 (long displacement)
21129 YYY may be one of `lss leq'.
21132 ZZZ may be one of `geq gtr'.
21133 (byte displacement)
21136 (word displacement)
21139 foo: brw DESTINATION ;
21142 (long displacement)
21145 foo: jmp DESTINATION ;
21153 (byte displacement)
21156 (word displacement)
21159 foo: brw DESTINATION ;
21162 (long displacement)
21165 foo: jmp DESTINATION ;
21169 File: as.info, Node: VAX-operands, Next: VAX-no, Prev: VAX-branch, Up: Vax-Dependent
21171 9.49.6 VAX Operands
21172 -------------------
21174 The immediate character is `$' for Unix compatibility, not `#' as DEC
21177 The indirect character is `*' for Unix compatibility, not `@' as DEC
21180 The displacement sizing character is ``' (an accent grave) for Unix
21181 compatibility, not `^' as DEC writes it. The letter preceding ``' may
21182 have either case. `G' is not understood, but all other letters (`b i l
21183 s w') are understood.
21185 Register names understood are `r0 r1 r2 ... r15 ap fp sp pc'. Upper
21186 and lower case letters are equivalent.
21191 Any expression is permitted in an operand. Operands are comma
21195 File: as.info, Node: VAX-no, Next: VAX-Syntax, Prev: VAX-operands, Up: Vax-Dependent
21197 9.49.7 Not Supported on VAX
21198 ---------------------------
21200 Vax bit fields can not be assembled with `as'. Someone can add the
21201 required code if they really need it.
21204 File: as.info, Node: VAX-Syntax, Prev: VAX-no, Up: Vax-Dependent
21211 * VAX-Chars:: Special Characters
21214 File: as.info, Node: VAX-Chars, Up: VAX-Syntax
21216 9.49.8.1 Special Characters
21217 ...........................
21219 The presence of a `#' appearing anywhere on a line indicates the start
21220 of a comment that extends to the end of that line.
21222 If a `#' appears as the first character of a line then the whole
21223 line is treated as a comment, but in this case the line can also be a
21224 logical line number directive (*note Comments::) or a preprocessor
21225 control command (*note Preprocessing::).
21227 The `;' character can be used to separate statements on the same
21231 File: as.info, Node: V850-Dependent, Next: XGATE-Dependent, Prev: TILEPro-Dependent, Up: Machine Dependencies
21233 9.50 v850 Dependent Features
21234 ============================
21238 * V850 Options:: Options
21239 * V850 Syntax:: Syntax
21240 * V850 Floating Point:: Floating Point
21241 * V850 Directives:: V850 Machine Directives
21242 * V850 Opcodes:: Opcodes
21245 File: as.info, Node: V850 Options, Next: V850 Syntax, Up: V850-Dependent
21250 `as' supports the following additional command-line options for the
21251 V850 processor family:
21253 `-wsigned_overflow'
21254 Causes warnings to be produced when signed immediate values
21255 overflow the space available for then within their opcodes. By
21256 default this option is disabled as it is possible to receive
21257 spurious warnings due to using exact bit patterns as immediate
21260 `-wunsigned_overflow'
21261 Causes warnings to be produced when unsigned immediate values
21262 overflow the space available for then within their opcodes. By
21263 default this option is disabled as it is possible to receive
21264 spurious warnings due to using exact bit patterns as immediate
21268 Specifies that the assembled code should be marked as being
21269 targeted at the V850 processor. This allows the linker to detect
21270 attempts to link such code with code assembled for other
21274 Specifies that the assembled code should be marked as being
21275 targeted at the V850E processor. This allows the linker to detect
21276 attempts to link such code with code assembled for other
21280 Specifies that the assembled code should be marked as being
21281 targeted at the V850E1 processor. This allows the linker to
21282 detect attempts to link such code with code assembled for other
21286 Specifies that the assembled code should be marked as being
21287 targeted at the V850 processor but support instructions that are
21288 specific to the extended variants of the process. This allows the
21289 production of binaries that contain target specific code, but
21290 which are also intended to be used in a generic fashion. For
21291 example libgcc.a contains generic routines used by the code
21292 produced by GCC for all versions of the v850 architecture,
21293 together with support routines only used by the V850E architecture.
21296 Specifies that the assembled code should be marked as being
21297 targeted at the V850E2 processor. This allows the linker to
21298 detect attempts to link such code with code assembled for other
21302 Specifies that the assembled code should be marked as being
21303 targeted at the V850E2V3 processor. This allows the linker to
21304 detect attempts to link such code with code assembled for other
21308 This is an alias for `-mv850e3v5'.
21311 Specifies that the assembled code should be marked as being
21312 targeted at the V850E3V5 processor. This allows the linker to
21313 detect attempts to link such code with code assembled for other
21317 Enables relaxation. This allows the .longcall and .longjump pseudo
21318 ops to be used in the assembler source code. These ops label
21319 sections of code which are either a long function call or a long
21320 branch. The assembler will then flag these sections of code and
21321 the linker will attempt to relax them.
21324 Marks the generated objecy file as supporting the old GCC ABI.
21327 Marks the generated objecy file as supporting the RH850 ABI. This
21331 Marks the generated objecy file as supporting a maximum 64-bits of
21332 alignment for variables defined in the source code.
21335 Marks the generated objecy file as supporting a maximum 32-bits of
21336 alignment for variables defined in the source code. This is the
21341 File: as.info, Node: V850 Syntax, Next: V850 Floating Point, Prev: V850 Options, Up: V850-Dependent
21348 * V850-Chars:: Special Characters
21349 * V850-Regs:: Register Names
21352 File: as.info, Node: V850-Chars, Next: V850-Regs, Up: V850 Syntax
21354 9.50.2.1 Special Characters
21355 ...........................
21357 `#' is the line comment character. If a `#' appears as the first
21358 character of a line, the whole line is treated as a comment, but in
21359 this case the line can also be a logical line number directive (*note
21360 Comments::) or a preprocessor control command (*note Preprocessing::).
21362 Two dashes (`--') can also be used to start a line comment.
21364 The `;' character can be used to separate statements on the same
21368 File: as.info, Node: V850-Regs, Prev: V850-Chars, Up: V850 Syntax
21370 9.50.2.2 Register Names
21371 .......................
21373 `as' supports the following names for registers:
21374 `general register 0'
21377 `general register 1'
21380 `general register 2'
21383 `general register 3'
21386 `general register 4'
21389 `general register 5'
21392 `general register 6'
21395 `general register 7'
21398 `general register 8'
21401 `general register 9'
21404 `general register 10'
21407 `general register 11'
21410 `general register 12'
21413 `general register 13'
21416 `general register 14'
21419 `general register 15'
21422 `general register 16'
21425 `general register 17'
21428 `general register 18'
21431 `general register 19'
21434 `general register 20'
21437 `general register 21'
21440 `general register 22'
21443 `general register 23'
21446 `general register 24'
21449 `general register 25'
21452 `general register 26'
21455 `general register 27'
21458 `general register 28'
21461 `general register 29'
21464 `general register 30'
21467 `general register 31'
21470 `system register 0'
21473 `system register 1'
21476 `system register 2'
21479 `system register 3'
21482 `system register 4'
21485 `system register 5'
21488 `system register 16'
21491 `system register 17'
21494 `system register 18'
21497 `system register 19'
21500 `system register 20'
21504 File: as.info, Node: V850 Floating Point, Next: V850 Directives, Prev: V850 Syntax, Up: V850-Dependent
21506 9.50.3 Floating Point
21507 ---------------------
21509 The V850 family uses IEEE floating-point numbers.
21512 File: as.info, Node: V850 Directives, Next: V850 Opcodes, Prev: V850 Floating Point, Up: V850-Dependent
21514 9.50.4 V850 Machine Directives
21515 ------------------------------
21517 `.offset <EXPRESSION>'
21518 Moves the offset into the current section to the specified amount.
21520 `.section "name", <type>'
21521 This is an extension to the standard .section directive. It sets
21522 the current section to be <type> and creates an alias for this
21523 section called "name".
21526 Specifies that the assembled code should be marked as being
21527 targeted at the V850 processor. This allows the linker to detect
21528 attempts to link such code with code assembled for other
21532 Specifies that the assembled code should be marked as being
21533 targeted at the V850E processor. This allows the linker to detect
21534 attempts to link such code with code assembled for other
21538 Specifies that the assembled code should be marked as being
21539 targeted at the V850E1 processor. This allows the linker to
21540 detect attempts to link such code with code assembled for other
21544 Specifies that the assembled code should be marked as being
21545 targeted at the V850E2 processor. This allows the linker to
21546 detect attempts to link such code with code assembled for other
21550 Specifies that the assembled code should be marked as being
21551 targeted at the V850E2V3 processor. This allows the linker to
21552 detect attempts to link such code with code assembled for other
21556 Specifies that the assembled code should be marked as being
21557 targeted at the V850E3V5 processor. This allows the linker to
21558 detect attempts to link such code with code assembled for other
21562 Specifies that the assembled code should be marked as being
21563 targeted at the V850E3V5 processor. This allows the linker to
21564 detect attempts to link such code with code assembled for other
21569 File: as.info, Node: V850 Opcodes, Prev: V850 Directives, Up: V850-Dependent
21574 `as' implements all the standard V850 opcodes.
21576 `as' also implements the following pseudo ops:
21579 Computes the higher 16 bits of the given expression and stores it
21580 into the immediate operand field of the given instruction. For
21583 `mulhi hi0(here - there), r5, r6'
21585 computes the difference between the address of labels 'here' and
21586 'there', takes the upper 16 bits of this difference, shifts it
21587 down 16 bits and then multiplies it by the lower 16 bits in
21588 register 5, putting the result into register 6.
21591 Computes the lower 16 bits of the given expression and stores it
21592 into the immediate operand field of the given instruction. For
21595 `addi lo(here - there), r5, r6'
21597 computes the difference between the address of labels 'here' and
21598 'there', takes the lower 16 bits of this difference and adds it to
21599 register 5, putting the result into register 6.
21602 Computes the higher 16 bits of the given expression and then adds
21603 the value of the most significant bit of the lower 16 bits of the
21604 expression and stores the result into the immediate operand field
21605 of the given instruction. For example the following code can be
21606 used to compute the address of the label 'here' and store it into
21609 `movhi hi(here), r0, r6' `movea lo(here), r6, r6'
21611 The reason for this special behaviour is that movea performs a sign
21612 extension on its immediate operand. So for example if the address
21613 of 'here' was 0xFFFFFFFF then without the special behaviour of the
21614 hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6,
21615 then the movea instruction would takes its immediate operand,
21616 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it
21617 into r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E).
21618 With the hi() pseudo op adding in the top bit of the lo() pseudo
21619 op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 =
21620 0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 -
21624 Computes the 32 bit value of the given expression and stores it
21625 into the immediate operand field of the given instruction (which
21626 must be a mov instruction). For example:
21628 `mov hilo(here), r6'
21630 computes the absolute address of label 'here' and puts the result
21634 Computes the offset of the named variable from the start of the
21635 Small Data Area (whoes address is held in register 4, the GP
21636 register) and stores the result as a 16 bit signed value in the
21637 immediate operand field of the given instruction. For example:
21639 `ld.w sdaoff(_a_variable)[gp],r6'
21641 loads the contents of the location pointed to by the label
21642 '_a_variable' into register 6, provided that the label is located
21643 somewhere within +/- 32K of the address held in the GP register.
21644 [Note the linker assumes that the GP register contains a fixed
21645 address set to the address of the label called '__gp'. This can
21646 either be set up automatically by the linker, or specifically set
21647 by using the `--defsym __gp=<value>' command line option].
21650 Computes the offset of the named variable from the start of the
21651 Tiny Data Area (whoes address is held in register 30, the EP
21652 register) and stores the result as a 4,5, 7 or 8 bit unsigned
21653 value in the immediate operand field of the given instruction.
21656 `sld.w tdaoff(_a_variable)[ep],r6'
21658 loads the contents of the location pointed to by the label
21659 '_a_variable' into register 6, provided that the label is located
21660 somewhere within +256 bytes of the address held in the EP
21661 register. [Note the linker assumes that the EP register contains
21662 a fixed address set to the address of the label called '__ep'.
21663 This can either be set up automatically by the linker, or
21664 specifically set by using the `--defsym __ep=<value>' command line
21668 Computes the offset of the named variable from address 0 and
21669 stores the result as a 16 bit signed value in the immediate
21670 operand field of the given instruction. For example:
21672 `movea zdaoff(_a_variable),zero,r6'
21674 puts the address of the label '_a_variable' into register 6,
21675 assuming that the label is somewhere within the first 32K of
21676 memory. (Strictly speaking it also possible to access the last
21677 32K of memory as well, as the offsets are signed).
21680 Computes the offset of the named variable from the start of the
21681 Call Table Area (whoes address is helg in system register 20, the
21682 CTBP register) and stores the result a 6 or 16 bit unsigned value
21683 in the immediate field of then given instruction or piece of data.
21686 `callt ctoff(table_func1)'
21688 will put the call the function whoes address is held in the call
21689 table at the location labeled 'table_func1'.
21692 Indicates that the following sequence of instructions is a long
21693 call to function `name'. The linker will attempt to shorten this
21694 call sequence if `name' is within a 22bit offset of the call. Only
21695 valid if the `-mrelax' command line switch has been enabled.
21698 Indicates that the following sequence of instructions is a long
21699 jump to label `name'. The linker will attempt to shorten this code
21700 sequence if `name' is within a 22bit offset of the jump. Only
21701 valid if the `-mrelax' command line switch has been enabled.
21704 For information on the V850 instruction set, see `V850 Family
21705 32-/16-Bit single-Chip Microcontroller Architecture Manual' from NEC.
21709 File: as.info, Node: XGATE-Dependent, Next: XSTORMY16-Dependent, Prev: V850-Dependent, Up: Machine Dependencies
21711 9.51 XGATE Dependent Features
21712 =============================
21716 * XGATE-Opts:: XGATE Options
21717 * XGATE-Syntax:: Syntax
21718 * XGATE-Directives:: Assembler Directives
21719 * XGATE-Float:: Floating Point
21720 * XGATE-opcodes:: Opcodes
21723 File: as.info, Node: XGATE-Opts, Next: XGATE-Syntax, Up: XGATE-Dependent
21725 9.51.1 XGATE Options
21726 --------------------
21728 The Freescale XGATE version of `as' has a few machine dependent options.
21731 This option controls the ABI and indicates to use a 16-bit integer
21732 ABI. It has no effect on the assembled instructions. This is the
21736 This option controls the ABI and indicates to use a 32-bit integer
21740 This option controls the ABI and indicates to use a 32-bit float
21741 ABI. This is the default.
21744 This option controls the ABI and indicates to use a 64-bit float
21747 `--print-insn-syntax'
21748 You can use the `--print-insn-syntax' option to obtain the syntax
21749 description of the instruction when an error is detected.
21752 The `--print-opcodes' option prints the list of all the
21753 instructions with their syntax. Once the list is printed `as'
21758 File: as.info, Node: XGATE-Syntax, Next: XGATE-Directives, Prev: XGATE-Opts, Up: XGATE-Dependent
21763 In XGATE RISC syntax, the instruction name comes first and it may be
21764 followed by up to three operands. Operands are separated by commas
21765 (`,'). `as' will complain if too many operands are specified for a
21766 given instruction. The same will happen if you specified too few
21773 The presence of a `;' character or a `!' character anywhere on a
21774 line indicates the start of a comment that extends to the end of that
21777 A `*' or a `#' character at the start of a line also introduces a
21778 line comment, but these characters do not work elsewhere on the line.
21779 If the first character of the line is a `#' then as well as starting a
21780 comment, the line could also be logical line number directive (*note
21781 Comments::) or a preprocessor control command (*note Preprocessing::).
21783 The XGATE assembler does not currently support a line separator
21786 The following addressing modes are understood for XGATE:
21790 "Immediate 3 Bit Wide"
21793 "Immediate 4 Bit Wide"
21796 "Immediate 8 Bit Wide"
21799 "Monadic Addressing"
21802 "Dyadic Addressing"
21805 "Triadic Addressing"
21808 "Relative Addressing 9 Bit Wide"
21811 "Relative Addressing 10 Bit Wide"
21814 "Index Register plus Immediate Offset"
21815 `REG, (REG, #NUMBER)'
21817 "Index Register plus Register Offset"
21820 "Index Register plus Register Offset with Post-increment"
21823 "Index Register plus Register Offset with Pre-decrement"
21826 The register can be either `R0', `R1', `R2', `R3', `R4', `R5',
21830 Convience macro opcodes to deal with 16-bit values have been added.
21832 "Immediate 16 Bit Wide"
21833 `#NUMBER', or `*SYMBOL'
21844 File: as.info, Node: XGATE-Directives, Next: XGATE-Float, Prev: XGATE-Syntax, Up: XGATE-Dependent
21846 9.51.3 Assembler Directives
21847 ---------------------------
21849 The XGATE version of `as' have the following specific assembler
21853 File: as.info, Node: XGATE-Float, Next: XGATE-opcodes, Prev: XGATE-Directives, Up: XGATE-Dependent
21855 9.51.4 Floating Point
21856 ---------------------
21858 Packed decimal (P) format floating literals are not supported(yet).
21860 The floating point formats generated by directives are these.
21863 `Single' precision floating point constants.
21866 `Double' precision floating point constants.
21870 `Extended' precision (`long double') floating point constants.
21873 File: as.info, Node: XGATE-opcodes, Prev: XGATE-Float, Up: XGATE-Dependent
21879 File: as.info, Node: XSTORMY16-Dependent, Next: Xtensa-Dependent, Prev: XGATE-Dependent, Up: Machine Dependencies
21881 9.52 XStormy16 Dependent Features
21882 =================================
21886 * XStormy16 Syntax:: Syntax
21887 * XStormy16 Directives:: Machine Directives
21888 * XStormy16 Opcodes:: Pseudo-Opcodes
21891 File: as.info, Node: XStormy16 Syntax, Next: XStormy16 Directives, Up: XSTORMY16-Dependent
21898 * XStormy16-Chars:: Special Characters
21901 File: as.info, Node: XStormy16-Chars, Up: XStormy16 Syntax
21903 9.52.1.1 Special Characters
21904 ...........................
21906 `#' is the line comment character. If a `#' appears as the first
21907 character of a line, the whole line is treated as a comment, but in
21908 this case the line can also be a logical line number directive (*note
21909 Comments::) or a preprocessor control command (*note Preprocessing::).
21911 A semicolon (`;') can be used to start a comment that extends from
21912 wherever the character appears on the line up to the end of the line.
21914 The `|' character can be used to separate statements on the same
21918 File: as.info, Node: XStormy16 Directives, Next: XStormy16 Opcodes, Prev: XStormy16 Syntax, Up: XSTORMY16-Dependent
21920 9.52.2 XStormy16 Machine Directives
21921 -----------------------------------
21924 Like the `--16bit-pointers' command line option this directive
21925 indicates that the assembly code makes use of 16-bit pointers.
21928 Like the `--32bit-pointers' command line option this directive
21929 indicates that the assembly code makes use of 32-bit pointers.
21932 Like the `--no-pointers' command line option this directive
21933 indicates that the assembly code does not makes use pointers.
21937 File: as.info, Node: XStormy16 Opcodes, Prev: XStormy16 Directives, Up: XSTORMY16-Dependent
21939 9.52.3 XStormy16 Pseudo-Opcodes
21940 -------------------------------
21942 `as' implements all the standard XStormy16 opcodes.
21944 `as' also implements the following pseudo ops:
21947 Computes the lower 16 bits of the given expression and stores it
21948 into the immediate operand field of the given instruction. For
21951 `add r6, @lo(here - there)'
21953 computes the difference between the address of labels 'here' and
21954 'there', takes the lower 16 bits of this difference and adds it to
21958 Computes the higher 16 bits of the given expression and stores it
21959 into the immediate operand field of the given instruction. For
21962 `addc r7, @hi(here - there)'
21964 computes the difference between the address of labels 'here' and
21965 'there', takes the upper 16 bits of this difference, shifts it
21966 down 16 bits and then adds it, along with the carry bit, to the
21967 value in register 7.
21971 File: as.info, Node: Xtensa-Dependent, Next: Z80-Dependent, Prev: XSTORMY16-Dependent, Up: Machine Dependencies
21973 9.53 Xtensa Dependent Features
21974 ==============================
21976 This chapter covers features of the GNU assembler that are specific
21977 to the Xtensa architecture. For details about the Xtensa instruction
21978 set, please consult the `Xtensa Instruction Set Architecture (ISA)
21983 * Xtensa Options:: Command-line Options.
21984 * Xtensa Syntax:: Assembler Syntax for Xtensa Processors.
21985 * Xtensa Optimizations:: Assembler Optimizations.
21986 * Xtensa Relaxation:: Other Automatic Transformations.
21987 * Xtensa Directives:: Directives for Xtensa Processors.
21990 File: as.info, Node: Xtensa Options, Next: Xtensa Syntax, Up: Xtensa-Dependent
21992 9.53.1 Command Line Options
21993 ---------------------------
21995 `--text-section-literals | --no-text-section-literals'
21996 Control the treatment of literal pools. The default is
21997 `--no-text-section-literals', which places literals in separate
21998 sections in the output file. This allows the literal pool to be
21999 placed in a data RAM/ROM. With `--text-section-literals', the
22000 literals are interspersed in the text section in order to keep
22001 them as close as possible to their references. This may be
22002 necessary for large assembly files, where the literals would
22003 otherwise be out of range of the `L32R' instructions in the text
22004 section. These options only affect literals referenced via
22005 PC-relative `L32R' instructions; literals for absolute mode `L32R'
22006 instructions are handled separately. *Note literal: Literal
22009 `--absolute-literals | --no-absolute-literals'
22010 Indicate to the assembler whether `L32R' instructions use absolute
22011 or PC-relative addressing. If the processor includes the absolute
22012 addressing option, the default is to use absolute `L32R'
22013 relocations. Otherwise, only the PC-relative `L32R' relocations
22016 `--target-align | --no-target-align'
22017 Enable or disable automatic alignment to reduce branch penalties
22018 at some expense in code size. *Note Automatic Instruction
22019 Alignment: Xtensa Automatic Alignment. This optimization is
22020 enabled by default. Note that the assembler will always align
22021 instructions like `LOOP' that have fixed alignment requirements.
22023 `--longcalls | --no-longcalls'
22024 Enable or disable transformation of call instructions to allow
22025 calls across a greater range of addresses. *Note Function Call
22026 Relaxation: Xtensa Call Relaxation. This option should be used
22027 when call targets can potentially be out of range. It may degrade
22028 both code size and performance, but the linker can generally
22029 optimize away the unnecessary overhead when a call ends up within
22030 range. The default is `--no-longcalls'.
22032 `--transform | --no-transform'
22033 Enable or disable all assembler transformations of Xtensa
22034 instructions, including both relaxation and optimization. The
22035 default is `--transform'; `--no-transform' should only be used in
22036 the rare cases when the instructions must be exactly as specified
22037 in the assembly source. Using `--no-transform' causes out of range
22038 instruction operands to be errors.
22040 `--rename-section OLDNAME=NEWNAME'
22041 Rename the OLDNAME section to NEWNAME. This option can be used
22042 multiple times to rename multiple sections.
22044 `--trampolines | --no-trampolines'
22045 Enable or disable transformation of jump instructions to allow
22046 jumps across a greater range of addresses. *Note Jump
22047 Trampolines: Xtensa Jump Relaxation. This option should be used
22048 when jump targets can potentially be out of range. In the absence
22049 of such jumps this option does not affect code size or
22050 performance. The default is `--trampolines'.
22053 File: as.info, Node: Xtensa Syntax, Next: Xtensa Optimizations, Prev: Xtensa Options, Up: Xtensa-Dependent
22055 9.53.2 Assembler Syntax
22056 -----------------------
22058 Block comments are delimited by `/*' and `*/'. End of line comments
22059 may be introduced with either `#' or `//'.
22061 If a `#' appears as the first character of a line then the whole
22062 line is treated as a comment, but in this case the line could also be a
22063 logical line number directive (*note Comments::) or a preprocessor
22064 control command (*note Preprocessing::).
22066 Instructions consist of a leading opcode or macro name followed by
22067 whitespace and an optional comma-separated list of operands:
22069 OPCODE [OPERAND, ...]
22071 Instructions must be separated by a newline or semicolon (`;').
22073 FLIX instructions, which bundle multiple opcodes together in a single
22074 instruction, are specified by enclosing the bundled opcodes inside
22085 The opcodes in a FLIX instruction are listed in the same order as the
22086 corresponding instruction slots in the TIE format declaration.
22087 Directives and labels are not allowed inside the braces of a FLIX
22088 instruction. A particular TIE format name can optionally be specified
22089 immediately after the opening brace, but this is usually unnecessary.
22090 The assembler will automatically search for a format that can encode the
22091 specified opcodes, so the format name need only be specified in rare
22092 cases where there is more than one applicable format and where it
22093 matters which of those formats is used. A FLIX instruction can also be
22094 specified on a single line by separating the opcodes with semicolons:
22096 { [FORMAT;] OPCODE0 [OPERANDS]; OPCODE1 [OPERANDS]; OPCODE2 [OPERANDS]; ... }
22098 If an opcode can only be encoded in a FLIX instruction but is not
22099 specified as part of a FLIX bundle, the assembler will choose the
22100 smallest format where the opcode can be encoded and will fill unused
22101 instruction slots with no-ops.
22105 * Xtensa Opcodes:: Opcode Naming Conventions.
22106 * Xtensa Registers:: Register Naming.
22109 File: as.info, Node: Xtensa Opcodes, Next: Xtensa Registers, Up: Xtensa Syntax
22111 9.53.2.1 Opcode Names
22112 .....................
22114 See the `Xtensa Instruction Set Architecture (ISA) Reference Manual'
22115 for a complete list of opcodes and descriptions of their semantics.
22117 If an opcode name is prefixed with an underscore character (`_'),
22118 `as' will not transform that instruction in any way. The underscore
22119 prefix disables both optimization (*note Xtensa Optimizations: Xtensa
22120 Optimizations.) and relaxation (*note Xtensa Relaxation: Xtensa
22121 Relaxation.) for that particular instruction. Only use the underscore
22122 prefix when it is essential to select the exact opcode produced by the
22123 assembler. Using this feature unnecessarily makes the code less
22124 efficient by disabling assembler optimization and less flexible by
22125 disabling relaxation.
22127 Note that this special handling of underscore prefixes only applies
22128 to Xtensa opcodes, not to either built-in macros or user-defined macros.
22129 When an underscore prefix is used with a macro (e.g., `_MOV'), it
22130 refers to a different macro. The assembler generally provides built-in
22131 macros both with and without the underscore prefix, where the underscore
22132 versions behave as if the underscore carries through to the instructions
22133 in the macros. For example, `_MOV' may expand to `_MOV.N'.
22135 The underscore prefix only applies to individual instructions, not to
22136 series of instructions. For example, if a series of instructions have
22137 underscore prefixes, the assembler will not transform the individual
22138 instructions, but it may insert other instructions between them (e.g.,
22139 to align a `LOOP' instruction). To prevent the assembler from
22140 modifying a series of instructions as a whole, use the `no-transform'
22141 directive. *Note transform: Transform Directive.
22144 File: as.info, Node: Xtensa Registers, Prev: Xtensa Opcodes, Up: Xtensa Syntax
22146 9.53.2.2 Register Names
22147 .......................
22149 The assembly syntax for a register file entry is the "short" name for a
22150 TIE register file followed by the index into that register file. For
22151 example, the general-purpose `AR' register file has a short name of
22152 `a', so these registers are named `a0'...`a15'. As a special feature,
22153 `sp' is also supported as a synonym for `a1'. Additional registers may
22154 be added by processor configuration options and by designer-defined TIE
22155 extensions. An initial `$' character is optional in all register names.
22158 File: as.info, Node: Xtensa Optimizations, Next: Xtensa Relaxation, Prev: Xtensa Syntax, Up: Xtensa-Dependent
22160 9.53.3 Xtensa Optimizations
22161 ---------------------------
22163 The optimizations currently supported by `as' are generation of density
22164 instructions where appropriate and automatic branch target alignment.
22168 * Density Instructions:: Using Density Instructions.
22169 * Xtensa Automatic Alignment:: Automatic Instruction Alignment.
22172 File: as.info, Node: Density Instructions, Next: Xtensa Automatic Alignment, Up: Xtensa Optimizations
22174 9.53.3.1 Using Density Instructions
22175 ...................................
22177 The Xtensa instruction set has a code density option that provides
22178 16-bit versions of some of the most commonly used opcodes. Use of these
22179 opcodes can significantly reduce code size. When possible, the
22180 assembler automatically translates instructions from the core Xtensa
22181 instruction set into equivalent instructions from the Xtensa code
22182 density option. This translation can be disabled by using underscore
22183 prefixes (*note Opcode Names: Xtensa Opcodes.), by using the
22184 `--no-transform' command-line option (*note Command Line Options:
22185 Xtensa Options.), or by using the `no-transform' directive (*note
22186 transform: Transform Directive.).
22188 It is a good idea _not_ to use the density instructions directly.
22189 The assembler will automatically select dense instructions where
22190 possible. If you later need to use an Xtensa processor without the code
22191 density option, the same assembly code will then work without
22195 File: as.info, Node: Xtensa Automatic Alignment, Prev: Density Instructions, Up: Xtensa Optimizations
22197 9.53.3.2 Automatic Instruction Alignment
22198 ........................................
22200 The Xtensa assembler will automatically align certain instructions, both
22201 to optimize performance and to satisfy architectural requirements.
22203 As an optimization to improve performance, the assembler attempts to
22204 align branch targets so they do not cross instruction fetch boundaries.
22205 (Xtensa processors can be configured with either 32-bit or 64-bit
22206 instruction fetch widths.) An instruction immediately following a call
22207 is treated as a branch target in this context, because it will be the
22208 target of a return from the call. This alignment has the potential to
22209 reduce branch penalties at some expense in code size. This
22210 optimization is enabled by default. You can disable it with the
22211 `--no-target-align' command-line option (*note Command Line Options:
22214 The target alignment optimization is done without adding instructions
22215 that could increase the execution time of the program. If there are
22216 density instructions in the code preceding a target, the assembler can
22217 change the target alignment by widening some of those instructions to
22218 the equivalent 24-bit instructions. Extra bytes of padding can be
22219 inserted immediately following unconditional jump and return
22220 instructions. This approach is usually successful in aligning many,
22221 but not all, branch targets.
22223 The `LOOP' family of instructions must be aligned such that the
22224 first instruction in the loop body does not cross an instruction fetch
22225 boundary (e.g., with a 32-bit fetch width, a `LOOP' instruction must be
22226 on either a 1 or 2 mod 4 byte boundary). The assembler knows about
22227 this restriction and inserts the minimal number of 2 or 3 byte no-op
22228 instructions to satisfy it. When no-op instructions are added, any
22229 label immediately preceding the original loop will be moved in order to
22230 refer to the loop instruction, not the newly generated no-op
22231 instruction. To preserve binary compatibility across processors with
22232 different fetch widths, the assembler conservatively assumes a 32-bit
22233 fetch width when aligning `LOOP' instructions (except if the first
22234 instruction in the loop is a 64-bit instruction).
22236 Previous versions of the assembler automatically aligned `ENTRY'
22237 instructions to 4-byte boundaries, but that alignment is now the
22238 programmer's responsibility.
22241 File: as.info, Node: Xtensa Relaxation, Next: Xtensa Directives, Prev: Xtensa Optimizations, Up: Xtensa-Dependent
22243 9.53.4 Xtensa Relaxation
22244 ------------------------
22246 When an instruction operand is outside the range allowed for that
22247 particular instruction field, `as' can transform the code to use a
22248 functionally-equivalent instruction or sequence of instructions. This
22249 process is known as "relaxation". This is typically done for branch
22250 instructions because the distance of the branch targets is not known
22251 until assembly-time. The Xtensa assembler offers branch relaxation and
22252 also extends this concept to function calls, `MOVI' instructions and
22253 other instructions with immediate fields.
22257 * Xtensa Branch Relaxation:: Relaxation of Branches.
22258 * Xtensa Call Relaxation:: Relaxation of Function Calls.
22259 * Xtensa Jump Relaxation:: Relaxation of Jumps.
22260 * Xtensa Immediate Relaxation:: Relaxation of other Immediate Fields.
22263 File: as.info, Node: Xtensa Branch Relaxation, Next: Xtensa Call Relaxation, Up: Xtensa Relaxation
22265 9.53.4.1 Conditional Branch Relaxation
22266 ......................................
22268 When the target of a branch is too far away from the branch itself,
22269 i.e., when the offset from the branch to the target is too large to fit
22270 in the immediate field of the branch instruction, it may be necessary to
22271 replace the branch with a branch around a jump. For example,
22281 (The `BNEZ.N' instruction would be used in this example only if the
22282 density option is available. Otherwise, `BNEZ' would be used.)
22284 This relaxation works well because the unconditional jump instruction
22285 has a much larger offset range than the various conditional branches.
22286 However, an error will occur if a branch target is beyond the range of a
22287 jump instruction. `as' cannot relax unconditional jumps. Similarly,
22288 an error will occur if the original input contains an unconditional
22289 jump to a target that is out of range.
22291 Branch relaxation is enabled by default. It can be disabled by using
22292 underscore prefixes (*note Opcode Names: Xtensa Opcodes.), the
22293 `--no-transform' command-line option (*note Command Line Options:
22294 Xtensa Options.), or the `no-transform' directive (*note transform:
22295 Transform Directive.).
22298 File: as.info, Node: Xtensa Call Relaxation, Next: Xtensa Jump Relaxation, Prev: Xtensa Branch Relaxation, Up: Xtensa Relaxation
22300 9.53.4.2 Function Call Relaxation
22301 .................................
22303 Function calls may require relaxation because the Xtensa immediate call
22304 instructions (`CALL0', `CALL4', `CALL8' and `CALL12') provide a
22305 PC-relative offset of only 512 Kbytes in either direction. For larger
22306 programs, it may be necessary to use indirect calls (`CALLX0',
22307 `CALLX4', `CALLX8' and `CALLX12') where the target address is specified
22308 in a register. The Xtensa assembler can automatically relax immediate
22309 call instructions into indirect call instructions. This relaxation is
22310 done by loading the address of the called function into the callee's
22311 return address register and then using a `CALLX' instruction. So, for
22316 might be relaxed to:
22322 Because the addresses of targets of function calls are not generally
22323 known until link-time, the assembler must assume the worst and relax all
22324 the calls to functions in other source files, not just those that really
22325 will be out of range. The linker can recognize calls that were
22326 unnecessarily relaxed, and it will remove the overhead introduced by the
22327 assembler for those cases where direct calls are sufficient.
22329 Call relaxation is disabled by default because it can have a negative
22330 effect on both code size and performance, although the linker can
22331 usually eliminate the unnecessary overhead. If a program is too large
22332 and some of the calls are out of range, function call relaxation can be
22333 enabled using the `--longcalls' command-line option or the `longcalls'
22334 directive (*note longcalls: Longcalls Directive.).
22337 File: as.info, Node: Xtensa Jump Relaxation, Next: Xtensa Immediate Relaxation, Prev: Xtensa Call Relaxation, Up: Xtensa Relaxation
22339 9.53.4.3 Jump Relaxation
22340 ........................
22342 Jump instruction may require relaxation because the Xtensa jump
22343 instruction (`J') provide a PC-relative offset of only 128 Kbytes in
22344 either direction. One option is to use jump long (`J.L') instruction,
22345 which depending on jump distance may be assembled as jump (`J') or
22346 indirect jump (`JX'). However it needs a free register. When there's
22347 no spare register it is possible to plant intermediate jump sites
22348 (trampolines) between the jump instruction and its target. These sites
22349 may be located in areas unreachable by normal code execution flow, in
22350 that case they only contain intermediate jumps, or they may be inserted
22351 in the middle of code block, in which case there's an additional jump
22352 from the beginning of the trampoline to the instruction past its end.
22365 might be relaxed to:
22395 The Xtensa assempler uses trampolines with jump around only when it
22396 cannot find suitable unreachable trampoline. There may be multiple
22397 trampolines between the jump instruction and its target.
22399 This relaxation does not apply to jumps to undefined symbols,
22400 assuming they will reach their targets once resolved.
22402 Jump relaxation is enabled by default because it does not affect
22403 code size or performance while the code itself is small. This
22404 relaxation may be disabled completely with `--no-trampolines' or
22405 `--no-transform' command-line options (*note Command Line Options:
22409 File: as.info, Node: Xtensa Immediate Relaxation, Prev: Xtensa Jump Relaxation, Up: Xtensa Relaxation
22411 9.53.4.4 Other Immediate Field Relaxation
22412 .........................................
22414 The assembler normally performs the following other relaxations. They
22415 can be disabled by using underscore prefixes (*note Opcode Names:
22416 Xtensa Opcodes.), the `--no-transform' command-line option (*note
22417 Command Line Options: Xtensa Options.), or the `no-transform' directive
22418 (*note transform: Transform Directive.).
22420 The `MOVI' machine instruction can only materialize values in the
22421 range from -2048 to 2047. Values outside this range are best
22422 materialized with `L32R' instructions. Thus:
22426 is assembled into the following machine code:
22428 .literal .L1, 100000
22431 The `L8UI' machine instruction can only be used with immediate
22432 offsets in the range from 0 to 255. The `L16SI' and `L16UI' machine
22433 instructions can only be used with offsets from 0 to 510. The `L32I'
22434 machine instruction can only be used with offsets from 0 to 1020. A
22435 load offset outside these ranges can be materialized with an `L32R'
22436 instruction if the destination register of the load is different than
22437 the source address register. For example:
22448 If the load destination and source address register are the same, an
22449 out-of-range offset causes an error.
22451 The Xtensa `ADDI' instruction only allows immediate operands in the
22452 range from -128 to 127. There are a number of alternate instruction
22453 sequences for the `ADDI' operation. First, if the immediate is 0, the
22454 `ADDI' will be turned into a `MOV.N' instruction (or the equivalent
22455 `OR' instruction if the code density option is not available). If the
22456 `ADDI' immediate is outside of the range -128 to 127, but inside the
22457 range -32896 to 32639, an `ADDMI' instruction or `ADDMI'/`ADDI'
22458 sequence will be used. Finally, if the immediate is outside of this
22459 range and a free register is available, an `L32R'/`ADD' sequence will
22460 be used with a literal allocated from the literal pool.
22469 is assembled into the following:
22471 .literal .L1, 50000
22473 addmi a5, a6, 0x200
22474 addmi a5, a6, 0x200
22480 File: as.info, Node: Xtensa Directives, Prev: Xtensa Relaxation, Up: Xtensa-Dependent
22485 The Xtensa assembler supports a region-based directive syntax:
22487 .begin DIRECTIVE [OPTIONS]
22491 All the Xtensa-specific directives that apply to a region of code use
22494 The directive applies to code between the `.begin' and the `.end'.
22495 The state of the option after the `.end' reverts to what it was before
22496 the `.begin'. A nested `.begin'/`.end' region can further change the
22497 state of the directive without having to be aware of its outer state.
22498 For example, consider:
22500 .begin no-transform
22508 The `ADD' opcodes at `L' and `N' in the outer `no-transform' region
22509 both result in `ADD' machine instructions, but the assembler selects an
22510 `ADD.N' instruction for the `ADD' at `M' in the inner `transform'
22513 The advantage of this style is that it works well inside macros
22514 which can preserve the context of their callers.
22516 The following directives are available:
22520 * Schedule Directive:: Enable instruction scheduling.
22521 * Longcalls Directive:: Use Indirect Calls for Greater Range.
22522 * Transform Directive:: Disable All Assembler Transformations.
22523 * Literal Directive:: Intermix Literals with Instructions.
22524 * Literal Position Directive:: Specify Inline Literal Pool Locations.
22525 * Literal Prefix Directive:: Specify Literal Section Name Prefix.
22526 * Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals.
22529 File: as.info, Node: Schedule Directive, Next: Longcalls Directive, Up: Xtensa Directives
22534 The `schedule' directive is recognized only for compatibility with
22535 Tensilica's assembler.
22537 .begin [no-]schedule
22540 This directive is ignored and has no effect on `as'.
22543 File: as.info, Node: Longcalls Directive, Next: Transform Directive, Prev: Schedule Directive, Up: Xtensa Directives
22548 The `longcalls' directive enables or disables function call relaxation.
22549 *Note Function Call Relaxation: Xtensa Call Relaxation.
22551 .begin [no-]longcalls
22552 .end [no-]longcalls
22554 Call relaxation is disabled by default unless the `--longcalls'
22555 command-line option is specified. The `longcalls' directive overrides
22556 the default determined by the command-line options.
22559 File: as.info, Node: Transform Directive, Next: Literal Directive, Prev: Longcalls Directive, Up: Xtensa Directives
22564 This directive enables or disables all assembler transformation,
22565 including relaxation (*note Xtensa Relaxation: Xtensa Relaxation.) and
22566 optimization (*note Xtensa Optimizations: Xtensa Optimizations.).
22568 .begin [no-]transform
22569 .end [no-]transform
22571 Transformations are enabled by default unless the `--no-transform'
22572 option is used. The `transform' directive overrides the default
22573 determined by the command-line options. An underscore opcode prefix,
22574 disabling transformation of that opcode, always takes precedence over
22575 both directives and command-line flags.
22578 File: as.info, Node: Literal Directive, Next: Literal Position Directive, Prev: Transform Directive, Up: Xtensa Directives
22583 The `.literal' directive is used to define literal pool data, i.e.,
22584 read-only 32-bit data accessed via `L32R' instructions.
22586 .literal LABEL, VALUE[, VALUE...]
22588 This directive is similar to the standard `.word' directive, except
22589 that the actual location of the literal data is determined by the
22590 assembler and linker, not by the position of the `.literal' directive.
22591 Using this directive gives the assembler freedom to locate the literal
22592 data in the most appropriate place and possibly to combine identical
22593 literals. For example, the code:
22599 can be used to load a pointer to the symbol `sym' into register
22600 `a4'. The value of `sym' will not be placed between the `ENTRY' and
22601 `L32R' instructions; instead, the assembler puts the data in a literal
22604 Literal pools are placed by default in separate literal sections;
22605 however, when using the `--text-section-literals' option (*note Command
22606 Line Options: Xtensa Options.), the literal pools for PC-relative mode
22607 `L32R' instructions are placed in the current section.(1) These text
22608 section literal pools are created automatically before `ENTRY'
22609 instructions and manually after `.literal_position' directives (*note
22610 literal_position: Literal Position Directive.). If there are no
22611 preceding `ENTRY' instructions, explicit `.literal_position' directives
22612 must be used to place the text section literal pools; otherwise, `as'
22613 will report an error.
22615 When literals are placed in separate sections, the literal section
22616 names are derived from the names of the sections where the literals are
22617 defined. The base literal section names are `.literal' for PC-relative
22618 mode `L32R' instructions and `.lit4' for absolute mode `L32R'
22619 instructions (*note absolute-literals: Absolute Literals Directive.).
22620 These base names are used for literals defined in the default `.text'
22621 section. For literals defined in other sections or within the scope of
22622 a `literal_prefix' directive (*note literal_prefix: Literal Prefix
22623 Directive.), the following rules determine the literal section name:
22625 1. If the current section is a member of a section group, the literal
22626 section name includes the group name as a suffix to the base
22627 `.literal' or `.lit4' name, with a period to separate the base
22628 name and group name. The literal section is also made a member of
22631 2. If the current section name (or `literal_prefix' value) begins with
22632 "`.gnu.linkonce.KIND.'", the literal section name is formed by
22633 replacing "`.KIND'" with the base `.literal' or `.lit4' name. For
22634 example, for literals defined in a section named
22635 `.gnu.linkonce.t.func', the literal section will be
22636 `.gnu.linkonce.literal.func' or `.gnu.linkonce.lit4.func'.
22638 3. If the current section name (or `literal_prefix' value) ends with
22639 `.text', the literal section name is formed by replacing that
22640 suffix with the base `.literal' or `.lit4' name. For example, for
22641 literals defined in a section named `.iram0.text', the literal
22642 section will be `.iram0.literal' or `.iram0.lit4'.
22644 4. If none of the preceding conditions apply, the literal section
22645 name is formed by adding the base `.literal' or `.lit4' name as a
22646 suffix to the current section name (or `literal_prefix' value).
22648 ---------- Footnotes ----------
22650 (1) Literals for the `.init' and `.fini' sections are always placed
22651 in separate sections, even when `--text-section-literals' is enabled.
22654 File: as.info, Node: Literal Position Directive, Next: Literal Prefix Directive, Prev: Literal Directive, Up: Xtensa Directives
22656 9.53.5.5 literal_position
22657 .........................
22659 When using `--text-section-literals' to place literals inline in the
22660 section being assembled, the `.literal_position' directive can be used
22661 to mark a potential location for a literal pool.
22665 The `.literal_position' directive is ignored when the
22666 `--text-section-literals' option is not used or when `L32R'
22667 instructions use the absolute addressing mode.
22669 The assembler will automatically place text section literal pools
22670 before `ENTRY' instructions, so the `.literal_position' directive is
22671 only needed to specify some other location for a literal pool. You may
22672 need to add an explicit jump instruction to skip over an inline literal
22675 For example, an interrupt vector does not begin with an `ENTRY'
22676 instruction so the assembler will be unable to automatically find a good
22677 place to put a literal pool. Moreover, the code for the interrupt
22678 vector must be at a specific starting address, so the literal pool
22679 cannot come before the start of the code. The literal pool for the
22680 vector must be explicitly positioned in the middle of the vector (before
22681 any uses of the literals, due to the negative offsets used by
22682 PC-relative `L32R' instructions). The `.literal_position' directive
22683 can be used to do this. In the following code, the literal for `M'
22684 will automatically be aligned correctly and is placed after the
22685 unconditional jump.
22696 File: as.info, Node: Literal Prefix Directive, Next: Absolute Literals Directive, Prev: Literal Position Directive, Up: Xtensa Directives
22698 9.53.5.6 literal_prefix
22699 .......................
22701 The `literal_prefix' directive allows you to override the default
22702 literal section names, which are derived from the names of the sections
22703 where the literals are defined.
22705 .begin literal_prefix [NAME]
22706 .end literal_prefix
22708 For literals defined within the delimited region, the literal section
22709 names are derived from the NAME argument instead of the name of the
22710 current section. The rules used to derive the literal section names do
22711 not change. *Note literal: Literal Directive. If the NAME argument is
22712 omitted, the literal sections revert to the defaults. This directive
22713 has no effect when using the `--text-section-literals' option (*note
22714 Command Line Options: Xtensa Options.).
22717 File: as.info, Node: Absolute Literals Directive, Prev: Literal Prefix Directive, Up: Xtensa Directives
22719 9.53.5.7 absolute-literals
22720 ..........................
22722 The `absolute-literals' and `no-absolute-literals' directives control
22723 the absolute vs. PC-relative mode for `L32R' instructions. These are
22724 relevant only for Xtensa configurations that include the absolute
22725 addressing option for `L32R' instructions.
22727 .begin [no-]absolute-literals
22728 .end [no-]absolute-literals
22730 These directives do not change the `L32R' mode--they only cause the
22731 assembler to emit the appropriate kind of relocation for `L32R'
22732 instructions and to place the literal values in the appropriate section.
22733 To change the `L32R' mode, the program must write the `LITBASE' special
22734 register. It is the programmer's responsibility to keep track of the
22735 mode and indicate to the assembler which mode is used in each region of
22738 If the Xtensa configuration includes the absolute `L32R' addressing
22739 option, the default is to assume absolute `L32R' addressing unless the
22740 `--no-absolute-literals' command-line option is specified. Otherwise,
22741 the default is to assume PC-relative `L32R' addressing. The
22742 `absolute-literals' directive can then be used to override the default
22743 determined by the command-line options.
22746 File: as.info, Node: Reporting Bugs, Next: Acknowledgements, Prev: Machine Dependencies, Up: Top
22751 Your bug reports play an essential role in making `as' reliable.
22753 Reporting a bug may help you by bringing a solution to your problem,
22754 or it may not. But in any case the principal function of a bug report
22755 is to help the entire community by making the next version of `as' work
22756 better. Bug reports are your contribution to the maintenance of `as'.
22758 In order for a bug report to serve its purpose, you must include the
22759 information that enables us to fix the bug.
22763 * Bug Criteria:: Have you found a bug?
22764 * Bug Reporting:: How to report bugs
22767 File: as.info, Node: Bug Criteria, Next: Bug Reporting, Up: Reporting Bugs
22769 10.1 Have You Found a Bug?
22770 ==========================
22772 If you are not sure whether you have found a bug, here are some
22775 * If the assembler gets a fatal signal, for any input whatever, that
22776 is a `as' bug. Reliable assemblers never crash.
22778 * If `as' produces an error message for valid input, that is a bug.
22780 * If `as' does not produce an error message for invalid input, that
22781 is a bug. However, you should note that your idea of "invalid
22782 input" might be our idea of "an extension" or "support for
22783 traditional practice".
22785 * If you are an experienced user of assemblers, your suggestions for
22786 improvement of `as' are welcome in any case.
22789 File: as.info, Node: Bug Reporting, Prev: Bug Criteria, Up: Reporting Bugs
22791 10.2 How to Report Bugs
22792 =======================
22794 A number of companies and individuals offer support for GNU products.
22795 If you obtained `as' from a support organization, we recommend you
22796 contact that organization first.
22798 You can find contact information for many support companies and
22799 individuals in the file `etc/SERVICE' in the GNU Emacs distribution.
22801 In any event, we also recommend that you send bug reports for `as'
22802 to `http://www.sourceware.org/bugzilla/'.
22804 The fundamental principle of reporting bugs usefully is this:
22805 *report all the facts*. If you are not sure whether to state a fact or
22806 leave it out, state it!
22808 Often people omit facts because they think they know what causes the
22809 problem and assume that some details do not matter. Thus, you might
22810 assume that the name of a symbol you use in an example does not matter.
22811 Well, probably it does not, but one cannot be sure. Perhaps the bug
22812 is a stray memory reference which happens to fetch from the location
22813 where that name is stored in memory; perhaps, if the name were
22814 different, the contents of that location would fool the assembler into
22815 doing the right thing despite the bug. Play it safe and give a
22816 specific, complete example. That is the easiest thing for you to do,
22817 and the most helpful.
22819 Keep in mind that the purpose of a bug report is to enable us to fix
22820 the bug if it is new to us. Therefore, always write your bug reports
22821 on the assumption that the bug has not been reported previously.
22823 Sometimes people give a few sketchy facts and ask, "Does this ring a
22824 bell?" This cannot help us fix a bug, so it is basically useless. We
22825 respond by asking for enough details to enable us to investigate. You
22826 might as well expedite matters by sending them to begin with.
22828 To enable us to fix the bug, you should include all these things:
22830 * The version of `as'. `as' announces it if you start it with the
22831 `--version' argument.
22833 Without this, we will not know whether there is any point in
22834 looking for the bug in the current version of `as'.
22836 * Any patches you may have applied to the `as' source.
22838 * The type of machine you are using, and the operating system name
22839 and version number.
22841 * What compiler (and its version) was used to compile `as'--e.g.
22844 * The command arguments you gave the assembler to assemble your
22845 example and observe the bug. To guarantee you will not omit
22846 something important, list them all. A copy of the Makefile (or
22847 the output from make) is sufficient.
22849 If we were to try to guess the arguments, we would probably guess
22850 wrong and then we might not encounter the bug.
22852 * A complete input file that will reproduce the bug. If the bug is
22853 observed when the assembler is invoked via a compiler, send the
22854 assembler source, not the high level language source. Most
22855 compilers will produce the assembler source when run with the `-S'
22856 option. If you are using `gcc', use the options `-v
22857 --save-temps'; this will save the assembler source in a file with
22858 an extension of `.s', and also show you exactly how `as' is being
22861 * A description of what behavior you observe that you believe is
22862 incorrect. For example, "It gets a fatal signal."
22864 Of course, if the bug is that `as' gets a fatal signal, then we
22865 will certainly notice it. But if the bug is incorrect output, we
22866 might not notice unless it is glaringly wrong. You might as well
22867 not give us a chance to make a mistake.
22869 Even if the problem you experience is a fatal signal, you should
22870 still say so explicitly. Suppose something strange is going on,
22871 such as, your copy of `as' is out of sync, or you have encountered
22872 a bug in the C library on your system. (This has happened!) Your
22873 copy might crash and ours would not. If you told us to expect a
22874 crash, then when ours fails to crash, we would know that the bug
22875 was not happening for us. If you had not told us to expect a
22876 crash, then we would not be able to draw any conclusion from our
22879 * If you wish to suggest changes to the `as' source, send us context
22880 diffs, as generated by `diff' with the `-u', `-c', or `-p' option.
22881 Always send diffs from the old file to the new file. If you even
22882 discuss something in the `as' source, refer to it by context, not
22885 The line numbers in our development sources will not match those
22886 in your sources. Your line numbers would convey no useful
22889 Here are some things that are not necessary:
22891 * A description of the envelope of the bug.
22893 Often people who encounter a bug spend a lot of time investigating
22894 which changes to the input file will make the bug go away and which
22895 changes will not affect it.
22897 This is often time consuming and not very useful, because the way
22898 we will find the bug is by running a single example under the
22899 debugger with breakpoints, not by pure deduction from a series of
22900 examples. We recommend that you save your time for something else.
22902 Of course, if you can find a simpler example to report _instead_
22903 of the original one, that is a convenience for us. Errors in the
22904 output will be easier to spot, running under the debugger will take
22905 less time, and so on.
22907 However, simplification is not vital; if you do not want to do
22908 this, report the bug anyway and send us the entire test case you
22911 * A patch for the bug.
22913 A patch for the bug does help us if it is a good one. But do not
22914 omit the necessary information, such as the test case, on the
22915 assumption that a patch is all we need. We might see problems
22916 with your patch and decide to fix the problem another way, or we
22917 might not understand it at all.
22919 Sometimes with a program as complicated as `as' it is very hard to
22920 construct an example that will make the program follow a certain
22921 path through the code. If you do not send us the example, we will
22922 not be able to construct one, so we will not be able to verify
22923 that the bug is fixed.
22925 And if we cannot understand what bug you are trying to fix, or why
22926 your patch should be an improvement, we will not install it. A
22927 test case will help us to understand.
22929 * A guess about what the bug is or what it depends on.
22931 Such guesses are usually wrong. Even we cannot guess right about
22932 such things without first using the debugger to find the facts.
22935 File: as.info, Node: Acknowledgements, Next: GNU Free Documentation License, Prev: Reporting Bugs, Up: Top
22937 11 Acknowledgements
22938 *******************
22940 If you have contributed to GAS and your name isn't listed here, it is
22941 not meant as a slight. We just don't know about it. Send mail to the
22942 maintainer, and we'll correct the situation. Currently the maintainer
22943 is Nick Clifton (email address `nickc@redhat.com').
22945 Dean Elsner wrote the original GNU assembler for the VAX.(1)
22947 Jay Fenlason maintained GAS for a while, adding support for
22948 GDB-specific debug information and the 68k series machines, most of the
22949 preprocessing pass, and extensive changes in `messages.c',
22950 `input-file.c', `write.c'.
22952 K. Richard Pixley maintained GAS for a while, adding various
22953 enhancements and many bug fixes, including merging support for several
22954 processors, breaking GAS up to handle multiple object file format back
22955 ends (including heavy rewrite, testing, an integration of the coff and
22956 b.out back ends), adding configuration including heavy testing and
22957 verification of cross assemblers and file splits and renaming,
22958 converted GAS to strictly ANSI C including full prototypes, added
22959 support for m680[34]0 and cpu32, did considerable work on i960
22960 including a COFF port (including considerable amounts of reverse
22961 engineering), a SPARC opcode file rewrite, DECstation, rs6000, and
22962 hp300hpux host ports, updated "know" assertions and made them work,
22963 much other reorganization, cleanup, and lint.
22965 Ken Raeburn wrote the high-level BFD interface code to replace most
22966 of the code in format-specific I/O modules.
22968 The original VMS support was contributed by David L. Kashtan. Eric
22969 Youngdale has done much work with it since.
22971 The Intel 80386 machine description was written by Eliot Dresselhaus.
22973 Minh Tran-Le at IntelliCorp contributed some AIX 386 support.
22975 The Motorola 88k machine description was contributed by Devon Bowen
22976 of Buffalo University and Torbjorn Granlund of the Swedish Institute of
22979 Keith Knowles at the Open Software Foundation wrote the original
22980 MIPS back end (`tc-mips.c', `tc-mips.h'), and contributed Rose format
22981 support (which hasn't been merged in yet). Ralph Campbell worked with
22982 the MIPS code to support a.out format.
22984 Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k,
22985 tc-h8300), and IEEE 695 object file format (obj-ieee), was written by
22986 Steve Chamberlain of Cygnus Support. Steve also modified the COFF back
22987 end to use BFD for some low-level operations, for use with the H8/300
22988 and AMD 29k targets.
22990 John Gilmore built the AMD 29000 support, added `.include' support,
22991 and simplified the configuration of which versions accept which
22992 directives. He updated the 68k machine description so that Motorola's
22993 opcodes always produced fixed-size instructions (e.g., `jsr'), while
22994 synthetic instructions remained shrinkable (`jbsr'). John fixed many
22995 bugs, including true tested cross-compilation support, and one bug in
22996 relaxation that took a week and required the proverbial one-bit fix.
22998 Ian Lance Taylor of Cygnus Support merged the Motorola and MIT
22999 syntax for the 68k, completed support for some COFF targets (68k, i386
23000 SVR3, and SCO Unix), added support for MIPS ECOFF and ELF targets,
23001 wrote the initial RS/6000 and PowerPC assembler, and made a few other
23004 Steve Chamberlain made GAS able to generate listings.
23006 Hewlett-Packard contributed support for the HP9000/300.
23008 Jeff Law wrote GAS and BFD support for the native HPPA object format
23009 (SOM) along with a fairly extensive HPPA testsuite (for both SOM and
23010 ELF object formats). This work was supported by both the Center for
23011 Software Science at the University of Utah and Cygnus Support.
23013 Support for ELF format files has been worked on by Mark Eichin of
23014 Cygnus Support (original, incomplete implementation for SPARC), Pete
23015 Hoogenboom and Jeff Law at the University of Utah (HPPA mainly),
23016 Michael Meissner of the Open Software Foundation (i386 mainly), and Ken
23017 Raeburn of Cygnus Support (sparc, and some initial 64-bit support).
23019 Linas Vepstas added GAS support for the ESA/390 "IBM 370"
23022 Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote
23023 GAS and BFD support for openVMS/Alpha.
23025 Timothy Wall, Michael Hayes, and Greg Smart contributed to the
23026 various tic* flavors.
23028 David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from
23029 Tensilica, Inc. added support for Xtensa processors.
23031 Several engineers at Cygnus Support have also provided many small
23032 bug fixes and configuration enhancements.
23034 Jon Beniston added support for the Lattice Mico32 architecture.
23036 Many others have contributed large or small bugfixes and
23037 enhancements. If you have contributed significant work and are not
23038 mentioned on this list, and want to be, let us know. Some of the
23039 history has been lost; we are not intentionally leaving anyone out.
23041 ---------- Footnotes ----------
23043 (1) Any more details?
23046 File: as.info, Node: GNU Free Documentation License, Next: AS Index, Prev: Acknowledgements, Up: Top
23048 Appendix A GNU Free Documentation License
23049 *****************************************
23051 Version 1.3, 3 November 2008
23053 Copyright (C) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc.
23056 Everyone is permitted to copy and distribute verbatim copies
23057 of this license document, but changing it is not allowed.
23061 The purpose of this License is to make a manual, textbook, or other
23062 functional and useful document "free" in the sense of freedom: to
23063 assure everyone the effective freedom to copy and redistribute it,
23064 with or without modifying it, either commercially or
23065 noncommercially. Secondarily, this License preserves for the
23066 author and publisher a way to get credit for their work, while not
23067 being considered responsible for modifications made by others.
23069 This License is a kind of "copyleft", which means that derivative
23070 works of the document must themselves be free in the same sense.
23071 It complements the GNU General Public License, which is a copyleft
23072 license designed for free software.
23074 We have designed this License in order to use it for manuals for
23075 free software, because free software needs free documentation: a
23076 free program should come with manuals providing the same freedoms
23077 that the software does. But this License is not limited to
23078 software manuals; it can be used for any textual work, regardless
23079 of subject matter or whether it is published as a printed book.
23080 We recommend this License principally for works whose purpose is
23081 instruction or reference.
23083 1. APPLICABILITY AND DEFINITIONS
23085 This License applies to any manual or other work, in any medium,
23086 that contains a notice placed by the copyright holder saying it
23087 can be distributed under the terms of this License. Such a notice
23088 grants a world-wide, royalty-free license, unlimited in duration,
23089 to use that work under the conditions stated herein. The
23090 "Document", below, refers to any such manual or work. Any member
23091 of the public is a licensee, and is addressed as "you". You
23092 accept the license if you copy, modify or distribute the work in a
23093 way requiring permission under copyright law.
23095 A "Modified Version" of the Document means any work containing the
23096 Document or a portion of it, either copied verbatim, or with
23097 modifications and/or translated into another language.
23099 A "Secondary Section" is a named appendix or a front-matter section
23100 of the Document that deals exclusively with the relationship of the
23101 publishers or authors of the Document to the Document's overall
23102 subject (or to related matters) and contains nothing that could
23103 fall directly within that overall subject. (Thus, if the Document
23104 is in part a textbook of mathematics, a Secondary Section may not
23105 explain any mathematics.) The relationship could be a matter of
23106 historical connection with the subject or with related matters, or
23107 of legal, commercial, philosophical, ethical or political position
23110 The "Invariant Sections" are certain Secondary Sections whose
23111 titles are designated, as being those of Invariant Sections, in
23112 the notice that says that the Document is released under this
23113 License. If a section does not fit the above definition of
23114 Secondary then it is not allowed to be designated as Invariant.
23115 The Document may contain zero Invariant Sections. If the Document
23116 does not identify any Invariant Sections then there are none.
23118 The "Cover Texts" are certain short passages of text that are
23119 listed, as Front-Cover Texts or Back-Cover Texts, in the notice
23120 that says that the Document is released under this License. A
23121 Front-Cover Text may be at most 5 words, and a Back-Cover Text may
23122 be at most 25 words.
23124 A "Transparent" copy of the Document means a machine-readable copy,
23125 represented in a format whose specification is available to the
23126 general public, that is suitable for revising the document
23127 straightforwardly with generic text editors or (for images
23128 composed of pixels) generic paint programs or (for drawings) some
23129 widely available drawing editor, and that is suitable for input to
23130 text formatters or for automatic translation to a variety of
23131 formats suitable for input to text formatters. A copy made in an
23132 otherwise Transparent file format whose markup, or absence of
23133 markup, has been arranged to thwart or discourage subsequent
23134 modification by readers is not Transparent. An image format is
23135 not Transparent if used for any substantial amount of text. A
23136 copy that is not "Transparent" is called "Opaque".
23138 Examples of suitable formats for Transparent copies include plain
23139 ASCII without markup, Texinfo input format, LaTeX input format,
23140 SGML or XML using a publicly available DTD, and
23141 standard-conforming simple HTML, PostScript or PDF designed for
23142 human modification. Examples of transparent image formats include
23143 PNG, XCF and JPG. Opaque formats include proprietary formats that
23144 can be read and edited only by proprietary word processors, SGML or
23145 XML for which the DTD and/or processing tools are not generally
23146 available, and the machine-generated HTML, PostScript or PDF
23147 produced by some word processors for output purposes only.
23149 The "Title Page" means, for a printed book, the title page itself,
23150 plus such following pages as are needed to hold, legibly, the
23151 material this License requires to appear in the title page. For
23152 works in formats which do not have any title page as such, "Title
23153 Page" means the text near the most prominent appearance of the
23154 work's title, preceding the beginning of the body of the text.
23156 The "publisher" means any person or entity that distributes copies
23157 of the Document to the public.
23159 A section "Entitled XYZ" means a named subunit of the Document
23160 whose title either is precisely XYZ or contains XYZ in parentheses
23161 following text that translates XYZ in another language. (Here XYZ
23162 stands for a specific section name mentioned below, such as
23163 "Acknowledgements", "Dedications", "Endorsements", or "History".)
23164 To "Preserve the Title" of such a section when you modify the
23165 Document means that it remains a section "Entitled XYZ" according
23166 to this definition.
23168 The Document may include Warranty Disclaimers next to the notice
23169 which states that this License applies to the Document. These
23170 Warranty Disclaimers are considered to be included by reference in
23171 this License, but only as regards disclaiming warranties: any other
23172 implication that these Warranty Disclaimers may have is void and
23173 has no effect on the meaning of this License.
23175 2. VERBATIM COPYING
23177 You may copy and distribute the Document in any medium, either
23178 commercially or noncommercially, provided that this License, the
23179 copyright notices, and the license notice saying this License
23180 applies to the Document are reproduced in all copies, and that you
23181 add no other conditions whatsoever to those of this License. You
23182 may not use technical measures to obstruct or control the reading
23183 or further copying of the copies you make or distribute. However,
23184 you may accept compensation in exchange for copies. If you
23185 distribute a large enough number of copies you must also follow
23186 the conditions in section 3.
23188 You may also lend copies, under the same conditions stated above,
23189 and you may publicly display copies.
23191 3. COPYING IN QUANTITY
23193 If you publish printed copies (or copies in media that commonly
23194 have printed covers) of the Document, numbering more than 100, and
23195 the Document's license notice requires Cover Texts, you must
23196 enclose the copies in covers that carry, clearly and legibly, all
23197 these Cover Texts: Front-Cover Texts on the front cover, and
23198 Back-Cover Texts on the back cover. Both covers must also clearly
23199 and legibly identify you as the publisher of these copies. The
23200 front cover must present the full title with all words of the
23201 title equally prominent and visible. You may add other material
23202 on the covers in addition. Copying with changes limited to the
23203 covers, as long as they preserve the title of the Document and
23204 satisfy these conditions, can be treated as verbatim copying in
23207 If the required texts for either cover are too voluminous to fit
23208 legibly, you should put the first ones listed (as many as fit
23209 reasonably) on the actual cover, and continue the rest onto
23212 If you publish or distribute Opaque copies of the Document
23213 numbering more than 100, you must either include a
23214 machine-readable Transparent copy along with each Opaque copy, or
23215 state in or with each Opaque copy a computer-network location from
23216 which the general network-using public has access to download
23217 using public-standard network protocols a complete Transparent
23218 copy of the Document, free of added material. If you use the
23219 latter option, you must take reasonably prudent steps, when you
23220 begin distribution of Opaque copies in quantity, to ensure that
23221 this Transparent copy will remain thus accessible at the stated
23222 location until at least one year after the last time you
23223 distribute an Opaque copy (directly or through your agents or
23224 retailers) of that edition to the public.
23226 It is requested, but not required, that you contact the authors of
23227 the Document well before redistributing any large number of
23228 copies, to give them a chance to provide you with an updated
23229 version of the Document.
23233 You may copy and distribute a Modified Version of the Document
23234 under the conditions of sections 2 and 3 above, provided that you
23235 release the Modified Version under precisely this License, with
23236 the Modified Version filling the role of the Document, thus
23237 licensing distribution and modification of the Modified Version to
23238 whoever possesses a copy of it. In addition, you must do these
23239 things in the Modified Version:
23241 A. Use in the Title Page (and on the covers, if any) a title
23242 distinct from that of the Document, and from those of
23243 previous versions (which should, if there were any, be listed
23244 in the History section of the Document). You may use the
23245 same title as a previous version if the original publisher of
23246 that version gives permission.
23248 B. List on the Title Page, as authors, one or more persons or
23249 entities responsible for authorship of the modifications in
23250 the Modified Version, together with at least five of the
23251 principal authors of the Document (all of its principal
23252 authors, if it has fewer than five), unless they release you
23253 from this requirement.
23255 C. State on the Title page the name of the publisher of the
23256 Modified Version, as the publisher.
23258 D. Preserve all the copyright notices of the Document.
23260 E. Add an appropriate copyright notice for your modifications
23261 adjacent to the other copyright notices.
23263 F. Include, immediately after the copyright notices, a license
23264 notice giving the public permission to use the Modified
23265 Version under the terms of this License, in the form shown in
23266 the Addendum below.
23268 G. Preserve in that license notice the full lists of Invariant
23269 Sections and required Cover Texts given in the Document's
23272 H. Include an unaltered copy of this License.
23274 I. Preserve the section Entitled "History", Preserve its Title,
23275 and add to it an item stating at least the title, year, new
23276 authors, and publisher of the Modified Version as given on
23277 the Title Page. If there is no section Entitled "History" in
23278 the Document, create one stating the title, year, authors,
23279 and publisher of the Document as given on its Title Page,
23280 then add an item describing the Modified Version as stated in
23281 the previous sentence.
23283 J. Preserve the network location, if any, given in the Document
23284 for public access to a Transparent copy of the Document, and
23285 likewise the network locations given in the Document for
23286 previous versions it was based on. These may be placed in
23287 the "History" section. You may omit a network location for a
23288 work that was published at least four years before the
23289 Document itself, or if the original publisher of the version
23290 it refers to gives permission.
23292 K. For any section Entitled "Acknowledgements" or "Dedications",
23293 Preserve the Title of the section, and preserve in the
23294 section all the substance and tone of each of the contributor
23295 acknowledgements and/or dedications given therein.
23297 L. Preserve all the Invariant Sections of the Document,
23298 unaltered in their text and in their titles. Section numbers
23299 or the equivalent are not considered part of the section
23302 M. Delete any section Entitled "Endorsements". Such a section
23303 may not be included in the Modified Version.
23305 N. Do not retitle any existing section to be Entitled
23306 "Endorsements" or to conflict in title with any Invariant
23309 O. Preserve any Warranty Disclaimers.
23311 If the Modified Version includes new front-matter sections or
23312 appendices that qualify as Secondary Sections and contain no
23313 material copied from the Document, you may at your option
23314 designate some or all of these sections as invariant. To do this,
23315 add their titles to the list of Invariant Sections in the Modified
23316 Version's license notice. These titles must be distinct from any
23317 other section titles.
23319 You may add a section Entitled "Endorsements", provided it contains
23320 nothing but endorsements of your Modified Version by various
23321 parties--for example, statements of peer review or that the text
23322 has been approved by an organization as the authoritative
23323 definition of a standard.
23325 You may add a passage of up to five words as a Front-Cover Text,
23326 and a passage of up to 25 words as a Back-Cover Text, to the end
23327 of the list of Cover Texts in the Modified Version. Only one
23328 passage of Front-Cover Text and one of Back-Cover Text may be
23329 added by (or through arrangements made by) any one entity. If the
23330 Document already includes a cover text for the same cover,
23331 previously added by you or by arrangement made by the same entity
23332 you are acting on behalf of, you may not add another; but you may
23333 replace the old one, on explicit permission from the previous
23334 publisher that added the old one.
23336 The author(s) and publisher(s) of the Document do not by this
23337 License give permission to use their names for publicity for or to
23338 assert or imply endorsement of any Modified Version.
23340 5. COMBINING DOCUMENTS
23342 You may combine the Document with other documents released under
23343 this License, under the terms defined in section 4 above for
23344 modified versions, provided that you include in the combination
23345 all of the Invariant Sections of all of the original documents,
23346 unmodified, and list them all as Invariant Sections of your
23347 combined work in its license notice, and that you preserve all
23348 their Warranty Disclaimers.
23350 The combined work need only contain one copy of this License, and
23351 multiple identical Invariant Sections may be replaced with a single
23352 copy. If there are multiple Invariant Sections with the same name
23353 but different contents, make the title of each such section unique
23354 by adding at the end of it, in parentheses, the name of the
23355 original author or publisher of that section if known, or else a
23356 unique number. Make the same adjustment to the section titles in
23357 the list of Invariant Sections in the license notice of the
23360 In the combination, you must combine any sections Entitled
23361 "History" in the various original documents, forming one section
23362 Entitled "History"; likewise combine any sections Entitled
23363 "Acknowledgements", and any sections Entitled "Dedications". You
23364 must delete all sections Entitled "Endorsements."
23366 6. COLLECTIONS OF DOCUMENTS
23368 You may make a collection consisting of the Document and other
23369 documents released under this License, and replace the individual
23370 copies of this License in the various documents with a single copy
23371 that is included in the collection, provided that you follow the
23372 rules of this License for verbatim copying of each of the
23373 documents in all other respects.
23375 You may extract a single document from such a collection, and
23376 distribute it individually under this License, provided you insert
23377 a copy of this License into the extracted document, and follow
23378 this License in all other respects regarding verbatim copying of
23381 7. AGGREGATION WITH INDEPENDENT WORKS
23383 A compilation of the Document or its derivatives with other
23384 separate and independent documents or works, in or on a volume of
23385 a storage or distribution medium, is called an "aggregate" if the
23386 copyright resulting from the compilation is not used to limit the
23387 legal rights of the compilation's users beyond what the individual
23388 works permit. When the Document is included in an aggregate, this
23389 License does not apply to the other works in the aggregate which
23390 are not themselves derivative works of the Document.
23392 If the Cover Text requirement of section 3 is applicable to these
23393 copies of the Document, then if the Document is less than one half
23394 of the entire aggregate, the Document's Cover Texts may be placed
23395 on covers that bracket the Document within the aggregate, or the
23396 electronic equivalent of covers if the Document is in electronic
23397 form. Otherwise they must appear on printed covers that bracket
23398 the whole aggregate.
23402 Translation is considered a kind of modification, so you may
23403 distribute translations of the Document under the terms of section
23404 4. Replacing Invariant Sections with translations requires special
23405 permission from their copyright holders, but you may include
23406 translations of some or all Invariant Sections in addition to the
23407 original versions of these Invariant Sections. You may include a
23408 translation of this License, and all the license notices in the
23409 Document, and any Warranty Disclaimers, provided that you also
23410 include the original English version of this License and the
23411 original versions of those notices and disclaimers. In case of a
23412 disagreement between the translation and the original version of
23413 this License or a notice or disclaimer, the original version will
23416 If a section in the Document is Entitled "Acknowledgements",
23417 "Dedications", or "History", the requirement (section 4) to
23418 Preserve its Title (section 1) will typically require changing the
23423 You may not copy, modify, sublicense, or distribute the Document
23424 except as expressly provided under this License. Any attempt
23425 otherwise to copy, modify, sublicense, or distribute it is void,
23426 and will automatically terminate your rights under this License.
23428 However, if you cease all violation of this License, then your
23429 license from a particular copyright holder is reinstated (a)
23430 provisionally, unless and until the copyright holder explicitly
23431 and finally terminates your license, and (b) permanently, if the
23432 copyright holder fails to notify you of the violation by some
23433 reasonable means prior to 60 days after the cessation.
23435 Moreover, your license from a particular copyright holder is
23436 reinstated permanently if the copyright holder notifies you of the
23437 violation by some reasonable means, this is the first time you have
23438 received notice of violation of this License (for any work) from
23439 that copyright holder, and you cure the violation prior to 30 days
23440 after your receipt of the notice.
23442 Termination of your rights under this section does not terminate
23443 the licenses of parties who have received copies or rights from
23444 you under this License. If your rights have been terminated and
23445 not permanently reinstated, receipt of a copy of some or all of
23446 the same material does not give you any rights to use it.
23448 10. FUTURE REVISIONS OF THIS LICENSE
23450 The Free Software Foundation may publish new, revised versions of
23451 the GNU Free Documentation License from time to time. Such new
23452 versions will be similar in spirit to the present version, but may
23453 differ in detail to address new problems or concerns. See
23454 `http://www.gnu.org/copyleft/'.
23456 Each version of the License is given a distinguishing version
23457 number. If the Document specifies that a particular numbered
23458 version of this License "or any later version" applies to it, you
23459 have the option of following the terms and conditions either of
23460 that specified version or of any later version that has been
23461 published (not as a draft) by the Free Software Foundation. If
23462 the Document does not specify a version number of this License,
23463 you may choose any version ever published (not as a draft) by the
23464 Free Software Foundation. If the Document specifies that a proxy
23465 can decide which future versions of this License can be used, that
23466 proxy's public statement of acceptance of a version permanently
23467 authorizes you to choose that version for the Document.
23471 "Massive Multiauthor Collaboration Site" (or "MMC Site") means any
23472 World Wide Web server that publishes copyrightable works and also
23473 provides prominent facilities for anybody to edit those works. A
23474 public wiki that anybody can edit is an example of such a server.
23475 A "Massive Multiauthor Collaboration" (or "MMC") contained in the
23476 site means any set of copyrightable works thus published on the MMC
23479 "CC-BY-SA" means the Creative Commons Attribution-Share Alike 3.0
23480 license published by Creative Commons Corporation, a not-for-profit
23481 corporation with a principal place of business in San Francisco,
23482 California, as well as future copyleft versions of that license
23483 published by that same organization.
23485 "Incorporate" means to publish or republish a Document, in whole or
23486 in part, as part of another Document.
23488 An MMC is "eligible for relicensing" if it is licensed under this
23489 License, and if all works that were first published under this
23490 License somewhere other than this MMC, and subsequently
23491 incorporated in whole or in part into the MMC, (1) had no cover
23492 texts or invariant sections, and (2) were thus incorporated prior
23493 to November 1, 2008.
23495 The operator of an MMC Site may republish an MMC contained in the
23496 site under CC-BY-SA on the same site at any time before August 1,
23497 2009, provided the MMC is eligible for relicensing.
23500 ADDENDUM: How to use this License for your documents
23501 ====================================================
23503 To use this License in a document you have written, include a copy of
23504 the License in the document and put the following copyright and license
23505 notices just after the title page:
23507 Copyright (C) YEAR YOUR NAME.
23508 Permission is granted to copy, distribute and/or modify this document
23509 under the terms of the GNU Free Documentation License, Version 1.3
23510 or any later version published by the Free Software Foundation;
23511 with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
23512 Texts. A copy of the license is included in the section entitled ``GNU
23513 Free Documentation License''.
23515 If you have Invariant Sections, Front-Cover Texts and Back-Cover
23516 Texts, replace the "with...Texts." line with this:
23518 with the Invariant Sections being LIST THEIR TITLES, with
23519 the Front-Cover Texts being LIST, and with the Back-Cover Texts
23522 If you have Invariant Sections without Cover Texts, or some other
23523 combination of the three, merge those two alternatives to suit the
23526 If your document contains nontrivial examples of program code, we
23527 recommend releasing these examples in parallel under your choice of
23528 free software license, such as the GNU General Public License, to
23529 permit their use in free software.
23532 File: as.info, Node: AS Index, Prev: GNU Free Documentation License, Up: Top
23540 * #: Comments. (line 33)
23541 * #APP: Preprocessing. (line 27)
23542 * #NO_APP: Preprocessing. (line 27)
23543 * $ in symbol names <1>: D10V-Chars. (line 53)
23544 * $ in symbol names <2>: SH-Chars. (line 15)
23545 * $ in symbol names <3>: SH64-Chars. (line 15)
23546 * $ in symbol names <4>: Meta-Chars. (line 10)
23547 * $ in symbol names: D30V-Chars. (line 70)
23548 * $a: ARM Mapping Symbols. (line 9)
23549 * $acos math builtin, TIC54X: TIC54X-Builtins. (line 10)
23550 * $asin math builtin, TIC54X: TIC54X-Builtins. (line 13)
23551 * $atan math builtin, TIC54X: TIC54X-Builtins. (line 16)
23552 * $atan2 math builtin, TIC54X: TIC54X-Builtins. (line 19)
23553 * $ceil math builtin, TIC54X: TIC54X-Builtins. (line 22)
23554 * $cos math builtin, TIC54X: TIC54X-Builtins. (line 28)
23555 * $cosh math builtin, TIC54X: TIC54X-Builtins. (line 25)
23556 * $cvf math builtin, TIC54X: TIC54X-Builtins. (line 31)
23557 * $cvi math builtin, TIC54X: TIC54X-Builtins. (line 34)
23558 * $d <1>: AArch64 Mapping Symbols.
23560 * $d: ARM Mapping Symbols. (line 15)
23561 * $exp math builtin, TIC54X: TIC54X-Builtins. (line 37)
23562 * $fabs math builtin, TIC54X: TIC54X-Builtins. (line 40)
23563 * $firstch subsym builtin, TIC54X: TIC54X-Macros. (line 26)
23564 * $floor math builtin, TIC54X: TIC54X-Builtins. (line 43)
23565 * $fmod math builtin, TIC54X: TIC54X-Builtins. (line 47)
23566 * $int math builtin, TIC54X: TIC54X-Builtins. (line 50)
23567 * $iscons subsym builtin, TIC54X: TIC54X-Macros. (line 43)
23568 * $isdefed subsym builtin, TIC54X: TIC54X-Macros. (line 34)
23569 * $ismember subsym builtin, TIC54X: TIC54X-Macros. (line 38)
23570 * $isname subsym builtin, TIC54X: TIC54X-Macros. (line 47)
23571 * $isreg subsym builtin, TIC54X: TIC54X-Macros. (line 50)
23572 * $lastch subsym builtin, TIC54X: TIC54X-Macros. (line 30)
23573 * $ldexp math builtin, TIC54X: TIC54X-Builtins. (line 53)
23574 * $log math builtin, TIC54X: TIC54X-Builtins. (line 59)
23575 * $log10 math builtin, TIC54X: TIC54X-Builtins. (line 56)
23576 * $max math builtin, TIC54X: TIC54X-Builtins. (line 62)
23577 * $min math builtin, TIC54X: TIC54X-Builtins. (line 65)
23578 * $pow math builtin, TIC54X: TIC54X-Builtins. (line 68)
23579 * $round math builtin, TIC54X: TIC54X-Builtins. (line 71)
23580 * $sgn math builtin, TIC54X: TIC54X-Builtins. (line 74)
23581 * $sin math builtin, TIC54X: TIC54X-Builtins. (line 77)
23582 * $sinh math builtin, TIC54X: TIC54X-Builtins. (line 80)
23583 * $sqrt math builtin, TIC54X: TIC54X-Builtins. (line 83)
23584 * $structacc subsym builtin, TIC54X: TIC54X-Macros. (line 57)
23585 * $structsz subsym builtin, TIC54X: TIC54X-Macros. (line 54)
23586 * $symcmp subsym builtin, TIC54X: TIC54X-Macros. (line 23)
23587 * $symlen subsym builtin, TIC54X: TIC54X-Macros. (line 20)
23588 * $t: ARM Mapping Symbols. (line 12)
23589 * $tan math builtin, TIC54X: TIC54X-Builtins. (line 86)
23590 * $tanh math builtin, TIC54X: TIC54X-Builtins. (line 89)
23591 * $trunc math builtin, TIC54X: TIC54X-Builtins. (line 92)
23592 * $x: AArch64 Mapping Symbols.
23594 * %gp: RX-Modifiers. (line 6)
23595 * %gpreg: RX-Modifiers. (line 22)
23596 * %pidreg: RX-Modifiers. (line 25)
23597 * -+ option, VAX/VMS: VAX-Opts. (line 71)
23598 * --: Command Line. (line 10)
23599 * --32 option, i386: i386-Options. (line 8)
23600 * --32 option, x86-64: i386-Options. (line 8)
23601 * --64 option, i386: i386-Options. (line 8)
23602 * --64 option, x86-64: i386-Options. (line 8)
23603 * --absolute-literals: Xtensa Options. (line 21)
23604 * --allow-reg-prefix: SH Options. (line 9)
23605 * --alternate: alternate. (line 6)
23606 * --base-size-default-16: M68K-Opts. (line 65)
23607 * --base-size-default-32: M68K-Opts. (line 65)
23608 * --big: SH Options. (line 9)
23609 * --bitwise-or option, M680x0: M68K-Opts. (line 58)
23610 * --disp-size-default-16: M68K-Opts. (line 74)
23611 * --disp-size-default-32: M68K-Opts. (line 74)
23612 * --divide option, i386: i386-Options. (line 24)
23613 * --dsp: SH Options. (line 9)
23614 * --emulation=crisaout command line option, CRIS: CRIS-Opts. (line 9)
23615 * --emulation=criself command line option, CRIS: CRIS-Opts. (line 9)
23616 * --enforce-aligned-data: Sparc-Aligned-Data. (line 11)
23617 * --fatal-warnings: W. (line 16)
23618 * --fdpic: SH Options. (line 31)
23619 * --fix-v4bx command line option, ARM: ARM Options. (line 173)
23620 * --fixed-special-register-names command line option, MMIX: MMIX-Opts.
23622 * --force-long-branches: M68HC11-Opts. (line 82)
23623 * --generate-example: M68HC11-Opts. (line 99)
23624 * --globalize-symbols command line option, MMIX: MMIX-Opts. (line 12)
23625 * --gnu-syntax command line option, MMIX: MMIX-Opts. (line 16)
23626 * --hash-size=NUMBER: Overview. (line 421)
23627 * --linker-allocated-gregs command line option, MMIX: MMIX-Opts.
23629 * --listing-cont-lines: listing. (line 34)
23630 * --listing-lhs-width: listing. (line 16)
23631 * --listing-lhs-width2: listing. (line 21)
23632 * --listing-rhs-width: listing. (line 28)
23633 * --little: SH Options. (line 9)
23634 * --longcalls: Xtensa Options. (line 35)
23635 * --march=ARCHITECTURE command line option, CRIS: CRIS-Opts. (line 34)
23636 * --MD: MD. (line 6)
23637 * --mul-bug-abort command line option, CRIS: CRIS-Opts. (line 62)
23638 * --no-absolute-literals: Xtensa Options. (line 21)
23639 * --no-expand command line option, MMIX: MMIX-Opts. (line 31)
23640 * --no-longcalls: Xtensa Options. (line 35)
23641 * --no-merge-gregs command line option, MMIX: MMIX-Opts. (line 36)
23642 * --no-mul-bug-abort command line option, CRIS: CRIS-Opts. (line 62)
23643 * --no-predefined-syms command line option, MMIX: MMIX-Opts. (line 22)
23644 * --no-pushj-stubs command line option, MMIX: MMIX-Opts. (line 54)
23645 * --no-stubs command line option, MMIX: MMIX-Opts. (line 54)
23646 * --no-target-align: Xtensa Options. (line 28)
23647 * --no-text-section-literals: Xtensa Options. (line 7)
23648 * --no-trampolines: Xtensa Options. (line 56)
23649 * --no-transform: Xtensa Options. (line 44)
23650 * --no-underscore command line option, CRIS: CRIS-Opts. (line 15)
23651 * --no-warn: W. (line 11)
23652 * --pcrel: M68K-Opts. (line 86)
23653 * --pic command line option, CRIS: CRIS-Opts. (line 27)
23654 * --print-insn-syntax <1>: M68HC11-Opts. (line 88)
23655 * --print-insn-syntax: XGATE-Opts. (line 25)
23656 * --print-opcodes <1>: M68HC11-Opts. (line 92)
23657 * --print-opcodes: XGATE-Opts. (line 29)
23658 * --register-prefix-optional option, M680x0: M68K-Opts. (line 45)
23659 * --relax: SH Options. (line 9)
23660 * --relax command line option, MMIX: MMIX-Opts. (line 19)
23661 * --rename-section: Xtensa Options. (line 52)
23662 * --renesas: SH Options. (line 9)
23663 * --short-branches: M68HC11-Opts. (line 67)
23664 * --small: SH Options. (line 9)
23665 * --statistics: statistics. (line 6)
23666 * --strict-direct-mode: M68HC11-Opts. (line 57)
23667 * --target-align: Xtensa Options. (line 28)
23668 * --text-section-literals: Xtensa Options. (line 7)
23669 * --traditional-format: traditional-format. (line 6)
23670 * --trampolines: Xtensa Options. (line 56)
23671 * --transform: Xtensa Options. (line 44)
23672 * --underscore command line option, CRIS: CRIS-Opts. (line 15)
23673 * --warn: W. (line 19)
23674 * --x32 option, i386: i386-Options. (line 8)
23675 * --x32 option, x86-64: i386-Options. (line 8)
23676 * --xgate-ramoffset: M68HC11-Opts. (line 36)
23677 * -1 option, VAX/VMS: VAX-Opts. (line 77)
23678 * -32addr command line option, Alpha: Alpha Options. (line 57)
23680 * -A options, i960: Options-i960. (line 6)
23686 * -Aleon: Sparc-Opts. (line 25)
23689 * -Asparc: Sparc-Opts. (line 25)
23690 * -Asparcfmaf: Sparc-Opts. (line 25)
23691 * -Asparcima: Sparc-Opts. (line 25)
23692 * -Asparclet: Sparc-Opts. (line 25)
23693 * -Asparclite: Sparc-Opts. (line 25)
23694 * -Asparcvis: Sparc-Opts. (line 25)
23695 * -Asparcvis2: Sparc-Opts. (line 25)
23696 * -Asparcvis3: Sparc-Opts. (line 25)
23697 * -Asparcvis3r: Sparc-Opts. (line 25)
23698 * -Av6: Sparc-Opts. (line 25)
23699 * -Av7: Sparc-Opts. (line 25)
23700 * -Av8: Sparc-Opts. (line 25)
23701 * -Av9: Sparc-Opts. (line 25)
23702 * -Av9a: Sparc-Opts. (line 25)
23703 * -Av9b: Sparc-Opts. (line 25)
23704 * -Av9c: Sparc-Opts. (line 25)
23705 * -Av9d: Sparc-Opts. (line 25)
23706 * -Av9e: Sparc-Opts. (line 25)
23707 * -Av9m: Sparc-Opts. (line 25)
23708 * -Av9v: Sparc-Opts. (line 25)
23709 * -b option, i960: Options-i960. (line 22)
23710 * -big option, M32R: M32R-Opts. (line 35)
23712 * -D, ignored on VAX: VAX-Opts. (line 11)
23713 * -d, VAX option: VAX-Opts. (line 16)
23714 * -eabi= command line option, ARM: ARM Options. (line 156)
23715 * -EB command line option, AArch64: AArch64 Options. (line 6)
23716 * -EB command line option, ARC: ARC Options. (line 31)
23717 * -EB command line option, ARM: ARM Options. (line 161)
23718 * -EB option (MIPS): MIPS Options. (line 13)
23719 * -EB option, M32R: M32R-Opts. (line 39)
23720 * -EB option, TILE-Gx: TILE-Gx Options. (line 11)
23721 * -EL command line option, AArch64: AArch64 Options. (line 10)
23722 * -EL command line option, ARC: ARC Options. (line 35)
23723 * -EL command line option, ARM: ARM Options. (line 165)
23724 * -EL option (MIPS): MIPS Options. (line 13)
23725 * -EL option, M32R: M32R-Opts. (line 32)
23726 * -EL option, TILE-Gx: TILE-Gx Options. (line 11)
23728 * -F command line option, Alpha: Alpha Options. (line 57)
23729 * -G command line option, Alpha: Alpha Options. (line 53)
23730 * -g command line option, Alpha: Alpha Options. (line 47)
23731 * -G option (MIPS): MIPS Options. (line 8)
23732 * -h option, VAX/VMS: VAX-Opts. (line 45)
23733 * -H option, VAX/VMS: VAX-Opts. (line 81)
23734 * -I PATH: I. (line 6)
23735 * -ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 87)
23736 * -Ip option, M32RX: M32R-Opts. (line 97)
23737 * -J, ignored on VAX: VAX-Opts. (line 27)
23739 * -k command line option, ARM: ARM Options. (line 169)
23740 * -KPIC option, M32R: M32R-Opts. (line 42)
23741 * -KPIC option, MIPS: MIPS Options. (line 21)
23743 * -l option, M680x0: M68K-Opts. (line 33)
23744 * -little option, M32R: M32R-Opts. (line 27)
23746 * -m11/03: PDP-11-Options. (line 140)
23747 * -m11/04: PDP-11-Options. (line 143)
23748 * -m11/05: PDP-11-Options. (line 146)
23749 * -m11/10: PDP-11-Options. (line 146)
23750 * -m11/15: PDP-11-Options. (line 149)
23751 * -m11/20: PDP-11-Options. (line 149)
23752 * -m11/21: PDP-11-Options. (line 152)
23753 * -m11/23: PDP-11-Options. (line 155)
23754 * -m11/24: PDP-11-Options. (line 155)
23755 * -m11/34: PDP-11-Options. (line 158)
23756 * -m11/34a: PDP-11-Options. (line 161)
23757 * -m11/35: PDP-11-Options. (line 164)
23758 * -m11/40: PDP-11-Options. (line 164)
23759 * -m11/44: PDP-11-Options. (line 167)
23760 * -m11/45: PDP-11-Options. (line 170)
23761 * -m11/50: PDP-11-Options. (line 170)
23762 * -m11/53: PDP-11-Options. (line 173)
23763 * -m11/55: PDP-11-Options. (line 170)
23764 * -m11/60: PDP-11-Options. (line 176)
23765 * -m11/70: PDP-11-Options. (line 170)
23766 * -m11/73: PDP-11-Options. (line 173)
23767 * -m11/83: PDP-11-Options. (line 173)
23768 * -m11/84: PDP-11-Options. (line 173)
23769 * -m11/93: PDP-11-Options. (line 173)
23770 * -m11/94: PDP-11-Options. (line 173)
23771 * -m16c option, M16C: M32C-Opts. (line 12)
23772 * -m31 option, s390: s390 Options. (line 8)
23773 * -m32 option, TILE-Gx: TILE-Gx Options. (line 8)
23774 * -m32bit-doubles: RX-Opts. (line 9)
23775 * -m32c option, M32C: M32C-Opts. (line 9)
23776 * -m32r option, M32R: M32R-Opts. (line 21)
23777 * -m32rx option, M32R2: M32R-Opts. (line 17)
23778 * -m32rx option, M32RX: M32R-Opts. (line 9)
23779 * -m4byte-align command line option, V850: V850 Options. (line 90)
23780 * -m64 option, s390: s390 Options. (line 8)
23781 * -m64 option, TILE-Gx: TILE-Gx Options. (line 8)
23782 * -m64bit-doubles: RX-Opts. (line 15)
23783 * -m68000 and related options: M68K-Opts. (line 98)
23784 * -m68hc11: M68HC11-Opts. (line 9)
23785 * -m68hc12: M68HC11-Opts. (line 14)
23786 * -m68hcs12: M68HC11-Opts. (line 21)
23787 * -m8byte-align command line option, V850: V850 Options. (line 86)
23788 * -m[no-]68851 command line option, M680x0: M68K-Opts. (line 21)
23789 * -m[no-]68881 command line option, M680x0: M68K-Opts. (line 21)
23790 * -m[no-]div command line option, M680x0: M68K-Opts. (line 21)
23791 * -m[no-]emac command line option, M680x0: M68K-Opts. (line 21)
23792 * -m[no-]float command line option, M680x0: M68K-Opts. (line 21)
23793 * -m[no-]mac command line option, M680x0: M68K-Opts. (line 21)
23794 * -m[no-]usp command line option, M680x0: M68K-Opts. (line 21)
23795 * -mabi= command line option, AArch64: AArch64 Options. (line 14)
23796 * -madd-bnd-prefix option, i386: i386-Options. (line 126)
23797 * -madd-bnd-prefix option, x86-64: i386-Options. (line 126)
23798 * -mall: PDP-11-Options. (line 26)
23799 * -mall-enabled command line option, LM32: LM32 Options. (line 30)
23800 * -mall-extensions: PDP-11-Options. (line 26)
23801 * -mall-opcodes command line option, AVR: AVR Options. (line 109)
23802 * -mapcs-26 command line option, ARM: ARM Options. (line 128)
23803 * -mapcs-32 command line option, ARM: ARM Options. (line 128)
23804 * -mapcs-float command line option, ARM: ARM Options. (line 142)
23805 * -mapcs-reentrant command line option, ARM: ARM Options. (line 147)
23806 * -marc[5|6|7|8] command line option, ARC: ARC Options. (line 6)
23807 * -march= command line option, AArch64: AArch64 Options. (line 37)
23808 * -march= command line option, ARM: ARM Options. (line 65)
23809 * -march= command line option, M680x0: M68K-Opts. (line 8)
23810 * -march= command line option, TIC6X: TIC6X Options. (line 6)
23811 * -march= option, i386: i386-Options. (line 31)
23812 * -march= option, s390: s390 Options. (line 25)
23813 * -march= option, x86-64: i386-Options. (line 31)
23814 * -matpcs command line option, ARM: ARM Options. (line 134)
23815 * -mavxscalar= option, i386: i386-Options. (line 84)
23816 * -mavxscalar= option, x86-64: i386-Options. (line 84)
23817 * -mbarrel-shift-enabled command line option, LM32: LM32 Options.
23819 * -mbig-endian: RX-Opts. (line 20)
23820 * -mbig-obj option, x86-64: i386-Options. (line 131)
23821 * -mbreak-enabled command line option, LM32: LM32 Options. (line 27)
23822 * -mccs command line option, ARM: ARM Options. (line 182)
23823 * -mcis: PDP-11-Options. (line 32)
23824 * -mconstant-gp command line option, IA-64: IA-64 Options. (line 6)
23825 * -mCPU command line option, Alpha: Alpha Options. (line 6)
23826 * -mcpu option, cpu: TIC54X-Opts. (line 15)
23827 * -mcpu=: RX-Opts. (line 75)
23828 * -mcpu= command line option, AArch64: AArch64 Options. (line 19)
23829 * -mcpu= command line option, ARM: ARM Options. (line 6)
23830 * -mcpu= command line option, Blackfin: Blackfin Options. (line 6)
23831 * -mcpu= command line option, M680x0: M68K-Opts. (line 14)
23832 * -mcsm: PDP-11-Options. (line 43)
23833 * -mdcache-enabled command line option, LM32: LM32 Options. (line 24)
23834 * -mdebug command line option, Alpha: Alpha Options. (line 25)
23835 * -mdivide-enabled command line option, LM32: LM32 Options. (line 9)
23836 * -mdsbt command line option, TIC6X: TIC6X Options. (line 13)
23837 * -me option, stderr redirect: TIC54X-Opts. (line 20)
23838 * -meis: PDP-11-Options. (line 46)
23839 * -mepiphany command line option, Epiphany: Epiphany Options. (line 9)
23840 * -mepiphany16 command line option, Epiphany: Epiphany Options.
23842 * -merrors-to-file option, stderr redirect: TIC54X-Opts. (line 20)
23843 * -mesa option, s390: s390 Options. (line 17)
23844 * -mevexlig= option, i386: i386-Options. (line 92)
23845 * -mevexlig= option, x86-64: i386-Options. (line 92)
23846 * -mevexrcig= option, i386: i386-Options. (line 144)
23847 * -mevexrcig= option, x86-64: i386-Options. (line 144)
23848 * -mevexwig= option, i386: i386-Options. (line 102)
23849 * -mevexwig= option, x86-64: i386-Options. (line 102)
23850 * -mf option, far-mode: TIC54X-Opts. (line 8)
23851 * -mf11: PDP-11-Options. (line 122)
23852 * -mfar-mode option, far-mode: TIC54X-Opts. (line 8)
23853 * -mfdpic command line option, Blackfin: Blackfin Options. (line 19)
23854 * -mfis: PDP-11-Options. (line 51)
23855 * -mfloat-abi= command line option, ARM: ARM Options. (line 151)
23856 * -mfp-11: PDP-11-Options. (line 56)
23857 * -mfpp: PDP-11-Options. (line 56)
23858 * -mfpu: PDP-11-Options. (line 56)
23859 * -mfpu= command line option, ARM: ARM Options. (line 81)
23860 * -mgcc-abi: RX-Opts. (line 63)
23861 * -mgcc-abi command line option, V850: V850 Options. (line 79)
23862 * -micache-enabled command line option, LM32: LM32 Options. (line 21)
23863 * -mimplicit-it command line option, ARM: ARM Options. (line 112)
23864 * -mint-register: RX-Opts. (line 57)
23865 * -mip2022 option, IP2K: IP2K-Opts. (line 14)
23866 * -mip2022ext option, IP2022: IP2K-Opts. (line 9)
23867 * -mj11: PDP-11-Options. (line 126)
23868 * -mka11: PDP-11-Options. (line 92)
23869 * -mkb11: PDP-11-Options. (line 95)
23870 * -mkd11a: PDP-11-Options. (line 98)
23871 * -mkd11b: PDP-11-Options. (line 101)
23872 * -mkd11d: PDP-11-Options. (line 104)
23873 * -mkd11e: PDP-11-Options. (line 107)
23874 * -mkd11f: PDP-11-Options. (line 110)
23875 * -mkd11h: PDP-11-Options. (line 110)
23876 * -mkd11k: PDP-11-Options. (line 114)
23877 * -mkd11q: PDP-11-Options. (line 110)
23878 * -mkd11z: PDP-11-Options. (line 118)
23879 * -mkev11: PDP-11-Options. (line 51)
23880 * -mlimited-eis: PDP-11-Options. (line 64)
23881 * -mlittle-endian: RX-Opts. (line 26)
23882 * -mlong <1>: XGATE-Opts. (line 13)
23883 * -mlong: M68HC11-Opts. (line 45)
23884 * -mlong-double <1>: XGATE-Opts. (line 21)
23885 * -mlong-double: M68HC11-Opts. (line 53)
23886 * -mm9s12x: M68HC11-Opts. (line 27)
23887 * -mm9s12xg: M68HC11-Opts. (line 32)
23888 * -mmcu= command line option, AVR: AVR Options. (line 6)
23889 * -mmfpt: PDP-11-Options. (line 70)
23890 * -mmicrocode: PDP-11-Options. (line 83)
23891 * -mmnemonic= option, i386: i386-Options. (line 109)
23892 * -mmnemonic= option, x86-64: i386-Options. (line 109)
23893 * -mmultiply-enabled command line option, LM32: LM32 Options. (line 6)
23894 * -mmutiproc: PDP-11-Options. (line 73)
23895 * -mmxps: PDP-11-Options. (line 77)
23896 * -mnaked-reg option, i386: i386-Options. (line 121)
23897 * -mnaked-reg option, x86-64: i386-Options. (line 121)
23898 * -mnan= command line option, MIPS: MIPS Options. (line 339)
23899 * -mno-cis: PDP-11-Options. (line 32)
23900 * -mno-csm: PDP-11-Options. (line 43)
23901 * -mno-dsbt command line option, TIC6X: TIC6X Options. (line 13)
23902 * -mno-eis: PDP-11-Options. (line 46)
23903 * -mno-extensions: PDP-11-Options. (line 29)
23904 * -mno-fdpic command line option, Blackfin: Blackfin Options. (line 22)
23905 * -mno-fis: PDP-11-Options. (line 51)
23906 * -mno-fp-11: PDP-11-Options. (line 56)
23907 * -mno-fpp: PDP-11-Options. (line 56)
23908 * -mno-fpu: PDP-11-Options. (line 56)
23909 * -mno-kev11: PDP-11-Options. (line 51)
23910 * -mno-limited-eis: PDP-11-Options. (line 64)
23911 * -mno-mfpt: PDP-11-Options. (line 70)
23912 * -mno-microcode: PDP-11-Options. (line 83)
23913 * -mno-mutiproc: PDP-11-Options. (line 73)
23914 * -mno-mxps: PDP-11-Options. (line 77)
23915 * -mno-pic: PDP-11-Options. (line 11)
23916 * -mno-pic command line option, TIC6X: TIC6X Options. (line 36)
23917 * -mno-regnames option, s390: s390 Options. (line 35)
23918 * -mno-skip-bug command line option, AVR: AVR Options. (line 112)
23919 * -mno-spl: PDP-11-Options. (line 80)
23920 * -mno-sym32: MIPS Options. (line 280)
23921 * -mno-verbose-error command line option, AArch64: AArch64 Options.
23923 * -mno-wrap command line option, AVR: AVR Options. (line 115)
23924 * -mnopic command line option, Blackfin: Blackfin Options. (line 22)
23925 * -momit-lock-prefix= option, i386: i386-Options. (line 135)
23926 * -momit-lock-prefix= option, x86-64: i386-Options. (line 135)
23927 * -mpic: PDP-11-Options. (line 11)
23928 * -mpic command line option, TIC6X: TIC6X Options. (line 36)
23929 * -mpid: RX-Opts. (line 50)
23930 * -mpid= command line option, TIC6X: TIC6X Options. (line 23)
23931 * -mregnames option, s390: s390 Options. (line 32)
23932 * -mrelax command line option, V850: V850 Options. (line 72)
23933 * -mrh850-abi command line option, V850: V850 Options. (line 82)
23934 * -mrmw command line option, AVR: AVR Options. (line 118)
23935 * -mrx-abi: RX-Opts. (line 69)
23936 * -mshort <1>: XGATE-Opts. (line 8)
23937 * -mshort: M68HC11-Opts. (line 40)
23938 * -mshort-double <1>: M68HC11-Opts. (line 49)
23939 * -mshort-double: XGATE-Opts. (line 17)
23940 * -msign-extend-enabled command line option, LM32: LM32 Options.
23942 * -msmall-data-limit: RX-Opts. (line 42)
23943 * -mspl: PDP-11-Options. (line 80)
23944 * -msse-check= option, i386: i386-Options. (line 74)
23945 * -msse-check= option, x86-64: i386-Options. (line 74)
23946 * -msse2avx option, i386: i386-Options. (line 70)
23947 * -msse2avx option, x86-64: i386-Options. (line 70)
23948 * -msym32: MIPS Options. (line 280)
23949 * -msyntax= option, i386: i386-Options. (line 115)
23950 * -msyntax= option, x86-64: i386-Options. (line 115)
23951 * -mt11: PDP-11-Options. (line 130)
23952 * -mthumb command line option, ARM: ARM Options. (line 103)
23953 * -mthumb-interwork command line option, ARM: ARM Options. (line 108)
23954 * -mtune= option, i386: i386-Options. (line 62)
23955 * -mtune= option, x86-64: i386-Options. (line 62)
23956 * -muse-conventional-section-names: RX-Opts. (line 33)
23957 * -muse-renesas-section-names: RX-Opts. (line 37)
23958 * -muser-enabled command line option, LM32: LM32 Options. (line 18)
23959 * -mv850 command line option, V850: V850 Options. (line 23)
23960 * -mv850any command line option, V850: V850 Options. (line 41)
23961 * -mv850e command line option, V850: V850 Options. (line 29)
23962 * -mv850e1 command line option, V850: V850 Options. (line 35)
23963 * -mv850e2 command line option, V850: V850 Options. (line 51)
23964 * -mv850e2v3 command line option, V850: V850 Options. (line 57)
23965 * -mv850e2v4 command line option, V850: V850 Options. (line 63)
23966 * -mv850e3v5 command line option, V850: V850 Options. (line 66)
23967 * -mverbose-error command line option, AArch64: AArch64 Options.
23969 * -mvxworks-pic option, MIPS: MIPS Options. (line 26)
23970 * -mwarn-areg-zero option, s390: s390 Options. (line 38)
23971 * -mwarn-deprecated command line option, ARM: ARM Options. (line 177)
23972 * -mzarch option, s390: s390 Options. (line 17)
23973 * -N command line option, CRIS: CRIS-Opts. (line 58)
23974 * -nIp option, M32RX: M32R-Opts. (line 101)
23975 * -no-bitinst, M32R2: M32R-Opts. (line 54)
23976 * -no-ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 93)
23977 * -no-mdebug command line option, Alpha: Alpha Options. (line 25)
23978 * -no-parallel option, M32RX: M32R-Opts. (line 51)
23979 * -no-relax option, i960: Options-i960. (line 66)
23980 * -no-warn-explicit-parallel-conflicts option, M32RX: M32R-Opts.
23982 * -no-warn-unmatched-high option, M32R: M32R-Opts. (line 111)
23983 * -nocpp ignored (MIPS): MIPS Options. (line 283)
23984 * -noreplace command line option, Alpha: Alpha Options. (line 40)
23986 * -O option, M32RX: M32R-Opts. (line 59)
23987 * -parallel option, M32RX: M32R-Opts. (line 46)
23989 * -r800 command line option, Z80: Z80 Options. (line 41)
23990 * -relax command line option, Alpha: Alpha Options. (line 32)
23991 * -replace command line option, Alpha: Alpha Options. (line 40)
23992 * -S, ignored on VAX: VAX-Opts. (line 11)
23993 * -t, ignored on VAX: VAX-Opts. (line 36)
23994 * -T, ignored on VAX: VAX-Opts. (line 11)
23996 * -V, redundant on VAX: VAX-Opts. (line 22)
23997 * -version: v. (line 6)
23999 * -warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. (line 65)
24000 * -warn-unmatched-high option, M32R: M32R-Opts. (line 105)
24001 * -Wnp option, M32RX: M32R-Opts. (line 83)
24002 * -Wnuh option, M32RX: M32R-Opts. (line 117)
24003 * -Wp option, M32RX: M32R-Opts. (line 75)
24004 * -wsigned_overflow command line option, V850: V850 Options. (line 9)
24005 * -Wuh option, M32RX: M32R-Opts. (line 114)
24006 * -wunsigned_overflow command line option, V850: V850 Options.
24008 * -x command line option, MMIX: MMIX-Opts. (line 44)
24009 * -z80 command line option, Z80: Z80 Options. (line 8)
24010 * -z8001 command line option, Z8000: Z8000 Options. (line 6)
24011 * -z8002 command line option, Z8000: Z8000 Options. (line 9)
24012 * . (symbol): Dot. (line 6)
24013 * .2byte directive, ARM: ARM Directives. (line 6)
24014 * .4byte directive, ARM: ARM Directives. (line 6)
24015 * .8byte directive, ARM: ARM Directives. (line 6)
24016 * .align directive, ARM: ARM Directives. (line 11)
24017 * .align directive, TILE-Gx: TILE-Gx Directives. (line 6)
24018 * .align directive, TILEPro: TILEPro Directives. (line 6)
24019 * .allow_suspicious_bundles directive, TILE-Gx: TILE-Gx Directives.
24021 * .allow_suspicious_bundles directive, TILEPro: TILEPro Directives.
24023 * .arch directive, ARM: ARM Directives. (line 18)
24024 * .arch directive, TIC6X: TIC6X Directives. (line 10)
24025 * .arch_extension directive, ARM: ARM Directives. (line 25)
24026 * .arm directive, ARM: ARM Directives. (line 34)
24027 * .big directive, M32RX: M32R-Directives. (line 88)
24028 * .bss directive, AArch64: AArch64 Directives. (line 6)
24029 * .bss directive, ARM: ARM Directives. (line 37)
24030 * .c6xabi_attribute directive, TIC6X: TIC6X Directives. (line 20)
24031 * .cantunwind directive, ARM: ARM Directives. (line 40)
24032 * .cantunwind directive, TIC6X: TIC6X Directives. (line 13)
24033 * .code directive, ARM: ARM Directives. (line 44)
24034 * .cpu directive, ARM: ARM Directives. (line 48)
24035 * .dn and .qn directives, ARM: ARM Directives. (line 55)
24036 * .eabi_attribute directive, ARM: ARM Directives. (line 78)
24037 * .ehtype directive, TIC6X: TIC6X Directives. (line 31)
24038 * .endp directive, TIC6X: TIC6X Directives. (line 34)
24039 * .even directive, ARM: ARM Directives. (line 106)
24040 * .extend directive, ARM: ARM Directives. (line 109)
24041 * .fnend directive, ARM: ARM Directives. (line 115)
24042 * .fnstart directive, ARM: ARM Directives. (line 124)
24043 * .force_thumb directive, ARM: ARM Directives. (line 127)
24044 * .fpu directive, ARM: ARM Directives. (line 131)
24045 * .global: MIPS insn. (line 12)
24046 * .gnu_attribute 4, N directive, MIPS: MIPS FP ABI History. (line 6)
24047 * .gnu_attribute Tag_GNU_MIPS_ABI_FP, N directive, MIPS: MIPS FP ABI History.
24049 * .handlerdata directive, ARM: ARM Directives. (line 135)
24050 * .handlerdata directive, TIC6X: TIC6X Directives. (line 39)
24051 * .insn: MIPS insn. (line 6)
24052 * .insn directive, s390: s390 Directives. (line 11)
24053 * .inst directive, ARM: ARM Directives. (line 144)
24054 * .ldouble directive, ARM: ARM Directives. (line 109)
24055 * .little directive, M32RX: M32R-Directives. (line 82)
24056 * .long directive, s390: s390 Directives. (line 16)
24057 * .ltorg directive, AArch64: AArch64 Directives. (line 9)
24058 * .ltorg directive, ARM: ARM Directives. (line 154)
24059 * .ltorg directive, s390: s390 Directives. (line 88)
24060 * .m32r directive, M32R: M32R-Directives. (line 66)
24061 * .m32r2 directive, M32R2: M32R-Directives. (line 77)
24062 * .m32rx directive, M32RX: M32R-Directives. (line 72)
24063 * .machine directive, s390: s390 Directives. (line 93)
24064 * .machinemode directive, s390: s390 Directives. (line 103)
24065 * .module: MIPS assembly options.
24067 * .module fp=NN directive, MIPS: MIPS FP ABI Selection.
24069 * .movsp directive, ARM: ARM Directives. (line 168)
24070 * .nan directive, MIPS: MIPS NaN Encodings. (line 6)
24071 * .no_pointers directive, XStormy16: XStormy16 Directives.
24073 * .nocmp directive, TIC6X: TIC6X Directives. (line 47)
24074 * .o: Object. (line 6)
24075 * .object_arch directive, ARM: ARM Directives. (line 173)
24076 * .packed directive, ARM: ARM Directives. (line 179)
24077 * .pad directive, ARM: ARM Directives. (line 184)
24078 * .param on HPPA: HPPA Directives. (line 19)
24079 * .personality directive, ARM: ARM Directives. (line 189)
24080 * .personality directive, TIC6X: TIC6X Directives. (line 55)
24081 * .personalityindex directive, ARM: ARM Directives. (line 192)
24082 * .personalityindex directive, TIC6X: TIC6X Directives. (line 51)
24083 * .pool directive, AArch64: AArch64 Directives. (line 23)
24084 * .pool directive, ARM: ARM Directives. (line 196)
24085 * .quad directive, s390: s390 Directives. (line 16)
24086 * .req directive, AArch64: AArch64 Directives. (line 26)
24087 * .req directive, ARM: ARM Directives. (line 199)
24088 * .require_canonical_reg_names directive, TILE-Gx: TILE-Gx Directives.
24090 * .require_canonical_reg_names directive, TILEPro: TILEPro Directives.
24092 * .save directive, ARM: ARM Directives. (line 204)
24093 * .scomm directive, TIC6X: TIC6X Directives. (line 58)
24094 * .secrel32 directive, ARM: ARM Directives. (line 242)
24095 * .set arch=CPU: MIPS ISA. (line 19)
24096 * .set at: MIPS Macros. (line 42)
24097 * .set at=REG: MIPS Macros. (line 36)
24098 * .set autoextend: MIPS autoextend. (line 6)
24099 * .set doublefloat: MIPS Floating-Point. (line 12)
24100 * .set dsp: MIPS ASE Instruction Generation Overrides.
24102 * .set dspr2: MIPS ASE Instruction Generation Overrides.
24104 * .set hardfloat: MIPS Floating-Point. (line 6)
24105 * .set insn32: MIPS assembly options.
24107 * .set macro: MIPS Macros. (line 31)
24108 * .set mcu: MIPS ASE Instruction Generation Overrides.
24110 * .set mdmx: MIPS ASE Instruction Generation Overrides.
24112 * .set mips3d: MIPS ASE Instruction Generation Overrides.
24114 * .set mipsN: MIPS ISA. (line 6)
24115 * .set msa: MIPS ASE Instruction Generation Overrides.
24117 * .set mt: MIPS ASE Instruction Generation Overrides.
24119 * .set noat: MIPS Macros. (line 42)
24120 * .set noautoextend: MIPS autoextend. (line 6)
24121 * .set nodsp: MIPS ASE Instruction Generation Overrides.
24123 * .set nodspr2: MIPS ASE Instruction Generation Overrides.
24125 * .set noinsn32: MIPS assembly options.
24127 * .set nomacro: MIPS Macros. (line 31)
24128 * .set nomcu: MIPS ASE Instruction Generation Overrides.
24130 * .set nomdmx: MIPS ASE Instruction Generation Overrides.
24132 * .set nomips3d: MIPS ASE Instruction Generation Overrides.
24134 * .set nomsa: MIPS ASE Instruction Generation Overrides.
24136 * .set nomt: MIPS ASE Instruction Generation Overrides.
24138 * .set nosmartmips: MIPS ASE Instruction Generation Overrides.
24140 * .set nosym32: MIPS Symbol Sizes. (line 6)
24141 * .set novirt: MIPS ASE Instruction Generation Overrides.
24143 * .set noxpa: MIPS ASE Instruction Generation Overrides.
24145 * .set pop: MIPS Option Stack. (line 6)
24146 * .set push: MIPS Option Stack. (line 6)
24147 * .set singlefloat: MIPS Floating-Point. (line 12)
24148 * .set smartmips: MIPS ASE Instruction Generation Overrides.
24150 * .set softfloat: MIPS Floating-Point. (line 6)
24151 * .set sym32: MIPS Symbol Sizes. (line 6)
24152 * .set virt: MIPS ASE Instruction Generation Overrides.
24154 * .set xpa: MIPS ASE Instruction Generation Overrides.
24156 * .setfp directive, ARM: ARM Directives. (line 228)
24157 * .short directive, s390: s390 Directives. (line 16)
24158 * .syntax directive, ARM: ARM Directives. (line 247)
24159 * .thumb directive, ARM: ARM Directives. (line 251)
24160 * .thumb_func directive, ARM: ARM Directives. (line 254)
24161 * .thumb_set directive, ARM: ARM Directives. (line 265)
24162 * .tlsdescseq directive, ARM: ARM Directives. (line 272)
24163 * .unreq directive, AArch64: AArch64 Directives. (line 31)
24164 * .unreq directive, ARM: ARM Directives. (line 277)
24165 * .unwind_raw directive, ARM: ARM Directives. (line 288)
24166 * .v850 directive, V850: V850 Directives. (line 14)
24167 * .v850e directive, V850: V850 Directives. (line 20)
24168 * .v850e1 directive, V850: V850 Directives. (line 26)
24169 * .v850e2 directive, V850: V850 Directives. (line 32)
24170 * .v850e2v3 directive, V850: V850 Directives. (line 38)
24171 * .v850e2v4 directive, V850: V850 Directives. (line 44)
24172 * .v850e3v5 directive, V850: V850 Directives. (line 50)
24173 * .vsave directive, ARM: ARM Directives. (line 295)
24174 * .z8001: Z8000 Directives. (line 11)
24175 * .z8002: Z8000 Directives. (line 15)
24176 * 16-bit code, i386: i386-16bit. (line 6)
24177 * 16bit_pointers directive, XStormy16: XStormy16 Directives.
24179 * 16byte directive, Nios II: Nios II Directives. (line 28)
24180 * 2byte directive, ARC: ARC Directives. (line 9)
24181 * 2byte directive, Nios II: Nios II Directives. (line 19)
24182 * 32bit_pointers directive, XStormy16: XStormy16 Directives.
24184 * 3byte directive, ARC: ARC Directives. (line 12)
24185 * 3DNow!, i386: i386-SIMD. (line 6)
24186 * 3DNow!, x86-64: i386-SIMD. (line 6)
24187 * 430 support: MSP430-Dependent. (line 6)
24188 * 4byte directive, ARC: ARC Directives. (line 15)
24189 * 4byte directive, Nios II: Nios II Directives. (line 22)
24190 * 8byte directive, Nios II: Nios II Directives. (line 25)
24191 * : (label): Statements. (line 31)
24192 * @hi pseudo-op, XStormy16: XStormy16 Opcodes. (line 21)
24193 * @lo pseudo-op, XStormy16: XStormy16 Opcodes. (line 10)
24194 * @word modifier, D10V: D10V-Word. (line 6)
24195 * \" (doublequote character): Strings. (line 43)
24196 * \\ (\ character): Strings. (line 40)
24197 * \b (backspace character): Strings. (line 15)
24198 * \DDD (octal character code): Strings. (line 30)
24199 * \f (formfeed character): Strings. (line 18)
24200 * \n (newline character): Strings. (line 21)
24201 * \r (carriage return character): Strings. (line 24)
24202 * \t (tab): Strings. (line 27)
24203 * \XD... (hex character code): Strings. (line 36)
24204 * _ opcode prefix: Xtensa Opcodes. (line 9)
24205 * a.out: Object. (line 6)
24206 * a.out symbol attributes: a.out Symbols. (line 6)
24207 * A_DIR environment variable, TIC54X: TIC54X-Env. (line 6)
24208 * AArch64 floating point (IEEE): AArch64 Floating Point.
24210 * AArch64 immediate character: AArch64-Chars. (line 13)
24211 * AArch64 line comment character: AArch64-Chars. (line 6)
24212 * AArch64 line separator: AArch64-Chars. (line 10)
24213 * AArch64 machine directives: AArch64 Directives. (line 6)
24214 * AArch64 opcodes: AArch64 Opcodes. (line 6)
24215 * AArch64 options (none): AArch64 Options. (line 6)
24216 * AArch64 register names: AArch64-Regs. (line 6)
24217 * AArch64 relocations: AArch64-Relocations. (line 6)
24218 * AArch64 support: AArch64-Dependent. (line 6)
24219 * ABI options, SH64: SH64 Options. (line 29)
24220 * abort directive: Abort. (line 6)
24221 * ABORT directive: ABORT (COFF). (line 6)
24222 * absolute section: Ld Sections. (line 29)
24223 * absolute-literals directive: Absolute Literals Directive.
24225 * ADDI instructions, relaxation: Xtensa Immediate Relaxation.
24227 * addition, permitted arguments: Infix Ops. (line 44)
24228 * addresses: Expressions. (line 6)
24229 * addresses, format of: Secs Background. (line 68)
24230 * addressing modes, D10V: D10V-Addressing. (line 6)
24231 * addressing modes, D30V: D30V-Addressing. (line 6)
24232 * addressing modes, H8/300: H8/300-Addressing. (line 6)
24233 * addressing modes, M680x0: M68K-Syntax. (line 21)
24234 * addressing modes, M68HC11: M68HC11-Syntax. (line 30)
24235 * addressing modes, SH: SH-Addressing. (line 6)
24236 * addressing modes, SH64: SH64-Addressing. (line 6)
24237 * addressing modes, XGATE: XGATE-Syntax. (line 29)
24238 * addressing modes, Z8000: Z8000-Addressing. (line 6)
24239 * ADR reg,<label> pseudo op, ARM: ARM Opcodes. (line 25)
24240 * ADRL reg,<label> pseudo op, ARM: ARM Opcodes. (line 35)
24241 * ADRP, ADD, LDR/STR group relocations, AArch64: AArch64-Relocations.
24243 * advancing location counter: Org. (line 6)
24244 * align directive: Align. (line 6)
24245 * align directive, Nios II: Nios II Directives. (line 6)
24246 * align directive, SPARC: Sparc-Directives. (line 9)
24247 * align directive, TIC54X: TIC54X-Directives. (line 6)
24248 * aligned instruction bundle: Bundle directives. (line 6)
24249 * alignment for NEON instructions: ARM-Neon-Alignment. (line 6)
24250 * alignment of branch targets: Xtensa Automatic Alignment.
24252 * alignment of LOOP instructions: Xtensa Automatic Alignment.
24254 * Alpha floating point (IEEE): Alpha Floating Point.
24256 * Alpha line comment character: Alpha-Chars. (line 6)
24257 * Alpha line separator: Alpha-Chars. (line 11)
24258 * Alpha notes: Alpha Notes. (line 6)
24259 * Alpha options: Alpha Options. (line 6)
24260 * Alpha registers: Alpha-Regs. (line 6)
24261 * Alpha relocations: Alpha-Relocs. (line 6)
24262 * Alpha support: Alpha-Dependent. (line 6)
24263 * Alpha Syntax: Alpha Options. (line 61)
24264 * Alpha-only directives: Alpha Directives. (line 10)
24265 * Altera Nios II support: NiosII-Dependent. (line 6)
24266 * altered difference tables: Word. (line 12)
24267 * alternate syntax for the 680x0: M68K-Moto-Syntax. (line 6)
24268 * ARC floating point (IEEE): ARC Floating Point. (line 6)
24269 * ARC line comment character: ARC-Chars. (line 6)
24270 * ARC line separator: ARC-Chars. (line 12)
24271 * ARC machine directives: ARC Directives. (line 6)
24272 * ARC opcodes: ARC Opcodes. (line 6)
24273 * ARC options (none): ARC Options. (line 6)
24274 * ARC register names: ARC-Regs. (line 6)
24275 * ARC support: ARC-Dependent. (line 6)
24276 * arc5 arc5, ARC: ARC Options. (line 10)
24277 * arc6 arc6, ARC: ARC Options. (line 13)
24278 * arc7 arc7, ARC: ARC Options. (line 21)
24279 * arc8 arc8, ARC: ARC Options. (line 24)
24280 * arch directive, i386: i386-Arch. (line 6)
24281 * arch directive, M680x0: M68K-Directives. (line 22)
24282 * arch directive, MSP 430: MSP430 Directives. (line 18)
24283 * arch directive, x86-64: i386-Arch. (line 6)
24284 * architecture options, i960: Options-i960. (line 6)
24285 * architecture options, IP2022: IP2K-Opts. (line 9)
24286 * architecture options, IP2K: IP2K-Opts. (line 14)
24287 * architecture options, M16C: M32C-Opts. (line 12)
24288 * architecture options, M32C: M32C-Opts. (line 9)
24289 * architecture options, M32R: M32R-Opts. (line 21)
24290 * architecture options, M32R2: M32R-Opts. (line 17)
24291 * architecture options, M32RX: M32R-Opts. (line 9)
24292 * architecture options, M680x0: M68K-Opts. (line 98)
24293 * Architecture variant option, CRIS: CRIS-Opts. (line 34)
24294 * architectures, Meta: Meta Options. (line 6)
24295 * architectures, PowerPC: PowerPC-Opts. (line 6)
24296 * architectures, SCORE: SCORE-Opts. (line 6)
24297 * architectures, SPARC: Sparc-Opts. (line 6)
24298 * arguments for addition: Infix Ops. (line 44)
24299 * arguments for subtraction: Infix Ops. (line 49)
24300 * arguments in expressions: Arguments. (line 6)
24301 * arithmetic functions: Operators. (line 6)
24302 * arithmetic operands: Arguments. (line 6)
24303 * ARM data relocations: ARM-Relocations. (line 6)
24304 * ARM floating point (IEEE): ARM Floating Point. (line 6)
24305 * ARM identifiers: ARM-Chars. (line 19)
24306 * ARM immediate character: ARM-Chars. (line 17)
24307 * ARM line comment character: ARM-Chars. (line 6)
24308 * ARM line separator: ARM-Chars. (line 14)
24309 * ARM machine directives: ARM Directives. (line 6)
24310 * ARM opcodes: ARM Opcodes. (line 6)
24311 * ARM options (none): ARM Options. (line 6)
24312 * ARM register names: ARM-Regs. (line 6)
24313 * ARM support: ARM-Dependent. (line 6)
24314 * ascii directive: Ascii. (line 6)
24315 * asciz directive: Asciz. (line 6)
24316 * asg directive, TIC54X: TIC54X-Directives. (line 20)
24317 * assembler bugs, reporting: Bug Reporting. (line 6)
24318 * assembler crash: Bug Criteria. (line 9)
24319 * assembler directive .3byte, RX: RX-Directives. (line 9)
24320 * assembler directive .arch, CRIS: CRIS-Pseudos. (line 45)
24321 * assembler directive .dword, CRIS: CRIS-Pseudos. (line 12)
24322 * assembler directive .far, M68HC11: M68HC11-Directives. (line 20)
24323 * assembler directive .fetchalign, RX: RX-Directives. (line 13)
24324 * assembler directive .interrupt, M68HC11: M68HC11-Directives.
24326 * assembler directive .mode, M68HC11: M68HC11-Directives. (line 16)
24327 * assembler directive .relax, M68HC11: M68HC11-Directives. (line 10)
24328 * assembler directive .syntax, CRIS: CRIS-Pseudos. (line 17)
24329 * assembler directive .xrefb, M68HC11: M68HC11-Directives. (line 31)
24330 * assembler directive BSPEC, MMIX: MMIX-Pseudos. (line 131)
24331 * assembler directive BYTE, MMIX: MMIX-Pseudos. (line 97)
24332 * assembler directive ESPEC, MMIX: MMIX-Pseudos. (line 131)
24333 * assembler directive GREG, MMIX: MMIX-Pseudos. (line 50)
24334 * assembler directive IS, MMIX: MMIX-Pseudos. (line 42)
24335 * assembler directive LOC, MMIX: MMIX-Pseudos. (line 7)
24336 * assembler directive LOCAL, MMIX: MMIX-Pseudos. (line 28)
24337 * assembler directive OCTA, MMIX: MMIX-Pseudos. (line 108)
24338 * assembler directive PREFIX, MMIX: MMIX-Pseudos. (line 120)
24339 * assembler directive TETRA, MMIX: MMIX-Pseudos. (line 108)
24340 * assembler directive WYDE, MMIX: MMIX-Pseudos. (line 108)
24341 * assembler directives, CRIS: CRIS-Pseudos. (line 6)
24342 * assembler directives, M68HC11: M68HC11-Directives. (line 6)
24343 * assembler directives, M68HC12: M68HC11-Directives. (line 6)
24344 * assembler directives, MMIX: MMIX-Pseudos. (line 6)
24345 * assembler directives, RL78: RL78-Directives. (line 6)
24346 * assembler directives, RX: RX-Directives. (line 6)
24347 * assembler directives, XGATE: XGATE-Directives. (line 6)
24348 * assembler internal logic error: As Sections. (line 13)
24349 * assembler version: v. (line 6)
24350 * assembler, and linker: Secs Background. (line 10)
24351 * assembly listings, enabling: a. (line 6)
24352 * assigning values to symbols <1>: Equ. (line 6)
24353 * assigning values to symbols: Setting Symbols. (line 6)
24354 * at register, MIPS: MIPS Macros. (line 36)
24355 * atmp directive, i860: Directives-i860. (line 16)
24356 * att_syntax pseudo op, i386: i386-Variations. (line 6)
24357 * att_syntax pseudo op, x86-64: i386-Variations. (line 6)
24358 * attributes, symbol: Symbol Attributes. (line 6)
24359 * auxiliary attributes, COFF symbols: COFF Symbols. (line 19)
24360 * auxiliary symbol information, COFF: Dim. (line 6)
24361 * AVR line comment character: AVR-Chars. (line 6)
24362 * AVR line separator: AVR-Chars. (line 14)
24363 * AVR modifiers: AVR-Modifiers. (line 6)
24364 * AVR opcode summary: AVR Opcodes. (line 6)
24365 * AVR options (none): AVR Options. (line 6)
24366 * AVR register names: AVR-Regs. (line 6)
24367 * AVR support: AVR-Dependent. (line 6)
24368 * backslash (\\): Strings. (line 40)
24369 * backspace (\b): Strings. (line 15)
24370 * balign directive: Balign. (line 6)
24371 * balignl directive: Balign. (line 27)
24372 * balignw directive: Balign. (line 27)
24373 * bes directive, TIC54X: TIC54X-Directives. (line 196)
24374 * big endian output, MIPS: Overview. (line 764)
24375 * big endian output, PJ: Overview. (line 667)
24376 * big-endian output, MIPS: MIPS Options. (line 13)
24377 * big-endian output, TIC6X: TIC6X Options. (line 46)
24378 * bignums: Bignums. (line 6)
24379 * binary constants, TIC54X: TIC54X-Constants. (line 8)
24380 * binary files, including: Incbin. (line 6)
24381 * binary integers: Integers. (line 6)
24382 * bit names, IA-64: IA-64-Bits. (line 6)
24383 * bitfields, not supported on VAX: VAX-no. (line 6)
24384 * Blackfin directives: Blackfin Directives. (line 6)
24385 * Blackfin options (none): Blackfin Options. (line 6)
24386 * Blackfin support: Blackfin-Dependent. (line 6)
24387 * Blackfin syntax: Blackfin Syntax. (line 6)
24388 * block: Z8000 Directives. (line 55)
24389 * BMI, i386: i386-BMI. (line 6)
24390 * BMI, x86-64: i386-BMI. (line 6)
24391 * branch improvement, M680x0: M68K-Branch. (line 6)
24392 * branch improvement, M68HC11: M68HC11-Branch. (line 6)
24393 * branch improvement, VAX: VAX-branch. (line 6)
24394 * branch instructions, relaxation: Xtensa Branch Relaxation.
24396 * branch recording, i960: Options-i960. (line 22)
24397 * branch statistics table, i960: Options-i960. (line 40)
24398 * branch target alignment: Xtensa Automatic Alignment.
24400 * break directive, TIC54X: TIC54X-Directives. (line 143)
24401 * BSD syntax: PDP-11-Syntax. (line 6)
24402 * bss directive, i960: Directives-i960. (line 6)
24403 * bss directive, TIC54X: TIC54X-Directives. (line 29)
24404 * bss section <1>: Ld Sections. (line 20)
24405 * bss section: bss. (line 6)
24406 * bug criteria: Bug Criteria. (line 6)
24407 * bug reports: Bug Reporting. (line 6)
24408 * bugs in assembler: Reporting Bugs. (line 6)
24409 * Built-in symbols, CRIS: CRIS-Symbols. (line 6)
24410 * builtin math functions, TIC54X: TIC54X-Builtins. (line 6)
24411 * builtin subsym functions, TIC54X: TIC54X-Macros. (line 16)
24412 * bundle: Bundle directives. (line 6)
24413 * bundle-locked: Bundle directives. (line 35)
24414 * bundle_align_mode directive: Bundle directives. (line 6)
24415 * bundle_lock directive: Bundle directives. (line 28)
24416 * bundle_unlock directive: Bundle directives. (line 28)
24417 * bus lock prefixes, i386: i386-Prefixes. (line 36)
24418 * bval: Z8000 Directives. (line 30)
24419 * byte directive: Byte. (line 6)
24420 * byte directive, TIC54X: TIC54X-Directives. (line 36)
24421 * C54XDSP_DIR environment variable, TIC54X: TIC54X-Env. (line 6)
24422 * c_mode directive, TIC54X: TIC54X-Directives. (line 51)
24423 * call directive, Nios II: Nios II Relocations. (line 38)
24424 * call instructions, i386: i386-Mnemonics. (line 56)
24425 * call instructions, relaxation: Xtensa Call Relaxation.
24427 * call instructions, x86-64: i386-Mnemonics. (line 56)
24428 * call_hiadj directive, Nios II: Nios II Relocations. (line 38)
24429 * call_lo directive, Nios II: Nios II Relocations. (line 38)
24430 * callj, i960 pseudo-opcode: callj-i960. (line 6)
24431 * carriage return (\r): Strings. (line 24)
24432 * case sensitivity, Z80: Z80-Case. (line 6)
24433 * cfi_endproc directive: CFI directives. (line 26)
24434 * cfi_sections directive: CFI directives. (line 6)
24435 * cfi_startproc directive: CFI directives. (line 16)
24436 * char directive, TIC54X: TIC54X-Directives. (line 36)
24437 * character constant, Z80: Z80-Chars. (line 20)
24438 * character constants: Characters. (line 6)
24439 * character escape codes: Strings. (line 15)
24440 * character escapes, Z80: Z80-Chars. (line 18)
24441 * character, single: Chars. (line 6)
24442 * characters used in symbols: Symbol Intro. (line 6)
24443 * clink directive, TIC54X: TIC54X-Directives. (line 45)
24444 * code16 directive, i386: i386-16bit. (line 6)
24445 * code16gcc directive, i386: i386-16bit. (line 6)
24446 * code32 directive, i386: i386-16bit. (line 6)
24447 * code64 directive, i386: i386-16bit. (line 6)
24448 * code64 directive, x86-64: i386-16bit. (line 6)
24449 * COFF auxiliary symbol information: Dim. (line 6)
24450 * COFF structure debugging: Tag. (line 6)
24451 * COFF symbol attributes: COFF Symbols. (line 6)
24452 * COFF symbol descriptor: Desc. (line 6)
24453 * COFF symbol storage class: Scl. (line 6)
24454 * COFF symbol type: Type. (line 11)
24455 * COFF symbols, debugging: Def. (line 6)
24456 * COFF value attribute: Val. (line 6)
24457 * COMDAT: Linkonce. (line 6)
24458 * comm directive: Comm. (line 6)
24459 * command line conventions: Command Line. (line 6)
24460 * command line options, V850: V850 Options. (line 9)
24461 * command-line options ignored, VAX: VAX-Opts. (line 6)
24462 * comment character, XStormy16: XStormy16-Chars. (line 11)
24463 * comments: Comments. (line 6)
24464 * comments, M680x0: M68K-Chars. (line 6)
24465 * comments, removed by preprocessor: Preprocessing. (line 11)
24466 * common directive, SPARC: Sparc-Directives. (line 12)
24467 * common sections: Linkonce. (line 6)
24468 * common variable storage: bss. (line 6)
24469 * compare and jump expansions, i960: Compare-and-branch-i960.
24471 * compare/branch instructions, i960: Compare-and-branch-i960.
24473 * comparison expressions: Infix Ops. (line 55)
24474 * conditional assembly: If. (line 6)
24475 * constant, single character: Chars. (line 6)
24476 * constants: Constants. (line 6)
24477 * constants, bignum: Bignums. (line 6)
24478 * constants, character: Characters. (line 6)
24479 * constants, converted by preprocessor: Preprocessing. (line 14)
24480 * constants, floating point: Flonums. (line 6)
24481 * constants, integer: Integers. (line 6)
24482 * constants, number: Numbers. (line 6)
24483 * constants, Sparc: Sparc-Constants. (line 6)
24484 * constants, string: Strings. (line 6)
24485 * constants, TIC54X: TIC54X-Constants. (line 6)
24486 * conversion instructions, i386: i386-Mnemonics. (line 37)
24487 * conversion instructions, x86-64: i386-Mnemonics. (line 37)
24488 * coprocessor wait, i386: i386-Prefixes. (line 40)
24489 * copy directive, TIC54X: TIC54X-Directives. (line 54)
24490 * cpu directive, M680x0: M68K-Directives. (line 30)
24491 * cpu directive, MSP 430: MSP430 Directives. (line 22)
24492 * CR16 line comment character: CR16-Chars. (line 6)
24493 * CR16 line separator: CR16-Chars. (line 13)
24494 * CR16 Operand Qualifiers: CR16 Operand Qualifiers.
24496 * CR16 support: CR16-Dependent. (line 6)
24497 * crash of assembler: Bug Criteria. (line 9)
24498 * CRIS --emulation=crisaout command line option: CRIS-Opts. (line 9)
24499 * CRIS --emulation=criself command line option: CRIS-Opts. (line 9)
24500 * CRIS --march=ARCHITECTURE command line option: CRIS-Opts. (line 34)
24501 * CRIS --mul-bug-abort command line option: CRIS-Opts. (line 62)
24502 * CRIS --no-mul-bug-abort command line option: CRIS-Opts. (line 62)
24503 * CRIS --no-underscore command line option: CRIS-Opts. (line 15)
24504 * CRIS --pic command line option: CRIS-Opts. (line 27)
24505 * CRIS --underscore command line option: CRIS-Opts. (line 15)
24506 * CRIS -N command line option: CRIS-Opts. (line 58)
24507 * CRIS architecture variant option: CRIS-Opts. (line 34)
24508 * CRIS assembler directive .arch: CRIS-Pseudos. (line 45)
24509 * CRIS assembler directive .dword: CRIS-Pseudos. (line 12)
24510 * CRIS assembler directive .syntax: CRIS-Pseudos. (line 17)
24511 * CRIS assembler directives: CRIS-Pseudos. (line 6)
24512 * CRIS built-in symbols: CRIS-Symbols. (line 6)
24513 * CRIS instruction expansion: CRIS-Expand. (line 6)
24514 * CRIS line comment characters: CRIS-Chars. (line 6)
24515 * CRIS options: CRIS-Opts. (line 6)
24516 * CRIS position-independent code: CRIS-Opts. (line 27)
24517 * CRIS pseudo-op .arch: CRIS-Pseudos. (line 45)
24518 * CRIS pseudo-op .dword: CRIS-Pseudos. (line 12)
24519 * CRIS pseudo-op .syntax: CRIS-Pseudos. (line 17)
24520 * CRIS pseudo-ops: CRIS-Pseudos. (line 6)
24521 * CRIS register names: CRIS-Regs. (line 6)
24522 * CRIS support: CRIS-Dependent. (line 6)
24523 * CRIS symbols in position-independent code: CRIS-Pic. (line 6)
24524 * ctbp register, V850: V850-Regs. (line 131)
24525 * ctoff pseudo-op, V850: V850 Opcodes. (line 111)
24526 * ctpc register, V850: V850-Regs. (line 119)
24527 * ctpsw register, V850: V850-Regs. (line 122)
24528 * current address: Dot. (line 6)
24529 * current address, advancing: Org. (line 6)
24530 * D10V @word modifier: D10V-Word. (line 6)
24531 * D10V addressing modes: D10V-Addressing. (line 6)
24532 * D10V floating point: D10V-Float. (line 6)
24533 * D10V line comment character: D10V-Chars. (line 6)
24534 * D10V opcode summary: D10V-Opcodes. (line 6)
24535 * D10V optimization: Overview. (line 527)
24536 * D10V options: D10V-Opts. (line 6)
24537 * D10V registers: D10V-Regs. (line 6)
24538 * D10V size modifiers: D10V-Size. (line 6)
24539 * D10V sub-instruction ordering: D10V-Chars. (line 14)
24540 * D10V sub-instructions: D10V-Subs. (line 6)
24541 * D10V support: D10V-Dependent. (line 6)
24542 * D10V syntax: D10V-Syntax. (line 6)
24543 * D30V addressing modes: D30V-Addressing. (line 6)
24544 * D30V floating point: D30V-Float. (line 6)
24545 * D30V Guarded Execution: D30V-Guarded. (line 6)
24546 * D30V line comment character: D30V-Chars. (line 6)
24547 * D30V nops: Overview. (line 535)
24548 * D30V nops after 32-bit multiply: Overview. (line 538)
24549 * D30V opcode summary: D30V-Opcodes. (line 6)
24550 * D30V optimization: Overview. (line 532)
24551 * D30V options: D30V-Opts. (line 6)
24552 * D30V registers: D30V-Regs. (line 6)
24553 * D30V size modifiers: D30V-Size. (line 6)
24554 * D30V sub-instruction ordering: D30V-Chars. (line 14)
24555 * D30V sub-instructions: D30V-Subs. (line 6)
24556 * D30V support: D30V-Dependent. (line 6)
24557 * D30V syntax: D30V-Syntax. (line 6)
24558 * data alignment on SPARC: Sparc-Aligned-Data. (line 6)
24559 * data and text sections, joining: R. (line 6)
24560 * data directive: Data. (line 6)
24561 * data directive, TIC54X: TIC54X-Directives. (line 61)
24562 * data relocations, ARM: ARM-Relocations. (line 6)
24563 * data section: Ld Sections. (line 9)
24564 * data1 directive, M680x0: M68K-Directives. (line 9)
24565 * data2 directive, M680x0: M68K-Directives. (line 12)
24566 * datalabel, SH64: SH64-Addressing. (line 16)
24567 * dbpc register, V850: V850-Regs. (line 125)
24568 * dbpsw register, V850: V850-Regs. (line 128)
24569 * debuggers, and symbol order: Symbols. (line 10)
24570 * debugging COFF symbols: Def. (line 6)
24571 * DEC syntax: PDP-11-Syntax. (line 6)
24572 * decimal integers: Integers. (line 12)
24573 * def directive: Def. (line 6)
24574 * def directive, TIC54X: TIC54X-Directives. (line 103)
24575 * density instructions: Density Instructions.
24577 * dependency tracking: MD. (line 6)
24578 * deprecated directives: Deprecated. (line 6)
24579 * desc directive: Desc. (line 6)
24580 * descriptor, of a.out symbol: Symbol Desc. (line 6)
24581 * dfloat directive, VAX: VAX-directives. (line 10)
24582 * difference tables altered: Word. (line 12)
24583 * difference tables, warning: K. (line 6)
24584 * differences, mmixal: MMIX-mmixal. (line 6)
24585 * dim directive: Dim. (line 6)
24586 * directives and instructions: Statements. (line 20)
24587 * directives for PowerPC: PowerPC-Pseudo. (line 6)
24588 * directives for SCORE: SCORE-Pseudo. (line 6)
24589 * directives, Blackfin: Blackfin Directives. (line 6)
24590 * directives, M32R: M32R-Directives. (line 6)
24591 * directives, M680x0: M68K-Directives. (line 6)
24592 * directives, machine independent: Pseudo Ops. (line 6)
24593 * directives, Xtensa: Xtensa Directives. (line 6)
24594 * directives, Z8000: Z8000 Directives. (line 6)
24595 * Disable floating-point instructions: MIPS Floating-Point. (line 6)
24596 * Disable single-precision floating-point operations: MIPS Floating-Point.
24598 * displacement sizing character, VAX: VAX-operands. (line 12)
24599 * dollar local symbols: Symbol Names. (line 110)
24600 * dot (symbol): Dot. (line 6)
24601 * double directive: Double. (line 6)
24602 * double directive, i386: i386-Float. (line 14)
24603 * double directive, M680x0: M68K-Float. (line 14)
24604 * double directive, M68HC11: M68HC11-Float. (line 14)
24605 * double directive, RX: RX-Float. (line 11)
24606 * double directive, TIC54X: TIC54X-Directives. (line 64)
24607 * double directive, VAX: VAX-float. (line 15)
24608 * double directive, x86-64: i386-Float. (line 14)
24609 * double directive, XGATE: XGATE-Float. (line 13)
24610 * doublequote (\"): Strings. (line 43)
24611 * drlist directive, TIC54X: TIC54X-Directives. (line 73)
24612 * drnolist directive, TIC54X: TIC54X-Directives. (line 73)
24613 * dual directive, i860: Directives-i860. (line 6)
24614 * dword directive, Nios II: Nios II Directives. (line 16)
24615 * EB command line option, Nios II: Nios II Options. (line 23)
24616 * ecr register, V850: V850-Regs. (line 113)
24617 * eight-byte integer: Quad. (line 9)
24618 * eipc register, V850: V850-Regs. (line 101)
24619 * eipsw register, V850: V850-Regs. (line 104)
24620 * eject directive: Eject. (line 6)
24621 * EL command line option, Nios II: Nios II Options. (line 26)
24622 * ELF symbol type: Type. (line 22)
24623 * else directive: Else. (line 6)
24624 * elseif directive: Elseif. (line 6)
24625 * empty expressions: Empty Exprs. (line 6)
24626 * emsg directive, TIC54X: TIC54X-Directives. (line 77)
24627 * emulation: Overview. (line 946)
24628 * encoding options, i386: i386-Mnemonics. (line 32)
24629 * encoding options, x86-64: i386-Mnemonics. (line 32)
24630 * end directive: End. (line 6)
24631 * enddual directive, i860: Directives-i860. (line 11)
24632 * endef directive: Endef. (line 6)
24633 * endfunc directive: Endfunc. (line 6)
24634 * endianness, MIPS: Overview. (line 764)
24635 * endianness, PJ: Overview. (line 667)
24636 * endif directive: Endif. (line 6)
24637 * endloop directive, TIC54X: TIC54X-Directives. (line 143)
24638 * endm directive: Macro. (line 138)
24639 * endm directive, TIC54X: TIC54X-Directives. (line 153)
24640 * endstruct directive, TIC54X: TIC54X-Directives. (line 216)
24641 * endunion directive, TIC54X: TIC54X-Directives. (line 250)
24642 * environment settings, TIC54X: TIC54X-Env. (line 6)
24643 * EOF, newline must precede: Statements. (line 14)
24644 * ep register, V850: V850-Regs. (line 95)
24645 * Epiphany line comment character: Epiphany-Chars. (line 6)
24646 * Epiphany line separator: Epiphany-Chars. (line 14)
24647 * Epiphany options: Epiphany Options. (line 6)
24648 * Epiphany support: Epiphany-Dependent. (line 6)
24649 * equ directive: Equ. (line 6)
24650 * equ directive, TIC54X: TIC54X-Directives. (line 191)
24651 * equiv directive: Equiv. (line 6)
24652 * eqv directive: Eqv. (line 6)
24653 * err directive: Err. (line 6)
24654 * error directive: Error. (line 6)
24655 * error messages: Errors. (line 6)
24656 * error on valid input: Bug Criteria. (line 12)
24657 * errors, caused by warnings: W. (line 16)
24658 * errors, continuing after: Z. (line 6)
24659 * ESA/390 floating point (IEEE): ESA/390 Floating Point.
24661 * ESA/390 support: ESA/390-Dependent. (line 6)
24662 * ESA/390 Syntax: ESA/390 Options. (line 8)
24663 * ESA/390-only directives: ESA/390 Directives. (line 12)
24664 * escape codes, character: Strings. (line 15)
24665 * eval directive, TIC54X: TIC54X-Directives. (line 24)
24666 * even: Z8000 Directives. (line 58)
24667 * even directive, M680x0: M68K-Directives. (line 15)
24668 * even directive, TIC54X: TIC54X-Directives. (line 6)
24669 * exitm directive: Macro. (line 141)
24670 * expr (internal section): As Sections. (line 17)
24671 * expression arguments: Arguments. (line 6)
24672 * expressions: Expressions. (line 6)
24673 * expressions, comparison: Infix Ops. (line 55)
24674 * expressions, empty: Empty Exprs. (line 6)
24675 * expressions, integer: Integer Exprs. (line 6)
24676 * extAuxRegister directive, ARC: ARC Directives. (line 18)
24677 * extCondCode directive, ARC: ARC Directives. (line 41)
24678 * extCoreRegister directive, ARC: ARC Directives. (line 53)
24679 * extend directive M680x0: M68K-Float. (line 17)
24680 * extend directive M68HC11: M68HC11-Float. (line 17)
24681 * extend directive XGATE: XGATE-Float. (line 16)
24682 * extended directive, i960: Directives-i960. (line 13)
24683 * extern directive: Extern. (line 6)
24684 * extInstruction directive, ARC: ARC Directives. (line 78)
24685 * fail directive: Fail. (line 6)
24686 * far_mode directive, TIC54X: TIC54X-Directives. (line 82)
24687 * faster processing (-f): f. (line 6)
24688 * fatal signal: Bug Criteria. (line 9)
24689 * fclist directive, TIC54X: TIC54X-Directives. (line 87)
24690 * fcnolist directive, TIC54X: TIC54X-Directives. (line 87)
24691 * fepc register, V850: V850-Regs. (line 107)
24692 * fepsw register, V850: V850-Regs. (line 110)
24693 * ffloat directive, VAX: VAX-directives. (line 14)
24694 * field directive, TIC54X: TIC54X-Directives. (line 91)
24695 * file directive: File. (line 6)
24696 * file directive, MSP 430: MSP430 Directives. (line 6)
24697 * file name, logical: File. (line 13)
24698 * files, including: Include. (line 6)
24699 * files, input: Input Files. (line 6)
24700 * fill directive: Fill. (line 6)
24701 * filling memory <1>: Space. (line 6)
24702 * filling memory: Skip. (line 6)
24703 * FLIX syntax: Xtensa Syntax. (line 6)
24704 * float directive: Float. (line 6)
24705 * float directive, i386: i386-Float. (line 14)
24706 * float directive, M680x0: M68K-Float. (line 11)
24707 * float directive, M68HC11: M68HC11-Float. (line 11)
24708 * float directive, RX: RX-Float. (line 8)
24709 * float directive, TIC54X: TIC54X-Directives. (line 64)
24710 * float directive, VAX: VAX-float. (line 15)
24711 * float directive, x86-64: i386-Float. (line 14)
24712 * float directive, XGATE: XGATE-Float. (line 10)
24713 * floating point numbers: Flonums. (line 6)
24714 * floating point numbers (double): Double. (line 6)
24715 * floating point numbers (single) <1>: Single. (line 6)
24716 * floating point numbers (single): Float. (line 6)
24717 * floating point, AArch64 (IEEE): AArch64 Floating Point.
24719 * floating point, Alpha (IEEE): Alpha Floating Point.
24721 * floating point, ARC (IEEE): ARC Floating Point. (line 6)
24722 * floating point, ARM (IEEE): ARM Floating Point. (line 6)
24723 * floating point, D10V: D10V-Float. (line 6)
24724 * floating point, D30V: D30V-Float. (line 6)
24725 * floating point, ESA/390 (IEEE): ESA/390 Floating Point.
24727 * floating point, H8/300 (IEEE): H8/300 Floating Point.
24729 * floating point, HPPA (IEEE): HPPA Floating Point. (line 6)
24730 * floating point, i386: i386-Float. (line 6)
24731 * floating point, i960 (IEEE): Floating Point-i960. (line 6)
24732 * floating point, M680x0: M68K-Float. (line 6)
24733 * floating point, M68HC11: M68HC11-Float. (line 6)
24734 * floating point, MSP 430 (IEEE): MSP430 Floating Point.
24736 * floating point, RX: RX-Float. (line 6)
24737 * floating point, s390: s390 Floating Point. (line 6)
24738 * floating point, SH (IEEE): SH Floating Point. (line 6)
24739 * floating point, SPARC (IEEE): Sparc-Float. (line 6)
24740 * floating point, V850 (IEEE): V850 Floating Point. (line 6)
24741 * floating point, VAX: VAX-float. (line 6)
24742 * floating point, x86-64: i386-Float. (line 6)
24743 * floating point, XGATE: XGATE-Float. (line 6)
24744 * floating point, Z80: Z80 Floating Point. (line 6)
24745 * flonums: Flonums. (line 6)
24746 * format of error messages: Errors. (line 24)
24747 * format of warning messages: Errors. (line 12)
24748 * formfeed (\f): Strings. (line 18)
24749 * func directive: Func. (line 6)
24750 * functions, in expressions: Operators. (line 6)
24751 * gbr960, i960 postprocessor: Options-i960. (line 40)
24752 * gfloat directive, VAX: VAX-directives. (line 18)
24753 * global: Z8000 Directives. (line 21)
24754 * global directive: Global. (line 6)
24755 * global directive, TIC54X: TIC54X-Directives. (line 103)
24756 * got directive, Nios II: Nios II Relocations. (line 38)
24757 * got_hiadj directive, Nios II: Nios II Relocations. (line 38)
24758 * got_lo directive, Nios II: Nios II Relocations. (line 38)
24759 * gotoff directive, Nios II: Nios II Relocations. (line 38)
24760 * gotoff_hiadj directive, Nios II: Nios II Relocations. (line 38)
24761 * gotoff_lo directive, Nios II: Nios II Relocations. (line 38)
24762 * gp register, MIPS: MIPS Small Data. (line 6)
24763 * gp register, V850: V850-Regs. (line 17)
24764 * gprel directive, Nios II: Nios II Relocations. (line 26)
24765 * grouping data: Sub-Sections. (line 6)
24766 * H8/300 addressing modes: H8/300-Addressing. (line 6)
24767 * H8/300 floating point (IEEE): H8/300 Floating Point.
24769 * H8/300 line comment character: H8/300-Chars. (line 6)
24770 * H8/300 line separator: H8/300-Chars. (line 8)
24771 * H8/300 machine directives (none): H8/300 Directives. (line 6)
24772 * H8/300 opcode summary: H8/300 Opcodes. (line 6)
24773 * H8/300 options: H8/300 Options. (line 6)
24774 * H8/300 registers: H8/300-Regs. (line 6)
24775 * H8/300 size suffixes: H8/300 Opcodes. (line 163)
24776 * H8/300 support: H8/300-Dependent. (line 6)
24777 * H8/300H, assembling for: H8/300 Directives. (line 8)
24778 * half directive, ARC: ARC Directives. (line 153)
24779 * half directive, Nios II: Nios II Directives. (line 10)
24780 * half directive, SPARC: Sparc-Directives. (line 17)
24781 * half directive, TIC54X: TIC54X-Directives. (line 111)
24782 * hex character code (\XD...): Strings. (line 36)
24783 * hexadecimal integers: Integers. (line 15)
24784 * hexadecimal prefix, Z80: Z80-Chars. (line 15)
24785 * hfloat directive, VAX: VAX-directives. (line 22)
24786 * hi directive, Nios II: Nios II Relocations. (line 20)
24787 * hi pseudo-op, V850: V850 Opcodes. (line 33)
24788 * hi0 pseudo-op, V850: V850 Opcodes. (line 10)
24789 * hiadj directive, Nios II: Nios II Relocations. (line 6)
24790 * hidden directive: Hidden. (line 6)
24791 * high directive, M32R: M32R-Directives. (line 18)
24792 * hilo pseudo-op, V850: V850 Opcodes. (line 55)
24793 * HPPA directives not supported: HPPA Directives. (line 11)
24794 * HPPA floating point (IEEE): HPPA Floating Point. (line 6)
24795 * HPPA Syntax: HPPA Options. (line 8)
24796 * HPPA-only directives: HPPA Directives. (line 24)
24797 * hword directive: hword. (line 6)
24798 * i370 support: ESA/390-Dependent. (line 6)
24799 * i386 16-bit code: i386-16bit. (line 6)
24800 * i386 arch directive: i386-Arch. (line 6)
24801 * i386 att_syntax pseudo op: i386-Variations. (line 6)
24802 * i386 conversion instructions: i386-Mnemonics. (line 37)
24803 * i386 floating point: i386-Float. (line 6)
24804 * i386 immediate operands: i386-Variations. (line 15)
24805 * i386 instruction naming: i386-Mnemonics. (line 6)
24806 * i386 instruction prefixes: i386-Prefixes. (line 6)
24807 * i386 intel_syntax pseudo op: i386-Variations. (line 6)
24808 * i386 jump optimization: i386-Jumps. (line 6)
24809 * i386 jump, call, return: i386-Variations. (line 41)
24810 * i386 jump/call operands: i386-Variations. (line 15)
24811 * i386 line comment character: i386-Chars. (line 6)
24812 * i386 line separator: i386-Chars. (line 18)
24813 * i386 memory references: i386-Memory. (line 6)
24814 * i386 mnemonic compatibility: i386-Mnemonics. (line 62)
24815 * i386 mul, imul instructions: i386-Notes. (line 6)
24816 * i386 options: i386-Options. (line 6)
24817 * i386 register operands: i386-Variations. (line 15)
24818 * i386 registers: i386-Regs. (line 6)
24819 * i386 sections: i386-Variations. (line 47)
24820 * i386 size suffixes: i386-Variations. (line 29)
24821 * i386 source, destination operands: i386-Variations. (line 22)
24822 * i386 support: i386-Dependent. (line 6)
24823 * i386 syntax compatibility: i386-Variations. (line 6)
24824 * i80386 support: i386-Dependent. (line 6)
24825 * i860 line comment character: i860-Chars. (line 6)
24826 * i860 line separator: i860-Chars. (line 14)
24827 * i860 machine directives: Directives-i860. (line 6)
24828 * i860 opcodes: Opcodes for i860. (line 6)
24829 * i860 support: i860-Dependent. (line 6)
24830 * i960 architecture options: Options-i960. (line 6)
24831 * i960 branch recording: Options-i960. (line 22)
24832 * i960 callj pseudo-opcode: callj-i960. (line 6)
24833 * i960 compare and jump expansions: Compare-and-branch-i960.
24835 * i960 compare/branch instructions: Compare-and-branch-i960.
24837 * i960 floating point (IEEE): Floating Point-i960. (line 6)
24838 * i960 line comment character: i960-Chars. (line 6)
24839 * i960 line separator: i960-Chars. (line 14)
24840 * i960 machine directives: Directives-i960. (line 6)
24841 * i960 opcodes: Opcodes for i960. (line 6)
24842 * i960 options: Options-i960. (line 6)
24843 * i960 support: i960-Dependent. (line 6)
24844 * IA-64 line comment character: IA-64-Chars. (line 6)
24845 * IA-64 line separator: IA-64-Chars. (line 8)
24846 * IA-64 options: IA-64 Options. (line 6)
24847 * IA-64 Processor-status-Register bit names: IA-64-Bits. (line 6)
24848 * IA-64 registers: IA-64-Regs. (line 6)
24849 * IA-64 relocations: IA-64-Relocs. (line 6)
24850 * IA-64 support: IA-64-Dependent. (line 6)
24851 * IA-64 Syntax: IA-64 Options. (line 87)
24852 * ident directive: Ident. (line 6)
24853 * identifiers, ARM: ARM-Chars. (line 19)
24854 * identifiers, MSP 430: MSP430-Chars. (line 17)
24855 * if directive: If. (line 6)
24856 * ifb directive: If. (line 21)
24857 * ifc directive: If. (line 25)
24858 * ifdef directive: If. (line 16)
24859 * ifeq directive: If. (line 33)
24860 * ifeqs directive: If. (line 36)
24861 * ifge directive: If. (line 40)
24862 * ifgt directive: If. (line 44)
24863 * ifle directive: If. (line 48)
24864 * iflt directive: If. (line 52)
24865 * ifnb directive: If. (line 56)
24866 * ifnc directive: If. (line 61)
24867 * ifndef directive: If. (line 65)
24868 * ifne directive: If. (line 72)
24869 * ifnes directive: If. (line 76)
24870 * ifnotdef directive: If. (line 65)
24871 * immediate character, AArch64: AArch64-Chars. (line 13)
24872 * immediate character, ARM: ARM-Chars. (line 17)
24873 * immediate character, M680x0: M68K-Chars. (line 13)
24874 * immediate character, VAX: VAX-operands. (line 6)
24875 * immediate fields, relaxation: Xtensa Immediate Relaxation.
24877 * immediate operands, i386: i386-Variations. (line 15)
24878 * immediate operands, x86-64: i386-Variations. (line 15)
24879 * imul instruction, i386: i386-Notes. (line 6)
24880 * imul instruction, x86-64: i386-Notes. (line 6)
24881 * incbin directive: Incbin. (line 6)
24882 * include directive: Include. (line 6)
24883 * include directive search path: I. (line 6)
24884 * indirect character, VAX: VAX-operands. (line 9)
24885 * infix operators: Infix Ops. (line 6)
24886 * inhibiting interrupts, i386: i386-Prefixes. (line 36)
24887 * input: Input Files. (line 6)
24888 * input file linenumbers: Input Files. (line 35)
24889 * instruction aliases, s390: s390 Aliases. (line 6)
24890 * instruction bundle: Bundle directives. (line 6)
24891 * instruction expansion, CRIS: CRIS-Expand. (line 6)
24892 * instruction expansion, MMIX: MMIX-Expand. (line 6)
24893 * instruction formats, s390: s390 Formats. (line 6)
24894 * instruction marker, s390: s390 Instruction Marker.
24896 * instruction mnemonics, s390: s390 Mnemonics. (line 6)
24897 * instruction naming, i386: i386-Mnemonics. (line 6)
24898 * instruction naming, x86-64: i386-Mnemonics. (line 6)
24899 * instruction operand modifier, s390: s390 Operand Modifier.
24901 * instruction operands, s390: s390 Operands. (line 6)
24902 * instruction prefixes, i386: i386-Prefixes. (line 6)
24903 * instruction set, M680x0: M68K-opcodes. (line 6)
24904 * instruction set, M68HC11: M68HC11-opcodes. (line 6)
24905 * instruction set, XGATE: XGATE-opcodes. (line 6)
24906 * instruction summary, AVR: AVR Opcodes. (line 6)
24907 * instruction summary, D10V: D10V-Opcodes. (line 6)
24908 * instruction summary, D30V: D30V-Opcodes. (line 6)
24909 * instruction summary, H8/300: H8/300 Opcodes. (line 6)
24910 * instruction summary, LM32: LM32 Opcodes. (line 6)
24911 * instruction summary, SH: SH Opcodes. (line 6)
24912 * instruction summary, SH64: SH64 Opcodes. (line 6)
24913 * instruction summary, Z8000: Z8000 Opcodes. (line 6)
24914 * instruction syntax, s390: s390 Syntax. (line 6)
24915 * instructions and directives: Statements. (line 20)
24916 * int directive: Int. (line 6)
24917 * int directive, H8/300: H8/300 Directives. (line 6)
24918 * int directive, i386: i386-Float. (line 21)
24919 * int directive, TIC54X: TIC54X-Directives. (line 111)
24920 * int directive, x86-64: i386-Float. (line 21)
24921 * integer expressions: Integer Exprs. (line 6)
24922 * integer, 16-byte: Octa. (line 6)
24923 * integer, 8-byte: Quad. (line 9)
24924 * integers: Integers. (line 6)
24925 * integers, 16-bit: hword. (line 6)
24926 * integers, 32-bit: Int. (line 6)
24927 * integers, binary: Integers. (line 6)
24928 * integers, decimal: Integers. (line 12)
24929 * integers, hexadecimal: Integers. (line 15)
24930 * integers, octal: Integers. (line 9)
24931 * integers, one byte: Byte. (line 6)
24932 * intel_syntax pseudo op, i386: i386-Variations. (line 6)
24933 * intel_syntax pseudo op, x86-64: i386-Variations. (line 6)
24934 * internal assembler sections: As Sections. (line 6)
24935 * internal directive: Internal. (line 6)
24936 * invalid input: Bug Criteria. (line 14)
24937 * invocation summary: Overview. (line 6)
24938 * IP2K architecture options: IP2K-Opts. (line 9)
24939 * IP2K line comment character: IP2K-Chars. (line 6)
24940 * IP2K line separator: IP2K-Chars. (line 14)
24941 * IP2K options: IP2K-Opts. (line 6)
24942 * IP2K support: IP2K-Dependent. (line 6)
24943 * irp directive: Irp. (line 6)
24944 * irpc directive: Irpc. (line 6)
24945 * ISA options, SH64: SH64 Options. (line 6)
24946 * joining text and data sections: R. (line 6)
24947 * jump instructions, i386: i386-Mnemonics. (line 56)
24948 * jump instructions, relaxation: Xtensa Jump Relaxation.
24950 * jump instructions, x86-64: i386-Mnemonics. (line 56)
24951 * jump optimization, i386: i386-Jumps. (line 6)
24952 * jump optimization, x86-64: i386-Jumps. (line 6)
24953 * jump/call operands, i386: i386-Variations. (line 15)
24954 * jump/call operands, x86-64: i386-Variations. (line 15)
24955 * L16SI instructions, relaxation: Xtensa Immediate Relaxation.
24957 * L16UI instructions, relaxation: Xtensa Immediate Relaxation.
24959 * L32I instructions, relaxation: Xtensa Immediate Relaxation.
24961 * L8UI instructions, relaxation: Xtensa Immediate Relaxation.
24963 * label (:): Statements. (line 31)
24964 * label directive, TIC54X: TIC54X-Directives. (line 123)
24965 * labels: Labels. (line 6)
24966 * lcomm directive: Lcomm. (line 6)
24967 * lcomm directive, COFF: i386-Directives. (line 6)
24968 * ld: Object. (line 15)
24969 * ldouble directive M680x0: M68K-Float. (line 17)
24970 * ldouble directive M68HC11: M68HC11-Float. (line 17)
24971 * ldouble directive XGATE: XGATE-Float. (line 16)
24972 * ldouble directive, TIC54X: TIC54X-Directives. (line 64)
24973 * LDR reg,=<expr> pseudo op, AArch64: AArch64 Opcodes. (line 9)
24974 * LDR reg,=<label> pseudo op, ARM: ARM Opcodes. (line 15)
24975 * leafproc directive, i960: Directives-i960. (line 18)
24976 * length directive, TIC54X: TIC54X-Directives. (line 127)
24977 * length of symbols: Symbol Intro. (line 14)
24978 * lflags directive (ignored): Lflags. (line 6)
24979 * line comment character: Comments. (line 19)
24980 * line comment character, AArch64: AArch64-Chars. (line 6)
24981 * line comment character, Alpha: Alpha-Chars. (line 6)
24982 * line comment character, ARC: ARC-Chars. (line 6)
24983 * line comment character, ARM: ARM-Chars. (line 6)
24984 * line comment character, AVR: AVR-Chars. (line 6)
24985 * line comment character, CR16: CR16-Chars. (line 6)
24986 * line comment character, D10V: D10V-Chars. (line 6)
24987 * line comment character, D30V: D30V-Chars. (line 6)
24988 * line comment character, Epiphany: Epiphany-Chars. (line 6)
24989 * line comment character, H8/300: H8/300-Chars. (line 6)
24990 * line comment character, i386: i386-Chars. (line 6)
24991 * line comment character, i860: i860-Chars. (line 6)
24992 * line comment character, i960: i960-Chars. (line 6)
24993 * line comment character, IA-64: IA-64-Chars. (line 6)
24994 * line comment character, IP2K: IP2K-Chars. (line 6)
24995 * line comment character, LM32: LM32-Chars. (line 6)
24996 * line comment character, M32C: M32C-Chars. (line 6)
24997 * line comment character, M680x0: M68K-Chars. (line 6)
24998 * line comment character, M68HC11: M68HC11-Syntax. (line 17)
24999 * line comment character, Meta: Meta-Chars. (line 6)
25000 * line comment character, MicroBlaze: MicroBlaze-Chars. (line 6)
25001 * line comment character, MIPS: MIPS-Chars. (line 6)
25002 * line comment character, MSP 430: MSP430-Chars. (line 6)
25003 * line comment character, Nios II: Nios II Chars. (line 6)
25004 * line comment character, NS32K: NS32K-Chars. (line 6)
25005 * line comment character, PJ: PJ-Chars. (line 6)
25006 * line comment character, PowerPC: PowerPC-Chars. (line 6)
25007 * line comment character, RL78: RL78-Chars. (line 6)
25008 * line comment character, RX: RX-Chars. (line 6)
25009 * line comment character, s390: s390 Characters. (line 6)
25010 * line comment character, SCORE: SCORE-Chars. (line 6)
25011 * line comment character, SH: SH-Chars. (line 6)
25012 * line comment character, SH64: SH64-Chars. (line 6)
25013 * line comment character, Sparc: Sparc-Chars. (line 6)
25014 * line comment character, TIC54X: TIC54X-Chars. (line 6)
25015 * line comment character, TIC6X: TIC6X Syntax. (line 6)
25016 * line comment character, V850: V850-Chars. (line 6)
25017 * line comment character, VAX: VAX-Chars. (line 6)
25018 * line comment character, XGATE: XGATE-Syntax. (line 16)
25019 * line comment character, XStormy16: XStormy16-Chars. (line 6)
25020 * line comment character, Z80: Z80-Chars. (line 6)
25021 * line comment character, Z8000: Z8000-Chars. (line 6)
25022 * line comment characters, CRIS: CRIS-Chars. (line 6)
25023 * line comment characters, MMIX: MMIX-Chars. (line 6)
25024 * line directive: Line. (line 6)
25025 * line directive, MSP 430: MSP430 Directives. (line 14)
25026 * line numbers, in input files: Input Files. (line 35)
25027 * line numbers, in warnings/errors: Errors. (line 16)
25028 * line separator character: Statements. (line 6)
25029 * line separator character, Nios II: Nios II Chars. (line 6)
25030 * line separator, AArch64: AArch64-Chars. (line 10)
25031 * line separator, Alpha: Alpha-Chars. (line 11)
25032 * line separator, ARC: ARC-Chars. (line 12)
25033 * line separator, ARM: ARM-Chars. (line 14)
25034 * line separator, AVR: AVR-Chars. (line 14)
25035 * line separator, CR16: CR16-Chars. (line 13)
25036 * line separator, Epiphany: Epiphany-Chars. (line 14)
25037 * line separator, H8/300: H8/300-Chars. (line 8)
25038 * line separator, i386: i386-Chars. (line 18)
25039 * line separator, i860: i860-Chars. (line 14)
25040 * line separator, i960: i960-Chars. (line 14)
25041 * line separator, IA-64: IA-64-Chars. (line 8)
25042 * line separator, IP2K: IP2K-Chars. (line 14)
25043 * line separator, LM32: LM32-Chars. (line 12)
25044 * line separator, M32C: M32C-Chars. (line 14)
25045 * line separator, M680x0: M68K-Chars. (line 20)
25046 * line separator, M68HC11: M68HC11-Syntax. (line 27)
25047 * line separator, Meta: Meta-Chars. (line 8)
25048 * line separator, MicroBlaze: MicroBlaze-Chars. (line 14)
25049 * line separator, MIPS: MIPS-Chars. (line 14)
25050 * line separator, MSP 430: MSP430-Chars. (line 14)
25051 * line separator, NS32K: NS32K-Chars. (line 18)
25052 * line separator, PJ: PJ-Chars. (line 14)
25053 * line separator, PowerPC: PowerPC-Chars. (line 18)
25054 * line separator, RL78: RL78-Chars. (line 14)
25055 * line separator, RX: RX-Chars. (line 14)
25056 * line separator, s390: s390 Characters. (line 13)
25057 * line separator, SCORE: SCORE-Chars. (line 14)
25058 * line separator, SH: SH-Chars. (line 8)
25059 * line separator, SH64: SH64-Chars. (line 13)
25060 * line separator, Sparc: Sparc-Chars. (line 14)
25061 * line separator, TIC54X: TIC54X-Chars. (line 17)
25062 * line separator, TIC6X: TIC6X Syntax. (line 13)
25063 * line separator, V850: V850-Chars. (line 13)
25064 * line separator, VAX: VAX-Chars. (line 14)
25065 * line separator, XGATE: XGATE-Syntax. (line 26)
25066 * line separator, XStormy16: XStormy16-Chars. (line 14)
25067 * line separator, Z80: Z80-Chars. (line 13)
25068 * line separator, Z8000: Z8000-Chars. (line 13)
25069 * lines starting with #: Comments. (line 33)
25070 * linker: Object. (line 15)
25071 * linker, and assembler: Secs Background. (line 10)
25072 * linkonce directive: Linkonce. (line 6)
25073 * list directive: List. (line 6)
25074 * list directive, TIC54X: TIC54X-Directives. (line 131)
25075 * listing control, turning off: Nolist. (line 6)
25076 * listing control, turning on: List. (line 6)
25077 * listing control: new page: Eject. (line 6)
25078 * listing control: paper size: Psize. (line 6)
25079 * listing control: subtitle: Sbttl. (line 6)
25080 * listing control: title line: Title. (line 6)
25081 * listings, enabling: a. (line 6)
25082 * literal directive: Literal Directive. (line 6)
25083 * literal pool entries, s390: s390 Literal Pool Entries.
25085 * literal_position directive: Literal Position Directive.
25087 * literal_prefix directive: Literal Prefix Directive.
25089 * little endian output, MIPS: Overview. (line 767)
25090 * little endian output, PJ: Overview. (line 670)
25091 * little-endian output, MIPS: MIPS Options. (line 13)
25092 * little-endian output, TIC6X: TIC6X Options. (line 46)
25093 * LM32 line comment character: LM32-Chars. (line 6)
25094 * LM32 line separator: LM32-Chars. (line 12)
25095 * LM32 modifiers: LM32-Modifiers. (line 6)
25096 * LM32 opcode summary: LM32 Opcodes. (line 6)
25097 * LM32 options (none): LM32 Options. (line 6)
25098 * LM32 register names: LM32-Regs. (line 6)
25099 * LM32 support: LM32-Dependent. (line 6)
25100 * ln directive: Ln. (line 6)
25101 * lo directive, Nios II: Nios II Relocations. (line 23)
25102 * lo pseudo-op, V850: V850 Opcodes. (line 22)
25103 * loc directive: Loc. (line 6)
25104 * loc_mark_labels directive: Loc_mark_labels. (line 6)
25105 * local common symbols: Lcomm. (line 6)
25106 * local directive: Local. (line 6)
25107 * local labels: Symbol Names. (line 40)
25108 * local symbol names: Symbol Names. (line 27)
25109 * local symbols, retaining in output: L. (line 6)
25110 * location counter: Dot. (line 6)
25111 * location counter, advancing: Org. (line 6)
25112 * location counter, Z80: Z80-Chars. (line 15)
25113 * logical file name: File. (line 13)
25114 * logical line number: Line. (line 6)
25115 * logical line numbers: Comments. (line 33)
25116 * long directive: Long. (line 6)
25117 * long directive, ARC: ARC Directives. (line 156)
25118 * long directive, i386: i386-Float. (line 21)
25119 * long directive, TIC54X: TIC54X-Directives. (line 135)
25120 * long directive, x86-64: i386-Float. (line 21)
25121 * longcall pseudo-op, V850: V850 Opcodes. (line 123)
25122 * longcalls directive: Longcalls Directive. (line 6)
25123 * longjump pseudo-op, V850: V850 Opcodes. (line 129)
25124 * loop directive, TIC54X: TIC54X-Directives. (line 143)
25125 * LOOP instructions, alignment: Xtensa Automatic Alignment.
25127 * low directive, M32R: M32R-Directives. (line 9)
25128 * lp register, V850: V850-Regs. (line 98)
25129 * lval: Z8000 Directives. (line 27)
25130 * LWP, i386: i386-LWP. (line 6)
25131 * LWP, x86-64: i386-LWP. (line 6)
25132 * M16C architecture option: M32C-Opts. (line 12)
25133 * M32C architecture option: M32C-Opts. (line 9)
25134 * M32C line comment character: M32C-Chars. (line 6)
25135 * M32C line separator: M32C-Chars. (line 14)
25136 * M32C modifiers: M32C-Modifiers. (line 6)
25137 * M32C options: M32C-Opts. (line 6)
25138 * M32C support: M32C-Dependent. (line 6)
25139 * M32R architecture options: M32R-Opts. (line 17)
25140 * M32R directives: M32R-Directives. (line 6)
25141 * M32R options: M32R-Opts. (line 6)
25142 * M32R support: M32R-Dependent. (line 6)
25143 * M32R warnings: M32R-Warnings. (line 6)
25144 * M680x0 addressing modes: M68K-Syntax. (line 21)
25145 * M680x0 architecture options: M68K-Opts. (line 98)
25146 * M680x0 branch improvement: M68K-Branch. (line 6)
25147 * M680x0 directives: M68K-Directives. (line 6)
25148 * M680x0 floating point: M68K-Float. (line 6)
25149 * M680x0 immediate character: M68K-Chars. (line 13)
25150 * M680x0 line comment character: M68K-Chars. (line 6)
25151 * M680x0 line separator: M68K-Chars. (line 20)
25152 * M680x0 opcodes: M68K-opcodes. (line 6)
25153 * M680x0 options: M68K-Opts. (line 6)
25154 * M680x0 pseudo-opcodes: M68K-Branch. (line 6)
25155 * M680x0 size modifiers: M68K-Syntax. (line 8)
25156 * M680x0 support: M68K-Dependent. (line 6)
25157 * M680x0 syntax: M68K-Syntax. (line 8)
25158 * M68HC11 addressing modes: M68HC11-Syntax. (line 30)
25159 * M68HC11 and M68HC12 support: M68HC11-Dependent. (line 6)
25160 * M68HC11 assembler directive .far: M68HC11-Directives. (line 20)
25161 * M68HC11 assembler directive .interrupt: M68HC11-Directives. (line 26)
25162 * M68HC11 assembler directive .mode: M68HC11-Directives. (line 16)
25163 * M68HC11 assembler directive .relax: M68HC11-Directives. (line 10)
25164 * M68HC11 assembler directive .xrefb: M68HC11-Directives. (line 31)
25165 * M68HC11 assembler directives: M68HC11-Directives. (line 6)
25166 * M68HC11 branch improvement: M68HC11-Branch. (line 6)
25167 * M68HC11 floating point: M68HC11-Float. (line 6)
25168 * M68HC11 line comment character: M68HC11-Syntax. (line 17)
25169 * M68HC11 line separator: M68HC11-Syntax. (line 27)
25170 * M68HC11 modifiers: M68HC11-Modifiers. (line 6)
25171 * M68HC11 opcodes: M68HC11-opcodes. (line 6)
25172 * M68HC11 options: M68HC11-Opts. (line 6)
25173 * M68HC11 pseudo-opcodes: M68HC11-Branch. (line 6)
25174 * M68HC11 syntax: M68HC11-Syntax. (line 6)
25175 * M68HC12 assembler directives: M68HC11-Directives. (line 6)
25176 * machine dependencies: Machine Dependencies.
25178 * machine directives, AArch64: AArch64 Directives. (line 6)
25179 * machine directives, ARC: ARC Directives. (line 6)
25180 * machine directives, ARM: ARM Directives. (line 6)
25181 * machine directives, H8/300 (none): H8/300 Directives. (line 6)
25182 * machine directives, i860: Directives-i860. (line 6)
25183 * machine directives, i960: Directives-i960. (line 6)
25184 * machine directives, MSP 430: MSP430 Directives. (line 6)
25185 * machine directives, Nios II: Nios II Directives. (line 6)
25186 * machine directives, SH: SH Directives. (line 6)
25187 * machine directives, SH64: SH64 Directives. (line 9)
25188 * machine directives, SPARC: Sparc-Directives. (line 6)
25189 * machine directives, TIC54X: TIC54X-Directives. (line 6)
25190 * machine directives, TIC6X: TIC6X Directives. (line 6)
25191 * machine directives, TILE-Gx: TILE-Gx Directives. (line 6)
25192 * machine directives, TILEPro: TILEPro Directives. (line 6)
25193 * machine directives, V850: V850 Directives. (line 6)
25194 * machine directives, VAX: VAX-directives. (line 6)
25195 * machine directives, x86: i386-Directives. (line 6)
25196 * machine directives, XStormy16: XStormy16 Directives.
25198 * machine independent directives: Pseudo Ops. (line 6)
25199 * machine instructions (not covered): Manual. (line 14)
25200 * machine relocations, Nios II: Nios II Relocations. (line 6)
25201 * machine-independent syntax: Syntax. (line 6)
25202 * macro directive: Macro. (line 28)
25203 * macro directive, TIC54X: TIC54X-Directives. (line 153)
25204 * macros: Macro. (line 6)
25205 * macros, count executed: Macro. (line 143)
25206 * Macros, MSP 430: MSP430-Macros. (line 6)
25207 * macros, TIC54X: TIC54X-Macros. (line 6)
25208 * make rules: MD. (line 6)
25209 * manual, structure and purpose: Manual. (line 6)
25210 * math builtins, TIC54X: TIC54X-Builtins. (line 6)
25211 * Maximum number of continuation lines: listing. (line 34)
25212 * memory references, i386: i386-Memory. (line 6)
25213 * memory references, x86-64: i386-Memory. (line 6)
25214 * memory-mapped registers, TIC54X: TIC54X-MMRegs. (line 6)
25215 * merging text and data sections: R. (line 6)
25216 * messages from assembler: Errors. (line 6)
25217 * Meta architectures: Meta Options. (line 6)
25218 * Meta line comment character: Meta-Chars. (line 6)
25219 * Meta line separator: Meta-Chars. (line 8)
25220 * Meta options: Meta Options. (line 6)
25221 * Meta registers: Meta-Regs. (line 6)
25222 * Meta support: Meta-Dependent. (line 6)
25223 * MicroBlaze architectures: MicroBlaze-Dependent.
25225 * MicroBlaze directives: MicroBlaze Directives.
25227 * MicroBlaze line comment character: MicroBlaze-Chars. (line 6)
25228 * MicroBlaze line separator: MicroBlaze-Chars. (line 14)
25229 * MicroBlaze support: MicroBlaze-Dependent.
25231 * minus, permitted arguments: Infix Ops. (line 49)
25232 * MIPS 32-bit microMIPS instruction generation override: MIPS assembly options.
25234 * MIPS architecture options: MIPS Options. (line 29)
25235 * MIPS big-endian output: MIPS Options. (line 13)
25236 * MIPS CPU override: MIPS ISA. (line 19)
25237 * MIPS directives to override command line options: MIPS assembly options.
25239 * MIPS DSP Release 1 instruction generation override: MIPS ASE Instruction Generation Overrides.
25241 * MIPS DSP Release 2 instruction generation override: MIPS ASE Instruction Generation Overrides.
25243 * MIPS endianness: Overview. (line 764)
25244 * MIPS eXtended Physical Address (XPA) instruction generation override: MIPS ASE Instruction Generation Overrides.
25246 * MIPS IEEE 754 NaN data encoding selection: MIPS NaN Encodings.
25248 * MIPS ISA: Overview. (line 770)
25249 * MIPS ISA override: MIPS ISA. (line 6)
25250 * MIPS line comment character: MIPS-Chars. (line 6)
25251 * MIPS line separator: MIPS-Chars. (line 14)
25252 * MIPS little-endian output: MIPS Options. (line 13)
25253 * MIPS MCU instruction generation override: MIPS ASE Instruction Generation Overrides.
25255 * MIPS MDMX instruction generation override: MIPS ASE Instruction Generation Overrides.
25257 * MIPS MIPS-3D instruction generation override: MIPS ASE Instruction Generation Overrides.
25259 * MIPS MT instruction generation override: MIPS ASE Instruction Generation Overrides.
25261 * MIPS option stack: MIPS Option Stack. (line 6)
25262 * MIPS processor: MIPS-Dependent. (line 6)
25263 * MIPS SIMD Architecture instruction generation override: MIPS ASE Instruction Generation Overrides.
25265 * MIT: M68K-Syntax. (line 6)
25266 * mlib directive, TIC54X: TIC54X-Directives. (line 159)
25267 * mlist directive, TIC54X: TIC54X-Directives. (line 164)
25268 * MMIX assembler directive BSPEC: MMIX-Pseudos. (line 131)
25269 * MMIX assembler directive BYTE: MMIX-Pseudos. (line 97)
25270 * MMIX assembler directive ESPEC: MMIX-Pseudos. (line 131)
25271 * MMIX assembler directive GREG: MMIX-Pseudos. (line 50)
25272 * MMIX assembler directive IS: MMIX-Pseudos. (line 42)
25273 * MMIX assembler directive LOC: MMIX-Pseudos. (line 7)
25274 * MMIX assembler directive LOCAL: MMIX-Pseudos. (line 28)
25275 * MMIX assembler directive OCTA: MMIX-Pseudos. (line 108)
25276 * MMIX assembler directive PREFIX: MMIX-Pseudos. (line 120)
25277 * MMIX assembler directive TETRA: MMIX-Pseudos. (line 108)
25278 * MMIX assembler directive WYDE: MMIX-Pseudos. (line 108)
25279 * MMIX assembler directives: MMIX-Pseudos. (line 6)
25280 * MMIX line comment characters: MMIX-Chars. (line 6)
25281 * MMIX options: MMIX-Opts. (line 6)
25282 * MMIX pseudo-op BSPEC: MMIX-Pseudos. (line 131)
25283 * MMIX pseudo-op BYTE: MMIX-Pseudos. (line 97)
25284 * MMIX pseudo-op ESPEC: MMIX-Pseudos. (line 131)
25285 * MMIX pseudo-op GREG: MMIX-Pseudos. (line 50)
25286 * MMIX pseudo-op IS: MMIX-Pseudos. (line 42)
25287 * MMIX pseudo-op LOC: MMIX-Pseudos. (line 7)
25288 * MMIX pseudo-op LOCAL: MMIX-Pseudos. (line 28)
25289 * MMIX pseudo-op OCTA: MMIX-Pseudos. (line 108)
25290 * MMIX pseudo-op PREFIX: MMIX-Pseudos. (line 120)
25291 * MMIX pseudo-op TETRA: MMIX-Pseudos. (line 108)
25292 * MMIX pseudo-op WYDE: MMIX-Pseudos. (line 108)
25293 * MMIX pseudo-ops: MMIX-Pseudos. (line 6)
25294 * MMIX register names: MMIX-Regs. (line 6)
25295 * MMIX support: MMIX-Dependent. (line 6)
25296 * mmixal differences: MMIX-mmixal. (line 6)
25297 * mmregs directive, TIC54X: TIC54X-Directives. (line 169)
25298 * mmsg directive, TIC54X: TIC54X-Directives. (line 77)
25299 * MMX, i386: i386-SIMD. (line 6)
25300 * MMX, x86-64: i386-SIMD. (line 6)
25301 * mnemonic compatibility, i386: i386-Mnemonics. (line 62)
25302 * mnemonic suffixes, i386: i386-Variations. (line 29)
25303 * mnemonic suffixes, x86-64: i386-Variations. (line 29)
25304 * mnemonics for opcodes, VAX: VAX-opcodes. (line 6)
25305 * mnemonics, AVR: AVR Opcodes. (line 6)
25306 * mnemonics, D10V: D10V-Opcodes. (line 6)
25307 * mnemonics, D30V: D30V-Opcodes. (line 6)
25308 * mnemonics, H8/300: H8/300 Opcodes. (line 6)
25309 * mnemonics, LM32: LM32 Opcodes. (line 6)
25310 * mnemonics, SH: SH Opcodes. (line 6)
25311 * mnemonics, SH64: SH64 Opcodes. (line 6)
25312 * mnemonics, Z8000: Z8000 Opcodes. (line 6)
25313 * mnolist directive, TIC54X: TIC54X-Directives. (line 164)
25314 * modifiers, M32C: M32C-Modifiers. (line 6)
25315 * Motorola syntax for the 680x0: M68K-Moto-Syntax. (line 6)
25316 * MOVI instructions, relaxation: Xtensa Immediate Relaxation.
25318 * MOVN, MOVZ and MOVK group relocations, AArch64: AArch64-Relocations.
25320 * MOVW and MOVT relocations, ARM: ARM-Relocations. (line 21)
25321 * MRI compatibility mode: M. (line 6)
25322 * mri directive: MRI. (line 6)
25323 * MRI mode, temporarily: MRI. (line 6)
25324 * MSP 430 floating point (IEEE): MSP430 Floating Point.
25326 * MSP 430 identifiers: MSP430-Chars. (line 17)
25327 * MSP 430 line comment character: MSP430-Chars. (line 6)
25328 * MSP 430 line separator: MSP430-Chars. (line 14)
25329 * MSP 430 machine directives: MSP430 Directives. (line 6)
25330 * MSP 430 macros: MSP430-Macros. (line 6)
25331 * MSP 430 opcodes: MSP430 Opcodes. (line 6)
25332 * MSP 430 options (none): MSP430 Options. (line 6)
25333 * MSP 430 profiling capability: MSP430 Profiling Capability.
25335 * MSP 430 register names: MSP430-Regs. (line 6)
25336 * MSP 430 support: MSP430-Dependent. (line 6)
25337 * MSP430 Assembler Extensions: MSP430-Ext. (line 6)
25338 * mul instruction, i386: i386-Notes. (line 6)
25339 * mul instruction, x86-64: i386-Notes. (line 6)
25340 * N32K support: NS32K-Dependent. (line 6)
25341 * name: Z8000 Directives. (line 18)
25342 * named section: Section. (line 6)
25343 * named sections: Ld Sections. (line 8)
25344 * names, symbol: Symbol Names. (line 6)
25345 * naming object file: o. (line 6)
25346 * NDS32 options: NDS32 Options. (line 6)
25347 * NDS32 processor: NDS32-Dependent. (line 6)
25348 * new page, in listings: Eject. (line 6)
25349 * newblock directive, TIC54X: TIC54X-Directives. (line 175)
25350 * newline (\n): Strings. (line 21)
25351 * newline, required at file end: Statements. (line 14)
25352 * Nios II line comment character: Nios II Chars. (line 6)
25353 * Nios II line separator character: Nios II Chars. (line 6)
25354 * Nios II machine directives: Nios II Directives. (line 6)
25355 * Nios II machine relocations: Nios II Relocations. (line 6)
25356 * Nios II opcodes: Nios II Opcodes. (line 6)
25357 * Nios II options: Nios II Options. (line 6)
25358 * Nios II support: NiosII-Dependent. (line 6)
25359 * Nios support: NiosII-Dependent. (line 6)
25360 * no-absolute-literals directive: Absolute Literals Directive.
25362 * no-longcalls directive: Longcalls Directive. (line 6)
25363 * no-relax command line option, Nios II: Nios II Options. (line 20)
25364 * no-schedule directive: Schedule Directive. (line 6)
25365 * no-transform directive: Transform Directive. (line 6)
25366 * nolist directive: Nolist. (line 6)
25367 * nolist directive, TIC54X: TIC54X-Directives. (line 131)
25368 * NOP pseudo op, ARM: ARM Opcodes. (line 9)
25369 * notes for Alpha: Alpha Notes. (line 6)
25370 * NS32K line comment character: NS32K-Chars. (line 6)
25371 * NS32K line separator: NS32K-Chars. (line 18)
25372 * null-terminated strings: Asciz. (line 6)
25373 * number constants: Numbers. (line 6)
25374 * number of macros executed: Macro. (line 143)
25375 * numbered subsections: Sub-Sections. (line 6)
25376 * numbers, 16-bit: hword. (line 6)
25377 * numeric values: Expressions. (line 6)
25378 * nword directive, SPARC: Sparc-Directives. (line 20)
25379 * object attributes: Object Attributes. (line 6)
25380 * object file: Object. (line 6)
25381 * object file format: Object Formats. (line 6)
25382 * object file name: o. (line 6)
25383 * object file, after errors: Z. (line 6)
25384 * obsolescent directives: Deprecated. (line 6)
25385 * octa directive: Octa. (line 6)
25386 * octal character code (\DDD): Strings. (line 30)
25387 * octal integers: Integers. (line 9)
25388 * offset directive: Offset. (line 6)
25389 * offset directive, V850: V850 Directives. (line 6)
25390 * opcode mnemonics, VAX: VAX-opcodes. (line 6)
25391 * opcode names, TILE-Gx: TILE-Gx Opcodes. (line 6)
25392 * opcode names, TILEPro: TILEPro Opcodes. (line 6)
25393 * opcode names, Xtensa: Xtensa Opcodes. (line 6)
25394 * opcode summary, AVR: AVR Opcodes. (line 6)
25395 * opcode summary, D10V: D10V-Opcodes. (line 6)
25396 * opcode summary, D30V: D30V-Opcodes. (line 6)
25397 * opcode summary, H8/300: H8/300 Opcodes. (line 6)
25398 * opcode summary, LM32: LM32 Opcodes. (line 6)
25399 * opcode summary, SH: SH Opcodes. (line 6)
25400 * opcode summary, SH64: SH64 Opcodes. (line 6)
25401 * opcode summary, Z8000: Z8000 Opcodes. (line 6)
25402 * opcodes for AArch64: AArch64 Opcodes. (line 6)
25403 * opcodes for ARC: ARC Opcodes. (line 6)
25404 * opcodes for ARM: ARM Opcodes. (line 6)
25405 * opcodes for MSP 430: MSP430 Opcodes. (line 6)
25406 * opcodes for Nios II: Nios II Opcodes. (line 6)
25407 * opcodes for V850: V850 Opcodes. (line 6)
25408 * opcodes, i860: Opcodes for i860. (line 6)
25409 * opcodes, i960: Opcodes for i960. (line 6)
25410 * opcodes, M680x0: M68K-opcodes. (line 6)
25411 * opcodes, M68HC11: M68HC11-opcodes. (line 6)
25412 * operand delimiters, i386: i386-Variations. (line 15)
25413 * operand delimiters, x86-64: i386-Variations. (line 15)
25414 * operand notation, VAX: VAX-operands. (line 6)
25415 * operands in expressions: Arguments. (line 6)
25416 * operator precedence: Infix Ops. (line 11)
25417 * operators, in expressions: Operators. (line 6)
25418 * operators, permitted arguments: Infix Ops. (line 6)
25419 * optimization, D10V: Overview. (line 527)
25420 * optimization, D30V: Overview. (line 532)
25421 * optimizations: Xtensa Optimizations.
25423 * option directive, ARC: ARC Directives. (line 159)
25424 * option directive, TIC54X: TIC54X-Directives. (line 179)
25425 * option summary: Overview. (line 6)
25426 * options for AArch64 (none): AArch64 Options. (line 6)
25427 * options for Alpha: Alpha Options. (line 6)
25428 * options for ARC (none): ARC Options. (line 6)
25429 * options for ARM (none): ARM Options. (line 6)
25430 * options for AVR (none): AVR Options. (line 6)
25431 * options for Blackfin (none): Blackfin Options. (line 6)
25432 * options for i386: i386-Options. (line 6)
25433 * options for IA-64: IA-64 Options. (line 6)
25434 * options for LM32 (none): LM32 Options. (line 6)
25435 * options for Meta: Meta Options. (line 6)
25436 * options for MSP430 (none): MSP430 Options. (line 6)
25437 * options for NDS32: NDS32 Options. (line 6)
25438 * options for Nios II: Nios II Options. (line 6)
25439 * options for PDP-11: PDP-11-Options. (line 6)
25440 * options for PowerPC: PowerPC-Opts. (line 6)
25441 * options for s390: s390 Options. (line 6)
25442 * options for SCORE: SCORE-Opts. (line 6)
25443 * options for SPARC: Sparc-Opts. (line 6)
25444 * options for TIC6X: TIC6X Options. (line 6)
25445 * options for V850 (none): V850 Options. (line 6)
25446 * options for VAX/VMS: VAX-Opts. (line 42)
25447 * options for x86-64: i386-Options. (line 6)
25448 * options for Z80: Z80 Options. (line 6)
25449 * options, all versions of assembler: Invoking. (line 6)
25450 * options, command line: Command Line. (line 13)
25451 * options, CRIS: CRIS-Opts. (line 6)
25452 * options, D10V: D10V-Opts. (line 6)
25453 * options, D30V: D30V-Opts. (line 6)
25454 * options, Epiphany: Epiphany Options. (line 6)
25455 * options, H8/300: H8/300 Options. (line 6)
25456 * options, i960: Options-i960. (line 6)
25457 * options, IP2K: IP2K-Opts. (line 6)
25458 * options, M32C: M32C-Opts. (line 6)
25459 * options, M32R: M32R-Opts. (line 6)
25460 * options, M680x0: M68K-Opts. (line 6)
25461 * options, M68HC11: M68HC11-Opts. (line 6)
25462 * options, MMIX: MMIX-Opts. (line 6)
25463 * options, PJ: PJ Options. (line 6)
25464 * options, RL78: RL78-Opts. (line 6)
25465 * options, RX: RX-Opts. (line 6)
25466 * options, SH: SH Options. (line 6)
25467 * options, SH64: SH64 Options. (line 6)
25468 * options, TIC54X: TIC54X-Opts. (line 6)
25469 * options, XGATE: XGATE-Opts. (line 6)
25470 * options, Z8000: Z8000 Options. (line 6)
25471 * org directive: Org. (line 6)
25472 * other attribute, of a.out symbol: Symbol Other. (line 6)
25473 * output file: Object. (line 6)
25474 * p2align directive: P2align. (line 6)
25475 * p2alignl directive: P2align. (line 28)
25476 * p2alignw directive: P2align. (line 28)
25477 * padding the location counter: Align. (line 6)
25478 * padding the location counter given a power of two: P2align. (line 6)
25479 * padding the location counter given number of bytes: Balign. (line 6)
25480 * page, in listings: Eject. (line 6)
25481 * paper size, for listings: Psize. (line 6)
25482 * paths for .include: I. (line 6)
25483 * patterns, writing in memory: Fill. (line 6)
25484 * PDP-11 comments: PDP-11-Syntax. (line 16)
25485 * PDP-11 floating-point register syntax: PDP-11-Syntax. (line 13)
25486 * PDP-11 general-purpose register syntax: PDP-11-Syntax. (line 10)
25487 * PDP-11 instruction naming: PDP-11-Mnemonics. (line 6)
25488 * PDP-11 line separator: PDP-11-Syntax. (line 19)
25489 * PDP-11 support: PDP-11-Dependent. (line 6)
25490 * PDP-11 syntax: PDP-11-Syntax. (line 6)
25491 * PIC code generation for ARM: ARM Options. (line 169)
25492 * PIC code generation for M32R: M32R-Opts. (line 42)
25493 * PIC selection, MIPS: MIPS Options. (line 21)
25494 * PJ endianness: Overview. (line 667)
25495 * PJ line comment character: PJ-Chars. (line 6)
25496 * PJ line separator: PJ-Chars. (line 14)
25497 * PJ options: PJ Options. (line 6)
25498 * PJ support: PJ-Dependent. (line 6)
25499 * plus, permitted arguments: Infix Ops. (line 44)
25500 * popsection directive: PopSection. (line 6)
25501 * Position-independent code, CRIS: CRIS-Opts. (line 27)
25502 * Position-independent code, symbols in, CRIS: CRIS-Pic. (line 6)
25503 * PowerPC architectures: PowerPC-Opts. (line 6)
25504 * PowerPC directives: PowerPC-Pseudo. (line 6)
25505 * PowerPC line comment character: PowerPC-Chars. (line 6)
25506 * PowerPC line separator: PowerPC-Chars. (line 18)
25507 * PowerPC options: PowerPC-Opts. (line 6)
25508 * PowerPC support: PPC-Dependent. (line 6)
25509 * precedence of operators: Infix Ops. (line 11)
25510 * precision, floating point: Flonums. (line 6)
25511 * prefix operators: Prefix Ops. (line 6)
25512 * prefixes, i386: i386-Prefixes. (line 6)
25513 * preprocessing: Preprocessing. (line 6)
25514 * preprocessing, turning on and off: Preprocessing. (line 27)
25515 * previous directive: Previous. (line 6)
25516 * primary attributes, COFF symbols: COFF Symbols. (line 13)
25517 * print directive: Print. (line 6)
25518 * proc directive, SPARC: Sparc-Directives. (line 25)
25519 * profiler directive, MSP 430: MSP430 Directives. (line 26)
25520 * profiling capability for MSP 430: MSP430 Profiling Capability.
25522 * protected directive: Protected. (line 6)
25523 * pseudo-op .arch, CRIS: CRIS-Pseudos. (line 45)
25524 * pseudo-op .dword, CRIS: CRIS-Pseudos. (line 12)
25525 * pseudo-op .syntax, CRIS: CRIS-Pseudos. (line 17)
25526 * pseudo-op BSPEC, MMIX: MMIX-Pseudos. (line 131)
25527 * pseudo-op BYTE, MMIX: MMIX-Pseudos. (line 97)
25528 * pseudo-op ESPEC, MMIX: MMIX-Pseudos. (line 131)
25529 * pseudo-op GREG, MMIX: MMIX-Pseudos. (line 50)
25530 * pseudo-op IS, MMIX: MMIX-Pseudos. (line 42)
25531 * pseudo-op LOC, MMIX: MMIX-Pseudos. (line 7)
25532 * pseudo-op LOCAL, MMIX: MMIX-Pseudos. (line 28)
25533 * pseudo-op OCTA, MMIX: MMIX-Pseudos. (line 108)
25534 * pseudo-op PREFIX, MMIX: MMIX-Pseudos. (line 120)
25535 * pseudo-op TETRA, MMIX: MMIX-Pseudos. (line 108)
25536 * pseudo-op WYDE, MMIX: MMIX-Pseudos. (line 108)
25537 * pseudo-opcodes for XStormy16: XStormy16 Opcodes. (line 6)
25538 * pseudo-opcodes, M680x0: M68K-Branch. (line 6)
25539 * pseudo-opcodes, M68HC11: M68HC11-Branch. (line 6)
25540 * pseudo-ops for branch, VAX: VAX-branch. (line 6)
25541 * pseudo-ops, CRIS: CRIS-Pseudos. (line 6)
25542 * pseudo-ops, machine independent: Pseudo Ops. (line 6)
25543 * pseudo-ops, MMIX: MMIX-Pseudos. (line 6)
25544 * psize directive: Psize. (line 6)
25545 * PSR bits: IA-64-Bits. (line 6)
25546 * pstring directive, TIC54X: TIC54X-Directives. (line 208)
25547 * psw register, V850: V850-Regs. (line 116)
25548 * purgem directive: Purgem. (line 6)
25549 * purpose of GNU assembler: GNU Assembler. (line 12)
25550 * pushsection directive: PushSection. (line 6)
25551 * quad directive: Quad. (line 6)
25552 * quad directive, i386: i386-Float. (line 21)
25553 * quad directive, x86-64: i386-Float. (line 21)
25554 * real-mode code, i386: i386-16bit. (line 6)
25555 * ref directive, TIC54X: TIC54X-Directives. (line 103)
25556 * refsym directive, MSP 430: MSP430 Directives. (line 30)
25557 * register directive, SPARC: Sparc-Directives. (line 29)
25558 * register names, AArch64: AArch64-Regs. (line 6)
25559 * register names, Alpha: Alpha-Regs. (line 6)
25560 * register names, ARC: ARC-Regs. (line 6)
25561 * register names, ARM: ARM-Regs. (line 6)
25562 * register names, AVR: AVR-Regs. (line 6)
25563 * register names, CRIS: CRIS-Regs. (line 6)
25564 * register names, H8/300: H8/300-Regs. (line 6)
25565 * register names, IA-64: IA-64-Regs. (line 6)
25566 * register names, LM32: LM32-Regs. (line 6)
25567 * register names, MMIX: MMIX-Regs. (line 6)
25568 * register names, MSP 430: MSP430-Regs. (line 6)
25569 * register names, Sparc: Sparc-Regs. (line 6)
25570 * register names, TILE-Gx: TILE-Gx Registers. (line 6)
25571 * register names, TILEPro: TILEPro Registers. (line 6)
25572 * register names, V850: V850-Regs. (line 6)
25573 * register names, VAX: VAX-operands. (line 17)
25574 * register names, Xtensa: Xtensa Registers. (line 6)
25575 * register names, Z80: Z80-Regs. (line 6)
25576 * register naming, s390: s390 Register. (line 6)
25577 * register operands, i386: i386-Variations. (line 15)
25578 * register operands, x86-64: i386-Variations. (line 15)
25579 * registers, D10V: D10V-Regs. (line 6)
25580 * registers, D30V: D30V-Regs. (line 6)
25581 * registers, i386: i386-Regs. (line 6)
25582 * registers, Meta: Meta-Regs. (line 6)
25583 * registers, SH: SH-Regs. (line 6)
25584 * registers, SH64: SH64-Regs. (line 6)
25585 * registers, TIC54X memory-mapped: TIC54X-MMRegs. (line 6)
25586 * registers, x86-64: i386-Regs. (line 6)
25587 * registers, Z8000: Z8000-Regs. (line 6)
25588 * relax-all command line option, Nios II: Nios II Options. (line 13)
25589 * relax-section command line option, Nios II: Nios II Options.
25591 * relaxation: Xtensa Relaxation. (line 6)
25592 * relaxation of ADDI instructions: Xtensa Immediate Relaxation.
25594 * relaxation of branch instructions: Xtensa Branch Relaxation.
25596 * relaxation of call instructions: Xtensa Call Relaxation.
25598 * relaxation of immediate fields: Xtensa Immediate Relaxation.
25600 * relaxation of jump instructions: Xtensa Jump Relaxation.
25602 * relaxation of L16SI instructions: Xtensa Immediate Relaxation.
25604 * relaxation of L16UI instructions: Xtensa Immediate Relaxation.
25606 * relaxation of L32I instructions: Xtensa Immediate Relaxation.
25608 * relaxation of L8UI instructions: Xtensa Immediate Relaxation.
25610 * relaxation of MOVI instructions: Xtensa Immediate Relaxation.
25612 * reloc directive: Reloc. (line 6)
25613 * relocation: Sections. (line 6)
25614 * relocation example: Ld Sections. (line 40)
25615 * relocations, AArch64: AArch64-Relocations. (line 6)
25616 * relocations, Alpha: Alpha-Relocs. (line 6)
25617 * relocations, Sparc: Sparc-Relocs. (line 6)
25618 * repeat prefixes, i386: i386-Prefixes. (line 44)
25619 * reporting bugs in assembler: Reporting Bugs. (line 6)
25620 * rept directive: Rept. (line 6)
25621 * reserve directive, SPARC: Sparc-Directives. (line 39)
25622 * return instructions, i386: i386-Variations. (line 41)
25623 * return instructions, x86-64: i386-Variations. (line 41)
25624 * REX prefixes, i386: i386-Prefixes. (line 46)
25625 * RL78 assembler directives: RL78-Directives. (line 6)
25626 * RL78 line comment character: RL78-Chars. (line 6)
25627 * RL78 line separator: RL78-Chars. (line 14)
25628 * RL78 modifiers: RL78-Modifiers. (line 6)
25629 * RL78 options: RL78-Opts. (line 6)
25630 * RL78 support: RL78-Dependent. (line 6)
25631 * rsect: Z8000 Directives. (line 52)
25632 * RX assembler directive .3byte: RX-Directives. (line 9)
25633 * RX assembler directive .fetchalign: RX-Directives. (line 13)
25634 * RX assembler directives: RX-Directives. (line 6)
25635 * RX floating point: RX-Float. (line 6)
25636 * RX line comment character: RX-Chars. (line 6)
25637 * RX line separator: RX-Chars. (line 14)
25638 * RX modifiers: RX-Modifiers. (line 6)
25639 * RX options: RX-Opts. (line 6)
25640 * RX support: RX-Dependent. (line 6)
25641 * s390 floating point: s390 Floating Point. (line 6)
25642 * s390 instruction aliases: s390 Aliases. (line 6)
25643 * s390 instruction formats: s390 Formats. (line 6)
25644 * s390 instruction marker: s390 Instruction Marker.
25646 * s390 instruction mnemonics: s390 Mnemonics. (line 6)
25647 * s390 instruction operand modifier: s390 Operand Modifier.
25649 * s390 instruction operands: s390 Operands. (line 6)
25650 * s390 instruction syntax: s390 Syntax. (line 6)
25651 * s390 line comment character: s390 Characters. (line 6)
25652 * s390 line separator: s390 Characters. (line 13)
25653 * s390 literal pool entries: s390 Literal Pool Entries.
25655 * s390 options: s390 Options. (line 6)
25656 * s390 register naming: s390 Register. (line 6)
25657 * s390 support: S/390-Dependent. (line 6)
25658 * sblock directive, TIC54X: TIC54X-Directives. (line 182)
25659 * sbttl directive: Sbttl. (line 6)
25660 * schedule directive: Schedule Directive. (line 6)
25661 * scl directive: Scl. (line 6)
25662 * SCORE architectures: SCORE-Opts. (line 6)
25663 * SCORE directives: SCORE-Pseudo. (line 6)
25664 * SCORE line comment character: SCORE-Chars. (line 6)
25665 * SCORE line separator: SCORE-Chars. (line 14)
25666 * SCORE options: SCORE-Opts. (line 6)
25667 * SCORE processor: SCORE-Dependent. (line 6)
25668 * sdaoff pseudo-op, V850: V850 Opcodes. (line 65)
25669 * search path for .include: I. (line 6)
25670 * sect directive, TIC54X: TIC54X-Directives. (line 188)
25671 * section directive (COFF version): Section. (line 16)
25672 * section directive (ELF version): Section. (line 76)
25673 * section directive, V850: V850 Directives. (line 9)
25674 * section override prefixes, i386: i386-Prefixes. (line 23)
25675 * Section Stack <1>: Previous. (line 6)
25676 * Section Stack <2>: Section. (line 71)
25677 * Section Stack <3>: PopSection. (line 6)
25678 * Section Stack <4>: SubSection. (line 6)
25679 * Section Stack: PushSection. (line 6)
25680 * section-relative addressing: Secs Background. (line 68)
25681 * sections: Sections. (line 6)
25682 * sections in messages, internal: As Sections. (line 6)
25683 * sections, i386: i386-Variations. (line 47)
25684 * sections, named: Ld Sections. (line 8)
25685 * sections, x86-64: i386-Variations. (line 47)
25686 * seg directive, SPARC: Sparc-Directives. (line 44)
25687 * segm: Z8000 Directives. (line 10)
25688 * set at directive, Nios II: Nios II Directives. (line 35)
25689 * set break directive, Nios II: Nios II Directives. (line 43)
25690 * set directive: Set. (line 6)
25691 * set directive, Nios II: Nios II Directives. (line 57)
25692 * set directive, TIC54X: TIC54X-Directives. (line 191)
25693 * set noat directive, Nios II: Nios II Directives. (line 31)
25694 * set nobreak directive, Nios II: Nios II Directives. (line 39)
25695 * set norelax directive, Nios II: Nios II Directives. (line 46)
25696 * set relaxall directive, Nios II: Nios II Directives. (line 53)
25697 * set relaxsection directive, Nios II: Nios II Directives. (line 49)
25698 * SH addressing modes: SH-Addressing. (line 6)
25699 * SH floating point (IEEE): SH Floating Point. (line 6)
25700 * SH line comment character: SH-Chars. (line 6)
25701 * SH line separator: SH-Chars. (line 8)
25702 * SH machine directives: SH Directives. (line 6)
25703 * SH opcode summary: SH Opcodes. (line 6)
25704 * SH options: SH Options. (line 6)
25705 * SH registers: SH-Regs. (line 6)
25706 * SH support: SH-Dependent. (line 6)
25707 * SH64 ABI options: SH64 Options. (line 29)
25708 * SH64 addressing modes: SH64-Addressing. (line 6)
25709 * SH64 ISA options: SH64 Options. (line 6)
25710 * SH64 line comment character: SH64-Chars. (line 6)
25711 * SH64 line separator: SH64-Chars. (line 13)
25712 * SH64 machine directives: SH64 Directives. (line 9)
25713 * SH64 opcode summary: SH64 Opcodes. (line 6)
25714 * SH64 options: SH64 Options. (line 6)
25715 * SH64 registers: SH64-Regs. (line 6)
25716 * SH64 support: SH64-Dependent. (line 6)
25717 * shigh directive, M32R: M32R-Directives. (line 26)
25718 * short directive: Short. (line 6)
25719 * short directive, ARC: ARC Directives. (line 168)
25720 * short directive, TIC54X: TIC54X-Directives. (line 111)
25721 * SIMD, i386: i386-SIMD. (line 6)
25722 * SIMD, x86-64: i386-SIMD. (line 6)
25723 * single character constant: Chars. (line 6)
25724 * single directive: Single. (line 6)
25725 * single directive, i386: i386-Float. (line 14)
25726 * single directive, x86-64: i386-Float. (line 14)
25727 * single quote, Z80: Z80-Chars. (line 20)
25728 * sixteen bit integers: hword. (line 6)
25729 * sixteen byte integer: Octa. (line 6)
25730 * size directive (COFF version): Size. (line 11)
25731 * size directive (ELF version): Size. (line 19)
25732 * size modifiers, D10V: D10V-Size. (line 6)
25733 * size modifiers, D30V: D30V-Size. (line 6)
25734 * size modifiers, M680x0: M68K-Syntax. (line 8)
25735 * size prefixes, i386: i386-Prefixes. (line 27)
25736 * size suffixes, H8/300: H8/300 Opcodes. (line 163)
25737 * size, translations, Sparc: Sparc-Size-Translations.
25739 * sizes operands, i386: i386-Variations. (line 29)
25740 * sizes operands, x86-64: i386-Variations. (line 29)
25741 * skip directive: Skip. (line 6)
25742 * skip directive, M680x0: M68K-Directives. (line 19)
25743 * skip directive, SPARC: Sparc-Directives. (line 48)
25744 * sleb128 directive: Sleb128. (line 6)
25745 * small data, MIPS: MIPS Small Data. (line 6)
25746 * SmartMIPS instruction generation override: MIPS ASE Instruction Generation Overrides.
25748 * SOM symbol attributes: SOM Symbols. (line 6)
25749 * source program: Input Files. (line 6)
25750 * source, destination operands; i386: i386-Variations. (line 22)
25751 * source, destination operands; x86-64: i386-Variations. (line 22)
25752 * sp register: Xtensa Registers. (line 6)
25753 * sp register, V850: V850-Regs. (line 14)
25754 * space directive: Space. (line 6)
25755 * space directive, TIC54X: TIC54X-Directives. (line 196)
25756 * space used, maximum for assembly: statistics. (line 6)
25757 * SPARC architectures: Sparc-Opts. (line 6)
25758 * Sparc constants: Sparc-Constants. (line 6)
25759 * SPARC data alignment: Sparc-Aligned-Data. (line 6)
25760 * SPARC floating point (IEEE): Sparc-Float. (line 6)
25761 * Sparc line comment character: Sparc-Chars. (line 6)
25762 * Sparc line separator: Sparc-Chars. (line 14)
25763 * SPARC machine directives: Sparc-Directives. (line 6)
25764 * SPARC options: Sparc-Opts. (line 6)
25765 * Sparc registers: Sparc-Regs. (line 6)
25766 * Sparc relocations: Sparc-Relocs. (line 6)
25767 * Sparc size translations: Sparc-Size-Translations.
25769 * SPARC support: Sparc-Dependent. (line 6)
25770 * SPARC syntax: Sparc-Aligned-Data. (line 21)
25771 * special characters, M680x0: M68K-Chars. (line 6)
25772 * special purpose registers, MSP 430: MSP430-Regs. (line 11)
25773 * sslist directive, TIC54X: TIC54X-Directives. (line 203)
25774 * ssnolist directive, TIC54X: TIC54X-Directives. (line 203)
25775 * stabd directive: Stab. (line 38)
25776 * stabn directive: Stab. (line 48)
25777 * stabs directive: Stab. (line 51)
25778 * stabX directives: Stab. (line 6)
25779 * standard assembler sections: Secs Background. (line 27)
25780 * standard input, as input file: Command Line. (line 10)
25781 * statement separator character: Statements. (line 6)
25782 * statement separator, AArch64: AArch64-Chars. (line 10)
25783 * statement separator, Alpha: Alpha-Chars. (line 11)
25784 * statement separator, ARC: ARC-Chars. (line 12)
25785 * statement separator, ARM: ARM-Chars. (line 14)
25786 * statement separator, AVR: AVR-Chars. (line 14)
25787 * statement separator, CR16: CR16-Chars. (line 13)
25788 * statement separator, Epiphany: Epiphany-Chars. (line 14)
25789 * statement separator, H8/300: H8/300-Chars. (line 8)
25790 * statement separator, i386: i386-Chars. (line 18)
25791 * statement separator, i860: i860-Chars. (line 14)
25792 * statement separator, i960: i960-Chars. (line 14)
25793 * statement separator, IA-64: IA-64-Chars. (line 8)
25794 * statement separator, IP2K: IP2K-Chars. (line 14)
25795 * statement separator, LM32: LM32-Chars. (line 12)
25796 * statement separator, M32C: M32C-Chars. (line 14)
25797 * statement separator, M68HC11: M68HC11-Syntax. (line 27)
25798 * statement separator, Meta: Meta-Chars. (line 8)
25799 * statement separator, MicroBlaze: MicroBlaze-Chars. (line 14)
25800 * statement separator, MIPS: MIPS-Chars. (line 14)
25801 * statement separator, MSP 430: MSP430-Chars. (line 14)
25802 * statement separator, NS32K: NS32K-Chars. (line 18)
25803 * statement separator, PJ: PJ-Chars. (line 14)
25804 * statement separator, PowerPC: PowerPC-Chars. (line 18)
25805 * statement separator, RL78: RL78-Chars. (line 14)
25806 * statement separator, RX: RX-Chars. (line 14)
25807 * statement separator, s390: s390 Characters. (line 13)
25808 * statement separator, SCORE: SCORE-Chars. (line 14)
25809 * statement separator, SH: SH-Chars. (line 8)
25810 * statement separator, SH64: SH64-Chars. (line 13)
25811 * statement separator, Sparc: Sparc-Chars. (line 14)
25812 * statement separator, TIC54X: TIC54X-Chars. (line 17)
25813 * statement separator, TIC6X: TIC6X Syntax. (line 13)
25814 * statement separator, V850: V850-Chars. (line 13)
25815 * statement separator, VAX: VAX-Chars. (line 14)
25816 * statement separator, XGATE: XGATE-Syntax. (line 26)
25817 * statement separator, XStormy16: XStormy16-Chars. (line 14)
25818 * statement separator, Z80: Z80-Chars. (line 13)
25819 * statement separator, Z8000: Z8000-Chars. (line 13)
25820 * statements, structure of: Statements. (line 6)
25821 * statistics, about assembly: statistics. (line 6)
25822 * stopping the assembly: Abort. (line 6)
25823 * string constants: Strings. (line 6)
25824 * string directive: String. (line 8)
25825 * string directive on HPPA: HPPA Directives. (line 137)
25826 * string directive, TIC54X: TIC54X-Directives. (line 208)
25827 * string literals: Ascii. (line 6)
25828 * string, copying to object file: String. (line 8)
25829 * string16 directive: String. (line 8)
25830 * string16, copying to object file: String. (line 8)
25831 * string32 directive: String. (line 8)
25832 * string32, copying to object file: String. (line 8)
25833 * string64 directive: String. (line 8)
25834 * string64, copying to object file: String. (line 8)
25835 * string8 directive: String. (line 8)
25836 * string8, copying to object file: String. (line 8)
25837 * struct directive: Struct. (line 6)
25838 * struct directive, TIC54X: TIC54X-Directives. (line 216)
25839 * structure debugging, COFF: Tag. (line 6)
25840 * sub-instruction ordering, D10V: D10V-Chars. (line 14)
25841 * sub-instruction ordering, D30V: D30V-Chars. (line 14)
25842 * sub-instructions, D10V: D10V-Subs. (line 6)
25843 * sub-instructions, D30V: D30V-Subs. (line 6)
25844 * subexpressions: Arguments. (line 24)
25845 * subsection directive: SubSection. (line 6)
25846 * subsym builtins, TIC54X: TIC54X-Macros. (line 16)
25847 * subtitles for listings: Sbttl. (line 6)
25848 * subtraction, permitted arguments: Infix Ops. (line 49)
25849 * summary of options: Overview. (line 6)
25850 * support: HPPA-Dependent. (line 6)
25851 * supporting files, including: Include. (line 6)
25852 * suppressing warnings: W. (line 11)
25853 * sval: Z8000 Directives. (line 33)
25854 * symbol attributes: Symbol Attributes. (line 6)
25855 * symbol attributes, a.out: a.out Symbols. (line 6)
25856 * symbol attributes, COFF: COFF Symbols. (line 6)
25857 * symbol attributes, SOM: SOM Symbols. (line 6)
25858 * symbol descriptor, COFF: Desc. (line 6)
25859 * symbol modifiers <1>: AVR-Modifiers. (line 12)
25860 * symbol modifiers <2>: LM32-Modifiers. (line 12)
25861 * symbol modifiers <3>: M68HC11-Modifiers. (line 12)
25862 * symbol modifiers: M32C-Modifiers. (line 11)
25863 * symbol modifiers, TILE-Gx: TILE-Gx Modifiers. (line 6)
25864 * symbol modifiers, TILEPro: TILEPro Modifiers. (line 6)
25865 * symbol names: Symbol Names. (line 6)
25866 * symbol names, $ in <1>: SH-Chars. (line 15)
25867 * symbol names, $ in <2>: Meta-Chars. (line 10)
25868 * symbol names, $ in <3>: D30V-Chars. (line 70)
25869 * symbol names, $ in <4>: SH64-Chars. (line 15)
25870 * symbol names, $ in: D10V-Chars. (line 53)
25871 * symbol names, local: Symbol Names. (line 27)
25872 * symbol names, temporary: Symbol Names. (line 40)
25873 * symbol storage class (COFF): Scl. (line 6)
25874 * symbol type: Symbol Type. (line 6)
25875 * symbol type, COFF: Type. (line 11)
25876 * symbol type, ELF: Type. (line 22)
25877 * symbol value: Symbol Value. (line 6)
25878 * symbol value, setting: Set. (line 6)
25879 * symbol values, assigning: Setting Symbols. (line 6)
25880 * symbol versioning: Symver. (line 6)
25881 * symbol, common: Comm. (line 6)
25882 * symbol, making visible to linker: Global. (line 6)
25883 * symbolic debuggers, information for: Stab. (line 6)
25884 * symbols: Symbols. (line 6)
25885 * Symbols in position-independent code, CRIS: CRIS-Pic. (line 6)
25886 * symbols with uppercase, VAX/VMS: VAX-Opts. (line 42)
25887 * symbols, assigning values to: Equ. (line 6)
25888 * Symbols, built-in, CRIS: CRIS-Symbols. (line 6)
25889 * Symbols, CRIS, built-in: CRIS-Symbols. (line 6)
25890 * symbols, local common: Lcomm. (line 6)
25891 * symver directive: Symver. (line 6)
25892 * syntax compatibility, i386: i386-Variations. (line 6)
25893 * syntax compatibility, x86-64: i386-Variations. (line 6)
25894 * syntax, AVR: AVR-Modifiers. (line 6)
25895 * syntax, Blackfin: Blackfin Syntax. (line 6)
25896 * syntax, D10V: D10V-Syntax. (line 6)
25897 * syntax, D30V: D30V-Syntax. (line 6)
25898 * syntax, LM32: LM32-Modifiers. (line 6)
25899 * syntax, M680x0: M68K-Syntax. (line 8)
25900 * syntax, M68HC11 <1>: M68HC11-Syntax. (line 6)
25901 * syntax, M68HC11: M68HC11-Modifiers. (line 6)
25902 * syntax, machine-independent: Syntax. (line 6)
25903 * syntax, RL78: RL78-Modifiers. (line 6)
25904 * syntax, RX: RX-Modifiers. (line 6)
25905 * syntax, SPARC: Sparc-Aligned-Data. (line 21)
25906 * syntax, TILE-Gx: TILE-Gx Syntax. (line 6)
25907 * syntax, TILEPro: TILEPro Syntax. (line 6)
25908 * syntax, XGATE: XGATE-Syntax. (line 6)
25909 * syntax, Xtensa assembler: Xtensa Syntax. (line 6)
25910 * sysproc directive, i960: Directives-i960. (line 37)
25911 * tab (\t): Strings. (line 27)
25912 * tab directive, TIC54X: TIC54X-Directives. (line 247)
25913 * tag directive: Tag. (line 6)
25914 * tag directive, TIC54X: TIC54X-Directives. (line 216)
25915 * TBM, i386: i386-TBM. (line 6)
25916 * TBM, x86-64: i386-TBM. (line 6)
25917 * tdaoff pseudo-op, V850: V850 Opcodes. (line 81)
25918 * temporary symbol names: Symbol Names. (line 40)
25919 * text and data sections, joining: R. (line 6)
25920 * text directive: Text. (line 6)
25921 * text section: Ld Sections. (line 9)
25922 * tfloat directive, i386: i386-Float. (line 14)
25923 * tfloat directive, x86-64: i386-Float. (line 14)
25924 * Thumb support: ARM-Dependent. (line 6)
25925 * TIC54X builtin math functions: TIC54X-Builtins. (line 6)
25926 * TIC54X line comment character: TIC54X-Chars. (line 6)
25927 * TIC54X line separator: TIC54X-Chars. (line 17)
25928 * TIC54X machine directives: TIC54X-Directives. (line 6)
25929 * TIC54X memory-mapped registers: TIC54X-MMRegs. (line 6)
25930 * TIC54X options: TIC54X-Opts. (line 6)
25931 * TIC54X subsym builtins: TIC54X-Macros. (line 16)
25932 * TIC54X support: TIC54X-Dependent. (line 6)
25933 * TIC54X-specific macros: TIC54X-Macros. (line 6)
25934 * TIC6X big-endian output: TIC6X Options. (line 46)
25935 * TIC6X line comment character: TIC6X Syntax. (line 6)
25936 * TIC6X line separator: TIC6X Syntax. (line 13)
25937 * TIC6X little-endian output: TIC6X Options. (line 46)
25938 * TIC6X machine directives: TIC6X Directives. (line 6)
25939 * TIC6X options: TIC6X Options. (line 6)
25940 * TIC6X support: TIC6X-Dependent. (line 6)
25941 * TILE-Gx machine directives: TILE-Gx Directives. (line 6)
25942 * TILE-Gx modifiers: TILE-Gx Modifiers. (line 6)
25943 * TILE-Gx opcode names: TILE-Gx Opcodes. (line 6)
25944 * TILE-Gx register names: TILE-Gx Registers. (line 6)
25945 * TILE-Gx support: TILE-Gx-Dependent. (line 6)
25946 * TILE-Gx syntax: TILE-Gx Syntax. (line 6)
25947 * TILEPro machine directives: TILEPro Directives. (line 6)
25948 * TILEPro modifiers: TILEPro Modifiers. (line 6)
25949 * TILEPro opcode names: TILEPro Opcodes. (line 6)
25950 * TILEPro register names: TILEPro Registers. (line 6)
25951 * TILEPro support: TILEPro-Dependent. (line 6)
25952 * TILEPro syntax: TILEPro Syntax. (line 6)
25953 * time, total for assembly: statistics. (line 6)
25954 * title directive: Title. (line 6)
25955 * tls_gd directive, Nios II: Nios II Relocations. (line 38)
25956 * tls_ie directive, Nios II: Nios II Relocations. (line 38)
25957 * tls_ldm directive, Nios II: Nios II Relocations. (line 38)
25958 * tls_ldo directive, Nios II: Nios II Relocations. (line 38)
25959 * tls_le directive, Nios II: Nios II Relocations. (line 38)
25960 * TMS320C6X support: TIC6X-Dependent. (line 6)
25961 * tp register, V850: V850-Regs. (line 20)
25962 * transform directive: Transform Directive. (line 6)
25963 * trusted compiler: f. (line 6)
25964 * turning preprocessing on and off: Preprocessing. (line 27)
25965 * type directive (COFF version): Type. (line 11)
25966 * type directive (ELF version): Type. (line 22)
25967 * type of a symbol: Symbol Type. (line 6)
25968 * ualong directive, SH: SH Directives. (line 6)
25969 * uaquad directive, SH: SH Directives. (line 6)
25970 * uaword directive, SH: SH Directives. (line 6)
25971 * ubyte directive, TIC54X: TIC54X-Directives. (line 36)
25972 * uchar directive, TIC54X: TIC54X-Directives. (line 36)
25973 * uhalf directive, TIC54X: TIC54X-Directives. (line 111)
25974 * uint directive, TIC54X: TIC54X-Directives. (line 111)
25975 * uleb128 directive: Uleb128. (line 6)
25976 * ulong directive, TIC54X: TIC54X-Directives. (line 135)
25977 * undefined section: Ld Sections. (line 36)
25978 * union directive, TIC54X: TIC54X-Directives. (line 250)
25979 * unsegm: Z8000 Directives. (line 14)
25980 * usect directive, TIC54X: TIC54X-Directives. (line 262)
25981 * ushort directive, TIC54X: TIC54X-Directives. (line 111)
25982 * uword directive, TIC54X: TIC54X-Directives. (line 111)
25983 * V850 command line options: V850 Options. (line 9)
25984 * V850 floating point (IEEE): V850 Floating Point. (line 6)
25985 * V850 line comment character: V850-Chars. (line 6)
25986 * V850 line separator: V850-Chars. (line 13)
25987 * V850 machine directives: V850 Directives. (line 6)
25988 * V850 opcodes: V850 Opcodes. (line 6)
25989 * V850 options (none): V850 Options. (line 6)
25990 * V850 register names: V850-Regs. (line 6)
25991 * V850 support: V850-Dependent. (line 6)
25992 * val directive: Val. (line 6)
25993 * value attribute, COFF: Val. (line 6)
25994 * value of a symbol: Symbol Value. (line 6)
25995 * var directive, TIC54X: TIC54X-Directives. (line 272)
25996 * VAX bitfields not supported: VAX-no. (line 6)
25997 * VAX branch improvement: VAX-branch. (line 6)
25998 * VAX command-line options ignored: VAX-Opts. (line 6)
25999 * VAX displacement sizing character: VAX-operands. (line 12)
26000 * VAX floating point: VAX-float. (line 6)
26001 * VAX immediate character: VAX-operands. (line 6)
26002 * VAX indirect character: VAX-operands. (line 9)
26003 * VAX line comment character: VAX-Chars. (line 6)
26004 * VAX line separator: VAX-Chars. (line 14)
26005 * VAX machine directives: VAX-directives. (line 6)
26006 * VAX opcode mnemonics: VAX-opcodes. (line 6)
26007 * VAX operand notation: VAX-operands. (line 6)
26008 * VAX register names: VAX-operands. (line 17)
26009 * VAX support: Vax-Dependent. (line 6)
26010 * Vax-11 C compatibility: VAX-Opts. (line 42)
26011 * VAX/VMS options: VAX-Opts. (line 42)
26012 * version directive: Version. (line 6)
26013 * version directive, TIC54X: TIC54X-Directives. (line 276)
26014 * version of assembler: v. (line 6)
26015 * versions of symbols: Symver. (line 6)
26016 * Virtualization instruction generation override: MIPS ASE Instruction Generation Overrides.
26018 * visibility <1>: Internal. (line 6)
26019 * visibility <2>: Protected. (line 6)
26020 * visibility: Hidden. (line 6)
26021 * VMS (VAX) options: VAX-Opts. (line 42)
26022 * vtable_entry directive: VTableEntry. (line 6)
26023 * vtable_inherit directive: VTableInherit. (line 6)
26024 * warning directive: Warning. (line 6)
26025 * warning for altered difference tables: K. (line 6)
26026 * warning messages: Errors. (line 6)
26027 * warnings, causing error: W. (line 16)
26028 * warnings, M32R: M32R-Warnings. (line 6)
26029 * warnings, suppressing: W. (line 11)
26030 * warnings, switching on: W. (line 19)
26031 * weak directive: Weak. (line 6)
26032 * weakref directive: Weakref. (line 6)
26033 * whitespace: Whitespace. (line 6)
26034 * whitespace, removed by preprocessor: Preprocessing. (line 7)
26035 * wide floating point directives, VAX: VAX-directives. (line 10)
26036 * width directive, TIC54X: TIC54X-Directives. (line 127)
26037 * Width of continuation lines of disassembly output: listing. (line 21)
26038 * Width of first line disassembly output: listing. (line 16)
26039 * Width of source line output: listing. (line 28)
26040 * wmsg directive, TIC54X: TIC54X-Directives. (line 77)
26041 * word directive: Word. (line 6)
26042 * word directive, ARC: ARC Directives. (line 171)
26043 * word directive, H8/300: H8/300 Directives. (line 6)
26044 * word directive, i386: i386-Float. (line 21)
26045 * word directive, Nios II: Nios II Directives. (line 13)
26046 * word directive, SPARC: Sparc-Directives. (line 51)
26047 * word directive, TIC54X: TIC54X-Directives. (line 111)
26048 * word directive, x86-64: i386-Float. (line 21)
26049 * writing patterns in memory: Fill. (line 6)
26050 * wval: Z8000 Directives. (line 24)
26051 * x86 machine directives: i386-Directives. (line 6)
26052 * x86-64 arch directive: i386-Arch. (line 6)
26053 * x86-64 att_syntax pseudo op: i386-Variations. (line 6)
26054 * x86-64 conversion instructions: i386-Mnemonics. (line 37)
26055 * x86-64 floating point: i386-Float. (line 6)
26056 * x86-64 immediate operands: i386-Variations. (line 15)
26057 * x86-64 instruction naming: i386-Mnemonics. (line 6)
26058 * x86-64 intel_syntax pseudo op: i386-Variations. (line 6)
26059 * x86-64 jump optimization: i386-Jumps. (line 6)
26060 * x86-64 jump, call, return: i386-Variations. (line 41)
26061 * x86-64 jump/call operands: i386-Variations. (line 15)
26062 * x86-64 memory references: i386-Memory. (line 6)
26063 * x86-64 options: i386-Options. (line 6)
26064 * x86-64 register operands: i386-Variations. (line 15)
26065 * x86-64 registers: i386-Regs. (line 6)
26066 * x86-64 sections: i386-Variations. (line 47)
26067 * x86-64 size suffixes: i386-Variations. (line 29)
26068 * x86-64 source, destination operands: i386-Variations. (line 22)
26069 * x86-64 support: i386-Dependent. (line 6)
26070 * x86-64 syntax compatibility: i386-Variations. (line 6)
26071 * xfloat directive, TIC54X: TIC54X-Directives. (line 64)
26072 * XGATE addressing modes: XGATE-Syntax. (line 29)
26073 * XGATE assembler directives: XGATE-Directives. (line 6)
26074 * XGATE floating point: XGATE-Float. (line 6)
26075 * XGATE line comment character: XGATE-Syntax. (line 16)
26076 * XGATE line separator: XGATE-Syntax. (line 26)
26077 * XGATE opcodes: XGATE-opcodes. (line 6)
26078 * XGATE options: XGATE-Opts. (line 6)
26079 * XGATE support: XGATE-Dependent. (line 6)
26080 * XGATE syntax: XGATE-Syntax. (line 6)
26081 * xlong directive, TIC54X: TIC54X-Directives. (line 135)
26082 * XStormy16 comment character: XStormy16-Chars. (line 11)
26083 * XStormy16 line comment character: XStormy16-Chars. (line 6)
26084 * XStormy16 line separator: XStormy16-Chars. (line 14)
26085 * XStormy16 machine directives: XStormy16 Directives.
26087 * XStormy16 pseudo-opcodes: XStormy16 Opcodes. (line 6)
26088 * XStormy16 support: XSTORMY16-Dependent. (line 6)
26089 * Xtensa architecture: Xtensa-Dependent. (line 6)
26090 * Xtensa assembler syntax: Xtensa Syntax. (line 6)
26091 * Xtensa directives: Xtensa Directives. (line 6)
26092 * Xtensa opcode names: Xtensa Opcodes. (line 6)
26093 * Xtensa register names: Xtensa Registers. (line 6)
26094 * xword directive, SPARC: Sparc-Directives. (line 55)
26095 * Z80 $: Z80-Chars. (line 15)
26096 * Z80 ': Z80-Chars. (line 20)
26097 * Z80 floating point: Z80 Floating Point. (line 6)
26098 * Z80 line comment character: Z80-Chars. (line 6)
26099 * Z80 line separator: Z80-Chars. (line 13)
26100 * Z80 options: Z80 Options. (line 6)
26101 * Z80 registers: Z80-Regs. (line 6)
26102 * Z80 support: Z80-Dependent. (line 6)
26103 * Z80 Syntax: Z80 Options. (line 47)
26104 * Z80, \: Z80-Chars. (line 18)
26105 * Z80, case sensitivity: Z80-Case. (line 6)
26106 * Z80-only directives: Z80 Directives. (line 9)
26107 * Z800 addressing modes: Z8000-Addressing. (line 6)
26108 * Z8000 directives: Z8000 Directives. (line 6)
26109 * Z8000 line comment character: Z8000-Chars. (line 6)
26110 * Z8000 line separator: Z8000-Chars. (line 13)
26111 * Z8000 opcode summary: Z8000 Opcodes. (line 6)
26112 * Z8000 options: Z8000 Options. (line 6)
26113 * Z8000 registers: Z8000-Regs. (line 6)
26114 * Z8000 support: Z8000-Dependent. (line 6)
26115 * zdaoff pseudo-op, V850: V850 Opcodes. (line 99)
26116 * zero register, V850: V850-Regs. (line 7)
26117 * zero-terminated strings: Asciz. (line 6)
26123 Node: Overview
\7f1725
26124 Node: Manual
\7f36226
26125 Node: GNU Assembler
\7f37170
26126 Node: Object Formats
\7f38341
26127 Node: Command Line
\7f38793
26128 Node: Input Files
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26129 Node: Object
\7f41861
26130 Node: Errors
\7f42757
26131 Node: Invoking
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26133 Node: alternate
\7f47818
26139 Node: listing
\7f50318
26144 Node: statistics
\7f58289
26145 Node: traditional-format
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26149 Node: Syntax
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26150 Node: Preprocessing
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26151 Node: Whitespace
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26152 Node: Comments
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26153 Node: Symbol Intro
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26154 Node: Statements
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26155 Node: Constants
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26156 Node: Characters
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26157 Node: Strings
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26158 Node: Chars
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26159 Node: Numbers
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26160 Node: Integers
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26161 Node: Bignums
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26162 Node: Flonums
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26163 Node: Sections
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26164 Node: Secs Background
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26165 Node: Ld Sections
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26166 Node: As Sections
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26167 Node: Sub-Sections
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26169 Node: Symbols
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26170 Node: Labels
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26171 Node: Setting Symbols
\7f89688
26172 Node: Symbol Names
\7f90242
26174 Node: Symbol Attributes
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26175 Node: Symbol Value
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26176 Node: Symbol Type
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26177 Node: a.out Symbols
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26178 Node: Symbol Desc
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26179 Node: Symbol Other
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26180 Node: COFF Symbols
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26181 Node: SOM Symbols
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26182 Node: Expressions
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26183 Node: Empty Exprs
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26184 Node: Integer Exprs
\7f101087
26185 Node: Arguments
\7f101482
26186 Node: Operators
\7f102588
26187 Node: Prefix Ops
\7f102923
26188 Node: Infix Ops
\7f103251
26189 Node: Pseudo Ops
\7f105641
26190 Node: Abort
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26191 Node: ABORT (COFF)
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26192 Node: Align
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26193 Node: Altmacro
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26194 Node: Ascii
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26195 Node: Asciz
\7f115805
26196 Node: Balign
\7f116050
26197 Node: Bundle directives
\7f117926
26198 Node: Byte
\7f120855
26199 Node: CFI directives
\7f121116
26200 Node: Comm
\7f126745
26201 Ref: Comm-Footnote-1
\7f128346
26202 Node: Data
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26204 Node: Desc
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26206 Node: Double
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26207 Node: Eject
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26208 Node: Else
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26209 Node: Elseif
\7f130827
26211 Node: Endef
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26212 Node: Endfunc
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26213 Node: Endif
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26215 Node: Equiv
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26218 Node: Error
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26219 Node: Exitm
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26220 Node: Extern
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26221 Node: Fail
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26222 Node: File
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26223 Node: Fill
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26224 Node: Float
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26225 Node: Func
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26226 Node: Global
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26227 Node: Gnu_attribute
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26228 Node: Hidden
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26229 Node: hword
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26230 Node: Ident
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26232 Node: Incbin
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26233 Node: Include
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26235 Node: Internal
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26237 Node: Irpc
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26238 Node: Lcomm
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26239 Node: Lflags
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26240 Node: Line
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26241 Node: Linkonce
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26242 Node: List
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26245 Node: Loc_mark_labels
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26246 Node: Local
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26247 Node: Long
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26248 Node: Macro
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26250 Node: Noaltmacro
\7f160601
26251 Node: Nolist
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26252 Node: Octa
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26253 Node: Offset
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26255 Node: P2align
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26256 Node: PopSection
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26257 Node: Previous
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26258 Node: Print
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26259 Node: Protected
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26260 Node: Psize
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26261 Node: Purgem
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26262 Node: PushSection
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26263 Node: Quad
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26264 Node: Reloc
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26265 Node: Rept
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26266 Node: Sbttl
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26268 Node: Section
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26270 Node: Short
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26271 Node: Single
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26272 Node: Size
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26273 Node: Skip
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26274 Node: Sleb128
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26275 Node: Space
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26276 Node: Stab
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26277 Node: String
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26278 Node: Struct
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26279 Node: SubSection
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26280 Node: Symver
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26282 Node: Text
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26283 Node: Title
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26284 Node: Type
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26285 Node: Uleb128
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26287 Node: Version
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26288 Node: VTableEntry
\7f192144
26289 Node: VTableInherit
\7f192434
26290 Node: Warning
\7f192884
26291 Node: Weak
\7f193118
26292 Node: Weakref
\7f193787
26293 Node: Word
\7f194752
26294 Node: Deprecated
\7f196598
26295 Node: Object Attributes
\7f196833
26296 Node: GNU Object Attributes
\7f198553
26297 Node: Defining New Object Attributes
\7f201780
26298 Node: Machine Dependencies
\7f202577
26299 Node: AArch64-Dependent
\7f206470
26300 Node: AArch64 Options
\7f206952
26301 Node: AArch64 Extensions
\7f209419
26302 Node: AArch64 Syntax
\7f210887
26303 Node: AArch64-Chars
\7f211187
26304 Node: AArch64-Regs
\7f211673
26305 Node: AArch64-Relocations
\7f211967
26306 Node: AArch64 Floating Point
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26307 Node: AArch64 Directives
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26308 Node: AArch64 Opcodes
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26309 Node: AArch64 Mapping Symbols
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26310 Node: Alpha-Dependent
\7f215871
26311 Node: Alpha Notes
\7f216311
26312 Node: Alpha Options
\7f216592
26313 Node: Alpha Syntax
\7f219067
26314 Node: Alpha-Chars
\7f219536
26315 Node: Alpha-Regs
\7f219948
26316 Node: Alpha-Relocs
\7f220335
26317 Node: Alpha Floating Point
\7f226593
26318 Node: Alpha Directives
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26319 Node: Alpha Opcodes
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26320 Node: ARC-Dependent
\7f232633
26321 Node: ARC Options
\7f233016
26322 Node: ARC Syntax
\7f234085
26323 Node: ARC-Chars
\7f234317
26324 Node: ARC-Regs
\7f234798
26325 Node: ARC Floating Point
\7f234922
26326 Node: ARC Directives
\7f235233
26327 Node: ARC Opcodes
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26328 Node: ARM-Dependent
\7f241424
26329 Node: ARM Options
\7f241889
26330 Node: ARM Syntax
\7f250813
26331 Node: ARM-Instruction-Set
\7f251181
26332 Node: ARM-Chars
\7f252401
26333 Node: ARM-Regs
\7f253112
26334 Node: ARM-Relocations
\7f253321
26335 Node: ARM-Neon-Alignment
\7f254455
26336 Node: ARM Floating Point
\7f254919
26337 Node: ARM Directives
\7f255118
26338 Ref: arm_fnend
\7f259566
26339 Ref: arm_fnstart
\7f259890
26340 Ref: arm_pad
\7f262298
26341 Ref: arm_save
\7f262900
26342 Ref: arm_setfp
\7f263601
26343 Node: ARM Opcodes
\7f266893
26344 Node: ARM Mapping Symbols
\7f268981
26345 Node: ARM Unwinding Tutorial
\7f269791
26346 Node: AVR-Dependent
\7f275993
26347 Node: AVR Options
\7f276283
26348 Node: AVR Syntax
\7f282004
26349 Node: AVR-Chars
\7f282291
26350 Node: AVR-Regs
\7f282850
26351 Node: AVR-Modifiers
\7f283429
26352 Node: AVR Opcodes
\7f285489
26353 Node: Blackfin-Dependent
\7f290735
26354 Node: Blackfin Options
\7f291047
26355 Node: Blackfin Syntax
\7f292021
26356 Node: Blackfin Directives
\7f298228
26357 Node: CR16-Dependent
\7f298974
26358 Node: CR16 Operand Qualifiers
\7f299274
26359 Node: CR16 Syntax
\7f302003
26360 Node: CR16-Chars
\7f302189
26361 Node: CRIS-Dependent
\7f302726
26362 Node: CRIS-Opts
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26363 Ref: march-option
\7f304758
26364 Node: CRIS-Expand
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26365 Node: CRIS-Symbols
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26366 Node: CRIS-Syntax
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26367 Node: CRIS-Chars
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26368 Node: CRIS-Pic
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26369 Ref: crispic
\7f310010
26370 Node: CRIS-Regs
\7f313550
26371 Node: CRIS-Pseudos
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26372 Ref: crisnous
\7f314743
26373 Node: D10V-Dependent
\7f316025
26374 Node: D10V-Opts
\7f316376
26375 Node: D10V-Syntax
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26376 Node: D10V-Size
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26377 Node: D10V-Subs
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26378 Node: D10V-Chars
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26379 Node: D10V-Regs
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26380 Node: D10V-Addressing
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26381 Node: D10V-Word
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26382 Node: D10V-Float
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26383 Node: D10V-Opcodes
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26384 Node: D30V-Dependent
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26385 Node: D30V-Opts
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26386 Node: D30V-Syntax
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26387 Node: D30V-Size
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26388 Node: D30V-Subs
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26389 Node: D30V-Chars
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26390 Node: D30V-Guarded
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26391 Node: D30V-Regs
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26392 Node: D30V-Addressing
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26393 Node: D30V-Float
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26394 Node: D30V-Opcodes
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26395 Node: Epiphany-Dependent
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26396 Node: Epiphany Options
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26397 Node: Epiphany Syntax
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26398 Node: Epiphany-Chars
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26399 Node: H8/300-Dependent
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26400 Node: H8/300 Options
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26401 Node: H8/300 Syntax
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26402 Node: H8/300-Chars
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26403 Node: H8/300-Regs
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26404 Node: H8/300-Addressing
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26405 Node: H8/300 Floating Point
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26406 Node: H8/300 Directives
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26407 Node: H8/300 Opcodes
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26408 Node: HPPA-Dependent
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26409 Node: HPPA Notes
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26410 Node: HPPA Options
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26411 Node: HPPA Syntax
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26412 Node: HPPA Floating Point
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26413 Node: HPPA Directives
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26414 Node: HPPA Opcodes
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26415 Node: ESA/390-Dependent
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26416 Node: ESA/390 Notes
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26417 Node: ESA/390 Options
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26418 Node: ESA/390 Syntax
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26419 Node: ESA/390 Floating Point
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26420 Node: ESA/390 Directives
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26421 Node: ESA/390 Opcodes
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26422 Node: i386-Dependent
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26423 Node: i386-Options
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26424 Node: i386-Directives
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26425 Node: i386-Syntax
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26426 Node: i386-Variations
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26427 Node: i386-Chars
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26428 Node: i386-Mnemonics
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26429 Node: i386-Regs
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26430 Node: i386-Prefixes
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26431 Node: i386-Memory
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26432 Node: i386-Jumps
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26433 Node: i386-Float
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26434 Node: i386-SIMD
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26435 Node: i386-LWP
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26436 Node: i386-BMI
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26437 Node: i386-TBM
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26438 Node: i386-16bit
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26439 Node: i386-Bugs
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26440 Node: i386-Arch
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26441 Node: i386-Notes
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26442 Node: i860-Dependent
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26443 Node: Notes-i860
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26444 Node: Options-i860
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26445 Node: Directives-i860
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26446 Node: Opcodes for i860
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26447 Node: Syntax of i860
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26448 Node: i860-Chars
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26449 Node: i960-Dependent
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26450 Node: Options-i960
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26451 Node: Floating Point-i960
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26452 Node: Directives-i960
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26453 Node: Opcodes for i960
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26454 Node: callj-i960
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26455 Node: Compare-and-branch-i960
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26456 Node: Syntax of i960
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26457 Node: i960-Chars
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26458 Node: IA-64-Dependent
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26459 Node: IA-64 Options
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26460 Node: IA-64 Syntax
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26461 Node: IA-64-Chars
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26462 Node: IA-64-Regs
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26463 Node: IA-64-Bits
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26464 Node: IA-64-Relocs
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26465 Node: IA-64 Opcodes
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26466 Node: IP2K-Dependent
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26467 Node: IP2K-Opts
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26468 Node: IP2K-Syntax
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26469 Node: IP2K-Chars
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26470 Node: LM32-Dependent
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26471 Node: LM32 Options
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26472 Node: LM32 Syntax
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26473 Node: LM32-Regs
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26474 Node: LM32-Modifiers
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26475 Node: LM32-Chars
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26476 Node: LM32 Opcodes
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26477 Node: M32C-Dependent
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26478 Node: M32C-Opts
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26479 Node: M32C-Syntax
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26480 Node: M32C-Modifiers
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26481 Node: M32C-Chars
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26482 Node: M32R-Dependent
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26483 Node: M32R-Opts
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26484 Node: M32R-Directives
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26485 Node: M32R-Warnings
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26486 Node: M68K-Dependent
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26487 Node: M68K-Opts
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26488 Node: M68K-Syntax
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26489 Node: M68K-Moto-Syntax
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26490 Node: M68K-Float
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26491 Node: M68K-Directives
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26492 Node: M68K-opcodes
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26493 Node: M68K-Branch
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26494 Node: M68K-Chars
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26495 Node: M68HC11-Dependent
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26496 Node: M68HC11-Opts
\7f467989
26497 Node: M68HC11-Syntax
\7f472294
26498 Node: M68HC11-Modifiers
\7f475085
26499 Node: M68HC11-Directives
\7f476913
26500 Node: M68HC11-Float
\7f478289
26501 Node: M68HC11-opcodes
\7f478817
26502 Node: M68HC11-Branch
\7f478999
26503 Node: Meta-Dependent
\7f481448
26504 Node: Meta Options
\7f481733
26505 Node: Meta Syntax
\7f482395
26506 Node: Meta-Chars
\7f482607
26507 Node: Meta-Regs
\7f482907
26508 Node: MicroBlaze-Dependent
\7f483183
26509 Node: MicroBlaze Directives
\7f483872
26510 Node: MicroBlaze Syntax
\7f485255
26511 Node: MicroBlaze-Chars
\7f485487
26512 Node: MIPS-Dependent
\7f486039
26513 Node: MIPS Options
\7f487476
26514 Node: MIPS Macros
\7f502130
26515 Ref: MIPS Macros-Footnote-1
\7f504844
26516 Node: MIPS Symbol Sizes
\7f504987
26517 Node: MIPS Small Data
\7f506659
26518 Node: MIPS ISA
\7f508822
26519 Node: MIPS assembly options
\7f510607
26520 Node: MIPS autoextend
\7f511740
26521 Node: MIPS insn
\7f512474
26522 Node: MIPS FP ABIs
\7f513754
26523 Node: MIPS FP ABI History
\7f514206
26524 Node: MIPS FP ABI Variants
\7f514966
26525 Node: MIPS FP ABI Selection
\7f517520
26526 Node: MIPS FP ABI Compatibility
\7f518584
26527 Node: MIPS NaN Encodings
\7f519394
26528 Node: MIPS Option Stack
\7f521357
26529 Node: MIPS ASE Instruction Generation Overrides
\7f522142
26530 Node: MIPS Floating-Point
\7f524856
26531 Node: MIPS Syntax
\7f525762
26532 Node: MIPS-Chars
\7f526024
26533 Node: MMIX-Dependent
\7f526566
26534 Node: MMIX-Opts
\7f526946
26535 Node: MMIX-Expand
\7f530550
26536 Node: MMIX-Syntax
\7f531865
26537 Ref: mmixsite
\7f532222
26538 Node: MMIX-Chars
\7f533063
26539 Node: MMIX-Symbols
\7f533937
26540 Node: MMIX-Regs
\7f536005
26541 Node: MMIX-Pseudos
\7f537030
26542 Ref: MMIX-loc
\7f537171
26543 Ref: MMIX-local
\7f538251
26544 Ref: MMIX-is
\7f538783
26545 Ref: MMIX-greg
\7f539054
26546 Ref: GREG-base
\7f539973
26547 Ref: MMIX-byte
\7f541290
26548 Ref: MMIX-constants
\7f541761
26549 Ref: MMIX-prefix
\7f542407
26550 Ref: MMIX-spec
\7f542781
26551 Node: MMIX-mmixal
\7f543115
26552 Node: MSP430-Dependent
\7f546613
26553 Node: MSP430 Options
\7f547082
26554 Node: MSP430 Syntax
\7f549045
26555 Node: MSP430-Macros
\7f549361
26556 Node: MSP430-Chars
\7f550092
26557 Node: MSP430-Regs
\7f550807
26558 Node: MSP430-Ext
\7f551367
26559 Node: MSP430 Floating Point
\7f553188
26560 Node: MSP430 Directives
\7f553412
26561 Node: MSP430 Opcodes
\7f554733
26562 Node: MSP430 Profiling Capability
\7f555128
26563 Node: NDS32-Dependent
\7f557457
26564 Node: NDS32 Options
\7f558069
26565 Node: NDS32 Syntax
\7f559970
26566 Node: NDS32-Chars
\7f560238
26567 Node: NDS32-Regs
\7f560705
26568 Node: NDS32-Ops
\7f561559
26569 Node: NiosII-Dependent
\7f565154
26570 Node: Nios II Options
\7f565573
26571 Node: Nios II Syntax
\7f566494
26572 Node: Nios II Chars
\7f566700
26573 Node: Nios II Relocations
\7f566891
26574 Node: Nios II Directives
\7f568463
26575 Node: Nios II Opcodes
\7f570026
26576 Node: NS32K-Dependent
\7f570301
26577 Node: NS32K Syntax
\7f570524
26578 Node: NS32K-Chars
\7f570673
26579 Node: PDP-11-Dependent
\7f571413
26580 Node: PDP-11-Options
\7f571802
26581 Node: PDP-11-Pseudos
\7f576873
26582 Node: PDP-11-Syntax
\7f577218
26583 Node: PDP-11-Mnemonics
\7f578050
26584 Node: PDP-11-Synthetic
\7f578352
26585 Node: PJ-Dependent
\7f578570
26586 Node: PJ Options
\7f578833
26587 Node: PJ Syntax
\7f579128
26588 Node: PJ-Chars
\7f579293
26589 Node: PPC-Dependent
\7f579842
26590 Node: PowerPC-Opts
\7f580175
26591 Node: PowerPC-Pseudo
\7f583671
26592 Node: PowerPC-Syntax
\7f584293
26593 Node: PowerPC-Chars
\7f584483
26594 Node: RL78-Dependent
\7f585234
26595 Node: RL78-Opts
\7f585632
26596 Node: RL78-Modifiers
\7f586171
26597 Node: RL78-Directives
\7f586947
26598 Node: RL78-Syntax
\7f587552
26599 Node: RL78-Chars
\7f587748
26600 Node: RX-Dependent
\7f588304
26601 Node: RX-Opts
\7f588735
26602 Node: RX-Modifiers
\7f592142
26603 Node: RX-Directives
\7f593246
26604 Node: RX-Float
\7f593986
26605 Node: RX-Syntax
\7f594627
26606 Node: RX-Chars
\7f594806
26607 Node: S/390-Dependent
\7f595358
26608 Node: s390 Options
\7f596074
26609 Node: s390 Characters
\7f597620
26610 Node: s390 Syntax
\7f598141
26611 Node: s390 Register
\7f599042
26612 Node: s390 Mnemonics
\7f599855
26613 Node: s390 Operands
\7f602875
26614 Node: s390 Formats
\7f605494
26615 Node: s390 Aliases
\7f613365
26616 Node: s390 Operand Modifier
\7f617262
26617 Node: s390 Instruction Marker
\7f621063
26618 Node: s390 Literal Pool Entries
\7f622079
26619 Node: s390 Directives
\7f624002
26620 Node: s390 Floating Point
\7f629058
26621 Node: SCORE-Dependent
\7f629504
26622 Node: SCORE-Opts
\7f629809
26623 Node: SCORE-Pseudo
\7f631097
26624 Node: SCORE-Syntax
\7f633174
26625 Node: SCORE-Chars
\7f633356
26626 Node: SH-Dependent
\7f633914
26627 Node: SH Options
\7f634325
26628 Node: SH Syntax
\7f635380
26629 Node: SH-Chars
\7f635653
26630 Node: SH-Regs
\7f636196
26631 Node: SH-Addressing
\7f636810
26632 Node: SH Floating Point
\7f637719
26633 Node: SH Directives
\7f638813
26634 Node: SH Opcodes
\7f639214
26635 Node: SH64-Dependent
\7f643536
26636 Node: SH64 Options
\7f643899
26637 Node: SH64 Syntax
\7f645696
26638 Node: SH64-Chars
\7f645979
26639 Node: SH64-Regs
\7f646528
26640 Node: SH64-Addressing
\7f647624
26641 Node: SH64 Directives
\7f648807
26642 Node: SH64 Opcodes
\7f649792
26643 Node: Sparc-Dependent
\7f650508
26644 Node: Sparc-Opts
\7f650920
26645 Node: Sparc-Aligned-Data
\7f655934
26646 Node: Sparc-Syntax
\7f656766
26647 Node: Sparc-Chars
\7f657340
26648 Node: Sparc-Regs
\7f657903
26649 Node: Sparc-Constants
\7f663204
26650 Node: Sparc-Relocs
\7f667964
26651 Node: Sparc-Size-Translations
\7f673100
26652 Node: Sparc-Float
\7f674749
26653 Node: Sparc-Directives
\7f674944
26654 Node: TIC54X-Dependent
\7f676904
26655 Node: TIC54X-Opts
\7f677667
26656 Node: TIC54X-Block
\7f678710
26657 Node: TIC54X-Env
\7f679070
26658 Node: TIC54X-Constants
\7f679418
26659 Node: TIC54X-Subsyms
\7f679820
26660 Node: TIC54X-Locals
\7f681729
26661 Node: TIC54X-Builtins
\7f682473
26662 Node: TIC54X-Ext
\7f684944
26663 Node: TIC54X-Directives
\7f685515
26664 Node: TIC54X-Macros
\7f696416
26665 Node: TIC54X-MMRegs
\7f698527
26666 Node: TIC54X-Syntax
\7f698765
26667 Node: TIC54X-Chars
\7f698955
26668 Node: TIC6X-Dependent
\7f699646
26669 Node: TIC6X Options
\7f699949
26670 Node: TIC6X Syntax
\7f701950
26671 Node: TIC6X Directives
\7f703052
26672 Node: TILE-Gx-Dependent
\7f705337
26673 Node: TILE-Gx Options
\7f705647
26674 Node: TILE-Gx Syntax
\7f705997
26675 Node: TILE-Gx Opcodes
\7f708231
26676 Node: TILE-Gx Registers
\7f708519
26677 Node: TILE-Gx Modifiers
\7f709291
26678 Node: TILE-Gx Directives
\7f714263
26679 Node: TILEPro-Dependent
\7f715167
26680 Node: TILEPro Options
\7f715476
26681 Node: TILEPro Syntax
\7f715660
26682 Node: TILEPro Opcodes
\7f717894
26683 Node: TILEPro Registers
\7f718185
26684 Node: TILEPro Modifiers
\7f718955
26685 Node: TILEPro Directives
\7f723720
26686 Node: Z80-Dependent
\7f724624
26687 Node: Z80 Options
\7f725012
26688 Node: Z80 Syntax
\7f726435
26689 Node: Z80-Chars
\7f727107
26690 Node: Z80-Regs
\7f727957
26691 Node: Z80-Case
\7f728309
26692 Node: Z80 Floating Point
\7f728754
26693 Node: Z80 Directives
\7f728948
26694 Node: Z80 Opcodes
\7f730573
26695 Node: Z8000-Dependent
\7f731917
26696 Node: Z8000 Options
\7f732878
26697 Node: Z8000 Syntax
\7f733095
26698 Node: Z8000-Chars
\7f733385
26699 Node: Z8000-Regs
\7f733867
26700 Node: Z8000-Addressing
\7f734657
26701 Node: Z8000 Directives
\7f735774
26702 Node: Z8000 Opcodes
\7f737383
26703 Node: Vax-Dependent
\7f747325
26704 Node: VAX-Opts
\7f747885
26705 Node: VAX-float
\7f751620
26706 Node: VAX-directives
\7f752252
26707 Node: VAX-opcodes
\7f753113
26708 Node: VAX-branch
\7f753502
26709 Node: VAX-operands
\7f756009
26710 Node: VAX-no
\7f756772
26711 Node: VAX-Syntax
\7f757028
26712 Node: VAX-Chars
\7f757194
26713 Node: V850-Dependent
\7f757748
26714 Node: V850 Options
\7f758146
26715 Node: V850 Syntax
\7f761792
26716 Node: V850-Chars
\7f762032
26717 Node: V850-Regs
\7f762576
26718 Node: V850 Floating Point
\7f764144
26719 Node: V850 Directives
\7f764350
26720 Node: V850 Opcodes
\7f766417
26721 Node: XGATE-Dependent
\7f772309
26722 Node: XGATE-Opts
\7f772729
26723 Node: XGATE-Syntax
\7f773720
26724 Node: XGATE-Directives
\7f775799
26725 Node: XGATE-Float
\7f776038
26726 Node: XGATE-opcodes
\7f776535
26727 Node: XSTORMY16-Dependent
\7f776647
26728 Node: XStormy16 Syntax
\7f776993
26729 Node: XStormy16-Chars
\7f777183
26730 Node: XStormy16 Directives
\7f777796
26731 Node: XStormy16 Opcodes
\7f778451
26732 Node: Xtensa-Dependent
\7f779507
26733 Node: Xtensa Options
\7f780241
26734 Node: Xtensa Syntax
\7f783395
26735 Node: Xtensa Opcodes
\7f785539
26736 Node: Xtensa Registers
\7f787333
26737 Node: Xtensa Optimizations
\7f787966
26738 Node: Density Instructions
\7f788418
26739 Node: Xtensa Automatic Alignment
\7f789520
26740 Node: Xtensa Relaxation
\7f791967
26741 Node: Xtensa Branch Relaxation
\7f792932
26742 Node: Xtensa Call Relaxation
\7f794304
26743 Node: Xtensa Jump Relaxation
\7f796085
26744 Node: Xtensa Immediate Relaxation
\7f798185
26745 Node: Xtensa Directives
\7f800759
26746 Node: Schedule Directive
\7f802468
26747 Node: Longcalls Directive
\7f802808
26748 Node: Transform Directive
\7f803352
26749 Node: Literal Directive
\7f804094
26750 Ref: Literal Directive-Footnote-1
\7f807633
26751 Node: Literal Position Directive
\7f807775
26752 Node: Literal Prefix Directive
\7f809474
26753 Node: Absolute Literals Directive
\7f810372
26754 Node: Reporting Bugs
\7f811679
26755 Node: Bug Criteria
\7f812405
26756 Node: Bug Reporting
\7f813172
26757 Node: Acknowledgements
\7f819821
26758 Ref: Acknowledgements-Footnote-1
\7f824786
26759 Node: GNU Free Documentation License
\7f824812
26760 Node: AS Index
\7f849981
projects / platform / upstream / binutils.git / blob