Fix continue target in graphics block order tests
authorDavid Neto <dneto@google.com>
Fri, 29 Jul 2016 20:35:12 +0000 (16:35 -0400)
committerPyry Haulos <phaulos@google.com>
Tue, 2 Aug 2016 15:32:54 +0000 (08:32 -0700)
Fixes validation of shaders in:
    dEQP-VK.spirv_assembly.instruction.graphics.selection_block_order.out_of_order_vert
    dEQP-VK.spirv_assembly.instruction.graphics.selection_block_order.out_of_order_tessc
    dEQP-VK.spirv_assembly.instruction.graphics.selection_block_order.out_of_order_tesse
    dEQP-VK.spirv_assembly.instruction.graphics.selection_block_order.out_of_order_geom
    dEQP-VK.spirv_assembly.instruction.graphics.selection_block_order.out_of_order_frag
    dEQP-VK.spirv_assembly.instruction.graphics.switch_block_order.out_of_order_vert
    dEQP-VK.spirv_assembly.instruction.graphics.switch_block_order.out_of_order_tessc
    dEQP-VK.spirv_assembly.instruction.graphics.switch_block_order.out_of_order_tesse
    dEQP-VK.spirv_assembly.instruction.graphics.switch_block_order.out_of_order_geom
    dEQP-VK.spirv_assembly.instruction.graphics.switch_block_order.out_of_order_frag
    dEQP-VK.spirv_assembly.instruction.graphics.opphi.out_of_order_vert
    dEQP-VK.spirv_assembly.instruction.graphics.opphi.out_of_order_tessc
    dEQP-VK.spirv_assembly.instruction.graphics.opphi.out_of_order_tesse
    dEQP-VK.spirv_assembly.instruction.graphics.opphi.out_of_order_geom
    dEQP-VK.spirv_assembly.instruction.graphics.opphi.out_of_order_frag

Fixes https://gitlab.khronos.org/vulkan/vulkancts/issues/443

external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsmInstructionTests.cpp

index bd5b18d..9cc43ca 100644 (file)
@@ -6127,7 +6127,7 @@ tcu::TestCaseGroup* createSelectionBlockOrderTests(tcu::TestContext& testCtx)
                "%loop      = OpLabel\n"
                "%ival      = OpLoad %i32 %iptr\n"
                "%lt_4      = OpSLessThan %bool %ival %c_i32_4\n"
-               "             OpLoopMerge %exit %loop None\n"
+               "             OpLoopMerge %exit %if_entry None\n"
                "             OpBranchConditional %lt_4 %if_entry %exit\n"
 
                // Merge block for loop.
@@ -6219,7 +6219,7 @@ tcu::TestCaseGroup* createSwitchBlockOrderTests(tcu::TestContext& testCtx)
                "%loop      = OpLabel\n"
                "%ival      = OpLoad %i32 %iptr\n"
                "%lt_4      = OpSLessThan %bool %ival %c_i32_4\n"
-               "             OpLoopMerge %exit %loop None\n"
+               "             OpLoopMerge %exit %switch_exit None\n"
                "             OpBranchConditional %lt_4 %switch_entry %exit\n"
 
                // Merge block for loop.
@@ -6649,7 +6649,7 @@ tcu::TestCaseGroup* createOpPhiTests(tcu::TestContext& testCtx)
                "%loop      = OpLabel\n"
                "%ival      = OpLoad %i32 %iptr\n"
                "%lt_4      = OpSLessThan %bool %ival %c_i32_4\n"
-               "             OpLoopMerge %exit %loop None\n"
+               "             OpLoopMerge %exit %phi None\n"
                "             OpBranchConditional %lt_4 %entry %exit\n"
 
                "%entry     = OpLabel\n"