Convert CONFIG_SYS_FSL_QMAN_V3 et al to Kconfig

This converts the following to Kconfig:
   CONFIG_FSL_NGPIXIS
   CONFIG_SYS_FSL_QMAN_V3
   CONFIG_SYS_FSL_RAID_ENGINE
   CONFIG_SYS_FSL_RMU
   CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
   CONFIG_SYS_FSL_SRIO_LIODN
   CONFIG_SYS_FSL_TBCLK_DIV
   CONFIG_SYS_FSL_USB1_PHY_ENABLE
   CONFIG_SYS_FSL_USB2_PHY_ENABLE
   CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
   CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/README b/README
index 4ef9e8c..a6c3061 100644 (file)
--- a/README
+++ b/README
@@ -294,12 +294,6 @@ The following options need to be configured:
                the "64" category of the Power ISA). This is necessary for ePAPR
                compliance, among other possible reasons.
 
                the "64" category of the Power ISA). This is necessary for ePAPR
                compliance, among other possible reasons.
 

-               CONFIG_SYS_FSL_TBCLK_DIV
-
-               Defines the core time base clock divider ratio compared to the
-               system clock.  On most PQ3 devices this is 8, on newer QorIQ
-               devices it can be 16 or 32.  The ratio varies from SoC to Soc.
-

                CONFIG_SYS_FSL_ERRATUM_A004510
 
                Enables a workaround for erratum A004510.  If set,
                CONFIG_SYS_FSL_ERRATUM_A004510
 
                Enables a workaround for erratum A004510.  If set,

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 91a5863..8a7bbb4 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -85,6 +85,7 @@ config ARCH_LS1043A
        select SYS_FSL_ERRATUM_A010539
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_DDR4
        select SYS_FSL_ERRATUM_A010539
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_DDR4

+       select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN

        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_I2C_MXC
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_I2C_MXC


@@ -123,6 +124,7 @@ config ARCH_LS1046A
        select SYS_FSL_ERRATUM_A010539
        select SYS_FSL_HAS_DDR4
        select SYS_FSL_SRDS_2
        select SYS_FSL_ERRATUM_A010539
        select SYS_FSL_HAS_DDR4
        select SYS_FSL_SRDS_2

+       select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN

        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_I2C_MXC
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_I2C_MXC

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 1850008..5824778 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -209,7 +209,6 @@
 
 /* SoC related */
 #ifdef CONFIG_ARCH_LS1043A
 
 /* SoC related */
 #ifdef CONFIG_ARCH_LS1043A

-#define CONFIG_SYS_FSL_QMAN_V3

 #define CONFIG_SYS_NUM_FMAN                    1
 #define CONFIG_SYS_NUM_FM1_DTSEC               7
 #define CONFIG_SYS_NUM_FM1_10GEC               1
 #define CONFIG_SYS_NUM_FMAN                    1
 #define CONFIG_SYS_NUM_FM1_DTSEC               7
 #define CONFIG_SYS_NUM_FM1_10GEC               1


@@ -256,7 +255,6 @@
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
 #elif defined(CONFIG_ARCH_LS1046A)
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
 #elif defined(CONFIG_ARCH_LS1046A)

-#define CONFIG_SYS_FSL_QMAN_V3

 #define CONFIG_SYS_NUM_FMAN                    1
 #define CONFIG_SYS_NUM_FM1_DTSEC               8
 #define CONFIG_SYS_NUM_FM1_10GEC               2
 #define CONFIG_SYS_NUM_FMAN                    1
 #define CONFIG_SYS_NUM_FM1_DTSEC               8
 #define CONFIG_SYS_NUM_FM1_10GEC               2

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index d01e69b..81f7991 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -78,6 +78,7 @@ config TARGET_P3041DS
        select PHYS_64BIT
        select ARCH_P3041
        select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select PHYS_64BIT
        select ARCH_P3041
        select BOARD_LATE_INIT if CHAIN_OF_TRUST

+       select FSL_NGPIXIS

        imply CMD_SATA
        imply PANIC_HANG
 
        imply CMD_SATA
        imply PANIC_HANG
 


@@ -86,6 +87,7 @@ config TARGET_P4080DS
        select PHYS_64BIT
        select ARCH_P4080
        select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select PHYS_64BIT
        select ARCH_P4080
        select BOARD_LATE_INIT if CHAIN_OF_TRUST

+       select FSL_NGPIXIS

        imply CMD_SATA
        imply PANIC_HANG
 
        imply CMD_SATA
        imply PANIC_HANG
 


@@ -94,6 +96,8 @@ config TARGET_P5040DS
        select PHYS_64BIT
        select ARCH_P5040
        select BOARD_LATE_INIT if CHAIN_OF_TRUST
        select PHYS_64BIT
        select ARCH_P5040
        select BOARD_LATE_INIT if CHAIN_OF_TRUST

+       select FSL_NGPIXIS
+       select SYS_FSL_RAID_ENGINE

        imply CMD_SATA
        imply PANIC_HANG
 
        imply CMD_SATA
        imply PANIC_HANG
 


@@ -262,6 +266,8 @@ config ARCH_B4420
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4

+       select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+       select SYS_FSL_USB1_PHY_ENABLE

        select SYS_PPC64
        select FSL_IFC
        imply CMD_EEPROM
        select SYS_PPC64
        select FSL_IFC
        imply CMD_EEPROM


@@ -293,6 +299,9 @@ config ARCH_B4860
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4

+       select SYS_FSL_SRIO_LIODN
+       select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+       select SYS_FSL_USB1_PHY_ENABLE

        select SYS_PPC64
        select FSL_IFC
        imply CMD_EEPROM
        select SYS_PPC64
        select FSL_IFC
        imply CMD_EEPROM


@@ -405,6 +414,7 @@ config ARCH_MPC8548
        select SYS_FSL_HAS_DDR2
        select SYS_FSL_HAS_DDR1
        select SYS_FSL_HAS_SEC
        select SYS_FSL_HAS_DDR2
        select SYS_FSL_HAS_DDR1
        select SYS_FSL_HAS_SEC

+       select SYS_FSL_RMU

        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_2
        select SYS_PPC_E500_USE_DEBUG_TLB
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_2
        select SYS_PPC_E500_USE_DEBUG_TLB


@@ -440,6 +450,7 @@ config ARCH_P1010
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4

+       select SYS_FSL_USB1_PHY_ENABLE

        select SYS_PPC_E500_USE_DEBUG_TLB
        select FSL_IFC
        imply CMD_EEPROM
        select SYS_PPC_E500_USE_DEBUG_TLB
        select FSL_IFC
        imply CMD_EEPROM


@@ -535,6 +546,7 @@ config ARCH_P1024
        select FSL_PCIE_RESET
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
        select FSL_PCIE_RESET
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC

+       select SYS_FSL_RMU

        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_2
        select SYS_PPC_E500_USE_DEBUG_TLB
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_2
        select SYS_PPC_E500_USE_DEBUG_TLB


@@ -610,6 +622,8 @@ config ARCH_P2041
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4

+       select SYS_FSL_USB1_PHY_ENABLE
+       select SYS_FSL_USB2_PHY_ENABLE

        select FSL_ELBC
        imply CMD_NAND
 
        select FSL_ELBC
        imply CMD_NAND
 


@@ -640,6 +654,8 @@ config ARCH_P3041
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4

+       select SYS_FSL_USB1_PHY_ENABLE
+       select SYS_FSL_USB2_PHY_ENABLE

        select FSL_ELBC
        imply CMD_NAND
        imply CMD_SATA
        select FSL_ELBC
        imply CMD_NAND
        imply CMD_SATA


@@ -681,6 +697,7 @@ config ARCH_P4080
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
        select SYS_FSL_QORIQ_CHASSIS1
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
        select SYS_FSL_QORIQ_CHASSIS1

+       select SYS_FSL_RMU

        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
        select FSL_ELBC
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
        select FSL_ELBC


@@ -711,6 +728,8 @@ config ARCH_P5040
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4

+       select SYS_FSL_USB1_PHY_ENABLE
+       select SYS_FSL_USB2_PHY_ENABLE

        select SYS_PPC64
        select FSL_ELBC
        imply CMD_SATA
        select SYS_PPC64
        select FSL_ELBC
        imply CMD_SATA


@@ -742,6 +761,9 @@ config ARCH_T1024
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_5
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_5

+       select SYS_FSL_SINGLE_SOURCE_CLK
+       select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+       select SYS_FSL_USB_DUAL_PHY_ENABLE

        select FSL_IFC
        imply CMD_EEPROM
        imply CMD_NAND
        select FSL_IFC
        imply CMD_EEPROM
        imply CMD_NAND


@@ -770,6 +792,9 @@ config ARCH_T1040
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_5
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_5

+       select SYS_FSL_SINGLE_SOURCE_CLK
+       select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+       select SYS_FSL_USB_DUAL_PHY_ENABLE

        select FSL_IFC
        imply CMD_MTDPARTS
        imply CMD_NAND
        select FSL_IFC
        imply CMD_MTDPARTS
        imply CMD_NAND


@@ -797,6 +822,9 @@ config ARCH_T1042
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_5
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_5

+       select SYS_FSL_SINGLE_SOURCE_CLK
+       select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+       select SYS_FSL_USB_DUAL_PHY_ENABLE

        select FSL_IFC
        imply CMD_MTDPARTS
        imply CMD_NAND
        select FSL_IFC
        imply CMD_MTDPARTS
        imply CMD_NAND


@@ -826,6 +854,9 @@ config ARCH_T2080
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4

+       select SYS_FSL_SRIO_LIODN
+       select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+       select SYS_FSL_USB_DUAL_PHY_ENABLE

        select SYS_PPC64
        select FSL_IFC
        imply CMD_SATA
        select SYS_PPC64
        select FSL_IFC
        imply CMD_SATA


@@ -859,6 +890,9 @@ config ARCH_T4240
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
        select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4

+       select SYS_FSL_SRIO_LIODN
+       select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+       select SYS_FSL_USB_DUAL_PHY_ENABLE

        select SYS_PPC64
        select FSL_IFC
        imply CMD_SATA
        select SYS_PPC64
        select FSL_IFC
        imply CMD_SATA


@@ -1147,6 +1181,12 @@ config FSL_PCIE_DISABLE_ASPM
 config FSL_PCIE_RESET
        bool
 
 config FSL_PCIE_RESET
        bool
 

+config SYS_FSL_RAID_ENGINE
+       bool
+
+config SYS_FSL_RMU
+       bool
+

 config SYS_FSL_QORIQ_CHASSIS1
        bool
 
 config SYS_FSL_QORIQ_CHASSIS1
        bool
 


@@ -1312,6 +1352,9 @@ config FSL_CORENET
        bool
        select SYS_FSL_CPC
 
        bool
        select SYS_FSL_CPC
 

+config FSL_NGPIXIS
+       bool
+

 config SYS_CPC_REINIT_F
        bool
        help
 config SYS_CPC_REINIT_F
        bool
        help


@@ -1347,6 +1390,33 @@ config SYS_FSL_PCIE_COMPAT
          Defines the string to utilize when trying to match PCIe device tree
          nodes for the given platform.
 
          Defines the string to utilize when trying to match PCIe device tree
          nodes for the given platform.
 

+config SYS_FSL_SINGLE_SOURCE_CLK
+       bool
+
+config SYS_FSL_SRIO_LIODN
+       bool
+
+config SYS_FSL_TBCLK_DIV
+       int
+       default 32 if ARCH_P2041 || ARCH_P3041
+       default 16 if ARCH_P4080 || ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \
+                       ARCH_B4420 || ARCH_T1040 || ARCH_T1042 || \
+                       ARCH_T1024 || ARCH_T2080
+       default 8
+       help
+         Defines the core time base clock divider ratio compared to the system
+         clock. On most PQ3 devices this is 8, on newer QorIQ devices it can
+         be 16 or 32. The ratio varies from SoC to Soc.
+
+config SYS_FSL_USB1_PHY_ENABLE
+       bool
+
+config SYS_FSL_USB2_PHY_ENABLE
+       bool
+
+config SYS_FSL_USB_DUAL_PHY_ENABLE
+       bool
+

 config SYS_MPC85XX_NO_RESETVEC
        bool "Discard resetvec section and move bootpg section up"
        depends on MPC85xx
 config SYS_MPC85XX_NO_RESETVEC
        bool "Discard resetvec section and move bootpg section up"
        depends on MPC85xx

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index ffa8b60..1b6cdc4 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -334,9 +334,6 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 /*
  * Get timebase clock frequency
  */
 /*
  * Get timebase clock frequency
  */

-#ifndef CONFIG_SYS_FSL_TBCLK_DIV
-#define CONFIG_SYS_FSL_TBCLK_DIV 8
-#endif

 __weak unsigned long get_tbclk(void)
 {
        unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
 __weak unsigned long get_tbclk(void)
 {
        unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;

diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
index 21b35db..bdd7338 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
@@ -31,10 +31,6 @@ ulong cpu_init_f(void)
        return 0;
 }
 
        return 0;
 }
 

-#ifndef CONFIG_SYS_FSL_TBCLK_DIV
-#define CONFIG_SYS_FSL_TBCLK_DIV 8
-#endif
-

 void udelay(unsigned long usec)
 {
        u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
 void udelay(unsigned long usec)
 {
        u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index f972bee..d3d4e9c 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -20,15 +20,12 @@
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  1
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  1
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5

-#define CONFIG_SYS_FSL_RMU

 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM       2
 
 #elif defined(CONFIG_ARCH_P1010)
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  4
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM       2
 
 #elif defined(CONFIG_ARCH_P1010)
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  4

-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE

 
 /* P1011 is single core version of P1020 */
 #elif defined(CONFIG_ARCH_P1011)
 
 /* P1011 is single core version of P1020 */
 #elif defined(CONFIG_ARCH_P1011)


@@ -65,7 +62,6 @@
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5

-#define CONFIG_SYS_FSL_RMU

 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM       2
 
 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM       2
 
 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */


@@ -73,10 +69,6 @@
 #define CONFIG_SYS_NUM_FM1_DTSEC       5
 #define CONFIG_SYS_NUM_FM1_10GEC       1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_NUM_FM1_DTSEC       5
 #define CONFIG_SYS_NUM_FM1_10GEC       1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000

-#define CONFIG_SYS_FSL_TBCLK_DIV       32
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY

 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5


@@ -87,10 +79,6 @@
 #define CONFIG_SYS_NUM_FM1_DTSEC       5
 #define CONFIG_SYS_NUM_FM1_10GEC       1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_NUM_FM1_DTSEC       5
 #define CONFIG_SYS_NUM_FM1_10GEC       1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000

-#define CONFIG_SYS_FSL_TBCLK_DIV       32
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY

 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5


@@ -103,11 +91,9 @@
 #define CONFIG_SYS_NUM_FM1_10GEC       1
 #define CONFIG_SYS_NUM_FM2_10GEC       1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_NUM_FM1_10GEC       1
 #define CONFIG_SYS_NUM_FM2_10GEC       1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000

-#define CONFIG_SYS_FSL_TBCLK_DIV       16

 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5

-#define CONFIG_SYS_FSL_RMU

 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM       2
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
 
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM       2
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
 


@@ -118,10 +104,6 @@
 #define CONFIG_SYS_NUM_FM2_DTSEC       5
 #define CONFIG_SYS_NUM_FM2_10GEC       1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_NUM_FM2_DTSEC       5
 #define CONFIG_SYS_NUM_FM2_10GEC       1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000

-#define CONFIG_SYS_FSL_TBCLK_DIV       16
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY

 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_ARCH_BSC9131)
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_ARCH_BSC9131)


@@ -135,7 +117,6 @@
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  3
 
 #elif defined(CONFIG_ARCH_T4240)
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  3
 
 #elif defined(CONFIG_ARCH_T4240)

-#define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */

 #ifdef CONFIG_ARCH_T4240
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 4 }
 #define CONFIG_SYS_NUM_FM1_DTSEC       8
 #ifdef CONFIG_ARCH_T4240
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 4 }
 #define CONFIG_SYS_NUM_FM1_DTSEC       8


@@ -158,24 +139,17 @@
 #define CONFIG_SYS_FM1_CLK             3
 #define CONFIG_SYS_FM2_CLK             3
 #define CONFIG_SYS_FM_MURAM_SIZE       0x60000
 #define CONFIG_SYS_FM1_CLK             3
 #define CONFIG_SYS_FM2_CLK             3
 #define CONFIG_SYS_FM_MURAM_SIZE       0x60000

-#define CONFIG_SYS_FSL_TBCLK_DIV       16

 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5

-#define CONFIG_SYS_FSL_SRIO_LIODN
-#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY

 
 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
 
 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)

-#define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */

 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_FM1_CLK             0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  4
 #define CONFIG_SYS_FM_MURAM_SIZE       0x60000
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_FM1_CLK             0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  4
 #define CONFIG_SYS_FM_MURAM_SIZE       0x60000

-#define CONFIG_SYS_FSL_TBCLK_DIV       16
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE

 
 #ifdef CONFIG_ARCH_B4860
 #define CONFIG_MAX_DSP_CPUS            12
 
 #ifdef CONFIG_ARCH_B4860
 #define CONFIG_MAX_DSP_CPUS            12


@@ -186,7 +160,6 @@
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5

-#define CONFIG_SYS_FSL_SRIO_LIODN

 #else
 #define CONFIG_MAX_DSP_CPUS            2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 4 }
 #else
 #define CONFIG_MAX_DSP_CPUS            2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 4 }


@@ -195,7 +168,6 @@
 #endif
 
 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
 #endif
 
 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)

-#define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */

 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 1, 1 }
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 1, 1 }
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_NUM_FMAN            1


@@ -206,17 +178,12 @@
 #define CONFIG_FM_PLAT_CLK_DIV 1
 #define CONFIG_SYS_FM1_CLK             CONFIG_FM_PLAT_CLK_DIV
 #define CONFIG_SYS_FM_MURAM_SIZE       0x30000
 #define CONFIG_FM_PLAT_CLK_DIV 1
 #define CONFIG_SYS_FM1_CLK             CONFIG_FM_PLAT_CLK_DIV
 #define CONFIG_SYS_FM_MURAM_SIZE       0x30000

-#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
-#define CONFIG_SYS_FSL_TBCLK_DIV       16
-#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY

 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define QE_MURAM_SIZE                  0x6000UL
 #define MAX_QE_RISC                    1
 #define QE_NUM_OF_SNUM                 28
 
 #elif defined(CONFIG_ARCH_T1024)
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define QE_MURAM_SIZE                  0x6000UL
 #define MAX_QE_RISC                    1
 #define QE_NUM_OF_SNUM                 28
 
 #elif defined(CONFIG_ARCH_T1024)

-#define CONFIG_SYS_FSL_QMAN_V3  /* QMAN version 3 */

 #define CONFIG_SYS_FSL_NUM_CC_PLL      2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1, 1, 1 }
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_NUM_CC_PLL      2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1, 1, 1 }
 #define CONFIG_SYS_FSL_SRDS_1


@@ -228,17 +195,12 @@
 #define CONFIG_SYS_FM1_CLK             0
 #define CONFIG_QBMAN_CLK_DIV           1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x30000
 #define CONFIG_SYS_FM1_CLK             0
 #define CONFIG_QBMAN_CLK_DIV           1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x30000

-#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
-#define CONFIG_SYS_FSL_TBCLK_DIV       16
-#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY

 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define QE_MURAM_SIZE                  0x6000UL
 #define MAX_QE_RISC                    1
 #define QE_NUM_OF_SNUM                 28
 
 #elif defined(CONFIG_ARCH_T2080)
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define QE_MURAM_SIZE                  0x6000UL
 #define MAX_QE_RISC                    1
 #define QE_NUM_OF_SNUM                 28
 
 #elif defined(CONFIG_ARCH_T2080)

-#define CONFIG_SYS_FSL_QMAN_V3

 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 4, 4, 4 }
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 4, 4, 4 }
 #define CONFIG_SYS_FSL_SRDS_1


@@ -246,7 +208,6 @@
 #define CONFIG_SYS_NUM_FM1_DTSEC       8
 #define CONFIG_SYS_NUM_FM1_10GEC       4
 #define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_NUM_FM1_DTSEC       8
 #define CONFIG_SYS_NUM_FM1_10GEC       4
 #define CONFIG_SYS_FSL_SRDS_2

-#define CONFIG_SYS_FSL_SRIO_LIODN

 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5


@@ -256,9 +217,6 @@
 #define CONFIG_SYS_FM1_CLK             0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_FM1_CLK             0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000

-#define CONFIG_SYS_FSL_TBCLK_DIV       16
-#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY

 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 
 
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 
 

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 52dc9e4..53742b2 100644 (file)
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -844,6 +844,10 @@ config SYS_DPAA_QBMAN
        help
          QBman fixups to allow deep sleep in DPAA 1 SOCs
 
        help
          QBman fixups to allow deep sleep in DPAA 1 SOCs
 

+config SYS_FSL_QMAN_V3
+       bool # QMAN version 3
+       depends on SYS_DPAA_QBMAN
+

 config TSEC_ENET
        select PHYLIB
        bool "Enable Three-Speed Ethernet Controller"
 config TSEC_ENET
        select PHYLIB
        bool "Enable Three-Speed Ethernet Controller"

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index c3b97f4..a0f48f0 100644 (file)
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -282,9 +282,15 @@ config EHCI_HCD_INIT_AFTER_RESET
 config USB_EHCI_FSL
        bool  "Support for FSL on-chip EHCI USB controller"
        select EHCI_HCD_INIT_AFTER_RESET
 config USB_EHCI_FSL
        bool  "Support for FSL on-chip EHCI USB controller"
        select EHCI_HCD_INIT_AFTER_RESET

+       select SYS_FSL_USB_INTERNAL_UTMI_PHY if MPC85xx && \
+               !(ARCH_B4860 || ARCH_B4420 || ARCH_P4080 || ARCH_P1020 || ARCH_P2020)

        ---help---
          Enables support for the on-chip EHCI controller on FSL chips.
 
        ---help---
          Enables support for the on-chip EHCI controller on FSL chips.
 

+config SYS_FSL_USB_INTERNAL_UTMI_PHY
+       bool
+       depends on USB_EHCI_FSL
+

 config USB_EHCI_TXFIFO_THRESH
        hex
        depends on USB_EHCI_TEGRA
 config USB_EHCI_TXFIFO_THRESH
        hex
        depends on USB_EHCI_TEGRA

diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h
index bc8aa3c..42e507b 100644 (file)
--- a/include/configs/P3041DS.h
+++ b/include/configs/P3041DS.h
@@ -7,8 +7,6 @@
  * P3041 DS board configuration file
  *
  */
  * P3041 DS board configuration file
  *
  */

-#define CONFIG_FSL_NGPIXIS             /* use common ngPIXIS code */
-

 #define CONFIG_SYS_DPAA_RMAN
 
 #define CONFIG_SYS_SRIO
 #define CONFIG_SYS_DPAA_RMAN
 
 #define CONFIG_SYS_SRIO

diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index 6375c65..fd55839 100644 (file)
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -7,7 +7,6 @@
  * P4080 DS board configuration file
  * Also supports P4040 DS
  */
  * P4080 DS board configuration file
  * Also supports P4040 DS
  */

-#define CONFIG_FSL_NGPIXIS             /* use common ngPIXIS code */

 
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1                   /* SRIO port 1 */
 
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1                   /* SRIO port 1 */

diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h
index fb73f0b..c8fc879 100644 (file)
--- a/include/configs/P5040DS.h
+++ b/include/configs/P5040DS.h
@@ -7,9 +7,6 @@
  * P5040 DS board configuration file
  *
  */
  * P5040 DS board configuration file
  *
  */

-#define CONFIG_FSL_NGPIXIS             /* use common ngPIXIS code */
-
-#define CONFIG_SYS_FSL_RAID_ENGINE

 
 #define CONFIG_ICS307_REFCLK_HZ                25000000  /* ICS307 ref clk freq */
 
 
 #define CONFIG_ICS307_REFCLK_HZ                25000000  /* ICS307 ref clk freq */