Merge branch 'for-2023.07' of https://source.denx.de/u-boot/custodians/u-boot-mpc8xx

This pull request adds support for the last CPU board from
CS GROUP France (previously CSSI).

That CPU board called CMPCPRO has a mpc8321E CPU (Family PQII PRO hence
its name) and can be plugged in place of the CMPC885 board.

In order to support that new board, the following changes are included
in this series:
- Make the mpc8xx watchdog driver more generic for reusing it
with mpc83xx
- Fix various small problems on mpc83xx platform
- Add a GPIO Driver for QE GPIOs
- Add support for mpc832x into mpc83xx SPI driver
- Refactor existing board code that will be shared with new board
- Add the new board

diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 5594a67..76ffdee 100644 (file)
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -2,7 +2,7 @@ variables:
   windows_vm: windows-2019
   ubuntu_vm: ubuntu-22.04
   macos_vm: macOS-12
-  ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20230308-21Mar2023
+  ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20230308-04Apr2023
   # Add '-u 0' options for Azure pipelines, otherwise we get "permission
   # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
   # since our $(ci_runner_image) user is not root.
@@ -254,7 +254,7 @@ stages:
           TEST_PY_BD: "sandbox"
         sandbox_clang:
           TEST_PY_BD: "sandbox"
-          OVERRIDE: "-O clang-14"
+          OVERRIDE: "-O clang-16"
         sandbox_nolto:
           TEST_PY_BD: "sandbox"
           BUILD_ENV: "NO_LTO=1"
@@ -263,7 +263,7 @@ stages:
           TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
         sandbox_vpl:
           TEST_PY_BD: "sandbox_vpl"
-          TEST_PY_TEST_SPEC: "test_vpl_help or test_spl"
+          TEST_PY_TEST_SPEC: "vpl or test_spl"
         sandbox_noinst:
           TEST_PY_BD: "sandbox_noinst"
           TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
@@ -297,6 +297,11 @@ stages:
         qemu_arm64:
           TEST_PY_BD: "qemu_arm64"
           TEST_PY_TEST_SPEC: "not sleep"
+        qemu_m68k:
+          TEST_PY_BD: "M5208EVBE"
+          TEST_PY_ID: "--id qemu"
+          TEST_PY_TEST_SPEC: "not sleep and not efi"
+          OVERRIDE: "-a CONFIG_M68K_QEMU=y -a ~CONFIG_MCFTMR"
         qemu_malta:
           TEST_PY_BD: "malta"
           TEST_PY_ID: "--id qemu"
@@ -509,7 +514,7 @@ stages:
           OVERRIDE: "-a ASAN"
         sandbox_clang_asan:
           BUILDMAN: "sandbox"
-          OVERRIDE: "-O clang-14 -a ASAN"
+          OVERRIDE: "-O clang-16 -a ASAN"
         samsung_socfpga:
           BUILDMAN: "samsung socfpga"
         sun4i:

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 5431bf6..b193fee 100644 (file)
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -10,7 +10,7 @@ default:
 
 # Grab our configured image.  The source for this is found
 # in the u-boot tree at tools/docker/Dockerfile
-image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20230308-21Mar2023
+image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20230308-04Apr2023
 
 # We run some tests in different order, to catch some failures quicker.
 stages:
@@ -277,7 +277,7 @@ sandbox test.py:
 sandbox with clang test.py:
   variables:
     TEST_PY_BD: "sandbox"
-    OVERRIDE: "-O clang-14"
+    OVERRIDE: "-O clang-16"
   <<: *buildman_and_testpy_dfn
 
 sandbox without LTO test.py:
@@ -301,7 +301,7 @@ sandbox_noinst_test.py:
 sandbox_vpl test.py:
   variables:
     TEST_PY_BD: "sandbox_vpl"
-    TEST_PY_TEST_SPEC: "test_vpl_help or test_spl"
+    TEST_PY_TEST_SPEC: "vpl or test_spl"
   <<: *buildman_and_testpy_dfn
 
 # Enable tracing and disable LTO, to ensure functions are not elided
@@ -355,6 +355,14 @@ qemu_arm64 test.py:
     TEST_PY_TEST_SPEC: "not sleep"
   <<: *buildman_and_testpy_dfn
 
+qemu_m68k test.py:
+  variables:
+    TEST_PY_BD: "M5208EVBE"
+    TEST_PY_ID: "--id qemu"
+    TEST_PY_TEST_SPEC: "not sleep and not efi"
+    OVERRIDE: "-a CONFIG_M68K_QEMU=y -a ~CONFIG_MCFTMR"
+  <<: *buildman_and_testpy_dfn
+
 qemu_malta test.py:
   variables:
     TEST_PY_BD: "malta"

diff --git a/Kconfig b/Kconfig
index 7a8c190..888b998 100644 (file)
--- a/Kconfig
+++ b/Kconfig
@@ -175,6 +175,8 @@ config CC_HAS_ASM_INLINE
 
 config XEN
        bool "Select U-Boot be run as a bootloader for XEN Virtual Machine"
+       depends on ARM64
+       select SSCANF
        help
          Enabling this option will make U-Boot be run as a bootloader
          for XEN [1] Virtual Machine.
@@ -427,7 +429,7 @@ config REMAKE_ELF
 
 config BUILD_TARGET
        string "Build target special images"
-       default "u-boot-elf.srec" if RCAR_GEN3
+       default "u-boot-elf.srec" if RCAR_64
        default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
        default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL
        default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
@@ -446,14 +448,14 @@ config BUILD_TARGET
 
 config HAS_BOARD_SIZE_LIMIT
        bool "Define a maximum size for the U-Boot image"
-       default y if RCAR_GEN3
+       default y if RCAR_64
        help
          In some cases, we need to enforce a hard limit on how big the U-Boot
          image itself can be.
 
 config BOARD_SIZE_LIMIT
        int "Maximum size of the U-Boot image in bytes"
-       default 1048576 if RCAR_GEN3
+       default 1048576 if RCAR_64
        depends on HAS_BOARD_SIZE_LIMIT
        help
          Maximum size of the U-Boot image. When defined, the build system

diff --git a/MAINTAINERS b/MAINTAINERS
index d2e245e..f752132 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -793,6 +793,15 @@ M: Alper Nebi Yasak <alpernebiyasak@gmail.com>
 S:     Maintained
 F:     tools/binman/
 
+BLKMAP
+M:     Tobias Waldekranz <tobias@waldekranz.com>
+S:     Maintained
+F:     cmd/blkmap.c
+F:     doc/usage/blkmap.rst
+F:     drivers/block/blkmap.c
+F:     include/blkmap.h
+F:     test/dm/blkmap.c
+
 BOOTDEVICE
 M:     Simon Glass <sjg@chromium.org>
 S:     Maintained
@@ -1172,13 +1181,6 @@ S:       Maintained
 T:     git https://source.denx.de/u-boot/custodians/u-boot-mmc.git
 F:     drivers/mmc/
 
-NAND FLASH
-M:     Dario Binacchi <dario.binacchi@amarulasolutions.com>
-M:     Michael Trimarchi <michael@amarulasolutions.com>
-S:     Maintained
-T:     git https://source.denx.de/u-boot/custodians/u-boot-nand-flash.git
-F:     drivers/mtd/nand/raw/
-
 NETWORK
 M:     Joe Hershberger <joe.hershberger@ni.com>
 M:     Ramon Fried <rfried.dev@gmail.com>
@@ -1202,6 +1204,14 @@ F:       cmd/nvme.c
 F:     include/nvme.h
 F:     doc/develop/driver-model/nvme.rst
 
+NVMXIP
+M:     Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+S:     Maintained
+F:     doc/develop/driver-model/nvmxip.rst
+F:     doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt
+F:     drivers/mtd/nvmxip/
+F:     test/dm/nvmxip.c
+
 NVMEM
 M:     Sean Anderson <seanga2@gmail.com>
 S:     Maintained
@@ -1297,6 +1307,13 @@ S:       Maintained
 T:     git https://source.denx.de/u-boot/custodians/u-boot-mpc85xx.git
 F:     arch/powerpc/cpu/mpc85xx/
 
+RAW NAND
+M:     Dario Binacchi <dario.binacchi@amarulasolutions.com>
+M:     Michael Trimarchi <michael@amarulasolutions.com>
+S:     Maintained
+T:     git https://source.denx.de/u-boot/custodians/u-boot-nand-flash.git
+F:     drivers/mtd/nand/raw/
+
 RISC-V
 M:     Rick Chen <rick@andestech.com>
 M:     Leo <ycliang@andestech.com>
@@ -1344,6 +1361,7 @@ F:        arch/sandbox/
 F:     doc/arch/sandbox.rst
 F:     drivers/*/*sandbox*.c
 F:     include/dt-bindings/*/sandbox*.h
+F:     include/os.h
 
 SEAMA
 M:     Linus Walleij <linus.walleij@linaro.org>
@@ -1389,6 +1407,14 @@ T:       git https://source.denx.de/u-boot/custodians/u-boot-spi.git
 F:     drivers/spi/
 F:     include/spi*
 
+SPI NAND
+M:     Dario Binacchi <dario.binacchi@amarulasolutions.com>
+M:     Michael Trimarchi <michael@amarulasolutions.com>
+R:     Frieder Schrempf <frieder.schrempf@kontron.de>
+S:     Maintained
+T:     git https://source.denx.de/u-boot/custodians/u-boot-nand-flash.git
+F:     drivers/mtd/nand/spi/
+
 SPI-NOR
 M:     Jagan Teki <jagan@amarulasolutions.com>
 M:     Vignesh R <vigneshr@ti.com>

diff --git a/Makefile b/Makefile
index 0f37c4b..166acba 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
 VERSION = 2023
 PATCHLEVEL = 04
 SUBLEVEL =
-EXTRAVERSION = -rc5
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*
@@ -437,6 +437,7 @@ KBUILD_LDFLAGS  :=
 ifeq ($(cc-name),clang)
 ifneq ($(CROSS_COMPILE),)
 CLANG_TARGET   := --target=$(notdir $(CROSS_COMPILE:%-=%))
+LDPPFLAGS      += $(CLANG_TARGET)
 GCC_TOOLCHAIN_DIR := $(dir $(shell which $(LD)))
 CLANG_PREFIX   := --prefix=$(GCC_TOOLCHAIN_DIR)
 GCC_TOOLCHAIN  := $(realpath $(GCC_TOOLCHAIN_DIR)/..)
@@ -893,8 +894,10 @@ u-boot-main := $(libs-y)
 ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y)
 PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a
 else
+ifndef CONFIG_CC_IS_CLANG
 PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`) -lgcc
 endif
+endif
 PLATFORM_LIBS += $(PLATFORM_LIBGCC)
 
 ifdef CONFIG_CC_COVERAGE
@@ -1522,6 +1525,9 @@ endif
 u-boot.uim: u-boot.bin FORCE
        $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 
+u-boot-nand.imx: u-boot.imx FORCE
+       $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
+
 u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL $(if $(CONFIG_OF_SEPARATE),u-boot.img,u-boot.uim) FORCE
        $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 
@@ -1758,7 +1764,7 @@ ifeq ($(CONFIG_KALLSYMS),y)
 endif
 
 ifeq ($(CONFIG_RISCV),y)
-       @tools/prelink-riscv $@ 0
+       @tools/prelink-riscv $@
 endif
 
 quiet_cmd_sym ?= SYM     $@

diff --git a/api/Kconfig b/api/Kconfig
index 6072288..b5a7399 100644 (file)
--- a/api/Kconfig
+++ b/api/Kconfig
@@ -1,13 +1,14 @@
-menu "API"
-
 config API
        bool "Enable U-Boot API"
+       depends on CC_IS_GCC
        help
          This option enables the U-Boot API. See api/README for more information.
 
+menu "API"
+       depends on API
+
 config SYS_MMC_MAX_DEVICE
        int  "Maximum number of MMC devices exposed via the API"
-       depends on API
        default 1
 
 config EXAMPLES

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f0118e2..b84c494 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -12,7 +12,7 @@ config ARM64
 
 config ARM64_CRC32
        bool "Enable support for CRC32 instruction"
-       depends on ARM64
+       depends on ARM64 && CC_IS_GCC
        default y
        help
          ARMv8 implements dedicated crc32 instruction for crc32 calculation.
@@ -1956,8 +1956,7 @@ config ARCH_ROCKCHIP
        imply ADC
        imply CMD_DM
        imply DEBUG_UART_BOARD_INIT
-       imply DISTRO_DEFAULTS if !ROCKCHIP_RK3399
-       imply BOOTSTD_DEFAULTS if !DISTRO_DEFAULTS
+       imply BOOTSTD_DEFAULTS
        imply FAT_WRITE
        imply SARADC_ROCKCHIP
        imply SPL_SYSRESET
@@ -2044,7 +2043,6 @@ config TARGET_XENGUEST_ARM64
        select OF_CONTROL
        select LINUX_KERNEL_IMAGE_HEADER
        select XEN_SERIAL
-       select SSCANF
        imply OF_HAS_PRIOR_STAGE
 
 config ARCH_GXP

diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index bf781f1..5530d02 100644 (file)
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -3,7 +3,13 @@
 # (C) Copyright 2000-2002
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
-CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \
+ifeq ($(CONFIG_ARM64),y)
+FIXED_REG := -ffixed-x18
+else
+FIXED_REG := -ffixed-r9
+endif
+
+CFLAGS_NON_EFI := -fno-pic $(FIXED_REG) -ffunction-sections -fdata-sections \
                  -fstack-protector-strong
 CFLAGS_EFI := -fpic -fshort-wchar
 
@@ -15,7 +21,7 @@ ifneq ($(LTO_ENABLE),y)
 PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
 endif
 
-PLATFORM_RELFLAGS += -fno-common -ffixed-r9
+PLATFORM_RELFLAGS += -fno-common $(FIXED_REG)
 PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
                     $(call cc-option,-mgeneral-regs-only) \
       $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 7d7aac0..69e281b 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -134,8 +134,8 @@ ENTRY(c_runtime_cpu_setup)
  */
 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
        mcr     p15, 0, r0, c7, c5, 0   @ invalidate icache
-       mcr     p15, 0, r0, c7, c10, 4  @ DSB
-       mcr     p15, 0, r0, c7, c5, 4   @ ISB
+       dsb
+       isb
 #endif
 
        bx      lr
@@ -188,8 +188,8 @@ ENTRY(cpu_init_cp15)
        mcr     p15, 0, r0, c8, c7, 0   @ invalidate TLBs
        mcr     p15, 0, r0, c7, c5, 0   @ invalidate icache
        mcr     p15, 0, r0, c7, c5, 6   @ invalidate BP array
-       mcr     p15, 0, r0, c7, c10, 4  @ DSB
-       mcr     p15, 0, r0, c7, c5, 4   @ ISB
+       dsb
+       isb
 
        /*
         * disable MMU stuff and caches

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 6973340..cb1131a 100644 (file)
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -93,10 +93,16 @@ u64 get_tcr(u64 *pips, u64 *pva_bits)
 
        if (el == 1) {
                tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
+               if (gd->arch.has_hafdbs)
+                       tcr |= TCR_EL1_HA | TCR_EL1_HD;
        } else if (el == 2) {
                tcr = TCR_EL2_RSVD | (ips << 16);
+               if (gd->arch.has_hafdbs)
+                       tcr |= TCR_EL2_HA | TCR_EL2_HD;
        } else {
                tcr = TCR_EL3_RSVD | (ips << 16);
+               if (gd->arch.has_hafdbs)
+                       tcr |= TCR_EL3_HA | TCR_EL3_HD;
        }
 
        /* PTWs cacheable, inner/outer WBWA and inner shareable */
@@ -200,6 +206,9 @@ static void __cmo_on_leaves(void (*cmo_fn)(unsigned long, unsigned long),
                    attrs != PTE_BLOCK_MEMTYPE(MT_NORMAL_NC))
                        continue;
 
+               if (gd->arch.has_hafdbs && (pte & (PTE_RDONLY | PTE_DBM)) != PTE_DBM)
+                       continue;
+
                end = va + BIT(level2shift(level)) - 1;
 
                /* No intersection with RAM? */
@@ -309,7 +318,7 @@ static void map_range(u64 virt, u64 phys, u64 size, int level,
        for (i = idx; size; i++) {
                u64 next_size, *next_table;
 
-               if (level >= 1 &&
+               if (level >= gd->arch.first_block_level &&
                    size >= map_size && !(virt & (map_size - 1))) {
                        if (level == 3)
                                table[i] = phys | attrs | PTE_TYPE_PAGE;
@@ -348,6 +357,12 @@ static void add_map(struct mm_region *map)
        if (va_bits < 39)
                level = 1;
 
+       if (!gd->arch.first_block_level)
+               gd->arch.first_block_level = 1;
+
+       if (gd->arch.has_hafdbs)
+               attrs |= PTE_DBM | PTE_RDONLY;
+
        map_range(map->virt, map->phys, map->size, level,
                  (u64 *)gd->arch.tlb_addr, attrs);
 }
@@ -361,7 +376,7 @@ static void count_range(u64 virt, u64 size, int level, int *cntp)
        for (i = idx; size; i++) {
                u64 next_size;
 
-               if (level >= 1 &&
+               if (level >= gd->arch.first_block_level &&
                    size >= map_size && !(virt & (map_size - 1))) {
                        virt += map_size;
                        size -= map_size;
@@ -399,7 +414,16 @@ static int count_ranges(void)
 __weak u64 get_page_table_size(void)
 {
        u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
-       u64 size;
+       u64 size, mmfr1;
+
+       asm volatile("mrs %0, id_aa64mmfr1_el1" : "=r" (mmfr1));
+       if ((mmfr1 & 0xf) == 2) {
+               gd->arch.has_hafdbs = true;
+               gd->arch.first_block_level = 2;
+       } else {
+               gd->arch.has_hafdbs = false;
+               gd->arch.first_block_level = 1;
+       }
 
        /* Account for all page tables we would need to cover our memory map */
        size = one_pt * count_ranges();

diff --git a/arch/arm/cpu/armv8/config.mk b/arch/arm/cpu/armv8/config.mk
index ca06ed3..4d74b2a 100644 (file)
--- a/arch/arm/cpu/armv8/config.mk
+++ b/arch/arm/cpu/armv8/config.mk
@@ -2,7 +2,6 @@
 #
 # (C) Copyright 2002
 # Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-PLATFORM_RELFLAGS += -fno-common -ffixed-x18
 PLATFORM_RELFLAGS += $(call cc-option,-mbranch-protection=none)
 
 PF_NO_UNALIGNED := $(call cc-option, -mstrict-align)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 97a4832..3385948 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
 
 dtb-$(CONFIG_ROCKCHIP_RK3588) += \
        rk3588-edgeble-neu6a-io.dtb \
+       rk3588-evb1-v10.dtb \
        rk3588-rock-5b.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RV1108) += \
@@ -191,6 +192,8 @@ dtb-$(CONFIG_ARCH_MESON) += \
        meson-gxbb-nanopi-k2.dtb \
        meson-gxbb-p200.dtb \
        meson-gxbb-p201.dtb \
+       meson-gxbb-wetek-hub.dtb \
+       meson-gxbb-wetek-play2.dtb \
        meson-gxl-s805x-libretech-ac.dtb \
        meson-gxl-s905d-libretech-pc.dtb \
        meson-gxl-s905w-jethome-jethub-j80.dtb \
@@ -198,20 +201,25 @@ dtb-$(CONFIG_ARCH_MESON) += \
        meson-gxl-s905x-libretech-cc.dtb \
        meson-gxl-s905x-libretech-cc-v2.dtb \
        meson-gxl-s905x-p212.dtb \
+       meson-gxm-gt1-ultimate.dtb \
        meson-gxm-khadas-vim2.dtb \
        meson-gxm-s912-libretech-pc.dtb \
        meson-gxm-wetek-core2.dtb \
        meson-g12a-radxa-zero.dtb \
        meson-g12a-sei510.dtb \
        meson-g12a-u200.dtb \
+       meson-g12b-a311d-bananapi-m2s.dtb \
        meson-g12b-a311d-khadas-vim3.dtb \
+       meson-g12b-bananapi-cm4-cm4io.dtb \
+       meson-g12b-gsking-x.dtb \
        meson-g12b-gtking.dtb \
        meson-g12b-gtking-pro.dtb \
-       meson-g12b-gsking-x.dtb \
        meson-g12b-odroid-go-ultra.dtb \
        meson-g12b-odroid-n2.dtb \
        meson-g12b-odroid-n2l.dtb \
        meson-g12b-odroid-n2-plus.dtb \
+       meson-g12b-radxa-zero2.dtb \
+       meson-sm1-bananapi-m2-pro.dtb \
        meson-sm1-bananapi-m5.dtb \
        meson-sm1-khadas-vim3l.dtb \
        meson-sm1-odroid-c4.dtb \
@@ -995,6 +1003,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
        imx8mn-beacon-kit.dtb \
        imx8mq-mnt-reform2.dtb \
        imx8mq-phanbell.dtb \
+       imx8mp-beacon-kit.dtb \
+       imx8mp-data-modul-edm-sbc.dtb \
        imx8mp-dhcom-pdk2.dtb \
        imx8mp-dhcom-pdk3.dtb \
        imx8mp-evk.dtb \
@@ -1042,10 +1052,14 @@ dtb-$(CONFIG_RCAR_GEN3) += \
        r8a77970-eagle-u-boot.dtb \
        r8a77980-condor-u-boot.dtb \
        r8a77990-ebisu-u-boot.dtb \
-       r8a77995-draak-u-boot.dtb \
-       r8a779a0-falcon-u-boot.dtb
+       r8a77995-draak-u-boot.dtb
+
+dtb-$(CONFIG_RCAR_GEN4) += \
+       r8a779a0-falcon-u-boot.dtb \
+       r8a779f0-spider-u-boot.dtb \
+       r8a779g0-white-hawk-u-boot.dtb
 
-ifdef CONFIG_RCAR_GEN3
+ifdef CONFIG_RCAR_64
 DTC_FLAGS += -R 4 -p 0x1000
 endif
 

diff --git a/arch/arm/dts/am335x-base0033.dts b/arch/arm/dts/am335x-base0033.dts
index 29782be..89c00ce 100644 (file)
--- a/arch/arm/dts/am335x-base0033.dts
+++ b/arch/arm/dts/am335x-base0033.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION
  *
  * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include "am335x-igep0033.dtsi"
@@ -46,39 +43,39 @@
 &am33xx_pinmux {
        nxp_hdmi_pins: pinmux_nxp_hdmi_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3)     /* xdma_event_intr0.clkout1 */
-                       AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data0 */
-                       AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data1 */
-                       AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data2 */
-                       AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)     /* lcd_data3 */
-                       AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data4 */
-                       AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data5 */
-                       AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data6 */
-                       AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)     /* lcd_data7 */
-                       AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data8 */
-                       AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data9 */
-                       AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data10 */
-                       AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)     /* lcd_data11 */
-                       AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data12 */
-                       AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data13 */
-                       AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data14 */
-                       AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)     /* lcd_data15 */
-                       AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)     /* lcd_vsync */
-                       AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)     /* lcd_hsync */
-                       AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)     /* lcd_pclk */
-                       AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)     /* lcd_ac_bias_en */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3)      /* xdma_event_intr0.clkout1 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
                >;
        };
        nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3)     /* xdma_event_intr0.clkout1 */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3)      /* xdma_event_intr0.clkout1 */
                >;
        };
 
        leds_base_pins: pinmux_leds_base_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_a5.gpio1_21 */
-                       AM33XX_IOPAD(0x888, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_csn3.gpio2_0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a5.gpio1_21 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT_PULLDOWN, MUX_MODE7)    /* gpmc_csn3.gpio2_0 */
                >;
        };
 };

diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi
index 43fe03d..67dfcd8 100644 (file)
--- a/arch/arm/dts/am335x-bone-common.dtsi
+++ b/arch/arm/dts/am335x-bone-common.dtsi
@@ -371,7 +371,6 @@
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&davinci_mdio_default>;
        pinctrl-1 = <&davinci_mdio_sleep>;
-       status = "okay";
 
        ethphy0: ethernet-phy@0 {
                reg = <0>;

diff --git a/arch/arm/dts/am335x-boneblack-hdmi.dtsi b/arch/arm/dts/am335x-boneblack-hdmi.dtsi
index 7cfddad..486f24d 100644 (file)
--- a/arch/arm/dts/am335x-boneblack-hdmi.dtsi
+++ b/arch/arm/dts/am335x-boneblack-hdmi.dtsi
@@ -85,8 +85,13 @@
                audio-ports = < TDA998x_I2S     0x03>;
 
                ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
                        port@0 {
-                               hdmi_0: endpoint@0 {
+                               reg = <0>;
+
+                               hdmi_0: endpoint {
                                        remote-endpoint = <&lcdc_0>;
                                };
                        };

diff --git a/arch/arm/dts/am335x-boneblack-wireless.dts b/arch/arm/dts/am335x-boneblack-wireless.dts
index 8b2b24c..afa4fdc 100644 (file)
--- a/arch/arm/dts/am335x-boneblack-wireless.dts
+++ b/arch/arm/dts/am335x-boneblack-wireless.dts
@@ -19,7 +19,7 @@
                regulator-name = "wlan-en-regulator";
                regulator-min-microvolt = <1800000>;
                regulator-max-microvolt = <1800000>;
-               startup-delay-us= <70000>;
+               startup-delay-us = <70000>;
 
                /* WL_EN */
                gpio = <&gpio3 9 0>;

diff --git a/arch/arm/dts/am335x-boneblack.dts b/arch/arm/dts/am335x-boneblack.dts
index 9312197..b956e2f 100644 (file)
--- a/arch/arm/dts/am335x-boneblack.dts
+++ b/arch/arm/dts/am335x-boneblack.dts
@@ -168,3 +168,7 @@
                "NC",
                "NC";
 };
+
+&baseboard_eeprom {
+       vcc-supply = <&ldo4_reg>;
+};

diff --git a/arch/arm/dts/am335x-boneblue.dts b/arch/arm/dts/am335x-boneblue.dts
index 856fdf5..f04f46d 100644 (file)
--- a/arch/arm/dts/am335x-boneblue.dts
+++ b/arch/arm/dts/am335x-boneblue.dts
@@ -107,7 +107,7 @@
                regulator-name = "wlan-en-regulator";
                regulator-min-microvolt = <1800000>;
                regulator-max-microvolt = <1800000>;
-               startup-delay-us= <70000>;
+               startup-delay-us = <70000>;
 
                /* WL_EN */
                gpio = <&gpio3 9 0>;

diff --git a/arch/arm/dts/am335x-bonegreen-wireless.dts b/arch/arm/dts/am335x-bonegreen-wireless.dts
index 74db0fc..b363d03 100644 (file)
--- a/arch/arm/dts/am335x-bonegreen-wireless.dts
+++ b/arch/arm/dts/am335x-bonegreen-wireless.dts
@@ -18,7 +18,7 @@
                regulator-name = "wlan-en-regulator";
                regulator-min-microvolt = <1800000>;
                regulator-max-microvolt = <1800000>;
-               startup-delay-us= <70000>;
+               startup-delay-us = <70000>;
 
                /* WL_EN */
                gpio = <&gpio0 26 0>;

diff --git a/arch/arm/dts/am335x-chiliboard.dts b/arch/arm/dts/am335x-chiliboard.dts
index 9c2a947..129a02b 100644 (file)
--- a/arch/arm/dts/am335x-chiliboard.dts
+++ b/arch/arm/dts/am335x-chiliboard.dts
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
+ * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/
  * Author: Rostislav Lisovy <lisovy@jablotron.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 /dts-v1/;
 #include "am335x-chilisom.dtsi"
@@ -37,79 +34,79 @@
 &am33xx_pinmux {
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1 */
-                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1)       /* mii1_rxerr.rmii1_rxerr */
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_txen.rmii1_txen */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_txd1.rmii1_txd1 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_txd0.rmii1_txd0 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1)       /* mii1_rxd1.rmii1_rxd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1)       /* mii1_rxd0.rmii1_rxd0 */
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* rmii1_ref_clk.rmii_ref_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
                        /* mdio_clk.mdio_clk */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        usb1_drvvbus: usb1_drvvbus {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */
+                       AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        sd_pins: pinmux_sd_card {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
-                       AM33XX_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
-                       AM33XX_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
-                       AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */
                >;
        };
 
        led_gpio_pins: led_gpio_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9e4, PIN_OUTPUT | MUX_MODE7) /* emu0.gpio3_7 */
-                       AM33XX_IOPAD(0x9e8, PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */
+                       AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_OUTPUT, MUX_MODE7) /* emu0.gpio3_7 */
+                       AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT, MUX_MODE7) /* emu1.gpio3_8 */
                >;
        };
 };

diff --git a/arch/arm/dts/am335x-chilisom.dtsi b/arch/arm/dts/am335x-chilisom.dtsi
index 1b43ebd..43b61e4 100644 (file)
--- a/arch/arm/dts/am335x-chilisom.dtsi
+++ b/arch/arm/dts/am335x-chilisom.dtsi
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
+ * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/
  * Author: Rostislav Lisovy <lisovy@jablotron.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 #include "am33xx.dtsi"
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -30,28 +27,28 @@
 
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        nandflash_pins: nandflash_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad0.gpmc_ad0 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad1.gpmc_ad1 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad2.gpmc_ad2 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad3.gpmc_ad3 */
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad4.gpmc_ad4 */
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad5.gpmc_ad5 */
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad6.gpmc_ad6 */
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad7.gpmc_ad7 */
-
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_wait0.gpmc_wait0 */
-                       AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0)      /* gpmc_csn0.gpmc_csn0 */
-                       AM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0)      /* gpmc_advn_ale.gpmc_advn_ale */
-                       AM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0)      /* gpmc_oen_ren.gpmc_oen_ren */
-                       AM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0)      /* gpmc_wen.gpmc_wen */
-                       AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0)      /* gpmc_be0n_cle.gpmc_be0n_cle */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE0)
+
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 };

diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts
index 2a2972f..6e79962 100644 (file)
--- a/arch/arm/dts/am335x-evm.dts
+++ b/arch/arm/dts/am335x-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -25,12 +22,16 @@
                };
        };
 
-       memory {
+       memory@80000000 {
                device_type = "memory";
                reg = <0x80000000 0x10000000>; /* 256 MB */
        };
 
-       vbat: fixedregulator@0 {
+       chosen {
+               stdout-path = &uart0;
+       };
+
+       vbat: fixedregulator0 {
                compatible = "regulator-fixed";
                regulator-name = "vbat";
                regulator-min-microvolt = <5000000>;
@@ -38,13 +39,13 @@
                regulator-boot-on;
        };
 
-       lis3_reg: fixedregulator@1 {
+       lis3_reg: fixedregulator1 {
                compatible = "regulator-fixed";
                regulator-name = "lis3_reg";
                regulator-boot-on;
        };
 
-       wlan_en_reg: fixedregulator@2 {
+       wlan_en_reg: fixedregulator2 {
                compatible = "regulator-fixed";
                regulator-name = "wlan-en-regulator";
                regulator-min-microvolt = <1800000>;
@@ -78,18 +79,18 @@
                                0x0201006c>;    /* DOWN */
        };
 
-       gpio_keys: volume_keys@0 {
+       gpio_keys: volume-keys {
                compatible = "gpio-keys";
                autorepeat;
 
-               switch@9 {
+               switch-9 {
                        label = "volume-up";
                        linux,code = <115>;
                        gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
                        gpio-key,wakeup;
                };
 
-               switch@10 {
+               switch-10 {
                        label = "volume-down";
                        linux,code = <114>;
                        gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
@@ -158,206 +159,206 @@
 
        matrix_keypad_s0: matrix_keypad_s0 {
                pinctrl-single,pins = <
-                       0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a5.gpio1_21 */
-                       0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a6.gpio1_22 */
-                       0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a9.gpio1_25 */
-                       0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a10.gpio1_26 */
-                       0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a11.gpio1_27 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a5.gpio1_21 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a6.gpio1_22 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)       /* gpmc_a9.gpio1_25 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a10.gpio1_26 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a11.gpio1_27 */
                >;
        };
 
        volume_keys_s0: volume_keys_s0 {
                pinctrl-single,pins = <
-                       0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* spi0_sclk.gpio0_2 */
-                       0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* spi0_d0.gpio0_3 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* spi0_sclk.gpio0_2 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7)       /* spi0_d0.gpio0_3 */
                >;
        };
 
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
-                       0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)        /* i2c0_sda.i2c0_sda */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)        /* i2c0_scl.i2c0_scl */
                >;
        };
 
        i2c1_pins: pinmux_i2c1_pins {
                pinctrl-single,pins = <
-                       0x158 (PIN_INPUT_PULLUP | MUX_MODE2)    /* spi0_d1.i2c1_sda */
-                       0x15c (PIN_INPUT_PULLUP | MUX_MODE2)    /* spi0_cs0.i2c1_scl */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2)        /* spi0_cs0.i2c1_scl */
                >;
        };
 
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
-                       0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart1_pins: pinmux_uart1_pins {
                pinctrl-single,pins = <
-                       0x178 (PIN_INPUT | MUX_MODE0)           /* uart1_ctsn.uart1_ctsn */
-                       0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
-                       0x180 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart1_rxd.uart1_rxd */
-                       0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        clkout2_pin: pinmux_clkout2_pin {
                pinctrl-single,pins = <
-                       0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)     /* xdma_event_intr1.clkout2 */
                >;
        };
 
        nandflash_pins_s0: nandflash_pins_s0 {
                pinctrl-single,pins = <
-                       0x0 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad0.gpmc_ad0 */
-                       0x4 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad1.gpmc_ad1 */
-                       0x8 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad2.gpmc_ad2 */
-                       0xc (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad3.gpmc_ad3 */
-                       0x10 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad4.gpmc_ad4 */
-                       0x14 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad5.gpmc_ad5 */
-                       0x18 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad6.gpmc_ad6 */
-                       0x1c (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad7.gpmc_ad7 */
-                       0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
-                       0x74 (PIN_INPUT_PULLUP | MUX_MODE7)     /* gpmc_wpn.gpio0_30 */
-                       0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0  */
-                       0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
-                       0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
-                       0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
-                       0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7)        /* gpmc_wpn.gpio0_31 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
        ecap0_pins: backlight_pins {
                pinctrl-single,pins = <
-                       0x164 0x0       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+                       AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0)
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1 */
-                       0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
-                       0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rctl */
-                       0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
-                       0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
-                       0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
-                       0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
-                       0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
-                       0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rgmii1_rclk */
-                       0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd3.rgmii1_rd3 */
-                       0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd2.rgmii1_rd2 */
-                       0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rd1 */
-                       0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rd0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)   /* mii1_txen.rgmii1_tctl */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)    /* mii1_rxdv.rgmii1_rctl */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd3.rgmii1_td3 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd2.rgmii1_td2 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd1.rgmii1_td1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd0.rgmii1_td0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)  /* mii1_txclk.rgmii1_tclk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)   /* mii1_rxclk.rgmii1_rclk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd3.rgmii1_rd3 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd2.rgmii1_rd2 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd1.rgmii1_rd1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd0.rgmii1_rd0 */
                >;
        };
 
        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* MDIO */
-                       0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
-                       0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
-                       0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)               /* spi0_cs1.gpio0_6 */
                >;
        };
 
        mmc3_pins: pinmux_mmc3_pins {
                pinctrl-single,pins = <
-                       0x44 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
-                       0x48 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
-                       0x4C (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
-                       0x78 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
-                       0x88 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
-                       0x8C (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3)       /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3)       /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3)        /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
                >;
        };
 
        wlan_pins: pinmux_wlan_pins {
                pinctrl-single,pins = <
-                       0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a0.gpio1_16 */
-                       0x19C (PIN_INPUT | MUX_MODE7)           /* mcasp0_ahclkr.gpio3_17 */
-                       0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a0.gpio1_16 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7)          /* mcasp0_ahclkr.gpio3_17 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7)        /* mcasp0_ahclkx.gpio3_21 */
                >;
        };
 
        lcd_pins_s0: lcd_pins_s0 {
                pinctrl-single,pins = <
-                       0x20 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad8.lcd_data23 */
-                       0x24 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad9.lcd_data22 */
-                       0x28 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad10.lcd_data21 */
-                       0x2c (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad11.lcd_data20 */
-                       0x30 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad12.lcd_data19 */
-                       0x34 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad13.lcd_data18 */
-                       0x38 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad14.lcd_data17 */
-                       0x3c (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad15.lcd_data16 */
-                       0xa0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data0.lcd_data0 */
-                       0xa4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data1.lcd_data1 */
-                       0xa8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data2.lcd_data2 */
-                       0xac (PIN_OUTPUT | MUX_MODE0)           /* lcd_data3.lcd_data3 */
-                       0xb0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data4.lcd_data4 */
-                       0xb4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data5.lcd_data5 */
-                       0xb8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data6.lcd_data6 */
-                       0xbc (PIN_OUTPUT | MUX_MODE0)           /* lcd_data7.lcd_data7 */
-                       0xc0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data8.lcd_data8 */
-                       0xc4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data9.lcd_data9 */
-                       0xc8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data10.lcd_data10 */
-                       0xcc (PIN_OUTPUT | MUX_MODE0)           /* lcd_data11.lcd_data11 */
-                       0xd0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data12.lcd_data12 */
-                       0xd4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data13.lcd_data13 */
-                       0xd8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data14.lcd_data14 */
-                       0xdc (PIN_OUTPUT | MUX_MODE0)           /* lcd_data15.lcd_data15 */
-                       0xe0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_vsync.lcd_vsync */
-                       0xe4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_hsync.lcd_hsync */
-                       0xe8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_pclk.lcd_pclk */
-                       0xec (PIN_OUTPUT | MUX_MODE0)           /* lcd_ac_bias_en.lcd_ac_bias_en */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1)              /* gpmc_ad8.lcd_data23 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1)              /* gpmc_ad9.lcd_data22 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1)             /* gpmc_ad10.lcd_data21 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1)             /* gpmc_ad11.lcd_data20 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1)             /* gpmc_ad12.lcd_data19 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1)             /* gpmc_ad13.lcd_data18 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1)             /* gpmc_ad14.lcd_data17 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1)             /* gpmc_ad15.lcd_data16 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
-       am335x_evm_audio_pins: am335x_evm_audio_pins {
+       mcasp1_pins: mcasp1_pins {
                pinctrl-single,pins = <
-                       0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
-                       0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
-                       0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
-                       0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
                >;
        };
 
        dcan1_pins_default: dcan1_pins_default {
                pinctrl-single,pins = <
-                       0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
-                       0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
                >;
        };
 };
@@ -486,7 +487,7 @@
 &epwmss0 {
        status = "okay";
 
-       ecap0: ecap@100 {
+       ecap0: pwm@100 {
                status = "okay";
                pinctrl-names = "default";
                pinctrl-0 = <&ecap0_pins>;
@@ -534,7 +535,7 @@
                #size-cells = <1>;
                partition@0 {
                        label = "NAND.SPL";
-                       reg = <0x00000000 0x000020000>;
+                       reg = <0x00000000 0x00020000>;
                };
                partition@1 {
                        label = "NAND.SPL.backup1";
@@ -578,19 +579,19 @@
 #include "tps65910.dtsi"
 
 &mcasp1 {
-               pinctrl-names = "default";
-               pinctrl-0 = <&am335x_evm_audio_pins>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcasp1_pins>;
 
-               status = "okay";
+       status = "okay";
 
-               op-mode = <0>;          /* MCASP_IIS_MODE */
-               tdm-slots = <2>;
-               /* 4 serializers */
-               serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
-                       0 0 1 2
-               >;
-               tx-num-evt = <32>;
-               rx-num-evt = <32>;
+       op-mode = <0>;          /* MCASP_IIS_MODE */
+       tdm-slots = <2>;
+       /* 4 serializers */
+       serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
+               0 0 1 2
+       >;
+       tx-num-evt = <32>;
+       rx-num-evt = <32>;
 };
 
 &tps {

diff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts
index b14bf2f..5d96225 100644 (file)
--- a/arch/arm/dts/am335x-evmsk.dts
+++ b/arch/arm/dts/am335x-evmsk.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /*
@@ -32,12 +29,12 @@
                };
        };
 
-       memory {
+       memory@80000000 {
                device_type = "memory";
                reg = <0x80000000 0x10000000>; /* 256 MB */
        };
 
-       vbat: fixedregulator@0 {
+       vbat: fixedregulator0 {
                compatible = "regulator-fixed";
                regulator-name = "vbat";
                regulator-min-microvolt = <5000000>;
@@ -45,13 +42,13 @@
                regulator-boot-on;
        };
 
-       lis3_reg: fixedregulator@1 {
+       lis3_reg: fixedregulator1 {
                compatible = "regulator-fixed";
                regulator-name = "lis3_reg";
                regulator-boot-on;
        };
 
-       wl12xx_vmmc: fixedregulator@2 {
+       wl12xx_vmmc: fixedregulator2 {
                pinctrl-names = "default";
                pinctrl-0 = <&wl12xx_gpio>;
                compatible = "regulator-fixed";
@@ -63,7 +60,7 @@
                enable-active-high;
        };
 
-       vtt_fixed: fixedregulator@3 {
+       vtt_fixed: fixedregulator3 {
                compatible = "regulator-fixed";
                regulator-name = "vtt";
                regulator-min-microvolt = <1500000>;
@@ -80,26 +77,26 @@
 
                compatible = "gpio-leds";
 
-               led@1 {
+               led1 {
                        label = "evmsk:green:usr0";
                        gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
                };
 
-               led@2 {
+               led2 {
                        label = "evmsk:green:usr1";
                        gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
                };
 
-               led@3 {
+               led3 {
                        label = "evmsk:green:mmc0";
                        gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "mmc0";
                        default-state = "off";
                };
 
-               led@4 {
+               led4 {
                        label = "evmsk:green:heartbeat";
                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
@@ -107,36 +104,38 @@
                };
        };
 
-       gpio_buttons: gpio_buttons@0 {
+       gpio_buttons: gpio_buttons0 {
                compatible = "gpio-keys";
+               #address-cells = <1>;
+               #size-cells = <0>;
 
-               switch@1 {
+               switch1 {
                        label = "button0";
                        linux,code = <0x100>;
                        gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
                };
 
-               switch@2 {
+               switch2 {
                        label = "button1";
                        linux,code = <0x101>;
                        gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
                };
 
-               switch@3 {
+               switch3 {
                        label = "button2";
                        linux,code = <0x102>;
                        gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
                        wakeup-source;
                };
 
-               switch@4 {
+               switch4 {
                        label = "button3";
                        linux,code = <0x103>;
                        gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
                };
        };
 
-       backlight {
+       lcd_bl: backlight {
                compatible = "pwm-backlight";
                pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>;
                brightness-levels = <0 58 61 66 75 90 125 170 255>;
@@ -207,234 +206,234 @@
 
        lcd_pins_default: lcd_pins_default {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad8.lcd_data23 */
-                       AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad9.lcd_data22 */
-                       AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad10.lcd_data21 */
-                       AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad11.lcd_data20 */
-                       AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad12.lcd_data19 */
-                       AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad13.lcd_data18 */
-                       AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad14.lcd_data17 */
-                       AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1)     /* gpmc_ad15.lcd_data16 */
-                       AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data0.lcd_data0 */
-                       AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data1.lcd_data1 */
-                       AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data2.lcd_data2 */
-                       AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)     /* lcd_data3.lcd_data3 */
-                       AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data4.lcd_data4 */
-                       AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data5.lcd_data5 */
-                       AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data6.lcd_data6 */
-                       AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)     /* lcd_data7.lcd_data7 */
-                       AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data8.lcd_data8 */
-                       AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data9.lcd_data9 */
-                       AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data10.lcd_data10 */
-                       AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)     /* lcd_data11.lcd_data11 */
-                       AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)     /* lcd_data12.lcd_data12 */
-                       AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)     /* lcd_data13.lcd_data13 */
-                       AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)     /* lcd_data14.lcd_data14 */
-                       AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)     /* lcd_data15.lcd_data15 */
-                       AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)     /* lcd_vsync.lcd_vsync */
-                       AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)     /* lcd_hsync.lcd_hsync */
-                       AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)     /* lcd_pclk.lcd_pclk */
-                       AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)     /* lcd_ac_bias_en.lcd_ac_bias_en */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1)      /* gpmc_ad8.lcd_data23 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1)      /* gpmc_ad9.lcd_data22 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad10.lcd_data21 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad11.lcd_data20 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad12.lcd_data19 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad13.lcd_data18 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad14.lcd_data17 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad15.lcd_data16 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
        lcd_pins_sleep: lcd_pins_sleep {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad8.lcd_data23 */
-                       AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad9.lcd_data22 */
-                       AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad10.lcd_data21 */
-                       AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad11.lcd_data20 */
-                       AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad12.lcd_data19 */
-                       AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad13.lcd_data18 */
-                       AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad14.lcd_data17 */
-                       AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad15.lcd_data16 */
-                       AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7)   /* lcd_data0.lcd_data0 */
-                       AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7)   /* lcd_data1.lcd_data1 */
-                       AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7)   /* lcd_data2.lcd_data2 */
-                       AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7)   /* lcd_data3.lcd_data3 */
-                       AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7)   /* lcd_data4.lcd_data4 */
-                       AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7)   /* lcd_data5.lcd_data5 */
-                       AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7)   /* lcd_data6.lcd_data6 */
-                       AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7)   /* lcd_data7.lcd_data7 */
-                       AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7)   /* lcd_data8.lcd_data8 */
-                       AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7)   /* lcd_data9.lcd_data9 */
-                       AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7)   /* lcd_data10.lcd_data10 */
-                       AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7)   /* lcd_data11.lcd_data11 */
-                       AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7)   /* lcd_data12.lcd_data12 */
-                       AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7)   /* lcd_data13.lcd_data13 */
-                       AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7)   /* lcd_data14.lcd_data14 */
-                       AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7)   /* lcd_data15.lcd_data15 */
-                       AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* lcd_vsync.lcd_vsync */
-                       AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* lcd_hsync.lcd_hsync */
-                       AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* lcd_pclk.lcd_pclk */
-                       AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* lcd_ac_bias_en.lcd_ac_bias_en */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad8.lcd_data23 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad9.lcd_data22 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad10.lcd_data21 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad11.lcd_data20 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad12.lcd_data19 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad13.lcd_data18 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad14.lcd_data17 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad15.lcd_data16 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
 
        user_leds_s0: user_leds_s0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x810, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_ad4.gpio1_4 */
-                       AM33XX_IOPAD(0x814, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_ad5.gpio1_5 */
-                       AM33XX_IOPAD(0x818, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_ad6.gpio1_6 */
-                       AM33XX_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_ad7.gpio1_7 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_OUTPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad4.gpio1_4 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad5.gpio1_5 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_OUTPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad6.gpio1_6 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_OUTPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad7.gpio1_7 */
                >;
        };
 
        gpio_keys_s0: gpio_keys_s0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_oen_ren.gpio2_3 */
-                       AM33XX_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_advn_ale.gpio2_2 */
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_wait0.gpio0_30 */
-                       AM33XX_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ben0_cle.gpio2_5 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7)  /* gpmc_oen_ren.gpio2_3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)    /* gpmc_wait0.gpio0_30 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */
                >;
        };
 
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        clkout2_pin: pinmux_clkout2_pin {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* xdma_event_intr1.clkout2 */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)     /* xdma_event_intr1.clkout2 */
                >;
        };
 
        ecap2_pins: backlight_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x99c, MUX_MODE4)  /* mcasp0_ahclkr.ecap2_in_pwm2_out */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, 0x0, MUX_MODE4)        /* mcasp0_ahclkr.ecap2_in_pwm2_out */
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1 */
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txen.rgmii1_tctl */
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxdv.rgmii1_rctl */
-                       AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd3.rgmii1_td3 */
-                       AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd2.rgmii1_td2 */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd1.rgmii1_td1 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd0.rgmii1_td0 */
-                       AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txclk.rgmii1_tclk */
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxclk.rgmii1_rclk */
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd3.rgmii1_rd3 */
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd2.rgmii1_rd2 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd1.rgmii1_rd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd0.rgmii1_rd0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)   /* mii1_txen.rgmii1_tctl */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)    /* mii1_rxdv.rgmii1_rctl */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd3.rgmii1_td3 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd2.rgmii1_td2 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd1.rgmii1_td1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd0.rgmii1_td0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)  /* mii1_txclk.rgmii1_tclk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)   /* mii1_rxclk.rgmii1_rclk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd3.rgmii1_rd3 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd2.rgmii1_rd2 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd1.rgmii1_rd1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd0.rgmii1_rd0 */
 
                        /* Slave 2 */
-                       AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a0.rgmii2_tctl */
-                       AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a1.rgmii2_rctl */
-                       AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a2.rgmii2_td3 */
-                       AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a3.rgmii2_td2 */
-                       AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a4.rgmii2_td1 */
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a5.rgmii2_td0 */
-                       AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* gpmc_a6.rgmii2_tclk */
-                       AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a7.rgmii2_rclk */
-                       AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a8.rgmii2_rd3 */
-                       AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a9.rgmii2_rd2 */
-                       AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a10.rgmii2_rd1 */
-                       AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* gpmc_a11.rgmii2_rd0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a0.rgmii2_tctl */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a1.rgmii2_rctl */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a2.rgmii2_td3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a3.rgmii2_td2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a4.rgmii2_td1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a5.rgmii2_td0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a6.rgmii2_tclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a7.rgmii2_rclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a8.rgmii2_rd3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a9.rgmii2_rd2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a10.rgmii2_rd1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a11.rgmii2_rd0 */
                >;
        };
 
        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 
                        /* Slave 2 reset value*/
-                       AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* MDIO */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)               /* spi0_cs1.gpio0_6 */
                >;
        };
 
        mcasp1_pins: mcasp1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
-                       AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
                >;
        };
 
        mcasp1_pins_sleep: mcasp1_pins_sleep {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        mmc2_pins: pinmux_mmc2_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
-                       AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
-                       AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
                >;
        };
 
        wl12xx_gpio: pinmux_wl12xx_gpio {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */
                >;
        };
 };
@@ -531,7 +530,7 @@
 &epwmss2 {
        status = "okay";
 
-       ecap2: ecap@100 {
+       ecap2: pwm@100 {
                status = "okay";
                pinctrl-names = "default";
                pinctrl-0 = <&ecap2_pins>;
@@ -722,7 +721,7 @@
 };
 
 &lcdc {
-      status = "okay";
+       status = "okay";
 };
 
 &rtc {

diff --git a/arch/arm/dts/am335x-guardian.dts b/arch/arm/dts/am335x-guardian.dts
index 067c402..c2fd610 100644 (file)
--- a/arch/arm/dts/am335x-guardian.dts
+++ b/arch/arm/dts/am335x-guardian.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  * Copyright (C) 2018 Robert Bosch Power Tools GmbH
  */
 /dts-v1/;
@@ -29,10 +29,10 @@
                reg = <0x80000000 0x10000000>; /* 256 MB */
        };
 
-       gpio_keys {
-               compatible = "gpio-keys";
+       guardian_buttons: gpio-keys {
                pinctrl-names = "default";
                pinctrl-0 = <&guardian_button_pins>;
+               compatible = "gpio-keys";
 
                select-button {
                        label = "guardian-select-button";
@@ -49,10 +49,10 @@
                };
        };
 
-       leds {
-               compatible = "gpio-leds";
+       guardian_leds: gpio-leds {
                pinctrl-names = "default";
                pinctrl-0 = <&guardian_led_pins>;
+               compatible = "gpio-leds";
 
                life-led {
                        label = "guardian:life-led";
@@ -98,7 +98,7 @@
 
        };
 
-       pwm7: dmtimer-pwm {
+       pwm7: pwm-7 {
                compatible = "ti,omap-dmtimer-pwm";
                ti,timers = <&timer7>;
                pinctrl-names = "default";

diff --git a/arch/arm/dts/am335x-icev2.dts b/arch/arm/dts/am335x-icev2.dts
index 2a1b3a5..a542724 100644 (file)
--- a/arch/arm/dts/am335x-icev2.dts
+++ b/arch/arm/dts/am335x-icev2.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /*
@@ -24,12 +21,12 @@
                tick-timer = &timer2;
        };
 
-       memory {
+       memory@80000000 {
                device_type = "memory";
                reg = <0x80000000 0x10000000>; /* 256 MB */
        };
 
-       vbat: fixedregulator@0 {
+       vbat: fixedregulator0 {
                compatible = "regulator-fixed";
                regulator-name = "vbat";
                regulator-min-microvolt = <5000000>;
@@ -37,7 +34,7 @@
                regulator-boot-on;
        };
 
-       vtt_fixed: fixedregulator@1 {
+       vtt_fixed: fixedregulator1 {
                compatible = "regulator-fixed";
                regulator-name = "vtt";
                regulator-min-microvolt = <1500000>;
@@ -48,52 +45,51 @@
                enable-active-high;
        };
 
-       leds@0 {
+       leds-iio {
                compatible = "gpio-leds";
-
-               led@0 {
+               led-out0 {
                        label = "out0";
                        gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
                };
 
-               led@1 {
+               led-out1 {
                        label = "out1";
                        gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
                };
 
-               led@2 {
+               led-out2 {
                        label = "out2";
                        gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
                };
 
-               led@3 {
+               led-out3 {
                        label = "out3";
                        gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
                };
 
-               led@4 {
+               led-out4 {
                        label = "out4";
                        gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
                };
 
-               led@5 {
+               led-out5 {
                        label = "out5";
                        gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
                };
 
-               led@6 {
+               led-out6 {
                        label = "out6";
                        gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
                };
 
-               led@7 {
+               led-out7 {
                        label = "out7";
                        gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
@@ -101,44 +97,44 @@
        };
 
        /* Tricolor status LEDs */
-       leds@1 {
+       leds1 {
                compatible = "gpio-leds";
                pinctrl-names = "default";
                pinctrl-0 = <&user_leds>;
 
-               led@0 {
+               led0 {
                        label = "status0:red:cpu0";
                        gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
                        linux,default-trigger = "cpu0";
                };
 
-               led@1 {
+               led1 {
                        label = "status0:green:usr";
                        gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
                };
 
-               led@2 {
+               led2 {
                        label = "status0:yellow:usr";
                        gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
                };
 
-               led@3 {
+               led3 {
                        label = "status1:red:mmc0";
                        gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
                        linux,default-trigger = "mmc0";
                };
 
-               led@4 {
+               led4 {
                        label = "status1:green:usr";
                        gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
                };
 
-               led@5 {
+               led5 {
                        label = "status1:yellow:usr";
                        gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
@@ -149,31 +145,31 @@
 &am33xx_pinmux {
        user_leds: user_leds {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
-                       AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
-                       AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
-                       AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
-                       AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
-                       AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
                >;
        };
 
        mmc0_pins_default: mmc0_pins_default {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
-                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
-                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
                        AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */
                >;
        };
 
        i2c0_pins_default: i2c0_pins_default {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
                >;
        };
 
@@ -188,71 +184,71 @@
 
        uart3_pins_default: uart3_pins_default {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
-                       AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1, RMII mode */
-                       AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLUP | MUX_MODE1))     /* mii1_crs.rmii1_crs_dv */
-                       AM33XX_IOPAD(0x944, (PIN_INPUT_PULLUP | MUX_MODE0))     /* rmii1_refclk.rmii1_refclk */
-                       AM33XX_IOPAD(0x940, (PIN_INPUT_PULLUP | MUX_MODE1))     /* mii1_rxd0.rmii1_rxd0 */
-                       AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLUP | MUX_MODE1))     /* mii1_rxd1.rmii1_rxd1 */
-                       AM33XX_IOPAD(0x910, (PIN_INPUT_PULLUP | MUX_MODE1))     /* mii1_rxerr.rmii1_rxerr */
-                       AM33XX_IOPAD(0x928, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))  /* mii1_txd0.rmii1_txd0 */
-                       AM33XX_IOPAD(0x924, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))  /* mii1_txd1.rmii1_txd1 */
-                       AM33XX_IOPAD(0x914, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))  /* mii1_txen.rmii1_txen */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1)        /* mii1_crs.rmii1_crs_dv */
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)      /* mii1_rxerr.rmii1_rxerr */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)    /* mii1_txd0.rmii1_txd0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)    /* mii1_txd1.rmii1_txd1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)   /* mii1_txen.rmii1_txen */
                        /* Slave 2, RMII mode */
-                       AM33XX_IOPAD(0x870, (PIN_INPUT_PULLUP | MUX_MODE3))     /* gpmc_wait0.rmii2_crs_dv */
-                       AM33XX_IOPAD(0x908, (PIN_INPUT_PULLUP | MUX_MODE1))     /* mii1_col.rmii2_refclk */
-                       AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLUP | MUX_MODE3))     /* gpmc_a11.rmii2_rxd0 */
-                       AM33XX_IOPAD(0x868, (PIN_INPUT_PULLUP | MUX_MODE3))     /* gpmc_a10.rmii2_rxd1 */
-                       AM33XX_IOPAD(0x874, (PIN_INPUT_PULLUP | MUX_MODE3))     /* gpmc_wpn.rmii2_rxerr */
-                       AM33XX_IOPAD(0x854, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))  /* gpmc_a5.rmii2_txd0 */
-                       AM33XX_IOPAD(0x850, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))  /* gpmc_a4.rmii2_txd1 */
-                       AM33XX_IOPAD(0x840, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))  /* gpmc_a0.rmii2_txen */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE3)      /* gpmc_wait0.rmii2_crs_dv */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE1)        /* mii1_col.rmii2_refclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE3)        /* gpmc_a11.rmii2_rxd0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE3)        /* gpmc_a10.rmii2_rxd1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE3)        /* gpmc_wpn.rmii2_rxerr */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3)      /* gpmc_a5.rmii2_txd0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3)      /* gpmc_a4.rmii2_txd1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)      /* gpmc_a0.rmii2_txen */
                >;
        };
 
        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x944, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x910, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
 
                        /* Slave 2 reset value */
-                       AM33XX_IOPAD(0x870, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x908, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x868, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x874, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x854, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x850, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x840, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* MDIO */
-                       AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0))     /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0))                    /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7))
-                       AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 };
@@ -276,6 +272,56 @@
        };
 };
 
+&spi0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&spi0_pins_default>;
+
+       sn65hvs882@1 {
+               compatible = "pisosr-gpio";
+               gpio-controller;
+               #gpio-cells = <2>;
+
+               load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
+
+               reg = <1>;
+               spi-max-frequency = <1000000>;
+               spi-cpol;
+       };
+
+       spi_nor: flash@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "winbond,w25q64", "jedec,spi-nor";
+               spi-max-frequency = <80000000>;
+               m25p,fast-read;
+               reg = <0>;
+
+               partition@0 {
+                       label = "u-boot-spl";
+                       reg = <0x0 0x80000>;
+                       read-only;
+               };
+
+               partition@1 {
+                       label = "u-boot";
+                       reg = <0x80000 0x100000>;
+                       read-only;
+               };
+
+               partition@2 {
+                       label = "u-boot-env";
+                       reg = <0x180000 0x20000>;
+                       read-only;
+               };
+
+               partition@3 {
+                       label = "misc";
+                       reg = <0x1A0000 0x660000>;
+               };
+       };
+};
+
 #include "tps65910.dtsi"
 
 &tps {
@@ -381,16 +427,17 @@
 };
 
 &gpio3 {
-       p4 {
+       pr1-mii-ctl-hog {
                gpio-hog;
                gpios = <4 GPIO_ACTIVE_HIGH>;
                output-high;
                line-name = "PR1_MII_CTRL";
        };
 
-       p10 {
+       mux-mii-hog {
                gpio-hog;
                gpios = <10 GPIO_ACTIVE_HIGH>;
+               /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */
                output-high;
                line-name = "MUX_MII_CTRL";
        };
@@ -437,52 +484,3 @@
        };
 };
 
-&spi0 {
-       status = "okay";
-       pinctrl-names = "default";
-       pinctrl-0 = <&spi0_pins_default>;
-
-       sn65hvs882@1 {
-               compatible = "pisosr-gpio";
-               gpio-controller;
-               #gpio-cells = <2>;
-
-               load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
-
-               reg = <1>;
-               spi-max-frequency = <1000000>;
-               spi-cpol;
-       };
-
-       spi_nor: flash@0 {
-               #address-cells = <1>;
-               #size-cells = <1>;
-               compatible = "winbond,w25q64", "jedec,spi-nor";
-               spi-max-frequency = <80000000>;
-               m25p,fast-read;
-               reg = <0>;
-
-               partition@0 {
-                       label = "u-boot-spl";
-                       reg = <0x0 0x80000>;
-                       read-only;
-               };
-
-               partition@1 {
-                       label = "u-boot";
-                       reg = <0x80000 0x100000>;
-                       read-only;
-               };
-
-               partition@2 {
-                       label = "u-boot-env";
-                       reg = <0x180000 0x20000>;
-                       read-only;
-               };
-
-               partition@3 {
-                       label = "misc";
-                       reg = <0x1A0000 0x660000>;
-               };
-       };
-};

diff --git a/arch/arm/dts/am335x-igep0033.dtsi b/arch/arm/dts/am335x-igep0033.dtsi
index f102f6a..ad57c74 100644 (file)
--- a/arch/arm/dts/am335x-igep0033.dtsi
+++ b/arch/arm/dts/am335x-igep0033.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x
  *
  * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 /dts-v1/;
@@ -57,41 +54,41 @@
 &am33xx_pinmux {
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        nandflash_pins: pinmux_nandflash_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad0.gpmc_ad0 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad1.gpmc_ad1 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad2.gpmc_ad2 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad3.gpmc_ad3 */
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad4.gpmc_ad4 */
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad5.gpmc_ad5 */
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad6.gpmc_ad6 */
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad7.gpmc_ad7 */
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_wait0.gpmc_wait0 */
-                       AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7)       /* gpmc_wpn.gpio0_30 */
-                       AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_csn0.gpmc_csn0 */
-                       AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)             /* gpmc_advn_ale.gpmc_advn_ale */
-                       AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)             /* gpmc_oen_ren.gpmc_oen_ren */
-                       AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)             /* gpmc_wen.gpmc_wen */
-                       AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_be0n_cle.gpmc_be0n_cle */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7)        /* gpmc_wpn.gpio0_31 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        leds_pins: pinmux_leds_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_a7.gpio1_23 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a7.gpio1_23 */
                >;
        };
 };
@@ -174,7 +171,7 @@
                /* MTD partition table */
                partition@0 {
                        label = "SPL";
-                       reg = <0x00000000 0x000080000>;
+                       reg = <0x00000000 0x00080000>;
                };
 
                partition@1 {
@@ -194,7 +191,7 @@
 
                partition@4 {
                        label = "File System";
-                       reg = <0x00780000 0x007880000>;
+                       reg = <0x00780000 0x07880000>;
                };
        };
 };

diff --git a/arch/arm/dts/am335x-osd335x-common.dtsi b/arch/arm/dts/am335x-osd335x-common.dtsi
index 2b55b7d..7cf4e9f 100644 (file)
--- a/arch/arm/dts/am335x-osd335x-common.dtsi
+++ b/arch/arm/dts/am335x-osd335x-common.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  *
  * Author: Robert Nelson <robertcnelson@gmail.com>
  */
@@ -36,8 +36,8 @@
 &am33xx_pinmux {
        i2c0_pins: pinmux-i2c0-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* (C17) I2C0_SDA.I2C0_SDA */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* (C16) I2C0_SCL.I2C0_SCL */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 };

diff --git a/arch/arm/dts/am335x-pdu001.dts b/arch/arm/dts/am335x-pdu001.dts
index ae43d61..5820324 100644 (file)
--- a/arch/arm/dts/am335x-pdu001.dts
+++ b/arch/arm/dts/am335x-pdu001.dts
@@ -5,7 +5,7 @@
  *
  * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
  *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
  *
  * SPDX-License-Identifier:  GPL-2.0+
  */
@@ -92,162 +92,162 @@
 
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        i2c1_pins: pinmux_i2c1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2)       /* spi0_d1.i2c1_sda */
-                       AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2)       /* spi0_cs0.i2c1_scl */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2)        /* spi0_cs0.i2c1_scl */
                >;
        };
 
        i2c2_pins: pinmux_i2c2_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE2)       /* spi0_clk.i2c2_sda */
-                       AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE2)       /* spi0_d0.i2c2_scl */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE2)       /* spi0_clk.i2c2_sda */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d0.i2c2_scl */
                >;
        };
 
        spi1_pins: pinmux_spi1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE3)             /* mcasp0_aclkx.spi1_sclk */
-                       AM33XX_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3)             /* mcasp0_fsx.spi1_d0 */
-                       AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE3)     /* mcasp0_axr0.spi1_d1 */
-                       AM33XX_IOPAD(0x99C, PIN_OUTPUT | MUX_MODE3)             /* mcasp0_ahclkr.spi1_cs0 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT, MUX_MODE3)          /* mcasp0_aclkx.spi1_sclk */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT, MUX_MODE3)            /* mcasp0_fsx.spi1_d0 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE3)   /* mcasp0_axr0.spi1_d1 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE3)         /* mcasp0_ahclkr.spi1_cs0 */
                >;
        };
 
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x96C, PIN_OUTPUT | MUX_MODE7)             /* uart0_rtsn.gpio1_9 */
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart1_pins: pinmux_uart1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart1_rxd.uart1_rxd */
-                       AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart1_txd.uart1_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart3_pins: pinmux_uart3_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE1)       /* spi0_cs1.uart3_rxd */
-                       AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* ecap0_in_pwm0_out.uart3_txd */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1)        /* spi0_cs1.uart3_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1)    /* ecap0_in_pwm0_out.uart3_txd */
                >;
        };
 
        clkout2_pin: pinmux_clkout2_pin {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* xdma_event_intr1.clkout2 */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)     /* xdma_event_intr1.clkout2 */
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Port 1 (emac0) */
-                       AM33XX_IOPAD(0x908, PIN_INPUT | MUX_MODE0)              /* mii1_col.mii1_col */
-                       AM33XX_IOPAD(0x90C, PIN_INPUT | MUX_MODE0)              /* mii1_crs.mii1_crs */
-                       AM33XX_IOPAD(0x910, PIN_INPUT | MUX_MODE0)              /* mii1_rxer.mii1_rxer */
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE0)             /* mii1_txen.mii1_txen */
-                       AM33XX_IOPAD(0x918, PIN_INPUT | MUX_MODE0)              /* mii1_rxdv.mii1_rxdv */
-                       AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE0)             /* mii1_txd3.mii1_txd3 */
-                       AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE0)             /* mii1_txd2.mii1_txd2 */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE0)             /* mii1_txd1.mii1_txd1 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE0)             /* mii1_txd0.mii1_txd0 */
-                       AM33XX_IOPAD(0x92c, PIN_INPUT | MUX_MODE0)              /* mii1_txclk.mii1_txclk */
-                       AM33XX_IOPAD(0x930, PIN_INPUT | MUX_MODE0)              /* mii1_rxclk.mii1_rxclk */
-                       AM33XX_IOPAD(0x934, PIN_INPUT | MUX_MODE0)              /* mii1_rxd3.mii1_rxd3 */
-                       AM33XX_IOPAD(0x938, PIN_INPUT | MUX_MODE0)              /* mii1_rxd2.mii1_rxd2 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT | MUX_MODE0)              /* mii1_rxd1.mii1_rxd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE0)              /* mii1_rxd0.mii1_rxd0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT, MUX_MODE0)
 
                        /* Port 2 (emac1) */
-                       AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1)             /* mii2_txen.gpmc_a0 */
-                       AM33XX_IOPAD(0x844, PIN_INPUT | MUX_MODE1)              /* mii2_rxdv.gpmc_a1 */
-                       AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1)             /* mii2_txd3.gpmc_a2 */
-                       AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1)             /* mii2_txd2.gpmc_a3 */
-                       AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1)             /* mii2_txd1.gpmc_a4 */
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1)             /* mii2_txd0.gpmc_a5 */
-                       AM33XX_IOPAD(0x858, PIN_INPUT | MUX_MODE1)              /* mii2_txclk.gpmc_a6 */
-                       AM33XX_IOPAD(0x85c, PIN_INPUT | MUX_MODE1)              /* mii2_rxclk.gpmc_a7 */
-                       AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE1)              /* mii2_rxd3.gpmc_a8 */
-                       AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE1)              /* mii2_rxd2.gpmc_a9 */
-                       AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE1)              /* mii2_rxd1.gpmc_a10 */
-                       AM33XX_IOPAD(0x86C, PIN_INPUT | MUX_MODE1)              /* mii2_rxd0.gpmc_a11 */
-                       AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE1)              /* mii2_crs.gpmc_wait0 */
-                       AM33XX_IOPAD(0x874, PIN_INPUT | MUX_MODE1)              /* mii2_rxer.gpmc_wpn */
-                       AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE1)              /* mii2_col.gpmc_ben1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1)               /* mii2_txen.gpmc_a0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT, MUX_MODE1)                /* mii2_rxdv.gpmc_a1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1)               /* mii2_txd3.gpmc_a2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1)               /* mii2_txd2.gpmc_a3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1)               /* mii2_txd1.gpmc_a4 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1)               /* mii2_txd0.gpmc_a5 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT, MUX_MODE1)                /* mii2_txclk.gpmc_a6 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT, MUX_MODE1)                /* mii2_rxclk.gpmc_a7 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE1)                /* mii2_rxd3.gpmc_a8 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE1)                /* mii2_rxd2.gpmc_a9 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE1)               /* mii2_rxd1.gpmc_a10 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE1)               /* mii2_rxd0.gpmc_a11 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT, MUX_MODE1)             /* mii2_crs.gpmc_wait0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT, MUX_MODE1)               /* mii2_rxer.gpmc_wpn */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT, MUX_MODE1)              /* mii2_col.gpmc_ben1 */
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        mmc1_pins: pinmux_mmc1_pins {
                /* eMMC */
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat3 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat2 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat1 */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat0 */
-                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_clk */
-                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        mmc2_pins: pinmux_mmc2_pins {
                /* SD cardcage */
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad3.mmc1_dat3 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad2.mmc1_dat2 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad1.mmc1_dat1 */
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad0.mmc1_dat0 */
-                       AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2)       /* gpmc_csn1.mmc1_clk */
-                       AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)       /* gpmc_csn2.mmc1_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad3.mmc1_dat3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad2.mmc1_dat2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad1.mmc1_dat1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad0.mmc1_dat0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)       /* gpmc_csn1.mmc1_clk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)       /* gpmc_csn2.mmc1_cmd */
                        /* card change signal for frontpanel SD cardcage */
-                       AM33XX_IOPAD(0x890, PIN_INPUT | MUX_MODE7)              /* gpmc_advn_ale.gpio2_2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT, MUX_MODE7)          /* gpmc_advn_ale.gpio2_2 */
                >;
        };
 
        lcd_pins_s0: lcd_pins_s0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data0.lcd_data0 */
-                       AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data1.lcd_data1 */
-                       AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data2.lcd_data2 */
-                       AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)             /* lcd_data3.lcd_data3 */
-                       AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data4.lcd_data4 */
-                       AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data5.lcd_data5 */
-                       AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data6.lcd_data6 */
-                       AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)             /* lcd_data7.lcd_data7 */
-                       AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data8.lcd_data8 */
-                       AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data9.lcd_data9 */
-                       AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data10.lcd_data10 */
-                       AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)             /* lcd_data11.lcd_data11 */
-                       AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data12.lcd_data12 */
-                       AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data13.lcd_data13 */
-                       AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data14.lcd_data14 */
-                       AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)             /* lcd_data15.lcd_data15 */
-                       AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)             /* lcd_vsync.lcd_vsync */
-                       AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)             /* lcd_hsync.lcd_hsync */
-                       AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)             /* lcd_pclk.lcd_pclk */
-                       AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)             /* lcd_ac_bias_en.lcd_ac_bias_en */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
        dcan0_pins: pinmux_dcan0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2)             /* uart1_ctsn.d_can0_tx */
-                       AM33XX_IOPAD(0x97c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* uart1_rtsn.d_can0_rx */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2)            /* uart1_ctsn.d_can0_tx */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2)    /* uart1_rtsn.d_can0_rx */
                >;
        };
 };
@@ -353,7 +353,7 @@
                };
        };
 
-       mcp79400: mcp79400@6f {
+       mcp79400: rtc@6f {
                compatible = "microchip,mcp7940x";
                reg = <0x6f>;
        };

diff --git a/arch/arm/dts/am335x-phycore-som.dtsi b/arch/arm/dts/am335x-phycore-som.dtsi
index 8d7c19e..3f9a4ea 100644 (file)
--- a/arch/arm/dts/am335x-phycore-som.dtsi
+++ b/arch/arm/dts/am335x-phycore-som.dtsi
@@ -1,11 +1,7 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2015 Phytec Messtechnik GmbH
  * Author: Teresa Remmet <t.remmet@phytec.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include "am33xx.dtsi"
@@ -31,17 +27,13 @@
                reg = <0x80000000 0x10000000>; /* 256 MB */
        };
 
-       regulators {
-               compatible = "simple-bus";
-
-               vcc5v: fixedregulator0 {
-                       compatible = "regulator-fixed";
-                       regulator-name = "vcc5v";
-                       regulator-min-microvolt = <5000000>;
-                       regulator-max-microvolt = <5000000>;
-                       regulator-boot-on;
-                       regulator-always-on;
-               };
+       vcc5v: fixedregulator0 {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc5v";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-boot-on;
+               regulator-always-on;
        };
 };
 
@@ -58,22 +50,22 @@
 &am33xx_pinmux {
        ethernet0_pins: pinmux_ethernet0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* mii1_crs.rmii1_crs_dv */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* mii1_rxerr.rmii1_rxerr */
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1)             /* mii1_txen.rmii1_txen */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1)             /* mii1_txd1.rmii1_txd1 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1)             /* mii1_txd0.rmii1_txd0 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* mii1_rxd1.rmii1_rxd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* mii1_rxd0.rmii1_rxd0 */
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* rmii1_refclk.rmii1_refclk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        mdio_pins: pinmux_mdio {
                pinctrl-single,pins = <
                        /* MDIO */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 };
@@ -105,8 +97,8 @@
 &am33xx_pinmux {
        i2c0_pins: pinmux_i2c0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0)      /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0)      /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
                >;
        };
 };
@@ -145,20 +137,20 @@
 &am33xx_pinmux {
                nandflash_pins: pinmux_nandflash {
                        pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad0.gpmc_ad0 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad1.gpmc_ad1 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad2.gpmc_ad2 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad3.gpmc_ad3 */
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad4.gpmc_ad4 */
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad5.gpmc_ad5 */
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad6.gpmc_ad6 */
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad7.gpmc_ad7 */
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_wait0.gpmc_wait0 */
-                       AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_csn0.gpmc_csn0 */
-                       AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)             /* gpmc_advn_ale.gpmc_advn_ale */
-                       AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)             /* gpmc_oen_ren.gpmc_oen_ren */
-                       AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)             /* gpmc_wen.gpmc_wen */
-                       AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_be0n_cle.gpmc_be0n_cle */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 };
@@ -297,10 +289,10 @@
 &am33xx_pinmux {
        spi0_pins: pinmux_spi0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* spi0_clk.spi0_clk */
-                       AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* spi0_d0.spi0_d0 */
-                       AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)       /* spi0_d1.spi0_d1 */
-                       AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0)       /* spi0_cs0.spi0_cs0 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 };
@@ -310,7 +302,7 @@
        pinctrl-0 = <&spi0_pins>;
        status = "okay";
 
-       serial_flash: m25p80@0 {
+       serial_flash: flash@0 {
                compatible = "jedec,spi-nor";
                spi-max-frequency = <48000000>;
                reg = <0x0>;

diff --git a/arch/arm/dts/am335x-pocketbeagle.dts b/arch/arm/dts/am335x-pocketbeagle.dts
index 62fe5ca..b379e3a 100644 (file)
--- a/arch/arm/dts/am335x-pocketbeagle.dts
+++ b/arch/arm/dts/am335x-pocketbeagle.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  *
  * Author: Robert Nelson <robertcnelson@gmail.com>
  */
@@ -23,28 +23,28 @@
 
                compatible = "gpio-leds";
 
-               usr0 {
+               led-usr0 {
                        label = "beaglebone:green:usr0";
                        gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
                        default-state = "off";
                };
 
-               usr1 {
+               led-usr1 {
                        label = "beaglebone:green:usr1";
                        gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "mmc0";
                        default-state = "off";
                };
 
-               usr2 {
+               led-usr2 {
                        label = "beaglebone:green:usr2";
                        gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "cpu0";
                        default-state = "off";
                };
 
-               usr3 {
+               led-usr3 {
                        label = "beaglebone:green:usr3";
                        gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
@@ -62,74 +62,74 @@
 &am33xx_pinmux {
        i2c2_pins: pinmux-i2c2-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3)       /* (D17) uart1_rtsn.I2C2_SCL */
-                       AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3)       /* (D18) uart1_ctsn.I2C2_SDA */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)      /* (D17) uart1_rtsn.I2C2_SCL */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)      /* (D18) uart1_ctsn.I2C2_SDA */
                >;
        };
 
        ehrpwm0_pins: pinmux-ehrpwm0-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* (A13) mcasp0_aclkx.ehrpwm0A */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (A13) mcasp0_aclkx.ehrpwm0A */
                >;
        };
 
        ehrpwm1_pins: pinmux-ehrpwm1-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE6)    /* (U14) gpmc_a2.ehrpwm1A */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE6)      /* (U14) gpmc_a2.ehrpwm1A */
                >;
        };
 
        mmc0_pins: pinmux-mmc0-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7)              /* (C15) spi0_cs1.gpio0[6] */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)       /* (G16) mmc0_dat0.mmc0_dat0 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)       /* (G15) mmc0_dat1.mmc0_dat1 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)       /* (F18) mmc0_dat2.mmc0_dat2 */
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)       /* (F17) mmc0_dat3.mmc0_dat3 */
-                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)       /* (G18) mmc0_cmd.mmc0_cmd */
-                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)       /* (G17) mmc0_clk.mmc0_clk */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)               /* (C15) spi0_cs1.gpio0[6] */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
                        AM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4)              /* (B12) mcasp0_aclkr.mmc0_sdwp */
                >;
        };
 
        spi0_pins: pinmux-spi0-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0)       /* (A17) spi0_sclk.spi0_sclk */
-                       AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0)       /* (B17) spi0_d0.spi0_d0 */
-                       AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)       /* (B16) spi0_d1.spi0_d1 */
-                       AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0)       /* (A16) spi0_cs0.spi0_cs0 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        spi1_pins: pinmux-spi1-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x964, PIN_INPUT_PULLUP | MUX_MODE4)       /* (C18) eCAP0_in_PWM0_out.spi1_sclk */
-                       AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE4)       /* (E18) uart0_ctsn.spi1_d0 */
-                       AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE4)       /* (E17) uart0_rtsn.spi1_d1 */
-                       AM33XX_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE4)       /* (A15) xdma_event_intr0.spi1_cs1 */
+                       AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4)       /* (C18) eCAP0_in_PWM0_out.spi1_sclk */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4)      /* (E18) uart0_ctsn.spi1_d0 */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4)      /* (E17) uart0_rtsn.spi1_d1 */
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE4)        /* (A15) xdma_event_intr0.spi1_cs1 */
                >;
        };
 
        usr_leds_pins: pinmux-usr-leds-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7)             /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */
-                       AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7)             /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */
-                       AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7)             /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */
-                       AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7)             /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)               /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)               /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7)               /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7)               /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */
                >;
        };
 
        uart0_pins: pinmux-uart0-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* (E15) uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* (E16) uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart4_pins: pinmux-uart4-pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6)       /* (T17) gpmc_wait0.uart4_rxd */
-                       AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6)    /* (U17) gpmc_wpn.uart4_txd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)      /* (T17) gpmc_wait0.uart4_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6)     /* (U17) gpmc_wpn.uart4_txd */
                >;
        };
 };

diff --git a/arch/arm/dts/am335x-pxm2.dtsi b/arch/arm/dts/am335x-pxm2.dtsi
index 645d221..a51d6ac 100644 (file)
--- a/arch/arm/dts/am335x-pxm2.dtsi
+++ b/arch/arm/dts/am335x-pxm2.dtsi
@@ -148,7 +148,7 @@
 &epwmss0 {
        status = "okay";
 
-       ecap0: ecap@100 {
+       ecap0: pwm@100 {
                status = "okay";
                pinctrl-names = "default";
                pinctrl-0 = <&ecap0_pins>;

diff --git a/arch/arm/dts/am335x-regor.dtsi b/arch/arm/dts/am335x-regor.dtsi
index 86b3f07..6fbf4ac 100644 (file)
--- a/arch/arm/dts/am335x-regor.dtsi
+++ b/arch/arm/dts/am335x-regor.dtsi
@@ -41,8 +41,8 @@
 &am33xx_pinmux {
        user_leds_pins: pinmux_user_leds {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8E0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* lcd_hsync.gpio2_22 */
-                       AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* mcasp0_fsx.gpio3_15 */
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7)    /* lcd_hsync.gpio2_22 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7)   /* mcasp0_fsx.gpio3_15 */
                >;
        };
 };
@@ -51,8 +51,8 @@
 &am33xx_pinmux {
        dcan1_pins: pinmux_dcan1 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2)      /* uart0_ctsn.d_can1_tx */
-                       AM33XX_IOPAD(0x96C, PIN_INPUT_PULLUP | MUX_MODE2)       /* uart0_rtsn.d_can1_rx */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2)     /* uart0_ctsn.d_can1_tx */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2)      /* uart0_rtsn.d_can1_rx */
                >;
        };
 };
@@ -67,20 +67,20 @@
 &am33xx_pinmux {
        ethernet1_pins: pinmux_ethernet1 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a0.mii2_txen */
-                       AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a1.mii2_rxdv */
-                       AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a2.mii2_txd3 */
-                       AM33XX_IOPAD(0x84C, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a3.mii2_txd2 */
-                       AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a4.mii2_txd1 */
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a5.mii2_txd0 */
-                       AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a6.mii2_txclk */
-                       AM33XX_IOPAD(0x85C, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a7.mii2_rxclk */
-                       AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a8.mii2_rxd3 */
-                       AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1)      /* gpmc_a9.mii2_rxd2 */
-                       AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a10.mii2_rxd1 */
-                       AM33XX_IOPAD(0x86C, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a11.mii2_rxd0 */
-                       AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_wpn.mii2_rxerr */
-                       AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_ben1.mii2_col */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a0.mii2_txen */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a1.mii2_rxdv */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a2.mii2_txd3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a3.mii2_txd2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a4.mii2_txd1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a5.mii2_txd0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a6.mii2_txclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a7.mii2_rxclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a8.mii2_rxd3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1)        /* gpmc_a9.mii2_rxd2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* gpmc_a10.mii2_rxd1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* gpmc_a11.mii2_rxd0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* gpmc_wpn.mii2_rxerr */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1)     /* gpmc_ben1.mii2_col */
                >;
        };
 };
@@ -112,15 +112,15 @@
        user_gpios_pins: pinmux_user_gpios {
                pinctrl-single,pins = <
                        /* DIGIN 1-4 */
-                       AM33XX_IOPAD(0x82C, PIN_INPUT | MUX_MODE7)              /* gpmc_ad11.gpio0_27 */
-                       AM33XX_IOPAD(0x828, PIN_INPUT | MUX_MODE7)              /* gpmc_ad10.gpio0_26 */
-                       AM33XX_IOPAD(0x824, PIN_INPUT | MUX_MODE7)              /* gpmc_ad9.gpio0_23 */
-                       AM33XX_IOPAD(0x820, PIN_INPUT | MUX_MODE7)              /* gpmc_ad8.gpio0_22 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT, MUX_MODE7)              /* gpmc_ad11.gpio0_27 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT, MUX_MODE7)              /* gpmc_ad10.gpio0_26 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT, MUX_MODE7)               /* gpmc_ad9.gpio0_23 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT, MUX_MODE7)               /* gpmc_ad8.gpio0_22 */
                        /* DIGOUT 1-4 */
-                       AM33XX_IOPAD(0x83C, PIN_OUTPUT | MUX_MODE7)             /* gpmc_ad15.gpio1_15 */
-                       AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE7)             /* gpmc_ad14.gpio1_14 */
-                       AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE7)             /* gpmc_ad13.gpio1_13 */
-                       AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE7)             /* gpmc_ad12.gpio1_12 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE7)             /* gpmc_ad15.gpio1_15 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE7)             /* gpmc_ad14.gpio1_14 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE7)             /* gpmc_ad13.gpio1_13 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE7)             /* gpmc_ad12.gpio1_12 */
                >;
        };
 };
@@ -129,13 +129,13 @@
 &am33xx_pinmux {
        mmc1_pins: pinmux_mmc1 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8F0, PIN_INPUT_PULLUP | MUX_MODE0)
-                       AM33XX_IOPAD(0x8F4, PIN_INPUT_PULLUP | MUX_MODE0)
-                       AM33XX_IOPAD(0x8F8, PIN_INPUT_PULLUP | MUX_MODE0)
-                       AM33XX_IOPAD(0x8FC, PIN_INPUT_PULLUP | MUX_MODE0)
-                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)
-                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)
-                       AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7)       /* spi0_cs1.mmc0_sdcd */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7)        /* spi0_cs1.mmc0_sdcd */
                >;
        };
 };
@@ -158,15 +158,15 @@
 &am33xx_pinmux {
        uart0_pins: pinmux_uart0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart2_pins: pinmux_uart2 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x92C, PIN_INPUT_PULLUP | MUX_MODE1)       /* mii1_tx_clk.uart2_rxd */
-                       AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_rx_clk.uart2_txd */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1)     /* mii1_tx_clk.uart2_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1)  /* mii1_rx_clk.uart2_txd */
                >;
        };
 };
@@ -187,9 +187,9 @@
 &am33xx_pinmux {
        uart1_rs485_pins: pinmux_uart1_rs485_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)
-                       AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 };

diff --git a/arch/arm/dts/am335x-rut.dts b/arch/arm/dts/am335x-rut.dts
index cc06f5d..7760b97 100644 (file)
--- a/arch/arm/dts/am335x-rut.dts
+++ b/arch/arm/dts/am335x-rut.dts
@@ -174,7 +174,7 @@
 &epwmss0 {
        status = "okay";
 
-       ecap0: ecap@100 {
+       ecap0: pwm@100 {
                status = "okay";
                pinctrl-names = "default";
                pinctrl-0 = <&ecap0_pins>;

diff --git a/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts
index 246a1a9..a2676d1 100644 (file)
--- a/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts
+++ b/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts
@@ -23,7 +23,7 @@
                regulator-name = "wlan-en-regulator";
                regulator-min-microvolt = <3300000>;
                regulator-max-microvolt = <3300000>;
-               startup-delay-us= <100000>;
+               startup-delay-us = <100000>;
        };
 };
 

diff --git a/arch/arm/dts/am335x-shc.dts b/arch/arm/dts/am335x-shc.dts
index a41a060..b44b159 100644 (file)
--- a/arch/arm/dts/am335x-shc.dts
+++ b/arch/arm/dts/am335x-shc.dts
@@ -36,10 +36,10 @@
                };
        };
 
-       gpio_keys {
+       gpio-keys {
                compatible = "gpio-keys";
 
-               back_button {
+               back-button {
                        label = "Back Button";
                        gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
                        linux,code = <KEY_BACK>;
@@ -47,7 +47,7 @@
                        wakeup-source;
                };
 
-               front_button {
+               front-button {
                        label = "Front Button";
                        gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
                        linux,code = <KEY_FRONT>;
@@ -144,14 +144,14 @@
 };
 
 &gpio1 {
-       hmtc_rst {
+       hmtc-rst-hog {
                gpio-hog;
                gpios = <24 GPIO_ACTIVE_LOW>;
                output-high;
                line-name = "homematic_reset";
        };
 
-       hmtc_prog {
+       hmtc-prog-hog {
                gpio-hog;
                gpios = <27 GPIO_ACTIVE_LOW>;
                output-high;
@@ -160,14 +160,14 @@
 };
 
 &gpio3 {
-       zgb_rst {
+       zgb-rst-hog {
                gpio-hog;
                gpios = <18 GPIO_ACTIVE_LOW>;
                output-low;
                line-name = "zigbee_reset";
        };
 
-       zgb_boot {
+       zgb-boot-hog {
                gpio-hog;
                gpios = <19 GPIO_ACTIVE_HIGH>;
                output-high;
@@ -383,193 +383,191 @@
        clkout2_pin: pinmux_clkout2_pin {
                pinctrl-single,pins = <
                        /* xdma_event_intr1.clkout2 */
-                       AM33XX_IOPAD(0x9b4, PIN_INPUT | MUX_MODE6)
+                       AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT, MUX_MODE6)
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1 */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0)
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
-                       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
-                       /* mdio_clk.mdio_clk */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        ehrpwm1_pins: pinmux_ehrpwm1 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.gpio1_19 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.gpio1_19 */
                >;
        };
 
        emmc_pins: pinmux_emmc_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x880, PIN_INPUT | MUX_MODE2)
-                       AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1)
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1)
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1)
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT, MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)
                >;
        };
 
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0)
-                       AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
                >;
        };
 
        mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE5)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE5)
                >;
        };
 
        mmc3_pins: pinmux_mmc3_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x830, PIN_INPUT | MUX_MODE3)
-                       AM33XX_IOPAD(0x834, PIN_INPUT | MUX_MODE3)
-                       AM33XX_IOPAD(0x838, PIN_INPUT | MUX_MODE3)
-                       AM33XX_IOPAD(0x83c, PIN_INPUT | MUX_MODE3)
-                       AM33XX_IOPAD(0x888, PIN_INPUT | MUX_MODE3)
-                       AM33XX_IOPAD(0x88c, PIN_INPUT | MUX_MODE3)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE3)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE3)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT, MUX_MODE3)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE3)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT, MUX_MODE3)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT, MUX_MODE3)
                >;
        };
 
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x968, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE0)
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
        uart1_pins: pinmux_uart1 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0)
-                       AM33XX_IOPAD(0x97C, PIN_OUTPUT | MUX_MODE0)
-                       AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0)
-                       AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0)
                >;
        };
 
        uart2_pins: pinmux_uart2_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1)
-                       AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1)
                >;
        };
 
        uart4_pins: pinmux_uart4_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6)
-                       AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE6)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE6)
                >;
        };
 
        user_leds_s0: user_leds_s0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x844, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLUP | MUX_MODE7)
-                       AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x86c, PIN_INPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x878, PIN_OUTPUT_PULLUP | MUX_MODE7)
-                       AM33XX_IOPAD(0x87c, PIN_INPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x894, PIN_INPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x958, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE7)
-                       AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLUP | MUX_MODE7)
-                       AM33XX_IOPAD(0x9a0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLUP, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLUP, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7)
                >;
        };
 };

diff --git a/arch/arm/dts/am335x-sl50.dts b/arch/arm/dts/am335x-sl50.dts
index ebb56bd..56c0943 100644 (file)
--- a/arch/arm/dts/am335x-sl50.dts
+++ b/arch/arm/dts/am335x-sl50.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 /dts-v1/;
 
@@ -34,25 +31,25 @@
                pinctrl-0 = <&led_pins>;
 
                led0 {
-                       label = "sl50:green:usr0";
+                       label = "sl50:red:usr0";
                        gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
                        default-state = "off";
                };
 
                led1 {
-                       label = "sl50:red:usr1";
+                       label = "sl50:green:usr1";
                        gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
                        default-state = "off";
                };
 
                led2 {
-                       label = "sl50:green:usr2";
+                       label = "sl50:red:usr2";
                        gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
                        default-state = "off";
                };
 
                led3 {
-                       label = "sl50:red:usr3";
+                       label = "sl50:green:usr3";
                        gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
                        default-state = "off";
                };
@@ -78,7 +75,7 @@
                #size-cells = <0>;
 
                /* audio external oscillator */
-               tlv320aic3x_mclk: oscillator@0 {
+               audio_mclk_fixed: oscillator@0 {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
                        clock-frequency  = <24576000>;  /* 24.576MHz */
@@ -91,7 +88,7 @@
                ti,audio-codec = <&audio_codec>;
                ti,mcasp-controller = <&mcasp0>;
 
-               clocks = <&tlv320aic3x_mclk>;
+               clocks = <&audio_mclk_fixed>;
                clock-names = "mclk";
 
                ti,audio-routing =
@@ -122,126 +119,126 @@
 
        led_pins: pinmux_led_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7)     /* gpmc_a5.gpio1_21 */
-                       AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7)     /* gpmc_a6.gpio1_22 */
-                       AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7)     /* gpmc_a7.gpio1_23 */
-                       AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7)     /* gpmc_a8.gpio1_24 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)       /* gpmc_a5.gpio1_21 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)       /* gpmc_a6.gpio1_22 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7)       /* gpmc_a7.gpio1_23 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7)       /* gpmc_a8.gpio1_24 */
                >;
        };
 
        uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart1_pins: pinmux_uart1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart1_rxd.uart1_rxd */
-                       AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart1_txd.uart1_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart4_pins: pinmux_uart4_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6)       /* gpmc_wait0.uart4_rxd */
-                       AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6)    /* gpmc_wpn.uart4_txd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)      /* gpmc_wait0.uart4_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6)     /* gpmc_wpn.uart4_txd */
                >;
        };
 
        i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_sda.i2c0_sda */
-                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_scl.i2c0_scl */
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        i2c2_pins: pinmux_i2c2_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3)       /* uart1_ctsn.i2c2_sda */
-                       AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3)       /* uart1_rtsn.i2c2_scl */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)      /* uart1_ctsn.i2c2_sda */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)      /* uart1_rtsn.i2c2_scl */
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1 */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxerr.mii1_rxerr */
-                       AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txen.mii1_txen */
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxdv.mii1_rxdv */
-                       AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd3.mii1_txd3 */
-                       AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd2.mii1_txd2 */
-                       AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd1.mii1_txd1 */
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd0.mii1_txd0 */
-                       AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_txclk.mii1_txclk */
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxclk.mii1_rxclk */
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxd3.mii1_rxd3 */
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxd2.mii1_rxd2 */
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxd1.mii1_rxd1 */
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0)       /* mii1_rxd0.mii1_rxd0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* MDIO */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
                >;
        };
 
        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
                >;
        };
 
        mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE7)              /* uart0_rtsn.gpio1_9 */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE7)             /* uart0_rtsn.gpio1_9 */
                >;
        };
 
        emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gpmc_a4.gpio1_20 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLUP, MUX_MODE7)        /* gpmc_a4.gpio1_20 */
                >;
        };
 
        emmc_pins: pinmux_emmc_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2)       /* gpmc_csn1.mmc1_clk */
-                       AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)       /* gpmc_csn2.mmc1_cmd */
-                       AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad0.mmc1_dat0 */
-                       AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad1.mmc1_dat1 */
-                       AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad2.mmc1_dat2 */
-                       AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad3.mmc1_dat3 */
-                       AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad4.mmc1_dat4 */
-                       AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad5.mmc1_dat5 */
-                       AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad6.mmc1_dat6 */
-                       AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad7.mmc1_dat7 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)       /* gpmc_csn1.mmc1_clk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)       /* gpmc_csn2.mmc1_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad0.mmc1_dat0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad1.mmc1_dat1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad2.mmc1_dat2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad3.mmc1_dat3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad4.mmc1_dat4 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad5.mmc1_dat5 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad6.mmc1_dat6 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad7.mmc1_dat7 */
                >;
        };
 
@@ -264,11 +261,11 @@
 
        spi0_pins: pinmux_spi0_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0)       /* SPI0_MOSI - spi0_d0.spi0_d0 */
-                       AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)       /* SPI0_MISO - spi0_d1.spi0_d1 */
-                       AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0)       /* SPI0_CLK  - spi0_clk.spi0_clk */
-                       AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0)       /* SPI0_CS0 (NBATTSS) - spi0_cs0.spi0_cs0 */
-                       AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0)       /* SPI0_CS1 (FPGA_FLASH_NCS) - spi0_cs1.spi0_cs1 */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MOSI */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MISO */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)        /* SPI0_CS0 (NBATTSS) */
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0)        /* SPI0_CS1 (FPGA_FLASH_NCS) */
                >;
        };
 
@@ -276,13 +273,13 @@
                pinctrl-single,pins = <
                        AM33XX_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7)     /* SoundPA_en - mcasp0_fsr.gpio3_19 */
                        AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7)     /* nKbdOnC - gpmc_ad10.gpio0_26 */
-                       AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE7)       /* nKbdInt - gpmc_ad12.gpio1_12 */
-                       AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE7)       /* nKbdReset - gpmc_ad13.gpio1_13 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7)       /* nKbdInt - gpmc_ad12.gpio1_12 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7)       /* nKbdReset - gpmc_ad13.gpio1_13 */
                        AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE7)       /* nDispReset - gpmc_ad14.gpio1_14 */
-                       AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7)       /* USB1_enPower - gpmc_a1.gpio1_17 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */
                        /* PDI Bus - Battery system */
-                       AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7)       /* nBattReset  gpmc_a0.gpio1_16 */
-                       AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE7)       /* BattPDIData gpmc_ad15.gpio1_15 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* nBattReset  gpmc_a0.gpio1_16 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7)       /* BattPDIData gpmc_ad15.gpio1_15 */
                >;
        };
 };
@@ -433,7 +430,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&spi0_pins>;
 
-       flash: n25q032@1 {
+       flash: flash@1 {
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "micron,n25q032";

diff --git a/arch/arm/dts/am335x-wega-rdk.dts b/arch/arm/dts/am335x-wega-rdk.dts
index fe50f30..2e04f6d 100644 (file)
--- a/arch/arm/dts/am335x-wega-rdk.dts
+++ b/arch/arm/dts/am335x-wega-rdk.dts
@@ -1,11 +1,7 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2015 Phytec Messtechnik GmbH
  * Author: Teresa Remmet <t.remmet@phytec.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 /dts-v1/;

diff --git a/arch/arm/dts/am335x-wega.dtsi b/arch/arm/dts/am335x-wega.dtsi
index f3e045d..408034d 100644 (file)
--- a/arch/arm/dts/am335x-wega.dtsi
+++ b/arch/arm/dts/am335x-wega.dtsi
@@ -1,11 +1,7 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2015 Phytec Messtechnik GmbH
  * Author: Teresa Remmet <t.remmet@phytec.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 / {
@@ -16,16 +12,12 @@
                compatible = "ti,da830-evm-audio";
        };
 
-       regulators {
-               compatible = "simple-bus";
-
-               vcc3v3: fixedregulator1 {
-                       compatible = "regulator-fixed";
-                       regulator-name = "vcc3v3";
-                       regulator-min-microvolt = <3300000>;
-                       regulator-max-microvolt = <3300000>;
-                       regulator-boot-on;
-               };
+       vcc3v3: fixedregulator1 {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc3v3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
        };
 };
 
@@ -33,11 +25,11 @@
 &am33xx_pinmux {
        mcasp0_pins: pinmux_mcasp0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x9AC, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahclkx.mcasp0_ahclkx */
-                       AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp0_aclkx.mcasp0_aclkx */
-                       AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp0_fsx.mcasp0_fsx */
-                       AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp0_axr0.mcasp0_axr0 */
-                       AM33XX_IOPAD(0x9A8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 };
@@ -85,8 +77,8 @@
 &am33xx_pinmux {
        dcan1_pins: pinmux_dcan1 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
-                       AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
                >;
        };
 };
@@ -101,20 +93,20 @@
 &am33xx_pinmux {
        ethernet1_pins: pinmux_ethernet1 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a0.mii2_txen */
-                       AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a1.mii2_rxdv */
-                       AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a2.mii2_txd3 */
-                       AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a3.mii2_txd2 */
-                       AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a4.mii2_txd1 */
-                       AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a5.mii2_txd0 */
-                       AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a6.mii2_txclk */
-                       AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a7.mii2_rxclk */
-                       AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a8.mii2_rxd3 */
-                       AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a9.mii2_rxd2 */
-                       AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a10.mii2_rxd1 */
-                       AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a11.mii2_rxd0 */
-                       AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_wpn.mii2_rxerr */
-                       AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_ben1.mii2_col */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a0.mii2_txen */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a1.mii2_rxdv */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a2.mii2_txd3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a3.mii2_txd2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a4.mii2_txd1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a5.mii2_txd0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a6.mii2_txclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a7.mii2_rxclk */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a8.mii2_rxd3 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a9.mii2_rxd2 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* gpmc_a10.mii2_rxd1 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* gpmc_a11.mii2_rxd0 */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* gpmc_wpn.mii2_rxerr */
+                       AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1)     /* gpmc_ben1.mii2_col */
                >;
        };
 };
@@ -142,13 +134,13 @@
 &am33xx_pinmux {
        mmc1_pins: pinmux_mmc1 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat3.mmc0_dat3 */
-                       AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat2.mmc0_dat2 */
-                       AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat1.mmc0_dat1 */
-                       AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat0.mmc0_dat0 */
-                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_clk.mmc0_clk */
-                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_cmd.mmc0_cmd */
-                       AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7)       /* spi0_cs1.mmc0_sdcd */
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7)        /* spi0_cs1.mmc0_sdcd */
                >;
        };
 };
@@ -172,17 +164,17 @@
 &am33xx_pinmux {
        uart0_pins: pinmux_uart0 {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
-                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+                       AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 
        uart1_pins: pinmux_uart1_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart1_rxd.uart1_rxd */
-                       AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart1_txd.uart1_txd */
-                       AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0)              /* uart1_ctsn.uart1_ctsn */
-                       AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart1_rtsn.uart1_rtsn */
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
                >;
        };
 };

diff --git a/arch/arm/dts/am33xx-clocks.dtsi b/arch/arm/dts/am33xx-clocks.dtsi
index 44b6268..2984b2f 100644 (file)
--- a/arch/arm/dts/am33xx-clocks.dtsi
+++ b/arch/arm/dts/am33xx-clocks.dtsi
@@ -1,14 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for AM33xx clock data
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 &scm_clocks {
-       sys_clkin_ck: sys_clkin_ck@40 {
+       sys_clkin_ck: clock-sys-clkin-22@40 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
@@ -16,7 +13,7 @@
                reg = <0x0040>;
        };
 
-       adc_tsc_fck: adc_tsc_fck {
+       adc_tsc_fck: clock-adc-tsc-fck {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&sys_clkin_ck>;
@@ -24,7 +21,7 @@
                clock-div = <1>;
        };
 
-       dcan0_fck: dcan0_fck {
+       dcan0_fck: clock-dcan0-fck {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&sys_clkin_ck>;
@@ -32,7 +29,7 @@
                clock-div = <1>;
        };
 
-       dcan1_fck: dcan1_fck {
+       dcan1_fck: clock-dcan1-fck {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&sys_clkin_ck>;
@@ -40,7 +37,7 @@
                clock-div = <1>;
        };
 
-       mcasp0_fck: mcasp0_fck {
+       mcasp0_fck: clock-mcasp0-fck {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&sys_clkin_ck>;
@@ -48,7 +45,7 @@
                clock-div = <1>;
        };
 
-       mcasp1_fck: mcasp1_fck {
+       mcasp1_fck: clock-mcasp1-fck {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&sys_clkin_ck>;
@@ -56,7 +53,7 @@
                clock-div = <1>;
        };
 
-       smartreflex0_fck: smartreflex0_fck {
+       smartreflex0_fck: clock-smartreflex0-fck {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&sys_clkin_ck>;
@@ -64,7 +61,7 @@
                clock-div = <1>;
        };
 
-       smartreflex1_fck: smartreflex1_fck {
+       smartreflex1_fck: clock-smartreflex1-fck {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&sys_clkin_ck>;
@@ -72,7 +69,7 @@
                clock-div = <1>;
        };
 
-       sha0_fck: sha0_fck {
+       sha0_fck: clock-sha0-fck {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&sys_clkin_ck>;
@@ -80,7 +77,7 @@
                clock-div = <1>;
        };
 
-       aes0_fck: aes0_fck {
+       aes0_fck: clock-aes0-fck {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&sys_clkin_ck>;
@@ -88,7 +85,7 @@
                clock-div = <1>;
        };
 
-       rng_fck: rng_fck {
+       rng_fck: clock-rng-fck {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&sys_clkin_ck>;
@@ -121,62 +118,62 @@
        };
 };
 &prcm_clocks {
-       clk_32768_ck: clk_32768_ck {
+       clk_32768_ck: clock-clk-32768 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <32768>;
        };
 
-       clk_rc32k_ck: clk_rc32k_ck {
+       clk_rc32k_ck: clock-clk-rc32k {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <32000>;
        };
 
-       virt_19200000_ck: virt_19200000_ck {
+       virt_19200000_ck: clock-virt-19200000 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <19200000>;
        };
 
-       virt_24000000_ck: virt_24000000_ck {
+       virt_24000000_ck: clock-virt-24000000 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <24000000>;
        };
 
-       virt_25000000_ck: virt_25000000_ck {
+       virt_25000000_ck: clock-virt-25000000 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <25000000>;
        };
 
-       virt_26000000_ck: virt_26000000_ck {
+       virt_26000000_ck: clock-virt-26000000 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <26000000>;
        };
 
-       tclkin_ck: tclkin_ck {
+       tclkin_ck: clock-tclkin {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <12000000>;
        };
 
-       dpll_core_ck: dpll_core_ck@490 {
+       dpll_core_ck: clock@490 {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-core-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
                reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
        };
 
-       dpll_core_x2_ck: dpll_core_x2_ck {
+       dpll_core_x2_ck: clock-dpll-core-x2 {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-x2-clock";
                clocks = <&dpll_core_ck>;
        };
 
-       dpll_core_m4_ck: dpll_core_m4_ck@480 {
+       dpll_core_m4_ck: clock-dpll-core-m4@480 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
@@ -185,7 +182,7 @@
                ti,index-starts-at-one;
        };
 
-       dpll_core_m5_ck: dpll_core_m5_ck@484 {
+       dpll_core_m5_ck: clock-dpll-core-m5@484 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
@@ -194,7 +191,7 @@
                ti,index-starts-at-one;
        };
 
-       dpll_core_m6_ck: dpll_core_m6_ck@4d8 {
+       dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
@@ -203,14 +200,14 @@
                ti,index-starts-at-one;
        };
 
-       dpll_mpu_ck: dpll_mpu_ck@488 {
+       dpll_mpu_ck: clock@488 {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
                reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
        };
 
-       dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
+       dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_mpu_ck>;
@@ -219,14 +216,14 @@
                ti,index-starts-at-one;
        };
 
-       dpll_ddr_ck: dpll_ddr_ck@494 {
+       dpll_ddr_ck: clock@494 {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-no-gate-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
                reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
        };
 
-       dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
+       dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_ddr_ck>;
@@ -235,7 +232,7 @@
                ti,index-starts-at-one;
        };
 
-       dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
+       dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_ddr_m2_ck>;
@@ -243,14 +240,14 @@
                clock-div = <2>;
        };
 
-       dpll_disp_ck: dpll_disp_ck@498 {
+       dpll_disp_ck: clock@498 {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-no-gate-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
                reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
        };
 
-       dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
+       dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_disp_ck>;
@@ -260,14 +257,14 @@
                ti,set-rate-parent;
        };
 
-       dpll_per_ck: dpll_per_ck@48c {
+       dpll_per_ck: clock@48c {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-no-gate-j-type-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
                reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
        };
 
-       dpll_per_m2_ck: dpll_per_m2_ck@4ac {
+       dpll_per_m2_ck: clock-dpll-per-m2@4ac {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_per_ck>;
@@ -276,7 +273,7 @@
                ti,index-starts-at-one;
        };
 
-       dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+       dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_per_m2_ck>;
@@ -284,7 +281,7 @@
                clock-div = <4>;
        };
 
-       dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+       dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_per_m2_ck>;
@@ -292,7 +289,7 @@
                clock-div = <4>;
        };
 
-       clk_24mhz: clk_24mhz {
+       clk_24mhz: clock-clk-24mhz {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_per_m2_ck>;
@@ -300,7 +297,7 @@
                clock-div = <8>;
        };
 
-       clkdiv32k_ck: clkdiv32k_ck {
+       clkdiv32k_ck: clock-clkdiv32k {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&clk_24mhz>;
@@ -308,7 +305,7 @@
                clock-div = <732>;
        };
 
-       l3_gclk: l3_gclk {
+       l3_gclk: clock-l3-gclk {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_core_m4_ck>;
@@ -316,14 +313,14 @@
                clock-div = <1>;
        };
 
-       pruss_ocp_gclk: pruss_ocp_gclk@530 {
+       pruss_ocp_gclk: clock-pruss-ocp-gclk@530 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
                reg = <0x0530>;
        };
 
-       mmu_fck: mmu_fck@914 {
+       mmu_fck: clock-mmu-fck-1@914 {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
                clocks = <&dpll_core_m4_ck>;
@@ -331,56 +328,56 @@
                reg = <0x0914>;
        };
 
-       timer1_fck: timer1_fck@528 {
+       timer1_fck: clock-timer1-fck@528 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
                reg = <0x0528>;
        };
 
-       timer2_fck: timer2_fck@508 {
+       timer2_fck: clock-timer2-fck@508 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
                reg = <0x0508>;
        };
 
-       timer3_fck: timer3_fck@50c {
+       timer3_fck: clock-timer3-fck@50c {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
                reg = <0x050c>;
        };
 
-       timer4_fck: timer4_fck@510 {
+       timer4_fck: clock-timer4-fck@510 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
                reg = <0x0510>;
        };
 
-       timer5_fck: timer5_fck@518 {
+       timer5_fck: clock-timer5-fck@518 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
                reg = <0x0518>;
        };
 
-       timer6_fck: timer6_fck@51c {
+       timer6_fck: clock-timer6-fck@51c {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
                reg = <0x051c>;
        };
 
-       timer7_fck: timer7_fck@504 {
+       timer7_fck: clock-timer7-fck@504 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
                reg = <0x0504>;
        };
 
-       usbotg_fck: usbotg_fck@47c {
+       usbotg_fck: clock-usbotg-fck-8@47c {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
                clocks = <&dpll_per_ck>;
@@ -388,7 +385,7 @@
                reg = <0x047c>;
        };
 
-       dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+       dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_core_m4_ck>;
@@ -396,7 +393,7 @@
                clock-div = <2>;
        };
 
-       ieee5000_fck: ieee5000_fck@e4 {
+       ieee5000_fck: clock-ieee5000-fck-1@e4 {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
                clocks = <&dpll_core_m4_div2_ck>;
@@ -404,14 +401,14 @@
                reg = <0x00e4>;
        };
 
-       wdt1_fck: wdt1_fck@538 {
+       wdt1_fck: clock-wdt1-fck@538 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
                reg = <0x0538>;
        };
 
-       l4_rtc_gclk: l4_rtc_gclk {
+       l4_rtc_gclk: clock-l4-rtc-gclk {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_core_m4_ck>;
@@ -419,7 +416,7 @@
                clock-div = <2>;
        };
 
-       l4hs_gclk: l4hs_gclk {
+       l4hs_gclk: clock-l4hs-gclk {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_core_m4_ck>;
@@ -427,7 +424,7 @@
                clock-div = <1>;
        };
 
-       l3s_gclk: l3s_gclk {
+       l3s_gclk: clock-l3s-gclk {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_core_m4_div2_ck>;
@@ -435,7 +432,7 @@
                clock-div = <1>;
        };
 
-       l4fw_gclk: l4fw_gclk {
+       l4fw_gclk: clock-l4fw-gclk {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_core_m4_div2_ck>;
@@ -443,7 +440,7 @@
                clock-div = <1>;
        };
 
-       l4ls_gclk: l4ls_gclk {
+       l4ls_gclk: clock-l4ls-gclk {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_core_m4_div2_ck>;
@@ -451,7 +448,7 @@
                clock-div = <1>;
        };
 
-       sysclk_div_ck: sysclk_div_ck {
+       sysclk_div_ck: clock-sysclk-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_core_m4_ck>;
@@ -459,7 +456,7 @@
                clock-div = <1>;
        };
 
-       cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+       cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_core_m5_ck>;
@@ -467,21 +464,21 @@
                clock-div = <2>;
        };
 
-       cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
+       cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
                reg = <0x0520>;
        };
 
-       gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
+       gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
                reg = <0x053c>;
        };
 
-       lcd_gclk: lcd_gclk@534 {
+       lcd_gclk: clock-lcd-gclk@534 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
@@ -489,7 +486,7 @@
                ti,set-rate-parent;
        };
 
-       mmc_clk: mmc_clk {
+       mmc_clk: clock-mmc {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_per_m2_ck>;
@@ -539,138 +536,138 @@
 };
 
 &prcm {
-       per_cm: per-cm@0 {
+       per_cm: clock@0 {
                compatible = "ti,omap4-cm";
                reg = <0x0 0x400>;
                #address-cells = <1>;
                #size-cells = <1>;
                ranges = <0 0x0 0x400>;
 
-               l4ls_clkctrl: l4ls-clkctrl@38 {
+               l4ls_clkctrl: clock@38 {
                        compatible = "ti,clkctrl";
                        reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
                        #clock-cells = <2>;
                };
 
-               l3s_clkctrl: l3s-clkctrl@1c {
+               l3s_clkctrl: clock@1c {
                        compatible = "ti,clkctrl";
                        reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
                        #clock-cells = <2>;
                };
 
-               l3_clkctrl: l3-clkctrl@24 {
+               l3_clkctrl: clock@24 {
                        compatible = "ti,clkctrl";
                        reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
                        #clock-cells = <2>;
                };
 
-               l4hs_clkctrl: l4hs-clkctrl@120 {
+               l4hs_clkctrl: clock@120 {
                        compatible = "ti,clkctrl";
                        reg = <0x120 0x4>;
                        #clock-cells = <2>;
                };
 
-               pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 {
+               pruss_ocp_clkctrl: clock@e8 {
                        compatible = "ti,clkctrl";
                        reg = <0xe8 0x4>;
                        #clock-cells = <2>;
                };
 
-               cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 {
+               cpsw_125mhz_clkctrl: clock@0 {
                        compatible = "ti,clkctrl";
                        reg = <0x0 0x18>;
                        #clock-cells = <2>;
                };
 
-               lcdc_clkctrl: lcdc-clkctrl@18 {
+               lcdc_clkctrl: clock@18 {
                        compatible = "ti,clkctrl";
                        reg = <0x18 0x4>;
                        #clock-cells = <2>;
                };
 
-               clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c {
+               clk_24mhz_clkctrl: clock@14c {
                        compatible = "ti,clkctrl";
                        reg = <0x14c 0x4>;
                        #clock-cells = <2>;
                };
        };
 
-       wkup_cm: wkup-cm@400 {
+       wkup_cm: clock@400 {
                compatible = "ti,omap4-cm";
                reg = <0x400 0x100>;
                #address-cells = <1>;
                #size-cells = <1>;
                ranges = <0 0x400 0x100>;
 
-               l4_wkup_clkctrl: l4-wkup-clkctrl@0 {
+               l4_wkup_clkctrl: clock@0 {
                        compatible = "ti,clkctrl";
                        reg = <0x0 0x10>, <0xb4 0x24>;
                        #clock-cells = <2>;
                };
 
-               l3_aon_clkctrl: l3-aon-clkctrl@14 {
+               l3_aon_clkctrl: clock@14 {
                        compatible = "ti,clkctrl";
                        reg = <0x14 0x4>;
                        #clock-cells = <2>;
                };
 
-               l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 {
+               l4_wkup_aon_clkctrl: clock@b0 {
                        compatible = "ti,clkctrl";
                        reg = <0xb0 0x4>;
                        #clock-cells = <2>;
                };
        };
 
-       mpu_cm: mpu-cm@600 {
+       mpu_cm: clock@600 {
                compatible = "ti,omap4-cm";
                reg = <0x600 0x100>;
                #address-cells = <1>;
                #size-cells = <1>;
                ranges = <0 0x600 0x100>;
 
-               mpu_clkctrl: mpu-clkctrl@0 {
+               mpu_clkctrl: clock@0 {
                        compatible = "ti,clkctrl";
                        reg = <0x0 0x8>;
                        #clock-cells = <2>;
                };
        };
 
-       l4_rtc_cm: l4-rtc-cm@800 {
+       l4_rtc_cm: clock@800 {
                compatible = "ti,omap4-cm";
                reg = <0x800 0x100>;
                #address-cells = <1>;
                #size-cells = <1>;
                ranges = <0 0x800 0x100>;
 
-               l4_rtc_clkctrl: l4-rtc-clkctrl@0 {
+               l4_rtc_clkctrl: clock@0 {
                        compatible = "ti,clkctrl";
                        reg = <0x0 0x4>;
                        #clock-cells = <2>;
                };
        };
 
-       gfx_l3_cm: gfx-l3-cm@900 {
+       gfx_l3_cm: clock@900 {
                compatible = "ti,omap4-cm";
                reg = <0x900 0x100>;
                #address-cells = <1>;
                #size-cells = <1>;
                ranges = <0 0x900 0x100>;
 
-               gfx_l3_clkctrl: gfx-l3-clkctrl@0 {
+               gfx_l3_clkctrl: clock@0 {
                        compatible = "ti,clkctrl";
                        reg = <0x0 0x8>;
                        #clock-cells = <2>;
                };
        };
 
-       l4_cefuse_cm: l4-cefuse-cm@a00 {
+       l4_cefuse_cm: clock@a00 {
                compatible = "ti,omap4-cm";
                reg = <0xa00 0x100>;
                #address-cells = <1>;
                #size-cells = <1>;
                ranges = <0 0xa00 0x100>;
 
-               l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 {
+               l4_cefuse_clkctrl: clock@0 {
                        compatible = "ti,clkctrl";
                        reg = <0x0 0x24>;
                        #clock-cells = <2>;

diff --git a/arch/arm/dts/am33xx-l4.dtsi b/arch/arm/dts/am33xx-l4.dtsi
index 5892612..2264a1a 100644 (file)
--- a/arch/arm/dts/am33xx-l4.dtsi
+++ b/arch/arm/dts/am33xx-l4.dtsi
@@ -1327,7 +1327,7 @@
                                #mbox-cells = <1>;
                                ti,mbox-num-users = <4>;
                                ti,mbox-num-fifos = <8>;
-                               mbox_wkupm3: wkup_m3 {
+                               mbox_wkupm3: mbox-wkup-m3 {
                                        ti,mbox-send-noirq;
                                        ti,mbox-tx = <0 0 0>;
                                        ti,mbox-rx = <0 0 3>;
@@ -1621,7 +1621,7 @@
                        };
                };
 
-               target-module@ae000 {                   /* 0x481ae000, ap 56 3a.0 */
+               target-module@ae000 {           /* 0x481ae000, ap 56 3a.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
                        reg = <0xae000 0x4>,
                              <0xae010 0x4>,
@@ -1798,7 +1798,7 @@
                                status = "disabled";
                                ranges = <0 0 0x1000>;
 
-                               ecap0: ecap@100 {
+                               ecap0: pwm@100 {
                                        compatible = "ti,am3352-ecap",
                                                     "ti,am33xx-ecap";
                                        #pwm-cells = <3>;
@@ -1859,7 +1859,7 @@
                                status = "disabled";
                                ranges = <0 0 0x1000>;
 
-                               ecap1: ecap@100 {
+                               ecap1: pwm@100 {
                                        compatible = "ti,am3352-ecap",
                                                     "ti,am33xx-ecap";
                                        #pwm-cells = <3>;
@@ -1920,7 +1920,7 @@
                                status = "disabled";
                                ranges = <0 0 0x1000>;
 
-                               ecap2: ecap@100 {
+                               ecap2: pwm@100 {
                                        compatible = "ti,am3352-ecap",
                                                     "ti,am33xx-ecap";
                                        #pwm-cells = <3>;

diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi
index 5871344..3c7e038 100644 (file)
--- a/arch/arm/dts/am33xx.dtsi
+++ b/arch/arm/dts/am33xx.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for AM33XX SoC
  *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/bus/ti-sysc.h>
@@ -175,7 +172,7 @@
         * for the moment, just use a fake OCP bus entry to represent
         * the whole bus hierarchy.
         */
-       ocp {
+       ocp: ocp {
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
@@ -325,11 +322,11 @@
                        ranges = <0x0 0x47810000 0x1000>;
 
                        mmc3: mmc@0 {
-                             compatible = "ti,am335-sdhci";
-                             ti,needs-special-reset;
-                             interrupts = <29>;
-                             reg = <0x0 0x1000>;
-                             status = "disabled";
+                               compatible = "ti,am335-sdhci";
+                               ti,needs-special-reset;
+                               interrupts = <29>;
+                               reg = <0x0 0x1000>;
+                               status = "disabled";
                        };
                };
 

diff --git a/arch/arm/dts/am3517-evm-ui.dtsi b/arch/arm/dts/am3517-evm-ui.dtsi
index 340e681..75ad421 100644 (file)
--- a/arch/arm/dts/am3517-evm-ui.dtsi
+++ b/arch/arm/dts/am3517-evm-ui.dtsi
@@ -70,61 +70,61 @@
                compatible = "gpio-keys-polled";
                poll-interval = <100>;
 
-               record {
+               key-record {
                        label = "Record";
-                       linux,code = <KEY_RECORD>;
+                       /* linux,code = <BTN_0>; */
                        gpios = <&tca6416_2 15 GPIO_ACTIVE_LOW>;
                };
 
-               play {
+               key-play {
                        label = "Play";
                        linux,code = <KEY_PLAY>;
                        gpios = <&tca6416_2 14 GPIO_ACTIVE_LOW>;
                };
 
-               Stop {
+               key-stop {
                        label = "Stop";
                        linux,code = <KEY_STOP>;
                        gpios = <&tca6416_2 13 GPIO_ACTIVE_LOW>;
                };
 
-               fwd {
+               key-fwd {
                        label = "FWD";
                        linux,code = <KEY_FASTFORWARD>;
                        gpios = <&tca6416_2 12 GPIO_ACTIVE_LOW>;
                };
 
-               rwd {
+               key-rwd {
                        label = "RWD";
                        linux,code = <KEY_REWIND>;
                        gpios = <&tca6416_2 11 GPIO_ACTIVE_LOW>;
                };
 
-               shift {
+               key-shift {
                        label = "Shift";
                        linux,code = <KEY_LEFTSHIFT>;
                        gpios = <&tca6416_2 10 GPIO_ACTIVE_LOW>;
                };
 
-               Mode {
+               key-mode {
                        label = "Mode";
                        linux,code = <BTN_MODE>;
                        gpios = <&tca6416_2 9 GPIO_ACTIVE_LOW>;
                };
 
-               Menu {
+               key-menu {
                        label = "Menu";
                        linux,code = <KEY_MENU>;
                        gpios = <&tca6416_2 8 GPIO_ACTIVE_LOW>;
                };
 
-               Up {
+               key-up {
                        label = "Up";
                        linux,code = <KEY_UP>;
                        gpios = <&tca6416_2 7 GPIO_ACTIVE_LOW>;
                };
 
-               Down {
+               key-down {
                        label = "Down";
                        linux,code = <KEY_DOWN>;
                        gpios = <&tca6416_2 6 GPIO_ACTIVE_LOW>;
@@ -137,14 +137,14 @@
        tlv320aic23_1: codec@1a {
                compatible = "ti,tlv320aic23";
                reg = <0x1a>;
-               #sound-dai-cells= <0>;
+               #sound-dai-cells = <0>;
                status = "okay";
        };
 
        tlv320aic23_2: codec@1b {
                compatible = "ti,tlv320aic23";
                reg = <0x1b>;
-               #sound-dai-cells= <0>;
+               #sound-dai-cells = <0>;
                status = "okay";
        };
 };
@@ -154,7 +154,7 @@
        tlv320aic23_3: codec@1a {
                compatible = "ti,tlv320aic23";
                reg = <0x1a>;
-               #sound-dai-cells= <0>;
+               #sound-dai-cells = <0>;
                status = "okay";
        };
 

diff --git a/arch/arm/dts/am3517-evm.dts b/arch/arm/dts/am3517-evm.dts
index a01f9cf..d21bb2c 100644 (file)
--- a/arch/arm/dts/am3517-evm.dts
+++ b/arch/arm/dts/am3517-evm.dts
@@ -26,66 +26,66 @@
                reg = <0x80000000 0x10000000>; /* 256 MB */
        };
 
-        vmmc_fixed: vmmc {
-                compatible = "regulator-fixed";
-                regulator-name = "vmmc_fixed";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-        };
+       vmmc_fixed: vmmc {
+               compatible = "regulator-fixed";
+               regulator-name = "vmmc_fixed";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
 
        gpio-keys {
                compatible = "gpio-keys-polled";
                poll-interval = <100>;
 
-               user_pb {
+               button-user {
                        label = "User Push Button";
                        linux,code = <BTN_0>;
                        gpios = <&tca6416 5 GPIO_ACTIVE_LOW>;
                };
 
-               user_sw_1 {
+               switch-1 {
                        label = "User Switch 1";
                        linux,code = <BTN_1>;
                        gpios = <&tca6416 8 GPIO_ACTIVE_LOW>;
                };
 
-               user_sw_2 {
+               switch-2 {
                        label = "User Switch 2";
                        linux,code = <BTN_2>;
                        gpios = <&tca6416 9 GPIO_ACTIVE_LOW>;
                };
 
-               user_sw_3 {
+               switch-3 {
                        label = "User Switch 3";
                        linux,code = <BTN_3>;
                        gpios = <&tca6416 10 GPIO_ACTIVE_LOW>;
                };
 
-               user_sw_4 {
+               switch-4 {
                        label = "User Switch 4";
                        linux,code = <BTN_4>;
                        gpios = <&tca6416 11 GPIO_ACTIVE_LOW>;
                };
 
-               user_sw_5 {
+               switch-5 {
                        label = "User Switch 5";
                        linux,code = <BTN_5>;
                        gpios = <&tca6416 12 GPIO_ACTIVE_LOW>;
                };
 
-               user_sw_6 {
+               switch-6 {
                        label = "User Switch 6";
                        linux,code = <BTN_6>;
                        gpios = <&tca6416 13 GPIO_ACTIVE_LOW>;
                };
 
-               user_sw_7 {
+               switch-7 {
                        label = "User Switch 7";
                        linux,code = <BTN_7>;
                        gpios = <&tca6416 14 GPIO_ACTIVE_LOW>;
                };
 
-               user_sw_8 {
+               switch-8 {
                        label = "User Switch 8";
                        linux,code = <BTN_8>;
                        gpios = <&tca6416 15 GPIO_ACTIVE_LOW>;
@@ -150,7 +150,7 @@
                enable-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* gpio_182 */
        };
 
-       pwm11: dmtimer-pwm@11 {
+       pwm11: pwm-11 {
                compatible = "ti,omap-dmtimer-pwm";
                pinctrl-names = "default";
                pinctrl-0 = <&pwm_pins>;
@@ -176,7 +176,7 @@
 };
 
 &davinci_mdio {
-            status = "okay";
+       status = "okay";
 };
 
 &dss {
@@ -223,7 +223,7 @@
 };
 
 &mmc3 {
-      status = "disabled";
+       status = "disabled";
 };
 
 &usbhshost {

diff --git a/arch/arm/dts/am3517.dtsi b/arch/arm/dts/am3517.dtsi
index 23ea381..2633fae 100644 (file)
--- a/arch/arm/dts/am3517.dtsi
+++ b/arch/arm/dts/am3517.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for am3517 SoC
  *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "omap3.dtsi"
@@ -43,7 +40,7 @@
                        clock-names = "ick";
                };
 
-               davinci_mdio: ethernet@5c030000 {
+               davinci_mdio: mdio@5c030000 {
                        compatible = "ti,davinci_mdio";
                        ti,hwmods = "davinci_mdio";
                        status = "disabled";

diff --git a/arch/arm/dts/am35xx-clocks.dtsi b/arch/arm/dts/am35xx-clocks.dtsi
index 00dd1f0..220d0a5 100644 (file)
--- a/arch/arm/dts/am35xx-clocks.dtsi
+++ b/arch/arm/dts/am35xx-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP3 clock data
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 &scm_clocks {
        emac_ick: emac_ick@32c {

diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi
index 6f60a32..42a0307 100644 (file)
--- a/arch/arm/dts/am4372.dtsi
+++ b/arch/arm/dts/am4372.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for AM4372 SoC
  *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/gpio/gpio.h>

diff --git a/arch/arm/dts/am437x-gp-evm.dts b/arch/arm/dts/am437x-gp-evm.dts
index 21f7691..bbd61f8 100644 (file)
--- a/arch/arm/dts/am437x-gp-evm.dts
+++ b/arch/arm/dts/am437x-gp-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /* AM437x GP EVM */
@@ -138,139 +135,138 @@
 
        i2c0_pins: i2c0_pins {
                pinctrl-single,pins = <
-                       0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
-                       0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
+                       AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
+                       AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
                >;
        };
 
        i2c1_pins: i2c1_pins {
                pinctrl-single,pins = <
-                       0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
-                       0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
+                       AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
+                       AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
                >;
        };
 
        mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
-                       0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+                       AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
                >;
        };
 
        ecap0_pins: backlight_pins {
                pinctrl-single,pins = <
-                       0x164 MUX_MODE0       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+                       AM4372_IOPAD(0x964, MUX_MODE0)       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
                >;
        };
 
        pixcir_ts_pins: pixcir_ts_pins {
                pinctrl-single,pins = <
-                       0x264 (PIN_INPUT_PULLUP | MUX_MODE7)  /* spi2_d0.gpio3_22 */
+                       AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7)  /* spi2_d0.gpio3_22 */
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1 */
-                       0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
-                       0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rxctl */
-                       0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
-                       0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
-                       0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
-                       0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
-                       0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
-                       0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rmii1_rclk */
-                       0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rxd3 */
-                       0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rxd2 */
-                       0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rxd1 */
-                       0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rxd0 */
+                       AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txen.rgmii1_txen */
+                       AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxdv.rgmii1_rxctl */
+                       AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd1.rgmii1_txd3 */
+                       AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd0.rgmii1_txd2 */
+                       AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd1.rgmii1_txd1 */
+                       AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd0.rgmii1_txd0 */
+                       AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txclk.rmii1_tclk */
+                       AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxclk.rmii1_rclk */
+                       AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd1.rgmii1_rxd3 */
+                       AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd0.rgmii1_rxd2 */
+                       AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd1.rgmii1_rxd1 */
+                       AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd0.rgmii1_rxd0 */
                >;
        };
 
        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* MDIO */
-                       0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
-                       0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
+                       AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
+                       AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
                >;
        };
 
        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
                >;
        };
 
        nand_flash_x8: nand_flash_x8 {
                pinctrl-single,pins = <
-                       0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* spi2_cs0.gpio/eMMCorNANDsel */
-                       0x0  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad0.gpmc_ad0 */
-                       0x4  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad1.gpmc_ad1 */
-                       0x8  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad2.gpmc_ad2 */
-                       0xc  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad3.gpmc_ad3 */
-                       0x10 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad4.gpmc_ad4 */
-                       0x14 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad5.gpmc_ad5 */
-                       0x18 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad6.gpmc_ad6 */
-                       0x1c (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad7.gpmc_ad7 */
-                       0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
-                       0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_wpn.gpmc_wpn */
-                       0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0  */
-                       0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
-                       0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
-                       0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
-                       0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
+                       AM4372_IOPAD(0x800, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad0.gpmc_ad0 */
+                       AM4372_IOPAD(0x804, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad1.gpmc_ad1 */
+                       AM4372_IOPAD(0x808, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad2.gpmc_ad2 */
+                       AM4372_IOPAD(0x80c, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad3.gpmc_ad3 */
+                       AM4372_IOPAD(0x810, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad4.gpmc_ad4 */
+                       AM4372_IOPAD(0x814, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad5.gpmc_ad5 */
+                       AM4372_IOPAD(0x818, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad6.gpmc_ad6 */
+                       AM4372_IOPAD(0x81c, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad7.gpmc_ad7 */
+                       AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_wait0.gpmc_wait0 */
+                       AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gpmc_wpn.gpmc_wpn */
+                       AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_csn0.gpmc_csn0  */
+                       AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)             /* gpmc_advn_ale.gpmc_advn_ale */
+                       AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)             /* gpmc_oen_ren.gpmc_oen_ren */
+                       AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)             /* gpmc_wen.gpmc_wen */
+                       AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_be0n_cle.gpmc_be0n_cle */
                >;
        };
 
        dss_pins: dss_pins {
                pinctrl-single,pins = <
-                       0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
-                       0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
-                       0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
-                       0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
-                       0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
-                       0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
-                       0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
-                       0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
-                       0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
-                       0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-                       0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-                       0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
-                       0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-                       0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-                       0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-                       0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
-                       0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-                       0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-                       0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-                       0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
-                       0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-                       0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-                       0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
-                       0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
-                       0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
-                       0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
-                       0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
-                       0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
+                       AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
+                       AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
+                       AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
+                       AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
+                       AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
+                       AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
+                       AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
+                       AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
+                       AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
+                       AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
+                       AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
+                       AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
+                       AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
+                       AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
 
                >;
        };
@@ -278,140 +274,140 @@
        lcd_pins: lcd_pins {
                pinctrl-single,pins = <
                        /* GPIO 5_8 to select LCD / HDMI */
-                       0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
+                       AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7)
                >;
        };
 
        dcan0_default: dcan0_default_pins {
                pinctrl-single,pins = <
-                       0x178 (PIN_OUTPUT | MUX_MODE2)          /* uart1_ctsn.d_can0_tx */
-                       0x17c (PIN_INPUT_PULLUP | MUX_MODE2)    /* uart1_rtsn.d_can0_rx */
+                       AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2)             /* uart1_ctsn.d_can0_tx */
+                       AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2)       /* uart1_rtsn.d_can0_rx */
                >;
        };
 
        dcan1_default: dcan1_default_pins {
                pinctrl-single,pins = <
-                       0x180 (PIN_OUTPUT | MUX_MODE2)          /* uart1_rxd.d_can1_tx */
-                       0x184 (PIN_INPUT_PULLUP | MUX_MODE2)    /* uart1_txd.d_can1_rx */
+                       AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2)             /* uart1_rxd.d_can1_tx */
+                       AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2)       /* uart1_txd.d_can1_rx */
                >;
        };
 
        vpfe0_pins_default: vpfe0_pins_default {
                pinctrl-single,pins = <
-                       0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_hd mode 0*/
-                       0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_vd mode 0*/
-                       0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_pclk mode 0*/
-                       0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data8 mode 0*/
-                       0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data9 mode 0*/
-                       0x208 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data0 mode 0*/
-                       0x20C (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data1 mode 0*/
-                       0x210 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data2 mode 0*/
-                       0x214 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data3 mode 0*/
-                       0x218 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data4 mode 0*/
-                       0x21C (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data5 mode 0*/
-                       0x220 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data6 mode 0*/
-                       0x224 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data7 mode 0*/
+                       AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_hd mode 0*/
+                       AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_vd mode 0*/
+                       AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_pclk mode 0*/
+                       AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data8 mode 0*/
+                       AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data9 mode 0*/
+                       AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data0 mode 0*/
+                       AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data1 mode 0*/
+                       AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data2 mode 0*/
+                       AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data3 mode 0*/
+                       AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data4 mode 0*/
+                       AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data5 mode 0*/
+                       AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data6 mode 0*/
+                       AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data7 mode 0*/
                >;
        };
 
        vpfe0_pins_sleep: vpfe0_pins_sleep {
                pinctrl-single,pins = <
-                       0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_hd mode 0*/
-                       0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_vd mode 0*/
-                       0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_pclk mode 0*/
-                       0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data8 mode 0*/
-                       0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data9 mode 0*/
-                       0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data0 mode 0*/
-                       0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data1 mode 0*/
-                       0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data2 mode 0*/
-                       0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data3 mode 0*/
-                       0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data4 mode 0*/
-                       0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data5 mode 0*/
-                       0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data6 mode 0*/
-                       0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data7 mode 0*/
+                       AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_hd mode 0*/
+                       AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_vd mode 0*/
+                       AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_pclk mode 0*/
+                       AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data8 mode 0*/
+                       AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data9 mode 0*/
+                       AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data0 mode 0*/
+                       AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data1 mode 0*/
+                       AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data2 mode 0*/
+                       AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data3 mode 0*/
+                       AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data4 mode 0*/
+                       AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data5 mode 0*/
+                       AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data6 mode 0*/
+                       AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data7 mode 0*/
                >;
        };
 
        vpfe1_pins_default: vpfe1_pins_default {
                pinctrl-single,pins = <
-                       0x1CC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0*/
-                       0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0*/
-                       0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0*/
-                       0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0*/
-                       0x1DC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0*/
-                       0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0*/
-                       0x1EC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0*/
-                       0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0*/
-                       0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0*/
-                       0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0*/
-                       0x1FC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0*/
-                       0x200 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0*/
-                       0x204 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0*/
+                       AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0*/
+                       AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0*/
+                       AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0*/
+                       AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0*/
+                       AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0*/
+                       AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0*/
+                       AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0*/
+                       AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0*/
+                       AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0*/
+                       AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0*/
+                       AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0*/
+                       AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0*/
+                       AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0*/
                >;
        };
 
        vpfe1_pins_sleep: vpfe1_pins_sleep {
                pinctrl-single,pins = <
-                       0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data9 mode 0*/
-                       0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data8 mode 0*/
-                       0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_hd mode 0*/
-                       0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_vd mode 0*/
-                       0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_pclk mode 0*/
-                       0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data0 mode 0*/
-                       0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data1 mode 0*/
-                       0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data2 mode 0*/
-                       0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data3 mode 0*/
-                       0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data4 mode 0*/
-                       0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data5 mode 0*/
-                       0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data6 mode 0*/
-                       0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data7 mode 0*/
+                       AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data9 mode 0*/
+                       AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data8 mode 0*/
+                       AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_hd mode 0*/
+                       AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_vd mode 0*/
+                       AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_pclk mode 0*/
+                       AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data0 mode 0*/
+                       AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data1 mode 0*/
+                       AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data2 mode 0*/
+                       AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data3 mode 0*/
+                       AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data4 mode 0*/
+                       AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data5 mode 0*/
+                       AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data6 mode 0*/
+                       AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data7 mode 0*/
                >;
        };
 
        mmc3_pins_default: pinmux_mmc3_pins_default {
                pinctrl-single,pins = <
-                       0x8c (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_clk.mmc2_clk */
-                       0x88 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_csn3.mmc2_cmd */
-                       0x44 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a1.mmc2_dat0 */
-                       0x48 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a2.mmc2_dat1 */
-                       0x4c (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a3.mmc2_dat2 */
-                       0x78 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_be1n.mmc2_dat3 */
+                       AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_clk.mmc2_clk */
+                       AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_csn3.mmc2_cmd */
+                       AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a1.mmc2_dat0 */
+                       AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a2.mmc2_dat1 */
+                       AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a3.mmc2_dat2 */
+                       AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_be1n.mmc2_dat3 */
                >;
        };
 
        mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
                pinctrl-single,pins = <
-                       0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_clk.mmc2_clk */
-                       0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_csn3.mmc2_cmd */
-                       0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a1.mmc2_dat0 */
-                       0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a2.mmc2_dat1 */
-                       0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a3.mmc2_dat2 */
-                       0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_be1n.mmc2_dat3 */
+                       AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_clk.mmc2_clk */
+                       AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_csn3.mmc2_cmd */
+                       AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_a1.mmc2_dat0 */
+                       AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_a2.mmc2_dat1 */
+                       AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_a3.mmc2_dat2 */
+                       AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_be1n.mmc2_dat3 */
                >;
        };
 
        wlan_pins_default: pinmux_wlan_pins_default {
                pinctrl-single,pins = <
-                       0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)          /* gpmc_a4.gpio1_20 WL_EN */
-                       0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)    /* gpmc_a7.gpio1_23 WL_IRQ*/
-                       0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)          /* gpmc_a0.gpio1_16 BT_EN*/
+                       AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)            /* gpmc_a4.gpio1_20 WL_EN */
+                       AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)      /* gpmc_a7.gpio1_23 WL_IRQ*/
+                       AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7)            /* gpmc_a0.gpio1_16 BT_EN*/
                >;
        };
 
        wlan_pins_sleep: pinmux_wlan_pins_sleep {
                pinctrl-single,pins = <
-                       0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)          /* gpmc_a4.gpio1_20 WL_EN */
-                       0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)    /* gpmc_a7.gpio1_23 WL_IRQ*/
-                       0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7)            /* gpmc_a0.gpio1_16 BT_EN*/
+                       AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)            /* gpmc_a4.gpio1_20 WL_EN */
+                       AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)      /* gpmc_a7.gpio1_23 WL_IRQ*/
+                       AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7)              /* gpmc_a0.gpio1_16 BT_EN*/
                >;
        };
 
        uart3_pins: uart3_pins {
                pinctrl-single,pins = <
-                       0x228 (PIN_INPUT | MUX_MODE0)           /* uart3_rxd.uart3_rxd */
-                       0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
-                       0x230 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart3_ctsn.uart3_ctsn */
-                       0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
+                       AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0)              /* uart3_rxd.uart3_rxd */
+                       AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
+                       AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart3_ctsn.uart3_ctsn */
+                       AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
                >;
        };
 };

diff --git a/arch/arm/dts/am437x-idk-evm.dts b/arch/arm/dts/am437x-idk-evm.dts
index 8f6824c..2c94c87 100644 (file)
--- a/arch/arm/dts/am437x-idk-evm.dts
+++ b/arch/arm/dts/am437x-idk-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /dts-v1/;

diff --git a/arch/arm/dts/am437x-sk-evm.dts b/arch/arm/dts/am437x-sk-evm.dts
index 66a3bd1..f1bb009 100644 (file)
--- a/arch/arm/dts/am437x-sk-evm.dts
+++ b/arch/arm/dts/am437x-sk-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /* AM437x SK EVM */
@@ -140,250 +137,250 @@
 &am43xx_pinmux {
        matrix_keypad_pins: matrix_keypad_pins {
                pinctrl-single,pins = <
-                       0x24c (PIN_OUTPUT | MUX_MODE7)  /* gpio5_13.gpio5_13 */
-                       0x250 (PIN_OUTPUT | MUX_MODE7)  /* spi4_sclk.gpio5_4 */
-                       0x254 (PIN_INPUT | MUX_MODE7)   /* spi4_d0.gpio5_5 */
-                       0x258 (PIN_INPUT | MUX_MODE7)   /* spi4_d1.gpio5_5 */
+                       AM4372_IOPAD(0xa4c, PIN_OUTPUT | MUX_MODE7)     /* gpio5_13.gpio5_13 */
+                       AM4372_IOPAD(0xa50, PIN_OUTPUT | MUX_MODE7)     /* spi4_sclk.gpio5_4 */
+                       AM4372_IOPAD(0xa54, PIN_INPUT | MUX_MODE7)      /* spi4_d0.gpio5_5 */
+                       AM4372_IOPAD(0xa58, PIN_INPUT | MUX_MODE7)      /* spi4_d1.gpio5_5 */
                >;
        };
 
        leds_pins: leds_pins {
                pinctrl-single,pins = <
-                       0x228 (PIN_OUTPUT | MUX_MODE7)  /* uart3_rxd.gpio5_2 */
-                       0x22c (PIN_OUTPUT | MUX_MODE7)  /* uart3_txd.gpio5_3 */
-                       0x230 (PIN_OUTPUT | MUX_MODE7)  /* uart3_ctsn.gpio5_0 */
-                       0x234 (PIN_OUTPUT | MUX_MODE7)  /* uart3_rtsn.gpio5_1 */
+                       AM4372_IOPAD(0xa28, PIN_OUTPUT | MUX_MODE7)     /* uart3_rxd.gpio5_2 */
+                       AM4372_IOPAD(0xa2c, PIN_OUTPUT | MUX_MODE7)     /* uart3_txd.gpio5_3 */
+                       AM4372_IOPAD(0xa30, PIN_OUTPUT | MUX_MODE7)     /* uart3_ctsn.gpio5_0 */
+                       AM4372_IOPAD(0xa34, PIN_OUTPUT | MUX_MODE7)     /* uart3_rtsn.gpio5_1 */
                >;
        };
 
        i2c0_pins: i2c0_pins {
                pinctrl-single,pins = <
-                       0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
-                       0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
+                       AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
+                       AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
                >;
        };
 
        i2c1_pins: i2c1_pins {
                pinctrl-single,pins = <
-                       0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
-                       0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
+                       AM4372_IOPAD(0x95c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
+                       AM4372_IOPAD(0x958, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
                >;
        };
 
        mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
-                       0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
-                       0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
-                       0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
-                       0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
-                       0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
-                       0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
-                       0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+                       AM4372_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
+                       AM4372_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
+                       AM4372_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
+                       AM4372_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
+                       AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
+                       AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
+                       AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
                >;
        };
 
        ecap0_pins: backlight_pins {
                pinctrl-single,pins = <
-                       0x164 (PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
+                       AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
                >;
        };
 
        edt_ft5306_ts_pins: edt_ft5306_ts_pins {
                pinctrl-single,pins = <
-                       0x74 (PIN_INPUT | MUX_MODE7)    /* gpmc_wpn.gpio0_31 */
-                       0x78 (PIN_OUTPUT | MUX_MODE7)   /* gpmc_be1n.gpio1_28 */
+                       AM4372_IOPAD(0x874, PIN_INPUT | MUX_MODE7)      /* gpmc_wpn.gpio0_31 */
+                       AM4372_IOPAD(0x878, PIN_OUTPUT | MUX_MODE7)     /* gpmc_be1n.gpio1_28 */
                >;
        };
 
        vpfe0_pins_default: vpfe0_pins_default {
                pinctrl-single,pins = <
-                       0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_hd mode 0*/
-                       0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_vd mode 0*/
-                       0x1b8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_field mode 0*/
-                       0x1bc (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_wen mode 0*/
-                       0x1c0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_pclk mode 0*/
-                       0x1c4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data8 mode 0*/
-                       0x1c8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data9 mode 0*/
-                       0x208 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data0 mode 0*/
-                       0x20c (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data1 mode 0*/
-                       0x210 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data2 mode 0*/
-                       0x214 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data3 mode 0*/
-                       0x218 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data4 mode 0*/
-                       0x21c (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data5 mode 0*/
-                       0x220 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data6 mode 0*/
-                       0x224 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data7 mode 0*/
+                       AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_hd mode 0*/
+                       AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_vd mode 0*/
+                       AM4372_IOPAD(0x9b8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_field mode 0*/
+                       AM4372_IOPAD(0x9bc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_wen mode 0*/
+                       AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_pclk mode 0*/
+                       AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data8 mode 0*/
+                       AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data9 mode 0*/
+                       AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data0 mode 0*/
+                       AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data1 mode 0*/
+                       AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data2 mode 0*/
+                       AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data3 mode 0*/
+                       AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data4 mode 0*/
+                       AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data5 mode 0*/
+                       AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data6 mode 0*/
+                       AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data7 mode 0*/
                >;
        };
 
        vpfe0_pins_sleep: vpfe0_pins_sleep {
                pinctrl-single,pins = <
-                       0x1b0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-                       0x1b4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-                       0x1b8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-                       0x1bc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-                       0x1c0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-                       0x1c4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-                       0x1c8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-                       0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-                       0x20c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-                       0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-                       0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-                       0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-                       0x21c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-                       0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
-                       0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+                       AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+                       AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+                       AM4372_IOPAD(0x9b8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+                       AM4372_IOPAD(0x9bc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+                       AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+                       AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+                       AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+                       AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+                       AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+                       AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+                       AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+                       AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+                       AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+                       AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+                       AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
                >;
        };
 
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1 */
-                       0x12c (PIN_OUTPUT | MUX_MODE2)  /* mii1_txclk.rmii1_tclk */
-                       0x114 (PIN_OUTPUT | MUX_MODE2)  /* mii1_txen.rgmii1_tctl */
-                       0x128 (PIN_OUTPUT | MUX_MODE2)  /* mii1_txd0.rgmii1_td0 */
-                       0x124 (PIN_OUTPUT | MUX_MODE2)  /* mii1_txd1.rgmii1_td1 */
-                       0x120 (PIN_OUTPUT | MUX_MODE2)  /* mii1_txd0.rgmii1_td2 */
-                       0x11c (PIN_OUTPUT | MUX_MODE2)  /* mii1_txd1.rgmii1_td3 */
-                       0x130 (PIN_INPUT | MUX_MODE2)   /* mii1_rxclk.rmii1_rclk */
-                       0x118 (PIN_INPUT | MUX_MODE2)   /* mii1_rxdv.rgmii1_rctl */
-                       0x140 (PIN_INPUT | MUX_MODE2)   /* mii1_rxd0.rgmii1_rd0 */
-                       0x13c (PIN_INPUT | MUX_MODE2)   /* mii1_rxd1.rgmii1_rd1 */
-                       0x138 (PIN_INPUT | MUX_MODE2)   /* mii1_rxd0.rgmii1_rd2 */
-                       0x134 (PIN_INPUT | MUX_MODE2)   /* mii1_rxd1.rgmii1_rd3 */
+                       AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE2)     /* mii1_txclk.rmii1_tclk */
+                       AM4372_IOPAD(0x914, PIN_OUTPUT | MUX_MODE2)     /* mii1_txen.rgmii1_tctl */
+                       AM4372_IOPAD(0x928, PIN_OUTPUT | MUX_MODE2)     /* mii1_txd0.rgmii1_td0 */
+                       AM4372_IOPAD(0x924, PIN_OUTPUT | MUX_MODE2)     /* mii1_txd1.rgmii1_td1 */
+                       AM4372_IOPAD(0x920, PIN_OUTPUT | MUX_MODE2)     /* mii1_txd0.rgmii1_td2 */
+                       AM4372_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE2)     /* mii1_txd1.rgmii1_td3 */
+                       AM4372_IOPAD(0x930, PIN_INPUT | MUX_MODE2)      /* mii1_rxclk.rmii1_rclk */
+                       AM4372_IOPAD(0x918, PIN_INPUT | MUX_MODE2)      /* mii1_rxdv.rgmii1_rctl */
+                       AM4372_IOPAD(0x940, PIN_INPUT | MUX_MODE2)      /* mii1_rxd0.rgmii1_rd0 */
+                       AM4372_IOPAD(0x93c, PIN_INPUT | MUX_MODE2)      /* mii1_rxd1.rgmii1_rd1 */
+                       AM4372_IOPAD(0x938, PIN_INPUT | MUX_MODE2)      /* mii1_rxd0.rgmii1_rd2 */
+                       AM4372_IOPAD(0x934, PIN_INPUT | MUX_MODE2)      /* mii1_rxd1.rgmii1_rd3 */
 
                        /* Slave 2 */
-                       0x58 (PIN_OUTPUT | MUX_MODE2)   /* gpmc_a6.rgmii2_tclk */
-                       0x40 (PIN_OUTPUT | MUX_MODE2)   /* gpmc_a0.rgmii2_tctl */
-                       0x54 (PIN_OUTPUT | MUX_MODE2)   /* gpmc_a5.rgmii2_td0 */
-                       0x50 (PIN_OUTPUT | MUX_MODE2)   /* gpmc_a4.rgmii2_td1 */
-                       0x4c (PIN_OUTPUT | MUX_MODE2)   /* gpmc_a3.rgmii2_td2 */
-                       0x48 (PIN_OUTPUT | MUX_MODE2)   /* gpmc_a2.rgmii2_td3 */
-                       0x5c (PIN_INPUT | MUX_MODE2)    /* gpmc_a7.rgmii2_rclk */
-                       0x44 (PIN_INPUT | MUX_MODE2)    /* gpmc_a1.rgmii2_rtcl */
-                       0x6c (PIN_INPUT | MUX_MODE2)    /* gpmc_a11.rgmii2_rd0 */
-                       0x68 (PIN_INPUT | MUX_MODE2)    /* gpmc_a10.rgmii2_rd1 */
-                       0x64 (PIN_INPUT | MUX_MODE2)    /* gpmc_a9.rgmii2_rd2 */
-                       0x60 (PIN_INPUT | MUX_MODE2)    /* gpmc_a8.rgmii2_rd3 */
+                       AM4372_IOPAD(0x858, PIN_OUTPUT | MUX_MODE2)     /* gpmc_a6.rgmii2_tclk */
+                       AM4372_IOPAD(0x840, PIN_OUTPUT | MUX_MODE2)     /* gpmc_a0.rgmii2_tctl */
+                       AM4372_IOPAD(0x854, PIN_OUTPUT | MUX_MODE2)     /* gpmc_a5.rgmii2_td0 */
+                       AM4372_IOPAD(0x850, PIN_OUTPUT | MUX_MODE2)     /* gpmc_a4.rgmii2_td1 */
+                       AM4372_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE2)     /* gpmc_a3.rgmii2_td2 */
+                       AM4372_IOPAD(0x848, PIN_OUTPUT | MUX_MODE2)     /* gpmc_a2.rgmii2_td3 */
+                       AM4372_IOPAD(0x85c, PIN_INPUT | MUX_MODE2)      /* gpmc_a7.rgmii2_rclk */
+                       AM4372_IOPAD(0x844, PIN_INPUT | MUX_MODE2)      /* gpmc_a1.rgmii2_rtcl */
+                       AM4372_IOPAD(0x86c, PIN_INPUT | MUX_MODE2)      /* gpmc_a11.rgmii2_rd0 */
+                       AM4372_IOPAD(0x868, PIN_INPUT | MUX_MODE2)      /* gpmc_a10.rgmii2_rd1 */
+                       AM4372_IOPAD(0x864, PIN_INPUT | MUX_MODE2)      /* gpmc_a9.rgmii2_rd2 */
+                       AM4372_IOPAD(0x860, PIN_INPUT | MUX_MODE2)      /* gpmc_a8.rgmii2_rd3 */
                >;
        };
 
        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
-                       0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
 
                        /* Slave 2 reset value */
-                       0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
                >;
        };
 
        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* MDIO */
-                       0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0)   /* mdio_data.mdio_data */
-                       0x14c (PIN_OUTPUT | MUX_MODE0)                  /* mdio_clk.mdio_clk */
+                       AM4372_IOPAD(0x948, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0)      /* mdio_data.mdio_data */
+                       AM4372_IOPAD(0x94c, PIN_OUTPUT | MUX_MODE0)                     /* mdio_clk.mdio_clk */
                >;
        };
 
        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
-                       0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
-                       0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
                >;
        };
 
        dss_pins: dss_pins {
                pinctrl-single,pins = <
-                       0x020 (PIN_OUTPUT | MUX_MODE1)  /* gpmc ad 8 -> DSS DATA 23 */
-                       0x024 (PIN_OUTPUT | MUX_MODE1)
-                       0x028 (PIN_OUTPUT | MUX_MODE1)
-                       0x02c (PIN_OUTPUT | MUX_MODE1)
-                       0x030 (PIN_OUTPUT | MUX_MODE1)
-                       0x034 (PIN_OUTPUT | MUX_MODE1)
-                       0x038 (PIN_OUTPUT | MUX_MODE1)
-                       0x03c (PIN_OUTPUT | MUX_MODE1)  /* gpmc ad 15 -> DSS DATA 16 */
-                       0x0a0 (PIN_OUTPUT | MUX_MODE0)  /* DSS DATA 0 */
-                       0x0a4 (PIN_OUTPUT | MUX_MODE0)
-                       0x0a8 (PIN_OUTPUT | MUX_MODE0)
-                       0x0ac (PIN_OUTPUT | MUX_MODE0)
-                       0x0b0 (PIN_OUTPUT | MUX_MODE0)
-                       0x0b4 (PIN_OUTPUT | MUX_MODE0)
-                       0x0b8 (PIN_OUTPUT | MUX_MODE0)
-                       0x0bc (PIN_OUTPUT | MUX_MODE0)
-                       0x0c0 (PIN_OUTPUT | MUX_MODE0)
-                       0x0c4 (PIN_OUTPUT | MUX_MODE0)
-                       0x0c8 (PIN_OUTPUT | MUX_MODE0)
-                       0x0cc (PIN_OUTPUT | MUX_MODE0)
-                       0x0d0 (PIN_OUTPUT | MUX_MODE0)
-                       0x0d4 (PIN_OUTPUT | MUX_MODE0)
-                       0x0d8 (PIN_OUTPUT | MUX_MODE0)
-                       0x0dc (PIN_OUTPUT | MUX_MODE0)  /* DSS DATA 15 */
-                       0x0e0 (PIN_OUTPUT | MUX_MODE0)  /* DSS VSYNC */
-                       0x0e4 (PIN_OUTPUT | MUX_MODE0)  /* DSS HSYNC */
-                       0x0e8 (PIN_OUTPUT | MUX_MODE0)  /* DSS PCLK */
-                       0x0ec (PIN_OUTPUT | MUX_MODE0)  /* DSS AC BIAS EN */
+                       AM4372_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1)     /* gpmc ad 8 -> DSS DATA 23 */
+                       AM4372_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1)
+                       AM4372_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1)
+                       AM4372_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1)
+                       AM4372_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1)
+                       AM4372_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1)
+                       AM4372_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1)
+                       AM4372_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1)     /* gpmc ad 15 -> DSS DATA 16 */
+                       AM4372_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)     /* DSS DATA 0 */
+                       AM4372_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)
+                       AM4372_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)
+                       AM4372_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)
+                       AM4372_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)
+                       AM4372_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)
+                       AM4372_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)
+                       AM4372_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)
+                       AM4372_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)
+                       AM4372_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)
+                       AM4372_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)
+                       AM4372_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)
+                       AM4372_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)
+                       AM4372_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)
+                       AM4372_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)
+                       AM4372_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)     /* DSS DATA 15 */
+                       AM4372_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)     /* DSS VSYNC */
+                       AM4372_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)     /* DSS HSYNC */
+                       AM4372_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)     /* DSS PCLK */
+                       AM4372_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)     /* DSS AC BIAS EN */
 
                >;
        };
 
        qspi_pins: qspi_pins {
                pinctrl-single,pins = <
-                       0x7c (PIN_OUTPUT | MUX_MODE3)   /* gpmc_csn0.qspi_csn */
-                       0x88 (PIN_OUTPUT | MUX_MODE2)   /* gpmc_csn3.qspi_clk */
-                       0x90 (PIN_INPUT | MUX_MODE3)    /* gpmc_advn_ale.qspi_d0 */
-                       0x94 (PIN_INPUT | MUX_MODE3)    /* gpmc_oen_ren.qspi_d1 */
-                       0x98 (PIN_INPUT | MUX_MODE3)    /* gpmc_wen.qspi_d2 */
-                       0x9c (PIN_INPUT | MUX_MODE3)    /* gpmc_be0n_cle.qspi_d3 */
+                       AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE3)     /* gpmc_csn0.qspi_csn */
+                       AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2)     /* gpmc_csn3.qspi_clk */
+                       AM4372_IOPAD(0x890, PIN_INPUT | MUX_MODE3)      /* gpmc_advn_ale.qspi_d0 */
+                       AM4372_IOPAD(0x894, PIN_INPUT | MUX_MODE3)      /* gpmc_oen_ren.qspi_d1 */
+                       AM4372_IOPAD(0x898, PIN_INPUT | MUX_MODE3)      /* gpmc_wen.qspi_d2 */
+                       AM4372_IOPAD(0x89c, PIN_INPUT | MUX_MODE3)      /* gpmc_be0n_cle.qspi_d3 */
                >;
        };
 
        mcasp1_pins: mcasp1_pins {
                pinctrl-single,pins = <
-                       0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4)  /* mii1_crs.mcasp1_aclkx */
-                       0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4)  /* mii1_rxerr.mcasp1_fsx */
-                       0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
-                       0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4)  /* rmii1_ref_clk.mcasp1_axr3 */
+                       AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4)     /* mii1_crs.mcasp1_aclkx */
+                       AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4)     /* mii1_rxerr.mcasp1_fsx */
+                       AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4)    /* mii1_col.mcasp1_axr2 */
+                       AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4)     /* rmii1_ref_clk.mcasp1_axr3 */
                >;
        };
 
        lcd_pins: lcd_pins {
                pinctrl-single,pins = <
-                       0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */
+                       AM4372_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */
                >;
        };
 
        usb1_pins: usb1_pins {
                pinctrl-single,pins = <
-                       0x2c0 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
+                       AM4372_IOPAD(0xac0, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
                >;
        };
 
        usb2_pins: usb2_pins {
                pinctrl-single,pins = <
-                       0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
+                       AM4372_IOPAD(0xac4, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
                >;
        };
 };

diff --git a/arch/arm/dts/am43x-epos-evm.dts b/arch/arm/dts/am43x-epos-evm.dts
index b940bc6..90455a6 100644 (file)
--- a/arch/arm/dts/am43x-epos-evm.dts
+++ b/arch/arm/dts/am43x-epos-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /* AM43x EPOS EVM */

diff --git a/arch/arm/dts/am43xx-clocks.dtsi b/arch/arm/dts/am43xx-clocks.dtsi
index b1127b5..07ed769 100644 (file)
--- a/arch/arm/dts/am43xx-clocks.dtsi
+++ b/arch/arm/dts/am43xx-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for AM43xx clock data
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 &scm_clocks {
        sys_clkin_ck: sys_clkin_ck {

diff --git a/arch/arm/dts/am571x-idk.dts b/arch/arm/dts/am571x-idk.dts
index 798fbfe..b3592b2 100644 (file)
--- a/arch/arm/dts/am571x-idk.dts
+++ b/arch/arm/dts/am571x-idk.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -77,17 +74,17 @@
 
 &mailbox5 {
        status = "okay";
-       mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+       mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
                status = "okay";
        };
-       mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+       mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
                status = "okay";
        };
 };
 
 &mailbox6 {
        status = "okay";
-       mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+       mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
                status = "okay";
        };
 };

diff --git a/arch/arm/dts/am5729-beagleboneai.dts b/arch/arm/dts/am5729-beagleboneai.dts
index 3429303..f772aef 100644 (file)
--- a/arch/arm/dts/am5729-beagleboneai.dts
+++ b/arch/arm/dts/am5729-beagleboneai.dts
@@ -4,6 +4,7 @@
  */
 
 /dts-v1/;
+
 #include "dra74x.dtsi"
 #include "dra74x-mmc-iodelay.dtsi"
 #include <dt-bindings/gpio/gpio.h>

diff --git a/arch/arm/dts/am572x-idk-common.dtsi b/arch/arm/dts/am572x-idk-common.dtsi
index c6d858b..c7dc844 100644 (file)
--- a/arch/arm/dts/am572x-idk-common.dtsi
+++ b/arch/arm/dts/am572x-idk-common.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -81,20 +81,20 @@
 
 &mailbox5 {
        status = "okay";
-       mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+       mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
                status = "okay";
        };
-       mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+       mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
                status = "okay";
        };
 };
 
 &mailbox6 {
        status = "okay";
-       mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+       mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
                status = "okay";
        };
-       mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+       mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
                status = "okay";
        };
 };

diff --git a/arch/arm/dts/am572x-idk.dts b/arch/arm/dts/am572x-idk.dts
index 42e88c1..ed9b912 100644 (file)
--- a/arch/arm/dts/am572x-idk.dts
+++ b/arch/arm/dts/am572x-idk.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /dts-v1/;

diff --git a/arch/arm/dts/am574x-idk.dts b/arch/arm/dts/am574x-idk.dts
index 0de7361..dd3f2ac 100644 (file)
--- a/arch/arm/dts/am574x-idk.dts
+++ b/arch/arm/dts/am574x-idk.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 

diff --git a/arch/arm/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/dts/am57xx-beagle-x15-common.dtsi
index 1912ea9..22d8d3d 100644 (file)
--- a/arch/arm/dts/am57xx-beagle-x15-common.dtsi
+++ b/arch/arm/dts/am57xx-beagle-x15-common.dtsi
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -571,20 +568,20 @@
 
 &mailbox5 {
        status = "okay";
-       mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+       mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
                status = "okay";
        };
-       mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+       mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
                status = "okay";
        };
 };
 
 &mailbox6 {
        status = "okay";
-       mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+       mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
                status = "okay";
        };
-       mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+       mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
                status = "okay";
        };
 };

diff --git a/arch/arm/dts/am57xx-beagle-x15-revb1.dts b/arch/arm/dts/am57xx-beagle-x15-revb1.dts
index 34c6996..9f65d36 100644 (file)
--- a/arch/arm/dts/am57xx-beagle-x15-revb1.dts
+++ b/arch/arm/dts/am57xx-beagle-x15-revb1.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "am57xx-beagle-x15-common.dtsi"

diff --git a/arch/arm/dts/am57xx-beagle-x15-revc.dts b/arch/arm/dts/am57xx-beagle-x15-revc.dts
index ccd9916..803c7f4 100644 (file)
--- a/arch/arm/dts/am57xx-beagle-x15-revc.dts
+++ b/arch/arm/dts/am57xx-beagle-x15-revc.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "am57xx-beagle-x15-common.dtsi"

diff --git a/arch/arm/dts/am57xx-beagle-x15.dts b/arch/arm/dts/am57xx-beagle-x15.dts
index 8d9bdf1..6373697 100644 (file)
--- a/arch/arm/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/dts/am57xx-beagle-x15.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "am57xx-beagle-x15-common.dtsi"

diff --git a/arch/arm/dts/am57xx-idk-common-u-boot.dtsi b/arch/arm/dts/am57xx-idk-common-u-boot.dtsi
index d0ce469..b07aea0 100644 (file)
--- a/arch/arm/dts/am57xx-idk-common-u-boot.dtsi
+++ b/arch/arm/dts/am57xx-idk-common-u-boot.dtsi
@@ -3,7 +3,6 @@
  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
  */
 #include "omap5-u-boot.dtsi"
-#include "dra7-ipu-common-early-boot.dtsi"
 
 / {
        xtal25mhz: xtal25mhz {

diff --git a/arch/arm/dts/am57xx-idk-common.dtsi b/arch/arm/dts/am57xx-idk-common.dtsi
index 590fb14..b83c9e9 100644 (file)
--- a/arch/arm/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/dts/am57xx-idk-common.dtsi
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "am57xx-industrial-grade.dtsi"
@@ -440,7 +437,7 @@
        status = "okay";
 
        spi-max-frequency = <76800000>;
-       m25p80@0 {
+       flash@0 {
                compatible = "s25fl256s1", "jedec,spi-nor";
                spi-max-frequency = <76800000>;
                reg = <0>;
@@ -456,7 +453,7 @@
                 */
                partition@0 {
                        label = "QSPI.SPL";
-                       reg = <0x00000000 0x000040000>;
+                       reg = <0x00000000 0x00040000>;
                };
                partition@1 {
                        label = "QSPI.u-boot";

diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi
index 4e46826..533dfdf 100644 (file)
--- a/arch/arm/dts/corstone1000.dtsi
+++ b/arch/arm/dts/corstone1000.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0 or MIT
 /*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
  * Copyright (c) 2022, Linaro Limited. All rights reserved.
  *
  */
@@ -38,6 +38,13 @@
                reg = <0x88200000 0x77e00000>;
        };
 
+       nvmxip-qspi@08000000 {
+               compatible = "nvmxip,qspi";
+               reg = <0x08000000 0x2000000>;
+               lba_shift = <9>;
+               lba = <65536>;
+       };
+
        gic: interrupt-controller@1c000000 {
                compatible = "arm,gic-400";
                #interrupt-cells = <3>;

diff --git a/arch/arm/dts/da850-evm.dts b/arch/arm/dts/da850-evm.dts
index b331cef..378af9f 100644 (file)
--- a/arch/arm/dts/da850-evm.dts
+++ b/arch/arm/dts/da850-evm.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree for DA850 EVM board
  *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation, version 2.
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 #include "da850.dtsi"
@@ -55,15 +52,15 @@
                enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */
 
                panel-info {
-                       ac-bias         = <255>;
-                       ac-bias-intrpt  = <0>;
-                       dma-burst-sz    = <16>;
-                       bpp             = <16>;
-                       fdd             = <0x80>;
-                       sync-edge       = <0>;
-                       sync-ctrl       = <1>;
-                       raster-order    = <0>;
-                       fifo-th         = <0>;
+                       ac-bias = <255>;
+                       ac-bias-intrpt = <0>;
+                       dma-burst-sz = <16>;
+                       bpp = <16>;
+                       fdd = <0x80>;
+                       sync-edge = <0>;
+                       sync-ctrl = <1>;
+                       raster-order = <0>;
+                       fifo-th = <0>;
                };
 
                display-timings {
@@ -268,7 +265,7 @@
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&spi1_pins &spi1_cs0_pin>;
-       flash: m25p80@0 {
+       flash: flash@0 {
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "m25p64";

diff --git a/arch/arm/dts/da850-lcdk.dts b/arch/arm/dts/da850-lcdk.dts
index db8ae56..9c8e9f0 100644 (file)
--- a/arch/arm/dts/da850-lcdk.dts
+++ b/arch/arm/dts/da850-lcdk.dts
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2016 BayLibre, Inc.
- *
- * Licensed under GPLv2.
  */
 /dts-v1/;
 #include "da850.dtsi"

diff --git a/arch/arm/dts/da850-lego-ev3.dts b/arch/arm/dts/da850-lego-ev3.dts
index e281d03..7207d12 100644 (file)
--- a/arch/arm/dts/da850-lego-ev3.dts
+++ b/arch/arm/dts/da850-lego-ev3.dts
@@ -1,12 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device tree for LEGO MINDSTORMS EV3
  *
  * Copyright (C) 2017 David Lechner <david@lechnology.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- *
- * This is an absolute minimum device tree instead of using the one from Linux
- * because the bootloader on the EV3 is limited to 256k. This saves us >10k.
  */
 
 /dts-v1/;
@@ -26,7 +22,7 @@
                stdout-path = &serial1;
        };
 
-       memory {
+       memory@c0000000 {
                device_type = "memory";
                reg = <0xc0000000 0x04000000>;
        };

diff --git a/arch/arm/dts/da850.dtsi b/arch/arm/dts/da850.dtsi
index 559659b..c96f64b 100644 (file)
--- a/arch/arm/dts/da850.dtsi
+++ b/arch/arm/dts/da850.dtsi
@@ -1,11 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
 /*
  * Copyright 2012 DENX Software Engineering GmbH
  * Heiko Schocher <hs@denx.de>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
  */
 #include <dt-bindings/interrupt-controller/irq.h>
 
@@ -373,7 +369,7 @@
                edma0: edma@0 {
                        compatible = "ti,edma3-tpcc";
                        /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
-                       reg =   <0x0 0x8000>;
+                       reg = <0x0 0x8000>;
                        reg-names = "edma3_cc";
                        interrupts = <11 12>;
                        interrupt-names = "edma3_ccint", "edma3_ccerrint";
@@ -384,14 +380,14 @@
                };
                edma0_tptc0: tptc@8000 {
                        compatible = "ti,edma3-tptc";
-                       reg =   <0x8000 0x400>;
+                       reg = <0x8000 0x400>;
                        interrupts = <13>;
                        interrupt-names = "edm3_tcerrint";
                        power-domains = <&psc0 1>;
                };
                edma0_tptc1: tptc@8400 {
                        compatible = "ti,edma3-tptc";
-                       reg =   <0x8400 0x400>;
+                       reg = <0x8400 0x400>;
                        interrupts = <32>;
                        interrupt-names = "edm3_tcerrint";
                        power-domains = <&psc0 2>;
@@ -399,7 +395,7 @@
                edma1: edma@230000 {
                        compatible = "ti,edma3-tpcc";
                        /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
-                       reg =   <0x230000 0x8000>;
+                       reg = <0x230000 0x8000>;
                        reg-names = "edma3_cc";
                        interrupts = <93 94>;
                        interrupt-names = "edma3_ccint", "edma3_ccerrint";
@@ -410,7 +406,7 @@
                };
                edma1_tptc0: tptc@238000 {
                        compatible = "ti,edma3-tptc";
-                       reg =   <0x238000 0x400>;
+                       reg = <0x238000 0x400>;
                        interrupts = <95>;
                        interrupt-names = "edm3_tcerrint";
                        power-domains = <&psc1 21>;
@@ -547,7 +543,7 @@
                        power-domains = <&psc1 17>;
                        status = "disabled";
                };
-               ecap0: ecap@306000 {
+               ecap0: pwm@306000 {
                        compatible = "ti,da850-ecap", "ti,am3352-ecap",
                                     "ti,am33xx-ecap";
                        #pwm-cells = <3>;
@@ -557,7 +553,7 @@
                        power-domains = <&psc1 20>;
                        status = "disabled";
                };
-               ecap1: ecap@307000 {
+               ecap1: pwm@307000 {
                        compatible = "ti,da850-ecap", "ti,am3352-ecap",
                                     "ti,am33xx-ecap";
                        #pwm-cells = <3>;
@@ -567,7 +563,7 @@
                        power-domains = <&psc1 20>;
                        status = "disabled";
                };
-               ecap2: ecap@308000 {
+               ecap2: pwm@308000 {
                        compatible = "ti,da850-ecap", "ti,am3352-ecap",
                                     "ti,am33xx-ecap";
                        #pwm-cells = <3>;
@@ -631,7 +627,7 @@
 
                        cppi41dma: dma-controller@201000 {
                                compatible = "ti,da830-cppi41";
-                               reg =  <0x201000 0x1000
+                               reg = <0x201000 0x1000
                                        0x202000 0x1000
                                        0x204000 0x4000>;
                                reg-names = "controller",

diff --git a/arch/arm/dts/dm8168-evm.dts b/arch/arm/dts/dm8168-evm.dts
index 0bf55fa..70255ab 100644 (file)
--- a/arch/arm/dts/dm8168-evm.dts
+++ b/arch/arm/dts/dm8168-evm.dts
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
 /dts-v1/;
 
 #include "dm816x.dtsi"
@@ -120,19 +116,19 @@
                        label = "X-Loader";
                        reg = <0 0x80000>;
                };
-               partition@0x80000 {
+               partition@80000 {
                        label = "U-Boot";
                        reg = <0x80000 0x1c0000>;
                };
-               partition@0x1c0000 {
+               partition@1c0000 {
                        label = "Environment";
                        reg = <0x240000 0x40000>;
                };
-               partition@0x280000 {
+               partition@280000 {
                        label = "Kernel";
                        reg = <0x280000 0x500000>;
                };
-               partition@0x780000 {
+               partition@780000 {
                        label = "Filesystem";
                        reg = <0x780000 0xf880000>;
                };
@@ -143,7 +139,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&mcspi1_pins>;
 
-       m25p80@0 {
+       flash@0 {
                compatible = "w25x32";
                spi-max-frequency = <48000000>;
                reg = <0>;

diff --git a/arch/arm/dts/dm816x-clocks.dtsi b/arch/arm/dts/dm816x-clocks.dtsi
index 51865eb..f7a839d 100644 (file)
--- a/arch/arm/dts/dm816x-clocks.dtsi
+++ b/arch/arm/dts/dm816x-clocks.dtsi
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
 
 &scrm {
        main_fapll: main_fapll {

diff --git a/arch/arm/dts/dm816x.dtsi b/arch/arm/dts/dm816x.dtsi
index fe58faf..c4a8653 100644 (file)
--- a/arch/arm/dts/dm816x.dtsi
+++ b/arch/arm/dts/dm816x.dtsi
@@ -1,8 +1,4 @@
-/*
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/omap.h>
@@ -67,8 +63,11 @@
                ranges;
 
                prcm: prcm@48180000 {
-                       compatible = "ti,dm816-prcm";
+                       compatible = "ti,dm816-prcm", "simple-bus";
                        reg = <0x48180000 0x4000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0 0x48180000 0x4000>;
 
                        prcm_clocks: clocks {
                                #address-cells = <1>;
@@ -90,6 +89,8 @@
                        dm816x_pinmux: pinmux@800 {
                                compatible = "pinctrl-single";
                                reg = <0x800 0x50a>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
                                #pinctrl-cells = <1>;
                                pinctrl-single,register-width = <16>;
                                pinctrl-single,function-mask = <0xf>;
@@ -125,6 +126,8 @@
                        };
 
                        scrm_clocks: clocks {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
                        };
 
                        scrm_clockdomains: clockdomains {
@@ -232,7 +235,7 @@
                        #mbox-cells = <1>;
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <12>;
-                       mbox_dsp: mbox_dsp {
+                       mbox_dsp: mbox-dsp {
                                ti,mbox-tx = <3 0 0>;
                                ti,mbox-rx = <0 0 0>;
                        };
@@ -368,7 +371,7 @@
                        ti,timer-pwm;
                };
 
-               uart1: uart@48020000 {
+               uart1: serial@48020000 {
                        compatible = "ti,am3352-uart", "ti,omap3-uart";
                        ti,hwmods = "uart1";
                        reg = <0x48020000 0x2000>;
@@ -378,7 +381,7 @@
                        dma-names = "tx", "rx";
                };
 
-               uart2: uart@48022000 {
+               uart2: serial@48022000 {
                        compatible = "ti,am3352-uart", "ti,omap3-uart";
                        ti,hwmods = "uart2";
                        reg = <0x48022000 0x2000>;
@@ -388,7 +391,7 @@
                        dma-names = "tx", "rx";
                };
 
-               uart3: uart@48024000 {
+               uart3: serial@48024000 {
                        compatible = "ti,am3352-uart", "ti,omap3-uart";
                        ti,hwmods = "uart3";
                        reg = <0x48024000 0x2000>;

diff --git a/arch/arm/dts/dra7-dspeve-thermal.dtsi b/arch/arm/dts/dra7-dspeve-thermal.dtsi
index 1c39a84..747ff0d 100644 (file)
--- a/arch/arm/dts/dra7-dspeve-thermal.dtsi
+++ b/arch/arm/dts/dra7-dspeve-thermal.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for DRA7x SoC DSPEVE thermal
  *
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/thermal/thermal.h>

diff --git a/arch/arm/dts/dra7-evm-common.dtsi b/arch/arm/dts/dra7-evm-common.dtsi
index 343e95f..8f3a005 100644 (file)
--- a/arch/arm/dts/dra7-evm-common.dtsi
+++ b/arch/arm/dts/dra7-evm-common.dtsi
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -132,7 +129,7 @@
        status = "okay";
 
        spi-max-frequency = <76800000>;
-       m25p80@0 {
+       flash@0 {
                compatible = "s25fl256s1";
                spi-max-frequency = <76800000>;
                reg = <0>;
@@ -148,7 +145,7 @@
                 */
                partition@0 {
                        label = "QSPI.SPL";
-                       reg = <0x00000000 0x000010000>;
+                       reg = <0x00000000 0x00010000>;
                };
                partition@1 {
                        label = "QSPI.SPL.backup1";
@@ -239,20 +236,20 @@
 
 &mailbox5 {
        status = "okay";
-       mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+       mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
                status = "okay";
        };
-       mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+       mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
                status = "okay";
        };
 };
 
 &mailbox6 {
        status = "okay";
-       mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+       mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
                status = "okay";
        };
-       mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+       mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
                status = "okay";
        };
 };

diff --git a/arch/arm/dts/dra7-evm-u-boot.dtsi b/arch/arm/dts/dra7-evm-u-boot.dtsi
index f1ff5f6..87b2451 100644 (file)
--- a/arch/arm/dts/dra7-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra7-evm-u-boot.dtsi
@@ -4,7 +4,6 @@
  */
 
 #include "omap5-u-boot.dtsi"
-#include "dra7-ipu-common-early-boot.dtsi"
 
 &pcf_gpio_21{
        u-boot,i2c-offset-len = <0>;

diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts
index 8e9a1a8..5333f17 100644 (file)
--- a/arch/arm/dts/dra7-evm.dts
+++ b/arch/arm/dts/dra7-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -315,7 +312,7 @@
                reg = <0x26>;
                gpio-controller;
                #gpio-cells = <2>;
-               p1 {
+               hdmi-audio-hog {
                        /* vin6_sel_s0: high: VIN6, low: audio */
                        gpio-hog;
                        gpios = <1 GPIO_ACTIVE_HIGH>;
@@ -419,7 +416,7 @@
                #size-cells = <1>;
                partition@0 {
                        label = "NAND.SPL";
-                       reg = <0x00000000 0x000020000>;
+                       reg = <0x00000000 0x00020000>;
                };
                partition@1 {
                        label = "NAND.SPL.backup1";

diff --git a/arch/arm/dts/dra7-iva-thermal.dtsi b/arch/arm/dts/dra7-iva-thermal.dtsi
index dd74a53..0a31313 100644 (file)
--- a/arch/arm/dts/dra7-iva-thermal.dtsi
+++ b/arch/arm/dts/dra7-iva-thermal.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for DRA7x SoC IVA thermal
  *
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/thermal/thermal.h>

diff --git a/arch/arm/dts/dra7-mmc-iodelay.dtsi b/arch/arm/dts/dra7-mmc-iodelay.dtsi
index 4acc215..d46a1c0 100644 (file)
--- a/arch/arm/dts/dra7-mmc-iodelay.dtsi
+++ b/arch/arm/dts/dra7-mmc-iodelay.dtsi
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * MMC IOdelay values for TI's DRA7xx SoCs.
- * Copyright (C) 2019 Texas Instruments
+ * Copyright (C) 2018 Texas Instruments
  * Author: Faiz Abbas <faiz_abbas@ti.com>
  */
 

diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index e2e958b..b1aef63 100644 (file)
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -1,9 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  * Based on "omap4.dtsi"
  */
 
@@ -134,7 +132,7 @@
         * the moment, just use a fake OCP bus entry to represent the whole bus
         * hierarchy.
         */
-       ocp {
+       ocp: ocp {
                compatible = "ti,dra7-l3-noc", "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
@@ -357,7 +355,13 @@
                        };
                };
 
-               axi@1 {
+               /*
+                * Register access seems to have complex dependencies and also
+                * seems to need an enabled phy. See the TRM chapter for "Table
+                * 26-678. Main Sequence PCIe Controller Global Initialization"
+                * and also dra7xx_pcie_probe().
+                */
+               axi1: target-module@51800000 {
                        compatible = "simple-bus";
                        #size-cells = <1>;
                        #address-cells = <1>;
@@ -372,8 +376,8 @@
                                #address-cells = <3>;
                                #size-cells = <2>;
                                device_type = "pci";
-                               ranges = <0x81000000 0 0          0x03000 0 0x00010000
-                                         0x82000000 0 0x30013000 0x13000 0 0xffed000>;
+                               ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>,
+                                        <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>;
                                bus-range = <0x00 0xff>;
                                #interrupt-cells = <1>;
                                num-lanes = <1>;
@@ -2112,4 +2116,4 @@
        temperature = <120000>; /* milli Celsius */
 };
 
-/include/ "dra7xx-clocks.dtsi"
+#include "dra7xx-clocks.dtsi"

diff --git a/arch/arm/dts/dra71-evm-u-boot.dtsi b/arch/arm/dts/dra71-evm-u-boot.dtsi
index f13eadf..8e7dc71 100644 (file)
--- a/arch/arm/dts/dra71-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra71-evm-u-boot.dtsi
@@ -4,7 +4,6 @@
  */
 
 #include "omap5-u-boot.dtsi"
-#include "dra7-ipu-common-early-boot.dtsi"
 
 &pcf_gpio_21{
        u-boot,i2c-offset-len = <0>;

diff --git a/arch/arm/dts/dra71-evm.dts b/arch/arm/dts/dra71-evm.dts
index 9bf0829..b322598 100644 (file)
--- a/arch/arm/dts/dra71-evm.dts
+++ b/arch/arm/dts/dra71-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "dra72-evm-common.dtsi"
@@ -160,7 +157,7 @@
 };
 
 &pcf_hdmi {
-       p0 {
+       hdmi-i2c-disable-hog {
                /*
                 * PM_OEn to High: Disable routing I2C3 to PM_I2C
                 * With this PM_SEL(p3) should not matter

diff --git a/arch/arm/dts/dra72-evm-common.dtsi b/arch/arm/dts/dra72-evm-common.dtsi
index 964e5e9..aa7a1c6 100644 (file)
--- a/arch/arm/dts/dra72-evm-common.dtsi
+++ b/arch/arm/dts/dra72-evm-common.dtsi
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -272,7 +269,7 @@
                 */
                lines-initial-states = <0x0f2b>;
 
-               p1 {
+               hdmi-audio-hog {
                        /* vin6_sel_s0: high: VIN6, low: audio */
                        gpio-hog;
                        gpios = <1 GPIO_ACTIVE_HIGH>;
@@ -343,7 +340,7 @@
                #size-cells = <1>;
                partition@0 {
                        label = "NAND.SPL";
-                       reg = <0x00000000 0x000020000>;
+                       reg = <0x00000000 0x00020000>;
                };
                partition@1 {
                        label = "NAND.SPL.backup1";
@@ -441,7 +438,7 @@
        status = "okay";
 
        spi-max-frequency = <76800000>;
-       m25p80@0 {
+       flash@0 {
                compatible = "s25fl256s1";
                spi-max-frequency = <76800000>;
                reg = <0>;
@@ -457,7 +454,7 @@
                 */
                partition@0 {
                        label = "QSPI.SPL";
-                       reg = <0x00000000 0x000010000>;
+                       reg = <0x00000000 0x00010000>;
                };
                partition@1 {
                        label = "QSPI.SPL.backup1";
@@ -549,17 +546,17 @@
 
 &mailbox5 {
        status = "okay";
-       mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+       mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
                status = "okay";
        };
-       mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+       mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
                status = "okay";
        };
 };
 
 &mailbox6 {
        status = "okay";
-       mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+       mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
                status = "okay";
        };
 };

diff --git a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
index f13eadf..8e7dc71 100644 (file)
--- a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
+++ b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
@@ -4,7 +4,6 @@
  */
 
 #include "omap5-u-boot.dtsi"
-#include "dra7-ipu-common-early-boot.dtsi"
 
 &pcf_gpio_21{
        u-boot,i2c-offset-len = <0>;

diff --git a/arch/arm/dts/dra72-evm-revc.dts b/arch/arm/dts/dra72-evm-revc.dts
index fafc2a4..a6dbdd5 100644 (file)
--- a/arch/arm/dts/dra72-evm-revc.dts
+++ b/arch/arm/dts/dra72-evm-revc.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 #include "dra72-evm-common.dtsi"
 #include "dra72x-mmc-iodelay.dtsi"

diff --git a/arch/arm/dts/dra72-evm-tps65917.dtsi b/arch/arm/dts/dra72-evm-tps65917.dtsi
index 57bfe5c..c7b4768 100644 (file)
--- a/arch/arm/dts/dra72-evm-tps65917.dtsi
+++ b/arch/arm/dts/dra72-evm-tps65917.dtsi
@@ -1,14 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /*
  * Integrated Power Management Chip
- * http://www.ti.com/lit/ds/symlink/tps65917-q1.pdf
+ * https://www.ti.com/lit/ds/symlink/tps65917-q1.pdf
  */
 
 &tps65917 {

diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts
index 154b0a0..2f24412 100644 (file)
--- a/arch/arm/dts/dra72-evm.dts
+++ b/arch/arm/dts/dra72-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
  */
 #include "dra72-evm-common.dtsi"
 #include "dra72x-mmc-iodelay.dtsi"

diff --git a/arch/arm/dts/dra72x-mmc-iodelay.dtsi b/arch/arm/dts/dra72x-mmc-iodelay.dtsi
index 088013c..98f2eac 100644 (file)
--- a/arch/arm/dts/dra72x-mmc-iodelay.dtsi
+++ b/arch/arm/dts/dra72x-mmc-iodelay.dtsi
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs.
  *
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /*

diff --git a/arch/arm/dts/dra72x.dtsi b/arch/arm/dts/dra72x.dtsi
index 6710760..481189d 100644 (file)
--- a/arch/arm/dts/dra72x.dtsi
+++ b/arch/arm/dts/dra72x.dtsi
@@ -1,9 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  * Based on "omap4.dtsi"
  */
 
@@ -31,12 +29,12 @@
 };
 
 &mailbox5 {
-       mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+       mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
                ti,mbox-tx = <6 2 2>;
                ti,mbox-rx = <4 2 2>;
                status = "disabled";
        };
-       mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+       mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
                ti,mbox-tx = <5 2 2>;
                ti,mbox-rx = <1 2 2>;
                status = "disabled";
@@ -44,7 +42,7 @@
 };
 
 &mailbox6 {
-       mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+       mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
                ti,mbox-tx = <6 2 2>;
                ti,mbox-rx = <4 2 2>;
                status = "disabled";

diff --git a/arch/arm/dts/dra74x-mmc-iodelay.dtsi b/arch/arm/dts/dra74x-mmc-iodelay.dtsi
index 214b9e6..b9d0401 100644 (file)
--- a/arch/arm/dts/dra74x-mmc-iodelay.dtsi
+++ b/arch/arm/dts/dra74x-mmc-iodelay.dtsi
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs.
  *
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /*

diff --git a/arch/arm/dts/dra74x.dtsi b/arch/arm/dts/dra74x.dtsi
index 24e6746..9ade216 100644 (file)
--- a/arch/arm/dts/dra74x.dtsi
+++ b/arch/arm/dts/dra74x.dtsi
@@ -1,9 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  * Based on "omap4.dtsi"
  */
 
@@ -100,12 +98,12 @@
 };
 
 &mailbox5 {
-       mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+       mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
                ti,mbox-tx = <6 2 2>;
                ti,mbox-rx = <4 2 2>;
                status = "disabled";
        };
-       mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+       mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
                ti,mbox-tx = <5 2 2>;
                ti,mbox-rx = <1 2 2>;
                status = "disabled";
@@ -113,12 +111,12 @@
 };
 
 &mailbox6 {
-       mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+       mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
                ti,mbox-tx = <6 2 2>;
                ti,mbox-rx = <4 2 2>;
                status = "disabled";
        };
-       mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+       mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
                ti,mbox-tx = <5 2 2>;
                ti,mbox-rx = <1 2 2>;
                status = "disabled";

diff --git a/arch/arm/dts/dra76-evm-u-boot.dtsi b/arch/arm/dts/dra76-evm-u-boot.dtsi
index db5a466..1216d93 100644 (file)
--- a/arch/arm/dts/dra76-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra76-evm-u-boot.dtsi
@@ -4,7 +4,6 @@
  */
 
 #include "omap5-u-boot.dtsi"
-#include "dra7-ipu-common-early-boot.dtsi"
 
 &cpsw_emac0 {
        phy-handle = <&dp83867_0>;

diff --git a/arch/arm/dts/dra76-evm.dts b/arch/arm/dts/dra76-evm.dts
index e3da17a..c131e7f 100644 (file)
--- a/arch/arm/dts/dra76-evm.dts
+++ b/arch/arm/dts/dra76-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -274,7 +271,7 @@
                reg = <0x26>;
                gpio-controller;
                #gpio-cells = <2>;
-               p1 {
+               hdmi-audio-hog {
                        /* vin6_sel_s0: high: VIN6, low: audio */
                        gpio-hog;
                        gpios = <1 GPIO_ACTIVE_HIGH>;
@@ -382,7 +379,7 @@
 
 &qspi {
        spi-max-frequency = <96000000>;
-       m25p80@0 {
+       flash@0 {
                spi-max-frequency = <96000000>;
        };
 };

diff --git a/arch/arm/dts/dra76x.dtsi b/arch/arm/dts/dra76x.dtsi
index 1c88c58..4f0e178 100644 (file)
--- a/arch/arm/dts/dra76x.dtsi
+++ b/arch/arm/dts/dra76x.dtsi
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "dra74x.dtsi"

diff --git a/arch/arm/dts/dra7xx-clocks.dtsi b/arch/arm/dts/dra7xx-clocks.dtsi
index cf229df..b0cfe55 100644 (file)
--- a/arch/arm/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/dts/dra7xx-clocks.dtsi
@@ -1,110 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for DRA7xx clock data
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 &cm_core_aon_clocks {
-       atl_clkin0_ck: atl_clkin0_ck {
+       atl_clkin0_ck: clock-atl-clkin0 {
                #clock-cells = <0>;
                compatible = "ti,dra7-atl-clock";
                clocks = <&atl_gfclk_mux>;
        };
 
-       atl_clkin1_ck: atl_clkin1_ck {
+       atl_clkin1_ck: clock-atl-clkin1 {
                #clock-cells = <0>;
                compatible = "ti,dra7-atl-clock";
                clocks = <&atl_gfclk_mux>;
        };
 
-       atl_clkin2_ck: atl_clkin2_ck {
+       atl_clkin2_ck: clock-atl-clkin2 {
                #clock-cells = <0>;
                compatible = "ti,dra7-atl-clock";
                clocks = <&atl_gfclk_mux>;
        };
 
-       atl_clkin3_ck: atl_clkin3_ck {
+       atl_clkin3_ck: clock-atl-clkin3 {
                #clock-cells = <0>;
                compatible = "ti,dra7-atl-clock";
                clocks = <&atl_gfclk_mux>;
        };
 
-       hdmi_clkin_ck: hdmi_clkin_ck {
+       hdmi_clkin_ck: clock-hdmi-clkin {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <0>;
        };
 
-       mlb_clkin_ck: mlb_clkin_ck {
+       mlb_clkin_ck: clock-mlb-clkin {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <0>;
        };
 
-       mlbp_clkin_ck: mlbp_clkin_ck {
+       mlbp_clkin_ck: clock-mlbp-clkin {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <0>;
        };
 
-       pciesref_acs_clk_ck: pciesref_acs_clk_ck {
+       pciesref_acs_clk_ck: clock-pciesref-acs {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <100000000>;
        };
 
-       ref_clkin0_ck: ref_clkin0_ck {
+       ref_clkin0_ck: clock-ref-clkin0 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <0>;
        };
 
-       ref_clkin1_ck: ref_clkin1_ck {
+       ref_clkin1_ck: clock-ref-clkin1 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <0>;
        };
 
-       ref_clkin2_ck: ref_clkin2_ck {
+       ref_clkin2_ck: clock-ref-clkin2 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <0>;
        };
 
-       ref_clkin3_ck: ref_clkin3_ck {
+       ref_clkin3_ck: clock-ref-clkin3 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <0>;
        };
 
-       rmii_clk_ck: rmii_clk_ck {
+       rmii_clk_ck: clock-rmii {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <0>;
        };
 
-       sdvenc_clkin_ck: sdvenc_clkin_ck {
+       sdvenc_clkin_ck: clock-sdvenc-clkin {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <0>;
        };
 
-       secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+       secure_32k_clk_src_ck: clock-secure-32k-clk-src {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <32768>;
        };
 
-       sys_clk32_crystal_ck: sys_clk32_crystal_ck {
+       sys_clk32_crystal_ck: clock-sys-clk32-crystal {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <32768>;
        };
 
-       sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
+       sys_clk32_pseudo_ck: clock-sys-clk32-pseudo {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&sys_clkin1>;
@@ -112,104 +109,104 @@
                clock-div = <610>;
        };
 
-       virt_12000000_ck: virt_12000000_ck {
+       virt_12000000_ck: clock-virt-12000000 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <12000000>;
        };
 
-       virt_13000000_ck: virt_13000000_ck {
+       virt_13000000_ck: clock-virt-13000000 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <13000000>;
        };
 
-       virt_16800000_ck: virt_16800000_ck {
+       virt_16800000_ck: clock-virt-16800000 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <16800000>;
        };
 
-       virt_19200000_ck: virt_19200000_ck {
+       virt_19200000_ck: clock-virt-19200000 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <19200000>;
        };
 
-       virt_20000000_ck: virt_20000000_ck {
+       virt_20000000_ck: clock-virt-20000000 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <20000000>;
        };
 
-       virt_26000000_ck: virt_26000000_ck {
+       virt_26000000_ck: clock-virt-26000000 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <26000000>;
        };
 
-       virt_27000000_ck: virt_27000000_ck {
+       virt_27000000_ck: clock-virt-27000000 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <27000000>;
        };
 
-       virt_38400000_ck: virt_38400000_ck {
+       virt_38400000_ck: clock-virt-38400000 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <38400000>;
        };
 
-       sys_clkin2: sys_clkin2 {
+       sys_clkin2: clock-sys-clkin2 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <22579200>;
        };
 
-       usb_otg_clkin_ck: usb_otg_clkin_ck {
+       usb_otg_clkin_ck: clock-usb-otg-clkin {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <0>;
        };
 
-       video1_clkin_ck: video1_clkin_ck {
+       video1_clkin_ck: clock-video1-clkin {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <0>;
        };
 
-       video1_m2_clkin_ck: video1_m2_clkin_ck {
+       video1_m2_clkin_ck: clock-video1-m2-clkin {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <0>;
        };
 
-       video2_clkin_ck: video2_clkin_ck {
+       video2_clkin_ck: clock-video2-clkin {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <0>;
        };
 
-       video2_m2_clkin_ck: video2_m2_clkin_ck {
+       video2_m2_clkin_ck: clock-video2-m2-clkin {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <0>;
        };
 
-       dpll_abe_ck: dpll_abe_ck@1e0 {
+       dpll_abe_ck: clock@1e0 {
                #clock-cells = <0>;
                compatible = "ti,omap4-dpll-m4xen-clock";
                clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
                reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
        };
 
-       dpll_abe_x2_ck: dpll_abe_x2_ck {
+       dpll_abe_x2_ck: clock-dpll-abe-x2 {
                #clock-cells = <0>;
                compatible = "ti,omap4-dpll-x2-clock";
                clocks = <&dpll_abe_ck>;
        };
 
-       dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
+       dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_abe_x2_ck>;
@@ -220,7 +217,7 @@
                ti,invert-autoidle-bit;
        };
 
-       abe_clk: abe_clk@108 {
+       abe_clk: clock-abe@108 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_abe_m2x2_ck>;
@@ -229,7 +226,7 @@
                ti,index-power-of-two;
        };
 
-       dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
+       dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_abe_ck>;
@@ -240,7 +237,7 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
+       dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_abe_x2_ck>;
@@ -251,7 +248,7 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_core_byp_mux: dpll_core_byp_mux@12c {
+       dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -259,20 +256,20 @@
                reg = <0x012c>;
        };
 
-       dpll_core_ck: dpll_core_ck@120 {
+       dpll_core_ck: clock@120 {
                #clock-cells = <0>;
                compatible = "ti,omap4-dpll-core-clock";
                clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
                reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
        };
 
-       dpll_core_x2_ck: dpll_core_x2_ck {
+       dpll_core_x2_ck: clock-dpll-core-x2 {
                #clock-cells = <0>;
                compatible = "ti,omap4-dpll-x2-clock";
                clocks = <&dpll_core_ck>;
        };
 
-       dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
+       dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
@@ -283,7 +280,7 @@
                ti,invert-autoidle-bit;
        };
 
-       mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+       mpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_core_h12x2_ck>;
@@ -291,14 +288,14 @@
                clock-div = <1>;
        };
 
-       dpll_mpu_ck: dpll_mpu_ck@160 {
+       dpll_mpu_ck: clock@160 {
                #clock-cells = <0>;
                compatible = "ti,omap5-mpu-dpll-clock";
                clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
                reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
        };
 
-       dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
+       dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_mpu_ck>;
@@ -309,7 +306,7 @@
                ti,invert-autoidle-bit;
        };
 
-       mpu_dclk_div: mpu_dclk_div {
+       mpu_dclk_div: clock-mpu-dclk-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_mpu_m2_ck>;
@@ -317,7 +314,7 @@
                clock-div = <1>;
        };
 
-       dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
+       dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_core_h12x2_ck>;
@@ -325,7 +322,7 @@
                clock-div = <1>;
        };
 
-       dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
+       dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
@@ -333,7 +330,7 @@
                reg = <0x0240>;
        };
 
-       dpll_dsp_ck: dpll_dsp_ck@234 {
+       dpll_dsp_ck: clock@234 {
                #clock-cells = <0>;
                compatible = "ti,omap4-dpll-clock";
                clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
@@ -342,7 +339,7 @@
                assigned-clock-rates = <600000000>;
        };
 
-       dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
+       dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_dsp_ck>;
@@ -355,7 +352,7 @@
                assigned-clock-rates = <600000000>;
        };
 
-       iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+       iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_core_h12x2_ck>;
@@ -363,7 +360,7 @@
                clock-div = <1>;
        };
 
-       dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
+       dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
@@ -371,7 +368,7 @@
                reg = <0x01ac>;
        };
 
-       dpll_iva_ck: dpll_iva_ck@1a0 {
+       dpll_iva_ck: clock@1a0 {
                #clock-cells = <0>;
                compatible = "ti,omap4-dpll-clock";
                clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
@@ -380,7 +377,7 @@
                assigned-clock-rates = <1165000000>;
        };
 
-       dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
+       dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_iva_ck>;
@@ -393,7 +390,7 @@
                assigned-clock-rates = <388333334>;
        };
 
-       iva_dclk: iva_dclk {
+       iva_dclk: clock-iva-dclk {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_iva_m2_ck>;
@@ -401,7 +398,7 @@
                clock-div = <1>;
        };
 
-       dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
+       dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -409,7 +406,7 @@
                reg = <0x02e4>;
        };
 
-       dpll_gpu_ck: dpll_gpu_ck@2d8 {
+       dpll_gpu_ck: clock@2d8 {
                #clock-cells = <0>;
                compatible = "ti,omap4-dpll-clock";
                clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
@@ -418,7 +415,7 @@
                assigned-clock-rates = <1277000000>;
        };
 
-       dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
+       dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_gpu_ck>;
@@ -431,7 +428,7 @@
                assigned-clock-rates = <425666667>;
        };
 
-       dpll_core_m2_ck: dpll_core_m2_ck@130 {
+       dpll_core_m2_ck: clock-dpll-core-m2-8@130 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_ck>;
@@ -442,7 +439,7 @@
                ti,invert-autoidle-bit;
        };
 
-       core_dpll_out_dclk_div: core_dpll_out_dclk_div {
+       core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_core_m2_ck>;
@@ -450,7 +447,7 @@
                clock-div = <1>;
        };
 
-       dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
+       dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -458,14 +455,14 @@
                reg = <0x021c>;
        };
 
-       dpll_ddr_ck: dpll_ddr_ck@210 {
+       dpll_ddr_ck: clock@210 {
                #clock-cells = <0>;
                compatible = "ti,omap4-dpll-clock";
                clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
                reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
        };
 
-       dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
+       dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_ddr_ck>;
@@ -476,7 +473,7 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
+       dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -484,14 +481,14 @@
                reg = <0x02b4>;
        };
 
-       dpll_gmac_ck: dpll_gmac_ck@2a8 {
+       dpll_gmac_ck: clock@2a8 {
                #clock-cells = <0>;
                compatible = "ti,omap4-dpll-clock";
                clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
                reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
        };
 
-       dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
+       dpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_gmac_ck>;
@@ -502,7 +499,7 @@
                ti,invert-autoidle-bit;
        };
 
-       video2_dclk_div: video2_dclk_div {
+       video2_dclk_div: clock-video2-dclk-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&video2_m2_clkin_ck>;
@@ -510,7 +507,7 @@
                clock-div = <1>;
        };
 
-       video1_dclk_div: video1_dclk_div {
+       video1_dclk_div: clock-video1-dclk-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&video1_m2_clkin_ck>;
@@ -518,7 +515,7 @@
                clock-div = <1>;
        };
 
-       hdmi_dclk_div: hdmi_dclk_div {
+       hdmi_dclk_div: clock-hdmi-dclk-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&hdmi_clkin_ck>;
@@ -526,7 +523,7 @@
                clock-div = <1>;
        };
 
-       per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+       per_dpll_hs_clk_div: clock-per-dpll-hs-clk-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_abe_m3x2_ck>;
@@ -534,7 +531,7 @@
                clock-div = <2>;
        };
 
-       usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+       usb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_abe_m3x2_ck>;
@@ -542,7 +539,7 @@
                clock-div = <3>;
        };
 
-       eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
+       eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_core_h12x2_ck>;
@@ -550,7 +547,7 @@
                clock-div = <1>;
        };
 
-       dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
+       dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
@@ -558,14 +555,14 @@
                reg = <0x0290>;
        };
 
-       dpll_eve_ck: dpll_eve_ck@284 {
+       dpll_eve_ck: clock@284 {
                #clock-cells = <0>;
                compatible = "ti,omap4-dpll-clock";
                clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
                reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
        };
 
-       dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
+       dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_eve_ck>;
@@ -576,7 +573,7 @@
                ti,invert-autoidle-bit;
        };
 
-       eve_dclk_div: eve_dclk_div {
+       eve_dclk_div: clock-eve-dclk-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_eve_m2_ck>;
@@ -584,7 +581,7 @@
                clock-div = <1>;
        };
 
-       dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
+       dpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
@@ -595,7 +592,7 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
+       dpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
@@ -606,7 +603,7 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
+       dpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
@@ -617,7 +614,7 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
+       dpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
@@ -628,7 +625,7 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
+       dpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
@@ -639,13 +636,13 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+       dpll_ddr_x2_ck: clock-dpll-ddr-x2 {
                #clock-cells = <0>;
                compatible = "ti,omap4-dpll-x2-clock";
                clocks = <&dpll_ddr_ck>;
        };
 
-       dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
+       dpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_ddr_x2_ck>;
@@ -656,13 +653,13 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_dsp_x2_ck: dpll_dsp_x2_ck {
+       dpll_dsp_x2_ck: clock-dpll-dsp-x2 {
                #clock-cells = <0>;
                compatible = "ti,omap4-dpll-x2-clock";
                clocks = <&dpll_dsp_ck>;
        };
 
-       dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
+       dpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_dsp_x2_ck>;
@@ -675,13 +672,13 @@
                assigned-clock-rates = <400000000>;
        };
 
-       dpll_gmac_x2_ck: dpll_gmac_x2_ck {
+       dpll_gmac_x2_ck: clock-dpll-gmac-x2 {
                #clock-cells = <0>;
                compatible = "ti,omap4-dpll-x2-clock";
                clocks = <&dpll_gmac_ck>;
        };
 
-       dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
+       dpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_gmac_x2_ck>;
@@ -692,7 +689,7 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
+       dpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_gmac_x2_ck>;
@@ -703,7 +700,7 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
+       dpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_gmac_x2_ck>;
@@ -714,7 +711,7 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
+       dpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_gmac_x2_ck>;
@@ -725,7 +722,7 @@
                ti,invert-autoidle-bit;
        };
 
-       gmii_m_clk_div: gmii_m_clk_div {
+       gmii_m_clk_div: clock-gmii-m-clk-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_gmac_h11x2_ck>;
@@ -733,7 +730,7 @@
                clock-div = <2>;
        };
 
-       hdmi_clk2_div: hdmi_clk2_div {
+       hdmi_clk2_div: clock-hdmi-clk2-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&hdmi_clkin_ck>;
@@ -741,7 +738,7 @@
                clock-div = <1>;
        };
 
-       hdmi_div_clk: hdmi_div_clk {
+       hdmi_div_clk: clock-hdmi-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&hdmi_clkin_ck>;
@@ -749,7 +746,7 @@
                clock-div = <1>;
        };
 
-       l3_iclk_div: l3_iclk_div@100 {
+       l3_iclk_div: clock-l3-iclk-div-4@100 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                ti,max-div = <2>;
@@ -759,7 +756,7 @@
                ti,index-power-of-two;
        };
 
-       l4_root_clk_div: l4_root_clk_div {
+       l4_root_clk_div: clock-l4-root-clk-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&l3_iclk_div>;
@@ -767,7 +764,7 @@
                clock-div = <2>;
        };
 
-       video1_clk2_div: video1_clk2_div {
+       video1_clk2_div: clock-video1-clk2-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&video1_clkin_ck>;
@@ -775,7 +772,7 @@
                clock-div = <1>;
        };
 
-       video1_div_clk: video1_div_clk {
+       video1_div_clk: clock-video1-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&video1_clkin_ck>;
@@ -783,7 +780,7 @@
                clock-div = <1>;
        };
 
-       video2_clk2_div: video2_clk2_div {
+       video2_clk2_div: clock-video2-clk2-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&video2_clkin_ck>;
@@ -791,7 +788,7 @@
                clock-div = <1>;
        };
 
-       video2_div_clk: video2_div_clk {
+       video2_div_clk: clock-video2-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&video2_clkin_ck>;
@@ -873,14 +870,14 @@
                reg = <0x0580>;
        };
 
-       dummy_ck: dummy_ck {
+       dummy_ck: clock-dummy {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <0>;
        };
 };
 &prm_clocks {
-       sys_clkin1: sys_clkin1@110 {
+       sys_clkin1: clock-sys-clkin1@110 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
@@ -888,28 +885,28 @@
                ti,index-starts-at-one;
        };
 
-       abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
+       abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&sys_clkin1>, <&sys_clkin2>;
                reg = <0x0118>;
        };
 
-       abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
+       abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
                reg = <0x0114>;
        };
 
-       abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
+       abe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
                reg = <0x010c>;
        };
 
-       abe_24m_fclk: abe_24m_fclk@11c {
+       abe_24m_fclk: clock-abe-24m@11c {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_abe_m2x2_ck>;
@@ -917,7 +914,7 @@
                ti,dividers = <8>, <16>;
        };
 
-       aess_fclk: aess_fclk@178 {
+       aess_fclk: clock-aess@178 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&abe_clk>;
@@ -925,7 +922,7 @@
                ti,max-div = <2>;
        };
 
-       abe_giclk_div: abe_giclk_div@174 {
+       abe_giclk_div: clock-abe-giclk-div@174 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&aess_fclk>;
@@ -933,7 +930,7 @@
                ti,max-div = <2>;
        };
 
-       abe_lp_clk_div: abe_lp_clk_div@1d8 {
+       abe_lp_clk_div: clock-abe-lp-clk-div@1d8 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_abe_m2x2_ck>;
@@ -941,7 +938,7 @@
                ti,dividers = <16>, <32>;
        };
 
-       abe_sys_clk_div: abe_sys_clk_div@120 {
+       abe_sys_clk_div: clock-abe-sys-clk-div@120 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&sys_clkin1>;
@@ -949,14 +946,14 @@
                ti,max-div = <2>;
        };
 
-       adc_gfclk_mux: adc_gfclk_mux@1dc {
+       adc_gfclk_mux: clock-adc-gfclk-mux@1dc {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
                reg = <0x01dc>;
        };
 
-       sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
+       sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&sys_clkin1>;
@@ -965,7 +962,7 @@
                ti,index-power-of-two;
        };
 
-       sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
+       sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&sys_clkin2>;
@@ -974,7 +971,7 @@
                ti,index-power-of-two;
        };
 
-       per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
+       per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_abe_m2_ck>;
@@ -983,7 +980,7 @@
                ti,index-power-of-two;
        };
 
-       dsp_gclk_div: dsp_gclk_div@18c {
+       dsp_gclk_div: clock-dsp-gclk-div@18c {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_dsp_m2_ck>;
@@ -992,7 +989,7 @@
                ti,index-power-of-two;
        };
 
-       gpu_dclk: gpu_dclk@1a0 {
+       gpu_dclk: clock-gpu-dclk@1a0 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_gpu_m2_ck>;
@@ -1001,7 +998,7 @@
                ti,index-power-of-two;
        };
 
-       emif_phy_dclk_div: emif_phy_dclk_div@190 {
+       emif_phy_dclk_div: clock-emif-phy-dclk-div@190 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_ddr_m2_ck>;
@@ -1010,7 +1007,7 @@
                ti,index-power-of-two;
        };
 
-       gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
+       gmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_gmac_m2_ck>;
@@ -1019,7 +1016,7 @@
                ti,index-power-of-two;
        };
 
-       gmac_main_clk: gmac_main_clk {
+       gmac_main_clk: clock-gmac-main {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&gmac_250m_dclk_div>;
@@ -1027,7 +1024,7 @@
                clock-div = <2>;
        };
 
-       l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
+       l3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_usb_m2_ck>;
@@ -1036,7 +1033,7 @@
                ti,index-power-of-two;
        };
 
-       usb_otg_dclk_div: usb_otg_dclk_div@184 {
+       usb_otg_dclk_div: clock-usb-otg-dclk-div@184 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&usb_otg_clkin_ck>;
@@ -1045,7 +1042,7 @@
                ti,index-power-of-two;
        };
 
-       sata_dclk_div: sata_dclk_div@1c0 {
+       sata_dclk_div: clock-sata-dclk-div@1c0 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&sys_clkin1>;
@@ -1054,7 +1051,7 @@
                ti,index-power-of-two;
        };
 
-       pcie2_dclk_div: pcie2_dclk_div@1b8 {
+       pcie2_dclk_div: clock-pcie2-dclk-div@1b8 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_pcie_ref_m2_ck>;
@@ -1063,7 +1060,7 @@
                ti,index-power-of-two;
        };
 
-       pcie_dclk_div: pcie_dclk_div@1b4 {
+       pcie_dclk_div: clock-pcie-dclk-div@1b4 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&apll_pcie_m2_ck>;
@@ -1072,7 +1069,7 @@
                ti,index-power-of-two;
        };
 
-       emu_dclk_div: emu_dclk_div@194 {
+       emu_dclk_div: clock-emu-dclk-div@194 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&sys_clkin1>;
@@ -1081,7 +1078,7 @@
                ti,index-power-of-two;
        };
 
-       secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
+       secure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&secure_32k_clk_src_ck>;
@@ -1090,28 +1087,28 @@
                ti,index-power-of-two;
        };
 
-       clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
+       clkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
                reg = <0x0158>;
        };
 
-       clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
+       clkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
                reg = <0x015c>;
        };
 
-       clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
+       clkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
                reg = <0x0160>;
        };
 
-       custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+       custefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&sys_clkin1>;
@@ -1119,21 +1116,21 @@
                clock-div = <2>;
        };
 
-       eve_clk: eve_clk@180 {
+       eve_clk: clock-eve@180 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
                reg = <0x0180>;
        };
 
-       hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
+       hdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&sys_clkin1>, <&sys_clkin2>;
                reg = <0x0164>;
        };
 
-       mlb_clk: mlb_clk@134 {
+       mlb_clk: clock-mlb@134 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&mlb_clkin_ck>;
@@ -1142,7 +1139,7 @@
                ti,index-power-of-two;
        };
 
-       mlbp_clk: mlbp_clk@130 {
+       mlbp_clk: clock-mlbp@130 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&mlbp_clkin_ck>;
@@ -1151,7 +1148,7 @@
                ti,index-power-of-two;
        };
 
-       per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
+       per_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_abe_m2_ck>;
@@ -1160,7 +1157,7 @@
                ti,index-power-of-two;
        };
 
-       timer_sys_clk_div: timer_sys_clk_div@144 {
+       timer_sys_clk_div: clock-timer-sys-clk-div@144 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&sys_clkin1>;
@@ -1168,21 +1165,21 @@
                ti,max-div = <2>;
        };
 
-       video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
+       video1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&sys_clkin1>, <&sys_clkin2>;
                reg = <0x0168>;
        };
 
-       video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
+       video2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&sys_clkin1>, <&sys_clkin2>;
                reg = <0x016c>;
        };
 
-       wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
+       wkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
@@ -1222,14 +1219,14 @@
        };
 };
 &cm_core_clocks {
-       dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
+       dpll_pcie_ref_ck: clock@200 {
                #clock-cells = <0>;
                compatible = "ti,omap4-dpll-clock";
                clocks = <&sys_clkin1>, <&sys_clkin1>;
                reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
        };
 
-       dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
+       dpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_pcie_ref_ck>;
@@ -1240,7 +1237,7 @@
                ti,invert-autoidle-bit;
        };
 
-       apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
+       apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 {
                compatible = "ti,mux-clock";
                clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
                #clock-cells = <0>;
@@ -1248,7 +1245,7 @@
                ti,bit-shift = <7>;
        };
 
-       apll_pcie_ck: apll_pcie_ck@21c {
+       apll_pcie_ck: clock@21c {
                #clock-cells = <0>;
                compatible = "ti,dra7-apll-clock";
                clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
@@ -1271,7 +1268,7 @@
                ti,bit-shift = <8>;
        };
 
-       optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
+       optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c {
                compatible = "ti,divider-clock";
                clocks = <&apll_pcie_ck>;
                #clock-cells = <0>;
@@ -1313,7 +1310,7 @@
                ti,bit-shift = <10>;
        };
 
-       apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
+       apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&apll_pcie_ck>;
@@ -1321,7 +1318,7 @@
                clock-div = <1>;
        };
 
-       apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
+       apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&apll_pcie_ck>;
@@ -1329,7 +1326,7 @@
                clock-div = <1>;
        };
 
-       apll_pcie_m2_ck: apll_pcie_m2_ck {
+       apll_pcie_m2_ck: clock-apll-pcie-m2 {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&apll_pcie_ck>;
@@ -1337,7 +1334,7 @@
                clock-div = <1>;
        };
 
-       dpll_per_byp_mux: dpll_per_byp_mux@14c {
+       dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
@@ -1345,14 +1342,14 @@
                reg = <0x014c>;
        };
 
-       dpll_per_ck: dpll_per_ck@140 {
+       dpll_per_ck: clock@140 {
                #clock-cells = <0>;
                compatible = "ti,omap4-dpll-clock";
                clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
                reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
        };
 
-       dpll_per_m2_ck: dpll_per_m2_ck@150 {
+       dpll_per_m2_ck: clock-dpll-per-m2-8@150 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_per_ck>;
@@ -1363,7 +1360,7 @@
                ti,invert-autoidle-bit;
        };
 
-       func_96m_aon_dclk_div: func_96m_aon_dclk_div {
+       func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_per_m2_ck>;
@@ -1371,7 +1368,7 @@
                clock-div = <1>;
        };
 
-       dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
+       dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
@@ -1379,14 +1376,14 @@
                reg = <0x018c>;
        };
 
-       dpll_usb_ck: dpll_usb_ck@180 {
+       dpll_usb_ck: clock@180 {
                #clock-cells = <0>;
                compatible = "ti,omap4-dpll-j-type-clock";
                clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
                reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
        };
 
-       dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
+       dpll_usb_m2_ck: clock-dpll-usb-m2-8@190 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_usb_ck>;
@@ -1397,7 +1394,7 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
+       dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_pcie_ref_ck>;
@@ -1408,13 +1405,13 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_per_x2_ck: dpll_per_x2_ck {
+       dpll_per_x2_ck: clock-dpll-per-x2 {
                #clock-cells = <0>;
                compatible = "ti,omap4-dpll-x2-clock";
                clocks = <&dpll_per_ck>;
        };
 
-       dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
+       dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_per_x2_ck>;
@@ -1425,7 +1422,7 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
+       dpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_per_x2_ck>;
@@ -1436,7 +1433,7 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
+       dpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_per_x2_ck>;
@@ -1447,7 +1444,7 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
+       dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_per_x2_ck>;
@@ -1458,7 +1455,7 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
+       dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_per_x2_ck>;
@@ -1469,7 +1466,7 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+       dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_usb_ck>;
@@ -1477,7 +1474,7 @@
                clock-div = <1>;
        };
 
-       func_128m_clk: func_128m_clk {
+       func_128m_clk: clock-func-128m {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_per_h11x2_ck>;
@@ -1485,7 +1482,7 @@
                clock-div = <2>;
        };
 
-       func_12m_fclk: func_12m_fclk {
+       func_12m_fclk: clock-func-12m-fclk {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_per_m2x2_ck>;
@@ -1493,7 +1490,7 @@
                clock-div = <16>;
        };
 
-       func_24m_clk: func_24m_clk {
+       func_24m_clk: clock-func-24m {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_per_m2_ck>;
@@ -1501,7 +1498,7 @@
                clock-div = <4>;
        };
 
-       func_48m_fclk: func_48m_fclk {
+       func_48m_fclk: clock-func-48m-fclk {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_per_m2x2_ck>;
@@ -1509,7 +1506,7 @@
                clock-div = <4>;
        };
 
-       func_96m_fclk: func_96m_fclk {
+       func_96m_fclk: clock-func-96m-fclk {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clocks = <&dpll_per_m2x2_ck>;
@@ -1517,7 +1514,7 @@
                clock-div = <2>;
        };
 
-       l3init_60m_fclk: l3init_60m_fclk@104 {
+       l3init_60m_fclk: clock-l3init-60m@104 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll_usb_m2_ck>;
@@ -1525,7 +1522,7 @@
                ti,dividers = <1>, <8>;
        };
 
-       clkout2_clk: clkout2_clk@6b0 {
+       clkout2_clk: clock-clkout2-8@6b0 {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
                clocks = <&clkoutmux2_clk_mux>;
@@ -1533,7 +1530,7 @@
                reg = <0x06b0>;
        };
 
-       l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
+       l3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
                clocks = <&dpll_usb_clkdcoldo>;
@@ -1702,7 +1699,7 @@
                reg = <0x1340>;
        };
 
-       usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
+       usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
                clocks = <&sys_32k_ck>;
@@ -1710,7 +1707,7 @@
                reg = <0x0640>;
        };
 
-       usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
+       usb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
                clocks = <&sys_32k_ck>;
@@ -1718,7 +1715,7 @@
                reg = <0x0688>;
        };
 
-       usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
+       usb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
                clocks = <&sys_32k_ck>;
@@ -1758,7 +1755,7 @@
                reg = <0x13d0>;
        };
 
-       gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
+       gpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
@@ -1768,7 +1765,7 @@
                assigned-clock-parents = <&dpll_gpu_m2_ck>;
        };
 
-       gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
+       gpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
@@ -1778,7 +1775,7 @@
                assigned-clock-parents = <&dpll_gpu_m2_ck>;
        };
 
-       l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
+       l3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&wkupaon_iclk_mux>;
@@ -2141,7 +2138,7 @@
                reg = <0x18e8>;
        };
 
-       vip1_gclk_mux: vip1_gclk_mux@1020 {
+       vip1_gclk_mux: clock-vip1-gclk-mux-24@1020 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
@@ -2149,7 +2146,7 @@
                reg = <0x1020>;
        };
 
-       vip2_gclk_mux: vip2_gclk_mux@1028 {
+       vip2_gclk_mux: clock-vip2-gclk-mux-24@1028 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
                clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;

diff --git a/arch/arm/dts/fsl-ls1088a-qds.dtsi b/arch/arm/dts/fsl-ls1088a-qds.dtsi
index 85dc745..4d21d4f 100644 (file)
--- a/arch/arm/dts/fsl-ls1088a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1088a-qds.dtsi
@@ -132,6 +132,14 @@
        };
 };
 
+&duart0 {
+       status = "okay";
+};
+
+&duart1 {
+       status = "okay";
+};
+
 &dspi {
        bus-num = <0>;
        status = "okay";

diff --git a/arch/arm/dts/fsl-ls1088a-rdb.dts b/arch/arm/dts/fsl-ls1088a-rdb.dts
index 01f8fcb..c63d415 100644 (file)
--- a/arch/arm/dts/fsl-ls1088a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1088a-rdb.dts
@@ -142,6 +142,14 @@
        };
 };
 
+&duart0 {
+       status = "okay";
+};
+
+&duart1 {
+       status = "okay";
+};
+
 &qspi {
        status = "okay";
 

diff --git a/arch/arm/dts/fsl-ls1088a-ten64.dts b/arch/arm/dts/fsl-ls1088a-ten64.dts
index 43b669c..55a7d41 100644 (file)
--- a/arch/arm/dts/fsl-ls1088a-ten64.dts
+++ b/arch/arm/dts/fsl-ls1088a-ten64.dts
@@ -20,6 +20,8 @@
        compatible = "traverse,ten64", "fsl,ls1088a";
 
        aliases {
+               serial0 = &duart0;
+               serial1 = &duart1;
                spi0 = &qspi;
        };
 
@@ -164,11 +166,11 @@
        status = "okay";
 };
 
-&serial0 {
+&duart0 {
        status = "okay";
 };
 
-&serial1 {
+&duart1 {
        status = "okay";
 };
 

diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index 9b7c54b..4782b83 100644 (file)
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -2,9 +2,10 @@
 /*
  * NXP ls1088a SOC common device tree source
  *
- * Copyright 2017, 2020-2021 NXP
+ * Copyright 2017, 2020-2021, 2023 NXP
  */
 
+#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 / {
        compatible = "fsl,ls1088a";
@@ -35,6 +36,48 @@
                             <1 10 0x8>; /* Hypervisor PPI, active-low */
        };
 
+       sysclk: sysclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <100000000>;
+               clock-output-names = "sysclk";
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+               dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
+
+               clockgen: clocking@1300000 {
+                       compatible = "fsl,ls1088a-clockgen";
+                       reg = <0 0x1300000 0 0xa0000>;
+                       #clock-cells = <2>;
+                       clocks = <&sysclk>;
+               };
+
+               duart0: serial@21c0500 {
+                       compatible = "fsl,ns16550", "ns16550a";
+                       reg = <0x0 0x21c0500 0x0 0x100>;
+                       clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+                                           QORIQ_CLK_PLL_DIV(4)>;
+                       interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       bootph-all;
+               };
+
+               duart1: serial@21c0600 {
+                       compatible = "fsl,ns16550", "ns16550a";
+                       reg = <0x0 0x21c0600 0x0 0x100>;
+                       clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+                                           QORIQ_CLK_PLL_DIV(4)>;
+                       interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       bootph-all;
+               };
+       };
+
        i2c0: i2c@2000000 {
                compatible = "fsl,vf610-i2c";
                #address-cells = <1>;
@@ -67,22 +110,6 @@
                interrupts = <0 35 4>;
        };
 
-       serial0: serial@21c0500 {
-               device_type = "serial";
-               compatible = "fsl,ns16550", "ns16550a";
-               reg = <0x0 0x21c0500 0x0 0x100>;
-               clock-frequency = <0>;  /* Updated by bootloader */
-               interrupts = <0 32 0x1>; /* edge triggered */
-       };
-
-       serial1: serial@21c0600 {
-               device_type = "serial";
-               compatible = "fsl,ns16550", "ns16550a";
-               reg = <0x0 0x21c0600 0x0 0x100>;
-               clock-frequency = <0>;  /* Updated by bootloader */
-               interrupts = <0 32 0x1>; /* edge triggered */
-       };
-
        dspi: dspi@2100000 {
                compatible = "fsl,vf610-dspi";
                #address-cells = <1>;

diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi b/arch/arm/dts/fsl-lx2160a-qds.dtsi
index 6635c52..e96605b 100644 (file)
--- a/arch/arm/dts/fsl-lx2160a-qds.dtsi
+++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP LX2160AQDS common device tree source
  *
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2020, 2023 NXP
  *
  */
 
@@ -11,6 +11,7 @@
 / {
        aliases {
                spi0 = &fspi;
+               serial0 = &uart0;
        };
 };
 
@@ -286,3 +287,11 @@
 &sata3 {
        status = "okay";
 };
+
+&uart0 {
+       status = "okay";
+};
+
+&uart1 {
+       status = "okay";
+};

diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts
index 3994097..aaa5959 100644 (file)
--- a/arch/arm/dts/fsl-lx2160a-rdb.dts
+++ b/arch/arm/dts/fsl-lx2160a-rdb.dts
@@ -5,7 +5,7 @@
  * Author:     Priyanka Jain <priyanka.jain@nxp.com>
  *             Sriram Dash <sriram.dash@nxp.com>
  *
- * Copyright 2018 NXP
+ * Copyright 2018, 2023 NXP
  *
  */
 
@@ -18,6 +18,7 @@
        compatible = "fsl,lx2160ardb", "fsl,lx2160a";
        aliases {
                spi0 = &fspi;
+               serial0 = &uart0;
        };
 };
 
@@ -137,3 +138,11 @@
 &sata3 {
        status = "okay";
 };
+
+&uart0 {
+       status = "okay";
+};
+
+&uart1 {
+       status = "okay";
+};

diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 57c7d3e..680c69c 100644 (file)
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP lx2160a SOC common device tree source
  *
- * Copyright 2018-2021 NXP
+ * Copyright 2018-2021, 2023 NXP
  *
  */
 
@@ -27,6 +27,50 @@
                clock-output-names = "sysclk";
        };
 
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+               dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
+
+               uart0: serial@21c0000 {
+                       compatible = "arm,sbsa-uart","arm,pl011";
+                       reg = <0x0 0x21c0000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                       current-speed = <115200>;
+                       status = "disabled";
+                       bootph-all;
+               };
+
+               uart1: serial@21d0000 {
+                       compatible = "arm,sbsa-uart","arm,pl011";
+                       reg = <0x0 0x21d0000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                       current-speed = <115200>;
+                       status = "disabled";
+                       bootph-all;
+               };
+
+               uart2: serial@21e0000 {
+                       compatible = "arm,sbsa-uart","arm,pl011";
+                       reg = <0x0 0x21e0000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                       current-speed = <115200>;
+                       status = "disabled";
+                       bootph-all;
+               };
+
+               uart3: serial@21f0000 {
+                       compatible = "arm,sbsa-uart","arm,pl011";
+                       reg = <0x0 0x21f0000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                       current-speed = <115200>;
+                       status = "disabled";
+                       bootph-all;
+               };
+       };
+
        crypto: crypto@8000000 {
                compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
                fsl,sec-era = <10>;
@@ -177,34 +221,6 @@
                status = "disabled";
        };
 
-       uart0: serial@21c0000 {
-               compatible = "arm,pl011";
-               reg = <0x0 0x21c0000 0x0 0x1000>;
-               clocks = <&clockgen 4 0>;
-               status = "disabled";
-       };
-
-       uart1: serial@21d0000 {
-               compatible = "arm,pl011";
-               reg = <0x0 0x21d0000 0x0 0x1000>;
-               clocks = <&clockgen 4 0>;
-               status = "disabled";
-       };
-
-       uart2: serial@21e0000 {
-               compatible = "arm,pl011";
-               reg = <0x0 0x21e0000 0x0 0x1000>;
-               clocks = <&clockgen 4 0>;
-               status = "disabled";
-       };
-
-       uart3: serial@21f0000 {
-               compatible = "arm,pl011";
-               reg = <0x0 0x21f0000 0x0 0x1000>;
-               clocks = <&clockgen 4 0>;
-               status = "disabled";
-       };
-
        dspi0: dspi@2100000 {
                compatible = "fsl,vf610-dspi";
                #address-cells = <1>;

diff --git a/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi b/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi
index 190567a..740a24d 100644 (file)
--- a/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi
@@ -8,6 +8,12 @@
        aliases {
                eeprom0 = &eeprom0;
        };
+
+       wdt-reboot {
+               compatible = "wdt-reboot";
+               wdt = <&wdog1>;
+               bootph-pre-ram;
+       };
 };
 
 &fec {
@@ -25,3 +31,7 @@
        gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
        enable-active-high;
 };
+
+&wdog1 {
+       bootph-pre-ram;
+};

diff --git a/arch/arm/dts/imx6sx-udoo-neo-basic-u-boot.dtsi b/arch/arm/dts/imx6sx-udoo-neo-basic-u-boot.dtsi
new file mode 100644 (file)
index 0000000..b5e1f2b
--- /dev/null
+++ b/arch/arm/dts/imx6sx-udoo-neo-basic-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+&soc {
+       bootph-all;
+};
+
+&aips1 {
+       bootph-all;
+};
+
+&pinctrl_uart1 {
+       bootph-all;
+};
+
+&uart1 {
+       bootph-all;
+};

diff --git a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
new file mode 100644 (file)
index 0000000..5ca631e
--- /dev/null
+++ b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Logic PD, Inc DBA Beacon EmbeddedWorks
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+       wdt-reboot {
+               compatible = "wdt-reboot";
+               wdt = <&wdog1>;
+               bootph-pre-ram;
+       };
+
+       firmware {
+               optee {
+                       compatible = "linaro,optee-tz";
+                       method = "smc";
+               };
+       };
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
+       bootph-pre-ram;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
+       bootph-pre-ram;
+};
+
+&crypto {
+       bootph-pre-ram;
+};
+
+&eqos {
+       /delete-property/ assigned-clocks;
+       /delete-property/ assigned-clock-parents;
+       /delete-property/ assigned-clock-rates;
+};
+
+&ethphy0 {
+       reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+       reset-assert-us = <15000>;
+       reset-deassert-us = <100000>;
+};
+
+&fec {
+       phy-reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <15>;
+       phy-reset-post-delay = <100>;
+};
+
+&flexspi {
+       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
+};
+
+&gpio1 {
+       bootph-pre-ram;
+};
+
+&gpio2 {
+       bootph-pre-ram;
+};
+
+&gpio3 {
+       bootph-pre-ram;
+};
+
+&gpio4 {
+       bootph-pre-ram;
+};
+
+&gpio5 {
+       bootph-pre-ram;
+};
+
+&i2c1 {
+       bootph-pre-ram;
+};
+
+&i2c2 {
+       bootph-pre-ram;
+};
+
+&i2c3 {
+       bootph-pre-ram;
+};
+
+&pca6416 {
+       compatible = "ti,tca6416";
+       label = "exp4";
+};
+
+&pca6416_1 {
+       compatible = "ti,tca6416";
+       label = "exp4";
+};
+
+&pca6416_3 {
+       compatible = "ti,tca6416";
+       label = "exp2";
+};
+
+&pinctrl_i2c1 {
+       bootph-pre-ram;
+};
+
+&pinctrl_pmic {
+       bootph-pre-ram;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+       bootph-pre-ram;
+};
+
+&pinctrl_uart2 {
+       bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+       bootph-pre-ram;
+};
+
+&pinctrl_usdhc2 {
+       bootph-pre-ram;
+};
+
+&pinctrl_usdhc3 {
+       bootph-pre-ram;
+};
+
+&pinctrl_wdog {
+       bootph-pre-ram;
+};
+
+&reg_usdhc2_vmmc {
+       bootph-pre-ram;
+       u-boot,off-on-delay-us = <20000>;
+};
+
+&sec_jr0 {
+       bootph-pre-ram;
+};
+
+&sec_jr1 {
+       bootph-pre-ram;
+};
+
+&sec_jr2 {
+       bootph-pre-ram;
+};
+
+&tpm {
+       compatible = "tcg,tpm_tis-spi";
+};
+
+&uart2 {
+       bootph-pre-ram;
+};
+
+&usdhc1 {
+       bootph-pre-ram;
+       assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
+       assigned-clock-rates = <400000000>;
+       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
+};
+
+&usdhc2 {
+       bootph-pre-ram;
+       sd-uhs-sdr104;
+       sd-uhs-ddr50;
+       assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
+       assigned-clock-rates = <400000000>;
+       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
+};
+
+&usdhc3 {
+       bootph-pre-ram;
+       mmc-hs400-1_8v;
+       mmc-hs400-enhanced-strobe;
+       assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+       assigned-clock-rates = <400000000>;
+       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
+};
+
+&usb3_0 {
+       dma-ranges = <0x40000000 0x40000000 0xc0000000>;
+       /delete-property/ power-domains;
+};
+
+&usb3_1 {
+       dma-ranges = <0x40000000 0x40000000 0xc0000000>;
+       /delete-property/ power-domains;
+};
+
+&usb_dwc3_0 {
+       compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
+       assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
+       assigned-clock-rates = <400000000>;
+};
+
+&usb_dwc3_1 {
+       compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
+       assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
+       assigned-clock-rates = <400000000>;
+};
+
+&usdhc1 {
+       status = "disabled";
+};
+
+&wdog1 {
+       bootph-pre-ram;
+};

diff --git a/arch/arm/dts/imx8mp-beacon-kit.dts b/arch/arm/dts/imx8mp-beacon-kit.dts
new file mode 100644 (file)
index 0000000..cdae45a
--- /dev/null
+++ b/arch/arm/dts/imx8mp-beacon-kit.dts
@@ -0,0 +1,550 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include "imx8mp.dtsi"
+#include "imx8mp-beacon-som.dtsi"
+
+/ {
+       model = "Beacon EmbeddedWorks i.MX8MPlus Development kit";
+       compatible = "beacon,imx8mp-beacon-kit", "fsl,imx8mp";
+
+       aliases {
+               ethernet0 = &eqos;
+               ethernet1 = &fec;
+       };
+
+       chosen {
+               stdout-path = &uart2;
+       };
+
+       connector {
+               compatible = "usb-c-connector";
+               label = "USB-C";
+               data-role = "dual";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+
+                               hs_ep: endpoint {
+                                       remote-endpoint = <&usb3_hs_ep>;
+                               };
+                       };
+                       port@1 {
+                               reg = <1>;
+
+                               ss_ep: endpoint {
+                                       remote-endpoint = <&hd3ss3220_in_ep>;
+                               };
+                       };
+               };
+       };
+
+       gpio-keys {
+               compatible = "gpio-keys";
+               autorepeat;
+
+               button-0 {
+                       label = "btn0";
+                       linux,code = <BTN_0>;
+                       gpios = <&pca6416_1 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+                       wakeup-source;
+               };
+
+               button-1 {
+                       label = "btn1";
+                       linux,code = <BTN_1>;
+                       gpios = <&pca6416_1 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+                       wakeup-source;
+               };
+
+               button-2 {
+                       label = "btn2";
+                       linux,code = <BTN_2>;
+                       gpios = <&pca6416_1 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+                       wakeup-source;
+               };
+
+               button-3 {
+                       label = "btn3";
+                       linux,code = <BTN_3>;
+                       gpios = <&pca6416_1 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+                       wakeup-source;
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_led3>;
+
+               led-0 {
+                       label = "gen_led0";
+                       gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+               };
+
+               led-1 {
+                       label = "gen_led1";
+                       gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+               };
+
+               led-2 {
+                       label = "gen_led2";
+                       gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+               };
+
+               led-3 {
+                       label = "heartbeat";
+                       gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "heartbeat";
+               };
+       };
+
+       pcie0_refclk: clock-pcie {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <100000000>;
+       };
+
+       reg_usdhc2_vmmc: regulator-usdhc2 {
+               compatible = "regulator-fixed";
+               regulator-name = "VSD_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+               startup-delay-us = <100>;
+               off-on-delay-us = <20000>;
+       };
+
+       reg_usb1_host_vbus: regulator-usb1-vbus {
+               compatible = "regulator-fixed";
+               regulator-name = "usb1_host_vbus";
+               regulator-max-microvolt = <5000000>;
+               regulator-min-microvolt = <5000000>;
+               gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+};
+
+&ecspi2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi2>;
+       cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+       status = "okay";
+
+       tpm: tpm@0 {
+               compatible = "infineon,slb9670";
+               reg = <0>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_tpm>;
+               reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
+               spi-max-frequency = <18500000>;
+       };
+};
+
+&fec {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec>;
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethphy1>;
+       fsl,magic-packet;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy1: ethernet-phy@3 {
+                       compatible = "ethernet-phy-id0022.1640",
+                                    "ethernet-phy-ieee802.3-c22";
+                       reg = <3>;
+                       reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
+                       reset-assert-us = <10000>;
+                       reset-deassert-us = <150000>;
+                       interrupt-parent = <&gpio4>;
+                       interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+               };
+       };
+};
+
+&flexcan1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan1>;
+       status = "okay";
+};
+
+&gpio2 {
+       usb-mux-hog {
+               gpio-hog;
+               gpios = <20 0>;
+               output-low;
+               line-name = "USB-C Mux En";
+       };
+};
+
+&i2c2 {
+       clock-frequency = <384000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c2>;
+       status = "okay";
+
+       pca6416_3: gpio@20 {
+               compatible = "nxp,pcal6416";
+               reg = <0x20>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-parent = <&gpio4>;
+               interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+       };
+};
+
+&i2c3 {
+       /* Connected to USB Hub */
+       usb-typec@52 {
+               compatible = "nxp,ptn5110";
+               reg = <0x52>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_typec>;
+               interrupt-parent = <&gpio4>;
+               interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+
+               connector {
+                       compatible = "usb-c-connector";
+                       label = "USB-C";
+                       power-role = "source";
+                       data-role = "host";
+                       source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+               };
+       };
+};
+
+&i2c4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c4>;
+       clock-frequency = <384000>;
+       status = "okay";
+
+       pca6416: gpio@20 {
+               compatible = "nxp,pcal6416";
+               reg = <0x20>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_pcal6414>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-parent = <&gpio4>;
+               interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+       };
+
+       pca6416_1: gpio@21 {
+               compatible = "nxp,pcal6416";
+               reg = <0x21>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-parent = <&gpio4>;
+               interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+
+               usb-hub-hog {
+                       gpio-hog;
+                       gpios = <7 0>;
+                       output-low;
+                       line-name = "USB Hub Enable";
+               };
+       };
+
+       usb-typec@47 {
+               compatible = "ti,hd3ss3220";
+               reg = <0x47>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_hd3ss3220>;
+               interrupt-parent = <&gpio4>;
+               interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+
+                               hd3ss3220_in_ep: endpoint {
+                                       remote-endpoint = <&ss_ep>;
+                               };
+                       };
+
+                       port@1 {
+                               reg = <1>;
+
+                               hd3ss3220_out_ep: endpoint {
+                                       remote-endpoint = <&usb3_role_switch>;
+                               };
+                       };
+               };
+       };
+};
+
+&pcie {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pcie>;
+       reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
+       status = "okay";
+};
+
+&pcie_phy {
+       fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+       clocks = <&pcie0_refclk>;
+       clock-names = "ref";
+       status = "okay";
+};
+
+&snvs_pwrkey {
+       status = "okay";
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2>;
+       status = "okay";
+};
+
+&uart3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart3>;
+       assigned-clocks = <&clk IMX8MP_CLK_UART3>;
+       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+       uart-has-rtscts;
+       status = "okay";
+};
+
+&usb3_0 {
+       status = "okay";
+};
+
+&usb_dwc3_0 {
+       dr_mode = "otg";
+       hnp-disable;
+       srp-disable;
+       adp-disable;
+       usb-role-switch;
+       status = "okay";
+
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               port@0 {
+                       reg = <0>;
+                       usb3_hs_ep: endpoint {
+                               remote-endpoint = <&hs_ep>;
+                       };
+               };
+               port@1 {
+                       reg = <1>;
+                       usb3_role_switch: endpoint {
+                               remote-endpoint = <&hd3ss3220_out_ep>;
+                       };
+               };
+       };
+};
+
+&usb3_phy0 {
+       vbus-supply = <&reg_usb1_host_vbus>;
+       status = "okay";
+};
+
+&usb3_1 {
+       status = "okay";
+};
+
+&usb_dwc3_1 {
+       dr_mode = "host";
+       status = "okay";
+};
+
+&usb3_phy1 {
+       status = "okay";
+};
+
+&usdhc2 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+       cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+       vmmc-supply = <&reg_usdhc2_vmmc>;
+       bus-width = <4>;
+       status = "okay";
+};
+
+&iomuxc {
+       pinctrl_ecspi2: ecspi2grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK   0x82
+                       MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI   0x82
+                       MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO   0x82
+                       MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13     0x40000
+               >;
+       };
+
+       pinctrl_fec: fecgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC       0x2
+                       MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO      0x2
+                       MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
+                       MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
+                       MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
+                       MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
+                       MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC  0x90
+                       MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL      0x90
+                       MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
+                       MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
+                       MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
+                       MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
+                       MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL      0x16
+                       MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
+                       MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02      0x140
+                       MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18      0x10
+               >;
+       };
+
+       pinctrl_flexcan1: flexcan1grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SPDIF_RX__CAN1_RX  0x154
+                       MX8MP_IOMUXC_SPDIF_TX__CAN1_TX  0x154
+               >;
+       };
+
+       pinctrl_hd3ss3220: hd3ss3220grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19      0x140
+               >;
+       };
+
+       pinctrl_i2c2: i2c2grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
+                       MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
+               >;
+       };
+
+       pinctrl_i2c4: i2c4grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
+                       MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
+               >;
+       };
+
+       pinctrl_led3: led3grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28      0x41
+               >;
+       };
+
+       pinctrl_pcal6414: pcal6414-gpiogrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27      0x10
+               >;
+       };
+
+       pinctrl_pcie: pciegrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05     0x10 /* PCIe_nDIS */
+                       MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x10 /* PCIe_nRST */
+               >;
+       };
+
+       pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19    0x40
+               >;
+       };
+
+       pinctrl_tpm: tpmgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00      0x19 /* Reset */
+                       MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29       0x1d6 /* IRQ */
+               >;
+       };
+
+       pinctrl_typec: typec1grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01       0xc4
+               >;
+       };
+
+       pinctrl_uart2: uart2grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX    0x140
+                       MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX    0x140
+               >;
+       };
+
+       pinctrl_uart3: uart3grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX          0x140
+                       MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX          0x140
+                       MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS          0x140
+                       MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS         0x140
+               >;
+       };
+
+       pinctrl_usdhc2: usdhc2grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x190
+                       MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d0
+                       MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d0
+                       MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d0
+                       MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d0
+                       MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d0
+                       MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
+               >;
+       };
+
+       pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x194
+                       MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d4
+                       MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d4
+                       MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d4
+                       MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d4
+                       MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d4
+                       MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
+               >;
+       };
+
+       pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x196
+                       MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d6
+                       MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d6
+                       MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d6
+                       MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d6
+                       MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d6
+                       MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
+               >;
+       };
+
+       pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12       0x1c4
+               >;
+       };
+};

diff --git a/arch/arm/dts/imx8mp-beacon-som.dtsi b/arch/arm/dts/imx8mp-beacon-som.dtsi
new file mode 100644 (file)
index 0000000..e5da908
--- /dev/null
+++ b/arch/arm/dts/imx8mp-beacon-som.dtsi
@@ -0,0 +1,416 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023 LogicPD, Inc. dba Beacon EmbeddedWorks
+ */
+
+/ {
+       aliases {
+               rtc0 = &rtc;
+               rtc1 = &snvs_rtc;
+       };
+
+       memory@40000000 {
+               device_type = "memory";
+               reg = <0x0 0x40000000 0 0xc0000000>,
+                     <0x1 0x00000000 0 0xc0000000>;
+       };
+
+       reg_wl_bt: regulator-wifi-bt {
+               compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_reg_wl_bt>;
+               regulator-name = "wl-bt-pow-dwn";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
+               startup-delay-us = <70000>;
+               regulator-always-on;
+       };
+};
+
+&A53_0 {
+       cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+       cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+       cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+       cpu-supply = <&buck2>;
+};
+
+&eqos {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_eqos>;
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethphy0>;
+       snps,force_thresh_dma_mode;
+       status = "okay";
+
+       mdio {
+               compatible = "snps,dwmac-mdio";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy0: ethernet-phy@3 {
+                       compatible = "ethernet-phy-id0022.1640",
+                                    "ethernet-phy-ieee802.3-c22";
+                       reg = <3>;
+                       reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
+                       interrupt-parent = <&gpio1>;
+                       interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+               };
+       };
+};
+
+&flexspi {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexspi0>;
+       status = "okay";
+
+       flash0: flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <80000000>;
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <4>;
+       };
+};
+
+&i2c1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c1>;
+       clock-frequency = <384000>;
+       status = "okay";
+
+       pmic@25 {
+               compatible = "nxp,pca9450c";
+               reg = <0x25>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_pmic>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+               regulators {
+                       buck1: BUCK1 {
+                               regulator-name = "BUCK1";
+                               regulator-min-microvolt = <600000>;
+                               regulator-max-microvolt = <2187500>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                               regulator-ramp-delay = <3125>;
+                       };
+
+                       buck2: BUCK2 {
+                               regulator-name = "BUCK2";
+                               regulator-min-microvolt = <600000>;
+                               regulator-max-microvolt = <2187500>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                               regulator-ramp-delay = <3125>;
+                               nxp,dvs-run-voltage = <950000>;
+                               nxp,dvs-standby-voltage = <850000>;
+                       };
+
+                       buck4: BUCK4 {
+                               regulator-name = "BUCK4";
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       buck5: BUCK5 {
+                               regulator-name = "BUCK5";
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       buck6: BUCK6 {
+                               regulator-name = "BUCK6";
+                               regulator-min-microvolt = <600000>;
+                               regulator-max-microvolt = <3400000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       ldo1: LDO1 {
+                               regulator-name = "LDO1";
+                               regulator-min-microvolt = <1600000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       ldo3: LDO3 {
+                               regulator-name = "LDO3";
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       ldo4: LDO4 {
+                               regulator-name = "LDO4";
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       ldo5: LDO5 {
+                               regulator-name = "LDO5";
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+               };
+       };
+};
+
+&i2c3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c3>;
+       clock-frequency = <384000>;
+       status = "okay";
+
+       eeprom@50 {
+               compatible = "atmel,24c64";
+               reg = <0x50>;
+               pagesize = <32>;
+               read-only;      /* Manufacturing EEPROM programmed at factory */
+       };
+
+       rtc: rtc@51 {
+               compatible = "nxp,pcf85263";
+               reg = <0x51>;
+       };
+};
+
+&snvs_pwrkey {
+       status = "okay";
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+       assigned-clocks = <&clk IMX8MP_CLK_UART1>;
+       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+       uart-has-rtscts;
+       status = "okay";
+};
+
+&usdhc1 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc1>;
+       pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+       bus-width = <4>;
+       vmmc-supply = <&reg_wl_bt>;
+       cap-sd-highspeed;
+       sd-uhs-sdr50;
+       sd-uhs-sdr104;
+       keep-power-in-suspend;
+       wakeup-source;
+       non-removable;
+       cap-power-off-card;
+       #address-cells = <1>;
+       #size-cells = <0>;
+       status = "okay";
+
+       mwifiex: wifi@1 {
+               compatible = "marvell,sd8997";
+               reg = <1>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_wlan>;
+               interrupt-parent = <&gpio2>;
+               interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+       };
+};
+
+&usdhc3 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc3>;
+       pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+       bus-width = <8>;
+       non-removable;
+       status = "okay";
+};
+
+&wdog1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_wdog>;
+       fsl,ext-reset-output;
+       status = "okay";
+};
+
+&iomuxc {
+       pinctrl_eqos: eqosgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC             0x2
+                       MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO           0x2
+                       MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0       0x90
+                       MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1       0x90
+                       MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2       0x90
+                       MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3       0x90
+                       MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK       0x90
+                       MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
+                       MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0       0x16
+                       MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1       0x16
+                       MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2       0x16
+                       MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3       0x16
+                       MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
+                       MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK       0x16
+                       MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22               0x10
+                       MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10     0x10
+               >;
+       };
+
+       pinctrl_flexspi0: flexspi0grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK           0x1c2
+                       MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B        0x82
+                       MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00      0x82
+                       MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01      0x82
+                       MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02      0x82
+                       MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03      0x82
+               >;
+       };
+
+       pinctrl_i2c1: i2c1grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL         0x400001c2
+                       MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA         0x400001c2
+               >;
+       };
+
+       pinctrl_i2c3: i2c3grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL         0x400001c2
+                       MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA         0x400001c2
+               >;
+       };
+
+       pinctrl_pmic: pmicgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03     0x1c0
+               >;
+       };
+
+       pinctrl_reg_wl_bt: reg-wl-btgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06      0x40
+               >;
+       };
+
+       pinctrl_uart1: uart1grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX    0x140
+                       MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX    0x140
+                       MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS   0x140
+                       MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS   0x140
+               >;
+       };
+
+       pinctrl_usdhc1: usdhc1grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK        0x190
+                       MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD        0x1d0
+                       MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0    0x1d0
+                       MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1    0x1d0
+                       MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2    0x1d0
+                       MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3    0x1d0
+               >;
+       };
+
+       pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK        0x194
+                       MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD        0x1d4
+                       MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0    0x1d4
+                       MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1    0x1d4
+                       MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2    0x1d4
+                       MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3    0x1d4
+               >;
+       };
+
+       pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK        0x196
+                       MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD        0x1d6
+                       MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0    0x1d6
+                       MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1    0x1d6
+                       MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2    0x1d6
+                       MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3    0x1d6
+               >;
+       };
+
+       pinctrl_usdhc3: usdhc3grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x190
+                       MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d0
+                       MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d0
+                       MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d0
+                       MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d0
+                       MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d0
+                       MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d0
+                       MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d0
+                       MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d0
+                       MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d0
+                       MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x190
+               >;
+       };
+
+       pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x194
+                       MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d4
+                       MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d4
+                       MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d4
+                       MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d4
+                       MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d4
+                       MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d4
+                       MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d4
+                       MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d4
+                       MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d4
+                       MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x194
+               >;
+       };
+
+       pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x196
+                       MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d6
+                       MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d6
+                       MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d6
+                       MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d6
+                       MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d6
+                       MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d6
+                       MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d6
+                       MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d6
+                       MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d6
+                       MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x196
+               >;
+       };
+
+       pinctrl_wdog: wdoggrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B   0x166
+               >;
+       };
+
+       pinctrl_wlan: wlangrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09              0x140
+               >;
+       };
+};

diff --git a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi
new file mode 100644 (file)
index 0000000..dd0f34f
--- /dev/null
+++ b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+       aliases {
+               eeprom0 = &eeprom;
+               mmc0 = &usdhc3; /* eMMC */
+               mmc1 = &usdhc2; /* MicroSD */
+               spi0 = &ecspi1;
+       };
+
+       config {
+               dmo,ram-coding-gpios = <&gpio3 20 0>, <&gpio4 3 0>, <&gpio4 1 0>;
+       };
+
+       wdt-reboot {
+               compatible = "wdt-reboot";
+               wdt = <&wdog1>;
+               bootph-pre-ram;
+       };
+};
+
+&buck4 {
+       bootph-pre-ram;
+};
+
+&buck5 {
+       bootph-pre-ram;
+};
+
+&ecspi1 {
+       bootph-pre-ram;
+       flash@0 {
+               bootph-pre-ram;
+       };
+};
+
+&eqos {
+       /delete-property/ assigned-clocks;
+       /delete-property/ assigned-clock-parents;
+       /delete-property/ assigned-clock-rates;
+};
+
+&gpio1 {
+       bootph-pre-ram;
+};
+
+&gpio2 {
+       bootph-pre-ram;
+};
+
+&gpio3 {
+       bootph-pre-ram;
+};
+
+&gpio4 {
+       bootph-pre-ram;
+};
+
+&gpio5 {
+       bootph-pre-ram;
+};
+
+&i2c3 {
+       bootph-pre-ram;
+};
+
+&pinctrl_ecspi1 {
+       bootph-pre-ram;
+};
+
+&pinctrl_hog_sbc {
+       bootph-pre-ram;
+};
+
+&pinctrl_i2c3 {
+       bootph-pre-ram;
+};
+
+&pinctrl_i2c3_gpio {
+       bootph-pre-ram;
+};
+
+&pinctrl_pmic {
+       bootph-pre-ram;
+};
+
+&pinctrl_uart3 {
+       bootph-pre-ram;
+};
+
+&pinctrl_usdhc2 {
+       bootph-pre-ram;
+};
+
+&pinctrl_usdhc3 {
+       bootph-pre-ram;
+};
+
+&pmic {
+       bootph-pre-ram;
+
+       regulators {
+               bootph-pre-ram;
+       };
+};
+
+&uart3 {
+       bootph-pre-ram;
+};
+
+&usdhc2 {
+       bootph-pre-ram;
+       sd-uhs-sdr104;
+       sd-uhs-ddr50;
+};
+
+&usdhc3 {
+       bootph-pre-ram;
+       mmc-hs400-1_8v;
+       mmc-hs400-enhanced-strobe;
+};
+
+&wdog1 {
+       bootph-pre-ram;
+};

diff --git a/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts b/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts
new file mode 100644 (file)
index 0000000..8066f7f
--- /dev/null
+++ b/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts
@@ -0,0 +1,973 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2022 Marek Vasut <marex@denx.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/net/qca-ar803x.h>
+#include "imx8mp.dtsi"
+
+/ {
+       model = "Data Modul i.MX8M Plus eDM SBC";
+       compatible = "dmo,imx8mp-data-modul-edm-sbc", "fsl,imx8mp";
+
+       aliases {
+               rtc0 = &rtc;
+               rtc1 = &snvs_rtc;
+       };
+
+       chosen {
+               stdout-path = &uart3;
+       };
+
+       memory@40000000 {
+               device_type = "memory";
+               /* There are 1/2/4 GiB options, adjusted by bootloader. */
+               reg = <0x0 0x40000000 0 0x40000000>;
+       };
+
+       backlight: backlight {
+               compatible = "pwm-backlight";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_panel_backlight>;
+               brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
+               default-brightness-level = <7>;
+               enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
+               pwms = <&pwm1 0 5000000 0>;
+               /* Disabled by default, unless display board plugged in. */
+               status = "disabled";
+       };
+
+       clk_xtal25: clk-xtal25 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <25000000>;
+       };
+
+       panel: panel {
+               backlight = <&backlight>;
+               power-supply = <&reg_panel_vcc>;
+               /* Disabled by default, unless display board plugged in. */
+               status = "disabled";
+       };
+
+       reg_panel_vcc: regulator-panel-vcc {
+               compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_panel_vcc_reg>;
+               regulator-name = "PANEL_VCC";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               gpio = <&gpio3 6 0>;
+               enable-active-high;
+               /* Disabled by default, unless display board plugged in. */
+               status = "disabled";
+       };
+
+       reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+               compatible = "regulator-fixed";
+               enable-active-high;
+               gpio = <&gpio2 19 0>; /* SD2_RESET */
+               off-on-delay-us = <12000>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
+               regulator-max-microvolt = <3300000>;
+               regulator-min-microvolt = <3300000>;
+               regulator-name = "VDD_3V3_SD";
+               startup-delay-us = <100>;
+               vin-supply = <&buck4>;
+       };
+
+       watchdog {
+               /* TPS3813 */
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_watchdog_gpio>;
+               compatible = "linux,wdt-gpio";
+               always-running;
+               gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
+               hw_algo = "level";
+               /* Reset triggers in 2..3 seconds */
+               hw_margin_ms = <1500>;
+               /* Disabled by default */
+               status = "disabled";
+       };
+};
+
+&A53_0 {
+       cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+       cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+       cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+       cpu-supply = <&buck2>;
+};
+
+&ecspi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi1>;
+       cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+       status = "okay";
+
+       flash@0 {       /* W25Q128JVEI */
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <100000000>;        /* Up to 133 MHz */
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <1>;
+       };
+};
+
+&ecspi2 {      /* Feature connector SPI */
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi2>;
+       cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+       /* Disabled by default, unless feature board plugged in. */
+       status = "disabled";
+};
+
+&ecspi3 {      /* Display connector SPI */
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi3>;
+       cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
+       /* Disabled by default, unless display board plugged in. */
+       status = "disabled";
+};
+
+&eqos {        /* First ethernet */
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_eqos>;
+       phy-handle = <&phy_eqos>;
+       phy-mode = "rgmii-id";
+       status = "okay";
+
+       mdio {
+               compatible = "snps,dwmac-mdio";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               /* Atheros AR8031 PHY */
+               phy_eqos: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <0>;
+                       /*
+                        * Dedicated ENET_WOL# signal is unused, the PHY
+                        * can wake the SoC up via INT signal as well.
+                        */
+                       interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
+                       reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+                       reset-assert-us = <10000>;
+                       reset-deassert-us = <10000>;
+                       qca,keep-pll-enabled;
+                       vddio-supply = <&vddio_eqos>;
+
+                       vddio_eqos: vddio-regulator {
+                               regulator-name = "VDDIO_EQOS";
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                       };
+
+                       vddh_eqos: vddh-regulator {
+                               regulator-name = "VDDH_EQOS";
+                       };
+               };
+       };
+};
+
+&fec { /* Second ethernet */
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec>;
+       phy-handle = <&phy_fec>;
+       phy-mode = "rgmii-id";
+       fsl,magic-packet;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               /* Atheros AR8031 PHY */
+               phy_fec: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <0>;
+                       /*
+                        * Dedicated ENET_WOL# signal is unused, the PHY
+                        * can wake the SoC up via INT signal as well.
+                        */
+                       interrupts-extended = <&gpio2 2 IRQ_TYPE_LEVEL_LOW>;
+                       reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
+                       reset-assert-us = <10000>;
+                       reset-deassert-us = <10000>;
+                       qca,keep-pll-enabled;
+                       vddio-supply = <&vddio_fec>;
+
+                       vddio_fec: vddio-regulator {
+                               regulator-name = "VDDIO_FEC";
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                       };
+
+                       vddh_fec: vddh-regulator {
+                               regulator-name = "VDDH_FEC";
+                       };
+               };
+       };
+};
+
+&flexcan1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan1>;
+       status = "okay";
+};
+
+&gpio1 {
+       gpio-line-names =
+               "", "USBHUB_RESET#", "WDOG_B#", "PMIC_INT#",
+               "", "M2_PCIE_RST#", "M2_PCIE_WAKE#", "GPIO5_IO03",
+               "GPIO5_IO04", "PDM_SEL", "ENET_WOL#", "ENET_INT#",
+               "", "", "", "ENET_RST#",
+               "", "", "", "", "", "", "", "",
+               "", "", "", "", "", "", "", "";
+};
+
+&gpio2 {
+       gpio-line-names =
+               "", "", "ENET2_INT#", "", "", "", "", "",
+               "WDOG_KICK#", "ENET2_RST#", "CAN_INT#", "RTC_IRQ#",
+               "", "", "", "",
+               "", "", "", "SD2_RESET#", "", "", "", "",
+               "", "", "", "", "", "", "", "";
+};
+
+&gpio3 {
+       gpio-line-names =
+               "BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "",
+               "", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8",
+               "CSI2_PD_1V8", "CSI2_RESET_1V8#", "", "",
+               "", "", "EEPROM_WP_1V8#", "", "", "", "", "",
+               "MEMCFG0", "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#",
+               "", "M2_W_DISABLE1_1V8#",
+               "M2_W_DISABLE2_1V8#", "", "I2C5_SCL_3V3", "I2C5_SDA_3V3",
+               "", "", "", "";
+};
+
+&gpio4 {
+       gpio-line-names =
+               "DSI_RESET_1V8#", "MEMCFG2", "", "MEMCFG1", "", "", "", "",
+               "", "", "", "", "", "", "", "",
+               "", "", "GRAPHICS_PRSNT_1V8#", "DSI_IRQ_1V8#",
+               "", "DIS_USB_DN1", "DIS_USB_DN2", "",
+               "", "", "", "", "", "", "", "";
+};
+
+&gpio5 {
+       gpio-line-names =
+               "", "", "", "", "", "WDOG_EN", "", "",
+               "", "SPI1_CS#", "", "",
+               "", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3",
+               "I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3",
+               "", "", "", "",
+               "", "SPI3_CS#", "", "", "", "", "", "";
+};
+
+&i2c1 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default", "gpio";
+       pinctrl-0 = <&pinctrl_i2c1>;
+       pinctrl-1 = <&pinctrl_i2c1_gpio>;
+       scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+       sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+       status = "okay";
+
+       usb-hub@2c {
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_usb_hub>;
+               compatible = "microchip,usb2514bi";
+               reg = <0x2c>;
+               individual-port-switching;
+               reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+               self-powered;
+       };
+
+       eeprom: eeprom@50 {
+               compatible = "atmel,24c32";
+               reg = <0x50>;
+               pagesize = <32>;
+       };
+
+       rtc: rtc@68 {
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_rtc>;
+               compatible = "st,m41t62";
+               reg = <0x68>;
+               interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       pcieclk: clk@6a {
+               compatible = "renesas,9fgv0241";
+               reg = <0x6a>;
+               clocks = <&clk_xtal25>;
+               #clock-cells = <1>;
+       };
+};
+
+&i2c2 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default", "gpio";
+       pinctrl-0 = <&pinctrl_i2c2>;
+       pinctrl-1 = <&pinctrl_i2c2_gpio>;
+       scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+       sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+       status = "okay";
+};
+
+&i2c3 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default", "gpio";
+       pinctrl-0 = <&pinctrl_i2c3>;
+       pinctrl-1 = <&pinctrl_i2c3_gpio>;
+       scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+       sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+       status = "okay";
+
+       pmic: pmic@25 {
+               compatible = "nxp,pca9450c";
+               reg = <0x25>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_pmic>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+               sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+
+               /*
+                * i.MX 8M Plus Data Sheet for Consumer Products
+                * 3.1.4 Operating ranges
+                * MIMX8ML8CVNKZAB
+                */
+               regulators {
+                       buck1: BUCK1 {  /* VDD_SOC (dual-phase with BUCK3) */
+                               regulator-min-microvolt = <850000>;
+                               regulator-max-microvolt = <1000000>;
+                               regulator-ramp-delay = <3125>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                       };
+
+                       buck2: BUCK2 {  /* VDD_ARM */
+                               regulator-min-microvolt = <850000>;
+                               regulator-max-microvolt = <1000000>;
+                               regulator-ramp-delay = <3125>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                       };
+
+                       buck4: BUCK4 {  /* VDD_3V3 */
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                       };
+
+                       buck5: BUCK5 {  /* VDD_1V8 */
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                       };
+
+                       buck6: BUCK6 {  /* NVCC_DRAM_1V1 */
+                               regulator-min-microvolt = <1100000>;
+                               regulator-max-microvolt = <1100000>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                       };
+
+                       ldo1: LDO1 {    /* NVCC_SNVS_1V8 */
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                       };
+
+                       ldo3: LDO3 {    /* VDDA_1V8 */
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                       };
+
+                       ldo4: LDO4 {    /* PMIC_LDO4 */
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                       };
+
+                       ldo5: LDO5 {    /* NVCC_SD2 */
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                       };
+               };
+       };
+};
+
+&i2c5 {        /* HDMI EDID bus */
+       clock-frequency = <100000>;
+       pinctrl-names = "default", "gpio";
+       pinctrl-0 = <&pinctrl_i2c5>;
+       pinctrl-1 = <&pinctrl_i2c5_gpio>;
+       scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+       sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+       status = "okay";
+};
+
+&iomuxc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>,
+                   <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>,
+                   <&pinctrl_panel_expansion>;
+
+       pinctrl_ecspi1: ecspi1-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK           0x44
+                       MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI           0x44
+                       MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO           0x44
+                       MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09             0x40
+               >;
+       };
+
+       pinctrl_ecspi2: ecspi2-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK           0x44
+                       MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI           0x44
+                       MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO           0x44
+                       MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13             0x40
+               >;
+       };
+
+       pinctrl_ecspi3: ecspi3-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK             0x44
+                       MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI             0x44
+                       MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO             0x44
+                       MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25              0x40
+               >;
+       };
+
+       pinctrl_eqos: eqos-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC             0x3
+                       MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO           0x3
+                       MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+                       MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK       0x1f
+                       MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0       0x1f
+                       MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1       0x1f
+                       MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2       0x1f
+                       MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3       0x1f
+                       MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK       0x91
+                       MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+                       MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0       0x91
+                       MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1       0x91
+                       MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2       0x91
+                       MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3       0x91
+                       /* ENET_RST# */
+                       MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15             0x6
+                       /* ENET_INT# */
+                       MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11             0x40000090
+               >;
+       };
+
+       pinctrl_fec: fec-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC               0x3
+                       MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO              0x3
+                       MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0         0x91
+                       MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1         0x91
+                       MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2         0x91
+                       MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3         0x91
+                       MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC          0x91
+                       MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL      0x91
+                       MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0         0x1f
+                       MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1         0x1f
+                       MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2         0x1f
+                       MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3         0x1f
+                       MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL      0x1f
+                       MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC         0x1f
+                       /* ENET2_RST# */
+                       MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09              0x6
+                       /* ENET2_INT# */
+                       MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02              0x40000090
+               >;
+       };
+
+       pinctrl_flexcan1: flexcan1-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SPDIF_RX__CAN1_RX                  0x154
+                       MX8MP_IOMUXC_SPDIF_TX__CAN1_TX                  0x154
+               >;
+       };
+
+       pinctrl_hog_feature: hog-feature-grp {
+               fsl,pins = <
+                       /* GPIO5_IO03 */
+                       MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07             0x40000006
+                       /* GPIO5_IO04 */
+                       MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08             0x40000006
+
+                       /* CAN_INT# */
+                       MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10            0x40000090
+               >;
+       };
+
+       pinctrl_hog_panel: hog-panel-grp {
+               fsl,pins = <
+                       /* GRAPHICS_GPIO0_1V8 */
+                       MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07            0x26
+               >;
+       };
+
+       pinctrl_hog_misc: hog-misc-grp {
+               fsl,pins = <
+                       /* ENET_WOL# -- shared by both PHYs */
+                       MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10             0x40000090
+
+                       /* PG_V_IN_VAR# */
+                       MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01             0x40000000
+                       /* CSI2_PD_1V8 */
+                       MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08            0x0
+                       /* CSI2_RESET_1V8# */
+                       MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09            0x0
+
+                       /* DIS_USB_DN1 */
+                       MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21              0x0
+                       /* DIS_USB_DN2 */
+                       MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22               0x0
+
+                       /* EEPROM_WP_1V8# */
+                       MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14               0x100
+                       /* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */
+                       MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21              0x0
+                       /* GRAPHICS_PRSNT_1V8# */
+                       MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18              0x40000000
+
+                       /* CLK_CCM_CLKO1_3V3 */
+                       MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1              0x10
+               >;
+       };
+
+       pinctrl_hog_sbc: hog-sbc-grp {
+               fsl,pins = <
+                       /* MEMCFG[0..2] straps */
+                       MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20               0x40000140
+                       MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03              0x40000140
+                       MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01               0x40000140
+               >;
+       };
+
+       pinctrl_i2c1: i2c1-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL                 0x40000084
+                       MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA                 0x40000084
+               >;
+       };
+
+       pinctrl_i2c1_gpio: i2c1-gpio-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14               0x84
+                       MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15               0x84
+               >;
+       };
+
+       pinctrl_i2c2: i2c2-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL                 0x40000084
+                       MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA                 0x40000084
+               >;
+       };
+
+       pinctrl_i2c2_gpio: i2c2-gpio-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16               0x84
+                       MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17               0x84
+               >;
+       };
+
+       pinctrl_i2c3: i2c3-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL                 0x40000084
+                       MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA                 0x40000084
+               >;
+       };
+
+       pinctrl_i2c3_gpio: i2c3-gpio-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18               0x84
+                       MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19               0x84
+               >;
+       };
+
+       pinctrl_i2c5: i2c5-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL             0x40000084
+                       MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA             0x40000084
+               >;
+       };
+
+       pinctrl_i2c5_gpio: i2c5-gpio-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26           0x84
+                       MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27           0x84
+               >;
+       };
+
+       pinctrl_panel_backlight: panel-backlight-grp {
+               fsl,pins = <
+                       /* BL_ENABLE_1V8 */
+                       MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00               0x104
+               >;
+       };
+
+       pinctrl_panel_expansion: panel-expansion-grp {
+               fsl,pins = <
+                       /* DSI_RESET_1V8# */
+                       MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00              0x2
+                       /* DSI_IRQ_1V8# */
+                       MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19              0x40000090
+               >;
+       };
+
+       pinctrl_panel_pwm: panel-pwm-grp {
+               fsl,pins = <
+                       /* BL_PWM_3V3 */
+                       MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT                 0x12
+               >;
+       };
+
+       pinctrl_panel_vcc_reg: panel-vcc-grp {
+               fsl,pins = <
+                       /* TFT_ENABLE_1V8 */
+                       MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06            0x104
+               >;
+       };
+
+       pinctrl_pcie0: pcie-grp {
+               fsl,pins = <
+                       /* M2_PCIE_RST# */
+                       MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05             0x2
+                       /* M2_W_DISABLE1_1V8# */
+                       MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23              0x2
+                       /* M2_W_DISABLE2_1V8# */
+                       MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24              0x2
+                       /* CLK_M2_32K768 */
+                       MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1           0x14
+                       /* M2_PCIE_WAKE# */
+                       MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06             0x40000140
+                       /* M2_PCIE_CLKREQ# */
+                       MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B            0x61
+               >;
+       };
+
+       pinctrl_pdm: pdm-grp {
+               fsl,pins = <
+                       /* PDM_SEL */
+                       MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09             0x0
+                       MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK         0x0
+                       MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00       0x0
+               >;
+       };
+
+       pinctrl_pmic: pmic-grp {
+               fsl,pins = <
+                       /* PMIC_nINT */
+                       MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03             0x40000090
+               >;
+       };
+
+       pinctrl_rtc: rtc-grp {
+               fsl,pins = <
+                       /* RTC_IRQ# */
+                       MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11             0x40000090
+               >;
+       };
+
+       pinctrl_sai1: sai1-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC   0xd6
+                       MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0xd6
+                       MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK   0xd6
+                       MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK      0xd6
+                       MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0xd6
+               >;
+       };
+
+       pinctrl_sai2: sai2-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC   0xd6
+                       MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
+                       MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK    0xd6
+                       MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK      0xd6
+               >;
+       };
+
+       pinctrl_sai3: sai3-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC   0xd6
+                       MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00  0xd6
+                       MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK    0xd6
+                       MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK      0xd6
+                       MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00  0xd6
+               >;
+       };
+
+       pinctrl_uart1: uart1-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX              0x49
+                       MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX              0x49
+                       MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS           0x49
+                       MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS           0x49
+               >;
+       };
+
+       pinctrl_uart2: uart2-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX            0x49
+                       MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX            0x49
+                       MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS           0x49
+                       MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS           0x49
+               >;
+       };
+
+       pinctrl_uart3: uart3-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX            0x49
+                       MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX            0x49
+               >;
+       };
+
+       pinctrl_uart4: uart4-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX            0x49
+                       MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX            0x49
+               >;
+       };
+
+       pinctrl_usdhc2: usdhc2-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                0x190
+                       MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                0x1d0
+                       MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0            0x1d0
+                       MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1            0x1d0
+                       MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2            0x1d0
+                       MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3            0x1d0
+                       MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT         0xc1
+               >;
+       };
+
+       pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                0x194
+                       MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                0x1d4
+                       MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0            0x1d4
+                       MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1            0x1d4
+                       MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2            0x1d4
+                       MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3            0x1d4
+                       MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT         0xc1
+               >;
+       };
+
+       pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                0x196
+                       MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                0x1d6
+                       MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0            0x1d6
+                       MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1            0x1d6
+                       MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2            0x1d6
+                       MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3            0x1d6
+                       MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT         0xc1
+               >;
+       };
+
+       pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19            0x20
+               >;
+       };
+
+       pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12               0x40000080
+               >;
+       };
+
+       pinctrl_usdhc3: usdhc3-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK              0x190
+                       MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD              0x1d0
+                       MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0          0x1d0
+                       MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1          0x1d0
+                       MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2          0x1d0
+                       MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3          0x1d0
+                       MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4            0x1d0
+                       MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5           0x1d0
+                       MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6           0x1d0
+                       MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7             0x1d0
+                       MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE          0x190
+                       MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B       0x141
+               >;
+       };
+
+       pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK              0x194
+                       MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD              0x1d4
+                       MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0          0x1d4
+                       MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1          0x1d4
+                       MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2          0x1d4
+                       MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3          0x1d4
+                       MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4            0x1d4
+                       MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5           0x1d4
+                       MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6           0x1d4
+                       MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7             0x1d4
+                       MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE          0x194
+                       MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B       0x141
+               >;
+       };
+
+       pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK              0x196
+                       MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD              0x1d6
+                       MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0          0x1d6
+                       MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1          0x1d6
+                       MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2          0x1d6
+                       MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3          0x1d6
+                       MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4            0x1d6
+                       MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5           0x1d6
+                       MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6           0x1d6
+                       MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7             0x1d6
+                       MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE          0x196
+                       MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B       0x141
+               >;
+       };
+
+       pinctrl_usb_hub: usb-hub-grp {
+               fsl,pins = <
+                       /* USBHUB_RESET# */
+                       MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01             0x4
+               >;
+       };
+
+       pinctrl_usb1: usb1-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR           0x6
+                       MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC            0x80
+               >;
+       };
+
+       pinctrl_watchdog_gpio: watchdog-gpio-grp {
+               fsl,pins = <
+                       /* WDOG_B# */
+                       MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B           0x26
+                       /* WDOG_EN -- ungate WDT RESET# signal propagation */
+                       MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05          0x6
+                       /* WDOG_KICK# / WDI */
+                       MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08              0x26
+               >;
+       };
+};
+
+&pwm1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_panel_pwm>;
+       /* Disabled by default, unless display board plugged in. */
+       status = "disabled";
+};
+
+/* SD slot */
+&usdhc2 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+       cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+       vmmc-supply = <&reg_usdhc2_vmmc>;
+       bus-width = <4>;
+       status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc3>;
+       pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+       vmmc-supply = <&buck4>;
+       vqmmc-supply = <&buck5>;
+       bus-width = <8>;
+       non-removable;
+       status = "okay";
+};
+
+&uart1 {       /* RS485 */
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+       uart-has-rtscts;
+       status = "disabled";    /* Optional */
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2>;
+       uart-has-rtscts;
+       status = "okay";
+};
+
+&uart3 {       /* A53 Debug */
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart3>;
+       status = "okay";
+};
+
+&uart4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart4>;
+       status = "okay";
+};
+
+&usb3_phy0 {
+       status = "okay";
+};
+
+&usb3_0 {
+       fsl,over-current-active-low;
+       status = "okay";
+};
+
+&usb_dwc3_0 {  /* Lower plug direct */
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usb1>;
+       dr_mode = "host";
+       status = "okay";
+};
+
+&usb3_phy1 {
+       status = "okay";
+};
+
+&usb3_1 {
+       status = "okay";
+};
+
+&usb_dwc3_1 {  /* Upper plug via HUB */
+       dr_mode = "host";
+       status = "okay";
+};
+
+&wdog1 {
+       status = "okay";
+};

diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts
index dad4670..78df7ce 100644 (file)
--- a/arch/arm/dts/k3-am625-r5-sk.dts
+++ b/arch/arm/dts/k3-am625-r5-sk.dts
@@ -47,7 +47,8 @@
                compatible = "ti,am654-rproc";
                reg = <0x00 0x00a90000 0x00 0x10>;
                power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-                               <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
+                               <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+                               <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
                resets = <&k3_reset 135 0>;
                clocks = <&k3_clks 61 0>;
                assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;

diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts
index c953a82..cc4b179 100644 (file)
--- a/arch/arm/dts/k3-am62a7-r5-sk.dts
+++ b/arch/arm/dts/k3-am62a7-r5-sk.dts
@@ -47,7 +47,8 @@
                compatible = "ti,am654-rproc";
                reg = <0x00 0x00a90000 0x00 0x10>;
                power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-                               <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
+                               <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+                               <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
                resets = <&k3_reset 135 0>;
                clocks = <&k3_clks 61 0>;
                assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;

diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts
index ca5ce4a..e870492 100644 (file)
--- a/arch/arm/dts/k3-am642-r5-evm.dts
+++ b/arch/arm/dts/k3-am642-r5-evm.dts
@@ -32,7 +32,8 @@
                compatible = "ti,am654-rproc";
                reg = <0x00 0x00a90000 0x00 0x10>;
                power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-                               <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
+                               <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+                               <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
                resets = <&k3_reset 135 0>;
                clocks = <&k3_clks 61 0>;
                assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;

diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts
index 9ff4dd3..32d4c31 100644 (file)
--- a/arch/arm/dts/k3-am642-r5-sk.dts
+++ b/arch/arm/dts/k3-am642-r5-sk.dts
@@ -34,7 +34,8 @@
                compatible = "ti,am654-rproc";
                reg = <0x00 0x00a90000 0x00 0x10>;
                power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-                               <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
+                               <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+                               <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
                resets = <&k3_reset 135 0>;
                clocks = <&k3_clks 61 0>;
                assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;

diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 55ad615..e62f921 100644 (file)
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -30,7 +30,8 @@
                compatible = "ti,am654-rproc";
                reg = <0x0 0x00a90000 0x0 0x10>;
                power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-                               <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
+                               <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
+                               <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
                resets = <&k3_reset 202 0>;
                clocks = <&k3_clks 61 1>;
                assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;

diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index e9e5053..1b40cf2 100644 (file)
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -25,7 +25,8 @@
                compatible = "ti,am654-rproc";
                reg = <0x0 0x00a90000 0x0 0x10>;
                power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-                               <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
+                               <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
+                               <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
                resets = <&k3_reset 202 0>;
                clocks = <&k3_clks 61 1>;
                assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;

diff --git a/arch/arm/dts/k3-j721e-r5-sk.dts b/arch/arm/dts/k3-j721e-r5-sk.dts
index 8d6eaa4..6986292 100644 (file)
--- a/arch/arm/dts/k3-j721e-r5-sk.dts
+++ b/arch/arm/dts/k3-j721e-r5-sk.dts
@@ -159,7 +159,8 @@
                compatible = "ti,am654-rproc";
                reg = <0x0 0x00a90000 0x0 0x10>;
                power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-                               <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
+                               <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
+                               <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
                resets = <&k3_reset 202 0>;
                clocks = <&k3_clks 61 1>;
                assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;

diff --git a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
index 0949caa..31f979f 100644 (file)
--- a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
@@ -33,7 +33,7 @@
 &cbass_main{
        bootph-pre-ram;
 
-       main_navss {
+       main_navss: bus@30000000 {
                bootph-pre-ram;
        };
 };
@@ -49,7 +49,7 @@
                bootph-pre-ram;
        };
 
-       mcu-navss {
+       mcu_navss: bus@28380000 {
                bootph-pre-ram;
 
                ringacc@2b800000 {
@@ -237,6 +237,10 @@
        bootph-pre-ram;
 };
 
+&hbmc {
+       status = "disabled";
+};
+
 &ospi0 {
        bootph-pre-ram;
 

diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
index bc61702..e02b334 100644 (file)
--- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
@@ -30,7 +30,8 @@
                compatible = "ti,am654-rproc";
                reg = <0x0 0x00a90000 0x0 0x10>;
                power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-                               <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
+                               <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
+                               <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
                resets = <&k3_reset 202 0>;
                clocks = <&k3_clks 61 1>;
                assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>;

diff --git a/arch/arm/dts/keystone-clocks.dtsi b/arch/arm/dts/keystone-clocks.dtsi
index 0c334b2..457515b 100644 (file)
--- a/arch/arm/dts/keystone-clocks.dtsi
+++ b/arch/arm/dts/keystone-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Device Tree Source for Keystone 2 clock tree
  *
- * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 clocks {
@@ -51,7 +48,7 @@ clocks {
                clock-output-names = "gemtraceclk";
        };
 
-       chipstmxptclk: chipstmxptclk {
+       chipstmxptclk: chipstmxptclk@2310164 {
                #clock-cells = <0>;
                compatible = "ti,keystone,pll-divider-clock";
                clocks = <&mainmuxclk>;
@@ -160,7 +157,7 @@ clocks {
                clock-output-names = "chipclk1rstiso112";
        };
 
-       clkmodrst0: clkmodrst0 {
+       clkmodrst0: clkmodrst0@2350000 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk16>;
@@ -171,7 +168,7 @@ clocks {
        };
 
 
-       clkusb: clkusb {
+       clkusb: clkusb@2350008 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk16>;
@@ -181,7 +178,7 @@ clocks {
                domain-id = <0>;
        };
 
-       clkaemifspi: clkaemifspi {
+       clkaemifspi: clkaemifspi@235000c {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk16>;
@@ -192,7 +189,7 @@ clocks {
        };
 
 
-       clkdebugsstrc: clkdebugsstrc {
+       clkdebugsstrc: clkdebugsstrc@2350014 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -202,7 +199,7 @@ clocks {
                domain-id = <1>;
        };
 
-       clktetbtrc: clktetbtrc {
+       clktetbtrc: clktetbtrc@2350018 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -212,7 +209,7 @@ clocks {
                domain-id = <1>;
        };
 
-       clkpa: clkpa {
+       clkpa: clkpa@235001c {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&paclk13>;
@@ -222,7 +219,7 @@ clocks {
                domain-id = <2>;
        };
 
-       clkcpgmac: clkcpgmac {
+       clkcpgmac: clkcpgmac@2350020 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&clkpa>;
@@ -232,7 +229,7 @@ clocks {
                domain-id = <2>;
        };
 
-       clksa: clksa {
+       clksa: clksa@2350024 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&clkpa>;
@@ -242,7 +239,7 @@ clocks {
                domain-id = <2>;
        };
 
-       clkpcie: clkpcie {
+       clkpcie: clkpcie@2350028 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk12>;
@@ -252,7 +249,7 @@ clocks {
                domain-id = <3>;
        };
 
-       clksr: clksr {
+       clksr: clksr@2350034 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk1rstiso112>;
@@ -262,7 +259,7 @@ clocks {
                domain-id = <6>;
        };
 
-       clkgem0: clkgem0 {
+       clkgem0: clkgem0@235003c {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk1>;
@@ -272,7 +269,7 @@ clocks {
                domain-id = <8>;
        };
 
-       clkddr30: clkddr30 {
+       clkddr30: clkddr30@235005c {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk12>;
@@ -282,7 +279,7 @@ clocks {
                domain-id = <16>;
        };
 
-       clkwdtimer0: clkwdtimer0 {
+       clkwdtimer0: clkwdtimer0@2350000 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&clkmodrst0>;
@@ -292,7 +289,7 @@ clocks {
                domain-id = <0>;
        };
 
-       clkwdtimer1: clkwdtimer1 {
+       clkwdtimer1: clkwdtimer1@2350000 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&clkmodrst0>;
@@ -302,7 +299,7 @@ clocks {
                domain-id = <0>;
        };
 
-       clkwdtimer2: clkwdtimer2 {
+       clkwdtimer2: clkwdtimer2@2350000 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&clkmodrst0>;
@@ -312,7 +309,7 @@ clocks {
                domain-id = <0>;
        };
 
-       clkwdtimer3: clkwdtimer3 {
+       clkwdtimer3: clkwdtimer3@2350000 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&clkmodrst0>;
@@ -322,7 +319,7 @@ clocks {
                domain-id = <0>;
        };
 
-       clktimer15: clktimer15 {
+       clktimer15: clktimer15@2350000 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&clkmodrst0>;
@@ -332,7 +329,7 @@ clocks {
                domain-id = <0>;
        };
 
-       clkuart0: clkuart0 {
+       clkuart0: clkuart0@2350000 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&clkmodrst0>;
@@ -342,7 +339,7 @@ clocks {
                domain-id = <0>;
        };
 
-       clkuart1: clkuart1 {
+       clkuart1: clkuart1@2350000 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&clkmodrst0>;
@@ -352,7 +349,7 @@ clocks {
                domain-id = <0>;
        };
 
-       clkaemif: clkaemif {
+       clkaemif: clkaemif@2350000 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&clkaemifspi>;
@@ -362,7 +359,7 @@ clocks {
                domain-id = <0>;
        };
 
-       clkusim: clkusim {
+       clkusim: clkusim@2350000 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&clkmodrst0>;
@@ -372,7 +369,7 @@ clocks {
                domain-id = <0>;
        };
 
-       clki2c: clki2c {
+       clki2c: clki2c@2350000 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&clkmodrst0>;
@@ -382,7 +379,7 @@ clocks {
                domain-id = <0>;
        };
 
-       clkspi: clkspi {
+       clkspi: clkspi@2350000 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&clkaemifspi>;
@@ -392,7 +389,7 @@ clocks {
                domain-id = <0>;
        };
 
-       clkgpio: clkgpio {
+       clkgpio: clkgpio@2350000 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&clkmodrst0>;
@@ -402,7 +399,7 @@ clocks {
                domain-id = <0>;
        };
 
-       clkkeymgr: clkkeymgr {
+       clkkeymgr: clkkeymgr@2350000 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&clkmodrst0>;

diff --git a/arch/arm/dts/keystone-k2e-clocks.dtsi b/arch/arm/dts/keystone-k2e-clocks.dtsi
index d56d68f..f759215 100644 (file)
--- a/arch/arm/dts/keystone-k2e-clocks.dtsi
+++ b/arch/arm/dts/keystone-k2e-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2014 Texas Instruments, Inc.
- *
  * Keystone 2 Edison SoC specific device tree
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 clocks {
@@ -35,7 +32,7 @@ clocks {
                reg-names = "control";
        };
 
-       clkusb1: clkusb1 {
+       clkusb1: clkusb1@2350004 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk16>;
@@ -45,7 +42,7 @@ clocks {
                domain-id = <0>;
        };
 
-       clkhyperlink0: clkhyperlink0 {
+       clkhyperlink0: clkhyperlink0@2350030 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk12>;
@@ -55,7 +52,7 @@ clocks {
                domain-id = <5>;
        };
 
-       clkpcie1: clkpcie1 {
+       clkpcie1: clkpcie1@235006c {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk12>;
@@ -65,7 +62,7 @@ clocks {
                domain-id = <18>;
        };
 
-       clkxge: clkxge {
+       clkxge: clkxge@23500c8 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;

diff --git a/arch/arm/dts/keystone-k2e-evm.dts b/arch/arm/dts/keystone-k2e-evm.dts
index bb197e1..ed76e56 100644 (file)
--- a/arch/arm/dts/keystone-k2e-evm.dts
+++ b/arch/arm/dts/keystone-k2e-evm.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2013-2014 Texas Instruments, Inc.
- *
  * Keystone 2 Edison EVM device tree
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 /dts-v1/;
 
@@ -13,7 +10,7 @@
 #include "keystone-k2e.dtsi"
 
 / {
-       compatible =  "ti,k2e-evm","ti,keystone";
+       compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone";
        model = "Texas Instruments Keystone 2 Edison EVM";
 
        soc {
@@ -120,7 +117,7 @@
 
 &spi0 {
        status = "okay";
-       nor_flash: n25q128a11@0 {
+       nor_flash: flash@0 {
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "Micron,n25q128a11", "jedec,spi-nor";

diff --git a/arch/arm/dts/keystone-k2e-netcp.dtsi b/arch/arm/dts/keystone-k2e-netcp.dtsi
index b13b3c9..45ebb0a 100644 (file)
--- a/arch/arm/dts/keystone-k2e-netcp.dtsi
+++ b/arch/arm/dts/keystone-k2e-netcp.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Device Tree Source for Keystone 2 Edison Netcp driver
  *
- * Copyright 2015 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 qmss: qmss@2a40000 {
@@ -15,9 +12,9 @@ qmss: qmss@2a40000 {
        #size-cells = <1>;
        clocks = <&chipclk13>;
        ranges;
-       queue-range     = <0 0x2000>;
-       linkram0        = <0x100000 0x4000>;
-       linkram1        = <0 0x10000>;
+       queue-range = <0 0x2000>;
+       linkram0 = <0x100000 0x4000>;
+       linkram1 = <0 0x10000>;
 
        qmgrs {
                #address-cells = <1>;
@@ -138,40 +135,40 @@ netcp: netcp@24000000 {
                        interfaces {
                                gbe0: interface-0 {
                                        slave-port = <0>;
-                                       link-interface  = <1>;
-                                       phy-handle      = <&ethphy0>;
+                                       link-interface = <1>;
+                                       phy-handle = <&ethphy0>;
                                };
                                gbe1: interface-1 {
                                        slave-port = <1>;
-                                       link-interface  = <1>;
-                                       phy-handle      = <&ethphy1>;
+                                       link-interface = <1>;
+                                       phy-handle = <&ethphy1>;
                                };
                        };
 
                        secondary-slave-ports {
                                port-2 {
                                        slave-port = <2>;
-                                       link-interface  = <2>;
+                                       link-interface = <2>;
                                };
                                port-3 {
                                        slave-port = <3>;
-                                       link-interface  = <2>;
+                                       link-interface = <2>;
                                };
                                port-4 {
                                        slave-port = <4>;
-                                       link-interface  = <2>;
+                                       link-interface = <2>;
                                };
                                port-5 {
                                        slave-port = <5>;
-                                       link-interface  = <2>;
+                                       link-interface = <2>;
                                };
                                port-6 {
                                        slave-port = <6>;
-                                       link-interface  = <2>;
+                                       link-interface = <2>;
                                };
                                port-7 {
                                        slave-port = <7>;
-                                       link-interface  = <2>;
+                                       link-interface = <2>;
                                };
                        };
                };

diff --git a/arch/arm/dts/keystone-k2e.dtsi b/arch/arm/dts/keystone-k2e.dtsi
index b5d9061..496bb31 100644 (file)
--- a/arch/arm/dts/keystone-k2e.dtsi
+++ b/arch/arm/dts/keystone-k2e.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2013-2014 Texas Instruments, Inc.
- *
  * Keystone 2 Edison soc device tree
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 / {
@@ -45,7 +42,7 @@
 
                usb: usb@2680000 {
                        interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
-                       dwc3@2690000 {
+                       usb@2690000 {
                                interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
                        };
                };
@@ -71,7 +68,7 @@
                        dma-ranges;
                        status = "disabled";
 
-                       dwc3@25010000 {
+                       usb@25010000 {
                                compatible = "synopsys,dwc3";
                                reg = <0x25010000 0x70000>;
                                interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
@@ -92,7 +89,7 @@
                        clock-names = "pcie";
                        #address-cells = <3>;
                        #size-cells = <2>;
-                       reg =  <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
+                       reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
                        ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
                                0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
 
@@ -133,14 +130,14 @@
                };
 
                mdio: mdio@24200f00 {
-                       compatible      = "ti,keystone_mdio", "ti,davinci_mdio";
+                       compatible = "ti,keystone_mdio", "ti,davinci_mdio";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <0x24200f00 0x100>;
                        status = "disabled";
                        clocks = <&clkcpgmac>;
                        clock-names = "fck";
-                       bus_freq        = <2500000>;
+                       bus_freq = <2500000>;
                };
                /include/ "keystone-k2e-netcp.dtsi"
        };

diff --git a/arch/arm/dts/keystone-k2g-evm.dts b/arch/arm/dts/keystone-k2g-evm.dts
index b5b511c..6376c62 100644 (file)
--- a/arch/arm/dts/keystone-k2g-evm.dts
+++ b/arch/arm/dts/keystone-k2g-evm.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2014 Texas Instruments, Inc.
- *
  * Device Tree Source for K2G EVM
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 /dts-v1/;
 
@@ -93,8 +90,8 @@
 &qspi {
        status = "okay";
 
-       flash0: m25p80@0 {
-               compatible = "s25fl512s","jedec,spi-nor";
+       flash0: flash@0 {
+               compatible = "s25fl512s", "jedec,spi-nor";
                reg = <0>;
                spi-tx-bus-width = <1>;
                spi-rx-bus-width = <4>;

diff --git a/arch/arm/dts/keystone-k2g-ice.dts b/arch/arm/dts/keystone-k2g-ice.dts
index ecca2df..cbdb6bf 100644 (file)
--- a/arch/arm/dts/keystone-k2g-ice.dts
+++ b/arch/arm/dts/keystone-k2g-ice.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Device Tree Source for K2G Industrial Communication Engine EVM
  *
@@ -38,7 +38,7 @@
 &qspi {
        status = "okay";
 
-       flash0: m25p80@0 {
+       flash0: flash@0 {
                compatible = "s25fl256s1", "jedec,spi-nor";
                reg = <0>;
                spi-tx-bus-width = <1>;

diff --git a/arch/arm/dts/keystone-k2g-netcp.dtsi b/arch/arm/dts/keystone-k2g-netcp.dtsi
index d76f2a1..136cd20 100644 (file)
--- a/arch/arm/dts/keystone-k2g-netcp.dtsi
+++ b/arch/arm/dts/keystone-k2g-netcp.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Device Tree Source for K2G Netcp driver
  *
- * Copyright 2015 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 qmss: qmss@4020000 {
@@ -17,8 +14,8 @@ qmss: qmss@4020000 {
        /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; */
        clock-names = "nss_vclk";
        ranges;
-       queue-range     = <0 0x80>;
-       linkram0        = <0x4020000 0x7ff>;
+       queue-range = <0 0x80>;
+       linkram0 = <0x4020000 0x7ff>;
 
        qmgrs {
                #address-cells = <1>;
@@ -80,12 +77,12 @@ knav_dmas: knav_dmas@0 {
 
        dma_gbe: dma_gbe@0 {
                reg = <0x4010000 0x100>,
-                         <0x4011000 0x2a0>, /* 21 Tx channels */
-                         <0x4012000 0x400>, /* 32 Rx channels */
-                         <0x4010100 0x80>,
-                         <0x4013000 0x400>; /* 32 Rx flows */
+                     <0x4011000 0x2a0>, /* 21 Tx channels */
+                     <0x4012000 0x400>, /* 32 Rx channels */
+                     <0x4010100 0x80>,
+                     <0x4013000 0x400>; /* 32 Rx flows */
                reg-names = "global", "txchan", "rxchan",
-                               "txsched", "rxflow";
+                           "txsched", "rxflow";
        };
 
 };
@@ -99,9 +96,9 @@ netcp: netcp@4000000 {
        reg = <0x2620110 0x8>;
        reg-names = "efuse";
        compatible = "ti,netcp-1.0";
-       status = "disabled";
        #address-cells = <1>;
        #size-cells = <1>;
+       status = "disabled";
        /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
        /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */
        clock-names = "ethss_clk";
@@ -130,7 +127,7 @@ netcp: netcp@4000000 {
                        interfaces {
                                gbe0: interface-0 {
                                        slave-port = <0>;
-                                       link-interface  = <5>;
+                                       link-interface = <5>;
                                };
                        };
                };

diff --git a/arch/arm/dts/keystone-k2g.dtsi b/arch/arm/dts/keystone-k2g.dtsi
index ede7118..f12af43 100644 (file)
--- a/arch/arm/dts/keystone-k2g.dtsi
+++ b/arch/arm/dts/keystone-k2g.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2014 Texas Instruments, Inc.
- *
  * Device Tree Source for K2G SOC
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -43,7 +40,7 @@
                };
        };
 
-       gic: interrupt-controller {
+       gic: interrupt-controller@2561000 {
                compatible = "arm,cortex-a15-gic";
                #interrupt-cells = <3>;
                interrupt-controller;

diff --git a/arch/arm/dts/keystone-k2hk-clocks.dtsi b/arch/arm/dts/keystone-k2hk-clocks.dtsi
index af9b719..4ba6912 100644 (file)
--- a/arch/arm/dts/keystone-k2hk-clocks.dtsi
+++ b/arch/arm/dts/keystone-k2hk-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2013-2014 Texas Instruments, Inc.
- *
  * Keystone 2 Kepler/Hawking SoC clock nodes
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 clocks {
@@ -53,7 +50,7 @@ clocks {
                reg-names = "control";
        };
 
-       clktsip: clktsip {
+       clktsip: clktsip@2350000 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk16>;
@@ -63,7 +60,7 @@ clocks {
                domain-id = <0>;
        };
 
-       clksrio: clksrio {
+       clksrio: clksrio@235002c {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk1rstiso13>;
@@ -73,7 +70,7 @@ clocks {
                domain-id = <4>;
        };
 
-       clkhyperlink0: clkhyperlink0 {
+       clkhyperlink0: clkhyperlink0@2350030 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk12>;
@@ -83,7 +80,7 @@ clocks {
                domain-id = <5>;
        };
 
-       clkgem1: clkgem1 {
+       clkgem1: clkgem1@2350040 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk1>;
@@ -93,7 +90,7 @@ clocks {
                domain-id = <9>;
        };
 
-       clkgem2: clkgem2 {
+       clkgem2: clkgem2@2350044 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk1>;
@@ -103,7 +100,7 @@ clocks {
                domain-id = <10>;
        };
 
-       clkgem3: clkgem3 {
+       clkgem3: clkgem3@2350048 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk1>;
@@ -113,7 +110,7 @@ clocks {
                domain-id = <11>;
        };
 
-       clkgem4: clkgem4 {
+       clkgem4: clkgem4@235004c {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk1>;
@@ -123,7 +120,7 @@ clocks {
                domain-id = <12>;
        };
 
-       clkgem5: clkgem5 {
+       clkgem5: clkgem5@2350050 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk1>;
@@ -133,7 +130,7 @@ clocks {
                domain-id = <13>;
        };
 
-       clkgem6: clkgem6 {
+       clkgem6: clkgem6@2350054 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk1>;
@@ -143,7 +140,7 @@ clocks {
                domain-id = <14>;
        };
 
-       clkgem7: clkgem7 {
+       clkgem7: clkgem7@2350058 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk1>;
@@ -153,7 +150,7 @@ clocks {
                domain-id = <15>;
        };
 
-       clkddr31: clkddr31 {
+       clkddr31: clkddr31@2350060 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -163,7 +160,7 @@ clocks {
                domain-id = <16>;
        };
 
-       clktac: clktac {
+       clktac: clktac@2350064 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -173,7 +170,7 @@ clocks {
                domain-id = <17>;
        };
 
-       clkrac01: clkrac01 {
+       clkrac01: clkrac01@2350068 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -183,7 +180,7 @@ clocks {
                domain-id = <17>;
        };
 
-       clkrac23: clkrac23 {
+       clkrac23: clkrac23@235006c {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -193,7 +190,7 @@ clocks {
                domain-id = <18>;
        };
 
-       clkfftc0: clkfftc0 {
+       clkfftc0: clkfftc0@2350070 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -203,7 +200,7 @@ clocks {
                domain-id = <19>;
        };
 
-       clkfftc1: clkfftc1 {
+       clkfftc1: clkfftc1@2350074 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -213,7 +210,7 @@ clocks {
                domain-id = <19>;
        };
 
-       clkfftc2: clkfftc2 {
+       clkfftc2: clkfftc2@2350078 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -223,7 +220,7 @@ clocks {
                domain-id = <20>;
        };
 
-       clkfftc3: clkfftc3 {
+       clkfftc3: clkfftc3@235007c {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -233,7 +230,7 @@ clocks {
                domain-id = <20>;
        };
 
-       clkfftc4: clkfftc4 {
+       clkfftc4: clkfftc4@2350080 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -243,7 +240,7 @@ clocks {
                domain-id = <20>;
        };
 
-       clkfftc5: clkfftc5 {
+       clkfftc5: clkfftc5@2350084 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -253,7 +250,7 @@ clocks {
                domain-id = <20>;
        };
 
-       clkaif: clkaif {
+       clkaif: clkaif@2350088 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -263,7 +260,7 @@ clocks {
                domain-id = <21>;
        };
 
-       clktcp3d0: clktcp3d0 {
+       clktcp3d0: clktcp3d0@235008c {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -273,7 +270,7 @@ clocks {
                domain-id = <22>;
        };
 
-       clktcp3d1: clktcp3d1 {
+       clktcp3d1: clktcp3d1@2350090 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -283,7 +280,7 @@ clocks {
                domain-id = <22>;
        };
 
-       clktcp3d2: clktcp3d2 {
+       clktcp3d2: clktcp3d2@2350094 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -293,7 +290,7 @@ clocks {
                domain-id = <23>;
        };
 
-       clktcp3d3: clktcp3d3 {
+       clktcp3d3: clktcp3d3@2350098 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -303,7 +300,7 @@ clocks {
                domain-id = <23>;
        };
 
-       clkvcp0: clkvcp0 {
+       clkvcp0: clkvcp0@235009c {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -313,7 +310,7 @@ clocks {
                domain-id = <24>;
        };
 
-       clkvcp1: clkvcp1 {
+       clkvcp1: clkvcp1@23500a0 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -323,7 +320,7 @@ clocks {
                domain-id = <24>;
        };
 
-       clkvcp2: clkvcp2 {
+       clkvcp2: clkvcp2@23500a4 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -333,7 +330,7 @@ clocks {
                domain-id = <24>;
        };
 
-       clkvcp3: clkvcp3 {
+       clkvcp3: clkvcp3@23500a8 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -343,7 +340,7 @@ clocks {
                domain-id = <24>;
        };
 
-       clkvcp4: clkvcp4 {
+       clkvcp4: clkvcp4@23500ac {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -353,7 +350,7 @@ clocks {
                domain-id = <25>;
        };
 
-       clkvcp5: clkvcp5 {
+       clkvcp5: clkvcp5@23500b0 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -363,7 +360,7 @@ clocks {
                domain-id = <25>;
        };
 
-       clkvcp6: clkvcp6 {
+       clkvcp6: clkvcp6@23500b4 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -373,7 +370,7 @@ clocks {
                domain-id = <25>;
        };
 
-       clkvcp7: clkvcp7 {
+       clkvcp7: clkvcp7@23500b8 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -383,7 +380,7 @@ clocks {
                domain-id = <25>;
        };
 
-       clkbcp: clkbcp {
+       clkbcp: clkbcp@23500bc {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -393,7 +390,7 @@ clocks {
                domain-id = <26>;
        };
 
-       clkdxb: clkdxb {
+       clkdxb: clkdxb@23500c0 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -403,7 +400,7 @@ clocks {
                domain-id = <27>;
        };
 
-       clkhyperlink1: clkhyperlink1 {
+       clkhyperlink1: clkhyperlink1@23500c4 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk12>;
@@ -413,7 +410,7 @@ clocks {
                domain-id = <28>;
        };
 
-       clkxge: clkxge {
+       clkxge: clkxge@23500c8 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;

diff --git a/arch/arm/dts/keystone-k2hk-evm.dts b/arch/arm/dts/keystone-k2hk-evm.dts
index acfcaff..ea53f3f 100644 (file)
--- a/arch/arm/dts/keystone-k2hk-evm.dts
+++ b/arch/arm/dts/keystone-k2hk-evm.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2013-2014 Texas Instruments, Inc.
- *
  * Keystone 2 Kepler/Hawking EVM device tree
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 /dts-v1/;
 
@@ -57,22 +54,22 @@
 
        leds {
                compatible = "gpio-leds";
-               debug1_1 {
+               led-debug-1-1 {
                        label = "keystone:green:debug1";
                        gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */
                };
 
-               debug1_2 {
+               led-debug-1-2 {
                        label = "keystone:red:debug1";
                        gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */
                };
 
-               debug2 {
+               led-debug-2 {
                        label = "keystone:blue:debug2";
                        gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */
                };
 
-               debug3 {
+               led-debug-3 {
                        label = "keystone:blue:debug3";
                        gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */
                };
@@ -148,7 +145,7 @@
 
 &spi0 {
        status = "okay";
-       nor_flash: n25q128a11@0 {
+       nor_flash: flash@0 {
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "Micron,n25q128a11", "jedec,spi-nor";

diff --git a/arch/arm/dts/keystone-k2hk-netcp.dtsi b/arch/arm/dts/keystone-k2hk-netcp.dtsi
index 77a32c3..580af63 100644 (file)
--- a/arch/arm/dts/keystone-k2hk-netcp.dtsi
+++ b/arch/arm/dts/keystone-k2hk-netcp.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Device Tree Source for Keystone 2 Hawking Netcp driver
  *
- * Copyright 2015 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 qmss: qmss@2a40000 {
@@ -15,9 +12,9 @@ qmss: qmss@2a40000 {
        #size-cells = <1>;
        clocks = <&chipclk13>;
        ranges;
-       queue-range     = <0 0x4000>;
-       linkram0        = <0x100000 0x8000>;
-       linkram1        = <0x0 0x10000>;
+       queue-range = <0 0x4000>;
+       linkram0 = <0x100000 0x8000>;
+       linkram1 = <0x0 0x10000>;
 
        qmgrs {
                #address-cells = <1>;
@@ -47,6 +44,7 @@ qmss: qmss@2a40000 {
                                    "region", "push", "pop";
                };
        };
+
        queue-pools {
                qpend {
                        qpend-0 {
@@ -89,6 +87,7 @@ qmss: qmss@2a40000 {
                        };
                };
        };
+
        descriptor-regions {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -129,7 +128,7 @@ netcp: netcp@2000000 {
        #size-cells = <1>;
 
        /* NetCP address range */
-       ranges  = <0 0x2000000 0x100000>;
+       ranges = <0 0x2000000 0x100000>;
 
        clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
        dma-coherent;
@@ -169,11 +168,11 @@ netcp: netcp@2000000 {
                        secondary-slave-ports {
                                port-2 {
                                        slave-port = <2>;
-                                       link-interface  = <2>;
+                                       link-interface = <2>;
                                };
                                port-3 {
                                        slave-port = <3>;
-                                       link-interface  = <2>;
+                                       link-interface = <2>;
                                };
                        };
                };

diff --git a/arch/arm/dts/keystone-k2hk.dtsi b/arch/arm/dts/keystone-k2hk.dtsi
index fc78696..ef02f23 100644 (file)
--- a/arch/arm/dts/keystone-k2hk.dtsi
+++ b/arch/arm/dts/keystone-k2hk.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2013-2014 Texas Instruments, Inc.
- *
  * Keystone 2 Kepler/Hawking soc specific device tree
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 / {

diff --git a/arch/arm/dts/keystone-k2l-clocks.dtsi b/arch/arm/dts/keystone-k2l-clocks.dtsi
index ef8464b..6355280 100644 (file)
--- a/arch/arm/dts/keystone-k2l-clocks.dtsi
+++ b/arch/arm/dts/keystone-k2l-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2013-2014 Texas Instruments, Inc.
- *
  * Keystone 2 lamarr SoC clock nodes
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 clocks {
@@ -44,7 +41,7 @@ clocks {
                reg-names = "control";
        };
 
-       clkdfeiqnsys: clkdfeiqnsys {
+       clkdfeiqnsys: clkdfeiqnsys@2350004 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk12>;
@@ -54,7 +51,7 @@ clocks {
                domain-id = <0>;
        };
 
-       clkpcie1: clkpcie1 {
+       clkpcie1: clkpcie1@235002c {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk12>;
@@ -64,7 +61,7 @@ clocks {
                domain-id = <4>;
        };
 
-       clkgem1: clkgem1 {
+       clkgem1: clkgem1@2350040 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk1>;
@@ -74,7 +71,7 @@ clocks {
                domain-id = <9>;
        };
 
-       clkgem2: clkgem2 {
+       clkgem2: clkgem2@2350044 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk1>;
@@ -84,7 +81,7 @@ clocks {
                domain-id = <10>;
        };
 
-       clkgem3: clkgem3 {
+       clkgem3: clkgem3@2350048 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk1>;
@@ -94,7 +91,7 @@ clocks {
                domain-id = <11>;
        };
 
-       clktac: clktac {
+       clktac: clktac@2350064 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -104,7 +101,7 @@ clocks {
                domain-id = <17>;
        };
 
-       clkrac: clkrac {
+       clkrac: clkrac@2350068 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -114,7 +111,7 @@ clocks {
                domain-id = <17>;
        };
 
-       clkdfepd0: clkdfepd0 {
+       clkdfepd0: clkdfepd0@235006c {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -124,7 +121,7 @@ clocks {
                domain-id = <18>;
        };
 
-       clkfftc0: clkfftc0 {
+       clkfftc0: clkfftc0@2350070 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -134,7 +131,7 @@ clocks {
                domain-id = <19>;
        };
 
-       clkosr: clkosr {
+       clkosr: clkosr@2350088 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -144,7 +141,7 @@ clocks {
                domain-id = <21>;
        };
 
-       clktcp3d0: clktcp3d0 {
+       clktcp3d0: clktcp3d0@235008c {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -154,7 +151,7 @@ clocks {
                domain-id = <22>;
        };
 
-       clktcp3d1: clktcp3d1 {
+       clktcp3d1: clktcp3d1@2350094 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -164,7 +161,7 @@ clocks {
                domain-id = <23>;
        };
 
-       clkvcp0: clkvcp0 {
+       clkvcp0: clkvcp0@235009c {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -174,7 +171,7 @@ clocks {
                domain-id = <24>;
        };
 
-       clkvcp1: clkvcp1 {
+       clkvcp1: clkvcp1@23500a0 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -184,7 +181,7 @@ clocks {
                domain-id = <24>;
        };
 
-       clkvcp2: clkvcp2 {
+       clkvcp2: clkvcp2@23500a4 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -194,7 +191,7 @@ clocks {
                domain-id = <24>;
        };
 
-       clkvcp3: clkvcp3 {
+       clkvcp3: clkvcp3@23500a8 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -204,7 +201,7 @@ clocks {
                domain-id = <24>;
        };
 
-       clkbcp: clkbcp {
+       clkbcp: clkbcp@23500bc {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -214,7 +211,7 @@ clocks {
                domain-id = <26>;
        };
 
-       clkdfepd1: clkdfepd1 {
+       clkdfepd1: clkdfepd1@23500c0 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -224,7 +221,7 @@ clocks {
                domain-id = <27>;
        };
 
-       clkfftc1: clkfftc1 {
+       clkfftc1: clkfftc1@23500c4 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -234,7 +231,7 @@ clocks {
                domain-id = <28>;
        };
 
-       clkiqnail: clkiqnail {
+       clkiqnail: clkiqnail@23500c8 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&chipclk13>;
@@ -244,7 +241,7 @@ clocks {
                domain-id = <29>;
        };
 
-       clkuart2: clkuart2 {
+       clkuart2: clkuart2@2350000 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&clkmodrst0>;
@@ -254,7 +251,7 @@ clocks {
                domain-id = <0>;
        };
 
-       clkuart3: clkuart3 {
+       clkuart3: clkuart3@2350000 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
                clocks = <&clkmodrst0>;

diff --git a/arch/arm/dts/keystone-k2l-evm.dts b/arch/arm/dts/keystone-k2l-evm.dts
index ca049ba..187f2ca 100644 (file)
--- a/arch/arm/dts/keystone-k2l-evm.dts
+++ b/arch/arm/dts/keystone-k2l-evm.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2014 Texas Instruments, Inc.
- *
  * Keystone 2 Lamarr EVM device tree
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 /dts-v1/;
 
@@ -97,7 +94,7 @@
 
 &spi0 {
        status ="okay";
-       nor_flash: n25q128a11@0 {
+       nor_flash: flash@0 {
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "Micron,n25q128a11", "jedec,spi-nor";

diff --git a/arch/arm/dts/keystone-k2l-netcp.dtsi b/arch/arm/dts/keystone-k2l-netcp.dtsi
index 6b95284..54c1128 100644 (file)
--- a/arch/arm/dts/keystone-k2l-netcp.dtsi
+++ b/arch/arm/dts/keystone-k2l-netcp.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Device Tree Source for Keystone 2 Lamarr Netcp driver
  *
- * Copyright 2015 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 qmss: qmss@2a40000 {
@@ -15,9 +12,9 @@ qmss: qmss@2a40000 {
        #size-cells = <1>;
        clocks = <&chipclk13>;
        ranges;
-       queue-range     = <0 0x2000>;
-       linkram0        = <0x100000 0x4000>;
-       linkram1        = <0x70000000 0x10000>; /* 1MB OSR mem */
+       queue-range = <0 0x2000>;
+       linkram0 = <0x100000 0x4000>;
+       linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
 
        qmgrs {
                #address-cells = <1>;
@@ -73,6 +70,7 @@ qmss: qmss@2a40000 {
                        };
                };
        };
+
        descriptor-regions {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -137,24 +135,24 @@ netcp: netcp@26000000 {
                        interfaces {
                                gbe0: interface-0 {
                                        slave-port = <0>;
-                                       link-interface  = <1>;
-                                       phy-handle      = <&ethphy0>;
+                                       link-interface = <1>;
+                                       phy-handle = <&ethphy0>;
                                };
                                gbe1: interface-1 {
                                        slave-port = <1>;
-                                       link-interface  = <1>;
-                                       phy-handle      = <&ethphy1>;
+                                       link-interface = <1>;
+                                       phy-handle = <&ethphy1>;
                                };
                        };
 
                        secondary-slave-ports {
                                port-2 {
                                        slave-port = <2>;
-                                       link-interface  = <2>;
+                                       link-interface = <2>;
                                };
                                port-3 {
                                        slave-port = <3>;
-                                       link-interface  = <2>;
+                                       link-interface = <2>;
                                };
                        };
                };

diff --git a/arch/arm/dts/keystone-k2l.dtsi b/arch/arm/dts/keystone-k2l.dtsi
index d681cab..dcc83a7 100644 (file)
--- a/arch/arm/dts/keystone-k2l.dtsi
+++ b/arch/arm/dts/keystone-k2l.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2014 Texas Instruments, Inc.
- *
  * Keystone 2 Lamarr SoC specific device tree
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 / {
@@ -31,23 +28,23 @@
        soc {
                /include/ "keystone-k2l-clocks.dtsi"
 
-               uart2: serial@02348400 {
+               uart2: serial@2348400 {
                        compatible = "ns16550a";
                        current-speed = <115200>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
                        reg = <0x02348400 0x100>;
-                       clocks  = <&clkuart2>;
+                       clocks = <&clkuart2>;
                        interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>;
                };
 
-               uart3:  serial@02348800 {
+               uart3:  serial@2348800 {
                        compatible = "ns16550a";
                        current-speed = <115200>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
                        reg = <0x02348800 0x100>;
-                       clocks  = <&clkuart3>;
+                       clocks = <&clkuart3>;
                        interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
                };
 
@@ -80,14 +77,14 @@
                };
 
                mdio: mdio@26200f00 {
-                       compatible      = "ti,keystone_mdio", "ti,davinci_mdio";
+                       compatible = "ti,keystone_mdio", "ti,davinci_mdio";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <0x26200f00 0x100>;
                        status = "disabled";
                        clocks = <&clkcpgmac>;
                        clock-names = "fck";
-                       bus_freq        = <2500000>;
+                       bus_freq = <2500000>;
                };
                /include/ "keystone-k2l-netcp.dtsi"
        };

diff --git a/arch/arm/dts/keystone.dtsi b/arch/arm/dts/keystone.dtsi
index 9a2e1f6..2afcab7 100644 (file)
--- a/arch/arm/dts/keystone.dtsi
+++ b/arch/arm/dts/keystone.dtsi
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -94,23 +91,23 @@
 
                /include/ "keystone-clocks.dtsi"
 
-               uart0: serial@02530c00 {
+               uart0: serial@2530c00 {
                        compatible = "ns16550a";
                        current-speed = <115200>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
                        reg = <0x02530c00 0x100>;
-                       clocks  = <&clkuart0>;
+                       clocks = <&clkuart0>;
                        interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
                };
 
-               uart1:  serial@02531000 {
+               uart1:  serial@2531000 {
                        compatible = "ns16550a";
                        current-speed = <115200>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
                        reg = <0x02531000 0x100>;
-                       clocks  = <&clkuart1>;
+                       clocks = <&clkuart1>;
                        interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
                };
 
@@ -198,7 +195,7 @@
                        dma-ranges;
                        status = "disabled";
 
-                       dwc3@2690000 {
+                       usb@2690000 {
                                compatible = "synopsys,dwc3";
                                reg = <0x2690000 0x70000>;
                                interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
@@ -206,7 +203,7 @@
                        };
                };
 
-               wdt: wdt@022f0080 {
+               wdt: wdt@22f0080 {
                        compatible = "ti,keystone-wdt","ti,davinci-wdt";
                        reg = <0x022f0080 0x80>;
                        clocks = <&clkwdtimer0>;
@@ -290,7 +287,7 @@
                        clock-names = "pcie";
                        #address-cells = <3>;
                        #size-cells = <2>;
-                       reg =  <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
+                       reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
                        ranges = <0x81000000 0 0 0x23250000 0 0x4000
                                0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
 

diff --git a/arch/arm/dts/meson-g12b-a311d-bananapi-m2s.dts b/arch/arm/dts/meson-g12b-a311d-bananapi-m2s.dts
new file mode 100644 (file)
index 0000000..3136531
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-a311d-bananapi-m2s.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-a311d.dtsi"
+#include "meson-g12b-bananapi.dtsi"
+
+/ {
+       compatible = "bananapi,bpi-m2s", "amlogic,a311d", "amlogic,g12b";
+       model = "BananaPi M2S";
+
+       aliases {
+               i2c0 = &i2c1;
+               i2c1 = &i2c3;
+       };
+};
+
+/* Camera (CSI) bus */
+&i2c1 {
+       status = "okay";
+       pinctrl-0 = <&i2c1_sda_h6_pins>, <&i2c1_sck_h7_pins>;
+       pinctrl-names = "default";
+};
+
+/* Display (DSI) bus */
+&i2c3 {
+       status = "okay";
+       pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+       pinctrl-names = "default";
+};

diff --git a/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io-u-boot.dtsi b/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io-u-boot.dtsi
new file mode 100644 (file)
index 0000000..a60ba27
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
+ */
+
+#include "meson-g12-common-u-boot.dtsi"

diff --git a/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts b/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts
new file mode 100644 (file)
index 0000000..1b0c388
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-bananapi-cm4.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+       compatible = "bananapi,bpi-cm4io", "bananapi,bpi-cm4", "amlogic,a311d", "amlogic,g12b";
+       model = "BananaPi BPI-CM4IO Baseboard with BPI-CM4 Module";
+
+       aliases {
+               ethernet0 = &ethmac;
+               i2c0 = &i2c1;
+               i2c1 = &i2c3;
+       };
+
+       adc-keys {
+               compatible = "adc-keys";
+               io-channels = <&saradc 2>;
+               io-channel-names = "buttons";
+               keyup-threshold-microvolt = <1710000>;
+
+               button-function {
+                       label = "Function";
+                       linux,code = <KEY_FN>;
+                       press-threshold-microvolt = <10000>;
+               };
+       };
+
+       hdmi_connector: hdmi-connector {
+               compatible = "hdmi-connector";
+               type = "a";
+
+               port {
+                       hdmi_connector_in: endpoint {
+                               remote-endpoint = <&hdmi_tx_tmds_out>;
+                       };
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               led-blue {
+                       color = <LED_COLOR_ID_BLUE>;
+                       function = LED_FUNCTION_STATUS;
+                       gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "heartbeat";
+               };
+
+               led-green {
+                       color = <LED_COLOR_ID_GREEN>;
+                       function = LED_FUNCTION_STATUS;
+                       gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+               };
+       };
+
+       sound {
+               compatible = "amlogic,axg-sound-card";
+               model = "BPI-CM4IO";
+               audio-aux-devs = <&tdmout_b>;
+               audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+                               "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+                               "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+                               "TDM_B Playback", "TDMOUT_B OUT";
+
+               assigned-clocks = <&clkc CLKID_MPLL2>,
+                                 <&clkc CLKID_MPLL0>,
+                                 <&clkc CLKID_MPLL1>;
+               assigned-clock-parents = <0>, <0>, <0>;
+               assigned-clock-rates = <294912000>,
+                                      <270950400>,
+                                      <393216000>;
+
+               dai-link-0 {
+                       sound-dai = <&frddr_a>;
+               };
+
+               dai-link-1 {
+                       sound-dai = <&frddr_b>;
+               };
+
+               dai-link-2 {
+                       sound-dai = <&frddr_c>;
+               };
+
+               /* 8ch hdmi interface */
+               dai-link-3 {
+                       sound-dai = <&tdmif_b>;
+                       dai-format = "i2s";
+                       dai-tdm-slot-tx-mask-0 = <1 1>;
+                       dai-tdm-slot-tx-mask-1 = <1 1>;
+                       dai-tdm-slot-tx-mask-2 = <1 1>;
+                       dai-tdm-slot-tx-mask-3 = <1 1>;
+                       mclk-fs = <256>;
+
+                       codec {
+                               sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+                       };
+               };
+
+               /* hdmi glue */
+               dai-link-4 {
+                       sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+                       codec {
+                               sound-dai = <&hdmi_tx>;
+                       };
+               };
+       };
+};
+
+&cecb_AO {
+       status = "okay";
+};
+
+&ethmac {
+       status = "okay";
+};
+
+&hdmi_tx {
+       status = "okay";
+};
+
+&hdmi_tx_tmds_port {
+       hdmi_tx_tmds_out: endpoint {
+               remote-endpoint = <&hdmi_connector_in>;
+       };
+};
+
+/* CSI port */
+&i2c1 {
+       status = "okay";
+};
+
+/* DSI port for touchscreen */
+&i2c3 {
+       status = "okay";
+};
+
+/* miniPCIe port with USB + SIM slot */
+&pcie {
+       status = "okay";
+};
+
+&sd_emmc_b {
+       status = "okay";
+};
+
+&tohdmitx {
+       status = "okay";
+};
+
+/* Peripheral Only USB-C port */
+&usb {
+       dr_mode = "peripheral";
+
+       status = "okay";
+};

diff --git a/arch/arm/dts/meson-g12b-bananapi-cm4.dtsi b/arch/arm/dts/meson-g12b-bananapi-cm4.dtsi
new file mode 100644 (file)
index 0000000..97e5229
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-bananapi-cm4.dtsi
@@ -0,0 +1,388 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
+ */
+
+#include "meson-g12b-a311d.dtsi"
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+
+/ {
+       aliases {
+               serial0 = &uart_AO;
+               rtc1 = &vrtc;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       emmc_pwrseq: emmc-pwrseq {
+               compatible = "mmc-pwrseq-emmc";
+               reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x40000000>;
+       };
+
+       sdio_pwrseq: sdio-pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               reset-gpios = <&gpio GPIOAO_6 GPIO_ACTIVE_LOW>;
+               clocks = <&wifi32k>;
+               clock-names = "ext_clock";
+       };
+
+       emmc_1v8: regulator-emmc-1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "EMMC_1V8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               vin-supply = <&vddao_3v3>;
+               regulator-always-on;
+       };
+
+       dc_in: regulator-dc-in {
+               compatible = "regulator-fixed";
+               regulator-name = "DC_IN";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-always-on;
+       };
+
+       vddio_c: regulator-vddio-c {
+               compatible = "regulator-gpio";
+               regulator-name = "VDDIO_C";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <3300000>;
+
+               enable-gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>;
+               enable-active-high;
+               regulator-always-on;
+
+               gpios = <&gpio_ao GPIOAO_9 GPIO_OPEN_DRAIN>;
+               gpios-states = <1>;
+
+               states = <1800000 0>,
+                        <3300000 1>;
+       };
+
+       vddao_1v8: regulator-vddao-1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDAO_1V8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               vin-supply = <&vddao_3v3>;
+               regulator-always-on;
+       };
+
+       vddao_3v3: regulator-vddao-3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDAO_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               vin-supply = <&dc_in>;
+               regulator-always-on;
+       };
+
+       vddcpu_a: regulator-vddcpu-a {
+               /*
+                * MP8756GD DC/DC Regulator.
+                */
+               compatible = "pwm-regulator";
+
+               regulator-name = "VDDCPU_A";
+               regulator-min-microvolt = <680000>;
+               regulator-max-microvolt = <1040000>;
+
+               pwm-supply = <&dc_in>;
+
+               pwms = <&pwm_ab 0 1250 0>;
+               pwm-dutycycle-range = <100 0>;
+
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       vddcpu_b: regulator-vddcpu-b {
+               /*
+                * SY8120B1ABC DC/DC Regulator.
+                */
+               compatible = "pwm-regulator";
+
+               regulator-name = "VDDCPU_B";
+               regulator-min-microvolt = <680000>;
+               regulator-max-microvolt = <1040000>;
+
+               pwm-supply = <&dc_in>;
+
+               pwms = <&pwm_AO_cd 1 1250 0>;
+               pwm-dutycycle-range = <100 0>;
+
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       wifi32k: wifi32k {
+               compatible = "pwm-clock";
+               #clock-cells = <0>;
+               clock-frequency = <32768>;
+               pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+       };
+};
+
+&arb {
+       status = "okay";
+};
+
+&clkc_audio {
+       status = "okay";
+};
+
+&cec_AO {
+       pinctrl-0 = <&cec_ao_a_h_pins>;
+       pinctrl-names = "default";
+       hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+       pinctrl-0 = <&cec_ao_b_h_pins>;
+       pinctrl-names = "default";
+       hdmi-phandle = <&hdmi_tx>;
+};
+
+&cpu0 {
+       cpu-supply = <&vddcpu_b>;
+       operating-points-v2 = <&cpu_opp_table_0>;
+       clocks = <&clkc CLKID_CPU_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu1 {
+       cpu-supply = <&vddcpu_b>;
+       operating-points-v2 = <&cpu_opp_table_0>;
+       clocks = <&clkc CLKID_CPU_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu100 {
+       cpu-supply = <&vddcpu_a>;
+       operating-points-v2 = <&cpub_opp_table_1>;
+       clocks = <&clkc CLKID_CPUB_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu101 {
+       cpu-supply = <&vddcpu_a>;
+       operating-points-v2 = <&cpub_opp_table_1>;
+       clocks = <&clkc CLKID_CPUB_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu102 {
+       cpu-supply = <&vddcpu_a>;
+       operating-points-v2 = <&cpub_opp_table_1>;
+       clocks = <&clkc CLKID_CPUB_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu103 {
+       cpu-supply = <&vddcpu_a>;
+       operating-points-v2 = <&cpub_opp_table_1>;
+       clocks = <&clkc CLKID_CPUB_CLK>;
+       clock-latency = <50000>;
+};
+
+&ext_mdio {
+       external_phy: ethernet-phy@0 {
+               /* Realtek RTL8211F (0x001cc916) */
+               reg = <0>;
+               max-speed = <1000>;
+
+               interrupt-parent = <&gpio_intc>;
+               /* MAC_INTR on GPIOZ_14 */
+               interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+       };
+};
+
+/* Ethernet to be enabled in baseboard DT */
+&ethmac {
+       pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
+       pinctrl-names = "default";
+       phy-mode = "rgmii-txid";
+       phy-handle = <&external_phy>;
+};
+
+&frddr_a {
+       status = "okay";
+};
+
+&frddr_b {
+       status = "okay";
+};
+
+&frddr_c {
+       status = "okay";
+};
+
+/* HDMI to be enabled in baseboard DT */
+&hdmi_tx {
+       pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+       pinctrl-names = "default";
+       hdmi-supply = <&dc_in>;
+};
+
+/* "Camera" I2C bus */
+&i2c1 {
+       pinctrl-0 = <&i2c1_sda_h6_pins>, <&i2c1_sck_h7_pins>;
+       pinctrl-names = "default";
+};
+
+/* Main I2C bus */
+&i2c2 {
+       pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>;
+       pinctrl-names = "default";
+};
+
+/* "ID" I2C bus */
+&i2c3 {
+       pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+       pinctrl-names = "default";
+};
+
+&pcie {
+       reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>;
+};
+
+&pwm_ab {
+       pinctrl-0 = <&pwm_a_e_pins>;
+       pinctrl-names = "default";
+       clocks = <&xtal>;
+       clock-names = "clkin0";
+
+       status = "okay";
+};
+
+&pwm_ef {
+       pinctrl-0 = <&pwm_e_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+
+&pwm_AO_cd {
+       pinctrl-0 = <&pwm_ao_d_e_pins>;
+       pinctrl-names = "default";
+       clocks = <&xtal>;
+       clock-names = "clkin1";
+
+       status = "okay";
+};
+
+&saradc {
+       vref-supply = <&vddao_1v8>;
+
+       status = "okay";
+};
+
+/* on-module SDIO WiFi */
+&sd_emmc_a {
+       pinctrl-0 = <&sdio_pins>;
+       pinctrl-1 = <&sdio_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       bus-width = <4>;
+       sd-uhs-sdr104;
+       max-frequency = <50000000>;
+
+       non-removable;
+       disable-wp;
+
+       /* WiFi firmware requires power in suspend */
+       keep-power-in-suspend;
+
+       mmc-pwrseq = <&sdio_pwrseq>;
+
+       vmmc-supply = <&vddao_3v3>;
+       vqmmc-supply = <&vddao_3v3>;
+
+       status = "okay";
+
+       rtl8822cs: wifi@1 {
+               reg = <1>;
+       };
+};
+
+/* SD card to be enabled in baseboard DT */
+&sd_emmc_b {
+       pinctrl-0 = <&sdcard_c_pins>;
+       pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+       pinctrl-names = "default", "clk-gate";
+
+       bus-width = <4>;
+       cap-sd-highspeed;
+       max-frequency = <50000000>;
+       disable-wp;
+
+       cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+       vmmc-supply = <&vddao_3v3>;
+       vqmmc-supply = <&vddio_c>;
+};
+
+/* on-module eMMC */
+&sd_emmc_c {
+       pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+       pinctrl-1 = <&emmc_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
+
+       bus-width = <8>;
+       cap-mmc-highspeed;
+       mmc-ddr-1_8v;
+       mmc-hs200-1_8v;
+       max-frequency = <200000000>;
+       disable-wp;
+
+       mmc-pwrseq = <&emmc_pwrseq>;
+       vmmc-supply = <&vddao_3v3>;
+       vqmmc-supply = <&vddao_1v8>;
+
+       status = "okay";
+};
+
+&tdmif_b {
+       status = "okay";
+};
+
+&tdmout_b {
+       status = "okay";
+};
+
+/* on-module UART BT */
+&uart_A {
+       pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+       pinctrl-names = "default";
+       uart-has-rtscts;
+
+       status = "okay";
+
+       bluetooth {
+               compatible = "realtek,rtl8822cs-bt";
+               enable-gpios  = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+               host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
+               device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
+       };
+};
+
+&uart_AO {
+       pinctrl-0 = <&uart_ao_a_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+
+&usb {
+       phys = <&usb2_phy0>, <&usb2_phy1>;
+       phy-names = "usb2-phy0", "usb2-phy1";
+};

diff --git a/arch/arm/dts/meson-g12b-bananapi-u-boot.dtsi b/arch/arm/dts/meson-g12b-bananapi-u-boot.dtsi
new file mode 100644 (file)
index 0000000..236f246
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-bananapi-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-g12-common-u-boot.dtsi"

diff --git a/arch/arm/dts/meson-g12b-bananapi.dtsi b/arch/arm/dts/meson-g12b-bananapi.dtsi
new file mode 100644 (file)
index 0000000..8370978
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-bananapi.dtsi
@@ -0,0 +1,521 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2023 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+       aliases {
+               serial0 = &uart_AO;
+               ethernet0 = &ethmac;
+               rtc1 = &vrtc;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 4 GiB */
+       };
+
+       adc-keys {
+               compatible = "adc-keys";
+               io-channels = <&saradc 2>;
+               io-channel-names = "buttons";
+               keyup-threshold-microvolt = <1710000>;
+
+               button-function {
+                       label = "RST";
+                       linux,code = <KEY_POWER>;
+                       press-threshold-microvolt = <10000>;
+               };
+       };
+
+       emmc_pwrseq: emmc-pwrseq {
+               compatible = "mmc-pwrseq-emmc";
+               reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+       };
+
+       fan0: pwm-fan {
+               compatible = "pwm-fan";
+               #cooling-cells = <2>;
+               cooling-min-state = <0>;
+               cooling-max-state = <3>;
+               cooling-levels = <0 120 170 220>;
+               pwms = <&pwm_cd 1 40000 0>;
+       };
+
+       hdmi-connector {
+               compatible = "hdmi-connector";
+               type = "a";
+
+               port {
+                       hdmi_connector_in: endpoint {
+                               remote-endpoint = <&hdmi_tx_tmds_out>;
+                       };
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               led-0 {
+                       color = <LED_COLOR_ID_BLUE>;
+                       function = LED_FUNCTION_STATUS;
+                       gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>;
+                       linux,default-trigger = "heartbeat";
+               };
+
+               led-1 {
+                       color = <LED_COLOR_ID_GREEN>;
+                       function = LED_FUNCTION_STATUS;
+                       gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+               };
+       };
+
+       sdio_pwrseq: sdio-pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+               clocks = <&wifi32k>;
+               clock-names = "ext_clock";
+       };
+
+       wifi32k: wifi32k {
+               compatible = "pwm-clock";
+               #clock-cells = <0>;
+               clock-frequency = <32768>;
+               pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+       };
+
+       dc_in: regulator-dc-in {
+               compatible = "regulator-fixed";
+               regulator-name = "DC_IN";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-always-on;
+       };
+
+       vcc_5v: regulator-vcc-5v {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC_5V";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               vin-supply = <&dc_in>;
+
+               gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+               enable-active-high;
+       };
+
+       vcc_3v3: regulator-vcc-3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               vin-supply = <&vsys_3v3>;
+               regulator-always-on;
+       };
+
+       vcc_1v8: regulator-vcc-1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC_1V8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               vin-supply = <&vcc_3v3>;
+               regulator-always-on;
+       };
+
+       vddao_1v8: regulator-vddao-1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDIO_AO1V8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               vin-supply = <&vsys_3v3>;
+               regulator-always-on;
+       };
+
+       vddcpu_a: regulator-vddcpu-a {
+               compatible = "pwm-regulator";
+               regulator-name = "VDDCPU_A";
+               regulator-min-microvolt = <690000>;
+               regulator-max-microvolt = <1050000>;
+               pwm-supply = <&dc_in>;
+               pwms = <&pwm_ab 0 1250 0>;
+               pwm-dutycycle-range = <100 0>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       vddcpu_b: regulator-vddcpu-b {
+               compatible = "pwm-regulator";
+               regulator-name = "VDDCPU_B";
+               regulator-min-microvolt = <690000>;
+               regulator-max-microvolt = <1050000>;
+               pwm-supply = <&vsys_3v3>;
+               pwms = <&pwm_AO_cd 1 1250 0>;
+               pwm-dutycycle-range = <100 0>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       vsys_3v3: regulator-vsys-3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "VSYS_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               vin-supply = <&dc_in>;
+               regulator-always-on;
+       };
+
+       emmc_1v8: regulator-emmc-1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "EMMC_AO1V8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               vin-supply = <&vcc_3v3>;
+               regulator-always-on;
+       };
+
+       usb_pwr: regulator-usb-pwr {
+               compatible = "regulator-fixed";
+               regulator-name = "USB_PWR";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               vin-supply = <&vcc_5v>;
+
+               gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       sound {
+               compatible = "amlogic,axg-sound-card";
+               model = "BPI-M2S";
+               audio-aux-devs = <&tdmout_b>;
+               audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+                               "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+                               "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+                               "TDM_B Playback", "TDMOUT_B OUT";
+
+               assigned-clocks = <&clkc CLKID_MPLL2>,
+                                 <&clkc CLKID_MPLL0>,
+                                 <&clkc CLKID_MPLL1>;
+               assigned-clock-parents = <0>, <0>, <0>;
+               assigned-clock-rates = <294912000>,
+                                      <270950400>,
+                                      <393216000>;
+
+               dai-link-0 {
+                       sound-dai = <&frddr_a>;
+               };
+
+               dai-link-1 {
+                       sound-dai = <&frddr_b>;
+               };
+
+               dai-link-2 {
+                       sound-dai = <&frddr_c>;
+               };
+
+               /* 8ch hdmi interface */
+               dai-link-3 {
+                       sound-dai = <&tdmif_b>;
+                       dai-format = "i2s";
+                       dai-tdm-slot-tx-mask-0 = <1 1>;
+                       dai-tdm-slot-tx-mask-1 = <1 1>;
+                       dai-tdm-slot-tx-mask-2 = <1 1>;
+                       dai-tdm-slot-tx-mask-3 = <1 1>;
+                       mclk-fs = <256>;
+
+                       codec {
+                               sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+                       };
+               };
+
+               /* hdmi glue */
+               dai-link-4 {
+                       sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+                       codec {
+                               sound-dai = <&hdmi_tx>;
+                       };
+               };
+       };
+};
+
+&arb {
+       status = "okay";
+};
+
+&clkc_audio {
+       status = "okay";
+};
+
+&cecb_AO {
+       pinctrl-0 = <&cec_ao_b_h_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+       hdmi-phandle = <&hdmi_tx>;
+};
+
+&cpu0 {
+       cpu-supply = <&vddcpu_b>;
+       operating-points-v2 = <&cpu_opp_table_0>;
+       clocks = <&clkc CLKID_CPU_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu1 {
+       cpu-supply = <&vddcpu_b>;
+       operating-points-v2 = <&cpu_opp_table_0>;
+       clocks = <&clkc CLKID_CPU_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu100 {
+       cpu-supply = <&vddcpu_a>;
+       operating-points-v2 = <&cpub_opp_table_1>;
+       clocks = <&clkc CLKID_CPUB_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu101 {
+       cpu-supply = <&vddcpu_a>;
+       operating-points-v2 = <&cpub_opp_table_1>;
+       clocks = <&clkc CLKID_CPUB_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu102 {
+       cpu-supply = <&vddcpu_a>;
+       operating-points-v2 = <&cpub_opp_table_1>;
+       clocks = <&clkc CLKID_CPUB_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu103 {
+       cpu-supply = <&vddcpu_a>;
+       operating-points-v2 = <&cpub_opp_table_1>;
+       clocks = <&clkc CLKID_CPUB_CLK>;
+       clock-latency = <50000>;
+};
+
+&ethmac {
+       pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+       phy-mode = "rgmii";
+       phy-handle = <&external_phy>;
+       amlogic,tx-delay-ns = <2>;
+};
+
+&ext_mdio {
+       external_phy: ethernet-phy@0 {
+               /* Realtek RTL8211F (0x001cc916) */
+               reg = <0>;
+               max-speed = <1000>;
+
+               reset-assert-us = <10000>;
+               reset-deassert-us = <80000>;
+               reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+               interrupt-parent = <&gpio_intc>;
+               /* MAC_INTR on GPIOZ_14 */
+               interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+       };
+};
+
+&frddr_a {
+       status = "okay";
+};
+
+&frddr_b {
+       status = "okay";
+};
+
+&frddr_c {
+       status = "okay";
+};
+
+&hdmi_tx {
+       status = "okay";
+       pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+       pinctrl-names = "default";
+       hdmi-supply = <&vcc_5v>;
+};
+
+&hdmi_tx_tmds_port {
+       hdmi_tx_tmds_out: endpoint {
+               remote-endpoint = <&hdmi_connector_in>;
+       };
+};
+
+/* Main i2c bus */
+&i2c2 {
+       status = "okay";
+       pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>;
+       pinctrl-names = "default";
+};
+
+&pcie {
+       status = "okay";
+       reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>;
+};
+
+&pwm_ab {
+       status = "okay";
+       pinctrl-0 = <&pwm_a_e_pins>;
+       pinctrl-names = "default";
+       clocks = <&xtal>;
+       clock-names = "clkin0";
+};
+
+&pwm_cd {
+       status = "okay";
+       pinctrl-0 = <&pwm_d_x6_pins>;
+       pinctrl-names = "default";
+       pwm-gpios = <&gpio GPIOAO_10 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+       status = "okay";
+       pinctrl-0 = <&pwm_e_pins>;
+       pinctrl-names = "default";
+};
+
+&pwm_AO_cd {
+       pinctrl-0 = <&pwm_ao_d_e_pins>;
+       pinctrl-names = "default";
+       clocks = <&xtal>;
+       clock-names = "clkin1";
+       status = "okay";
+};
+
+&saradc {
+       status = "okay";
+       vref-supply = <&vddao_1v8>;
+};
+
+/* SDIO */
+&sd_emmc_a {
+       /* enable if WiFi/BT board connected */
+       status = "disabled";
+       pinctrl-0 = <&sdio_pins>;
+       pinctrl-1 = <&sdio_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       bus-width = <4>;
+       sd-uhs-sdr104;
+       max-frequency = <50000000>;
+
+       non-removable;
+       disable-wp;
+
+       /* WiFi firmware requires power in suspend */
+       keep-power-in-suspend;
+
+       mmc-pwrseq = <&sdio_pwrseq>;
+
+       vmmc-supply = <&vsys_3v3>;
+       vqmmc-supply = <&vddao_1v8>;
+
+       rtl8822cs: wifi@1 {
+               reg = <1>;
+       };
+};
+
+/* SD card */
+&sd_emmc_b {
+       status = "okay";
+       pinctrl-0 = <&sdcard_c_pins>;
+       pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+       pinctrl-names = "default", "clk-gate";
+
+       bus-width = <4>;
+       cap-sd-highspeed;
+       max-frequency = <50000000>;
+       disable-wp;
+
+       cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+       vmmc-supply = <&vsys_3v3>;
+       vqmmc-supply = <&vsys_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+       status = "okay";
+       pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+       pinctrl-1 = <&emmc_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
+
+       bus-width = <8>;
+       cap-mmc-highspeed;
+       mmc-ddr-1_8v;
+       mmc-hs200-1_8v;
+       max-frequency = <200000000>;
+       disable-wp;
+
+       mmc-pwrseq = <&emmc_pwrseq>;
+       vmmc-supply = <&vcc_3v3>;
+       vqmmc-supply = <&emmc_1v8>;
+};
+
+&tdmif_b {
+       status = "okay";
+};
+
+&tdmout_b {
+       status = "okay";
+};
+
+&tohdmitx {
+       status = "okay";
+};
+
+&uart_A {
+       /* enable if WiFi/BT board connected */
+       status = "disabled";
+       pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+       pinctrl-names = "default";
+       uart-has-rtscts;
+
+       bluetooth {
+               compatible = "realtek,rtl8822cs-bt";
+               enable-gpios  = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+               host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
+               device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
+       };
+};
+
+&uart_AO {
+       status = "okay";
+       pinctrl-0 = <&uart_ao_a_pins>;
+       pinctrl-names = "default";
+};
+
+&usb2_phy0 {
+       phy-supply = <&dc_in>;
+};
+
+&usb2_phy1 {
+       phy-supply = <&usb_pwr>;
+};
+
+&usb3_pcie_phy {
+       phy-supply = <&usb_pwr>;
+};
+
+&usb {
+       status = "okay";
+       dr_mode = "peripheral";
+       phys = <&usb2_phy0>, <&usb2_phy1>;
+       phy-names = "usb2-phy0", "usb2-phy1";
+};

diff --git a/arch/arm/dts/meson-g12b-radxa-zero2-u-boot.dtsi b/arch/arm/dts/meson-g12b-radxa-zero2-u-boot.dtsi
new file mode 100644 (file)
index 0000000..236f246
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-radxa-zero2-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-g12-common-u-boot.dtsi"

diff --git a/arch/arm/dts/meson-g12b-radxa-zero2.dts b/arch/arm/dts/meson-g12b-radxa-zero2.dts
new file mode 100644 (file)
index 0000000..890f5bf
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-radxa-zero2.dts
@@ -0,0 +1,489 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2022 Radxa Limited
+ * Author: Yuntian Zhang <yt@radxa.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-a311d.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+       compatible = "radxa,zero2", "amlogic,a311d", "amlogic,g12b";
+       model = "Radxa Zero2";
+
+       aliases {
+               serial0 = &uart_AO;
+               serial2 = &uart_A;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x80000000>;
+       };
+
+       gpio-keys-polled {
+               compatible = "gpio-keys-polled";
+               poll-interval = <100>;
+               power-button {
+                       label = "power";
+                       linux,code = <KEY_POWER>;
+                       gpios = <&gpio_ao GPIOAO_3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               led-green {
+                       color = <LED_COLOR_ID_GREEN>;
+                       function = LED_FUNCTION_STATUS;
+                       gpios = <&gpio GPIOA_12 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "heartbeat";
+               };
+       };
+
+       hdmi-connector {
+               compatible = "hdmi-connector";
+               type = "a";
+
+               port {
+                       hdmi_connector_in: endpoint {
+                               remote-endpoint = <&hdmi_tx_tmds_out>;
+                       };
+               };
+       };
+
+       emmc_pwrseq: emmc-pwrseq {
+               compatible = "mmc-pwrseq-emmc";
+               reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+       };
+
+       sdio_pwrseq: sdio-pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+               clocks = <&wifi32k>;
+               clock-names = "ext_clock";
+       };
+
+       ao_5v: regulator-ao-5v {
+               compatible = "regulator-fixed";
+               regulator-name = "AO_5V";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-always-on;
+       };
+
+       vcc_1v8: regulator-vcc-1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC_1V8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               vin-supply = <&vcc_3v3>;
+               regulator-always-on;
+       };
+
+       vcc_3v3: regulator-vcc-3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               vin-supply = <&vddao_3v3>;
+               regulator-always-on;
+               /* FIXME: actually controlled by VDDCPU_B_EN */
+       };
+
+       vddao_1v8: regulator-vddao-1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDIO_AO1V8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               vin-supply = <&vddao_3v3>;
+               regulator-always-on;
+       };
+
+       vddao_3v3: regulator-vddao-3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDAO_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               vin-supply = <&ao_5v>;
+               regulator-always-on;
+       };
+
+       vddcpu_a: regulator-vddcpu-a {
+               /*
+                * MP8756GD Regulator.
+                */
+               compatible = "pwm-regulator";
+
+               regulator-name = "VDDCPU_A";
+               regulator-min-microvolt = <730000>;
+               regulator-max-microvolt = <1022000>;
+
+               pwm-supply = <&ao_5v>;
+
+               pwms = <&pwm_ab 0 1250 0>;
+               pwm-dutycycle-range = <100 0>;
+
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       vddcpu_b: regulator-vddcpu-b {
+               /*
+                * Silergy SY8120B1ABC Regulator.
+                */
+               compatible = "pwm-regulator";
+
+               regulator-name = "VDDCPU_B";
+               regulator-min-microvolt = <730000>;
+               regulator-max-microvolt = <1022000>;
+
+               pwm-supply = <&ao_5v>;
+
+               pwms = <&pwm_AO_cd 1 1250 0>;
+               pwm-dutycycle-range = <100 0>;
+
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       sound {
+               compatible = "amlogic,axg-sound-card";
+               model = "RADXA-ZERO2";
+               audio-aux-devs = <&tdmout_b>;
+               audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+                               "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+                               "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+                               "TDM_B Playback", "TDMOUT_B OUT";
+
+               assigned-clocks = <&clkc CLKID_MPLL2>,
+                                 <&clkc CLKID_MPLL0>,
+                                 <&clkc CLKID_MPLL1>;
+               assigned-clock-parents = <0>, <0>, <0>;
+               assigned-clock-rates = <294912000>,
+                                      <270950400>,
+                                      <393216000>;
+
+               dai-link-0 {
+                       sound-dai = <&frddr_a>;
+               };
+
+               dai-link-1 {
+                       sound-dai = <&frddr_b>;
+               };
+
+               dai-link-2 {
+                       sound-dai = <&frddr_c>;
+               };
+
+               /* 8ch hdmi interface */
+               dai-link-3 {
+                       sound-dai = <&tdmif_b>;
+                       dai-format = "i2s";
+                       dai-tdm-slot-tx-mask-0 = <1 1>;
+                       dai-tdm-slot-tx-mask-1 = <1 1>;
+                       dai-tdm-slot-tx-mask-2 = <1 1>;
+                       dai-tdm-slot-tx-mask-3 = <1 1>;
+                       mclk-fs = <256>;
+
+                       codec {
+                               sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+                       };
+               };
+
+               /* hdmi glue */
+               dai-link-4 {
+                       sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+                       codec {
+                               sound-dai = <&hdmi_tx>;
+                       };
+               };
+       };
+
+       wifi32k: clock-0 {
+               compatible = "pwm-clock";
+               #clock-cells = <0>;
+               clock-frequency = <32768>;
+               pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+       };
+};
+
+&arb {
+       status = "okay";
+};
+
+&cec_AO {
+       pinctrl-0 = <&cec_ao_a_h_pins>;
+       pinctrl-names = "default";
+       status = "disabled";
+       hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+       pinctrl-0 = <&cec_ao_b_h_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+       hdmi-phandle = <&hdmi_tx>;
+};
+
+&clkc_audio {
+       status = "okay";
+};
+
+&cpu0 {
+       cpu-supply = <&vddcpu_b>;
+       operating-points-v2 = <&cpu_opp_table_0>;
+       clocks = <&clkc CLKID_CPU_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu1 {
+       cpu-supply = <&vddcpu_b>;
+       operating-points-v2 = <&cpu_opp_table_0>;
+       clocks = <&clkc CLKID_CPU_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu100 {
+       cpu-supply = <&vddcpu_a>;
+       operating-points-v2 = <&cpub_opp_table_1>;
+       clocks = <&clkc CLKID_CPUB_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu101 {
+       cpu-supply = <&vddcpu_a>;
+       operating-points-v2 = <&cpub_opp_table_1>;
+       clocks = <&clkc CLKID_CPUB_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu102 {
+       cpu-supply = <&vddcpu_a>;
+       operating-points-v2 = <&cpub_opp_table_1>;
+       clocks = <&clkc CLKID_CPUB_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu103 {
+       cpu-supply = <&vddcpu_a>;
+       operating-points-v2 = <&cpub_opp_table_1>;
+       clocks = <&clkc CLKID_CPUB_CLK>;
+       clock-latency = <50000>;
+};
+
+&frddr_a {
+       status = "okay";
+};
+
+&frddr_b {
+       status = "okay";
+};
+
+&frddr_c {
+       status = "okay";
+};
+
+&gpio {
+       gpio-line-names =
+               /* GPIOZ */
+               "PIN_27", "PIN_28", "PIN_7", "PIN_11", "PIN_13", "PIN_15", "PIN_18", "PIN_40",
+               "", "", "", "", "", "", "", "",
+               /* GPIOH */
+               "", "", "", "", "PIN_19", "PIN_21", "PIN_24", "PIN_23",
+               "",
+               /* BOOT */
+               "", "", "", "", "", "", "", "",
+               "", "", "", "", "EMMC_PWRSEQ", "", "", "",
+               /* GPIOC */
+               "", "", "", "", "", "", "SD_CD", "PIN_36",
+               /* GPIOA */
+               "PIN_32", "PIN_12", "PIN_35", "", "", "PIN_38", "", "",
+               "", "", "", "", "LED_GREEN", "PIN_31", "PIN_3", "PIN_5",
+               /* GPIOX */
+               "", "", "", "", "", "", "SDIO_PWRSEQ", "",
+               "", "", "", "", "", "", "", "",
+               "", "BT_SHUTDOWN", "", "";
+};
+
+&gpio_ao {
+       gpio-line-names =
+               /* GPIOAO */
+               "PIN_8", "PIN_10", "", "BTN_POWER", "", "", "", "PIN_29",
+               "PIN_33", "PIN_37", "FAN", "",
+               /* GPIOE */
+               "", "", "";
+};
+
+&hdmi_tx {
+       status = "okay";
+       pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+       pinctrl-names = "default";
+       hdmi-supply = <&ao_5v>;
+};
+
+&hdmi_tx_tmds_port {
+       hdmi_tx_tmds_out: endpoint {
+               remote-endpoint = <&hdmi_connector_in>;
+       };
+};
+
+&ir {
+       status = "disabled";
+       pinctrl-0 = <&remote_input_ao_pins>;
+       pinctrl-names = "default";
+};
+
+&pwm_ab {
+       pinctrl-0 = <&pwm_a_e_pins>;
+       pinctrl-names = "default";
+       clocks = <&xtal>;
+       clock-names = "clkin0";
+       status = "okay";
+};
+
+&pwm_ef {
+       pinctrl-0 = <&pwm_e_pins>;
+       pinctrl-names = "default";
+       clocks = <&xtal>;
+       clock-names = "clkin0";
+       status = "okay";
+};
+
+&pwm_AO_ab {
+       pinctrl-0 = <&pwm_ao_a_pins>;
+       pinctrl-names = "default";
+       clocks = <&xtal>;
+       clock-names = "clkin0";
+       status = "okay";
+};
+
+&pwm_AO_cd {
+       pinctrl-0 = <&pwm_ao_d_e_pins>;
+       pinctrl-names = "default";
+       clocks = <&xtal>;
+       clock-names = "clkin1";
+       status = "okay";
+};
+
+&saradc {
+       status = "okay";
+       vref-supply = <&vddao_1v8>;
+};
+
+/* SDIO */
+&sd_emmc_a {
+       status = "okay";
+       pinctrl-0 = <&sdio_pins>;
+       pinctrl-1 = <&sdio_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       bus-width = <4>;
+       cap-sd-highspeed;
+       max-frequency = <100000000>;
+
+       non-removable;
+       disable-wp;
+
+       /* WiFi firmware requires power to be kept while in suspend */
+       keep-power-in-suspend;
+
+       mmc-pwrseq = <&sdio_pwrseq>;
+
+       vmmc-supply = <&vddao_3v3>;
+       vqmmc-supply = <&vddao_1v8>;
+
+       brcmf: wifi@1 {
+               reg = <1>;
+               compatible = "brcm,bcm4329-fmac";
+       };
+};
+
+/* SD card */
+&sd_emmc_b {
+       status = "okay";
+       pinctrl-0 = <&sdcard_c_pins>;
+       pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+       pinctrl-names = "default", "clk-gate";
+
+       bus-width = <4>;
+       cap-sd-highspeed;
+       max-frequency = <50000000>;
+       disable-wp;
+
+       cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+       vmmc-supply = <&vddao_3v3>;
+       vqmmc-supply = <&vddao_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+       status = "okay";
+       pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+       pinctrl-1 = <&emmc_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
+
+       bus-width = <8>;
+       cap-mmc-highspeed;
+       mmc-ddr-1_8v;
+       mmc-hs200-1_8v;
+       max-frequency = <200000000>;
+       disable-wp;
+
+       mmc-pwrseq = <&emmc_pwrseq>;
+       vmmc-supply = <&vcc_3v3>;
+       vqmmc-supply = <&vcc_1v8>;
+};
+
+&tdmif_b {
+       status = "okay";
+};
+
+&tdmout_b {
+       status = "okay";
+};
+
+&tohdmitx {
+       status = "okay";
+};
+
+&uart_A {
+       status = "okay";
+       pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+       pinctrl-names = "default";
+       uart-has-rtscts;
+
+       bluetooth {
+               compatible = "brcm,bcm43438-bt";
+               shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+               max-speed = <2000000>;
+               clocks = <&wifi32k>;
+               clock-names = "lpo";
+       };
+};
+
+&uart_AO {
+       status = "okay";
+       pinctrl-0 = <&uart_ao_a_pins>;
+       pinctrl-names = "default";
+};
+
+&usb {
+       status = "okay";
+};

diff --git a/arch/arm/dts/meson-g12b-s922x-bananapi-m2s.dts b/arch/arm/dts/meson-g12b-s922x-bananapi-m2s.dts
new file mode 100644 (file)
index 0000000..7f66f26
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-s922x-bananapi-m2s.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-s922x.dtsi"
+#include "meson-g12b-bananapi.dtsi"
+
+/ {
+       compatible = "bananapi,bpi-m2s", "amlogic,s922x", "amlogic,g12b";
+       model = "BananaPi M2S";
+};

diff --git a/arch/arm/dts/meson-gxbb-wetek-hub.dts b/arch/arm/dts/meson-gxbb-wetek-hub.dts
new file mode 100644 (file)
index 0000000..5873301
--- /dev/null
+++ b/arch/arm/dts/meson-gxbb-wetek-hub.dts
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb-wetek.dtsi"
+#include <dt-bindings/sound/meson-aiu.h>
+
+/ {
+       compatible = "wetek,hub", "amlogic,meson-gxbb";
+       model = "WeTek Hub";
+
+       sound {
+               compatible = "amlogic,gx-sound-card";
+               model = "WETEK-HUB";
+               assigned-clocks = <&clkc CLKID_MPLL0>,
+                                 <&clkc CLKID_MPLL1>,
+                                 <&clkc CLKID_MPLL2>;
+               assigned-clock-parents = <0>, <0>, <0>;
+               assigned-clock-rates = <294912000>,
+                                      <270950400>,
+                                      <393216000>;
+               status = "okay";
+
+               dai-link-0 {
+                       sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+               };
+
+               dai-link-1 {
+                       sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+                       dai-format = "i2s";
+                       mclk-fs = <256>;
+
+                       codec-0 {
+                               sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+                       };
+               };
+
+               dai-link-2 {
+                       sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+                       codec-0 {
+                               sound-dai = <&hdmi_tx>;
+                       };
+               };
+       };
+};
+
+&aiu {
+       status = "okay";
+};
+
+&ir {
+       linux,rc-map-name = "rc-wetek-hub";
+};

diff --git a/arch/arm/dts/meson-gxbb-wetek-play2.dts b/arch/arm/dts/meson-gxbb-wetek-play2.dts
new file mode 100644 (file)
index 0000000..505ffcd
--- /dev/null
+++ b/arch/arm/dts/meson-gxbb-wetek-play2.dts
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb-wetek.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/sound/meson-aiu.h>
+
+/ {
+       compatible = "wetek,play2", "amlogic,meson-gxbb";
+       model = "WeTek Play 2";
+
+       spdif_dit: audio-codec-0 {
+               #sound-dai-cells = <0>;
+               compatible = "linux,spdif-dit";
+               status = "okay";
+               sound-name-prefix = "DIT";
+       };
+
+       leds {
+               led-wifi {
+                       label = "wetek-play:wifi-status";
+                       gpios = <&gpio GPIODV_26 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+               };
+
+               led-ethernet {
+                       label = "wetek-play:ethernet-status";
+                       gpios = <&gpio GPIODV_27 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+               };
+       };
+
+       gpio-keys-polled {
+               compatible = "gpio-keys-polled";
+               poll-interval = <100>;
+
+               button {
+                       label = "reset";
+                       linux,code = <KEY_RESTART>;
+                       gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
+               };
+       };
+
+       sound {
+               compatible = "amlogic,gx-sound-card";
+               model = "WETEK-PLAY2";
+               assigned-clocks = <&clkc CLKID_MPLL0>,
+                                 <&clkc CLKID_MPLL1>,
+                                 <&clkc CLKID_MPLL2>;
+               assigned-clock-parents = <0>, <0>, <0>;
+               assigned-clock-rates = <294912000>,
+                                      <270950400>,
+                                      <393216000>;
+               status = "okay";
+
+               dai-link-0 {
+                       sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+               };
+
+               dai-link-1 {
+                       sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>;
+               };
+
+               dai-link-2 {
+                       sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+                       dai-format = "i2s";
+                       mclk-fs = <256>;
+
+                       codec-0 {
+                               sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+                       };
+               };
+
+               dai-link-3 {
+                       sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>;
+
+                       codec-0 {
+                               sound-dai = <&spdif_dit>;
+                       };
+               };
+
+               dai-link-4 {
+                       sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+                       codec-0 {
+                               sound-dai = <&hdmi_tx>;
+                       };
+               };
+       };
+};
+
+&aiu {
+       status = "okay";
+       pinctrl-0 = <&spdif_out_y_pins>;
+       pinctrl-names = "default";
+};
+
+&i2c_A {
+       status = "okay";
+       pinctrl-0 = <&i2c_a_pins>;
+       pinctrl-names = "default";
+};
+
+&usb1_phy {
+       status = "okay";
+};
+
+&usb1 {
+       status = "okay";
+};
+
+&ir {
+       linux,rc-map-name = "rc-wetek-play2";
+};

diff --git a/arch/arm/dts/meson-gxbb-wetek-u-boot.dtsi b/arch/arm/dts/meson-gxbb-wetek-u-boot.dtsi
new file mode 100644 (file)
index 0000000..3743053
--- /dev/null
+++ b/arch/arm/dts/meson-gxbb-wetek-u-boot.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-gx-u-boot.dtsi"
+
+&ethmac {
+       snps,reset-gpio = <&gpio GPIOZ_14 0>;
+       snps,reset-delays-us = <0 10000 1000000>;
+       snps,reset-active-low;
+};

diff --git a/arch/arm/dts/meson-gxbb-wetek.dtsi b/arch/arm/dts/meson-gxbb-wetek.dtsi
new file mode 100644 (file)
index 0000000..94dafb9
--- /dev/null
+++ b/arch/arm/dts/meson-gxbb-wetek.dtsi
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Andreas Färber
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Kevin Hilman <khilman@kernel.org>
+ */
+
+#include "meson-gxbb.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+       aliases {
+               serial0 = &uart_AO;
+               ethernet0 = &ethmac;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x40000000>;
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               led-power {
+                       /* red in suspend or power-off */
+                       color = <LED_COLOR_ID_BLUE>;
+                       function = LED_FUNCTION_POWER;
+                       gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
+                       default-state = "on";
+                       panic-indicator;
+               };
+       };
+
+       usb_pwr: regulator-usb-pwrs {
+               compatible = "regulator-fixed";
+
+               regulator-name = "USB_PWR";
+
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+
+               gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       vddio_boot: regulator-vddio_boot {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDIO_BOOT";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+       };
+
+       vddao_3v3: regulator-vddao_3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDAO_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
+
+       vddio_ao18: regulator-vddio_ao18 {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDIO_AO18";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-always-on;
+       };
+
+       vcc_3v3: regulator-vcc_3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
+
+       emmc_pwrseq: emmc-pwrseq {
+               compatible = "mmc-pwrseq-emmc";
+               reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+       };
+
+       wifi32k: wifi32k {
+               compatible = "pwm-clock";
+               #clock-cells = <0>;
+               clock-frequency = <32768>;
+               pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+       };
+
+       sdio_pwrseq: sdio-pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+               clocks = <&wifi32k>;
+               clock-names = "ext_clock";
+       };
+
+       cvbs-connector {
+               compatible = "composite-video-connector";
+
+               port {
+                       cvbs_connector_in: endpoint {
+                               remote-endpoint = <&cvbs_vdac_out>;
+                       };
+               };
+       };
+
+       hdmi-connector {
+               compatible = "hdmi-connector";
+               type = "a";
+
+               port {
+                       hdmi_connector_in: endpoint {
+                               remote-endpoint = <&hdmi_tx_tmds_out>;
+                       };
+               };
+       };
+};
+
+&cec_AO {
+       status = "okay";
+       pinctrl-0 = <&ao_cec_pins>;
+       pinctrl-names = "default";
+       hdmi-phandle = <&hdmi_tx>;
+};
+
+&cvbs_vdac_port {
+       cvbs_vdac_out: endpoint {
+               remote-endpoint = <&cvbs_connector_in>;
+       };
+};
+
+&ethmac {
+       status = "okay";
+       pinctrl-0 = <&eth_rgmii_pins>;
+       pinctrl-names = "default";
+
+       phy-handle = <&eth_phy0>;
+       phy-mode = "rgmii";
+
+       amlogic,tx-delay-ns = <2>;
+
+       mdio {
+               compatible = "snps,dwmac-mdio";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               eth_phy0: ethernet-phy@0 {
+                       /* Realtek RTL8211F (0x001cc916) */
+                       reg = <0>;
+
+                       reset-assert-us = <10000>;
+                       reset-deassert-us = <80000>;
+                       reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
+                       interrupt-parent = <&gpio_intc>;
+                       /* MAC_INTR on GPIOZ_15 */
+                       interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+               };
+       };
+};
+
+&hdmi_tx {
+       status = "okay";
+       pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+       pinctrl-names = "default";
+       hdmi-supply = <&vddio_ao18>;
+};
+
+&hdmi_tx_tmds_port {
+       hdmi_tx_tmds_out: endpoint {
+               remote-endpoint = <&hdmi_connector_in>;
+       };
+};
+
+&ir {
+       status = "okay";
+       pinctrl-0 = <&remote_input_ao_pins>;
+       pinctrl-names = "default";
+};
+
+&pwm_ef {
+       status = "okay";
+       pinctrl-0 = <&pwm_e_pins>;
+       pinctrl-names = "default";
+       clocks = <&clkc CLKID_FCLK_DIV4>;
+       clock-names = "clkin0";
+};
+
+&saradc {
+       status = "okay";
+       vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+       status = "okay";
+       pinctrl-0 = <&sdio_pins>;
+       pinctrl-1 = <&sdio_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       bus-width = <4>;
+       cap-sd-highspeed;
+       max-frequency = <50000000>;
+
+       non-removable;
+       disable-wp;
+
+       /* WiFi firmware requires power to be kept while in suspend */
+       keep-power-in-suspend;
+
+       mmc-pwrseq = <&sdio_pwrseq>;
+
+       vmmc-supply = <&vddao_3v3>;
+       vqmmc-supply = <&vddio_boot>;
+
+       brcmf: wifi@1 {
+               reg = <1>;
+               compatible = "brcm,bcm4329-fmac";
+       };
+};
+
+/* SD card */
+&sd_emmc_b {
+       status = "okay";
+       pinctrl-0 = <&sdcard_pins>;
+       pinctrl-1 = <&sdcard_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
+
+       bus-width = <4>;
+       cap-sd-highspeed;
+       max-frequency = <50000000>;
+       disable-wp;
+
+       cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
+
+       vmmc-supply = <&vddao_3v3>;
+       vqmmc-supply = <&vcc_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+       status = "okay";
+       pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+       pinctrl-1 = <&emmc_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
+
+       bus-width = <8>;
+       cap-mmc-highspeed;
+       max-frequency = <200000000>;
+       non-removable;
+       disable-wp;
+       mmc-ddr-1_8v;
+       mmc-hs200-1_8v;
+
+       mmc-pwrseq = <&emmc_pwrseq>;
+       vmmc-supply = <&vcc_3v3>;
+       vqmmc-supply = <&vddio_boot>;
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_A {
+       status = "okay";
+       pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+       pinctrl-names = "default";
+       uart-has-rtscts;
+
+       bluetooth {
+               compatible = "brcm,bcm43438-bt";
+               shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>;
+       };
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_AO {
+       status = "okay";
+       pinctrl-0 = <&uart_ao_a_pins>;
+       pinctrl-names = "default";
+};
+
+&usb0_phy {
+       status = "okay";
+       phy-supply = <&usb_pwr>;
+};
+
+&usb0 {
+       status = "okay";
+};

diff --git a/arch/arm/dts/meson-gxm-gt1-ultimate-u-boot.dtsi b/arch/arm/dts/meson-gxm-gt1-ultimate-u-boot.dtsi
new file mode 100644 (file)
index 0000000..39270ea
--- /dev/null
+++ b/arch/arm/dts/meson-gxm-gt1-ultimate-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-gxl-u-boot.dtsi"

diff --git a/arch/arm/dts/meson-gxm-gt1-ultimate.dts b/arch/arm/dts/meson-gxm-gt1-ultimate.dts
new file mode 100644 (file)
index 0000000..2c26788
--- /dev/null
+++ b/arch/arm/dts/meson-gxm-gt1-ultimate.dts
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxm.dtsi"
+#include "meson-gx-p23x-q20x.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+       compatible = "azw,gt1-ultimate", "amlogic,s912", "amlogic,meson-gxm";
+       model = "Beelink GT1 Ultimate";
+
+       leds {
+               compatible = "gpio-leds";
+
+               led-white {
+                       color = <LED_COLOR_ID_WHITE>;
+                       function = LED_FUNCTION_POWER;
+                       gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
+                       default-state = "on";
+                       panic-indicator;
+               };
+       };
+
+       adc-keys {
+               compatible = "adc-keys";
+               io-channels = <&saradc 0>;
+               io-channel-names = "buttons";
+               keyup-threshold-microvolt = <1710000>;
+
+               button-function {
+                       label = "update";
+                       linux,code = <KEY_VENDOR>;
+                       press-threshold-microvolt = <10000>;
+               };
+       };
+};
+
+&ethmac {
+       pinctrl-0 = <&eth_pins>;
+       pinctrl-names = "default";
+       phy-handle = <&external_phy>;
+       amlogic,tx-delay-ns = <2>;
+       phy-mode = "rgmii";
+};
+
+&external_mdio {
+       external_phy: ethernet-phy@0 {
+               /* Realtek RTL8211F (0x001cc916) */
+               reg = <0>;
+               max-speed = <1000>;
+
+               reset-assert-us = <10000>;
+               reset-deassert-us = <80000>;
+               reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
+               interrupt-parent = <&gpio_intc>;
+               /* MAC_INTR on GPIOZ_15 */
+               interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
+       };
+};
+
+&ir {
+       linux,rc-map-name = "rc-beelink-gs1";
+};
+
+&sd_emmc_a {
+       brcmf: wifi@1 {
+               reg = <1>;
+               compatible = "brcm,bcm4329-fmac";
+       };
+};
+
+&uart_A {
+       status = "okay";
+       pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+       pinctrl-names = "default";
+       uart-has-rtscts;
+
+       bluetooth {
+               compatible = "brcm,bcm43438-bt";
+               shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+               max-speed = <2000000>;
+               clocks = <&wifi32k>;
+               clock-names = "lpo";
+       };
+};

diff --git a/arch/arm/dts/meson-sm1-bananapi-m2-pro-u-boot.dtsi b/arch/arm/dts/meson-sm1-bananapi-m2-pro-u-boot.dtsi
new file mode 100644 (file)
index 0000000..4a1aeda
--- /dev/null
+++ b/arch/arm/dts/meson-sm1-bananapi-m2-pro-u-boot.dtsi
@@ -0,0 +1,14 @@
+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-sm1-u-boot.dtsi"
+
+&ethmac {
+       snps,reset-gpio = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+       snps,reset-delays-us = <0 10000 1000000>;
+       snps,reset-active-low;
+};

diff --git a/arch/arm/dts/meson-sm1-bananapi-m2-pro.dts b/arch/arm/dts/meson-sm1-bananapi-m2-pro.dts
new file mode 100644 (file)
index 0000000..5860343
--- /dev/null
+++ b/arch/arm/dts/meson-sm1-bananapi-m2-pro.dts
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-bananapi.dtsi"
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+       compatible = "bananapi,bpi-m2-pro", "amlogic,sm1";
+       model = "Banana Pi BPI-M2-PRO";
+
+       sound {
+               compatible = "amlogic,axg-sound-card";
+               model = "BPI-M2-PRO";
+               audio-aux-devs = <&tdmout_b>;
+               audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+                               "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+                               "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+                               "TDM_B Playback", "TDMOUT_B OUT";
+
+               assigned-clocks = <&clkc CLKID_MPLL2>,
+                                 <&clkc CLKID_MPLL0>,
+                                 <&clkc CLKID_MPLL1>;
+               assigned-clock-parents = <0>, <0>, <0>;
+               assigned-clock-rates = <294912000>,
+                                      <270950400>,
+                                      <393216000>;
+
+               dai-link-0 {
+                       sound-dai = <&frddr_a>;
+               };
+
+               dai-link-1 {
+                       sound-dai = <&frddr_b>;
+               };
+
+               dai-link-2 {
+                       sound-dai = <&frddr_c>;
+               };
+
+               /* 8ch hdmi interface */
+               dai-link-3 {
+                       sound-dai = <&tdmif_b>;
+                       dai-format = "i2s";
+                       dai-tdm-slot-tx-mask-0 = <1 1>;
+                       dai-tdm-slot-tx-mask-1 = <1 1>;
+                       dai-tdm-slot-tx-mask-2 = <1 1>;
+                       dai-tdm-slot-tx-mask-3 = <1 1>;
+                       mclk-fs = <256>;
+
+                       codec {
+                               sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+                       };
+               };
+
+               /* hdmi glue */
+               dai-link-4 {
+                       sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+                       codec {
+                               sound-dai = <&hdmi_tx>;
+                       };
+               };
+       };
+};
+
+&clkc_audio {
+       status = "okay";
+};
+
+&frddr_a {
+       status = "okay";
+};
+
+&frddr_b {
+       status = "okay";
+};
+
+&frddr_c {
+       status = "okay";
+};
+
+&tdmif_b {
+       status = "okay";
+};
+
+&tdmout_b {
+       status = "okay";
+};
+
+&tohdmitx {
+       status = "okay";
+};

diff --git a/arch/arm/dts/meson-sm1-bananapi-m5.dts b/arch/arm/dts/meson-sm1-bananapi-m5.dts
index effaa13..f045bf8 100644 (file)
--- a/arch/arm/dts/meson-sm1-bananapi-m5.dts
+++ b/arch/arm/dts/meson-sm1-bananapi-m5.dts
@@ -6,10 +6,7 @@
 
 /dts-v1/;
 
-#include "meson-sm1.dtsi"
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include "meson-sm1-bananapi.dtsi"
 #include <dt-bindings/sound/meson-g12a-toacodec.h>
 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
 
@@ -17,28 +14,6 @@
        compatible = "bananapi,bpi-m5", "amlogic,sm1";
        model = "Banana Pi BPI-M5";
 
-       adc_keys {
-               compatible = "adc-keys";
-               io-channels = <&saradc 2>;
-               io-channel-names = "buttons";
-               keyup-threshold-microvolt = <1800000>;
-
-               key {
-                       label = "SW3";
-                       linux,code = <BTN_3>;
-                       press-threshold-microvolt = <1700000>;
-               };
-       };
-
-       aliases {
-               serial0 = &uart_AO;
-               ethernet0 = &ethmac;
-       };
-
-       chosen {
-               stdout-path = "serial0:115200n8";
-       };
-
        /* TOFIX: handle CVBS_DET on SARADC channel 0 */
        cvbs-connector {
                compatible = "composite-video-connector";
@@ -50,150 +25,6 @@
                };
        };
 
-       emmc_pwrseq: emmc-pwrseq {
-               compatible = "mmc-pwrseq-emmc";
-               reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
-       };
-
-       gpio-keys {
-               compatible = "gpio-keys";
-
-               key {
-                       label = "SW1";
-                       linux,code = <BTN_1>;
-                       gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
-                       interrupt-parent = <&gpio_intc>;
-                       interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
-               };
-       };
-
-       hdmi-connector {
-               compatible = "hdmi-connector";
-               type = "a";
-
-               port {
-                       hdmi_connector_in: endpoint {
-                               remote-endpoint = <&hdmi_tx_tmds_out>;
-                       };
-               };
-       };
-
-       leds {
-               compatible = "gpio-leds";
-
-               green {
-                       color = <LED_COLOR_ID_GREEN>;
-                       function = LED_FUNCTION_STATUS;
-                       gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
-               };
-
-               blue {
-                       color = <LED_COLOR_ID_BLUE>;
-                       function = LED_FUNCTION_STATUS;
-                       gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
-                       linux,default-trigger = "heartbeat";
-               };
-       };
-
-       memory@0 {
-               device_type = "memory";
-               reg = <0x0 0x0 0x0 0x40000000>;
-       };
-
-       emmc_1v8: regulator-emmc_1v8 {
-               compatible = "regulator-fixed";
-               regulator-name = "EMMC_1V8";
-               regulator-min-microvolt = <1800000>;
-               regulator-max-microvolt = <1800000>;
-               vin-supply = <&vddao_3v3>;
-               regulator-always-on;
-       };
-
-       dc_in: regulator-dc_in {
-               compatible = "regulator-fixed";
-               regulator-name = "DC_IN";
-               regulator-min-microvolt = <5000000>;
-               regulator-max-microvolt = <5000000>;
-               regulator-always-on;
-       };
-
-       vddio_c: regulator-vddio_c {
-               compatible = "regulator-gpio";
-               regulator-name = "VDDIO_C";
-               regulator-min-microvolt = <1800000>;
-               regulator-max-microvolt = <3300000>;
-
-               enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
-               enable-active-high;
-               regulator-always-on;
-
-               gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>;
-               gpios-states = <1>;
-
-               states = <1800000 0>,
-                        <3300000 1>;
-       };
-
-       tflash_vdd: regulator-tflash_vdd {
-               compatible = "regulator-fixed";
-               regulator-name = "TFLASH_VDD";
-               regulator-min-microvolt = <3300000>;
-               regulator-max-microvolt = <3300000>;
-               vin-supply = <&dc_in>;
-               gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
-               enable-active-high;
-               regulator-always-on;
-       };
-
-       vddao_1v8: regulator-vddao_1v8 {
-               compatible = "regulator-fixed";
-               regulator-name = "VDDAO_1V8";
-               regulator-min-microvolt = <1800000>;
-               regulator-max-microvolt = <1800000>;
-               vin-supply = <&vddao_3v3>;
-               regulator-always-on;
-       };
-
-       vddao_3v3: regulator-vddao_3v3 {
-               compatible = "regulator-fixed";
-               regulator-name = "VDDAO_3V3";
-               regulator-min-microvolt = <3300000>;
-               regulator-max-microvolt = <3300000>;
-               vin-supply = <&dc_in>;
-               regulator-always-on;
-       };
-
-       vddcpu: regulator-vddcpu {
-               /*
-                * SY8120B1ABC DC/DC Regulator.
-                */
-               compatible = "pwm-regulator";
-
-               regulator-name = "VDDCPU";
-               regulator-min-microvolt = <690000>;
-               regulator-max-microvolt = <1050000>;
-
-               vin-supply = <&dc_in>;
-
-               pwms = <&pwm_AO_cd 1 1250 0>;
-               pwm-dutycycle-range = <100 0>;
-
-               regulator-boot-on;
-               regulator-always-on;
-       };
-
-       /* USB Hub Power Enable */
-       vl_pwr_en: regulator-vl_pwr_en {
-               compatible = "regulator-fixed";
-               regulator-name = "VL_PWR_EN";
-               regulator-min-microvolt = <5000000>;
-               regulator-max-microvolt = <5000000>;
-               vin-supply = <&dc_in>;
-
-               gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
-               enable-active-high;
-       };
-
        sound {
                compatible = "amlogic,axg-sound-card";
                model = "BPI-M5";
@@ -233,7 +64,6 @@
                assigned-clock-rates = <294912000>,
                                       <270950400>,
                                       <393216000>;
-               status = "okay";
 
                dai-link-0 {
                        sound-dai = <&frddr_a>;
@@ -319,68 +149,17 @@
        status = "okay";
 };
 
-&arb {
-       status = "okay";
-};
 
 &clkc_audio {
        status = "okay";
 };
 
-&cpu0 {
-       cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
-       clock-latency = <50000>;
-};
-
-&cpu1 {
-       cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU1_CLK>;
-       clock-latency = <50000>;
-};
-
-&cpu2 {
-       cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU2_CLK>;
-       clock-latency = <50000>;
-};
-
-&cpu3 {
-       cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU3_CLK>;
-       clock-latency = <50000>;
-};
-
 &cvbs_vdac_port {
        cvbs_vdac_out: endpoint {
                remote-endpoint = <&cvbs_connector_in>;
        };
 };
 
-&ext_mdio {
-       external_phy: ethernet-phy@0 {
-               /* Realtek RTL8211F (0x001cc916) */
-               reg = <0>;
-               max-speed = <1000>;
-
-               interrupt-parent = <&gpio_intc>;
-               /* MAC_INTR on GPIOZ_14 */
-               interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
-       };
-};
-
-&ethmac {
-       pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
-       pinctrl-names = "default";
-       status = "okay";
-       phy-mode = "rgmii-txid";
-       phy-handle = <&external_phy>;
-};
-
 &frddr_a {
        status = "okay";
 };
@@ -393,191 +172,6 @@
        status = "okay";
 };
 
-&gpio {
-       gpio-line-names =
-               /* GPIOZ */
-               "ETH_MDIO", /* GPIOZ_0 */
-               "ETH_MDC", /* GPIOZ_1 */
-               "ETH_RXCLK", /* GPIOZ_2 */
-               "ETH_RX_DV", /* GPIOZ_3 */
-               "ETH_RXD0", /* GPIOZ_4 */
-               "ETH_RXD1", /* GPIOZ_5 */
-               "ETH_RXD2", /* GPIOZ_6 */
-               "ETH_RXD3", /* GPIOZ_7 */
-               "ETH_TXCLK", /* GPIOZ_8 */
-               "ETH_TXEN", /* GPIOZ_9 */
-               "ETH_TXD0", /* GPIOZ_10 */
-               "ETH_TXD1", /* GPIOZ_11 */
-               "ETH_TXD2", /* GPIOZ_12 */
-               "ETH_TXD3", /* GPIOZ_13 */
-               "ETH_INTR", /* GPIOZ_14 */
-               "ETH_NRST", /* GPIOZ_15 */
-               /* GPIOH */
-               "HDMI_SDA", /* GPIOH_0 */
-               "HDMI_SCL", /* GPIOH_1 */
-               "HDMI_HPD", /* GPIOH_2 */
-               "HDMI_CEC", /* GPIOH_3 */
-               "VL-RST_N", /* GPIOH_4 */
-               "CON1-P36", /* GPIOH_5 */
-               "VL-PWREN", /* GPIOH_6 */
-               "WiFi_3V3_1V8", /* GPIOH_7 */
-               "TFLASH_VDD_EN", /* GPIOH_8 */
-               /* BOOT */
-               "eMMC_D0", /* BOOT_0 */
-               "eMMC_D1", /* BOOT_1 */
-               "eMMC_D2", /* BOOT_2 */
-               "eMMC_D3", /* BOOT_3 */
-               "eMMC_D4", /* BOOT_4 */
-               "eMMC_D5", /* BOOT_5 */
-               "eMMC_D6", /* BOOT_6 */
-               "eMMC_D7", /* BOOT_7 */
-               "eMMC_CLK", /* BOOT_8 */
-               "",
-               "eMMC_CMD", /* BOOT_10 */
-               "",
-               "eMMC_RST#", /* BOOT_12 */
-               "eMMC_DS", /* BOOT_13 */
-               /* GPIOC */
-               "SD_D0_B", /* GPIOC_0 */
-               "SD_D1_B", /* GPIOC_1 */
-               "SD_D2_B", /* GPIOC_2 */
-               "SD_D3_B", /* GPIOC_3 */
-               "SD_CLK_B", /* GPIOC_4 */
-               "SD_CMD_B", /* GPIOC_5 */
-               "CARD_EN_DET", /* GPIOC_6 */
-               "",
-               /* GPIOA */
-               "", "", "", "", "", "", "", "",
-               "", "", "", "", "", "",
-               "CON1-P27", /* GPIOA_14 */
-               "CON1-P28", /* GPIOA_15 */
-               /* GPIOX */
-               "CON1-P16", /* GPIOX_0 */
-               "CON1-P18", /* GPIOX_1 */
-               "CON1-P22", /* GPIOX_2 */
-               "CON1-P11", /* GPIOX_3 */
-               "CON1-P13", /* GPIOX_4 */
-               "CON1-P07", /* GPIOX_5 */
-               "CON1-P33", /* GPIOX_6 */
-               "CON1-P15", /* GPIOX_7 */
-               "CON1-P19", /* GPIOX_8 */
-               "CON1-P21", /* GPIOX_9 */
-               "CON1-P24", /* GPIOX_10 */
-               "CON1-P23", /* GPIOX_11 */
-               "CON1-P08", /* GPIOX_12 */
-               "CON1-P10", /* GPIOX_13 */
-               "CON1-P29", /* GPIOX_14 */
-               "CON1-P31", /* GPIOX_15 */
-               "CON1-P26", /* GPIOX_16 */
-               "CON1-P03", /* GPIOX_17 */
-               "CON1-P05", /* GPIOX_18 */
-               "CON1-P32"; /* GPIOX_19 */
-
-       /*
-        * WARNING: The USB Hub on the BPI-M5 needs a reset signal
-        * to be turned high in order to be detected by the USB Controller
-        * This signal should be handled by a USB specific power sequence
-        * in order to reset the Hub when USB bus is powered down.
-        */
-       usb-hub {
-               gpio-hog;
-               gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
-               output-high;
-               line-name = "usb-hub-reset";
-       };
-};
-
-&gpio_ao {
-       gpio-line-names =
-               /* GPIOAO */
-               "DEBUG TX", /* GPIOAO_0 */
-               "DEBUG RX", /* GPIOAO_1 */
-               "SYS_LED2", /* GPIOAO_2 */
-               "UPDATE_KEY", /* GPIOAO_3 */
-               "CON1-P40", /* GPIOAO_4 */
-               "IR_IN", /* GPIOAO_5 */
-               "TF_3V3N_1V8_EN", /* GPIOAO_6 */
-               "CON1-P35", /* GPIOAO_7 */
-               "CON1-P12", /* GPIOAO_8 */
-               "CON1-P37", /* GPIOAO_9 */
-               "CON1-P38", /* GPIOAO_10 */
-               "SYS_LED", /* GPIOAO_11 */
-               /* GPIOE */
-               "VDDEE_PWM", /* GPIOE_0 */
-               "VDDCPU_PWM", /* GPIOE_1 */
-               "TF_PWR_EN"; /* GPIOE_2 */
-};
-
-&hdmi_tx {
-       status = "okay";
-       pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
-       pinctrl-names = "default";
-       hdmi-supply = <&dc_in>;
-};
-
-&hdmi_tx_tmds_port {
-       hdmi_tx_tmds_out: endpoint {
-               remote-endpoint = <&hdmi_connector_in>;
-       };
-};
-
-&ir {
-       status = "okay";
-       pinctrl-0 = <&remote_input_ao_pins>;
-       pinctrl-names = "default";
-};
-
-&pwm_AO_cd {
-       pinctrl-0 = <&pwm_ao_d_e_pins>;
-       pinctrl-names = "default";
-       clocks = <&xtal>;
-       clock-names = "clkin1";
-       status = "okay";
-};
-
-&saradc {
-       status = "okay";
-       vref-supply = <&vddao_1v8>;
-};
-
-/* SD card */
-&sd_emmc_b {
-       status = "okay";
-       pinctrl-0 = <&sdcard_c_pins>;
-       pinctrl-1 = <&sdcard_clk_gate_c_pins>;
-       pinctrl-names = "default", "clk-gate";
-
-       bus-width = <4>;
-       cap-sd-highspeed;
-       max-frequency = <50000000>;
-       disable-wp;
-
-       /* TOFIX: SD card is barely usable in SDR modes */
-
-       cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
-       vmmc-supply = <&tflash_vdd>;
-       vqmmc-supply = <&vddio_c>;
-};
-
-/* eMMC */
-&sd_emmc_c {
-       status = "okay";
-       pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
-       pinctrl-1 = <&emmc_clk_gate_pins>;
-       pinctrl-names = "default", "clk-gate";
-
-       bus-width = <8>;
-       cap-mmc-highspeed;
-       mmc-ddr-1_8v;
-       mmc-hs200-1_8v;
-       max-frequency = <200000000>;
-       disable-wp;
-
-       mmc-pwrseq = <&emmc_pwrseq>;
-       vmmc-supply = <&vddao_3v3>;
-       vqmmc-supply = <&emmc_1v8>;
-};
-
 &tdmif_b {
        status = "okay";
 };
@@ -625,22 +219,3 @@
 &toddr_c {
        status = "okay";
 };
-
-&uart_AO {
-       status = "okay";
-       pinctrl-0 = <&uart_ao_a_pins>;
-       pinctrl-names = "default";
-};
-
-&usb {
-       status = "okay";
-};
-
-&usb2_phy0 {
-       phy-supply = <&dc_in>;
-};
-
-&usb2_phy1 {
-       /* Enable the hub which is connected to this port */
-       phy-supply = <&vl_pwr_en>;
-};

diff --git a/arch/arm/dts/meson-sm1-bananapi.dtsi b/arch/arm/dts/meson-sm1-bananapi.dtsi
new file mode 100644 (file)
index 0000000..17045ff
--- /dev/null
+++ b/arch/arm/dts/meson-sm1-bananapi.dtsi
@@ -0,0 +1,435 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-sm1.dtsi"
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+
+/ {
+       adc-keys {
+               compatible = "adc-keys";
+               io-channels = <&saradc 2>;
+               io-channel-names = "buttons";
+               keyup-threshold-microvolt = <1800000>;
+
+               button-sw3 {
+                       label = "SW3";
+                       linux,code = <BTN_3>;
+                       press-threshold-microvolt = <1700000>;
+               };
+       };
+
+       aliases {
+               serial0 = &uart_AO;
+               ethernet0 = &ethmac;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       emmc_pwrseq: emmc-pwrseq {
+               compatible = "mmc-pwrseq-emmc";
+               reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+       };
+
+       gpio-keys {
+               compatible = "gpio-keys";
+
+               key {
+                       label = "SW1";
+                       linux,code = <BTN_1>;
+                       gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
+                       interrupt-parent = <&gpio_intc>;
+                       interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
+               };
+       };
+
+       hdmi-connector {
+               compatible = "hdmi-connector";
+               type = "a";
+
+               port {
+                       hdmi_connector_in: endpoint {
+                               remote-endpoint = <&hdmi_tx_tmds_out>;
+                       };
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               led-green {
+                       color = <LED_COLOR_ID_GREEN>;
+                       function = LED_FUNCTION_STATUS;
+                       gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+               };
+
+               led-blue {
+                       color = <LED_COLOR_ID_BLUE>;
+                       function = LED_FUNCTION_STATUS;
+                       gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
+                       linux,default-trigger = "heartbeat";
+               };
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x40000000>;
+       };
+
+       emmc_1v8: regulator-emmc_1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "EMMC_1V8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               vin-supply = <&vddao_3v3>;
+               regulator-always-on;
+       };
+
+       dc_in: regulator-dc_in {
+               compatible = "regulator-fixed";
+               regulator-name = "DC_IN";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-always-on;
+       };
+
+       vddio_c: regulator-vddio_c {
+               compatible = "regulator-gpio";
+               regulator-name = "VDDIO_C";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <3300000>;
+
+               enable-gpios = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>;
+               enable-active-high;
+               regulator-always-on;
+
+               gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>;
+               gpios-states = <1>;
+
+               states = <1800000 0>,
+                        <3300000 1>;
+       };
+
+       tflash_vdd: regulator-tflash_vdd {
+               compatible = "regulator-fixed";
+               regulator-name = "TFLASH_VDD";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               vin-supply = <&dc_in>;
+               gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+               enable-active-high;
+               regulator-always-on;
+       };
+
+       vddao_1v8: regulator-vddao_1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDAO_1V8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               vin-supply = <&vddao_3v3>;
+               regulator-always-on;
+       };
+
+       vddao_3v3: regulator-vddao_3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDAO_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               vin-supply = <&dc_in>;
+               regulator-always-on;
+       };
+
+       vddcpu: regulator-vddcpu {
+               /*
+                * SY8120B1ABC DC/DC Regulator.
+                */
+               compatible = "pwm-regulator";
+
+               regulator-name = "VDDCPU";
+               regulator-min-microvolt = <690000>;
+               regulator-max-microvolt = <1050000>;
+
+               pwm-supply = <&dc_in>;
+
+               pwms = <&pwm_AO_cd 1 1250 0>;
+               pwm-dutycycle-range = <100 0>;
+
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       /* USB Hub Power Enable */
+       vl_pwr_en: regulator-vl_pwr_en {
+               compatible = "regulator-fixed";
+               regulator-name = "VL_PWR_EN";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               vin-supply = <&dc_in>;
+
+               gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+};
+
+&arb {
+       status = "okay";
+};
+
+&cpu0 {
+       cpu-supply = <&vddcpu>;
+       operating-points-v2 = <&cpu_opp_table>;
+       clocks = <&clkc CLKID_CPU_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu1 {
+       cpu-supply = <&vddcpu>;
+       operating-points-v2 = <&cpu_opp_table>;
+       clocks = <&clkc CLKID_CPU1_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu2 {
+       cpu-supply = <&vddcpu>;
+       operating-points-v2 = <&cpu_opp_table>;
+       clocks = <&clkc CLKID_CPU2_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu3 {
+       cpu-supply = <&vddcpu>;
+       operating-points-v2 = <&cpu_opp_table>;
+       clocks = <&clkc CLKID_CPU3_CLK>;
+       clock-latency = <50000>;
+};
+
+&ext_mdio {
+       external_phy: ethernet-phy@0 {
+               /* Realtek RTL8211F (0x001cc916) */
+               reg = <0>;
+               max-speed = <1000>;
+
+               interrupt-parent = <&gpio_intc>;
+               /* MAC_INTR on GPIOZ_14 */
+               interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+       };
+};
+
+&ethmac {
+       pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+       phy-mode = "rgmii-txid";
+       phy-handle = <&external_phy>;
+};
+
+&gpio {
+       gpio-line-names =
+               /* GPIOZ */
+               "ETH_MDIO", /* GPIOZ_0 */
+               "ETH_MDC", /* GPIOZ_1 */
+               "ETH_RXCLK", /* GPIOZ_2 */
+               "ETH_RX_DV", /* GPIOZ_3 */
+               "ETH_RXD0", /* GPIOZ_4 */
+               "ETH_RXD1", /* GPIOZ_5 */
+               "ETH_RXD2", /* GPIOZ_6 */
+               "ETH_RXD3", /* GPIOZ_7 */
+               "ETH_TXCLK", /* GPIOZ_8 */
+               "ETH_TXEN", /* GPIOZ_9 */
+               "ETH_TXD0", /* GPIOZ_10 */
+               "ETH_TXD1", /* GPIOZ_11 */
+               "ETH_TXD2", /* GPIOZ_12 */
+               "ETH_TXD3", /* GPIOZ_13 */
+               "ETH_INTR", /* GPIOZ_14 */
+               "ETH_NRST", /* GPIOZ_15 */
+               /* GPIOH */
+               "HDMI_SDA", /* GPIOH_0 */
+               "HDMI_SCL", /* GPIOH_1 */
+               "HDMI_HPD", /* GPIOH_2 */
+               "HDMI_CEC", /* GPIOH_3 */
+               "VL-RST_N", /* GPIOH_4 */
+               "CON1-P36", /* GPIOH_5 */
+               "VL-PWREN", /* GPIOH_6 */
+               "WiFi_3V3_1V8", /* GPIOH_7 */
+               "TFLASH_VDD_EN", /* GPIOH_8 */
+               /* BOOT */
+               "eMMC_D0", /* BOOT_0 */
+               "eMMC_D1", /* BOOT_1 */
+               "eMMC_D2", /* BOOT_2 */
+               "eMMC_D3", /* BOOT_3 */
+               "eMMC_D4", /* BOOT_4 */
+               "eMMC_D5", /* BOOT_5 */
+               "eMMC_D6", /* BOOT_6 */
+               "eMMC_D7", /* BOOT_7 */
+               "eMMC_CLK", /* BOOT_8 */
+               "",
+               "eMMC_CMD", /* BOOT_10 */
+               "",
+               "eMMC_RST#", /* BOOT_12 */
+               "eMMC_DS", /* BOOT_13 */
+               "", "",
+               /* GPIOC */
+               "SD_D0_B", /* GPIOC_0 */
+               "SD_D1_B", /* GPIOC_1 */
+               "SD_D2_B", /* GPIOC_2 */
+               "SD_D3_B", /* GPIOC_3 */
+               "SD_CLK_B", /* GPIOC_4 */
+               "SD_CMD_B", /* GPIOC_5 */
+               "CARD_EN_DET", /* GPIOC_6 */
+               "",
+               /* GPIOA */
+               "", "", "", "", "", "", "", "",
+               "", "", "", "", "", "",
+               "CON1-P27", /* GPIOA_14 */
+               "CON1-P28", /* GPIOA_15 */
+               /* GPIOX */
+               "CON1-P16", /* GPIOX_0 */
+               "CON1-P18", /* GPIOX_1 */
+               "CON1-P22", /* GPIOX_2 */
+               "CON1-P11", /* GPIOX_3 */
+               "CON1-P13", /* GPIOX_4 */
+               "CON1-P07", /* GPIOX_5 */
+               "CON1-P33", /* GPIOX_6 */
+               "CON1-P15", /* GPIOX_7 */
+               "CON1-P19", /* GPIOX_8 */
+               "CON1-P21", /* GPIOX_9 */
+               "CON1-P24", /* GPIOX_10 */
+               "CON1-P23", /* GPIOX_11 */
+               "CON1-P08", /* GPIOX_12 */
+               "CON1-P10", /* GPIOX_13 */
+               "CON1-P29", /* GPIOX_14 */
+               "CON1-P31", /* GPIOX_15 */
+               "CON1-P26", /* GPIOX_16 */
+               "CON1-P03", /* GPIOX_17 */
+               "CON1-P05", /* GPIOX_18 */
+               "CON1-P32"; /* GPIOX_19 */
+
+       /*
+        * WARNING: The USB Hub needs a reset signal to be turned high in
+        * order to be detected by the USB Controller. This signal should
+        * be handled by a USB specific power sequence to reset the Hub
+        * when the USB bus is powered down.
+        */
+       usb-hub-hog {
+               gpio-hog;
+               gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
+               output-high;
+               line-name = "usb-hub-reset";
+       };
+};
+
+&gpio_ao {
+       gpio-line-names =
+               /* GPIOAO */
+               "DEBUG TX", /* GPIOAO_0 */
+               "DEBUG RX", /* GPIOAO_1 */
+               "SYS_LED2", /* GPIOAO_2 */
+               "UPDATE_KEY", /* GPIOAO_3 */
+               "CON1-P40", /* GPIOAO_4 */
+               "IR_IN", /* GPIOAO_5 */
+               "TF_3V3N_1V8_EN", /* GPIOAO_6 */
+               "CON1-P35", /* GPIOAO_7 */
+               "CON1-P12", /* GPIOAO_8 */
+               "CON1-P37", /* GPIOAO_9 */
+               "CON1-P38", /* GPIOAO_10 */
+               "SYS_LED", /* GPIOAO_11 */
+               /* GPIOE */
+               "VDDEE_PWM", /* GPIOE_0 */
+               "VDDCPU_PWM", /* GPIOE_1 */
+               "TF_PWR_EN"; /* GPIOE_2 */
+};
+
+&hdmi_tx {
+       status = "okay";
+       pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+       pinctrl-names = "default";
+       hdmi-supply = <&dc_in>;
+};
+
+&hdmi_tx_tmds_port {
+       hdmi_tx_tmds_out: endpoint {
+               remote-endpoint = <&hdmi_connector_in>;
+       };
+};
+
+&ir {
+       status = "okay";
+       pinctrl-0 = <&remote_input_ao_pins>;
+       pinctrl-names = "default";
+};
+
+&pwm_AO_cd {
+       pinctrl-0 = <&pwm_ao_d_e_pins>;
+       pinctrl-names = "default";
+       clocks = <&xtal>;
+       clock-names = "clkin1";
+       status = "okay";
+};
+
+&saradc {
+       status = "okay";
+       vref-supply = <&vddao_1v8>;
+};
+
+/* SD card */
+&sd_emmc_b {
+       status = "okay";
+       pinctrl-0 = <&sdcard_c_pins>;
+       pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+       pinctrl-names = "default", "clk-gate";
+
+       bus-width = <4>;
+       cap-sd-highspeed;
+       max-frequency = <50000000>;
+       disable-wp;
+
+       /* TOFIX: SD card is barely usable in SDR modes */
+
+       cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+       vmmc-supply = <&tflash_vdd>;
+       vqmmc-supply = <&vddio_c>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+       status = "okay";
+       pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+       pinctrl-1 = <&emmc_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
+
+       bus-width = <8>;
+       cap-mmc-highspeed;
+       mmc-ddr-1_8v;
+       mmc-hs200-1_8v;
+       max-frequency = <200000000>;
+       disable-wp;
+
+       mmc-pwrseq = <&emmc_pwrseq>;
+       vmmc-supply = <&vddao_3v3>;
+       vqmmc-supply = <&emmc_1v8>;
+};
+
+&uart_AO {
+       status = "okay";
+       pinctrl-0 = <&uart_ao_a_pins>;
+       pinctrl-names = "default";
+};
+
+&usb {
+       status = "okay";
+};
+
+&usb2_phy0 {
+       phy-supply = <&dc_in>;
+};
+
+&usb2_phy1 {
+       /* Enable the hub which is connected to this port */
+       phy-supply = <&vl_pwr_en>;
+};

diff --git a/arch/arm/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/dts/omap-gpmc-smsc911x.dtsi
index ded7e8f..9cf5265 100644 (file)
--- a/arch/arm/dts/omap-gpmc-smsc911x.dtsi
+++ b/arch/arm/dts/omap-gpmc-smsc911x.dtsi
@@ -8,9 +8,9 @@
 
 / {
        vddvario: regulator-vddvario {
-                 compatible = "regulator-fixed";
-                 regulator-name = "vddvario";
-                 regulator-always-on;
+               compatible = "regulator-fixed";
+               regulator-name = "vddvario";
+               regulator-always-on;
        };
 
        vdd33a: regulator-vdd33a {

diff --git a/arch/arm/dts/omap-gpmc-smsc9221.dtsi b/arch/arm/dts/omap-gpmc-smsc9221.dtsi
index 73e272f..ac81793 100644 (file)
--- a/arch/arm/dts/omap-gpmc-smsc9221.dtsi
+++ b/arch/arm/dts/omap-gpmc-smsc9221.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Common file for GPMC connected smsc9221 on omaps
  *
@@ -11,9 +12,9 @@
 
 / {
        vddvario: regulator-vddvario {
-                 compatible = "regulator-fixed";
-                 regulator-name = "vddvario";
-                 regulator-always-on;
+               compatible = "regulator-fixed";
+               regulator-name = "vddvario";
+               regulator-always-on;
        };
 
        vdd33a: regulator-vdd33a {

diff --git a/arch/arm/dts/omap3-beagle-xm-ab.dts b/arch/arm/dts/omap3-beagle-xm-ab.dts
index 7ac3bcf..cb6968a 100644 (file)
--- a/arch/arm/dts/omap3-beagle-xm-ab.dts
+++ b/arch/arm/dts/omap3-beagle-xm-ab.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "omap3-beagle-xm.dts"

diff --git a/arch/arm/dts/omap3-beagle-xm.dts b/arch/arm/dts/omap3-beagle-xm.dts
index 8461159..73152f6 100644 (file)
--- a/arch/arm/dts/omap3-beagle-xm.dts
+++ b/arch/arm/dts/omap3-beagle-xm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -30,26 +27,26 @@
                ethernet = &ethernet;
        };
 
-       leds {
+       led-controller-1 {
                compatible = "gpio-leds";
 
-               heartbeat {
+               led-1 {
                        label = "beagleboard::usr0";
                        gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
                        linux,default-trigger = "heartbeat";
                };
 
-               mmc {
+               led-2 {
                        label = "beagleboard::usr1";
                        gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
                        linux,default-trigger = "mmc0";
                };
        };
 
-       pwmleds {
+       led-controller-2 {
                compatible = "pwm-leds";
 
-               pmu_stat {
+               led-3 {
                        label = "beagleboard::pmu_stat";
                        pwms = <&twl_pwmled 1 7812500>;
                        max-brightness = <127>;
@@ -360,7 +357,7 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
-               ethernet: usbether@1 {
+               ethernet: ethernet@1 {
                        compatible = "usb424,ec00";
                        reg = <1>;
                };

diff --git a/arch/arm/dts/omap3-beagle.dts b/arch/arm/dts/omap3-beagle.dts
index 4ceee2b..321b6d7 100644 (file)
--- a/arch/arm/dts/omap3-beagle.dts
+++ b/arch/arm/dts/omap3-beagle.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -31,18 +28,18 @@
 
        leds {
                compatible = "gpio-leds";
-               pmu_stat {
+               led-pmu-stat {
                        label = "beagleboard::pmu_stat";
                        gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
                };
 
-               heartbeat {
+               led-heartbeat {
                        label = "beagleboard::usr0";
                        gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
                        linux,default-trigger = "heartbeat";
                };
 
-               mmc {
+               led-mmc {
                        label = "beagleboard::usr1";
                        gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
                        linux,default-trigger = "mmc0";

diff --git a/arch/arm/dts/omap3-cpu-thermal.dtsi b/arch/arm/dts/omap3-cpu-thermal.dtsi
index 235ecfd..e677d1d 100644 (file)
--- a/arch/arm/dts/omap3-cpu-thermal.dtsi
+++ b/arch/arm/dts/omap3-cpu-thermal.dtsi
@@ -1,16 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP3 SoC CPU thermal
  *
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/thermal/thermal.h>
 
-cpu_thermal: cpu_thermal {
+cpu_thermal: cpu-thermal {
        polling-delay-passive = <250>; /* milliseconds */
        polling-delay = <1000>; /* milliseconds */
        coefficients = <0 20000>;

diff --git a/arch/arm/dts/omap3-evm-37xx.dts b/arch/arm/dts/omap3-evm-37xx.dts
index a14303b..abd403c 100644 (file)
--- a/arch/arm/dts/omap3-evm-37xx.dts
+++ b/arch/arm/dts/omap3-evm-37xx.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -63,7 +60,7 @@
                interrupt-parent = <&gpmc>;
                interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                             <1 IRQ_TYPE_NONE>; /* termcount */
-               linux,mtd-name= "hynix,h8kds0un0mer-4em";
+               linux,mtd-name = "hynix,h8kds0un0mer-4em";
                nand-bus-width = <16>;
                gpmc,device-width = <2>;
                ti,nand-ecc-opt = "bch8";

diff --git a/arch/arm/dts/omap3-evm-processor-common.dtsi b/arch/arm/dts/omap3-evm-processor-common.dtsi
index b4109f4..e6ba30a 100644 (file)
--- a/arch/arm/dts/omap3-evm-processor-common.dtsi
+++ b/arch/arm/dts/omap3-evm-processor-common.dtsi
@@ -195,7 +195,7 @@
  * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V.
  */
 &gpio2 {
-       en_usb2_port {
+       en-usb2-port-hog {
                gpio-hog;
                gpios = <29 GPIO_ACTIVE_HIGH>;  /* gpio_61 */
                output-low;

diff --git a/arch/arm/dts/omap3-evm.dts b/arch/arm/dts/omap3-evm.dts
index 21a3b88..f95eea6 100644 (file)
--- a/arch/arm/dts/omap3-evm.dts
+++ b/arch/arm/dts/omap3-evm.dts
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -63,7 +60,7 @@
                interrupt-parent = <&gpmc>;
                interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                             <1 IRQ_TYPE_NONE>; /* termcount */
-               linux,mtd-name= "micron,mt29f2g16abdhc";
+               linux,mtd-name = "micron,mt29f2g16abdhc";
                nand-bus-width = <16>;
                gpmc,device-width = <2>;
                ti,nand-ecc-opt = "bch8";

diff --git a/arch/arm/dts/omap3-igep.dtsi b/arch/arm/dts/omap3-igep.dtsi
index f33cc80..2192026 100644 (file)
--- a/arch/arm/dts/omap3-igep.dtsi
+++ b/arch/arm/dts/omap3-igep.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Common device tree for IGEP boards based on AM/DM37x
  *
- * Copyright (C) 2012 Javier Martinez Canillas <javier@osg.samsung.com>
+ * Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
  * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 /dts-v1/;
 
@@ -114,7 +111,7 @@
                interrupt-parent = <&gpmc>;
                interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                             <1 IRQ_TYPE_NONE>; /* termcount */
-               linux,mtd-name= "micron,mt29c4g96maz";
+               linux,mtd-name = "micron,mt29c4g96maz";
                nand-bus-width = <16>;
                gpmc,device-width = <2>;
                ti,nand-ecc-opt = "bch8";

diff --git a/arch/arm/dts/omap3-igep0020-common.dtsi b/arch/arm/dts/omap3-igep0020-common.dtsi
index d62481d..73d8f47 100644 (file)
--- a/arch/arm/dts/omap3-igep0020-common.dtsi
+++ b/arch/arm/dts/omap3-igep0020-common.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Common Device Tree Source for IGEPv2
  *
- * Copyright (C) 2014 Javier Martinez Canillas <javier@osg.samsung.com>
+ * Copyright (C) 2014 Javier Martinez Canillas <javier@dowhile0.org>
  * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include "omap3-igep.dtsi"

diff --git a/arch/arm/dts/omap3-igep0020.dts b/arch/arm/dts/omap3-igep0020.dts
index 33d6b4e..cf3ac84 100644 (file)
--- a/arch/arm/dts/omap3-igep0020.dts
+++ b/arch/arm/dts/omap3-igep0020.dts
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x)
  *
- * Copyright (C) 2012 Javier Martinez Canillas <javier@osg.samsung.com>
+ * Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
  * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include "omap3-igep0020-common.dtsi"

diff --git a/arch/arm/dts/omap3.dtsi b/arch/arm/dts/omap3.dtsi
index 4043ecb..622ee45 100644 (file)
--- a/arch/arm/dts/omap3.dtsi
+++ b/arch/arm/dts/omap3.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP3 SoC
  *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -356,7 +353,7 @@
                        #mbox-cells = <1>;
                        ti,mbox-num-users = <2>;
                        ti,mbox-num-fifos = <2>;
-                       mbox_dsp: dsp {
+                       mbox_dsp: mbox-dsp {
                                ti,mbox-tx = <0 0 0>;
                                ti,mbox-rx = <1 0 0>;
                        };

diff --git a/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi
index 858aa07..5e9d1af 100644 (file)
--- a/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi
+++ b/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP34XX/OMAP36XX clock data
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 &cm_clocks {
        security_l4_ick2: security_l4_ick2 {

diff --git a/arch/arm/dts/omap34xx.dtsi b/arch/arm/dts/omap34xx.dtsi
index a703d09..28ca9c3 100644 (file)
--- a/arch/arm/dts/omap34xx.dtsi
+++ b/arch/arm/dts/omap34xx.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP34xx/OMAP35xx SoC
  *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/media/omap3-isp.h>

diff --git a/arch/arm/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
index 15d1866..9974d52 100644 (file)
--- a/arch/arm/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
+++ b/arch/arm/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 &prm_clocks {
        corex2_d3_fck: corex2_d3_fck {

diff --git a/arch/arm/dts/omap36xx-clocks.dtsi b/arch/arm/dts/omap36xx-clocks.dtsi
index a21d1f0..e66fc57 100644 (file)
--- a/arch/arm/dts/omap36xx-clocks.dtsi
+++ b/arch/arm/dts/omap36xx-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP36xx clock data
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 &cm_clocks {
        dpll4_ck: dpll4_ck@d00 {

diff --git a/arch/arm/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/dts/omap36xx-omap3430es2plus-clocks.dtsi
index 1a4fbdf..945537a 100644 (file)
--- a/arch/arm/dts/omap36xx-omap3430es2plus-clocks.dtsi
+++ b/arch/arm/dts/omap36xx-omap3430es2plus-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP34xx/OMAP36xx clock data
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 &cm_clocks {
        ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 {

diff --git a/arch/arm/dts/omap36xx.dtsi b/arch/arm/dts/omap36xx.dtsi
index 52e1b8c..e5f0207 100644 (file)
--- a/arch/arm/dts/omap36xx.dtsi
+++ b/arch/arm/dts/omap36xx.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP3 SoC
  *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/bus/ti-sysc.h>

diff --git a/arch/arm/dts/omap3xxx-clocks.dtsi b/arch/arm/dts/omap3xxx-clocks.dtsi
index 9bd9164..685c82a 100644 (file)
--- a/arch/arm/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/dts/omap3xxx-clocks.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP3 clock data
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 &prm_clocks {
        virt_16_8m_ck: virt_16_8m_ck {

diff --git a/arch/arm/dts/omap4-cpu-thermal.dtsi b/arch/arm/dts/omap4-cpu-thermal.dtsi
index ab7f87a..801b4f1 100644 (file)
--- a/arch/arm/dts/omap4-cpu-thermal.dtsi
+++ b/arch/arm/dts/omap4-cpu-thermal.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP4/5 SoC CPU thermal
  *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <dt-bindings/thermal/thermal.h>
@@ -16,20 +13,20 @@ cpu_thermal: cpu_thermal {
        polling-delay = <1000>; /* milliseconds */
 
                        /* sensor       ID */
-        thermal-sensors = <&bandgap     0>;
+       thermal-sensors = <&bandgap     0>;
 
        cpu_trips: trips {
-                cpu_alert0: cpu_alert {
-                        temperature = <100000>; /* millicelsius */
-                        hysteresis = <2000>; /* millicelsius */
-                        type = "passive";
-                };
-                cpu_crit: cpu_crit {
-                        temperature = <125000>; /* millicelsius */
-                        hysteresis = <2000>; /* millicelsius */
-                        type = "critical";
-                };
-        };
+               cpu_alert0: cpu_alert {
+                       temperature = <100000>; /* millicelsius */
+                       hysteresis = <2000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu_crit: cpu_crit {
+                       temperature = <125000>; /* millicelsius */
+                       hysteresis = <2000>; /* millicelsius */
+                       type = "critical";
+               };
+       };
 
        cpu_cooling_maps: cooling-maps {
                map0 {

diff --git a/arch/arm/dts/omap4-l4.dtsi b/arch/arm/dts/omap4-l4.dtsi
index 424a694..84d92b8 100644 (file)
--- a/arch/arm/dts/omap4-l4.dtsi
+++ b/arch/arm/dts/omap4-l4.dtsi
@@ -599,11 +599,11 @@
                                #mbox-cells = <1>;
                                ti,mbox-num-users = <3>;
                                ti,mbox-num-fifos = <8>;
-                               mbox_ipu: mbox_ipu {
+                               mbox_ipu: mbox-ipu {
                                        ti,mbox-tx = <0 0 0>;
                                        ti,mbox-rx = <1 0 0>;
                                };
-                               mbox_dsp: mbox_dsp {
+                               mbox_dsp: mbox-dsp {
                                        ti,mbox-tx = <3 0 0>;
                                        ti,mbox-rx = <2 0 0>;
                                };

diff --git a/arch/arm/dts/omap4-panda-common.dtsi b/arch/arm/dts/omap4-panda-common.dtsi
index c124b20..6174fbe 100644 (file)
--- a/arch/arm/dts/omap4-panda-common.dtsi
+++ b/arch/arm/dts/omap4-panda-common.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2011-2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2013 Texas Instruments Incorporated - https://www.ti.com/
  */
 #include <dt-bindings/input/input.h>
 #include "elpida_ecb240abacn.dtsi"
@@ -29,13 +29,13 @@
                        &led_wkgpio_pins
                >;
 
-               heartbeat {
+               led-heartbeat {
                        label = "pandaboard::status1";
                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
                };
 
-               mmc {
+               led-mmc {
                        label = "pandaboard::status2";
                        gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "mmc0";
@@ -538,7 +538,7 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
-               ethernet: usbether@1 {
+               ethernet: ethernet@1 {
                        compatible = "usb424,ec00";
                        reg = <1>;
                };

diff --git a/arch/arm/dts/omap4-panda-es.dts b/arch/arm/dts/omap4-panda-es.dts
index 9dd307b..35e4f34 100644 (file)
--- a/arch/arm/dts/omap4-panda-es.dts
+++ b/arch/arm/dts/omap4-panda-es.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -63,10 +63,10 @@
                &led_wkgpio_pins
        >;
 
-       heartbeat {
+       led-heartbeat {
                gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
        };
-       mmc {
+       led-mmc {
                gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
        };
 };

diff --git a/arch/arm/dts/omap4-panda.dts b/arch/arm/dts/omap4-panda.dts
index fb2f477..529d5bc 100644 (file)
--- a/arch/arm/dts/omap4-panda.dts
+++ b/arch/arm/dts/omap4-panda.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 

diff --git a/arch/arm/dts/omap4-sdp-es23plus.dts b/arch/arm/dts/omap4-sdp-es23plus.dts
index 4215452..869f627 100644 (file)
--- a/arch/arm/dts/omap4-sdp-es23plus.dts
+++ b/arch/arm/dts/omap4-sdp-es23plus.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  */
 #include "omap4-sdp.dts"
 

diff --git a/arch/arm/dts/omap4-sdp.dts b/arch/arm/dts/omap4-sdp.dts
index 28b989c..9e97614 100644 (file)
--- a/arch/arm/dts/omap4-sdp.dts
+++ b/arch/arm/dts/omap4-sdp.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -45,58 +45,60 @@
                regulator-boot-on;
        };
 
-       leds {
+       led-controller-1 {
                compatible = "gpio-leds";
-               debug0 {
+
+               led-1 {
                        label = "omap4:green:debug0";
                        gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */
                };
 
-               debug1 {
+               led-2 {
                        label = "omap4:green:debug1";
                        gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */
                };
 
-               debug2 {
+               led-3 {
                        label = "omap4:green:debug2";
                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */
                };
 
-               debug3 {
+               led-4 {
                        label = "omap4:green:debug3";
                        gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */
                };
 
-               debug4 {
+               led-5 {
                        label = "omap4:green:debug4";
                        gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */
                };
 
-               user1 {
+               led-6 {
                        label = "omap4:blue:user";
                        gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */
                };
 
-               user2 {
+               led-7 {
                        label = "omap4:red:user";
                        gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */
                };
 
-               user3 {
+               led-8 {
                        label = "omap4:green:user";
                        gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */
                };
        };
 
-       pwmleds {
+       led-controller-2 {
                compatible = "pwm-leds";
-               kpad {
+
+               led-9 {
                        label = "omap4::keypad";
                        pwms = <&twl_pwm 0 7812500>;
                        max-brightness = <127>;
                };
 
-               charging {
+               led-10 {
                        label = "omap4:green:chrg";
                        pwms = <&twl_pwmled 0 7812500>;
                        max-brightness = <255>;
@@ -428,7 +430,7 @@
 
        /*
         * Temperature Sensor
-        * http://www.ti.com/lit/ds/symlink/tmp105.pdf
+        * https://www.ti.com/lit/ds/symlink/tmp105.pdf
         */
        tmp105@48 {
                compatible = "ti,tmp105";
@@ -453,7 +455,7 @@
 
        /*
         * 3-Axis Digital Compass
-        * http://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf
+        * https://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf
         */
        hmc5843@1e {
                compatible = "honeywell,hmc5843";
@@ -662,8 +664,9 @@
                };
        };
 
-       lcd0: display {
+       lcd0: panel@0 {
                compatible = "tpo,taal", "panel-dsi-cm";
+               reg = <0>;
                label = "lcd0";
 
                reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;      /* 102 */
@@ -687,8 +690,9 @@
                };
        };
 
-       lcd1: display {
+       lcd1: panel@0 {
                compatible = "tpo,taal", "panel-dsi-cm";
+               reg = <0>;
                label = "lcd1";
 
                reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;      /* 104 */

diff --git a/arch/arm/dts/omap4.dtsi b/arch/arm/dts/omap4.dtsi
index 763bdea..d1ab5f4 100644 (file)
--- a/arch/arm/dts/omap4.dtsi
+++ b/arch/arm/dts/omap4.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/bus/ti-sysc.h>
@@ -71,7 +71,7 @@
                interrupt-parent = <&gic>;
        };
 
-       L2: l2-cache-controller@48242000 {
+       L2: cache-controller@48242000 {
                compatible = "arm,pl310-cache";
                reg = <0x48242000 0x1000>;
                cache-unified;
@@ -389,7 +389,7 @@
                        status = "disabled";
                };
 
-               target-module@56000000 {
+               sgx_module: target-module@56000000 {
                        compatible = "ti,sysc-omap4", "ti,sysc";
                        reg = <0x5600fe00 0x4>,
                              <0x5600fe10 0x4>;
@@ -551,6 +551,9 @@
                                                clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
                                                         <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
                                                clock-names = "fck", "sys_clk";
+
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
                                        };
                                };
 
@@ -583,6 +586,9 @@
                                                clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
                                                         <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
                                                clock-names = "fck", "sys_clk";
+
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
                                        };
                                };
 

diff --git a/arch/arm/dts/omap443x-clocks.dtsi b/arch/arm/dts/omap443x-clocks.dtsi
index 3929786..581e088 100644 (file)
--- a/arch/arm/dts/omap443x-clocks.dtsi
+++ b/arch/arm/dts/omap443x-clocks.dtsi
@@ -8,6 +8,7 @@
        bandgap_fclk: bandgap_fclk@1888 {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
+               clock-output-names = "bandgap_fclk";
                clocks = <&sys_32k_ck>;
                ti,bit-shift = <8>;
                reg = <0x1888>;

diff --git a/arch/arm/dts/omap443x.dtsi b/arch/arm/dts/omap443x.dtsi
index cbcdcb4..a7ee13b 100644 (file)
--- a/arch/arm/dts/omap443x.dtsi
+++ b/arch/arm/dts/omap443x.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP443x SoC
  *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "omap4.dtsi"

diff --git a/arch/arm/dts/omap4460.dtsi b/arch/arm/dts/omap4460.dtsi
index 2223dc0..21ddff9 100644 (file)
--- a/arch/arm/dts/omap4460.dtsi
+++ b/arch/arm/dts/omap4460.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP4460 SoC
  *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  */
 #include "omap4.dtsi"
 

diff --git a/arch/arm/dts/omap5-board-common.dtsi b/arch/arm/dts/omap5-board-common.dtsi
index 1eedd8d..45435bb 100644 (file)
--- a/arch/arm/dts/omap5-board-common.dtsi
+++ b/arch/arm/dts/omap5-board-common.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  */
 #include "omap5.dtsi"
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -149,7 +149,7 @@
 
 &gpio8 {
        /* TI trees use GPIO instead of msecure, see also muxing */
-       p234 {
+       msecure-hog {
                gpio-hog;
                gpios = <10 GPIO_ACTIVE_HIGH>;
                output-high;

diff --git a/arch/arm/dts/omap5-core-thermal.dtsi b/arch/arm/dts/omap5-core-thermal.dtsi
index de8a3d4..e0d8e39 100644 (file)
--- a/arch/arm/dts/omap5-core-thermal.dtsi
+++ b/arch/arm/dts/omap5-core-thermal.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP543x SoC CORE thermal
  *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <dt-bindings/thermal/thermal.h>

diff --git a/arch/arm/dts/omap5-gpu-thermal.dtsi b/arch/arm/dts/omap5-gpu-thermal.dtsi
index bc3090f..1b4b7d9 100644 (file)
--- a/arch/arm/dts/omap5-gpu-thermal.dtsi
+++ b/arch/arm/dts/omap5-gpu-thermal.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP543x SoC GPU thermal
  *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <dt-bindings/thermal/thermal.h>

diff --git a/arch/arm/dts/omap5-l4.dtsi b/arch/arm/dts/omap5-l4.dtsi
index 8582016..4521b64 100644 (file)
--- a/arch/arm/dts/omap5-l4.dtsi
+++ b/arch/arm/dts/omap5-l4.dtsi
@@ -195,7 +195,7 @@
                                #size-cells = <1>;
                                utmi-mode = <2>;
                                ranges = <0 0 0x20000>;
-                               dwc3: dwc3@10000 {
+                               dwc3: usb@10000 {
                                        compatible = "snps,dwc3";
                                        reg = <0x10000 0x10000>;
                                        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
@@ -482,7 +482,7 @@
                                clocks = <&usb_phy_cm_clk32k>,
                                <&sys_clkin>,
                                <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
-                               clock-names =   "wkupclk",
+                               clock-names = "wkupclk",
                                "sysclk",
                                "refclk";
                                #phy-cells = <0>;
@@ -616,11 +616,11 @@
                                #mbox-cells = <1>;
                                ti,mbox-num-users = <3>;
                                ti,mbox-num-fifos = <8>;
-                               mbox_ipu: mbox_ipu {
+                               mbox_ipu: mbox-ipu {
                                        ti,mbox-tx = <0 0 0>;
                                        ti,mbox-rx = <1 0 0>;
                                };
-                               mbox_dsp: mbox_dsp {
+                               mbox_dsp: mbox-dsp {
                                        ti,mbox-tx = <3 0 0>;
                                        ti,mbox-rx = <2 0 0>;
                                };

diff --git a/arch/arm/dts/omap5-uevm.dts b/arch/arm/dts/omap5-uevm.dts
index 9441e9a..b289b57 100644 (file)
--- a/arch/arm/dts/omap5-uevm.dts
+++ b/arch/arm/dts/omap5-uevm.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  */
 /dts-v1/;
 
@@ -189,7 +189,7 @@
                #size-cells = <0>;
        };
 
-       ethernet: usbether@3 {
+       ethernet: ethernet@3 {
                compatible = "usb424,9730";
                reg = <3>;
        };

diff --git a/arch/arm/dts/omap5.dtsi b/arch/arm/dts/omap5.dtsi
index 2ac7f02..76ab2cb 100644 (file)
--- a/arch/arm/dts/omap5.dtsi
+++ b/arch/arm/dts/omap5.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  *
  * Based on "omap4.dtsi"
  */

diff --git a/arch/arm/dts/omap54xx-clocks.dtsi b/arch/arm/dts/omap54xx-clocks.dtsi
index 42f2c44..4dd3c93 100644 (file)
--- a/arch/arm/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/dts/omap54xx-clocks.dtsi
@@ -1118,7 +1118,7 @@
                };
        };
 
-       l4per_cm: l4per_cm@1000 {
+       l4per_cm: clock@1000 {
                compatible = "ti,omap4-cm";
                reg = <0x1000 0x200>;
                #address-cells = <1>;

diff --git a/arch/arm/dts/r8a779f0-spider-cpu.dtsi b/arch/arm/dts/r8a779f0-spider-cpu.dtsi
new file mode 100644 (file)
index 0000000..dd8e0e1
--- /dev/null
+++ b/arch/arm/dts/r8a779f0-spider-cpu.dtsi
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: (GPL-2.0 or MIT)
+/*
+ * Device Tree Source for the Spider CPU board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "r8a779f0.dtsi"
+
+/ {
+       model = "Renesas Spider CPU board";
+       compatible = "renesas,spider-cpu", "renesas,r8a779f0";
+
+       aliases {
+               serial0 = &hscif0;
+               serial1 = &scif0;
+       };
+
+       chosen {
+               bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
+               stdout-path = "serial0:1843200n8";
+       };
+
+       memory@48000000 {
+               device_type = "memory";
+               /* first 128MB is reserved for secure area. */
+               reg = <0x0 0x48000000 0x0 0x78000000>;
+       };
+
+       memory@480000000 {
+               device_type = "memory";
+               reg = <0x4 0x80000000 0x0 0x80000000>;
+       };
+
+       rc21012_ufs: clk-rc21012-ufs {
+               compatible = "fixed-clock";
+               clock-frequency = <38400000>;
+               #clock-cells = <0>;
+       };
+
+       reg_1p8v: regulator-1p8v {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-1.8V";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       reg_3p3v: regulator-3p3v {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-3.3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+};
+
+&extal_clk {
+       clock-frequency = <20000000>;
+};
+
+&extalr_clk {
+       clock-frequency = <32768>;
+};
+
+&hscif0 {
+       pinctrl-0 = <&hscif0_pins>;
+       pinctrl-names = "default";
+
+       uart-has-rtscts;
+       status = "okay";
+};
+
+&i2c0 {
+       pinctrl-0 = <&i2c0_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+       clock-frequency = <400000>;
+
+       gpio_exp_20: gpio@20 {
+               compatible = "ti,tca9554";
+               reg = <0x20>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+};
+
+&i2c4 {
+       pinctrl-0 = <&i2c4_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+       clock-frequency = <400000>;
+
+       eeprom@50 {
+               compatible = "rohm,br24g01", "atmel,24c01";
+               label = "cpu-board";
+               reg = <0x50>;
+               pagesize = <8>;
+       };
+};
+
+/*
+ * This board also has a microSD slot which we will not support upstream
+ * because we cannot directly switch voltages in software.
+ */
+&mmc0 {
+       pinctrl-0 = <&mmc_pins>;
+       pinctrl-1 = <&mmc_pins>;
+       pinctrl-names = "default", "state_uhs";
+
+       vmmc-supply = <&reg_3p3v>;
+       vqmmc-supply = <&reg_1p8v>;
+       mmc-hs200-1_8v;
+       mmc-hs400-1_8v;
+       bus-width = <8>;
+       no-sd;
+       no-sdio;
+       non-removable;
+       full-pwr-cycle-in-suspend;
+       status = "okay";
+};
+
+&pfc {
+       pinctrl-0 = <&scif_clk_pins>;
+       pinctrl-names = "default";
+
+       hscif0_pins: hscif0 {
+               groups = "hscif0_data", "hscif0_ctrl";
+               function = "hscif0";
+       };
+
+       i2c0_pins: i2c0 {
+               groups = "i2c0";
+               function = "i2c0";
+       };
+
+       i2c4_pins: i2c4 {
+               groups = "i2c4";
+               function = "i2c4";
+       };
+
+       mmc_pins: mmc {
+               groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
+               function = "mmc";
+               power-source = <1800>;
+       };
+
+       scif0_pins: scif0 {
+               groups = "scif0_data", "scif0_ctrl";
+               function = "scif0";
+       };
+
+       scif_clk_pins: scif_clk {
+               groups = "scif_clk";
+               function = "scif_clk";
+       };
+};
+
+&rwdt {
+       timeout-sec = <60>;
+       status = "okay";
+};
+
+&scif0 {
+       pinctrl-0 = <&scif0_pins>;
+       pinctrl-names = "default";
+
+       uart-has-rtscts;
+       status = "okay";
+};
+
+&scif_clk {
+       clock-frequency = <24000000>;
+};
+
+&ufs {
+       status = "okay";
+};
+
+&ufs30_clk {
+       compatible = "gpio-gate-clock";
+       clocks = <&rc21012_ufs>;
+       enable-gpios = <&gpio_exp_20 4 GPIO_ACTIVE_LOW>;
+       /delete-property/ clock-frequency;
+};

diff --git a/arch/arm/dts/r8a779f0-spider-ethernet.dtsi b/arch/arm/dts/r8a779f0-spider-ethernet.dtsi
new file mode 100644 (file)
index 0000000..33c1015
--- /dev/null
+++ b/arch/arm/dts/r8a779f0-spider-ethernet.dtsi
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Spider Ethernet sub-board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+&eth_serdes {
+       status = "okay";
+};
+
+&i2c4 {
+       eeprom@52 {
+               compatible = "rohm,br24g01", "atmel,24c01";
+               label = "ethernet-sub-board";
+               reg = <0x52>;
+               pagesize = <8>;
+       };
+};
+
+&pfc {
+       tsn0_pins: tsn0 {
+               groups = "tsn0_mdio_b", "tsn0_link_b";
+               function = "tsn0";
+               power-source = <1800>;
+       };
+
+       tsn1_pins: tsn1 {
+               groups = "tsn1_mdio_b", "tsn1_link_b";
+               function = "tsn1";
+               power-source = <1800>;
+       };
+
+       tsn2_pins: tsn2 {
+               groups = "tsn2_mdio_b", "tsn2_link_b";
+               function = "tsn2";
+               power-source = <1800>;
+       };
+};
+
+&rswitch {
+       pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+
+       ethernet-ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               port@0 {
+                       reg = <0>;
+                       phy-handle = <&u101>;
+                       phy-mode = "sgmii";
+                       phys = <&eth_serdes 0>;
+
+                       mdio {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               u101: ethernet-phy@1 {
+                                       reg = <1>;
+                                       compatible = "ethernet-phy-ieee802.3-c45";
+                                       interrupt-parent = <&gpio3>;
+                                       interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+                               };
+                       };
+               };
+               port@1 {
+                       reg = <1>;
+                       phy-handle = <&u201>;
+                       phy-mode = "sgmii";
+                       phys = <&eth_serdes 1>;
+
+                       mdio {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               u201: ethernet-phy@2 {
+                                       reg = <2>;
+                                       compatible = "ethernet-phy-ieee802.3-c45";
+                                       interrupt-parent = <&gpio3>;
+                                       interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+                               };
+                       };
+               };
+               port@2 {
+                       reg = <2>;
+                       phy-handle = <&u301>;
+                       phy-mode = "sgmii";
+                       phys = <&eth_serdes 2>;
+
+                       mdio {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               u301: ethernet-phy@3 {
+                                       reg = <3>;
+                                       compatible = "ethernet-phy-ieee802.3-c45";
+                                       interrupt-parent = <&gpio3>;
+                                       interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+                               };
+                       };
+               };
+       };
+};

diff --git a/arch/arm/dts/r8a779f0-spider-u-boot.dts b/arch/arm/dts/r8a779f0-spider-u-boot.dts
new file mode 100644 (file)
index 0000000..26fc8bc
--- /dev/null
+++ b/arch/arm/dts/r8a779f0-spider-u-boot.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Spider board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a779f0-spider.dts"
+#include "r8a779f0-u-boot.dtsi"
+
+/ {
+       aliases {
+               spi0 = &rpc;
+       };
+};
+
+&pfc {
+       qspi0_pins: qspi0 {
+               groups = "qspi0_ctrl", "qspi0_data4";
+               function = "qspi0";
+       };
+};
+
+&rpc {
+       pinctrl-0 = <&qspi0_pins>;
+       pinctrl-names = "default";
+
+       #address-cells = <1>;
+       #size-cells = <0>;
+       spi-max-frequency = <40000000>;
+       status = "okay";
+
+       spi-flash@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "s25fs512s", "jedec,spi-nor";
+               reg = <0>;
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <1>;
+               spi-max-frequency = <40000000>;
+       };
+};

diff --git a/arch/arm/dts/r8a779f0-spider.dts b/arch/arm/dts/r8a779f0-spider.dts
new file mode 100644 (file)
index 0000000..7aac3f4
--- /dev/null
+++ b/arch/arm/dts/r8a779f0-spider.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 or MIT)
+/*
+ * Device Tree Source for the Spider CPU and BreakOut boards
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a779f0-spider-cpu.dtsi"
+#include "r8a779f0-spider-ethernet.dtsi"
+
+/ {
+       model = "Renesas Spider CPU and Breakout boards based on r8a779f0";
+       compatible = "renesas,spider-breakout", "renesas,spider-cpu", "renesas,r8a779f0";
+};
+
+&i2c4 {
+       eeprom@51 {
+               compatible = "rohm,br24g01", "atmel,24c01";
+               label = "breakout-board";
+               reg = <0x51>;
+               pagesize = <8>;
+       };
+};

diff --git a/arch/arm/dts/r8a779f0-u-boot.dtsi b/arch/arm/dts/r8a779f0-u-boot.dtsi
new file mode 100644 (file)
index 0000000..0f98c09
--- /dev/null
+++ b/arch/arm/dts/r8a779f0-u-boot.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on R-Car R8A779F0 SoC
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+/ {
+       soc {
+               rpc: spi@ee200000 {
+                       compatible = "renesas,r8a779f0-rpc-if", "renesas,rcar-gen4-rpc-if";
+                       reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
+                       interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 629>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 629>;
+                       bank-width = <2>;
+                       num-cs = <1>;
+                       status = "disabled";
+               };
+       };
+};
+
+&extalr_clk {
+       bootph-all;
+};

diff --git a/arch/arm/dts/r8a779f0.dtsi b/arch/arm/dts/r8a779f0.dtsi
new file mode 100644 (file)
index 0000000..f20b612
--- /dev/null
+++ b/arch/arm/dts/r8a779f0.dtsi
@@ -0,0 +1,1179 @@
+// SPDX-License-Identifier: (GPL-2.0 or MIT)
+/*
+ * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a779f0-sysc.h>
+
+/ {
+       compatible = "renesas,r8a779f0";
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       cluster01_opp: opp-table-0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-500000000 {
+                       opp-hz = /bits/ 64 <500000000>;
+                       opp-microvolt = <880000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp-800000000 {
+                       opp-hz = /bits/ 64 <800000000>;
+                       opp-microvolt = <880000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp-1000000000 {
+                       opp-hz = /bits/ 64 <1000000000>;
+                       opp-microvolt = <880000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp-1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <880000>;
+                       clock-latency-ns = <500000>;
+                       opp-suspend;
+               };
+       };
+
+       cluster23_opp: opp-table-1 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-500000000 {
+                       opp-hz = /bits/ 64 <500000000>;
+                       opp-microvolt = <880000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp-800000000 {
+                       opp-hz = /bits/ 64 <800000000>;
+                       opp-microvolt = <880000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp-1000000000 {
+                       opp-hz = /bits/ 64 <1000000000>;
+                       opp-microvolt = <880000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp-1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <880000>;
+                       clock-latency-ns = <500000>;
+                       opp-suspend;
+               };
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu-map {
+                       cluster0 {
+                               core0 {
+                                       cpu = <&a55_0>;
+                               };
+                               core1 {
+                                       cpu = <&a55_1>;
+                               };
+                       };
+
+                       cluster1 {
+                               core0 {
+                                       cpu = <&a55_2>;
+                               };
+                               core1 {
+                                       cpu = <&a55_3>;
+                               };
+                       };
+
+                       cluster2 {
+                               core0 {
+                                       cpu = <&a55_4>;
+                               };
+                               core1 {
+                                       cpu = <&a55_5>;
+                               };
+                       };
+
+                       cluster3 {
+                               core0 {
+                                       cpu = <&a55_6>;
+                               };
+                               core1 {
+                                       cpu = <&a55_7>;
+                               };
+                       };
+               };
+
+               a55_0: cpu@0 {
+                       compatible = "arm,cortex-a55";
+                       reg = <0>;
+                       device_type = "cpu";
+                       power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
+                       next-level-cache = <&L3_CA55_0>;
+                       enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
+                       clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
+                       operating-points-v2 = <&cluster01_opp>;
+               };
+
+               a55_1: cpu@100 {
+                       compatible = "arm,cortex-a55";
+                       reg = <0x100>;
+                       device_type = "cpu";
+                       power-domains = <&sysc R8A779F0_PD_A1E0D0C1>;
+                       next-level-cache = <&L3_CA55_0>;
+                       enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
+                       clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
+                       operating-points-v2 = <&cluster01_opp>;
+               };
+
+               a55_2: cpu@10000 {
+                       compatible = "arm,cortex-a55";
+                       reg = <0x10000>;
+                       device_type = "cpu";
+                       power-domains = <&sysc R8A779F0_PD_A1E0D1C0>;
+                       next-level-cache = <&L3_CA55_1>;
+                       enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
+                       clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
+                       operating-points-v2 = <&cluster01_opp>;
+               };
+
+               a55_3: cpu@10100 {
+                       compatible = "arm,cortex-a55";
+                       reg = <0x10100>;
+                       device_type = "cpu";
+                       power-domains = <&sysc R8A779F0_PD_A1E0D1C1>;
+                       next-level-cache = <&L3_CA55_1>;
+                       enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
+                       clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
+                       operating-points-v2 = <&cluster01_opp>;
+               };
+
+               a55_4: cpu@20000 {
+                       compatible = "arm,cortex-a55";
+                       reg = <0x20000>;
+                       device_type = "cpu";
+                       power-domains = <&sysc R8A779F0_PD_A1E1D0C0>;
+                       next-level-cache = <&L3_CA55_2>;
+                       enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
+                       clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
+                       operating-points-v2 = <&cluster23_opp>;
+               };
+
+               a55_5: cpu@20100 {
+                       compatible = "arm,cortex-a55";
+                       reg = <0x20100>;
+                       device_type = "cpu";
+                       power-domains = <&sysc R8A779F0_PD_A1E1D0C1>;
+                       next-level-cache = <&L3_CA55_2>;
+                       enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
+                       clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
+                       operating-points-v2 = <&cluster23_opp>;
+               };
+
+               a55_6: cpu@30000 {
+                       compatible = "arm,cortex-a55";
+                       reg = <0x30000>;
+                       device_type = "cpu";
+                       power-domains = <&sysc R8A779F0_PD_A1E1D1C0>;
+                       next-level-cache = <&L3_CA55_3>;
+                       enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
+                       clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
+                       operating-points-v2 = <&cluster23_opp>;
+               };
+
+               a55_7: cpu@30100 {
+                       compatible = "arm,cortex-a55";
+                       reg = <0x30100>;
+                       device_type = "cpu";
+                       power-domains = <&sysc R8A779F0_PD_A1E1D1C1>;
+                       next-level-cache = <&L3_CA55_3>;
+                       enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
+                       clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
+                       operating-points-v2 = <&cluster23_opp>;
+               };
+
+               L3_CA55_0: cache-controller-0 {
+                       compatible = "cache";
+                       power-domains = <&sysc R8A779F0_PD_A2E0D0>;
+                       cache-unified;
+                       cache-level = <3>;
+               };
+
+               L3_CA55_1: cache-controller-1 {
+                       compatible = "cache";
+                       power-domains = <&sysc R8A779F0_PD_A2E0D1>;
+                       cache-unified;
+                       cache-level = <3>;
+               };
+
+               L3_CA55_2: cache-controller-2 {
+                       compatible = "cache";
+                       power-domains = <&sysc R8A779F0_PD_A2E1D0>;
+                       cache-unified;
+                       cache-level = <3>;
+               };
+
+               L3_CA55_3: cache-controller-3 {
+                       compatible = "cache";
+                       power-domains = <&sysc R8A779F0_PD_A2E1D1>;
+                       cache-unified;
+                       cache-level = <3>;
+               };
+
+               idle-states {
+                       entry-method = "psci";
+
+                       CPU_SLEEP_0: cpu-sleep-0 {
+                               compatible = "arm,idle-state";
+                               arm,psci-suspend-param = <0x0010000>;
+                               local-timer-stop;
+                               entry-latency-us = <400>;
+                               exit-latency-us = <500>;
+                               min-residency-us = <4000>;
+                       };
+               };
+       };
+
+       extal_clk: extal {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       extalr_clk: extalr {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       pmu_a55 {
+               compatible = "arm,cortex-a55-pmu";
+               interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       psci {
+               compatible = "arm,psci-1.0", "arm,psci-0.2";
+               method = "smc";
+       };
+
+       /* External SCIF clock - to be overridden by boards that provide it */
+       scif_clk: scif {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+       };
+
+       soc: soc {
+               compatible = "simple-bus";
+               interrupt-parent = <&gic>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               rwdt: watchdog@e6020000 {
+                       compatible = "renesas,r8a779f0-wdt",
+                                    "renesas,rcar-gen4-wdt";
+                       reg = <0 0xe6020000 0 0x0c>;
+                       interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 907>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 907>;
+                       status = "disabled";
+               };
+
+               pfc: pinctrl@e6050000 {
+                       compatible = "renesas,pfc-r8a779f0";
+                       reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
+                             <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>;
+               };
+
+               gpio0: gpio@e6050180 {
+                       compatible = "renesas,gpio-r8a779f0",
+                                    "renesas,rcar-gen4-gpio";
+                       reg = <0 0xe6050180 0 0x54>;
+                       interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 915>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 915>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&pfc 0 0 21>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio1: gpio@e6050980 {
+                       compatible = "renesas,gpio-r8a779f0",
+                                    "renesas,rcar-gen4-gpio";
+                       reg = <0 0xe6050980 0 0x54>;
+                       interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 915>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 915>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&pfc 0 32 25>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio2: gpio@e6051180 {
+                       compatible = "renesas,gpio-r8a779f0",
+                                    "renesas,rcar-gen4-gpio";
+                       reg = <0 0xe6051180 0 0x54>;
+                       interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 915>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 915>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&pfc 0 64 17>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio3: gpio@e6051980 {
+                       compatible = "renesas,gpio-r8a779f0",
+                                    "renesas,rcar-gen4-gpio";
+                       reg = <0 0xe6051980 0 0x54>;
+                       interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 915>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 915>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&pfc 0 96 19>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               cmt0: timer@e60f0000 {
+                       compatible = "renesas,r8a779f0-cmt0",
+                                    "renesas,rcar-gen4-cmt0";
+                       reg = <0 0xe60f0000 0 0x1004>;
+                       interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 910>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 910>;
+                       status = "disabled";
+               };
+
+               cmt1: timer@e6130000 {
+                       compatible = "renesas,r8a779f0-cmt1",
+                                    "renesas,rcar-gen4-cmt1";
+                       reg = <0 0xe6130000 0 0x1004>;
+                       interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 911>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 911>;
+                       status = "disabled";
+               };
+
+               cmt2: timer@e6140000 {
+                       compatible = "renesas,r8a779f0-cmt1",
+                                    "renesas,rcar-gen4-cmt1";
+                       reg = <0 0xe6140000 0 0x1004>;
+                       interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 912>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 912>;
+                       status = "disabled";
+               };
+
+               cmt3: timer@e6148000 {
+                       compatible = "renesas,r8a779f0-cmt1",
+                                    "renesas,rcar-gen4-cmt1";
+                       reg = <0 0xe6148000 0 0x1004>;
+                       interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 913>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 913>;
+                       status = "disabled";
+               };
+
+               cpg: clock-controller@e6150000 {
+                       compatible = "renesas,r8a779f0-cpg-mssr";
+                       reg = <0 0xe6150000 0 0x4000>;
+                       clocks = <&extal_clk>, <&extalr_clk>;
+                       clock-names = "extal", "extalr";
+                       #clock-cells = <2>;
+                       #power-domain-cells = <0>;
+                       #reset-cells = <1>;
+               };
+
+               rst: reset-controller@e6160000 {
+                       compatible = "renesas,r8a779f0-rst";
+                       reg = <0 0xe6160000 0 0x4000>;
+               };
+
+               sysc: system-controller@e6180000 {
+                       compatible = "renesas,r8a779f0-sysc";
+                       reg = <0 0xe6180000 0 0x4000>;
+                       #power-domain-cells = <1>;
+               };
+
+               tsc: thermal@e6198000 {
+                       compatible = "renesas,r8a779f0-thermal";
+                       /* The 4th sensor is in control domain and not for Linux */
+                       reg = <0 0xe6198000 0 0x200>,
+                             <0 0xe61a0000 0 0x200>,
+                             <0 0xe61a8000 0 0x200>;
+                       clocks = <&cpg CPG_MOD 919>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 919>;
+                       #thermal-sensor-cells = <1>;
+               };
+
+               tmu0: timer@e61e0000 {
+                       compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
+                       reg = <0 0xe61e0000 0 0x30>;
+                       interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 713>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 713>;
+                       status = "disabled";
+               };
+
+               tmu1: timer@e6fc0000 {
+                       compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
+                       reg = <0 0xe6fc0000 0 0x30>;
+                       interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 714>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 714>;
+                       status = "disabled";
+               };
+
+               tmu2: timer@e6fd0000 {
+                       compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
+                       reg = <0 0xe6fd0000 0 0x30>;
+                       interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 715>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 715>;
+                       status = "disabled";
+               };
+
+               tmu3: timer@e6fe0000 {
+                       compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
+                       reg = <0 0xe6fe0000 0 0x30>;
+                       interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 716>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 716>;
+                       status = "disabled";
+               };
+
+               tmu4: timer@ffc00000 {
+                       compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
+                       reg = <0 0xffc00000 0 0x30>;
+                       interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 717>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 717>;
+                       status = "disabled";
+               };
+
+               eth_serdes: phy@e6444000 {
+                       compatible = "renesas,r8a779f0-ether-serdes";
+                       reg = <0 0xe6444000 0 0x2800>;
+                       clocks = <&cpg CPG_MOD 1506>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 1506>;
+                       #phy-cells = <1>;
+                       status = "disabled";
+               };
+
+               i2c0: i2c@e6500000 {
+                       compatible = "renesas,i2c-r8a779f0",
+                                    "renesas,rcar-gen4-i2c";
+                       reg = <0 0xe6500000 0 0x40>;
+                       interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 518>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 518>;
+                       dmas = <&dmac0 0x91>, <&dmac0 0x90>,
+                              <&dmac1 0x91>, <&dmac1 0x90>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       i2c-scl-internal-delay-ns = <110>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c1: i2c@e6508000 {
+                       compatible = "renesas,i2c-r8a779f0",
+                                    "renesas,rcar-gen4-i2c";
+                       reg = <0 0xe6508000 0 0x40>;
+                       interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 519>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 519>;
+                       dmas = <&dmac0 0x93>, <&dmac0 0x92>,
+                              <&dmac1 0x93>, <&dmac1 0x92>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       i2c-scl-internal-delay-ns = <110>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c2: i2c@e6510000 {
+                       compatible = "renesas,i2c-r8a779f0",
+                                    "renesas,rcar-gen4-i2c";
+                       reg = <0 0xe6510000 0 0x40>;
+                       interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 520>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 520>;
+                       dmas = <&dmac0 0x95>, <&dmac0 0x94>,
+                              <&dmac1 0x95>, <&dmac1 0x94>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       i2c-scl-internal-delay-ns = <110>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c3: i2c@e66d0000 {
+                       compatible = "renesas,i2c-r8a779f0",
+                                    "renesas,rcar-gen4-i2c";
+                       reg = <0 0xe66d0000 0 0x40>;
+                       interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 521>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 521>;
+                       dmas = <&dmac0 0x97>, <&dmac0 0x96>,
+                              <&dmac1 0x97>, <&dmac1 0x96>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       i2c-scl-internal-delay-ns = <110>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c4: i2c@e66d8000 {
+                       compatible = "renesas,i2c-r8a779f0",
+                                    "renesas,rcar-gen4-i2c";
+                       reg = <0 0xe66d8000 0 0x40>;
+                       interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 522>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 522>;
+                       dmas = <&dmac0 0x99>, <&dmac0 0x98>,
+                              <&dmac1 0x99>, <&dmac1 0x98>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       i2c-scl-internal-delay-ns = <110>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c5: i2c@e66e0000 {
+                       compatible = "renesas,i2c-r8a779f0",
+                                    "renesas,rcar-gen4-i2c";
+                       reg = <0 0xe66e0000 0 0x40>;
+                       interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 523>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 523>;
+                       dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
+                              <&dmac1 0x9b>, <&dmac1 0x9a>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       i2c-scl-internal-delay-ns = <110>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               hscif0: serial@e6540000 {
+                       compatible = "renesas,hscif-r8a779f0",
+                                    "renesas,rcar-gen4-hscif", "renesas,hscif";
+                       reg = <0 0xe6540000 0 0x60>;
+                       interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 514>,
+                                <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x31>, <&dmac0 0x30>,
+                              <&dmac1 0x31>, <&dmac1 0x30>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 514>;
+                       status = "disabled";
+               };
+
+               hscif1: serial@e6550000 {
+                       compatible = "renesas,hscif-r8a779f0",
+                                    "renesas,rcar-gen4-hscif", "renesas,hscif";
+                       reg = <0 0xe6550000 0 0x60>;
+                       interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 515>,
+                                <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x33>, <&dmac0 0x32>,
+                              <&dmac1 0x33>, <&dmac1 0x32>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 515>;
+                       status = "disabled";
+               };
+
+               hscif2: serial@e6560000 {
+                       compatible = "renesas,hscif-r8a779f0",
+                                    "renesas,rcar-gen4-hscif", "renesas,hscif";
+                       reg = <0 0xe6560000 0 0x60>;
+                       interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 516>,
+                                <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x35>, <&dmac0 0x34>,
+                              <&dmac1 0x35>, <&dmac1 0x34>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 516>;
+                       status = "disabled";
+               };
+
+               hscif3: serial@e66a0000 {
+                       compatible = "renesas,hscif-r8a779f0",
+                                    "renesas,rcar-gen4-hscif", "renesas,hscif";
+                       reg = <0 0xe66a0000 0 0x60>;
+                       interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 517>,
+                                <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x37>, <&dmac0 0x36>,
+                              <&dmac1 0x37>, <&dmac1 0x36>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 517>;
+                       status = "disabled";
+               };
+
+               ufs: ufs@e6860000 {
+                       compatible = "renesas,r8a779f0-ufs";
+                       reg = <0 0xe6860000 0 0x100>;
+                       interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>;
+                       clock-names = "fck", "ref_clk";
+                       freq-table-hz = <200000000 200000000>, <38400000 38400000>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 1514>;
+                       status = "disabled";
+               };
+
+               rswitch: ethernet@e6880000 {
+                       compatible = "renesas,r8a779f0-ether-switch";
+                       reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>;
+                       reg-names = "base", "secure_base";
+                       interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "mfwd_error", "race_error",
+                                         "coma_error", "gwca0_error",
+                                         "gwca1_error", "etha0_error",
+                                         "etha1_error", "etha2_error",
+                                         "gptp0_status", "gptp1_status",
+                                         "mfwd_status", "race_status",
+                                         "coma_status", "gwca0_status",
+                                         "gwca1_status", "etha0_status",
+                                         "etha1_status", "etha2_status",
+                                         "rmac0_status", "rmac1_status",
+                                         "rmac2_status",
+                                         "gwca0_rxtx0", "gwca0_rxtx1",
+                                         "gwca0_rxtx2", "gwca0_rxtx3",
+                                         "gwca0_rxtx4", "gwca0_rxtx5",
+                                         "gwca0_rxtx6", "gwca0_rxtx7",
+                                         "gwca1_rxtx0", "gwca1_rxtx1",
+                                         "gwca1_rxtx2", "gwca1_rxtx3",
+                                         "gwca1_rxtx4", "gwca1_rxtx5",
+                                         "gwca1_rxtx6", "gwca1_rxtx7",
+                                         "gwca0_rxts0", "gwca0_rxts1",
+                                         "gwca1_rxts0", "gwca1_rxts1",
+                                         "rmac0_mdio", "rmac1_mdio",
+                                         "rmac2_mdio",
+                                         "rmac0_phy", "rmac1_phy",
+                                         "rmac2_phy";
+                       clocks = <&cpg CPG_MOD 1505>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 1505>;
+                       status = "disabled";
+
+                       ethernet-ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       phys = <&eth_serdes 0>;
+                               };
+                               port@1 {
+                                       reg = <1>;
+                                       phys = <&eth_serdes 1>;
+                               };
+                               port@2 {
+                                       reg = <2>;
+                                       phys = <&eth_serdes 2>;
+                               };
+                       };
+               };
+
+               scif0: serial@e6e60000 {
+                       compatible = "renesas,scif-r8a779f0",
+                                    "renesas,rcar-gen4-scif", "renesas,scif";
+                       reg = <0 0xe6e60000 0 64>;
+                       interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 702>,
+                                <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x51>, <&dmac0 0x50>,
+                              <&dmac1 0x51>, <&dmac1 0x50>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 702>;
+                       status = "disabled";
+               };
+
+               scif1: serial@e6e68000 {
+                       compatible = "renesas,scif-r8a779f0",
+                                    "renesas,rcar-gen4-scif", "renesas,scif";
+                       reg = <0 0xe6e68000 0 64>;
+                       interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 703>,
+                                <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x53>, <&dmac0 0x52>,
+                              <&dmac1 0x53>, <&dmac1 0x52>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 703>;
+                       status = "disabled";
+               };
+
+               scif3: serial@e6c50000 {
+                       compatible = "renesas,scif-r8a779f0",
+                                    "renesas,rcar-gen4-scif", "renesas,scif";
+                       reg = <0 0xe6c50000 0 64>;
+                       interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 704>,
+                                <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x57>, <&dmac0 0x56>,
+                              <&dmac1 0x57>, <&dmac1 0x56>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 704>;
+                       status = "disabled";
+               };
+
+               scif4: serial@e6c40000 {
+                       compatible = "renesas,scif-r8a779f0",
+                                    "renesas,rcar-gen4-scif", "renesas,scif";
+                       reg = <0 0xe6c40000 0 64>;
+                       interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 705>,
+                                <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x59>, <&dmac0 0x58>,
+                              <&dmac1 0x59>, <&dmac1 0x58>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 705>;
+                       status = "disabled";
+               };
+
+               msiof0: spi@e6e90000 {
+                       compatible = "renesas,msiof-r8a779f0",
+                                    "renesas,rcar-gen4-msiof";
+                       reg = <0 0xe6e90000 0 0x0064>;
+                       interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 618>;
+                       dmas = <&dmac0 0x41>, <&dmac0 0x40>,
+                              <&dmac1 0x41>, <&dmac1 0x40>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 618>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               msiof1: spi@e6ea0000 {
+                       compatible = "renesas,msiof-r8a779f0",
+                                    "renesas,rcar-gen4-msiof";
+                       reg = <0 0xe6ea0000 0 0x0064>;
+                       interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 619>;
+                       dmas = <&dmac0 0x43>, <&dmac0 0x42>,
+                              <&dmac1 0x43>, <&dmac1 0x42>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 619>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               msiof2: spi@e6c00000 {
+                       compatible = "renesas,msiof-r8a779f0",
+                                    "renesas,rcar-gen4-msiof";
+                       reg = <0 0xe6c00000 0 0x0064>;
+                       interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 620>;
+                       dmas = <&dmac0 0x45>, <&dmac0 0x44>,
+                              <&dmac1 0x45>, <&dmac1 0x44>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 620>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               msiof3: spi@e6c10000 {
+                       compatible = "renesas,msiof-r8a779f0",
+                                    "renesas,rcar-gen4-msiof";
+                       reg = <0 0xe6c10000 0 0x0064>;
+                       interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 621>;
+                       dmas = <&dmac0 0x47>, <&dmac0 0x46>,
+                              <&dmac1 0x47>, <&dmac1 0x46>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 621>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               dmac0: dma-controller@e7350000 {
+                       compatible = "renesas,dmac-r8a779f0",
+                                    "renesas,rcar-gen4-dmac";
+                       reg = <0 0xe7350000 0 0x1000>,
+                             <0 0xe7300000 0 0x10000>;
+                       interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "error",
+                                         "ch0", "ch1", "ch2", "ch3", "ch4",
+                                         "ch5", "ch6", "ch7", "ch8", "ch9",
+                                         "ch10", "ch11", "ch12", "ch13",
+                                         "ch14", "ch15";
+                       clocks = <&cpg CPG_MOD 709>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 709>;
+                       #dma-cells = <1>;
+                       dma-channels = <16>;
+                       iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
+                                <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
+                                <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
+                                <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
+                                <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
+                                <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
+                                <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
+                                <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
+               };
+
+               dmac1: dma-controller@e7351000 {
+                       compatible = "renesas,dmac-r8a779f0",
+                                    "renesas,rcar-gen4-dmac";
+                       reg = <0 0xe7351000 0 0x1000>,
+                             <0 0xe7310000 0 0x10000>;
+                       interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "error",
+                                         "ch0", "ch1", "ch2", "ch3", "ch4",
+                                         "ch5", "ch6", "ch7", "ch8", "ch9",
+                                         "ch10", "ch11", "ch12", "ch13",
+                                         "ch14", "ch15";
+                       clocks = <&cpg CPG_MOD 710>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 710>;
+                       #dma-cells = <1>;
+                       dma-channels = <16>;
+                       iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
+                                <&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
+                                <&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
+                                <&ipmmu_ds0 22>, <&ipmmu_ds0 23>,
+                                <&ipmmu_ds0 24>, <&ipmmu_ds0 25>,
+                                <&ipmmu_ds0 26>, <&ipmmu_ds0 27>,
+                                <&ipmmu_ds0 28>, <&ipmmu_ds0 29>,
+                                <&ipmmu_ds0 30>, <&ipmmu_ds0 31>;
+               };
+
+               mmc0: mmc@ee140000 {
+                       compatible = "renesas,sdhi-r8a779f0",
+                                    "renesas,rcar-gen4-sdhi";
+                       reg = <0 0xee140000 0 0x2000>;
+                       interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>;
+                       clock-names = "core", "clkh";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 706>;
+                       max-frequency = <200000000>;
+                       iommus = <&ipmmu_ds0 32>;
+                       status = "disabled";
+               };
+
+               ipmmu_rt0: iommu@ee480000 {
+                       compatible = "renesas,ipmmu-r8a779f0",
+                                    "renesas,rcar-gen4-ipmmu-vmsa";
+                       reg = <0 0xee480000 0 0x20000>;
+                       renesas,ipmmu-main = <&ipmmu_mm 10>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       #iommu-cells = <1>;
+               };
+
+               ipmmu_rt1: iommu@ee4c0000 {
+                       compatible = "renesas,ipmmu-r8a779f0",
+                                    "renesas,rcar-gen4-ipmmu-vmsa";
+                       reg = <0 0xee4c0000 0 0x20000>;
+                       renesas,ipmmu-main = <&ipmmu_mm 19>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       #iommu-cells = <1>;
+               };
+
+               ipmmu_ds0: iommu@eed00000 {
+                       compatible = "renesas,ipmmu-r8a779f0",
+                                    "renesas,rcar-gen4-ipmmu-vmsa";
+                       reg = <0 0xeed00000 0 0x20000>;
+                       renesas,ipmmu-main = <&ipmmu_mm 0>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       #iommu-cells = <1>;
+               };
+
+               ipmmu_hc: iommu@eed40000 {
+                       compatible = "renesas,ipmmu-r8a779f0",
+                                    "renesas,rcar-gen4-ipmmu-vmsa";
+                       reg = <0 0xeed40000 0 0x20000>;
+                       renesas,ipmmu-main = <&ipmmu_mm 2>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       #iommu-cells = <1>;
+               };
+
+               ipmmu_mm: iommu@eefc0000 {
+                       compatible = "renesas,ipmmu-r8a779f0",
+                                    "renesas,rcar-gen4-ipmmu-vmsa";
+                       reg = <0 0xeefc0000 0 0x20000>;
+                       interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       #iommu-cells = <1>;
+               };
+
+               gic: interrupt-controller@f1000000 {
+                       compatible = "arm,gic-v3";
+                       #interrupt-cells = <3>;
+                       #address-cells = <0>;
+                       interrupt-controller;
+                       reg = <0x0 0xf1000000 0 0x20000>,
+                             <0x0 0xf1060000 0 0x110000>;
+                       interrupts = <GIC_PPI 9
+                                     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+               };
+
+               prr: chipid@fff00044 {
+                       compatible = "renesas,prr";
+                       reg = <0 0xfff00044 0 4>;
+               };
+       };
+
+       thermal-zones {
+               sensor_thermal1: sensor1-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+                       thermal-sensors = <&tsc 0>;
+
+                       trips {
+                               sensor1_crit: sensor1-crit {
+                                       temperature = <120000>;
+                                       hysteresis = <1000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               sensor_thermal2: sensor2-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+                       thermal-sensors = <&tsc 1>;
+
+                       trips {
+                               sensor2_crit: sensor2-crit {
+                                       temperature = <120000>;
+                                       hysteresis = <1000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               sensor_thermal3: sensor3-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+                       thermal-sensors = <&tsc 2>;
+
+                       trips {
+                               sensor3_crit: sensor3-crit {
+                                       temperature = <120000>;
+                                       hysteresis = <1000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+       };
+
+       ufs30_clk: ufs30-clk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+};

diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi
new file mode 100644 (file)
index 0000000..150657f
--- /dev/null
+++ b/arch/arm/dts/r8a779g0-u-boot.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on R-Car R8A779G0 SoC
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+/ {
+       soc {
+               rpc: spi@ee200000 {
+                       compatible = "renesas,r8a779g0-rpc-if", "renesas,rcar-gen4-rpc-if";
+                       reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
+                       interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 629>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 629>;
+                       bank-width = <2>;
+                       num-cs = <1>;
+                       status = "disabled";
+               };
+       };
+};
+
+&extalr_clk {
+       bootph-all;
+};

diff --git a/arch/arm/dts/r8a779g0-white-hawk-cpu.dtsi b/arch/arm/dts/r8a779g0-white-hawk-cpu.dtsi
new file mode 100644 (file)
index 0000000..bb4a527
--- /dev/null
+++ b/arch/arm/dts/r8a779g0-white-hawk-cpu.dtsi
@@ -0,0 +1,375 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the White Hawk CPU board
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include "r8a779g0.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+       model = "Renesas White Hawk CPU board";
+       compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0";
+
+       aliases {
+               ethernet0 = &avb0;
+               serial0 = &hscif0;
+       };
+
+       chosen {
+               bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
+               stdout-path = "serial0:921600n8";
+       };
+
+       keys {
+               compatible = "gpio-keys";
+
+               pinctrl-0 = <&keys_pins>;
+               pinctrl-names = "default";
+
+               key-1 {
+                       gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_1>;
+                       label = "SW47";
+                       wakeup-source;
+                       debounce-interval = <20>;
+               };
+
+               key-2 {
+                       gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_2>;
+                       label = "SW48";
+                       wakeup-source;
+                       debounce-interval = <20>;
+               };
+
+               key-3 {
+                       gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_3>;
+                       label = "SW49";
+                       wakeup-source;
+                       debounce-interval = <20>;
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               led-1 {
+                       gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
+                       color = <LED_COLOR_ID_GREEN>;
+                       function = LED_FUNCTION_INDICATOR;
+                       function-enumerator = <1>;
+               };
+
+               led-2 {
+                       gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
+                       color = <LED_COLOR_ID_GREEN>;
+                       function = LED_FUNCTION_INDICATOR;
+                       function-enumerator = <2>;
+               };
+
+               led-3 {
+                       gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
+                       color = <LED_COLOR_ID_GREEN>;
+                       function = LED_FUNCTION_INDICATOR;
+                       function-enumerator = <3>;
+               };
+       };
+
+       memory@48000000 {
+               device_type = "memory";
+               /* first 128MB is reserved for secure area. */
+               reg = <0x0 0x48000000 0x0 0x78000000>;
+       };
+
+       memory@480000000 {
+               device_type = "memory";
+               reg = <0x4 0x80000000 0x0 0x80000000>;
+       };
+
+       memory@600000000 {
+               device_type = "memory";
+               reg = <0x6 0x00000000 0x1 0x00000000>;
+       };
+
+       mini-dp-con {
+               compatible = "dp-connector";
+               label = "CN5";
+               type = "mini";
+
+               port {
+                       mini_dp_con_in: endpoint {
+                               remote-endpoint = <&sn65dsi86_out>;
+                       };
+               };
+       };
+
+       reg_1p2v: regulator-1p2v {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-1.2V";
+               regulator-min-microvolt = <1200000>;
+               regulator-max-microvolt = <1200000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       reg_1p8v: regulator-1p8v {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-1.8V";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       reg_3p3v: regulator-3p3v {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-3.3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       sn65dsi86_refclk: clk-x6 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <38400000>;
+       };
+};
+
+&avb0 {
+       pinctrl-0 = <&avb0_pins>;
+       pinctrl-names = "default";
+       phy-handle = <&phy0>;
+       tx-internal-delay-ps = <2000>;
+       status = "okay";
+
+       phy0: ethernet-phy@0 {
+               compatible = "ethernet-phy-id0022.1622",
+                            "ethernet-phy-ieee802.3-c22";
+               rxc-skew-ps = <1500>;
+               reg = <0>;
+               interrupt-parent = <&gpio7>;
+               interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+               reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
+       };
+};
+
+&dsi0 {
+       status = "okay";
+
+       ports {
+               port@1 {
+                       dsi0_out: endpoint {
+                               remote-endpoint = <&sn65dsi86_in>;
+                               data-lanes = <1 2 3 4>;
+                       };
+               };
+       };
+};
+
+&du {
+       status = "okay";
+};
+
+&extal_clk {
+       clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+       clock-frequency = <32768>;
+};
+
+&hscif0 {
+       status = "okay";
+};
+
+&i2c0 {
+       pinctrl-0 = <&i2c0_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+       clock-frequency = <400000>;
+
+       io_expander_a: gpio@20 {
+               compatible = "onnn,pca9654";
+               reg = <0x20>;
+               interrupt-parent = <&gpio0>;
+               interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+       };
+
+       eeprom@50 {
+               compatible = "rohm,br24g01", "atmel,24c01";
+               label = "cpu-board";
+               reg = <0x50>;
+               pagesize = <8>;
+       };
+};
+
+&i2c1 {
+       pinctrl-0 = <&i2c1_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+       clock-frequency = <400000>;
+
+       bridge@2c {
+               compatible = "ti,sn65dsi86";
+               reg = <0x2c>;
+
+               clocks = <&sn65dsi86_refclk>;
+               clock-names = "refclk";
+
+               interrupt-parent = <&intc_ex>;
+               interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+               enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+
+               vccio-supply = <&reg_1p8v>;
+               vpll-supply = <&reg_1p8v>;
+               vcca-supply = <&reg_1p2v>;
+               vcc-supply = <&reg_1p2v>;
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               sn65dsi86_in: endpoint {
+                                       remote-endpoint = <&dsi0_out>;
+                               };
+                       };
+
+                       port@1 {
+                               reg = <1>;
+                               sn65dsi86_out: endpoint {
+                                       remote-endpoint = <&mini_dp_con_in>;
+                               };
+                       };
+               };
+       };
+};
+
+&mmc0 {
+       pinctrl-0 = <&mmc_pins>;
+       pinctrl-1 = <&mmc_pins>;
+       pinctrl-names = "default", "state_uhs";
+
+       vmmc-supply = <&reg_3p3v>;
+       vqmmc-supply = <&reg_1p8v>;
+       mmc-hs200-1_8v;
+       mmc-hs400-1_8v;
+       bus-width = <8>;
+       no-sd;
+       no-sdio;
+       non-removable;
+       full-pwr-cycle-in-suspend;
+       status = "okay";
+};
+
+&pfc {
+       pinctrl-0 = <&scif_clk_pins>;
+       pinctrl-names = "default";
+
+       avb0_pins: avb0 {
+               mux {
+                       groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
+                                "avb0_txcrefclk";
+                       function = "avb0";
+               };
+
+               pins_mdio {
+                       groups = "avb0_mdio";
+                       drive-strength = <21>;
+               };
+
+               pins_mii {
+                       groups = "avb0_rgmii";
+                       drive-strength = <21>;
+               };
+
+       };
+       hscif0_pins: hscif0 {
+               groups = "hscif0_data";
+               function = "hscif0";
+       };
+
+       i2c0_pins: i2c0 {
+               groups = "i2c0";
+               function = "i2c0";
+       };
+
+       i2c1_pins: i2c1 {
+               groups = "i2c1";
+               function = "i2c1";
+       };
+
+       keys_pins: keys {
+               pins = "GP_5_0", "GP_5_1", "GP_5_2";
+               bias-pull-up;
+       };
+
+       mmc_pins: mmc {
+               groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
+               function = "mmc";
+               power-source = <1800>;
+       };
+
+       qspi0_pins: qspi0 {
+               groups = "qspi0_ctrl", "qspi0_data4";
+               function = "qspi0";
+       };
+
+       scif_clk_pins: scif_clk {
+               groups = "scif_clk";
+               function = "scif_clk";
+       };
+};
+
+&rpc {
+       pinctrl-0 = <&qspi0_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+
+       flash@0 {
+               compatible = "spansion,s25fs512s", "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <40000000>;
+               spi-rx-bus-width = <4>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       boot@0 {
+                               reg = <0x0 0x1200000>;
+                               read-only;
+                       };
+                       user@1200000 {
+                               reg = <0x1200000 0x2e00000>;
+                       };
+               };
+       };
+};
+
+&rwdt {
+       timeout-sec = <60>;
+       status = "okay";
+};
+
+&scif_clk {
+       clock-frequency = <24000000>;
+};

diff --git a/arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi b/arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi
new file mode 100644 (file)
index 0000000..ae7522b
--- /dev/null
+++ b/arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R-Car V4H White Hawk CSI/DSI sub-board
+ *
+ * Copyright (C) 2022 Glider bv
+ */
+
+&i2c0 {
+       eeprom@52 {
+               compatible = "rohm,br24g01", "atmel,24c01";
+               label = "csi-dsi-sub-board-id";
+               reg = <0x52>;
+               pagesize = <8>;
+       };
+};

diff --git a/arch/arm/dts/r8a779g0-white-hawk-ethernet.dtsi b/arch/arm/dts/r8a779g0-white-hawk-ethernet.dtsi
new file mode 100644 (file)
index 0000000..4f411f9
--- /dev/null
+++ b/arch/arm/dts/r8a779g0-white-hawk-ethernet.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R-Car V4H White Hawk RAVB/Ethernet(1000Base-T1)
+ * sub-board
+ *
+ * Copyright (C) 2022 Glider bv
+ */
+
+&i2c0 {
+       eeprom@53 {
+               compatible = "rohm,br24g01", "atmel,24c01";
+               label = "ethernet-sub-board-id";
+               reg = <0x53>;
+               pagesize = <8>;
+       };
+};

diff --git a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dts b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dts
new file mode 100644 (file)
index 0000000..efc1b95
--- /dev/null
+++ b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the White Hawk board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a779g0-white-hawk.dts"
+#include "r8a779g0-u-boot.dtsi"
+
+/ {
+       aliases {
+               spi0 = &rpc;
+       };
+};
+
+&pfc {
+       qspi0_pins: qspi0 {
+               groups = "qspi0_ctrl", "qspi0_data4";
+               function = "qspi0";
+       };
+};
+
+&rpc {
+       pinctrl-0 = <&qspi0_pins>;
+       pinctrl-names = "default";
+
+       #address-cells = <1>;
+       #size-cells = <0>;
+       spi-max-frequency = <40000000>;
+       status = "okay";
+
+       spi-flash@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "s25fs512s", "jedec,spi-nor";
+               reg = <0>;
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <1>;
+               spi-max-frequency = <40000000>;
+       };
+};

diff --git a/arch/arm/dts/r8a779g0-white-hawk.dts b/arch/arm/dts/r8a779g0-white-hawk.dts
new file mode 100644 (file)
index 0000000..04a2b6b
--- /dev/null
+++ b/arch/arm/dts/r8a779g0-white-hawk.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the White Hawk CPU and BreakOut boards
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a779g0-white-hawk-cpu.dtsi"
+#include "r8a779g0-white-hawk-csi-dsi.dtsi"
+#include "r8a779g0-white-hawk-ethernet.dtsi"
+
+/ {
+       model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0";
+       compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0";
+};
+
+&i2c0 {
+       eeprom@51 {
+               compatible = "rohm,br24g01", "atmel,24c01";
+               label = "breakout-board";
+               reg = <0x51>;
+               pagesize = <8>;
+       };
+};

diff --git a/arch/arm/dts/r8a779g0.dtsi b/arch/arm/dts/r8a779g0.dtsi
new file mode 100644 (file)
index 0000000..7a87a5d
--- /dev/null
+++ b/arch/arm/dts/r8a779g0.dtsi
@@ -0,0 +1,1355 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R-Car V4H (R8A779G0) SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a779g0-sysc.h>
+
+/ {
+       compatible = "renesas,r8a779g0";
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       cluster0_opp: opp-table-0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-500000000 {
+                       opp-hz = /bits/ 64 <500000000>;
+                       opp-microvolt = <825000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp-1000000000 {
+                       opp-hz = /bits/ 64 <1000000000>;
+                       opp-microvolt = <825000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp-1500000000 {
+                       opp-hz = /bits/ 64 <1500000000>;
+                       opp-microvolt = <825000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp-1700000000 {
+                       opp-hz = /bits/ 64 <1700000000>;
+                       opp-microvolt = <825000>;
+                       clock-latency-ns = <500000>;
+                       opp-suspend;
+               };
+               opp-1800000000 {
+                       opp-hz = /bits/ 64 <1800000000>;
+                       opp-microvolt = <880000>;
+                       clock-latency-ns = <500000>;
+                       turbo-mode;
+               };
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu-map {
+                       cluster0 {
+                               core0 {
+                                       cpu = <&a76_0>;
+                               };
+                               core1 {
+                                       cpu = <&a76_1>;
+                               };
+                       };
+
+                       cluster1 {
+                               core0 {
+                                       cpu = <&a76_2>;
+                               };
+                               core1 {
+                                       cpu = <&a76_3>;
+                               };
+                       };
+               };
+
+               a76_0: cpu@0 {
+                       compatible = "arm,cortex-a76";
+                       reg = <0>;
+                       device_type = "cpu";
+                       power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
+                       next-level-cache = <&L3_CA76_0>;
+                       enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
+                       clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
+                       operating-points-v2 = <&cluster0_opp>;
+               };
+
+               a76_1: cpu@100 {
+                       compatible = "arm,cortex-a76";
+                       reg = <0x100>;
+                       device_type = "cpu";
+                       power-domains = <&sysc R8A779G0_PD_A1E0D0C1>;
+                       next-level-cache = <&L3_CA76_0>;
+                       enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
+                       clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
+                       operating-points-v2 = <&cluster0_opp>;
+               };
+
+               a76_2: cpu@10000 {
+                       compatible = "arm,cortex-a76";
+                       reg = <0x10000>;
+                       device_type = "cpu";
+                       power-domains = <&sysc R8A779G0_PD_A1E0D1C0>;
+                       next-level-cache = <&L3_CA76_1>;
+                       enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
+                       clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
+                       operating-points-v2 = <&cluster0_opp>;
+               };
+
+               a76_3: cpu@10100 {
+                       compatible = "arm,cortex-a76";
+                       reg = <0x10100>;
+                       device_type = "cpu";
+                       power-domains = <&sysc R8A779G0_PD_A1E0D1C1>;
+                       next-level-cache = <&L3_CA76_1>;
+                       enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
+                       clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
+                       operating-points-v2 = <&cluster0_opp>;
+               };
+
+               idle-states {
+                       entry-method = "psci";
+
+                       CPU_SLEEP_0: cpu-sleep-0 {
+                               compatible = "arm,idle-state";
+                               arm,psci-suspend-param = <0x0010000>;
+                               local-timer-stop;
+                               entry-latency-us = <400>;
+                               exit-latency-us = <500>;
+                               min-residency-us = <4000>;
+                       };
+              };
+
+               L3_CA76_0: cache-controller-0 {
+                       compatible = "cache";
+                       power-domains = <&sysc R8A779G0_PD_A2E0D0>;
+                       cache-unified;
+                       cache-level = <3>;
+               };
+
+               L3_CA76_1: cache-controller-1 {
+                       compatible = "cache";
+                       power-domains = <&sysc R8A779G0_PD_A2E0D1>;
+                       cache-unified;
+                       cache-level = <3>;
+               };
+       };
+
+       psci {
+               compatible = "arm,psci-1.0", "arm,psci-0.2";
+               method = "smc";
+       };
+
+       extal_clk: extal {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       extalr_clk: extalr {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       pmu_a76 {
+               compatible = "arm,cortex-a76-pmu";
+               interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       /* External SCIF clock - to be overridden by boards that provide it */
+       scif_clk: scif {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+       };
+
+       soc: soc {
+               compatible = "simple-bus";
+               interrupt-parent = <&gic>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               rwdt: watchdog@e6020000 {
+                       compatible = "renesas,r8a779g0-wdt",
+                                    "renesas,rcar-gen4-wdt";
+                       reg = <0 0xe6020000 0 0x0c>;
+                       interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 907>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 907>;
+                       status = "disabled";
+               };
+
+               pfc: pinctrl@e6050000 {
+                       compatible = "renesas,pfc-r8a779g0";
+                       reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
+                             <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
+                             <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
+                             <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>,
+                             <0 0xe6068000 0 0x16c>;
+               };
+
+               gpio0: gpio@e6050180 {
+                       compatible = "renesas,gpio-r8a779g0",
+                                    "renesas,rcar-gen4-gpio";
+                       reg = <0 0xe6050180 0 0x54>;
+                       interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 915>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 915>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&pfc 0 0 19>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio1: gpio@e6050980 {
+                       compatible = "renesas,gpio-r8a779g0",
+                                    "renesas,rcar-gen4-gpio";
+                       reg = <0 0xe6050980 0 0x54>;
+                       interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 915>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 915>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&pfc 0 32 29>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio2: gpio@e6058180 {
+                       compatible = "renesas,gpio-r8a779g0",
+                                    "renesas,rcar-gen4-gpio";
+                       reg = <0 0xe6058180 0 0x54>;
+                       interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 916>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 916>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&pfc 0 64 20>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio3: gpio@e6058980 {
+                       compatible = "renesas,gpio-r8a779g0",
+                                    "renesas,rcar-gen4-gpio";
+                       reg = <0 0xe6058980 0 0x54>;
+                       interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 916>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 916>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&pfc 0 96 30>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio4: gpio@e6060180 {
+                       compatible = "renesas,gpio-r8a779g0",
+                                    "renesas,rcar-gen4-gpio";
+                       reg = <0 0xe6060180 0 0x54>;
+                       interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 917>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 917>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&pfc 0 128 25>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio5: gpio@e6060980 {
+                       compatible = "renesas,gpio-r8a779g0",
+                                    "renesas,rcar-gen4-gpio";
+                       reg = <0 0xe6060980 0 0x54>;
+                       interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 917>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 917>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&pfc 0 160 21>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio6: gpio@e6061180 {
+                       compatible = "renesas,gpio-r8a779g0",
+                                    "renesas,rcar-gen4-gpio";
+                       reg = <0 0xe6061180 0 0x54>;
+                       interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 917>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 917>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&pfc 0 192 21>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio7: gpio@e6061980 {
+                       compatible = "renesas,gpio-r8a779g0",
+                                    "renesas,rcar-gen4-gpio";
+                       reg = <0 0xe6061980 0 0x54>;
+                       interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 917>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 917>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&pfc 0 224 21>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio8: gpio@e6068180 {
+                       compatible = "renesas,gpio-r8a779g0",
+                                    "renesas,rcar-gen4-gpio";
+                       reg = <0 0xe6068180 0 0x54>;
+                       interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 918>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 918>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&pfc 0 256 14>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               cmt0: timer@e60f0000 {
+                       compatible = "renesas,r8a779g0-cmt0",
+                                    "renesas,rcar-gen4-cmt0";
+                       reg = <0 0xe60f0000 0 0x1004>;
+                       interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 910>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 910>;
+                       status = "disabled";
+               };
+
+               cmt1: timer@e6130000 {
+                       compatible = "renesas,r8a779g0-cmt1",
+                                    "renesas,rcar-gen4-cmt1";
+                       reg = <0 0xe6130000 0 0x1004>;
+                       interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 911>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 911>;
+                       status = "disabled";
+               };
+
+               cmt2: timer@e6140000 {
+                       compatible = "renesas,r8a779g0-cmt1",
+                                    "renesas,rcar-gen4-cmt1";
+                       reg = <0 0xe6140000 0 0x1004>;
+                       interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 912>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 912>;
+                       status = "disabled";
+               };
+
+               cmt3: timer@e6148000 {
+                       compatible = "renesas,r8a779g0-cmt1",
+                                    "renesas,rcar-gen4-cmt1";
+                       reg = <0 0xe6148000 0 0x1004>;
+                       interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 913>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 913>;
+                       status = "disabled";
+               };
+
+               cpg: clock-controller@e6150000 {
+                       compatible = "renesas,r8a779g0-cpg-mssr";
+                       reg = <0 0xe6150000 0 0x4000>;
+                       clocks = <&extal_clk>, <&extalr_clk>;
+                       clock-names = "extal", "extalr";
+                       #clock-cells = <2>;
+                       #power-domain-cells = <0>;
+                       #reset-cells = <1>;
+               };
+
+               rst: reset-controller@e6160000 {
+                       compatible = "renesas,r8a779g0-rst";
+                       reg = <0 0xe6160000 0 0x4000>;
+               };
+
+               sysc: system-controller@e6180000 {
+                       compatible = "renesas,r8a779g0-sysc";
+                       reg = <0 0xe6180000 0 0x4000>;
+                       #power-domain-cells = <1>;
+               };
+
+               intc_ex: interrupt-controller@e61c0000 {
+                       compatible = "renesas,intc-ex-r8a779g0", "renesas,irqc";
+                       #interrupt-cells = <2>;
+                       interrupt-controller;
+                       reg = <0 0xe61c0000 0 0x200>;
+                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 611>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 611>;
+               };
+
+               tmu0: timer@e61e0000 {
+                       compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
+                       reg = <0 0xe61e0000 0 0x30>;
+                       interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 713>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 713>;
+                       status = "disabled";
+               };
+
+               tmu1: timer@e6fc0000 {
+                       compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
+                       reg = <0 0xe6fc0000 0 0x30>;
+                       interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 714>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 714>;
+                       status = "disabled";
+               };
+
+               tmu2: timer@e6fd0000 {
+                       compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
+                       reg = <0 0xe6fd0000 0 0x30>;
+                       interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 715>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 715>;
+                       status = "disabled";
+               };
+
+               tmu3: timer@e6fe0000 {
+                       compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
+                       reg = <0 0xe6fe0000 0 0x30>;
+                       interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 716>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 716>;
+                       status = "disabled";
+               };
+
+               tmu4: timer@ffc00000 {
+                       compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
+                       reg = <0 0xffc00000 0 0x30>;
+                       interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 717>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 717>;
+                       status = "disabled";
+               };
+
+               i2c0: i2c@e6500000 {
+                       compatible = "renesas,i2c-r8a779g0",
+                                    "renesas,rcar-gen4-i2c";
+                       reg = <0 0xe6500000 0 0x40>;
+                       interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 518>;
+                       dmas = <&dmac0 0x91>, <&dmac0 0x90>,
+                              <&dmac1 0x91>, <&dmac1 0x90>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 518>;
+                       i2c-scl-internal-delay-ns = <110>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c1: i2c@e6508000 {
+                       compatible = "renesas,i2c-r8a779g0",
+                                    "renesas,rcar-gen4-i2c";
+                       reg = <0 0xe6508000 0 0x40>;
+                       interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 519>;
+                       dmas = <&dmac0 0x93>, <&dmac0 0x92>,
+                              <&dmac1 0x93>, <&dmac1 0x92>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 519>;
+                       i2c-scl-internal-delay-ns = <110>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c2: i2c@e6510000 {
+                       compatible = "renesas,i2c-r8a779g0",
+                                    "renesas,rcar-gen4-i2c";
+                       reg = <0 0xe6510000 0 0x40>;
+                       interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 520>;
+                       dmas = <&dmac0 0x95>, <&dmac0 0x94>,
+                              <&dmac1 0x95>, <&dmac1 0x94>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 520>;
+                       i2c-scl-internal-delay-ns = <110>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c3: i2c@e66d0000 {
+                       compatible = "renesas,i2c-r8a779g0",
+                                    "renesas,rcar-gen4-i2c";
+                       reg = <0 0xe66d0000 0 0x40>;
+                       interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 521>;
+                       dmas = <&dmac0 0x97>, <&dmac0 0x96>,
+                              <&dmac1 0x97>, <&dmac1 0x96>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 521>;
+                       i2c-scl-internal-delay-ns = <110>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c4: i2c@e66d8000 {
+                       compatible = "renesas,i2c-r8a779g0",
+                                    "renesas,rcar-gen4-i2c";
+                       reg = <0 0xe66d8000 0 0x40>;
+                       interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 522>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       dmas = <&dmac0 0x99>, <&dmac0 0x98>,
+                              <&dmac1 0x99>, <&dmac1 0x98>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 522>;
+                       i2c-scl-internal-delay-ns = <110>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c5: i2c@e66e0000 {
+                       compatible = "renesas,i2c-r8a779g0",
+                                    "renesas,rcar-gen4-i2c";
+                       reg = <0 0xe66e0000 0 0x40>;
+                       interrupts = <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 523>;
+                       dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
+                              <&dmac1 0x9b>, <&dmac1 0x9a>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 523>;
+                       i2c-scl-internal-delay-ns = <110>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               hscif0: serial@e6540000 {
+                       compatible = "renesas,hscif-r8a779g0",
+                                    "renesas,rcar-gen4-hscif", "renesas,hscif";
+                       reg = <0 0xe6540000 0 0x60>;
+                       interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 514>,
+                                <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x31>, <&dmac0 0x30>,
+                              <&dmac1 0x31>, <&dmac1 0x30>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 514>;
+                       status = "disabled";
+               };
+
+               hscif1: serial@e6550000 {
+                       compatible = "renesas,hscif-r8a779g0",
+                                    "renesas,rcar-gen4-hscif", "renesas,hscif";
+                       reg = <0 0xe6550000 0 0x60>;
+                       interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 515>,
+                                <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x33>, <&dmac0 0x32>,
+                              <&dmac1 0x33>, <&dmac1 0x32>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 515>;
+                       status = "disabled";
+               };
+
+               hscif2: serial@e6560000 {
+                       compatible = "renesas,hscif-r8a779g0",
+                                    "renesas,rcar-gen4-hscif", "renesas,hscif";
+                       reg = <0 0xe6560000 0 0x60>;
+                       interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 516>,
+                                <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x35>, <&dmac0 0x34>,
+                              <&dmac1 0x35>, <&dmac1 0x34>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 516>;
+                       status = "disabled";
+               };
+
+               hscif3: serial@e66a0000 {
+                       compatible = "renesas,hscif-r8a779g0",
+                                    "renesas,rcar-gen4-hscif", "renesas,hscif";
+                       reg = <0 0xe66a0000 0 0x60>;
+                       interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 517>,
+                                <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x37>, <&dmac0 0x36>,
+                              <&dmac1 0x37>, <&dmac1 0x36>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 517>;
+                       status = "disabled";
+               };
+
+               avb0: ethernet@e6800000 {
+                       compatible = "renesas,etheravb-r8a779g0",
+                                    "renesas,etheravb-rcar-gen4";
+                       reg = <0 0xe6800000 0 0x800>;
+                       interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4",
+                                         "ch5", "ch6", "ch7", "ch8", "ch9",
+                                         "ch10", "ch11", "ch12", "ch13",
+                                         "ch14", "ch15", "ch16", "ch17",
+                                         "ch18", "ch19", "ch20", "ch21",
+                                         "ch22", "ch23", "ch24";
+                       clocks = <&cpg CPG_MOD 211>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 211>;
+                       phy-mode = "rgmii";
+                       rx-internal-delay-ps = <0>;
+                       tx-internal-delay-ps = <0>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               avb1: ethernet@e6810000 {
+                       compatible = "renesas,etheravb-r8a779g0",
+                                    "renesas,etheravb-rcar-gen4";
+                       reg = <0 0xe6810000 0 0x800>;
+                       interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4",
+                                         "ch5", "ch6", "ch7", "ch8", "ch9",
+                                         "ch10", "ch11", "ch12", "ch13",
+                                         "ch14", "ch15", "ch16", "ch17",
+                                         "ch18", "ch19", "ch20", "ch21",
+                                         "ch22", "ch23", "ch24";
+                       clocks = <&cpg CPG_MOD 212>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 212>;
+                       phy-mode = "rgmii";
+                       rx-internal-delay-ps = <0>;
+                       tx-internal-delay-ps = <0>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               avb2: ethernet@e6820000 {
+                       compatible = "renesas,etheravb-r8a779g0",
+                                    "renesas,etheravb-rcar-gen4";
+                       reg = <0 0xe6820000 0 0x1000>;
+                       interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4",
+                                         "ch5", "ch6", "ch7", "ch8", "ch9",
+                                         "ch10", "ch11", "ch12", "ch13",
+                                         "ch14", "ch15", "ch16", "ch17",
+                                         "ch18", "ch19", "ch20", "ch21",
+                                         "ch22", "ch23", "ch24";
+                       clocks = <&cpg CPG_MOD 213>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 213>;
+                       phy-mode = "rgmii";
+                       rx-internal-delay-ps = <0>;
+                       tx-internal-delay-ps = <0>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               pwm0: pwm@e6e30000 {
+                       compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e30000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
+               pwm1: pwm@e6e31000 {
+                       compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e31000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
+               pwm2: pwm@e6e32000 {
+                       compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e32000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
+               pwm3: pwm@e6e33000 {
+                       compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e33000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
+               pwm4: pwm@e6e34000 {
+                       compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e34000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
+               pwm5: pwm@e6e35000 {
+                       compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e35000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
+               pwm6: pwm@e6e36000 {
+                       compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e36000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
+               pwm7: pwm@e6e37000 {
+                       compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e37000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
+               pwm8: pwm@e6e38000 {
+                       compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e38000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
+               pwm9: pwm@e6e39000 {
+                       compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e39000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
+               scif0: serial@e6e60000 {
+                       compatible = "renesas,scif-r8a779g0",
+                                    "renesas,rcar-gen4-scif", "renesas,scif";
+                       reg = <0 0xe6e60000 0 64>;
+                       interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 702>,
+                                <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x51>, <&dmac0 0x50>,
+                              <&dmac1 0x51>, <&dmac1 0x50>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 702>;
+                       status = "disabled";
+               };
+
+               scif1: serial@e6e68000 {
+                       compatible = "renesas,scif-r8a779g0",
+                                    "renesas,rcar-gen4-scif", "renesas,scif";
+                       reg = <0 0xe6e68000 0 64>;
+                       interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 703>,
+                                <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x53>, <&dmac0 0x52>,
+                              <&dmac1 0x53>, <&dmac1 0x52>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 703>;
+                       status = "disabled";
+               };
+
+               scif3: serial@e6c50000 {
+                       compatible = "renesas,scif-r8a779g0",
+                                    "renesas,rcar-gen4-scif", "renesas,scif";
+                       reg = <0 0xe6c50000 0 64>;
+                       interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 704>,
+                                <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x57>, <&dmac0 0x56>,
+                              <&dmac1 0x57>, <&dmac1 0x56>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 704>;
+                       status = "disabled";
+               };
+
+               scif4: serial@e6c40000 {
+                       compatible = "renesas,scif-r8a779g0",
+                                    "renesas,rcar-gen4-scif", "renesas,scif";
+                       reg = <0 0xe6c40000 0 64>;
+                       interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 705>,
+                                <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
+                                <&scif_clk>;
+                       clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x59>, <&dmac0 0x58>,
+                              <&dmac1 0x59>, <&dmac1 0x58>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 705>;
+                       status = "disabled";
+               };
+
+               tpu: pwm@e6e80000 {
+                       compatible = "renesas,tpu-r8a779g0", "renesas,tpu";
+                       reg = <0 0xe6e80000 0 0x148>;
+                       interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 718>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 718>;
+                       #pwm-cells = <3>;
+                       status = "disabled";
+               };
+
+               msiof0: spi@e6e90000 {
+                       compatible = "renesas,msiof-r8a779g0",
+                                    "renesas,rcar-gen4-msiof";
+                       reg = <0 0xe6e90000 0 0x0064>;
+                       interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 618>;
+                       dmas = <&dmac0 0x41>, <&dmac0 0x40>,
+                              <&dmac1 0x41>, <&dmac1 0x40>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 618>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               msiof1: spi@e6ea0000 {
+                       compatible = "renesas,msiof-r8a779g0",
+                                    "renesas,rcar-gen4-msiof";
+                       reg = <0 0xe6ea0000 0 0x0064>;
+                       interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 619>;
+                       dmas = <&dmac0 0x43>, <&dmac0 0x42>,
+                              <&dmac1 0x43>, <&dmac1 0x42>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 619>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               msiof2: spi@e6c00000 {
+                       compatible = "renesas,msiof-r8a779g0",
+                                    "renesas,rcar-gen4-msiof";
+                       reg = <0 0xe6c00000 0 0x0064>;
+                       interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 620>;
+                       dmas = <&dmac0 0x45>, <&dmac0 0x44>,
+                              <&dmac1 0x45>, <&dmac1 0x44>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 620>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               msiof3: spi@e6c10000 {
+                       compatible = "renesas,msiof-r8a779g0",
+                                    "renesas,rcar-gen4-msiof";
+                       reg = <0 0xe6c10000 0 0x0064>;
+                       interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 621>;
+                       dmas = <&dmac0 0x47>, <&dmac0 0x46>,
+                              <&dmac1 0x47>, <&dmac1 0x46>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 621>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               msiof4: spi@e6c20000 {
+                       compatible = "renesas,msiof-r8a779g0",
+                                    "renesas,rcar-gen4-msiof";
+                       reg = <0 0xe6c20000 0 0x0064>;
+                       interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 622>;
+                       dmas = <&dmac0 0x49>, <&dmac0 0x48>,
+                              <&dmac1 0x49>, <&dmac1 0x48>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 622>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               msiof5: spi@e6c28000 {
+                       compatible = "renesas,msiof-r8a779g0",
+                                    "renesas,rcar-gen4-msiof";
+                       reg = <0 0xe6c28000 0 0x0064>;
+                       interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 623>;
+                       dmas = <&dmac0 0x4b>, <&dmac0 0x4a>,
+                              <&dmac1 0x4b>, <&dmac1 0x4a>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 623>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               dmac0: dma-controller@e7350000 {
+                       compatible = "renesas,dmac-r8a779g0",
+                                    "renesas,rcar-gen4-dmac";
+                       reg = <0 0xe7350000 0 0x1000>,
+                             <0 0xe7300000 0 0x10000>;
+                       interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "error",
+                                         "ch0", "ch1", "ch2", "ch3", "ch4",
+                                         "ch5", "ch6", "ch7", "ch8", "ch9",
+                                         "ch10", "ch11", "ch12", "ch13",
+                                         "ch14", "ch15";
+                       clocks = <&cpg CPG_MOD 709>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 709>;
+                       #dma-cells = <1>;
+                       dma-channels = <16>;
+               };
+
+               dmac1: dma-controller@e7351000 {
+                       compatible = "renesas,dmac-r8a779g0",
+                                    "renesas,rcar-gen4-dmac";
+                       reg = <0 0xe7351000 0 0x1000>,
+                             <0 0xe7310000 0 0x10000>;
+                       interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "error",
+                                         "ch0", "ch1", "ch2", "ch3", "ch4",
+                                         "ch5", "ch6", "ch7", "ch8", "ch9",
+                                         "ch10", "ch11", "ch12", "ch13",
+                                         "ch14", "ch15";
+                       clocks = <&cpg CPG_MOD 710>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 710>;
+                       #dma-cells = <1>;
+                       dma-channels = <16>;
+               };
+
+               mmc0: mmc@ee140000 {
+                       compatible = "renesas,sdhi-r8a779g0",
+                                    "renesas,rcar-gen4-sdhi";
+                       reg = <0 0xee140000 0 0x2000>;
+                       interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 706>,
+                                <&cpg CPG_CORE R8A779G0_CLK_SD0H>;
+                       clock-names = "core", "clkh";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 706>;
+                       max-frequency = <200000000>;
+                       status = "disabled";
+               };
+
+               rpc: spi@ee200000 {
+                       compatible = "renesas,r8a779g0-rpc-if",
+                                    "renesas,rcar-gen4-rpc-if";
+                       reg = <0 0xee200000 0 0x200>,
+                             <0 0x08000000 0 0x04000000>,
+                             <0 0xee208000 0 0x100>;
+                       reg-names = "regs", "dirmap", "wbuf";
+                       interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 629>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 629>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               gic: interrupt-controller@f1000000 {
+                       compatible = "arm,gic-v3";
+                       #interrupt-cells = <3>;
+                       #address-cells = <0>;
+                       interrupt-controller;
+                       reg = <0x0 0xf1000000 0 0x20000>,
+                             <0x0 0xf1060000 0 0x110000>;
+                       interrupts = <GIC_PPI 9
+                                     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+               };
+
+               fcpvd0: fcp@fea10000 {
+                       compatible = "renesas,fcpv";
+                       reg = <0 0xfea10000 0 0x200>;
+                       clocks = <&cpg CPG_MOD 508>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 508>;
+               };
+
+               fcpvd1: fcp@fea11000 {
+                       compatible = "renesas,fcpv";
+                       reg = <0 0xfea11000 0 0x200>;
+                       clocks = <&cpg CPG_MOD 509>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 509>;
+               };
+
+               vspd0: vsp@fea20000 {
+                       compatible = "renesas,vsp2";
+                       reg = <0 0xfea20000 0 0x7000>;
+                       interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 830>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 830>;
+
+                       renesas,fcp = <&fcpvd0>;
+               };
+
+               vspd1: vsp@fea28000 {
+                       compatible = "renesas,vsp2";
+                       reg = <0 0xfea28000 0 0x7000>;
+                       interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 831>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 831>;
+
+                       renesas,fcp = <&fcpvd1>;
+               };
+
+               du: display@feb00000 {
+                       compatible = "renesas,du-r8a779g0";
+                       reg = <0 0xfeb00000 0 0x40000>;
+                       interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 411>;
+                       clock-names = "du.0";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 411>;
+                       reset-names = "du.0";
+                       renesas,vsps = <&vspd0 0>, <&vspd1 0>;
+
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       du_out_dsi0: endpoint {
+                                               remote-endpoint = <&dsi0_in>;
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                                       du_out_dsi1: endpoint {
+                                               remote-endpoint = <&dsi1_in>;
+                                       };
+                               };
+                       };
+               };
+
+               dsi0: dsi-encoder@fed80000 {
+                       compatible = "renesas,r8a779g0-dsi-csi2-tx";
+                       reg = <0 0xfed80000 0 0x10000>;
+                       clocks = <&cpg CPG_MOD 415>,
+                                <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
+                                <&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
+                       clock-names = "fck", "dsi", "pll";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 415>;
+
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       dsi0_in: endpoint {
+                                               remote-endpoint = <&du_out_dsi0>;
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                               };
+                       };
+               };
+
+               dsi1: dsi-encoder@fed90000 {
+                       compatible = "renesas,r8a779g0-dsi-csi2-tx";
+                       reg = <0 0xfed90000 0 0x10000>;
+                       clocks = <&cpg CPG_MOD 416>,
+                                <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
+                                <&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
+                       clock-names = "fck", "dsi", "pll";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 416>;
+
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       dsi1_in: endpoint {
+                                               remote-endpoint = <&du_out_dsi1>;
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                               };
+                       };
+               };
+
+               prr: chipid@fff00044 {
+                       compatible = "renesas,prr";
+                       reg = <0 0xfff00044 0 4>;
+               };
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+       };
+};

diff --git a/arch/arm/dts/rk3066a-mk808.dts b/arch/arm/dts/rk3066a-mk808.dts
index 667d57a..06790f0 100644 (file)
--- a/arch/arm/dts/rk3066a-mk808.dts
+++ b/arch/arm/dts/rk3066a-mk808.dts
@@ -32,7 +32,7 @@
                keyup-threshold-microvolt = <2500000>;
                poll-interval = <100>;
 
-               recovery {
+               button-recovery {
                        label = "recovery";
                        linux,code = <KEY_VENDOR>;
                        press-threshold-microvolt = <0>;
@@ -157,7 +157,32 @@
        pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
        pinctrl-names = "default";
        vmmc-supply = <&vcc_wifi>;
+       #address-cells = <1>;
+       #size-cells = <0>;
        status = "okay";
+
+       brcmf: wifi@1 {
+               compatible = "brcm,bcm4329-fmac";
+               reg = <1>;
+       };
+};
+
+&nfc {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       status = "okay";
+
+       nand@0 {
+               reg = <0>;
+               label = "rk-nand";
+               nand-bus-width = <8>;
+               nand-ecc-mode = "hw";
+               nand-ecc-step-size = <1024>;
+               nand-ecc-strength = <40>;
+               nand-is-boot-medium;
+               rockchip,boot-blks = <8>;
+               rockchip,boot-ecc-strength = <24>;
+       };
 };
 
 &pinctrl {

diff --git a/arch/arm/dts/rk3066a-u-boot.dtsi b/arch/arm/dts/rk3066a-u-boot.dtsi
index bc6e609..06f405c 100644 (file)
--- a/arch/arm/dts/rk3066a-u-boot.dtsi
+++ b/arch/arm/dts/rk3066a-u-boot.dtsi
@@ -2,3 +2,28 @@
 
 #include "rockchip-u-boot.dtsi"
 #include "rk3xxx-u-boot.dtsi"
+
+&gpio0 {
+       gpio-ranges = <&pinctrl 0 0 32>;
+};
+
+&gpio1 {
+       gpio-ranges = <&pinctrl 0 32 32>;
+};
+
+&gpio2 {
+       gpio-ranges = <&pinctrl 0 64 32>;
+};
+
+&gpio3 {
+       gpio-ranges = <&pinctrl 0 96 32>;
+};
+
+&gpio4 {
+       gpio-ranges = <&pinctrl 0 128 32>;
+};
+
+&gpio6 {
+       status = "disabled";
+};
+

diff --git a/arch/arm/dts/rk3066a.dtsi b/arch/arm/dts/rk3066a.dtsi
index c25b969..de9915d 100644 (file)
--- a/arch/arm/dts/rk3066a.dtsi
+++ b/arch/arm/dts/rk3066a.dtsi
@@ -202,8 +202,9 @@
        cru: clock-controller@20000000 {
                compatible = "rockchip,rk3066a-cru";
                reg = <0x20000000 0x1000>;
+               clocks = <&xin24m>;
+               clock-names = "xin24m";
                rockchip,grf = <&grf>;
-
                #clock-cells = <1>;
                #reset-cells = <1>;
                assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,

diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts
index e7138a4..118deac 100644 (file)
--- a/arch/arm/dts/rk3188-radxarock.dts
+++ b/arch/arm/dts/rk3188-radxarock.dts
@@ -6,7 +6,6 @@
 /dts-v1/;
 #include <dt-bindings/input/input.h>
 #include "rk3188.dtsi"
-#include "rk3188-radxarock-u-boot.dtsi"
 
 / {
        model = "Radxa Rock";
@@ -25,7 +24,7 @@
                compatible = "gpio-keys";
                autorepeat;
 
-               power {
+               key-power {
                        gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
                        linux,code = <KEY_POWER>;
                        label = "GPIO Key Power";
@@ -72,7 +71,7 @@
                #sound-dai-cells = <0>;
        };
 
-       ir_recv: gpio-ir-receiver {
+       ir_recv: ir-receiver {
                compatible = "gpio-ir-receiver";
                gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
                pinctrl-names = "default";
@@ -127,18 +126,21 @@
 };
 
 &emac {
-       status = "okay";
-
+       phy = <&phy0>;
+       phy-supply = <&vcc_rmii>;
        pinctrl-names = "default";
        pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
+       status = "okay";
 
-       phy = <&phy0>;
-       phy-supply = <&vcc_rmii>;
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
 
-       phy0: ethernet-phy@0 {
-               reg = <0>;
-               interrupt-parent = <&gpio3>;
-               interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
+               phy0: ethernet-phy@0 {
+                       reg = <0>;
+                       interrupt-parent = <&gpio3>;
+                       interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
+               };
        };
 };
 

diff --git a/arch/arm/dts/rk3188-u-boot.dtsi b/arch/arm/dts/rk3188-u-boot.dtsi
index 735776c..176f9e6 100644 (file)
--- a/arch/arm/dts/rk3188-u-boot.dtsi
+++ b/arch/arm/dts/rk3188-u-boot.dtsi
@@ -12,6 +12,19 @@
 
 &gpio0 {
        compatible = "rockchip,gpio-bank";
+       gpio-ranges = <&pinctrl 0 0 32>;
+};
+
+&gpio1 {
+       gpio-ranges = <&pinctrl 0 32 32>;
+};
+
+&gpio2 {
+       gpio-ranges = <&pinctrl 0 64 32>;
+};
+
+&gpio3 {
+       gpio-ranges = <&pinctrl 0 96 32>;
 };
 
 &pmu {

diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi
index 9a80f83..44b54af 100644 (file)
--- a/arch/arm/dts/rk3188.dtsi
+++ b/arch/arm/dts/rk3188.dtsi
@@ -54,7 +54,7 @@
                };
        };
 
-       cpu0_opp_table: opp_table0 {
+       cpu0_opp_table: opp-table-0 {
                compatible = "operating-points-v2";
                opp-shared;
 
@@ -195,8 +195,9 @@
        cru: clock-controller@20000000 {
                compatible = "rockchip,rk3188-cru";
                reg = <0x20000000 0x1000>;
+               clocks = <&xin24m>;
+               clock-names = "xin24m";
                rockchip,grf = <&grf>;
-
                #clock-cells = <1>;
                #reset-cells = <1>;
        };
@@ -223,7 +224,7 @@
                #size-cells = <1>;
                ranges;
 
-               gpio0: gpio0@2000a000 {
+               gpio0: gpio@2000a000 {
                        compatible = "rockchip,rk3188-gpio-bank0";
                        reg = <0x2000a000 0x100>;
                        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
@@ -236,7 +237,7 @@
                        #interrupt-cells = <2>;
                };
 
-               gpio1: gpio1@2003c000 {
+               gpio1: gpio@2003c000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x2003c000 0x100>;
                        interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
@@ -249,7 +250,7 @@
                        #interrupt-cells = <2>;
                };
 
-               gpio2: gpio2@2003e000 {
+               gpio2: gpio@2003e000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x2003e000 0x100>;
                        interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
@@ -262,7 +263,7 @@
                        #interrupt-cells = <2>;
                };
 
-               gpio3: gpio3@20080000 {
+               gpio3: gpio@20080000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x20080000 0x100>;
                        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
@@ -275,15 +276,15 @@
                        #interrupt-cells = <2>;
                };
 
-               pcfg_pull_up: pcfg_pull_up {
+               pcfg_pull_up: pcfg-pull-up {
                        bias-pull-up;
                };
 
-               pcfg_pull_down: pcfg_pull_down {
+               pcfg_pull_down: pcfg-pull-down {
                        bias-pull-down;
                };
 
-               pcfg_pull_none: pcfg_pull_none {
+               pcfg_pull_none: pcfg-pull-none {
                        bias-disable;
                };
 
@@ -378,7 +379,7 @@
                                rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
                        };
 
-                       lcdc1_rgb24: ldcd1-rgb24 {
+                       lcdc1_rgb24: lcdc1-rgb24 {
                                rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
                                                <2 RK_PA1 1 &pcfg_pull_none>,
                                                <2 RK_PA2 1 &pcfg_pull_none>,
@@ -606,7 +607,6 @@
 
 &global_timer {
        interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
-       status = "disabled";
 };
 
 &local_timer {
@@ -641,6 +641,11 @@
 &grf {
        compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";
 
+       io_domains: io-domains {
+               compatible = "rockchip,rk3188-io-voltage-domain";
+               status = "disabled";
+       };
+
        usbphy: usbphy {
                compatible = "rockchip,rk3188-usb-phy";
                #address-cells = <1>;

diff --git a/arch/arm/dts/rk3288-miqi.dtsi b/arch/arm/dts/rk3288-miqi.dtsi
index cb80cbf..00c8613 100644 (file)
--- a/arch/arm/dts/rk3288-miqi.dtsi
+++ b/arch/arm/dts/rk3288-miqi.dtsi
@@ -18,21 +18,6 @@
                clock-output-names = "ext_gmac";
        };
 
-       io_domains: io-domains {
-               compatible = "rockchip,rk3288-io-voltage-domain";
-               rockchip,grf = <&grf>;
-
-               audio-supply = <&vcca_33>;
-               flash0-supply = <&vcc_flash>;
-               flash1-supply = <&vcc_lan>;
-               gpio30-supply = <&vcc_io>;
-               gpio1830-supply = <&vcc_io>;
-               lcdc-supply = <&vcc_io>;
-               sdcard-supply = <&vccio_sd>;
-               wifi-supply = <&vcc_18>;
-       };
-
-
        leds {
                compatible = "gpio-leds";
 
@@ -277,6 +262,18 @@
        status = "okay";
 };
 
+&io_domains {
+       audio-supply = <&vcca_33>;
+       flash0-supply = <&vcc_flash>;
+       flash1-supply = <&vcc_lan>;
+       gpio30-supply = <&vcc_io>;
+       gpio1830-supply = <&vcc_io>;
+       lcdc-supply = <&vcc_io>;
+       sdcard-supply = <&vccio_sd>;
+       wifi-supply = <&vcc_18>;
+       status = "okay";
+};
+
 &pinctrl {
        pcfg_output_high: pcfg-output-high {
                output-high;

diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi b/arch/arm/dts/rk3288-phycore-som.dtsi
index 821525f..70c0030 100644 (file)
--- a/arch/arm/dts/rk3288-phycore-som.dtsi
+++ b/arch/arm/dts/rk3288-phycore-som.dtsi
@@ -71,22 +71,6 @@
                clock-output-names = "ext_gmac";
        };
 
-       io_domains: io_domains {
-               compatible = "rockchip,rk3288-io-voltage-domain";
-
-               status = "okay";
-               sdcard-supply = <&vdd_io_sd>;
-               flash0-supply = <&vdd_emmc_io>;
-               flash1-supply = <&vdd_misc_1v8>;
-               gpio1830-supply = <&vdd_3v3_io>;
-               gpio30-supply = <&vdd_3v3_io>;
-               bb-supply = <&vdd_3v3_io>;
-               dvp-supply = <&vdd_3v3_io>;
-               lcdc-supply = <&vdd_3v3_io>;
-               wifi-supply = <&vdd_3v3_io>;
-               audio-supply = <&vdd_3v3_io>;
-       };
-
        leds: user-leds {
                compatible = "gpio-leds";
                pinctrl-names = "default";
@@ -197,6 +181,20 @@
        ddc-i2c-bus = <&i2c5>;
 };
 
+&io_domains {
+       audio-supply = <&vdd_3v3_io>;
+       bb-supply = <&vdd_3v3_io>;
+       dvp-supply = <&vdd_3v3_io>;
+       flash0-supply = <&vdd_emmc_io>;
+       flash1-supply = <&vdd_misc_1v8>;
+       gpio1830-supply = <&vdd_3v3_io>;
+       gpio30-supply = <&vdd_3v3_io>;
+       lcdc-supply = <&vdd_3v3_io>;
+       sdcard-supply = <&vdd_io_sd>;
+       wifi-supply = <&vdd_3v3_io>;
+       status = "okay";
+};
+
 &i2c0 {
        status = "okay";
        clock-frequency = <400000>;

diff --git a/arch/arm/dts/rk3288-popmetal.dtsi b/arch/arm/dts/rk3288-popmetal.dtsi
index 0253933..d732a70 100644 (file)
--- a/arch/arm/dts/rk3288-popmetal.dtsi
+++ b/arch/arm/dts/rk3288-popmetal.dtsi
@@ -71,22 +71,6 @@
                };
        };
 
-       io_domains: io-domains {
-               compatible = "rockchip,rk3288-io-voltage-domain";
-               rockchip,grf = <&grf>;
-
-               audio-supply = <&vcca_33>;
-               bb-supply = <&vcc_io>;
-               dvp-supply = <&vcc18_dvp>;
-               flash0-supply = <&vcc_flash>;
-               flash1-supply = <&vcc_lan>;
-               gpio30-supply = <&vcc_io>;
-               gpio1830-supply = <&vcc_io>;
-               lcdc-supply = <&vcc_io>;
-               sdcard-supply = <&vccio_sd>;
-               wifi-supply = <&vccio_wl>;
-       };
-
        ir: ir-receiver {
                compatible = "gpio-ir-receiver";
                gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
@@ -443,6 +427,20 @@
        status = "okay";
 };
 
+&io_domains {
+       audio-supply = <&vcca_33>;
+       bb-supply = <&vcc_io>;
+       dvp-supply = <&vcc18_dvp>;
+       flash0-supply = <&vcc_flash>;
+       flash1-supply = <&vcc_lan>;
+       gpio30-supply = <&vcc_io>;
+       gpio1830-supply = <&vcc_io>;
+       lcdc-supply = <&vcc_io>;
+       sdcard-supply = <&vccio_sd>;
+       wifi-supply = <&vccio_wl>;
+       status = "okay";
+};
+
 &pinctrl {
        ak8963 {
                comp_int: comp-int {

diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi
index 1894162..1920698 100644 (file)
--- a/arch/arm/dts/rk3288-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-u-boot.dtsi
@@ -91,6 +91,11 @@
        bootph-all;
 };
 
+&edp {
+       clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
+       clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
+};
+
 &gpio7 {
        bootph-all;
 };

diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index 35db882..434b0d4 100644 (file)
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -198,21 +198,6 @@
                /* Faux input supply.  See bt_regulator description. */
                vin-supply = <&bt_regulator>;
        };
-
-       io-domains {
-               compatible = "rockchip,rk3288-io-voltage-domain";
-               rockchip,grf = <&grf>;
-
-               audio-supply = <&vcc18_codec>;
-               bb-supply = <&vcc33_io>;
-               dvp-supply = <&vcc_18>;
-               flash0-supply = <&vcc18_flashio>;
-               gpio1830-supply = <&vcc33_io>;
-               gpio30-supply = <&vcc33_io>;
-               lcdc-supply = <&vcc33_lcd>;
-               sdcard-supply = <&vccio_sd>;
-               wifi-supply = <&vcc18_wl>;
-       };
 };
 
 &cpu0 {
@@ -503,6 +488,19 @@
        clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
 };
 
+&io_domains {
+       audio-supply = <&vcc18_codec>;
+       bb-supply = <&vcc33_io>;
+       dvp-supply = <&vcc_18>;
+       flash0-supply = <&vcc18_flashio>;
+       gpio1830-supply = <&vcc33_io>;
+       gpio30-supply = <&vcc33_io>;
+       lcdc-supply = <&vcc33_lcd>;
+       sdcard-supply = <&vccio_sd>;
+       wifi-supply = <&vcc18_wl>;
+       status = "okay";
+};
+
 &wdt {
        status = "okay";
 };

diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 8c394c1..dd1d989 100644 (file)
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -7,13 +7,16 @@
 #include <dt-bindings/clock/rk3288-cru.h>
 #include <dt-bindings/power/rk3288-power.h>
 #include <dt-bindings/thermal/thermal.h>
-#include <dt-bindings/video/rk3288.h>
-#include "skeleton.dtsi"
+#include <dt-bindings/soc/rockchip,boot-mode.h>
 
 / {
+       #address-cells = <1>;
+       #size-cells = <1>;
+
        compatible = "rockchip,rk3288";
 
        interrupt-parent = <&gic>;
+
        aliases {
                ethernet0 = &gmac;
                i2c0 = &i2c0;
@@ -672,9 +675,7 @@
                #pwm-cells = <3>;
                pinctrl-names = "default";
                pinctrl-0 = <&pwm0_pin>;
-               clocks = <&cru PCLK_PWM>;
-               clock-names = "pwm";
-               rockchip,grf = <&grf>;
+               clocks = <&cru PCLK_RKPWM>;
                status = "disabled";
        };
 
@@ -684,9 +685,7 @@
                #pwm-cells = <3>;
                pinctrl-names = "default";
                pinctrl-0 = <&pwm1_pin>;
-               clocks = <&cru PCLK_PWM>;
-               clock-names = "pwm";
-               rockchip,grf = <&grf>;
+               clocks = <&cru PCLK_RKPWM>;
                status = "disabled";
        };
 
@@ -696,21 +695,17 @@
                #pwm-cells = <3>;
                pinctrl-names = "default";
                pinctrl-0 = <&pwm2_pin>;
-               clocks = <&cru PCLK_PWM>;
-               clock-names = "pwm";
-               rockchip,grf = <&grf>;
+               clocks = <&cru PCLK_RKPWM>;
                status = "disabled";
        };
 
        pwm3: pwm@ff680030 {
                compatible = "rockchip,rk3288-pwm";
                reg = <0xff680030 0x10>;
-               #pwm-cells = <2>;
+               #pwm-cells = <3>;
                pinctrl-names = "default";
                pinctrl-0 = <&pwm3_pin>;
-               clocks = <&cru PCLK_PWM>;
-               clock-names = "pwm";
-               rockchip,grf = <&grf>;
+               clocks = <&cru PCLK_RKPWM>;
                status = "disabled";
        };
 
@@ -732,8 +727,128 @@
        };
 
        pmu: power-management@ff730000 {
-               compatible = "rockchip,rk3288-pmu", "syscon";
+               compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
                reg = <0xff730000 0x100>;
+
+               power: power-controller {
+                       compatible = "rockchip,rk3288-power-controller";
+                       #power-domain-cells = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       assigned-clocks = <&cru SCLK_EDP_24M>;
+                       assigned-clock-parents = <&xin24m>;
+
+                       /*
+                        * Note: Although SCLK_* are the working clocks
+                        * of device without including on the NOC, needed for
+                        * synchronous reset.
+                        *
+                        * The clocks on the which NOC:
+                        * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
+                        * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
+                        * ACLK_RGA is on ACLK_RGA_NIU.
+                        * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
+                        *
+                        * Which clock are device clocks:
+                        *      clocks          devices
+                        *      *_IEP           IEP:Image Enhancement Processor
+                        *      *_ISP           ISP:Image Signal Processing
+                        *      *_VIP           VIP:Video Input Processor
+                        *      *_VOP*          VOP:Visual Output Processor
+                        *      *_RGA           RGA
+                        *      *_EDP*          EDP
+                        *      *_LVDS_*        LVDS
+                        *      *_HDMI          HDMI
+                        *      *_MIPI_*        MIPI
+                        */
+                       power-domain@RK3288_PD_VIO {
+                               reg = <RK3288_PD_VIO>;
+                               clocks = <&cru ACLK_IEP>,
+                                        <&cru ACLK_ISP>,
+                                        <&cru ACLK_RGA>,
+                                        <&cru ACLK_VIP>,
+                                        <&cru ACLK_VOP0>,
+                                        <&cru ACLK_VOP1>,
+                                        <&cru DCLK_VOP0>,
+                                        <&cru DCLK_VOP1>,
+                                        <&cru HCLK_IEP>,
+                                        <&cru HCLK_ISP>,
+                                        <&cru HCLK_RGA>,
+                                        <&cru HCLK_VIP>,
+                                        <&cru HCLK_VOP0>,
+                                        <&cru HCLK_VOP1>,
+                                        <&cru PCLK_EDP_CTRL>,
+                                        <&cru PCLK_HDMI_CTRL>,
+                                        <&cru PCLK_LVDS_PHY>,
+                                        <&cru PCLK_MIPI_CSI>,
+                                        <&cru PCLK_MIPI_DSI0>,
+                                        <&cru PCLK_MIPI_DSI1>,
+                                        <&cru SCLK_EDP_24M>,
+                                        <&cru SCLK_EDP>,
+                                        <&cru SCLK_ISP_JPE>,
+                                        <&cru SCLK_ISP>,
+                                        <&cru SCLK_RGA>;
+                               pm_qos = <&qos_vio0_iep>,
+                                        <&qos_vio1_vop>,
+                                        <&qos_vio1_isp_w0>,
+                                        <&qos_vio1_isp_w1>,
+                                        <&qos_vio0_vop>,
+                                        <&qos_vio0_vip>,
+                                        <&qos_vio2_rga_r>,
+                                        <&qos_vio2_rga_w>,
+                                        <&qos_vio1_isp_r>;
+                               #power-domain-cells = <0>;
+                       };
+
+                       /*
+                        * Note: The following 3 are HEVC(H.265) clocks,
+                        * and on the ACLK_HEVC_NIU (NOC).
+                        */
+                       power-domain@RK3288_PD_HEVC {
+                               reg = <RK3288_PD_HEVC>;
+                               clocks = <&cru ACLK_HEVC>,
+                                        <&cru SCLK_HEVC_CABAC>,
+                                        <&cru SCLK_HEVC_CORE>;
+                               pm_qos = <&qos_hevc_r>,
+                                        <&qos_hevc_w>;
+                               #power-domain-cells = <0>;
+                       };
+
+                       /*
+                        * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
+                        * (video endecoder & decoder) clocks that on the
+                        * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
+                        */
+                       power-domain@RK3288_PD_VIDEO {
+                               reg = <RK3288_PD_VIDEO>;
+                               clocks = <&cru ACLK_VCODEC>,
+                                        <&cru HCLK_VCODEC>;
+                               pm_qos = <&qos_video>;
+                               #power-domain-cells = <0>;
+                       };
+
+                       /*
+                        * Note: ACLK_GPU is the GPU clock,
+                        * and on the ACLK_GPU_NIU (NOC).
+                        */
+                       power-domain@RK3288_PD_GPU {
+                               reg = <RK3288_PD_GPU>;
+                               clocks = <&cru ACLK_GPU>;
+                               pm_qos = <&qos_gpu_r>,
+                                        <&qos_gpu_w>;
+                               #power-domain-cells = <0>;
+                       };
+               };
+
+               reboot-mode {
+                       compatible = "syscon-reboot-mode";
+                       offset = <0x94>;
+                       mode-normal = <BOOT_NORMAL>;
+                       mode-recovery = <BOOT_RECOVERY>;
+                       mode-bootloader = <BOOT_FASTBOOT>;
+                       mode-loader = <BOOT_BL_DOWNLOAD>;
+               };
        };
 
        sgrf: syscon@ff740000 {
@@ -760,8 +875,58 @@
        };
 
        grf: syscon@ff770000 {
-               compatible = "rockchip,rk3288-grf", "syscon";
+               compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
                reg = <0xff770000 0x1000>;
+
+               edp_phy: edp-phy {
+                       compatible = "rockchip,rk3288-dp-phy";
+                       clocks = <&cru SCLK_EDP_24M>;
+                       clock-names = "24m";
+                       #phy-cells = <0>;
+                       status = "disabled";
+               };
+
+               io_domains: io-domains {
+                       compatible = "rockchip,rk3288-io-voltage-domain";
+                       status = "disabled";
+               };
+
+               usbphy: usbphy {
+                       compatible = "rockchip,rk3288-usb-phy";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+
+                       usbphy0: usb-phy@320 {
+                               #phy-cells = <0>;
+                               reg = <0x320>;
+                               clocks = <&cru SCLK_OTGPHY0>;
+                               clock-names = "phyclk";
+                               #clock-cells = <0>;
+                               resets = <&cru SRST_USBOTG_PHY>;
+                               reset-names = "phy-reset";
+                       };
+
+                       usbphy1: usb-phy@334 {
+                               #phy-cells = <0>;
+                               reg = <0x334>;
+                               clocks = <&cru SCLK_OTGPHY1>;
+                               clock-names = "phyclk";
+                               #clock-cells = <0>;
+                               resets = <&cru SRST_USBHOST0_PHY>;
+                               reset-names = "phy-reset";
+                       };
+
+                       usbphy2: usb-phy@348 {
+                               #phy-cells = <0>;
+                               reg = <0x348>;
+                               clocks = <&cru SCLK_OTGPHY2>;
+                               clock-names = "phyclk";
+                               #clock-cells = <0>;
+                               resets = <&cru SRST_USBHOST1_PHY>;
+                               reset-names = "phy-reset";
+                       };
+               };
        };
 
        wdt: watchdog@ff800000 {
@@ -848,7 +1013,7 @@
 
        vopb: vop@ff930000 {
                compatible = "rockchip,rk3288-vop";
-               reg = <0xff930000 0x19c>;
+               reg = <0xff930000 0x19c>, <0xff931000 0x1000>;
                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
                clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -862,24 +1027,24 @@
                        #address-cells = <1>;
                        #size-cells = <0>;
 
-                       vopb_out_edp: endpoint@0 {
+                       vopb_out_hdmi: endpoint@0 {
                                reg = <0>;
-                               remote-endpoint = <&edp_in_vopb>;
+                               remote-endpoint = <&hdmi_in_vopb>;
                        };
 
-                       vopb_out_hdmi: endpoint@1 {
+                       vopb_out_edp: endpoint@1 {
                                reg = <1>;
-                               remote-endpoint = <&hdmi_in_vopb>;
+                               remote-endpoint = <&edp_in_vopb>;
                        };
 
-                       vopb_out_lvds: endpoint@2 {
+                       vopb_out_mipi: endpoint@2 {
                                reg = <2>;
-                               remote-endpoint = <&lvds_in_vopb>;
+                               remote-endpoint = <&mipi_in_vopb>;
                        };
 
-                       vopb_out_mipi: endpoint@3 {
+                       vopb_out_lvds: endpoint@3 {
                                reg = <3>;
-                               remote-endpoint = <&mipi_in_vopb>;
+                               remote-endpoint = <&lvds_in_vopb>;
                        };
                };
        };
@@ -897,7 +1062,7 @@
 
        vopl: vop@ff940000 {
                compatible = "rockchip,rk3288-vop";
-               reg = <0xff940000 0x19c>;
+               reg = <0xff940000 0x19c>, <0xff941000 0x1000>;
                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
                clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -911,24 +1076,24 @@
                        #address-cells = <1>;
                        #size-cells = <0>;
 
-                       vopl_out_edp: endpoint@0 {
+                       vopl_out_hdmi: endpoint@0 {
                                reg = <0>;
-                               remote-endpoint = <&edp_in_vopl>;
+                               remote-endpoint = <&hdmi_in_vopl>;
                        };
 
-                       vopl_out_hdmi: endpoint@1 {
+                       vopl_out_edp: endpoint@1 {
                                reg = <1>;
-                               remote-endpoint = <&hdmi_in_vopl>;
+                               remote-endpoint = <&edp_in_vopl>;
                        };
 
-                       vopl_out_lvds: endpoint@2 {
+                       vopl_out_mipi: endpoint@2 {
                                reg = <2>;
-                               remote-endpoint = <&lvds_in_vopl>;
+                               remote-endpoint = <&mipi_in_vopl>;
                        };
 
-                       vopl_out_mipi: endpoint@3 {
+                       vopl_out_lvds: endpoint@3 {
                                reg = <3>;
-                               remote-endpoint = <&mipi_in_vopl>;
+                               remote-endpoint = <&lvds_in_vopl>;
                        };
                };
        };
@@ -945,11 +1110,11 @@
        };
 
        mipi_dsi: mipi@ff960000 {
-               compatible = "rockchip,rk3288_mipi_dsi";
+               compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
                reg = <0xff960000 0x4000>;
                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cru PCLK_MIPI_DSI0>;
-               clock-names = "pclk_mipi";
+               clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
+               clock-names = "ref", "pclk";
                power-domains = <&power RK3288_PD_VIO>;
                rockchip,grf = <&grf>;
                status = "disabled";
@@ -975,7 +1140,7 @@
                reg = <0xff96c000 0x4000>;
                clocks = <&cru PCLK_LVDS_PHY>;
                clock-names = "pclk_lvds";
-               pinctrl-names = "default";
+               pinctrl-names = "lcdc";
                pinctrl-0 = <&lcdc_ctl>;
                power-domains = <&power RK3288_PD_VIO>;
                rockchip,grf = <&grf>;
@@ -1004,19 +1169,24 @@
        };
 
        edp: dp@ff970000 {
-               compatible = "rockchip,rk3288-edp";
+               compatible = "rockchip,rk3288-dp";
                reg = <0xff970000 0x4000>;
                interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
-               clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
+               clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+               clock-names = "dp", "pclk";
+               phys = <&edp_phy>;
+               phy-names = "dp";
+               power-domains = <&power RK3288_PD_VIO>;
                resets = <&cru SRST_EDP>;
-               reset-names = "edp";
+               reset-names = "dp";
                rockchip,grf = <&grf>;
-               power-domains = <&power RK3288_PD_VIO>;
                status = "disabled";
 
                ports {
-                       edp_in: port {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       edp_in: port@0 {
+                               reg = <0>;
                                #address-cells = <1>;
                                #size-cells = <0>;
                                edp_in_vopb: endpoint@0 {
@@ -1038,8 +1208,8 @@
                #sound-dai-cells = <0>;
                rockchip,grf = <&grf>;
                interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
-               clock-names = "iahb", "isfr";
+               clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
+               clock-names = "iahb", "isfr", "cec";
                power-domains = <&power RK3288_PD_VIO>;
                status = "disabled";
 
@@ -1241,39 +1411,6 @@
                interrupts = <GIC_PPI 9 0xf04>;
        };
 
-       cpuidle: cpuidle {
-               compatible = "rockchip,rk3288-cpuidle";
-       };
-
-       usbphy: phy {
-               compatible = "rockchip,rk3288-usb-phy";
-               rockchip,grf = <&grf>;
-               #address-cells = <1>;
-               #size-cells = <0>;
-               status = "disabled";
-
-               usbphy0: usb-phy0 {
-                       #phy-cells = <0>;
-                       reg = <0x320>;
-                       clocks = <&cru SCLK_OTGPHY0>;
-                       clock-names = "phyclk";
-               };
-
-               usbphy1: usb-phy1 {
-                       #phy-cells = <0>;
-                       reg = <0x334>;
-                       clocks = <&cru SCLK_OTGPHY1>;
-                       clock-names = "phyclk";
-               };
-
-               usbphy2: usb-phy2 {
-                       #phy-cells = <0>;
-                       reg = <0x348>;
-                       clocks = <&cru SCLK_OTGPHY2>;
-                       clock-names = "phyclk";
-               };
-       };
-
        pinctrl: pinctrl {
                compatible = "rockchip,rk3288-pinctrl";
                rockchip,grf = <&grf>;
@@ -1860,62 +1997,4 @@
                        };
                };
        };
-
-       power: power-controller {
-               compatible = "rockchip,rk3288-power-controller";
-               #power-domain-cells = <1>;
-               rockchip,pmu = <&pmu>;
-               #address-cells = <1>;
-               #size-cells = <0>;
-
-               pd_gpu {
-                       reg = <RK3288_PD_GPU>;
-                       clocks = <&cru ACLK_GPU>;
-               };
-
-               pd_hevc {
-                       reg = <RK3288_PD_HEVC>;
-                       clocks = <&cru ACLK_HEVC>,
-                                <&cru SCLK_HEVC_CABAC>,
-                                <&cru SCLK_HEVC_CORE>,
-                                <&cru HCLK_HEVC>;
-               };
-
-               pd_vio {
-                       reg = <RK3288_PD_VIO>;
-                       clocks = <&cru ACLK_IEP>,
-                                <&cru ACLK_ISP>,
-                                <&cru ACLK_RGA>,
-                                <&cru ACLK_VIP>,
-                                <&cru ACLK_VOP0>,
-                                <&cru ACLK_VOP1>,
-                                <&cru DCLK_VOP0>,
-                                <&cru DCLK_VOP1>,
-                                <&cru HCLK_IEP>,
-                                <&cru HCLK_ISP>,
-                                <&cru HCLK_RGA>,
-                                <&cru HCLK_VIP>,
-                                <&cru HCLK_VOP0>,
-                                <&cru HCLK_VOP1>,
-                                <&cru PCLK_EDP_CTRL>,
-                                <&cru PCLK_HDMI_CTRL>,
-                                <&cru PCLK_LVDS_PHY>,
-                                <&cru PCLK_MIPI_CSI>,
-                                <&cru PCLK_MIPI_DSI0>,
-                                <&cru PCLK_MIPI_DSI1>,
-                                <&cru SCLK_EDP_24M>,
-                                <&cru SCLK_EDP>,
-                                <&cru SCLK_HDMI_CEC>,
-                                <&cru SCLK_HDMI_HDCP>,
-                                <&cru SCLK_ISP_JPE>,
-                                <&cru SCLK_ISP>,
-                                <&cru SCLK_RGA>;
-               };
-
-               pd_video {
-                       reg = <RK3288_PD_VIDEO>;
-                       clocks = <&cru ACLK_VCODEC>,
-                                <&cru HCLK_VCODEC>;
-               };
-       };
 };

diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
index 4e79173..d183e93 100644 (file)
--- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
@@ -16,3 +16,7 @@
        bootph-all;
        status = "okay";
 };
+
+&vcc5v0_usb30 {
+       regulator-boot-on;
+};

diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 9ef1e84..801c91a 100644 (file)
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -13,6 +13,14 @@
        };
 };
 
+&sdhci {
+       cap-mmc-highspeed;
+       mmc-ddr-1_8v;
+       mmc-hs200-1_8v;
+       mmc-hs400-1_8v;
+       mmc-hs400-enhanced-strobe;
+};
+
 &sdmmc2 {
        status = "disabled";
 };
@@ -26,3 +34,11 @@
        bootph-all;
        status = "okay";
 };
+
+&vcc5v0_usb_host {
+       regulator-boot-on;
+};
+
+&vcc5v0_usb_hub {
+       regulator-boot-on;
+};

diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
index 3235bd3..373f369 100644 (file)
--- a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
@@ -18,7 +18,5 @@
 
 &sdmmc {
        bus-width = <4>;
-       bootph-all;
-       u-boot,spl-fifo-mode;
        status = "okay";
 };

diff --git a/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi b/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi
new file mode 100644 (file)
index 0000000..bd2e259
--- /dev/null
+++ b/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+       aliases {
+               mmc0 = &sdmmc;
+               mmc1 = &sdhci;
+       };
+
+       chosen {
+               u-boot,spl-boot-order = &sdhci;
+       };
+};
+
+&sdhci {
+       bootph-all;
+};

diff --git a/arch/arm/dts/rk3588-evb1-v10.dts b/arch/arm/dts/rk3588-evb1-v10.dts
new file mode 100644 (file)
index 0000000..b91af02
--- /dev/null
+++ b/arch/arm/dts/rk3588-evb1-v10.dts
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3588.dtsi"
+
+/ {
+       model = "Rockchip RK3588 EVB1 V10 Board";
+       compatible = "rockchip,rk3588-evb1-v10", "rockchip,rk3588";
+
+       aliases {
+               mmc0 = &sdhci;
+               serial2 = &uart2;
+       };
+
+       chosen {
+               stdout-path = "serial2:1500000n8";
+       };
+
+       backlight: backlight {
+               compatible = "pwm-backlight";
+               power-supply = <&vcc12v_dcin>;
+               pwms = <&pwm2 0 25000 0>;
+       };
+
+       vcc12v_dcin: vcc12v-dcin-regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc12v_dcin";
+               regulator-always-on;
+               regulator-boot-on;
+               regulator-min-microvolt = <12000000>;
+               regulator-max-microvolt = <12000000>;
+       };
+
+       vcc5v0_sys: vcc5v0-sys-regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc5v0_sys";
+               regulator-always-on;
+               regulator-boot-on;
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               vin-supply = <&vcc12v_dcin>;
+       };
+};
+
+&gmac0 {
+       clock_in_out = "output";
+       phy-handle = <&rgmii_phy>;
+       phy-mode = "rgmii-rxid";
+       pinctrl-0 = <&gmac0_miim
+                    &gmac0_tx_bus2
+                    &gmac0_rx_bus2
+                    &gmac0_rgmii_clk
+                    &gmac0_rgmii_bus>;
+       pinctrl-names = "default";
+       rx_delay = <0x00>;
+       tx_delay = <0x43>;
+       status = "okay";
+};
+
+&i2c2 {
+       status = "okay";
+
+       hym8563: rtc@51 {
+               compatible = "haoyu,hym8563";
+               reg = <0x51>;
+               #clock-cells = <0>;
+               clock-output-names = "hym8563";
+               pinctrl-names = "default";
+               pinctrl-0 = <&hym8563_int>;
+               interrupt-parent = <&gpio0>;
+               interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;
+               wakeup-source;
+       };
+};
+
+&mdio0 {
+       rgmii_phy: ethernet-phy@1 {
+               /* RTL8211F */
+               compatible = "ethernet-phy-id001c.c916";
+               reg = <0x1>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&rtl8211f_rst>;
+               reset-assert-us = <20000>;
+               reset-deassert-us = <100000>;
+               reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+       };
+};
+
+&pinctrl {
+       rtl8211f {
+               rtl8211f_rst: rtl8211f-rst {
+                       rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+
+       };
+
+       hym8563 {
+               hym8563_int: hym8563-int {
+                       rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+       };
+};
+
+&pwm2 {
+       status = "okay";
+};
+
+&sdhci {
+       bus-width = <8>;
+       no-sdio;
+       no-sd;
+       non-removable;
+       max-frequency = <200000000>;
+       mmc-hs400-1_8v;
+       mmc-hs400-enhanced-strobe;
+       status = "okay";
+};
+
+&uart2 {
+       pinctrl-0 = <&uart2m0_xfer>;
+       status = "okay";
+};

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index bee4c32..85075bf 100644 (file)
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -7,16 +7,23 @@
 
 / {
        aliases {
-               mmc0 = &sdmmc;
+               mmc1 = &sdmmc;
        };
 
        chosen {
-               u-boot,spl-boot-order = &sdmmc;
+               u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
        };
 };
 
 &sdmmc {
        bus-width = <4>;
-       bootph-pre-ram;
        status = "okay";
 };
+
+&sdhci {
+       cap-mmc-highspeed;
+       mmc-ddr-1_8v;
+       mmc-hs200-1_8v;
+       pinctrl-names = "default";
+       pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>;
+};

diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 1e225d7..5201ba2 100644 (file)
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -18,20 +18,6 @@
                reg = <0x0 0xfd58a000 0x0 0x2000>;
        };
 
-       sdmmc: mmc@fe2c0000 {
-               compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
-               reg = <0x0 0xfe2c0000 0x0 0x4000>;
-               interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
-               clocks = <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>,
-                        <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>;
-               clock-names = "ciu-drive", "ciu-sample", "biu", "ciu";
-               fifo-depth = <0x100>;
-               max-frequency = <200000000>;
-               pinctrl-names = "default";
-               pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
-               status = "disabled";
-       };
-
        otp: nvmem@fecc0000 {
                compatible = "rockchip,rk3588-otp";
                reg = <0x0 0xfecc0000 0x0 0x400>;
@@ -43,6 +29,12 @@
                        reg = <0x07 0x10>;
                };
        };
+
+       rng: rng@fe378000 {
+               compatible = "rockchip,trngv1";
+               reg = <0x0 0xfe378000 0x0 0x200>;
+               status = "disabled";
+       };
 };
 
 &xin24m {
@@ -60,6 +52,23 @@
        status = "okay";
 };
 
+&scmi {
+       bootph-pre-ram;
+};
+
+&scmi_clk {
+       bootph-pre-ram;
+};
+
+&sdmmc {
+       bootph-pre-ram;
+       u-boot,spl-fifo-mode;
+};
+
+&sdhci {
+       bootph-pre-ram;
+};
+
 &uart2 {
        clock-frequency = <24000000>;
        bootph-pre-ram;

diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi
index 005cde6..fca8503 100644 (file)
--- a/arch/arm/dts/rk3588s.dtsi
+++ b/arch/arm/dts/rk3588s.dtsi
@@ -1099,6 +1099,21 @@
                };
        };
 
+       sdmmc: mmc@fe2c0000 {
+               compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
+               reg = <0x0 0xfe2c0000 0x0 0x4000>;
+               interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
+                        <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+               clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+               fifo-depth = <0x100>;
+               max-frequency = <200000000>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
+               power-domains = <&power RK3588_PD_SDMMC>;
+               status = "disabled";
+       };
+
        sdhci: mmc@fe2e0000 {
                compatible = "rockchip,rk3588-dwcmshc";
                reg = <0x0 0xfe2e0000 0x0 0x10000>;

diff --git a/arch/arm/dts/rk3xxx-u-boot.dtsi b/arch/arm/dts/rk3xxx-u-boot.dtsi
index f50bacd..6af6a45 100644 (file)
--- a/arch/arm/dts/rk3xxx-u-boot.dtsi
+++ b/arch/arm/dts/rk3xxx-u-boot.dtsi
@@ -33,3 +33,7 @@
 &uart2 {
        clock-frequency = <24000000>;
 };
+
+&xin24m {
+       bootph-all;
+};

diff --git a/arch/arm/dts/rk3xxx.dtsi b/arch/arm/dts/rk3xxx.dtsi
index 616a828..cb4e42e 100644 (file)
--- a/arch/arm/dts/rk3xxx.dtsi
+++ b/arch/arm/dts/rk3xxx.dtsi
@@ -76,6 +76,13 @@
                reg = <0x1013c200 0x20>;
                interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
                clocks = <&cru CORE_PERI>;
+               status = "disabled";
+               /* The clock source and the sched_clock provided by the arm_global_timer
+                * on Rockchip rk3066a/rk3188 are quite unstable because their rates
+                * depend on the CPU frequency.
+                * Keep the arm_global_timer disabled in order to have the
+                * DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default.
+                */
        };
 
        local_timer: local-timer@1013c600 {
@@ -186,8 +193,6 @@
                compatible = "snps,arc-emac";
                reg = <0x10204000 0x3c>;
                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-               #address-cells = <1>;
-               #size-cells = <0>;
 
                rockchip,grf = <&grf>;
 

diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
index 3cf51f0..6d82bf6 100644 (file)
--- a/arch/arm/dts/stm32mp131.dtsi
+++ b/arch/arm/dts/stm32mp131.dtsi
@@ -191,6 +191,54 @@
                        dma-requests = <48>;
                };
 
+               fmc: memory-controller@58002000 {
+                       compatible = "st,stm32mp1-fmc2-ebi";
+                       reg = <0x58002000 0x1000>;
+                       ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+                                <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+                                <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+                                <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+                                <4 0 0x80000000 0x10000000>; /* NAND */
+                       #address-cells = <2>;
+                       #size-cells = <1>;
+                       clocks = <&rcc FMC_K>;
+                       resets = <&rcc FMC_R>;
+                       status = "disabled";
+
+                       nand-controller@4,0 {
+                               compatible = "st,stm32mp1-fmc2-nfc";
+                               reg = <4 0x00000000 0x1000>,
+                                     <4 0x08010000 0x1000>,
+                                     <4 0x08020000 0x1000>,
+                                     <4 0x01000000 0x1000>,
+                                     <4 0x09010000 0x1000>,
+                                     <4 0x09020000 0x1000>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
+                                      <&mdma 24 0x2 0x12000a08 0x0 0x0>,
+                                      <&mdma 25 0x2 0x12000a0a 0x0 0x0>;
+                               dma-names = "tx", "rx", "ecc";
+                               status = "disabled";
+                       };
+               };
+
+               qspi: spi@58003000 {
+                       compatible = "st,stm32f469-qspi";
+                       reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
+                       reg-names = "qspi", "qspi_mm";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+                       dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>,
+                              <&mdma 26 0x2 0x10100008 0x0 0x0>;
+                       dma-names = "tx", "rx";
+                       clocks = <&rcc QSPI_K>;
+                       resets = <&rcc QSPI_R>;
+                       status = "disabled";
+               };
+
                sdmmc1: mmc@58005000 {
                        compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
                        arm,primecell-periphid = <0x20253180>;

diff --git a/arch/arm/dts/sun6i-a31-mixtile-loftq.dts b/arch/arm/dts/sun6i-a31-mixtile-loftq.dts
index dde9bdf..bd98fb3 100644 (file)
--- a/arch/arm/dts/sun6i-a31-mixtile-loftq.dts
+++ b/arch/arm/dts/sun6i-a31-mixtile-loftq.dts
@@ -6,6 +6,9 @@
  */
 
 /dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
 #include "sun6i-a31.dtsi"
 
 / {
@@ -19,6 +22,15 @@
        chosen {
                stdout-path = "serial0:115200n8";
        };
+
+       reg_usb1_vbus: usb1-vbus {
+               compatible = "regulator-fixed";
+               regulator-name = "usb1-vbus";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               enable-active-high;
+               gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */
+       };
 };
 
 &ehci0 {
@@ -56,3 +68,8 @@
        pinctrl-0 = <&uart0_ph_pins>;
        status = "okay";
 };
+
+&usbphy {
+       usb1_vbus-supply = <&reg_usb1_vbus>;
+       status = "okay";
+};

diff --git a/arch/arm/dts/tegra30-u-boot.dtsi b/arch/arm/dts/tegra30-u-boot.dtsi
index 7c11972..3038227 100644 (file)
--- a/arch/arm/dts/tegra30-u-boot.dtsi
+++ b/arch/arm/dts/tegra30-u-boot.dtsi
@@ -1,3 +1,12 @@
 #include <config.h>
 
 #include "tegra-u-boot.dtsi"
+
+/ {
+       host1x@50000000 {
+               bootph-all;
+               dc@54200000 {
+                       bootph-all;
+               };
+       };
+};

diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 90e66c7..f002ebc 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -194,6 +194,5 @@ int rockchip_get_clk(struct udevice **devp);
  * Return: 0 success, or error value
  */
 int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
-int rockchip_get_scmi_clk(struct udevice **devp);
 
 #endif

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
index 3ea59e9..7f4a908 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
@@ -11,12 +11,12 @@
 #define KHz            1000
 #define OSC_HZ         (24 * MHz)
 
-#define CPU_PVTPLL_HZ  (1008 * MHz)
 #define LPLL_HZ                (816 * MHz)
 #define GPLL_HZ                (1188 * MHz)
 #define CPLL_HZ                (1500 * MHz)
 #define NPLL_HZ         (850 * MHz)
 #define PPLL_HZ                (1100 * MHz)
+#define SPLL_HZ                (702 * MHz)
 
 /* RK3588 pll id */
 enum rk3588_pll_id {
@@ -447,5 +447,22 @@ enum {
        CLK_I2C0_SEL_MASK                       = 1 << CLK_I2C0_SEL_SHIFT,
        CLK_I2C_SEL_200M                        = 0,
        CLK_I2C_SEL_100M,
+
+       /* SECURECRU_CLKSEL_CON01 */
+       SCMI_HCLK_SD_SEL_SHIFT                  = 2,
+       SCMI_HCLK_SD_SEL_MASK                   = 3 << SCMI_HCLK_SD_SEL_SHIFT,
+       SCMI_HCLK_SD_SEL_150M                   = 0,
+       SCMI_HCLK_SD_SEL_100M,
+       SCMI_HCLK_SD_SEL_50M,
+       SCMI_HCLK_SD_SEL_24M,
+
+       /* SECURECRU_CLKSEL_CON03 */
+       SCMI_CCLK_SD_SEL_SHIFT                  = 12,
+       SCMI_CCLK_SD_SEL_MASK                   = 3 << SCMI_CCLK_SD_SEL_SHIFT,
+       SCMI_CCLK_SD_SEL_GPLL                   = 0,
+       SCMI_CCLK_SD_SEL_SPLL,
+       SCMI_CCLK_SD_SEL_24M,
+       SCMI_CCLK_SD_DIV_SHIFT                  = 6,
+       SCMI_CCLK_SD_DIV_MASK                   = 0x3f << SCMI_CCLK_SD_DIV_SHIFT,
 };
 #endif

diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h
index 46b7e07..30f5680 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -16,8 +16,8 @@
        b       reset
        .space  0x7c
 
-       .word   0xe28f0058      // add     r0, pc, #88
-       .word   0xe59f1054      // ldr     r1, [pc, #84]
+       .word   0xe28f0070      // add     r0, pc, #112  // @(fel_stash - .)
+       .word   0xe59f106c      // ldr     r1, [pc, #108] // fel_stash - .
        .word   0xe0800001      // add     r0, r0, r1
        .word   0xe580d000      // str     sp, [r0]
        .word   0xe580e004      // str     lr, [r0, #4]
@@ -28,8 +28,12 @@
        .word   0xee1cef10      // mrc     15, 0, lr, cr12, cr0, {0}
        .word   0xe580e010      // str     lr, [r0, #16]
 
-       .word   0xe59f1024      // ldr     r1, [pc, #36] ; 0x170000a0
-       .word   0xe59f0024      // ldr     r0, [pc, #36] ; CONFIG_*_TEXT_BASE
+       .word   0xe59f1034      // ldr     r1, [pc, #52] ; RVBAR_ADDRESS
+       .word   0xe59f0034      // ldr     r0, [pc, #52] ; SUNXI_SRAMC_BASE
+       .word   0xe5900024      // ldr     r0, [r0, #36] ; SRAM_VER_REG
+       .word   0xe21000ff      // ands    r0, r0, #255    ; 0xff
+       .word   0x159f102c      // ldrne   r1, [pc, #44] ; RVBAR_ALTERNATIVE
+       .word   0xe59f002c      // ldr     r0, [pc, #44] ; CONFIG_*TEXT_BASE
        .word   0xe5810000      // str     r0, [r1]
        .word   0xf57ff04f      // dsb     sy
        .word   0xf57ff06f      // isb     sy
@@ -39,11 +43,10 @@
        .word   0xf57ff06f      // isb     sy
        .word   0xe320f003      // wfi
        .word   0xeafffffd      // b       @wfi
-#ifndef CONFIG_SUN50I_GEN_H6
-       .word   0x017000a0      // writeable RVBAR mapping address
-#else
-       .word   0x09010040      // writeable RVBAR mapping address
-#endif
+
+       .word   CONFIG_SUNXI_RVBAR_ADDRESS      // writable RVBAR mapping addr
+       .word   SUNXI_SRAMC_BASE
+       .word   CONFIG_SUNXI_RVBAR_ALTERNATIVE  // address for die variant
 #ifdef CONFIG_SPL_BUILD
        .word   CONFIG_SPL_TEXT_BASE
 #else

diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
index 134679d..6db869c 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
@@ -137,6 +137,14 @@ check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240);
 #define MSTR_ACTIVE_RANKS(x)   (((x == 2) ? 3 : 1) << 24)
 #define MSTR_BURST_LENGTH(x)   (((x) >> 1) << 16)
 
+#define TPR10_CA_BIT_DELAY     BIT(16)
+#define TPR10_DX_BIT_DELAY0    BIT(17)
+#define TPR10_DX_BIT_DELAY1    BIT(18)
+#define TPR10_WRITE_LEVELING   BIT(20)
+#define TPR10_READ_CALIBRATION BIT(21)
+#define TPR10_READ_TRAINING    BIT(22)
+#define TPR10_WRITE_TRAINING   BIT(23)
+
 struct dram_para {
        u32 clk;
        enum sunxi_dram_type type;
@@ -144,6 +152,15 @@ struct dram_para {
        u8 rows;
        u8 ranks;
        u8 bus_full_width;
+       u32 dx_odt;
+       u32 dx_dri;
+       u32 ca_dri;
+       u32 odt_en;
+       u32 tpr0;
+       u32 tpr2;
+       u32 tpr10;
+       u32 tpr11;
+       u32 tpr12;
 };
 
 

diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h
index 6444af2..7613d84 100644 (file)
--- a/arch/arm/include/asm/arch-tegra/dc.h
+++ b/arch/arm/include/asm/arch-tegra/dc.h
@@ -569,4 +569,12 @@ enum {
 #define DC_N_WINDOWS                   5
 #define DC_REG_SAVE_SPACE              (DC_N_WINDOWS + 5)
 
+#define TEGRA_DSI_A            "dsi@54300000"
+#define TEGRA_DSI_B            "dsi@54400000"
+
+struct tegra_dc_plat {
+       struct udevice *dev;            /* Display controller device */
+       struct dc_ctlr *dc;             /* Display controller regmap */
+};
+
 #endif /* __ASM_ARCH_TEGRA_DC_H */

diff --git a/arch/arm/include/asm/arch-tegra30/display.h b/arch/arm/include/asm/arch-tegra30/display.h
new file mode 100644 (file)
index 0000000..9411525
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/display.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
+#define __ASM_ARCH_TEGRA_DISPLAY_H
+
+#include <asm/arch-tegra/dc.h>
+
+/* This holds information about a window which can be displayed */
+struct disp_ctl_win {
+       enum win_color_depth_id fmt;    /* Color depth/format */
+       unsigned int    bpp;            /* Bits per pixel */
+       phys_addr_t     phys_addr;      /* Physical address in memory */
+       unsigned int    x;              /* Horizontal address offset (bytes) */
+       unsigned int    y;              /* Veritical address offset (bytes) */
+       unsigned int    w;              /* Width of source window */
+       unsigned int    h;              /* Height of source window */
+       unsigned int    stride;         /* Number of bytes per line */
+       unsigned int    out_x;          /* Left edge of output window (col) */
+       unsigned int    out_y;          /* Top edge of output window (row) */
+       unsigned int    out_w;          /* Width of output window in pixels */
+       unsigned int    out_h;          /* Height of output window in pixels */
+};
+
+#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/

diff --git a/arch/arm/include/asm/arch-tegra30/dsi.h b/arch/arm/include/asm/arch-tegra30/dsi.h
new file mode 100644 (file)
index 0000000..7ade132
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/dsi.h
@@ -0,0 +1,217 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef __ASM_ARCH_TEGRA_DSI_H
+#define __ASM_ARCH_TEGRA_DSI_H
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+/* Register definitions for the Tegra display serial interface */
+
+/* DSI syncpoint register 0x000 ~ 0x002 */
+struct dsi_syncpt_reg {
+       /* Address 0x000 ~ 0x002 */
+       uint incr_syncpt;               /* _INCR_SYNCPT_0 */
+       uint incr_syncpt_ctrl;          /* _INCR_SYNCPT_CNTRL_0 */
+       uint incr_syncpt_err;           /* _INCR_SYNCPT_ERROR_0 */
+};
+
+/* DSI misc register 0x008 ~ 0x015 */
+struct dsi_misc_reg {
+       /* Address 0x008 ~ 0x015 */
+       uint ctxsw;                     /* _CTXSW_0 */
+       uint dsi_rd_data;               /* _DSI_RD_DATA_0 */
+       uint dsi_wr_data;               /* _DSI_WR_DATA_0 */
+       uint dsi_pwr_ctrl;              /* _DSI_POWER_CONTROL_0 */
+       uint int_enable;                /* _INT_ENABLE_0 */
+       uint int_status;                /* _INT_STATUS_0 */
+       uint int_mask;                  /* _INT_MASK_0 */
+       uint host_dsi_ctrl;             /* _HOST_DSI_CONTROL_0 */
+       uint dsi_ctrl;                  /* _DSI_CONTROL_0 */
+       uint dsi_sol_delay;             /* _DSI_SOL_DELAY_0 */
+       uint dsi_max_threshold;         /* _DSI_MAX_THRESHOLD_0 */
+       uint dsi_trigger;               /* _DSI_TRIGGER_0 */
+       uint dsi_tx_crc;                /* _DSI_TX_CRC_0 */
+       uint dsi_status;                /* _DSI_STATUS_0 */
+};
+
+/* DSI init sequence register 0x01a ~ 0x022 */
+struct dsi_init_seq_reg {
+       /* Address 0x01a ~ 0x022 */
+       uint dsi_init_seq_ctrl;         /* _DSI_INIT_SEQ_CONTROL_0 */
+       uint dsi_init_seq_data_0;       /* _DSI_INIT_SEQ_DATA_0_0 */
+       uint dsi_init_seq_data_1;       /* _DSI_INIT_SEQ_DATA_1_0 */
+       uint dsi_init_seq_data_2;       /* _DSI_INIT_SEQ_DATA_2_0 */
+       uint dsi_init_seq_data_3;       /* _DSI_INIT_SEQ_DATA_3_0 */
+       uint dsi_init_seq_data_4;       /* _DSI_INIT_SEQ_DATA_4_0 */
+       uint dsi_init_seq_data_5;       /* _DSI_INIT_SEQ_DATA_5_0 */
+       uint dsi_init_seq_data_6;       /* _DSI_INIT_SEQ_DATA_6_0 */
+       uint dsi_init_seq_data_7;       /* _DSI_INIT_SEQ_DATA_7_0 */
+};
+
+/* DSI packet sequence register 0x023 ~ 0x02e */
+struct dsi_pkt_seq_reg {
+       /* Address 0x023 ~ 0x02e */
+       uint dsi_pkt_seq_0_lo;          /* _DSI_PKT_SEQ_0_LO_0 */
+       uint dsi_pkt_seq_0_hi;          /* _DSI_PKT_SEQ_0_HI_0 */
+       uint dsi_pkt_seq_1_lo;          /* _DSI_PKT_SEQ_1_LO_0 */
+       uint dsi_pkt_seq_1_hi;          /* _DSI_PKT_SEQ_1_HI_0 */
+       uint dsi_pkt_seq_2_lo;          /* _DSI_PKT_SEQ_2_LO_0 */
+       uint dsi_pkt_seq_2_hi;          /* _DSI_PKT_SEQ_2_HI_0 */
+       uint dsi_pkt_seq_3_lo;          /* _DSI_PKT_SEQ_3_LO_0 */
+       uint dsi_pkt_seq_3_hi;          /* _DSI_PKT_SEQ_3_HI_0 */
+       uint dsi_pkt_seq_4_lo;          /* _DSI_PKT_SEQ_4_LO_0 */
+       uint dsi_pkt_seq_4_hi;          /* _DSI_PKT_SEQ_4_HI_0 */
+       uint dsi_pkt_seq_5_lo;          /* _DSI_PKT_SEQ_5_LO_0 */
+       uint dsi_pkt_seq_5_hi;          /* _DSI_PKT_SEQ_5_HI_0 */
+};
+
+/* DSI packet length register 0x033 ~ 0x037 */
+struct dsi_pkt_len_reg {
+       /* Address 0x033 ~ 0x037 */
+       uint dsi_dcs_cmds;              /* _DSI_DCS_CMDS_0 */
+       uint dsi_pkt_len_0_1;           /* _DSI_PKT_LEN_0_1_0 */
+       uint dsi_pkt_len_2_3;           /* _DSI_PKT_LEN_2_3_0 */
+       uint dsi_pkt_len_4_5;           /* _DSI_PKT_LEN_4_5_0 */
+       uint dsi_pkt_len_6_7;           /* _DSI_PKT_LEN_6_7_0 */
+};
+
+/* DSI PHY timing register 0x03c ~ 0x03f */
+struct dsi_timing_reg {
+       /* Address 0x03c ~ 0x03f */
+       uint dsi_phy_timing_0;          /* _DSI_PHY_TIMING_0_0 */
+       uint dsi_phy_timing_1;          /* _DSI_PHY_TIMING_1_0 */
+       uint dsi_phy_timing_2;          /* _DSI_PHY_TIMING_2_0 */
+       uint dsi_bta_timing;            /* _DSI_BTA_TIMING_0 */
+};
+
+/* DSI timeout register 0x044 ~ 0x046 */
+struct dsi_timeout_reg {
+       /* Address 0x044 ~ 0x046 */
+       uint dsi_timeout_0;             /* _DSI_TIMEOUT_0_0 */
+       uint dsi_timeout_1;             /* _DSI_TIMEOUT_1_0 */
+       uint dsi_to_tally;              /* _DSI_TO_TALLY_0 */
+};
+
+/* DSI PAD control register 0x04b ~ 0x04e */
+struct dsi_pad_ctrl_reg {
+       /* Address 0x04b ~ 0x04e */
+       uint pad_ctrl;                  /* _PAD_CONTROL_0 */
+       uint pad_ctrl_cd;               /* _PAD_CONTROL_CD_0 */
+       uint pad_cd_status;             /* _PAD_CD_STATUS_0 */
+       uint dsi_vid_mode_control;      /* _DSI_VID_MODE_CONTROL_0 */
+};
+
+/* Display Serial Interface (DSI_) regs */
+struct dsi_ctlr {
+       struct dsi_syncpt_reg syncpt;   /* SYNCPT register 0x000 ~ 0x002 */
+       uint reserved0[5];              /* reserved_0[5] */
+
+       struct dsi_misc_reg misc;       /* MISC register 0x008 ~ 0x015 */
+       uint reserved1[4];              /* reserved_1[4] */
+
+       struct dsi_init_seq_reg init;   /* INIT register 0x01a ~ 0x022 */
+       struct dsi_pkt_seq_reg pkt;     /* PKT register 0x023 ~ 0x02e */
+       uint reserved2[4];              /* reserved_2[4] */
+
+       struct dsi_pkt_len_reg len;     /* LEN registers 0x033 ~ 0x037 */
+       uint reserved3[4];              /* reserved_3[4] */
+
+       struct dsi_timing_reg ptiming;  /* TIMING registers 0x03c ~ 0x03f */
+       uint reserved4[4];              /* reserved_4[4] */
+
+       struct dsi_timeout_reg timeout; /* TIMEOUT registers 0x044 ~ 0x046 */
+       uint reserved5[4];              /* reserved_5[4] */
+
+       struct dsi_pad_ctrl_reg pad;    /* PAD registers 0x04b ~ 0x04e */
+};
+
+#define DSI_POWER_CONTROL_ENABLE       BIT(0)
+
+#define DSI_HOST_CONTROL_FIFO_RESET    BIT(21)
+#define DSI_HOST_CONTROL_CRC_RESET     BIT(20)
+#define DSI_HOST_CONTROL_TX_TRIG_SOL   (0 << 12)
+#define DSI_HOST_CONTROL_TX_TRIG_FIFO  (1 << 12)
+#define DSI_HOST_CONTROL_TX_TRIG_HOST  (2 << 12)
+#define DSI_HOST_CONTROL_RAW           BIT(6)
+#define DSI_HOST_CONTROL_HS            BIT(5)
+#define DSI_HOST_CONTROL_FIFO_SEL      BIT(4)
+#define DSI_HOST_CONTROL_IMM_BTA       BIT(3)
+#define DSI_HOST_CONTROL_PKT_BTA       BIT(2)
+#define DSI_HOST_CONTROL_CS            BIT(1)
+#define DSI_HOST_CONTROL_ECC           BIT(0)
+
+#define DSI_CONTROL_HS_CLK_CTRL                BIT(20)
+#define DSI_CONTROL_CHANNEL(c)         (((c) & 0x3) << 16)
+#define DSI_CONTROL_FORMAT(f)          (((f) & 0x3) << 12)
+#define DSI_CONTROL_TX_TRIG(x)         (((x) & 0x3) <<  8)
+#define DSI_CONTROL_LANES(n)           (((n) & 0x3) <<  4)
+#define DSI_CONTROL_DCS_ENABLE         BIT(3)
+#define DSI_CONTROL_SOURCE(s)          (((s) & 0x1) <<  2)
+#define DSI_CONTROL_VIDEO_ENABLE       BIT(1)
+#define DSI_CONTROL_HOST_ENABLE                BIT(0)
+
+#define DSI_TRIGGER_HOST               BIT(1)
+#define DSI_TRIGGER_VIDEO              BIT(0)
+
+#define DSI_STATUS_IDLE                        BIT(10)
+#define DSI_STATUS_UNDERFLOW           BIT(9)
+#define DSI_STATUS_OVERFLOW            BIT(8)
+
+#define DSI_TIMING_FIELD(value, period, hwinc) \
+       ((DIV_ROUND_CLOSEST(value, period) - (hwinc)) & 0xff)
+
+#define DSI_TIMEOUT_LRX(x)             (((x) & 0xffff) << 16)
+#define DSI_TIMEOUT_HTX(x)             (((x) & 0xffff) <<  0)
+#define DSI_TIMEOUT_PR(x)              (((x) & 0xffff) << 16)
+#define DSI_TIMEOUT_TA(x)              (((x) & 0xffff) <<  0)
+
+#define DSI_TALLY_TA(x)                        (((x) & 0xff) << 16)
+#define DSI_TALLY_LRX(x)               (((x) & 0xff) <<  8)
+#define DSI_TALLY_HTX(x)               (((x) & 0xff) <<  0)
+
+#define DSI_PAD_CONTROL_PAD_PULLDN_ENAB(x)     (((x) & 0x1) << 28)
+#define DSI_PAD_CONTROL_PAD_SLEWUPADJ(x)       (((x) & 0x7) << 24)
+#define DSI_PAD_CONTROL_PAD_SLEWDNADJ(x)       (((x) & 0x7) << 20)
+#define DSI_PAD_CONTROL_PAD_PREEMP_EN(x)       (((x) & 0x1) << 19)
+#define DSI_PAD_CONTROL_PAD_PDIO_CLK(x)                (((x) & 0x1) << 18)
+#define DSI_PAD_CONTROL_PAD_PDIO(x)            (((x) & 0x3) << 16)
+#define DSI_PAD_CONTROL_PAD_LPUPADJ(x)         (((x) & 0x3) << 14)
+#define DSI_PAD_CONTROL_PAD_LPDNADJ(x)         (((x) & 0x3) << 12)
+
+/*
+ * pixel format as used in the DSI_CONTROL_FORMAT field
+ */
+enum tegra_dsi_format {
+       TEGRA_DSI_FORMAT_16P,
+       TEGRA_DSI_FORMAT_18NP,
+       TEGRA_DSI_FORMAT_18P,
+       TEGRA_DSI_FORMAT_24P,
+};
+
+/* DSI calibration in VI region */
+#define TEGRA_VI_BASE                  0x54080000
+
+#define CSI_CILA_MIPI_CAL_CONFIG_0     0x22a
+#define  MIPI_CAL_TERMOSA(x)           (((x) & 0x1f) << 0)
+
+#define CSI_CILB_MIPI_CAL_CONFIG_0     0x22b
+#define  MIPI_CAL_TERMOSB(x)           (((x) & 0x1f) << 0)
+
+#define CSI_CIL_PAD_CONFIG             0x229
+#define  PAD_CIL_PDVREG(x)             (((x) & 0x01) << 1)
+
+#define CSI_DSI_MIPI_CAL_CONFIG                0x234
+#define  MIPI_CAL_HSPDOSD(x)           (((x) & 0x1f) << 16)
+#define  MIPI_CAL_HSPUOSD(x)           (((x) & 0x1f) << 8)
+
+#define CSI_MIPIBIAS_PAD_CONFIG                0x235
+#define  PAD_DRIV_DN_REF(x)            (((x) & 0x7) << 16)
+#define  PAD_DRIV_UP_REF(x)            (((x) & 0x7) << 8)
+
+#endif /* __ASM_ARCH_TEGRA_DSI_H */

diff --git a/arch/arm/include/asm/arch-tegra30/pwm.h b/arch/arm/include/asm/arch-tegra30/pwm.h
new file mode 100644 (file)
index 0000000..c314e2b
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/pwm.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Tegra pulse width frequency modulator definitions
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_ARCH_TEGRA30_PWM_H
+#define __ASM_ARCH_TEGRA30_PWM_H
+
+#include <asm/arch-tegra/pwm.h>
+
+#endif /* __ASM_ARCH_TEGRA30_PWM_H */

diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 9f58ced..19a9e11 100644 (file)
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -49,10 +49,13 @@
 #define PTE_TYPE_BLOCK         (1 << 0)
 #define PTE_TYPE_VALID         (1 << 0)
 
-#define PTE_TABLE_PXN          (1UL << 59)
-#define PTE_TABLE_XN           (1UL << 60)
-#define PTE_TABLE_AP           (1UL << 61)
-#define PTE_TABLE_NS           (1UL << 63)
+#define PTE_RDONLY             BIT(7)
+#define PTE_DBM                        BIT(51)
+
+#define PTE_TABLE_PXN          BIT(59)
+#define PTE_TABLE_XN           BIT(60)
+#define PTE_TABLE_AP           BIT(61)
+#define PTE_TABLE_NS           BIT(63)
 
 /*
  * Block
@@ -99,6 +102,15 @@
 #define TCR_TG0_16K            (2 << 14)
 #define TCR_EPD1_DISABLE       (1 << 23)
 
+#define TCR_EL1_HA             BIT(39)
+#define TCR_EL1_HD             BIT(40)
+
+#define TCR_EL2_HA             BIT(21)
+#define TCR_EL2_HD             BIT(22)
+
+#define TCR_EL3_HA             BIT(21)
+#define TCR_EL3_HD             BIT(22)
+
 #define TCR_EL1_RSVD           (1U << 31)
 #define TCR_EL2_RSVD           (1U << 31 | 1 << 23)
 #define TCR_EL3_RSVD           (1U << 31 | 1 << 23)

diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 8698783..0c13075 100644 (file)
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -52,6 +52,8 @@ struct arch_global_data {
 #if defined(CONFIG_ARM64)
        unsigned long tlb_fillptr;
        unsigned long tlb_emerg;
+       unsigned int first_block_level;
+       bool has_hafdbs;
 #endif
 #endif
 #ifdef CFG_SYS_MEM_RESERVE_SECURE

diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c
index 2e09141..125dc0b 100644 (file)
--- a/arch/arm/lib/interrupts_64.c
+++ b/arch/arm/lib/interrupts_64.c
@@ -37,6 +37,40 @@ static void show_efi_loaded_images(struct pt_regs *regs)
        efi_print_image_infos((void *)regs->elr);
 }
 
+static void dump_far(unsigned long esr)
+{
+       unsigned long el, far;
+
+       switch ((esr >> 26) & 0b111111) {
+       case 0x20:
+       case 0x21:
+       case 0x24:
+       case 0x25:
+       case 0x22:
+       case 0x34:
+       case 0x35:
+               break;
+       default:
+               return;
+       }
+
+       asm("mrs        %0, CurrentEl": "=r" (el));
+
+       switch (el >> 2) {
+       case 1:
+               asm("mrs        %0, FAR_EL1": "=r" (far));
+               break;
+       case 2:
+               asm("mrs        %0, FAR_EL2": "=r" (far));
+               break;
+       default:
+               /* don't print anything to make output pretty */
+               return;
+       }
+
+       printf(", far 0x%lx", far);
+}
+
 static void dump_instr(struct pt_regs *regs)
 {
        u32 *addr = (u32 *)(regs->elr & ~3UL);
@@ -165,7 +199,9 @@ void do_sync(struct pt_regs *pt_regs)
            smh_emulate_trap(pt_regs))
                return;
        efi_restore_gd();
-       printf("\"Synchronous Abort\" handler, esr 0x%08lx\n", pt_regs->esr);
+       printf("\"Synchronous Abort\" handler, esr 0x%08lx", pt_regs->esr);
+       dump_far(pt_regs->esr);
+       printf("\n");
        show_regs(pt_regs);
        show_efi_loaded_images(pt_regs);
        panic("Resetting CPU ...\n");

diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
index de15d09..a1f44d9 100644 (file)
--- a/arch/arm/lib/lib1funcs.S
+++ b/arch/arm/lib/lib1funcs.S
@@ -419,4 +419,21 @@ ENTRY(__gnu_thumb1_case_uhi)
        ret     lr
 ENDPROC(__gnu_thumb1_case_uhi)
 .popsection
+
+/* Taken and adapted from: https://github.com/gcc-mirror/gcc/blob/4f181f9c7ee3efc509d185fdfda33be9018f1611/libgcc/config/arm/lib1funcs.S#L2156 */
+.pushsection .text.__gnu_thumb1_case_si, "ax"
+ENTRY(__gnu_thumb1_case_si)
+       push    {r0, r1}
+       mov     r1, lr
+       adds    r1, r1, #2      /* Align to word.  */
+       lsrs    r1, r1, #2
+       lsls    r0, r0, #2
+       lsls    r1, r1, #2
+       ldr     r0, [r1, r0]
+       adds    r0, r0, r1
+       mov     lr, r0
+       pop     {r0, r1}
+       mov     pc, lr          /* We know we were called from thumb code.  */
+ENDPROC(__gnu_thumb1_case_si)
+.popsection
 #endif

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 9bcb23c..906f538 100644 (file)
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -136,6 +136,12 @@ u-boot.imx: MKIMAGEOUTPUT = u-boot.imx.log
 u-boot.imx: u-boot.bin u-boot.cfgout $(PLUGIN).bin FORCE
        $(call if_changed,mkimage)
 
+quiet_cmd_u-boot-nand_imx = GEN     $@
+cmd_u-boot-nand_imx = (dd bs=1024 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@
+
+u-boot-nand.imx: u-boot.imx FORCE
+       $(call if_changed,u-boot-nand_imx)
+
 ifeq ($(CONFIG_MULTI_DTB_FIT),y)
 MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
        -T $(IMAGE_TYPE) -e $(CONFIG_TEXT_BASE)

diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 5e4836b..dc51f97 100644 (file)
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -170,6 +170,23 @@ config TARGET_IMX8MN_VENICE
        select GATEWORKS_SC
        select MISC
 
+config TARGET_IMX8MP_DATA_MODUL_EDM_SBC
+       bool "Data Modul eDM SBC i.MX8M Plus"
+       select BINMAN
+       select IMX8MP
+       select IMX8M_LPDDR4
+       select SUPPORT_SPL
+
+config TARGET_IMX8MP_BEACON
+       bool "imx8mm Beacon Embedded devkit"
+       select BINMAN
+       select IMX8MP
+       select SUPPORT_SPL
+       select IMX8M_LPDDR4
+       select FSL_CAAM
+       select ARCH_MISC_INIT
+       select SPL_CRYPTO if SPL
+
 config TARGET_IMX8MP_DH_DHCOM_PDK2
        bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus"
        select BINMAN
@@ -326,10 +343,12 @@ endchoice
 source "board/advantech/imx8mp_rsb3720a1/Kconfig"
 source "board/beacon/imx8mm/Kconfig"
 source "board/beacon/imx8mn/Kconfig"
+source "board/beacon/imx8mp/Kconfig"
 source "board/bsh/imx8mn_smm_s2/Kconfig"
 source "board/cloos/imx8mm_phg/Kconfig"
 source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
 source "board/data_modul/imx8mm_edm_sbc/Kconfig"
+source "board/data_modul/imx8mp_edm_sbc/Kconfig"
 source "board/dhelectronics/dh_imx8mp/Kconfig"
 source "board/engicam/imx8mm/Kconfig"
 source "board/engicam/imx8mp/Kconfig"

diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 7edbac2..a8c3a59 100644 (file)
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -187,11 +187,6 @@ config K3_X509_SWRV
        help
          SWRV for X509 certificate used for boot images
 
-config K3_BOARD_DETECT
-       bool "Support for Board detection"
-       help
-          Support for board detection.
-
 source "board/ti/am65x/Kconfig"
 source "board/ti/am64x/Kconfig"
 source "board/ti/am62x/Kconfig"

diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c
index a91c15c..026c4f9 100644 (file)
--- a/arch/arm/mach-k3/am625_init.c
+++ b/arch/arm/mach-k3/am625_init.c
@@ -9,7 +9,7 @@
 #include <spl.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/sysfw-loader.h>
+#include "sysfw-loader.h"
 #include "common.h"
 #include <dm.h>
 #include <dm/uclass-internal.h>

diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62a7_init.c
index 02da24a..a89a9b4 100644 (file)
--- a/arch/arm/mach-k3/am62a7_init.c
+++ b/arch/arm/mach-k3/am62a7_init.c
@@ -8,7 +8,7 @@
 #include <spl.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/sysfw-loader.h>
+#include "sysfw-loader.h"
 #include "common.h"
 #include <dm.h>
 #include <dm/uclass-internal.h>

diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index 1bf7e16..0c295e7 100644 (file)
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -12,10 +12,8 @@
 #include <spl.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/sysfw-loader.h>
-#include <asm/arch/sys_proto.h>
+#include "sysfw-loader.h"
 #include "common.h"
-#include <asm/arch/sys_proto.h>
 #include <linux/soc/ti/ti_sci_protocol.h>
 #include <dm.h>
 #include <dm/uclass-internal.h>
@@ -100,8 +98,8 @@ void do_dt_magic(void)
 {
        int ret, rescan;
 
-       if (IS_ENABLED(CONFIG_K3_BOARD_DETECT))
-               do_board_detect();
+       /* Perform board detection */
+       do_board_detect();
 
        /*
         * Board detection has been done.
@@ -185,8 +183,6 @@ void board_init_f(ulong dummy)
 
        preloader_console_init();
 
-       do_dt_magic();
-
 #if defined(CONFIG_K3_LOAD_SYSFW)
        /*
         * Process pinctrl for serial3 a.k.a. MAIN UART1 module and continue
@@ -213,6 +209,8 @@ void board_init_f(ulong dummy)
        /* Output System Firmware version info */
        k3_sysfw_print_ver();
 
+       do_dt_magic();
+
 #if defined(CONFIG_ESM_K3)
        /* Probe/configure ESM0 */
        ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev);
@@ -346,54 +344,3 @@ u32 spl_boot_device(void)
        else
                return __get_backup_bootmedia(devstat);
 }
-
-#if defined(CONFIG_SYS_K3_SPL_ATF)
-
-#define AM64X_DEV_RTI8                 127
-#define AM64X_DEV_RTI9                 128
-#define AM64X_DEV_R5FSS0_CORE0         121
-#define AM64X_DEV_R5FSS0_CORE1         122
-
-void release_resources_for_core_shutdown(void)
-{
-       struct ti_sci_handle *ti_sci = get_ti_sci_handle();
-       struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
-       struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
-       int ret;
-       u32 i;
-
-       const u32 put_device_ids[] = {
-               AM64X_DEV_RTI9,
-               AM64X_DEV_RTI8,
-       };
-
-       /* Iterate through list of devices to put (shutdown) */
-       for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
-               u32 id = put_device_ids[i];
-
-               ret = dev_ops->put_device(ti_sci, id);
-               if (ret)
-                       panic("Failed to put device %u (%d)\n", id, ret);
-       }
-
-       const u32 put_core_ids[] = {
-               AM64X_DEV_R5FSS0_CORE1,
-               AM64X_DEV_R5FSS0_CORE0, /* Handle CPU0 after CPU1 */
-       };
-
-       /* Iterate through list of cores to put (shutdown) */
-       for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
-               u32 id = put_core_ids[i];
-
-               /*
-                * Queue up the core shutdown request. Note that this call
-                * needs to be followed up by an actual invocation of an WFE
-                * or WFI CPU instruction.
-                */
-               ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
-               if (ret)
-                       panic("Failed sending core %u shutdown message (%d)\n",
-                             id, ret);
-       }
-}
-#endif

diff --git a/arch/arm/mach-k3/am654_init.c b/arch/arm/mach-k3/am654_init.c
index 70059ed..0d3889c 100644 (file)
--- a/arch/arm/mach-k3/am654_init.c
+++ b/arch/arm/mach-k3/am654_init.c
@@ -13,8 +13,7 @@
 #include <asm/io.h>
 #include <spl.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/sysfw-loader.h>
-#include <asm/arch/sys_proto.h>
+#include "sysfw-loader.h"
 #include "common.h"
 #include <dm.h>
 #include <dm/uclass-internal.h>
@@ -245,8 +244,8 @@ void board_init_f(ulong dummy)
        /* Output System Firmware version info */
        k3_sysfw_print_ver();
 
-       if (IS_ENABLED(CONFIG_K3_BOARD_DETECT))
-               do_board_detect();
+       /* Perform board detection */
+       do_board_detect();
 
 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
        ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
@@ -353,54 +352,3 @@ u32 spl_boot_device(void)
        else
                return __get_backup_bootmedia(devstat);
 }
-
-#ifdef CONFIG_SYS_K3_SPL_ATF
-
-#define AM6_DEV_MCU_RTI0                       134
-#define AM6_DEV_MCU_RTI1                       135
-#define AM6_DEV_MCU_ARMSS0_CPU0                        159
-#define AM6_DEV_MCU_ARMSS0_CPU1                        245
-
-void release_resources_for_core_shutdown(void)
-{
-       struct ti_sci_handle *ti_sci = get_ti_sci_handle();
-       struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
-       struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
-       int ret;
-       u32 i;
-
-       const u32 put_device_ids[] = {
-               AM6_DEV_MCU_RTI0,
-               AM6_DEV_MCU_RTI1,
-       };
-
-       /* Iterate through list of devices to put (shutdown) */
-       for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
-               u32 id = put_device_ids[i];
-
-               ret = dev_ops->put_device(ti_sci, id);
-               if (ret)
-                       panic("Failed to put device %u (%d)\n", id, ret);
-       }
-
-       const u32 put_core_ids[] = {
-               AM6_DEV_MCU_ARMSS0_CPU1,
-               AM6_DEV_MCU_ARMSS0_CPU0,        /* Handle CPU0 after CPU1 */
-       };
-
-       /* Iterate through list of cores to put (shutdown) */
-       for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
-               u32 id = put_core_ids[i];
-
-               /*
-                * Queue up the core shutdown request. Note that this call
-                * needs to be followed up by an actual invocation of an WFE
-                * or WFI CPU instruction.
-                */
-               ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
-               if (ret)
-                       panic("Failed sending core %u shutdown message (%d)\n",
-                             id, ret);
-       }
-}
-#endif

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index a2adb79..7baab7d 100644 (file)
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -19,7 +19,6 @@
 #include <asm/cache.h>
 #include <linux/soc/ti/ti_sci_protocol.h>
 #include <fdt_support.h>
-#include <asm/arch/sys_proto.h>
 #include <asm/hardware.h>
 #include <asm/io.h>
 #include <fs_loader.h>
@@ -189,9 +188,37 @@ int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
        return size;
 }
 
-__weak void release_resources_for_core_shutdown(void)
+void release_resources_for_core_shutdown(void)
 {
-       debug("%s not implemented...\n", __func__);
+       struct ti_sci_handle *ti_sci = get_ti_sci_handle();
+       struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
+       struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
+       int ret;
+       u32 i;
+
+       /* Iterate through list of devices to put (shutdown) */
+       for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
+               u32 id = put_device_ids[i];
+
+               ret = dev_ops->put_device(ti_sci, id);
+               if (ret)
+                       panic("Failed to put device %u (%d)\n", id, ret);
+       }
+
+       /* Iterate through list of cores to put (shutdown) */
+       for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
+               u32 id = put_core_ids[i];
+
+               /*
+                * Queue up the core shutdown request. Note that this call
+                * needs to be followed up by an actual invocation of an WFE
+                * or WFI CPU instruction.
+                */
+               ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
+               if (ret)
+                       panic("Failed sending core %u shutdown message (%d)\n",
+                             id, ret);
+       }
 }
 
 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
@@ -227,6 +254,31 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
        if (ret)
                panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
 
+#if (CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS) && IS_ENABLED(CONFIG_SYS_K3_SPL_ATF))
+       /* Authenticate ATF */
+       void *image_addr = (void *)fit_image_info[IMAGE_ID_ATF].image_start;
+
+       debug("%s: Authenticating image: addr=%lx, size=%ld, os=%s\n", __func__,
+             fit_image_info[IMAGE_ID_ATF].image_start,
+             fit_image_info[IMAGE_ID_ATF].image_len,
+             image_os_match[IMAGE_ID_ATF]);
+
+       ti_secure_image_post_process(&image_addr,
+                                    (size_t *)&fit_image_info[IMAGE_ID_ATF].image_len);
+
+       /* Authenticate OPTEE */
+       image_addr = (void *)fit_image_info[IMAGE_ID_OPTEE].image_start;
+
+       debug("%s: Authenticating image: addr=%lx, size=%ld, os=%s\n", __func__,
+             fit_image_info[IMAGE_ID_OPTEE].image_start,
+             fit_image_info[IMAGE_ID_OPTEE].image_len,
+             image_os_match[IMAGE_ID_OPTEE]);
+
+       ti_secure_image_post_process(&image_addr,
+                                    (size_t *)&fit_image_info[IMAGE_ID_OPTEE].image_len);
+
+#endif
+
        if (!fit_image_info[IMAGE_ID_DM_FW].image_len &&
            !(size > 0 && valid_elf_image(loadaddr))) {
                shut_cpu = 1;
@@ -288,9 +340,15 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image,
                        break;
                }
        }
+       /*
+        * Only DM and the DTBs are being authenticated here,
+        * rest will be authenticated when A72 cluster is up
+        */
+       if ((i != IMAGE_ID_ATF) && (i != IMAGE_ID_OPTEE))
 #endif
-
-       ti_secure_image_post_process(p_image, p_size);
+       {
+               ti_secure_image_post_process(p_image, p_size);
+       }
 }
 #endif
 
@@ -367,24 +425,21 @@ int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
        return 0;
 }
 
-int fdt_disable_node(void *blob, char *node_path)
+#if defined(CONFIG_OF_SYSTEM_SETUP)
+int ft_system_setup(void *blob, struct bd_info *bd)
 {
-       int offs;
        int ret;
 
-       offs = fdt_path_offset(blob, node_path);
-       if (offs < 0) {
-               printf("Node %s not found.\n", node_path);
-               return offs;
-       }
-       ret = fdt_setprop_string(blob, offs, "status", "disabled");
-       if (ret < 0) {
-               printf("Could not add status property to node %s: %s\n",
-                      node_path, fdt_strerror(ret));
-               return ret;
-       }
-       return 0;
+       ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
+       if (ret < 0)
+               ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
+                                        "sram@70000000");
+       if (ret)
+               printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
+
+       return ret;
 }
+#endif
 
 #endif
 
@@ -472,26 +527,6 @@ int print_cpuinfo(void)
 }
 #endif
 
-bool soc_is_j721e(void)
-{
-       u32 soc;
-
-       soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
-               JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
-
-       return soc == J721E;
-}
-
-bool soc_is_j7200(void)
-{
-       u32 soc;
-
-       soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
-               JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
-
-       return soc == J7200;
-}
-
 #ifdef CONFIG_ARM64
 void board_prep_linux(struct bootm_headers *images)
 {
@@ -612,3 +647,13 @@ int misc_init_r(void)
 
        return 0;
 }
+
+/**
+ * do_board_detect() - Detect board description
+ *
+ * Function to detect board description. This is expected to be
+ * overridden in the SoC family board file where desired.
+ */
+void __weak do_board_detect(void)
+{
+}

diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index 8f38fce..130f502 100644 (file)
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -9,9 +9,6 @@
 #include <asm/armv7_mpu.h>
 #include <asm/hardware.h>
 
-#define J721E  0xbb64
-#define J7200  0xbb6d
-
 struct fwl_data {
        const char *name;
        u16 fwl_id;
@@ -38,3 +35,5 @@ void mmr_unlock(phys_addr_t base, u32 partition);
 bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
 enum k3_device_type get_device_type(void);
 void ti_secure_image_post_process(void **p_image, size_t *p_size);
+struct ti_sci_handle *get_ti_sci_handle(void);
+void do_board_detect(void);

diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h
index db4a32c..88d5894 100644 (file)
--- a/arch/arm/mach-k3/include/mach/am62_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am62_hardware.h
@@ -57,4 +57,12 @@
 
 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START     0x43c30000
 
+#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
+
+static const u32 put_device_ids[] = {};
+
+static const u32 put_core_ids[] = {};
+
+#endif
+
 #endif /* __ASM_ARCH_AM62_HARDWARE_H */

diff --git a/arch/arm/mach-k3/include/mach/am62a_hardware.h b/arch/arm/mach-k3/include/mach/am62a_hardware.h
index 13bf50f..1108080 100644 (file)
--- a/arch/arm/mach-k3/include/mach/am62a_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am62a_hardware.h
@@ -86,4 +86,12 @@
 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START     0x70000001
 #endif /* CONFIG_CPU_V7R */
 
+#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
+
+static const u32 put_device_ids[] = {};
+
+static const u32 put_core_ids[] = {};
+
+#endif
+
 #endif /* __ASM_ARCH_AM62A_HARDWARE_H */

diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h
index 207ef95..44df887 100644 (file)
--- a/arch/arm/mach-k3/include/mach/am64_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am64_hardware.h
@@ -7,6 +7,11 @@
 #ifndef __ASM_ARCH_AM64_HARDWARE_H
 #define __ASM_ARCH_AM64_HARDWARE_H
 
+#include <config.h>
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
 #define PADCFG_MMR1_BASE                               0x000f0000
 #define MCU_PADCFG_MMR1_BASE                           0x04080000
 #define WKUP_CTRL_MMR0_BASE                            0x43000000
@@ -41,4 +46,23 @@
 /* Use Last 2K as Scratch pad */
 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START             0x7019f800
 
+#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
+
+#define AM64X_DEV_RTI8                 127
+#define AM64X_DEV_RTI9                 128
+#define AM64X_DEV_R5FSS0_CORE0         121
+#define AM64X_DEV_R5FSS0_CORE1         122
+
+static const u32 put_device_ids[] = {
+       AM64X_DEV_RTI9,
+       AM64X_DEV_RTI8,
+};
+
+static const u32 put_core_ids[] = {
+       AM64X_DEV_R5FSS0_CORE1,
+       AM64X_DEV_R5FSS0_CORE0, /* Handle CPU0 after CPU1 */
+};
+
+#endif
+
 #endif /* __ASM_ARCH_DRA8_HARDWARE_H */

diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h
index f9f3291..029041f 100644 (file)
--- a/arch/arm/mach-k3/include/mach/am6_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am6_hardware.h
@@ -39,4 +39,23 @@
 
 #define        NAVSS_NBSS_THREADMAP                            0x10
 
+#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
+
+#define AM6_DEV_MCU_RTI0                       134
+#define AM6_DEV_MCU_RTI1                       135
+#define AM6_DEV_MCU_ARMSS0_CPU0                        159
+#define AM6_DEV_MCU_ARMSS0_CPU1                        245
+
+static const u32 put_device_ids[] = {
+       AM6_DEV_MCU_RTI0,
+       AM6_DEV_MCU_RTI1,
+};
+
+static const u32 put_core_ids[] = {
+       AM6_DEV_MCU_ARMSS0_CPU1,
+       AM6_DEV_MCU_ARMSS0_CPU0,        /* Handle CPU0 after CPU1 */
+};
+
+#endif
+
 #endif /* __ASM_ARCH_AM6_HARDWARE_H */

diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index 2c60ef8..9faf1d6 100644 (file)
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -6,6 +6,8 @@
 #ifndef _ASM_ARCH_HARDWARE_H_
 #define _ASM_ARCH_HARDWARE_H_
 
+#include <asm/io.h>
+
 #ifdef CONFIG_SOC_K3_AM654
 #include "am6_hardware.h"
 #endif
@@ -36,6 +38,29 @@
 #define JTAG_ID_VARIANT_MASK   (0xf << 28)
 #define JTAG_ID_PARTNO_SHIFT   12
 #define JTAG_ID_PARTNO_MASK    (0xffff << 12)
+#define JTAG_ID_PARTNO_AM65X   0xbb5a
+#define JTAG_ID_PARTNO_J721E   0xbb64
+#define JTAG_ID_PARTNO_J7200   0xbb6d
+#define JTAG_ID_PARTNO_AM64X   0xbb38
+#define JTAG_ID_PARTNO_J721S2  0xbb75
+#define JTAG_ID_PARTNO_AM62X   0xbb7e
+#define JTAG_ID_PARTNO_AM62AX   0xbb8d
+
+#define K3_SOC_ID(id, ID) \
+static inline bool soc_is_##id(void) \
+{ \
+       u32 soc = (readl(CTRLMMR_WKUP_JTAG_ID) & \
+               JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT; \
+       return soc == JTAG_ID_PARTNO_##ID; \
+}
+K3_SOC_ID(am65x, AM65X)
+K3_SOC_ID(j721e, J721E)
+K3_SOC_ID(j7200, J7200)
+K3_SOC_ID(am64x, AM64X)
+K3_SOC_ID(j721s2, J721S2)
+K3_SOC_ID(am62x, AM62X)
+K3_SOC_ID(am62ax, AM62AX)
+
 #define K3_SEC_MGR_SYS_STATUS          0x44234100
 #define SYS_STATUS_DEV_TYPE_SHIFT      0
 #define SYS_STATUS_DEV_TYPE_MASK       (0xf)

diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h
index 247dee9..376db38 100644 (file)
--- a/arch/arm/mach-k3/include/mach/j721e_hardware.h
+++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h
@@ -38,4 +38,23 @@
 /* MCU SCRATCHPAD usage */
 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START     CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
 
+#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
+
+#define J721E_DEV_MCU_RTI0                     262
+#define J721E_DEV_MCU_RTI1                     263
+#define J721E_DEV_MCU_ARMSS0_CPU0              250
+#define J721E_DEV_MCU_ARMSS0_CPU1              251
+
+static const u32 put_device_ids[] = {
+       J721E_DEV_MCU_RTI0,
+       J721E_DEV_MCU_RTI1,
+};
+
+static const u32 put_core_ids[] = {
+       J721E_DEV_MCU_ARMSS0_CPU1,
+       J721E_DEV_MCU_ARMSS0_CPU0,      /* Handle CPU0 after CPU1 */
+};
+
+#endif
+
 #endif /* __ASM_ARCH_J721E_HARDWARE_H */

diff --git a/arch/arm/mach-k3/include/mach/j721s2_hardware.h b/arch/arm/mach-k3/include/mach/j721s2_hardware.h
index 2e155ed..7948bcf 100644 (file)
--- a/arch/arm/mach-k3/include/mach/j721s2_hardware.h
+++ b/arch/arm/mach-k3/include/mach/j721s2_hardware.h
@@ -38,4 +38,23 @@
 /* MCU SCRATCHPAD usage */
 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START     CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
 
+#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
+
+#define J721S2_DEV_MCU_RTI0                    295
+#define J721S2_DEV_MCU_RTI1                    296
+#define J721S2_DEV_MCU_ARMSS0_CPU0             284
+#define J721S2_DEV_MCU_ARMSS0_CPU1             285
+
+static const u32 put_device_ids[] = {
+       J721S2_DEV_MCU_RTI0,
+       J721S2_DEV_MCU_RTI1,
+};
+
+static const u32 put_core_ids[] = {
+       J721S2_DEV_MCU_ARMSS0_CPU1,
+       J721S2_DEV_MCU_ARMSS0_CPU0,     /* Handle CPU0 after CPU1 */
+};
+
+#endif
+
 #endif /* __ASM_ARCH_J721S2_HARDWARE_H */

diff --git a/arch/arm/mach-k3/include/mach/sys_proto.h b/arch/arm/mach-k3/include/mach/sys_proto.h
deleted file mode 100644 (file)
index 3d3d90d..0000000
--- a/arch/arm/mach-k3/include/mach/sys_proto.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
- *     Andreas Dannenberg <dannenberg@ti.com>
- */
-
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-void sdelay(unsigned long loops);
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
-                 u32 bound);
-struct ti_sci_handle *get_ti_sci_handle(void);
-int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name);
-int do_board_detect(void);
-void release_resources_for_core_shutdown(void);
-int fdt_disable_node(void *blob, char *node_path);
-
-bool soc_is_j721e(void);
-bool soc_is_j7200(void);
-
-void k3_spl_init(void);
-void k3_mem_init(void);
-bool check_rom_loaded_sysfw(void);
-#endif

diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 9cae3ac..9bba5f7 100644 (file)
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -12,9 +12,8 @@
 #include <asm/io.h>
 #include <asm/armv7_mpu.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/sysfw-loader.h>
+#include "sysfw-loader.h"
 #include "common.h"
-#include <asm/arch/sys_proto.h>
 #include <linux/soc/ti/ti_sci_protocol.h>
 #include <dm.h>
 #include <dm/uclass-internal.h>
@@ -140,8 +139,8 @@ void do_dt_magic(void)
        int ret, rescan, mmc_dev = -1;
        static struct mmc *mmc;
 
-       if (IS_ENABLED(CONFIG_K3_BOARD_DETECT))
-               do_board_detect();
+       /* Perform board detection */
+       do_board_detect();
 
        /*
         * Board detection has been done.
@@ -267,8 +266,8 @@ void board_init_f(ulong dummy)
        /* Output System Firmware version info */
        k3_sysfw_print_ver();
 
-       if (IS_ENABLED(CONFIG_K3_BOARD_DETECT))
-               do_board_detect();
+       /* Perform board detection */
+       do_board_detect();
 
 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
        ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
@@ -378,58 +377,3 @@ u32 spl_boot_device(void)
        else
                return __get_backup_bootmedia(main_devstat);
 }
-
-#ifdef CONFIG_SYS_K3_SPL_ATF
-
-#define J721E_DEV_MCU_RTI0                     262
-#define J721E_DEV_MCU_RTI1                     263
-#define J721E_DEV_MCU_ARMSS0_CPU0              250
-#define J721E_DEV_MCU_ARMSS0_CPU1              251
-
-void release_resources_for_core_shutdown(void)
-{
-       struct ti_sci_handle *ti_sci;
-       struct ti_sci_dev_ops *dev_ops;
-       struct ti_sci_proc_ops *proc_ops;
-       int ret;
-       u32 i;
-
-       const u32 put_device_ids[] = {
-               J721E_DEV_MCU_RTI0,
-               J721E_DEV_MCU_RTI1,
-       };
-
-       ti_sci = get_ti_sci_handle();
-       dev_ops = &ti_sci->ops.dev_ops;
-       proc_ops = &ti_sci->ops.proc_ops;
-
-       /* Iterate through list of devices to put (shutdown) */
-       for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
-               u32 id = put_device_ids[i];
-
-               ret = dev_ops->put_device(ti_sci, id);
-               if (ret)
-                       panic("Failed to put device %u (%d)\n", id, ret);
-       }
-
-       const u32 put_core_ids[] = {
-               J721E_DEV_MCU_ARMSS0_CPU1,
-               J721E_DEV_MCU_ARMSS0_CPU0,      /* Handle CPU0 after CPU1 */
-       };
-
-       /* Iterate through list of cores to put (shutdown) */
-       for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
-               u32 id = put_core_ids[i];
-
-               /*
-                * Queue up the core shutdown request. Note that this call
-                * needs to be followed up by an actual invocation of an WFE
-                * or WFI CPU instruction.
-                */
-               ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
-               if (ret)
-                       panic("Failed sending core %u shutdown message (%d)\n",
-                             id, ret);
-       }
-}
-#endif

diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c
index 09e55ed..712a7e2 100644 (file)
--- a/arch/arm/mach-k3/j721s2_init.c
+++ b/arch/arm/mach-k3/j721s2_init.c
@@ -12,16 +12,61 @@
 #include <asm/io.h>
 #include <asm/armv7_mpu.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/sysfw-loader.h>
+#include "sysfw-loader.h"
 #include "common.h"
-#include <asm/arch/sys_proto.h>
 #include <linux/soc/ti/ti_sci_protocol.h>
 #include <dm.h>
 #include <dm/uclass-internal.h>
 #include <dm/pinctrl.h>
+#include <dm/root.h>
 #include <mmc.h>
 #include <remoteproc.h>
 
+struct fwl_data cbass_hc_cfg0_fwls[] = {
+       { "PCIE0_CFG", 2577, 7 },
+       { "EMMC8SS0_CFG", 2579, 4 },
+       { "USB3SS0_CORE", 2580, 4 },
+       { "USB3SS1_CORE", 2581, 1 },
+}, cbass_hc2_fwls[] = {
+       { "PCIE0", 2547, 24 },
+       { "HC2_WIZ16B8M4CT2", 2552, 1 },
+}, cbass_rc_cfg0_fwls[] = {
+       { "EMMCSD4SS0_CFG", 2400, 4 },
+}, infra_cbass0_fwls[] = {
+       { "PSC0", 5, 1 },
+       { "PLL_CTRL0", 6, 1 },
+       { "PLL_MMR0", 8, 26 },
+       { "CTRL_MMR0", 9, 16 },
+       { "GPIO0", 16, 1 },
+}, mcu_cbass0_fwls[] = {
+       { "MCU_R5FSS0_CORE0", 1024, 4 },
+       { "MCU_R5FSS0_CORE0_CFG", 1025, 3 },
+       { "MCU_R5FSS0_CORE1", 1028, 4 },
+       { "MCU_R5FSS0_CORE1_CFG", 1029, 1 },
+       { "MCU_FSS0_CFG", 1032, 12 },
+       { "MCU_FSS0_S1", 1033, 8 },
+       { "MCU_FSS0_S0", 1036, 8 },
+       { "MCU_PSROM49152X32", 1048, 1 },
+       { "MCU_MSRAM128KX64", 1050, 8 },
+       { "MCU_MSRAM128KX64_CFG", 1051, 1 },
+       { "MCU_TIMER0", 1056, 1 },
+       { "MCU_TIMER9", 1065, 1 },
+       { "MCU_USART0", 1120, 1 },
+       { "MCU_I2C0", 1152, 1 },
+       { "MCU_CTRL_MMR0", 1200, 8 },
+       { "MCU_PLL_MMR0", 1201, 3 },
+       { "MCU_CPSW0", 1220, 2 },
+}, wkup_cbass0_fwls[] = {
+       { "WKUP_PSC0", 129, 1 },
+       { "WKUP_PLL_CTRL0", 130, 1 },
+       { "WKUP_CTRL_MMR0", 131, 16 },
+       { "WKUP_GPIO0", 132, 1 },
+       { "WKUP_I2C0", 144, 1 },
+       { "WKUP_USART0", 160, 1 },
+}, navss_cbass0_fwls[] = {
+       { "NACSS_VIRT0", 6253, 1 },
+};
+
 static void ctrl_mmr_unlock(void)
 {
        /* Unlock all WKUP_CTRL_MMR0 module registers */
@@ -150,6 +195,14 @@ void k3_spl_init(void)
                        if (ret)
                                panic("Failed to initialize clk-k3!\n");
                }
+
+               remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
+               remove_fwl_configs(cbass_hc2_fwls, ARRAY_SIZE(cbass_hc2_fwls));
+               remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
+               remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
+               remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
+               remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
+               remove_fwl_configs(navss_cbass0_fwls, ARRAY_SIZE(navss_cbass0_fwls));
        }
 
        /* Output System Firmware version info */
@@ -182,6 +235,69 @@ void k3_mem_init(void)
        spl_enable_dcache();
 }
 
+/* Support for the various EVM / SK families */
+#if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT)
+void do_dt_magic(void)
+{
+       int ret, rescan, mmc_dev = -1;
+       static struct mmc *mmc;
+
+       do_board_detect();
+
+       /*
+        * Board detection has been done.
+        * Let us see if another dtb wouldn't be a better match
+        * for our board
+        */
+       if (IS_ENABLED(CONFIG_CPU_V7R)) {
+               ret = fdtdec_resetup(&rescan);
+               if (!ret && rescan) {
+                       dm_uninit();
+                       dm_init_and_scan(true);
+               }
+       }
+
+       /*
+        * Because of multi DTB configuration, the MMC device has
+        * to be re-initialized after reconfiguring FDT inorder to
+        * boot from MMC. Do this when boot mode is MMC and ROM has
+        * not loaded SYSFW.
+        */
+       switch (spl_boot_device()) {
+       case BOOT_DEVICE_MMC1:
+               mmc_dev = 0;
+               break;
+       case BOOT_DEVICE_MMC2:
+       case BOOT_DEVICE_MMC2_2:
+               mmc_dev = 1;
+               break;
+       }
+
+       if (mmc_dev > 0 && !check_rom_loaded_sysfw()) {
+               ret = mmc_init_device(mmc_dev);
+               if (!ret) {
+                       mmc = find_mmc_device(mmc_dev);
+                       if (mmc) {
+                               ret = mmc_init(mmc);
+                               if (ret)
+                                       printf("mmc init failed with error: %d\n", ret);
+                       }
+               }
+       }
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+       k3_spl_init();
+#if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT)
+       do_dt_magic();
+#endif
+       k3_mem_init();
+}
+#endif
+
 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
 {
        switch (boot_device) {
@@ -264,57 +380,3 @@ u32 spl_boot_device(void)
        else
                return __get_backup_bootmedia(main_devstat);
 }
-
-#define J721S2_DEV_MCU_RTI0                    295
-#define J721S2_DEV_MCU_RTI1                    296
-#define J721S2_DEV_MCU_ARMSS0_CPU0             284
-#define J721S2_DEV_MCU_ARMSS0_CPU1             285
-
-void release_resources_for_core_shutdown(void)
-{
-       if (IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)) {
-               struct ti_sci_handle *ti_sci;
-               struct ti_sci_dev_ops *dev_ops;
-               struct ti_sci_proc_ops *proc_ops;
-               int ret;
-               u32 i;
-
-               const u32 put_device_ids[] = {
-                       J721S2_DEV_MCU_RTI0,
-                       J721S2_DEV_MCU_RTI1,
-               };
-
-               ti_sci = get_ti_sci_handle();
-               dev_ops = &ti_sci->ops.dev_ops;
-               proc_ops = &ti_sci->ops.proc_ops;
-
-               /* Iterate through list of devices to put (shutdown) */
-               for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
-                       u32 id = put_device_ids[i];
-
-                       ret = dev_ops->put_device(ti_sci, id);
-                       if (ret)
-                               panic("Failed to put device %u (%d)\n", id, ret);
-               }
-
-               const u32 put_core_ids[] = {
-                       J721S2_DEV_MCU_ARMSS0_CPU1,
-                       J721S2_DEV_MCU_ARMSS0_CPU0,     /* Handle CPU0 after CPU1 */
-               };
-
-               /* Iterate through list of cores to put (shutdown) */
-               for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
-                       u32 id = put_core_ids[i];
-
-                       /*
-                        * Queue up the core shutdown request. Note that this call
-                        * needs to be followed up by an actual invocation of an WFE
-                        * or WFI CPU instruction.
-                        */
-                       ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
-                       if (ret)
-                               panic("Failed sending core %u shutdown message (%d)\n",
-                                     id, ret);
-               }
-       }
-}

diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c
index 092588f..6179f73 100644 (file)
--- a/arch/arm/mach-k3/security.c
+++ b/arch/arm/mach-k3/security.c
@@ -17,7 +17,6 @@
 #include <linux/soc/ti/ti_sci_protocol.h>
 #include <mach/spl.h>
 #include <spl.h>
-#include <asm/arch/sys_proto.h>
 #include <linux/dma-mapping.h>
 
 #include "common.h"

diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index c4c5c37..9be2d9e 100644 (file)
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -23,7 +23,6 @@
 #include <spi_flash.h>
 
 #include <asm/io.h>
-#include <asm/arch/sys_proto.h>
 #include "common.h"
 
 DECLARE_GLOBAL_DATA_PTR;

diff --git a/arch/arm/mach-k3/include/mach/sysfw-loader.h b/arch/arm/mach-k3/sysfw-loader.h
similarity index 100%
rename from arch/arm/mach-k3/include/mach/sysfw-loader.h
rename to arch/arm/mach-k3/sysfw-loader.h

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index b1f2e97..ac484c7 100644 (file)
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -381,6 +381,16 @@ config MVEBU_SPL_NAND_BADBLK_LOCATION
          Value 0x0 = SLC flash = BBI at page 0 or page 1
          Value 0x1 = MLC flash = BBI at last page in the block
 
+config MVEBU_SPL_SATA_BLKSZ
+       int "SATA block size"
+       depends on MVEBU_SPL_BOOT_DEVICE_SATA
+       range 512 32768
+       default 512
+       help
+         Block size of the SATA disk in bytes.
+         Typically 512 bytes for majority of disks
+         and 4096 bytes for 4K Native disks.
+
 config MVEBU_EFUSE
        bool "Enable eFuse support"
        depends on HAVE_MVEBU_EFUSE

diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 90f8833..0584ed2 100644 (file)
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -73,6 +73,11 @@ KWB_CFG_NAND_BLKSZ = $(CONFIG_SYS_NAND_BLOCK_SIZE)
 KWB_CFG_NAND_BADBLK_LOCATION = $(CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION)
 endif
 
+ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA),)
+KWB_REPLACE += SATA_BLKSZ
+KWB_CFG_SATA_BLKSZ = $(CONFIG_MVEBU_SPL_SATA_BLKSZ)
+endif
+
 ifneq ($(CONFIG_SECURED_MODE_IMAGE),)
 KWB_REPLACE += CSK_INDEX
 KWB_CFG_CSK_INDEX = $(CONFIG_SECURED_MODE_CSK_INDEX)

diff --git a/arch/arm/mach-mvebu/kwbimage.cfg.in b/arch/arm/mach-mvebu/kwbimage.cfg.in
index 90cf00c..588c259 100644 (file)
--- a/arch/arm/mach-mvebu/kwbimage.cfg.in
+++ b/arch/arm/mach-mvebu/kwbimage.cfg.in
@@ -16,6 +16,9 @@ VERSION               1
 #@NAND_BLKSZ
 #@NAND_BADBLK_LOCATION
 
+# SATA configuration
+#@SATA_BLKSZ
+
 # Enable BootROM output via DEBUG flag on SoCs which require it
 #@DEBUG
 

diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
index 6b8c72a..379daa8 100644 (file)
--- a/arch/arm/mach-mvebu/spl.c
+++ b/arch/arm/mach-mvebu/spl.c
@@ -208,10 +208,15 @@ int spl_parse_board_header(struct spl_image_info *spl_image,
 
        /*
         * For SATA srcaddr is specified in number of sectors.
-        * This expects that sector size is 512 bytes.
+        * Retrieve block size of the first SCSI device (same
+        * code used by the spl_sata_load_image_raw() function)
+        * or fallback to default sector size of 512 bytes.
         */
-       if (IS_ENABLED(CONFIG_SPL_SATA) && mhdr->blockid == IBR_HDR_SATA_ID)
-               spl_image->offset *= 512;
+       if (IS_ENABLED(CONFIG_SPL_SATA) && mhdr->blockid == IBR_HDR_SATA_ID) {
+               struct blk_desc *blk_dev = blk_get_devnum_by_uclass_id(UCLASS_SCSI, 0);
+               unsigned long blksz = blk_dev ? blk_dev->blksz : 512;
+               spl_image->offset *= blksz;
+       }
 
        if (spl_image->offset % 4 != 0) {
                printf("ERROR: Wrong srcaddr (0x%08x) in kwbimage\n",

diff --git a/arch/arm/mach-omap2/omap3/lowlevel_init.S b/arch/arm/mach-omap2/omap3/lowlevel_init.S
index ab7cdcf..1ab9472 100644 (file)
--- a/arch/arm/mach-omap2/omap3/lowlevel_init.S
+++ b/arch/arm/mach-omap2/omap3/lowlevel_init.S
@@ -15,13 +15,14 @@
 #include <asm/arch/clocks_omap3.h>
 #include <linux/linkage.h>
 
+.arch_extension sec
+
 /*
  * Funtion for making PPA HAL API calls in secure devices
  * Input:
  *     R0 - Service ID
  *     R1 - paramer list
  */
-/* TODO: Re-evaluate the comment at the end regarding armv5 vs armv7 */
 ENTRY(do_omap3_emu_romcode_call)
        PUSH {r4-r12, lr} @ Save all registers from ROM code!
        MOV r12, r0     @ Copy the Secure Service ID in R12
@@ -32,8 +33,7 @@ ENTRY(do_omap3_emu_romcode_call)
        MOV r6, #0xFF   @ Indicate new Task call
        mcr     p15, 0, r0, c7, c10, 4  @ DSB
        mcr     p15, 0, r0, c7, c10, 5  @ DMB
-       .word   0xe1600071      @ SMC #1 to call PPA service - hand assembled
-                               @ because we use -march=armv5
+       SMC     #1      @ Call PPA service
        POP {r4-r12, pc}
 ENDPROC(do_omap3_emu_romcode_call)
 

diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 921153a..1ef7d68 100644 (file)
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -40,6 +40,10 @@ config RCAR_GEN3
        imply SPL_USE_TINY_PRINTF
        imply SPL_YMODEM_SUPPORT
 
+config RCAR_GEN4
+       bool "Renesas ARM SoCs R-Car Gen4 (64bit)"
+       select RCAR_64
+
 config RZA1
        prompt "Renesas ARM SoCs RZ/A1 (32bit)"
        select CPU_V7A

diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 3b14721..57ed1d6 100644 (file)
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -7,5 +7,6 @@ config OF_LIBFDT_OVERLAY
        default y if RCAR_64
 
 source "arch/arm/mach-rmobile/Kconfig.rcar3"
+source "arch/arm/mach-rmobile/Kconfig.rcar4"
 
 endif

diff --git a/arch/arm/mach-rmobile/Kconfig.rcar3 b/arch/arm/mach-rmobile/Kconfig.rcar3
index 680aa45..5f33821 100644 (file)
--- a/arch/arm/mach-rmobile/Kconfig.rcar3
+++ b/arch/arm/mach-rmobile/Kconfig.rcar3
@@ -70,12 +70,6 @@ config R8A77995
        imply CLK_R8A77995
        imply PINCTRL_PFC_R8A77995
 
-config R8A779A0
-       bool "Renesas SoC R8A779A0"
-       select GICV3
-       imply CLK_R8A779A0
-       imply PINCTRL_PFC_R8A779A0
-
 config RZ_G2
        bool "Renesas ARM SoCs RZ/G2 (64bit)"
 
@@ -123,12 +117,6 @@ config TARGET_EBISU
        help
           Support for Renesas R-Car Gen3 Ebisu platform
 
-config TARGET_FALCON
-       bool "Falcon board"
-       imply R8A779A0
-       help
-          Support for Renesas R-Car Gen3 Falcon platform
-
 config TARGET_HIHOPE_RZG2
        bool "HiHope RZ/G2 board"
        imply MULTI_DTB_FIT
@@ -176,7 +164,6 @@ source "board/renesas/condor/Kconfig"
 source "board/renesas/draak/Kconfig"
 source "board/renesas/eagle/Kconfig"
 source "board/renesas/ebisu/Kconfig"
-source "board/renesas/falcon/Kconfig"
 source "board/renesas/salvator-x/Kconfig"
 source "board/renesas/ulcb/Kconfig"
 source "board/beacon/beacon-rzg2m/Kconfig"

diff --git a/arch/arm/mach-rmobile/Kconfig.rcar4 b/arch/arm/mach-rmobile/Kconfig.rcar4
new file mode 100644 (file)
index 0000000..d4f93c8
--- /dev/null
+++ b/arch/arm/mach-rmobile/Kconfig.rcar4
@@ -0,0 +1,53 @@
+if RCAR_GEN4
+
+menu "Select Target SoC"
+
+config R8A779A0
+       bool "Renesas SoC R8A779A0"
+       select GICV3
+       imply CLK_R8A779A0
+       imply PINCTRL_PFC_R8A779A0
+
+config R8A779F0
+       bool "Renesas SoC R8A779F0"
+       select GICV3
+       imply CLK_R8A779F0
+       imply PINCTRL_PFC_R8A779F0
+
+config R8A779G0
+       bool "Renesas SoC R8A779G0"
+       select GICV3
+       imply CLK_R8A779G0
+       imply PINCTRL_PFC_R8A779G0
+
+endmenu
+
+choice
+       prompt "Renesas ARM64 SoCs board select"
+       optional
+
+config TARGET_FALCON
+       bool "Falcon board"
+       imply R8A779A0
+       help
+          Support for Renesas R-Car Gen3 Falcon platform
+
+config TARGET_SPIDER
+       bool "Spider board"
+       imply R8A779F0
+       help
+         Support for Renesas R-Car Gen4 Spider platform
+
+config TARGET_WHITEHAWK
+       bool "White Hawk board"
+       imply R8A779G0
+       help
+         Support for Renesas R-Car Gen4 White Hawk platform
+
+endchoice
+
+source "board/renesas/falcon/Kconfig"
+source "board/renesas/spider/Kconfig"
+source "board/renesas/whitehawk/Kconfig"
+
+endif

diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 5b86221..fadb6eb 100644 (file)
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -10,7 +10,7 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
 obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
 obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
 obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
-obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
+obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
 obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o
 
 ifneq ($(CONFIG_R8A779A0),)

diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-rmobile/cpu_info-rcar.c
index ac9c623..62017f5 100644 (file)
--- a/arch/arm/mach-rmobile/cpu_info-rcar.c
+++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
@@ -14,7 +14,7 @@
 
 static u32 rmobile_get_prr(void)
 {
-       if (IS_ENABLED(CONFIG_RCAR_GEN3))
+       if (IS_ENABLED(CONFIG_RCAR_64))
                return readl(0xFFF00044);
 
        return readl(0xFF000044);

diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index 246029a..7e7465a 100644 (file)
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -19,8 +19,8 @@ int arch_cpu_init(void)
 }
 #endif
 
-/* R-Car Gen3 D-cache is enabled in memmap-gen3.c */
-#ifndef CONFIG_RCAR_GEN3
+/* R-Car Gen3 and Gen4 D-cache is enabled in memmap-gen3.c */
+#ifndef CONFIG_RCAR_64
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
@@ -76,6 +76,8 @@ static const struct {
        { RMOBILE_CPU_TYPE_R8A77990, "R8A77990" },
        { RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
        { RMOBILE_CPU_TYPE_R8A779A0, "R8A779A0" },
+       { RMOBILE_CPU_TYPE_R8A779F0, "R8A779F0" },
+       { RMOBILE_CPU_TYPE_R8A779G0, "R8A779G0" },
        { 0x0, "CPU" },
 };
 

diff --git a/arch/arm/mach-rmobile/include/mach/rcar-gen4-base.h b/arch/arm/mach-rmobile/include/mach/rcar-gen4-base.h
new file mode 100644 (file)
index 0000000..ac57698
--- /dev/null
+++ b/arch/arm/mach-rmobile/include/mach/rcar-gen4-base.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * ./arch/arm/mach-rmobile/include/mach/rcar-gen4-base.h
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#ifndef __ASM_ARCH_RCAR_GEN4_BASE_H
+#define __ASM_ARCH_RCAR_GEN4_BASE_H
+
+/*
+ * R-Car (R8A779F0) I/O Addresses
+ */
+#define RWDT_BASE              0xE6020000
+#define SWDT_BASE              0xE6030000
+#define TMU_BASE               0xE61E0000
+
+/* SCIF */
+#define SCIF0_BASE             0xE6E60000
+#define SCIF1_BASE             0xE6E68000
+#define SCIF2_BASE             0xE6E88000
+#define SCIF3_BASE             0xE6C50000
+#define SCIF4_BASE             0xE6C40000
+#define SCIF5_BASE             0xE6F30000
+
+/* CPG */
+#define CPGWPR                 0xE6150000
+#define CPGWPCR                        0xE6150004
+
+/* Reset */
+#define RST_BASE               0xE6160000 /* Domain0 */
+#define RST_SRESCR0            (RST_BASE + 0x18)
+#define RST_SPRES              0x5AA58000
+
+/* Arm Generic Timer */
+#define CNTCR_BASE             0xE6080000
+#define CNTFID0                        (CNTCR_BASE + 0x020)
+#define CNTCR_EN               BIT(0)
+
+/* GICv3 */
+/* Distributor Registers */
+#define GICD_BASE              0xF1000000
+#define GICR_BASE              (GICR_LPI_BASE)
+
+/* ReDistributor Registers for Control and Physical LPIs */
+#define GICR_LPI_BASE          0xF1060000
+#define GICR_WAKER             0x0014
+#define GICR_PWRR              0x0024
+#define GICR_LPI_WAKER         (GICR_LPI_BASE + GICR_WAKER)
+#define GICR_LPI_PWRR          (GICR_LPI_BASE + GICR_PWRR)
+
+/* ReDistributor Registers for SGIs and PPIs */
+#define GICR_SGI_BASE          0xF1070000
+#define GICR_IGROUPR0          0x0080
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <linux/bitops.h>
+
+/* RWDT */
+struct rcar_rwdt {
+       u32 rwtcnt;
+       u32 rwtcsra;
+       u32 rwtcsrb;
+};
+
+/* SWDT */
+struct rcar_swdt {
+       u32 swtcnt;
+       u32 swtcsra;
+       u32 swtcsrb;
+};
+#endif
+
+#endif /* __ASM_ARCH_RCAR_GEN4_BASE_H */

diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h
index 53f9a80..a14c2aa 100644 (file)
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -16,6 +16,8 @@
 #include <asm/arch/r8a7794.h>
 #elif defined(CONFIG_RCAR_GEN3)
 #include <asm/arch/rcar-gen3-base.h>
+#elif defined(CONFIG_RCAR_GEN4)
+#include <asm/arch/rcar-gen4-base.h>
 #elif defined(CONFIG_R7S72100)
 #else
 #error "SOC Name not defined"
@@ -37,6 +39,8 @@
 #define RMOBILE_CPU_TYPE_R8A77990      0x57
 #define RMOBILE_CPU_TYPE_R8A77995      0x58
 #define RMOBILE_CPU_TYPE_R8A779A0      0x59
+#define RMOBILE_CPU_TYPE_R8A779F0      0x5A
+#define RMOBILE_CPU_TYPE_R8A779G0      0x5C
 
 #ifndef __ASSEMBLY__
 const u8 *rzg_get_cpu_name(void);

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 0390431..327779a 100644 (file)
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -119,7 +119,7 @@ config ROCKCHIP_RK322X
 config ROCKCHIP_RK3288
        bool "Support Rockchip RK3288"
        select CPU_V7A
-       select OF_BOARD_SETUP
+       select OF_SYSTEM_SETUP
        select SKIP_LOWLEVEL_INIT_ONLY
        select SUPPORT_SPL
        select SPL
@@ -288,7 +288,9 @@ config ROCKCHIP_RK3568
        select BOARD_LATE_INIT
        select DM_REGULATOR_FIXED
        select DM_RESET
+       imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
        imply ROCKCHIP_COMMON_BOARD
+       imply OF_LIBFDT_OVERLAY
        imply ROCKCHIP_OTP
        imply MISC_INIT_R
        help
@@ -309,9 +311,13 @@ config ROCKCHIP_RK3588
        select REGMAP
        select SYSCON
        select BOARD_LATE_INIT
+       imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
        imply ROCKCHIP_COMMON_BOARD
+       imply OF_LIBFDT_OVERLAY
        imply ROCKCHIP_OTP
        imply MISC_INIT_R
+       imply CLK_SCMI
+       imply SCMI_FIRMWARE
        help
          The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and
          quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4,
@@ -428,7 +434,7 @@ config TPL_ROCKCHIP_COMMON_BOARD
 
 config ROCKCHIP_EXTERNAL_TPL
        bool "Use external TPL binary"
-       default y if ROCKCHIP_RK3568
+       default y if ROCKCHIP_RK3568 || ROCKCHIP_RK3588
        help
          Some Rockchip SoCs require an external TPL to initialize DRAM.
          Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to

diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c
index 849014d..7d03f0c 100644 (file)
--- a/arch/arm/mach-rockchip/misc.c
+++ b/arch/arm/mach-rockchip/misc.c
@@ -83,7 +83,7 @@ int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
 
        /* read the cpu_id range from the efuses */
        ret = misc_read(dev, cpuid_offset, cpuid, cpuid_length);
-       if (ret) {
+       if (ret < 0) {
                debug("%s: reading cpuid from the efuses failed\n",
                      __func__);
                return -1;

diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
index 3ad2887..26c7e41 100644 (file)
--- a/arch/arm/mach-rockchip/rk3288/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
@@ -138,7 +138,7 @@ static int ft_rk3288w_setup(void *blob)
        return ret;
 }
 
-int ft_board_setup(void *blob, struct bd_info *bd)
+int ft_system_setup(void *blob, struct bd_info *bd)
 {
        if (soc_is_rk3288w())
                return ft_rk3288w_setup(blob);

diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
index aee71ca..3596b82 100644 (file)
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -1,5 +1,11 @@
 if ROCKCHIP_RK3588
 
+config TARGET_EVB_RK3588
+       bool "Rockchip EVB1 v10"
+       select BOARD_LATE_INIT
+       help
+         RK3588 EVB is a evaluation board for Rockchp RK3588.
+
 config TARGET_RK3588_NEU6
        bool "Edgeble Neural Compute Module 6(Neu6) SoM"
        select BOARD_LATE_INIT
@@ -51,6 +57,7 @@ config SYS_MALLOC_F_LEN
        default 0x80000
 
 source board/edgeble/neural-compute-module-6/Kconfig
+source board/rockchip/evb_rk3588/Kconfig
 source board/radxa/rock5b-rk3588/Kconfig
 
 endif

diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index dc4112d..e2f67fc 100644 (file)
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -190,7 +190,7 @@ static void setup_boot_mode(void)
                  __func__, boot_ctx, boot_mode, instance, forced_mode);
        switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
        case BOOT_SERIAL_UART:
-               if (instance > ARRAY_SIZE(serial_addr))
+               if (instance >= ARRAY_SIZE(serial_addr))
                        break;
                /* serial : search associated node in devicetree */
                sprintf(cmd, "serial@%x", serial_addr[instance]);
@@ -220,7 +220,7 @@ static void setup_boot_mode(void)
                break;
        case BOOT_FLASH_SD:
        case BOOT_FLASH_EMMC:
-               if (instance > ARRAY_SIZE(sdmmc_addr))
+               if (instance >= ARRAY_SIZE(sdmmc_addr))
                        break;
                /* search associated sdmmc node in devicetree */
                sprintf(cmd, "mmc@%x", sdmmc_addr[instance]);

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 6417aee..6dcbb09 100644 (file)
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -52,37 +52,56 @@ config DRAM_SUN50I_H616
          like H616.
 
 if DRAM_SUN50I_H616
-config DRAM_SUN50I_H616_WRITE_LEVELING
-       bool "H616 DRAM write leveling"
-       ---help---
-         Select this when DRAM on your H616 board needs write leveling.
+config DRAM_SUN50I_H616_DX_ODT
+       hex "H616 DRAM DX ODT parameter"
+       help
+         DX ODT value from vendor DRAM settings.
 
-config DRAM_SUN50I_H616_READ_CALIBRATION
-       bool "H616 DRAM read calibration"
-       ---help---
-         Select this when DRAM on your H616 board needs read calibration.
+config DRAM_SUN50I_H616_DX_DRI
+       hex "H616 DRAM DX DRI parameter"
+       help
+         DX DRI value from vendor DRAM settings.
 
-config DRAM_SUN50I_H616_READ_TRAINING
-       bool "H616 DRAM read training"
-       ---help---
-         Select this when DRAM on your H616 board needs read training.
+config DRAM_SUN50I_H616_CA_DRI
+       hex "H616 DRAM CA DRI parameter"
+       help
+         CA DRI value from vendor DRAM settings.
 
-config DRAM_SUN50I_H616_WRITE_TRAINING
-       bool "H616 DRAM write training"
-       ---help---
-         Select this when DRAM on your H616 board needs write training.
+config DRAM_SUN50I_H616_ODT_EN
+       hex "H616 DRAM ODT EN parameter"
+       default 0x1
+       help
+         ODT EN value from vendor DRAM settings.
 
-config DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION
-       bool "H616 DRAM bit delay compensation"
-       ---help---
-         Select this when DRAM on your H616 board needs bit delay
-         compensation.
+config DRAM_SUN50I_H616_TPR0
+       hex "H616 DRAM TPR0 parameter"
+       default 0x0
+       help
+         TPR0 value from vendor DRAM settings.
 
-config DRAM_SUN50I_H616_UNKNOWN_FEATURE
-       bool "H616 DRAM unknown feature"
-       ---help---
-         Select this when DRAM on your H616 board needs this unknown
-         feature.
+config DRAM_SUN50I_H616_TPR2
+       hex "H616 DRAM TPR2 parameter"
+       default 0x0
+       help
+         TPR2 value from vendor DRAM settings.
+
+config DRAM_SUN50I_H616_TPR10
+       hex "H616 DRAM TPR10 parameter"
+       help
+         TPR10 value from vendor DRAM settings. It tells which features
+         should be configured, like write leveling, read calibration, etc.
+
+config DRAM_SUN50I_H616_TPR11
+       hex "H616 DRAM TPR11 parameter"
+       default 0x0
+       help
+         TPR11 value from vendor DRAM settings.
+
+config DRAM_SUN50I_H616_TPR12
+       hex "H616 DRAM TPR12 parameter"
+       default 0x0
+       help
+         TPR12 value from vendor DRAM settings.
 endif
 
 config SUN6I_PRCM
@@ -110,6 +129,32 @@ config SUNXI_SRAM_ADDRESS
        Some newer SoCs map the boot ROM at address 0 instead and move the
        SRAM to a different address.
 
+config SUNXI_RVBAR_ADDRESS
+       hex
+       depends on ARM64
+       default 0x09010040 if SUN50I_GEN_H6
+       default 0x017000a0
+       ---help---
+       The read-only RVBAR system register holds the address of the first
+       instruction to execute after a reset. Allwinner cores provide a
+       writable MMIO backing store for this register, to allow to set the
+       entry point when switching to AArch64. This store is on different
+       addresses, depending on the SoC.
+
+config SUNXI_RVBAR_ALTERNATIVE
+       hex
+       depends on ARM64
+       default 0x08100040 if MACH_SUN50I_H616
+       default SUNXI_RVBAR_ADDRESS
+       ---help---
+       The H616 die exists in at least two variants, with one having the
+       RVBAR registers at a different address. If the SoC variant ID
+       (stored in SRAM_VER_REG[7:0]) is not 0, we need to use the
+       other address.
+       Set this alternative address to the same as the normal address
+       for all other SoCs, so the content of the SRAM_VER_REG becomes
+       irrelevant there, and we can use the same code.
+
 config SUNXI_A64_TIMER_ERRATUM
        bool
 
@@ -499,12 +544,12 @@ config DRAM_ZQ
 
 config DRAM_ODT_EN
        bool "sunxi dram odt enable"
+       depends on !MACH_SUN50I_H616
        default y if MACH_SUN8I_A23
        default y if MACH_SUNXI_H3_H5
        default y if MACH_SUN8I_R40
        default y if MACH_SUN50I
        default y if MACH_SUN50I_H6
-       default y if MACH_SUN50I_H616
        ---help---
        Select this to enable dram odt (on die termination).
 

diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 454c845..1f9416d 100644 (file)
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -234,37 +234,49 @@ static const u8 phy_init[] = {
        0x09, 0x05, 0x18
 };
 
-static void mctl_phy_configure_odt(void)
+static void mctl_phy_configure_odt(struct dram_para *para)
 {
-       writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x388);
-       writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x38c);
+       unsigned int val;
 
-       writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x3c8);
-       writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x3cc);
+       val = para->dx_dri & 0x1f;
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x388);
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x38c);
 
-       writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x408);
-       writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x40c);
+       val = (para->dx_dri >> 8) & 0x1f;
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c8);
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3cc);
 
-       writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x448);
-       writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x44c);
+       val = (para->dx_dri >> 16) & 0x1f;
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x408);
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x40c);
 
-       writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x340);
-       writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x344);
+       val = (para->dx_dri >> 24) & 0x1f;
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x448);
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x44c);
 
-       writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x348);
-       writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x34c);
+       val = para->ca_dri & 0x1f;
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x340);
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x344);
 
-       writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x380);
-       writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x384);
+       val = (para->ca_dri >> 8) & 0x1f;
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x348);
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x34c);
 
-       writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x3c0);
-       writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x3c4);
+       val = para->dx_odt & 0x1f;
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x380);
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x384);
 
-       writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x400);
-       writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x404);
+       val = (para->dx_odt >> 8) & 0x1f;
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c0);
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c4);
 
-       writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x440);
-       writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x444);
+       val = (para->dx_odt >> 16) & 0x1f;
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x400);
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x404);
+
+       val = (para->dx_odt >> 24) & 0x1f;
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x440);
+       writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x444);
 
        dmb();
 }
@@ -285,7 +297,7 @@ static bool mctl_phy_write_leveling(struct dram_para *para)
        else
                val = 3;
 
-       mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x188), val, val);
+       mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x188), val, val);
 
        clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4);
 
@@ -314,7 +326,7 @@ static bool mctl_phy_write_leveling(struct dram_para *para)
                else
                        val = 3;
 
-               mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x188), val, val);
+               mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x188), val, val);
 
                clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4);
        }
@@ -398,26 +410,26 @@ static bool mctl_phy_read_training(struct dram_para *para)
        setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 6);
        setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 1);
 
-       mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x840), 0xc, 0xc);
+       mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x840), 0xc, 0xc);
        if (readl(SUNXI_DRAM_PHY0_BASE + 0x840) & 3)
                result = false;
 
        if (para->bus_full_width) {
-               mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0xa40), 0xc, 0xc);
+               mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa40), 0xc, 0xc);
                if (readl(SUNXI_DRAM_PHY0_BASE + 0xa40) & 3)
                        result = false;
        }
 
-       ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x898);
-       ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x850);
+       ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x898);
+       ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x850);
        for (i = 0; i < 9; i++) {
                val1 = readl(&ptr1[i]);
                val2 = readl(&ptr2[i]);
                if (val1 - val2 <= 6)
                        result = false;
        }
-       ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x8bc);
-       ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x874);
+       ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x8bc);
+       ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x874);
        for (i = 0; i < 9; i++) {
                val1 = readl(&ptr1[i]);
                val2 = readl(&ptr2[i]);
@@ -426,8 +438,8 @@ static bool mctl_phy_read_training(struct dram_para *para)
        }
 
        if (para->bus_full_width) {
-               ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xa98);
-               ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xa50);
+               ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa98);
+               ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa50);
                for (i = 0; i < 9; i++) {
                        val1 = readl(&ptr1[i]);
                        val2 = readl(&ptr2[i]);
@@ -435,8 +447,8 @@ static bool mctl_phy_read_training(struct dram_para *para)
                                result = false;
                }
 
-               ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xabc);
-               ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xa74);
+               ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xabc);
+               ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa74);
                for (i = 0; i < 9; i++) {
                        val1 = readl(&ptr1[i]);
                        val2 = readl(&ptr2[i]);
@@ -454,12 +466,12 @@ static bool mctl_phy_read_training(struct dram_para *para)
                setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 6);
                setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 1);
 
-               mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x840), 0xc, 0xc);
+               mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x840), 0xc, 0xc);
                if (readl(SUNXI_DRAM_PHY0_BASE + 0x840) & 3)
                        result = false;
 
                if (para->bus_full_width) {
-                       mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0xa40), 0xc, 0xc);
+                       mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa40), 0xc, 0xc);
                        if (readl(SUNXI_DRAM_PHY0_BASE + 0xa40) & 3)
                                result = false;
                }
@@ -488,26 +500,26 @@ static bool mctl_phy_write_training(struct dram_para *para)
        setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
        setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x20);
 
-       mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x8e0), 3, 3);
+       mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x8e0), 3, 3);
        if (readl(SUNXI_DRAM_PHY0_BASE + 0x8e0) & 0xc)
                result = false;
 
        if (para->bus_full_width) {
-               mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0xae0), 3, 3);
+               mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0xae0), 3, 3);
                if (readl(SUNXI_DRAM_PHY0_BASE + 0xae0) & 0xc)
                        result = false;
        }
 
-       ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x938);
-       ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x8f0);
+       ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x938);
+       ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x8f0);
        for (i = 0; i < 9; i++) {
                val1 = readl(&ptr1[i]);
                val2 = readl(&ptr2[i]);
                if (val1 - val2 <= 6)
                        result = false;
        }
-       ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x95c);
-       ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x914);
+       ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x95c);
+       ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x914);
        for (i = 0; i < 9; i++) {
                val1 = readl(&ptr1[i]);
                val2 = readl(&ptr2[i]);
@@ -516,16 +528,16 @@ static bool mctl_phy_write_training(struct dram_para *para)
        }
 
        if (para->bus_full_width) {
-               ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xb38);
-               ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xaf0);
+               ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xb38);
+               ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xaf0);
                for (i = 0; i < 9; i++) {
                        val1 = readl(&ptr1[i]);
                        val2 = readl(&ptr2[i]);
                        if (val1 - val2 <= 6)
                                result = false;
                }
-               ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xb5c);
-               ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xb14);
+               ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xb5c);
+               ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xb14);
                for (i = 0; i < 9; i++) {
                        val1 = readl(&ptr1[i]);
                        val2 = readl(&ptr2[i]);
@@ -542,12 +554,12 @@ static bool mctl_phy_write_training(struct dram_para *para)
                setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
                setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x20);
 
-               mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x8e0), 3, 3);
+               mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x8e0), 3, 3);
                if (readl(SUNXI_DRAM_PHY0_BASE + 0x8e0) & 0xc)
                        result = false;
 
                if (para->bus_full_width) {
-                       mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0xae0), 3, 3);
+                       mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0xae0), 3, 3);
                        if (readl(SUNXI_DRAM_PHY0_BASE + 0xae0) & 0xc)
                                result = false;
                }
@@ -560,116 +572,254 @@ static bool mctl_phy_write_training(struct dram_para *para)
        return result;
 }
 
-static bool mctl_phy_bit_delay_compensation(struct dram_para *para)
+static void mctl_phy_bit_delay_compensation(struct dram_para *para)
 {
-       u32 *ptr;
+       u32 *ptr, val;
        int i;
 
-       clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1);
-       setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 8);
-       clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
+       if (para->tpr10 & TPR10_DX_BIT_DELAY1) {
+               clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1);
+               setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 8);
+               clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
 
-       ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x484);
-       for (i = 0; i < 9; i++) {
-               writel_relaxed(0x16, ptr);
-               writel_relaxed(0x16, ptr + 0x30);
-               ptr += 2;
-       }
-       writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4d0);
-       writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x590);
-       writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4cc);
-       writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x58c);
+               if (para->tpr10 & BIT(30))
+                       val = para->tpr11 & 0x3f;
+               else
+                       val = (para->tpr11 & 0xf) << 1;
 
-       ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x4d8);
-       for (i = 0; i < 9; i++) {
-               writel_relaxed(0x1a, ptr);
-               writel_relaxed(0x1a, ptr + 0x30);
-               ptr += 2;
-       }
-       writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x524);
-       writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x5e4);
-       writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x520);
-       writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x5e0);
+               ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x484);
+               for (i = 0; i < 9; i++) {
+                       writel_relaxed(val, ptr);
+                       writel_relaxed(val, ptr + 0x30);
+                       ptr += 2;
+               }
 
-       ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x604);
-       for (i = 0; i < 9; i++) {
-               writel_relaxed(0x1a, ptr);
-               writel_relaxed(0x1a, ptr + 0x30);
-               ptr += 2;
-       }
-       writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x650);
-       writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x710);
-       writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x64c);
-       writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x70c);
+               if (para->tpr10 & BIT(30))
+                       val = (para->odt_en >> 15) & 0x1e;
+               else
+                       val = (para->tpr11 >> 15) & 0x1e;
 
-       ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x658);
-       for (i = 0; i < 9; i++) {
-               writel_relaxed(0x1a, ptr);
-               writel_relaxed(0x1a, ptr + 0x30);
-               ptr += 2;
-       }
-       writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x6a4);
-       writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x764);
-       writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x6a0);
-       writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x760);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x4d0);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x590);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x4cc);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x58c);
 
-       dmb();
+               if (para->tpr10 & BIT(30))
+                       val = (para->tpr11 >> 8) & 0x3f;
+               else
+                       val = (para->tpr11 >> 3) & 0x1e;
 
-       setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1);
+               ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d8);
+               for (i = 0; i < 9; i++) {
+                       writel_relaxed(val, ptr);
+                       writel_relaxed(val, ptr + 0x30);
+                       ptr += 2;
+               }
 
-       /* second part */
-       clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, 0x80);
-       clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 4);
+               if (para->tpr10 & BIT(30))
+                       val = (para->odt_en >> 19) & 0x1e;
+               else
+                       val = (para->tpr11 >> 19) & 0x1e;
 
-       ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x480);
-       for (i = 0; i < 9; i++) {
-               writel_relaxed(0x10, ptr);
-               writel_relaxed(0x10, ptr + 0x30);
-               ptr += 2;
-       }
-       writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x528);
-       writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x5e8);
-       writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x4c8);
-       writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x588);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x524);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x5e4);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x520);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x5e0);
 
-       ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x4d4);
-       for (i = 0; i < 9; i++) {
-               writel_relaxed(0x12, ptr);
-               writel_relaxed(0x12, ptr + 0x30);
-               ptr += 2;
-       }
-       writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x52c);
-       writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x5ec);
-       writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x51c);
-       writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x5dc);
+               if (para->tpr10 & BIT(30))
+                       val = (para->tpr11 >> 16) & 0x3f;
+               else
+                       val = (para->tpr11 >> 7) & 0x1e;
 
-       ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x600);
-       for (i = 0; i < 9; i++) {
-               writel_relaxed(0x12, ptr);
-               writel_relaxed(0x12, ptr + 0x30);
-               ptr += 2;
-       }
-       writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x6a8);
-       writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x768);
-       writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x648);
-       writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x708);
+               ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x604);
+               for (i = 0; i < 9; i++) {
+                       writel_relaxed(val, ptr);
+                       writel_relaxed(val, ptr + 0x30);
+                       ptr += 2;
+               }
 
-       ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x654);
-       for (i = 0; i < 9; i++) {
-               writel_relaxed(0x14, ptr);
-               writel_relaxed(0x14, ptr + 0x30);
-               ptr += 2;
+               if (para->tpr10 & BIT(30))
+                       val = (para->odt_en >> 23) & 0x1e;
+               else
+                       val = (para->tpr11 >> 23) & 0x1e;
+
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x650);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x710);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x64c);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x70c);
+
+               if (para->tpr10 & BIT(30))
+                       val = (para->tpr11 >> 24) & 0x3f;
+               else
+                       val = (para->tpr11 >> 11) & 0x1e;
+
+               ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x658);
+               for (i = 0; i < 9; i++) {
+                       writel_relaxed(val, ptr);
+                       writel_relaxed(val, ptr + 0x30);
+                       ptr += 2;
+               }
+
+               if (para->tpr10 & BIT(30))
+                       val = (para->odt_en >> 27) & 0x1e;
+               else
+                       val = (para->tpr11 >> 27) & 0x1e;
+
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x6a4);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x764);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x6a0);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x760);
+
+               dmb();
+
+               setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1);
        }
-       writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x6ac);
-       writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x76c);
-       writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x69c);
-       writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x75c);
 
-       dmb();
+       if (para->tpr10 & TPR10_DX_BIT_DELAY0) {
+               clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, 0x80);
+               clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 4);
+
+               if (para->tpr10 & BIT(30))
+                       val = para->tpr12 & 0x3f;
+               else
+                       val = (para->tpr12 & 0xf) << 1;
+
+               ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x480);
+               for (i = 0; i < 9; i++) {
+                       writel_relaxed(val, ptr);
+                       writel_relaxed(val, ptr + 0x30);
+                       ptr += 2;
+               }
 
-       setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, 0x80);
+               if (para->tpr10 & BIT(30))
+                       val = (para->odt_en << 1) & 0x1e;
+               else
+                       val = (para->tpr12 >> 15) & 0x1e;
 
-       return true;
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x528);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x5e8);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x4c8);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x588);
+
+               if (para->tpr10 & BIT(30))
+                       val = (para->tpr12 >> 8) & 0x3f;
+               else
+                       val = (para->tpr12 >> 3) & 0x1e;
+
+               ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d4);
+               for (i = 0; i < 9; i++) {
+                       writel_relaxed(val, ptr);
+                       writel_relaxed(val, ptr + 0x30);
+                       ptr += 2;
+               }
+
+               if (para->tpr10 & BIT(30))
+                       val = (para->odt_en >> 3) & 0x1e;
+               else
+                       val = (para->tpr12 >> 19) & 0x1e;
+
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x52c);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x5ec);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x51c);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x5dc);
+
+               if (para->tpr10 & BIT(30))
+                       val = (para->tpr12 >> 16) & 0x3f;
+               else
+                       val = (para->tpr12 >> 7) & 0x1e;
+
+               ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x600);
+               for (i = 0; i < 9; i++) {
+                       writel_relaxed(val, ptr);
+                       writel_relaxed(val, ptr + 0x30);
+                       ptr += 2;
+               }
+
+               if (para->tpr10 & BIT(30))
+                       val = (para->odt_en >> 7) & 0x1e;
+               else
+                       val = (para->tpr12 >> 23) & 0x1e;
+
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x6a8);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x768);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x648);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x708);
+
+               if (para->tpr10 & BIT(30))
+                       val = (para->tpr12 >> 24) & 0x3f;
+               else
+                       val = (para->tpr12 >> 11) & 0x1e;
+
+               ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x654);
+               for (i = 0; i < 9; i++) {
+                       writel_relaxed(val, ptr);
+                       writel_relaxed(val, ptr + 0x30);
+                       ptr += 2;
+               }
+
+               if (para->tpr10 & BIT(30))
+                       val = (para->odt_en >> 11) & 0x1e;
+               else
+                       val = (para->tpr12 >> 27) & 0x1e;
+
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x6ac);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x76c);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x69c);
+               writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x75c);
+
+               dmb();
+
+               setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, 0x80);
+       }
+}
+
+static void mctl_phy_ca_bit_delay_compensation(struct dram_para *para)
+{
+       u32 val, *ptr;
+       int i;
+
+       if (para->tpr0 & BIT(30))
+               val = (para->tpr0 >> 7) & 0x3e;
+       else
+               val = (para->tpr10 >> 3) & 0x1e;
+
+       ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x780);
+       for (i = 0; i < 32; i++)
+               writel(val, &ptr[i]);
+
+       val = (para->tpr10 << 1) & 0x1e;
+       writel(val, SUNXI_DRAM_PHY0_BASE + 0x7d8);
+       writel(val, SUNXI_DRAM_PHY0_BASE + 0x7dc);
+       writel(val, SUNXI_DRAM_PHY0_BASE + 0x7e0);
+       writel(val, SUNXI_DRAM_PHY0_BASE + 0x7f4);
+
+       /* following configuration is DDR3 specific */
+       val = (para->tpr10 >> 7) & 0x1e;
+       if (para->tpr2 & 1) {
+               writel(val, SUNXI_DRAM_PHY0_BASE + 0x794);
+               if (para->ranks == 2) {
+                       val = (para->tpr10 >> 11) & 0x1e;
+                       writel(val, SUNXI_DRAM_PHY0_BASE + 0x7e4);
+               }
+               if (para->tpr0 & BIT(31)) {
+                       val = (para->tpr0 << 1) & 0x3e;
+                       writel(val, SUNXI_DRAM_PHY0_BASE + 0x790);
+                       writel(val, SUNXI_DRAM_PHY0_BASE + 0x7b8);
+                       writel(val, SUNXI_DRAM_PHY0_BASE + 0x7cc);
+               }
+       } else {
+               writel(val, SUNXI_DRAM_PHY0_BASE + 0x7d4);
+               if (para->ranks == 2) {
+                       val = (para->tpr10 >> 11) & 0x1e;
+                       writel(val, SUNXI_DRAM_PHY0_BASE + 0x79c);
+               }
+               if (para->tpr0 & BIT(31)) {
+                       val = (para->tpr0 << 1) & 0x3e;
+                       writel(val, SUNXI_DRAM_PHY0_BASE + 0x78c);
+                       writel(val, SUNXI_DRAM_PHY0_BASE + 0x7a4);
+                       writel(val, SUNXI_DRAM_PHY0_BASE + 0x7b8);
+               }
+       }
 }
 
 static bool mctl_phy_init(struct dram_para *para)
@@ -678,7 +828,7 @@ static bool mctl_phy_init(struct dram_para *para)
                        (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
        struct sunxi_mctl_ctl_reg * const mctl_ctl =
                        (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-       u32 val, *ptr;
+       u32 val, val2, *ptr, mr0, mr2;
        int i;
 
        if (para->bus_full_width)
@@ -687,42 +837,40 @@ static bool mctl_phy_init(struct dram_para *para)
                val = 3;
        clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x3c, 0xf, val);
 
-       writel(0xd, SUNXI_DRAM_PHY0_BASE + 0x14);
-       writel(0xd, SUNXI_DRAM_PHY0_BASE + 0x35c);
-       writel(0xd, SUNXI_DRAM_PHY0_BASE + 0x368);
-       writel(0xd, SUNXI_DRAM_PHY0_BASE + 0x374);
+       if (para->tpr2 & 0x100) {
+               val = 9;
+               val2 = 7;
+       } else {
+               val = 13;
+               val2 = 9;
+       }
+
+       writel(val, SUNXI_DRAM_PHY0_BASE + 0x14);
+       writel(val, SUNXI_DRAM_PHY0_BASE + 0x35c);
+       writel(val, SUNXI_DRAM_PHY0_BASE + 0x368);
+       writel(val, SUNXI_DRAM_PHY0_BASE + 0x374);
 
        writel(0, SUNXI_DRAM_PHY0_BASE + 0x18);
        writel(0, SUNXI_DRAM_PHY0_BASE + 0x360);
        writel(0, SUNXI_DRAM_PHY0_BASE + 0x36c);
        writel(0, SUNXI_DRAM_PHY0_BASE + 0x378);
 
-       writel(9, SUNXI_DRAM_PHY0_BASE + 0x1c);
-       writel(9, SUNXI_DRAM_PHY0_BASE + 0x364);
-       writel(9, SUNXI_DRAM_PHY0_BASE + 0x370);
-       writel(9, SUNXI_DRAM_PHY0_BASE + 0x37c);
+       writel(val2, SUNXI_DRAM_PHY0_BASE + 0x1c);
+       writel(val2, SUNXI_DRAM_PHY0_BASE + 0x364);
+       writel(val2, SUNXI_DRAM_PHY0_BASE + 0x370);
+       writel(val2, SUNXI_DRAM_PHY0_BASE + 0x37c);
 
-       ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xc0);
+       ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xc0);
        for (i = 0; i < ARRAY_SIZE(phy_init); i++)
                writel(phy_init[i], &ptr[i]);
 
-       if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_UNKNOWN_FEATURE)) {
-               ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x780);
-               for (i = 0; i < 32; i++)
-                       writel(0x16, &ptr[i]);
-               writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x78c);
-               writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7a4);
-               writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7b8);
-               writel(0x8, SUNXI_DRAM_PHY0_BASE + 0x7d4);
-               writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7dc);
-               writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7e0);
-       }
+       if (para->tpr10 & TPR10_CA_BIT_DELAY)
+               mctl_phy_ca_bit_delay_compensation(para);
 
        writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x3dc);
        writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x45c);
 
-       if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
-               mctl_phy_configure_odt();
+       mctl_phy_configure_odt(para);
 
        clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 7, 0xa);
 
@@ -738,7 +886,7 @@ static bool mctl_phy_init(struct dram_para *para)
 
        clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14c, 8);
 
-       mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x180), 4, 4);
+       mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x180), 4, 4);
 
        writel(0x37, SUNXI_DRAM_PHY0_BASE + 0x58);
        clrbits_le32(&mctl_com->unk_0x500, 0x200);
@@ -766,7 +914,15 @@ static bool mctl_phy_init(struct dram_para *para)
        writel(1, &mctl_ctl->swctl);
        mctl_await_completion(&mctl_ctl->swstat, 1, 1);
 
-       writel(0x1f14, &mctl_ctl->mrctrl1);
+       if (para->tpr2 & 0x100) {
+               mr0 = 0x1b50;
+               mr2 = 0x10;
+       } else {
+               mr0 = 0x1f14;
+               mr2 = 0x20;
+       }
+
+       writel(mr0, &mctl_ctl->mrctrl1);
        writel(0x80000030, &mctl_ctl->mrctrl0);
        mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
 
@@ -774,7 +930,7 @@ static bool mctl_phy_init(struct dram_para *para)
        writel(0x80001030, &mctl_ctl->mrctrl0);
        mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
 
-       writel(0x20, &mctl_ctl->mrctrl1);
+       writel(mr2, &mctl_ctl->mrctrl1);
        writel(0x80002030, &mctl_ctl->mrctrl0);
        mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
 
@@ -788,7 +944,7 @@ static bool mctl_phy_init(struct dram_para *para)
        clrbits_le32(&mctl_ctl->rfshctl3, 1);
        writel(1, &mctl_ctl->swctl);
 
-       if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_WRITE_LEVELING)) {
+       if (para->tpr10 & TPR10_WRITE_LEVELING) {
                for (i = 0; i < 5; i++)
                        if (mctl_phy_write_leveling(para))
                                break;
@@ -798,7 +954,7 @@ static bool mctl_phy_init(struct dram_para *para)
                }
        }
 
-       if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION)) {
+       if (para->tpr10 & TPR10_READ_CALIBRATION) {
                for (i = 0; i < 5; i++)
                        if (mctl_phy_read_calibration(para))
                                break;
@@ -808,7 +964,7 @@ static bool mctl_phy_init(struct dram_para *para)
                }
        }
 
-       if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_READ_TRAINING)) {
+       if (para->tpr10 & TPR10_READ_TRAINING) {
                for (i = 0; i < 5; i++)
                        if (mctl_phy_read_training(para))
                                break;
@@ -818,7 +974,7 @@ static bool mctl_phy_init(struct dram_para *para)
                }
        }
 
-       if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_WRITE_TRAINING)) {
+       if (para->tpr10 & TPR10_WRITE_TRAINING) {
                for (i = 0; i < 5; i++)
                        if (mctl_phy_write_training(para))
                                break;
@@ -828,8 +984,7 @@ static bool mctl_phy_init(struct dram_para *para)
                }
        }
 
-       if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION))
-               mctl_phy_bit_delay_compensation(para);
+       mctl_phy_bit_delay_compensation(para);
 
        clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 4);
 
@@ -873,7 +1028,7 @@ static bool mctl_ctrl_init(struct dram_para *para)
        writel(0x06000400, &mctl_ctl->unk_0x3240);
        writel(0x06000400, &mctl_ctl->unk_0x4240);
 
-       setbits_le32(&mctl_com->cr, BIT(31));
+       writel(BIT(31), &mctl_com->cr);
 
        mctl_set_addrmap(para);
 
@@ -1007,6 +1162,15 @@ unsigned long sunxi_dram_init(void)
        struct dram_para para = {
                .clk = CONFIG_DRAM_CLK,
                .type = SUNXI_DRAM_TYPE_DDR3,
+               .dx_odt = CONFIG_DRAM_SUN50I_H616_DX_ODT,
+               .dx_dri = CONFIG_DRAM_SUN50I_H616_DX_DRI,
+               .ca_dri = CONFIG_DRAM_SUN50I_H616_CA_DRI,
+               .odt_en = CONFIG_DRAM_SUN50I_H616_ODT_EN,
+               .tpr0 = CONFIG_DRAM_SUN50I_H616_TPR0,
+               .tpr2 = CONFIG_DRAM_SUN50I_H616_TPR2,
+               .tpr10 = CONFIG_DRAM_SUN50I_H616_TPR10,
+               .tpr11 = CONFIG_DRAM_SUN50I_H616_TPR11,
+               .tpr12 = CONFIG_DRAM_SUN50I_H616_TPR12,
        };
        unsigned long size;
 

diff --git a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c
index 8f50834..eea4d6a 100644 (file)
--- a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c
+++ b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c
@@ -48,10 +48,22 @@ void mctl_set_timing_params(struct dram_para *para)
        u8 tcl          = 7;                    /* JEDEC: CL / 2 => 6 */
        u8 tcwl         = 5;                    /* JEDEC: 8 */
        u8 t_rdata_en   = 9;                    /* ? */
+       u8 t_wr_lat     = 5;                    /* ? */
 
-       u8 twtp         = 14;                   /* (WL + BL / 2 + tWR) / 2 */
-       u8 twr2rd       = trtp + 7;             /* (WL + BL / 2 + tWTR) / 2 */
-       u8 trd2wr       = 5;                    /* (RL + BL / 2 + 2 - WL) / 2 */
+       u8 twtp;                                /* (WL + BL / 2 + tWR) / 2 */
+       u8 twr2rd;                              /* (WL + BL / 2 + tWTR) / 2 */
+       u8 trd2wr;                              /* (RL + BL / 2 + 2 - WL) / 2 */
+
+       if (para->tpr2 & 0x100) {
+               tcl = 5;
+               tcwl = 4;
+               t_rdata_en = 5;
+               t_wr_lat = 3;
+       }
+
+       twtp   = tcl + 2 + tcwl;
+       twr2rd = trtp + 2 + tcwl;
+       trd2wr = tcl + 3 - tcwl;
 
        /* set DRAM timing */
        writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,
@@ -85,7 +97,7 @@ void mctl_set_timing_params(struct dram_para *para)
        clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660);
 
        /* Configure DFI timing */
-       writel((tcl - 2) | 0x2000000 | (t_rdata_en << 16) | 0x808000,
+       writel(t_wr_lat | 0x2000000 | (t_rdata_en << 16) | 0x808000,
               &mctl_ctl->dfitmg0);
        writel(0x100202, &mctl_ctl->dfitmg1);
 

diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 76233ef..1911563 100644 (file)
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -198,7 +198,17 @@ source "board/freescale/m5373evb/Kconfig"
 source "board/sysam/amcore/Kconfig"
 source "board/sysam/stmark2/Kconfig"
 
+config M68K_QEMU
+       bool "Build with workarounds for incomplete QEMU emulation"
+       default n
+       help
+         QEMU 8.x currently does not implement RAMBAR accesses and
+         DMA timers. Enable this option for U-Boot CI purposes only
+         to skip the RAMBAR accesses.
+
 config MCFTMR
        bool "Use DMA timer"
+       default y if !M68K_QEMU
+       default n if M68K_QEMU
 
 endmenu

diff --git a/arch/m68k/cpu/mcf523x/interrupts.c b/arch/m68k/cpu/mcf523x/interrupts.c
index b02ea29..09c7f9e 100644 (file)
--- a/arch/m68k/cpu/mcf523x/interrupts.c
+++ b/arch/m68k/cpu/mcf523x/interrupts.c
@@ -22,7 +22,7 @@ int interrupt_init(void)
        return 0;
 }
 
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
 void dtimer_intr_setup(void)
 {
        int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);

diff --git a/arch/m68k/cpu/mcf52x2/interrupts.c b/arch/m68k/cpu/mcf52x2/interrupts.c
index e787c76..c5ed060 100644 (file)
--- a/arch/m68k/cpu/mcf52x2/interrupts.c
+++ b/arch/m68k/cpu/mcf52x2/interrupts.c
@@ -34,7 +34,7 @@ int interrupt_init(void)
        return 0;
 }
 
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
 void dtimer_intr_setup(void)
 {
        intctrl_t *intp = (intctrl_t *) (CFG_SYS_INTR_BASE);
@@ -42,7 +42,7 @@ void dtimer_intr_setup(void)
        clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
        setbits_be32(&intp->int_icr1, CFG_SYS_TMRINTR_PRI);
 }
-#endif                         /* CFG_MCFTMR */
+#endif                         /* CONFIG_MCFTMR */
 #endif                         /* CONFIG_M5272 */
 
 #if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
@@ -63,7 +63,7 @@ int interrupt_init(void)
        return 0;
 }
 
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
 void dtimer_intr_setup(void)
 {
        int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
@@ -72,7 +72,7 @@ void dtimer_intr_setup(void)
        clrbits_be32(&intp->imrl0, 0x00000001);
        clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK);
 }
-#endif                         /* CFG_MCFTMR */
+#endif                         /* CONFIG_MCFTMR */
 #endif                         /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
 
 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
@@ -83,11 +83,11 @@ int interrupt_init(void)
        return 0;
 }
 
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
 void dtimer_intr_setup(void)
 {
        mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
        mbar_writeByte(MCFSIM_TIMER2ICR, CFG_SYS_TMRINTR_PRI);
 }
-#endif                         /* CFG_MCFTMR */
+#endif                         /* CONFIG_MCFTMR */
 #endif                         /* CONFIG_M5249 || CONFIG_M5253 */

diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S
index d48d019..51d2e23 100644 (file)
--- a/arch/m68k/cpu/mcf52x2/start.S
+++ b/arch/m68k/cpu/mcf52x2/start.S
@@ -98,7 +98,7 @@ _start:
        nop
        move.w  #0x2700,%sr
 
-#if defined(CONFIG_M5208)
+#if defined(CONFIG_M5208) && !defined(CONFIG_M68K_QEMU)
        /* Initialize RAMBAR: locate SRAM and validate it */
        move.l  #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
        movec   %d0, %RAMBAR1
@@ -120,7 +120,7 @@ _start:
        movec   %d0, %RAMBAR0
 #endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
 
-#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
+#if (defined(CONFIG_M5282) || defined(CONFIG_M5271)) && !defined(CONFIG_M68K_QEMU)
        /* set MBAR address + valid flag */
        move.l  #(CFG_SYS_MBAR + 1), %d0
        move.l  %d0, 0x40000000

diff --git a/arch/m68k/cpu/mcf532x/interrupts.c b/arch/m68k/cpu/mcf532x/interrupts.c
index bbe823c..4f72fa8 100644 (file)
--- a/arch/m68k/cpu/mcf532x/interrupts.c
+++ b/arch/m68k/cpu/mcf532x/interrupts.c
@@ -23,7 +23,7 @@ int interrupt_init(void)
        return 0;
 }
 
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
 void dtimer_intr_setup(void)
 {
        int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);

diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c
index 1ce2448..bc3a2f3 100644 (file)
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -159,14 +159,14 @@ void cpu_init_f(void)
        /* NAND */
        out_8(&pm->pmcr0, 63);
 
-#ifdef CONFIG_SYS_I2C_0
+#ifdef CFG_SYS_I2C_0
        out_8(&gpio->par_cani2c, 0xF0);
        /* I2C0 pull up */
        out_be16(&gpio->pcr_b, 0x003C);
        /* I2C0 max speed */
        out_8(&gpio->srcr_cani2c, 0x03);
 #endif
-#ifdef CONFIG_SYS_I2C_2
+#ifdef CFG_SYS_I2C_2
        /* I2C2 */
        out_8(&gpio->par_ssi0h, 0xA0);
        /* I2C2, UART7 */
@@ -184,7 +184,7 @@ void cpu_init_f(void)
        /* I2C2 pull up */
        out_be16(&gpio->pcr_h, 0xF000);
 #endif
-#ifdef CONFIG_SYS_I2C_5
+#ifdef CFG_SYS_I2C_5
        /* I2C5 */
        out_8(&gpio->par_uart1, 0x0A);
        /* I2C5 pull up */

diff --git a/arch/m68k/cpu/mcf5445x/interrupts.c b/arch/m68k/cpu/mcf5445x/interrupts.c
index fb80a87..400f3de 100644 (file)
--- a/arch/m68k/cpu/mcf5445x/interrupts.c
+++ b/arch/m68k/cpu/mcf5445x/interrupts.c
@@ -26,7 +26,7 @@ int interrupt_init(void)
        return 0;
 }
 
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
 void dtimer_intr_setup(void)
 {
        int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);

diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c
index eb73da6..5c78eb9 100644 (file)
--- a/arch/m68k/cpu/mcf5445x/speed.c
+++ b/arch/m68k/cpu/mcf5445x/speed.c
@@ -129,9 +129,8 @@ int get_clocks(void)
        setup_5441x_clocks();
 #endif
 
-#ifdef CONFIG_SYS_FSL_I2C
-       gd->arch.i2c1_clk = gd->bus_clk;
-#endif
+       if (IS_ENABLED(CONFIG_SYS_I2C_FSL))
+               gd->arch.i2c1_clk = gd->bus_clk;
 
        return (0);
 }

diff --git a/arch/m68k/dts/M5208EVBE.dts b/arch/m68k/dts/M5208EVBE.dts
index 78973fc..1c32718 100644 (file)
--- a/arch/m68k/dts/M5208EVBE.dts
+++ b/arch/m68k/dts/M5208EVBE.dts
@@ -23,3 +23,9 @@
 &fec0 {
        status = "okay";
 };
+
+&i2c0 {
+       clock-frequency = <80000>;
+       u-boot,i2c-slave-addr = <0x7f>;
+       status = "okay";
+};

diff --git a/arch/m68k/dts/M5253DEMO.dts b/arch/m68k/dts/M5253DEMO.dts
index 515484a..a3f0706 100644 (file)
--- a/arch/m68k/dts/M5253DEMO.dts
+++ b/arch/m68k/dts/M5253DEMO.dts
@@ -20,3 +20,8 @@
        status = "okay";
 };
 
+&i2c0 {
+       clock-frequency = <80000>;
+       u-boot,i2c-slave-addr = <0x7f>;
+       status = "okay";
+};

diff --git a/arch/m68k/dts/M5275EVB.dts b/arch/m68k/dts/M5275EVB.dts
index 4737f92..d79f8a7 100644 (file)
--- a/arch/m68k/dts/M5275EVB.dts
+++ b/arch/m68k/dts/M5275EVB.dts
@@ -27,3 +27,9 @@
 &fec1 {
        status = "okay";
 };
+
+&i2c0 {
+       clock-frequency = <80000>;
+       u-boot,i2c-slave-addr = <0x7f>;
+       status = "okay";
+};

diff --git a/arch/m68k/dts/M53017EVB.dts b/arch/m68k/dts/M53017EVB.dts
index 31c50b6..90851dd 100644 (file)
--- a/arch/m68k/dts/M53017EVB.dts
+++ b/arch/m68k/dts/M53017EVB.dts
@@ -27,3 +27,9 @@
 &fec1 {
        status = "okay";
 };
+
+&i2c0 {
+       clock-frequency = <80000>;
+       u-boot,i2c-slave-addr = <0x7f>;
+       status = "okay";
+};

diff --git a/arch/m68k/dts/M5329AFEE.dts b/arch/m68k/dts/M5329AFEE.dts
index de4af47..c1cd284 100644 (file)
--- a/arch/m68k/dts/M5329AFEE.dts
+++ b/arch/m68k/dts/M5329AFEE.dts
@@ -23,3 +23,9 @@
 &fec0 {
        status = "okay";
 };
+
+&i2c0 {
+       clock-frequency = <80000>;
+       u-boot,i2c-slave-addr = <0x7f>;
+       status = "okay";
+};

diff --git a/arch/m68k/dts/M5329BFEE.dts b/arch/m68k/dts/M5329BFEE.dts
index 2b2aae2..51ec4b5 100644 (file)
--- a/arch/m68k/dts/M5329BFEE.dts
+++ b/arch/m68k/dts/M5329BFEE.dts
@@ -23,3 +23,9 @@
 &fec0 {
        status = "okay";
 };
+
+&i2c0 {
+       clock-frequency = <80000>;
+       u-boot,i2c-slave-addr = <0x7f>;
+       status = "okay";
+};

diff --git a/arch/m68k/dts/M5373EVB.dts b/arch/m68k/dts/M5373EVB.dts
index 7df8206..27ce800 100644 (file)
--- a/arch/m68k/dts/M5373EVB.dts
+++ b/arch/m68k/dts/M5373EVB.dts
@@ -23,3 +23,7 @@
 &fec0 {
        status = "okay";
 };
+
+&i2c0 {
+       status = "okay";
+};

diff --git a/arch/m68k/dts/astro_mcf5373l.dts b/arch/m68k/dts/astro_mcf5373l.dts
index d3caf12..40f84dd 100644 (file)
--- a/arch/m68k/dts/astro_mcf5373l.dts
+++ b/arch/m68k/dts/astro_mcf5373l.dts
@@ -20,3 +20,8 @@
        status = "okay";
 };
 
+&i2c0 {
+       clock-frequency = <80000>;
+       u-boot,i2c-slave-addr = <0x7f>;
+       status = "okay";
+};

diff --git a/arch/m68k/dts/eb_cpu5282.dts b/arch/m68k/dts/eb_cpu5282.dts
index 925f9af..27f33b9 100644 (file)
--- a/arch/m68k/dts/eb_cpu5282.dts
+++ b/arch/m68k/dts/eb_cpu5282.dts
@@ -23,3 +23,12 @@
 &fec0 {
        status = "okay";
 };
+
+&i2c0 {
+       status = "okay";
+
+       rtc@68 {
+               compatible = "dallas,ds1338";
+               reg = <0x68>;
+       };
+};

diff --git a/arch/m68k/dts/eb_cpu5282_internal.dts b/arch/m68k/dts/eb_cpu5282_internal.dts
index ae6a815..53a94ea 100644 (file)
--- a/arch/m68k/dts/eb_cpu5282_internal.dts
+++ b/arch/m68k/dts/eb_cpu5282_internal.dts
@@ -23,3 +23,12 @@
 &fec0 {
        status = "okay";
 };
+
+&i2c0 {
+       status = "okay";
+
+       rtc@68 {
+               compatible = "dallas,ds1338";
+               reg = <0x68>;
+       };
+};

diff --git a/arch/m68k/dts/mcf5208.dtsi b/arch/m68k/dts/mcf5208.dtsi
index 4802dd3..9392fac 100644 (file)
--- a/arch/m68k/dts/mcf5208.dtsi
+++ b/arch/m68k/dts/mcf5208.dtsi
@@ -42,5 +42,15 @@
                        timeout-loop = <50000>;
                        status = "disabled";
                };
+
+               i2c0: i2c@fc058000 {
+                       compatible = "fsl-i2c";
+                       #address-cells=<1>;
+                       #size-cells=<0>;
+                       cell-index = <0>;
+                       reg = <0xfc058000 0x14>;
+                       clock-frequency = <100000>;
+                       status = "disabled";
+               };
        };
 };

diff --git a/arch/m68k/dts/mcf523x.dtsi b/arch/m68k/dts/mcf523x.dtsi
index 550e824..41c7b9b 100644 (file)
--- a/arch/m68k/dts/mcf523x.dtsi
+++ b/arch/m68k/dts/mcf523x.dtsi
@@ -51,6 +51,16 @@
                                timeout-loop = <50000>;
                                status = "disabled";
                        };
+
+                       i2c0: i2c@300 {
+                               compatible = "fsl-i2c";
+                               #address-cells=<1>;
+                               #size-cells=<0>;
+                               cell-index = <0>;
+                               reg = <0x300 0x14>;
+                               clock-frequency = <100000>;
+                               status = "disabled";
+                       };
                };
        };
 };

diff --git a/arch/m68k/dts/mcf5249.dtsi b/arch/m68k/dts/mcf5249.dtsi
index 248b3dc..d45d553 100644 (file)
--- a/arch/m68k/dts/mcf5249.dtsi
+++ b/arch/m68k/dts/mcf5249.dtsi
@@ -33,6 +33,34 @@
                                reg = <0x200 0x40>;
                                status = "disabled";
                        };
+
+                       i2c0: i2c@280 {
+                               compatible = "fsl-i2c";
+                               #address-cells=<1>;
+                               #size-cells=<0>;
+                               cell-index = <0>;
+                               reg = <0x280 0x14>;
+                               clock-frequency = <100000>;
+                               status = "disabled";
+                       };
+               };
+
+               mbar2: mbar2@80000000 {
+                       compatible = "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x00000000 0x80000000 0x10000>;
+                       reg = <0x80000000 0x10000>;
+
+                       i2c1: i2c@440 {
+                               compatible = "fsl-i2c";
+                               #address-cells=<1>;
+                               #size-cells=<0>;
+                               cell-index = <0>;
+                               reg = <0x440 0x14>;
+                               clock-frequency = <100000>;
+                               status = "disabled";
+                       };
                };
        };
 };

diff --git a/arch/m68k/dts/mcf5253.dtsi b/arch/m68k/dts/mcf5253.dtsi
index 3bde2d6..b9816f4 100644 (file)
--- a/arch/m68k/dts/mcf5253.dtsi
+++ b/arch/m68k/dts/mcf5253.dtsi
@@ -39,6 +39,34 @@
                                reg = <0xc00 0x40>;
                                status = "disabled";
                        };
+
+                       i2c0: i2c@280 {
+                               compatible = "fsl-i2c";
+                               #address-cells=<1>;
+                               #size-cells=<0>;
+                               cell-index = <0>;
+                               reg = <0x280 0x14>;
+                               clock-frequency = <100000>;
+                               status = "disabled";
+                       };
+               };
+
+               mbar2: mbar2@80000000 {
+                       compatible = "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x00000000 0x80000000 0x10000>;
+                       reg = <0x80000000 0x10000>;
+
+                       i2c1: i2c@440 {
+                               compatible = "fsl-i2c";
+                               #address-cells=<1>;
+                               #size-cells=<0>;
+                               cell-index = <0>;
+                               reg = <0x440 0x14>;
+                               clock-frequency = <100000>;
+                               status = "disabled";
+                       };
                };
        };
 };

diff --git a/arch/m68k/dts/mcf5271.dtsi b/arch/m68k/dts/mcf5271.dtsi
index b3484c2..fc82bd3 100644 (file)
--- a/arch/m68k/dts/mcf5271.dtsi
+++ b/arch/m68k/dts/mcf5271.dtsi
@@ -49,6 +49,16 @@
                                timeout-loop = <50000>;
                                status = "disabled";
                        };
+
+                       i2c0: i2c@300 {
+                               compatible = "fsl-i2c";
+                               #address-cells=<1>;
+                               #size-cells=<0>;
+                               cell-index = <0>;
+                               reg = <0x300 0x14>;
+                               clock-frequency = <100000>;
+                               status = "disabled";
+                       };
                };
        };
 };

diff --git a/arch/m68k/dts/mcf5275.dtsi b/arch/m68k/dts/mcf5275.dtsi
index 99dd7d3..402517c 100644 (file)
--- a/arch/m68k/dts/mcf5275.dtsi
+++ b/arch/m68k/dts/mcf5275.dtsi
@@ -59,6 +59,16 @@
                                timeout-loop = <50000>;
                                status = "disabled";
                        };
+
+                       i2c0: i2c@300 {
+                               compatible = "fsl-i2c";
+                               #address-cells=<1>;
+                               #size-cells=<0>;
+                               cell-index = <0>;
+                               reg = <0x300 0x14>;
+                               clock-frequency = <100000>;
+                               status = "disabled";
+                       };
                };
        };
 };

diff --git a/arch/m68k/dts/mcf5282.dtsi b/arch/m68k/dts/mcf5282.dtsi
index d9916b1..883c0d0 100644 (file)
--- a/arch/m68k/dts/mcf5282.dtsi
+++ b/arch/m68k/dts/mcf5282.dtsi
@@ -49,6 +49,16 @@
                                timeout-loop = <50000>;
                                status = "disabled";
                        };
+
+                       i2c0: i2c@300 {
+                               compatible = "fsl-i2c";
+                               #address-cells=<1>;
+                               #size-cells=<0>;
+                               cell-index = <0>;
+                               reg = <0x300 0x14>;
+                               clock-frequency = <100000>;
+                               status = "disabled";
+                       };
                };
        };
 };

diff --git a/arch/m68k/dts/mcf5301x.dtsi b/arch/m68k/dts/mcf5301x.dtsi
index f60898a..a13afad 100644 (file)
--- a/arch/m68k/dts/mcf5301x.dtsi
+++ b/arch/m68k/dts/mcf5301x.dtsi
@@ -65,5 +65,15 @@
                        timeout-loop = <50000>;
                        status = "disabled";
                };
+
+               i2c0: i2c@0xfc058000 {
+                       compatible = "fsl-i2c";
+                       #address-cells=<1>;
+                       #size-cells=<0>;
+                       cell-index = <0>;
+                       reg = <0xfc058000 0x100>;
+                       clock-frequency = <100000>;
+                       status = "disabled";
+               };
        };
 };

diff --git a/arch/m68k/dts/mcf5307.dtsi b/arch/m68k/dts/mcf5307.dtsi
index e199cf9..d6d386b 100644 (file)
--- a/arch/m68k/dts/mcf5307.dtsi
+++ b/arch/m68k/dts/mcf5307.dtsi
@@ -34,6 +34,16 @@
                                reg = <0x200 0x40>;
                                status = "disabled";
                        };
+
+                       i2c0: i2c@280 {
+                               compatible = "fsl-i2c";
+                               #address-cells=<1>;
+                               #size-cells=<0>;
+                               cell-index = <0>;
+                               reg = <0x280 0x14>;
+                               clock-frequency = <100000>;
+                               status = "disabled";
+                       };
                };
        };
 };

diff --git a/arch/m68k/dts/mcf5329.dtsi b/arch/m68k/dts/mcf5329.dtsi
index de34896..7501cc4 100644 (file)
--- a/arch/m68k/dts/mcf5329.dtsi
+++ b/arch/m68k/dts/mcf5329.dtsi
@@ -42,5 +42,15 @@
                        timeout-loop = <50000>;
                        status = "disabled";
                };
+
+               i2c0: i2c@0xfc058000 {
+                       compatible = "fsl-i2c";
+                       #address-cells=<1>;
+                       #size-cells=<0>;
+                       cell-index = <0>;
+                       reg = <0xfc058000 0x100>;
+                       clock-frequency = <100000>;
+                       status = "disabled";
+               };
        };
 };

diff --git a/arch/m68k/dts/mcf537x.dtsi b/arch/m68k/dts/mcf537x.dtsi
index 2a2a32a..338b8b4 100644 (file)
--- a/arch/m68k/dts/mcf537x.dtsi
+++ b/arch/m68k/dts/mcf537x.dtsi
@@ -42,5 +42,15 @@
                        timeout-loop = <50000>;
                        status = "disabled";
                };
+
+               i2c0: i2c@0xfc058000 {
+                       compatible = "fsl-i2c";
+                       #address-cells=<1>;
+                       #size-cells=<0>;
+                       cell-index = <0>;
+                       reg = <0xfc058000 0x100>;
+                       clock-frequency = <100000>;
+                       status = "disabled";
+               };
        };
 };

diff --git a/arch/m68k/dts/mcf5441x.dtsi b/arch/m68k/dts/mcf5441x.dtsi
index 6769bdc..dcca363 100644 (file)
--- a/arch/m68k/dts/mcf5441x.dtsi
+++ b/arch/m68k/dts/mcf5441x.dtsi
@@ -103,5 +103,65 @@
                        timeout-loop = <50000>;
                        status = "disabled";
                };
+
+               i2c0: i2c@0xfc058000 {
+                       compatible = "fsl-i2c";
+                       #address-cells=<1>;
+                       #size-cells=<0>;
+                       cell-index = <0>;
+                       reg = <0xfc058000 0x100>;
+                       clock-frequency = <100000>;
+                       status = "disabled";
+               };
+
+               i2c1: i2c@0xfc038000 {
+                       compatible = "fsl-i2c";
+                       #address-cells=<1>;
+                       #size-cells=<0>;
+                       cell-index = <1>;
+                       reg = <0xfc038000 0x100>;
+                       clock-frequency = <100000>;
+                       status = "disabled";
+               };
+
+               i2c2: i2c@0xfc010000 {
+                       compatible = "fsl-i2c";
+                       #address-cells=<1>;
+                       #size-cells=<0>;
+                       cell-index = <2>;
+                       reg = <0xfc010000 0x100>;
+                       clock-frequency = <100000>;
+                       status = "disabled";
+               };
+
+               i2c3: i2c@0xfc014000 {
+                       compatible = "fsl-i2c";
+                       #address-cells=<1>;
+                       #size-cells=<0>;
+                       cell-index = <3>;
+                       reg = <0xfc014000 0x100>;
+                       clock-frequency = <100000>;
+                       status = "disabled";
+               };
+
+               i2c4: i2c@0xfc018000 {
+                       compatible = "fsl-i2c";
+                       #address-cells=<1>;
+                       #size-cells=<0>;
+                       cell-index = <4>;
+                       reg = <0xfc018000 0x100>;
+                       clock-frequency = <100000>;
+                       status = "disabled";
+               };
+
+               i2c5: i2c@0xfc01c000 {
+                       compatible = "fsl-i2c";
+                       #address-cells=<1>;
+                       #size-cells=<0>;
+                       cell-index = <5>;
+                       reg = <0xfc01c000 0x100>;
+                       clock-frequency = <100000>;
+                       status = "disabled";
+               };
        };
 };

diff --git a/arch/m68k/dts/stmark2.dts b/arch/m68k/dts/stmark2.dts
index ebe8580..3ba68b7 100644 (file)
--- a/arch/m68k/dts/stmark2.dts
+++ b/arch/m68k/dts/stmark2.dts
@@ -41,3 +41,7 @@
        status = "okay";
        mii-base = <0>;
 };
+
+&i2c0 {
+       status = "okay";
+};

diff --git a/arch/m68k/include/asm/fsl_i2c.h b/arch/m68k/include/asm/fsl_i2c.h
index 9c54fde..dc6b37a 100644 (file)
--- a/arch/m68k/include/asm/fsl_i2c.h
+++ b/arch/m68k/include/asm/fsl_i2c.h
@@ -57,4 +57,14 @@ typedef struct fsl_i2c_base {
 #define I2C_DR_RES     ~(I2C_DR)
 } fsl_i2c_t;
 
+#if CONFIG_IS_ENABLED(DM_I2C)
+struct fsl_i2c_dev {
+       struct fsl_i2c_base __iomem *base;      /* register base */
+       u32 i2c_clk;
+       u32 index;
+       u8 slaveadd;
+       uint speed;
+};
+#endif
+
 #endif /* _ASM_I2C_H_ */

diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index 74516cc..aafa4f4 100644 (file)
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -16,7 +16,7 @@
 #define CFG_SYS_UART_BASE              (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@@ -25,6 +25,8 @@
 #define CFG_SYS_TMRINTR_PEND           (CFG_SYS_TMRINTR_MASK)
 #define CFG_SYS_TMRINTR_PRI            (6)
 #define CFG_SYS_TIMER_PRESCALER        (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE            (MMAP_PIT0)
 #endif
 
 #define CFG_SYS_INTR_BASE              (MMAP_INTC0)
@@ -38,7 +40,7 @@
 #define CFG_SYS_UART_BASE              (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@@ -47,6 +49,8 @@
 #define CFG_SYS_TMRINTR_PEND   (CFG_SYS_TMRINTR_MASK)
 #define CFG_SYS_TMRINTR_PRI            (0x1E)          /* Level must include inorder to work */
 #define CFG_SYS_TIMER_PRESCALER        (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE            (MMAP_PIT0)
 #endif
 
 #define CFG_SYS_INTR_BASE              (MMAP_INTC0)
@@ -63,7 +67,7 @@
 #define CFG_SYS_NUM_IRQS               (64)
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG             (mbar_readLong(MCFSIM_IPR))
@@ -72,6 +76,8 @@
 #define CFG_SYS_TMRINTR_PEND   (CFG_SYS_TMRINTR_MASK)
 #define CFG_SYS_TMRINTR_PRI            (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
 #define CFG_SYS_TIMER_PRESCALER        (((gd->bus_clk / 2000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE            (MMAP_PIT0)
 #endif
 #endif                         /* CONFIG_M5249 */
 
@@ -86,7 +92,7 @@
 #define CFG_SYS_NUM_IRQS               (64)
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG             (mbar_readLong(MCFSIM_IPR))
@@ -95,6 +101,8 @@
 #define CFG_SYS_TMRINTR_PEND   (CFG_SYS_TMRINTR_MASK)
 #define CFG_SYS_TMRINTR_PRI            (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
 #define CFG_SYS_TIMER_PRESCALER        (((gd->bus_clk / 2000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE            (MMAP_PIT0)
 #endif
 #endif                         /* CONFIG_M5253 */
 
@@ -105,7 +113,7 @@
 #define CFG_SYS_UART_BASE              (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@@ -114,6 +122,8 @@
 #define CFG_SYS_TMRINTR_PEND   (CFG_SYS_TMRINTR_MASK)
 #define CFG_SYS_TMRINTR_PRI            (0x1E) /* Interrupt level 3, priority 6 */
 #define CFG_SYS_TIMER_PRESCALER        (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE            (MMAP_PIT0)
 #endif
 
 #define CFG_SYS_INTR_BASE              (MMAP_INTC0)
@@ -130,7 +140,7 @@
 #define CFG_SYS_NUM_IRQS               (64)
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_TMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_TMR3)
 #define CFG_SYS_TMRPND_REG             (((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr)
@@ -139,6 +149,8 @@
 #define CFG_SYS_TMRINTR_PEND   (0)
 #define CFG_SYS_TMRINTR_PRI            (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
 #define CFG_SYS_TIMER_PRESCALER        (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE            (MMAP_PIT0)
 #endif
 #endif                         /* CONFIG_M5272 */
 
@@ -152,7 +164,7 @@
 #define CFG_SYS_NUM_IRQS               (192)
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@@ -161,6 +173,8 @@
 #define CFG_SYS_TMRINTR_PEND   (CFG_SYS_TMRINTR_MASK)
 #define CFG_SYS_TMRINTR_PRI            (0x1E)
 #define CFG_SYS_TIMER_PRESCALER        (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE            (MMAP_PIT0)
 #endif
 #endif                         /* CONFIG_M5275 */
 
@@ -174,7 +188,7 @@
 #define CFG_SYS_NUM_IRQS               (128)
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@@ -183,6 +197,8 @@
 #define CFG_SYS_TMRINTR_PEND   (CFG_SYS_TMRINTR_MASK)
 #define CFG_SYS_TMRINTR_PRI            (0x1E)          /* Level must include inorder to work */
 #define CFG_SYS_TIMER_PRESCALER        (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE            (MMAP_PIT0)
 #endif
 #endif                         /* CONFIG_M5282 */
 
@@ -196,7 +212,7 @@
 #define CFG_SYS_NUM_IRQS             (64)
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE          (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE             (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG             (((volatile intctrl_t *) \
@@ -207,6 +223,8 @@
 #define CFG_SYS_TMRINTR_PRI          (MCFSIM_ICR_AUTOVEC | \
                                        MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
 #define CFG_SYS_TIMER_PRESCALER      (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE            (MMAP_PIT0)
 #endif
 #endif                          /* CONFIG_M5307 */
 
@@ -217,7 +235,7 @@
 #define CFG_SYS_UART_BASE              (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@@ -226,6 +244,8 @@
 #define CFG_SYS_TMRINTR_PEND           (CFG_SYS_TMRINTR_MASK)
 #define CFG_SYS_TMRINTR_PRI            (6)
 #define CFG_SYS_TIMER_PRESCALER        (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE            (MMAP_PIT0)
 #endif
 
 #define CFG_SYS_INTR_BASE              (MMAP_INTC0)
@@ -239,7 +259,7 @@
 #define CFG_SYS_UART_BASE              (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@@ -248,6 +268,8 @@
 #define CFG_SYS_TMRINTR_PEND   (CFG_SYS_TMRINTR_MASK)
 #define CFG_SYS_TMRINTR_PRI            (6)
 #define CFG_SYS_TIMER_PRESCALER        (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE            (MMAP_PIT0)
 #endif
 
 #define CFG_SYS_INTR_BASE              (MMAP_INTC0)
@@ -269,7 +291,7 @@
 #define MMAP_DSPI                      MMAP_DSPI0
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG     (((int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@@ -278,6 +300,8 @@
 #define CFG_SYS_TMRINTR_PEND           (CFG_SYS_TMRINTR_MASK)
 #define CFG_SYS_TMRINTR_PRI            (6)
 #define CFG_SYS_TIMER_PRESCALER        (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE            (MMAP_PIT0)
 #endif
 
 #define CFG_SYS_INTR_BASE              (MMAP_INTC0)

diff --git a/arch/m68k/lib/time.c b/arch/m68k/lib/time.c
index ca8c039..61db1e6 100644 (file)
--- a/arch/m68k/lib/time.c
+++ b/arch/m68k/lib/time.c
@@ -25,7 +25,7 @@ static volatile ulong timestamp = 0;
 #define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
 #endif
 
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
 #ifndef CFG_SYS_UDELAY_BASE
 #      error   "uDelay base not defined!"
 #endif
@@ -111,8 +111,6 @@ ulong get_timer(ulong base)
        return (timestamp - base);
 }
 
-#endif                         /* CFG_MCFTMR */
-
 /*
  * This function is derived from PowerPC code (read timebase as long long).
  * On M68K it just returns the timer value.
@@ -121,6 +119,40 @@ unsigned long long get_ticks(void)
 {
        return get_timer(0);
 }
+#else
+static u64 timer64 __section(".data");
+static u16 timer16 __section(".data");
+
+uint64_t __weak get_ticks(void)
+{
+       volatile pit_t *timerp = (pit_t *) (CFG_SYS_UDELAY_BASE);
+       u16 val = ~timerp->pcntr;
+
+       if (timer16 > val)
+               timer64 += 0xffff - timer16 + val;
+       else
+               timer64 += val - timer16;
+
+       timer16 = val;
+
+       return timer64;
+}
+
+/* PIT timer */
+int timer_init(void)
+{
+       volatile pit_t *timerp = (pit_t *) (CFG_SYS_UDELAY_BASE);
+
+       timer16 = 0;
+       timer64 = 0;
+
+       /* Set up PIT as timebase clock */
+       timerp->pmr = 0xffff;
+       timerp->pcsr = PIT_PCSR_EN | PIT_PCSR_OVW;
+
+       return 0;
+}
+#endif                         /* CONFIG_MCFTMR */
 
 unsigned long usec2ticks(unsigned long usec)
 {

diff --git a/arch/powerpc/dts/mpc8379erdb.dts b/arch/powerpc/dts/mpc8379erdb.dts
index 2e7c8f1..3db5ece 100644 (file)
--- a/arch/powerpc/dts/mpc8379erdb.dts
+++ b/arch/powerpc/dts/mpc8379erdb.dts
@@ -13,6 +13,11 @@
        #address-cells = <1>;
        #size-cells = <1>;
 
+       aliases {
+               serial0 = &serial0;
+               serial1 = &serial1;
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -60,6 +65,28 @@
                        clock-frequency = <0>;
                };
 
+               serial0: serial@4500 {
+                       cell-index = <0>;
+                       device_type = "serial";
+                       compatible = "fsl,ns16550", "ns16550";
+                       reg = <0x4500 0x100>;
+                       clock-frequency = <333333000>;
+                       interrupts = <9 0x8>;
+                       interrupt-parent = <&ipic>;
+                       bootph-all;
+               };
+
+               serial1: serial@4600 {
+                       cell-index = <1>;
+                       device_type = "serial";
+                       compatible = "fsl,ns16550", "ns16550";
+                       reg = <0x4600 0x100>;
+                       clock-frequency = <333333000>;
+                       interrupts = <10 0x8>;
+                       interrupt-parent = <&ipic>;
+                       bootph-all;
+               };
+
                ipic: interrupt-controller@700 {
                        compatible = "fsl,ipic";
                        interrupt-controller;

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 48ca4ff..f6ed059 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -24,6 +24,9 @@ config TARGET_SIFIVE_UNMATCHED
        bool "Support SiFive Unmatched Board"
        select SYS_CACHE_SHIFT_6
 
+config TARGET_STARFIVE_VISIONFIVE2
+       bool "Support StarFive VisionFive2 Board"
+
 config TARGET_SIPEED_MAIX
        bool "Support Sipeed Maix Board"
        select SYS_CACHE_SHIFT_6
@@ -65,12 +68,14 @@ source "board/sifive/unleashed/Kconfig"
 source "board/sifive/unmatched/Kconfig"
 source "board/openpiton/riscv64/Kconfig"
 source "board/sipeed/maix/Kconfig"
+source "board/starfive/visionfive2/Kconfig"
 
 # platform-specific options below
 source "arch/riscv/cpu/andesv5/Kconfig"
 source "arch/riscv/cpu/fu540/Kconfig"
 source "arch/riscv/cpu/fu740/Kconfig"
 source "arch/riscv/cpu/generic/Kconfig"
+source "arch/riscv/cpu/jh7110/Kconfig"
 
 # architecture-specific options below
 

diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk
index a8ed3fa..9cf2aef 100644 (file)
--- a/arch/riscv/config.mk
+++ b/arch/riscv/config.mk
@@ -16,16 +16,17 @@
 ifdef CONFIG_32BIT
 KBUILD_LDFLAGS         += -m $(32bit-emul)
 EFI_LDS                        := elf_riscv32_efi.lds
+PLATFORM_ELFFLAGS      += -B riscv -O elf32-littleriscv
 endif
 
 ifdef CONFIG_64BIT
 KBUILD_LDFLAGS         += -m $(64bit-emul)
 EFI_LDS                        := elf_riscv64_efi.lds
+PLATFORM_ELFFLAGS      += -B riscv -O elf64-littleriscv
 endif
 
 PLATFORM_CPPFLAGS      += -ffixed-gp -fpic
-PLATFORM_RELFLAGS      += -fno-common -gdwarf-2 -ffunction-sections \
-                          -fdata-sections
+PLATFORM_RELFLAGS      += -fno-common -ffunction-sections -fdata-sections
 LDFLAGS_u-boot         += --gc-sections -static -pie
 
 EFI_CRT0               := crt0_riscv_efi.o

diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig
new file mode 100644 (file)
index 0000000..3f14541
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/Kconfig
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+
+config STARFIVE_JH7110
+       bool
+       select ARCH_EARLY_INIT_R
+       select CLK_JH7110
+       select CPU
+       select CPU_RISCV
+       select RAM
+       select RESET_JH7110
+       select SUPPORT_SPL
+       select SPL_RAM if SPL
+       select SPL_STARFIVE_DDR
+       select PINCTRL_STARFIVE_JH7110
+       imply MMC
+       imply MMC_BROKEN_CD
+       imply MMC_SPI
+       imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+       imply SIFIVE_CACHE
+       imply SIFIVE_CCACHE
+       imply SMP
+       imply SPI
+       imply SPL_CPU
+       imply SPL_LOAD_FIT
+       imply SPL_OPENSBI
+       imply SPL_SIFIVE_CLINT

diff --git a/arch/riscv/cpu/jh7110/Makefile b/arch/riscv/cpu/jh7110/Makefile
new file mode 100644 (file)
index 0000000..951c956
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y += spl.o
+else
+obj-y += cpu.o
+obj-y += dram.o
+endif

diff --git a/arch/riscv/cpu/jh7110/cpu.c b/arch/riscv/cpu/jh7110/cpu.c
new file mode 100644 (file)
index 0000000..1d7c026
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/cpu.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ */
+
+#include <asm/cache.h>
+#include <irq_func.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+       disable_interrupts();
+
+       cache_flush();
+
+       return 0;
+}

diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c
new file mode 100644 (file)
index 0000000..2ad3f20
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/dram.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+       return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+       return fdtdec_setup_memory_banksize();
+}
+
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+{
+       /*
+        * Ensure that we run from first 4GB so that all
+        * addresses used by U-Boot are 32bit addresses.
+        *
+        * This in-turn ensures that 32bit DMA capable
+        * devices work fine because DMA mapping APIs will
+        * provide 32bit DMA addresses only.
+        */
+       if (IS_ENABLED(CONFIG_64BIT) && gd->ram_top > SZ_4G)
+               return SZ_4G;
+
+       return gd->ram_top;
+}

diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
new file mode 100644 (file)
index 0000000..104f0fe
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <asm/csr.h>
+#include <asm/sections.h>
+#include <dm.h>
+#include <log.h>
+
+#define CSR_U74_FEATURE_DISABLE        0x7c1
+#define L2_LIM_MEM_END 0x81FFFFFUL
+
+int spl_soc_init(void)
+{
+       int ret;
+       struct udevice *dev;
+
+       /* DDR init */
+       ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+       if (ret) {
+               debug("DRAM init failed: %d\n", ret);
+               return ret;
+       }
+
+       return 0;
+}
+
+void harts_early_init(void)
+{
+       ulong *ptr;
+       u8 *tmp;
+       ulong len, remain;
+       /*
+        * Feature Disable CSR
+        *
+        * Clear feature disable CSR to '0' to turn on all features for
+        * each core. This operation must be in M-mode.
+        */
+       if (CONFIG_IS_ENABLED(RISCV_MMODE))
+               csr_write(CSR_U74_FEATURE_DISABLE, 0);
+
+       /* clear L2 LIM  memory
+        * set __bss_end to 0x81FFFFF region to zero
+        * The L2 Cache Controller supports ECC. ECC is applied to SRAM.
+        * If it is not cleared, the ECC part is invalid, and an ECC error
+        * will be reported when reading data.
+        */
+       ptr = (ulong *)&__bss_end;
+       len = L2_LIM_MEM_END - (ulong)&__bss_end;
+       remain = len % sizeof(ulong);
+       len /= sizeof(ulong);
+
+       while (len--)
+               *ptr++ = 0;
+
+       /* clear the remain bytes */
+       if (remain) {
+               tmp = (u8 *)ptr;
+               while (remain--)
+                       *tmp++ = 0;
+       }
+}

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 4687bca..dad22bf 100644 (file)
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -250,9 +250,10 @@ spl_secondary_hart_stack_gd_setup:
 spl_call_board_init_r:
        mv      a0, zero
        mv      a1, zero
-       jal     board_init_r
+       j       board_init_r
 #endif
 
+#if !defined(CONFIG_SPL_BUILD)
 /*
  * void relocate_code(addr_sp, gd, addr_moni)
  *
@@ -283,9 +284,7 @@ stack_setup:
        beq     t0, s4, clear_bss       /* skip relocation */
 
        mv      t1, s4                  /* t1 <- scratch for copy_loop */
-       la      t3, __bss_start
-       sub     t3, t3, t0              /* t3 <- __bss_start_ofs */
-       add     t2, t0, t3              /* t2 <- source end address */
+       la      t2, __bss_start         /* t2 <- source end address */
 
 copy_loop:
        LREG    t5, 0(t0)
@@ -304,17 +303,12 @@ fix_rela_dyn:
        add     t1, t1, t6              /* t1 <- rela_dyn_start in RAM */
        add     t2, t2, t6              /* t2 <- rela_dyn_end in RAM */
 
-/*
- * skip first reserved entry: address, type, addend
- */
-       j       10f
-
 6:
-       LREG    t5, -(REGBYTES*2)(t1)   /* t5 <-- relocation info:type */
+       LREG    t5, REGBYTES(t1)        /* t5 <-- relocation info:type */
        li      t3, R_RISCV_RELATIVE    /* reloc type R_RISCV_RELATIVE */
        bne     t5, t3, 8f              /* skip non-RISCV_RELOC entries */
-       LREG    t3, -(REGBYTES*3)(t1)
-       LREG    t5, -(REGBYTES)(t1)     /* t5 <-- addend */
+       LREG    t3, 0(t1)
+       LREG    t5, (REGBYTES * 2)(t1)  /* t5 <-- addend */
        add     t5, t5, t6              /* t5 <-- location to fix up in RAM */
        add     t3, t3, t6              /* t3 <-- location to fix up in RAM */
        SREG    t5, 0(t3)
@@ -325,25 +319,24 @@ fix_rela_dyn:
        add     t4, t4, t6
 
 9:
-       LREG    t5, -(REGBYTES*2)(t1)   /* t5 <-- relocation info:type */
        srli    t0, t5, SYM_INDEX       /* t0 <--- sym table index */
        andi    t5, t5, 0xFF            /* t5 <--- relocation type */
        li      t3, RELOC_TYPE
        bne     t5, t3, 10f             /* skip non-addned entries */
 
-       LREG    t3, -(REGBYTES*3)(t1)
+       LREG    t3, 0(t1)
        li      t5, SYM_SIZE
        mul     t0, t0, t5
        add     s5, t4, t0
-       LREG    t0, -(REGBYTES)(t1)     /* t0 <-- addend */
+       LREG    t0, (REGBYTES * 2)(t1)  /* t0 <-- addend */
        LREG    t5, REGBYTES(s5)
        add     t5, t5, t0
        add     t5, t5, t6              /* t5 <-- location to fix up in RAM */
        add     t3, t3, t6              /* t3 <-- location to fix up in RAM */
        SREG    t5, 0(t3)
 10:
-       addi    t1, t1, (REGBYTES*3)
-       ble     t1, t2, 6b
+       addi    t1, t1, (REGBYTES * 3)
+       blt     t1, t2, 6b
 
 /*
  * trap update
@@ -408,6 +401,7 @@ call_board_init_r:
  * jump to it ...
  */
        jr      t4                      /* jump to board_init_r() */
+#endif /* !defined(CONFIG_SPL_BUILD) */
 
 #if CONFIG_IS_ENABLED(SMP)
 hart_out_of_bounds_loop:

diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
index 9935363..d1113a5 100644 (file)
--- a/arch/riscv/cpu/u-boot-spl.lds
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -32,14 +32,6 @@ SECTIONS
        } > .spl_mem
        . = ALIGN(4);
 
-       .got : {
-               __got_start = .;
-               *(.got.plt) *(.got)
-               __got_end = .;
-       } > .spl_mem
-
-       . = ALIGN(4);
-
        __u_boot_list : {
                KEEP(*(SORT(__u_boot_list*)));
        } > .spl_mem
@@ -52,24 +44,7 @@ SECTIONS
                __binman_sym_end = .;
        } > .spl_mem
 
-       . = ALIGN(4);
-
-       /DISCARD/ : { *(.rela.plt*) }
-       .rela.dyn : {
-               __rel_dyn_start = .;
-               *(.rela*)
-               __rel_dyn_end = .;
-       } > .spl_mem
-
-       . = ALIGN(4);
-
-       .dynsym : {
-               __dyn_sym_start = .;
-               *(.dynsym)
-               __dyn_sym_end = .;
-       } > .spl_mem
-
-       . = ALIGN(4);
+       . = ALIGN(8);
 
        _end = .;
        _image_binary_end = .;

diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds
index 1c937ae..15b5cbc 100644 (file)
--- a/arch/riscv/cpu/u-boot.lds
+++ b/arch/riscv/cpu/u-boot.lds
@@ -57,7 +57,7 @@ SECTIONS
                __efi_runtime_rel_stop = .;
        }
 
-       . = ALIGN(4);
+       . = ALIGN(8);
 
        /DISCARD/ : { *(.rela.plt*) }
        .rela.dyn : {
@@ -66,7 +66,7 @@ SECTIONS
                __rel_dyn_end = .;
        }
 
-       . = ALIGN(4);
+       . = ALIGN(8);
 
        .dynsym : {
                __dyn_sym_start = .;
@@ -74,7 +74,7 @@ SECTIONS
                __dyn_sym_end = .;
        }
 
-       . = ALIGN(4);
+       . = ALIGN(8);
 
        _end = .;
 

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index c576c55..79a5869 100644 (file)
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -7,7 +7,8 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb
 include $(srctree)/scripts/Makefile.dts
 
 targets += $(dtb-y)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
new file mode 100644 (file)
index 0000000..3c322c5
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include "binman.dtsi"
+#include "jh7110-u-boot.dtsi"
+/ {
+       chosen {
+               bootph-pre-ram;
+       };
+
+       firmware {
+               spi0 = &qspi;
+               bootph-pre-ram;
+       };
+
+       config {
+               bootph-pre-ram;
+               u-boot,spl-payload-offset = <0x100000>;
+       };
+
+       memory@40000000 {
+               bootph-pre-ram;
+       };
+};
+
+&uart0 {
+       bootph-pre-ram;
+};
+
+&mmc0 {
+       bootph-pre-ram;
+};
+
+&mmc1 {
+       bootph-pre-ram;
+};
+
+&qspi {
+       bootph-pre-ram;
+
+       nor-flash@0 {
+               bootph-pre-ram;
+       };
+};
+
+&sysgpio {
+       bootph-pre-ram;
+};
+
+&mmc0_pins {
+       bootph-pre-ram;
+       mmc0-pins-rest {
+               bootph-pre-ram;
+       };
+};
+
+&mmc1_pins {
+       bootph-pre-ram;
+       mmc1-pins0 {
+               bootph-pre-ram;
+       };
+
+       mmc1-pins1 {
+               bootph-pre-ram;
+       };
+};
+

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
new file mode 100644 (file)
index 0000000..b9d26d7
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+#include "jh7110-starfive-visionfive-2.dtsi"
+
+/ {
+       model = "StarFive VisionFive 2 v1.2A";
+       compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
+};

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
new file mode 100644 (file)
index 0000000..3c322c5
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include "binman.dtsi"
+#include "jh7110-u-boot.dtsi"
+/ {
+       chosen {
+               bootph-pre-ram;
+       };
+
+       firmware {
+               spi0 = &qspi;
+               bootph-pre-ram;
+       };
+
+       config {
+               bootph-pre-ram;
+               u-boot,spl-payload-offset = <0x100000>;
+       };
+
+       memory@40000000 {
+               bootph-pre-ram;
+       };
+};
+
+&uart0 {
+       bootph-pre-ram;
+};
+
+&mmc0 {
+       bootph-pre-ram;
+};
+
+&mmc1 {
+       bootph-pre-ram;
+};
+
+&qspi {
+       bootph-pre-ram;
+
+       nor-flash@0 {
+               bootph-pre-ram;
+       };
+};
+
+&sysgpio {
+       bootph-pre-ram;
+};
+
+&mmc0_pins {
+       bootph-pre-ram;
+       mmc0-pins-rest {
+               bootph-pre-ram;
+       };
+};
+
+&mmc1_pins {
+       bootph-pre-ram;
+       mmc1-pins0 {
+               bootph-pre-ram;
+       };
+
+       mmc1-pins1 {
+               bootph-pre-ram;
+       };
+};
+

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
new file mode 100644 (file)
index 0000000..3b3b345
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+#include "jh7110-starfive-visionfive-2.dtsi"
+
+/ {
+       model = "StarFive VisionFive 2 v1.3B";
+       compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
+};

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
new file mode 100644 (file)
index 0000000..c6b6dfa
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -0,0 +1,319 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "jh7110.dtsi"
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+/ {
+       aliases {
+               serial0 = &uart0;
+               spi0 = &qspi;
+               mmc0 = &mmc0;
+               mmc1 = &mmc1;
+               i2c0 = &i2c0;
+               i2c2 = &i2c2;
+               i2c5 = &i2c5;
+               i2c6 = &i2c6;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       cpus {
+               timebase-frequency = <4000000>;
+       };
+
+       memory@40000000 {
+               device_type = "memory";
+               reg = <0x0 0x40000000 0x2 0x0>;
+       };
+};
+
+&osc {
+       clock-frequency = <24000000>;
+};
+
+&rtc_osc {
+       clock-frequency = <32768>;
+};
+
+&gmac0_rmii_refin {
+       clock-frequency = <50000000>;
+};
+
+&gmac0_rgmii_rxin {
+       clock-frequency = <125000000>;
+};
+
+&gmac1_rmii_refin {
+       clock-frequency = <50000000>;
+};
+
+&gmac1_rgmii_rxin {
+       clock-frequency = <125000000>;
+};
+
+&i2stx_bclk_ext {
+       clock-frequency = <12288000>;
+};
+
+&i2stx_lrck_ext {
+       clock-frequency = <192000>;
+};
+
+&i2srx_bclk_ext {
+       clock-frequency = <12288000>;
+};
+
+&i2srx_lrck_ext {
+       clock-frequency = <192000>;
+};
+
+&tdm_ext {
+       clock-frequency = <49152000>;
+};
+
+&mclk_ext {
+       clock-frequency = <12288000>;
+};
+
+&uart0 {
+       reg-offset = <0>;
+       current-speed = <115200>;
+       clock-frequency = <24000000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_pins>;
+       status = "okay";
+};
+
+&i2c0 {
+       clock-frequency = <100000>;
+       i2c-sda-hold-time-ns = <300>;
+       i2c-sda-falling-time-ns = <510>;
+       i2c-scl-falling-time-ns = <510>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c0_pins>;
+       status = "okay";
+};
+
+&i2c2 {
+       clock-frequency = <100000>;
+       i2c-sda-hold-time-ns = <300>;
+       i2c-sda-falling-time-ns = <510>;
+       i2c-scl-falling-time-ns = <510>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c2_pins>;
+       status = "okay";
+};
+
+&i2c5 {
+       clock-frequency = <100000>;
+       i2c-sda-hold-time-ns = <300>;
+       i2c-sda-falling-time-ns = <510>;
+       i2c-scl-falling-time-ns = <510>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c5_pins>;
+       status = "okay";
+};
+
+&i2c6 {
+       clock-frequency = <100000>;
+       i2c-sda-hold-time-ns = <300>;
+       i2c-sda-falling-time-ns = <510>;
+       i2c-scl-falling-time-ns = <510>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c6_pins>;
+       status = "okay";
+};
+
+&sysgpio {
+       status = "okay";
+       uart0_pins: uart0-0 {
+               tx-pins {
+                       pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
+                                            GPOEN_ENABLE,
+                                            GPI_NONE)>;
+                       bias-disable;
+                       drive-strength = <12>;
+                       input-disable;
+                       input-schmitt-disable;
+                       slew-rate = <0>;
+               };
+
+               rx-pins {
+                       pinmux = <GPIOMUX(6, GPOUT_LOW,
+                                            GPOEN_DISABLE,
+                                            GPI_SYS_UART0_RX)>;
+                       bias-disable; /* external pull-up */
+                       drive-strength = <2>;
+                       input-enable;
+                       input-schmitt-enable;
+                       slew-rate = <0>;
+               };
+       };
+
+       i2c0_pins: i2c0-0 {
+               i2c-pins {
+                       pinmux = <GPIOMUX(57, GPOUT_LOW,
+                                             GPOEN_SYS_I2C0_CLK,
+                                             GPI_SYS_I2C0_CLK)>,
+                                <GPIOMUX(58, GPOUT_LOW,
+                                             GPOEN_SYS_I2C0_DATA,
+                                             GPI_SYS_I2C0_DATA)>;
+                       bias-disable; /* external pull-up */
+                       input-enable;
+                       input-schmitt-enable;
+               };
+       };
+
+       i2c2_pins: i2c2-0 {
+               i2c-pins {
+                       pinmux = <GPIOMUX(3, GPOUT_LOW,
+                                            GPOEN_SYS_I2C2_CLK,
+                                            GPI_SYS_I2C2_CLK)>,
+                                <GPIOMUX(2, GPOUT_LOW,
+                                            GPOEN_SYS_I2C2_DATA,
+                                            GPI_SYS_I2C2_DATA)>;
+                       bias-disable; /* external pull-up */
+                       input-enable;
+                       input-schmitt-enable;
+               };
+       };
+
+       i2c5_pins: i2c5-0 {
+               i2c-pins {
+                       pinmux = <GPIOMUX(19, GPOUT_LOW,
+                                             GPOEN_SYS_I2C5_CLK,
+                                             GPI_SYS_I2C5_CLK)>,
+                                <GPIOMUX(20, GPOUT_LOW,
+                                             GPOEN_SYS_I2C5_DATA,
+                                             GPI_SYS_I2C5_DATA)>;
+                       bias-disable; /* external pull-up */
+                       input-enable;
+                       input-schmitt-enable;
+               };
+       };
+
+       i2c6_pins: i2c6-0 {
+               i2c-pins {
+                       pinmux = <GPIOMUX(16, GPOUT_LOW,
+                                             GPOEN_SYS_I2C6_CLK,
+                                             GPI_SYS_I2C6_CLK)>,
+                                <GPIOMUX(17, GPOUT_LOW,
+                                             GPOEN_SYS_I2C6_DATA,
+                                             GPI_SYS_I2C6_DATA)>;
+                       bias-disable; /* external pull-up */
+                       input-enable;
+                       input-schmitt-enable;
+               };
+       };
+
+       mmc0_pins: mmc0-pins {
+                mmc0-pins-rest {
+                       pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+                                             GPOEN_ENABLE, GPI_NONE)>;
+                       bias-pull-up;
+                       drive-strength = <12>;
+                       input-disable;
+                       input-schmitt-disable;
+                       slew-rate = <0>;
+               };
+       };
+
+       mmc1_pins: mmc1-pins {
+               mmc1-pins0 {
+                       pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
+                                             GPOEN_ENABLE, GPI_NONE)>;
+                       bias-pull-up;
+                       drive-strength = <12>;
+                       input-disable;
+                       input-schmitt-disable;
+                       slew-rate = <0>;
+               };
+
+               mmc1-pins1 {
+                       pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
+                                            GPOEN_SYS_SDIO1_CMD, GPI_SYS_SDIO1_CMD)>,
+                               <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
+                                            GPOEN_SYS_SDIO1_DATA0, GPI_SYS_SDIO1_DATA0)>,
+                               <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
+                                            GPOEN_SYS_SDIO1_DATA1, GPI_SYS_SDIO1_DATA1)>,
+                               <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
+                                            GPOEN_SYS_SDIO1_DATA2, GPI_SYS_SDIO1_DATA2)>,
+                               <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
+                                            GPOEN_SYS_SDIO1_DATA3, GPI_SYS_SDIO1_DATA3)>;
+                       bias-pull-up;
+                       drive-strength = <12>;
+                       input-enable;
+                       input-schmitt-enable;
+                       slew-rate = <0>;
+               };
+       };
+};
+
+&mmc0 {
+       compatible = "snps,dw-mshc";
+       max-frequency = <100000000>;
+       bus-width = <8>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&mmc0_pins>;
+       cap-mmc-highspeed;
+       mmc-ddr-1_8v;
+       mmc-hs200-1_8v;
+       non-removable;
+       cap-mmc-hw-reset;
+       post-power-on-delay-ms = <200>;
+       status = "okay";
+
+};
+
+&mmc1 {
+       compatible = "snps,dw-mshc";
+       max-frequency = <100000000>;
+       bus-width = <4>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&mmc1_pins>;
+       no-sdio;
+       no-mmc;
+       broken-cd;
+       cap-sd-highspeed;
+       post-power-on-delay-ms = <200>;
+       status = "okay";
+};
+
+&qspi {
+       spi-max-frequency = <250000000>;
+       status = "okay";
+
+       nor-flash@0 {
+               compatible = "jedec,spi-nor";
+               reg=<0>;
+               spi-max-frequency = <100000000>;
+               cdns,tshsl-ns = <1>;
+               cdns,tsd2d-ns = <1>;
+               cdns,tchsh-ns = <1>;
+               cdns,tslch-ns = <1>;
+       };
+};
+
+&syscrg {
+       assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
+                         <&syscrg JH7110_SYSCLK_BUS_ROOT>,
+                         <&syscrg JH7110_SYSCLK_PERH_ROOT>,
+                         <&syscrg JH7110_SYSCLK_QSPI_REF>;
+       assigned-clock-parents = <&syscrg JH7110_SYSCLK_PLL0_OUT>,
+                                <&syscrg JH7110_SYSCLK_PLL2_OUT>,
+                                <&syscrg JH7110_SYSCLK_PLL2_OUT>,
+                                <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
+       assigned-clock-rates = <0>, <0>, <0>, <0>;
+};
+
+&aoncrg {
+       assigned-clocks = <&aoncrg JH7110_AONCLK_APB_FUNC>;
+       assigned-clock-parents = <&osc>;
+       assigned-clock-rates = <0>;
+};

diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
new file mode 100644 (file)
index 0000000..c221195
--- /dev/null
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+/ {
+       cpus: cpus {
+               bootph-pre-ram;
+
+               S7_0: cpu@0 {
+                       bootph-pre-ram;
+                       status = "okay";
+                       cpu0_intc: interrupt-controller {
+                               bootph-pre-ram;
+                       };
+               };
+
+               U74_1: cpu@1 {
+                       bootph-pre-ram;
+                       cpu1_intc: interrupt-controller {
+                               bootph-pre-ram;
+                       };
+               };
+
+               U74_2: cpu@2 {
+                       bootph-pre-ram;
+                       cpu2_intc: interrupt-controller {
+                               bootph-pre-ram;
+                       };
+               };
+
+               U74_3: cpu@3 {
+                       bootph-pre-ram;
+                       cpu3_intc: interrupt-controller {
+                               bootph-pre-ram;
+                       };
+               };
+
+               U74_4: cpu@4 {
+                       bootph-pre-ram;
+                       cpu4_intc: interrupt-controller {
+                               bootph-pre-ram;
+                       };
+               };
+       };
+
+       soc {
+               bootph-pre-ram;
+
+               clint: timer@2000000 {
+                       bootph-pre-ram;
+               };
+
+               dmc: dmc@15700000 {
+                       bootph-pre-ram;
+                       compatible = "starfive,jh7110-dmc";
+                       reg = <0x0 0x15700000 0x0 0x10000>,
+                               <0x0 0x13000000 0x0 0x10000>;
+                       resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+                               <&syscrg JH7110_SYSRST_DDR_OSC>,
+                               <&syscrg JH7110_SYSRST_DDR_APB>;
+                       reset-names = "axi", "osc", "apb";
+                       clocks = <&syscrg JH7110_SYSCLK_PLL1_OUT>;
+                       clock-names = "pll1_out";
+                       clock-frequency = <2133>;
+               };
+       };
+};
+
+&osc {
+       bootph-pre-ram;
+};
+
+&gmac0_rmii_refin {
+       bootph-pre-ram;
+};
+
+&aoncrg {
+       bootph-pre-ram;
+};
+
+&syscrg {
+       bootph-pre-ram;
+       starfive,sys-syscon = <&sys_syscon>;
+};
+
+&stgcrg {
+       bootph-pre-ram;
+};
+
+&sys_syscon {
+       bootph-pre-ram;
+};
+
+&S7_0 {
+       status = "okay";
+};

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
new file mode 100644 (file)
index 0000000..bd60879
--- /dev/null
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -0,0 +1,573 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+#include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+/ {
+       compatible = "starfive,jh7110";
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               S7_0: cpu@0 {
+                       compatible = "sifive,s7", "riscv";
+                       reg = <0>;
+                       device_type = "cpu";
+                       i-cache-block-size = <64>;
+                       i-cache-sets = <64>;
+                       i-cache-size = <16384>;
+                       next-level-cache = <&ccache>;
+                       riscv,isa = "rv64imac_zba_zbb";
+                       status = "disabled";
+
+                       cpu0_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               U74_1: cpu@1 {
+                       compatible = "sifive,u74-mc", "riscv";
+                       reg = <1>;
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <64>;
+                       d-cache-size = <32768>;
+                       d-tlb-sets = <1>;
+                       d-tlb-size = <40>;
+                       device_type = "cpu";
+                       i-cache-block-size = <64>;
+                       i-cache-sets = <64>;
+                       i-cache-size = <32768>;
+                       i-tlb-sets = <1>;
+                       i-tlb-size = <40>;
+                       mmu-type = "riscv,sv39";
+                       next-level-cache = <&ccache>;
+                       riscv,isa = "rv64imafdc_zba_zbb";
+                       tlb-split;
+
+                       cpu1_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               U74_2: cpu@2 {
+                       compatible = "sifive,u74-mc", "riscv";
+                       reg = <2>;
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <64>;
+                       d-cache-size = <32768>;
+                       d-tlb-sets = <1>;
+                       d-tlb-size = <40>;
+                       device_type = "cpu";
+                       i-cache-block-size = <64>;
+                       i-cache-sets = <64>;
+                       i-cache-size = <32768>;
+                       i-tlb-sets = <1>;
+                       i-tlb-size = <40>;
+                       mmu-type = "riscv,sv39";
+                       next-level-cache = <&ccache>;
+                       riscv,isa = "rv64imafdc_zba_zbb";
+                       tlb-split;
+
+                       cpu2_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               U74_3: cpu@3 {
+                       compatible = "sifive,u74-mc", "riscv";
+                       reg = <3>;
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <64>;
+                       d-cache-size = <32768>;
+                       d-tlb-sets = <1>;
+                       d-tlb-size = <40>;
+                       device_type = "cpu";
+                       i-cache-block-size = <64>;
+                       i-cache-sets = <64>;
+                       i-cache-size = <32768>;
+                       i-tlb-sets = <1>;
+                       i-tlb-size = <40>;
+                       mmu-type = "riscv,sv39";
+                       next-level-cache = <&ccache>;
+                       riscv,isa = "rv64imafdc_zba_zbb";
+                       tlb-split;
+
+                       cpu3_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               U74_4: cpu@4 {
+                       compatible = "sifive,u74-mc", "riscv";
+                       reg = <4>;
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <64>;
+                       d-cache-size = <32768>;
+                       d-tlb-sets = <1>;
+                       d-tlb-size = <40>;
+                       device_type = "cpu";
+                       i-cache-block-size = <64>;
+                       i-cache-sets = <64>;
+                       i-cache-size = <32768>;
+                       i-tlb-sets = <1>;
+                       i-tlb-size = <40>;
+                       mmu-type = "riscv,sv39";
+                       next-level-cache = <&ccache>;
+                       riscv,isa = "rv64imafdc_zba_zbb";
+                       tlb-split;
+
+                       cpu4_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu-map {
+                       cluster0 {
+                               core0 {
+                                       cpu = <&S7_0>;
+                               };
+
+                               core1 {
+                                       cpu = <&U74_1>;
+                               };
+
+                               core2 {
+                                       cpu = <&U74_2>;
+                               };
+
+                               core3 {
+                                       cpu = <&U74_3>;
+                               };
+
+                               core4 {
+                                       cpu = <&U74_4>;
+                               };
+                       };
+               };
+       };
+
+       osc: oscillator {
+               compatible = "fixed-clock";
+               clock-output-names = "osc";
+               #clock-cells = <0>;
+       };
+
+       rtc_osc: rtc-oscillator {
+               compatible = "fixed-clock";
+               clock-output-names = "rtc_osc";
+               #clock-cells = <0>;
+       };
+
+       gmac0_rmii_refin: gmac0-rmii-refin-clock {
+               compatible = "fixed-clock";
+               clock-output-names = "gmac0_rmii_refin";
+               #clock-cells = <0>;
+       };
+
+       gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
+               compatible = "fixed-clock";
+               clock-output-names = "gmac0_rgmii_rxin";
+               #clock-cells = <0>;
+       };
+
+       gmac1_rmii_refin: gmac1-rmii-refin-clock {
+               compatible = "fixed-clock";
+               clock-output-names = "gmac1_rmii_refin";
+               #clock-cells = <0>;
+       };
+
+       gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
+               compatible = "fixed-clock";
+               clock-output-names = "gmac1_rgmii_rxin";
+               #clock-cells = <0>;
+       };
+
+       i2stx_bclk_ext: i2stx-bclk-ext-clock {
+               compatible = "fixed-clock";
+               clock-output-names = "i2stx_bclk_ext";
+               #clock-cells = <0>;
+       };
+
+       i2stx_lrck_ext: i2stx-lrck-ext-clock {
+               compatible = "fixed-clock";
+               clock-output-names = "i2stx_lrck_ext";
+               #clock-cells = <0>;
+       };
+
+       i2srx_bclk_ext: i2srx-bclk-ext-clock {
+               compatible = "fixed-clock";
+               clock-output-names = "i2srx_bclk_ext";
+               #clock-cells = <0>;
+       };
+
+       i2srx_lrck_ext: i2srx-lrck-ext-clock {
+               compatible = "fixed-clock";
+               clock-output-names = "i2srx_lrck_ext";
+               #clock-cells = <0>;
+       };
+
+       tdm_ext: tdm-ext-clock {
+               compatible = "fixed-clock";
+               clock-output-names = "tdm_ext";
+               #clock-cells = <0>;
+       };
+
+       mclk_ext: mclk-ext-clock {
+               compatible = "fixed-clock";
+               clock-output-names = "mclk_ext";
+               #clock-cells = <0>;
+       };
+
+       soc {
+               compatible = "simple-bus";
+               interrupt-parent = <&plic>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               clint: timer@2000000 {
+                       compatible = "starfive,jh7110-clint", "sifive,clint0";
+                       reg = <0x0 0x2000000 0x0 0x10000>;
+                       interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+                                             <&cpu1_intc 3>, <&cpu1_intc 7>,
+                                             <&cpu2_intc 3>, <&cpu2_intc 7>,
+                                             <&cpu3_intc 3>, <&cpu3_intc 7>,
+                                             <&cpu4_intc 3>, <&cpu4_intc 7>;
+               };
+
+               plic: interrupt-controller@c000000 {
+                       compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
+                       reg = <0x0 0xc000000 0x0 0x4000000>;
+                       interrupts-extended = <&cpu0_intc 11>,
+                                             <&cpu1_intc 11>, <&cpu1_intc 9>,
+                                             <&cpu2_intc 11>, <&cpu2_intc 9>,
+                                             <&cpu3_intc 11>, <&cpu3_intc 9>,
+                                             <&cpu4_intc 11>, <&cpu4_intc 9>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       #address-cells = <0>;
+                       riscv,ndev = <136>;
+               };
+
+               ccache: cache-controller@2010000 {
+                       compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
+                       reg = <0x0 0x2010000 0x0 0x4000>;
+                       interrupts = <1>, <3>, <4>, <2>;
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-sets = <2048>;
+                       cache-size = <2097152>;
+                       cache-unified;
+               };
+
+               uart0: serial@10000000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x10000000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
+                                <&syscrg JH7110_SYSCLK_UART0_APB>;
+                       clock-names = "baudclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_UART0_APB>,
+                                <&syscrg JH7110_SYSRST_UART0_CORE>;
+                       interrupts = <32>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       status = "disabled";
+               };
+
+               uart1: serial@10010000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x10010000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
+                                <&syscrg JH7110_SYSCLK_UART1_APB>;
+                       clock-names = "baudclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_UART1_APB>,
+                                <&syscrg JH7110_SYSRST_UART1_CORE>;
+                       interrupts = <33>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       status = "disabled";
+               };
+
+               uart2: serial@10020000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x10020000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
+                                <&syscrg JH7110_SYSCLK_UART2_APB>;
+                       clock-names = "baudclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_UART2_APB>,
+                                <&syscrg JH7110_SYSRST_UART2_CORE>;
+                       interrupts = <34>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       status = "disabled";
+               };
+
+               i2c0: i2c@10030000 {
+                       compatible = "snps,designware-i2c";
+                       reg = <0x0 0x10030000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
+                       clock-names = "ref";
+                       resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
+                       interrupts = <35>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c1: i2c@10040000 {
+                       compatible = "snps,designware-i2c";
+                       reg = <0x0 0x10040000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
+                       clock-names = "ref";
+                       resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
+                       interrupts = <36>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c2: i2c@10050000 {
+                       compatible = "snps,designware-i2c";
+                       reg = <0x0 0x10050000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
+                       clock-names = "ref";
+                       resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
+                       interrupts = <37>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               stgcrg: clock-controller@10230000 {
+                       compatible = "starfive,jh7110-stgcrg";
+                       reg = <0x0 0x10230000 0x0 0x10000>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
+               stg_syscon: stg_syscon@10240000 {
+                       compatible = "starfive,jh7110-stg-syscon","syscon";
+                       reg = <0x0 0x10240000 0x0 0x1000>;
+               };
+
+               uart3: serial@12000000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x12000000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
+                                <&syscrg JH7110_SYSCLK_UART3_APB>;
+                       clock-names = "baudclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_UART3_APB>,
+                                <&syscrg JH7110_SYSRST_UART3_CORE>;
+                       interrupts = <45>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       status = "disabled";
+               };
+
+               uart4: serial@12010000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x12010000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
+                                <&syscrg JH7110_SYSCLK_UART4_APB>;
+                       clock-names = "baudclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_UART4_APB>,
+                                <&syscrg JH7110_SYSRST_UART4_CORE>;
+                       interrupts = <46>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       status = "disabled";
+               };
+
+               uart5: serial@12020000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x12020000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
+                                <&syscrg JH7110_SYSCLK_UART5_APB>;
+                       clock-names = "baudclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_UART5_APB>,
+                                <&syscrg JH7110_SYSRST_UART5_CORE>;
+                       interrupts = <47>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       status = "disabled";
+               };
+
+               i2c3: i2c@12030000 {
+                       compatible = "snps,designware-i2c";
+                       reg = <0x0 0x12030000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
+                       clock-names = "ref";
+                       resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
+                       interrupts = <48>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c4: i2c@12040000 {
+                       compatible = "snps,designware-i2c";
+                       reg = <0x0 0x12040000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
+                       clock-names = "ref";
+                       resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
+                       interrupts = <49>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c5: i2c@12050000 {
+                       compatible = "snps,designware-i2c";
+                       reg = <0x0 0x12050000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
+                       clock-names = "ref";
+                       resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
+                       interrupts = <50>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c6: i2c@12060000 {
+                       compatible = "snps,designware-i2c";
+                       reg = <0x0 0x12060000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
+                       clock-names = "ref";
+                       resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
+                       interrupts = <51>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               qspi: spi@13010000 {
+                       compatible = "cdns,qspi-nor";
+                       reg = <0x0 0x13010000 0x0 0x10000
+                               0x0 0x21000000 0x0 0x400000>;
+                       clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>;
+                       clock-names = "clk_ref";
+                       resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
+                                <&syscrg JH7110_SYSRST_QSPI_AHB>,
+                                <&syscrg JH7110_SYSRST_QSPI_REF>;
+                       reset-names = "rst_apb", "rst_ahb", "rst_ref";
+                       cdns,fifo-depth = <256>;
+                       cdns,fifo-width = <4>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               syscrg: clock-controller@13020000 {
+                       compatible = "starfive,jh7110-syscrg";
+                       reg = <0x0 0x13020000 0x0 0x10000>;
+                       clocks = <&osc>, <&gmac1_rmii_refin>,
+                                <&gmac1_rgmii_rxin>,
+                                <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+                                <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+                                <&tdm_ext>, <&mclk_ext>;
+                       clock-names = "osc", "gmac1_rmii_refin",
+                                     "gmac1_rgmii_rxin",
+                                     "i2stx_bclk_ext", "i2stx_lrck_ext",
+                                     "i2srx_bclk_ext", "i2srx_lrck_ext",
+                                     "tdm_ext", "mclk_ext";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
+               sys_syscon: sys_syscon@13030000 {
+                       compatible = "starfive,jh7110-sys-syscon","syscon";
+                       reg = <0x0 0x13030000 0x0 0x1000>;
+               };
+
+               sysgpio: pinctrl@13040000 {
+                       compatible = "starfive,jh7110-sys-pinctrl";
+                       reg = <0x0 0x13040000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
+                       resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
+                       interrupts = <86>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               mmc0: mmc@16010000 {
+                       compatible = "starfive,jh7110-mmc";
+                       reg = <0x0 0x16010000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
+                                <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
+                       clock-names = "biu", "ciu";
+                       resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
+                       reset-names = "reset";
+                       interrupts = <74>;
+                       fifo-depth = <32>;
+                       fifo-watermark-aligned;
+                       data-addr = <0>;
+                       starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
+                       status = "disabled";
+               };
+
+               mmc1: mmc@16020000 {
+                       compatible = "starfive,jh7110-mmc";
+                       reg = <0x0 0x16020000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
+                                <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
+                       clock-names = "biu", "ciu";
+                       resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
+                       reset-names = "reset";
+                       interrupts = <75>;
+                       fifo-depth = <32>;
+                       fifo-watermark-aligned;
+                       data-addr = <0>;
+                       starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
+                       status = "disabled";
+               };
+
+               aoncrg: clock-controller@17000000 {
+                       compatible = "starfive,jh7110-aoncrg";
+                       reg = <0x0 0x17000000 0x0 0x10000>;
+                       clocks = <&osc>, <&rtc_osc>,
+                                <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
+                                <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
+                                <&syscrg JH7110_SYSCLK_APB_BUS>,
+                                <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>;
+                       clock-names = "osc", "rtc_osc", "gmac0_rmii_refin",
+                                     "gmac0_rgmii_rxin", "stg_axiahb",
+                                     "apb_bus", "gmac0_gtxclk";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
+               aon_syscon: aon_syscon@17010000 {
+                       compatible = "starfive,jh7110-aon-syscon","syscon";
+                       reg = <0x0 0x17010000 0x0 0x1000>;
+               };
+
+               aongpio: pinctrl@17020000 {
+                       compatible = "starfive,jh7110-aon-pinctrl";
+                       reg = <0x0 0x17020000 0x0 0x10000>;
+                       resets = <&aoncrg JH7110_AONRST_IOMUX>;
+                       interrupts = <85>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+       };
+};

diff --git a/arch/riscv/include/asm/arch-jh7110/regs.h b/arch/riscv/include/asm/arch-jh7110/regs.h
new file mode 100644 (file)
index 0000000..0502687
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7110/regs.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ */
+
+#ifndef __STARFIVE_JH7110_REGS_H
+#define __STARFIVE_JH7110_REGS_H
+
+#define JH7110_SYS_CRG                 0x13020000
+#define JH7110_SYS_SYSCON              0x13030000
+#define JH7110_SYS_IOMUX               0x13040000
+#define JH7110_AON_CRG                 0x17000000
+#define JH7110_AON_SYSCON              0x17010000
+
+#define JH7110_BOOT_MODE_SELECT_REG    0x1702002c
+#define JH7110_BOOT_MODE_SELECT_MASK   GENMASK(1, 0)
+
+#endif /* __STARFIVE_JH7110_REGS_H */

diff --git a/arch/riscv/include/asm/arch-jh7110/spl.h b/arch/riscv/include/asm/arch-jh7110/spl.h
new file mode 100644 (file)
index 0000000..23ce887
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7110/spl.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ */
+
+#ifndef _SPL_STARFIVE_H
+#define _SPL_STARFIVE_H
+
+int spl_soc_init(void);
+
+#endif /* _SPL_STARFIVE_H */

diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index 220266e..b16e6df 100644 (file)
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -180,7 +180,7 @@ static inline u64 readq(const volatile void __iomem *addr)
  *  IO port access primitives
  *  -------------------------
  *
- * The NDS32 doesn't have special IO access instructions just like ARM;
+ * The RISC-V doesn't have special IO access instructions just like ARM;
  * all IO is memory mapped.
  * Note that these are defined to perform little endian accesses
  * only.  Their primary purpose is to access PCI and ISA peripherals.

diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c
index 636d354..5149633 100644 (file)
--- a/arch/sandbox/cpu/cpu.c
+++ b/arch/sandbox/cpu/cpu.c
@@ -31,7 +31,7 @@ static struct udevice *map_dev;
 unsigned long map_len;
 #endif
 
-void sandbox_exit(void)
+void __noreturn sandbox_exit(void)
 {
        /* Do this here while it still has an effect */
        os_fd_restore();
@@ -230,7 +230,7 @@ phys_addr_t map_to_sysmem(const void *ptr)
        return mentry->tag;
 }
 
-unsigned int sandbox_read(const void *addr, enum sandboxio_size_t size)
+unsigned long sandbox_read(const void *addr, enum sandboxio_size_t size)
 {
        struct sandbox_state *state = state_get_current();
 

diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 5e66304..9e93a0f 100644 (file)
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -166,7 +166,7 @@ int os_write_file(const char *fname, const void *buf, int size)
        return 0;
 }
 
-int os_filesize(int fd)
+off_t os_filesize(int fd)
 {
        off_t size;
 
@@ -218,7 +218,7 @@ err:
 int os_map_file(const char *pathname, int os_flags, void **bufp, int *sizep)
 {
        void *ptr;
-       int size;
+       off_t size;
        int ifd;
 
        ifd = os_open(pathname, os_flags);
@@ -231,6 +231,10 @@ int os_map_file(const char *pathname, int os_flags, void **bufp, int *sizep)
                printf("Cannot get file size of '%s'\n", pathname);
                return -EIO;
        }
+       if ((unsigned long long)size > (unsigned long long)SIZE_MAX) {
+               printf("File '%s' too large to map\n", pathname);
+               return -EIO;
+       }
 
        ptr = mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, ifd, 0);
        if (ptr == MAP_FAILED) {

diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index 69da378..d678349 100644 (file)
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -10,6 +10,7 @@
 #include <fdtdec.h>
 #include <log.h>
 #include <os.h>
+#include <trace.h>
 #include <asm/malloc.h>
 #include <asm/state.h>
 #include <asm/test.h>
@@ -525,6 +526,10 @@ int state_uninit(void)
        if (state->jumped_fname)
                os_unlink(state->jumped_fname);
 
+       /* Disable tracing before unmapping RAM */
+       if (IS_ENABLED(CONFIG_TRACE))
+               trace_set_enabled(0);
+
        os_free(state->state_fdt);
        os_free(state->ram_buf);
        memset(state, '\0', sizeof(*state));

diff --git a/arch/sandbox/dts/sandbox64.dts b/arch/sandbox/dts/sandbox64.dts
index f21fc18..1953655 100644 (file)
--- a/arch/sandbox/dts/sandbox64.dts
+++ b/arch/sandbox/dts/sandbox64.dts
@@ -89,6 +89,19 @@
                cs-gpios = <0>, <&gpio_a 0>;
        };
 
+       nvmxip-qspi1@08000000 {
+               compatible = "nvmxip,qspi";
+               reg = /bits/ 64 <0x08000000 0x00200000>;
+               lba_shift = <9>;
+               lba = <4096>;
+       };
+
+       nvmxip-qspi2@08200000 {
+               compatible = "nvmxip,qspi";
+               reg = /bits/ 64 <0x08200000 0x00100000>;
+               lba_shift = <9>;
+               lba = <2048>;
+       };
 };
 
 #include "sandbox.dtsi"

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index d72d7a5..bcdea0b 100644 (file)
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -129,7 +129,7 @@
                        status = "disabled";
                        compatible = "fwupd,vbe-simple";
                        storage = "mmc3";
-                       skip-offset = <0x400000>;
+                       skip-offset = <0x800000>;
                        area-start = <0>;
                        area-size = <0xe00000>;
                        state-offset = <0xdffc00>;
@@ -1802,6 +1802,20 @@
                compatible = "u-boot,fwu-mdata-gpt";
                fwu-mdata-store = <&mmc0>;
        };
+
+       nvmxip-qspi1@08000000 {
+               compatible = "nvmxip,qspi";
+               reg = <0x08000000 0x00200000>;
+               lba_shift = <9>;
+               lba = <4096>;
+       };
+
+       nvmxip-qspi2@08200000 {
+               compatible = "nvmxip,qspi";
+               reg = <0x08200000 0x00100000>;
+               lba_shift = <9>;
+               lba = <2048>;
+       };
 };
 
 #include "sandbox_pmic.dtsi"

diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h
index ad6c29a..31ab728 100644 (file)
--- a/arch/sandbox/include/asm/io.h
+++ b/arch/sandbox/include/asm/io.h
@@ -45,7 +45,7 @@ static inline void unmap_sysmem(const void *vaddr)
 /* Map from a pointer to our RAM buffer */
 phys_addr_t map_to_sysmem(const void *ptr);
 
-unsigned int sandbox_read(const void *addr, enum sandboxio_size_t size);
+unsigned long sandbox_read(const void *addr, enum sandboxio_size_t size);
 void sandbox_write(void *addr, unsigned int val, enum sandboxio_size_t size);
 
 #define readb(addr) sandbox_read((const void *)addr, SB_SIZE_8)

diff --git a/arch/sandbox/include/asm/posix_types.h b/arch/sandbox/include/asm/posix_types.h
index ec18ed7..e1442c4 100644 (file)
--- a/arch/sandbox/include/asm/posix_types.h
+++ b/arch/sandbox/include/asm/posix_types.h
@@ -1,5 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
- *  linux/include/asm-arm/posix_types.h
+ * Based on linux/include/asm-arm/posix_types.h
  *
  *  Copyright (C) 1996-1998 Russell King.
  *
@@ -10,8 +11,8 @@
  *  Changelog:
  *   27-06-1996        RMK     Created
  */
-#ifndef __ARCH_ARM_POSIX_TYPES_H
-#define __ARCH_ARM_POSIX_TYPES_H
+#ifndef __ARCH_SANDBOX_POSIX_TYPES_H
+#define __ARCH_SANDBOX_POSIX_TYPES_H
 
 /*
  * This file is generally used by user-level software, so you need to

diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h
index 4853dc9..e482271 100644 (file)
--- a/arch/sandbox/include/asm/test.h
+++ b/arch/sandbox/include/asm/test.h
@@ -300,6 +300,7 @@ void sandbox_cros_ec_set_test_flags(struct udevice *dev, uint flags);
  */
 int sandbox_cros_ec_get_pwm_duty(struct udevice *dev, uint index, uint *duty);
 
+#if IS_ENABLED(CONFIG_SANDBOX_SDL)
 /**
  * sandbox_sdl_set_bpp() - Set the depth of the sandbox display
  *
@@ -315,6 +316,13 @@ int sandbox_cros_ec_get_pwm_duty(struct udevice *dev, uint index, uint *duty);
  * after the change
  */
 int sandbox_sdl_set_bpp(struct udevice *dev, enum video_log2_bpp l2bpp);
+#else
+static inline int sandbox_sdl_set_bpp(struct udevice *dev,
+                                     enum video_log2_bpp l2bpp)
+{
+       return -ENOSYS;
+}
+#endif
 
 /**
  * sandbox_set_fake_efi_mgr_dev() - Control EFI bootmgr producing valid bootflow

diff --git a/arch/sandbox/include/asm/u-boot-sandbox.h b/arch/sandbox/include/asm/u-boot-sandbox.h
index 9eb1932..e702774 100644 (file)
--- a/arch/sandbox/include/asm/u-boot-sandbox.h
+++ b/arch/sandbox/include/asm/u-boot-sandbox.h
@@ -87,6 +87,6 @@ void sandbox_set_enable_pci_map(int enable);
 void sandbox_reset(void);
 
 /* Exit sandbox (quit U-Boot) */
-void sandbox_exit(void);
+void __noreturn sandbox_exit(void);
 
 #endif /* _U_BOOT_SANDBOX_H_ */

diff --git a/bin/travis-ci/conf.M5208EVBE_qemu b/bin/travis-ci/conf.M5208EVBE_qemu
new file mode 100644 (file)
index 0000000..947f13c
--- /dev/null
+++ b/bin/travis-ci/conf.M5208EVBE_qemu
@@ -0,0 +1,27 @@
+# Copyright (c) 2023 Marek Vasut <marek.vasut+renesas@mailbox.org>
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+console_impl=qemu
+qemu_machine="mcf5208evb"
+qemu_binary="qemu-system-m68k"
+qemu_extra_args="-nographic -serial mon:stdio -net user,tftp=${UBOOT_TRAVIS_BUILD_DIR} -net nic,model=mcf-fec"
+qemu_kernel_args="-bios ${U_BOOT_BUILD_DIR}/u-boot.bin"
+reset_impl=none
+flash_impl=none

diff --git a/board/amlogic/beelink-s922x/MAINTAINERS b/board/amlogic/beelink-s922x/MAINTAINERS
index 47b6227..8dddeb9 100644 (file)
--- a/board/amlogic/beelink-s922x/MAINTAINERS
+++ b/board/amlogic/beelink-s922x/MAINTAINERS
@@ -3,8 +3,9 @@ M:      Christian Hewitt <christianshewitt@gmail.com>
 S:     Maintained
 L:     u-boot-amlogic@groups.io
 F:     board/amlogic/beelink-s922x/
+F:     configs/beelink-gsking-x_defconfig
 F:     configs/beelink-gtking_defconfig
 F:     configs/beelink-gtkingpro_defconfig
-F:     configs/beelink-gsking-x_defconfig
+F:     doc/board/amlogic/beelink-gskingx.rst
 F:     doc/board/amlogic/beelink-gtking.rst
 F:     doc/board/amlogic/beelink-gtkingpro.rst

diff --git a/board/amlogic/p200/MAINTAINERS b/board/amlogic/p200/MAINTAINERS
index 33ca3df..fe451dd 100644 (file)
--- a/board/amlogic/p200/MAINTAINERS
+++ b/board/amlogic/p200/MAINTAINERS
@@ -7,6 +7,10 @@ F:     board/amlogic/p200/
 F:     configs/nanopi-k2_defconfig
 F:     configs/odroid-c2_defconfig
 F:     configs/p200_defconfig
+F:     configs/wetek-hub_defconfig
+F:     configs/wetek-play2_defconfig
 F:     doc/board/amlogic/p200.rst
 F:     doc/board/amlogic/nanopi-k2.rst
 F:     doc/board/amlogic/odroid-c2.rst
+F:      doc/board/amlogic/wetek-hub.rst
+F:      doc/board/amlogic/wetek-play2.rst

diff --git a/board/amlogic/q200/MAINTAINERS b/board/amlogic/q200/MAINTAINERS
index 9c84cca..aece8d5 100644 (file)
--- a/board/amlogic/q200/MAINTAINERS
+++ b/board/amlogic/q200/MAINTAINERS
@@ -4,9 +4,11 @@ S:     Maintained
 L:     u-boot-amlogic@groups.io
 F:     board/amlogic/q200/
 F:     include/configs/q200.h
+F:     configs/beelink-gt1-ultimate_defconfig
 F:     configs/khadas-vim2_defconfig
 F:     configs/libretech-s905d-pc_defconfig
 F:     configs/libretech-s912-pc_defconfig
 F:     configs/wetek-core2_defconfig
+F:     doc/board/amlogic/beelink-gt1-ultimate.rst
 F:     doc/board/amlogic/khadas-vim2.rst
 F:     doc/board/amlogic/wetek-core2.rst

diff --git a/board/amlogic/u200/MAINTAINERS b/board/amlogic/u200/MAINTAINERS
index 47cec23..f429c21 100644 (file)
--- a/board/amlogic/u200/MAINTAINERS
+++ b/board/amlogic/u200/MAINTAINERS
@@ -4,7 +4,10 @@ S:     Maintained
 L:     u-boot-amlogic@groups.io
 F:     board/amlogic/u200/
 F:     configs/u200_defconfig
+F:     configs/bananapi-m2pro_defconfig
 F:     configs/bananapi-m5_defconfig
 F:     configs/radxa-zero_defconfig
 F:     doc/board/amlogic/u200.rst
+F:     doc/board/amlogic/bananapi-m2pro.rst
+F:     doc/board/amlogic/bananapi-m5.rst
 F:     doc/board/amlogic/radxa-zero.rst

diff --git a/board/amlogic/w400/MAINTAINERS b/board/amlogic/w400/MAINTAINERS
index 96ccda2..117f79e 100644 (file)
--- a/board/amlogic/w400/MAINTAINERS
+++ b/board/amlogic/w400/MAINTAINERS
@@ -3,4 +3,10 @@ M:     Neil Armstrong <neil.armstrong@linaro.org>
 S:     Maintained
 L:     u-boot-amlogic@groups.io
 F:     board/amlogic/w400/
+F:     configs/bananapi-cm4-cm4io_defconfig
+F:     configs/bananapi-m2s_defconfig
+F:     configs/radxa-zero2_defconfig
 F:     doc/board/amlogic/w400.rst
+F:     doc/board/amlogic/bananapi-cm4io.rst
+F:     doc/board/amlogic/bananapi-m2s.rst
+F:     doc/board/amlogic/radxa-zero2.rst

diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig
index 5616e22..cf99809 100644 (file)
--- a/board/armltd/vexpress64/Kconfig
+++ b/board/armltd/vexpress64/Kconfig
@@ -12,8 +12,13 @@ config SYS_CONFIG_NAME
 config VEXPRESS64_BASE_MODEL
        bool
        select SEMIHOSTING
+       imply VIRTIO_MMIO
        select VIRTIO_BLK if VIRTIO_MMIO
        select VIRTIO_NET if VIRTIO_MMIO
+       select DM_ETH if VIRTIO_NET
+       imply RTC_PL031
+       select DM_RTC if RTC_PL031
+       imply EFI_SET_TIME if DM_RTC
        select LINUX_KERNEL_IMAGE_HEADER
        select POSITION_INDEPENDENT
 
@@ -23,7 +28,7 @@ choice
 config TARGET_VEXPRESS64_BASE_FVP
        bool "Support Versatile Express ARMv8a FVP BASE model"
        select VEXPRESS64_BASE_MODEL
-       select OF_BOARD
+       imply OF_HAS_PRIOR_STAGE
 
 config TARGET_VEXPRESS64_BASER_FVP
        bool "Support Versatile Express ARMv8r64 FVP BASE model"

diff --git a/board/beacon/imx8mp/Kconfig b/board/beacon/imx8mp/Kconfig
new file mode 100644 (file)
index 0000000..3c0fca9
--- /dev/null
+++ b/board/beacon/imx8mp/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_IMX8MP_BEACON
+
+config SYS_BOARD
+       default "imx8mp"
+
+config SYS_VENDOR
+       default "beacon"
+
+config SYS_CONFIG_NAME
+       default "imx8mp_beacon"
+
+config IMX_CONFIG
+       default "board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg"
+
+
+endif

diff --git a/board/beacon/imx8mp/MAINTAINERS b/board/beacon/imx8mp/MAINTAINERS
new file mode 100644 (file)
index 0000000..3750551
--- /dev/null
+++ b/board/beacon/imx8mp/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX8MP Beacon EmbeddedWorks Devkit
+M:     Adam Ford <aford173@gmail.com>
+S:     Maintained
+F:     board/beacon/imx8mp/
+F:     include/configs/imx8mp_beacon.h
+F:     configs/imx8mp_beacon_defconfig

diff --git a/board/beacon/imx8mp/Makefile b/board/beacon/imx8mp/Makefile
new file mode 100644 (file)
index 0000000..264720f
--- /dev/null
+++ b/board/beacon/imx8mp/Makefile
@@ -0,0 +1,13 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2022 Logic PD, Inc dba Beacon EmbeddedWorks
+#
+
+obj-y += imx8mp_beacon.o
+obj-y += ../../freescale/common/
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif

diff --git a/board/beacon/imx8mp/imx8mp_beacon.c b/board/beacon/imx8mp/imx8mp_beacon.c
new file mode 100644 (file)
index 0000000..8963a51
--- /dev/null
+++ b/board/beacon/imx8mp/imx8mp_beacon.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks */
+
+#include <common.h>
+#include <init.h>
+#include <miiphy.h>
+#include <asm/arch/sys_proto.h>
+
+static void setup_fec(void)
+{
+       struct iomuxc_gpr_base_regs *gpr =
+               (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+       /* Enable RGMII TX clk output */
+       setbits_le32(&gpr->gpr[1], BIT(22));
+}
+
+#if IS_ENABLED(CONFIG_NET)
+int board_phy_config(struct phy_device *phydev)
+{
+       if (phydev->drv->config)
+               phydev->drv->config(phydev);
+       return 0;
+}
+#endif
+
+int board_init(void)
+{
+       int ret = 0;
+
+       if (CONFIG_IS_ENABLED(FEC_MXC))
+               setup_fec();
+
+       return ret;
+}

diff --git a/board/beacon/imx8mp/imx8mp_beacon.env b/board/beacon/imx8mp/imx8mp_beacon.env
new file mode 100644 (file)
index 0000000..ec9fbd3
--- /dev/null
+++ b/board/beacon/imx8mp/imx8mp_beacon.env
@@ -0,0 +1,19 @@
+boot_fdt=try
+boot_fit=no
+console=ttymxc1,115200
+fdt_addr=0x43000000
+fdt_addr_r=0x43000000
+fdt_file=imx8mp-beacon-kit.dtb
+finduuid=part uuid mmc ${mmcdev}:2 uuid
+image=Image
+kernel_addr_r=0x40480000
+loadfdt=echo ${fdt_file}; fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdt_file}
+loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+mmcargs=setenv bootargs console=${console}  root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}
+mmcboot=echo Booting from mmc ...; run finduuid; run mmcargs; if test ${boot_fit} = yes || test ${boot_fit} = try; then bootm ${loadaddr}; else if run loadfdt; then booti ${loadaddr} - ${fdt_addr_r}; else echo WARN: Cannot load the DT; fi; fi;
+mmcdev=1
+mmcpart=1
+netargs=setenv bootargs ${jh_clk} console=${console} root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
+netboot=echo Booting from net ...; run netargs;  if test ${ip_dyn} = yes; then setenv get_cmd dhcp; else setenv get_cmd tftp; fi; ${get_cmd} ${loadaddr} ${image}; if test ${boot_fit} = yes || test ${boot_fit} = try; then bootm ${loadaddr}; else if ${get_cmd} ${fdt_addr_r} ${fdt_file}; then booti ${loadaddr} - ${fdt_addr_r}; else echo WARN: Cannot load the DT; fi; fi;
+optargs=audit=0 video=LVDS-1:d video=LVDS-2:d
+scriptaddr=0x40480000

diff --git a/board/beacon/imx8mp/imximage-8mp-lpddr4.cfg b/board/beacon/imx8mp/imximage-8mp-lpddr4.cfg
new file mode 100644 (file)
index 0000000..6dedf17
--- /dev/null
+++ b/board/beacon/imx8mp/imximage-8mp-lpddr4.cfg
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+
+ROM_VERSION    v2
+BOOT_FROM      sd
+LOADER         u-boot-spl-ddr.bin      0x920000

diff --git a/board/beacon/imx8mp/lpddr4_timing.c b/board/beacon/imx8mp/lpddr4_timing.c
new file mode 100644 (file)
index 0000000..ae0b848
--- /dev/null
+++ b/board/beacon/imx8mp/lpddr4_timing.c
@@ -0,0 +1,1881 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2022 Logic PD, Inc dba Beacon EmbeddedWorks */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+       /** Initialize DDRC registers **/
+       { 0x3d400304, 0x1 },
+       { 0x3d400030, 0x1 },
+       { 0x3d400000, 0xa3080020 },
+       { 0x3d400020, 0x1322 },
+       { 0x3d400024, 0x1e84800 },
+       { 0x3d400064, 0x3d017c },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+       { 0x3d400070, 0x1027f54 },
+#else
+       { 0x3d400070, 0x7027f90 },
+#endif
+       { 0x3d400074, 0x790 },
+       { 0x3d4000d0, 0xc00307a3 },
+       { 0x3d4000d4, 0xc50000 },
+       { 0x3d4000dc, 0xf4003f },
+       { 0x3d4000e0, 0x330000 },
+       { 0x3d4000e8, 0x660048 },
+       { 0x3d4000ec, 0x160048 },
+       { 0x3d400100, 0x2028112a },
+       { 0x3d400104, 0x8083f },
+       { 0x3d40010c, 0xe0e000 },
+       { 0x3d400110, 0x12040a12 },
+       { 0x3d400114, 0x2050f0f },
+       { 0x3d400118, 0x1010009 },
+       { 0x3d40011c, 0x501 },
+       { 0x3d400130, 0x20800 },
+       { 0x3d400134, 0xe100002 },
+       { 0x3d400138, 0x184 },
+       { 0x3d400144, 0xc80064 },
+       { 0x3d400180, 0x3e8001e },
+       { 0x3d400184, 0x3207a12 },
+       { 0x3d400188, 0x0 },
+       { 0x3d400190, 0x49f820e },
+       { 0x3d400194, 0x80303 },
+       { 0x3d4001b4, 0x1f0e },
+       { 0x3d4001a0, 0xe0400018 },
+       { 0x3d4001a4, 0xdf00e4 },
+       { 0x3d4001a8, 0x80000000 },
+       { 0x3d4001b0, 0x11 },
+       { 0x3d4001c0, 0x1 },
+       { 0x3d4001c4, 0x1 },
+       { 0x3d4000f4, 0xc99 },
+       { 0x3d400108, 0x9121c1c },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+       { 0x3d400200, 0x13 },
+       { 0x3d40020c, 0x13131300 },
+       { 0x3d400210, 0x1f1f },
+       { 0x3d400204, 0x50505 },
+       { 0x3d400214, 0x4040404 },
+       { 0x3d400218, 0x68040404 },
+#else
+       { 0x3d400200, 0x16 },
+       { 0x3d40020c, 0x0 },
+       { 0x3d400210, 0x1f1f },
+       { 0x3d400204, 0x80808 },
+       { 0x3d400214, 0x7070707 },
+       { 0x3d400218, 0x68070707 },
+#endif
+       { 0x3d40021c, 0xf08 },
+       { 0x3d400250, 0x1705 },
+       { 0x3d400254, 0x2c },
+       { 0x3d40025c, 0x4000030 },
+       { 0x3d400264, 0x900093e7 },
+       { 0x3d40026c, 0x2005574 },
+       { 0x3d400400, 0x111 },
+       { 0x3d400404, 0x72ff },
+       { 0x3d400408, 0x72ff },
+       { 0x3d400494, 0x2100e07 },
+       { 0x3d400498, 0x620096 },
+       { 0x3d40049c, 0x1100e07 },
+       { 0x3d4004a0, 0xc8012c },
+       { 0x3d402020, 0x1020 },
+       { 0x3d402024, 0x30d400 },
+       { 0x3d402050, 0x20d000 },
+       { 0x3d402064, 0x60026 },
+       { 0x3d4020dc, 0x840000 },
+       { 0x3d4020e0, 0x330000 },
+       { 0x3d4020e8, 0x660048 },
+       { 0x3d4020ec, 0x160048 },
+       { 0x3d402100, 0xa040105 },
+       { 0x3d402104, 0x30407 },
+       { 0x3d402108, 0x203060b },
+       { 0x3d40210c, 0x505000 },
+       { 0x3d402110, 0x2040202 },
+       { 0x3d402114, 0x2030202 },
+       { 0x3d402118, 0x1010004 },
+       { 0x3d40211c, 0x301 },
+       { 0x3d402130, 0x20300 },
+       { 0x3d402134, 0xa100002 },
+       { 0x3d402138, 0x27 },
+       { 0x3d402144, 0x14000a },
+       { 0x3d402180, 0x640004 },
+       { 0x3d402190, 0x3818200 },
+       { 0x3d402194, 0x80303 },
+       { 0x3d4021b4, 0x100 },
+       { 0x3d4020f4, 0xc99 },
+       { 0x3d403020, 0x1020 },
+       { 0x3d403024, 0xc3500 },
+       { 0x3d403050, 0x20d000 },
+       { 0x3d403064, 0x3000a },
+       { 0x3d4030dc, 0x840000 },
+       { 0x3d4030e0, 0x330000 },
+       { 0x3d4030e8, 0x660048 },
+       { 0x3d4030ec, 0x160048 },
+       { 0x3d403100, 0xa010102 },
+       { 0x3d403104, 0x30404 },
+       { 0x3d403108, 0x203060b },
+       { 0x3d40310c, 0x505000 },
+       { 0x3d403110, 0x2040202 },
+       { 0x3d403114, 0x2030202 },
+       { 0x3d403118, 0x1010004 },
+       { 0x3d40311c, 0x301 },
+       { 0x3d403130, 0x20300 },
+       { 0x3d403134, 0xa100002 },
+       { 0x3d403138, 0xa },
+       { 0x3d403144, 0x50003 },
+       { 0x3d403180, 0x190004 },
+       { 0x3d403190, 0x3818200 },
+       { 0x3d403194, 0x80303 },
+       { 0x3d4031b4, 0x100 },
+       { 0x3d4030f4, 0xc99 },
+       { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+       { 0x100a0, 0x0 },
+       { 0x100a1, 0x1 },
+       { 0x100a2, 0x2 },
+       { 0x100a3, 0x3 },
+       { 0x100a4, 0x4 },
+       { 0x100a5, 0x5 },
+       { 0x100a6, 0x6 },
+       { 0x100a7, 0x7 },
+       { 0x110a0, 0x0 },
+       { 0x110a1, 0x1 },
+       { 0x110a2, 0x3 },
+       { 0x110a3, 0x4 },
+       { 0x110a4, 0x5 },
+       { 0x110a5, 0x2 },
+       { 0x110a6, 0x7 },
+       { 0x110a7, 0x6 },
+       { 0x120a0, 0x0 },
+       { 0x120a1, 0x1 },
+       { 0x120a2, 0x3 },
+       { 0x120a3, 0x2 },
+       { 0x120a4, 0x5 },
+       { 0x120a5, 0x4 },
+       { 0x120a6, 0x7 },
+       { 0x120a7, 0x6 },
+       { 0x130a0, 0x0 },
+       { 0x130a1, 0x1 },
+       { 0x130a2, 0x2 },
+       { 0x130a3, 0x3 },
+       { 0x130a4, 0x4 },
+       { 0x130a5, 0x5 },
+       { 0x130a6, 0x6 },
+       { 0x130a7, 0x7 },
+       { 0x1005f, 0x1ff },
+       { 0x1015f, 0x1ff },
+       { 0x1105f, 0x1ff },
+       { 0x1115f, 0x1ff },
+       { 0x1205f, 0x1ff },
+       { 0x1215f, 0x1ff },
+       { 0x1305f, 0x1ff },
+       { 0x1315f, 0x1ff },
+       { 0x11005f, 0x1ff },
+       { 0x11015f, 0x1ff },
+       { 0x11105f, 0x1ff },
+       { 0x11115f, 0x1ff },
+       { 0x11205f, 0x1ff },
+       { 0x11215f, 0x1ff },
+       { 0x11305f, 0x1ff },
+       { 0x11315f, 0x1ff },
+       { 0x21005f, 0x1ff },
+       { 0x21015f, 0x1ff },
+       { 0x21105f, 0x1ff },
+       { 0x21115f, 0x1ff },
+       { 0x21205f, 0x1ff },
+       { 0x21215f, 0x1ff },
+       { 0x21305f, 0x1ff },
+       { 0x21315f, 0x1ff },
+       { 0x55, 0x1ff },
+       { 0x1055, 0x1ff },
+       { 0x2055, 0x1ff },
+       { 0x3055, 0x1ff },
+       { 0x4055, 0x1ff },
+       { 0x5055, 0x1ff },
+       { 0x6055, 0x1ff },
+       { 0x7055, 0x1ff },
+       { 0x8055, 0x1ff },
+       { 0x9055, 0x1ff },
+       { 0x200c5, 0x18 },
+       { 0x1200c5, 0x7 },
+       { 0x2200c5, 0x7 },
+       { 0x2002e, 0x2 },
+       { 0x12002e, 0x2 },
+       { 0x22002e, 0x2 },
+       { 0x90204, 0x0 },
+       { 0x190204, 0x0 },
+       { 0x290204, 0x0 },
+       { 0x20024, 0x1e3 },
+       { 0x2003a, 0x2 },
+       { 0x120024, 0x1e3 },
+       { 0x2003a, 0x2 },
+       { 0x220024, 0x1e3 },
+       { 0x2003a, 0x2 },
+       { 0x20056, 0x3 },
+       { 0x120056, 0x3 },
+       { 0x220056, 0x3 },
+       { 0x1004d, 0xe00 },
+       { 0x1014d, 0xe00 },
+       { 0x1104d, 0xe00 },
+       { 0x1114d, 0xe00 },
+       { 0x1204d, 0xe00 },
+       { 0x1214d, 0xe00 },
+       { 0x1304d, 0xe00 },
+       { 0x1314d, 0xe00 },
+       { 0x11004d, 0xe00 },
+       { 0x11014d, 0xe00 },
+       { 0x11104d, 0xe00 },
+       { 0x11114d, 0xe00 },
+       { 0x11204d, 0xe00 },
+       { 0x11214d, 0xe00 },
+       { 0x11304d, 0xe00 },
+       { 0x11314d, 0xe00 },
+       { 0x21004d, 0xe00 },
+       { 0x21014d, 0xe00 },
+       { 0x21104d, 0xe00 },
+       { 0x21114d, 0xe00 },
+       { 0x21204d, 0xe00 },
+       { 0x21214d, 0xe00 },
+       { 0x21304d, 0xe00 },
+       { 0x21314d, 0xe00 },
+       { 0x10049, 0xeba },
+       { 0x10149, 0xeba },
+       { 0x11049, 0xeba },
+       { 0x11149, 0xeba },
+       { 0x12049, 0xeba },
+       { 0x12149, 0xeba },
+       { 0x13049, 0xeba },
+       { 0x13149, 0xeba },
+       { 0x110049, 0xeba },
+       { 0x110149, 0xeba },
+       { 0x111049, 0xeba },
+       { 0x111149, 0xeba },
+       { 0x112049, 0xeba },
+       { 0x112149, 0xeba },
+       { 0x113049, 0xeba },
+       { 0x113149, 0xeba },
+       { 0x210049, 0xeba },
+       { 0x210149, 0xeba },
+       { 0x211049, 0xeba },
+       { 0x211149, 0xeba },
+       { 0x212049, 0xeba },
+       { 0x212149, 0xeba },
+       { 0x213049, 0xeba },
+       { 0x213149, 0xeba },
+       { 0x43, 0x63 },
+       { 0x1043, 0x63 },
+       { 0x2043, 0x63 },
+       { 0x3043, 0x63 },
+       { 0x4043, 0x63 },
+       { 0x5043, 0x63 },
+       { 0x6043, 0x63 },
+       { 0x7043, 0x63 },
+       { 0x8043, 0x63 },
+       { 0x9043, 0x63 },
+       { 0x20018, 0x3 },
+       { 0x20075, 0x4 },
+       { 0x20050, 0x0 },
+       { 0x20008, 0x3e8 },
+       { 0x120008, 0x64 },
+       { 0x220008, 0x19 },
+       { 0x20088, 0x9 },
+       { 0x200b2, 0x104 },
+       { 0x10043, 0x5a1 },
+       { 0x10143, 0x5a1 },
+       { 0x11043, 0x5a1 },
+       { 0x11143, 0x5a1 },
+       { 0x12043, 0x5a1 },
+       { 0x12143, 0x5a1 },
+       { 0x13043, 0x5a1 },
+       { 0x13143, 0x5a1 },
+       { 0x1200b2, 0x104 },
+       { 0x110043, 0x5a1 },
+       { 0x110143, 0x5a1 },
+       { 0x111043, 0x5a1 },
+       { 0x111143, 0x5a1 },
+       { 0x112043, 0x5a1 },
+       { 0x112143, 0x5a1 },
+       { 0x113043, 0x5a1 },
+       { 0x113143, 0x5a1 },
+       { 0x2200b2, 0x104 },
+       { 0x210043, 0x5a1 },
+       { 0x210143, 0x5a1 },
+       { 0x211043, 0x5a1 },
+       { 0x211143, 0x5a1 },
+       { 0x212043, 0x5a1 },
+       { 0x212143, 0x5a1 },
+       { 0x213043, 0x5a1 },
+       { 0x213143, 0x5a1 },
+       { 0x200fa, 0x1 },
+       { 0x1200fa, 0x1 },
+       { 0x2200fa, 0x1 },
+       { 0x20019, 0x1 },
+       { 0x120019, 0x1 },
+       { 0x220019, 0x1 },
+       { 0x200f0, 0x660 },
+       { 0x200f1, 0x0 },
+       { 0x200f2, 0x4444 },
+       { 0x200f3, 0x8888 },
+       { 0x200f4, 0x5665 },
+       { 0x200f5, 0x0 },
+       { 0x200f6, 0x0 },
+       { 0x200f7, 0xf000 },
+       { 0x20025, 0x0 },
+       { 0x2002d, 0x0 },
+       { 0x12002d, 0x0 },
+       { 0x22002d, 0x0 },
+       { 0x2007d, 0x212 },
+       { 0x12007d, 0x212 },
+       { 0x22007d, 0x212 },
+       { 0x2007c, 0x61 },
+       { 0x12007c, 0x61 },
+       { 0x22007c, 0x61 },
+       { 0x1004a, 0x500 },
+       { 0x1104a, 0x500 },
+       { 0x1204a, 0x500 },
+       { 0x1304a, 0x500 },
+       { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+       { 0x200b2, 0x0 },
+       { 0x1200b2, 0x0 },
+       { 0x2200b2, 0x0 },
+       { 0x200cb, 0x0 },
+       { 0x10043, 0x0 },
+       { 0x110043, 0x0 },
+       { 0x210043, 0x0 },
+       { 0x10143, 0x0 },
+       { 0x110143, 0x0 },
+       { 0x210143, 0x0 },
+       { 0x11043, 0x0 },
+       { 0x111043, 0x0 },
+       { 0x211043, 0x0 },
+       { 0x11143, 0x0 },
+       { 0x111143, 0x0 },
+       { 0x211143, 0x0 },
+       { 0x12043, 0x0 },
+       { 0x112043, 0x0 },
+       { 0x212043, 0x0 },
+       { 0x12143, 0x0 },
+       { 0x112143, 0x0 },
+       { 0x212143, 0x0 },
+       { 0x13043, 0x0 },
+       { 0x113043, 0x0 },
+       { 0x213043, 0x0 },
+       { 0x13143, 0x0 },
+       { 0x113143, 0x0 },
+       { 0x213143, 0x0 },
+       { 0x80, 0x0 },
+       { 0x100080, 0x0 },
+       { 0x200080, 0x0 },
+       { 0x1080, 0x0 },
+       { 0x101080, 0x0 },
+       { 0x201080, 0x0 },
+       { 0x2080, 0x0 },
+       { 0x102080, 0x0 },
+       { 0x202080, 0x0 },
+       { 0x3080, 0x0 },
+       { 0x103080, 0x0 },
+       { 0x203080, 0x0 },
+       { 0x4080, 0x0 },
+       { 0x104080, 0x0 },
+       { 0x204080, 0x0 },
+       { 0x5080, 0x0 },
+       { 0x105080, 0x0 },
+       { 0x205080, 0x0 },
+       { 0x6080, 0x0 },
+       { 0x106080, 0x0 },
+       { 0x206080, 0x0 },
+       { 0x7080, 0x0 },
+       { 0x107080, 0x0 },
+       { 0x207080, 0x0 },
+       { 0x8080, 0x0 },
+       { 0x108080, 0x0 },
+       { 0x208080, 0x0 },
+       { 0x9080, 0x0 },
+       { 0x109080, 0x0 },
+       { 0x209080, 0x0 },
+       { 0x10080, 0x0 },
+       { 0x110080, 0x0 },
+       { 0x210080, 0x0 },
+       { 0x10180, 0x0 },
+       { 0x110180, 0x0 },
+       { 0x210180, 0x0 },
+       { 0x11080, 0x0 },
+       { 0x111080, 0x0 },
+       { 0x211080, 0x0 },
+       { 0x11180, 0x0 },
+       { 0x111180, 0x0 },
+       { 0x211180, 0x0 },
+       { 0x12080, 0x0 },
+       { 0x112080, 0x0 },
+       { 0x212080, 0x0 },
+       { 0x12180, 0x0 },
+       { 0x112180, 0x0 },
+       { 0x212180, 0x0 },
+       { 0x13080, 0x0 },
+       { 0x113080, 0x0 },
+       { 0x213080, 0x0 },
+       { 0x13180, 0x0 },
+       { 0x113180, 0x0 },
+       { 0x213180, 0x0 },
+       { 0x10081, 0x0 },
+       { 0x110081, 0x0 },
+       { 0x210081, 0x0 },
+       { 0x10181, 0x0 },
+       { 0x110181, 0x0 },
+       { 0x210181, 0x0 },
+       { 0x11081, 0x0 },
+       { 0x111081, 0x0 },
+       { 0x211081, 0x0 },
+       { 0x11181, 0x0 },
+       { 0x111181, 0x0 },
+       { 0x211181, 0x0 },
+       { 0x12081, 0x0 },
+       { 0x112081, 0x0 },
+       { 0x212081, 0x0 },
+       { 0x12181, 0x0 },
+       { 0x112181, 0x0 },
+       { 0x212181, 0x0 },
+       { 0x13081, 0x0 },
+       { 0x113081, 0x0 },
+       { 0x213081, 0x0 },
+       { 0x13181, 0x0 },
+       { 0x113181, 0x0 },
+       { 0x213181, 0x0 },
+       { 0x100d0, 0x0 },
+       { 0x1100d0, 0x0 },
+       { 0x2100d0, 0x0 },
+       { 0x101d0, 0x0 },
+       { 0x1101d0, 0x0 },
+       { 0x2101d0, 0x0 },
+       { 0x110d0, 0x0 },
+       { 0x1110d0, 0x0 },
+       { 0x2110d0, 0x0 },
+       { 0x111d0, 0x0 },
+       { 0x1111d0, 0x0 },
+       { 0x2111d0, 0x0 },
+       { 0x120d0, 0x0 },
+       { 0x1120d0, 0x0 },
+       { 0x2120d0, 0x0 },
+       { 0x121d0, 0x0 },
+       { 0x1121d0, 0x0 },
+       { 0x2121d0, 0x0 },
+       { 0x130d0, 0x0 },
+       { 0x1130d0, 0x0 },
+       { 0x2130d0, 0x0 },
+       { 0x131d0, 0x0 },
+       { 0x1131d0, 0x0 },
+       { 0x2131d0, 0x0 },
+       { 0x100d1, 0x0 },
+       { 0x1100d1, 0x0 },
+       { 0x2100d1, 0x0 },
+       { 0x101d1, 0x0 },
+       { 0x1101d1, 0x0 },
+       { 0x2101d1, 0x0 },
+       { 0x110d1, 0x0 },
+       { 0x1110d1, 0x0 },
+       { 0x2110d1, 0x0 },
+       { 0x111d1, 0x0 },
+       { 0x1111d1, 0x0 },
+       { 0x2111d1, 0x0 },
+       { 0x120d1, 0x0 },
+       { 0x1120d1, 0x0 },
+       { 0x2120d1, 0x0 },
+       { 0x121d1, 0x0 },
+       { 0x1121d1, 0x0 },
+       { 0x2121d1, 0x0 },
+       { 0x130d1, 0x0 },
+       { 0x1130d1, 0x0 },
+       { 0x2130d1, 0x0 },
+       { 0x131d1, 0x0 },
+       { 0x1131d1, 0x0 },
+       { 0x2131d1, 0x0 },
+       { 0x10068, 0x0 },
+       { 0x10168, 0x0 },
+       { 0x10268, 0x0 },
+       { 0x10368, 0x0 },
+       { 0x10468, 0x0 },
+       { 0x10568, 0x0 },
+       { 0x10668, 0x0 },
+       { 0x10768, 0x0 },
+       { 0x10868, 0x0 },
+       { 0x11068, 0x0 },
+       { 0x11168, 0x0 },
+       { 0x11268, 0x0 },
+       { 0x11368, 0x0 },
+       { 0x11468, 0x0 },
+       { 0x11568, 0x0 },
+       { 0x11668, 0x0 },
+       { 0x11768, 0x0 },
+       { 0x11868, 0x0 },
+       { 0x12068, 0x0 },
+       { 0x12168, 0x0 },
+       { 0x12268, 0x0 },
+       { 0x12368, 0x0 },
+       { 0x12468, 0x0 },
+       { 0x12568, 0x0 },
+       { 0x12668, 0x0 },
+       { 0x12768, 0x0 },
+       { 0x12868, 0x0 },
+       { 0x13068, 0x0 },
+       { 0x13168, 0x0 },
+       { 0x13268, 0x0 },
+       { 0x13368, 0x0 },
+       { 0x13468, 0x0 },
+       { 0x13568, 0x0 },
+       { 0x13668, 0x0 },
+       { 0x13768, 0x0 },
+       { 0x13868, 0x0 },
+       { 0x10069, 0x0 },
+       { 0x10169, 0x0 },
+       { 0x10269, 0x0 },
+       { 0x10369, 0x0 },
+       { 0x10469, 0x0 },
+       { 0x10569, 0x0 },
+       { 0x10669, 0x0 },
+       { 0x10769, 0x0 },
+       { 0x10869, 0x0 },
+       { 0x11069, 0x0 },
+       { 0x11169, 0x0 },
+       { 0x11269, 0x0 },
+       { 0x11369, 0x0 },
+       { 0x11469, 0x0 },
+       { 0x11569, 0x0 },
+       { 0x11669, 0x0 },
+       { 0x11769, 0x0 },
+       { 0x11869, 0x0 },
+       { 0x12069, 0x0 },
+       { 0x12169, 0x0 },
+       { 0x12269, 0x0 },
+       { 0x12369, 0x0 },
+       { 0x12469, 0x0 },
+       { 0x12569, 0x0 },
+       { 0x12669, 0x0 },
+       { 0x12769, 0x0 },
+       { 0x12869, 0x0 },
+       { 0x13069, 0x0 },
+       { 0x13169, 0x0 },
+       { 0x13269, 0x0 },
+       { 0x13369, 0x0 },
+       { 0x13469, 0x0 },
+       { 0x13569, 0x0 },
+       { 0x13669, 0x0 },
+       { 0x13769, 0x0 },
+       { 0x13869, 0x0 },
+       { 0x1008c, 0x0 },
+       { 0x11008c, 0x0 },
+       { 0x21008c, 0x0 },
+       { 0x1018c, 0x0 },
+       { 0x11018c, 0x0 },
+       { 0x21018c, 0x0 },
+       { 0x1108c, 0x0 },
+       { 0x11108c, 0x0 },
+       { 0x21108c, 0x0 },
+       { 0x1118c, 0x0 },
+       { 0x11118c, 0x0 },
+       { 0x21118c, 0x0 },
+       { 0x1208c, 0x0 },
+       { 0x11208c, 0x0 },
+       { 0x21208c, 0x0 },
+       { 0x1218c, 0x0 },
+       { 0x11218c, 0x0 },
+       { 0x21218c, 0x0 },
+       { 0x1308c, 0x0 },
+       { 0x11308c, 0x0 },
+       { 0x21308c, 0x0 },
+       { 0x1318c, 0x0 },
+       { 0x11318c, 0x0 },
+       { 0x21318c, 0x0 },
+       { 0x1008d, 0x0 },
+       { 0x11008d, 0x0 },
+       { 0x21008d, 0x0 },
+       { 0x1018d, 0x0 },
+       { 0x11018d, 0x0 },
+       { 0x21018d, 0x0 },
+       { 0x1108d, 0x0 },
+       { 0x11108d, 0x0 },
+       { 0x21108d, 0x0 },
+       { 0x1118d, 0x0 },
+       { 0x11118d, 0x0 },
+       { 0x21118d, 0x0 },
+       { 0x1208d, 0x0 },
+       { 0x11208d, 0x0 },
+       { 0x21208d, 0x0 },
+       { 0x1218d, 0x0 },
+       { 0x11218d, 0x0 },
+       { 0x21218d, 0x0 },
+       { 0x1308d, 0x0 },
+       { 0x11308d, 0x0 },
+       { 0x21308d, 0x0 },
+       { 0x1318d, 0x0 },
+       { 0x11318d, 0x0 },
+       { 0x21318d, 0x0 },
+       { 0x100c0, 0x0 },
+       { 0x1100c0, 0x0 },
+       { 0x2100c0, 0x0 },
+       { 0x101c0, 0x0 },
+       { 0x1101c0, 0x0 },
+       { 0x2101c0, 0x0 },
+       { 0x102c0, 0x0 },
+       { 0x1102c0, 0x0 },
+       { 0x2102c0, 0x0 },
+       { 0x103c0, 0x0 },
+       { 0x1103c0, 0x0 },
+       { 0x2103c0, 0x0 },
+       { 0x104c0, 0x0 },
+       { 0x1104c0, 0x0 },
+       { 0x2104c0, 0x0 },
+       { 0x105c0, 0x0 },
+       { 0x1105c0, 0x0 },
+       { 0x2105c0, 0x0 },
+       { 0x106c0, 0x0 },
+       { 0x1106c0, 0x0 },
+       { 0x2106c0, 0x0 },
+       { 0x107c0, 0x0 },
+       { 0x1107c0, 0x0 },
+       { 0x2107c0, 0x0 },
+       { 0x108c0, 0x0 },
+       { 0x1108c0, 0x0 },
+       { 0x2108c0, 0x0 },
+       { 0x110c0, 0x0 },
+       { 0x1110c0, 0x0 },
+       { 0x2110c0, 0x0 },
+       { 0x111c0, 0x0 },
+       { 0x1111c0, 0x0 },
+       { 0x2111c0, 0x0 },
+       { 0x112c0, 0x0 },
+       { 0x1112c0, 0x0 },
+       { 0x2112c0, 0x0 },
+       { 0x113c0, 0x0 },
+       { 0x1113c0, 0x0 },
+       { 0x2113c0, 0x0 },
+       { 0x114c0, 0x0 },
+       { 0x1114c0, 0x0 },
+       { 0x2114c0, 0x0 },
+       { 0x115c0, 0x0 },
+       { 0x1115c0, 0x0 },
+       { 0x2115c0, 0x0 },
+       { 0x116c0, 0x0 },
+       { 0x1116c0, 0x0 },
+       { 0x2116c0, 0x0 },
+       { 0x117c0, 0x0 },
+       { 0x1117c0, 0x0 },
+       { 0x2117c0, 0x0 },
+       { 0x118c0, 0x0 },
+       { 0x1118c0, 0x0 },
+       { 0x2118c0, 0x0 },
+       { 0x120c0, 0x0 },
+       { 0x1120c0, 0x0 },
+       { 0x2120c0, 0x0 },
+       { 0x121c0, 0x0 },
+       { 0x1121c0, 0x0 },
+       { 0x2121c0, 0x0 },
+       { 0x122c0, 0x0 },
+       { 0x1122c0, 0x0 },
+       { 0x2122c0, 0x0 },
+       { 0x123c0, 0x0 },
+       { 0x1123c0, 0x0 },
+       { 0x2123c0, 0x0 },
+       { 0x124c0, 0x0 },
+       { 0x1124c0, 0x0 },
+       { 0x2124c0, 0x0 },
+       { 0x125c0, 0x0 },
+       { 0x1125c0, 0x0 },
+       { 0x2125c0, 0x0 },
+       { 0x126c0, 0x0 },
+       { 0x1126c0, 0x0 },
+       { 0x2126c0, 0x0 },
+       { 0x127c0, 0x0 },
+       { 0x1127c0, 0x0 },
+       { 0x2127c0, 0x0 },
+       { 0x128c0, 0x0 },
+       { 0x1128c0, 0x0 },
+       { 0x2128c0, 0x0 },
+       { 0x130c0, 0x0 },
+       { 0x1130c0, 0x0 },
+       { 0x2130c0, 0x0 },
+       { 0x131c0, 0x0 },
+       { 0x1131c0, 0x0 },
+       { 0x2131c0, 0x0 },
+       { 0x132c0, 0x0 },
+       { 0x1132c0, 0x0 },
+       { 0x2132c0, 0x0 },
+       { 0x133c0, 0x0 },
+       { 0x1133c0, 0x0 },
+       { 0x2133c0, 0x0 },
+       { 0x134c0, 0x0 },
+       { 0x1134c0, 0x0 },
+       { 0x2134c0, 0x0 },
+       { 0x135c0, 0x0 },
+       { 0x1135c0, 0x0 },
+       { 0x2135c0, 0x0 },
+       { 0x136c0, 0x0 },
+       { 0x1136c0, 0x0 },
+       { 0x2136c0, 0x0 },
+       { 0x137c0, 0x0 },
+       { 0x1137c0, 0x0 },
+       { 0x2137c0, 0x0 },
+       { 0x138c0, 0x0 },
+       { 0x1138c0, 0x0 },
+       { 0x2138c0, 0x0 },
+       { 0x100c1, 0x0 },
+       { 0x1100c1, 0x0 },
+       { 0x2100c1, 0x0 },
+       { 0x101c1, 0x0 },
+       { 0x1101c1, 0x0 },
+       { 0x2101c1, 0x0 },
+       { 0x102c1, 0x0 },
+       { 0x1102c1, 0x0 },
+       { 0x2102c1, 0x0 },
+       { 0x103c1, 0x0 },
+       { 0x1103c1, 0x0 },
+       { 0x2103c1, 0x0 },
+       { 0x104c1, 0x0 },
+       { 0x1104c1, 0x0 },
+       { 0x2104c1, 0x0 },
+       { 0x105c1, 0x0 },
+       { 0x1105c1, 0x0 },
+       { 0x2105c1, 0x0 },
+       { 0x106c1, 0x0 },
+       { 0x1106c1, 0x0 },
+       { 0x2106c1, 0x0 },
+       { 0x107c1, 0x0 },
+       { 0x1107c1, 0x0 },
+       { 0x2107c1, 0x0 },
+       { 0x108c1, 0x0 },
+       { 0x1108c1, 0x0 },
+       { 0x2108c1, 0x0 },
+       { 0x110c1, 0x0 },
+       { 0x1110c1, 0x0 },
+       { 0x2110c1, 0x0 },
+       { 0x111c1, 0x0 },
+       { 0x1111c1, 0x0 },
+       { 0x2111c1, 0x0 },
+       { 0x112c1, 0x0 },
+       { 0x1112c1, 0x0 },
+       { 0x2112c1, 0x0 },
+       { 0x113c1, 0x0 },
+       { 0x1113c1, 0x0 },
+       { 0x2113c1, 0x0 },
+       { 0x114c1, 0x0 },
+       { 0x1114c1, 0x0 },
+       { 0x2114c1, 0x0 },
+       { 0x115c1, 0x0 },
+       { 0x1115c1, 0x0 },
+       { 0x2115c1, 0x0 },
+       { 0x116c1, 0x0 },
+       { 0x1116c1, 0x0 },
+       { 0x2116c1, 0x0 },
+       { 0x117c1, 0x0 },
+       { 0x1117c1, 0x0 },
+       { 0x2117c1, 0x0 },
+       { 0x118c1, 0x0 },
+       { 0x1118c1, 0x0 },
+       { 0x2118c1, 0x0 },
+       { 0x120c1, 0x0 },
+       { 0x1120c1, 0x0 },
+       { 0x2120c1, 0x0 },
+       { 0x121c1, 0x0 },
+       { 0x1121c1, 0x0 },
+       { 0x2121c1, 0x0 },
+       { 0x122c1, 0x0 },
+       { 0x1122c1, 0x0 },
+       { 0x2122c1, 0x0 },
+       { 0x123c1, 0x0 },
+       { 0x1123c1, 0x0 },
+       { 0x2123c1, 0x0 },
+       { 0x124c1, 0x0 },
+       { 0x1124c1, 0x0 },
+       { 0x2124c1, 0x0 },
+       { 0x125c1, 0x0 },
+       { 0x1125c1, 0x0 },
+       { 0x2125c1, 0x0 },
+       { 0x126c1, 0x0 },
+       { 0x1126c1, 0x0 },
+       { 0x2126c1, 0x0 },
+       { 0x127c1, 0x0 },
+       { 0x1127c1, 0x0 },
+       { 0x2127c1, 0x0 },
+       { 0x128c1, 0x0 },
+       { 0x1128c1, 0x0 },
+       { 0x2128c1, 0x0 },
+       { 0x130c1, 0x0 },
+       { 0x1130c1, 0x0 },
+       { 0x2130c1, 0x0 },
+       { 0x131c1, 0x0 },
+       { 0x1131c1, 0x0 },
+       { 0x2131c1, 0x0 },
+       { 0x132c1, 0x0 },
+       { 0x1132c1, 0x0 },
+       { 0x2132c1, 0x0 },
+       { 0x133c1, 0x0 },
+       { 0x1133c1, 0x0 },
+       { 0x2133c1, 0x0 },
+       { 0x134c1, 0x0 },
+       { 0x1134c1, 0x0 },
+       { 0x2134c1, 0x0 },
+       { 0x135c1, 0x0 },
+       { 0x1135c1, 0x0 },
+       { 0x2135c1, 0x0 },
+       { 0x136c1, 0x0 },
+       { 0x1136c1, 0x0 },
+       { 0x2136c1, 0x0 },
+       { 0x137c1, 0x0 },
+       { 0x1137c1, 0x0 },
+       { 0x2137c1, 0x0 },
+       { 0x138c1, 0x0 },
+       { 0x1138c1, 0x0 },
+       { 0x2138c1, 0x0 },
+       { 0x10020, 0x0 },
+       { 0x110020, 0x0 },
+       { 0x210020, 0x0 },
+       { 0x11020, 0x0 },
+       { 0x111020, 0x0 },
+       { 0x211020, 0x0 },
+       { 0x12020, 0x0 },
+       { 0x112020, 0x0 },
+       { 0x212020, 0x0 },
+       { 0x13020, 0x0 },
+       { 0x113020, 0x0 },
+       { 0x213020, 0x0 },
+       { 0x20072, 0x0 },
+       { 0x20073, 0x0 },
+       { 0x20074, 0x0 },
+       { 0x100aa, 0x0 },
+       { 0x110aa, 0x0 },
+       { 0x120aa, 0x0 },
+       { 0x130aa, 0x0 },
+       { 0x20010, 0x0 },
+       { 0x120010, 0x0 },
+       { 0x220010, 0x0 },
+       { 0x20011, 0x0 },
+       { 0x120011, 0x0 },
+       { 0x220011, 0x0 },
+       { 0x100ae, 0x0 },
+       { 0x1100ae, 0x0 },
+       { 0x2100ae, 0x0 },
+       { 0x100af, 0x0 },
+       { 0x1100af, 0x0 },
+       { 0x2100af, 0x0 },
+       { 0x110ae, 0x0 },
+       { 0x1110ae, 0x0 },
+       { 0x2110ae, 0x0 },
+       { 0x110af, 0x0 },
+       { 0x1110af, 0x0 },
+       { 0x2110af, 0x0 },
+       { 0x120ae, 0x0 },
+       { 0x1120ae, 0x0 },
+       { 0x2120ae, 0x0 },
+       { 0x120af, 0x0 },
+       { 0x1120af, 0x0 },
+       { 0x2120af, 0x0 },
+       { 0x130ae, 0x0 },
+       { 0x1130ae, 0x0 },
+       { 0x2130ae, 0x0 },
+       { 0x130af, 0x0 },
+       { 0x1130af, 0x0 },
+       { 0x2130af, 0x0 },
+       { 0x20020, 0x0 },
+       { 0x120020, 0x0 },
+       { 0x220020, 0x0 },
+       { 0x100a0, 0x0 },
+       { 0x100a1, 0x0 },
+       { 0x100a2, 0x0 },
+       { 0x100a3, 0x0 },
+       { 0x100a4, 0x0 },
+       { 0x100a5, 0x0 },
+       { 0x100a6, 0x0 },
+       { 0x100a7, 0x0 },
+       { 0x110a0, 0x0 },
+       { 0x110a1, 0x0 },
+       { 0x110a2, 0x0 },
+       { 0x110a3, 0x0 },
+       { 0x110a4, 0x0 },
+       { 0x110a5, 0x0 },
+       { 0x110a6, 0x0 },
+       { 0x110a7, 0x0 },
+       { 0x120a0, 0x0 },
+       { 0x120a1, 0x0 },
+       { 0x120a2, 0x0 },
+       { 0x120a3, 0x0 },
+       { 0x120a4, 0x0 },
+       { 0x120a5, 0x0 },
+       { 0x120a6, 0x0 },
+       { 0x120a7, 0x0 },
+       { 0x130a0, 0x0 },
+       { 0x130a1, 0x0 },
+       { 0x130a2, 0x0 },
+       { 0x130a3, 0x0 },
+       { 0x130a4, 0x0 },
+       { 0x130a5, 0x0 },
+       { 0x130a6, 0x0 },
+       { 0x130a7, 0x0 },
+       { 0x2007c, 0x0 },
+       { 0x12007c, 0x0 },
+       { 0x22007c, 0x0 },
+       { 0x2007d, 0x0 },
+       { 0x12007d, 0x0 },
+       { 0x22007d, 0x0 },
+       { 0x400fd, 0x0 },
+       { 0x400c0, 0x0 },
+       { 0x90201, 0x0 },
+       { 0x190201, 0x0 },
+       { 0x290201, 0x0 },
+       { 0x90202, 0x0 },
+       { 0x190202, 0x0 },
+       { 0x290202, 0x0 },
+       { 0x90203, 0x0 },
+       { 0x190203, 0x0 },
+       { 0x290203, 0x0 },
+       { 0x90204, 0x0 },
+       { 0x190204, 0x0 },
+       { 0x290204, 0x0 },
+       { 0x90205, 0x0 },
+       { 0x190205, 0x0 },
+       { 0x290205, 0x0 },
+       { 0x90206, 0x0 },
+       { 0x190206, 0x0 },
+       { 0x290206, 0x0 },
+       { 0x90207, 0x0 },
+       { 0x190207, 0x0 },
+       { 0x290207, 0x0 },
+       { 0x90208, 0x0 },
+       { 0x190208, 0x0 },
+       { 0x290208, 0x0 },
+       { 0x10062, 0x0 },
+       { 0x10162, 0x0 },
+       { 0x10262, 0x0 },
+       { 0x10362, 0x0 },
+       { 0x10462, 0x0 },
+       { 0x10562, 0x0 },
+       { 0x10662, 0x0 },
+       { 0x10762, 0x0 },
+       { 0x10862, 0x0 },
+       { 0x11062, 0x0 },
+       { 0x11162, 0x0 },
+       { 0x11262, 0x0 },
+       { 0x11362, 0x0 },
+       { 0x11462, 0x0 },
+       { 0x11562, 0x0 },
+       { 0x11662, 0x0 },
+       { 0x11762, 0x0 },
+       { 0x11862, 0x0 },
+       { 0x12062, 0x0 },
+       { 0x12162, 0x0 },
+       { 0x12262, 0x0 },
+       { 0x12362, 0x0 },
+       { 0x12462, 0x0 },
+       { 0x12562, 0x0 },
+       { 0x12662, 0x0 },
+       { 0x12762, 0x0 },
+       { 0x12862, 0x0 },
+       { 0x13062, 0x0 },
+       { 0x13162, 0x0 },
+       { 0x13262, 0x0 },
+       { 0x13362, 0x0 },
+       { 0x13462, 0x0 },
+       { 0x13562, 0x0 },
+       { 0x13662, 0x0 },
+       { 0x13762, 0x0 },
+       { 0x13862, 0x0 },
+       { 0x20077, 0x0 },
+       { 0x10001, 0x0 },
+       { 0x11001, 0x0 },
+       { 0x12001, 0x0 },
+       { 0x13001, 0x0 },
+       { 0x10040, 0x0 },
+       { 0x10140, 0x0 },
+       { 0x10240, 0x0 },
+       { 0x10340, 0x0 },
+       { 0x10440, 0x0 },
+       { 0x10540, 0x0 },
+       { 0x10640, 0x0 },
+       { 0x10740, 0x0 },
+       { 0x10840, 0x0 },
+       { 0x10030, 0x0 },
+       { 0x10130, 0x0 },
+       { 0x10230, 0x0 },
+       { 0x10330, 0x0 },
+       { 0x10430, 0x0 },
+       { 0x10530, 0x0 },
+       { 0x10630, 0x0 },
+       { 0x10730, 0x0 },
+       { 0x10830, 0x0 },
+       { 0x11040, 0x0 },
+       { 0x11140, 0x0 },
+       { 0x11240, 0x0 },
+       { 0x11340, 0x0 },
+       { 0x11440, 0x0 },
+       { 0x11540, 0x0 },
+       { 0x11640, 0x0 },
+       { 0x11740, 0x0 },
+       { 0x11840, 0x0 },
+       { 0x11030, 0x0 },
+       { 0x11130, 0x0 },
+       { 0x11230, 0x0 },
+       { 0x11330, 0x0 },
+       { 0x11430, 0x0 },
+       { 0x11530, 0x0 },
+       { 0x11630, 0x0 },
+       { 0x11730, 0x0 },
+       { 0x11830, 0x0 },
+       { 0x12040, 0x0 },
+       { 0x12140, 0x0 },
+       { 0x12240, 0x0 },
+       { 0x12340, 0x0 },
+       { 0x12440, 0x0 },
+       { 0x12540, 0x0 },
+       { 0x12640, 0x0 },
+       { 0x12740, 0x0 },
+       { 0x12840, 0x0 },
+       { 0x12030, 0x0 },
+       { 0x12130, 0x0 },
+       { 0x12230, 0x0 },
+       { 0x12330, 0x0 },
+       { 0x12430, 0x0 },
+       { 0x12530, 0x0 },
+       { 0x12630, 0x0 },
+       { 0x12730, 0x0 },
+       { 0x12830, 0x0 },
+       { 0x13040, 0x0 },
+       { 0x13140, 0x0 },
+       { 0x13240, 0x0 },
+       { 0x13340, 0x0 },
+       { 0x13440, 0x0 },
+       { 0x13540, 0x0 },
+       { 0x13640, 0x0 },
+       { 0x13740, 0x0 },
+       { 0x13840, 0x0 },
+       { 0x13030, 0x0 },
+       { 0x13130, 0x0 },
+       { 0x13230, 0x0 },
+       { 0x13330, 0x0 },
+       { 0x13430, 0x0 },
+       { 0x13530, 0x0 },
+       { 0x13630, 0x0 },
+       { 0x13730, 0x0 },
+       { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+       { 0xd0000, 0x0 },
+       { 0x54003, 0xfa0 },
+       { 0x54004, 0x2 },
+       { 0x54005, 0x2228 },
+       { 0x54006, 0x14 },
+       { 0x54008, 0x131f },
+       { 0x54009, 0xc8 },
+       { 0x5400b, 0x2 },
+       { 0x5400f, 0x100 },
+       { 0x54012, 0x310 },
+       { 0x54019, 0x3ff4 },
+       { 0x5401a, 0x33 },
+       { 0x5401b, 0x4866 },
+       { 0x5401c, 0x4800 },
+       { 0x5401e, 0x16 },
+       { 0x5401f, 0x3ff4 },
+       { 0x54020, 0x33 },
+       { 0x54021, 0x4866 },
+       { 0x54022, 0x4800 },
+       { 0x54024, 0x16 },
+       { 0x5402b, 0x1000 },
+       { 0x5402c, 0x3 },
+       { 0x54032, 0xf400 },
+       { 0x54033, 0x333f },
+       { 0x54034, 0x6600 },
+       { 0x54035, 0x48 },
+       { 0x54036, 0x48 },
+       { 0x54037, 0x1600 },
+       { 0x54038, 0xf400 },
+       { 0x54039, 0x333f },
+       { 0x5403a, 0x6600 },
+       { 0x5403b, 0x48 },
+       { 0x5403c, 0x48 },
+       { 0x5403d, 0x1600 },
+       { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+       { 0xd0000, 0x0 },
+       { 0x54002, 0x101 },
+       { 0x54003, 0x190 },
+       { 0x54004, 0x2 },
+       { 0x54005, 0x2228 },
+       { 0x54006, 0x14 },
+       { 0x54008, 0x121f },
+       { 0x54009, 0xc8 },
+       { 0x5400b, 0x2 },
+       { 0x5400f, 0x100 },
+       { 0x54012, 0x310 },
+       { 0x54019, 0x84 },
+       { 0x5401a, 0x33 },
+       { 0x5401b, 0x4866 },
+       { 0x5401c, 0x4800 },
+       { 0x5401e, 0x16 },
+       { 0x5401f, 0x84 },
+       { 0x54020, 0x33 },
+       { 0x54021, 0x4866 },
+       { 0x54022, 0x4800 },
+       { 0x54024, 0x16 },
+       { 0x5402b, 0x1000 },
+       { 0x5402c, 0x3 },
+       { 0x54032, 0x8400 },
+       { 0x54033, 0x3300 },
+       { 0x54034, 0x6600 },
+       { 0x54035, 0x48 },
+       { 0x54036, 0x48 },
+       { 0x54037, 0x1600 },
+       { 0x54038, 0x8400 },
+       { 0x54039, 0x3300 },
+       { 0x5403a, 0x6600 },
+       { 0x5403b, 0x48 },
+       { 0x5403c, 0x48 },
+       { 0x5403d, 0x1600 },
+       { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+       { 0xd0000, 0x0 },
+       { 0x54002, 0x102 },
+       { 0x54003, 0x64 },
+       { 0x54004, 0x2 },
+       { 0x54005, 0x2228 },
+       { 0x54006, 0x14 },
+       { 0x54008, 0x121f },
+       { 0x54009, 0xc8 },
+       { 0x5400b, 0x2 },
+       { 0x5400f, 0x100 },
+       { 0x54012, 0x310 },
+       { 0x54019, 0x84 },
+       { 0x5401a, 0x33 },
+       { 0x5401b, 0x4866 },
+       { 0x5401c, 0x4800 },
+       { 0x5401e, 0x16 },
+       { 0x5401f, 0x84 },
+       { 0x54020, 0x33 },
+       { 0x54021, 0x4866 },
+       { 0x54022, 0x4800 },
+       { 0x54024, 0x16 },
+       { 0x5402b, 0x1000 },
+       { 0x5402c, 0x3 },
+       { 0x54032, 0x8400 },
+       { 0x54033, 0x3300 },
+       { 0x54034, 0x6600 },
+       { 0x54035, 0x48 },
+       { 0x54036, 0x48 },
+       { 0x54037, 0x1600 },
+       { 0x54038, 0x8400 },
+       { 0x54039, 0x3300 },
+       { 0x5403a, 0x6600 },
+       { 0x5403b, 0x48 },
+       { 0x5403c, 0x48 },
+       { 0x5403d, 0x1600 },
+       { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+       { 0xd0000, 0x0 },
+       { 0x54003, 0xfa0 },
+       { 0x54004, 0x2 },
+       { 0x54005, 0x2228 },
+       { 0x54006, 0x14 },
+       { 0x54008, 0x61 },
+       { 0x54009, 0xc8 },
+       { 0x5400b, 0x2 },
+       { 0x5400f, 0x100 },
+       { 0x54010, 0x1f7f },
+       { 0x54012, 0x310 },
+       { 0x54019, 0x3ff4 },
+       { 0x5401a, 0x33 },
+       { 0x5401b, 0x4866 },
+       { 0x5401c, 0x4800 },
+       { 0x5401e, 0x16 },
+       { 0x5401f, 0x3ff4 },
+       { 0x54020, 0x33 },
+       { 0x54021, 0x4866 },
+       { 0x54022, 0x4800 },
+       { 0x54024, 0x16 },
+       { 0x5402b, 0x1000 },
+       { 0x5402c, 0x3 },
+       { 0x54032, 0xf400 },
+       { 0x54033, 0x333f },
+       { 0x54034, 0x6600 },
+       { 0x54035, 0x48 },
+       { 0x54036, 0x48 },
+       { 0x54037, 0x1600 },
+       { 0x54038, 0xf400 },
+       { 0x54039, 0x333f },
+       { 0x5403a, 0x6600 },
+       { 0x5403b, 0x48 },
+       { 0x5403c, 0x48 },
+       { 0x5403d, 0x1600 },
+       { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+       { 0xd0000, 0x0 },
+       { 0x90000, 0x10 },
+       { 0x90001, 0x400 },
+       { 0x90002, 0x10e },
+       { 0x90003, 0x0 },
+       { 0x90004, 0x0 },
+       { 0x90005, 0x8 },
+       { 0x90029, 0xb },
+       { 0x9002a, 0x480 },
+       { 0x9002b, 0x109 },
+       { 0x9002c, 0x8 },
+       { 0x9002d, 0x448 },
+       { 0x9002e, 0x139 },
+       { 0x9002f, 0x8 },
+       { 0x90030, 0x478 },
+       { 0x90031, 0x109 },
+       { 0x90032, 0x0 },
+       { 0x90033, 0xe8 },
+       { 0x90034, 0x109 },
+       { 0x90035, 0x2 },
+       { 0x90036, 0x10 },
+       { 0x90037, 0x139 },
+       { 0x90038, 0xb },
+       { 0x90039, 0x7c0 },
+       { 0x9003a, 0x139 },
+       { 0x9003b, 0x44 },
+       { 0x9003c, 0x633 },
+       { 0x9003d, 0x159 },
+       { 0x9003e, 0x14f },
+       { 0x9003f, 0x630 },
+       { 0x90040, 0x159 },
+       { 0x90041, 0x47 },
+       { 0x90042, 0x633 },
+       { 0x90043, 0x149 },
+       { 0x90044, 0x4f },
+       { 0x90045, 0x633 },
+       { 0x90046, 0x179 },
+       { 0x90047, 0x8 },
+       { 0x90048, 0xe0 },
+       { 0x90049, 0x109 },
+       { 0x9004a, 0x0 },
+       { 0x9004b, 0x7c8 },
+       { 0x9004c, 0x109 },
+       { 0x9004d, 0x0 },
+       { 0x9004e, 0x1 },
+       { 0x9004f, 0x8 },
+       { 0x90050, 0x0 },
+       { 0x90051, 0x45a },
+       { 0x90052, 0x9 },
+       { 0x90053, 0x0 },
+       { 0x90054, 0x448 },
+       { 0x90055, 0x109 },
+       { 0x90056, 0x40 },
+       { 0x90057, 0x633 },
+       { 0x90058, 0x179 },
+       { 0x90059, 0x1 },
+       { 0x9005a, 0x618 },
+       { 0x9005b, 0x109 },
+       { 0x9005c, 0x40c0 },
+       { 0x9005d, 0x633 },
+       { 0x9005e, 0x149 },
+       { 0x9005f, 0x8 },
+       { 0x90060, 0x4 },
+       { 0x90061, 0x48 },
+       { 0x90062, 0x4040 },
+       { 0x90063, 0x633 },
+       { 0x90064, 0x149 },
+       { 0x90065, 0x0 },
+       { 0x90066, 0x4 },
+       { 0x90067, 0x48 },
+       { 0x90068, 0x40 },
+       { 0x90069, 0x633 },
+       { 0x9006a, 0x149 },
+       { 0x9006b, 0x10 },
+       { 0x9006c, 0x4 },
+       { 0x9006d, 0x18 },
+       { 0x9006e, 0x0 },
+       { 0x9006f, 0x4 },
+       { 0x90070, 0x78 },
+       { 0x90071, 0x549 },
+       { 0x90072, 0x633 },
+       { 0x90073, 0x159 },
+       { 0x90074, 0xd49 },
+       { 0x90075, 0x633 },
+       { 0x90076, 0x159 },
+       { 0x90077, 0x94a },
+       { 0x90078, 0x633 },
+       { 0x90079, 0x159 },
+       { 0x9007a, 0x441 },
+       { 0x9007b, 0x633 },
+       { 0x9007c, 0x149 },
+       { 0x9007d, 0x42 },
+       { 0x9007e, 0x633 },
+       { 0x9007f, 0x149 },
+       { 0x90080, 0x1 },
+       { 0x90081, 0x633 },
+       { 0x90082, 0x149 },
+       { 0x90083, 0x0 },
+       { 0x90084, 0xe0 },
+       { 0x90085, 0x109 },
+       { 0x90086, 0xa },
+       { 0x90087, 0x10 },
+       { 0x90088, 0x109 },
+       { 0x90089, 0x9 },
+       { 0x9008a, 0x3c0 },
+       { 0x9008b, 0x149 },
+       { 0x9008c, 0x9 },
+       { 0x9008d, 0x3c0 },
+       { 0x9008e, 0x159 },
+       { 0x9008f, 0x18 },
+       { 0x90090, 0x10 },
+       { 0x90091, 0x109 },
+       { 0x90092, 0x0 },
+       { 0x90093, 0x3c0 },
+       { 0x90094, 0x109 },
+       { 0x90095, 0x18 },
+       { 0x90096, 0x4 },
+       { 0x90097, 0x48 },
+       { 0x90098, 0x18 },
+       { 0x90099, 0x4 },
+       { 0x9009a, 0x58 },
+       { 0x9009b, 0xb },
+       { 0x9009c, 0x10 },
+       { 0x9009d, 0x109 },
+       { 0x9009e, 0x1 },
+       { 0x9009f, 0x10 },
+       { 0x900a0, 0x109 },
+       { 0x900a1, 0x5 },
+       { 0x900a2, 0x7c0 },
+       { 0x900a3, 0x109 },
+       { 0x40000, 0x811 },
+       { 0x40020, 0x880 },
+       { 0x40040, 0x0 },
+       { 0x40060, 0x0 },
+       { 0x40001, 0x4008 },
+       { 0x40021, 0x83 },
+       { 0x40041, 0x4f },
+       { 0x40061, 0x0 },
+       { 0x40002, 0x4040 },
+       { 0x40022, 0x83 },
+       { 0x40042, 0x51 },
+       { 0x40062, 0x0 },
+       { 0x40003, 0x811 },
+       { 0x40023, 0x880 },
+       { 0x40043, 0x0 },
+       { 0x40063, 0x0 },
+       { 0x40004, 0x720 },
+       { 0x40024, 0xf },
+       { 0x40044, 0x1740 },
+       { 0x40064, 0x0 },
+       { 0x40005, 0x16 },
+       { 0x40025, 0x83 },
+       { 0x40045, 0x4b },
+       { 0x40065, 0x0 },
+       { 0x40006, 0x716 },
+       { 0x40026, 0xf },
+       { 0x40046, 0x2001 },
+       { 0x40066, 0x0 },
+       { 0x40007, 0x716 },
+       { 0x40027, 0xf },
+       { 0x40047, 0x2800 },
+       { 0x40067, 0x0 },
+       { 0x40008, 0x716 },
+       { 0x40028, 0xf },
+       { 0x40048, 0xf00 },
+       { 0x40068, 0x0 },
+       { 0x40009, 0x720 },
+       { 0x40029, 0xf },
+       { 0x40049, 0x1400 },
+       { 0x40069, 0x0 },
+       { 0x4000a, 0xe08 },
+       { 0x4002a, 0xc15 },
+       { 0x4004a, 0x0 },
+       { 0x4006a, 0x0 },
+       { 0x4000b, 0x625 },
+       { 0x4002b, 0x15 },
+       { 0x4004b, 0x0 },
+       { 0x4006b, 0x0 },
+       { 0x4000c, 0x4028 },
+       { 0x4002c, 0x80 },
+       { 0x4004c, 0x0 },
+       { 0x4006c, 0x0 },
+       { 0x4000d, 0xe08 },
+       { 0x4002d, 0xc1a },
+       { 0x4004d, 0x0 },
+       { 0x4006d, 0x0 },
+       { 0x4000e, 0x625 },
+       { 0x4002e, 0x1a },
+       { 0x4004e, 0x0 },
+       { 0x4006e, 0x0 },
+       { 0x4000f, 0x4040 },
+       { 0x4002f, 0x80 },
+       { 0x4004f, 0x0 },
+       { 0x4006f, 0x0 },
+       { 0x40010, 0x2604 },
+       { 0x40030, 0x15 },
+       { 0x40050, 0x0 },
+       { 0x40070, 0x0 },
+       { 0x40011, 0x708 },
+       { 0x40031, 0x5 },
+       { 0x40051, 0x0 },
+       { 0x40071, 0x2002 },
+       { 0x40012, 0x8 },
+       { 0x40032, 0x80 },
+       { 0x40052, 0x0 },
+       { 0x40072, 0x0 },
+       { 0x40013, 0x2604 },
+       { 0x40033, 0x1a },
+       { 0x40053, 0x0 },
+       { 0x40073, 0x0 },
+       { 0x40014, 0x708 },
+       { 0x40034, 0xa },
+       { 0x40054, 0x0 },
+       { 0x40074, 0x2002 },
+       { 0x40015, 0x4040 },
+       { 0x40035, 0x80 },
+       { 0x40055, 0x0 },
+       { 0x40075, 0x0 },
+       { 0x40016, 0x60a },
+       { 0x40036, 0x15 },
+       { 0x40056, 0x1200 },
+       { 0x40076, 0x0 },
+       { 0x40017, 0x61a },
+       { 0x40037, 0x15 },
+       { 0x40057, 0x1300 },
+       { 0x40077, 0x0 },
+       { 0x40018, 0x60a },
+       { 0x40038, 0x1a },
+       { 0x40058, 0x1200 },
+       { 0x40078, 0x0 },
+       { 0x40019, 0x642 },
+       { 0x40039, 0x1a },
+       { 0x40059, 0x1300 },
+       { 0x40079, 0x0 },
+       { 0x4001a, 0x4808 },
+       { 0x4003a, 0x880 },
+       { 0x4005a, 0x0 },
+       { 0x4007a, 0x0 },
+       { 0x900a4, 0x0 },
+       { 0x900a5, 0x790 },
+       { 0x900a6, 0x11a },
+       { 0x900a7, 0x8 },
+       { 0x900a8, 0x7aa },
+       { 0x900a9, 0x2a },
+       { 0x900aa, 0x10 },
+       { 0x900ab, 0x7b2 },
+       { 0x900ac, 0x2a },
+       { 0x900ad, 0x0 },
+       { 0x900ae, 0x7c8 },
+       { 0x900af, 0x109 },
+       { 0x900b0, 0x10 },
+       { 0x900b1, 0x10 },
+       { 0x900b2, 0x109 },
+       { 0x900b3, 0x10 },
+       { 0x900b4, 0x2a8 },
+       { 0x900b5, 0x129 },
+       { 0x900b6, 0x8 },
+       { 0x900b7, 0x370 },
+       { 0x900b8, 0x129 },
+       { 0x900b9, 0xa },
+       { 0x900ba, 0x3c8 },
+       { 0x900bb, 0x1a9 },
+       { 0x900bc, 0xc },
+       { 0x900bd, 0x408 },
+       { 0x900be, 0x199 },
+       { 0x900bf, 0x14 },
+       { 0x900c0, 0x790 },
+       { 0x900c1, 0x11a },
+       { 0x900c2, 0x8 },
+       { 0x900c3, 0x4 },
+       { 0x900c4, 0x18 },
+       { 0x900c5, 0xe },
+       { 0x900c6, 0x408 },
+       { 0x900c7, 0x199 },
+       { 0x900c8, 0x8 },
+       { 0x900c9, 0x8568 },
+       { 0x900ca, 0x108 },
+       { 0x900cb, 0x18 },
+       { 0x900cc, 0x790 },
+       { 0x900cd, 0x16a },
+       { 0x900ce, 0x8 },
+       { 0x900cf, 0x1d8 },
+       { 0x900d0, 0x169 },
+       { 0x900d1, 0x10 },
+       { 0x900d2, 0x8558 },
+       { 0x900d3, 0x168 },
+       { 0x900d4, 0x70 },
+       { 0x900d5, 0x788 },
+       { 0x900d6, 0x16a },
+       { 0x900d7, 0x1ff8 },
+       { 0x900d8, 0x85a8 },
+       { 0x900d9, 0x1e8 },
+       { 0x900da, 0x50 },
+       { 0x900db, 0x798 },
+       { 0x900dc, 0x16a },
+       { 0x900dd, 0x60 },
+       { 0x900de, 0x7a0 },
+       { 0x900df, 0x16a },
+       { 0x900e0, 0x8 },
+       { 0x900e1, 0x8310 },
+       { 0x900e2, 0x168 },
+       { 0x900e3, 0x8 },
+       { 0x900e4, 0xa310 },
+       { 0x900e5, 0x168 },
+       { 0x900e6, 0xa },
+       { 0x900e7, 0x408 },
+       { 0x900e8, 0x169 },
+       { 0x900e9, 0x6e },
+       { 0x900ea, 0x0 },
+       { 0x900eb, 0x68 },
+       { 0x900ec, 0x0 },
+       { 0x900ed, 0x408 },
+       { 0x900ee, 0x169 },
+       { 0x900ef, 0x0 },
+       { 0x900f0, 0x8310 },
+       { 0x900f1, 0x168 },
+       { 0x900f2, 0x0 },
+       { 0x900f3, 0xa310 },
+       { 0x900f4, 0x168 },
+       { 0x900f5, 0x1ff8 },
+       { 0x900f6, 0x85a8 },
+       { 0x900f7, 0x1e8 },
+       { 0x900f8, 0x68 },
+       { 0x900f9, 0x798 },
+       { 0x900fa, 0x16a },
+       { 0x900fb, 0x78 },
+       { 0x900fc, 0x7a0 },
+       { 0x900fd, 0x16a },
+       { 0x900fe, 0x68 },
+       { 0x900ff, 0x790 },
+       { 0x90100, 0x16a },
+       { 0x90101, 0x8 },
+       { 0x90102, 0x8b10 },
+       { 0x90103, 0x168 },
+       { 0x90104, 0x8 },
+       { 0x90105, 0xab10 },
+       { 0x90106, 0x168 },
+       { 0x90107, 0xa },
+       { 0x90108, 0x408 },
+       { 0x90109, 0x169 },
+       { 0x9010a, 0x58 },
+       { 0x9010b, 0x0 },
+       { 0x9010c, 0x68 },
+       { 0x9010d, 0x0 },
+       { 0x9010e, 0x408 },
+       { 0x9010f, 0x169 },
+       { 0x90110, 0x0 },
+       { 0x90111, 0x8b10 },
+       { 0x90112, 0x168 },
+       { 0x90113, 0x1 },
+       { 0x90114, 0xab10 },
+       { 0x90115, 0x168 },
+       { 0x90116, 0x0 },
+       { 0x90117, 0x1d8 },
+       { 0x90118, 0x169 },
+       { 0x90119, 0x80 },
+       { 0x9011a, 0x790 },
+       { 0x9011b, 0x16a },
+       { 0x9011c, 0x18 },
+       { 0x9011d, 0x7aa },
+       { 0x9011e, 0x6a },
+       { 0x9011f, 0xa },
+       { 0x90120, 0x0 },
+       { 0x90121, 0x1e9 },
+       { 0x90122, 0x8 },
+       { 0x90123, 0x8080 },
+       { 0x90124, 0x108 },
+       { 0x90125, 0xf },
+       { 0x90126, 0x408 },
+       { 0x90127, 0x169 },
+       { 0x90128, 0xc },
+       { 0x90129, 0x0 },
+       { 0x9012a, 0x68 },
+       { 0x9012b, 0x9 },
+       { 0x9012c, 0x0 },
+       { 0x9012d, 0x1a9 },
+       { 0x9012e, 0x0 },
+       { 0x9012f, 0x408 },
+       { 0x90130, 0x169 },
+       { 0x90131, 0x0 },
+       { 0x90132, 0x8080 },
+       { 0x90133, 0x108 },
+       { 0x90134, 0x8 },
+       { 0x90135, 0x7aa },
+       { 0x90136, 0x6a },
+       { 0x90137, 0x0 },
+       { 0x90138, 0x8568 },
+       { 0x90139, 0x108 },
+       { 0x9013a, 0xb7 },
+       { 0x9013b, 0x790 },
+       { 0x9013c, 0x16a },
+       { 0x9013d, 0x1f },
+       { 0x9013e, 0x0 },
+       { 0x9013f, 0x68 },
+       { 0x90140, 0x8 },
+       { 0x90141, 0x8558 },
+       { 0x90142, 0x168 },
+       { 0x90143, 0xf },
+       { 0x90144, 0x408 },
+       { 0x90145, 0x169 },
+       { 0x90146, 0xd },
+       { 0x90147, 0x0 },
+       { 0x90148, 0x68 },
+       { 0x90149, 0x0 },
+       { 0x9014a, 0x408 },
+       { 0x9014b, 0x169 },
+       { 0x9014c, 0x0 },
+       { 0x9014d, 0x8558 },
+       { 0x9014e, 0x168 },
+       { 0x9014f, 0x8 },
+       { 0x90150, 0x3c8 },
+       { 0x90151, 0x1a9 },
+       { 0x90152, 0x3 },
+       { 0x90153, 0x370 },
+       { 0x90154, 0x129 },
+       { 0x90155, 0x20 },
+       { 0x90156, 0x2aa },
+       { 0x90157, 0x9 },
+       { 0x90158, 0x8 },
+       { 0x90159, 0xe8 },
+       { 0x9015a, 0x109 },
+       { 0x9015b, 0x0 },
+       { 0x9015c, 0x8140 },
+       { 0x9015d, 0x10c },
+       { 0x9015e, 0x10 },
+       { 0x9015f, 0x8138 },
+       { 0x90160, 0x104 },
+       { 0x90161, 0x8 },
+       { 0x90162, 0x448 },
+       { 0x90163, 0x109 },
+       { 0x90164, 0xf },
+       { 0x90165, 0x7c0 },
+       { 0x90166, 0x109 },
+       { 0x90167, 0x0 },
+       { 0x90168, 0xe8 },
+       { 0x90169, 0x109 },
+       { 0x9016a, 0x47 },
+       { 0x9016b, 0x630 },
+       { 0x9016c, 0x109 },
+       { 0x9016d, 0x8 },
+       { 0x9016e, 0x618 },
+       { 0x9016f, 0x109 },
+       { 0x90170, 0x8 },
+       { 0x90171, 0xe0 },
+       { 0x90172, 0x109 },
+       { 0x90173, 0x0 },
+       { 0x90174, 0x7c8 },
+       { 0x90175, 0x109 },
+       { 0x90176, 0x8 },
+       { 0x90177, 0x8140 },
+       { 0x90178, 0x10c },
+       { 0x90179, 0x0 },
+       { 0x9017a, 0x478 },
+       { 0x9017b, 0x109 },
+       { 0x9017c, 0x0 },
+       { 0x9017d, 0x1 },
+       { 0x9017e, 0x8 },
+       { 0x9017f, 0x8 },
+       { 0x90180, 0x4 },
+       { 0x90181, 0x0 },
+       { 0x90006, 0x8 },
+       { 0x90007, 0x7c8 },
+       { 0x90008, 0x109 },
+       { 0x90009, 0x0 },
+       { 0x9000a, 0x400 },
+       { 0x9000b, 0x106 },
+       { 0xd00e7, 0x400 },
+       { 0x90017, 0x0 },
+       { 0x9001f, 0x29 },
+       { 0x90026, 0x68 },
+       { 0x400d0, 0x0 },
+       { 0x400d1, 0x101 },
+       { 0x400d2, 0x105 },
+       { 0x400d3, 0x107 },
+       { 0x400d4, 0x10f },
+       { 0x400d5, 0x202 },
+       { 0x400d6, 0x20a },
+       { 0x400d7, 0x20b },
+       { 0x2003a, 0x2 },
+       { 0x200be, 0x3 },
+       { 0x2000b, 0x465 },
+       { 0x2000c, 0xfa },
+       { 0x2000d, 0x9c4 },
+       { 0x2000e, 0x2c },
+       { 0x12000b, 0x70 },
+       { 0x12000c, 0x19 },
+       { 0x12000d, 0xfa },
+       { 0x12000e, 0x10 },
+       { 0x22000b, 0x1c },
+       { 0x22000c, 0x6 },
+       { 0x22000d, 0x3e },
+       { 0x22000e, 0x10 },
+       { 0x9000c, 0x0 },
+       { 0x9000d, 0x173 },
+       { 0x9000e, 0x60 },
+       { 0x9000f, 0x6110 },
+       { 0x90010, 0x2152 },
+       { 0x90011, 0xdfbd },
+       { 0x90012, 0x2060 },
+       { 0x90013, 0x6152 },
+       { 0x20010, 0x5a },
+       { 0x20011, 0x3 },
+       { 0x40080, 0xe0 },
+       { 0x40081, 0x12 },
+       { 0x40082, 0xe0 },
+       { 0x40083, 0x12 },
+       { 0x40084, 0xe0 },
+       { 0x40085, 0x12 },
+       { 0x140080, 0xe0 },
+       { 0x140081, 0x12 },
+       { 0x140082, 0xe0 },
+       { 0x140083, 0x12 },
+       { 0x140084, 0xe0 },
+       { 0x140085, 0x12 },
+       { 0x240080, 0xe0 },
+       { 0x240081, 0x12 },
+       { 0x240082, 0xe0 },
+       { 0x240083, 0x12 },
+       { 0x240084, 0xe0 },
+       { 0x240085, 0x12 },
+       { 0x400fd, 0xf },
+       { 0x10011, 0x1 },
+       { 0x10012, 0x1 },
+       { 0x10013, 0x180 },
+       { 0x10018, 0x1 },
+       { 0x10002, 0x6209 },
+       { 0x100b2, 0x1 },
+       { 0x101b4, 0x1 },
+       { 0x102b4, 0x1 },
+       { 0x103b4, 0x1 },
+       { 0x104b4, 0x1 },
+       { 0x105b4, 0x1 },
+       { 0x106b4, 0x1 },
+       { 0x107b4, 0x1 },
+       { 0x108b4, 0x1 },
+       { 0x11011, 0x1 },
+       { 0x11012, 0x1 },
+       { 0x11013, 0x180 },
+       { 0x11018, 0x1 },
+       { 0x11002, 0x6209 },
+       { 0x110b2, 0x1 },
+       { 0x111b4, 0x1 },
+       { 0x112b4, 0x1 },
+       { 0x113b4, 0x1 },
+       { 0x114b4, 0x1 },
+       { 0x115b4, 0x1 },
+       { 0x116b4, 0x1 },
+       { 0x117b4, 0x1 },
+       { 0x118b4, 0x1 },
+       { 0x12011, 0x1 },
+       { 0x12012, 0x1 },
+       { 0x12013, 0x180 },
+       { 0x12018, 0x1 },
+       { 0x12002, 0x6209 },
+       { 0x120b2, 0x1 },
+       { 0x121b4, 0x1 },
+       { 0x122b4, 0x1 },
+       { 0x123b4, 0x1 },
+       { 0x124b4, 0x1 },
+       { 0x125b4, 0x1 },
+       { 0x126b4, 0x1 },
+       { 0x127b4, 0x1 },
+       { 0x128b4, 0x1 },
+       { 0x13011, 0x1 },
+       { 0x13012, 0x1 },
+       { 0x13013, 0x180 },
+       { 0x13018, 0x1 },
+       { 0x13002, 0x6209 },
+       { 0x130b2, 0x1 },
+       { 0x131b4, 0x1 },
+       { 0x132b4, 0x1 },
+       { 0x133b4, 0x1 },
+       { 0x134b4, 0x1 },
+       { 0x135b4, 0x1 },
+       { 0x136b4, 0x1 },
+       { 0x137b4, 0x1 },
+       { 0x138b4, 0x1 },
+       { 0x20089, 0x1 },
+       { 0x20088, 0x19 },
+       { 0xc0080, 0x2 },
+       { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+       {
+               /* P0 4000mts 1D */
+               .drate = 4000,
+               .fw_type = FW_1D_IMAGE,
+               .fsp_cfg = ddr_fsp0_cfg,
+               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+       },
+       {
+               /* P1 400mts 1D */
+               .drate = 400,
+               .fw_type = FW_1D_IMAGE,
+               .fsp_cfg = ddr_fsp1_cfg,
+               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+       },
+       {
+               /* P2 100mts 1D */
+               .drate = 100,
+               .fw_type = FW_1D_IMAGE,
+               .fsp_cfg = ddr_fsp2_cfg,
+               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+       },
+       {
+               /* P0 4000mts 2D */
+               .drate = 4000,
+               .fw_type = FW_2D_IMAGE,
+               .fsp_cfg = ddr_fsp0_2d_cfg,
+               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+       },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+       .ddrc_cfg = ddr_ddrc_cfg,
+       .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+       .ddrphy_cfg = ddr_ddrphy_cfg,
+       .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+       .fsp_msg = ddr_dram_fsp_msg,
+       .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+       .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+       .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+       .ddrphy_pie = ddr_phy_pie,
+       .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+       .fsp_table = { 4000, 400, 100, },
+};
+
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+void board_dram_ecc_scrub(void)
+{
+       ddrc_inline_ecc_scrub(0x0, 0x3ffffff);
+       ddrc_inline_ecc_scrub(0x20000000, 0x23ffffff);
+       ddrc_inline_ecc_scrub(0x40000000, 0x43ffffff);
+       ddrc_inline_ecc_scrub(0x4000000, 0x7ffffff);
+       ddrc_inline_ecc_scrub(0x24000000, 0x27ffffff);
+       ddrc_inline_ecc_scrub(0x44000000, 0x47ffffff);
+       ddrc_inline_ecc_scrub(0x8000000, 0xbffffff);
+       ddrc_inline_ecc_scrub(0x28000000, 0x2bffffff);
+       ddrc_inline_ecc_scrub(0x48000000, 0x4bffffff);
+       ddrc_inline_ecc_scrub(0xc000000, 0xfffffff);
+       ddrc_inline_ecc_scrub(0x2c000000, 0x2fffffff);
+       ddrc_inline_ecc_scrub(0x4c000000, 0x4fffffff);
+       ddrc_inline_ecc_scrub(0x10000000, 0x13ffffff);
+       ddrc_inline_ecc_scrub(0x30000000, 0x33ffffff);
+       ddrc_inline_ecc_scrub(0x50000000, 0x53ffffff);
+       ddrc_inline_ecc_scrub(0x14000000, 0x17ffffff);
+       ddrc_inline_ecc_scrub(0x34000000, 0x37ffffff);
+       ddrc_inline_ecc_scrub(0x54000000, 0x57ffffff);
+       ddrc_inline_ecc_scrub(0x18000000, 0x1bffffff);
+       ddrc_inline_ecc_scrub(0x38000000, 0x3bffffff);
+       ddrc_inline_ecc_scrub(0x58000000, 0x5bffffff);
+       ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff);
+}
+#endif

diff --git a/board/beacon/imx8mp/spl.c b/board/beacon/imx8mp/spl.c
new file mode 100644 (file)
index 0000000..591e8ca
--- /dev/null
+++ b/board/beacon/imx8mp/spl.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2022 Logic PD, Inc dba Beacon EmbeddedWorks
+ *
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/ddr.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+       return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_dram_init(void)
+{
+       ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+       if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+               struct udevice *dev;
+               int ret;
+
+               ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+               if (ret)
+                       printf("Failed to initialize caam_jr: %d\n", ret);
+       }
+       /*
+        * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
+        * not allow to change it. Should set the clock after PMIC
+        * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
+        * set by ROM for ND VDD_SOC
+        */
+       if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) {
+               clock_enable(CCGR_GIC, 0);
+               clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
+               clock_enable(CCGR_GIC, 1);
+       }
+}
+
+#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
+int power_init_board(void)
+{
+       struct udevice *dev;
+       int ret;
+
+       ret = pmic_get("pmic@25", &dev);
+       if (ret == -ENODEV) {
+               puts("No pmic@25\n");
+               return 0;
+       }
+       if (ret != 0)
+               return ret;
+
+       /* BUCKxOUT_DVS0/1 control BUCK123 output */
+       pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+       /*
+        * increase VDD_SOC to typical value 0.95V before first
+        * DRAM access, set DVS1 to 0.85v for suspend.
+        * Enable DVS control through PMIC_STBY_REQ and
+        * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
+        */
+       if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV))
+               pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
+       else
+               pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
+
+       pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
+       pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+       /* Kernel uses OD/OD freq for SOC */
+       /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
+       pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
+
+       return 0;
+}
+#endif
+
+#if IS_ENABLED(CONFIG_SPL_LOAD_FIT)
+int board_fit_config_name_match(const char *name)
+{
+       /* Just empty function now - can't decide what to choose */
+       debug("%s: %s\n", __func__, name);
+
+       return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+       int ret;
+
+       arch_cpu_init();
+
+       init_uart_clk(1);
+
+       ret = spl_early_init();
+       if (ret) {
+               debug("spl_init() failed: %d\n", ret);
+               hang();
+       }
+
+       preloader_console_init();
+
+       enable_tzc380();
+
+       power_init_board();
+
+       /* DDR initialization */
+       spl_dram_init();
+}

diff --git a/board/data_modul/imx8mp_edm_sbc/Kconfig b/board/data_modul/imx8mp_edm_sbc/Kconfig
new file mode 100644 (file)
index 0000000..d7a55b4
--- /dev/null
+++ b/board/data_modul/imx8mp_edm_sbc/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX8MP_DATA_MODUL_EDM_SBC
+
+config SYS_BOARD
+       default "imx8mp_edm_sbc"
+
+config SYS_VENDOR
+       default "data_modul"
+
+config SYS_CONFIG_NAME
+       default "imx8mp_data_modul_edm_sbc"
+
+config IMX_CONFIG
+       default "board/data_modul/imx8mp_edm_sbc/imximage.cfg"
+
+endif

diff --git a/board/data_modul/imx8mp_edm_sbc/MAINTAINERS b/board/data_modul/imx8mp_edm_sbc/MAINTAINERS
new file mode 100644 (file)
index 0000000..a67e104
--- /dev/null
+++ b/board/data_modul/imx8mp_edm_sbc/MAINTAINERS
@@ -0,0 +1,8 @@
+Data Modul eDM SBC i.MX8M Plus
+M:     Marek Vasut <marex@denx.de>
+S:     Maintained
+F:     arch/arm/dts/imx8mp-data-modul-edm-sbc.dts
+F:     arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi
+F:     board/data_modul/imx8mp_data_modul_edm_sbc/
+F:     configs/imx8mp_data_modul_edm_sbc_defconfig
+F:     include/configs/imx8mp_data_modul_edm_sbc.h

diff --git a/board/data_modul/imx8mp_edm_sbc/Makefile b/board/data_modul/imx8mp_edm_sbc/Makefile
new file mode 100644 (file)
index 0000000..28c1d62
--- /dev/null
+++ b/board/data_modul/imx8mp_edm_sbc/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2022 Marek Vasut <marex@denx.de>
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o lpddr4_timing_4G_32.o
+else
+obj-y += imx8mp_data_modul_edm_sbc.o
+endif
+
+obj-y += ../common/common.o

diff --git a/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c
new file mode 100644 (file)
index 0000000..9fbbbc1
--- /dev/null
+++ b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <env.h>
+#include <env_internal.h>
+#include <malloc.h>
+#include <net.h>
+#include <spl.h>
+
+#include "../common/common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void dmo_setup_second_mac_address(void)
+{
+       u8 enetaddr[6];
+       int ret;
+
+       /* In case 'eth1addr' is already set in environment, do nothing. */
+       ret = eth_env_get_enetaddr_by_index("eth", 1, enetaddr);
+       if (ret)        /* valid 'eth1addr' is already set */
+               return;
+
+       /* Read 'ethaddr' from environment and validate. */
+       ret = eth_env_get_enetaddr_by_index("eth", 0, enetaddr);
+       if (!ret)       /* 'ethaddr' in environment is not valid, stop */
+               return;
+
+       /* Set 'eth1addr' as 'ethaddr' + 1 */
+       enetaddr[5]++;
+
+       eth_env_set_enetaddr_by_index("eth", 1, enetaddr);
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+       /* Environment is always in eMMC boot partitions */
+       return prio ? ENVL_UNKNOWN : ENVL_MMC;
+}
+
+int board_init(void)
+{
+       return 0;
+}
+
+int board_late_init(void)
+{
+       struct udevice *dev;
+       int ret;
+
+       dmo_setup_boot_device();
+       dmo_setup_mac_address();
+       dmo_setup_second_mac_address();
+
+       ret = uclass_get_device_by_name(UCLASS_MISC, "usb-hub@2c", &dev);
+       if (ret)
+               printf("Error bringing up USB hub (%d)\n", ret);
+
+       return 0;
+}

diff --git a/board/data_modul/imx8mp_edm_sbc/imximage.cfg b/board/data_modul/imx8mp_edm_sbc/imximage.cfg
new file mode 100644 (file)
index 0000000..8aadedb
--- /dev/null
+++ b/board/data_modul/imx8mp_edm_sbc/imximage.cfg
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+ROM_VERSION    v2
+BOOT_FROM      sd
+LOADER         u-boot-spl-ddr.bin      0x920000

diff --git a/board/data_modul/imx8mp_edm_sbc/lpddr4_timing.h b/board/data_modul/imx8mp_edm_sbc/lpddr4_timing.h
new file mode 100644 (file)
index 0000000..24569d5
--- /dev/null
+++ b/board/data_modul/imx8mp_edm_sbc/lpddr4_timing.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+extern struct dram_timing_info dmo_imx8mp_sbc_dram_timing_32_32;
+
+#endif /* __LPDDR4_TIMING_H__ */

diff --git a/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c b/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c
new file mode 100644 (file)
index 0000000..04cef3a
--- /dev/null
+++ b/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c
@@ -0,0 +1,1849 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2019.04_5.4.x and above version
+ * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga:
+ * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h>
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+       /** Initialize DDRC registers **/
+       { 0x3d400304, 0x1 },
+       { 0x3d400030, 0x1 },
+       { 0x3d400000, 0xa3080020 },
+       { 0x3d400020, 0x1303 },
+       { 0x3d400024, 0x1c79100 },
+       { 0x3d400064, 0x710106 },
+       { 0x3d400070, 0x7027f90 },
+       { 0x3d400074, 0x790 },
+       { 0x3d4000d0, 0xc0030720 },
+       { 0x3d4000d4, 0xb80000 },
+       { 0x3d4000dc, 0xe40036 },
+       { 0x3d4000e0, 0x330000 },
+       { 0x3d4000e8, 0x660048 },
+       { 0x3d4000ec, 0x160048 },
+       { 0x3d400100, 0x1e262028 },
+       { 0x3d400104, 0x7073b },
+       { 0x3d40010c, 0xe0e000 },
+       { 0x3d400110, 0x11040a11 },
+       { 0x3d400114, 0x2050e0e },
+       { 0x3d400118, 0x1010008 },
+       { 0x3d40011c, 0x501 },
+       { 0x3d400130, 0x20700 },
+       { 0x3d400134, 0xe100002 },
+       { 0x3d400138, 0x10d },
+       { 0x3d400144, 0xbb005e },
+       { 0x3d400180, 0x3a5001c },
+       { 0x3d400184, 0x2f071e5 },
+       { 0x3d400188, 0x0 },
+       { 0x3d400190, 0x49b820c },
+       { 0x3d400194, 0x80303 },
+       { 0x3d4001b4, 0x1b0c },
+       { 0x3d4001a0, 0xe0400018 },
+       { 0x3d4001a4, 0xdf00e4 },
+       { 0x3d4001a8, 0x80000000 },
+       { 0x3d4001b0, 0x11 },
+       { 0x3d4001c0, 0x1 },
+       { 0x3d4001c4, 0x1 },
+       { 0x3d4000f4, 0xc99 },
+       { 0x3d400108, 0x810191a },
+       { 0x3d400200, 0x17 },
+       { 0x3d40020c, 0x0 },
+       { 0x3d400210, 0x1f1f },
+       { 0x3d400204, 0x80808 },
+       { 0x3d400214, 0x7070707 },
+       { 0x3d400218, 0x7070707 },
+       { 0x3d40021c, 0xf0f },
+       { 0x3d400250, 0x1705 },
+       { 0x3d400254, 0x2c },
+       { 0x3d40025c, 0x4000030 },
+       { 0x3d400264, 0x900093e7 },
+       { 0x3d40026c, 0x2005574 },
+       { 0x3d400400, 0x111 },
+       { 0x3d400404, 0x72ff },
+       { 0x3d400408, 0x72ff },
+       { 0x3d400494, 0x2100e07 },
+       { 0x3d400498, 0x620096 },
+       { 0x3d40049c, 0x1100e07 },
+       { 0x3d4004a0, 0xc8012c },
+       { 0x3d402020, 0x1001 },
+       { 0x3d402024, 0x30d400 },
+       { 0x3d402050, 0x20d000 },
+       { 0x3d402064, 0xc001c },
+       { 0x3d4020dc, 0x840000 },
+       { 0x3d4020e0, 0x330000 },
+       { 0x3d4020e8, 0x660048 },
+       { 0x3d4020ec, 0x160048 },
+       { 0x3d402100, 0xa040305 },
+       { 0x3d402104, 0x30407 },
+       { 0x3d402108, 0x203060b },
+       { 0x3d40210c, 0x505000 },
+       { 0x3d402110, 0x2040202 },
+       { 0x3d402114, 0x2030202 },
+       { 0x3d402118, 0x1010004 },
+       { 0x3d40211c, 0x301 },
+       { 0x3d402130, 0x20300 },
+       { 0x3d402134, 0xa100002 },
+       { 0x3d402138, 0x1d },
+       { 0x3d402144, 0x14000a },
+       { 0x3d402180, 0x640004 },
+       { 0x3d402190, 0x3818200 },
+       { 0x3d402194, 0x80303 },
+       { 0x3d4021b4, 0x100 },
+       { 0x3d4020f4, 0xc99 },
+       { 0x3d403020, 0x1001 },
+       { 0x3d403024, 0xc3500 },
+       { 0x3d403050, 0x20d000 },
+       { 0x3d403064, 0x30007 },
+       { 0x3d4030dc, 0x840000 },
+       { 0x3d4030e0, 0x330000 },
+       { 0x3d4030e8, 0x660048 },
+       { 0x3d4030ec, 0x160048 },
+       { 0x3d403100, 0xa010102 },
+       { 0x3d403104, 0x30404 },
+       { 0x3d403108, 0x203060b },
+       { 0x3d40310c, 0x505000 },
+       { 0x3d403110, 0x2040202 },
+       { 0x3d403114, 0x2030202 },
+       { 0x3d403118, 0x1010004 },
+       { 0x3d40311c, 0x301 },
+       { 0x3d403130, 0x20300 },
+       { 0x3d403134, 0xa100002 },
+       { 0x3d403138, 0x8 },
+       { 0x3d403144, 0x50003 },
+       { 0x3d403180, 0x190004 },
+       { 0x3d403190, 0x3818200 },
+       { 0x3d403194, 0x80303 },
+       { 0x3d4031b4, 0x100 },
+       { 0x3d4030f4, 0xc99 },
+       { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+       { 0x100a0, 0x6 },
+       { 0x100a1, 0x7 },
+       { 0x100a2, 0x0 },
+       { 0x100a3, 0x1 },
+       { 0x100a4, 0x3 },
+       { 0x100a5, 0x2 },
+       { 0x100a6, 0x4 },
+       { 0x100a7, 0x5 },
+       { 0x110a0, 0x0 },
+       { 0x110a1, 0x1 },
+       { 0x110a2, 0x3 },
+       { 0x110a3, 0x4 },
+       { 0x110a4, 0x5 },
+       { 0x110a5, 0x2 },
+       { 0x110a6, 0x7 },
+       { 0x110a7, 0x6 },
+       { 0x120a0, 0x0 },
+       { 0x120a1, 0x1 },
+       { 0x120a2, 0x3 },
+       { 0x120a3, 0x2 },
+       { 0x120a4, 0x5 },
+       { 0x120a5, 0x4 },
+       { 0x120a6, 0x7 },
+       { 0x120a7, 0x6 },
+       { 0x130a0, 0x6 },
+       { 0x130a1, 0x7 },
+       { 0x130a2, 0x0 },
+       { 0x130a3, 0x1 },
+       { 0x130a4, 0x3 },
+       { 0x130a5, 0x2 },
+       { 0x130a6, 0x4 },
+       { 0x130a7, 0x5 },
+       { 0x1005f, 0x1ff },
+       { 0x1015f, 0x1ff },
+       { 0x1105f, 0x1ff },
+       { 0x1115f, 0x1ff },
+       { 0x1205f, 0x1ff },
+       { 0x1215f, 0x1ff },
+       { 0x1305f, 0x1ff },
+       { 0x1315f, 0x1ff },
+       { 0x11005f, 0x1ff },
+       { 0x11015f, 0x1ff },
+       { 0x11105f, 0x1ff },
+       { 0x11115f, 0x1ff },
+       { 0x11205f, 0x1ff },
+       { 0x11215f, 0x1ff },
+       { 0x11305f, 0x1ff },
+       { 0x11315f, 0x1ff },
+       { 0x21005f, 0x1ff },
+       { 0x21015f, 0x1ff },
+       { 0x21105f, 0x1ff },
+       { 0x21115f, 0x1ff },
+       { 0x21205f, 0x1ff },
+       { 0x21215f, 0x1ff },
+       { 0x21305f, 0x1ff },
+       { 0x21315f, 0x1ff },
+       { 0x55, 0x1ff },
+       { 0x1055, 0x1ff },
+       { 0x2055, 0x1ff },
+       { 0x3055, 0x1ff },
+       { 0x4055, 0x1ff },
+       { 0x5055, 0x1ff },
+       { 0x6055, 0x1ff },
+       { 0x7055, 0x1ff },
+       { 0x8055, 0x1ff },
+       { 0x9055, 0x1ff },
+       { 0x200c5, 0x19 },
+       { 0x1200c5, 0x7 },
+       { 0x2200c5, 0x7 },
+       { 0x2002e, 0x2 },
+       { 0x12002e, 0x2 },
+       { 0x22002e, 0x2 },
+       { 0x90204, 0x0 },
+       { 0x190204, 0x0 },
+       { 0x290204, 0x0 },
+       { 0x20024, 0x1e3 },
+       { 0x2003a, 0x2 },
+       { 0x120024, 0x1e3 },
+       { 0x2003a, 0x2 },
+       { 0x220024, 0x1e3 },
+       { 0x2003a, 0x2 },
+       { 0x20056, 0x3 },
+       { 0x120056, 0x3 },
+       { 0x220056, 0x3 },
+       { 0x1004d, 0xe00 },
+       { 0x1014d, 0xe00 },
+       { 0x1104d, 0xe00 },
+       { 0x1114d, 0xe00 },
+       { 0x1204d, 0xe00 },
+       { 0x1214d, 0xe00 },
+       { 0x1304d, 0xe00 },
+       { 0x1314d, 0xe00 },
+       { 0x11004d, 0xe00 },
+       { 0x11014d, 0xe00 },
+       { 0x11104d, 0xe00 },
+       { 0x11114d, 0xe00 },
+       { 0x11204d, 0xe00 },
+       { 0x11214d, 0xe00 },
+       { 0x11304d, 0xe00 },
+       { 0x11314d, 0xe00 },
+       { 0x21004d, 0xe00 },
+       { 0x21014d, 0xe00 },
+       { 0x21104d, 0xe00 },
+       { 0x21114d, 0xe00 },
+       { 0x21204d, 0xe00 },
+       { 0x21214d, 0xe00 },
+       { 0x21304d, 0xe00 },
+       { 0x21314d, 0xe00 },
+       { 0x10049, 0xeba },
+       { 0x10149, 0xeba },
+       { 0x11049, 0xeba },
+       { 0x11149, 0xeba },
+       { 0x12049, 0xeba },
+       { 0x12149, 0xeba },
+       { 0x13049, 0xeba },
+       { 0x13149, 0xeba },
+       { 0x110049, 0xeba },
+       { 0x110149, 0xeba },
+       { 0x111049, 0xeba },
+       { 0x111149, 0xeba },
+       { 0x112049, 0xeba },
+       { 0x112149, 0xeba },
+       { 0x113049, 0xeba },
+       { 0x113149, 0xeba },
+       { 0x210049, 0xeba },
+       { 0x210149, 0xeba },
+       { 0x211049, 0xeba },
+       { 0x211149, 0xeba },
+       { 0x212049, 0xeba },
+       { 0x212149, 0xeba },
+       { 0x213049, 0xeba },
+       { 0x213149, 0xeba },
+       { 0x43, 0xe7 },
+       { 0x1043, 0xe7 },
+       { 0x2043, 0xe7 },
+       { 0x3043, 0xe7 },
+       { 0x4043, 0xe7 },
+       { 0x5043, 0xe7 },
+       { 0x6043, 0xe7 },
+       { 0x7043, 0xe7 },
+       { 0x8043, 0xe7 },
+       { 0x9043, 0xe7 },
+       { 0x20018, 0x3 },
+       { 0x20075, 0x4 },
+       { 0x20050, 0x0 },
+       { 0x20008, 0x3a5 },
+       { 0x120008, 0x64 },
+       { 0x220008, 0x19 },
+       { 0x20088, 0x9 },
+       { 0x200b2, 0x104 },
+       { 0x10043, 0x5a1 },
+       { 0x10143, 0x5a1 },
+       { 0x11043, 0x5a1 },
+       { 0x11143, 0x5a1 },
+       { 0x12043, 0x5a1 },
+       { 0x12143, 0x5a1 },
+       { 0x13043, 0x5a1 },
+       { 0x13143, 0x5a1 },
+       { 0x1200b2, 0x104 },
+       { 0x110043, 0x5a1 },
+       { 0x110143, 0x5a1 },
+       { 0x111043, 0x5a1 },
+       { 0x111143, 0x5a1 },
+       { 0x112043, 0x5a1 },
+       { 0x112143, 0x5a1 },
+       { 0x113043, 0x5a1 },
+       { 0x113143, 0x5a1 },
+       { 0x2200b2, 0x104 },
+       { 0x210043, 0x5a1 },
+       { 0x210143, 0x5a1 },
+       { 0x211043, 0x5a1 },
+       { 0x211143, 0x5a1 },
+       { 0x212043, 0x5a1 },
+       { 0x212143, 0x5a1 },
+       { 0x213043, 0x5a1 },
+       { 0x213143, 0x5a1 },
+       { 0x200fa, 0x1 },
+       { 0x1200fa, 0x1 },
+       { 0x2200fa, 0x1 },
+       { 0x20019, 0x1 },
+       { 0x120019, 0x1 },
+       { 0x220019, 0x1 },
+       { 0x200f0, 0x660 },
+       { 0x200f1, 0x0 },
+       { 0x200f2, 0x4444 },
+       { 0x200f3, 0x8888 },
+       { 0x200f4, 0x5665 },
+       { 0x200f5, 0x0 },
+       { 0x200f6, 0x0 },
+       { 0x200f7, 0xf000 },
+       { 0x20025, 0x0 },
+       { 0x2002d, 0x0 },
+       { 0x12002d, 0x0 },
+       { 0x22002d, 0x0 },
+       { 0x2007d, 0x212 },
+       { 0x12007d, 0x212 },
+       { 0x22007d, 0x212 },
+       { 0x2007c, 0x61 },
+       { 0x12007c, 0x61 },
+       { 0x22007c, 0x61 },
+       { 0x1004a, 0x500 },
+       { 0x1104a, 0x500 },
+       { 0x1204a, 0x500 },
+       { 0x1304a, 0x500 },
+       { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+       { 0x200b2, 0x0 },
+       { 0x1200b2, 0x0 },
+       { 0x2200b2, 0x0 },
+       { 0x200cb, 0x0 },
+       { 0x10043, 0x0 },
+       { 0x110043, 0x0 },
+       { 0x210043, 0x0 },
+       { 0x10143, 0x0 },
+       { 0x110143, 0x0 },
+       { 0x210143, 0x0 },
+       { 0x11043, 0x0 },
+       { 0x111043, 0x0 },
+       { 0x211043, 0x0 },
+       { 0x11143, 0x0 },
+       { 0x111143, 0x0 },
+       { 0x211143, 0x0 },
+       { 0x12043, 0x0 },
+       { 0x112043, 0x0 },
+       { 0x212043, 0x0 },
+       { 0x12143, 0x0 },
+       { 0x112143, 0x0 },
+       { 0x212143, 0x0 },
+       { 0x13043, 0x0 },
+       { 0x113043, 0x0 },
+       { 0x213043, 0x0 },
+       { 0x13143, 0x0 },
+       { 0x113143, 0x0 },
+       { 0x213143, 0x0 },
+       { 0x80, 0x0 },
+       { 0x100080, 0x0 },
+       { 0x200080, 0x0 },
+       { 0x1080, 0x0 },
+       { 0x101080, 0x0 },
+       { 0x201080, 0x0 },
+       { 0x2080, 0x0 },
+       { 0x102080, 0x0 },
+       { 0x202080, 0x0 },
+       { 0x3080, 0x0 },
+       { 0x103080, 0x0 },
+       { 0x203080, 0x0 },
+       { 0x4080, 0x0 },
+       { 0x104080, 0x0 },
+       { 0x204080, 0x0 },
+       { 0x5080, 0x0 },
+       { 0x105080, 0x0 },
+       { 0x205080, 0x0 },
+       { 0x6080, 0x0 },
+       { 0x106080, 0x0 },
+       { 0x206080, 0x0 },
+       { 0x7080, 0x0 },
+       { 0x107080, 0x0 },
+       { 0x207080, 0x0 },
+       { 0x8080, 0x0 },
+       { 0x108080, 0x0 },
+       { 0x208080, 0x0 },
+       { 0x9080, 0x0 },
+       { 0x109080, 0x0 },
+       { 0x209080, 0x0 },
+       { 0x10080, 0x0 },
+       { 0x110080, 0x0 },
+       { 0x210080, 0x0 },
+       { 0x10180, 0x0 },
+       { 0x110180, 0x0 },
+       { 0x210180, 0x0 },
+       { 0x11080, 0x0 },
+       { 0x111080, 0x0 },
+       { 0x211080, 0x0 },
+       { 0x11180, 0x0 },
+       { 0x111180, 0x0 },
+       { 0x211180, 0x0 },
+       { 0x12080, 0x0 },
+       { 0x112080, 0x0 },
+       { 0x212080, 0x0 },
+       { 0x12180, 0x0 },
+       { 0x112180, 0x0 },
+       { 0x212180, 0x0 },
+       { 0x13080, 0x0 },
+       { 0x113080, 0x0 },
+       { 0x213080, 0x0 },
+       { 0x13180, 0x0 },
+       { 0x113180, 0x0 },
+       { 0x213180, 0x0 },
+       { 0x10081, 0x0 },
+       { 0x110081, 0x0 },
+       { 0x210081, 0x0 },
+       { 0x10181, 0x0 },
+       { 0x110181, 0x0 },
+       { 0x210181, 0x0 },
+       { 0x11081, 0x0 },
+       { 0x111081, 0x0 },
+       { 0x211081, 0x0 },
+       { 0x11181, 0x0 },
+       { 0x111181, 0x0 },
+       { 0x211181, 0x0 },
+       { 0x12081, 0x0 },
+       { 0x112081, 0x0 },
+       { 0x212081, 0x0 },
+       { 0x12181, 0x0 },
+       { 0x112181, 0x0 },
+       { 0x212181, 0x0 },
+       { 0x13081, 0x0 },
+       { 0x113081, 0x0 },
+       { 0x213081, 0x0 },
+       { 0x13181, 0x0 },
+       { 0x113181, 0x0 },
+       { 0x213181, 0x0 },
+       { 0x100d0, 0x0 },
+       { 0x1100d0, 0x0 },
+       { 0x2100d0, 0x0 },
+       { 0x101d0, 0x0 },
+       { 0x1101d0, 0x0 },
+       { 0x2101d0, 0x0 },
+       { 0x110d0, 0x0 },
+       { 0x1110d0, 0x0 },
+       { 0x2110d0, 0x0 },
+       { 0x111d0, 0x0 },
+       { 0x1111d0, 0x0 },
+       { 0x2111d0, 0x0 },
+       { 0x120d0, 0x0 },
+       { 0x1120d0, 0x0 },
+       { 0x2120d0, 0x0 },
+       { 0x121d0, 0x0 },
+       { 0x1121d0, 0x0 },
+       { 0x2121d0, 0x0 },
+       { 0x130d0, 0x0 },
+       { 0x1130d0, 0x0 },
+       { 0x2130d0, 0x0 },
+       { 0x131d0, 0x0 },
+       { 0x1131d0, 0x0 },
+       { 0x2131d0, 0x0 },
+       { 0x100d1, 0x0 },
+       { 0x1100d1, 0x0 },
+       { 0x2100d1, 0x0 },
+       { 0x101d1, 0x0 },
+       { 0x1101d1, 0x0 },
+       { 0x2101d1, 0x0 },
+       { 0x110d1, 0x0 },
+       { 0x1110d1, 0x0 },
+       { 0x2110d1, 0x0 },
+       { 0x111d1, 0x0 },
+       { 0x1111d1, 0x0 },
+       { 0x2111d1, 0x0 },
+       { 0x120d1, 0x0 },
+       { 0x1120d1, 0x0 },
+       { 0x2120d1, 0x0 },
+       { 0x121d1, 0x0 },
+       { 0x1121d1, 0x0 },
+       { 0x2121d1, 0x0 },
+       { 0x130d1, 0x0 },
+       { 0x1130d1, 0x0 },
+       { 0x2130d1, 0x0 },
+       { 0x131d1, 0x0 },
+       { 0x1131d1, 0x0 },
+       { 0x2131d1, 0x0 },
+       { 0x10068, 0x0 },
+       { 0x10168, 0x0 },
+       { 0x10268, 0x0 },
+       { 0x10368, 0x0 },
+       { 0x10468, 0x0 },
+       { 0x10568, 0x0 },
+       { 0x10668, 0x0 },
+       { 0x10768, 0x0 },
+       { 0x10868, 0x0 },
+       { 0x11068, 0x0 },
+       { 0x11168, 0x0 },
+       { 0x11268, 0x0 },
+       { 0x11368, 0x0 },
+       { 0x11468, 0x0 },
+       { 0x11568, 0x0 },
+       { 0x11668, 0x0 },
+       { 0x11768, 0x0 },
+       { 0x11868, 0x0 },
+       { 0x12068, 0x0 },
+       { 0x12168, 0x0 },
+       { 0x12268, 0x0 },
+       { 0x12368, 0x0 },
+       { 0x12468, 0x0 },
+       { 0x12568, 0x0 },
+       { 0x12668, 0x0 },
+       { 0x12768, 0x0 },
+       { 0x12868, 0x0 },
+       { 0x13068, 0x0 },
+       { 0x13168, 0x0 },
+       { 0x13268, 0x0 },
+       { 0x13368, 0x0 },
+       { 0x13468, 0x0 },
+       { 0x13568, 0x0 },
+       { 0x13668, 0x0 },
+       { 0x13768, 0x0 },
+       { 0x13868, 0x0 },
+       { 0x10069, 0x0 },
+       { 0x10169, 0x0 },
+       { 0x10269, 0x0 },
+       { 0x10369, 0x0 },
+       { 0x10469, 0x0 },
+       { 0x10569, 0x0 },
+       { 0x10669, 0x0 },
+       { 0x10769, 0x0 },
+       { 0x10869, 0x0 },
+       { 0x11069, 0x0 },
+       { 0x11169, 0x0 },
+       { 0x11269, 0x0 },
+       { 0x11369, 0x0 },
+       { 0x11469, 0x0 },
+       { 0x11569, 0x0 },
+       { 0x11669, 0x0 },
+       { 0x11769, 0x0 },
+       { 0x11869, 0x0 },
+       { 0x12069, 0x0 },
+       { 0x12169, 0x0 },
+       { 0x12269, 0x0 },
+       { 0x12369, 0x0 },
+       { 0x12469, 0x0 },
+       { 0x12569, 0x0 },
+       { 0x12669, 0x0 },
+       { 0x12769, 0x0 },
+       { 0x12869, 0x0 },
+       { 0x13069, 0x0 },
+       { 0x13169, 0x0 },
+       { 0x13269, 0x0 },
+       { 0x13369, 0x0 },
+       { 0x13469, 0x0 },
+       { 0x13569, 0x0 },
+       { 0x13669, 0x0 },
+       { 0x13769, 0x0 },
+       { 0x13869, 0x0 },
+       { 0x1008c, 0x0 },
+       { 0x11008c, 0x0 },
+       { 0x21008c, 0x0 },
+       { 0x1018c, 0x0 },
+       { 0x11018c, 0x0 },
+       { 0x21018c, 0x0 },
+       { 0x1108c, 0x0 },
+       { 0x11108c, 0x0 },
+       { 0x21108c, 0x0 },
+       { 0x1118c, 0x0 },
+       { 0x11118c, 0x0 },
+       { 0x21118c, 0x0 },
+       { 0x1208c, 0x0 },
+       { 0x11208c, 0x0 },
+       { 0x21208c, 0x0 },
+       { 0x1218c, 0x0 },
+       { 0x11218c, 0x0 },
+       { 0x21218c, 0x0 },
+       { 0x1308c, 0x0 },
+       { 0x11308c, 0x0 },
+       { 0x21308c, 0x0 },
+       { 0x1318c, 0x0 },
+       { 0x11318c, 0x0 },
+       { 0x21318c, 0x0 },
+       { 0x1008d, 0x0 },
+       { 0x11008d, 0x0 },
+       { 0x21008d, 0x0 },
+       { 0x1018d, 0x0 },
+       { 0x11018d, 0x0 },
+       { 0x21018d, 0x0 },
+       { 0x1108d, 0x0 },
+       { 0x11108d, 0x0 },
+       { 0x21108d, 0x0 },
+       { 0x1118d, 0x0 },
+       { 0x11118d, 0x0 },
+       { 0x21118d, 0x0 },
+       { 0x1208d, 0x0 },
+       { 0x11208d, 0x0 },
+       { 0x21208d, 0x0 },
+       { 0x1218d, 0x0 },
+       { 0x11218d, 0x0 },
+       { 0x21218d, 0x0 },
+       { 0x1308d, 0x0 },
+       { 0x11308d, 0x0 },
+       { 0x21308d, 0x0 },
+       { 0x1318d, 0x0 },
+       { 0x11318d, 0x0 },
+       { 0x21318d, 0x0 },
+       { 0x100c0, 0x0 },
+       { 0x1100c0, 0x0 },
+       { 0x2100c0, 0x0 },
+       { 0x101c0, 0x0 },
+       { 0x1101c0, 0x0 },
+       { 0x2101c0, 0x0 },
+       { 0x102c0, 0x0 },
+       { 0x1102c0, 0x0 },
+       { 0x2102c0, 0x0 },
+       { 0x103c0, 0x0 },
+       { 0x1103c0, 0x0 },
+       { 0x2103c0, 0x0 },
+       { 0x104c0, 0x0 },
+       { 0x1104c0, 0x0 },
+       { 0x2104c0, 0x0 },
+       { 0x105c0, 0x0 },
+       { 0x1105c0, 0x0 },
+       { 0x2105c0, 0x0 },
+       { 0x106c0, 0x0 },
+       { 0x1106c0, 0x0 },
+       { 0x2106c0, 0x0 },
+       { 0x107c0, 0x0 },
+       { 0x1107c0, 0x0 },
+       { 0x2107c0, 0x0 },
+       { 0x108c0, 0x0 },
+       { 0x1108c0, 0x0 },
+       { 0x2108c0, 0x0 },
+       { 0x110c0, 0x0 },
+       { 0x1110c0, 0x0 },
+       { 0x2110c0, 0x0 },
+       { 0x111c0, 0x0 },
+       { 0x1111c0, 0x0 },
+       { 0x2111c0, 0x0 },
+       { 0x112c0, 0x0 },
+       { 0x1112c0, 0x0 },
+       { 0x2112c0, 0x0 },
+       { 0x113c0, 0x0 },
+       { 0x1113c0, 0x0 },
+       { 0x2113c0, 0x0 },
+       { 0x114c0, 0x0 },
+       { 0x1114c0, 0x0 },
+       { 0x2114c0, 0x0 },
+       { 0x115c0, 0x0 },
+       { 0x1115c0, 0x0 },
+       { 0x2115c0, 0x0 },
+       { 0x116c0, 0x0 },
+       { 0x1116c0, 0x0 },
+       { 0x2116c0, 0x0 },
+       { 0x117c0, 0x0 },
+       { 0x1117c0, 0x0 },
+       { 0x2117c0, 0x0 },
+       { 0x118c0, 0x0 },
+       { 0x1118c0, 0x0 },
+       { 0x2118c0, 0x0 },
+       { 0x120c0, 0x0 },
+       { 0x1120c0, 0x0 },
+       { 0x2120c0, 0x0 },
+       { 0x121c0, 0x0 },
+       { 0x1121c0, 0x0 },
+       { 0x2121c0, 0x0 },
+       { 0x122c0, 0x0 },
+       { 0x1122c0, 0x0 },
+       { 0x2122c0, 0x0 },
+       { 0x123c0, 0x0 },
+       { 0x1123c0, 0x0 },
+       { 0x2123c0, 0x0 },
+       { 0x124c0, 0x0 },
+       { 0x1124c0, 0x0 },
+       { 0x2124c0, 0x0 },
+       { 0x125c0, 0x0 },
+       { 0x1125c0, 0x0 },
+       { 0x2125c0, 0x0 },
+       { 0x126c0, 0x0 },
+       { 0x1126c0, 0x0 },
+       { 0x2126c0, 0x0 },
+       { 0x127c0, 0x0 },
+       { 0x1127c0, 0x0 },
+       { 0x2127c0, 0x0 },
+       { 0x128c0, 0x0 },
+       { 0x1128c0, 0x0 },
+       { 0x2128c0, 0x0 },
+       { 0x130c0, 0x0 },
+       { 0x1130c0, 0x0 },
+       { 0x2130c0, 0x0 },
+       { 0x131c0, 0x0 },
+       { 0x1131c0, 0x0 },
+       { 0x2131c0, 0x0 },
+       { 0x132c0, 0x0 },
+       { 0x1132c0, 0x0 },
+       { 0x2132c0, 0x0 },
+       { 0x133c0, 0x0 },
+       { 0x1133c0, 0x0 },
+       { 0x2133c0, 0x0 },
+       { 0x134c0, 0x0 },
+       { 0x1134c0, 0x0 },
+       { 0x2134c0, 0x0 },
+       { 0x135c0, 0x0 },
+       { 0x1135c0, 0x0 },
+       { 0x2135c0, 0x0 },
+       { 0x136c0, 0x0 },
+       { 0x1136c0, 0x0 },
+       { 0x2136c0, 0x0 },
+       { 0x137c0, 0x0 },
+       { 0x1137c0, 0x0 },
+       { 0x2137c0, 0x0 },
+       { 0x138c0, 0x0 },
+       { 0x1138c0, 0x0 },
+       { 0x2138c0, 0x0 },
+       { 0x100c1, 0x0 },
+       { 0x1100c1, 0x0 },
+       { 0x2100c1, 0x0 },
+       { 0x101c1, 0x0 },
+       { 0x1101c1, 0x0 },
+       { 0x2101c1, 0x0 },
+       { 0x102c1, 0x0 },
+       { 0x1102c1, 0x0 },
+       { 0x2102c1, 0x0 },
+       { 0x103c1, 0x0 },
+       { 0x1103c1, 0x0 },
+       { 0x2103c1, 0x0 },
+       { 0x104c1, 0x0 },
+       { 0x1104c1, 0x0 },
+       { 0x2104c1, 0x0 },
+       { 0x105c1, 0x0 },
+       { 0x1105c1, 0x0 },
+       { 0x2105c1, 0x0 },
+       { 0x106c1, 0x0 },
+       { 0x1106c1, 0x0 },
+       { 0x2106c1, 0x0 },
+       { 0x107c1, 0x0 },
+       { 0x1107c1, 0x0 },
+       { 0x2107c1, 0x0 },
+       { 0x108c1, 0x0 },
+       { 0x1108c1, 0x0 },
+       { 0x2108c1, 0x0 },
+       { 0x110c1, 0x0 },
+       { 0x1110c1, 0x0 },
+       { 0x2110c1, 0x0 },
+       { 0x111c1, 0x0 },
+       { 0x1111c1, 0x0 },
+       { 0x2111c1, 0x0 },
+       { 0x112c1, 0x0 },
+       { 0x1112c1, 0x0 },
+       { 0x2112c1, 0x0 },
+       { 0x113c1, 0x0 },
+       { 0x1113c1, 0x0 },
+       { 0x2113c1, 0x0 },
+       { 0x114c1, 0x0 },
+       { 0x1114c1, 0x0 },
+       { 0x2114c1, 0x0 },
+       { 0x115c1, 0x0 },
+       { 0x1115c1, 0x0 },
+       { 0x2115c1, 0x0 },
+       { 0x116c1, 0x0 },
+       { 0x1116c1, 0x0 },
+       { 0x2116c1, 0x0 },
+       { 0x117c1, 0x0 },
+       { 0x1117c1, 0x0 },
+       { 0x2117c1, 0x0 },
+       { 0x118c1, 0x0 },
+       { 0x1118c1, 0x0 },
+       { 0x2118c1, 0x0 },
+       { 0x120c1, 0x0 },
+       { 0x1120c1, 0x0 },
+       { 0x2120c1, 0x0 },
+       { 0x121c1, 0x0 },
+       { 0x1121c1, 0x0 },
+       { 0x2121c1, 0x0 },
+       { 0x122c1, 0x0 },
+       { 0x1122c1, 0x0 },
+       { 0x2122c1, 0x0 },
+       { 0x123c1, 0x0 },
+       { 0x1123c1, 0x0 },
+       { 0x2123c1, 0x0 },
+       { 0x124c1, 0x0 },
+       { 0x1124c1, 0x0 },
+       { 0x2124c1, 0x0 },
+       { 0x125c1, 0x0 },
+       { 0x1125c1, 0x0 },
+       { 0x2125c1, 0x0 },
+       { 0x126c1, 0x0 },
+       { 0x1126c1, 0x0 },
+       { 0x2126c1, 0x0 },
+       { 0x127c1, 0x0 },
+       { 0x1127c1, 0x0 },
+       { 0x2127c1, 0x0 },
+       { 0x128c1, 0x0 },
+       { 0x1128c1, 0x0 },
+       { 0x2128c1, 0x0 },
+       { 0x130c1, 0x0 },
+       { 0x1130c1, 0x0 },
+       { 0x2130c1, 0x0 },
+       { 0x131c1, 0x0 },
+       { 0x1131c1, 0x0 },
+       { 0x2131c1, 0x0 },
+       { 0x132c1, 0x0 },
+       { 0x1132c1, 0x0 },
+       { 0x2132c1, 0x0 },
+       { 0x133c1, 0x0 },
+       { 0x1133c1, 0x0 },
+       { 0x2133c1, 0x0 },
+       { 0x134c1, 0x0 },
+       { 0x1134c1, 0x0 },
+       { 0x2134c1, 0x0 },
+       { 0x135c1, 0x0 },
+       { 0x1135c1, 0x0 },
+       { 0x2135c1, 0x0 },
+       { 0x136c1, 0x0 },
+       { 0x1136c1, 0x0 },
+       { 0x2136c1, 0x0 },
+       { 0x137c1, 0x0 },
+       { 0x1137c1, 0x0 },
+       { 0x2137c1, 0x0 },
+       { 0x138c1, 0x0 },
+       { 0x1138c1, 0x0 },
+       { 0x2138c1, 0x0 },
+       { 0x10020, 0x0 },
+       { 0x110020, 0x0 },
+       { 0x210020, 0x0 },
+       { 0x11020, 0x0 },
+       { 0x111020, 0x0 },
+       { 0x211020, 0x0 },
+       { 0x12020, 0x0 },
+       { 0x112020, 0x0 },
+       { 0x212020, 0x0 },
+       { 0x13020, 0x0 },
+       { 0x113020, 0x0 },
+       { 0x213020, 0x0 },
+       { 0x20072, 0x0 },
+       { 0x20073, 0x0 },
+       { 0x20074, 0x0 },
+       { 0x100aa, 0x0 },
+       { 0x110aa, 0x0 },
+       { 0x120aa, 0x0 },
+       { 0x130aa, 0x0 },
+       { 0x20010, 0x0 },
+       { 0x120010, 0x0 },
+       { 0x220010, 0x0 },
+       { 0x20011, 0x0 },
+       { 0x120011, 0x0 },
+       { 0x220011, 0x0 },
+       { 0x100ae, 0x0 },
+       { 0x1100ae, 0x0 },
+       { 0x2100ae, 0x0 },
+       { 0x100af, 0x0 },
+       { 0x1100af, 0x0 },
+       { 0x2100af, 0x0 },
+       { 0x110ae, 0x0 },
+       { 0x1110ae, 0x0 },
+       { 0x2110ae, 0x0 },
+       { 0x110af, 0x0 },
+       { 0x1110af, 0x0 },
+       { 0x2110af, 0x0 },
+       { 0x120ae, 0x0 },
+       { 0x1120ae, 0x0 },
+       { 0x2120ae, 0x0 },
+       { 0x120af, 0x0 },
+       { 0x1120af, 0x0 },
+       { 0x2120af, 0x0 },
+       { 0x130ae, 0x0 },
+       { 0x1130ae, 0x0 },
+       { 0x2130ae, 0x0 },
+       { 0x130af, 0x0 },
+       { 0x1130af, 0x0 },
+       { 0x2130af, 0x0 },
+       { 0x20020, 0x0 },
+       { 0x120020, 0x0 },
+       { 0x220020, 0x0 },
+       { 0x100a0, 0x0 },
+       { 0x100a1, 0x0 },
+       { 0x100a2, 0x0 },
+       { 0x100a3, 0x0 },
+       { 0x100a4, 0x0 },
+       { 0x100a5, 0x0 },
+       { 0x100a6, 0x0 },
+       { 0x100a7, 0x0 },
+       { 0x110a0, 0x0 },
+       { 0x110a1, 0x0 },
+       { 0x110a2, 0x0 },
+       { 0x110a3, 0x0 },
+       { 0x110a4, 0x0 },
+       { 0x110a5, 0x0 },
+       { 0x110a6, 0x0 },
+       { 0x110a7, 0x0 },
+       { 0x120a0, 0x0 },
+       { 0x120a1, 0x0 },
+       { 0x120a2, 0x0 },
+       { 0x120a3, 0x0 },
+       { 0x120a4, 0x0 },
+       { 0x120a5, 0x0 },
+       { 0x120a6, 0x0 },
+       { 0x120a7, 0x0 },
+       { 0x130a0, 0x0 },
+       { 0x130a1, 0x0 },
+       { 0x130a2, 0x0 },
+       { 0x130a3, 0x0 },
+       { 0x130a4, 0x0 },
+       { 0x130a5, 0x0 },
+       { 0x130a6, 0x0 },
+       { 0x130a7, 0x0 },
+       { 0x2007c, 0x0 },
+       { 0x12007c, 0x0 },
+       { 0x22007c, 0x0 },
+       { 0x2007d, 0x0 },
+       { 0x12007d, 0x0 },
+       { 0x22007d, 0x0 },
+       { 0x400fd, 0x0 },
+       { 0x400c0, 0x0 },
+       { 0x90201, 0x0 },
+       { 0x190201, 0x0 },
+       { 0x290201, 0x0 },
+       { 0x90202, 0x0 },
+       { 0x190202, 0x0 },
+       { 0x290202, 0x0 },
+       { 0x90203, 0x0 },
+       { 0x190203, 0x0 },
+       { 0x290203, 0x0 },
+       { 0x90204, 0x0 },
+       { 0x190204, 0x0 },
+       { 0x290204, 0x0 },
+       { 0x90205, 0x0 },
+       { 0x190205, 0x0 },
+       { 0x290205, 0x0 },
+       { 0x90206, 0x0 },
+       { 0x190206, 0x0 },
+       { 0x290206, 0x0 },
+       { 0x90207, 0x0 },
+       { 0x190207, 0x0 },
+       { 0x290207, 0x0 },
+       { 0x90208, 0x0 },
+       { 0x190208, 0x0 },
+       { 0x290208, 0x0 },
+       { 0x10062, 0x0 },
+       { 0x10162, 0x0 },
+       { 0x10262, 0x0 },
+       { 0x10362, 0x0 },
+       { 0x10462, 0x0 },
+       { 0x10562, 0x0 },
+       { 0x10662, 0x0 },
+       { 0x10762, 0x0 },
+       { 0x10862, 0x0 },
+       { 0x11062, 0x0 },
+       { 0x11162, 0x0 },
+       { 0x11262, 0x0 },
+       { 0x11362, 0x0 },
+       { 0x11462, 0x0 },
+       { 0x11562, 0x0 },
+       { 0x11662, 0x0 },
+       { 0x11762, 0x0 },
+       { 0x11862, 0x0 },
+       { 0x12062, 0x0 },
+       { 0x12162, 0x0 },
+       { 0x12262, 0x0 },
+       { 0x12362, 0x0 },
+       { 0x12462, 0x0 },
+       { 0x12562, 0x0 },
+       { 0x12662, 0x0 },
+       { 0x12762, 0x0 },
+       { 0x12862, 0x0 },
+       { 0x13062, 0x0 },
+       { 0x13162, 0x0 },
+       { 0x13262, 0x0 },
+       { 0x13362, 0x0 },
+       { 0x13462, 0x0 },
+       { 0x13562, 0x0 },
+       { 0x13662, 0x0 },
+       { 0x13762, 0x0 },
+       { 0x13862, 0x0 },
+       { 0x20077, 0x0 },
+       { 0x10001, 0x0 },
+       { 0x11001, 0x0 },
+       { 0x12001, 0x0 },
+       { 0x13001, 0x0 },
+       { 0x10040, 0x0 },
+       { 0x10140, 0x0 },
+       { 0x10240, 0x0 },
+       { 0x10340, 0x0 },
+       { 0x10440, 0x0 },
+       { 0x10540, 0x0 },
+       { 0x10640, 0x0 },
+       { 0x10740, 0x0 },
+       { 0x10840, 0x0 },
+       { 0x10030, 0x0 },
+       { 0x10130, 0x0 },
+       { 0x10230, 0x0 },
+       { 0x10330, 0x0 },
+       { 0x10430, 0x0 },
+       { 0x10530, 0x0 },
+       { 0x10630, 0x0 },
+       { 0x10730, 0x0 },
+       { 0x10830, 0x0 },
+       { 0x11040, 0x0 },
+       { 0x11140, 0x0 },
+       { 0x11240, 0x0 },
+       { 0x11340, 0x0 },
+       { 0x11440, 0x0 },
+       { 0x11540, 0x0 },
+       { 0x11640, 0x0 },
+       { 0x11740, 0x0 },
+       { 0x11840, 0x0 },
+       { 0x11030, 0x0 },
+       { 0x11130, 0x0 },
+       { 0x11230, 0x0 },
+       { 0x11330, 0x0 },
+       { 0x11430, 0x0 },
+       { 0x11530, 0x0 },
+       { 0x11630, 0x0 },
+       { 0x11730, 0x0 },
+       { 0x11830, 0x0 },
+       { 0x12040, 0x0 },
+       { 0x12140, 0x0 },
+       { 0x12240, 0x0 },
+       { 0x12340, 0x0 },
+       { 0x12440, 0x0 },
+       { 0x12540, 0x0 },
+       { 0x12640, 0x0 },
+       { 0x12740, 0x0 },
+       { 0x12840, 0x0 },
+       { 0x12030, 0x0 },
+       { 0x12130, 0x0 },
+       { 0x12230, 0x0 },
+       { 0x12330, 0x0 },
+       { 0x12430, 0x0 },
+       { 0x12530, 0x0 },
+       { 0x12630, 0x0 },
+       { 0x12730, 0x0 },
+       { 0x12830, 0x0 },
+       { 0x13040, 0x0 },
+       { 0x13140, 0x0 },
+       { 0x13240, 0x0 },
+       { 0x13340, 0x0 },
+       { 0x13440, 0x0 },
+       { 0x13540, 0x0 },
+       { 0x13640, 0x0 },
+       { 0x13740, 0x0 },
+       { 0x13840, 0x0 },
+       { 0x13030, 0x0 },
+       { 0x13130, 0x0 },
+       { 0x13230, 0x0 },
+       { 0x13330, 0x0 },
+       { 0x13430, 0x0 },
+       { 0x13530, 0x0 },
+       { 0x13630, 0x0 },
+       { 0x13730, 0x0 },
+       { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+       { 0xd0000, 0x0 },
+       { 0x54003, 0xe94 },
+       { 0x54004, 0x2 },
+       { 0x54005, 0x2228 },
+       { 0x54006, 0x14 },
+       { 0x54008, 0x131f },
+       { 0x54009, 0xc8 },
+       { 0x5400b, 0x2 },
+       { 0x5400f, 0x100 },
+       { 0x54012, 0x310 },
+       { 0x54019, 0x36e4 },
+       { 0x5401a, 0x33 },
+       { 0x5401b, 0x4866 },
+       { 0x5401c, 0x4800 },
+       { 0x5401e, 0x16 },
+       { 0x5401f, 0x36e4 },
+       { 0x54020, 0x33 },
+       { 0x54021, 0x4866 },
+       { 0x54022, 0x4800 },
+       { 0x54024, 0x16 },
+       { 0x5402b, 0x1000 },
+       { 0x5402c, 0x3 },
+       { 0x54032, 0xe400 },
+       { 0x54033, 0x3336 },
+       { 0x54034, 0x6600 },
+       { 0x54035, 0x48 },
+       { 0x54036, 0x48 },
+       { 0x54037, 0x1600 },
+       { 0x54038, 0xe400 },
+       { 0x54039, 0x3336 },
+       { 0x5403a, 0x6600 },
+       { 0x5403b, 0x48 },
+       { 0x5403c, 0x48 },
+       { 0x5403d, 0x1600 },
+       { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+       { 0xd0000, 0x0 },
+       { 0x54002, 0x101 },
+       { 0x54003, 0x190 },
+       { 0x54004, 0x2 },
+       { 0x54005, 0x2228 },
+       { 0x54006, 0x14 },
+       { 0x54008, 0x121f },
+       { 0x54009, 0xc8 },
+       { 0x5400b, 0x2 },
+       { 0x5400f, 0x100 },
+       { 0x54012, 0x310 },
+       { 0x54019, 0x84 },
+       { 0x5401a, 0x33 },
+       { 0x5401b, 0x4866 },
+       { 0x5401c, 0x4800 },
+       { 0x5401e, 0x16 },
+       { 0x5401f, 0x84 },
+       { 0x54020, 0x33 },
+       { 0x54021, 0x4866 },
+       { 0x54022, 0x4800 },
+       { 0x54024, 0x16 },
+       { 0x5402b, 0x1000 },
+       { 0x5402c, 0x3 },
+       { 0x54032, 0x8400 },
+       { 0x54033, 0x3300 },
+       { 0x54034, 0x6600 },
+       { 0x54035, 0x48 },
+       { 0x54036, 0x48 },
+       { 0x54037, 0x1600 },
+       { 0x54038, 0x8400 },
+       { 0x54039, 0x3300 },
+       { 0x5403a, 0x6600 },
+       { 0x5403b, 0x48 },
+       { 0x5403c, 0x48 },
+       { 0x5403d, 0x1600 },
+       { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+       { 0xd0000, 0x0 },
+       { 0x54002, 0x102 },
+       { 0x54003, 0x64 },
+       { 0x54004, 0x2 },
+       { 0x54005, 0x2228 },
+       { 0x54006, 0x14 },
+       { 0x54008, 0x121f },
+       { 0x54009, 0xc8 },
+       { 0x5400b, 0x2 },
+       { 0x5400f, 0x100 },
+       { 0x54012, 0x310 },
+       { 0x54019, 0x84 },
+       { 0x5401a, 0x33 },
+       { 0x5401b, 0x4866 },
+       { 0x5401c, 0x4800 },
+       { 0x5401e, 0x16 },
+       { 0x5401f, 0x84 },
+       { 0x54020, 0x33 },
+       { 0x54021, 0x4866 },
+       { 0x54022, 0x4800 },
+       { 0x54024, 0x16 },
+       { 0x5402b, 0x1000 },
+       { 0x5402c, 0x3 },
+       { 0x54032, 0x8400 },
+       { 0x54033, 0x3300 },
+       { 0x54034, 0x6600 },
+       { 0x54035, 0x48 },
+       { 0x54036, 0x48 },
+       { 0x54037, 0x1600 },
+       { 0x54038, 0x8400 },
+       { 0x54039, 0x3300 },
+       { 0x5403a, 0x6600 },
+       { 0x5403b, 0x48 },
+       { 0x5403c, 0x48 },
+       { 0x5403d, 0x1600 },
+       { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+       { 0xd0000, 0x0 },
+       { 0x54003, 0xe94 },
+       { 0x54004, 0x2 },
+       { 0x54005, 0x2228 },
+       { 0x54006, 0x14 },
+       { 0x54008, 0x61 },
+       { 0x54009, 0xc8 },
+       { 0x5400b, 0x2 },
+       { 0x5400f, 0x100 },
+       { 0x54010, 0x1f7f },
+       { 0x54012, 0x310 },
+       { 0x54019, 0x36e4 },
+       { 0x5401a, 0x33 },
+       { 0x5401b, 0x4866 },
+       { 0x5401c, 0x4800 },
+       { 0x5401e, 0x16 },
+       { 0x5401f, 0x36e4 },
+       { 0x54020, 0x33 },
+       { 0x54021, 0x4866 },
+       { 0x54022, 0x4800 },
+       { 0x54024, 0x16 },
+       { 0x5402b, 0x1000 },
+       { 0x5402c, 0x3 },
+       { 0x54032, 0xe400 },
+       { 0x54033, 0x3336 },
+       { 0x54034, 0x6600 },
+       { 0x54035, 0x48 },
+       { 0x54036, 0x48 },
+       { 0x54037, 0x1600 },
+       { 0x54038, 0xe400 },
+       { 0x54039, 0x3336 },
+       { 0x5403a, 0x6600 },
+       { 0x5403b, 0x48 },
+       { 0x5403c, 0x48 },
+       { 0x5403d, 0x1600 },
+       { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+       { 0xd0000, 0x0 },
+       { 0x90000, 0x10 },
+       { 0x90001, 0x400 },
+       { 0x90002, 0x10e },
+       { 0x90003, 0x0 },
+       { 0x90004, 0x0 },
+       { 0x90005, 0x8 },
+       { 0x90029, 0xb },
+       { 0x9002a, 0x480 },
+       { 0x9002b, 0x109 },
+       { 0x9002c, 0x8 },
+       { 0x9002d, 0x448 },
+       { 0x9002e, 0x139 },
+       { 0x9002f, 0x8 },
+       { 0x90030, 0x478 },
+       { 0x90031, 0x109 },
+       { 0x90032, 0x0 },
+       { 0x90033, 0xe8 },
+       { 0x90034, 0x109 },
+       { 0x90035, 0x2 },
+       { 0x90036, 0x10 },
+       { 0x90037, 0x139 },
+       { 0x90038, 0xb },
+       { 0x90039, 0x7c0 },
+       { 0x9003a, 0x139 },
+       { 0x9003b, 0x44 },
+       { 0x9003c, 0x633 },
+       { 0x9003d, 0x159 },
+       { 0x9003e, 0x14f },
+       { 0x9003f, 0x630 },
+       { 0x90040, 0x159 },
+       { 0x90041, 0x47 },
+       { 0x90042, 0x633 },
+       { 0x90043, 0x149 },
+       { 0x90044, 0x4f },
+       { 0x90045, 0x633 },
+       { 0x90046, 0x179 },
+       { 0x90047, 0x8 },
+       { 0x90048, 0xe0 },
+       { 0x90049, 0x109 },
+       { 0x9004a, 0x0 },
+       { 0x9004b, 0x7c8 },
+       { 0x9004c, 0x109 },
+       { 0x9004d, 0x0 },
+       { 0x9004e, 0x1 },
+       { 0x9004f, 0x8 },
+       { 0x90050, 0x0 },
+       { 0x90051, 0x45a },
+       { 0x90052, 0x9 },
+       { 0x90053, 0x0 },
+       { 0x90054, 0x448 },
+       { 0x90055, 0x109 },
+       { 0x90056, 0x40 },
+       { 0x90057, 0x633 },
+       { 0x90058, 0x179 },
+       { 0x90059, 0x1 },
+       { 0x9005a, 0x618 },
+       { 0x9005b, 0x109 },
+       { 0x9005c, 0x40c0 },
+       { 0x9005d, 0x633 },
+       { 0x9005e, 0x149 },
+       { 0x9005f, 0x8 },
+       { 0x90060, 0x4 },
+       { 0x90061, 0x48 },
+       { 0x90062, 0x4040 },
+       { 0x90063, 0x633 },
+       { 0x90064, 0x149 },
+       { 0x90065, 0x0 },
+       { 0x90066, 0x4 },
+       { 0x90067, 0x48 },
+       { 0x90068, 0x40 },
+       { 0x90069, 0x633 },
+       { 0x9006a, 0x149 },
+       { 0x9006b, 0x10 },
+       { 0x9006c, 0x4 },
+       { 0x9006d, 0x18 },
+       { 0x9006e, 0x0 },
+       { 0x9006f, 0x4 },
+       { 0x90070, 0x78 },
+       { 0x90071, 0x549 },
+       { 0x90072, 0x633 },
+       { 0x90073, 0x159 },
+       { 0x90074, 0xd49 },
+       { 0x90075, 0x633 },
+       { 0x90076, 0x159 },
+       { 0x90077, 0x94a },
+       { 0x90078, 0x633 },
+       { 0x90079, 0x159 },
+       { 0x9007a, 0x441 },
+       { 0x9007b, 0x633 },
+       { 0x9007c, 0x149 },
+       { 0x9007d, 0x42 },
+       { 0x9007e, 0x633 },
+       { 0x9007f, 0x149 },
+       { 0x90080, 0x1 },
+       { 0x90081, 0x633 },
+       { 0x90082, 0x149 },
+       { 0x90083, 0x0 },
+       { 0x90084, 0xe0 },
+       { 0x90085, 0x109 },
+       { 0x90086, 0xa },
+       { 0x90087, 0x10 },
+       { 0x90088, 0x109 },
+       { 0x90089, 0x9 },
+       { 0x9008a, 0x3c0 },
+       { 0x9008b, 0x149 },
+       { 0x9008c, 0x9 },
+       { 0x9008d, 0x3c0 },
+       { 0x9008e, 0x159 },
+       { 0x9008f, 0x18 },
+       { 0x90090, 0x10 },
+       { 0x90091, 0x109 },
+       { 0x90092, 0x0 },
+       { 0x90093, 0x3c0 },
+       { 0x90094, 0x109 },
+       { 0x90095, 0x18 },
+       { 0x90096, 0x4 },
+       { 0x90097, 0x48 },
+       { 0x90098, 0x18 },
+       { 0x90099, 0x4 },
+       { 0x9009a, 0x58 },
+       { 0x9009b, 0xb },
+       { 0x9009c, 0x10 },
+       { 0x9009d, 0x109 },
+       { 0x9009e, 0x1 },
+       { 0x9009f, 0x10 },
+       { 0x900a0, 0x109 },
+       { 0x900a1, 0x5 },
+       { 0x900a2, 0x7c0 },
+       { 0x900a3, 0x109 },
+       { 0x40000, 0x811 },
+       { 0x40020, 0x880 },
+       { 0x40040, 0x0 },
+       { 0x40060, 0x0 },
+       { 0x40001, 0x4008 },
+       { 0x40021, 0x83 },
+       { 0x40041, 0x4f },
+       { 0x40061, 0x0 },
+       { 0x40002, 0x4040 },
+       { 0x40022, 0x83 },
+       { 0x40042, 0x51 },
+       { 0x40062, 0x0 },
+       { 0x40003, 0x811 },
+       { 0x40023, 0x880 },
+       { 0x40043, 0x0 },
+       { 0x40063, 0x0 },
+       { 0x40004, 0x720 },
+       { 0x40024, 0xf },
+       { 0x40044, 0x1740 },
+       { 0x40064, 0x0 },
+       { 0x40005, 0x16 },
+       { 0x40025, 0x83 },
+       { 0x40045, 0x4b },
+       { 0x40065, 0x0 },
+       { 0x40006, 0x716 },
+       { 0x40026, 0xf },
+       { 0x40046, 0x2001 },
+       { 0x40066, 0x0 },
+       { 0x40007, 0x716 },
+       { 0x40027, 0xf },
+       { 0x40047, 0x2800 },
+       { 0x40067, 0x0 },
+       { 0x40008, 0x716 },
+       { 0x40028, 0xf },
+       { 0x40048, 0xf00 },
+       { 0x40068, 0x0 },
+       { 0x40009, 0x720 },
+       { 0x40029, 0xf },
+       { 0x40049, 0x1400 },
+       { 0x40069, 0x0 },
+       { 0x4000a, 0xe08 },
+       { 0x4002a, 0xc15 },
+       { 0x4004a, 0x0 },
+       { 0x4006a, 0x0 },
+       { 0x4000b, 0x625 },
+       { 0x4002b, 0x15 },
+       { 0x4004b, 0x0 },
+       { 0x4006b, 0x0 },
+       { 0x4000c, 0x4028 },
+       { 0x4002c, 0x80 },
+       { 0x4004c, 0x0 },
+       { 0x4006c, 0x0 },
+       { 0x4000d, 0xe08 },
+       { 0x4002d, 0xc1a },
+       { 0x4004d, 0x0 },
+       { 0x4006d, 0x0 },
+       { 0x4000e, 0x625 },
+       { 0x4002e, 0x1a },
+       { 0x4004e, 0x0 },
+       { 0x4006e, 0x0 },
+       { 0x4000f, 0x4040 },
+       { 0x4002f, 0x80 },
+       { 0x4004f, 0x0 },
+       { 0x4006f, 0x0 },
+       { 0x40010, 0x2604 },
+       { 0x40030, 0x15 },
+       { 0x40050, 0x0 },
+       { 0x40070, 0x0 },
+       { 0x40011, 0x708 },
+       { 0x40031, 0x5 },
+       { 0x40051, 0x0 },
+       { 0x40071, 0x2002 },
+       { 0x40012, 0x8 },
+       { 0x40032, 0x80 },
+       { 0x40052, 0x0 },
+       { 0x40072, 0x0 },
+       { 0x40013, 0x2604 },
+       { 0x40033, 0x1a },
+       { 0x40053, 0x0 },
+       { 0x40073, 0x0 },
+       { 0x40014, 0x708 },
+       { 0x40034, 0xa },
+       { 0x40054, 0x0 },
+       { 0x40074, 0x2002 },
+       { 0x40015, 0x4040 },
+       { 0x40035, 0x80 },
+       { 0x40055, 0x0 },
+       { 0x40075, 0x0 },
+       { 0x40016, 0x60a },
+       { 0x40036, 0x15 },
+       { 0x40056, 0x1200 },
+       { 0x40076, 0x0 },
+       { 0x40017, 0x61a },
+       { 0x40037, 0x15 },
+       { 0x40057, 0x1300 },
+       { 0x40077, 0x0 },
+       { 0x40018, 0x60a },
+       { 0x40038, 0x1a },
+       { 0x40058, 0x1200 },
+       { 0x40078, 0x0 },
+       { 0x40019, 0x642 },
+       { 0x40039, 0x1a },
+       { 0x40059, 0x1300 },
+       { 0x40079, 0x0 },
+       { 0x4001a, 0x4808 },
+       { 0x4003a, 0x880 },
+       { 0x4005a, 0x0 },
+       { 0x4007a, 0x0 },
+       { 0x900a4, 0x0 },
+       { 0x900a5, 0x790 },
+       { 0x900a6, 0x11a },
+       { 0x900a7, 0x8 },
+       { 0x900a8, 0x7aa },
+       { 0x900a9, 0x2a },
+       { 0x900aa, 0x10 },
+       { 0x900ab, 0x7b2 },
+       { 0x900ac, 0x2a },
+       { 0x900ad, 0x0 },
+       { 0x900ae, 0x7c8 },
+       { 0x900af, 0x109 },
+       { 0x900b0, 0x10 },
+       { 0x900b1, 0x10 },
+       { 0x900b2, 0x109 },
+       { 0x900b3, 0x10 },
+       { 0x900b4, 0x2a8 },
+       { 0x900b5, 0x129 },
+       { 0x900b6, 0x8 },
+       { 0x900b7, 0x370 },
+       { 0x900b8, 0x129 },
+       { 0x900b9, 0xa },
+       { 0x900ba, 0x3c8 },
+       { 0x900bb, 0x1a9 },
+       { 0x900bc, 0xc },
+       { 0x900bd, 0x408 },
+       { 0x900be, 0x199 },
+       { 0x900bf, 0x14 },
+       { 0x900c0, 0x790 },
+       { 0x900c1, 0x11a },
+       { 0x900c2, 0x8 },
+       { 0x900c3, 0x4 },
+       { 0x900c4, 0x18 },
+       { 0x900c5, 0xe },
+       { 0x900c6, 0x408 },
+       { 0x900c7, 0x199 },
+       { 0x900c8, 0x8 },
+       { 0x900c9, 0x8568 },
+       { 0x900ca, 0x108 },
+       { 0x900cb, 0x18 },
+       { 0x900cc, 0x790 },
+       { 0x900cd, 0x16a },
+       { 0x900ce, 0x8 },
+       { 0x900cf, 0x1d8 },
+       { 0x900d0, 0x169 },
+       { 0x900d1, 0x10 },
+       { 0x900d2, 0x8558 },
+       { 0x900d3, 0x168 },
+       { 0x900d4, 0x70 },
+       { 0x900d5, 0x788 },
+       { 0x900d6, 0x16a },
+       { 0x900d7, 0x1ff8 },
+       { 0x900d8, 0x85a8 },
+       { 0x900d9, 0x1e8 },
+       { 0x900da, 0x50 },
+       { 0x900db, 0x798 },
+       { 0x900dc, 0x16a },
+       { 0x900dd, 0x60 },
+       { 0x900de, 0x7a0 },
+       { 0x900df, 0x16a },
+       { 0x900e0, 0x8 },
+       { 0x900e1, 0x8310 },
+       { 0x900e2, 0x168 },
+       { 0x900e3, 0x8 },
+       { 0x900e4, 0xa310 },
+       { 0x900e5, 0x168 },
+       { 0x900e6, 0xa },
+       { 0x900e7, 0x408 },
+       { 0x900e8, 0x169 },
+       { 0x900e9, 0x6e },
+       { 0x900ea, 0x0 },
+       { 0x900eb, 0x68 },
+       { 0x900ec, 0x0 },
+       { 0x900ed, 0x408 },
+       { 0x900ee, 0x169 },
+       { 0x900ef, 0x0 },
+       { 0x900f0, 0x8310 },
+       { 0x900f1, 0x168 },
+       { 0x900f2, 0x0 },
+       { 0x900f3, 0xa310 },
+       { 0x900f4, 0x168 },
+       { 0x900f5, 0x1ff8 },
+       { 0x900f6, 0x85a8 },
+       { 0x900f7, 0x1e8 },
+       { 0x900f8, 0x68 },
+       { 0x900f9, 0x798 },
+       { 0x900fa, 0x16a },
+       { 0x900fb, 0x78 },
+       { 0x900fc, 0x7a0 },
+       { 0x900fd, 0x16a },
+       { 0x900fe, 0x68 },
+       { 0x900ff, 0x790 },
+       { 0x90100, 0x16a },
+       { 0x90101, 0x8 },
+       { 0x90102, 0x8b10 },
+       { 0x90103, 0x168 },
+       { 0x90104, 0x8 },
+       { 0x90105, 0xab10 },
+       { 0x90106, 0x168 },
+       { 0x90107, 0xa },
+       { 0x90108, 0x408 },
+       { 0x90109, 0x169 },
+       { 0x9010a, 0x58 },
+       { 0x9010b, 0x0 },
+       { 0x9010c, 0x68 },
+       { 0x9010d, 0x0 },
+       { 0x9010e, 0x408 },
+       { 0x9010f, 0x169 },
+       { 0x90110, 0x0 },
+       { 0x90111, 0x8b10 },
+       { 0x90112, 0x168 },
+       { 0x90113, 0x1 },
+       { 0x90114, 0xab10 },
+       { 0x90115, 0x168 },
+       { 0x90116, 0x0 },
+       { 0x90117, 0x1d8 },
+       { 0x90118, 0x169 },
+       { 0x90119, 0x80 },
+       { 0x9011a, 0x790 },
+       { 0x9011b, 0x16a },
+       { 0x9011c, 0x18 },
+       { 0x9011d, 0x7aa },
+       { 0x9011e, 0x6a },
+       { 0x9011f, 0xa },
+       { 0x90120, 0x0 },
+       { 0x90121, 0x1e9 },
+       { 0x90122, 0x8 },
+       { 0x90123, 0x8080 },
+       { 0x90124, 0x108 },
+       { 0x90125, 0xf },
+       { 0x90126, 0x408 },
+       { 0x90127, 0x169 },
+       { 0x90128, 0xc },
+       { 0x90129, 0x0 },
+       { 0x9012a, 0x68 },
+       { 0x9012b, 0x9 },
+       { 0x9012c, 0x0 },
+       { 0x9012d, 0x1a9 },
+       { 0x9012e, 0x0 },
+       { 0x9012f, 0x408 },
+       { 0x90130, 0x169 },
+       { 0x90131, 0x0 },
+       { 0x90132, 0x8080 },
+       { 0x90133, 0x108 },
+       { 0x90134, 0x8 },
+       { 0x90135, 0x7aa },
+       { 0x90136, 0x6a },
+       { 0x90137, 0x0 },
+       { 0x90138, 0x8568 },
+       { 0x90139, 0x108 },
+       { 0x9013a, 0xb7 },
+       { 0x9013b, 0x790 },
+       { 0x9013c, 0x16a },
+       { 0x9013d, 0x1f },
+       { 0x9013e, 0x0 },
+       { 0x9013f, 0x68 },
+       { 0x90140, 0x8 },
+       { 0x90141, 0x8558 },
+       { 0x90142, 0x168 },
+       { 0x90143, 0xf },
+       { 0x90144, 0x408 },
+       { 0x90145, 0x169 },
+       { 0x90146, 0xd },
+       { 0x90147, 0x0 },
+       { 0x90148, 0x68 },
+       { 0x90149, 0x0 },
+       { 0x9014a, 0x408 },
+       { 0x9014b, 0x169 },
+       { 0x9014c, 0x0 },
+       { 0x9014d, 0x8558 },
+       { 0x9014e, 0x168 },
+       { 0x9014f, 0x8 },
+       { 0x90150, 0x3c8 },
+       { 0x90151, 0x1a9 },
+       { 0x90152, 0x3 },
+       { 0x90153, 0x370 },
+       { 0x90154, 0x129 },
+       { 0x90155, 0x20 },
+       { 0x90156, 0x2aa },
+       { 0x90157, 0x9 },
+       { 0x90158, 0x8 },
+       { 0x90159, 0xe8 },
+       { 0x9015a, 0x109 },
+       { 0x9015b, 0x0 },
+       { 0x9015c, 0x8140 },
+       { 0x9015d, 0x10c },
+       { 0x9015e, 0x10 },
+       { 0x9015f, 0x8138 },
+       { 0x90160, 0x104 },
+       { 0x90161, 0x8 },
+       { 0x90162, 0x448 },
+       { 0x90163, 0x109 },
+       { 0x90164, 0xf },
+       { 0x90165, 0x7c0 },
+       { 0x90166, 0x109 },
+       { 0x90167, 0x0 },
+       { 0x90168, 0xe8 },
+       { 0x90169, 0x109 },
+       { 0x9016a, 0x47 },
+       { 0x9016b, 0x630 },
+       { 0x9016c, 0x109 },
+       { 0x9016d, 0x8 },
+       { 0x9016e, 0x618 },
+       { 0x9016f, 0x109 },
+       { 0x90170, 0x8 },
+       { 0x90171, 0xe0 },
+       { 0x90172, 0x109 },
+       { 0x90173, 0x0 },
+       { 0x90174, 0x7c8 },
+       { 0x90175, 0x109 },
+       { 0x90176, 0x8 },
+       { 0x90177, 0x8140 },
+       { 0x90178, 0x10c },
+       { 0x90179, 0x0 },
+       { 0x9017a, 0x478 },
+       { 0x9017b, 0x109 },
+       { 0x9017c, 0x0 },
+       { 0x9017d, 0x1 },
+       { 0x9017e, 0x8 },
+       { 0x9017f, 0x8 },
+       { 0x90180, 0x4 },
+       { 0x90181, 0x0 },
+       { 0x90006, 0x8 },
+       { 0x90007, 0x7c8 },
+       { 0x90008, 0x109 },
+       { 0x90009, 0x0 },
+       { 0x9000a, 0x400 },
+       { 0x9000b, 0x106 },
+       { 0xd00e7, 0x400 },
+       { 0x90017, 0x0 },
+       { 0x9001f, 0x29 },
+       { 0x90026, 0x68 },
+       { 0x400d0, 0x0 },
+       { 0x400d1, 0x101 },
+       { 0x400d2, 0x105 },
+       { 0x400d3, 0x107 },
+       { 0x400d4, 0x10f },
+       { 0x400d5, 0x202 },
+       { 0x400d6, 0x20a },
+       { 0x400d7, 0x20b },
+       { 0x2003a, 0x2 },
+       { 0x200be, 0x3 },
+       { 0x2000b, 0x419 },
+       { 0x2000c, 0xe9 },
+       { 0x2000d, 0x91c },
+       { 0x2000e, 0x2c },
+       { 0x12000b, 0x70 },
+       { 0x12000c, 0x19 },
+       { 0x12000d, 0xfa },
+       { 0x12000e, 0x10 },
+       { 0x22000b, 0x1c },
+       { 0x22000c, 0x6 },
+       { 0x22000d, 0x3e },
+       { 0x22000e, 0x10 },
+       { 0x9000c, 0x0 },
+       { 0x9000d, 0x173 },
+       { 0x9000e, 0x60 },
+       { 0x9000f, 0x6110 },
+       { 0x90010, 0x2152 },
+       { 0x90011, 0xdfbd },
+       { 0x90012, 0x2060 },
+       { 0x90013, 0x6152 },
+       { 0x20010, 0x5a },
+       { 0x20011, 0x3 },
+       { 0x40080, 0xe0 },
+       { 0x40081, 0x12 },
+       { 0x40082, 0xe0 },
+       { 0x40083, 0x12 },
+       { 0x40084, 0xe0 },
+       { 0x40085, 0x12 },
+       { 0x140080, 0xe0 },
+       { 0x140081, 0x12 },
+       { 0x140082, 0xe0 },
+       { 0x140083, 0x12 },
+       { 0x140084, 0xe0 },
+       { 0x140085, 0x12 },
+       { 0x240080, 0xe0 },
+       { 0x240081, 0x12 },
+       { 0x240082, 0xe0 },
+       { 0x240083, 0x12 },
+       { 0x240084, 0xe0 },
+       { 0x240085, 0x12 },
+       { 0x400fd, 0xf },
+       { 0x10011, 0x1 },
+       { 0x10012, 0x1 },
+       { 0x10013, 0x180 },
+       { 0x10018, 0x1 },
+       { 0x10002, 0x6209 },
+       { 0x100b2, 0x1 },
+       { 0x101b4, 0x1 },
+       { 0x102b4, 0x1 },
+       { 0x103b4, 0x1 },
+       { 0x104b4, 0x1 },
+       { 0x105b4, 0x1 },
+       { 0x106b4, 0x1 },
+       { 0x107b4, 0x1 },
+       { 0x108b4, 0x1 },
+       { 0x11011, 0x1 },
+       { 0x11012, 0x1 },
+       { 0x11013, 0x180 },
+       { 0x11018, 0x1 },
+       { 0x11002, 0x6209 },
+       { 0x110b2, 0x1 },
+       { 0x111b4, 0x1 },
+       { 0x112b4, 0x1 },
+       { 0x113b4, 0x1 },
+       { 0x114b4, 0x1 },
+       { 0x115b4, 0x1 },
+       { 0x116b4, 0x1 },
+       { 0x117b4, 0x1 },
+       { 0x118b4, 0x1 },
+       { 0x12011, 0x1 },
+       { 0x12012, 0x1 },
+       { 0x12013, 0x180 },
+       { 0x12018, 0x1 },
+       { 0x12002, 0x6209 },
+       { 0x120b2, 0x1 },
+       { 0x121b4, 0x1 },
+       { 0x122b4, 0x1 },
+       { 0x123b4, 0x1 },
+       { 0x124b4, 0x1 },
+       { 0x125b4, 0x1 },
+       { 0x126b4, 0x1 },
+       { 0x127b4, 0x1 },
+       { 0x128b4, 0x1 },
+       { 0x13011, 0x1 },
+       { 0x13012, 0x1 },
+       { 0x13013, 0x180 },
+       { 0x13018, 0x1 },
+       { 0x13002, 0x6209 },
+       { 0x130b2, 0x1 },
+       { 0x131b4, 0x1 },
+       { 0x132b4, 0x1 },
+       { 0x133b4, 0x1 },
+       { 0x134b4, 0x1 },
+       { 0x135b4, 0x1 },
+       { 0x136b4, 0x1 },
+       { 0x137b4, 0x1 },
+       { 0x138b4, 0x1 },
+       { 0x20089, 0x1 },
+       { 0x20088, 0x19 },
+       { 0xc0080, 0x2 },
+       { 0xd0000, 0x1 }
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+       {
+               /* P0 3733mts 1D */
+               .drate = 3733,
+               .fw_type = FW_1D_IMAGE,
+               .fsp_cfg = ddr_fsp0_cfg,
+               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+       },
+       {
+               /* P1 400mts 1D */
+               .drate = 400,
+               .fw_type = FW_1D_IMAGE,
+               .fsp_cfg = ddr_fsp1_cfg,
+               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+       },
+       {
+               /* P2 100mts 1D */
+               .drate = 100,
+               .fw_type = FW_1D_IMAGE,
+               .fsp_cfg = ddr_fsp2_cfg,
+               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+       },
+       {
+               /* P0 3733mts 2D */
+               .drate = 3733,
+               .fw_type = FW_2D_IMAGE,
+               .fsp_cfg = ddr_fsp0_2d_cfg,
+               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+       },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dmo_imx8mp_sbc_dram_timing_32_32 = {
+       .ddrc_cfg = ddr_ddrc_cfg,
+       .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+       .ddrphy_cfg = ddr_ddrphy_cfg,
+       .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+       .fsp_msg = ddr_dram_fsp_msg,
+       .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+       .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+       .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+       .ddrphy_pie = ddr_phy_pie,
+       .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+       .fsp_table = { 3733, 400, 100, },
+};

diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c
new file mode 100644 (file)
index 0000000..c30185e
--- /dev/null
+++ b/board/data_modul/imx8mp_edm_sbc/spl.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <spl.h>
+
+#include <asm-generic/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/mach-imx/boot_mode.h>
+
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+#include <power/pmic.h>
+#include <power/pca9450.h>
+
+#include "lpddr4_timing.h"
+
+#include "../common/common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int data_modul_imx_edm_sbc_board_power_init(void)
+{
+       struct udevice *dev;
+       int ret;
+
+       ret = pmic_get("pmic@25", &dev);
+       if (ret == -ENODEV) {
+               puts("Failed to get PMIC\n");
+               return 0;
+       }
+       if (ret != 0)
+               return ret;
+
+       /* BUCKxOUT_DVS0/1 control BUCK123 output. */
+       pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+       /* Increase VDD_SOC to typical value 0.95V before first DRAM access. */
+       if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
+               /* Set DVS0 to 0.85V for special case. */
+               pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
+       else
+               pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c);
+
+       /* Set DVS1 to 0.85v for suspend. */
+       pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
+
+       /*
+        * Enable DVS control through PMIC_STBY_REQ and
+        * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H).
+        */
+       pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+       /* Kernel uses OD/OD frequency for SoC. */
+
+       /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */
+       pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c);
+
+       /* Set LDO4 and CONFIG2 to enable the I2C level translator. */
+       pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59);
+       pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
+
+       return 0;
+}
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+       if (boot_dev_spl == SPI_NOR_BOOT)       /* SPI NOR */
+               return BOOT_DEVICE_SPI;
+
+       if (boot_dev_spl == MMC3_BOOT)          /* eMMC */
+               return BOOT_DEVICE_MMC2;
+
+       return BOOT_DEVICE_MMC1;                /* SD */
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+       int boot_device = spl_boot_device();
+
+       spl_boot_list[0] = boot_device;         /* 1:SD 2:eMMC 8:SPI NOR */
+
+       if (boot_device == BOOT_DEVICE_SPI) {           /* SPI, eMMC, SD */
+               spl_boot_list[1] = BOOT_DEVICE_MMC2;    /* eMMC */
+               spl_boot_list[2] = BOOT_DEVICE_MMC1;    /* SD */
+       } else if (boot_device == BOOT_DEVICE_MMC1) {   /* SD, eMMC, SPI */
+               spl_boot_list[1] = BOOT_DEVICE_MMC2;    /* eMMC */
+               spl_boot_list[2] = BOOT_DEVICE_SPI;     /* SPI */
+       } else {                                        /* eMMC, SPI, SD */
+               spl_boot_list[1] = BOOT_DEVICE_SPI;     /* SPI */
+               spl_boot_list[2] = BOOT_DEVICE_MMC1;    /* SD */
+       }
+
+       spl_boot_list[3] = BOOT_DEVICE_UART;    /* YModem */
+       spl_boot_list[4] = BOOT_DEVICE_NONE;
+}
+
+static struct dram_timing_info *dram_timing_info[8] = {
+       &dmo_imx8mp_sbc_dram_timing_32_32,      /* 32 Gbit x32 */
+       NULL,                                   /* 32 Gbit x16 */
+       NULL,                                   /* 16 Gbit x32 */
+       NULL,                                   /* 16 Gbit x16 */
+       NULL,                                   /* 8 Gbit x32 */
+       NULL,                                   /* 8 Gbit x16 */
+       NULL,                                   /* INVALID */
+       NULL,                                   /* INVALID */
+};
+
+void board_init_f(ulong dummy)
+{
+       dmo_board_init_f(MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B, dram_timing_info);
+}

diff --git a/board/emulation/common/qemu_dfu.c b/board/emulation/common/qemu_dfu.c
index 332d659..7e7d84f 100644 (file)
--- a/board/emulation/common/qemu_dfu.c
+++ b/board/emulation/common/qemu_dfu.c
@@ -48,7 +48,7 @@ void set_dfu_alt_info(char *interface, char *devstr)
            env_get("dfu_alt_info"))
                return;
 
-       memset(buf, 0, sizeof(buf));
+       memset(buf, 0, DFU_ALT_BUF_LEN);
 
        /*
         * Currently dfu_alt_info is needed on Qemu ARM64 for

diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 33842d0..2a75205 100644 (file)
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -55,45 +55,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pl01x_serial_plat serial0 = {
-#if CONFIG_CONS_INDEX == 0
-       .base = CFG_SYS_SERIAL0,
-#elif CONFIG_CONS_INDEX == 1
-       .base = CFG_SYS_SERIAL1,
-#else
-#error "Unsupported console index value."
-#endif
-       .type = TYPE_PL011,
-};
-
-U_BOOT_DRVINFO(nxp_serial0) = {
-       .name = "serial_pl01x",
-       .plat = &serial0,
-};
-
-static struct pl01x_serial_plat serial1 = {
-       .base = CFG_SYS_SERIAL1,
-       .type = TYPE_PL011,
-};
-
-U_BOOT_DRVINFO(nxp_serial1) = {
-       .name = "serial_pl01x",
-       .plat = &serial1,
-};
-
-static void uart_get_clock(void)
-{
-       serial0.clock = get_serial_clock();
-       serial1.clock = get_serial_clock();
-}
-
 int board_early_init_f(void)
 {
 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD)
        i2c_early_init_f();
 #endif
-       /* get required clock for UART IP */
-       uart_get_clock();
 
 #ifdef CONFIG_EMC2305
        select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305, 0);

diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README
index 5d5c5e7..34f05f3 100644 (file)
--- a/board/freescale/m53017evb/README
+++ b/board/freescale/m53017evb/README
@@ -87,7 +87,7 @@ CONFIG_SYS_FEC0_PINMUX                -- Set FEC0 Pin configuration
 CONFIG_SYS_FEC0_MIIBASE                -- Set FEC0 MII base register
 MCFFEC_TOUT_LOOP               -- set FEC timeout loop
 
-CFG_MCFTMR                     -- define to use DMA timer
+CONFIG_MCFTMR                  -- define to use DMA timer
 
 CONFIG_SYS_I2C_FSL             -- define to use FSL common I2C driver
 CONFIG_SYS_I2C_SOFT            -- define for I2C bit-banged

diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README
index e8bf75f..7240648 100644 (file)
--- a/board/freescale/m5373evb/README
+++ b/board/freescale/m5373evb/README
@@ -86,7 +86,7 @@ CONFIG_SYS_FEC0_PINMUX                -- Set FEC0 Pin configuration
 CONFIG_SYS_FEC0_MIIBASE        -- Set FEC0 MII base register
 MCFFEC_TOUT_LOOP       -- set FEC timeout loop
 
-CFG_MCFTMR             -- define to use DMA timer
+CONFIG_MCFTMR          -- define to use DMA timer
 
 CONFIG_SYS_I2C_FSL     -- define to use FSL common I2C driver
 CONFIG_SYS_I2C_SOFT    -- define for I2C bit-banged

diff --git a/board/purism/librem5/librem5.c b/board/purism/librem5/librem5.c
index caa0265..386ed1b 100644 (file)
--- a/board/purism/librem5/librem5.c
+++ b/board/purism/librem5/librem5.c
@@ -41,7 +41,7 @@ int board_early_init_f(void)
 #if IS_ENABLED(CONFIG_LOAD_ENV_FROM_MMC_BOOT_PARTITION)
 uint board_mmc_get_env_part(struct mmc *mmc)
 {
-       uint part = (mmc->part_config >> 3) & PART_ACCESS_MASK;
+       uint part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
 
        if (part == 7)
                part = 0;

diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c
index 0ddae95..f38453a 100644 (file)
--- a/board/renesas/rcar-common/common.c
+++ b/board/renesas/rcar-common/common.c
@@ -16,7 +16,7 @@
 #include <asm/arch/rmobile.h>
 #include <linux/libfdt.h>
 
-#ifdef CONFIG_RCAR_GEN3
+#ifdef CONFIG_RCAR_64
 
 DECLARE_GLOBAL_DATA_PTR;
 

diff --git a/board/renesas/spider/Kconfig b/board/renesas/spider/Kconfig
new file mode 100644 (file)
index 0000000..8df2e85
--- /dev/null
+++ b/board/renesas/spider/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SPIDER
+
+config SYS_SOC
+       default "rmobile"
+
+config SYS_BOARD
+       default "spider"
+
+config SYS_VENDOR
+       default "renesas"
+
+config SYS_CONFIG_NAME
+       default "spider"
+
+endif

diff --git a/board/renesas/spider/Makefile b/board/renesas/spider/Makefile
new file mode 100644 (file)
index 0000000..545cb58
--- /dev/null
+++ b/board/renesas/spider/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/spider/Makefile
+#
+# Copyright (C) 2020 Renesas Electronics Corp.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := spider.o ../rcar-common/common.o

diff --git a/board/renesas/spider/spider.c b/board/renesas/spider/spider.c
new file mode 100644 (file)
index 0000000..caf88dc
--- /dev/null
+++ b/board/renesas/spider/spider.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board/renesas/spider/spider.c
+ *     This file is Spider board support.
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <common.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <linux/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void init_generic_timer(void)
+{
+       const u32 freq = CONFIG_SYS_CLK_FREQ;
+
+       /* Update memory mapped and register based freqency */
+       asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
+       writel(freq, CNTFID0);
+
+       /* Enable counter */
+       setbits_le32(CNTCR_BASE, CNTCR_EN);
+}
+
+static void init_gic_v3(void)
+{
+        /* GIC v3 power on */
+       writel(BIT(1), GICR_LPI_PWRR);
+
+       /* Wait till the WAKER_CA_BIT changes to 0 */
+       clrbits_le32(GICR_LPI_WAKER, BIT(1));
+       while (readl(GICR_LPI_WAKER) & BIT(2))
+               ;
+
+       writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
+}
+
+void s_init(void)
+{
+       if (current_el() == 3)
+               init_generic_timer();
+}
+
+int board_early_init_f(void)
+{
+       /* Unlock CPG access */
+       writel(0x5A5AFFFF, CPGWPR);
+       writel(0xA5A50000, CPGWPCR);
+
+       return 0;
+}
+
+int board_init(void)
+{
+       if (current_el() == 3)
+               init_gic_v3();
+
+       return 0;
+}
+
+void reset_cpu(void)
+{
+       writel(RST_SPRES, RST_SRESCR0);
+}

diff --git a/board/renesas/whitehawk/Kconfig b/board/renesas/whitehawk/Kconfig
new file mode 100644 (file)
index 0000000..05a8789
--- /dev/null
+++ b/board/renesas/whitehawk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_WHITEHAWK
+
+config SYS_SOC
+       default "rmobile"
+
+config SYS_BOARD
+       default "whitehawk"
+
+config SYS_VENDOR
+       default "renesas"
+
+config SYS_CONFIG_NAME
+       default "whitehawk"
+
+endif

diff --git a/board/renesas/whitehawk/Makefile b/board/renesas/whitehawk/Makefile
new file mode 100644 (file)
index 0000000..ed5bdc0
--- /dev/null
+++ b/board/renesas/whitehawk/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/whitehawk/Makefile
+#
+# Copyright (C) 2021 Renesas Electronics Corp.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := whitehawk.o ../rcar-common/common.o

diff --git a/board/renesas/whitehawk/whitehawk.c b/board/renesas/whitehawk/whitehawk.c
new file mode 100644 (file)
index 0000000..19f09e0
--- /dev/null
+++ b/board/renesas/whitehawk/whitehawk.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board/renesas/whitehawk/whitehawk.c
+ *     This file is White Hawk board support.
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <common.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/processor.h>
+#include <linux/errno.h>
+#include <asm/system.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void init_generic_timer(void)
+{
+       const u32 freq = CONFIG_SYS_CLK_FREQ;
+
+       /* Update memory mapped and register based freqency */
+       asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
+       writel(freq, CNTFID0);
+
+       /* Enable counter */
+       setbits_le32(CNTCR_BASE, CNTCR_EN);
+}
+
+static void init_gic_v3(void)
+{
+        /* GIC v3 power on */
+       writel(BIT(1), GICR_LPI_PWRR);
+
+       /* Wait till the WAKER_CA_BIT changes to 0 */
+       clrbits_le32(GICR_LPI_WAKER, BIT(1));
+       while (readl(GICR_LPI_WAKER) & BIT(2))
+               ;
+
+       writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
+}
+
+void s_init(void)
+{
+       if (current_el() == 3)
+               init_generic_timer();
+}
+
+int board_early_init_f(void)
+{
+       /* Unlock CPG access */
+       writel(0x5A5AFFFF, CPGWPR);
+       writel(0xA5A50000, CPGWPCR);
+
+       return 0;
+}
+
+int board_init(void)
+{
+       if (current_el() == 3)
+               init_gic_v3();
+
+       return 0;
+}
+
+void reset_cpu(void)
+{
+       writel(RST_SPRES, RST_SRESCR0);
+}

diff --git a/board/rockchip/evb_rk3588/Kconfig b/board/rockchip/evb_rk3588/Kconfig
new file mode 100644 (file)
index 0000000..d38efe6
--- /dev/null
+++ b/board/rockchip/evb_rk3588/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3588
+
+config SYS_BOARD
+       default "evb_rk3588"
+
+config SYS_VENDOR
+       default "rockchip"
+
+config SYS_CONFIG_NAME
+       default "evb_rk3588"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+       def_bool y
+
+endif

diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS
new file mode 100644 (file)
index 0000000..7b7df3c
--- /dev/null
+++ b/board/rockchip/evb_rk3588/MAINTAINERS
@@ -0,0 +1,7 @@
+EVB-RK3588
+M:     Kever Yang <kever.yang@rock-chips.com>
+S:     Maintained
+F:     board/rockchip/evb_rk3588
+F:     include/configs/evb_rk3588.h
+F:     configs/evb-rk3588_defconfig
+F:     arch/arm/dts/rk3588-evb-u-boot.dtsi

diff --git a/board/rockchip/evb_rk3588/Makefile b/board/rockchip/evb_rk3588/Makefile
new file mode 100644 (file)
index 0000000..240d2ec
--- /dev/null
+++ b/board/rockchip/evb_rk3588/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier:     GPL-2.0+
+#
+# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
+#
+
+obj-y += evb-rk3588.o

diff --git a/board/rockchip/evb_rk3588/evb-rk3588.c b/board/rockchip/evb_rk3588/evb-rk3588.c
new file mode 100644 (file)
index 0000000..caf94d8
--- /dev/null
+++ b/board/rockchip/evb_rk3588/evb-rk3588.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
+ */
+
+#include <fdtdec.h>
+#include <fdt_support.h>
+
+#ifdef CONFIG_OF_BOARD_SETUP
+static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob)
+{
+       struct fdt_memory gap1 = {
+               .start = 0x3fc000000,
+               .end = 0x3fc4fffff,
+       };
+       struct fdt_memory gap2 = {
+               .start = 0x3fff00000,
+               .end = 0x3ffffffff,
+       };
+       unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
+       unsigned int ret;
+
+       /*
+        * Inject the reserved-memory nodes into the DTS
+        */
+       ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1,  NULL, 0,
+                                        NULL, flags);
+       if (ret)
+               return ret;
+
+       return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2,  NULL, 0,
+                                         NULL, flags);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+       return rk3588_add_reserved_memory_fdt_nodes(blob);
+}
+#endif

diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c
index df705b7..2653e10 100644 (file)
--- a/board/siemens/iot2050/board.c
+++ b/board/siemens/iot2050/board.c
@@ -21,7 +21,6 @@
 #include <spl.h>
 #include <version.h>
 #include <linux/delay.h>
-#include <asm/arch/sys_proto.h>
 #include <asm/arch/hardware.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
@@ -482,19 +481,10 @@ fixup_error:
 
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
-       int ret;
-
-       ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
-       if (ret < 0)
-               ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
-                                        "sram@70000000");
-       if (ret)
-               pr_err("%s: fixing up msmc ram failed %d\n", __func__, ret);
-
        if (board_is_m2())
                m2_fdt_fixup(blob);
 
-       return ret;
+       return 0;
 }
 #endif
 

diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index ca8f025..1a1b184 100644 (file)
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -872,7 +872,7 @@ int mmc_get_boot(void)
                STM32_SDMMC3_BASE
        };
 
-       if (instance > ARRAY_SIZE(sdmmc_addr))
+       if (instance >= ARRAY_SIZE(sdmmc_addr))
                return 0;
 
        /* search associated sdmmc node in devicetree */

diff --git a/board/starfive/visionfive2/Kconfig b/board/starfive/visionfive2/Kconfig
new file mode 100644 (file)
index 0000000..2186a93
--- /dev/null
+++ b/board/starfive/visionfive2/Kconfig
@@ -0,0 +1,53 @@
+if TARGET_STARFIVE_VISIONFIVE2
+
+config SYS_CPU
+       default "jh7110"
+
+config SYS_BOARD
+       default "visionfive2"
+
+config SYS_VENDOR
+       default "starfive"
+
+config SYS_CONFIG_NAME
+       default "starfive-visionfive2"
+
+config TEXT_BASE
+       default 0x40200000 if SPL
+       default 0x40000000 if !RISCV_SMODE
+       default 0x40200000 if RISCV_SMODE
+
+config SPL_TEXT_BASE
+       default 0x08000000
+
+config SPL_OPENSBI_LOAD_ADDR
+       default 0x80000000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+       def_bool y
+       select STARFIVE_JH7110
+       select SUPPORT_SPL
+       select BINMAN
+       imply CMD_CPU
+       imply CMD_DHCP
+       imply CMD_EXT2
+       imply CMD_EXT4
+       imply CMD_FAT
+       imply CMD_FS_GENERIC
+       imply CMD_GPIO
+       imply CMD_GPT
+       imply CMD_MMC
+       imply CMD_NET
+       imply CMD_PING
+       imply CMD_SF
+       imply DM_GPIO
+       imply DOS_PARTITION
+       imply EFI_PARTITION
+       imply MII
+       imply IP_DYN
+       imply ISO_PARTITION
+       imply PARTITION_TYPE_GUID
+       imply PHY_LIB
+       imply PHY_MSCC
+
+endif

diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS
new file mode 100644 (file)
index 0000000..c536908
--- /dev/null
+++ b/board/starfive/visionfive2/MAINTAINERS
@@ -0,0 +1,7 @@
+STARFIVE JH7110 VISIONFIVE2 BOARD
+M: startfive
+S:     Maintained
+F:     arch/riscv/include/asm/arch-jh7110/
+F:     board/starfive/visionfive2/
+F:     include/configs/starfive-visionfive2.h
+F:     configs/starfive_visionfive2_defconfig

diff --git a/board/starfive/visionfive2/Makefile b/board/starfive/visionfive2/Makefile
new file mode 100644 (file)
index 0000000..66c854d
--- /dev/null
+++ b/board/starfive/visionfive2/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+#
+
+obj-y  := starfive_visionfive2.o
+obj-$(CONFIG_SPL_BUILD) += spl.o

diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
new file mode 100644 (file)
index 0000000..db0b4cb
--- /dev/null
+++ b/board/starfive/visionfive2/spl.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/arch/regs.h>
+#include <asm/arch/spl.h>
+#include <asm/io.h>
+#include <log.h>
+#include <spl.h>
+
+#define JH7110_CLK_CPU_ROOT_OFFSET             0x0U
+#define JH7110_CLK_CPU_ROOT_SHIFT              24
+#define JH7110_CLK_CPU_ROOT_MASK               GENMASK(29, 24)
+
+int spl_board_init_f(void)
+{
+       int ret;
+
+       ret = spl_soc_init();
+       if (ret) {
+               debug("JH7110 SPL init failed: %d\n", ret);
+               return ret;
+       }
+
+       return 0;
+}
+
+u32 spl_boot_device(void)
+{
+       u32 mode;
+
+       mode = in_le32(JH7110_BOOT_MODE_SELECT_REG)
+                               & JH7110_BOOT_MODE_SELECT_MASK;
+       switch (mode) {
+       case 0:
+               return BOOT_DEVICE_SPI;
+
+       case 1:
+               return BOOT_DEVICE_MMC2;
+
+       case 2:
+               return BOOT_DEVICE_MMC1;
+
+       case 3:
+               return BOOT_DEVICE_UART;
+
+       default:
+               debug("Unsupported boot device 0x%x.\n", mode);
+               return BOOT_DEVICE_NONE;
+       }
+}
+
+void board_init_f(ulong dummy)
+{
+       int ret;
+
+       ret = spl_early_init();
+       if (ret)
+               panic("spl_early_init() failed: %d\n", ret);
+
+       riscv_cpu_setup(NULL, NULL);
+       preloader_console_init();
+
+       /* Set the parent clock of cpu_root clock to pll0,
+        * it must be initialized here
+        */
+       clrsetbits_le32(JH7110_SYS_CRG + JH7110_CLK_CPU_ROOT_OFFSET,
+                       JH7110_CLK_CPU_ROOT_MASK,
+                       BIT(JH7110_CLK_CPU_ROOT_SHIFT));
+
+       ret = spl_board_init_f();
+       if (ret) {
+               debug("spl_board_init_f init failed: %d\n", ret);
+               return;
+       }
+}
+
+#if CONFIG_IS_ENABLED(SPL_LOAD_FIT)
+int board_fit_config_name_match(const char *name)
+{
+       /* boot using first FIT config */
+       return 0;
+}
+#endif

diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c
new file mode 100644 (file)
index 0000000..613fe79
--- /dev/null
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <cpu_func.h>
+#include <linux/bitops.h>
+
+#define JH7110_L2_PREFETCHER_BASE_ADDR         0x2030000
+#define JH7110_L2_PREFETCHER_HART_OFFSET       0x2000
+
+/* enable U74-mc hart1~hart4 prefetcher */
+static void enable_prefetcher(void)
+{
+       u8 hart;
+       u32 *reg;
+
+       /* JH7110 use U74MC CORE IP, it include five cores(one S7 and four U7),
+        * but only U7 cores support prefetcher configuration
+        */
+       for (hart = 1; hart < 5; hart++) {
+               reg = (void *)(u64)(JH7110_L2_PREFETCHER_BASE_ADDR
+                                       + hart * JH7110_L2_PREFETCHER_HART_OFFSET);
+
+               mb(); /* memory barrier */
+               setbits_le32(reg, 0x1);
+               mb(); /* memory barrier */
+       }
+}
+
+int board_init(void)
+{
+       enable_caches();
+       enable_prefetcher();
+
+       return 0;
+}

diff --git a/board/theobroma-systems/puma_rk3399/Kconfig b/board/theobroma-systems/puma_rk3399/Kconfig
index 15af555..cc745f5 100644 (file)
--- a/board/theobroma-systems/puma_rk3399/Kconfig
+++ b/board/theobroma-systems/puma_rk3399/Kconfig
@@ -11,6 +11,7 @@ config SYS_CONFIG_NAME
 
 config BOARD_SPECIFIC_OPTIONS # dummy
        def_bool y
+       select ENV_IS_NOWHERE
 
 config ENV_SIZE
        default 0x4000

diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
index 97f398b..614a60e 100644 (file)
--- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c
+++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
@@ -136,10 +136,6 @@ int mmc_get_env_dev(void)
        return CONFIG_SYS_MMC_ENV_DEV;
 }
 
-#if !IS_ENABLED(CONFIG_ENV_IS_NOWHERE)
-#error Please enable CONFIG_ENV_IS_NOWHERE
-#endif
-
 enum env_location arch_env_get_location(enum env_operation op, int prio)
 {
        const char *boot_device =

diff --git a/board/theobroma-systems/ringneck_px30/Kconfig b/board/theobroma-systems/ringneck_px30/Kconfig
index 24d9480..c33253b 100644 (file)
--- a/board/theobroma-systems/ringneck_px30/Kconfig
+++ b/board/theobroma-systems/ringneck_px30/Kconfig
@@ -11,6 +11,7 @@ config SYS_CONFIG_NAME
 
 config BOARD_SPECIFIC_OPTIONS # dummy
        def_bool y
+       select ENV_IS_NOWHERE
 
 config ENV_SIZE
        default 0x3000

diff --git a/board/theobroma-systems/ringneck_px30/ringneck-px30.c b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
index 47d1a40..bb1bb4a 100644 (file)
--- a/board/theobroma-systems/ringneck_px30/ringneck-px30.c
+++ b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
@@ -118,10 +118,6 @@ int mmc_get_env_dev(void)
        return CONFIG_SYS_MMC_ENV_DEV;
 }
 
-#if !IS_ENABLED(CONFIG_ENV_IS_NOWHERE)
-#error Please enable CONFIG_ENV_IS_NOWHERE
-#endif
-
 enum env_location arch_env_get_location(enum env_operation op, int prio)
 {
        const char *boot_device =

diff --git a/board/ti/am62ax/evm.c b/board/ti/am62ax/evm.c
index beef3f2..f2dd3b4 100644 (file)
--- a/board/ti/am62ax/evm.c
+++ b/board/ti/am62ax/evm.c
@@ -7,7 +7,6 @@
  */
 
 #include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <common.h>
 #include <dm/uclass.h>

diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c
index 20b2a70..034fbed 100644 (file)
--- a/board/ti/am62x/evm.c
+++ b/board/ti/am62x/evm.c
@@ -15,7 +15,6 @@
 #include <fdt_support.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
 #include <dm/uclass.h>
 
 DECLARE_GLOBAL_DATA_PTR;

diff --git a/board/ti/am64x/am64x.env b/board/ti/am64x/am64x.env
new file mode 100644 (file)
index 0000000..c3960be
--- /dev/null
+++ b/board/ti/am64x/am64x.env
@@ -0,0 +1,63 @@
+#include <environment/ti/ti_armv7_common.env>
+#include <environment/ti/mmc.env>
+#include <environment/ti/k3_dfu.env>
+
+findfdt=
+       if test $board_name = am64x_gpevm; then
+               setenv name_fdt k3-am642-evm.dtb; fi;
+       if test $board_name = am64x_skevm; then
+               setenv name_fdt k3-am642-sk.dtb; fi;
+       if test $name_fdt = undefined; then
+               echo WARNING: Could not determine device tree to use; fi;
+name_kern=Image
+console=ttyS2,115200n8
+args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 ${mtdparts}
+run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+
+boot=mmc
+mmcdev=1
+bootpart=1:2
+bootdir=/boot
+rd_spec=-
+init_mmc=run args_all args_mmc
+get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}
+get_overlay_mmc=
+       fdt address ${fdtaddr};
+       fdt resize 0x100000;
+       for overlay in $name_overlays;
+       do;
+       load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} &&
+       fdt apply ${dtboaddr};
+       done;
+get_kern_mmc=load mmc ${bootpart} ${loadaddr}
+       ${bootdir}/${name_kern}
+get_fit_mmc=load mmc ${bootpart} ${addr_fit}
+       ${bootdir}/${name_fit}
+partitions=name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}
+
+args_usb=run finduuid;setenv bootargs console=${console}
+       ${optargs}
+       root=PARTUUID=${uuid} rw
+       rootfstype=${mmcrootfstype}
+init_usb=run args_all args_usb
+get_fdt_usb=load usb ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}
+get_overlay_usb=
+       fdt address ${fdtaddr};
+       fdt resize 0x100000;
+       for overlay in $name_overlays;
+       do;
+       load usb ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && fdt apply
+       ${dtboaddr};
+       done;
+get_kern_usb=load usb ${bootpart} ${loadaddr}
+       ${bootdir}/${name_kern}
+get_fit_usb=load usb ${bootpart} ${addr_fit}
+       ${bootdir}/${name_fit}
+usbboot=setenv boot usb;
+       setenv bootpart 0:2;
+       usb start;
+       run findfdt;
+       run init_usb;
+       run get_kern_usb;
+       run get_fdt_usb;
+       run run_kern;

diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c
index c88139a..b63792e 100644 (file)
--- a/board/ti/am64x/evm.c
+++ b/board/ti/am64x/evm.c
@@ -14,7 +14,6 @@
 #include <spl.h>
 #include <fdt_support.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
 #include <env.h>
 
 #include "../common/board_detect.h"

diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index b266ccb..706b219 100644 (file)
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -13,7 +13,6 @@
 #include <image.h>
 #include <init.h>
 #include <net.h>
-#include <asm/arch/sys_proto.h>
 #include <asm/arch/hardware.h>
 #include <asm/global_data.h>
 #include <asm/gpio.h>
@@ -21,7 +20,6 @@
 #include <asm/omap_common.h>
 #include <env.h>
 #include <spl.h>
-#include <asm/arch/sys_proto.h>
 
 #include "../common/board_detect.h"
 
@@ -101,24 +99,6 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-       int ret;
-
-       ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
-       if (ret < 0)
-               ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
-                                        "sram@70000000");
-       if (ret) {
-               printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
-               return ret;
-       }
-
-       return 0;
-}
-#endif
-
 #ifdef CONFIG_TI_I2C_BOARD_DETECT
 int do_board_detect(void)
 {

diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig
index f03357c..49edd98 100644 (file)
--- a/board/ti/common/Kconfig
+++ b/board/ti/common/Kconfig
@@ -1,6 +1,5 @@
 config TI_I2C_BOARD_DETECT
        bool "Support for Board detection for TI platforms"
-       select K3_BOARD_DETECT if ARCH_K3
        help
           Support for detection board information on Texas Instrument's
           Evaluation Boards which have I2C based EEPROM detection

diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index d4e672a..2398bea 100644 (file)
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -15,13 +15,11 @@
 #include <init.h>
 #include <log.h>
 #include <net.h>
-#include <asm/arch/sys_proto.h>
 #include <asm/arch/hardware.h>
 #include <asm/global_data.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <spl.h>
-#include <asm/arch/sys_proto.h>
 #include <dm.h>
 #include <dm/uclass-internal.h>
 
@@ -144,18 +142,9 @@ void spl_perform_fixups(struct spl_image_info *spl_image)
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
-       int ret;
-
-       ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
-       if (ret < 0)
-               ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
-                                        "sram@70000000");
-       if (ret)
-               printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
-
        detect_enable_hyperflash(blob);
 
-       return ret;
+       return 0;
 }
 #endif
 

diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env
index 446395a..c181741 100644 (file)
--- a/board/ti/j721e/j721e.env
+++ b/board/ti/j721e/j721e.env
@@ -12,6 +12,8 @@ findfdt=
        setenv name_fdt ${default_device_tree};
        if test $board_name = j721e; then
                setenv name_fdt k3-j721e-common-proc-board.dtb; fi;
+       if test $board_name = j7200; then
+               setenv name_fdt k3-j7200-common-proc-board.dtb; fi;
        if test $board_name = j721e-eaik || test $board_name = j721e-sk; then
                setenv name_fdt k3-j721e-sk.dtb; fi;
        setenv fdtfile ${name_fdt}
@@ -21,7 +23,6 @@ args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000
        ${mtdparts}
 run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
 
-#if CONFIG_SYS_K3_SPL_ATF
 #if CONFIG_TARGET_J721E_R5_EVM
 addr_mcur5f0_0load=0x89000000
 name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw
@@ -29,7 +30,6 @@ name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw
 addr_mcur5f0_0load=0x89000000
 name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw
 #endif
-#endif
 
 boot=mmc
 mmcdev=1

diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index c86715f..09d2688 100644 (file)
--- a/board/ti/j721s2/evm.c
+++ b/board/ti/j721s2/evm.c
@@ -15,12 +15,10 @@
 #include <init.h>
 #include <log.h>
 #include <net.h>
-#include <asm/arch/sys_proto.h>
 #include <asm/arch/hardware.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <spl.h>
-#include <asm/arch/sys_proto.h>
 #include <dm.h>
 #include <dm/uclass-internal.h>
 #include <dm/root.h>
@@ -73,22 +71,6 @@ int dram_init_banksize(void)
        return 0;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-       int ret;
-
-       ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
-       if (ret < 0)
-               ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
-                                        "sram@70000000");
-       if (ret)
-               printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
-
-       return ret;
-}
-#endif
-
 #ifdef CONFIG_TI_I2C_BOARD_DETECT
 /*
  * Functions specific to EVM and SK designs of J721S2/AM68 family.
@@ -208,66 +190,3 @@ int board_late_init(void)
 void spl_board_init(void)
 {
 }
-
-/* Support for the various EVM / SK families */
-#if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT)
-void do_dt_magic(void)
-{
-       int ret, rescan, mmc_dev = -1;
-       static struct mmc *mmc;
-
-       do_board_detect();
-
-       /*
-        * Board detection has been done.
-        * Let us see if another dtb wouldn't be a better match
-        * for our board
-        */
-       if (IS_ENABLED(CONFIG_CPU_V7R)) {
-               ret = fdtdec_resetup(&rescan);
-               if (!ret && rescan) {
-                       dm_uninit();
-                       dm_init_and_scan(true);
-               }
-       }
-
-       /*
-        * Because of multi DTB configuration, the MMC device has
-        * to be re-initialized after reconfiguring FDT inorder to
-        * boot from MMC. Do this when boot mode is MMC and ROM has
-        * not loaded SYSFW.
-        */
-       switch (spl_boot_device()) {
-       case BOOT_DEVICE_MMC1:
-               mmc_dev = 0;
-               break;
-       case BOOT_DEVICE_MMC2:
-       case BOOT_DEVICE_MMC2_2:
-               mmc_dev = 1;
-               break;
-       }
-
-       if (mmc_dev > 0 && !check_rom_loaded_sysfw()) {
-               ret = mmc_init_device(mmc_dev);
-               if (!ret) {
-                       mmc = find_mmc_device(mmc_dev);
-                       if (mmc) {
-                               ret = mmc_init(mmc);
-                               if (ret)
-                                       printf("mmc init failed with error: %d\n", ret);
-                       }
-               }
-       }
-}
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-void board_init_f(ulong dummy)
-{
-       k3_spl_init();
-#if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT)
-       do_dt_magic();
-#endif
-       k3_mem_init();
-}
-#endif

diff --git a/board/ti/j721s2/j721s2.env b/board/ti/j721s2/j721s2.env
index 2152f88..f446777 100644 (file)
--- a/board/ti/j721s2/j721s2.env
+++ b/board/ti/j721s2/j721s2.env
@@ -25,12 +25,10 @@ boot=mmc
 mmcdev=1
 bootpart=1:2
 bootdir=/boot
-#if CONFIG_SYS_K3_SPL_ATF
 #if CONFIG_TARGET_J721S2_R5_EVM
 addr_mcur5f0_0load=0x89000000
 name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw
 #endif
-#endif
 rd_spec=-
 init_mmc=run args_all args_mmc
 get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}

diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
index 6007f11..48fdb1e 100644 (file)
--- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
+++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
@@ -212,17 +212,6 @@ int checkboard(void)
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
-#if defined(CONFIG_FDT_FIXUP_PARTITIONS)
-       static struct node_info nodes[] = {
-               { "fsl,imx6ull-gpmi-nand", MTD_DEV_TYPE_NAND, },
-               { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
-       };
-
-       /* Update partition nodes using info from mtdparts env var */
-       puts("   Updating MTD partitions...\n");
-       fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
-#endif
-
        return ft_common_board_setup(blob, bd);
 }
 #endif

diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c
index 6ce4fa3..3e79ab9 100644 (file)
--- a/board/toradex/colibri_imx7/colibri_imx7.c
+++ b/board/toradex/colibri_imx7/colibri_imx7.c
@@ -303,16 +303,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
                        fdt_status_disabled(blob, off);
        }
 #endif
-#if defined(CONFIG_FDT_FIXUP_PARTITIONS)
-       static const struct node_info nodes[] = {
-               { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
-               { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
-       };
-
-       /* Update partition nodes using info from mtdparts env var */
-       puts("   Updating MTD partitions...\n");
-       fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
-#endif
 
        return ft_common_board_setup(blob, bd);
 }

diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.c b/board/toradex/verdin-imx8mp/lpddr4_timing.c
index 3e00d9b..29ea31e 100644 (file)
--- a/board/toradex/verdin-imx8mp/lpddr4_timing.c
+++ b/board/toradex/verdin-imx8mp/lpddr4_timing.c
@@ -13,6 +13,33 @@
 
 #include <linux/kernel.h>
 #include <asm/arch/ddr.h>
+#include "lpddr4_timing.h"
+
+struct dram_cfg_param ddr_ddrc_cfg_single_rank_patch[] = {
+       { 0x3d400000, 0xa1080020},
+       { 0x3d400200, 0x1f},
+       { 0x3d40021c, 0xf07}
+};
+
+struct dram_cfg_param ddr_fsp0_cfg_single_rank_patch[] = {
+       { 0x54012, 0x110},
+       { 0x5402c, 0x1}
+};
+
+struct dram_cfg_param ddr_fsp1_cfg_single_rank_patch[] = {
+       { 0x54012, 0x110},
+       { 0x5402c, 0x1}
+};
+
+struct dram_cfg_param ddr_fsp2_cfg_single_rank_patch[] = {
+       { 0x54012, 0x110},
+       { 0x5402c, 0x1}
+};
+
+struct dram_cfg_param ddr_fsp0_2d_cfg_single_rank_patch[] = {
+       { 0x54012, 0x110},
+       { 0x5402c, 0x1}
+};
 
 struct dram_cfg_param ddr_ddrc_cfg[] = {
        /** Initialize DDRC registers **/
@@ -21,9 +48,9 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d400000, 0xa3080020 },
        { 0x3d400020, 0x1303 },
        { 0x3d400024, 0x1e84800 },
-       { 0x3d400064, 0x7a0118 },
-       { 0x3d400070, 0x61027f10 },
-       { 0x3d400074, 0x7b0 },
+       { 0x3d400064, 0x7a017c },
+       { 0x3d400070, 0x7027f90 },
+       { 0x3d400074, 0x790 },
        { 0x3d4000d0, 0xc00307a3 },
        { 0x3d4000d4, 0xc50000 },
        { 0x3d4000dc, 0xf4003f },
@@ -31,15 +58,15 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d4000e8, 0x660048 },
        { 0x3d4000ec, 0x160048 },
        { 0x3d400100, 0x2028222a },
-       { 0x3d400104, 0x807bf },
+       { 0x3d400104, 0x8083f },
        { 0x3d40010c, 0xe0e000 },
        { 0x3d400110, 0x12040a12 },
        { 0x3d400114, 0x2050f0f },
        { 0x3d400118, 0x1010009 },
-       { 0x3d40011c, 0x501 },
+       { 0x3d40011c, 0x502 },
        { 0x3d400130, 0x20800 },
        { 0x3d400134, 0xe100002 },
-       { 0x3d400138, 0x120 },
+       { 0x3d400138, 0x184 },
        { 0x3d400144, 0xc80064 },
        { 0x3d400180, 0x3e8001e },
        { 0x3d400184, 0x3207a12 },
@@ -53,15 +80,16 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d4001b0, 0x11 },
        { 0x3d4001c0, 0x1 },
        { 0x3d4001c4, 0x1 },
-       { 0x3d4000f4, 0xc99 },
-       { 0x3d400108, 0x9121c1c },
-       { 0x3d400200, 0x18 },
+       { 0x3d4000f4, 0x799 },
+       { 0x3d400108, 0x9121b1c },
+       { 0x3d400200, 0x17 },
+       { 0x3d400208, 0x0 },
        { 0x3d40020c, 0x0 },
        { 0x3d400210, 0x1f1f },
        { 0x3d400204, 0x80808 },
        { 0x3d400214, 0x7070707 },
        { 0x3d400218, 0x7070707 },
-       { 0x3d40021c, 0xf07 },
+       { 0x3d40021c, 0xf08 },
        { 0x3d400250, 0x1705 },
        { 0x3d400254, 0x2c },
        { 0x3d40025c, 0x4000030 },
@@ -77,7 +105,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d402020, 0x1001 },
        { 0x3d402024, 0x30d400 },
        { 0x3d402050, 0x20d000 },
-       { 0x3d402064, 0xc001c },
+       { 0x3d402064, 0xc0026 },
        { 0x3d4020dc, 0x840000 },
        { 0x3d4020e0, 0x330000 },
        { 0x3d4020e8, 0x660048 },
@@ -89,20 +117,20 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d402110, 0x2040202 },
        { 0x3d402114, 0x2030202 },
        { 0x3d402118, 0x1010004 },
-       { 0x3d40211c, 0x301 },
+       { 0x3d40211c, 0x302 },
        { 0x3d402130, 0x20300 },
        { 0x3d402134, 0xa100002 },
-       { 0x3d402138, 0x1d },
+       { 0x3d402138, 0x27 },
        { 0x3d402144, 0x14000a },
        { 0x3d402180, 0x640004 },
        { 0x3d402190, 0x3818200 },
        { 0x3d402194, 0x80303 },
        { 0x3d4021b4, 0x100 },
-       { 0x3d4020f4, 0xc99 },
+       { 0x3d4020f4, 0x599 },
        { 0x3d403020, 0x1001 },
        { 0x3d403024, 0xc3500 },
        { 0x3d403050, 0x20d000 },
-       { 0x3d403064, 0x30007 },
+       { 0x3d403064, 0x3000a },
        { 0x3d4030dc, 0x840000 },
        { 0x3d4030e0, 0x330000 },
        { 0x3d4030e8, 0x660048 },
@@ -114,16 +142,16 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d403110, 0x2040202 },
        { 0x3d403114, 0x2030202 },
        { 0x3d403118, 0x1010004 },
-       { 0x3d40311c, 0x301 },
+       { 0x3d40311c, 0x302 },
        { 0x3d403130, 0x20300 },
        { 0x3d403134, 0xa100002 },
-       { 0x3d403138, 0x8 },
+       { 0x3d403138, 0xa },
        { 0x3d403144, 0x50003 },
        { 0x3d403180, 0x190004 },
        { 0x3d403190, 0x3818200 },
        { 0x3d403194, 0x80303 },
        { 0x3d4031b4, 0x100 },
-       { 0x3d4030f4, 0xc99 },
+       { 0x3d4030f4, 0x599 },
        { 0x3d400028, 0x0 },
 };
 
@@ -1700,15 +1728,15 @@ struct dram_cfg_param ddr_phy_pie[] = {
        { 0x400d7, 0x20b },
        { 0x2003a, 0x2 },
        { 0x200be, 0x3 },
-       { 0x2000b, 0x7d },
+       { 0x2000b, 0x465 },
        { 0x2000c, 0xfa },
        { 0x2000d, 0x9c4 },
        { 0x2000e, 0x2c },
-       { 0x12000b, 0xc },
+       { 0x12000b, 0x70 },
        { 0x12000c, 0x19 },
        { 0x12000d, 0xfa },
        { 0x12000e, 0x10 },
-       { 0x22000b, 0x3 },
+       { 0x22000b, 0x1c },
        { 0x22000c, 0x6 },
        { 0x22000d, 0x3e },
        { 0x22000e, 0x10 },
@@ -1834,311 +1862,7 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = {
        },
 };
 
-struct dram_cfg_param ddr_ddrc_cfg2[] = {
-       /** Initialize DDRC registers **/
-       { 0x3d400304, 0x1 },
-       { 0x3d400030, 0x1 },
-       { 0x3d400000, 0xa1080020 },
-       { 0x3d400020, 0x1303 },
-       { 0x3d400024, 0x1e84800 },
-       { 0x3d400064, 0x7a0118 },
-       { 0x3d400070, 0x61027f10 },
-       { 0x3d400074, 0x7b0 },
-       { 0x3d4000d0, 0xc00307a3 },
-       { 0x3d4000d4, 0xc50000 },
-       { 0x3d4000dc, 0xf4003f },
-       { 0x3d4000e0, 0x330000 },
-       { 0x3d4000e8, 0x660048 },
-       { 0x3d4000ec, 0x160048 },
-       { 0x3d400100, 0x2028222a },
-       { 0x3d400104, 0x807bf },
-       { 0x3d40010c, 0xe0e000 },
-       { 0x3d400110, 0x12040a12 },
-       { 0x3d400114, 0x2050f0f },
-       { 0x3d400118, 0x1010009 },
-       { 0x3d40011c, 0x501 },
-       { 0x3d400130, 0x20800 },
-       { 0x3d400134, 0xe100002 },
-       { 0x3d400138, 0x120 },
-       { 0x3d400144, 0xc80064 },
-       { 0x3d400180, 0x3e8001e },
-       { 0x3d400184, 0x3207a12 },
-       { 0x3d400188, 0x0 },
-       { 0x3d400190, 0x49f820e },
-       { 0x3d400194, 0x80303 },
-       { 0x3d4001b4, 0x1f0e },
-       { 0x3d4001a0, 0xe0400018 },
-       { 0x3d4001a4, 0xdf00e4 },
-       { 0x3d4001a8, 0x80000000 },
-       { 0x3d4001b0, 0x11 },
-       { 0x3d4001c0, 0x1 },
-       { 0x3d4001c4, 0x1 },
-       { 0x3d4000f4, 0xc99 },
-       { 0x3d400108, 0x9121c1c },
-       { 0x3d400200, 0x1f },
-       { 0x3d40020c, 0x0 },
-       { 0x3d400210, 0x1f1f },
-       { 0x3d400204, 0x80808 },
-       { 0x3d400214, 0x7070707 },
-       { 0x3d400218, 0x7070707 },
-       { 0x3d40021c, 0xf07 },
-       { 0x3d400250, 0x1705 },
-       { 0x3d400254, 0x2c },
-       { 0x3d40025c, 0x4000030 },
-       { 0x3d400264, 0x900093e7 },
-       { 0x3d40026c, 0x2005574 },
-       { 0x3d400400, 0x111 },
-       { 0x3d400404, 0x72ff },
-       { 0x3d400408, 0x72ff },
-       { 0x3d400494, 0x2100e07 },
-       { 0x3d400498, 0x620096 },
-       { 0x3d40049c, 0x1100e07 },
-       { 0x3d4004a0, 0xc8012c },
-       { 0x3d402020, 0x1001 },
-       { 0x3d402024, 0x30d400 },
-       { 0x3d402050, 0x20d000 },
-       { 0x3d402064, 0xc001c },
-       { 0x3d4020dc, 0x840000 },
-       { 0x3d4020e0, 0x330000 },
-       { 0x3d4020e8, 0x660048 },
-       { 0x3d4020ec, 0x160048 },
-       { 0x3d402100, 0xa040305 },
-       { 0x3d402104, 0x30407 },
-       { 0x3d402108, 0x203060b },
-       { 0x3d40210c, 0x505000 },
-       { 0x3d402110, 0x2040202 },
-       { 0x3d402114, 0x2030202 },
-       { 0x3d402118, 0x1010004 },
-       { 0x3d40211c, 0x301 },
-       { 0x3d402130, 0x20300 },
-       { 0x3d402134, 0xa100002 },
-       { 0x3d402138, 0x1d },
-       { 0x3d402144, 0x14000a },
-       { 0x3d402180, 0x640004 },
-       { 0x3d402190, 0x3818200 },
-       { 0x3d402194, 0x80303 },
-       { 0x3d4021b4, 0x100 },
-       { 0x3d4020f4, 0xc99 },
-       { 0x3d403020, 0x1001 },
-       { 0x3d403024, 0xc3500 },
-       { 0x3d403050, 0x20d000 },
-       { 0x3d403064, 0x30007 },
-       { 0x3d4030dc, 0x840000 },
-       { 0x3d4030e0, 0x330000 },
-       { 0x3d4030e8, 0x660048 },
-       { 0x3d4030ec, 0x160048 },
-       { 0x3d403100, 0xa010102 },
-       { 0x3d403104, 0x30404 },
-       { 0x3d403108, 0x203060b },
-       { 0x3d40310c, 0x505000 },
-       { 0x3d403110, 0x2040202 },
-       { 0x3d403114, 0x2030202 },
-       { 0x3d403118, 0x1010004 },
-       { 0x3d40311c, 0x301 },
-       { 0x3d403130, 0x20300 },
-       { 0x3d403134, 0xa100002 },
-       { 0x3d403138, 0x8 },
-       { 0x3d403144, 0x50003 },
-       { 0x3d403180, 0x190004 },
-       { 0x3d403190, 0x3818200 },
-       { 0x3d403194, 0x80303 },
-       { 0x3d4031b4, 0x100 },
-       { 0x3d4030f4, 0xc99 },
-       { 0x3d400028, 0x0 },
-};
-
-/* P0 message block parameter for training firmware */
-struct dram_cfg_param ddr_fsp0_cfg2[] = {
-       { 0xd0000, 0x0 },
-       { 0x54003, 0xfa0 },
-       { 0x54004, 0x2 },
-       { 0x54005, 0x2228 },
-       { 0x54006, 0x14 },
-       { 0x54008, 0x131f },
-       { 0x54009, 0xc8 },
-       { 0x5400b, 0x2 },
-       { 0x5400f, 0x100 },
-       { 0x54012, 0x110 },
-       { 0x54019, 0x3ff4 },
-       { 0x5401a, 0x33 },
-       { 0x5401b, 0x4866 },
-       { 0x5401c, 0x4800 },
-       { 0x5401e, 0x16 },
-       { 0x5401f, 0x3ff4 },
-       { 0x54020, 0x33 },
-       { 0x54021, 0x4866 },
-       { 0x54022, 0x4800 },
-       { 0x54024, 0x16 },
-       { 0x5402b, 0x1000 },
-       { 0x5402c, 0x1 },
-       { 0x54032, 0xf400 },
-       { 0x54033, 0x333f },
-       { 0x54034, 0x6600 },
-       { 0x54035, 0x48 },
-       { 0x54036, 0x48 },
-       { 0x54037, 0x1600 },
-       { 0x54038, 0xf400 },
-       { 0x54039, 0x333f },
-       { 0x5403a, 0x6600 },
-       { 0x5403b, 0x48 },
-       { 0x5403c, 0x48 },
-       { 0x5403d, 0x1600 },
-       { 0xd0000, 0x1 },
-};
-
-/* P1 message block parameter for training firmware */
-struct dram_cfg_param ddr_fsp1_cfg2[] = {
-       { 0xd0000, 0x0 },
-       { 0x54002, 0x101 },
-       { 0x54003, 0x190 },
-       { 0x54004, 0x2 },
-       { 0x54005, 0x2228 },
-       { 0x54006, 0x14 },
-       { 0x54008, 0x121f },
-       { 0x54009, 0xc8 },
-       { 0x5400b, 0x2 },
-       { 0x5400f, 0x100 },
-       { 0x54012, 0x110 },
-       { 0x54019, 0x84 },
-       { 0x5401a, 0x33 },
-       { 0x5401b, 0x4866 },
-       { 0x5401c, 0x4800 },
-       { 0x5401e, 0x16 },
-       { 0x5401f, 0x84 },
-       { 0x54020, 0x33 },
-       { 0x54021, 0x4866 },
-       { 0x54022, 0x4800 },
-       { 0x54024, 0x16 },
-       { 0x5402b, 0x1000 },
-       { 0x5402c, 0x1 },
-       { 0x54032, 0x8400 },
-       { 0x54033, 0x3300 },
-       { 0x54034, 0x6600 },
-       { 0x54035, 0x48 },
-       { 0x54036, 0x48 },
-       { 0x54037, 0x1600 },
-       { 0x54038, 0x8400 },
-       { 0x54039, 0x3300 },
-       { 0x5403a, 0x6600 },
-       { 0x5403b, 0x48 },
-       { 0x5403c, 0x48 },
-       { 0x5403d, 0x1600 },
-       { 0xd0000, 0x1 },
-};
-
-/* P2 message block parameter for training firmware */
-struct dram_cfg_param ddr_fsp2_cfg2[] = {
-       { 0xd0000, 0x0 },
-       { 0x54002, 0x102 },
-       { 0x54003, 0x64 },
-       { 0x54004, 0x2 },
-       { 0x54005, 0x2228 },
-       { 0x54006, 0x14 },
-       { 0x54008, 0x121f },
-       { 0x54009, 0xc8 },
-       { 0x5400b, 0x2 },
-       { 0x5400f, 0x100 },
-       { 0x54012, 0x110 },
-       { 0x54019, 0x84 },
-       { 0x5401a, 0x33 },
-       { 0x5401b, 0x4866 },
-       { 0x5401c, 0x4800 },
-       { 0x5401e, 0x16 },
-       { 0x5401f, 0x84 },
-       { 0x54020, 0x33 },
-       { 0x54021, 0x4866 },
-       { 0x54022, 0x4800 },
-       { 0x54024, 0x16 },
-       { 0x5402b, 0x1000 },
-       { 0x5402c, 0x1 },
-       { 0x54032, 0x8400 },
-       { 0x54033, 0x3300 },
-       { 0x54034, 0x6600 },
-       { 0x54035, 0x48 },
-       { 0x54036, 0x48 },
-       { 0x54037, 0x1600 },
-       { 0x54038, 0x8400 },
-       { 0x54039, 0x3300 },
-       { 0x5403a, 0x6600 },
-       { 0x5403b, 0x48 },
-       { 0x5403c, 0x48 },
-       { 0x5403d, 0x1600 },
-       { 0xd0000, 0x1 },
-};
-
-/* P0 2D message block parameter for training firmware */
-struct dram_cfg_param ddr_fsp0_2d_cfg2[] = {
-       { 0xd0000, 0x0 },
-       { 0x54003, 0xfa0 },
-       { 0x54004, 0x2 },
-       { 0x54005, 0x2228 },
-       { 0x54006, 0x14 },
-       { 0x54008, 0x61 },
-       { 0x54009, 0xc8 },
-       { 0x5400b, 0x2 },
-       { 0x5400d, 0x100 },
-       { 0x5400f, 0x100 },
-       { 0x54010, 0x1f7f },
-       { 0x54012, 0x110 },
-       { 0x54019, 0x3ff4 },
-       { 0x5401a, 0x33 },
-       { 0x5401b, 0x4866 },
-       { 0x5401c, 0x4800 },
-       { 0x5401e, 0x16 },
-       { 0x5401f, 0x3ff4 },
-       { 0x54020, 0x33 },
-       { 0x54021, 0x4866 },
-       { 0x54022, 0x4800 },
-       { 0x54024, 0x16 },
-       { 0x5402b, 0x1000 },
-       { 0x5402c, 0x1 },
-       { 0x54032, 0xf400 },
-       { 0x54033, 0x333f },
-       { 0x54034, 0x6600 },
-       { 0x54035, 0x48 },
-       { 0x54036, 0x48 },
-       { 0x54037, 0x1600 },
-       { 0x54038, 0xf400 },
-       { 0x54039, 0x333f },
-       { 0x5403a, 0x6600 },
-       { 0x5403b, 0x48 },
-       { 0x5403c, 0x48 },
-       { 0x5403d, 0x1600 },
-       { 0xd0000, 0x1 },
-};
-
-struct dram_fsp_msg ddr_dram_fsp_msg2[] = {
-       {
-               /* P0 4000mts 1D */
-               .drate = 4000,
-               .fw_type = FW_1D_IMAGE,
-               .fsp_cfg = ddr_fsp0_cfg2,
-               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg2),
-       },
-       {
-               /* P1 400mts 1D */
-               .drate = 400,
-               .fw_type = FW_1D_IMAGE,
-               .fsp_cfg = ddr_fsp1_cfg2,
-               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg2),
-       },
-       {
-               /* P2 100mts 1D */
-               .drate = 100,
-               .fw_type = FW_1D_IMAGE,
-               .fsp_cfg = ddr_fsp2_cfg2,
-               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg2),
-       },
-       {
-               /* P0 4000mts 2D */
-               .drate = 4000,
-               .fw_type = FW_2D_IMAGE,
-               .fsp_cfg = ddr_fsp0_2d_cfg2,
-               .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg2),
-       },
-};
-
-/* quad die, dual rank aka 8 GB DDR timing config params */
+/* ddr timing config params */
 struct dram_timing_info dram_timing = {
        .ddrc_cfg = ddr_ddrc_cfg,
        .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
@@ -2153,17 +1877,36 @@ struct dram_timing_info dram_timing = {
        .fsp_table = { 4000, 400, 100, },
 };
 
-/* dual die, single rank aka 1 GB (untested), 2 GB or 4 GB DDR timing config params */
-struct dram_timing_info dram_timing2 = {
-       .ddrc_cfg = ddr_ddrc_cfg2,
-       .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg2),
-       .ddrphy_cfg = ddr_ddrphy_cfg,
-       .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
-       .fsp_msg = ddr_dram_fsp_msg2,
-       .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg2),
-       .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
-       .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
-       .ddrphy_pie = ddr_phy_pie,
-       .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
-       .fsp_table = { 4000, 400, 100, },
-};
+static void apply_cfg_patch(struct dram_cfg_param *cfg, int cfg_sz,
+                           struct dram_cfg_param *patch, int patch_sz)
+{
+       int i, j;
+
+       for (i = 0; i < cfg_sz; i++)
+               for (j = 0; j < patch_sz; j++)
+                       if (cfg[i].reg == patch[j].reg)
+                               cfg[i].val = patch[j].val;
+}
+
+void lpddr4_single_rank_training_patch(void)
+{
+       apply_cfg_patch(ddr_ddrc_cfg, ARRAY_SIZE(ddr_ddrc_cfg),
+                       ddr_ddrc_cfg_single_rank_patch,
+                       ARRAY_SIZE(ddr_ddrc_cfg_single_rank_patch));
+
+       apply_cfg_patch(ddr_fsp0_cfg, ARRAY_SIZE(ddr_fsp0_cfg),
+                       ddr_fsp0_cfg_single_rank_patch,
+                       ARRAY_SIZE(ddr_fsp0_cfg_single_rank_patch));
+
+       apply_cfg_patch(ddr_fsp1_cfg, ARRAY_SIZE(ddr_fsp1_cfg),
+                       ddr_fsp1_cfg_single_rank_patch,
+                       ARRAY_SIZE(ddr_fsp1_cfg_single_rank_patch));
+
+       apply_cfg_patch(ddr_fsp2_cfg, ARRAY_SIZE(ddr_fsp2_cfg),
+                       ddr_fsp2_cfg_single_rank_patch,
+                       ARRAY_SIZE(ddr_fsp2_cfg_single_rank_patch));
+
+       apply_cfg_patch(ddr_fsp0_2d_cfg, ARRAY_SIZE(ddr_fsp0_2d_cfg),
+                       ddr_fsp0_2d_cfg_single_rank_patch,
+                       ARRAY_SIZE(ddr_fsp0_2d_cfg_single_rank_patch));
+}

diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.h b/board/toradex/verdin-imx8mp/lpddr4_timing.h
new file mode 100644 (file)
index 0000000..95e74e3
--- /dev/null
+++ b/board/toradex/verdin-imx8mp/lpddr4_timing.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2022 Toradex
+ */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+void lpddr4_single_rank_training_patch(void);
+
+#endif /* __LPDDR4_TIMING_H__ */

diff --git a/board/toradex/verdin-imx8mp/spl.c b/board/toradex/verdin-imx8mp/spl.c
index ea99e37..73729a4 100644 (file)
--- a/board/toradex/verdin-imx8mp/spl.c
+++ b/board/toradex/verdin-imx8mp/spl.c
@@ -21,8 +21,7 @@
 #include <dm/uclass.h>
 #include <power/pmic.h>
 #include <power/pca9450.h>
-
-extern struct dram_timing_info dram_timing2;
+#include "lpddr4_timing.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -34,13 +33,19 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
 void spl_dram_init(void)
 {
        /*
-        * try configuring for quad die, dual rank aka 8 GB falling back to
-        * dual die, single rank aka 1 GB (untested), 2 GB or 4 GB if it fails
+        * Try configuring for dual rank memory falling back to single rank
         */
-       if (ddr_init(&dram_timing)) {
-               printf("Quad die, dual rank failed, attempting dual die, single rank configuration.\n");
-               ddr_init(&dram_timing2);
+       if (!ddr_init(&dram_timing)) {
+               puts("DDR configured as dual rank\n");
+               return;
+       }
+
+       lpddr4_single_rank_training_patch();
+       if (!ddr_init(&dram_timing)) {
+               puts("DDR configured as single rank\n");
+               return;
        }
+       puts("DDR configuration failed\n");
 }
 
 void spl_board_init(void)

diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c
index d34b7e3..57d2944 100644 (file)
--- a/boot/bootdev-uclass.c
+++ b/boot/bootdev-uclass.c
@@ -174,6 +174,8 @@ int bootdev_find_in_blk(struct udevice *dev, struct udevice *blk,
        } else {
                ret = fs_set_blk_dev_with_part(desc, bflow->part);
                bflow->state = BOOTFLOWST_PART;
+               if (ret)
+                       return log_msg_ret("fs", ret);
 
                /* Use an #ifdef due to info.sys_ind */
 #ifdef CONFIG_DOS_PARTITION
@@ -181,8 +183,7 @@ int bootdev_find_in_blk(struct udevice *dev, struct udevice *blk,
                          blk->name, bflow->part, info.sys_ind,
                          ret ? -1 : fs_get_type());
 #endif
-               if (ret)
-                       return log_msg_ret("fs", ret);
+               bflow->blk = blk;
                bflow->state = BOOTFLOWST_FS;
        }
 
@@ -364,7 +365,8 @@ int bootdev_unbind_dev(struct udevice *parent)
  * @seqp: Returns the sequence number, or -1 if none
  * @method_flagsp: If non-NULL, returns any flags implied by the label
  * (enum bootflow_meth_flags_t), 0 if none
- * Returns: sequence number on success, else -ve error code
+ * Returns: sequence number on success, -EPFNOSUPPORT is the uclass is not
+ * known, other -ve error code on other error
  */
 static int label_to_uclass(const char *label, int *seqp, int *method_flagsp)
 {
@@ -394,8 +396,7 @@ static int label_to_uclass(const char *label, int *seqp, int *method_flagsp)
                        id = UCLASS_ETH;
                        method_flags |= BOOTFLOW_METHF_DHCP_ONLY;
                } else {
-                       log_warning("Unknown uclass '%s' in label\n", label);
-                       return -EINVAL;
+                       return -EPFNOSUPPORT;
                }
        }
        if (id == UCLASS_USB)
@@ -458,7 +459,6 @@ int bootdev_find_by_label(const char *label, struct udevice **devp,
                }
                log_debug("- no device in %s\n", media->name);
        }
-       log_warning("Unknown seq %d for label '%s'\n", seq, label);
 
        return -ENOENT;
 }
@@ -577,9 +577,28 @@ int bootdev_next_label(struct bootflow_iter *iter, struct udevice **devp,
 
        log_debug("next\n");
        for (dev = NULL; !dev && iter->labels[++iter->cur_label];) {
-               log_debug("Scanning: %s\n", iter->labels[iter->cur_label]);
-               bootdev_hunt_and_find_by_label(iter->labels[iter->cur_label],
-                                              &dev, method_flagsp);
+               const char *label = iter->labels[iter->cur_label];
+               int ret;
+
+               log_debug("Scanning: %s\n", label);
+               ret = bootdev_hunt_and_find_by_label(label, &dev,
+                                                    method_flagsp);
+               if (iter->flags & BOOTFLOWIF_SHOW) {
+                       if (ret == -EPFNOSUPPORT) {
+                               log_warning("Unknown uclass '%s' in label\n",
+                                           label);
+                       } else if (ret == -ENOENT) {
+                               /*
+                                * looking for, e.g. 'scsi0' should find
+                                * something if SCSI is present
+                                */
+                               if (!trailing_strtol(label)) {
+                                       log_warning("No bootdevs for '%s'\n",
+                                                   label);
+                               }
+                       }
+               }
+
        }
 
        if (!dev)

diff --git a/boot/bootm.c b/boot/bootm.c
index 2eec60e..4144ff3 100644 (file)
--- a/boot/bootm.c
+++ b/boot/bootm.c
@@ -113,6 +113,10 @@ static int bootm_find_os(struct cmd_tbl *cmdtp, int flag, int argc,
                         char *const argv[])
 {
        const void *os_hdr;
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+       const void *vendor_boot_img;
+       const void *boot_img;
+#endif
        bool ep_found = false;
        int ret;
 
@@ -181,14 +185,23 @@ static int bootm_find_os(struct cmd_tbl *cmdtp, int flag, int argc,
 #endif
 #ifdef CONFIG_ANDROID_BOOT_IMAGE
        case IMAGE_FORMAT_ANDROID:
+               boot_img = os_hdr;
+               vendor_boot_img = NULL;
+               if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) {
+                       boot_img = map_sysmem(get_abootimg_addr(), 0);
+                       vendor_boot_img = map_sysmem(get_avendor_bootimg_addr(), 0);
+               }
                images.os.type = IH_TYPE_KERNEL;
-               images.os.comp = android_image_get_kcomp(os_hdr);
+               images.os.comp = android_image_get_kcomp(boot_img, vendor_boot_img);
                images.os.os = IH_OS_LINUX;
-
-               images.os.end = android_image_get_end(os_hdr);
-               images.os.load = android_image_get_kload(os_hdr);
+               images.os.end = android_image_get_end(boot_img, vendor_boot_img);
+               images.os.load = android_image_get_kload(boot_img, vendor_boot_img);
                images.ep = images.os.load;
                ep_found = true;
+               if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) {
+                       unmap_sysmem(vendor_boot_img);
+                       unmap_sysmem(boot_img);
+               }
                break;
 #endif
        default:
@@ -889,6 +902,10 @@ static const void *boot_get_kernel(struct cmd_tbl *cmdtp, int flag, int argc,
        int             os_noffset;
 #endif
 
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+       const void *boot_img;
+       const void *vendor_boot_img;
+#endif
        img_addr = genimg_get_kernel_addr_fit(argc < 1 ? NULL : argv[0],
                                              &fit_uname_config,
                                              &fit_uname_kernel);
@@ -964,10 +981,20 @@ static const void *boot_get_kernel(struct cmd_tbl *cmdtp, int flag, int argc,
 #endif
 #ifdef CONFIG_ANDROID_BOOT_IMAGE
        case IMAGE_FORMAT_ANDROID:
+               boot_img = buf;
+               vendor_boot_img = NULL;
+               if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) {
+                       boot_img = map_sysmem(get_abootimg_addr(), 0);
+                       vendor_boot_img = map_sysmem(get_avendor_bootimg_addr(), 0);
+               }
                printf("## Booting Android Image at 0x%08lx ...\n", img_addr);
-               if (android_image_get_kernel(buf, images->verify,
+               if (android_image_get_kernel(boot_img, vendor_boot_img, images->verify,
                                             os_data, os_len))
                        return NULL;
+               if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) {
+                       unmap_sysmem(vendor_boot_img);
+                       unmap_sysmem(boot_img);
+               }
                break;
 #endif
        default:

diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c
index 6a97ac0..6f70f22 100644 (file)
--- a/boot/bootmeth_efi.c
+++ b/boot/bootmeth_efi.c
@@ -94,7 +94,7 @@ static int get_efi_pxe_vci(char *str, int max_len)
        return 0;
 }
 
-static int efiload_read_file(struct blk_desc *desc, struct bootflow *bflow)
+static void set_efi_bootdev(struct blk_desc *desc, struct bootflow *bflow)
 {
        const struct udevice *media_dev;
        int size = bflow->size;
@@ -102,11 +102,6 @@ static int efiload_read_file(struct blk_desc *desc, struct bootflow *bflow)
        char devnum_str[9];
        char dirname[200];
        char *last_slash;
-       int ret;
-
-       ret = bootmeth_alloc_file(bflow, 0x2000000, 0x10000);
-       if (ret)
-               return log_msg_ret("read", ret);
 
        /*
         * This is a horrible hack to tell EFI about this boot device. Once we
@@ -117,7 +112,9 @@ static int efiload_read_file(struct blk_desc *desc, struct bootflow *bflow)
         * this can go away.
         */
        media_dev = dev_get_parent(bflow->dev);
-       snprintf(devnum_str, sizeof(devnum_str), "%x", dev_seq(media_dev));
+       snprintf(devnum_str, sizeof(devnum_str), "%x:%x",
+                desc ? desc->devnum : dev_seq(media_dev),
+                bflow->part);
 
        strlcpy(dirname, bflow->fname, sizeof(dirname));
        last_slash = strrchr(dirname, '/');
@@ -130,6 +127,15 @@ static int efiload_read_file(struct blk_desc *desc, struct bootflow *bflow)
        dev_name = device_get_uclass_id(media_dev) == UCLASS_MASS_STORAGE ?
                 "usb" : dev_get_uclass_name(media_dev);
        efi_set_bootdev(dev_name, devnum_str, bflow->fname, bflow->buf, size);
+}
+
+static int efiload_read_file(struct blk_desc *desc, struct bootflow *bflow)
+{
+       int ret;
+
+       ret = bootmeth_alloc_file(bflow, 0x2000000, 0x10000);
+       if (ret)
+               return log_msg_ret("read", ret);
 
        return 0;
 }
@@ -235,21 +241,21 @@ static int distro_efi_read_bootflow_file(struct udevice *dev,
 
        /* try the various available names */
        ret = -ENOENT;
-       for (seq = 0; ret; seq++) {
+       *fname = '\0';
+       for (seq = 0; ret == -ENOENT; seq++) {
                ret = distro_efi_get_fdt_name(fname, sizeof(fname), seq);
-               if (ret == -EALREADY) {
+               if (ret == -EALREADY)
                        bflow->flags = BOOTFLOWF_USE_PRIOR_FDT;
-                       break;
-               }
-               if (ret)
-                       return log_msg_ret("nam", ret);
-               ret = bootmeth_common_read_file(dev, bflow, fname, fdt_addr,
-                                               &size);
+               if (!ret)
+                       ret = bootmeth_common_read_file(dev, bflow, fname,
+                                                       fdt_addr, &size);
        }
 
-       bflow->fdt_fname = strdup(fname);
-       if (!bflow->fdt_fname)
-               return log_msg_ret("fil", -ENOMEM);
+       if (*fname) {
+               bflow->fdt_fname = strdup(fname);
+               if (!bflow->fdt_fname)
+                       return log_msg_ret("fil", -ENOMEM);
+       }
 
        if (!ret) {
                bflow->fdt_size = size;
@@ -373,6 +379,13 @@ int distro_efi_boot(struct udevice *dev, struct bootflow *bflow)
 
        /* A non-zero buffer indicates the kernel is there */
        if (bflow->buf) {
+               /* Set the EFI bootdev again, since reading an FDT loses it! */
+               if (bflow->blk) {
+                       struct blk_desc *desc = dev_get_uclass_plat(bflow->blk);
+
+                       set_efi_bootdev(desc, bflow);
+               }
+
                kernel = (ulong)map_to_sysmem(bflow->buf);
 
                /*

diff --git a/boot/image-android.c b/boot/image-android.c
index 2628db3..88e40bc 100644 (file)
--- a/boot/image-android.c
+++ b/boot/image-android.c
@@ -18,7 +18,193 @@
 
 static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1];
 
-static ulong android_image_get_kernel_addr(const struct andr_img_hdr *hdr)
+static ulong checksum(const unsigned char *buffer, ulong size)
+{
+       ulong sum = 0;
+
+       for (ulong i = 0; i < size; i++)
+               sum += buffer[i];
+       return sum;
+}
+
+static bool is_trailer_present(ulong bootconfig_end_addr)
+{
+       return !strncmp((char *)(bootconfig_end_addr - BOOTCONFIG_MAGIC_SIZE),
+                       BOOTCONFIG_MAGIC, BOOTCONFIG_MAGIC_SIZE);
+}
+
+static ulong add_trailer(ulong bootconfig_start_addr, ulong bootconfig_size)
+{
+       ulong end;
+       ulong sum;
+
+       if (!bootconfig_start_addr)
+               return -1;
+       if (!bootconfig_size)
+               return 0;
+
+       end = bootconfig_start_addr + bootconfig_size;
+       if (is_trailer_present(end))
+               return 0;
+
+       memcpy((void *)(end), &bootconfig_size, BOOTCONFIG_SIZE_SIZE);
+       sum = checksum((unsigned char *)bootconfig_start_addr, bootconfig_size);
+       memcpy((void *)(end + BOOTCONFIG_SIZE_SIZE), &sum,
+              BOOTCONFIG_CHECKSUM_SIZE);
+       memcpy((void *)(end + BOOTCONFIG_SIZE_SIZE + BOOTCONFIG_CHECKSUM_SIZE),
+              BOOTCONFIG_MAGIC, BOOTCONFIG_MAGIC_SIZE);
+
+       return BOOTCONFIG_TRAILER_SIZE;
+}
+
+static void android_boot_image_v3_v4_parse_hdr(const struct andr_boot_img_hdr_v3 *hdr,
+                                              struct andr_image_data *data)
+{
+       ulong end;
+
+       data->kcmdline = hdr->cmdline;
+       data->header_version = hdr->header_version;
+       data->ramdisk_ptr = env_get_ulong("ramdisk_addr_r", 16, 0);
+
+       /*
+        * The header takes a full page, the remaining components are aligned
+        * on page boundary.
+        */
+       end = (ulong)hdr;
+       end += ANDR_GKI_PAGE_SIZE;
+       data->kernel_ptr = end;
+       data->kernel_size = hdr->kernel_size;
+       end += ALIGN(hdr->kernel_size, ANDR_GKI_PAGE_SIZE);
+       data->ramdisk_size = hdr->ramdisk_size;
+       data->boot_ramdisk_size = hdr->ramdisk_size;
+       end += ALIGN(hdr->ramdisk_size, ANDR_GKI_PAGE_SIZE);
+
+       if (hdr->header_version > 3)
+               end += ALIGN(hdr->signature_size, ANDR_GKI_PAGE_SIZE);
+
+       data->boot_img_total_size = end - (ulong)hdr;
+}
+
+static void android_vendor_boot_image_v3_v4_parse_hdr(const struct andr_vnd_boot_img_hdr
+                                                     *hdr, struct andr_image_data *data)
+{
+       ulong end;
+
+       /*
+        * The header takes a full page, the remaining components are aligned
+        * on page boundary.
+        */
+       data->kcmdline_extra = hdr->cmdline;
+       data->tags_addr = hdr->tags_addr;
+       data->image_name = hdr->name;
+       data->kernel_addr = hdr->kernel_addr;
+       data->ramdisk_addr = hdr->ramdisk_addr;
+       data->dtb_load_addr = hdr->dtb_addr;
+       data->bootconfig_size = hdr->bootconfig_size;
+       end = (ulong)hdr;
+       end += hdr->page_size;
+       if (hdr->vendor_ramdisk_size) {
+               data->vendor_ramdisk_ptr = end;
+               data->vendor_ramdisk_size = hdr->vendor_ramdisk_size;
+               data->ramdisk_size += hdr->vendor_ramdisk_size;
+               end += ALIGN(hdr->vendor_ramdisk_size, hdr->page_size);
+       }
+
+       data->dtb_ptr = end;
+       data->dtb_size = hdr->dtb_size;
+
+       end += ALIGN(hdr->dtb_size, hdr->page_size);
+       end += ALIGN(hdr->vendor_ramdisk_table_size, hdr->page_size);
+       data->bootconfig_addr = end;
+       if (hdr->bootconfig_size) {
+               data->bootconfig_size += add_trailer(data->bootconfig_addr,
+                                                    data->bootconfig_size);
+               data->ramdisk_size += data->bootconfig_size;
+       }
+       end += ALIGN(data->bootconfig_size, hdr->page_size);
+       data->vendor_boot_img_total_size = end - (ulong)hdr;
+}
+
+static void android_boot_image_v0_v1_v2_parse_hdr(const struct andr_boot_img_hdr_v0 *hdr,
+                                                 struct andr_image_data *data)
+{
+       ulong end;
+
+       data->image_name = hdr->name;
+       data->kcmdline = hdr->cmdline;
+       data->kernel_addr = hdr->kernel_addr;
+       data->ramdisk_addr = hdr->ramdisk_addr;
+       data->header_version = hdr->header_version;
+       data->dtb_load_addr = hdr->dtb_addr;
+
+       end = (ulong)hdr;
+
+       /*
+        * The header takes a full page, the remaining components are aligned
+        * on page boundary
+        */
+
+       end += hdr->page_size;
+
+       data->kernel_ptr = end;
+       data->kernel_size = hdr->kernel_size;
+       end += ALIGN(hdr->kernel_size, hdr->page_size);
+
+       data->ramdisk_ptr = end;
+       data->ramdisk_size = hdr->ramdisk_size;
+       end += ALIGN(hdr->ramdisk_size, hdr->page_size);
+
+       data->second_ptr = end;
+       data->second_size = hdr->second_size;
+       end += ALIGN(hdr->second_size, hdr->page_size);
+
+       if (hdr->header_version >= 1) {
+               data->recovery_dtbo_ptr = end;
+               data->recovery_dtbo_size = hdr->recovery_dtbo_size;
+               end += ALIGN(hdr->recovery_dtbo_size, hdr->page_size);
+       }
+
+       if (hdr->header_version >= 2) {
+               data->dtb_ptr = end;
+               data->dtb_size = hdr->dtb_size;
+               end += ALIGN(hdr->dtb_size, hdr->page_size);
+       }
+
+       data->boot_img_total_size = end - (ulong)hdr;
+}
+
+bool android_image_get_data(const void *boot_hdr, const void *vendor_boot_hdr,
+                           struct andr_image_data *data)
+{
+       if (!boot_hdr || !data) {
+               printf("boot_hdr or data params can't be NULL\n");
+               return false;
+       }
+
+       if (!is_android_boot_image_header(boot_hdr)) {
+               printf("Incorrect boot image header\n");
+               return false;
+       }
+
+       if (((struct andr_boot_img_hdr_v0 *)boot_hdr)->header_version > 2) {
+               if (!vendor_boot_hdr) {
+                       printf("For boot header v3+ vendor boot image has to be provided\n");
+                       return false;
+               }
+               if (!is_android_vendor_boot_image_header(vendor_boot_hdr)) {
+                       printf("Incorrect vendor boot image header\n");
+                       return false;
+               }
+               android_boot_image_v3_v4_parse_hdr(boot_hdr, data);
+               android_vendor_boot_image_v3_v4_parse_hdr(vendor_boot_hdr, data);
+       } else {
+               android_boot_image_v0_v1_v2_parse_hdr(boot_hdr, data);
+       }
+
+       return true;
+}
+
+static ulong android_image_get_kernel_addr(struct andr_image_data *img_data)
 {
        /*
         * All the Android tools that generate a boot.img use this
@@ -31,23 +217,25 @@ static ulong android_image_get_kernel_addr(const struct andr_img_hdr *hdr)
         *
         * Otherwise, we will return the actual value set by the user.
         */
-       if (hdr->kernel_addr == ANDROID_IMAGE_DEFAULT_KERNEL_ADDR)
-               return (ulong)hdr + hdr->page_size;
+       if (img_data->kernel_addr  == ANDROID_IMAGE_DEFAULT_KERNEL_ADDR)
+               return img_data->kernel_ptr;
 
        /*
         * abootimg creates images where all load addresses are 0
         * and we need to fix them.
         */
-       if (hdr->kernel_addr == 0 && hdr->ramdisk_addr == 0)
+       if (img_data->kernel_addr == 0 && img_data->ramdisk_addr == 0)
                return env_get_ulong("kernel_addr_r", 16, 0);
 
-       return hdr->kernel_addr;
+       return img_data->kernel_addr;
 }
 
 /**
  * android_image_get_kernel() - processes kernel part of Android boot images
- * @hdr:       Pointer to image header, which is at the start
+ * @hdr:       Pointer to boot image header, which is at the start
  *                     of the image.
+ * @vendor_boot_img:   Pointer to vendor boot image header, which is at the
+ *                             start of the image.
  * @verify:    Checksum verification flag. Currently unimplemented.
  * @os_data:   Pointer to a ulong variable, will hold os data start
  *                     address.
@@ -59,30 +247,42 @@ static ulong android_image_get_kernel_addr(const struct andr_img_hdr *hdr)
  * Return: Zero, os start address and length on success,
  *             otherwise on failure.
  */
-int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
+int android_image_get_kernel(const void *hdr,
+                            const void *vendor_boot_img, int verify,
                             ulong *os_data, ulong *os_len)
 {
-       u32 kernel_addr = android_image_get_kernel_addr(hdr);
-       const struct legacy_img_hdr *ihdr = (const struct legacy_img_hdr *)
-               ((uintptr_t)hdr + hdr->page_size);
+       struct andr_image_data img_data = {0};
+       u32 kernel_addr;
+       const struct legacy_img_hdr *ihdr;
+
+       if (!android_image_get_data(hdr, vendor_boot_img, &img_data))
+               return -EINVAL;
+
+       kernel_addr = android_image_get_kernel_addr(&img_data);
+       ihdr = (const struct legacy_img_hdr *)img_data.kernel_ptr;
 
        /*
         * Not all Android tools use the id field for signing the image with
         * sha1 (or anything) so we don't check it. It is not obvious that the
         * string is null terminated so we take care of this.
         */
-       strncpy(andr_tmp_str, hdr->name, ANDR_BOOT_NAME_SIZE);
+       strlcpy(andr_tmp_str, img_data.image_name, ANDR_BOOT_NAME_SIZE);
        andr_tmp_str[ANDR_BOOT_NAME_SIZE] = '\0';
        if (strlen(andr_tmp_str))
                printf("Android's image name: %s\n", andr_tmp_str);
 
        printf("Kernel load addr 0x%08x size %u KiB\n",
-              kernel_addr, DIV_ROUND_UP(hdr->kernel_size, 1024));
+              kernel_addr, DIV_ROUND_UP(img_data.kernel_size, 1024));
 
        int len = 0;
-       if (*hdr->cmdline) {
-               printf("Kernel command line: %s\n", hdr->cmdline);
-               len += strlen(hdr->cmdline);
+       if (*img_data.kcmdline) {
+               printf("Kernel command line: %s\n", img_data.kcmdline);
+               len += strlen(img_data.kcmdline);
+       }
+
+       if (img_data.kcmdline_extra) {
+               printf("Kernel extra command line: %s\n", img_data.kcmdline_extra);
+               len += strlen(img_data.kcmdline_extra);
        }
 
        char *bootargs = env_get("bootargs");
@@ -100,8 +300,14 @@ int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
                strcpy(newbootargs, bootargs);
                strcat(newbootargs, " ");
        }
-       if (*hdr->cmdline)
-               strcat(newbootargs, hdr->cmdline);
+
+       if (*img_data.kcmdline)
+               strcat(newbootargs, img_data.kcmdline);
+
+       if (img_data.kcmdline_extra) {
+               strcat(newbootargs, " ");
+               strcat(newbootargs, img_data.kcmdline_extra);
+       }
 
        env_set("bootargs", newbootargs);
 
@@ -109,56 +315,63 @@ int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
                if (image_get_magic(ihdr) == IH_MAGIC) {
                        *os_data = image_get_data(ihdr);
                } else {
-                       *os_data = (ulong)hdr;
-                       *os_data += hdr->page_size;
+                       *os_data = img_data.kernel_ptr;
                }
        }
        if (os_len) {
                if (image_get_magic(ihdr) == IH_MAGIC)
                        *os_len = image_get_data_size(ihdr);
                else
-                       *os_len = hdr->kernel_size;
+                       *os_len = img_data.kernel_size;
        }
        return 0;
 }
 
-int android_image_check_header(const struct andr_img_hdr *hdr)
+bool is_android_vendor_boot_image_header(const void *vendor_boot_img)
 {
-       return memcmp(ANDR_BOOT_MAGIC, hdr->magic, ANDR_BOOT_MAGIC_SIZE);
+       return !memcmp(VENDOR_BOOT_MAGIC, vendor_boot_img, ANDR_VENDOR_BOOT_MAGIC_SIZE);
 }
 
-ulong android_image_get_end(const struct andr_img_hdr *hdr)
+bool is_android_boot_image_header(const void *hdr)
 {
-       ulong end;
+       return !memcmp(ANDR_BOOT_MAGIC, hdr, ANDR_BOOT_MAGIC_SIZE);
+}
 
-       /*
-        * The header takes a full page, the remaining components are aligned
-        * on page boundary
-        */
-       end = (ulong)hdr;
-       end += hdr->page_size;
-       end += ALIGN(hdr->kernel_size, hdr->page_size);
-       end += ALIGN(hdr->ramdisk_size, hdr->page_size);
-       end += ALIGN(hdr->second_size, hdr->page_size);
+ulong android_image_get_end(const struct andr_boot_img_hdr_v0 *hdr,
+                           const void *vendor_boot_img)
+{
+       struct andr_image_data img_data;
 
-       if (hdr->header_version >= 1)
-               end += ALIGN(hdr->recovery_dtbo_size, hdr->page_size);
+       if (!android_image_get_data(hdr, vendor_boot_img, &img_data))
+               return -EINVAL;
 
-       if (hdr->header_version >= 2)
-               end += ALIGN(hdr->dtb_size, hdr->page_size);
+       if (img_data.header_version > 2)
+               return 0;
 
-       return end;
+       return img_data.boot_img_total_size;
 }
 
-ulong android_image_get_kload(const struct andr_img_hdr *hdr)
+ulong android_image_get_kload(const void *hdr,
+                             const void *vendor_boot_img)
 {
-       return android_image_get_kernel_addr(hdr);
+       struct andr_image_data img_data;
+
+       if (!android_image_get_data(hdr, vendor_boot_img, &img_data))
+               return -EINVAL;
+
+       return android_image_get_kernel_addr(&img_data);
 }
 
-ulong android_image_get_kcomp(const struct andr_img_hdr *hdr)
+ulong android_image_get_kcomp(const void *hdr,
+                             const void *vendor_boot_img)
 {
-       const void *p = (void *)((uintptr_t)hdr + hdr->page_size);
+       struct andr_image_data img_data;
+       const void *p;
+
+       if (!android_image_get_data(hdr, vendor_boot_img, &img_data))
+               return -EINVAL;
 
+       p = (const void *)img_data.kernel_ptr;
        if (image_get_magic((struct legacy_img_hdr *)p) == IH_MAGIC)
                return image_get_comp((struct legacy_img_hdr *)p);
        else if (get_unaligned_le32(p) == LZ4F_MAGIC)
@@ -167,41 +380,66 @@ ulong android_image_get_kcomp(const struct andr_img_hdr *hdr)
                return image_decomp_type(p, sizeof(u32));
 }
 
-int android_image_get_ramdisk(const struct andr_img_hdr *hdr,
+int android_image_get_ramdisk(const void *hdr, const void *vendor_boot_img,
                              ulong *rd_data, ulong *rd_len)
 {
-       if (!hdr->ramdisk_size) {
+       struct andr_image_data img_data = {0};
+       ulong ramdisk_ptr;
+
+       if (!android_image_get_data(hdr, vendor_boot_img, &img_data))
+               return -EINVAL;
+
+       if (!img_data.ramdisk_size) {
                *rd_data = *rd_len = 0;
                return -1;
        }
+       if (img_data.header_version > 2) {
+               ramdisk_ptr = img_data.ramdisk_ptr;
+               memcpy((void *)(ramdisk_ptr), (void *)img_data.vendor_ramdisk_ptr,
+                      img_data.vendor_ramdisk_size);
+               memcpy((void *)(ramdisk_ptr + img_data.vendor_ramdisk_size),
+                      (void *)img_data.ramdisk_ptr,
+                      img_data.boot_ramdisk_size);
+               if (img_data.bootconfig_size) {
+                       memcpy((void *)
+                              (ramdisk_ptr + img_data.vendor_ramdisk_size +
+                              img_data.boot_ramdisk_size),
+                              (void *)img_data.bootconfig_addr,
+                              img_data.bootconfig_size);
+               }
+       }
 
-       printf("RAM disk load addr 0x%08x size %u KiB\n",
-              hdr->ramdisk_addr, DIV_ROUND_UP(hdr->ramdisk_size, 1024));
+       printf("RAM disk load addr 0x%08lx size %u KiB\n",
+              img_data.ramdisk_ptr, DIV_ROUND_UP(img_data.ramdisk_size, 1024));
 
-       *rd_data = (unsigned long)hdr;
-       *rd_data += hdr->page_size;
-       *rd_data += ALIGN(hdr->kernel_size, hdr->page_size);
+       *rd_data = img_data.ramdisk_ptr;
 
-       *rd_len = hdr->ramdisk_size;
+       *rd_len = img_data.ramdisk_size;
        return 0;
 }
 
-int android_image_get_second(const struct andr_img_hdr *hdr,
-                             ulong *second_data, ulong *second_len)
+int android_image_get_second(const void *hdr, ulong *second_data, ulong *second_len)
 {
-       if (!hdr->second_size) {
+       struct andr_image_data img_data;
+
+       if (!android_image_get_data(hdr, NULL, &img_data))
+               return -EINVAL;
+
+       if (img_data.header_version > 2) {
+               printf("Second stage bootloader is only supported for boot image version <= 2\n");
+               return -EOPNOTSUPP;
+       }
+
+       if (!img_data.second_size) {
                *second_data = *second_len = 0;
                return -1;
        }
 
-       *second_data = (unsigned long)hdr;
-       *second_data += hdr->page_size;
-       *second_data += ALIGN(hdr->kernel_size, hdr->page_size);
-       *second_data += ALIGN(hdr->ramdisk_size, hdr->page_size);
+       *second_data = img_data.second_ptr;
 
        printf("second address is 0x%lx\n",*second_data);
 
-       *second_len = hdr->second_size;
+       *second_len = img_data.second_size;
        return 0;
 }
 
@@ -226,19 +464,19 @@ int android_image_get_second(const struct andr_img_hdr *hdr,
  */
 bool android_image_get_dtbo(ulong hdr_addr, ulong *addr, u32 *size)
 {
-       const struct andr_img_hdr *hdr;
+       const struct andr_boot_img_hdr_v0 *hdr;
        ulong dtbo_img_addr;
        bool ret = true;
 
        hdr = map_sysmem(hdr_addr, sizeof(*hdr));
-       if (android_image_check_header(hdr)) {
+       if (!is_android_boot_image_header(hdr)) {
                printf("Error: Boot Image header is incorrect\n");
                ret = false;
                goto exit;
        }
 
-       if (hdr->header_version < 1) {
-               printf("Error: header_version must be >= 1 to get dtbo\n");
+       if (hdr->header_version != 1 && hdr->header_version != 2) {
+               printf("Error: header version must be >= 1 and <= 2 to get dtbo\n");
                ret = false;
                goto exit;
        }
@@ -269,18 +507,20 @@ exit:
 /**
  * android_image_get_dtb_img_addr() - Get the address of DTB area in boot image.
  * @hdr_addr: Boot image header address
+ * @vhdr_addr: Vendor Boot image header address
  * @addr: Will contain the address of DTB area in boot image
  *
  * Return: true on success or false on fail.
  */
-static bool android_image_get_dtb_img_addr(ulong hdr_addr, ulong *addr)
+static bool android_image_get_dtb_img_addr(ulong hdr_addr, ulong vhdr_addr, ulong *addr)
 {
-       const struct andr_img_hdr *hdr;
+       const struct andr_boot_img_hdr_v0 *hdr;
+       const struct andr_vnd_boot_img_hdr *v_hdr;
        ulong dtb_img_addr;
        bool ret = true;
 
        hdr = map_sysmem(hdr_addr, sizeof(*hdr));
-       if (android_image_check_header(hdr)) {
+       if (!is_android_boot_image_header(hdr)) {
                printf("Error: Boot Image header is incorrect\n");
                ret = false;
                goto exit;
@@ -292,22 +532,40 @@ static bool android_image_get_dtb_img_addr(ulong hdr_addr, ulong *addr)
                goto exit;
        }
 
-       if (hdr->dtb_size == 0) {
-               printf("Error: dtb_size is 0\n");
-               ret = false;
-               goto exit;
+       if (hdr->header_version == 2) {
+               if (!hdr->dtb_size) {
+                       printf("Error: dtb_size is 0\n");
+                       ret = false;
+                       goto exit;
+               }
+               /* Calculate the address of DTB area in boot image */
+               dtb_img_addr = hdr_addr;
+               dtb_img_addr += hdr->page_size;
+               dtb_img_addr += ALIGN(hdr->kernel_size, hdr->page_size);
+               dtb_img_addr += ALIGN(hdr->ramdisk_size, hdr->page_size);
+               dtb_img_addr += ALIGN(hdr->second_size, hdr->page_size);
+               dtb_img_addr += ALIGN(hdr->recovery_dtbo_size, hdr->page_size);
+
+               *addr = dtb_img_addr;
        }
 
-       /* Calculate the address of DTB area in boot image */
-       dtb_img_addr = hdr_addr;
-       dtb_img_addr += hdr->page_size;
-       dtb_img_addr += ALIGN(hdr->kernel_size, hdr->page_size);
-       dtb_img_addr += ALIGN(hdr->ramdisk_size, hdr->page_size);
-       dtb_img_addr += ALIGN(hdr->second_size, hdr->page_size);
-       dtb_img_addr += ALIGN(hdr->recovery_dtbo_size, hdr->page_size);
-
-       *addr = dtb_img_addr;
-
+       if (hdr->header_version > 2) {
+               v_hdr = map_sysmem(vhdr_addr, sizeof(*v_hdr));
+               if (!v_hdr->dtb_size) {
+                       printf("Error: dtb_size is 0\n");
+                       ret = false;
+                       unmap_sysmem(v_hdr);
+                       goto exit;
+               }
+               /* Calculate the address of DTB area in boot image */
+               dtb_img_addr = vhdr_addr;
+               dtb_img_addr += v_hdr->page_size;
+               if (v_hdr->vendor_ramdisk_size)
+                       dtb_img_addr += ALIGN(v_hdr->vendor_ramdisk_size, v_hdr->page_size);
+               *addr = dtb_img_addr;
+               unmap_sysmem(v_hdr);
+               goto exit;
+       }
 exit:
        unmap_sysmem(hdr);
        return ret;
@@ -316,6 +574,7 @@ exit:
 /**
  * android_image_get_dtb_by_index() - Get address and size of blob in DTB area.
  * @hdr_addr: Boot image header address
+ * @vendor_boot_img: Pointer to vendor boot image header, which is at the start of the image.
  * @index: Index of desired DTB in DTB area (starting from 0)
  * @addr: If not NULL, will contain address to specified DTB
  * @size: If not NULL, will contain size of specified DTB
@@ -325,20 +584,32 @@ exit:
  *
  * Return: true on success or false on error.
  */
-bool android_image_get_dtb_by_index(ulong hdr_addr, u32 index, ulong *addr,
-                                   u32 *size)
+bool android_image_get_dtb_by_index(ulong hdr_addr, ulong vendor_boot_img,
+                                   u32 index, ulong *addr, u32 *size)
 {
-       const struct andr_img_hdr *hdr;
-       bool res;
+       struct andr_image_data img_data;
+       const struct andr_boot_img_hdr_v0 *hdr;
+       const struct andr_vnd_boot_img_hdr *vhdr;
+
+       hdr = map_sysmem(hdr_addr, sizeof(*hdr));
+       if (vendor_boot_img != -1)
+               vhdr = map_sysmem(vendor_boot_img, sizeof(*vhdr));
+       if (!android_image_get_data(hdr, vhdr, &img_data)) {
+               if (vendor_boot_img != -1)
+                       unmap_sysmem(vhdr);
+               unmap_sysmem(hdr);
+               return false;
+       }
+       if (vendor_boot_img != -1)
+               unmap_sysmem(vhdr);
+       unmap_sysmem(hdr);
+
        ulong dtb_img_addr;     /* address of DTB part in boot image */
        u32 dtb_img_size;       /* size of DTB payload in boot image */
        ulong dtb_addr;         /* address of DTB blob with specified index  */
        u32 i;                  /* index iterator */
 
-       res = android_image_get_dtb_img_addr(hdr_addr, &dtb_img_addr);
-       if (!res)
-               return false;
-
+       android_image_get_dtb_img_addr(hdr_addr, vendor_boot_img, &dtb_img_addr);
        /* Check if DTB area of boot image is in DTBO format */
        if (android_dt_check_header(dtb_img_addr)) {
                return android_dt_get_fdt_by_index(dtb_img_addr, index, addr,
@@ -346,9 +617,7 @@ bool android_image_get_dtb_by_index(ulong hdr_addr, u32 index, ulong *addr,
        }
 
        /* Find out the address of DTB with specified index in concat blobs */
-       hdr = map_sysmem(hdr_addr, sizeof(*hdr));
-       dtb_img_size = hdr->dtb_size;
-       unmap_sysmem(hdr);
+       dtb_img_size = img_data.dtb_size;
        i = 0;
        dtb_addr = dtb_img_addr;
        while (dtb_addr < dtb_img_addr + dtb_img_size) {
@@ -393,8 +662,12 @@ bool android_image_get_dtb_by_index(ulong hdr_addr, u32 index, ulong *addr,
  * returns:
  *     no returned results
  */
-void android_print_contents(const struct andr_img_hdr *hdr)
+void android_print_contents(const struct andr_boot_img_hdr_v0 *hdr)
 {
+       if (hdr->header_version >= 3) {
+               printf("Content print is not supported for boot image header version > 2");
+               return;
+       }
        const char * const p = IMAGE_INDENT_STRING;
        /* os_version = ver << 11 | lvl */
        u32 os_ver = hdr->os_version >> 11;
@@ -427,7 +700,7 @@ void android_print_contents(const struct andr_img_hdr *hdr)
                       hdr->header_size);
        }
 
-       if (hdr->header_version >= 2) {
+       if (hdr->header_version == 2) {
                printf("%sdtb size:             %x\n", p, hdr->dtb_size);
                printf("%sdtb addr:             %llx\n", p, hdr->dtb_addr);
        }
@@ -485,14 +758,14 @@ static bool android_image_print_dtb_info(const struct fdt_header *fdt,
  */
 bool android_image_print_dtb_contents(ulong hdr_addr)
 {
-       const struct andr_img_hdr *hdr;
+       const struct andr_boot_img_hdr_v0 *hdr;
        bool res;
        ulong dtb_img_addr;     /* address of DTB part in boot image */
        u32 dtb_img_size;       /* size of DTB payload in boot image */
        ulong dtb_addr;         /* address of DTB blob with specified index  */
        u32 i;                  /* index iterator */
 
-       res = android_image_get_dtb_img_addr(hdr_addr, &dtb_img_addr);
+       res = android_image_get_dtb_img_addr(hdr_addr, 0, &dtb_img_addr);
        if (!res)
                return false;
 

diff --git a/boot/image-board.c b/boot/image-board.c
index 9bf7082..d500da1 100644 (file)
--- a/boot/image-board.c
+++ b/boot/image-board.c
@@ -284,7 +284,7 @@ int genimg_get_format(const void *img_addr)
                        return IMAGE_FORMAT_FIT;
        }
        if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE) &&
-           !android_image_check_header(img_addr))
+           is_android_boot_image_header(img_addr))
                return IMAGE_FORMAT_ANDROID;
 
        return IMAGE_FORMAT_INVALID;
@@ -328,7 +328,7 @@ static int select_ramdisk(struct bootm_headers *images, const char *select, u8 a
        bool done_select = !select;
        bool done = false;
        int rd_noffset;
-       ulong rd_addr;
+       ulong rd_addr = 0;
        char *buf;
 
        if (CONFIG_IS_ENABLED(FIT)) {
@@ -426,11 +426,22 @@ static int select_ramdisk(struct bootm_headers *images, const char *select, u8 a
                break;
        case IMAGE_FORMAT_ANDROID:
                if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) {
-                       void *ptr = map_sysmem(images->os.start, 0);
                        int ret;
+                       if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) {
+                               void *boot_img = map_sysmem(get_abootimg_addr(), 0);
+                               void *vendor_boot_img = map_sysmem(get_avendor_bootimg_addr(), 0);
+
+                               ret = android_image_get_ramdisk(boot_img, vendor_boot_img,
+                                                               rd_datap, rd_lenp);
+                               unmap_sysmem(vendor_boot_img);
+                               unmap_sysmem(boot_img);
+                       } else {
+                               void *ptr = map_sysmem(images->os.start, 0);
+
+                               ret = android_image_get_ramdisk(ptr, NULL, rd_datap, rd_lenp);
+                               unmap_sysmem(ptr);
+                       }
 
-                       ret = android_image_get_ramdisk(ptr, rd_datap, rd_lenp);
-                       unmap_sysmem(ptr);
                        if (ret)
                                return ret;
                        done = true;
@@ -1115,7 +1126,8 @@ fallback:
                        }
 
                        /* get script subimage data address and length */
-                       if (fit_image_get_data(fit_hdr, noffset, &fit_data, &fit_len)) {
+                       if (fit_image_get_data_and_size(fit_hdr, noffset,
+                                                       &fit_data, &fit_len)) {
                                puts("Could not find script subimage data\n");
                                return 1;
                        }

diff --git a/boot/image-fdt.c b/boot/image-fdt.c
index 714d05d..f10200f 100644 (file)
--- a/boot/image-fdt.c
+++ b/boot/image-fdt.c
@@ -529,14 +529,15 @@ int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch,
                }
 #ifdef CONFIG_ANDROID_BOOT_IMAGE
        } else if (genimg_get_format(buf) == IMAGE_FORMAT_ANDROID) {
-               struct andr_img_hdr *hdr = buf;
+               void *hdr = buf;
                ulong           fdt_data, fdt_len;
                u32                     fdt_size, dtb_idx;
                /*
                 * Firstly check if this android boot image has dtb field.
                 */
                dtb_idx = (u32)env_get_ulong("adtb_idx", 10, 0);
-               if (android_image_get_dtb_by_index((ulong)hdr, dtb_idx, &fdt_addr, &fdt_size)) {
+               if (android_image_get_dtb_by_index((ulong)hdr, 0,
+                                                  dtb_idx, &fdt_addr, &fdt_size)) {
                        fdt_blob = (char *)map_sysmem(fdt_addr, 0);
                        if (fdt_check_header(fdt_blob))
                                goto no_fdt;

diff --git a/boot/vbe_simple.c b/boot/vbe_simple.c
index 59676d8..12682ab 100644 (file)
--- a/boot/vbe_simple.c
+++ b/boot/vbe_simple.c
@@ -148,11 +148,13 @@ static int vbe_simple_read_bootflow(struct udevice *dev, struct bootflow *bflow)
 {
        int ret;
 
-       if (vbe_phase() == VBE_PHASE_FIRMWARE) {
-               ret = vbe_simple_read_bootflow_fw(dev, bflow);
-               if (ret)
-                       return log_msg_ret("fw", ret);
-               return 0;
+       if (CONFIG_IS_ENABLED(BOOTMETH_VBE_SIMPLE_FW)) {
+               if (vbe_phase() == VBE_PHASE_FIRMWARE) {
+                       ret = vbe_simple_read_bootflow_fw(dev, bflow);
+                       if (ret)
+                               return log_msg_ret("fw", ret);
+                       return 0;
+               }
        }
 
        return -EINVAL;

diff --git a/cmd/2048.c b/cmd/2048.c
new file mode 100644 (file)
index 0000000..fa60aa9
--- /dev/null
+++ b/cmd/2048.c
@@ -0,0 +1,397 @@
+// SPDX-License-Identifier: MIT
+// SPDX-FileCopyrightText: © 2014 Maurits van der Schee
+
+/* Console version of the game "2048" for GNU/Linux */
+
+#include <common.h>
+#include <cli.h>
+#include <command.h>
+#include <rand.h>
+#include <linux/delay.h>
+
+#define SIZE 4
+static uint score;
+
+static void getColor(uint value, char *color, size_t length)
+{
+       u8 original[] = {
+               8, 255, 1, 255, 2, 255, 3, 255,
+               4, 255, 5, 255, 6, 255, 7, 255,
+               9, 0, 10, 0, 11, 0, 12, 0, 13,
+               0, 14, 0, 255, 0, 255, 0};
+       u8 *scheme = original;
+       u8 *background = scheme + 0;
+       u8 *foreground = scheme + 1;
+
+       if (value > 0) {
+               while (value >>= 1) {
+                       if (background + 2 < scheme + sizeof(original)) {
+                               background += 2;
+                               foreground += 2;
+                       }
+               }
+       }
+       snprintf(color, length, "\033[38;5;%d;48;5;%dm", *foreground,
+                *background);
+}
+
+static void drawBoard(u16 board[SIZE][SIZE])
+{
+       int x, y;
+       char color[40], reset[] = "\033[0m";
+
+       printf("\033[H");
+       printf("2048.c %17d pts\n\n", score);
+
+       for (y = 0; y < SIZE; y++) {
+               for (x = 0; x < SIZE; x++) {
+                       getColor(board[x][y], color, 40);
+                       printf("%s", color);
+                       printf("       ");
+                       printf("%s", reset);
+               }
+               printf("\n");
+               for (x = 0; x < SIZE; x++) {
+                       getColor(board[x][y], color, 40);
+                       printf("%s", color);
+                       if (board[x][y] != 0) {
+                               char s[8];
+                               s8 t;
+
+                               snprintf(s, 8, "%u", board[x][y]);
+                               t = 7 - strlen(s);
+                               printf("%*s%s%*s", t - t / 2, "", s, t / 2, "");
+                       } else {
+                               printf("   ·   ");
+                       }
+                       printf("%s", reset);
+               }
+               printf("\n");
+               for (x = 0; x < SIZE; x++) {
+                       getColor(board[x][y], color, 40);
+                       printf("%s", color);
+                       printf("       ");
+                       printf("%s", reset);
+               }
+               printf("\n");
+       }
+       printf("\n");
+       printf("        ←, ↑, →, ↓ or q        \n");
+       printf("\033[A");
+}
+
+static int8_t findTarget(u16 array[SIZE], int x, int stop)
+{
+       int t;
+
+       /* if the position is already on the first, don't evaluate */
+       if (x == 0)
+               return x;
+       for (t = x - 1; t >= 0; t--) {
+               if (array[t]) {
+                       if (array[t] != array[x]) {
+                               /* merge is not possible, take next position */
+                               return t + 1;
+                       }
+                       return t;
+               }
+
+               /* we should not slide further, return this one */
+               if (t == stop)
+                       return t;
+       }
+       /* we did not find a */
+       return x;
+}
+
+static bool slideArray(u16 array[SIZE])
+{
+       bool success = false;
+       int x, t, stop = 0;
+
+       for (x = 0; x < SIZE; x++) {
+               if (array[x] != 0) {
+                       t = findTarget(array, x, stop);
+                       /*
+                        * if target is not original position, then move or
+                        * merge
+                        */
+                       if (t != x) {
+                               /*
+                                * if target is not zero, set stop to avoid
+                                * double merge
+                                */
+                               if (array[t]) {
+                                       score += array[t] + array[x];
+                                       stop = t + 1;
+                               }
+                               array[t] += array[x];
+                               array[x] = 0;
+                               success = true;
+                       }
+               }
+       }
+       return success;
+}
+
+static void rotateBoard(u16 board[SIZE][SIZE])
+{
+       s8 i, j, n = SIZE;
+       int tmp;
+
+       for (i = 0; i < n / 2; i++) {
+               for (j = i; j < n - i - 1; j++) {
+                       tmp = board[i][j];
+                       board[i][j] = board[j][n - i - 1];
+                       board[j][n - i - 1] = board[n - i - 1][n - j - 1];
+                       board[n - i - 1][n - j - 1] = board[n - j - 1][i];
+                       board[n - j - 1][i] = tmp;
+               }
+       }
+}
+
+static bool moveUp(u16 board[SIZE][SIZE])
+{
+       bool success = false;
+       int x;
+
+       for (x = 0; x < SIZE; x++)
+               success |= slideArray(board[x]);
+
+       return success;
+}
+
+static bool moveLeft(u16 board[SIZE][SIZE])
+{
+       bool success;
+
+       rotateBoard(board);
+       success = moveUp(board);
+       rotateBoard(board);
+       rotateBoard(board);
+       rotateBoard(board);
+       return success;
+}
+
+static bool moveDown(u16 board[SIZE][SIZE])
+{
+       bool success;
+
+       rotateBoard(board);
+       rotateBoard(board);
+       success = moveUp(board);
+       rotateBoard(board);
+       rotateBoard(board);
+       return success;
+}
+
+static bool moveRight(u16 board[SIZE][SIZE])
+{
+       bool success;
+
+       rotateBoard(board);
+       rotateBoard(board);
+       rotateBoard(board);
+       success = moveUp(board);
+       rotateBoard(board);
+       return success;
+}
+
+static bool findPairDown(u16 board[SIZE][SIZE])
+{
+       bool success = false;
+       int x, y;
+
+       for (x = 0; x < SIZE; x++) {
+               for (y = 0; y < SIZE - 1; y++) {
+                       if (board[x][y] == board[x][y + 1])
+                               return true;
+               }
+       }
+
+       return success;
+}
+
+static int16_t countEmpty(u16 board[SIZE][SIZE])
+{
+       int x, y;
+       int count = 0;
+
+       for (x = 0; x < SIZE; x++) {
+               for (y = 0; y < SIZE; y++) {
+                       if (board[x][y] == 0)
+                               count++;
+               }
+       }
+       return count;
+}
+
+static bool gameEnded(u16 board[SIZE][SIZE])
+{
+       bool ended = true;
+
+       if (countEmpty(board) > 0)
+               return false;
+       if (findPairDown(board))
+               return false;
+       rotateBoard(board);
+       if (findPairDown(board))
+               ended = false;
+       rotateBoard(board);
+       rotateBoard(board);
+       rotateBoard(board);
+
+       return ended;
+}
+
+static void addRandom(u16 board[SIZE][SIZE])
+{
+       int x, y;
+       int r, len = 0;
+       u16 n, list[SIZE * SIZE][2];
+
+       for (x = 0; x < SIZE; x++) {
+               for (y = 0; y < SIZE; y++) {
+                       if (board[x][y] == 0) {
+                               list[len][0] = x;
+                               list[len][1] = y;
+                               len++;
+                       }
+               }
+       }
+
+       if (len > 0) {
+               r = rand() % len;
+               x = list[r][0];
+               y = list[r][1];
+               n = ((rand() % 10) / 9 + 1) * 2;
+               board[x][y] = n;
+       }
+}
+
+static int test(void)
+{
+       u16 array[SIZE];
+       u16 data[] = {
+               0, 0, 0, 2,     2, 0, 0, 0,
+               0, 0, 2, 2,     4, 0, 0, 0,
+               0, 2, 0, 2,     4, 0, 0, 0,
+               2, 0, 0, 2,     4, 0, 0, 0,
+               2, 0, 2, 0,     4, 0, 0, 0,
+               2, 2, 2, 0,     4, 2, 0, 0,
+               2, 0, 2, 2,     4, 2, 0, 0,
+               2, 2, 0, 2,     4, 2, 0, 0,
+               2, 2, 2, 2,     4, 4, 0, 0,
+               4, 4, 2, 2,     8, 4, 0, 0,
+               2, 2, 4, 4,     4, 8, 0, 0,
+               8, 0, 2, 2,     8, 4, 0, 0,
+               4, 0, 2, 2,     4, 4, 0, 0
+       };
+       u16 *in, *out;
+       u16 t, tests;
+       int i;
+       bool success = true;
+
+       tests = (sizeof(data) / sizeof(data[0])) / (2 * SIZE);
+       for (t = 0; t < tests; t++) {
+               in = data + t * 2 * SIZE;
+               out = in + SIZE;
+               for (i = 0; i < SIZE; i++)
+                       array[i] = in[i];
+               slideArray(array);
+               for (i = 0; i < SIZE; i++) {
+                       if (array[i] != out[i])
+                               success = false;
+               }
+               if (!success) {
+                       for (i = 0; i < SIZE; i++)
+                               printf("%d ", in[i]);
+                       printf(" = > ");
+                       for (i = 0; i < SIZE; i++)
+                               printf("%d ", array[i]);
+                       printf("expected ");
+                       for (i = 0; i < SIZE; i++)
+                               printf("%d ", in[i]);
+                       printf(" = > ");
+                       for (i = 0; i < SIZE; i++)
+                               printf("%d ", out[i]);
+                       printf("\n");
+                       break;
+               }
+       }
+       if (success)
+               printf("All %u tests executed successfully\n", tests);
+
+       return !success;
+}
+
+static int do_2048(struct cmd_tbl *cmdtp, int flag, int argc,
+                  char *const argv[])
+{
+       struct cli_ch_state cch_s, *cch = &cch_s;
+       u16 board[SIZE][SIZE];
+       bool success;
+
+       if (argc == 2 && strcmp(argv[1], "test") == 0)
+               return test();
+
+       score = 0;
+
+       printf("\033[?25l\033[2J\033[H");
+
+       memset(board, 0, sizeof(board));
+       addRandom(board);
+       addRandom(board);
+       drawBoard(board);
+       cli_ch_init(cch);
+       while (true) {
+               int c;
+
+               c = cli_ch_process(cch, 0);
+               if (!c) {
+                       c = getchar();
+                       c = cli_ch_process(cch, c);
+               }
+               switch (c) {
+               case CTL_CH('b'): /* left arrow */
+                       success = moveLeft(board);
+                       break;
+               case CTL_CH('f'): /* right arrow */
+                       success = moveRight(board);
+                       break;
+               case CTL_CH('p'):/* up arrow */
+                       success = moveUp(board);
+                       break;
+               case CTL_CH('n'): /* down arrow */
+                       success = moveDown(board);
+                       break;
+               default:
+                       success = false;
+               }
+               if (success) {
+                       drawBoard(board);
+                       mdelay(150);
+                       addRandom(board);
+                       drawBoard(board);
+                       if (gameEnded(board)) {
+                               printf("         GAME OVER          \n");
+                               break;
+                       }
+               }
+               if (c == 'q') {
+                       printf("            QUIT            \n");
+                       break;
+               }
+       }
+
+       printf("\033[?25h");
+
+       return 0;
+}
+
+U_BOOT_CMD(
+       2048,   2,      1,      do_2048,
+       "The 2048 game",
+       "Use your arrow keys to move the tiles. When two tiles with "
+       "the same number touch, they merge into one!"
+);

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 8c9b430..e45b884 100644 (file)
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1446,7 +1446,8 @@ config CMD_SATA
 
 config CMD_SCSI
        bool "scsi - Access to SCSI devices"
-       default y if SCSI
+       depends on SCSI
+       default y
        help
          This provides a 'scsi' command which provides access to SCSI (Small
          Computer System Interface) devices. The command provides a way to
@@ -1940,6 +1941,17 @@ endif
 
 menu "Misc commands"
 
+config CMD_2048
+       bool "Play 2048"
+       help
+         This is a simple sliding block puzzle game designed by Italian web
+         developer Gabriele Cirulli. The game's objective is to slide numbered
+         tiles on a grid to combine them to create a tile with the number
+         2048.
+
+         This needs ANSI support on your terminal to work. It is not fully
+         functional on a video device.
+
 config CMD_BMP
        bool "Enable 'bmp' command"
        depends on VIDEO
@@ -1980,6 +1992,25 @@ config CMD_BLOCK_CACHE
          during development, but also allows the cache to be disabled when
          it might hurt performance (e.g. when using the ums command).
 
+config CMD_BLKMAP
+       bool "blkmap - Composable virtual block devices"
+       depends on BLKMAP
+       default y if BLKMAP
+       help
+         Create virtual block devices that are backed by various sources,
+         e.g. RAM, or parts of an existing block device. Though much more
+         rudimentary, it borrows a lot of ideas from Linux's device mapper
+         subsystem.
+
+         Example use-cases:
+         - Treat a region of RAM as a block device, i.e. a RAM disk. This let's
+            you extract files from filesystem images stored in RAM (perhaps as a
+            result of a TFTP transfer).
+         - Create a virtual partition on an existing device. This let's you
+            access filesystems that aren't stored at an exact partition
+            boundary. A common example is a filesystem image embedded in an FIT
+            image.
+
 config CMD_BUTTON
        bool "button"
        depends on BUTTON

diff --git a/cmd/Makefile b/cmd/Makefile
index e032091..6c37521 100644 (file)
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -12,6 +12,7 @@ obj-y += panic.o
 obj-y += version.o
 
 # command
+obj-$(CONFIG_CMD_2048) += 2048.o
 obj-$(CONFIG_CMD_ACPI) += acpi.o
 obj-$(CONFIG_CMD_ADDRMAP) += addrmap.o
 obj-$(CONFIG_CMD_AES) += aes.o
@@ -27,6 +28,7 @@ obj-$(CONFIG_CMD_BCB) += bcb.o
 obj-$(CONFIG_CMD_BDI) += bdinfo.o
 obj-$(CONFIG_CMD_BIND) += bind.o
 obj-$(CONFIG_CMD_BINOP) += binop.o
+obj-$(CONFIG_CMD_BLKMAP) += blkmap.o
 obj-$(CONFIG_CMD_BLOBLIST) += bloblist.o
 obj-$(CONFIG_CMD_BLOCK_CACHE) += blkcache.o
 obj-$(CONFIG_CMD_BMP) += bmp.o

diff --git a/cmd/abootimg.c b/cmd/abootimg.c
index f48a9dc..2653b55 100644 (file)
--- a/cmd/abootimg.c
+++ b/cmd/abootimg.c
@@ -15,17 +15,28 @@
 
 /* Please use abootimg_addr() macro to obtain the boot image address */
 static ulong _abootimg_addr = -1;
+static ulong _avendor_bootimg_addr = -1;
+
+ulong get_abootimg_addr(void)
+{
+       return (_abootimg_addr == -1 ? image_load_addr : _abootimg_addr);
+}
+
+ulong get_avendor_bootimg_addr(void)
+{
+       return _avendor_bootimg_addr;
+}
 
 static int abootimg_get_ver(int argc, char *const argv[])
 {
-       const struct andr_img_hdr *hdr;
+       const struct andr_boot_img_hdr_v0 *hdr;
        int res = CMD_RET_SUCCESS;
 
        if (argc > 1)
                return CMD_RET_USAGE;
 
        hdr = map_sysmem(abootimg_addr(), sizeof(*hdr));
-       if (android_image_check_header(hdr)) {
+       if (!is_android_boot_image_header(hdr)) {
                printf("Error: Boot Image header is incorrect\n");
                res = CMD_RET_FAILURE;
                goto exit;
@@ -65,33 +76,43 @@ static int abootimg_get_recovery_dtbo(int argc, char *const argv[])
 
 static int abootimg_get_dtb_load_addr(int argc, char *const argv[])
 {
-       const struct andr_img_hdr *hdr;
-       int res = CMD_RET_SUCCESS;
-
        if (argc > 1)
                return CMD_RET_USAGE;
+       struct andr_image_data img_data = {0};
+       const struct andr_boot_img_hdr_v0 *hdr;
+       const struct andr_vnd_boot_img_hdr *vhdr;
 
        hdr = map_sysmem(abootimg_addr(), sizeof(*hdr));
-       if (android_image_check_header(hdr)) {
-               printf("Error: Boot Image header is incorrect\n");
-               res = CMD_RET_FAILURE;
-               goto exit;
+       if (get_avendor_bootimg_addr() != -1)
+               vhdr = map_sysmem(get_avendor_bootimg_addr(), sizeof(*vhdr));
+
+       if (!android_image_get_data(hdr, vhdr, &img_data)) {
+               if (get_avendor_bootimg_addr() != -1)
+                       unmap_sysmem(vhdr);
+               unmap_sysmem(hdr);
+               return CMD_RET_FAILURE;
        }
 
-       if (hdr->header_version < 2) {
+       if (get_avendor_bootimg_addr() != -1)
+               unmap_sysmem(vhdr);
+       unmap_sysmem(hdr);
+
+       if (img_data.header_version < 2) {
                printf("Error: header_version must be >= 2 for this\n");
-               res = CMD_RET_FAILURE;
-               goto exit;
+               return CMD_RET_FAILURE;
+       }
+
+       if (!img_data.dtb_load_addr) {
+               printf("Error: failed to read dtb_load_addr\n");
+               return CMD_RET_FAILURE;
        }
 
        if (argc == 0)
-               printf("%lx\n", (ulong)hdr->dtb_addr);
+               printf("%lx\n", (ulong)img_data.dtb_load_addr);
        else
-               env_set_hex(argv[0], (ulong)hdr->dtb_addr);
+               env_set_hex(argv[0], (ulong)img_data.dtb_load_addr);
 
-exit:
-       unmap_sysmem(hdr);
-       return res;
+       return CMD_RET_SUCCESS;
 }
 
 static int abootimg_get_dtb_by_index(int argc, char *const argv[])
@@ -117,7 +138,8 @@ static int abootimg_get_dtb_by_index(int argc, char *const argv[])
                return CMD_RET_FAILURE;
        }
 
-       if (!android_image_get_dtb_by_index(abootimg_addr(), num,
+       if (!android_image_get_dtb_by_index(abootimg_addr(),
+                                           get_avendor_bootimg_addr(), num,
                                            &addr, &size)) {
                return CMD_RET_FAILURE;
        }
@@ -158,7 +180,7 @@ static int do_abootimg_addr(struct cmd_tbl *cmdtp, int flag, int argc,
        char *endp;
        ulong img_addr;
 
-       if (argc != 2)
+       if (argc < 2 || argc > 3)
                return CMD_RET_USAGE;
 
        img_addr = hextoul(argv[1], &endp);
@@ -168,6 +190,17 @@ static int do_abootimg_addr(struct cmd_tbl *cmdtp, int flag, int argc,
        }
 
        _abootimg_addr = img_addr;
+
+       if (argc == 3) {
+               img_addr = simple_strtoul(argv[2], &endp, 16);
+               if (*endp != '\0') {
+                       printf("Error: Wrong vendor image address\n");
+                       return CMD_RET_FAILURE;
+               }
+
+               _avendor_bootimg_addr = img_addr;
+       }
+
        return CMD_RET_SUCCESS;
 }
 
@@ -211,7 +244,7 @@ static int do_abootimg_dump(struct cmd_tbl *cmdtp, int flag, int argc,
 }
 
 static struct cmd_tbl cmd_abootimg_sub[] = {
-       U_BOOT_CMD_MKENT(addr, 2, 1, do_abootimg_addr, "", ""),
+       U_BOOT_CMD_MKENT(addr, 3, 1, do_abootimg_addr, "", ""),
        U_BOOT_CMD_MKENT(dump, 2, 1, do_abootimg_dump, "", ""),
        U_BOOT_CMD_MKENT(get, 5, 1, do_abootimg_get, "", ""),
 };
@@ -239,7 +272,7 @@ static int do_abootimg(struct cmd_tbl *cmdtp, int flag, int argc,
 U_BOOT_CMD(
        abootimg, CONFIG_SYS_MAXARGS, 0, do_abootimg,
        "manipulate Android Boot Image",
-       "addr <addr>\n"
+       "addr <boot_img_addr> [<vendor_boot_img_addr>]>\n"
        "    - set the address in RAM where boot image is located\n"
        "      ($loadaddr is used by default)\n"
        "abootimg dump dtb\n"

diff --git a/cmd/blk_common.c b/cmd/blk_common.c
index 75a072c..9f9d432 100644 (file)
--- a/cmd/blk_common.c
+++ b/cmd/blk_common.c
@@ -11,6 +11,7 @@
 #include <common.h>
 #include <blk.h>
 #include <command.h>
+#include <mapmem.h>
 
 int blk_common_cmd(int argc, char *const argv[], enum uclass_id uclass_id,
                   int *cur_devnump)
@@ -63,31 +64,37 @@ int blk_common_cmd(int argc, char *const argv[], enum uclass_id uclass_id,
 
        default: /* at least 4 args */
                if (strcmp(argv[1], "read") == 0) {
-                       ulong addr = hextoul(argv[2], NULL);
+                       phys_addr_t paddr = hextoul(argv[2], NULL);
                        lbaint_t blk = hextoul(argv[3], NULL);
                        ulong cnt = hextoul(argv[4], NULL);
+                       void *vaddr;
                        ulong n;
 
                        printf("\n%s read: device %d block # "LBAFU", count %lu ... ",
                               if_name, *cur_devnump, blk, cnt);
 
+                       vaddr = map_sysmem(paddr, 512 * cnt);
                        n = blk_read_devnum(uclass_id, *cur_devnump, blk, cnt,
-                                           (ulong *)addr);
+                                           vaddr);
+                       unmap_sysmem(vaddr);
 
                        printf("%ld blocks read: %s\n", n,
                               n == cnt ? "OK" : "ERROR");
                        return n == cnt ? 0 : 1;
                } else if (strcmp(argv[1], "write") == 0) {
-                       ulong addr = hextoul(argv[2], NULL);
+                       phys_addr_t paddr = hextoul(argv[2], NULL);
                        lbaint_t blk = hextoul(argv[3], NULL);
                        ulong cnt = hextoul(argv[4], NULL);
+                       void *vaddr;
                        ulong n;
 
                        printf("\n%s write: device %d block # "LBAFU", count %lu ... ",
                               if_name, *cur_devnump, blk, cnt);
 
+                       vaddr = map_sysmem(paddr, 512 * cnt);
                        n = blk_write_devnum(uclass_id, *cur_devnump, blk, cnt,
-                                            (ulong *)addr);
+                                            vaddr);
+                       unmap_sysmem(vaddr);
 
                        printf("%ld blocks written: %s\n", n,
                               n == cnt ? "OK" : "ERROR");

diff --git a/cmd/blkmap.c b/cmd/blkmap.c
new file mode 100644 (file)
index 0000000..b34c013
--- /dev/null
+++ b/cmd/blkmap.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Addiva Elektronik
+ * Author: Tobias Waldekranz <tobias@waldekranz.com>
+ */
+
+#include <blk.h>
+#include <blkmap.h>
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <dm/device.h>
+
+static int blkmap_curr_dev;
+
+struct map_ctx {
+       struct udevice *dev;
+       lbaint_t blknr, blkcnt;
+};
+
+typedef int (*map_parser_fn)(struct map_ctx *ctx, int argc, char *const argv[]);
+
+struct map_handler {
+       const char *name;
+       map_parser_fn fn;
+};
+
+int do_blkmap_map_linear(struct map_ctx *ctx, int argc, char *const argv[])
+{
+       struct blk_desc *lbd;
+       int err, ldevnum;
+       lbaint_t lblknr;
+
+       if (argc < 4)
+               return CMD_RET_USAGE;
+
+       ldevnum = dectoul(argv[2], NULL);
+       lblknr = dectoul(argv[3], NULL);
+
+       lbd = blk_get_devnum_by_uclass_idname(argv[1], ldevnum);
+       if (!lbd) {
+               printf("Found no device matching \"%s %d\"\n",
+                      argv[1], ldevnum);
+               return CMD_RET_FAILURE;
+       }
+
+       err = blkmap_map_linear(ctx->dev, ctx->blknr, ctx->blkcnt,
+                               lbd->bdev, lblknr);
+       if (err) {
+               printf("Unable to map \"%s %d\" at block 0x" LBAF ": %d\n",
+                      argv[1], ldevnum, ctx->blknr, err);
+
+               return CMD_RET_FAILURE;
+       }
+
+       printf("Block 0x" LBAF "+0x" LBAF " mapped to block 0x" LBAF " of \"%s %d\"\n",
+              ctx->blknr, ctx->blkcnt, lblknr, argv[1], ldevnum);
+       return CMD_RET_SUCCESS;
+}
+
+int do_blkmap_map_mem(struct map_ctx *ctx, int argc, char *const argv[])
+{
+       phys_addr_t addr;
+       int err;
+
+       if (argc < 2)
+               return CMD_RET_USAGE;
+
+       addr = hextoul(argv[1], NULL);
+
+       err = blkmap_map_pmem(ctx->dev, ctx->blknr, ctx->blkcnt, addr);
+       if (err) {
+               printf("Unable to map %#llx at block 0x" LBAF ": %d\n",
+                      (unsigned long long)addr, ctx->blknr, err);
+               return CMD_RET_FAILURE;
+       }
+
+       printf("Block 0x" LBAF "+0x" LBAF " mapped to %#llx\n",
+              ctx->blknr, ctx->blkcnt, (unsigned long long)addr);
+       return CMD_RET_SUCCESS;
+}
+
+struct map_handler map_handlers[] = {
+       { .name = "linear", .fn = do_blkmap_map_linear },
+       { .name = "mem", .fn = do_blkmap_map_mem },
+
+       { .name = NULL }
+};
+
+static int do_blkmap_map(struct cmd_tbl *cmdtp, int flag,
+                        int argc, char *const argv[])
+{
+       struct map_handler *handler;
+       struct map_ctx ctx;
+
+       if (argc < 5)
+               return CMD_RET_USAGE;
+
+       ctx.dev = blkmap_from_label(argv[1]);
+       if (!ctx.dev) {
+               printf("\"%s\" is not the name of any known blkmap\n", argv[1]);
+               return CMD_RET_FAILURE;
+       }
+
+       ctx.blknr = hextoul(argv[2], NULL);
+       ctx.blkcnt = hextoul(argv[3], NULL);
+       argc -= 4;
+       argv += 4;
+
+       for (handler = map_handlers; handler->name; handler++) {
+               if (!strcmp(handler->name, argv[0]))
+                       return handler->fn(&ctx, argc, argv);
+       }
+
+       printf("Unknown map type \"%s\"\n", argv[0]);
+       return CMD_RET_USAGE;
+}
+
+static int do_blkmap_create(struct cmd_tbl *cmdtp, int flag,
+                           int argc, char *const argv[])
+{
+       const char *label;
+       int err;
+
+       if (argc != 2)
+               return CMD_RET_USAGE;
+
+       label = argv[1];
+
+       err = blkmap_create(label, NULL);
+       if (err) {
+               printf("Unable to create \"%s\": %d\n", label, err);
+               return CMD_RET_FAILURE;
+       }
+
+       printf("Created \"%s\"\n", label);
+       return CMD_RET_SUCCESS;
+}
+
+static int do_blkmap_destroy(struct cmd_tbl *cmdtp, int flag,
+                            int argc, char *const argv[])
+{
+       struct udevice *dev;
+       const char *label;
+       int err;
+
+       if (argc != 2)
+               return CMD_RET_USAGE;
+
+       label = argv[1];
+
+       dev = blkmap_from_label(label);
+       if (!dev) {
+               printf("\"%s\" is not the name of any known blkmap\n", label);
+               return CMD_RET_FAILURE;
+       }
+
+       err = blkmap_destroy(dev);
+       if (err) {
+               printf("Unable to destroy \"%s\": %d\n", label, err);
+               return CMD_RET_FAILURE;
+       }
+
+       printf("Destroyed \"%s\"\n", label);
+       return CMD_RET_SUCCESS;
+}
+
+static int do_blkmap_get(struct cmd_tbl *cmdtp, int flag,
+                        int argc, char *const argv[])
+{
+       struct udevice *dev;
+       const char *label;
+       int err;
+
+       if (argc < 3)
+               return CMD_RET_USAGE;
+
+       label = argv[1];
+
+       dev = blkmap_from_label(label);
+       if (!dev) {
+               printf("\"%s\" is not the name of any known blkmap\n", label);
+               return CMD_RET_FAILURE;
+       }
+
+       if (!strcmp(argv[2], "dev")) {
+               if (argc == 3) {
+                       printf("%d\n", dev_seq(dev));
+               } else {
+                       err = env_set_hex(argv[3], dev_seq(dev));
+                       if (err)
+                               return CMD_RET_FAILURE;
+               }
+       } else {
+               return CMD_RET_USAGE;
+       }
+
+       return CMD_RET_SUCCESS;
+}
+
+static int do_blkmap_common(struct cmd_tbl *cmdtp, int flag,
+                           int argc, char *const argv[])
+{
+       /* The subcommand parsing pops the original argv[0] ("blkmap")
+        * which blk_common_cmd expects. Push it back again.
+        */
+       argc++;
+       argv--;
+
+       return blk_common_cmd(argc, argv, UCLASS_BLKMAP, &blkmap_curr_dev);
+}
+
+U_BOOT_CMD_WITH_SUBCMDS(
+       blkmap, "Composeable virtual block devices",
+       "info - list configured devices\n"
+       "blkmap part - list available partitions on current blkmap device\n"
+       "blkmap dev [<dev>] - show or set current blkmap device\n"
+       "blkmap read <addr> <blk#> <cnt>\n"
+       "blkmap write <addr> <blk#> <cnt>\n"
+       "blkmap get <label> dev [<var>] - store device number in variable\n"
+       "blkmap create <label> - create device\n"
+       "blkmap destroy <label> - destroy device\n"
+       "blkmap map <label> <blk#> <cnt> linear <interface> <dev> <blk#> - device mapping\n"
+       "blkmap map <label> <blk#> <cnt> mem <addr> - memory mapping\n",
+       U_BOOT_SUBCMD_MKENT(info, 2, 1, do_blkmap_common),
+       U_BOOT_SUBCMD_MKENT(part, 2, 1, do_blkmap_common),
+       U_BOOT_SUBCMD_MKENT(dev, 4, 1, do_blkmap_common),
+       U_BOOT_SUBCMD_MKENT(read, 5, 1, do_blkmap_common),
+       U_BOOT_SUBCMD_MKENT(write, 5, 1, do_blkmap_common),
+       U_BOOT_SUBCMD_MKENT(get, 5, 1, do_blkmap_get),
+       U_BOOT_SUBCMD_MKENT(create, 2, 1, do_blkmap_create),
+       U_BOOT_SUBCMD_MKENT(destroy, 2, 1, do_blkmap_destroy),
+       U_BOOT_SUBCMD_MKENT(map, 32, 1, do_blkmap_map));

diff --git a/cmd/bootflow.c b/cmd/bootflow.c
index 42f6e14..cfe3422 100644 (file)
--- a/cmd/bootflow.c
+++ b/cmd/bootflow.c
@@ -181,6 +181,9 @@ static int do_bootflow_scan(struct cmd_tbl *cmdtp, int flag, int argc,
        if (list)
                show_footer(i, num_valid);
 
+       if (IS_ENABLED(CONFIG_CMD_BOOTFLOW_FULL) && !num_valid && !list)
+               printf("No bootflows found; try again with -l\n");
+
        return 0;
 }
 
@@ -387,6 +390,11 @@ static int do_bootflow_menu(struct cmd_tbl *cmdtp, int flag, int argc,
        bool text_mode = false;
        int ret;
 
+       if (!IS_ENABLED(CONFIG_EXPO)) {
+               printf("Menu not supported\n");
+               return CMD_RET_FAILURE;
+       }
+
        if (argc > 1 && *argv[1] == '-')
                text_mode = strchr(argv[1], 't');
 
@@ -394,20 +402,15 @@ static int do_bootflow_menu(struct cmd_tbl *cmdtp, int flag, int argc,
        if (ret)
                return CMD_RET_FAILURE;
 
-       if (IS_ENABLED(CONFIG_EXPO)) {
-               ret = bootflow_menu_run(std, text_mode, &bflow);
-               if (ret) {
-                       if (ret == -EAGAIN)
-                               printf("Nothing chosen\n");
-                       else
-                               printf("Menu failed (err=%d)\n", ret);
+       ret = bootflow_menu_run(std, text_mode, &bflow);
+       if (ret) {
+               if (ret == -EAGAIN)
+                       printf("Nothing chosen\n");
+               else {
+                       printf("Menu failed (err=%d)\n", ret);
+                       return CMD_RET_FAILURE;
                }
-       } else {
-               printf("Menu not supported\n");
-               ret = -ENOSYS;
        }
-       if (ret)
-               return CMD_RET_FAILURE;
 
        printf("Selected: %s\n", bflow->os_name ? bflow->os_name : bflow->name);
        std->cur_bootflow = bflow;

diff --git a/cmd/console.c b/cmd/console.c
index 620a961..58c2cf1 100644 (file)
--- a/cmd/console.c
+++ b/cmd/console.c
@@ -9,6 +9,7 @@
  */
 #include <common.h>
 #include <command.h>
+#include <iomux.h>
 #include <stdio_dev.h>
 
 extern void _do_coninfo (void);
@@ -33,9 +34,15 @@ static int do_coninfo(struct cmd_tbl *cmd, int flag, int argc,
                       (dev->flags & DEV_FLAGS_OUTPUT) ? "O" : "");
 
                for (l = 0; l < MAX_FILES; l++) {
-                       if (stdio_devices[l] == dev) {
-                               printf("|   |-- %s\n", stdio_names[l]);
+                       if (CONFIG_IS_ENABLED(CONSOLE_MUX)) {
+                               if (iomux_match_device(console_devices[l],
+                                                      cd_count[l], dev) >= 0)
+                                       printf("|   |-- %s\n", stdio_names[l]);
+                       } else {
+                               if (stdio_devices[l] == dev)
+                                       printf("|   |-- %s\n", stdio_names[l]);
                        }
+
                }
        }
        return 0;

diff --git a/cmd/date.c b/cmd/date.c
index 58505e6..fe9c8c6 100644 (file)
--- a/cmd/date.c
+++ b/cmd/date.c
@@ -98,7 +98,7 @@ static int do_date(struct cmd_tbl *cmdtp, int flag, int argc,
                                puts("## Get date failed\n");
                        }
                }
-               /* FALL TROUGH */
+               fallthrough;
        case 1:                 /* get date & time */
 #ifdef CONFIG_DM_RTC
                rcode = dm_rtc_get(dev, &tm);

diff --git a/cmd/fdt.c b/cmd/fdt.c
index 04b664e..aae3278 100644 (file)
--- a/cmd/fdt.c
+++ b/cmd/fdt.c
@@ -36,16 +36,21 @@ static int is_printable_string(const void *data, int len);
  */
 struct fdt_header *working_fdt;
 
-void set_working_fdt_addr(ulong addr)
+static void set_working_fdt_addr_quiet(ulong addr)
 {
        void *buf;
 
-       printf("Working FDT set to %lx\n", addr);
        buf = map_sysmem(addr, 0);
        working_fdt = buf;
        env_set_hex("fdtaddr", addr);
 }
 
+void set_working_fdt_addr(ulong addr)
+{
+       printf("Working FDT set to %lx\n", addr);
+       set_working_fdt_addr_quiet(addr);
+}
+
 /*
  * Get a value from the fdt and format it to be set in the environment
  */
@@ -192,10 +197,14 @@ static int do_fdt(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
                if ((quiet && fdt_check_header(blob)) ||
                    (!quiet && !fdt_valid(&blob)))
                        return 1;
-               if (control)
+               if (control) {
                        gd->fdt_blob = blob;
-               else
-                       set_working_fdt_addr(addr);
+               } else {
+                       if (quiet)
+                               set_working_fdt_addr_quiet(addr);
+                       else
+                               set_working_fdt_addr(addr);
+               }
 
                if (argc >= 2) {
                        int  len;
@@ -475,18 +484,9 @@ static int do_fdt(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
                                        if (ret != 0)
                                                return ret;
                                } else if (subcmd[0] == 'a') {
-                                       /* Get address */
-                                       char buf[19];
-
-                                       snprintf(buf, sizeof(buf), "%lx",
-                                                (ulong)map_to_sysmem(nodep));
-                                       env_set(var, buf);
+                                       env_set_hex(var, (ulong)map_to_sysmem(nodep));
                                } else if (subcmd[0] == 's') {
-                                       /* Get size */
-                                       char buf[11];
-
-                                       sprintf(buf, "0x%08X", len);
-                                       env_set(var, buf);
+                                       env_set_hex(var, len);
                                } else
                                        return CMD_RET_USAGE;
                                return 0;

diff --git a/cmd/ide.c b/cmd/ide.c
index 6739f0b..ddc87d3 100644 (file)
--- a/cmd/ide.c
+++ b/cmd/ide.c
@@ -10,12 +10,15 @@
 
 #include <common.h>
 #include <blk.h>
+#include <dm.h>
 #include <config.h>
 #include <watchdog.h>
 #include <command.h>
 #include <image.h>
 #include <asm/byteorder.h>
 #include <asm/io.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
 
 #include <ide.h>
 #include <ata.h>
@@ -31,8 +34,25 @@ int do_ide(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
        if (argc == 2) {
                if (strncmp(argv[1], "res", 3) == 0) {
+                       struct udevice *dev;
+                       int ret;
+
                        puts("\nReset IDE: ");
-                       ide_init();
+                       ret = uclass_find_first_device(UCLASS_IDE, &dev);
+                       ret = device_remove(dev, DM_REMOVE_NORMAL);
+                       if (!ret)
+                               ret = device_chld_unbind(dev, NULL);
+                       if (ret) {
+                               printf("Cannot remove IDE (err=%dE)\n", ret);
+                               return CMD_RET_FAILURE;
+                       }
+
+                       ret = uclass_first_device_err(UCLASS_IDE, &dev);
+                       if (ret) {
+                               printf("Init failed (err=%dE)\n", ret);
+                               return CMD_RET_FAILURE;
+                       }
+
                        return 0;
                }
        }

diff --git a/cmd/mmc.c b/cmd/mmc.c
index 94deb9a..c6bd81c 100644 (file)
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -175,7 +175,7 @@ static int do_mmcinfo(struct cmd_tbl *cmdtp, int flag, int argc,
                        curr_device = 0;
                else {
                        puts("No MMC device available\n");
-                       return 1;
+                       return CMD_RET_FAILURE;
                }
        }
 
@@ -927,7 +927,7 @@ static int mmc_partconf_print(struct mmc *mmc, const char *varname)
 static int do_mmc_partconf(struct cmd_tbl *cmdtp, int flag,
                           int argc, char *const argv[])
 {
-       int dev;
+       int ret, dev;
        struct mmc *mmc;
        u8 ack, part_num, access;
 
@@ -953,13 +953,17 @@ static int do_mmc_partconf(struct cmd_tbl *cmdtp, int flag,
        access = dectoul(argv[4], NULL);
 
        /* acknowledge to be sent during boot operation */
-       return mmc_set_part_conf(mmc, ack, part_num, access);
+       ret = mmc_set_part_conf(mmc, ack, part_num, access);
+       if (ret != 0)
+               return CMD_RET_FAILURE;
+
+       return CMD_RET_SUCCESS;
 }
 
 static int do_mmc_rst_func(struct cmd_tbl *cmdtp, int flag,
                           int argc, char *const argv[])
 {
-       int dev;
+       int ret, dev;
        struct mmc *mmc;
        u8 enable;
 
@@ -988,7 +992,11 @@ static int do_mmc_rst_func(struct cmd_tbl *cmdtp, int flag,
                return CMD_RET_FAILURE;
        }
 
-       return mmc_set_rst_n_function(mmc, enable);
+       ret = mmc_set_rst_n_function(mmc, enable);
+       if (ret != 0)
+               return CMD_RET_FAILURE;
+
+       return CMD_RET_SUCCESS;
 }
 #endif
 static int do_mmc_setdsr(struct cmd_tbl *cmdtp, int flag,

diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c
index 49797b2..ca24a5c 100644 (file)
--- a/cmd/mvebu/bubt.c
+++ b/cmd/mvebu/bubt.c
@@ -223,8 +223,7 @@ static int mmc_burn_image(size_t image_size)
        orig_part = mmc->block_dev.hwpart;
 #endif
 
-       part = (mmc->part_config >> 3) & PART_ACCESS_MASK;
-
+       part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
        if (part == 7)
                part = 0;
 
@@ -925,8 +924,11 @@ static int check_image_header(void)
        offset = le32_to_cpu(hdr->srcaddr);
        size = le32_to_cpu(hdr->blocksize);
 
-       if (hdr->blockid == 0x78) /* SATA id */
-               offset *= 512;
+       if (hdr->blockid == 0x78) { /* SATA id */
+               struct blk_desc *blk_dev = IS_ENABLED(BLK) ? blk_get_devnum_by_uclass_id(UCLASS_SCSI, 0) : NULL;
+               unsigned long blksz = blk_dev ? blk_dev->blksz : 512;
+               offset *= blksz;
+       }
 
        if (offset % 4 != 0 || size < 4 || size % 4 != 0) {
                printf("Error: Bad A38x image blocksize.\n");

diff --git a/cmd/pci.c b/cmd/pci.c
index 58a7475..78b661d 100644 (file)
--- a/cmd/pci.c
+++ b/cmd/pci.c
@@ -517,6 +517,7 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
                        addr = hextoul(argv[3], NULL);
                if (argc > 4)
                        value = hextoul(argv[4], NULL);
+               fallthrough;
        case 'h':               /* header */
        case 'b':               /* bars */
                if (argc < 3)

diff --git a/cmd/regulator.c b/cmd/regulator.c
index ed4996d..8988c90 100644 (file)
--- a/cmd/regulator.c
+++ b/cmd/regulator.c
@@ -37,6 +37,7 @@ static int do_dev(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
                        printf("Can't get the regulator: %s!\n", name);
                        return failure(ret);
                }
+               fallthrough;
        case 1:
                if (!currdev) {
                        printf("Regulator device is not set!\n\n");

diff --git a/common/Kconfig b/common/Kconfig
index 7ff6255..f2783ee 100644 (file)
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -742,7 +742,7 @@ config SYS_MALLOC_BOOTPARAMS
 config SYS_BOOTPARAMS_LEN
        hex "Size of the bootparam buffer to malloc in bytes"
        depends on SYS_MALLOC_BOOTPARAMS
-       default 0x20000 if MIPS || RCAR_GEN3
+       default 0x20000 if MIPS || RCAR_64
        default 0x10000
 
 config ID_EEPROM

diff --git a/common/board_f.c b/common/board_f.c
index f3c1ab5..1688e27 100644 (file)
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -863,7 +863,7 @@ static const init_fnc_t init_sequence_f[] = {
        /* get CPU and bus clocks according to the environment variable */
        get_clocks,             /* get CPU and bus clocks (etc.) */
 #endif
-#if !defined(CONFIG_M68K)
+#if !defined(CONFIG_M68K) || (defined(CONFIG_M68K) && !defined(CONFIG_MCFTMR))
        timer_init,             /* initialize timer */
 #endif
 #if defined(CONFIG_BOARD_POSTCLK_INIT)

diff --git a/common/board_r.c b/common/board_r.c
index 6b4180b..d798c00 100644 (file)
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -519,20 +519,6 @@ static int initr_post(void)
 }
 #endif
 
-#if defined(CONFIG_IDE) && !defined(CONFIG_BLK)
-static int initr_ide(void)
-{
-       puts("IDE:   ");
-#if defined(CONFIG_START_IDE)
-       if (board_start_ide())
-               ide_init();
-#else
-       ide_init();
-#endif
-       return 0;
-}
-#endif
-
 #if defined(CFG_PRAM)
 /*
  * Export available size of memory for Linux, taking into account the
@@ -783,9 +769,6 @@ static init_fnc_t init_sequence_r[] = {
 #ifdef CONFIG_POST
        initr_post,
 #endif
-#if defined(CONFIG_IDE) && !defined(CONFIG_BLK)
-       initr_ide,
-#endif
 #ifdef CONFIG_LAST_STAGE_INIT
        INIT_FUNC_WATCHDOG_RESET
        /*

diff --git a/common/cli_getch.c b/common/cli_getch.c
index 87c23ed..61d4cb2 100644 (file)
--- a/common/cli_getch.c
+++ b/common/cli_getch.c
@@ -129,7 +129,7 @@ static int cli_ch_esc(struct cli_ch_state *cch, int ichar,
 
        *actp = act;
 
-       return act == ESC_CONVERTED ? ichar : 0;
+       return ichar;
 }
 
 int cli_ch_process(struct cli_ch_state *cch, int ichar)
@@ -145,6 +145,7 @@ int cli_ch_process(struct cli_ch_state *cch, int ichar)
                                return cch->esc_save[cch->emit_upto++];
                        cch->emit_upto = 0;
                        cch->emitting = false;
+                       cch->esc_len = 0;
                }
                return 0;
        } else if (ichar == -ETIMEDOUT) {
@@ -185,7 +186,7 @@ int cli_ch_process(struct cli_ch_state *cch, int ichar)
                        cch->esc_save[cch->esc_len++] = ichar;
                        ichar = cch->esc_save[cch->emit_upto++];
                        cch->emitting = true;
-                       break;
+                       return ichar;
                case ESC_CONVERTED:
                        /* valid escape sequence, return the resulting char */
                        cch->esc_len = 0;

diff --git a/common/cli_readline.c b/common/cli_readline.c
index 709e9c3..e83743e 100644 (file)
--- a/common/cli_readline.c
+++ b/common/cli_readline.c
@@ -284,10 +284,9 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len,
                        }
 
                        ichar = getcmd_getch();
+                       ichar = cli_ch_process(cch, ichar);
                }
 
-               ichar = cli_ch_process(cch, ichar);
-
                /* ichar=0x0 when error occurs in U-Boot getc */
                if (!ichar)
                        continue;

diff --git a/common/fdt_simplefb.c b/common/fdt_simplefb.c
index 282c34f..069ced7 100644 (file)
--- a/common/fdt_simplefb.c
+++ b/common/fdt_simplefb.c
@@ -71,7 +71,13 @@ int fdt_simplefb_add_node(void *blob)
        return fdt_simplefb_configure_node(blob, off);
 }
 
-int fdt_simplefb_enable_existing_node(void *blob)
+/**
+ * fdt_simplefb_enable_existing_node() - enable simple-framebuffer DT node
+ *
+ * @blob:      device-tree
+ * Return:     0 on success, non-zero otherwise
+ */
+static int fdt_simplefb_enable_existing_node(void *blob)
 {
        int off;
 

diff --git a/common/fdt_support.c b/common/fdt_support.c
index dbceec6..2053fe3 100644 (file)
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -1486,11 +1486,11 @@ out:
 }
 
 /**
- * fdt_node_offset_by_compat_reg: Find a node that matches compatiable and
+ * fdt_node_offset_by_compat_reg: Find a node that matches compatible and
  * who's reg property matches a physical cpu address
  *
  * @blob: ptr to device tree
- * @compat: compatiable string to match
+ * @compat: compatible string to match
  * @compat_off: property name
  *
  */

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index bd5e6ad..a072216 100644 (file)
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -378,7 +378,7 @@ int default_spl_mmc_emmc_boot_partition(struct mmc *mmc)
         * 1 and 2 match up to boot0 / boot1 and 7 is user data
         * which is the first physical partition (0).
         */
-       part = (mmc->part_config >> 3) & PART_ACCESS_MASK;
+       part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
        if (part == 7)
                part = 0;
 #endif

diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig
index 3263414..7b46580 100644 (file)
--- a/configs/M5208EVBE_defconfig
+++ b/configs/M5208EVBE_defconfig
@@ -4,7 +4,6 @@ CONFIG_SYS_MALLOC_LEN=0x20000
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="M5208EVBE"
-CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x40010000
 CONFIG_ENV_ADDR=0x2000
 CONFIG_TARGET_M5208EVBE=y
@@ -38,11 +37,8 @@ CONFIG_NETMASK="255.255.255.0"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.162.1.1"
 CONFIG_SYS_RX_ETH_BUFFER=8
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x58000
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=80000
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y

diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig
index 0b92456..f96a2f2 100644 (file)
--- a/configs/M5235EVB_Flash32_defconfig
+++ b/configs/M5235EVB_Flash32_defconfig
@@ -61,3 +61,4 @@ CONFIG_MCFFEC=y
 CONFIG_MII=y
 CONFIG_MCFUART=y
 CONFIG_WATCHDOG_TIMEOUT_MSECS=5000
+CONFIG_DM_I2C=y

diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig
index fbd3e08..67991b5 100644 (file)
--- a/configs/M5235EVB_defconfig
+++ b/configs/M5235EVB_defconfig
@@ -4,7 +4,6 @@ CONFIG_SYS_MALLOC_LEN=0x20000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="M5235EVB"
-CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_TARGET_M5235EVB=y
@@ -61,3 +60,4 @@ CONFIG_MCFFEC=y
 CONFIG_MII=y
 CONFIG_MCFUART=y
 CONFIG_WATCHDOG_TIMEOUT_MSECS=5000
+CONFIG_DM_I2C=y

diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig
index e6ab998..99bf18f 100644 (file)
--- a/configs/M5253DEMO_defconfig
+++ b/configs/M5253DEMO_defconfig
@@ -37,11 +37,8 @@ CONFIG_SYS_ATA_ALT_OFFSET=0xC0
 CONFIG_SYS_ATA_IDE0_OFFSET=0
 CONFIG_ATAPI=y
 CONFIG_IDE_RESET=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x280
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=80000
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_SYS_MAX_FLASH_SECT=2048
 CONFIG_USE_SYS_MAX_FLASH_BANKS=y

diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig
index 1c51c4a..6b46c6f 100644 (file)
--- a/configs/M5272C3_defconfig
+++ b/configs/M5272C3_defconfig
@@ -4,7 +4,6 @@ CONFIG_SYS_MALLOC_LEN=0x40000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="M5272C3"
-CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_TARGET_M5272C3=y

diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig
index ca1c184..557e694 100644 (file)
--- a/configs/M5275EVB_defconfig
+++ b/configs/M5275EVB_defconfig
@@ -4,7 +4,6 @@ CONFIG_SYS_MALLOC_LEN=0x40000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="M5275EVB"
-CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x800000
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_TARGET_M5275EVB=y
@@ -34,11 +33,8 @@ CONFIG_OVERWRITE_ETHADDR_ONCE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
 CONFIG_SYS_RX_ETH_BUFFER=8
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x300
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=80000
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_FLASH_SHOW_PROGRESS=0

diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig
index 2b053e3..1997f38 100644 (file)
--- a/configs/M5282EVB_defconfig
+++ b/configs/M5282EVB_defconfig
@@ -4,7 +4,6 @@ CONFIG_SYS_MALLOC_LEN=0x40000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="M5282EVB"
-CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_TARGET_M5282EVB=y

diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig
index c70964f..7014e2f 100644 (file)
--- a/configs/M53017EVB_defconfig
+++ b/configs/M53017EVB_defconfig
@@ -4,7 +4,6 @@ CONFIG_SYS_MALLOC_LEN=0x20000
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_SECT_SIZE=0x8000
 CONFIG_DEFAULT_DEVICE_TREE="M53017EVB"
-CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x40010000
 CONFIG_ENV_ADDR=0x40000
 CONFIG_TARGET_M53017EVB=y
@@ -40,11 +39,8 @@ CONFIG_NETMASK="255.255.255.0"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.162.1.1"
 CONFIG_SYS_RX_ETH_BUFFER=8
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x58000
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=80000
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
@@ -57,6 +53,7 @@ CONFIG_SYS_MAX_FLASH_SECT=137
 CONFIG_MCFFEC=y
 CONFIG_SYS_UNIFY_CACHE=y
 CONFIG_MII=y
+CONFIG_DM_RTC=y
 CONFIG_MCFRTC=y
 CONFIG_SYS_MCFRTC_BASE=0xFC0A8000
 CONFIG_MCFUART=y

diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig
index 455eea2..1857cf7 100644 (file)
--- a/configs/M5329AFEE_defconfig
+++ b/configs/M5329AFEE_defconfig
@@ -4,7 +4,6 @@ CONFIG_SYS_MALLOC_LEN=0x20000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="M5329AFEE"
-CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x40010000
 CONFIG_ENV_ADDR=0x4000
 CONFIG_TARGET_M5329EVB=y
@@ -39,11 +38,8 @@ CONFIG_NETMASK="255.255.255.0"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.162.1.1"
 CONFIG_SYS_RX_ETH_BUFFER=8
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x58000
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=80000
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
@@ -55,6 +51,7 @@ CONFIG_SYS_MAX_FLASH_SECT=137
 CONFIG_MCFFEC=y
 CONFIG_SYS_UNIFY_CACHE=y
 CONFIG_MII=y
+CONFIG_DM_RTC=y
 CONFIG_MCFRTC=y
 CONFIG_SYS_MCFRTC_BASE=0xFC0A8000
 CONFIG_MCFUART=y

diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig
index 0251444..449ad2a 100644 (file)
--- a/configs/M5329BFEE_defconfig
+++ b/configs/M5329BFEE_defconfig
@@ -4,7 +4,6 @@ CONFIG_SYS_MALLOC_LEN=0x20000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="M5329BFEE"
-CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x40010000
 CONFIG_ENV_ADDR=0x4000
 CONFIG_TARGET_M5329EVB=y
@@ -40,11 +39,8 @@ CONFIG_NETMASK="255.255.255.0"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.162.1.1"
 CONFIG_SYS_RX_ETH_BUFFER=8
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x58000
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=80000
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
@@ -57,6 +53,7 @@ CONFIG_MTD_RAW_NAND=y
 CONFIG_MCFFEC=y
 CONFIG_SYS_UNIFY_CACHE=y
 CONFIG_MII=y
+CONFIG_DM_RTC=y
 CONFIG_MCFRTC=y
 CONFIG_SYS_MCFRTC_BASE=0xFC0A8000
 CONFIG_MCFUART=y

diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig
index eec95da..05c3b37 100644 (file)
--- a/configs/M5373EVB_defconfig
+++ b/configs/M5373EVB_defconfig
@@ -4,7 +4,6 @@ CONFIG_SYS_MALLOC_LEN=0x20000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="M5373EVB"
-CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x40010000
 CONFIG_ENV_ADDR=0x4000
 CONFIG_TARGET_M5373EVB=y
@@ -40,7 +39,8 @@ CONFIG_NETMASK="255.255.255.0"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.162.1.1"
 CONFIG_SYS_RX_ETH_BUFFER=8
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
 CONFIG_SYS_I2C_FSL=y
 CONFIG_SYS_FSL_I2C_OFFSET=0x58000
 CONFIG_SYS_I2C_SLAVE=0x7F

diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 8f3f54c..7bb878f 100644 (file)
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -4,6 +4,8 @@ CONFIG_SYS_MALLOC_LEN=0x80000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb"
+CONFIG_DEBUG_UART_BASE=0xe0004500
+CONFIG_DEBUG_UART_CLOCK=333333000
 CONFIG_SYS_CLK_FREQ=66666667
 CONFIG_ENV_ADDR=0xFE080000
 # CONFIG_SYS_PCI_64BIT is not set
@@ -118,6 +120,7 @@ CONFIG_LCRR_DBYP_PLL_BYPASSED=y
 CONFIG_LCRR_CLKDIV_8=y
 CONFIG_FSL_SERDES=y
 CONFIG_USE_UBOOTPATH=y
+CONFIG_DEBUG_UART=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -185,7 +188,9 @@ CONFIG_MII=y
 CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_RTC_DS1374=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_FSL=y

diff --git a/configs/a64-olinuxino-emmc_defconfig b/configs/a64-olinuxino-emmc_defconfig
index 8ec9eb3..a5989fa 100644 (file)
--- a/configs/a64-olinuxino-emmc_defconfig
+++ b/configs/a64-olinuxino-emmc_defconfig
@@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino-emmc"
 CONFIG_SPL=y
 CONFIG_MACH_SUN50I=y
-CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SUPPORT_EMMC_BOOT=y

diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig
index 16cef18..0b469c2 100644 (file)
--- a/configs/a64-olinuxino_defconfig
+++ b/configs/a64-olinuxino_defconfig
@@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino"
 CONFIG_SPL=y
 CONFIG_MACH_SUN50I=y
-CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SUN8I_EMAC=y

diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index bddd94c..4af274e 100644 (file)
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -30,7 +30,7 @@ CONFIG_SPL_SPI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
 CONFIG_LOGLEVEL=7

diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig
index 898403a..bdd4b64 100644 (file)
--- a/configs/am65x_hs_evm_a53_defconfig
+++ b/configs/am65x_hs_evm_a53_defconfig
@@ -30,7 +30,7 @@ CONFIG_SPL_SPI=y
 # CONFIG_PSCI_RESET is not set
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_fit_${boot}; run get_overlaystring; run run_fit"
 CONFIG_LOGLEVEL=7

diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig
index ae44b66..292af6e 100644 (file)
--- a/configs/amarula_a64_relic_defconfig
+++ b/configs/amarula_a64_relic_defconfig
@@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
 CONFIG_SPL=y
 CONFIG_MACH_SUN50I=y
-CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 # CONFIG_VIDEO_DE2 is not set
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig
index 827ebfe..f12859b 100644 (file)
--- a/configs/astro_mcf5373l_defconfig
+++ b/configs/astro_mcf5373l_defconfig
@@ -34,11 +34,8 @@ CONFIG_FPGA_CYCLON2=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_SPARTAN3=y
 CONFIG_SYS_FPGA_PROG_FEEDBACK=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x58000
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=80000
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_FLASH_SHOW_PROGRESS=0
@@ -46,6 +43,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_SECT=259
+CONFIG_DM_RTC=y
 CONFIG_MCFRTC=y
 CONFIG_SYS_MCFRTC_BASE=0xFC0A8000
 CONFIG_MCFUART=y

diff --git a/configs/bananapi-cm4-cm4io_defconfig b/configs/bananapi-cm4-cm4io_defconfig
new file mode 100644 (file)
index 0000000..0801b9d
--- /dev/null
+++ b/configs/bananapi-cm4-cm4io_defconfig
@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-bananapi-cm4-cm4io"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING="bpi-cm4io"
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_REMAKE_ELF=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_MESON=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y

diff --git a/configs/bananapi-m2-pro_defconfig b/configs/bananapi-m2-pro_defconfig
new file mode 100644 (file)
index 0000000..28b603f
--- /dev/null
+++ b/configs/bananapi-m2-pro_defconfig
@@ -0,0 +1,76 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-bananapi-m2-pro"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING="bpi-m2-pro"
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_REMAKE_ELF=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y

diff --git a/configs/bananapi-m2s_defconfig b/configs/bananapi-m2s_defconfig
new file mode 100644 (file)
index 0000000..3109e0c
--- /dev/null
+++ b/configs/bananapi-m2s_defconfig
@@ -0,0 +1,82 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-bananapi-m2s"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" bpi-m2s"
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_REMAKE_ELF=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_AHCI_PCI=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_MESON=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y

diff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig
index 99dc2f7..d957071 100644 (file)
--- a/configs/bananapi_m64_defconfig
+++ b/configs/bananapi_m64_defconfig
@@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-bananapi-m64"
 CONFIG_SPL=y
 CONFIG_MACH_SUN50I=y
-CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SUPPORT_EMMC_BOOT=y

diff --git a/configs/beelink-gt1-ultimate_defconfig b/configs/beelink-gt1-ultimate_defconfig
new file mode 100644 (file)
index 0000000..4ec76cb
--- /dev/null
+++ b/configs/beelink-gt1-ultimate_defconfig
@@ -0,0 +1,78 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-gt1-ultimate"
+CONFIG_DM_RESET=y
+CONFIG_MESON_GXM=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" beelink-gt1"
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SARADC_MESON=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MMIOREG=y
+CONFIG_MESON_GXL_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXL=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_GXL=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y

diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index b50577f..2f1a201 100644 (file)
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -104,4 +104,3 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_FDT_FIXUP_PARTITIONS=y

diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index 3a67ea3..8439742 100644 (file)
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -102,4 +102,3 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_FDT_FIXUP_PARTITIONS=y

diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig
index 9c906ed..9940258 100644 (file)
--- a/configs/controlcenterdc_defconfig
+++ b/configs/controlcenterdc_defconfig
@@ -72,6 +72,7 @@ CONFIG_ARP_TIMEOUT=200
 CONFIG_NET_RETRY_COUNT=50
 CONFIG_USE_ROOTPATH=y
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SYS_SATA_MAX_PORTS=2
 CONFIG_SCSI_AHCI=y
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y

diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
index 383317f..35f7635 100644 (file)
--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
@@ -52,3 +52,4 @@ CONFIG_DM_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_ISP1760=y
 CONFIG_ERRNO_STR=y
+CONFIG_NVMXIP_QSPI=y

diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index 3487cc2..fa2d7f3 100644 (file)
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -28,6 +28,7 @@ CONFIG_SPL_SPI=y
 CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x10000000
 CONFIG_SYS_MEMTEST_END=0x20000000
+CONFIG_LTO=y
 CONFIG_SYS_MONITOR_LEN=409600
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -39,6 +40,10 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_WATCHDOG=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
 CONFIG_CMD_MEMTEST=y
@@ -113,6 +118,7 @@ CONFIG_USB_GADGET_MANUFACTURER="dh"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
+CONFIG_SDP_LOADADDR=0x17ffffc0
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
 CONFIG_IMX_WATCHDOG=y

diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig
index 6f0882f..f86635d 100644 (file)
--- a/configs/eb_cpu5282_defconfig
+++ b/configs/eb_cpu5282_defconfig
@@ -34,10 +34,9 @@ CONFIG_CMD_DATE=y
 CONFIG_OVERWRITE_ETHADDR_ONCE=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
 CONFIG_SYS_RX_ETH_BUFFER=8
-CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x300
-CONFIG_SYS_I2C_SLAVE=0
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
 CONFIG_LED_STATUS=y
 CONFIG_LED_STATUS0=y
 CONFIG_LED_STATUS_BIT=8

diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig
index 5f4ec93..1982fea 100644 (file)
--- a/configs/eb_cpu5282_internal_defconfig
+++ b/configs/eb_cpu5282_internal_defconfig
@@ -32,10 +32,8 @@ CONFIG_CMD_DATE=y
 CONFIG_OVERWRITE_ETHADDR_ONCE=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
 CONFIG_SYS_RX_ETH_BUFFER=8
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x300
-CONFIG_SYS_I2C_SLAVE=0
 CONFIG_LED_STATUS=y
 CONFIG_LED_STATUS0=y
 CONFIG_LED_STATUS_BIT=8
@@ -50,5 +48,6 @@ CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_MCFFEC=y
 CONFIG_MII=y
+CONFIG_DM_RTC=y
 CONFIG_RTC_DS1338=y
 CONFIG_MCFUART=y

diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
new file mode 100644 (file)
index 0000000..ddeadb8
--- /dev/null
+++ b/configs/evb-rk3588_defconfig
@@ -0,0 +1,69 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10"
+CONFIG_DM_RESET=y
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3588=y
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYSRESET=y
+CONFIG_ERRNO_STR=y

diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig
index f045757..4eac7b2 100644 (file)
--- a/configs/highbank_defconfig
+++ b/configs/highbank_defconfig
@@ -30,6 +30,7 @@ CONFIG_RESET_TO_RETRY=y
 CONFIG_MISC_INIT_R=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_ENV_IS_IN_NVRAM=y
+CONFIG_SYS_SATA_MAX_PORTS=5
 CONFIG_SCSI_AHCI=y
 CONFIG_SYS_64BIT_LBA=y
 CONFIG_BOOTCOUNT_LIMIT=y

diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig
new file mode 100644 (file)
index 0000000..ca6ee2f
--- /dev/null
+++ b/configs/imx8mp_beacon_defconfig
@@ -0,0 +1,182 @@
+CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-beacon-kit"
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_SYS_HAS_ARMV8_SECURE_BASE=y
+CONFIG_TARGET_IMX8MP_BEACON=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0x960000
+CONFIG_SPL=y
+CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y
+CONFIG_ARMV8_MULTIENTRY=y
+CONFIG_ARMV8_SET_SMPEN=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_ARMV8_PSCI=y
+CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4
+CONFIG_ARMV8_PSCI_RELOCATE=y
+CONFIG_ARMV8_SECURE_BASE=0x970000
+CONFIG_ARMV8_EA_EL3_FIRST=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=524288
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_DEFAULT_FDT_FILE="imx8mp-beacon-kit.dtb"
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+CONFIG_SPL_MAX_SIZE=0x26000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x98fc00
+CONFIG_SPL_BSS_MAX_SIZE=0x400
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+CONFIG_SYS_BOOTM_LEN=0x2000000
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_SOURCE_FILE="imx8mp_beacon"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth1"
+CONFIG_SPL_DM=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
+CONFIG_GPIO_HOG=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+# CONFIG_DM_RNG is not set
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_TPM2_TIS_SPI=y
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_MX7 is not set
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_SDP_LOADADDR=0x0
+CONFIG_USB_FUNCTION_ACM=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+# CONFIG_WATCHDOG_AUTOSTART is not set
+CONFIG_IMX_WATCHDOG=y
+CONFIG_TPM=y
+# CONFIG_SPL_SHA512 is not set
+# CONFIG_SPL_SHA384 is not set

diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig
new file mode 100644 (file)
index 0000000..950d557
--- /dev/null
+++ b/configs/imx8mp_data_modul_edm_sbc_defconfig
@@ -0,0 +1,267 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0xFFFC0000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-data-modul-edm-sbc"
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_TARGET_IMX8MP_DATA_MODUL_EDM_SBC=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
+CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_DEBUG_UART_BASE=0x30880000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_ENV_OFFSET_REDUND=0xFFFC0000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_DEBUG_UART=y
+CONFIG_LTO=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_MONITOR_LEN=1048576
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
+CONFIG_USE_PREBOOT=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-data-modul-edm-sbc.dtb"
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x25000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x96fc00
+CONFIG_SPL_BSS_MAX_SIZE=0x400
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0x96fc00
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x4c000000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000
+CONFIG_SPL_WATCHDOG=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2081
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_SYS_BOOTM_LEN=0x8000000
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_SIZE=16384
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
+CONFIG_CMD_MD5SUM=y
+CONFIG_MD5SUM_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_SHA1SUM_VERIFY=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MBR=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_BKOPS_ENABLE=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_SYSBOOT=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_SMC=y
+CONFIG_HASH_VERIFY=y
+CONFIG_CMD_BTRFS=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
+CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
+CONFIG_MMC_SPEED_MODE_SET=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_TSIZE=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_TIMEOUT=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_GPIO_HOG=y
+CONFIG_SPL_GPIO_HOG=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+# CONFIG_INPUT is not set
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_USB_HUB_USB251XB=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
+CONFIG_SPL_DM_REGULATOR_PCA9450=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_M41T62=y
+CONFIG_CONS_INDEX=3
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Data Modul"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_SDP_LOADADDR=0x0
+CONFIG_USB_FUNCTION_ACM=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_OF_LIBFDT_OVERLAY=y

diff --git a/configs/iot2050_pg1_defconfig b/configs/iot2050_pg1_defconfig
index b027696..957e3c4 100644 (file)
--- a/configs/iot2050_pg1_defconfig
+++ b/configs/iot2050_pg1_defconfig
@@ -28,6 +28,7 @@ CONFIG_SPL_SPI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTSTAGE=y
 CONFIG_SHOW_BOOT_PROGRESS=y

diff --git a/configs/iot2050_pg2_defconfig b/configs/iot2050_pg2_defconfig
index b206677..1d221ad 100644 (file)
--- a/configs/iot2050_pg2_defconfig
+++ b/configs/iot2050_pg2_defconfig
@@ -28,6 +28,7 @@ CONFIG_DISTRO_DEFAULTS=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_BOOTSTAGE=y
 CONFIG_SHOW_BOOT_PROGRESS=y
 CONFIG_SPL_SHOW_BOOT_PROGRESS=y

diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 9b6512b..f929978 100644 (file)
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -31,6 +31,7 @@ CONFIG_SPL_SPI=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
 CONFIG_LOGLEVEL=7

diff --git a/configs/j7200_hs_evm_a72_defconfig b/configs/j7200_hs_evm_a72_defconfig
index cfd2e80..e83525b 100644 (file)
--- a/configs/j7200_hs_evm_a72_defconfig
+++ b/configs/j7200_hs_evm_a72_defconfig
@@ -32,6 +32,7 @@ CONFIG_SPL_SPI=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
 CONFIG_LOGLEVEL=7

diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 452e4b9..46ad1b7 100644 (file)
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -29,6 +29,7 @@ CONFIG_SPL_SPI=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
 CONFIG_LOGLEVEL=7

diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig
index 651df4a..df4bf01 100644 (file)
--- a/configs/j721e_hs_evm_a72_defconfig
+++ b/configs/j721e_hs_evm_a72_defconfig
@@ -30,6 +30,7 @@ CONFIG_SPL_SPI=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_fit_${boot}; run get_overlay_${boot}; run run_fit"
 CONFIG_LOGLEVEL=7

diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index 3a91df7..9889e1b 100644 (file)
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -28,7 +28,7 @@ CONFIG_SPL_SPI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
 CONFIG_LOGLEVEL=7

diff --git a/configs/j721s2_hs_evm_a72_defconfig b/configs/j721s2_hs_evm_a72_defconfig
index 453f2aa..035d87b 100644 (file)
--- a/configs/j721s2_hs_evm_a72_defconfig
+++ b/configs/j721s2_hs_evm_a72_defconfig
@@ -31,7 +31,7 @@ CONFIG_SPL_SPI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
 CONFIG_LOGLEVEL=7

diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig
index 30b1651..ea71f05 100644 (file)
--- a/configs/libretech-cc_v2_defconfig
+++ b/configs/libretech-cc_v2_defconfig
@@ -51,7 +51,7 @@ CONFIG_MESON_GXL_USB_PHY=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_MESON_GXL=y
 CONFIG_POWER_DOMAIN=y
-CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_MESON_SERIAL=y

diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
index ae01d83..15ac90f 100644 (file)
--- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
@@ -86,7 +86,8 @@ CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig
index 2361c35..78dd20a 100644 (file)
--- a/configs/ls1028aqds_tfa_defconfig
+++ b/configs/ls1028aqds_tfa_defconfig
@@ -92,7 +92,8 @@ CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
index af560c6..2c3c9bd 100644 (file)
--- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
@@ -80,7 +80,8 @@ CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig
index 93e8721..3384b98 100644 (file)
--- a/configs/ls1028ardb_tfa_defconfig
+++ b/configs/ls1028ardb_tfa_defconfig
@@ -86,7 +86,8 @@ CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig
index 4195724..09e273a 100644 (file)
--- a/configs/ls1088aqds_tfa_defconfig
+++ b/configs/ls1088aqds_tfa_defconfig
@@ -118,7 +118,9 @@ CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
index 5633901..558958c 100644 (file)
--- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
@@ -90,7 +90,9 @@ CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig
index fd466a5..89f8141 100644 (file)
--- a/configs/ls1088ardb_tfa_defconfig
+++ b/configs/ls1088ardb_tfa_defconfig
@@ -96,7 +96,9 @@ CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig
index c080706..b7dcd16 100644 (file)
--- a/configs/mk808_defconfig
+++ b/configs/mk808_defconfig
@@ -18,7 +18,7 @@ CONFIG_SPL_TEXT_BASE=0x60000000
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3066=y
 # CONFIG_ROCKCHIP_STIMER is not set
-CONFIG_TPL_TEXT_BASE=0x10080C04
+CONFIG_TPL_TEXT_BASE=0x10080c00
 CONFIG_TPL_STACK=0x1008FFFF
 CONFIG_TARGET_MK808=y
 CONFIG_SPL_STACK_R_ADDR=0x70000000
@@ -53,6 +53,9 @@ CONFIG_SYS_PBSIZE=276
 # CONFIG_BOOTM_VXWORKS is not set
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
@@ -78,6 +81,7 @@ CONFIG_TPL_SYSCON=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_TPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x80000000
 CONFIG_ROCKCHIP_GPIO=y
 # CONFIG_SPL_DM_I2C is not set
 CONFIG_LED=y
@@ -106,6 +110,12 @@ CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_TPL_TIMER=y
 CONFIG_DESIGNWARE_APB_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
 # CONFIG_TPL_OF_LIBFDT is not set

diff --git a/configs/nanopi_a64_defconfig b/configs/nanopi_a64_defconfig
index 70fc257..6082387 100644 (file)
--- a/configs/nanopi_a64_defconfig
+++ b/configs/nanopi_a64_defconfig
@@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-nanopi-a64"
 CONFIG_SPL=y
 CONFIG_MACH_SUN50I=y
-CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SUN8I_EMAC=y
 CONFIG_USB_EHCI_HCD=y

diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig
index c9b2252..fb1ce4c 100644 (file)
--- a/configs/neu6a-io-rk3588_defconfig
+++ b/configs/neu6a-io-rk3588_defconfig
@@ -62,5 +62,4 @@ CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
-# CONFIG_BINMAN_FDT is not set
 CONFIG_ERRNO_STR=y

diff --git a/configs/oceanic_5205_5inmfd_defconfig b/configs/oceanic_5205_5inmfd_defconfig
index 2ebca67..6cdcf78 100644 (file)
--- a/configs/oceanic_5205_5inmfd_defconfig
+++ b/configs/oceanic_5205_5inmfd_defconfig
@@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-oceanic-5205-5inmfd"
 CONFIG_SPL=y
 CONFIG_MACH_SUN50I=y
-CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
 CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
 CONFIG_DRAM_CLK=552
 CONFIG_DRAM_ZQ=3881949

diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig
index 3b78ad7..df11ad8 100644 (file)
--- a/configs/orangepi_win_defconfig
+++ b/configs/orangepi_win_defconfig
@@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win"
 CONFIG_SPL=y
 CONFIG_MACH_SUN50I=y
-CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
 CONFIG_MACPWR="PD14"
 CONFIG_SPL_SPI_SUNXI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig
index 72fc419..6cb942f 100644 (file)
--- a/configs/orangepi_zero2_defconfig
+++ b/configs/orangepi_zero2_defconfig
@@ -2,10 +2,10 @@ CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h616-orangepi-zero2"
 CONFIG_SPL=y
-CONFIG_DRAM_SUN50I_H616_WRITE_LEVELING=y
-CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION=y
-CONFIG_DRAM_SUN50I_H616_READ_TRAINING=y
-CONFIG_DRAM_SUN50I_H616_WRITE_TRAINING=y
+CONFIG_DRAM_SUN50I_H616_DX_ODT=0x08080808
+CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
+CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e
+CONFIG_DRAM_SUN50I_H616_TPR10=0xf83438
 CONFIG_MACH_SUN50I_H616=y
 CONFIG_R_I2C_ENABLE=y
 CONFIG_SPL_SPI_SUNXI=y

diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index f42f4e5..08c13b5 100644 (file)
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
 CONFIG_SPL=y
 CONFIG_MACH_SUN50I=y
-CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
 CONFIG_PINE64_DT_SELECTION=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus"

diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index 9e3e23f..59017b2 100644 (file)
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -55,7 +55,6 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
 CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_NOWHERE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_SPI_MAX_HZ=50000000

diff --git a/configs/r8a779a0_falcon_defconfig b/configs/r8a779a0_falcon_defconfig
index 083055a..14feaf1 100644 (file)
--- a/configs/r8a779a0_falcon_defconfig
+++ b/configs/r8a779a0_falcon_defconfig
@@ -10,7 +10,7 @@ CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="r8a779a0-falcon-u-boot"
 CONFIG_SPL_TEXT_BASE=0xe6338000
-CONFIG_RCAR_GEN3=y
+CONFIG_RCAR_GEN4=y
 CONFIG_TARGET_FALCON=y
 CONFIG_SPL_STACK=0xe6304000
 CONFIG_SYS_CLK_FREQ=16666666

diff --git a/configs/r8a779f0_spider_defconfig b/configs/r8a779f0_spider_defconfig
new file mode 100644 (file)
index 0000000..895ce3d
--- /dev/null
+++ b/configs/r8a779f0_spider_defconfig
@@ -0,0 +1,74 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0xD00000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a779f0-spider-u-boot"
+CONFIG_RCAR_GEN4=y
+CONFIG_TARGET_SPIDER=y
+CONFIG_SYS_CLK_FREQ=20000000
+# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x58000000
+CONFIG_SYS_BOOT_GET_CMDLINE=y
+CONFIG_SYS_BARGSIZE=2048
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
+CONFIG_FIT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="tftp 0x48080000 Image && tftp 0x48000000 Image-r8a779f0-spider.dtb && booti 0x48080000 - 0x48000000"
+CONFIG_DEFAULT_FDT_FILE="r8a779f0-spider.dtb"
+CONFIG_SYS_MALLOC_BOOTPARAMS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=2048
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_I2C=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_MARVELL_10G=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_RENESAS_ETHER_SWITCH=y
+CONFIG_PHY_R8A779F0_ETHERNET_SERDES=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_BAUDRATE=1843200
+CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y

diff --git a/configs/r8a779g0_whitehawk_defconfig b/configs/r8a779g0_whitehawk_defconfig
new file mode 100644 (file)
index 0000000..e78bb5b
--- /dev/null
+++ b/configs/r8a779g0_whitehawk_defconfig
@@ -0,0 +1,74 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xFFFE0000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a779g0-white-hawk-u-boot"
+CONFIG_RCAR_GEN4=y
+CONFIG_TARGET_WHITEHAWK=y
+CONFIG_SYS_CLK_FREQ=16666666
+# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x58000000
+CONFIG_SYS_BOOT_GET_CMDLINE=y
+CONFIG_SYS_BARGSIZE=2048
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
+CONFIG_FIT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="tftp 0x48080000 Image && tftp 0x48000000 Image-r8a779g0-white-hawk.dtb && booti 0x48080000 - 0x48000000"
+CONFIG_DEFAULT_FDT_FILE="r8a779g0-white-hawk.dtb"
+CONFIG_SYS_MALLOC_BOOTPARAMS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=2048
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_VERSION_VARIABLE=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_I2C=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_BITBANGMII=y
+CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_RENESAS_RAVB=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_BAUDRATE=921600
+CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y

diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig
index 2100cf2..1df9cab 100644 (file)
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -37,9 +37,12 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_ATF=y
 CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
@@ -60,8 +63,9 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
-CONFIG_REGULATOR_PWM=y
-CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=1500000
@@ -73,5 +77,4 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
 CONFIG_ERRNO_STR=y

diff --git a/configs/radxa-zero2_defconfig b/configs/radxa-zero2_defconfig
new file mode 100644 (file)
index 0000000..2218b0d
--- /dev/null
+++ b/configs/radxa-zero2_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-radxa-zero2"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" radxa-zero2"
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_REMAKE_ELF=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+# CONFIG_PHY_REALTEK is not set
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+# CONFIG_ETH_DESIGNWARE_MESON8B is not set
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y

diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig
index 91706d8..e9234ef 100644 (file)
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -68,7 +68,6 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
 CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_NOWHERE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y

diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index e753832..f0db15b 100644 (file)
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -39,7 +39,10 @@ CONFIG_SPL_ATF=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
@@ -58,10 +61,11 @@ CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_SPL_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
@@ -69,5 +73,12 @@ CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
-# CONFIG_BINMAN_FDT is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
 CONFIG_ERRNO_STR=y

diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index f3026c7..d3136ac 100644 (file)
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -58,6 +58,7 @@ CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
+# CONFIG_SPL_MMC_SDHCI_SDMA is not set
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
@@ -66,7 +67,5 @@ CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_SYSRESET=y
-# CONFIG_BINMAN_FDT is not set
 CONFIG_ERRNO_STR=y

diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index af2c56a..bb877b6 100644 (file)
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -260,3 +260,4 @@ CONFIG_FWU_MULTI_BANK_UPDATE=y
 CONFIG_UNIT_TEST=y
 CONFIG_UT_TIME=y
 CONFIG_UT_DM=y
+CONFIG_NVMXIP_QSPI=y

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index cbace25..657de0a 100644 (file)
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -147,6 +147,7 @@ CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
 CONFIG_AXI=y
 CONFIG_AXI_SANDBOX=y
+CONFIG_BLKMAP=y
 CONFIG_SYS_IDE_MAXBUS=1
 CONFIG_SYS_ATA_BASE_ADDR=0x100
 CONFIG_SYS_ATA_STRIDE=4
@@ -322,6 +323,7 @@ CONFIG_WDT=y
 CONFIG_WDT_GPIO=y
 CONFIG_WDT_SANDBOX=y
 CONFIG_WDT_ALARM_SANDBOX=y
+CONFIG_WDT_FTWDT010=y
 CONFIG_FS_CBFS=y
 CONFIG_FS_CRAMFS=y
 CONFIG_ADDR_MAP=y
@@ -334,8 +336,10 @@ CONFIG_ERRNO_STR=y
 CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
 CONFIG_EFI_CAPSULE_ON_DISK=y
 CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_CAPSULE_AUTHENTICATE=y
 CONFIG_EFI_SECURE_BOOT=y
 CONFIG_TEST_FDTDEC=y
 CONFIG_UNIT_TEST=y
 CONFIG_UT_TIME=y
 CONFIG_UT_DM=y
+CONFIG_CMD_2048=y

diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig
index e9fcc5b..8c2bcea 100644 (file)
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -226,6 +226,7 @@ CONFIG_ERRNO_STR=y
 CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
 CONFIG_EFI_CAPSULE_ON_DISK=y
 CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
+CONFIG_EFI_CAPSULE_AUTHENTICATE=y
 CONFIG_UNIT_TEST=y
 CONFIG_UT_TIME=y
 CONFIG_UT_DM=y

diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 4cbdab0..836e0c0 100644 (file)
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -24,6 +24,7 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
 CONFIG_SPL=y
 CONFIG_ENV_OFFSET_REDUND=0x180000
 CONFIG_SYS_LOAD_ADDR=0x22000000
+CONFIG_LTO=y
 CONFIG_FIT=y
 CONFIG_NAND_BOOT=y
 CONFIG_BOOTDELAY=3

diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig
index a5e1478..d9b0eb3 100644 (file)
--- a/configs/sopine_baseboard_defconfig
+++ b/configs/sopine_baseboard_defconfig
@@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-sopine-baseboard"
 CONFIG_SPL=y
 CONFIG_MACH_SUN50I=y
-CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
 CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
 CONFIG_DRAM_CLK=552
 CONFIG_DRAM_ZQ=3881949

diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
new file mode 100644 (file)
index 0000000..550d0ff
--- /dev/null
+++ b/configs/starfive_visionfive2_defconfig
@@ -0,0 +1,79 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000000
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.3b"
+CONFIG_SPL_TEXT_BASE=0x8000000
+CONFIG_SYS_PROMPT="StarFive #"
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_STACK=0x8180000
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
+CONFIG_SPL_OPENSBI_LOAD_ADDR=0x40000000
+CONFIG_ARCH_RV64I=y
+CONFIG_CMODEL_MEDANY=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_QSPI_BOOT=y
+CONFIG_SD_BOOT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
+CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_BSS_START_ADDR=0x8040000
+CONFIG_SPL_BSS_MAX_SIZE=0x10000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80000000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x400000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_JH7110=y
+# CONFIG_I2C is not set
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_SPL_PINCONF=y
+CONFIG_SPL_PINCTRL_STARFIVE=y
+CONFIG_SPL_PINCTRL_STARFIVE_JH7110=y
+CONFIG_PINCTRL_STARFIVE=y
+# CONFIG_RAM_SIFIVE is not set
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_TIMER_EARLY=y
+CONFIG_OF_LIBFDT_OVERLAY=y

diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index faf5f09..086e6bc 100644 (file)
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -46,6 +46,7 @@ CONFIG_SPL_POWER=y
 CONFIG_SPL_SPI_FLASH_MTD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
 CONFIG_FDT_SIMPLEFB=y
+CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
 CONFIG_SYS_PBSIZE=1050
 CONFIG_SYS_BOOTM_LEN=0x2000000
 CONFIG_CMD_ADTIMG=y

diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig
index 0005e42..a8eda7b 100644 (file)
--- a/configs/stm32mp15_defconfig
+++ b/configs/stm32mp15_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_STM32MP=y
 CONFIG_TFABOOT=y
-CONFIG_SYS_MALLOC_F_LEN=0x20000
+CONFIG_SYS_MALLOC_F_LEN=0x80000
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
 CONFIG_ENV_OFFSET=0x480000
 CONFIG_ENV_SECT_SIZE=0x40000
@@ -22,6 +22,7 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=1
 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
 CONFIG_FDT_SIMPLEFB=y
+CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
 CONFIG_SYS_PBSIZE=1050
 CONFIG_SYS_BOOTM_LEN=0x2000000
 CONFIG_CMD_ADTIMG=y

diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index 06fa43b..2269156 100644 (file)
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -23,6 +23,7 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=1
 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
 CONFIG_FDT_SIMPLEFB=y
+CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
 CONFIG_SYS_PBSIZE=1050
 CONFIG_SYS_BOOTM_LEN=0x2000000
 CONFIG_CMD_ADTIMG=y

diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig
index ee75709..b8d354f 100644 (file)
--- a/configs/stmark2_defconfig
+++ b/configs/stmark2_defconfig
@@ -49,3 +49,7 @@ CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_CF_SPI=y
 CONFIG_REGEX=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_I2C=y
+CONFIG_CMD_I2C=y
+CONFIG_SYS_I2C_FSL=y

diff --git a/configs/tqma6dl_mba6_mmc_defconfig b/configs/tqma6dl_mba6_mmc_defconfig
index a02ee92..34d0ddd 100644 (file)
--- a/configs/tqma6dl_mba6_mmc_defconfig
+++ b/configs/tqma6dl_mba6_mmc_defconfig
@@ -51,7 +51,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
@@ -61,4 +64,6 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_PFUZE100=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-# CONFIG_SPECIFY_CONSOLE_INDEX is not set
+CONFIG_DM_SERIAL=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y

diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig
index 8f7e0ac..1bd7f8d 100644 (file)
--- a/configs/tqma6dl_mba6_spi_defconfig
+++ b/configs/tqma6dl_mba6_spi_defconfig
@@ -55,7 +55,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
@@ -65,4 +68,6 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_PFUZE100=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-# CONFIG_SPECIFY_CONSOLE_INDEX is not set
+CONFIG_DM_SERIAL=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y

diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig
index 48822f3..f1f4232 100644 (file)
--- a/configs/tqma6q_mba6_mmc_defconfig
+++ b/configs/tqma6q_mba6_mmc_defconfig
@@ -51,7 +51,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
@@ -61,4 +64,6 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_PFUZE100=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-# CONFIG_SPECIFY_CONSOLE_INDEX is not set
+CONFIG_DM_SERIAL=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y

diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig
index ed77426..cc8616f 100644 (file)
--- a/configs/tqma6q_mba6_spi_defconfig
+++ b/configs/tqma6q_mba6_spi_defconfig
@@ -55,7 +55,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
@@ -65,4 +68,6 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_PFUZE100=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-# CONFIG_SPECIFY_CONSOLE_INDEX is not set
+CONFIG_DM_SERIAL=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y

diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig
index 9400c64..bd9476c 100644 (file)
--- a/configs/tqma6s_mba6_mmc_defconfig
+++ b/configs/tqma6s_mba6_mmc_defconfig
@@ -51,7 +51,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
@@ -61,4 +64,6 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_PFUZE100=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-# CONFIG_SPECIFY_CONSOLE_INDEX is not set
+CONFIG_DM_SERIAL=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y

diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig
index ddbf9a7..a9aa3fc 100644 (file)
--- a/configs/tqma6s_mba6_spi_defconfig
+++ b/configs/tqma6s_mba6_spi_defconfig
@@ -55,7 +55,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
@@ -65,4 +68,6 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_PFUZE100=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-# CONFIG_SPECIFY_CONSOLE_INDEX is not set
+CONFIG_DM_SERIAL=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y

diff --git a/configs/vexpress_fvp_defconfig b/configs/vexpress_fvp_defconfig
new file mode 100644 (file)
index 0000000..7362c1f
--- /dev/null
+++ b/configs/vexpress_fvp_defconfig
@@ -0,0 +1,5 @@
+CONFIG_ARM=y
+CONFIG_ARCH_VEXPRESS64=y
+CONFIG_DEFAULT_DEVICE_TREE="arm_fvp"
+CONFIG_IDENT_STRING=" arm_fvp"
+# CONFIG_DISPLAY_CPUINFO is not set

diff --git a/configs/wetek-core2_defconfig b/configs/wetek-core2_defconfig
index f5149fc..07d2587 100644 (file)
--- a/configs/wetek-core2_defconfig
+++ b/configs/wetek-core2_defconfig
@@ -44,7 +44,7 @@ CONFIG_MESON_GXL_USB_PHY=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_MESON_GXL=y
 CONFIG_POWER_DOMAIN=y
-CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DEBUG_UART_ANNOUNCE=y

diff --git a/configs/wetek-hub_defconfig b/configs/wetek-hub_defconfig
new file mode 100644 (file)
index 0000000..634833f
--- /dev/null
+++ b/configs/wetek-hub_defconfig
@@ -0,0 +1,70 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" wetek-hub"
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-wetek-hub"
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SARADC_MESON=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_PHY=y
+CONFIG_MESON_GXBB_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXBB=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y

diff --git a/configs/wetek-play2_defconfig b/configs/wetek-play2_defconfig
new file mode 100644 (file)
index 0000000..6d33b09
--- /dev/null
+++ b/configs/wetek-play2_defconfig
@@ -0,0 +1,70 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" wetek-play2"
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-wetek-play2"
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SARADC_MESON=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_PHY=y
+CONFIG_MESON_GXBB_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXBB=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y

diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig
index 38b82c3..aedb327 100644 (file)
--- a/configs/x96_mate_defconfig
+++ b/configs/x96_mate_defconfig
@@ -3,6 +3,13 @@ CONFIG_ARCH_SUNXI=y
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h616-x96-mate"
 CONFIG_SPL=y
 CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION=y
+CONFIG_DRAM_SUN50I_H616_DX_ODT=0x03030303
+CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
+CONFIG_DRAM_SUN50I_H616_CA_DRI=0x1c12
+CONFIG_DRAM_SUN50I_H616_TPR0=0xc0000c05
+CONFIG_DRAM_SUN50I_H616_TPR10=0x2f0007
+CONFIG_DRAM_SUN50I_H616_TPR11=0xffffdddd
+CONFIG_DRAM_SUN50I_H616_TPR12=0xfedf7557
 CONFIG_MACH_SUN50I_H616=y
 CONFIG_R_I2C_ENABLE=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

diff --git a/disk/part.c b/disk/part.c
index d449635..35300df 100644 (file)
--- a/disk/part.c
+++ b/disk/part.c
@@ -140,6 +140,7 @@ void dev_print(struct blk_desc *dev_desc)
        case UCLASS_NVME:
        case UCLASS_PVBLOCK:
        case UCLASS_HOST:
+       case UCLASS_BLKMAP:
                printf ("Vendor: %s Rev: %s Prod: %s\n",
                        dev_desc->vendor,
                        dev_desc->revision,

diff --git a/doc/android/boot-image.rst b/doc/android/boot-image.rst
index 71db025..c719b4d 100644 (file)
--- a/doc/android/boot-image.rst
+++ b/doc/android/boot-image.rst
@@ -27,11 +27,21 @@ next image headers:
 * v2: used in devices launched with Android 10; adds ``dtb`` field, which
   references payload containing DTB blobs (either concatenated one after the
   other, or in Android DTBO image format)
+* v3: used in devices launched with Android 11; adds ``vendor_boot`` partition
+  and removes the second-stage bootloader and recovery image support. The new
+  ``vendor_boot`` partition holds the device tree blob (DTB) and a vendor ramdisk.
+  The generic ramdisk in ``boot`` partition is loaded immediately following
+  the vendor ramdisk.
+* v4: used in devices launched with Android 12; provides a boot signature in boot
+  image header, supports multiple vendor ramdisk fragments in ``vendor_boot``
+  partition. This version also adds a bootconfig section at the end of the vendor
+  boot image, this section contains boot configuration parameters known at build time
+  (see [9]_ for details).
 
 v2, v1 and v0 formats are backward compatible.
 
 The Android Boot Image format is represented by
-:c:type:`struct andr_img_hdr <andr_img_hdr>` in U-Boot, and can be seen in
+:c:type:`struct andr_image_data <andr_image_data>` in U-Boot, and can be seen in
 ``include/android_image.h``. U-Boot supports booting Android Boot Image and also
 has associated command
 
@@ -153,3 +163,4 @@ References
 .. [6] :doc:`avb2`
 .. [7] https://source.android.com/devices/bootloader
 .. [8] https://connect.linaro.org/resources/san19/san19-217/
+.. [9] https://source.android.com/docs/core/architecture/bootloader/implementing-bootconfig

diff --git a/doc/arch/m68k.rst b/doc/arch/m68k.rst
index a9180fd..8474ece 100644 (file)
--- a/doc/arch/m68k.rst
+++ b/doc/arch/m68k.rst
@@ -5,7 +5,7 @@ M68K / ColdFire
 
 History
 -------
-* November 02, 2017    Angelo Dureghello <angelo@sysam.it>
+* November 02, 2017    Angelo Dureghello <angelo@kernel-space.org>
 * August   08, 2005    Jens Scharsig <esw@bus-elektronik.de>
   MCF5282 implementation without preloader
 * January  12, 2004    <josef.baumgartner@telex.de>

diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst
index cd7f8a2..77ca6bc 100644 (file)
--- a/doc/arch/sandbox/sandbox.rst
+++ b/doc/arch/sandbox/sandbox.rst
@@ -388,7 +388,7 @@ The device can be marked removeable with 'host bind -r'.
 A disk image can be created using the following commands::
 
    $> truncate -s 1200M ./disk.raw
-   $> echo -e "label: gpt\n,64M,U\n,,L" | /usr/sbin/sgdisk  ./disk.raw
+   $> /usr/sbin/sgdisk --new=1:0:+64M --typecode=1:EF00 --new=2:0:0 --typecode=2:8300 disk.raw
    $> lodev=`sudo losetup -P -f --show ./disk.raw`
    $> sudo mkfs.vfat -n EFI -v ${lodev}p1
    $> sudo mkfs.ext4 -L ROOT -v ${lodev}p2

diff --git a/doc/board/amlogic/bananapi-cm4io.rst b/doc/board/amlogic/bananapi-cm4io.rst
new file mode 100644 (file)
index 0000000..672cbee
--- /dev/null
+++ b/doc/board/amlogic/bananapi-cm4io.rst
@@ -0,0 +1,153 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for BananaPi CM4 with CM4IO (A311D)
+==========================================
+
+BPI-CM4 is a system-on-module board manufactured by Sinovoip. It follows the Raspberry Pi
+CM4 interface specification but with a single HDMI port and a single DSI output:
+
+ - Amlogic A311D Arm Cortex-A53 dual-core + Cortex-A73 quad-core SoC 
+ - 4GB DDR4 SDRAM
+ - 16GB eMMC
+ - NPU
+ - HDMI 2.1 display
+ - Gigabit Ethernet
+ - RTL8822CS WiFi (a/b/g/n/ac) + BT 5.0
+
+BPI-CM4IO is a carrier board for the BPI-CM4 module with the following specification:
+
+ - CM4 interface
+ - HDMI interface
+ - MIPI CSI interface
+ - MIPI DSI interface
+ - Ethernet interface
+ - PCIe interface
+ - SD (micro)
+ - SIM (micro)
+ - 26-pin GPIO
+ - UART serial
+ - 1x USB-C (power)
+ - 2x USB 2.0
+
+Schematics are available from the manufacturer: https://wiki.banana-pi.org/Banana_Pi_BPI-CM4
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make bananapi-cm4io_defconfig
+    $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh bananapi-cm4io /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+    $ DIR=bananapi-cm4io
+    $ git clone --depth 1 https://github.com/Dangku/amlogic-u-boot.git -b khadas-g12b-v2015.01-m2s $DIR
+
+    $ cd $DIR
+    $ make bananapi_cm4_defconfig
+    $ make
+    $ export UBDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+    $ cp $UBDIR/build/scp_task/bl301.bin fip/
+    $ cp $UBDIR/build/board/bananapi/bananpi_cm4/firmware/acs.bin fip/
+    $ cp $UBDIR/fip/g12a/bl2.bin fip/
+    $ cp $UBDIR/fip/g12a/bl30.bin fip/
+    $ cp $UBDIR/fip/g12a/bl31.img fip/
+    $ cp $UBDIR/fip/g12a/ddr3_1d.fw fip/
+    $ cp $UBDIR/fip/g12a/ddr4_1d.fw fip/
+    $ cp $UBDIR/fip/g12a/ddr4_2d.fw fip/
+    $ cp $UBDIR/fip/g12a/diag_lpddr4.fw fip/
+    $ cp $UBDIR/fip/g12a/lpddr3_1d.fw fip/
+    $ cp $UBDIR/fip/g12a/lpddr4_1d.fw fip/
+    $ cp $UBDIR/fip/g12a/lpddr4_2d.fw fip/
+    $ cp $UBDIR/fip/g12a/piei.fw fip/
+    $ cp $UBDIR/fip/g12a/aml_ddr.fw fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ sh fip/blx_fix.sh \
+         fip/bl30.bin \
+         fip/zero_tmp \
+         fip/bl30_zero.bin \
+         fip/bl301.bin \
+         fip/bl301_zero.bin \
+         fip/bl30_new.bin \
+         bl30
+
+    $ sh fip/blx_fix.sh \
+         fip/bl2.bin \
+         fip/zero_tmp \
+         fip/bl2_zero.bin \
+         fip/acs.bin \
+         fip/bl21_zero.bin \
+         fip/bl2_new.bin \
+         bl2
+
+    $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+                                       --output fip/bl30_new.bin.g12a.enc \
+                                       --level v3
+    $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+                                       --output fip/bl30_new.bin.enc \
+                                       --level v3 --type bl30
+    $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+                                       --output fip/bl31.img.enc \
+                                       --level v3 --type bl31
+    $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+                                       --output fip/bl33.bin.enc \
+                                       --level v3 --type bl33 --compress lz4
+    $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+                                       --output fip/bl2.n.bin.sig
+    $ $UBDIR/fip/g12b/aml_encrypt_g12b --bootmk \
+                                       --output fip/u-boot.bin \
+                                       --bl2 fip/bl2.n.bin.sig \
+                                       --bl30 fip/bl30_new.bin.enc \
+                                       --bl31 fip/bl31.img.enc \
+                                       --bl33 fip/bl33.bin.enc \
+                                       --ddrfw1 fip/ddr4_1d.fw \
+                                       --ddrfw2 fip/ddr4_2d.fw \
+                                       --ddrfw3 fip/ddr3_1d.fw \
+                                       --ddrfw4 fip/piei.fw \
+                                       --ddrfw5 fip/lpddr4_1d.fw \
+                                       --ddrfw6 fip/lpddr4_2d.fw \
+                                       --ddrfw7 fip/diag_lpddr4.fw \
+                                       --ddrfw8 fip/aml_ddr.fw \
+                                       --ddrfw9 fip/lpddr3_1d.fw \
+                                       --level v3
+
+Then write the image to SD or eMMC with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/boot_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/bananapi-m2pro.rst b/doc/board/amlogic/bananapi-m2pro.rst
new file mode 100644 (file)
index 0000000..6c35943
--- /dev/null
+++ b/doc/board/amlogic/bananapi-m2pro.rst
@@ -0,0 +1,143 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for BananaPi BPI-M2-PRO (S905X3)
+=======================================
+
+BananaPi BPI-M2-PRO is a Single Board Computer manufactured by Sinovoip with the
+following specification:
+
+ - Amlogic S905X3 Arm Cortex-A55 quad-core SoC
+ - 2GB DDR4 SDRAM
+ - 16GB eMMC
+ - Gigabit Ethernet
+ - RTL8821CU USB WiFi (a/b/g/n/ac) + BT 5.0
+ - HDMI 2.1 display
+ - 40-pin GPIO header
+ - 2x USB 3.0 Host
+ - 1x DC Jack (power)
+ - microSD
+ - UART serial
+ - Infrared receiver
+
+Schematics are available from the manufacturer: https://wiki.banana-pi.org/Banana_Pi_BPI-M2_Pro
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make bananapi-m2pro_defconfig
+    $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh bananapi-m2pro /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+    $ DIR=bananapi-m2pro
+    $ git clone --depth 1 https://github.com/Dangku/amlogic-u-boot.git -b odroidg12-v2015.01-c4-m5 $DIR
+
+    $ cd $DIR
+    $ make bananapi_m2pro_defconfig
+    $ make
+    $ export UBOOTDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+    $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+    $ cp $UBOOTDIR/build/board/bananapi/bananpi_m5/firmware/acs.bin fip/
+    $ cp $UBOOTDIR/fip/g12a/bl2.bin fip/
+    $ cp $UBOOTDIR/fip/g12a/bl30.bin fip/
+    $ cp $UBOOTDIR/fip/g12a/bl31.img fip/
+    $ cp $UBOOTDIR/fip/g12a/ddr3_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/ddr4_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/ddr4_2d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/diag_lpddr4.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/lpddr3_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/lpddr4_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/lpddr4_2d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/piei.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/aml_ddr.fw fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ sh fip/blx_fix.sh \
+         fip/bl30.bin \
+         fip/zero_tmp \
+         fip/bl30_zero.bin \
+         fip/bl301.bin \
+         fip/bl301_zero.bin \
+         fip/bl30_new.bin \
+         bl30
+
+    $ sh fip/blx_fix.sh \
+         fip/bl2.bin \
+         fip/zero_tmp \
+         fip/bl2_zero.bin \
+         fip/acs.bin \
+         fip/bl21_zero.bin \
+         fip/bl2_new.bin \
+         bl2
+
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
+                                          --output fip/bl30_new.bin.g12a.enc \
+                                          --level v3
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
+                                          --output fip/bl30_new.bin.enc \
+                                          --level v3 --type bl30
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
+                                          --output fip/bl31.img.enc \
+                                          --level v3 --type bl31
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
+                                          --output fip/bl33.bin.enc \
+                                          --level v3 --type bl33 --compress lz4
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
+                                          --output fip/bl2.n.bin.sig
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \
+                                          --output fip/u-boot.bin \
+                                          --bl2 fip/bl2.n.bin.sig \
+                                          --bl30 fip/bl30_new.bin.enc \
+                                          --bl31 fip/bl31.img.enc \
+                                          --bl33 fip/bl33.bin.enc \
+                                          --ddrfw1 fip/ddr4_1d.fw \
+                                          --ddrfw2 fip/ddr4_2d.fw \
+                                          --ddrfw3 fip/ddr3_1d.fw \
+                                          --ddrfw4 fip/piei.fw \
+                                          --ddrfw5 fip/lpddr4_1d.fw \
+                                          --ddrfw6 fip/lpddr4_2d.fw \
+                                          --ddrfw7 fip/diag_lpddr4.fw \
+                                          --ddrfw8 fip/aml_ddr.fw \
+                                          --ddrfw9 fip/lpddr3_1d.fw \
+                                          --level v3
+
+Then write the image to SD or eMMC with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/boot_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/bananapi-m2s.rst b/doc/board/amlogic/bananapi-m2s.rst
new file mode 100644 (file)
index 0000000..4a1be47
--- /dev/null
+++ b/doc/board/amlogic/bananapi-m2s.rst
@@ -0,0 +1,153 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for BananaPi M2S (A311D & S922X)
+=======================================
+
+BananaPi BPI-M2S ships is a Single Board Computer manufactured by Sinovoip that ships in
+two variants with Amlogic S922X or A311D SoC and the following common specification:
+
+- 16GB eMMC
+- HDMI 2.1a video
+- 2x 10/100/1000 Base-T Ethernet (1x RTL8211F, 1x RTL811H)
+- 2x USB 2.0 ports
+- 2x Status LED's (green/blue)
+- 1x Power/Reset button
+- 1x micro SD card slot
+- 40-pin GPIO header
+- PWM fan header
+- UART header
+
+The S992X variant has:
+- 2GB LPDDR4 RAM
+
+The A311D variant has:
+
+- 4GB LPDDR4 RAM
+- NPU (5.0 TOPS)
+- MIPI DSI header
+- MIPI CSI header
+
+An optional RTL8822CS SDIO WiFi/BT mezzanine is available for both board variants.
+
+Schematics are available from the manufacturer: https://wiki.banana-pi.org/Banana_Pi_BPI-M2S
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make bananapi-m2s_defconfig
+    $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh bananapi-m2s /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+    $ DIR=bananapi-m2s
+    $ git clone --depth 1 https://github.com/Dangku/amlogic-u-boot.git -b khadas-g12b-v2015.01-m2s $DIR
+
+    $ cd $DIR
+    $ make bananapi_m2s_defconfig
+    $ make
+    $ export UBDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+    $ cp $UBDIR/build/scp_task/bl301.bin fip/
+    $ cp $UBDIR/build/board/bananapi/bananpi_m2s/firmware/acs.bin fip/
+    $ cp $UBDIR/fip/g12a/bl2.bin fip/
+    $ cp $UBDIR/fip/g12a/bl30.bin fip/
+    $ cp $UBDIR/fip/g12a/bl31.img fip/
+    $ cp $UBDIR/fip/g12a/ddr3_1d.fw fip/
+    $ cp $UBDIR/fip/g12a/ddr4_1d.fw fip/
+    $ cp $UBDIR/fip/g12a/ddr4_2d.fw fip/
+    $ cp $UBDIR/fip/g12a/diag_lpddr4.fw fip/
+    $ cp $UBDIR/fip/g12a/lpddr3_1d.fw fip/
+    $ cp $UBDIR/fip/g12a/lpddr4_1d.fw fip/
+    $ cp $UBDIR/fip/g12a/lpddr4_2d.fw fip/
+    $ cp $UBDIR/fip/g12a/piei.fw fip/
+    $ cp $UBDIR/fip/g12a/aml_ddr.fw fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ sh fip/blx_fix.sh \
+         fip/bl30.bin \
+         fip/zero_tmp \
+         fip/bl30_zero.bin \
+         fip/bl301.bin \
+         fip/bl301_zero.bin \
+         fip/bl30_new.bin \
+         bl30
+
+    $ sh fip/blx_fix.sh \
+         fip/bl2.bin \
+         fip/zero_tmp \
+         fip/bl2_zero.bin \
+         fip/acs.bin \
+         fip/bl21_zero.bin \
+         fip/bl2_new.bin \
+         bl2
+
+    $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+                                       --output fip/bl30_new.bin.g12a.enc \
+                                       --level v3
+    $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+                                       --output fip/bl30_new.bin.enc \
+                                       --level v3 --type bl30
+    $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+                                       --output fip/bl31.img.enc \
+                                       --level v3 --type bl31
+    $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+                                       --output fip/bl33.bin.enc \
+                                       --level v3 --type bl33 --compress lz4
+    $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+                                       --output fip/bl2.n.bin.sig
+    $ $UBDIR/fip/g12b/aml_encrypt_g12b --bootmk \
+                                       --output fip/u-boot.bin \
+                                       --bl2 fip/bl2.n.bin.sig \
+                                       --bl30 fip/bl30_new.bin.enc \
+                                       --bl31 fip/bl31.img.enc \
+                                       --bl33 fip/bl33.bin.enc \
+                                       --ddrfw1 fip/ddr4_1d.fw \
+                                       --ddrfw2 fip/ddr4_2d.fw \
+                                       --ddrfw3 fip/ddr3_1d.fw \
+                                       --ddrfw4 fip/piei.fw \
+                                       --ddrfw5 fip/lpddr4_1d.fw \
+                                       --ddrfw6 fip/lpddr4_2d.fw \
+                                       --ddrfw7 fip/diag_lpddr4.fw \
+                                       --ddrfw8 fip/aml_ddr.fw \
+                                       --ddrfw9 fip/lpddr3_1d.fw \
+                                       --level v3
+
+Then write the image to SD or eMMC with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/boot_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/bananapi-m5.rst b/doc/board/amlogic/bananapi-m5.rst
new file mode 100644 (file)
index 0000000..009ea0b
--- /dev/null
+++ b/doc/board/amlogic/bananapi-m5.rst
@@ -0,0 +1,142 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for BananaPi BPI-M5 (S905X3)
+===================================
+
+BananaPi BPI-M5 is a Single Board Computer manufactured by Sinovoip with the following
+specification:
+
+ - Amlogic S905X3 Arm Cortex-A55 quad-core SoC
+ - 4GB DDR4 SDRAM
+ - 16GB eMMC
+ - Gigabit Ethernet
+ - HDMI 2.1 display
+ - 40-pin GPIO header
+ - 4x USB 3.0 Host
+ - 1x USB-C (power)
+ - microSD
+ - UART serial
+ - Infrared receiver
+
+Schematics are available from the manufacturer: https://wiki.banana-pi.org/Banana_Pi_BPI-M5
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make bananapi-m5_defconfig
+    $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh bananapi-m5 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+    $ DIR=bananapi-m5
+    $ git clone --depth 1 https://github.com/Dangku/amlogic-u-boot.git -b odroidg12-v2015.01-c4-m5 $DIR
+
+    $ cd $DIR
+    $ make bananapi_m5_defconfig
+    $ make
+    $ export UBOOTDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+    $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+    $ cp $UBOOTDIR/build/board/bananapi/bananpi_m5/firmware/acs.bin fip/
+    $ cp $UBOOTDIR/fip/g12a/bl2.bin fip/
+    $ cp $UBOOTDIR/fip/g12a/bl30.bin fip/
+    $ cp $UBOOTDIR/fip/g12a/bl31.img fip/
+    $ cp $UBOOTDIR/fip/g12a/ddr3_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/ddr4_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/ddr4_2d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/diag_lpddr4.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/lpddr3_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/lpddr4_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/lpddr4_2d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/piei.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/aml_ddr.fw fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ sh fip/blx_fix.sh \
+         fip/bl30.bin \
+         fip/zero_tmp \
+         fip/bl30_zero.bin \
+         fip/bl301.bin \
+         fip/bl301_zero.bin \
+         fip/bl30_new.bin \
+         bl30
+
+    $ sh fip/blx_fix.sh \
+         fip/bl2.bin \
+         fip/zero_tmp \
+         fip/bl2_zero.bin \
+         fip/acs.bin \
+         fip/bl21_zero.bin \
+         fip/bl2_new.bin \
+         bl2
+
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
+                                          --output fip/bl30_new.bin.g12a.enc \
+                                          --level v3
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
+                                          --output fip/bl30_new.bin.enc \
+                                          --level v3 --type bl30
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
+                                          --output fip/bl31.img.enc \
+                                          --level v3 --type bl31
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
+                                          --output fip/bl33.bin.enc \
+                                          --level v3 --type bl33 --compress lz4
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
+                                          --output fip/bl2.n.bin.sig
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \
+                                          --output fip/u-boot.bin \
+                                          --bl2 fip/bl2.n.bin.sig \
+                                          --bl30 fip/bl30_new.bin.enc \
+                                          --bl31 fip/bl31.img.enc \
+                                          --bl33 fip/bl33.bin.enc \
+                                          --ddrfw1 fip/ddr4_1d.fw \
+                                          --ddrfw2 fip/ddr4_2d.fw \
+                                          --ddrfw3 fip/ddr3_1d.fw \
+                                          --ddrfw4 fip/piei.fw \
+                                          --ddrfw5 fip/lpddr4_1d.fw \
+                                          --ddrfw6 fip/lpddr4_2d.fw \
+                                          --ddrfw7 fip/diag_lpddr4.fw \
+                                          --ddrfw8 fip/aml_ddr.fw \
+                                          --ddrfw9 fip/lpddr3_1d.fw \
+                                          --level v3
+
+Then write the image to SD or eMMC with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/boot_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/beelink-gskingx.rst b/doc/board/amlogic/beelink-gskingx.rst
new file mode 100644 (file)
index 0000000..8a8296e
--- /dev/null
+++ b/doc/board/amlogic/beelink-gskingx.rst
@@ -0,0 +1,122 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Beelink GS-King-X (S922X)
+====================================
+
+The Shenzen AZW (Beelink) GS-King-X is based on the Amlogic W400 reference board with an
+S922X-H chip and the following specifications:
+
+- 4GB LPDDR4 RAM
+- 64GB eMMC storage
+- 10/100/1000 Base-T Ethernet
+- AP6356S Wireless (802.11 a/b/g/n/ac, BT 4.1)
+- HDMI 2.1 video
+- S/PDIF optical output
+- 2x ESS9018 audio DACs
+- 4x Ricor RT6862 audio amps
+- Analogue headphone output
+- 1x USB 2.0 OTG port
+- 3x USB 3.0 ports
+- IR receiver
+- 1x micro SD card slot (internal)
+- USB SATA controller with 2x 3.5" drive bays
+- 1x Power on/off button
+
+Beelink do not provide public schematics, but have been willing to share them with known
+distro developers to assist with development.
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make beelink-gsking-x_defconfig
+    $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh beelink-s922x /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Beelink released an Amlogic "SDK" dump in their forums but the U-Boot sources included
+result in 2GB RAM detected. The following FIPs were generated with newer sources and
+detect 4GB RAM: https://github.com/LibreELEC/amlogic-boot-fip/tree/master/beelink-s922x
+
+.. code-block:: bash
+
+    $ wget https://github.com/LibreELEC/amlogic-boot-fip/archive/master.zip
+    $ unzip master.zip
+    $ export FIPDIR=$PWD/amlogic-boot-fip/beelink-s922x
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+    $ mkdir fip
+    $ cp $FIPDIR/* fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ sh fip/blx_fix.sh \
+         fip/bl30.bin \
+         fip/zero_tmp \
+         fip/bl30_zero.bin \
+         fip/bl301.bin \
+         fip/bl301_zero.bin \
+         fip/bl30_new.bin \
+         bl30
+
+    $ sh fip/blx_fix.sh \
+         fip/bl2.bin \
+         fip/zero_tmp \
+         fip/bl2_zero.bin \
+         fip/acs.bin \
+         fip/bl21_zero.bin \
+         fip/bl2_new.bin \
+         bl2
+
+    $ fip/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+                           --output fip/bl30_new.bin.g12a.enc \
+                           --level v3
+    $ fip/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+                           --output fip/bl30_new.bin.enc \
+                           --level v3 --type bl30
+    $ fip/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+                           --output fip/bl31.img.enc \
+                           --level v3 --type bl31
+    $ fip/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+                           --output fip/bl33.bin.enc \
+                           --level v3 --type bl33
+    $ fip/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+                           --output fip/bl2.n.bin.sig
+    $ fip/aml_encrypt_g12b --bootmk \
+                           --output fip/u-boot.bin \
+                           --bl2 fip/bl2.n.bin.sig \
+                           --bl30 fip/bl30_new.bin.enc \
+                           --bl31 fip/bl31.img.enc \
+                           --bl33 fip/bl33.bin.enc \
+                           --ddrfw1 fip/ddr4_1d.fw \
+                           --ddrfw2 fip/ddr4_2d.fw \
+                           --ddrfw3 fip/ddr3_1d.fw \
+                           --ddrfw4 fip/piei.fw \
+                           --ddrfw5 fip/lpddr4_1d.fw \
+                           --ddrfw6 fip/lpddr4_2d.fw \
+                           --ddrfw7 fip/diag_lpddr4.fw \
+                           --ddrfw8 fip/aml_ddr.fw \
+                           --level v3
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/boot_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/beelink-gt1-ultimate.rst b/doc/board/amlogic/beelink-gt1-ultimate.rst
new file mode 100644 (file)
index 0000000..a78a1a2
--- /dev/null
+++ b/doc/board/amlogic/beelink-gt1-ultimate.rst
@@ -0,0 +1,110 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Beelink GT1 Ultimate (S912)
+======================================
+
+Beelink GT1 Ultimate is an Android STB manufactured by Shenzen AZW (Beelink) with the
+following specification:
+
+- 2GB or 3GB DDR3 RAM
+- 32GB eMMC
+- HDMI 2.1 video
+- S/PDIF optical output
+- 10/100/1000 Ethernet
+- AP6356S Wireless (802.11 a/b/g/n/ac, BT 4.2)
+- 3x USB 2.0 ports
+- IR receiver
+- 1x micro SD card slot
+- 1x Power LED (white)
+- 1x Reset button (internal)
+
+The GT1 (non-ultimate) board has QCA9377 WiFi/BT but is otherwise identical and should
+be capable of booting images prepared for the Ultimate box (NB: there are known clones
+of both boxes which may differ in specifications).
+
+Beelink do not provide public schematics, but have been willing to share them with known
+distro developers on request.
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make beelink-gt1-ultimate_defconfig
+    $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh beelink-gt1 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide firmware sources or tools needed to create the bootloader image
+and Beelink has not publicly shared the U-Boot sources needed to build the FIP binaries
+for signing. However you can download them from the amlogic-fip-repo.
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip/beelink-gt1
+    $ export FIPDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+    $ mkdir fip
+    $ cp $FIPDIR/bl2.bin fip/
+    $ cp $FIPDIR/acs.bin fip/
+    $ cp $FIPDIR/bl21.bin fip/
+    $ cp $FIPDIR/bl30.bin fip/
+    $ cp $FIPDIR/bl301.bin fip/
+    $ cp $FIPDIR/bl31.img fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ $FIPDIR/blx_fix.sh \
+              fip/bl30.bin \
+              fip/zero_tmp \
+              fip/bl30_zero.bin \
+              fip/bl301.bin \
+              fip/bl301_zero.bin \
+              fip/bl30_new.bin \
+              bl30
+
+    $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+    $ $FIPDIR/blx_fix.sh \
+              fip/bl2_acs.bin \
+              fip/zero_tmp \
+              fip/bl2_zero.bin \
+              fip/bl21.bin \
+              fip/bl21_zero.bin \
+              fip/bl2_new.bin \
+              bl2
+
+    $ $FIPDIR/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+    $ $FIPDIR/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+    $ $FIPDIR/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+    $ $FIPDIR/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+    $ $FIPDIR/aml_encrypt_gxl --bootmk \
+                              --output fip/u-boot.bin \
+                              --bl2 fip/bl2.n.bin.sig \
+                              --bl30 fip/bl30_new.bin.enc \
+                              --bl31 fip/bl31.img.enc \
+                              --bl33 fip/bl33.bin.enc
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/boot_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/beelink-gtking.rst b/doc/board/amlogic/beelink-gtking.rst
index 2fb50c5..8171b69 100644 (file)
--- a/doc/board/amlogic/beelink-gtking.rst
+++ b/doc/board/amlogic/beelink-gtking.rst
@@ -1,10 +1,10 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for Beelink GT-King
-==========================
+U-Boot for Beelink GT-King (S922X)
+==================================
 
-The Shenzen AZW (Beelink) GT-King is based on the Amlogic W400 reference
-board with an S922X-H chip.
+The Shenzen AZW (Beelink) GT-King is based on the Amlogic W400 reference board with an
+S922X-H chip and the following specifications:
 
 - 4GB LPDDR4 RAM
 - 64GB eMMC storage
@@ -18,10 +18,10 @@ board with an S922X-H chip.
 - IR receiver
 - 1x micro SD card slot
 
-Beelink do not provide public schematics, but have been willing
-to share them with known distro developers on request.
+Beelink do not provide public schematics, but have been willing to share them with known
+distro developers to assist with development.
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -30,21 +30,22 @@ U-Boot compilation
     $ make beelink-gtking_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
-Amlogic does not provide sources for the firmware and for tools needed
-to create the bootloader image. Beelink have provided the Amlogic "SDK"
-in their forums, but the u-boot sources included result in 2GB RAM being
-detected. The following FIPs were generated with newer private sources
-and give correct (4GB) RAM detection:
+.. code-block:: bash
 
-https://github.com/LibreELEC/amlogic-boot-fip/tree/master/beelink-s922x
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh beelink-s922x /path/to/u-boot/u-boot.bin my-output-dir
 
-NB: Beelink use a common board config for GT-King, GT-King Pro and the
-GS-King-X model, hence the "beelink-s922x" name.
+U-Boot Manual Signing
+---------------------
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `beelink-s922x`
+Beelink released an Amlogic "SDK" dump in their forums, but the U-Boot sources included
+result in 2GB RAM detected. The following FIPs were generated with newer sources and
+detect 4GB RAM: https://github.com/LibreELEC/amlogic-boot-fip/tree/master/beelink-s922x
 
 .. code-block:: bash
 
@@ -61,57 +62,57 @@ Go back to the mainline U-Boot source tree then:
     $ cp u-boot.bin fip/bl33.bin
 
     $ sh fip/blx_fix.sh \
-       fip/bl30.bin \
-       fip/zero_tmp \
-       fip/bl30_zero.bin \
-       fip/bl301.bin \
-       fip/bl301_zero.bin \
-       fip/bl30_new.bin \
-       bl30
+         fip/bl30.bin \
+         fip/zero_tmp \
+         fip/bl30_zero.bin \
+         fip/bl301.bin \
+         fip/bl301_zero.bin \
+         fip/bl30_new.bin \
+         bl30
 
     $ sh fip/blx_fix.sh \
-       fip/bl2.bin \
-       fip/zero_tmp \
-       fip/bl2_zero.bin \
-       fip/acs.bin \
-       fip/bl21_zero.bin \
-       fip/bl2_new.bin \
-       bl2
+         fip/bl2.bin \
+         fip/zero_tmp \
+         fip/bl2_zero.bin \
+         fip/acs.bin \
+         fip/bl21_zero.bin \
+         fip/bl2_new.bin \
+         bl2
 
     $ fip/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
-                               --output fip/bl30_new.bin.g12a.enc \
-                               --level v3
+                           --output fip/bl30_new.bin.g12a.enc \
+                           --level v3
     $ fip/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
-                               --output fip/bl30_new.bin.enc \
-                               --level v3 --type bl30
+                           --output fip/bl30_new.bin.enc \
+                           --level v3 --type bl30
     $ fip/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
-                               --output fip/bl31.img.enc \
-                               --level v3 --type bl31
+                           --output fip/bl31.img.enc \
+                           --level v3 --type bl31
     $ fip/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
-                               --output fip/bl33.bin.enc \
-                               --level v3 --type bl33
+                           --output fip/bl33.bin.enc \
+                           --level v3 --type bl33
     $ fip/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
-                               --output fip/bl2.n.bin.sig
+                           --output fip/bl2.n.bin.sig
     $ fip/aml_encrypt_g12b --bootmk \
-               --output fip/u-boot.bin \
-               --bl2 fip/bl2.n.bin.sig \
-               --bl30 fip/bl30_new.bin.enc \
-               --bl31 fip/bl31.img.enc \
-               --bl33 fip/bl33.bin.enc \
-               --ddrfw1 fip/ddr4_1d.fw \
-               --ddrfw2 fip/ddr4_2d.fw \
-               --ddrfw3 fip/ddr3_1d.fw \
-               --ddrfw4 fip/piei.fw \
-               --ddrfw5 fip/lpddr4_1d.fw \
-               --ddrfw6 fip/lpddr4_2d.fw \
-               --ddrfw7 fip/diag_lpddr4.fw \
-               --ddrfw8 fip/aml_ddr.fw \
-               --level v3
-
-and then write the image to SD with:
+                           --output fip/u-boot.bin \
+                           --bl2 fip/bl2.n.bin.sig \
+                           --bl30 fip/bl30_new.bin.enc \
+                           --bl31 fip/bl31.img.enc \
+                           --bl33 fip/bl33.bin.enc \
+                           --ddrfw1 fip/ddr4_1d.fw \
+                           --ddrfw2 fip/ddr4_2d.fw \
+                           --ddrfw3 fip/ddr3_1d.fw \
+                           --ddrfw4 fip/piei.fw \
+                           --ddrfw5 fip/lpddr4_1d.fw \
+                           --ddrfw6 fip/lpddr4_2d.fw \
+                           --ddrfw7 fip/diag_lpddr4.fw \
+                           --ddrfw8 fip/aml_ddr.fw \
+                           --level v3
+
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
+    $ DEV=/dev/boot_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/beelink-gtkingpro.rst b/doc/board/amlogic/beelink-gtkingpro.rst
index 07bb04b..eb0b7d4 100644 (file)
--- a/doc/board/amlogic/beelink-gtkingpro.rst
+++ b/doc/board/amlogic/beelink-gtkingpro.rst
@@ -1,10 +1,10 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for Beelink GT-King Pro
-==============================
+U-Boot for Beelink GT-King Pro (S922X)
+======================================
 
-The Shenzen AZW (Beelink) GT-King Pro is based on the Amlogic W400 reference
-board with an S922X-H chip.
+The Shenzen AZW (Beelink) GT-King Pro is based on the Amlogic W400 reference board with
+an S922X-H chip and the following specifications:
 
 - 4GB LPDDR4 RAM
 - 64GB eMMC storage
@@ -19,10 +19,10 @@ board with an S922X-H chip.
 - 1x SD card slot
 - 1x Power on/off button
 
-Beelink do not provide public schematics, but have been willing
-to share them with known distro developers on request.
+Beelink do not provide public schematics, but have been willing to share them with known  
+distro developers to assist with development.
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -31,21 +31,22 @@ U-Boot compilation
     $ make beelink-gtkingpro_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
-Amlogic does not provide sources for the firmware and for tools needed
-to create the bootloader image. Beelink have provided the Amlogic "SDK"
-in their forums, but the u-boot sources included result in 2GB RAM being
-detected. The following FIPs were generated with newer private sources
-and give correct (4GB) RAM detection:
+.. code-block:: bash
 
-https://github.com/LibreELEC/amlogic-boot-fip/tree/master/beelink-s922x
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh beelink-s922x /path/to/u-boot/u-boot.bin my-output-dir
 
-NB: Beelink use a common board config for GT-King, GT-King Pro and the
-GS-King-X model, hence the "beelink-s922x" name.
+U-Boot Manual Signing
+---------------------
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `beelink-s922x`
+Beelink released an Amlogic "SDK" dump in their forums, but the U-Boot sources included
+result in 2GB RAM detected. The following FIPs were generated with newer sources and
+detect 4GB RAM: https://github.com/LibreELEC/amlogic-boot-fip/tree/master/beelink-s922x
 
 .. code-block:: bash
 
@@ -62,57 +63,57 @@ Go back to the mainline U-Boot source tree then:
     $ cp u-boot.bin fip/bl33.bin
 
     $ sh fip/blx_fix.sh \
-       fip/bl30.bin \
-       fip/zero_tmp \
-       fip/bl30_zero.bin \
-       fip/bl301.bin \
-       fip/bl301_zero.bin \
-       fip/bl30_new.bin \
-       bl30
+         fip/bl30.bin \
+         fip/zero_tmp \
+         fip/bl30_zero.bin \
+         fip/bl301.bin \
+         fip/bl301_zero.bin \
+         fip/bl30_new.bin \
+         bl30
 
     $ sh fip/blx_fix.sh \
-       fip/bl2.bin \
-       fip/zero_tmp \
-       fip/bl2_zero.bin \
-       fip/acs.bin \
-       fip/bl21_zero.bin \
-       fip/bl2_new.bin \
-       bl2
+         fip/bl2.bin \
+         fip/zero_tmp \
+         fip/bl2_zero.bin \
+         fip/acs.bin \
+         fip/bl21_zero.bin \
+         fip/bl2_new.bin \
+         bl2
 
     $ fip/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
-                               --output fip/bl30_new.bin.g12a.enc \
-                               --level v3
+                           --output fip/bl30_new.bin.g12a.enc \
+                           --level v3
     $ fip/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
-                               --output fip/bl30_new.bin.enc \
-                               --level v3 --type bl30
+                           --output fip/bl30_new.bin.enc \
+                           --level v3 --type bl30
     $ fip/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
-                               --output fip/bl31.img.enc \
-                               --level v3 --type bl31
+                           --output fip/bl31.img.enc \
+                           --level v3 --type bl31
     $ fip/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
-                               --output fip/bl33.bin.enc \
-                               --level v3 --type bl33
+                           --output fip/bl33.bin.enc \
+                           --level v3 --type bl33
     $ fip/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
-                               --output fip/bl2.n.bin.sig
+                           --output fip/bl2.n.bin.sig
     $ fip/aml_encrypt_g12b --bootmk \
-               --output fip/u-boot.bin \
-               --bl2 fip/bl2.n.bin.sig \
-               --bl30 fip/bl30_new.bin.enc \
-               --bl31 fip/bl31.img.enc \
-               --bl33 fip/bl33.bin.enc \
-               --ddrfw1 fip/ddr4_1d.fw \
-               --ddrfw2 fip/ddr4_2d.fw \
-               --ddrfw3 fip/ddr3_1d.fw \
-               --ddrfw4 fip/piei.fw \
-               --ddrfw5 fip/lpddr4_1d.fw \
-               --ddrfw6 fip/lpddr4_2d.fw \
-               --ddrfw7 fip/diag_lpddr4.fw \
-               --ddrfw8 fip/aml_ddr.fw \
-               --level v3
-
-and then write the image to SD with:
+                           --output fip/u-boot.bin \
+                           --bl2 fip/bl2.n.bin.sig \
+                           --bl30 fip/bl30_new.bin.enc \
+                           --bl31 fip/bl31.img.enc \
+                           --bl33 fip/bl33.bin.enc \
+                           --ddrfw1 fip/ddr4_1d.fw \
+                           --ddrfw2 fip/ddr4_2d.fw \
+                           --ddrfw3 fip/ddr3_1d.fw \
+                           --ddrfw4 fip/piei.fw \
+                           --ddrfw5 fip/lpddr4_1d.fw \
+                           --ddrfw6 fip/lpddr4_2d.fw \
+                           --ddrfw7 fip/diag_lpddr4.fw \
+                           --ddrfw8 fip/aml_ddr.fw \
+                           --level v3
+
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
+    $ DEV=/dev/boot_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/boot-flow.rst b/doc/board/amlogic/boot-flow.rst
index 2049672..041297c 100644 (file)
--- a/doc/board/amlogic/boot-flow.rst
+++ b/doc/board/amlogic/boot-flow.rst
@@ -3,132 +3,134 @@
 Amlogic SoC Boot Flow
 =====================
 
-The Amlogic SoCs have a pre-defined boot sequence in the SoC ROM code. Here are
-the possible boot sources of different SoC families supported by U-Boot:
+Amlogic SoCs follow a pre-defined boot sequence stored in SoC ROM code. The possible boot
+sequences of the different SoC families are:
 
-GX* & AXG family
+GX* & AXG Family
 ----------------
 
-+----------+--------------------+-------+-------+---------------+---------------+
-|          |   1                | 2     | 3     |    4          |     5         |
-+==========+====================+=======+=======+===============+===============+
-| S905     | POC=0: SPI NOR     | eMMC  | NAND  | SD Card       | USB Device    |
-| S905X    |                    |       |       |               |               |
-| S905L    |                    |       |       |               |               |
-| S905W    |                    |       |       |               |               |
-| S912     |                    |       |       |               |               |
-+----------+--------------------+-------+-------+---------------+---------------+
-| S805X    | POC=0: SPI NOR     | eMMC  | NAND  | USB Device    | -             |
-| A113D    |                    |       |       |               |               |
-| A113X    |                    |       |       |               |               |
-+----------+--------------------+-------+-------+---------------+---------------+
++----------+-------------------+---------+---------+---------+---------+
+|          |   1               | 2       | 3       | 4       | 5       |
++==========+===================+=========+=========+=========+=========+
+| S905     | POC=0: SPI NOR    | eMMC    | NAND    | SD      | USB     |
+| S905D    |                   |         |         |         |         |
+| S905L    |                   |         |         |         |         |
+| S905W    |                   |         |         |         |         |
+| S905X    |                   |         |         |         |         |
+| S905Y    |                   |         |         |         |         |
+| S912     |                   |         |         |         |         |
++----------+-------------------+---------+---------+---------+---------+
+| S805X    | POC=0: SPI NOR    | eMMC    | NAND    | USB     | -       |
+| A113D    |                   |         |         |         |         |
+| A113X    |                   |         |         |         |         |
++----------+-------------------+---------+---------+---------+---------+
 
 POC pin: `NAND_CLE`
 
-Some boards provide a button to force USB BOOT which disables the eMMC clock signal
-to bypass the eMMC stage. Others have removable eMMC modules; removing the eMMC and
-SDCard will allow boot from USB.
+Some boards provide a button to force USB boot by disabling the eMMC clock signal and
+allowing the eMMC step to be bypassed. Others have removable eMMC modules; removing an
+eMMC module and SD card will allow boot from USB.
 
-An exception is the lafrite board (aml-s805x-xx) which has no SDCard slot and boots
-from SPI. The only ways to boot the lafrite board from USB are:
+An exception is the Libre Computer AML-S805X-XX (LaFrite) board which has no SD card
+slot and boots from SPI. Booting a LaFrite board from USB requires either:
 
- - Erase the first sectors of SPI NOR flash
- - Insert an HDMI boot plug forcing boot over USB
+ - Erasing the first sectors of SPI NOR flash
+ - Inserting an HDMI boot plug forcing boot over USB
 
-The VIM1 and initial VIM2 boards provide a test point on the eMMC signals to block
-the storage from answering and continue to the next boot step.
+The VIM1 and initial VIM2 boards provide a test point on the eMMC signals to block the
+storage from answering, allowing boot to continue with the next boot step.
 
-The USB Device boot uses the first USB interface. On some boards this port is only
-available on an USB-A type connector and needs an special Type-A to Type-A cable to
-communicate with the BootROM.
+USB boot uses the first USB interface. On some boards this port is only available on a
+USB-A type connector and requires a special Type-A to Type-A cable to communicate with
+the BootROM.
 
-G12* & SM1 family
+G12* & SM1 Family
 -----------------
 
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| POC0  | POC1  | POC2  | 1             | 2             | 3             | 4             |
-+=======+=======+=======+===============+===============+===============+===============+
-| 0     | 0     | 0     | USB Device    | SPI NOR       | NAND/eMMC     | SDCard        |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 0     | 0     | 1     | USB Device    | NAND/eMMC     | SDCard        | -             |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 0     | 1     | 0     | SPI NOR       | NAND/eMMC     | SDCard        | USB Device    |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 0     | 1     | 1     | SPI NAND      | NAND/eMMC     | USB Device    | -             |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 1     | 0     | 0     | USB Device    | SPI NOR       | NAND/eMMC     | SDCard        |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 1     | 0     | 1     | USB Device    | NAND/eMMC     | SDCard        | -             |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 1     | 1     | 0     | SPI NOR       | NAND/eMMC     | SDCard        | USB Device    |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 1     | 1     | 1     | NAND/eMMC     | SDCard        | USB Device    | -             |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-
-The last option (1/1/1) is the normal default seen on production devices.
++-------+-------+-------+------------+------------+------------+-----------+
+| POC0  | POC1  | POC2  | 1          | 2          | 3          | 4         |
++=======+=======+=======+============+============+============+===========+
+| 0     | 0     | 0     | USB        | SPI-NOR    | NAND/eMMC  | SD        |
++-------+-------+-------+------------+------------+-------------+----------+
+| 0     | 0     | 1     | USB        | NAND/eMMC  | SD         | -         |
++-------+-------+-------+------------+------------+------------+-----------+
+| 0     | 1     | 0     | SPI-NOR    | NAND/eMMC  | SD         | USB       |
++-------+-------+-------+------------+------------+------------+-----------+
+| 0     | 1     | 1     | SPI-NAND   | NAND/eMMC  | USB        | -         |
++-------+-------+-------+------------+------------+------------+-----------+
+| 1     | 0     | 0     | USB        | SPI-NOR    | NAND/eMMC  | SD        |
++-------+-------+-------+------------+------------+------------+-----------+
+| 1     | 0     | 1     | USB        | NAND/eMMC  | SD         | -         |
++-------+-------+-------+------------+------------+------------+-----------+
+| 1     | 1     | 0     | SPI-NOR    | NAND/eMMC  | SD         | USB       |
++-------+-------+-------+------------+------------+------------+-----------+
+| 1     | 1     | 1     | NAND/eMMC  | SD         | USB        | -         |
++-------+-------+-------+------------+------------+------------+-----------+
+
+The last option (1/1/1) is the normal default seen on production devices:
 
  * POC0 pin: `BOOT_4` (0 and all other 1 means SPI NAND boot first)
  * POC1 pin: `BOOT_5` (0 and all other 1 means USB Device boot first
  * POC2 pin: `BOOT_6` (0 and all other 1 means SPI NOR boot first)
 
 Most boards provide a button to force USB BOOT which lowers `BOOT_5` to 0. Some boards
-provide a test point on the eMMC or SPI NOR clock signals to block the storage from
-answering and continue to the next boot step.
+provide a test point on eMMC or SPI NOR clock signals to block storage from answering
+and allowing boot to continue from the next boot step.
 
-The Khadas VIM3/3L boards embed a microcontroller which sets POC signals according
-to its configuration or a specific key press sequence to either boot from SPI NOR
-or eMMC then SDCard, or boot as an USB Device.
+The Khadas VIM3/3L boards embed a microcontroller which sets POC signals according to
+its configuration or a specific key press sequence to either boot from SPI NOR or eMMC
+then SD card, or boot as a USB device.
 
-The Odroid N2/N2+ has a hardware switch to select between SPI NOR or eMMC boot.
+The Odroid N2/N2+ has a hardware switch to select between SPI NOR or eMMC boot. The
+Odroid HC4 has a button to disable SPI-NOR allowing boot from SD card.
 
 Boot Modes
 ----------
 
- * SDCard
+ * SD
 
-The BootROM fetches the first SDCard sectors in one sequence, then checks the content
-of the data. The BootROM expects to find the FIP binary in sector 1, 512 bytes offset
-from the start.
+The BootROM fetches the first SD card sectors in one sequence then checks the content of
+the data. It expects to find the FIP binary in sector 1, 512 bytes offset from the start.
 
  * eMMC
 
-The BootROM fetches the first sectors in one sequence, first on the main partition,
-and then on the Boot0 followed by Boot1 HW partitions. After each read, the BootROM
-checks the data and looks to the next partition if it fails. The BootROM expects to
-find the FIP binary in sector 1, 512 bytes offset from the start.
+The BootROM fetches the first sectors of the main partition in one sequence then checks
+the content of the data. On GXL and newer boards it expects to find the FIP binary in
+sector 1, 512 bytes offset from the start. If not found it checks the boot0 partition,
+then the boot1 partition. On GXBB it expects to find the FIP binary at an offset that
+conflicts with MBR partition tables, but this has been worked around (thus avoiding the
+need for a partition scheme that relocates the MBR). For a more detailed explanation
+please see: https://github.com/LibreELEC/amlogic-boot-fip/pull/8
 
- * SPI NOR
+ * SPI-NOR
 
-The BootROM fetches the first SPI NOR sectors in one sequence, then checks the content
-of the data. The BootROM expects to find the FIP binary in sector 1, 512 bytes offset
-from the start.
+The BootROM fetches the first SPI NOR sectors in one sequence then checks the content of
+the data. It expects to find the FIP binary in sector 1, 512 bytes offset from the start.
 
- * NAND & SPI NAND
+ * NAND & SPI-NAND
 
 These modes are rarely used in open platforms and no details are available.
 
- * USB Device
+ * USB
 
-The BootROM sets the USB Gadget interface to serve a custom USB protocol with the
-USB ID 1b8e:c003. The Amlogic `update` utility is designed to use this protocol. It
-is also implemented in the Amlogic Vendor U-Boot.
+The BootROM supports a custom USB protocol and sets the USB Gadget interface to use the
+USB ID 1b8e:c003. The Amlogic `update` utility uses this protocol. It is also supported
+in the Amlogic vendor U-Boot sources.
 
-The open-source `pyamlboot` utility https://github.com/superna9999/pyamlboot also
-implements this protocol and can load U-Boot in memory in order to start the SoC
-without any attached storage or to recover from a failed/incorrect image flash.
+The `pyamlboot` utility https://github.com/superna9999/pyamlboot is open-source and also
+implements the USB protocol. It can load U-Boot into memory to start the SoC without the
+storage being attached, or to recover the device from a failed/incorrect image flash.
 
-HDMI Recovery
--------------
+HDMI Recovery Dongle
+--------------------
 
-The BootROM also briefly reads 8 bytes at address I2C 0x52 offset 0xf8 (248) on the
-HDMI DDC bus. If the content is `boot@USB` it will force USB boot mode. If the content
-is `boot@SDC` it will force SDCard boot mode.
+The BootROM also reads 8 bytes at address I2C 0x52 offset 0xf8 (248) on the HDMI DDC bus
+during startup. The content `boot@USB` forces USB boot. The content `boot@SDC` forces SD
+card boot. The content `boot@SPI` forces SPI-NOT boot. If an SD card or USB device does
+not enumerate the BootROM continues with the normal boot sequence.
 
-If USB Device doesn't enumerate or SD Card boot step doesn't work, the BootROM will
-continue with the normal boot sequence.
+HDMI boot dongles can be created by connecting a 256bytes EEPROM set to answer on address
+0x52, with `boot@USB` or `boot@SDC` or `boot@SPI` programmed at offset 0xf8 (248).
 
-Special boot dongles can be built by connecting a 256bytes EEPROM set to answer on
-address 0x52, and program `boot@USB` or `boot@SDC` at offset 0xf8 (248).
-
-Note: If the SoC is booted with USB Device forced at first step, it will keep the boot
-order on warm reboot. Only cold reboot (power removed) will reset the boot order.
+If the SoC is booted with USB Device forced at first step, it will retain the forced boot
+order on warm reboot. Only cold reboot (removing power) will reset the boot order.

diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst
index f945f67..66b581c 100644 (file)
--- a/doc/board/amlogic/index.rst
+++ b/doc/board/amlogic/index.rst
@@ -10,73 +10,65 @@ An up-do-date matrix is also available on: http://linux-meson.com
 
 This matrix concerns the actual source code version.
 
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-|                               | S905      | S905X           | S912         | A113X       | S905X2     | S922X       | S905X3       |
-|                               |           | S805X           | S905D        |             | S905D2     | A311D       | S905D3       |
-|                               |           | S905W           |              |             | S905Y2     |             |              |
-+===============================+===========+=================+==============+=============+============+=============+==============+
-| Boards                        | Odroid-C2 | P212            | Khadas VIM2  | S400        | U200       | Odroid-N2   | SEI610       |
-|                               | Nanopi-K2 | Khadas-VIM      | Libretech-PC | JetHub J100 | SEI510     | Khadas-VIM3 | Khadas-VIM3L |
-|                               | P200      | LibreTech-CC v1 | WeTek Core2  |             | Radxa Zero | GT-King/Pro | Odroid-C4    |
-|                               | P201      | LibreTech-AC v2 |              |             |            | GSKing-X    | Odroid-HC4   |
-|                               |           | JetHub J80      |              |             |            | Odroid-Go-  | BananaPi-M5  |
-|                               |           |                 |              |             |            | Ultra       |              |
-|                               |           |                 |              |             |            | Odroid-N2L  |              |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| UART                          | **Yes**   | **Yes**         | **Yes**      | **Yes**     | **Yes**    | **Yes**     | **Yes**      |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Pinctrl/GPIO                  | **Yes**   | **Yes**         | **Yes**      | **Yes**     | **Yes**    | **Yes**     | **Yes**      |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Clock Control                 | **Yes**   | **Yes**         | **Yes**      | **Yes**     | **Yes**    | **Yes**     | **Yes**      |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| PWM                           | **Yes**   | **Yes**         | **Yes**      | **Yes**     | **Yes**    | **Yes**     | **Yes**      |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Reset Control                 | **Yes**   | **Yes**         | **Yes**      | **Yes**     | **Yes**    | **Yes**     | **Yes**      |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Infrared Decoder              | No        | No              | No           | No          | No         | No          | No           |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Ethernet                      | **Yes**   | **Yes**         | **Yes**      | **Yes**     | **Yes**    | **Yes**     | **Yes**      |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Multi-core                    | **Yes**   | **Yes**         | **Yes**      | **Yes**     | **Yes**    | **Yes**     | **Yes**      |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Fuse access                   | **Yes**   | **Yes**         |**Yes**       |**Yes**      |**Yes**     |**Yes**      | **Yes**      |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| SPI (FC)                      | **Yes**   | **Yes**         | **Yes**      | **Yes**     |**Yes**     | **Yes**     | No           |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| SPI (CC)                      | No        | No              | No           | No          | No         | No          | No           |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| I2C                           | **Yes**   | **Yes**         | **Yes**      | **Yes**     | **Yes**    | **Yes**     | **Yes**      |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| USB                           | **Yes**   | **Yes**         | **Yes**      | **Yes**     | **Yes**    | **Yes**     | **Yes**      |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| USB OTG                       | No        | **Yes**         | **Yes**      | **Yes**     | **Yes**    | **Yes**     | **Yes**      |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| eMMC                          | **Yes**   | **Yes**         | **Yes**      | **Yes**     | **Yes**    | **Yes**     | **Yes**      |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| SDCard                        | **Yes**   | **Yes**         | **Yes**      | **Yes**     | **Yes**    | **Yes**     | **Yes**      |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| NAND                          | No        | No              | No           | No          | No         | No          | No           |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| ADC                           | **Yes**   | **Yes**         | **Yes**      | **Yes**     | No         | No          | No           |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| CVBS Output                   | **Yes**   | **Yes**         | **Yes**      | *N/A*       | **Yes**    | **Yes**     | **Yes**      |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| HDMI Output                   | **Yes**   | **Yes**         | **Yes**      | *N/A*       | **Yes**    | **Yes**     | **Yes**      |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| CEC                           | No        | No              | No           | *N/A*       | No         | No          | No           |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Thermal Sensor                | No        | No              | No           | No          | No         | No          | No           |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| LCD/LVDS Output               | No        | *N/A*           | No           | No          | No         | No          | No           |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| MIPI DSI Output               | *N/A*     | *N/A*           | *N/A*        | No          | No         | No          | No           |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| SoC (version) information     | **Yes**   | **Yes**         | **Yes**      | **Yes**     | **Yes**    | **Yes**     | **Yes**      |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| PCIe (+NVMe)                  | *N/A*     | *N/A*           | *N/A*        | **Yes**     | **Yes**    | **Yes**     | **Yes**      |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Watchdog                      | *N/A*     | **Yes**         | *N/A*        | *N/A*       | *N/A*      | *N/A*       | *N/A*        |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| SoCs              | S905      | S805X    | S912     | A113X    | S905X2   | S922X    | S905X3   |
+|                   |           | S905X    | S905D    |          | S905D2   | A311D    | S905D3   |
+|                   |           | S905W    |          |          | S905Y2   |          |          |
++===================+===========+==========+==========+==========+==========+==========+==========+
+| UART              | **Yes**   | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Pinctrl/GPIO      | **Yes**   | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Clock Control     | **Yes**   | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| PWM               | **Yes**   | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Reset Control     | **Yes**   | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Infrared Decoder  | No        | No       | No       | No       | No       | No       | No       |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Ethernet          | **Yes**   | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Multi-core        | **Yes**   | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Fuse access       | **Yes**   | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| SPI (FC)          | **Yes**   | **Yes**  | **Yes**  | **Yes**  |**Yes**   | **Yes**  | No       |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| SPI (CC)          | No        | No       | No       | No       | No       | No       | No       |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| I2C               | **Yes**   | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| USB               | **Yes**   | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| USB OTG           | No        | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| eMMC              | **Yes**   | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| SDCard            | **Yes**   | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| NAND              | No        | No       | No       | No       | No       | No       | No       |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| ADC               | **Yes**   | **Yes**  | **Yes**  | **Yes**  | No       | No       | No       |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| CVBS Output       | **Yes**   | **Yes**  | **Yes**  | *N/A*    | **Yes**  | **Yes**  | **Yes**  |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| HDMI Output       | **Yes**   | **Yes**  | **Yes**  | *N/A*    | **Yes**  | **Yes**  | **Yes**  |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| CEC               | No        | No       | No       | *N/A*    | No       | No       | No       |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Thermal Sensor    | No        | No       | No       | No       | No       | No       | No       |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| LCD/LVDS Output   | No        | *N/A*    | No       | No       | No       | No       | No       |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| MIPI DSI Output   | *N/A*     | *N/A*    | *N/A*    | No       | No       | No       | No       |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| SoC Rev/Info      | **Yes**   | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  | **Yes**  |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| PCIe (+NVMe)      | *N/A*     | *N/A*    | *N/A*    | **Yes**  | **Yes**  | **Yes**  | **Yes**  |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Watchdog          | *N/A*     | **Yes**  | *N/A*    | *N/A*    | *N/A*    | *N/A*    | *N/A*    |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
 
 Boot Documentation
 ------------------
@@ -84,8 +76,8 @@ Boot Documentation
 .. toctree::
    :maxdepth: 1
 
-   pre-generated-fip
    boot-flow
+   pre-generated-fip
 
 Board Documentation
 -------------------
@@ -93,19 +85,26 @@ Board Documentation
 .. toctree::
    :maxdepth: 1
 
+   bananapi-cm4io
+   bananapi-m2pro
+   bananapi-m2s
+   bananapi-m5
+   beelink-gskingx
+   beelink-gt1-ultimate
    beelink-gtking
    beelink-gtkingpro
-   jethub-j100
    jethub-j80
+   jethub-j100
+   khadas-vim
    khadas-vim2
-   khadas-vim3l
    khadas-vim3
-   khadas-vim
+   khadas-vim3l
    libretech-ac
    libretech-cc
    nanopi-k2
    odroid-c2
    odroid-c4
+   odroid-hc4
    odroid-n2
    odroid-n2l
    odroid-go-ultra
@@ -114,9 +113,12 @@ Board Documentation
    p212
    q200
    radxa-zero
-   s400
+   radxa-zero2
    sei510
    sei610
+   s400
    u200
    wetek-core2
+   wetek-hub
+   wetek-play2
    w400

diff --git a/doc/board/amlogic/jethub-j100.rst b/doc/board/amlogic/jethub-j100.rst
index dd1ed68..86acdaf 100644 (file)
--- a/doc/board/amlogic/jethub-j100.rst
+++ b/doc/board/amlogic/jethub-j100.rst
@@ -1,11 +1,10 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for JetHub J100
-=======================
+U-Boot for JetHub J100 (A113X)
+==============================
 
-JetHome Jethub D1 (http://jethome.ru/jethub-d1) is a series of home
-automation controller manufactured by JetHome with the following
-specifications:
+JetHome Jethub D1 (http://jethome.ru/jethub-d1) is a home automation controller device
+manufactured by JetHome with the following specifications:
 
  - Amlogic A113X (ARM Cortex-A53) quad-core up to 1.5GHz
  - no video out
@@ -22,16 +21,15 @@ specifications:
  - DC source with a voltage of 9 to 56 V / Passive POE
  - DIN Rail Mounting case
 
-Basic version also has:
+The basic version also has:
 
- - TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output
-   power and Zigbee 3.0 support.
+ - TI CC2538 + CC2592 Zigbee Wireless with upto 20dBm output power and Zigbee 3.0
  - 1 x 1-Wire
  - 2 x RS-485
  - 4 x dry contact digital GPIO inputs
  - 3 x relay GPIO outputs
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -40,14 +38,21 @@ U-Boot compilation
     $ make jethub_j100_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `jethub-j100`
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh jethub-j100 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain binaries
-from the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
 
 .. code-block:: bash
 
@@ -55,7 +60,7 @@ from the git tree published by the board vendor:
     $ cd jethub-u-boot
     $ export FIPDIR=$PWD
 
-Go back to mainline U-boot source tree then :
+Go back to the mainline U-Boot source tree then:
 
 .. code-block:: bash
 
@@ -90,27 +95,27 @@ Go back to mainline U-boot source tree then :
         bl2
 
     $ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl30_new.bin \
-                                        --output fip/bl30_new.bin.enc \
-                                        --level v3 --type bl30
+                                   --output fip/bl30_new.bin.enc \
+                                   --level v3 --type bl30
     $ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl31.img \
-                                        --output fip/bl31.img.enc \
-                                        --level v3 --type bl31
+                                   --output fip/bl31.img.enc \
+                                   --level v3 --type bl31
     $ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl33.bin --compress lz4 \
-                                        --output fip/bl33.bin.enc \
-                                        --level v3 --type bl33
+                                   --output fip/bl33.bin.enc \
+                                   --level v3 --type bl33
     $ $FIPDIR/j100/aml_encrypt_axg --bl2sig --input fip/bl2_new.bin \
-                                        --output fip/bl2.n.bin.sig
+                                   --output fip/bl2.n.bin.sig
     $ $FIPDIR/j100/aml_encrypt_axg --bootmk \
-                --output fip/u-boot.bin \
-                --bl2 fip/bl2.n.bin.sig \
-                --bl30 fip/bl30_new.bin.enc \
-                --bl31 fip/bl31.img.enc \
-                --bl33 fip/bl33.bin.enc --level v3
+                                   --output fip/u-boot.bin \
+                                   --bl2 fip/bl2.n.bin.sig \
+                                   --bl30 fip/bl30_new.bin.enc \
+                                   --bl31 fip/bl31.img.enc \
+                                   --bl33 fip/bl33.bin.enc --level v3
 
-and then write the image to eMMC with:
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_emmc_device
+    $ DEV=/dev/boot_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/jethub-j80.rst b/doc/board/amlogic/jethub-j80.rst
index f669a01..9195df6 100644 (file)
--- a/doc/board/amlogic/jethub-j80.rst
+++ b/doc/board/amlogic/jethub-j80.rst
@@ -1,10 +1,10 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for JetHub J80
-======================
+U-Boot for JetHub J80 (S905W)
+=============================
 
-JetHome Jethub H1 (http://jethome.ru/jethub-h1) is a home automation
-controller manufactured by JetHome with the following specifications:
+JetHome Jethub H1 (http://jethome.ru/jethub-h1) is a home automation controller device
+manufactured by JetHome with the following specifications:
 
  - Amlogic S905W (ARM Cortex-A53) quad-core up to 1.5GHz
  - No video out
@@ -21,7 +21,7 @@ controller manufactured by JetHome with the following specifications:
  - DC source 5V microUSB
  - Square plastic case
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -30,14 +30,21 @@ U-Boot compilation
     $ make jethub_j80_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `jethub-j80`
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh jethub-j80 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain binaries
-from the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
 
 .. code-block:: bash
 
@@ -45,7 +52,7 @@ from the git tree published by the board vendor:
     $ cd jethub-u-boot
     $ export FIPDIR=$PWD
 
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
 
 .. code-block:: bash
 
@@ -84,16 +91,16 @@ Go back to mainline U-Boot source tree then :
     $ $FIPDIR/j80/aml_encrypt_gxl --bl3enc --input fip/bl33.bin --compress lz4
     $ $FIPDIR/j80/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
     $ $FIPDIR/j80/aml_encrypt_gxl --bootmk \
-                --output fip/u-boot.bin \
-                --bl2 fip/bl2.n.bin.sig \
-                --bl30 fip/bl30_new.bin.enc \
-                --bl31 fip/bl31.img.enc \
-                --bl33 fip/bl33.bin.enc
+                                  --output fip/u-boot.bin \
+                                  --bl2 fip/bl2.n.bin.sig \
+                                  --bl30 fip/bl30_new.bin.enc \
+                                  --bl31 fip/bl31.img.enc \
+                                  --bl33 fip/bl33.bin.enc
 
-and then write the image to SD/eMMC with:
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
+    $ DEV=/dev/boot_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/khadas-vim.rst b/doc/board/amlogic/khadas-vim.rst
index 04025d7..20370ed 100644 (file)
--- a/doc/board/amlogic/khadas-vim.rst
+++ b/doc/board/amlogic/khadas-vim.rst
@@ -1,24 +1,24 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for Khadas VIM
-======================
+U-Boot for Khadas VIM (S905X)
+=============================
 
-Khadas VIM is an Open Source DIY Box manufactured by Shenzhen Wesion
-Technology Co., Ltd with the following specifications:
+Khadas VIM is a Single Board Computer manufactured by Shenzhen Wesion Technology Co. Ltd
+with the following specifications:
 
  - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz
  - ARM Mali 450 GPU
  - 2GB DDR3 SDRAM
+ - 8GB/16GB eMMC
  - 10/100 Ethernet
  - HDMI 2.0 4K/60Hz display
  - 40-pin GPIO header
  - 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG
- - 8GB/16GBeMMC
  - microSD
  - SDIO Wifi Module, Bluetooth
- - Two channels IR receiver
+ - Two channel IR receiver
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -27,14 +27,21 @@ U-Boot compilation
     $ make khadas-vim_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `khadas-vim`
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh khadas-vim /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
 
 .. code-block:: bash
 
@@ -64,40 +71,40 @@ Go back to mainline U-Boot source tree then :
     $ cp u-boot.bin fip/bl33.bin
 
     $ $FIPDIR/blx_fix.sh \
-       fip/bl30.bin \
-       fip/zero_tmp \
-       fip/bl30_zero.bin \
-       fip/bl301.bin \
-       fip/bl301_zero.bin \
-       fip/bl30_new.bin \
-       bl30
+              fip/bl30.bin \
+              fip/zero_tmp \
+              fip/bl30_zero.bin \
+              fip/bl301.bin \
+              fip/bl301_zero.bin \
+              fip/bl30_new.bin \
+              bl30
 
     $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
 
     $ $FIPDIR/blx_fix.sh \
-       fip/bl2_acs.bin \
-       fip/zero_tmp \
-       fip/bl2_zero.bin \
-       fip/bl21.bin \
-       fip/bl21_zero.bin \
-       fip/bl2_new.bin \
-       bl2
+              fip/bl2_acs.bin \
+              fip/zero_tmp \
+              fip/bl2_zero.bin \
+              fip/bl21.bin \
+              fip/bl21_zero.bin \
+              fip/bl2_new.bin \
+              bl2
 
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
     $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
-               --output fip/u-boot.bin \
-               --bl2 fip/bl2.n.bin.sig \
-               --bl30 fip/bl30_new.bin.enc \
-               --bl31 fip/bl31.img.enc \
-               --bl33 fip/bl33.bin.enc
+                                  --output fip/u-boot.bin \
+                                  --bl2 fip/bl2.n.bin.sig \
+                                  --bl30 fip/bl30_new.bin.enc \
+                                  --bl31 fip/bl31.img.enc \
+                                  --bl33 fip/bl33.bin.enc
 
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
+    $ DEV=/dev/boot_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/khadas-vim2.rst b/doc/board/amlogic/khadas-vim2.rst
index 7ac3bdc..58f1870 100644 (file)
--- a/doc/board/amlogic/khadas-vim2.rst
+++ b/doc/board/amlogic/khadas-vim2.rst
@@ -1,25 +1,25 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for Khadas VIM2
-=======================
+U-Boot for Khadas VIM2 (S912)
+=============================
 
-Khadas VIM2 is an Open Source DIY Box manufactured by Shenzhen Wesion
-Technology Co., Ltd with the following specifications:
+Khadas VIM2 is a Single Board Computer manufactured by Shenzhen Wesion Technology Co. Ltd
+with the following specifications:
 
  - Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz
  - ARM Mali T860 GPU
- - 2/3GB DDR4 SDRAM
+ - 2GB/3GB DDR4 SDRAM
+ - 16GB/32GB/64GB eMMC
  - 10/100/1000 Ethernet
  - HDMI 2.0 4K/60Hz display
  - 40-pin GPIO header
  - 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG
- - 16GB/32GB/64GB eMMC
  - 2MB SPI Flash
  - microSD
  - SDIO Wifi Module, Bluetooth
  - Two channels IR receiver
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -28,14 +28,21 @@ U-Boot compilation
     $ make khadas-vim2_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh khadas-vim2 /path/to/u-boot/u-boot.bin my-output-dir
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `khadas-vim2`
+U-Boot Manual Signing
+---------------------
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
 
 .. code-block:: bash
 
@@ -50,7 +57,7 @@ the git tree published by the board vendor:
     $ make
     $ export FIPDIR=$PWD/fip
 
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
 
 .. code-block:: bash
 
@@ -65,40 +72,40 @@ Go back to mainline U-Boot source tree then :
     $ cp u-boot.bin fip/bl33.bin
 
     $ $FIPDIR/blx_fix.sh \
-       fip/bl30.bin \
-       fip/zero_tmp \
-       fip/bl30_zero.bin \
-       fip/bl301.bin \
-       fip/bl301_zero.bin \
-       fip/bl30_new.bin \
-       bl30
+              fip/bl30.bin \
+              fip/zero_tmp \
+              fip/bl30_zero.bin \
+              fip/bl301.bin \
+              fip/bl301_zero.bin \
+              fip/bl30_new.bin \
+              bl30
 
     $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
 
     $ $FIPDIR/blx_fix.sh \
-       fip/bl2_acs.bin \
-       fip/zero_tmp \
-       fip/bl2_zero.bin \
-       fip/bl21.bin \
-       fip/bl21_zero.bin \
-       fip/bl2_new.bin \
-       bl2
+              fip/bl2_acs.bin \
+              fip/zero_tmp \
+              fip/bl2_zero.bin \
+              fip/bl21.bin \
+              fip/bl21_zero.bin \
+              fip/bl2_new.bin \
+              bl2
 
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
     $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
-               --output fip/u-boot.bin \
-               --bl2 fip/bl2.n.bin.sig \
-               --bl30 fip/bl30_new.bin.enc \
-               --bl31 fip/bl31.img.enc \
-               --bl33 fip/bl33.bin.enc
+                                  --output fip/u-boot.bin \
+                                  --bl2 fip/bl2.n.bin.sig \
+                                  --bl30 fip/bl30_new.bin.enc \
+                                  --bl31 fip/bl31.img.enc \
+                                  --bl33 fip/bl33.bin.enc
 
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
     $ DEV=/dev/your_sd_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/khadas-vim3.rst b/doc/board/amlogic/khadas-vim3.rst
index 73dc32b..4959590 100644 (file)
--- a/doc/board/amlogic/khadas-vim3.rst
+++ b/doc/board/amlogic/khadas-vim3.rst
@@ -1,10 +1,10 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for Khadas VIM3
-======================
+U-Boot for Khadas VIM3 (A311D)
+==============================
 
-Khadas VIM3 is a single board computer manufactured by Shenzhen Wesion
-Technology Co., Ltd. with the following specifications:
+Khadas VIM3 is a Single Board Computer manufactured by Shenzhen Wesion Technology Co. Ltd
+with the following specifications:
 
  - Amlogic A311D Arm Cortex-A53 dual-core + Cortex-A73 quad-core SoC
  - 4GB LPDDR4 SDRAM
@@ -20,32 +20,27 @@ Schematics are available on the manufacturer website.
 
 PCIe Setup
 ----------
-The VIM3 on-board  MCU can mux the PCIe/USB3.0 shared differential
-lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
-an USB3.0 Type A connector and a M.2 Key M slot.
-The PHY driving these differential lines is shared between
-the USB3.0 controller and the PCIe Controller, thus only
-a single controller can use it.
 
-To setup for PCIe, run the following commands from U-Boot:
+The on-board MCU can mux the PCIe/USB3.0 shared differential lines using a FUSB340TMX USB
+3.1 SuperSpeed Data Switch between a USB3.0 Type-A connector and an M.2 Key M slot. The
+PHY driving these differential lines is shared between the USB3.0 controller and the PCIe
+Controller, thus only a single controller can use it.
+
+To setup for PCIe run the following commands from U-Boot then power-cycle the board:
 
 .. code-block:: none
 
     i2c dev i2c@5000
     i2c mw 0x18 0x33 1
 
-Then power-cycle the board.
-
-To set back to USB3.0, run the following commands from U-Boot:
+To revert to USB3.0 run the following commands from U-Boot then power-cycle the board:
 
 .. code-block:: none
 
     i2c dev i2c@5000
     i2c mw 0x18 0x33 0
 
-Then power-cycle the board.
-
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -54,14 +49,21 @@ U-Boot compilation
     $ make khadas-vim3_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh khadas-vim3 /path/to/u-boot/u-boot.bin my-output-dir
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `khadas-vim3`
+U-Boot Manual Signing
+---------------------
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
 
 .. code-block:: bash
 
@@ -72,16 +74,14 @@ the git tree published by the board vendor:
     $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
 
     $ DIR=vim3-u-boot
-    $ git clone --depth 1 \
-       https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 \
-       $DIR
+    $ git clone --depth 1 https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 $DIR
 
     $ cd vim3-u-boot
     $ make kvim3_defconfig
     $ make CROSS_COMPILE=aarch64-none-elf-
     $ export UBOOTDIR=$PWD
 
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
 
 .. code-block:: bash
 
@@ -105,58 +105,58 @@ Go back to mainline U-Boot source tree then :
     $ cp u-boot.bin fip/bl33.bin
 
     $ bash fip/blx_fix.sh \
-       fip/bl30.bin \
-       fip/zero_tmp \
-       fip/bl30_zero.bin \
-       fip/bl301.bin \
-       fip/bl301_zero.bin \
-       fip/bl30_new.bin \
-       bl30
+           fip/bl30.bin \
+           fip/zero_tmp \
+           fip/bl30_zero.bin \
+           fip/bl301.bin \
+           fip/bl301_zero.bin \
+           fip/bl30_new.bin \
+           bl30
 
     $ bash fip/blx_fix.sh \
-       fip/bl2.bin \
-       fip/zero_tmp \
-       fip/bl2_zero.bin \
-       fip/acs.bin \
-       fip/bl21_zero.bin \
-       fip/bl2_new.bin \
-       bl2
+           fip/bl2.bin \
+           fip/zero_tmp \
+           fip/bl2_zero.bin \
+           fip/acs.bin \
+           fip/bl21_zero.bin \
+           fip/bl2_new.bin \
+           bl2
 
     $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
-                                       --output fip/bl30_new.bin.g12a.enc \
-                                       --level v3
+                                          --output fip/bl30_new.bin.g12a.enc \
+                                          --level v3
     $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
-                                       --output fip/bl30_new.bin.enc \
-                                       --level v3 --type bl30
+                                          --output fip/bl30_new.bin.enc \
+                                          --level v3 --type bl30
     $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
-                                       --output fip/bl31.img.enc \
-                                       --level v3 --type bl31
+                                          --output fip/bl31.img.enc \
+                                          --level v3 --type bl31
     $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
-                                       --output fip/bl33.bin.enc \
-                                       --level v3 --type bl33 --compress lz4
+                                          --output fip/bl33.bin.enc \
+                                          --level v3 --type bl33 --compress lz4
     $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
-                                       --output fip/bl2.n.bin.sig
+                                          --output fip/bl2.n.bin.sig
     $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \
-               --output fip/u-boot.bin \
-               --bl2 fip/bl2.n.bin.sig \
-               --bl30 fip/bl30_new.bin.enc \
-               --bl31 fip/bl31.img.enc \
-               --bl33 fip/bl33.bin.enc \
-               --ddrfw1 fip/ddr4_1d.fw \
-               --ddrfw2 fip/ddr4_2d.fw \
-               --ddrfw3 fip/ddr3_1d.fw \
-               --ddrfw4 fip/piei.fw \
-               --ddrfw5 fip/lpddr4_1d.fw \
-               --ddrfw6 fip/lpddr4_2d.fw \
-               --ddrfw7 fip/diag_lpddr4.fw \
-               --ddrfw8 fip/aml_ddr.fw \
-               --ddrfw9 fip/lpddr3_1d.fw \
-               --level v3
-
-and then write the image to SD with:
+                                          --output fip/u-boot.bin \
+                                          --bl2 fip/bl2.n.bin.sig \
+                                          --bl30 fip/bl30_new.bin.enc \
+                                          --bl31 fip/bl31.img.enc \
+                                          --bl33 fip/bl33.bin.enc \
+                                          --ddrfw1 fip/ddr4_1d.fw \
+                                          --ddrfw2 fip/ddr4_2d.fw \
+                                          --ddrfw3 fip/ddr3_1d.fw \
+                                          --ddrfw4 fip/piei.fw \
+                                          --ddrfw5 fip/lpddr4_1d.fw \
+                                          --ddrfw6 fip/lpddr4_2d.fw \
+                                          --ddrfw7 fip/diag_lpddr4.fw \
+                                          --ddrfw8 fip/aml_ddr.fw \
+                                          --ddrfw9 fip/lpddr3_1d.fw \
+                                          --level v3
+
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
+    $ DEV=/dev/boot_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/khadas-vim3l.rst b/doc/board/amlogic/khadas-vim3l.rst
index 692ab3d..cd21466 100644 (file)
--- a/doc/board/amlogic/khadas-vim3l.rst
+++ b/doc/board/amlogic/khadas-vim3l.rst
@@ -1,10 +1,10 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for Khadas VIM3L
-=======================
+U-Boot for Khadas VIM3L (S905D3)
+================================
 
-Khadas VIM3L is a single board computer manufactured by Shenzhen Wesion
-Technology Co., Ltd. with the following specifications:
+Khadas VIM3L is a Single Board Computer manufactured by Shenzhen Wesion Technology Co. Ltd
+with the following specifications:
 
  - Amlogic S905D3 Arm Cortex-A55 quad-core SoC
  - 2GB LPDDR4 SDRAM
@@ -20,32 +20,27 @@ Schematics are available on the manufacturer website.
 
 PCIe Setup
 ----------
-The VIM3 on-board  MCU can mux the PCIe/USB3.0 shared differential
-lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
-an USB3.0 Type A connector and a M.2 Key M slot.
-The PHY driving these differential lines is shared between
-the USB3.0 controller and the PCIe Controller, thus only
-a single controller can use it.
 
-To setup for PCIe, run the following commands from U-Boot:
+The on-board MCU can mux the PCIe/USB3.0 shared differential lines using a FUSB340TMX USB
+3.1 SuperSpeed Data Switch between a USB3.0 Type-A connector and an M.2 Key-M slot. The
+PHY driving these differential lines is shared between the USB3.0 controller and the PCIe
+Controller, thus only a single controller can use it.
+
+To setup for PCIe run the following commands from U-Boot then power-cycle the board:
 
 .. code-block:: none
 
     i2c dev i2c@5000
     i2c mw 0x18 0x33 1
 
-Then power-cycle the board.
-
-To set back to USB3.0, run the following commands from U-Boot:
+To revert to USB3.0 run the following commands from U-Boot then power-cycle the board:
 
 .. code-block:: none
 
     i2c dev i2c@5000
     i2c mw 0x18 0x33 0
 
-Then power-cycle the board.
-
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -54,14 +49,21 @@ U-Boot compilation
     $ make khadas-vim3l_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh khadas-vim3l /path/to/u-boot/u-boot.bin my-output-dir
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `khadas-vim3l`
+U-Boot Manual Signing
+---------------------
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
 
 .. code-block:: bash
 
@@ -72,16 +74,14 @@ the git tree published by the board vendor:
     $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
 
     $ DIR=vim3l-u-boot
-    $ git clone --depth 1 \
-       https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 \
-       $DIR
+    $ git clone --depth 1 https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 $DIR
 
     $ cd vim3l-u-boot
     $ make kvim3l_defconfig
     $ make CROSS_COMPILE=aarch64-none-elf-
     $ export UBOOTDIR=$PWD
 
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
 
 .. code-block:: bash
 
@@ -105,58 +105,58 @@ Go back to mainline U-Boot source tree then :
     $ cp u-boot.bin fip/bl33.bin
 
     $ bash fip/blx_fix.sh \
-       fip/bl30.bin \
-       fip/zero_tmp \
-       fip/bl30_zero.bin \
-       fip/bl301.bin \
-       fip/bl301_zero.bin \
-       fip/bl30_new.bin \
-       bl30
+           fip/bl30.bin \
+           fip/zero_tmp \
+           fip/bl30_zero.bin \
+           fip/bl301.bin \
+           fip/bl301_zero.bin \
+           fip/bl30_new.bin \
+           bl30
 
     $ bash fip/blx_fix.sh \
-       fip/bl2.bin \
-       fip/zero_tmp \
-       fip/bl2_zero.bin \
-       fip/acs.bin \
-       fip/bl21_zero.bin \
-       fip/bl2_new.bin \
-       bl2
+           fip/bl2.bin \
+           fip/zero_tmp \
+           fip/bl2_zero.bin \
+           fip/acs.bin \
+           fip/bl21_zero.bin \
+           fip/bl2_new.bin \
+           bl2
 
     $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
-                                       --output fip/bl30_new.bin.g12a.enc \
-                                       --level v3
+                                          --output fip/bl30_new.bin.g12a.enc \
+                                          --level v3
     $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
-                                       --output fip/bl30_new.bin.enc \
-                                       --level v3 --type bl30
+                                          --output fip/bl30_new.bin.enc \
+                                          --level v3 --type bl30
     $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
-                                       --output fip/bl31.img.enc \
-                                       --level v3 --type bl31
+                                          --output fip/bl31.img.enc \
+                                          --level v3 --type bl31
     $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
-                                       --output fip/bl33.bin.enc \
-                                       --level v3 --type bl33 --compress lz4
+                                          --output fip/bl33.bin.enc \
+                                          --level v3 --type bl33 --compress lz4
     $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
-                                       --output fip/bl2.n.bin.sig
+                                          --output fip/bl2.n.bin.sig
     $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \
-               --output fip/u-boot.bin \
-               --bl2 fip/bl2.n.bin.sig \
-               --bl30 fip/bl30_new.bin.enc \
-               --bl31 fip/bl31.img.enc \
-               --bl33 fip/bl33.bin.enc \
-               --ddrfw1 fip/ddr4_1d.fw \
-               --ddrfw2 fip/ddr4_2d.fw \
-               --ddrfw3 fip/ddr3_1d.fw \
-               --ddrfw4 fip/piei.fw \
-               --ddrfw5 fip/lpddr4_1d.fw \
-               --ddrfw6 fip/lpddr4_2d.fw \
-               --ddrfw7 fip/diag_lpddr4.fw \
-               --ddrfw8 fip/aml_ddr.fw \
-               --ddrfw9 fip/lpddr3_1d.fw \
-               --level v3
-
-and then write the image to SD with:
+                                          --output fip/u-boot.bin \
+                                          --bl2 fip/bl2.n.bin.sig \
+                                          --bl30 fip/bl30_new.bin.enc \
+                                          --bl31 fip/bl31.img.enc \
+                                          --bl33 fip/bl33.bin.enc \
+                                          --ddrfw1 fip/ddr4_1d.fw \
+                                          --ddrfw2 fip/ddr4_2d.fw \
+                                          --ddrfw3 fip/ddr3_1d.fw \
+                                          --ddrfw4 fip/piei.fw \
+                                          --ddrfw5 fip/lpddr4_1d.fw \
+                                          --ddrfw6 fip/lpddr4_2d.fw \
+                                          --ddrfw7 fip/diag_lpddr4.fw \
+                                          --ddrfw8 fip/aml_ddr.fw \
+                                          --ddrfw9 fip/lpddr3_1d.fw \
+                                          --level v3
+
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
+    $ DEV=/dev/boot_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/libretech-ac.rst b/doc/board/amlogic/libretech-ac.rst
index 7a915f9..fa151c0 100644 (file)
--- a/doc/board/amlogic/libretech-ac.rst
+++ b/doc/board/amlogic/libretech-ac.rst
@@ -1,9 +1,9 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for LibreTech AC
-=======================
+U-Boot for LibreTech-AC 'LaFrite' (S805X)
+=========================================
 
-LibreTech AC is a single board computer manufactured by Libre Technology
+LibreTech-AC aka 'LaFrite' is a Single Board Computer manufactured by Libre Computer
 with the following specifications:
 
  - Amlogic S805X ARM Cortex-A53 quad-core SoC @ 1.2GHz
@@ -13,12 +13,13 @@ with the following specifications:
  - HDMI 2.0 4K/60Hz display
  - 40-pin GPIO header
  - 4 x USB 2.0 Host
- - eMMC, SPI NOR Flash
+ - SPI NOR Flash
+ - Removable eMMC module
  - Infrared receiver
 
 Schematics are available on the manufacturer website.
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -27,14 +28,21 @@ U-Boot compilation
     $ make libretech-ac_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `lafrite`
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh lafrite /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
 
 .. code-block:: bash
 
@@ -50,7 +58,7 @@ the git tree published by the board vendor:
     $ make
     $ export UBOOTDIR=$PWD
 
-Download the latest Amlogic Buildroot package, and extract it :
+Download the latest Amlogic buildroot package and extract it:
 
 .. code-block:: bash
 
@@ -58,7 +66,7 @@ Download the latest Amlogic Buildroot package, and extract it :
     $ tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180418.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180418/bootloader
     $ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180418
 
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
 
 .. code-block:: bash
 
@@ -73,40 +81,40 @@ Go back to mainline U-Boot source tree then :
     $ cp u-boot.bin fip/bl33.bin
 
     $ sh $UBOOTDIR/blx_fix.sh \
-       fip/bl30.bin \
-       fip/zero_tmp \
-       fip/bl30_zero.bin \
-       fip/bl301.bin \
-       fip/bl301_zero.bin \
-       fip/bl30_new.bin \
-       bl30
+                   fip/bl30.bin \
+                   fip/zero_tmp \
+                   fip/bl30_zero.bin \
+                   fip/bl301.bin \
+                   fip/bl301_zero.bin \
+                   fip/bl30_new.bin \
+                   bl30
 
     $ $BRDIR/bootloader/uboot-repo/fip/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
 
     $ sh $UBOOTDIR/blx_fix.sh \
-       fip/bl2_acs.bin \
-       fip/zero_tmp \
-       fip/bl2_zero.bin \
-       fip/bl21.bin \
-       fip/bl21_zero.bin \
-       fip/bl2_new.bin \
-       bl2
+                   fip/bl2_acs.bin \
+                   fip/zero_tmp \
+                   fip/bl2_zero.bin \
+                   fip/bl21.bin \
+                   fip/bl21_zero.bin \
+                   fip/bl2_new.bin \
+                   bl2
 
     $ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
     $ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
     $ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
     $ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
     $ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bootmk \
-               --output fip/u-boot.bin \
-               --bl2 fip/bl2.n.bin.sig \
-               --bl30 fip/bl30_new.bin.enc \
-               --bl31 fip/bl31.img.enc \
-               --bl33 fip/bl33.bin.enc
+                   --output fip/u-boot.bin \
+                   --bl2 fip/bl2.n.bin.sig \
+                   --bl30 fip/bl30_new.bin.enc \
+                   --bl31 fip/bl31.img.enc \
+                   --bl33 fip/bl33.bin.enc
 
-and then write the image to SD with:
+Then write U-Boot to USB or SPI-NOR with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
+    $ DEV=/dev/boot_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/libretech-cc.rst b/doc/board/amlogic/libretech-cc.rst
index 596ce45..08a84a4 100644 (file)
--- a/doc/board/amlogic/libretech-cc.rst
+++ b/doc/board/amlogic/libretech-cc.rst
@@ -1,12 +1,12 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for LibreTech CCs
-========================
+U-Boot for LibreTech CC 'LePotato' (S905X)
+==========================================
 
-LibreTech CC is a single board computer manufactured by Libre Technology
-with the following specifications:
+LibreTech CC is a Single Board Computer manufactured by Libre Computer Technology with
+the following specifications:
 
-V1:
+v1:
 
  - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz
  - ARM Mali 450 GPU
@@ -19,14 +19,14 @@ V1:
  - Infrared receiver
  - Jack for CVBS and Audio
 
-V2:
+v2:
 
  - Added SPI NOR
  - Removed Jack
 
 Schematics are available on the manufacturer website.
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -37,36 +37,21 @@ U-Boot compilation
 
 Use libretech-cc_v2_defconfig for v2.
 
-Image creation
---------------
-
-To boot the system, u-boot must be combined with several earlier stage
-bootloaders:
-
-* bl2.bin: vendor-provided binary blob
-* bl21.bin: built from vendor u-boot source
-* bl30.bin: vendor-provided binary blob
-* bl301.bin: built from vendor u-boot source
-* bl31.bin: vendor-provided binary blob
-* acs.bin: built from vendor u-boot source
-
-These binaries and the tools required below have been collected and prebuilt
-for convenience at <https://github.com/BayLibre/u-boot/releases/>. These
-apply to both v1 and v2.
-
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `lepotato`
-
-Download and extract the libretech-cc release from there, and set FIPDIR to
-point to the `fip` subdirectory.
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
 .. code-block:: bash
 
-    $ export FIPDIR=/path/to/extracted/fip
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh lepotato /path/to/u-boot/u-boot.bin my-output-dir
 
-Alternatively, you can obtain the original vendor u-boot tree which
-contains the required blobs and sources, and build yourself.
-Note that old compilers are required for this to build. The compilers here
-are suggested by Amlogic, and they are 32-bit x86 binaries.
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
 
 .. code-block:: bash
 
@@ -81,9 +66,7 @@ are suggested by Amlogic, and they are 32-bit x86 binaries.
     $ make
     $ export FIPDIR=$PWD/fip
 
-Once you have the binaries available (either through the prebuilt download,
-or having built the vendor u-boot yourself), you can then proceed to glue
-everything together. Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
 
 .. code-block:: bash
 
@@ -98,51 +81,40 @@ everything together. Go back to mainline U-Boot source tree then :
     $ cp u-boot.bin fip/bl33.bin
 
     $ $FIPDIR/blx_fix.sh \
-       fip/bl30.bin \
-       fip/zero_tmp \
-       fip/bl30_zero.bin \
-       fip/bl301.bin \
-       fip/bl301_zero.bin \
-       fip/bl30_new.bin \
-       bl30
+              fip/bl30.bin \
+              fip/zero_tmp \
+              fip/bl30_zero.bin \
+              fip/bl301.bin \
+              fip/bl301_zero.bin \
+              fip/bl30_new.bin \
+              bl30
 
     $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
 
     $ $FIPDIR/blx_fix.sh \
-       fip/bl2_acs.bin \
-       fip/zero_tmp \
-       fip/bl2_zero.bin \
-       fip/bl21.bin \
-       fip/bl21_zero.bin \
-       fip/bl2_new.bin \
-       bl2
+              fip/bl2_acs.bin \
+              fip/zero_tmp \
+              fip/bl2_zero.bin \
+              fip/bl21.bin \
+              fip/bl21_zero.bin \
+              fip/bl2_new.bin \
+              bl2
 
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
     $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
-               --output fip/u-boot.bin \
-               --bl2 fip/bl2.n.bin.sig \
-               --bl30 fip/bl30_new.bin.enc \
-               --bl31 fip/bl31.img.enc \
-               --bl33 fip/bl33.bin.enc
+                                  --output fip/u-boot.bin \
+                                  --bl2 fip/bl2.n.bin.sig \
+                                  --bl30 fip/bl30_new.bin.enc \
+                                  --bl31 fip/bl31.img.enc \
+                                  --bl33 fip/bl33.bin.enc
 
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
+    $ DEV=/dev/boot_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
-
-Note that Amlogic provides aml_encrypt_gxl as a 32-bit x86 binary with no
-source code. Should you prefer to avoid that, there are open source reverse
-engineered versions available:
-
-1. gxlimg <https://github.com/repk/gxlimg>, which comes with a handy
-   Makefile that automates the whole process.
-2. meson-tools <https://github.com/afaerber/meson-tools>
-
-However, these community-developed alternatives are not endorsed by or
-supported by Amlogic.
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/nanopi-k2.rst b/doc/board/amlogic/nanopi-k2.rst
index 76ff874..53a0a41 100644 (file)
--- a/doc/board/amlogic/nanopi-k2.rst
+++ b/doc/board/amlogic/nanopi-k2.rst
@@ -1,10 +1,10 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for NanoPi-K2
-====================
+U-Boot for NanoPi-K2 (S905)
+===========================
 
-NanoPi-K2 is a single board computer manufactured by FriendlyElec
-with the following specifications:
+NanoPi-K2 is a single board computer manufactured by FriendlyElec with the following
+specifications:
 
  - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
  - ARM Mali 450 GPU
@@ -18,7 +18,7 @@ with the following specifications:
 
 Schematics are available on the manufacturer website.
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -27,14 +27,21 @@ U-Boot compilation
     $ make nanopi-k2_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `nanopi-k2`
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh nanopi-k2 /path/to/u-boot/u-boot.bin my-output-dir
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
 
 .. code-block:: bash
 
@@ -43,7 +50,6 @@ the git tree published by the board vendor:
     $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
     $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
     $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
-    $ git clone https://github.com/BayLibre/u-boot.git -b libretech-cc amlogic-u-boot
     $ git clone https://github.com/friendlyarm/u-boot.git -b nanopi-k2-v2015.01 amlogic-u-boot
     $ cd amlogic-u-boot
     $ sed -i 's/aarch64-linux-gnu-/aarch64-none-elf-/' Makefile
@@ -52,7 +58,7 @@ the git tree published by the board vendor:
     $ make
     $ export FIPDIR=$PWD/fip
 
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
 
 .. code-block:: bash
 
@@ -65,42 +71,52 @@ Go back to mainline U-Boot source tree then :
     $ cp $FIPDIR/gxb/bl301.bin fip/
     $ cp $FIPDIR/gxb/bl31.img fip/
     $ cp u-boot.bin fip/bl33.bin
+    $ wget https://github.com/LibreELEC/amlogic-boot-fip/raw/master/nanopi-k2/bl1.bin.hardkernel fip/bl1.bin.hardkernel
+    $ chmod +x fip/bl1.bin.hardkernel
+    $ wget https://github.com/LibreELEC/amlogic-boot-fip/raw/master/nanopi-k2/aml_chksum fip/aml_chksum
+    $ chmod +x fip/aml_chksum
 
     $ $FIPDIR/blx_fix.sh \
-       fip/bl30.bin \
-       fip/zero_tmp \
-       fip/bl30_zero.bin \
-       fip/bl301.bin \
-       fip/bl301_zero.bin \
-       fip/bl30_new.bin \
-       bl30
-
-    $ $FIPDIR/fip_create \
-        --bl30 fip/bl30_new.bin \
-        --bl31 fip/bl31.img \
-        --bl33 fip/bl33.bin \
-        fip/fip.bin
-
+              fip/bl30.bin \
+              fip/zero_tmp \
+              fip/bl30_zero.bin \
+              fip/bl301.bin \
+              fip/bl301_zero.bin \
+              fip/bl30_new.bin \
+              bl30
+
+    $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin \
+                         --bl31 fip/bl31.img \
+                         --bl33 fip/bl33.bin \
+                         fip/fip.bin
+
+    $ sed -i 's/\x73\x02\x08\x91/\x1F\x20\x03\xD5/' fip/bl2.bin
     $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
 
     $ $FIPDIR/blx_fix.sh \
-       fip/bl2_acs.bin \
-       fip/zero_tmp \
-       fip/bl2_zero.bin \
-       fip/bl21.bin \
-       fip/bl21_zero.bin \
-       fip/bl2_new.bin \
-       bl2
+              fip/bl2_acs.bin \
+              fip/zero_tmp \
+              fip/bl2_zero.bin \
+              fip/bl21.bin \
+              fip/bl21_zero.bin \
+              fip/bl2_new.bin \
+              bl2
 
     $ cat fip/bl2_new.bin fip/fip.bin > fip/boot_new.bin
 
     $ $FIPDIR/gxb/aml_encrypt_gxb --bootsig \
-               --input fip/boot_new.bin
-               --output fip/u-boot.bin
+                                  --input fip/boot_new.bin
+                                  --output fip/u-boot.bin
 
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
-    $ dd if=fip/u-boot.bin of=$DEV conv=fsync,notrunc bs=512 seek=1
+    $ DEV=/dev/boot_device
+    $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 conv=fsync
+    $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 seek=9 skip=8 count=87 conv=fsync,notrunc
+    $ dd if=/dev/zero of=fip/u-boot.bin.gxbb bs=512 seek=8 count=1 conv=fsync,notrunc
+    $ dd if=bl1.bin.hardkernel of=fip/u-boot.bin.gxbb bs=512 seek=2 skip=2 count=1 conv=fsync,notrunc
+    $ ./aml_chksum fip/u-boot.bin.gxbb
+    $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/odroid-c2.rst b/doc/board/amlogic/odroid-c2.rst
index 8a1be4b..922ab0c 100644 (file)
--- a/doc/board/amlogic/odroid-c2.rst
+++ b/doc/board/amlogic/odroid-c2.rst
@@ -1,12 +1,12 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for ODROID-C2
-====================
+U-Boot for ODROID-C2 (S905)
+===========================
 
-ODROID-C2 is a single board computer manufactured by Hardkernel
-Co. Ltd with the following specifications:
+ODROID-C2 is a single board computer manufactured by Hardkernel with the following
+specifications:
 
- - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 2GHz
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
  - ARM Mali 450 GPU
  - 2GB DDR3 SDRAM
  - Gigabit Ethernet
@@ -16,9 +16,9 @@ Co. Ltd with the following specifications:
  - eMMC, microSD
  - Infrared receiver
 
-Schematics are available on the manufacturer website.
+Schematics are available on the manufacturer website: https://wiki.odroid.com
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -27,38 +27,45 @@ U-Boot compilation
     $ make odroid-c2_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `odroid-c2`
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh odroid-c2 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
 
 .. code-block:: bash
 
     $ DIR=odroid-c2
-    $ git clone --depth 1 \
-       https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \
-       $DIR
+    $ git clone --depth 1 https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 $DIR
+
     $ $DIR/fip/fip_create --bl30  $DIR/fip/gxb/bl30.bin \
-                       --bl301 $DIR/fip/gxb/bl301.bin \
-                       --bl31  $DIR/fip/gxb/bl31.bin \
-                       --bl33  u-boot.bin \
-                       $DIR/fip.bin
+                          --bl301 $DIR/fip/gxb/bl301.bin \
+                          --bl31  $DIR/fip/gxb/bl31.bin \
+                          --bl33  u-boot.bin \
+                          $DIR/fip.bin
+
     $ $DIR/fip/fip_create --dump $DIR/fip.bin
     $ cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin
     $ $DIR/fip/gxb/aml_encrypt_gxb --bootsig \
-                                --input $DIR/boot_new.bin \
-                                --output $DIR/u-boot.img
+                                   --input $DIR/boot_new.bin \
+                                   --output $DIR/u-boot.img
     $ dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96
 
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
+    $ DEV=/dev/your_boot_device
     $ BL1=$DIR/sd_fuse/bl1.bin.hardkernel
     $ dd if=$BL1 of=$DEV conv=fsync bs=1 count=442
     $ dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1

diff --git a/doc/board/amlogic/odroid-c4.rst b/doc/board/amlogic/odroid-c4.rst
index b512c6a..6994b95 100644 (file)
--- a/doc/board/amlogic/odroid-c4.rst
+++ b/doc/board/amlogic/odroid-c4.rst
@@ -1,10 +1,10 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for ODROID-C4
-====================
+U-Boot for ODROID-C4 (S905X3)
+=============================
 
-ODROID-C4 is a single board computer manufactured by Hardkernel
-Co. Ltd with the following specifications:
+ODROID-C4 is a Single Board Computer manufactured by Hardkernel with the following
+specifications:
 
  - Amlogic S905X3 Arm Cortex-A55 quad-core SoC
  - 4GB DDR4 SDRAM
@@ -17,12 +17,9 @@ Co. Ltd with the following specifications:
  - UART serial
  - Infrared receiver
 
-The ODROID-HC4 is a variant with a PCIe-SATA controller, the same commands
-applies for HC4.
-
 Schematics are available on the manufacturer website.
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -31,14 +28,21 @@ U-Boot compilation
     $ make odroid-c4_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh odroid-c4 /path/to/u-boot/u-boot.bin my-output-dir
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `odroid-c4` or `odroid-hc4`
+U-Boot Manual Signing
+---------------------
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
 
 .. code-block:: bash
 
@@ -58,7 +62,7 @@ the git tree published by the board vendor:
     $ make
     $ export UBOOTDIR=$PWD
 
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
 
 .. code-block:: bash
 
@@ -82,58 +86,58 @@ Go back to mainline U-Boot source tree then :
     $ cp u-boot.bin fip/bl33.bin
 
     $ sh fip/blx_fix.sh \
-       fip/bl30.bin \
-       fip/zero_tmp \
-       fip/bl30_zero.bin \
-       fip/bl301.bin \
-       fip/bl301_zero.bin \
-       fip/bl30_new.bin \
-       bl30
+         fip/bl30.bin \
+         fip/zero_tmp \
+         fip/bl30_zero.bin \
+         fip/bl301.bin \
+         fip/bl301_zero.bin \
+         fip/bl30_new.bin \
+         bl30
 
     $ sh fip/blx_fix.sh \
-       fip/bl2.bin \
-       fip/zero_tmp \
-       fip/bl2_zero.bin \
-       fip/acs.bin \
-       fip/bl21_zero.bin \
-       fip/bl2_new.bin \
-       bl2
+         fip/bl2.bin \
+         fip/zero_tmp \
+         fip/bl2_zero.bin \
+         fip/acs.bin \
+         fip/bl21_zero.bin \
+         fip/bl2_new.bin \
+         bl2
 
     $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
-                                       --output fip/bl30_new.bin.g12a.enc \
-                                       --level v3
+                                          --output fip/bl30_new.bin.g12a.enc \
+                                          --level v3
     $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
-                                       --output fip/bl30_new.bin.enc \
-                                       --level v3 --type bl30
+                                          --output fip/bl30_new.bin.enc \
+                                          --level v3 --type bl30
     $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
-                                       --output fip/bl31.img.enc \
-                                       --level v3 --type bl31
+                                          --output fip/bl31.img.enc \
+                                          --level v3 --type bl31
     $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
-                                       --output fip/bl33.bin.enc \
-                                       --level v3 --type bl33 --compress lz4
+                                          --output fip/bl33.bin.enc \
+                                          --level v3 --type bl33 --compress lz4
     $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
-                                       --output fip/bl2.n.bin.sig
+                                          --output fip/bl2.n.bin.sig
     $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \
-               --output fip/u-boot.bin \
-               --bl2 fip/bl2.n.bin.sig \
-               --bl30 fip/bl30_new.bin.enc \
-               --bl31 fip/bl31.img.enc \
-               --bl33 fip/bl33.bin.enc \
-               --ddrfw1 fip/ddr4_1d.fw \
-               --ddrfw2 fip/ddr4_2d.fw \
-               --ddrfw3 fip/ddr3_1d.fw \
-               --ddrfw4 fip/piei.fw \
-               --ddrfw5 fip/lpddr4_1d.fw \
-               --ddrfw6 fip/lpddr4_2d.fw \
-               --ddrfw7 fip/diag_lpddr4.fw \
-               --ddrfw8 fip/aml_ddr.fw \
-               --ddrfw9 fip/lpddr3_1d.fw \
-               --level v3
-
-and then write the image to SD with:
+                                          --output fip/u-boot.bin \
+                                          --bl2 fip/bl2.n.bin.sig \
+                                          --bl30 fip/bl30_new.bin.enc \
+                                          --bl31 fip/bl31.img.enc \
+                                          --bl33 fip/bl33.bin.enc \
+                                          --ddrfw1 fip/ddr4_1d.fw \
+                                          --ddrfw2 fip/ddr4_2d.fw \
+                                          --ddrfw3 fip/ddr3_1d.fw \
+                                          --ddrfw4 fip/piei.fw \
+                                          --ddrfw5 fip/lpddr4_1d.fw \
+                                          --ddrfw6 fip/lpddr4_2d.fw \
+                                          --ddrfw7 fip/diag_lpddr4.fw \
+                                          --ddrfw8 fip/aml_ddr.fw \
+                                          --ddrfw9 fip/lpddr3_1d.fw \
+                                          --level v3
+
+Then write the image to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
+    $ DEV=/dev/boot_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/odroid-go-ultra.rst b/doc/board/amlogic/odroid-go-ultra.rst
index 8df9e0c..caf0e38 100644 (file)
--- a/doc/board/amlogic/odroid-go-ultra.rst
+++ b/doc/board/amlogic/odroid-go-ultra.rst
@@ -1,10 +1,9 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for ODROID-GO-ULTRA
-==========================
+U-Boot for ODROID-GO-ULTRA (S922X)
+==================================
 
-The Odroid Go Ultra is a portable gaming device with the following
-characteristics:
+The ODROID GO ULTRA is a portable gaming device with the following characteristics:
 
  - Amlogic S922X SoC
  - RK817 & RK818 PMICs
@@ -19,7 +18,7 @@ characteristics:
  - 2x ADC Analog Joysticks
  - USB-C Port for USB2 Device and Charging
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -28,7 +27,20 @@ U-Boot compilation
     $ make odroid-go-ultra_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
-Pleaser refer to :doc:`pre-generated-fip` with codename `odroid-go-ultra`
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh odroid-go-ultra /path/to/u-boot/u-boot.bin my-output-dir
+
+Then write the image to SD or eMMC with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/boot_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/odroid-hc4.rst b/doc/board/amlogic/odroid-hc4.rst
new file mode 100644 (file)
index 0000000..1d37be2
--- /dev/null
+++ b/doc/board/amlogic/odroid-hc4.rst
@@ -0,0 +1,142 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for ODROID-HC4 (S905X3)
+==============================
+
+ODROID-HC4 is a variant of the ODROID-C4 single board computer manufactured by Hardkernel
+with the following specification:
+
+ - Amlogic S905X3 Arm Cortex-A55 quad-core SoC
+ - 4GB DDR4 SDRAM
+ - 16MB XT25F128B SPI-NOR flash
+ - Gigabit Ethernet
+ - HDMI 2.1 display
+ - 7-pin GPIO header for OLED display and RTC
+ - 1x USB 2.0 host (micro)
+ - 2x SATA ports via ASM1061 PCIe to SATA controller
+ - microSD
+ - UART serial
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make odroid-hc4_defconfig
+    $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh odroid-hc4 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+    $ DIR=odroid-hc4
+    $ git clone --depth 1 https://github.com/hardkernel/u-boot.git -b odroidg12-v2015.01 $DIR
+
+    $ cd odroid-hc4
+    $ make odroidc4_defconfig
+    $ make
+    $ export UBOOTDIR=$PWD
+
+Go back to mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+    $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+    $ cp $UBOOTDIR/build/board/hardkernel/odroidc4/firmware/acs.bin fip/
+    $ cp $UBOOTDIR/fip/g12a/bl2.bin fip/
+    $ cp $UBOOTDIR/fip/g12a/bl30.bin fip/
+    $ cp $UBOOTDIR/fip/g12a/bl31.img fip/
+    $ cp $UBOOTDIR/fip/g12a/ddr3_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/ddr4_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/ddr4_2d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/diag_lpddr4.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/lpddr3_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/lpddr4_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/lpddr4_2d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/piei.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/aml_ddr.fw fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ sh fip/blx_fix.sh \
+         fip/bl30.bin \
+         fip/zero_tmp \
+         fip/bl30_zero.bin \
+         fip/bl301.bin \
+         fip/bl301_zero.bin \
+         fip/bl30_new.bin \
+         bl30
+
+    $ sh fip/blx_fix.sh \
+         fip/bl2.bin \
+         fip/zero_tmp \
+         fip/bl2_zero.bin \
+         fip/acs.bin \
+         fip/bl21_zero.bin \
+         fip/bl2_new.bin \
+         bl2
+
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
+                                                    --output fip/bl30_new.bin.g12a.enc \
+                                                    --level v3
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
+                                                   --output fip/bl30_new.bin.enc \
+                                                   --level v3 --type bl30
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
+                                                   --output fip/bl31.img.enc \
+                                                   --level v3 --type bl31
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
+                                                   --output fip/bl33.bin.enc \
+                                                   --level v3 --type bl33 --compress lz4
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
+                                                   --output fip/bl2.n.bin.sig
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \
+                                          --output fip/u-boot.bin \
+                                          --bl2 fip/bl2.n.bin.sig \
+                                          --bl30 fip/bl30_new.bin.enc \
+                                          --bl31 fip/bl31.img.enc \
+                                          --bl33 fip/bl33.bin.enc \
+                                          --ddrfw1 fip/ddr4_1d.fw \
+                                          --ddrfw2 fip/ddr4_2d.fw \
+                                          --ddrfw3 fip/ddr3_1d.fw \
+                                          --ddrfw4 fip/piei.fw \
+                                          --ddrfw5 fip/lpddr4_1d.fw \
+                                          --ddrfw6 fip/lpddr4_2d.fw \
+                                          --ddrfw7 fip/diag_lpddr4.fw \
+                                          --ddrfw8 fip/aml_ddr.fw \
+                                          --ddrfw9 fip/lpddr3_1d.fw \
+                                          --level v3
+
+Then write U-Boot to SD or SPI-NOR with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/boot_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/odroid-n2.rst b/doc/board/amlogic/odroid-n2.rst
index 7aad36e..883720f 100644 (file)
--- a/doc/board/amlogic/odroid-n2.rst
+++ b/doc/board/amlogic/odroid-n2.rst
@@ -1,10 +1,10 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for ODROID-N2
-====================
+U-Boot for ODROID-N2/N2+ (S922X)
+================================
 
-ODROID-N2 is a single board computer manufactured by Hardkernel
-Co. Ltd with the following specifications:
+ODROID-N2 and ODROID-N2+ are a Single Board Computers manufactured by Hardkernel with the
+following specifications:
 
  - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
  - 4GB DDR4 SDRAM
@@ -15,9 +15,13 @@ Co. Ltd with the following specifications:
  - eMMC, microSD
  - Infrared receiver
 
-Schematics are available on the manufacturer website.
+ODROID-N2+ uses Rev-C silicon allowing higher CPU opp-points. U-Boot contains logic to
+read the model detail from SARADC and select the correct device-tree file if FDTDIR is
+used instead of an FDT reference to a specfic device-tree.
 
-U-Boot compilation
+Schematics are available on the manufacturer website: https://wiki.odroid.com
+
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -26,14 +30,21 @@ U-Boot compilation
     $ make odroid-n2_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh odroid-n2 /path/to/u-boot/u-boot.bin my-output-dir
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `odroid-n2` or `odroid-n2-plus`
+U-Boot Manual Signing
+---------------------
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
 
 .. code-block:: bash
 
@@ -44,16 +55,14 @@ the git tree published by the board vendor:
     $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
 
     $ DIR=odroid-n2
-    $ git clone --depth 1 \
-       https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01 \
-       $DIR
+    $ git clone --depth 1 https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01 $DIR
 
     $ cd odroid-n2
     $ make odroidn2_defconfig
     $ make
     $ export UBOOTDIR=$PWD
 
- Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
 
 .. code-block:: bash
 
@@ -76,57 +85,57 @@ the git tree published by the board vendor:
     $ cp u-boot.bin fip/bl33.bin
 
     $ sh fip/blx_fix.sh \
-       fip/bl30.bin \
-       fip/zero_tmp \
-       fip/bl30_zero.bin \
-       fip/bl301.bin \
-       fip/bl301_zero.bin \
-       fip/bl30_new.bin \
-       bl30
+         fip/bl30.bin \
+         fip/zero_tmp \
+         fip/bl30_zero.bin \
+         fip/bl301.bin \
+         fip/bl301_zero.bin \
+         fip/bl30_new.bin \
+         bl30
 
     $ sh fip/blx_fix.sh \
-       fip/bl2.bin \
-       fip/zero_tmp \
-       fip/bl2_zero.bin \
-       fip/acs.bin \
-       fip/bl21_zero.bin \
-       fip/bl2_new.bin \
-       bl2
+         fip/bl2.bin \
+         fip/zero_tmp \
+         fip/bl2_zero.bin \
+         fip/acs.bin \
+         fip/bl21_zero.bin \
+         fip/bl2_new.bin \
+         bl2
 
     $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
-                                       --output fip/bl30_new.bin.g12a.enc \
-                                       --level v3
+                                          --output fip/bl30_new.bin.g12a.enc \
+                                          --level v3
     $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
-                                       --output fip/bl30_new.bin.enc \
-                                       --level v3 --type bl30
+                                          --output fip/bl30_new.bin.enc \
+                                          --level v3 --type bl30
     $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
-                                       --output fip/bl31.img.enc \
-                                       --level v3 --type bl31
+                                          --output fip/bl31.img.enc \
+                                          --level v3 --type bl31
     $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
-                                       --output fip/bl33.bin.enc \
-                                       --level v3 --type bl33 --compress lz4
+                                          --output fip/bl33.bin.enc \
+                                          --level v3 --type bl33 --compress lz4
     $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
-                                       --output fip/bl2.n.bin.sig
+                                          --output fip/bl2.n.bin.sig
     $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \
-               --output fip/u-boot.bin \
-               --bl2 fip/bl2.n.bin.sig \
-               --bl30 fip/bl30_new.bin.enc \
-               --bl31 fip/bl31.img.enc \
-               --bl33 fip/bl33.bin.enc \
-               --ddrfw1 fip/ddr4_1d.fw \
-               --ddrfw2 fip/ddr4_2d.fw \
-               --ddrfw3 fip/ddr3_1d.fw \
-               --ddrfw4 fip/piei.fw \
-               --ddrfw5 fip/lpddr4_1d.fw \
-               --ddrfw6 fip/lpddr4_2d.fw \
-               --ddrfw7 fip/diag_lpddr4.fw \
-               --ddrfw8 fip/aml_ddr.fw \
-               --level v3
-
-and then write the image to SD with:
+                                          --output fip/u-boot.bin \
+                                          --bl2 fip/bl2.n.bin.sig \
+                                          --bl30 fip/bl30_new.bin.enc \
+                                          --bl31 fip/bl31.img.enc \
+                                          --bl33 fip/bl33.bin.enc \
+                                          --ddrfw1 fip/ddr4_1d.fw \
+                                          --ddrfw2 fip/ddr4_2d.fw \
+                                          --ddrfw3 fip/ddr3_1d.fw \
+                                          --ddrfw4 fip/piei.fw \
+                                          --ddrfw5 fip/lpddr4_1d.fw \
+                                          --ddrfw6 fip/lpddr4_2d.fw \
+                                          --ddrfw7 fip/diag_lpddr4.fw \
+                                          --ddrfw8 fip/aml_ddr.fw \
+                                          --level v3
+
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
+    $ DEV=/dev/boot_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/odroid-n2l.rst b/doc/board/amlogic/odroid-n2l.rst
index afd4409..6d58175 100644 (file)
--- a/doc/board/amlogic/odroid-n2l.rst
+++ b/doc/board/amlogic/odroid-n2l.rst
@@ -1,22 +1,23 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for ODROID-N2L
-=====================
+U-Boot for ODROID-N2L (S922X)
+=============================
 
-ODROID-N2L is a single board computer manufactured by Hardkernel
-Co. Ltd with the following specifications:
+ODROID-N2L is a Single Board Computer manufactured by Hardkernel with the following
+specifications:
 
  - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
  - 4GB DDR4 SDRAM
  - HDMI 2.1 4K/60Hz display
  - 40-pin GPIO header
- - 1 x USB 3.0 Host, 1 x USB USB 2.0 Host
+ - 1x USB 3.0 Host
+ - 1x USB 2.0 Host
  - eMMC, microSD
  - MIPI DSI Port
 
-Schematics are available on the manufacturer website.
+Schematics are available on the manufacturer website: https://wiki.odroid.com
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -25,7 +26,20 @@ U-Boot compilation
     $ make odroid-n2l_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `odroid-n2l`
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh odroid-n2l /path/to/u-boot/u-boot.bin my-output-dir
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/boot_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/p200.rst b/doc/board/amlogic/p200.rst
index 5e7c6b0..e223897 100644 (file)
--- a/doc/board/amlogic/p200.rst
+++ b/doc/board/amlogic/p200.rst
@@ -1,25 +1,24 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for Amlogic P200
-=======================
+U-Boot for Amlogic P200 (S905)
+==============================
 
-P200 is a reference board manufactured by Amlogic with the following
-specifications:
+P200 is a reference board manufactured by Amlogic with the following specification:
 
  - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
  - ARM Mali 450 GPU
  - 2GB DDR3 SDRAM
  - Gigabit Ethernet
  - HDMI 2.0 4K/60Hz display
- - 2 x USB 2.0 Host
+ - 2x USB 2.0 Host
  - eMMC, microSD
  - Infrared receiver
  - SDIO WiFi Module
- - CVBS+Stereo Audio Jack
+ - CVBS + Stereo Audio Jack
 
 Schematics are available from Amlogic on demand.
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -28,14 +27,21 @@ U-Boot compilation
     $ make p200_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `p200`
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh p200 /path/to/u-boot/u-boot.bin my-output-dir
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image but sources have been shared by Linux development contractor, Baylibre:
 
 .. code-block:: bash
 
@@ -50,7 +56,7 @@ the git tree published by the board vendor:
     $ make
     $ export FIPDIR=$PWD/fip
 
-Go back to mainline U-boot source tree then :
+Go back to the mainline U-Boot source tree then:
 
 .. code-block:: bash
 
@@ -63,37 +69,51 @@ Go back to mainline U-boot source tree then :
     $ cp $FIPDIR/gxb/bl301.bin fip/
     $ cp $FIPDIR/gxb/bl31.img fip/
     $ cp u-boot.bin fip/bl33.bin
+    $ wget https://github.com/LibreELEC/amlogic-boot-fip/raw/master/nanopi-k2/bl1.bin.hardkernel fip/bl1.bin.hardkernel
+    $ chmod +x fip/bl1.bin.hardkernel
+    $ wget https://github.com/LibreELEC/amlogic-boot-fip/raw/master/nanopi-k2/aml_chksum fip/aml_chksum
+    $ chmod +x fip/aml_chksum
 
     $ $FIPDIR/blx_fix.sh \
-       fip/bl30.bin \
-        fip/zero_tmp \
-        fip/bl30_zero.bin \
-        fip/bl301.bin \
-        fip/bl301_zero.bin \
-        fip/bl30_new.bin \
-        bl30
+              fip/bl30.bin \
+              fip/zero_tmp \
+              fip/bl30_zero.bin \
+              fip/bl301.bin \
+              fip/bl301_zero.bin \
+              fip/bl30_new.bin \
+              bl30
 
     $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
 
     $ $FIPDIR/blx_fix.sh \
-        fip/bl2_acs.bin \
-        fip/zero_tmp \
-        fip/bl2_zero.bin \
-        fip/bl21.bin \
-        fip/bl21_zero.bin \
-        fip/bl2_new.bin \
-        bl2
-
-    $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin --bl31 fip/bl31.img --bl33 fip/bl33.bin fip/fip.bin
+              fip/bl2_acs.bin \
+              fip/zero_tmp \
+              fip/bl2_zero.bin \
+              fip/bl21.bin \
+              fip/bl21_zero.bin \
+              fip/bl2_new.bin \
+              bl2
+
+    $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin \
+                         --bl31 fip/bl31.img \
+                         --bl33 fip/bl33.bin \
+                         fip/fip.bin
 
     $ cat fip/bl2_new.bin fip/fip.bin >fip/boot_new.bin
 
-    $ $FIPDIR/gxb/aml_encrypt_gxb --bootsig --input fip/boot_new.bin --output fip/u-boot.bin
+    $ $FIPDIR/gxb/aml_encrypt_gxb --bootsig \
+                                  --input fip/boot_new.bin \
+                                  --output fip/u-boot.bin
 
 and then write the image to SD with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ DEV=/dev/boot_device
+    $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 conv=fsync
+    $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 seek=9 skip=8 count=87 conv=fsync,notrunc
+    $ dd if=/dev/zero of=fip/u-boot.bin.gxbb bs=512 seek=8 count=1 conv=fsync,notrunc
+    $ dd if=bl1.bin.hardkernel of=fip/u-boot.bin.gxbb bs=512 seek=2 skip=2 count=1 conv=fsync,notrunc
+    $ ./aml_chksum fip/u-boot.bin.gxbb
+    $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/p201.rst b/doc/board/amlogic/p201.rst
index 2cd2365..28aae98 100644 (file)
--- a/doc/board/amlogic/p201.rst
+++ b/doc/board/amlogic/p201.rst
@@ -1,25 +1,24 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for Amlogic P201
-=======================
+U-Boot for Amlogic P201 (S905)
+==============================
 
-P201 is a reference board manufactured by Amlogic with the following
-specifications:
+P201 is a reference board manufactured by Amlogic with the following specifications:
 
  - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
  - ARM Mali 450 GPU
  - 2GB DDR3 SDRAM
  - 10/100 Ethernet
  - HDMI 2.0 4K/60Hz display
- - 2 x USB 2.0 Host
+ - 2x USB 2.0 Host
  - eMMC, microSD
  - Infrared receiver
  - SDIO WiFi Module
- - CVBS+Stereo Audio Jack
+ - CVBS + Stereo Audio Jack
 
 Schematics are available from Amlogic on demand.
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -28,14 +27,21 @@ U-Boot compilation
     $ make p201_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `p201`
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh p201 /path/to/u-boot/u-boot.bin my-output-dir
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image but sources have been shared by Linux development contractor, Baylibre:
 
 .. code-block:: bash
 
@@ -63,37 +69,51 @@ Go back to mainline U-boot source tree then :
     $ cp $FIPDIR/gxb/bl301.bin fip/
     $ cp $FIPDIR/gxb/bl31.img fip/
     $ cp u-boot.bin fip/bl33.bin
+    $ wget https://github.com/LibreELEC/amlogic-boot-fip/raw/master/nanopi-k2/bl1.bin.hardkernel fip/bl1.bin.hardkernel
+    $ chmod +x fip/bl1.bin.hardkernel
+    $ wget https://github.com/LibreELEC/amlogic-boot-fip/raw/master/nanopi-k2/aml_chksum fip/aml_chksum
+    $ chmod +x fip/aml_chksum
 
     $ $FIPDIR/blx_fix.sh \
-       fip/bl30.bin \
-        fip/zero_tmp \
-        fip/bl30_zero.bin \
-        fip/bl301.bin \
-        fip/bl301_zero.bin \
-        fip/bl30_new.bin \
-        bl30
+              fip/bl30.bin \
+              fip/zero_tmp \
+              fip/bl30_zero.bin \
+              fip/bl301.bin \
+              fip/bl301_zero.bin \
+              fip/bl30_new.bin \
+              bl30
 
     $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
 
     $ $FIPDIR/blx_fix.sh \
-        fip/bl2_acs.bin \
-        fip/zero_tmp \
-        fip/bl2_zero.bin \
-        fip/bl21.bin \
-        fip/bl21_zero.bin \
-        fip/bl2_new.bin \
-        bl2
-
-    $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin --bl31 fip/bl31.img --bl33 fip/bl33.bin fip/fip.bin
+              fip/bl2_acs.bin \
+              fip/zero_tmp \
+              fip/bl2_zero.bin \
+              fip/bl21.bin \
+              fip/bl21_zero.bin \
+              fip/bl2_new.bin \
+              bl2
+
+    $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin \
+                         --bl31 fip/bl31.img \
+                         --bl33 fip/bl33.bin \
+                         fip/fip.bin
 
     $ cat fip/bl2_new.bin fip/fip.bin >fip/boot_new.bin
 
-    $ $FIPDIR/gxb/aml_encrypt_gxb --bootsig --input fip/boot_new.bin --output fip/u-boot.bin
+    $ $FIPDIR/gxb/aml_encrypt_gxb --bootsig \
+                                  --input fip/boot_new.bin \
+                                  --output fip/u-boot.bin
 
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ DEV=/dev/boot_device
+    $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 conv=fsync
+    $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 seek=9 skip=8 count=87 conv=fsync,notrunc
+    $ dd if=/dev/zero of=fip/u-boot.bin.gxbb bs=512 seek=8 count=1 conv=fsync,notrunc
+    $ dd if=bl1.bin.hardkernel of=fip/u-boot.bin.gxbb bs=512 seek=2 skip=2 count=1 conv=fsync,notrunc
+    $ ./aml_chksum fip/u-boot.bin.gxbb
+    $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/pre-generated-fip.rst b/doc/board/amlogic/pre-generated-fip.rst
index c63ea61..6a43d77 100644 (file)
--- a/doc/board/amlogic/pre-generated-fip.rst
+++ b/doc/board/amlogic/pre-generated-fip.rst
@@ -1,24 +1,57 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-Pre-Generated FIP file set
-==========================
+Pre-Generated FIP File Repo
+===========================
 
-The Amlogic ARMv8 based SoCs uses a vendor variant of the Trusted Firmware-A
-boot architecture.
+Pre-built Flattened Image Package (FIP) sources and Amlogic signing binaries for many
+commercially available boards and some Android STB devices are collected for use with
+distro build-systems here: https://github.com/LibreELEC/amlogic-boot-fip
 
-You can find documentation on the Trusted Firmware-A architecture on: https://www.trustedfirmware.org/projects/tf-a/
+Using the pre-built FIP sources to sign U-Boot is simple, e.g. for LePotato:
 
-The Trusted Firmware-A uses the following boot elements (simplified):
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh lepotato /path/to/u-boot/u-boot.bin my-output-dir
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/boot_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
+
+Files Included
+--------------
+
+Amlogic ARMv8 SoCs use a vendor modified variant of the ARM Trusted Firmware-A boot
+architecture. See documentation here: https://www.trustedfirmware.org/projects/tf-a/
+
+Trusted Firmware-A uses the following boot elements (simplified):
+
+- BL1: First boot step implemented in ROM on Amlogic SoCs
+
+- BL2: Second boot step used to initialize the SoC main clocks & DDR interface. BL21
+  and ACS board-specific binaries must be "inserted" into the BL2 binary before signing
+  and packaging in order to be flashed on the platform
+
+- BL30: Amlogic Secure Co-Processor (SCP) firmware used to handle all system management
+  operations (DVFS, suspend/resume, ..)
+
+- BL301: Amlogic Secure Co-Processor (SCP) board-specific firmware "plug-in" to handle
+  custom DVFS & suspend-resume parameters
 
-- BL1: First boot step, implemented in ROM on Amlogic SoCs
-- BL2: Second boot step, used to initialize the SoC main clocks & DDR interface. The BL21 and ACS board-specific binaries are "inserted" in the BL32 binary before signing/packaging in order to be flashed on the platform.
-- BL30: Amlogic Secure Co-Processor (SCP) firmware used to handle all the system management operations (DVFS, suspend/resume, ...)
-- BL301: Amlogic Secure Co-Processor (SCP) board-specific firmware "plug-in" to handle custom DVFS & suspend-resume parameters
 - BL31: Initializes the interrupt controller and the system management interface (PSCI)
-- BL32 (Optional): Is the Trusted Environment Execution (TEE) Operating System to run secure Trusted Apps, e.g. OP-TEE
+
+- BL32 (Optional): Is the Trusted Environment Execution (TEE) Operating System used to
+  run secure Trusted Apps, e.g. OP-TEE
+
 - BL33: Is the last non-secure step, usually U-Boot which loads Linux
 
-Amlogic provides in binary form:
+Amlogic sources provide the following binaries:
 
 - bl2.bin
 - bl30.bin
@@ -26,10 +59,50 @@ Amlogic provides in binary form:
 - bl31.img
 - bl32.bin
 
-And for lastest SoCs, Amlogic also provides the DDR drivers used by the BL2 binary.
+For G12A/B and SM1 Amlogic also provides DDR drivers used by the BL2 binary:
+
+- ddr4_1d.fw
+- ddr4_2d.fw
+- ddr3_1d.fw
+- piei.fw
+- lpddr4_1d.fw
+- lpddr4_2d.fw
+- diag_lpddr4.fw
+- aml_ddr.fw
+
+The following files are generated from the Amlogic U-Boot fork:
+
+- acs.bin: Contains the PLL & DDR parameters for the board
+- bl301.bin: Contains the DVFS & suspend-resume handling code for the board
+- bl33.bin: U-boot binary image
+
+The acs.bin and bl301.bin files use U-Boot GPL-2.0+ headers and U-Boot build system and
+are thus considered to be issued from GPL-2.0+ source code.
+
+Amlogic alo provides pre-compiled x86_64 and Python2 binaries:
 
-The licence of these files wasn't clear until recently, the currently Amlogic distribution licence
-is the following:
+- aml_encrypt_gxb
+- aml_encrypt_gxl
+- aml_encrypt_g12a
+- aml_encrypt_g12b
+- acs_tool.pyc
+
+The repo replaces the pre-compiled acs_tool.pyc with a Python3 acs_tool.py that can be
+used with modern build hosts.
+
+The repo also provides the following files used with GXBB boards:
+
+- bl1.bin.hardkernel
+- aml_chksum
+
+The repo also supports the open-source 'gxlimg' signing tool that can be used to sign
+U-Boot binaries for GXL/GXM/G12A/G12B/SM1 boards: https://github.com/repk/gxlimg
+
+Licensing
+---------
+
+The licence of Amlogic provided binaries was not historically clear but has now been
+clarified. The current Amlogic distribution licence is below:
 
 .. code-block:: C
 
@@ -56,38 +129,3 @@ is the following:
     // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-The following files are generated from the Amlogic U-Boot fork:
-
-- acs.bin: contains the PLL & DDR parameters for the board
-- bl301.bin: contains the DVFS & suspend-resume handling code for the board
-- bl33.bin: U-boot binary image
-
-The acs.bin & bl301.bin uses the U-Boot GPL-2.0+ headers & build systems, thus those
-are considered issued from GPL-2.0+ source code.
-
-The tools used to sign & package those binary files are delivered in binary format
-for Intel x86-64 and Python 2.x only.
-
-A collection of pre-built with the corresponding Amlogic binaries for the common
-commercially available boards were collected in the https://github.com/LibreELEC/amlogic-boot-fip
-repository.
-
-Using this collection for a commercially available board is very easy.
-
-Here considering the Libre Computer AML-S905X-CC, which codename is `lepotato`:
-
-.. code-block:: bash
-
-    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
-    $ cd amlogic-boot-fip
-    $ mkdir my-output-dir
-    $ ./build-fip.sh lepotato /path/to/u-boot/u-boot.bin my-output-dir
-
-and then write the image to SD with:
-
-.. code-block:: bash
-
-    $ DEV=/dev/your_sd_device
-    $ dd if=my-output-dir/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=my-output-dir/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

diff --git a/doc/board/amlogic/q200.rst b/doc/board/amlogic/q200.rst
index 3ac4116..32ea472 100644 (file)
--- a/doc/board/amlogic/q200.rst
+++ b/doc/board/amlogic/q200.rst
@@ -1,24 +1,24 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for Amlogic Q200
-=======================
+U-Boot for Amlogic Q200 (S912)
+==============================
 
-Q200 is a reference board manufactured by Amlogic with the following
-specifications:
+Q200 is a reference board manufactured by Amlogic with the following specifications:
 
  - Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz
  - ARM Mali T860 GPU
  - 2/3GB DDR4 SDRAM
  - 10/100/1000 Ethernet
  - HDMI 2.0 4K/60Hz display
- - 2 x USB 2.0 Host, 1 x USB 2.0 Device
+ - 2x USB 2.0 Host
+ - 1x USB 2.0 Device
  - 16GB/32GB/64GB eMMC
  - 2MB SPI Flash
  - microSD
  - SDIO Wifi Module, Bluetooth
  - IR receiver
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -27,12 +27,21 @@ U-Boot compilation
     $ make khadas-vim2_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh q200 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image but sources have been shared by Linux development contractor, Baylibre:
 
 .. code-block:: bash
 
@@ -47,7 +56,7 @@ the git tree published by the board vendor:
     $ make
     $ export FIPDIR=$PWD/fip
 
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
 
 .. code-block:: bash
 
@@ -62,40 +71,40 @@ Go back to mainline U-Boot source tree then :
     $ cp u-boot.bin fip/bl33.bin
 
     $ $FIPDIR/blx_fix.sh \
-       fip/bl30.bin \
-       fip/zero_tmp \
-       fip/bl30_zero.bin \
-       fip/bl301.bin \
-       fip/bl301_zero.bin \
-       fip/bl30_new.bin \
-       bl30
+              fip/bl30.bin \
+              fip/zero_tmp \
+              fip/bl30_zero.bin \
+              fip/bl301.bin \
+              fip/bl301_zero.bin \
+              fip/bl30_new.bin \
+              bl30
 
     $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
 
     $ $FIPDIR/blx_fix.sh \
-       fip/bl2_acs.bin \
-       fip/zero_tmp \
-       fip/bl2_zero.bin \
-       fip/bl21.bin \
-       fip/bl21_zero.bin \
-       fip/bl2_new.bin \
-       bl2
+              fip/bl2_acs.bin \
+              fip/zero_tmp \
+              fip/bl2_zero.bin \
+              fip/bl21.bin \
+              fip/bl21_zero.bin \
+              fip/bl2_new.bin \
+              bl2
 
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
     $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
-               --output fip/u-boot.bin \
-               --bl2 fip/bl2.n.bin.sig \
-               --bl30 fip/bl30_new.bin.enc \
-               --bl31 fip/bl31.img.enc \
-               --bl33 fip/bl33.bin.enc
+                                  --output fip/u-boot.bin \
+                                  --bl2 fip/bl2.n.bin.sig \
+                                  --bl30 fip/bl30_new.bin.enc \
+                                  --bl31 fip/bl31.img.enc \
+                                  --bl33 fip/bl33.bin.enc
 
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
+    $ DEV=/dev/boot_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/radxa-zero.rst b/doc/board/amlogic/radxa-zero.rst
index f5611f5..14ce3cf 100644 (file)
--- a/doc/board/amlogic/radxa-zero.rst
+++ b/doc/board/amlogic/radxa-zero.rst
@@ -1,14 +1,13 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for Radxa Zero
-=====================
+U-Boot for Radxa Zero (S905Y2)
+==============================
 
-Radxa Zero is a small form factor SBC based on the Amlogic S905Y2
-chipset that ships in a number of RAM/eMMC configurations:
+Radxa Zero is a small form factor SBC based on the Amlogic S905Y2 chipset that ships in
+a number of RAM/eMMC configurations:
 
-Boards with 512MB/1GB LPDDR4 RAM have no eMMC storage and BCM43436
-wireless (2.4GHz b/g/n) while 2GB/4GB boards have 8/16/32/64/128GB
-eMMC storage and BCM4345 wireless (2.4/5GHz a/b/g/n/ac).
+512MB/1GB LPDDR4 RAM boards have no eMMC and BCM43436 wireless (2.4GHz b/g/n) while the
+2GB/4GB boards have 8/16/32/64/128GB eMMC and BCM4345 wireless (2.4/5GHz a/b/g/n/ac).
 
 - Amlogic S905Y2 quad-core Cortex-A53
 - Mali G31-MP2 GPU
@@ -18,11 +17,9 @@ eMMC storage and BCM4345 wireless (2.4/5GHz a/b/g/n/ac).
 - 1x micro SD Card slot
 - 40 Pin GPIO header
 
-Schematics are available on the manufacturer website:
+Schematics are available on the manufacturer website: https://dl.radxa.com/zero/docs/hw
 
-https://dl.radxa.com/zero/docs/hw/RADAX_ZERO_V13_SCH_20210309.pdf
-
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -31,14 +28,21 @@ U-Boot compilation
     $ make radxa-zero_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh radxa-zero /path/to/u-boot/u-boot.bin my-output-dir
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `radxa-zero`
+U-Boot Manual Signing
+---------------------
 
-Amlogic does not provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-git trees published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
 
 .. code-block:: bash
 
@@ -61,16 +65,16 @@ git trees published by the board vendor:
     $ cd ../fip/radxa-zero
     $ make
 
-This will generate:
+This will generate the signed U-Boot binaries:
 
 .. code-block:: bash
 
     $ u-boot.bin u-boot.bin.sd.bin u-boot.bin.usb.bl2 u-boot.bin.usb.tpl
 
-Then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
+    $ DEV=/dev/boot_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/radxa-zero2.rst b/doc/board/amlogic/radxa-zero2.rst
new file mode 100644 (file)
index 0000000..dccf592
--- /dev/null
+++ b/doc/board/amlogic/radxa-zero2.rst
@@ -0,0 +1,80 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Radxa Zero2 (A311D)
+==============================
+
+Radxa Zero2 is a small form factor SBC based on the Amlogic A311D chipset with the
+following specification:
+
+- Amlogic A311D (Quad A73 + Dual A53) CPU
+- 4GB LPDDR4 RAM
+- 32/64/128GB eMMC
+- Mali G52-MP4 GPU
+- HDMI 2.1 output (micro)
+- BCM4345 WiFi (2.4/5GHz a/b/g/n/ac) and BT 5.0
+- 1x USB 2.0 port - Type C (OTG)
+- 1x USB 3.0 port - Type C (Host)
+- 1x micro SD Card slot
+- 40 Pin GPIO header
+
+Schematics are available on request from Radxa.
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make radxa-zero2_defconfig
+    $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh radxa-zero2 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
+
+.. code-block:: bash
+
+    $ git clone -b radxa-zero-v2021.07 https://github.com/radxa/u-boot.git
+    $ git clone https://github.com/radxa/fip.git
+
+    $ sudo apt-get install -y gcc-aarch64-linux-gnu device-tree-compiler libncurses5 libncurses5-dev
+    $ sudo apt-get install -y bc python dosfstools flex build-essential libssl-dev mtools
+
+    $ wget https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz
+    $ sudo tar xvf gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz -C /opt
+
+    $ export CROSS_COMPILE=/opt/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf/bin/aarch64-none-elf-
+    $ export ARCH=arm
+    $ cd u-boot
+    $ make radxa-zero2_defconfig
+    $ make
+
+    $ cp u-boot.bin ../fip/radxa-zero2/bl33.bin
+    $ cd ../fip/radxa-zero2
+    $ make
+
+This will generate the signed U-Boot binaries:
+
+.. code-block:: bash
+
+    $ u-boot.bin u-boot.bin.sd.bin u-boot.bin.usb.bl2 u-boot.bin.usb.tpl
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/boot_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/s400.rst b/doc/board/amlogic/s400.rst
index c92817b..59dda82 100644 (file)
--- a/doc/board/amlogic/s400.rst
+++ b/doc/board/amlogic/s400.rst
@@ -1,15 +1,14 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for Amlogic S400
-=======================
+U-Boot for Amlogic S400 (A113X)
+===============================
 
-S400 is a reference board manufactured by Amlogic with the following
-specifications:
+S400 is a reference board manufactured by Amlogic with the following specifications:
 
- - Amlogic A113DX ARM Cortex-A53 quad-core SoC @ 1.2GHz
+ - Amlogic A113X ARM Cortex-A53 quad-core SoC @ 1.2GHz
  - 1GB DDR4 SDRAM
  - 10/100 Ethernet
- - 2 x USB 2.0 Host
+ - 2x USB 2.0 Host
  - eMMC
  - Infrared receiver
  - SDIO WiFi Module
@@ -19,7 +18,7 @@ specifications:
 
 Schematics are available from Amlogic on demand.
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -28,14 +27,21 @@ U-Boot compilation
     $ make s400_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `s400`
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh s400 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image but sources have been shared by Linux development contractor, Baylibre:
 
 .. code-block:: bash
 
@@ -65,47 +71,47 @@ Go back to mainline U-boot source tree then :
     $ cp u-boot.bin fip/bl33.bin
 
     $ $FIPDIR/blx_fix.sh \
-       fip/bl30.bin \
-       fip/zero_tmp \
-       fip/bl30_zero.bin \
-       fip/bl301.bin \
-       fip/bl301_zero.bin \
-       fip/bl30_new.bin \
-       bl30
+              fip/bl30.bin \
+              fip/zero_tmp \
+              fip/bl30_zero.bin \
+              fip/bl301.bin \
+              fip/bl301_zero.bin \
+              fip/bl30_new.bin \
+              bl30
 
     $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
 
     $ $FIPDIR/blx_fix.sh \
-       fip/bl2_acs.bin \
-       fip/zero_tmp \
-       fip/bl2_zero.bin \
-       fip/bl21.bin \
-       fip/bl21_zero.bin \
-       fip/bl2_new.bin \
-       bl2
+              fip/bl2_acs.bin \
+              fip/zero_tmp \
+              fip/bl2_zero.bin \
+              fip/bl21.bin \
+              fip/bl21_zero.bin \
+              fip/bl2_new.bin \
+              bl2
 
     $ $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl30_new.bin \
-                                       --output fip/bl30_new.bin.enc \
-                                       --level v3 --type bl30
+                                           --output fip/bl30_new.bin.enc \
+                                           --level v3 --type bl30
     $ $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl31.img \
-                                       --output fip/bl31.img.enc \
-                                       --level v3 --type bl31
+                                           --output fip/bl31.img.enc \
+                                           --level v3 --type bl31
     $ $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl33.bin --compress lz4 \
-                                       --output fip/bl33.bin.enc \
-                                       --level v3 --type bl33
+                                           --output fip/bl33.bin.enc \
+                                           --level v3 --type bl33
     $ $FIPDIR/axg/aml_encrypt_axg --bl2sig --input fip/bl2_new.bin \
-                                       --output fip/bl2.n.bin.sig
+                                           --output fip/bl2.n.bin.sig
     $ $FIPDIR/axg/aml_encrypt_axg --bootmk \
-               --output fip/u-boot.bin \
-               --bl2 fip/bl2.n.bin.sig \
-               --bl30 fip/bl30_new.bin.enc \
-               --bl31 fip/bl31.img.enc \
-               --bl33 fip/bl33.bin.enc --level v3
+                                  --output fip/u-boot.bin \
+                                  --bl2 fip/bl2.n.bin.sig \
+                                  --bl30 fip/bl30_new.bin.enc \
+                                  --bl31 fip/bl31.img.enc \
+                                  --bl33 fip/bl33.bin.enc --level v3
 
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
+    $ DEV=/dev/boot_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/sei510.rst b/doc/board/amlogic/sei510.rst
index c55e778..87cb701 100644 (file)
--- a/doc/board/amlogic/sei510.rst
+++ b/doc/board/amlogic/sei510.rst
@@ -1,21 +1,20 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for Amlogic SEI510
-=========================
+U-Boot for Amlogic SEI510 (S905X2)
+==================================
 
-SEI510 is a customer board manufactured by SEI Robotics with the following
-specifications:
+SEI510 is a customer board manufactured by SEI Robotics with the following specification:
 
  - Amlogic S905X2 ARM Cortex-A53 quad-core SoC
  - 2GB DDR4 SDRAM
  - 10/100 Ethernet (Internal PHY)
- - 1 x USB 3.0 Host
+ - 1x USB 3.0 Host
  - eMMC
  - SDcard
  - Infrared receiver
  - SDIO WiFi Module
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -24,14 +23,21 @@ U-Boot compilation
     $ make sei510_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `sei510`
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh sei510 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
 
 .. code-block:: bash
 
@@ -46,7 +52,7 @@ the git tree published by the board vendor:
     $ make
     $ export UBOOTDIR=$PWD
 
-Download the latest Amlogic Buildroot package, and extract it :
+Download the latest Amlogic Buildroot package and extract it:
 
 .. code-block:: bash
 
@@ -55,7 +61,7 @@ Download the latest Amlogic Buildroot package, and extract it :
     $ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
     $ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
 
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
 
 .. code-block:: bash
 
@@ -77,56 +83,56 @@ Go back to mainline U-Boot source tree then :
     $ cp u-boot.bin fip/bl33.bin
 
     $ sh fip/blx_fix.sh \
-       fip/bl30.bin \
-       fip/zero_tmp \
-       fip/bl30_zero.bin \
-       fip/bl301.bin \
-       fip/bl301_zero.bin \
-       fip/bl30_new.bin \
-       bl30
+         fip/bl30.bin \
+         fip/zero_tmp \
+         fip/bl30_zero.bin \
+         fip/bl301.bin \
+         fip/bl301_zero.bin \
+         fip/bl30_new.bin \
+         bl30
 
     $ sh fip/blx_fix.sh \
-       fip/bl2.bin \
-       fip/zero_tmp \
-       fip/bl2_zero.bin \
-       fip/acs.bin \
-       fip/bl21_zero.bin \
-       fip/bl2_new.bin \
-       bl2
+         fip/bl2.bin \
+         fip/zero_tmp \
+         fip/bl2_zero.bin \
+         fip/acs.bin \
+         fip/bl21_zero.bin \
+         fip/bl2_new.bin \
+         bl2
 
     $ $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
-                                       --output fip/bl30_new.bin.g12a.enc \
-                                       --level v3
+                                              --output fip/bl30_new.bin.g12a.enc \
+                                              --level v3
     $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
-                                       --output fip/bl30_new.bin.enc \
-                                       --level v3 --type bl30
+                                             --output fip/bl30_new.bin.enc \
+                                             --level v3 --type bl30
     $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
-                                       --output fip/bl31.img.enc \
-                                       --level v3 --type bl31
+                                             --output fip/bl31.img.enc \
+                                             --level v3 --type bl31
     $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
-                                       --output fip/bl33.bin.enc \
-                                       --level v3 --type bl33
+                                             --output fip/bl33.bin.enc \
+                                             --level v3 --type bl33
     $ $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
-                                       --output fip/bl2.n.bin.sig
+                                             --output fip/bl2.n.bin.sig
     $ $FIPDIR/g12a/aml_encrypt_g12a --bootmk \
-               --output fip/u-boot.bin \
-               --bl2 fip/bl2.n.bin.sig \
-               --bl30 fip/bl30_new.bin.enc \
-               --bl31 fip/bl31.img.enc \
-               --bl33 fip/bl33.bin.enc \
-               --ddrfw1 fip/ddr4_1d.fw \
-               --ddrfw2 fip/ddr4_2d.fw \
-               --ddrfw3 fip/ddr3_1d.fw \
-               --ddrfw4 fip/piei.fw \
-               --ddrfw5 fip/lpddr4_1d.fw \
-               --ddrfw6 fip/lpddr4_2d.fw \
-               --ddrfw7 fip/diag_lpddr4.fw \
-               --level v3
-
-and then write the image to SD with:
+                                    --output fip/u-boot.bin \
+                                    --bl2 fip/bl2.n.bin.sig \
+                                    --bl30 fip/bl30_new.bin.enc \
+                                    --bl31 fip/bl31.img.enc \
+                                    --bl33 fip/bl33.bin.enc \
+                                    --ddrfw1 fip/ddr4_1d.fw \
+                                    --ddrfw2 fip/ddr4_2d.fw \
+                                    --ddrfw3 fip/ddr3_1d.fw \
+                                    --ddrfw4 fip/piei.fw \
+                                    --ddrfw5 fip/lpddr4_1d.fw \
+                                    --ddrfw6 fip/lpddr4_2d.fw \
+                                    --ddrfw7 fip/diag_lpddr4.fw \
+                                    --level v3
+
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
+    $ DEV=/dev/boot_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/sei610.rst b/doc/board/amlogic/sei610.rst
index 2d75449..64f6257 100644 (file)
--- a/doc/board/amlogic/sei610.rst
+++ b/doc/board/amlogic/sei610.rst
@@ -1,23 +1,22 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for Amlogic SEI610
-=========================
+U-Boot for Amlogic SEI610 (S905X3)
+==================================
 
-SEI610 is a customer board manufactured by SEI Robotics with the following
-specifications:
+SEI610 is a customer board manufactured by SEI Robotics with the following specification:
 
  - Amlogic S905X3 ARM Cortex-A55 quad-core SoC
  - 2GB DDR4 SDRAM
  - 10/100 Ethernet (Internal PHY)
- - 1 x USB 3.0 Host
- - 1 x USB Type-C DRD
- - 1 x FTDI USB Serial Debug Interface
+ - 1x USB 3.0 Host
+ - 1x USB Type-C DRD
+ - 1x FTDI USB Serial Debug Interface
  - eMMC
  - SDcard
  - Infrared receiver
  - SDIO WiFi Module
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -26,14 +25,21 @@ U-Boot compilation
     $ make sei610_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `sei610`
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh sei610 /path/to/u-boot/u-boot.bin my-output-dir
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
 
 .. code-block:: bash
 
@@ -48,7 +54,7 @@ the git tree published by the board vendor:
     $ make
     $ export UBOOTDIR=$PWD
 
-Download the latest Amlogic Buildroot package, and extract it :
+Download the latest Amlogic buildroot package and extract it:
 
 .. code-block:: bash
 
@@ -57,8 +63,7 @@ Download the latest Amlogic Buildroot package, and extract it :
     $ export BRDIR=$PWD/buildroot-openlinux-A113-201901
     $ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
 
-Go back to mainline U-Boot source tree then :
-
+Go back to the mainline U-Boot source tree then:
 
 .. code-block:: bash
 
@@ -80,56 +85,56 @@ Go back to mainline U-Boot source tree then :
     $ cp u-boot.bin fip/bl33.bin
 
     $ sh fip/blx_fix.sh \
-       fip/bl30.bin \
-       fip/zero_tmp \
-       fip/bl30_zero.bin \
-       fip/bl301.bin \
-       fip/bl301_zero.bin \
-       fip/bl30_new.bin \
-       bl30
+         fip/bl30.bin \
+         fip/zero_tmp \
+         fip/bl30_zero.bin \
+         fip/bl301.bin \
+         fip/bl301_zero.bin \
+         fip/bl30_new.bin \
+         bl30
 
     $ sh fip/blx_fix.sh \
-       fip/bl2.bin \
-       fip/zero_tmp \
-       fip/bl2_zero.bin \
-       fip/acs.bin \
-       fip/bl21_zero.bin \
-       fip/bl2_new.bin \
-       bl2
+         fip/bl2.bin \
+         fip/zero_tmp \
+         fip/bl2_zero.bin \
+         fip/acs.bin \
+         fip/bl21_zero.bin \
+         fip/bl2_new.bin \
+         bl2
 
     $ $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
-                                       --output fip/bl30_new.bin.g12a.enc \
-                                       --level v3
+                                              --output fip/bl30_new.bin.g12a.enc \
+                                              --level v3
     $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
-                                       --output fip/bl30_new.bin.enc \
-                                       --level v3 --type bl30
+                                             --output fip/bl30_new.bin.enc \
+                                             --level v3 --type bl30
     $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
-                                       --output fip/bl31.img.enc \
-                                       --level v3 --type bl31
+                                             --output fip/bl31.img.enc \
+                                             --level v3 --type bl31
     $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
-                                       --output fip/bl33.bin.enc \
-                                       --level v3 --type bl33
+                                             --output fip/bl33.bin.enc \
+                                             --level v3 --type bl33
     $ $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
-                                       --output fip/bl2.n.bin.sig
+                                             --output fip/bl2.n.bin.sig
     $ $FIPDIR/g12a/aml_encrypt_g12a --bootmk \
-               --output fip/u-boot.bin \
-               --bl2 fip/bl2.n.bin.sig \
-               --bl30 fip/bl30_new.bin.enc \
-               --bl31 fip/bl31.img.enc \
-               --bl33 fip/bl33.bin.enc \
-               --ddrfw1 fip/ddr4_1d.fw \
-               --ddrfw2 fip/ddr4_2d.fw \
-               --ddrfw3 fip/ddr3_1d.fw \
-               --ddrfw4 fip/piei.fw \
-               --ddrfw5 fip/lpddr4_1d.fw \
-               --ddrfw6 fip/lpddr4_2d.fw \
-               --ddrfw7 fip/diag_lpddr4.fw \
-               --level v3
-
-and then write the image to SD with:
+                                    --output fip/u-boot.bin \
+                                    --bl2 fip/bl2.n.bin.sig \
+                                    --bl30 fip/bl30_new.bin.enc \
+                                    --bl31 fip/bl31.img.enc \
+                                    --bl33 fip/bl33.bin.enc \
+                                    --ddrfw1 fip/ddr4_1d.fw \
+                                    --ddrfw2 fip/ddr4_2d.fw \
+                                    --ddrfw3 fip/ddr3_1d.fw \
+                                    --ddrfw4 fip/piei.fw \
+                                    --ddrfw5 fip/lpddr4_1d.fw \
+                                    --ddrfw6 fip/lpddr4_2d.fw \
+                                    --ddrfw7 fip/diag_lpddr4.fw \
+                                    --level v3
+
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
+    $ DEV=/dev/boot_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/u200.rst b/doc/board/amlogic/u200.rst
index 53213fd..8254d4d 100644 (file)
--- a/doc/board/amlogic/u200.rst
+++ b/doc/board/amlogic/u200.rst
@@ -1,15 +1,14 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for Amlogic U200
-=======================
+U-Boot for Amlogic U200 (S905X2)
+================================
 
-U200 is a reference board manufactured by Amlogic with the following
-specifications:
+U200 is a reference board manufactured by Amlogic with the following specification:
 
  - Amlogic S905D2 ARM Cortex-A53 quad-core SoC
  - 2GB DDR4 SDRAM
  - 10/100 Ethernet (Internal PHY)
- - 1 x USB 3.0 Host
+ - 1x USB 3.0 Host
  - eMMC
  - SDcard
  - Infrared receiver
@@ -20,7 +19,7 @@ specifications:
 
 Schematics are available from Amlogic on demand.
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -29,14 +28,21 @@ U-Boot compilation
     $ make u200_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `u200`
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh u200 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
 
 .. code-block:: bash
 
@@ -51,7 +57,7 @@ the git tree published by the board vendor:
     $ make
     $ export UBOOTDIR=$PWD
 
-Download the latest Amlogic Buildroot package, and extract it :
+Download the latest Amlogic buildroot package and extract it:
 
 .. code-block:: bash
 
@@ -60,7 +66,7 @@ Download the latest Amlogic Buildroot package, and extract it :
     $ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
     $ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
 
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
 
 .. code-block:: bash
 
@@ -82,56 +88,56 @@ Go back to mainline U-Boot source tree then :
     $ cp u-boot.bin fip/bl33.bin
 
     $ sh fip/blx_fix.sh \
-       fip/bl30.bin \
-       fip/zero_tmp \
-       fip/bl30_zero.bin \
-       fip/bl301.bin \
-       fip/bl301_zero.bin \
-       fip/bl30_new.bin \
-       bl30
+         fip/bl30.bin \
+         fip/zero_tmp \
+         fip/bl30_zero.bin \
+         fip/bl301.bin \
+         fip/bl301_zero.bin \
+         fip/bl30_new.bin \
+         bl30
 
     $ sh fip/blx_fix.sh \
-       fip/bl2.bin \
-       fip/zero_tmp \
-       fip/bl2_zero.bin \
-       fip/acs.bin \
-       fip/bl21_zero.bin \
-       fip/bl2_new.bin \
-       bl2
+         fip/bl2.bin \
+         fip/zero_tmp \
+         fip/bl2_zero.bin \
+         fip/acs.bin \
+         fip/bl21_zero.bin \
+         fip/bl2_new.bin \
+         bl2
 
     $ $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
-                                       --output fip/bl30_new.bin.g12a.enc \
-                                       --level v3
+                                              --output fip/bl30_new.bin.g12a.enc \
+                                              --level v3
     $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
-                                       --output fip/bl30_new.bin.enc \
-                                       --level v3 --type bl30
+                                             --output fip/bl30_new.bin.enc \
+                                             --level v3 --type bl30
     $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
-                                       --output fip/bl31.img.enc \
-                                       --level v3 --type bl31
+                                             --output fip/bl31.img.enc \
+                                             --level v3 --type bl31
     $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
-                                       --output fip/bl33.bin.enc \
-                                       --level v3 --type bl33
+                                             --output fip/bl33.bin.enc \
+                                             --level v3 --type bl33
     $ $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
-                                       --output fip/bl2.n.bin.sig
+                                             --output fip/bl2.n.bin.sig
     $ $FIPDIR/g12a/aml_encrypt_g12a --bootmk \
-               --output fip/u-boot.bin \
-               --bl2 fip/bl2.n.bin.sig \
-               --bl30 fip/bl30_new.bin.enc \
-               --bl31 fip/bl31.img.enc \
-               --bl33 fip/bl33.bin.enc \
-               --ddrfw1 fip/ddr4_1d.fw \
-               --ddrfw2 fip/ddr4_2d.fw \
-               --ddrfw3 fip/ddr3_1d.fw \
-               --ddrfw4 fip/piei.fw \
-               --ddrfw5 fip/lpddr4_1d.fw \
-               --ddrfw6 fip/lpddr4_2d.fw \
-               --ddrfw7 fip/diag_lpddr4.fw \
-               --level v3
-
-and then write the image to SD with:
+                                    --output fip/u-boot.bin \
+                                    --bl2 fip/bl2.n.bin.sig \
+                                    --bl30 fip/bl30_new.bin.enc \
+                                    --bl31 fip/bl31.img.enc \
+                                    --bl33 fip/bl33.bin.enc \
+                                    --ddrfw1 fip/ddr4_1d.fw \
+                                    --ddrfw2 fip/ddr4_2d.fw \
+                                    --ddrfw3 fip/ddr3_1d.fw \
+                                    --ddrfw4 fip/piei.fw \
+                                    --ddrfw5 fip/lpddr4_1d.fw \
+                                    --ddrfw6 fip/lpddr4_2d.fw \
+                                    --ddrfw7 fip/diag_lpddr4.fw \
+                                    --level v3
+
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
+    $ DEV=/dev/boot_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/w400.rst b/doc/board/amlogic/w400.rst
index 38dbf52..d2a8107 100644 (file)
--- a/doc/board/amlogic/w400.rst
+++ b/doc/board/amlogic/w400.rst
@@ -1,15 +1,14 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for Amlogic W400
-=======================
+U-Boot for Amlogic W400 (S922X)
+===============================
 
-U200 is a reference board manufactured by Amlogic with the following
-specifications:
+W400 is a reference board manufactured by Amlogic with the following specification:
 
  - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
  - 2GB DDR4 SDRAM
  - 10/100 Ethernet (Internal PHY)
- - 1 x USB 3.0 Host
+ - 1x USB 3.0 Host
  - eMMC
  - SDcard
  - Infrared receiver
@@ -20,7 +19,7 @@ specifications:
 
 Schematics are available from Amlogic on demand.
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -29,12 +28,21 @@ U-Boot compilation
     $ make w400_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh jethub-j100 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
 
 .. code-block:: bash
 
@@ -49,7 +57,7 @@ the git tree published by the board vendor:
     $ make
     $ export UBOOTDIR=$PWD
 
-Download the latest Amlogic Buildroot package, and extract it :
+Download the latest Amlogic buildroot package and extract it:
 
 .. code-block:: bash
 
@@ -58,7 +66,7 @@ Download the latest Amlogic Buildroot package, and extract it :
     $ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
     $ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
 
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
 
 .. code-block:: bash
 
@@ -81,57 +89,57 @@ Go back to mainline U-Boot source tree then :
     $ cp u-boot.bin fip/bl33.bin
 
     $ sh fip/blx_fix.sh \
-       fip/bl30.bin \
-       fip/zero_tmp \
-       fip/bl30_zero.bin \
-       fip/bl301.bin \
-       fip/bl301_zero.bin \
-       fip/bl30_new.bin \
-       bl30
+         fip/bl30.bin \
+         fip/zero_tmp \
+         fip/bl30_zero.bin \
+         fip/bl301.bin \
+         fip/bl301_zero.bin \
+         fip/bl30_new.bin \
+         bl30
 
     $ sh fip/blx_fix.sh \
-       fip/bl2.bin \
-       fip/zero_tmp \
-       fip/bl2_zero.bin \
-       fip/acs.bin \
-       fip/bl21_zero.bin \
-       fip/bl2_new.bin \
-       bl2
+         fip/bl2.bin \
+         fip/zero_tmp \
+         fip/bl2_zero.bin \
+         fip/acs.bin \
+         fip/bl21_zero.bin \
+         fip/bl2_new.bin \
+         bl2
 
     $ $FIPDIR/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
-                                       --output fip/bl30_new.bin.g12a.enc \
-                                       --level v3
+                                              --output fip/bl30_new.bin.g12a.enc \
+                                              --level v3
     $ $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
-                                       --output fip/bl30_new.bin.enc \
-                                       --level v3 --type bl30
+                                             --output fip/bl30_new.bin.enc \
+                                             --level v3 --type bl30
     $ $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
-                                       --output fip/bl31.img.enc \
-                                       --level v3 --type bl31
+                                             --output fip/bl31.img.enc \
+                                             --level v3 --type bl31
     $ $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
-                                       --output fip/bl33.bin.enc \
-                                       --level v3 --type bl33
+                                             --output fip/bl33.bin.enc \
+                                             --level v3 --type bl33
     $ $FIPDIR/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
-                                       --output fip/bl2.n.bin.sig
+                                             --output fip/bl2.n.bin.sig
     $ $FIPDIR/g12b/aml_encrypt_g12b --bootmk \
-               --output fip/u-boot.bin \
-               --bl2 fip/bl2.n.bin.sig \
-               --bl30 fip/bl30_new.bin.enc \
-               --bl31 fip/bl31.img.enc \
-               --bl33 fip/bl33.bin.enc \
-               --ddrfw1 fip/ddr4_1d.fw \
-               --ddrfw2 fip/ddr4_2d.fw \
-               --ddrfw3 fip/ddr3_1d.fw \
-               --ddrfw4 fip/piei.fw \
-               --ddrfw5 fip/lpddr4_1d.fw \
-               --ddrfw6 fip/lpddr4_2d.fw \
-               --ddrfw7 fip/diag_lpddr4.fw \
-               --ddrfw8 fip/aml_ddr.fw \
-               --level v3
-
-and then write the image to SD with:
+                                    --output fip/u-boot.bin \
+                                    --bl2 fip/bl2.n.bin.sig \
+                                    --bl30 fip/bl30_new.bin.enc \
+                                    --bl31 fip/bl31.img.enc \
+                                    --bl33 fip/bl33.bin.enc \
+                                    --ddrfw1 fip/ddr4_1d.fw \
+                                    --ddrfw2 fip/ddr4_2d.fw \
+                                    --ddrfw3 fip/ddr3_1d.fw \
+                                    --ddrfw4 fip/piei.fw \
+                                    --ddrfw5 fip/lpddr4_1d.fw \
+                                    --ddrfw6 fip/lpddr4_2d.fw \
+                                    --ddrfw7 fip/diag_lpddr4.fw \
+                                    --ddrfw8 fip/aml_ddr.fw \
+                                    --level v3
+
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
+    $ DEV=/dev/boot_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/wetek-core2.rst b/doc/board/amlogic/wetek-core2.rst
index 0147d5f..137262e 100644 (file)
--- a/doc/board/amlogic/wetek-core2.rst
+++ b/doc/board/amlogic/wetek-core2.rst
@@ -1,23 +1,24 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-U-Boot for WeTek Core2
-======================
+U-Boot for WeTek Core2 (S912)
+=============================
 
-WeTek Core2 is an Android STB based on the Q200 reference design with
-the following specifications:
+WeTek Core2 is an Android STB based on the Q200 reference design with the following
+specifications:
 
  - Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz
  - ARM Mali T820 GPU
  - 3GB DDR4 SDRAM
  - 10/100 Realtek RTL8152 Ethernet (internal USB)
  - HDMI 2.0 4K/60Hz display
- - 2x USB 2.0 Host, 1x USB 2.0 OTG (internal)
+ - 2x USB 2.0 Host
+ - 1x USB 2.0 OTG (internal)
  - 32GB eMMC
  - microSD
  - SDIO Wifi Module, Bluetooth
  - Two channel IR receiver
 
-U-Boot compilation
+U-Boot Compilation
 ------------------
 
 .. code-block:: bash
@@ -26,15 +27,22 @@ U-Boot compilation
     $ make wetek-core2_defconfig
     $ make
 
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
 
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `wetek-core2`
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh wetek-core2 /path/to/u-boot/u-boot.bin my-output-dir
 
-Amlogic does not provide sources for the firmware or the tools needed
-to create the bootloader image, and WeTek has not publicly shared the
-precompiled FIP binaries. However the public Khadas VIM2 sources also
-work with the Core2 box so we can use the Khadas git tree:
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide firmware sources or tools needed to create the bootloader image
+and WeTek has not publicly shared the precompiled FIP binaries. However the Khadas VIM2
+sources also work with the Core2 box so we can use the Khadas git tree:
 
 .. code-block:: bash
 
@@ -49,7 +57,7 @@ work with the Core2 box so we can use the Khadas git tree:
     $ make
     $ export FIPDIR=$PWD/fip
 
-Go back to mainline U-Boot source tree then:
+Go back to the mainline U-Boot source tree then:
 
 .. code-block:: bash
 
@@ -61,38 +69,42 @@ Go back to mainline U-Boot source tree then:
     $ cp $FIPDIR/gxl/bl301.bin fip/
     $ cp $FIPDIR/gxl/bl31.img fip/
     $ cp u-boot.bin fip/bl33.bin
+
     $ $FIPDIR/blx_fix.sh \
-        fip/bl30.bin \
-        fip/zero_tmp \
-        fip/bl30_zero.bin \
-        fip/bl301.bin \
-        fip/bl301_zero.bin \
-        fip/bl30_new.bin \
-        bl30
+              fip/bl30.bin \
+              fip/zero_tmp \
+              fip/bl30_zero.bin \
+              fip/bl301.bin \
+              fip/bl301_zero.bin \
+              fip/bl30_new.bin \
+              bl30
+
     $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
     $ $FIPDIR/blx_fix.sh \
-        fip/bl2_acs.bin \
-        fip/zero_tmp \
-        fip/bl2_zero.bin \
-        fip/bl21.bin \
-        fip/bl21_zero.bin \
-        fip/bl2_new.bin \
-        bl2
+              fip/bl2_acs.bin \
+              fip/zero_tmp \
+              fip/bl2_zero.bin \
+              fip/bl21.bin \
+              fip/bl21_zero.bin \
+              fip/bl2_new.bin \
+              bl2
+
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
     $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
     $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
-        --output fip/u-boot.bin \
-        --bl2 fip/bl2.n.bin.sig \
-        --bl30 fip/bl30_new.bin.enc \
-        --bl31 fip/bl31.img.enc \
-        --bl33 fip/bl33.bin.enc
+                                  --output fip/u-boot.bin \
+                                  --bl2 fip/bl2.n.bin.sig \
+                                  --bl30 fip/bl30_new.bin.enc \
+                                  --bl31 fip/bl31.img.enc \
+                                  --bl33 fip/bl33.bin.enc
 
-then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
 
 .. code-block:: bash
 
-    $ DEV=/dev/your_sd_device
+    $ DEV=/dev/boot_device
     $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
-    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/wetek-hub.rst b/doc/board/amlogic/wetek-hub.rst
new file mode 100644 (file)
index 0000000..212f044
--- /dev/null
+++ b/doc/board/amlogic/wetek-hub.rst
@@ -0,0 +1,111 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for WeTek Hub (S905)
+===========================
+
+WeTek Hub is a small form-factor Android STB manufactured by WeTek with the following
+specification:
+
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
+ - ARM Mali 450 GPU
+ - 1GB DDR3 SDRAM
+ - 8GB eMMC
+ - Gigabit Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 1x USB otg
+ - microSD
+ - UART jack
+ - Infrared receiver
+
+Schematics are not publicly available but have been shared privately to maintainers.
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make wetek-hub_defconfig
+    $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh wetek-hub /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image and WeTek has not publicly shared the U-Boot sources needed to build FIP binaries
+for signing. However you can download them from the amlogic-fip-repo.
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip/wetek-hub
+    $ export FIPDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ cp $FIPDIR/bl2.bin fip/
+    $ cp $FIPDIR/acs.bin fip/
+    $ cp $FIPDIR/bl21.bin fip/
+    $ cp $FIPDIR/bl30.bin fip/
+    $ cp $FIPDIR/bl301.bin fip/
+    $ cp $FIPDIR/bl31.img fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ $FIPDIR/blx_fix.sh \
+              fip/bl30.bin \
+              fip/zero_tmp \
+              fip/bl30_zero.bin \
+              fip/bl301.bin \
+              fip/bl301_zero.bin \
+              fip/bl30_new.bin \
+              bl30
+
+    $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin \
+                         --bl31 fip/bl31.img \
+                         --bl33 fip/bl33.bin \
+                         fip/fip.bin
+
+    $ sed -i 's/\x73\x02\x08\x91/\x1F\x20\x03\xD5/' fip/bl2.bin
+    $ python3 $FIPDIR/acs_tool.py fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+    $ $FIPDIR/blx_fix.sh \
+              fip/bl2_acs.bin \
+              fip/zero_tmp \
+              fip/bl2_zero.bin \
+              fip/bl21.bin \
+              fip/bl21_zero.bin \
+              fip/bl2_new.bin \
+              bl2
+
+    $ cat fip/bl2_new.bin fip/fip.bin > fip/boot_new.bin
+
+    $ $FIPDIR/aml_encrypt_gxb --bootsig \
+                              --input fip/boot_new.bin
+                              --output fip/u-boot.bin
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/boot_device
+    $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 conv=fsync
+    $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 seek=9 skip=8 count=87 conv=fsync,notrunc
+    $ dd if=/dev/zero of=fip/u-boot.bin.gxbb bs=512 seek=8 count=1 conv=fsync,notrunc
+    $ dd if=bl1.bin.hardkernel of=fip/u-boot.bin.gxbb bs=512 seek=2 skip=2 count=1 conv=fsync,notrunc
+    $ ./aml_chksum fip/u-boot.bin.gxbb
+    $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/amlogic/wetek-play2.rst b/doc/board/amlogic/wetek-play2.rst
new file mode 100644 (file)
index 0000000..74580b9
--- /dev/null
+++ b/doc/board/amlogic/wetek-play2.rst
@@ -0,0 +1,116 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for WeTek Play2 (S905)
+=============================
+
+WeTek Play2 is an Android STB manufactured by WeTek with the following specification:
+
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - 8GB eMMC
+ - Gigabit Ethernet
+ - AP6335 (v1) or AP6255 (v2) WiFi (b/g/n) and BT 4.0
+ - HDMI 2.0 4K/60Hz display
+ - 2x USB 2.0 host
+ - 1x USB 2.0 otg
+ - microSD
+ - UART jack
+ - Infrared receiver
+ - Power LED (blue)
+ - Power button (case, front)
+ - Reset button (underside)
+ - DVB Card: DVB-S or DVB-T/C or ATSC
+
+Schematics are not publicly available but have been shared privately to maintainers.
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make wetek-play2_defconfig
+    $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip
+    $ mkdir my-output-dir
+    $ ./build-fip.sh wetek-play2 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image and WeTek has not publicly shared the U-Boot sources needed to build FIP binaries
+for signing. However you can download them from the amlogic-fip-repo.
+
+.. code-block:: bash
+
+    $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+    $ cd amlogic-boot-fip/wetek-play2
+    $ export FIPDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ cp $FIPDIR/bl2.bin fip/
+    $ cp $FIPDIR/acs.bin fip/
+    $ cp $FIPDIR/bl21.bin fip/
+    $ cp $FIPDIR/bl30.bin fip/
+    $ cp $FIPDIR/bl301.bin fip/
+    $ cp $FIPDIR/bl31.img fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ $FIPDIR/blx_fix.sh \
+              fip/bl30.bin \
+              fip/zero_tmp \
+              fip/bl30_zero.bin \
+              fip/bl301.bin \
+              fip/bl301_zero.bin \
+              fip/bl30_new.bin \
+              bl30
+
+    $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin \
+                         --bl31 fip/bl31.img \
+                         --bl33 fip/bl33.bin \
+                         fip/fip.bin
+
+    $ sed -i 's/\x73\x02\x08\x91/\x1F\x20\x03\xD5/' fip/bl2.bin
+    $ python3 $FIPDIR/acs_tool.py fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+    $ $FIPDIR/blx_fix.sh \
+              fip/bl2_acs.bin \
+              fip/zero_tmp \
+              fip/bl2_zero.bin \
+              fip/bl21.bin \
+              fip/bl21_zero.bin \
+              fip/bl2_new.bin \
+              bl2
+
+    $ cat fip/bl2_new.bin fip/fip.bin > fip/boot_new.bin
+
+    $ $FIPDIR/aml_encrypt_gxb --bootsig \
+                              --input fip/boot_new.bin
+                              --output fip/u-boot.bin
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/boot_device
+    $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 conv=fsync
+    $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 seek=9 skip=8 count=87 conv=fsync,notrunc
+    $ dd if=/dev/zero of=fip/u-boot.bin.gxbb bs=512 seek=8 count=1 conv=fsync,notrunc
+    $ dd if=bl1.bin.hardkernel of=fip/u-boot.bin.gxbb bs=512 seek=2 skip=2 count=1 conv=fsync,notrunc
+    $ ./aml_chksum fip/u-boot.bin.gxbb
+    $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=1 count=440

diff --git a/doc/board/beacon/beacon-imx8mp.rst b/doc/board/beacon/beacon-imx8mp.rst
new file mode 100644 (file)
index 0000000..375931c
--- /dev/null
+++ b/doc/board/beacon/beacon-imx8mp.rst
@@ -0,0 +1,52 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the Beacon EmbeddedWorks i.MX8M Plus Devkit
+======================================================
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get DDR firmware
+- Build U-Boot
+- Burn U-Noot to microSD Card
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone https://github.com/nxp-imx/imx-atf.git -b v2.6
+    $ make PLAT=imx8mp bl31 CROSS_COMPILE=aarch64-linux-gnu-
+    $ cp build/imx8mn/release/bl31.bin ../
+
+Get the DDR firmware
+--------------------
+
+.. code-block:: bash
+
+    $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.15.bin
+    $ chmod +x firmware-imx-8.15.bin
+    $ ./firmware-imx-8.15
+    $ cp firmware-imx-8.15/firmware/ddr/synopsys/lpddr4*.bin .
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+    $ make imx8mp_beacon_defconfig
+    $ make CROSS_COMPILE=aarch64-linux-gnu-
+
+Burn U-Boot to microSD Card
+---------------------------
+
+.. code-block:: bash
+
+    $ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32
+
+Boot
+----
+Set baseboard DIP switch:
+S17: 1100XXXX

diff --git a/doc/board/beacon/index.rst b/doc/board/beacon/index.rst
new file mode 100644 (file)
index 0000000..1fe1046
--- /dev/null
+++ b/doc/board/beacon/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Beacon
+======
+
+.. toctree::
+   :maxdepth: 2
+
+   beacon-imx8mp

diff --git a/doc/board/index.rst b/doc/board/index.rst
index 618d22e..b2da6ec 100644 (file)
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -14,6 +14,7 @@ Board-specific doc
    apple/index
    armltd/index
    atmel/index
+   beacon/index
    broadcom/index
    bsh/index
    cloos/index
@@ -39,6 +40,7 @@ Board-specific doc
    sipeed/index
    socionext/index
    st/index
+   starfive/index
    ste/index
    tbs/index
    ti/index

diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index b5563b8..1dccb17 100644 (file)
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -91,6 +91,7 @@ List of mainline supported Rockchip boards:
      - Rockchip Evb-RK3568 (evb-rk3568)
 
 * rk3588
+     - Rockchip EVB (evb-rk3588)
      - Edgeble Neural Compute Module 6 SoM - Neu6a (neu6a-io-rk3588)
      - Radxa ROCK 5B (rock5b-rk3588)
 
@@ -185,6 +186,15 @@ To build rk3568 boards:
         make evb-rk3568_defconfig
         make CROSS_COMPILE=aarch64-linux-gnu-
 
+To build rk3588 boards:
+
+.. code-block:: bash
+
+        export BL31=../rkbin/bin/rk35/rk3588_bl31_v1.33.elf
+        export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.09.bin
+        make evb-rk3588_defconfig
+        make CROSS_COMPILE=aarch64-linux-gnu-
+
 Flashing
 --------
 
@@ -380,9 +390,8 @@ Program with commands in a bash script ./flash.sh:
 
         #!/bin/sh
 
-        printf "RK30" > tplspl.bin
-        dd if=u-boot-tpl.bin >> tplspl.bin
-        truncate -s %2048 tplspl.bin
+        printf "RK30" | dd conv=notrunc bs=4 count=1 of=u-boot-tpl.bin
+        truncate -s %2048 u-boot-tpl.bin
         truncate -s %2048 u-boot-spl.bin
         ../tools/boot_merger --verbose config-flash.ini
         ../tools/upgrade_tool ul ./RK30xxLoader_uboot.bin
@@ -406,7 +415,7 @@ config-flash.ini:
         NUM=2
         LOADER1=FlashData
         LOADER2=FlashBoot
-        FlashData=tplspl.bin
+        FlashData=u-boot-tpl.bin
         FlashBoot=u-boot-spl.bin
         [OUTPUT]
         PATH=RK30xxLoader_uboot.bin

diff --git a/doc/board/starfive/index.rst b/doc/board/starfive/index.rst
new file mode 100644 (file)
index 0000000..0c52dc7
--- /dev/null
+++ b/doc/board/starfive/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+StarFive
+========
+
+.. toctree::
+   :maxdepth: 1
+
+   visionfive2

diff --git a/doc/board/starfive/visionfive2.rst b/doc/board/starfive/visionfive2.rst
new file mode 100644 (file)
index 0000000..22d2a31
--- /dev/null
+++ b/doc/board/starfive/visionfive2.rst
@@ -0,0 +1,492 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+StarFive VisionFive2
+====================
+
+JH7110 RISC-V SoC
+---------------------
+The JH7110 is 4+1 64-bit RISC-V SoC from StarFive.
+
+The StarFive VisionFive2 development platform is based on JH7110 and capable
+of running Linux.
+
+Mainline support
+----------------
+
+The support for following drivers are already enabled:
+
+1. ns16550 UART Driver.
+2. StarFive JH7110 clock Driver.
+3. StarFive JH7110 reset Driver.
+4. Cadence QSPI controller Driver.
+5. MMC SPI Driver for MMC/SD support.
+
+Booting from MMC using U-Boot SPL
+---------------------------------
+
+The current U-Boot port is supported in S-mode only and loaded from DRAM.
+
+A prior stage M-mode firmware/bootloader (e.g OpenSBI) is required to
+boot the u-boot.itb in S-mode and provide M-mode runtime services.
+
+Currently, the u-boot.itb is used as a dynamic of the OpenSBI FW_DYNAMIC
+firmware with the latest.
+
+Building
+~~~~~~~~
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+   export CROSS_COMPILE=<riscv64 toolchain prefix>
+
+Before building U-Boot SPL, OpenSBI must be built first. OpenSBI can be
+cloned and built for JH7110 as below:
+
+.. code-block:: console
+
+       git clone https://github.com/riscv/opensbi.git
+       cd opensbi
+       make PLATFORM=generic FW_TEXT_START=0x40000000 FW_OPTIONS=0
+
+More detailed description of steps required to build FW_DYNAMIC firmware
+is beyond the scope of this document. Please refer OpenSBI documenation.
+(Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git)
+
+Now build the U-Boot SPL and U-Boot proper
+
+.. code-block:: console
+
+       cd <U-Boot-dir>
+       make starfive_visionfive2_13b_defconfig
+       make OPENSBI=$(opensbi_dir)/opensbi/build/platform/generic/firmware/fw_dynamic.bin
+
+This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
+
+u-boot-spl.bin cannot be used directly on StarFive VisionFive2,we need
+to convert the u-boot-spl.bin to u-boot-spl.bin.normal.out with
+the below command:
+
+       ./spl_tool -c -f $(Uboot_PATH)/spl/u-boot-spl.bin
+
+More detailed description of spl_tool,please refer spl_tool documenation.
+(Note: spl_tool git repo is at https://github.com/starfive-tech/Tools/tree/master/spl_tool)
+
+This will generate u-boot-spl.bin.normal.out file.
+
+Flashing
+~~~~~~~~
+
+SPL loads the U-Boot SPL (u-boot-spl.bin.normal.out) from a partition with GUID type
+2E54B353-1271-4842-806F-E436D6AF6985
+
+U-Boot SPL expects a U-Boot FIT image (u-boot.itb) from a partition with GUID
+type BC13C2FF-59E6-4262-A352-B275FD6F7172
+
+FIT image (u-boot.itb) is a combination of fw_dynamic.bin, u-boot-nodtb.bin and
+device tree blob (jh7110-starfive-visionfive-2-v1.3b.dtb/jh7110-starfive-visionfive-2-v1.2a.dtb)
+
+Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch)
+
+.. code-block:: bash
+
+       sudo sgdisk --clear \
+         --set-alignment=2 \
+         --new=1:4096:8191 --change-name=1:spl --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985\
+         --new=2:8192:16383 --change-name=2:uboot --typecode=2:BC13C2FF-59E6-4262-A352-B275FD6F7172  \
+         --new=3:16384:1654784 --change-name=3:system --typecode=3:EBD0A0A2-B9E5-4433-87C0-68B6B72699C7 \
+         /dev/sdb
+
+Program the SD card
+
+.. code-block:: bash
+
+       sudo dd if=u-boot-spl.bin.normal.out of=/dev/sdb1
+       sudo dd if=u-boot.itb of=/dev/sdb2
+
+       sudo mount /dev/sdb3 /mnt/
+       sudo cp u-boot-spl.bin.normal.out /mnt/
+       sudo cp u-boot.itb /mnt/
+       sudo cp Image.gz /mnt/
+       sudo cp initramfs.cpio.gz /mnt/
+       sudo cp jh7110-starfive-visionfive-2-v1.3b.dtb /mnt/
+       sudo umount /mnt
+
+Booting
+~~~~~~~
+
+Change DIP switches MSEL[1:0] are set to 10, select the boot mode to SD.
+Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+
+Sample boot log from StarFive VisionFive2 board
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. code-block:: none
+
+
+       U-Boot SPL 2023.04-rc2-00055-gfc43b9c51a-dirty (Mar 02 2023 - 10:51:39 +0800)
+       DDR version: dc2e84f0.
+       Trying to boot from MMC2
+
+       OpenSBI v1.2-80-g4b28afc
+       ____                    _____ ____ _____
+       / __ \                  / ____|  _ \_   _|
+       | |  | |_ __   ___ _ __ | (___ | |_) || |
+       | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
+       | |__| | |_) |  __/ | | |____) | |_) || |_
+       \____/| .__/ \___|_| |_|_____/|___/_____|
+                       | |
+                       |_|
+
+       Platform Name             : StarFive VisionFive 2 v1.3B
+       Platform Features         : medeleg
+       Platform HART Count       : 5
+       Platform IPI Device       : aclint-mswi
+       Platform Timer Device     : aclint-mtimer @ 4000000Hz
+       Platform Console Device   : uart8250
+       Platform HSM Device       : ---
+       Platform PMU Device       : ---
+       Platform Reboot Device    : ---
+       Platform Shutdown Device  : ---
+       Platform Suspend Device   : ---
+       Firmware Base             : 0x40000000
+       Firmware Size             : 264 KB
+       Firmware RW Offset        : 0x20000
+       Runtime SBI Version       : 1.0
+
+       Domain0 Name              : root
+       Domain0 Boot HART         : 2
+       Domain0 HARTs             : 0*,1*,2*,3*,4*
+       Domain0 Region00          : 0x0000000002000000-0x000000000200ffff M: (I,R,W) S/U: ()
+       Domain0 Region01          : 0x0000000040000000-0x000000004001ffff M: (R,X) S/U: ()
+       Domain0 Region02          : 0x0000000040000000-0x000000004007ffff M: (R,W) S/U: ()
+       Domain0 Region03          : 0x0000000000000000-0xffffffffffffffff M: (R,W,X) S/U: (R,W,X)
+       Domain0 Next Address      : 0x0000000040200000
+       Domain0 Next Arg1         : 0x0000000040287970
+       Domain0 Next Mode         : S-mode
+       Domain0 SysReset          : yes
+       Domain0 SysSuspend        : yes
+
+       Boot HART ID              : 2
+       Boot HART Domain          : root
+       Boot HART Priv Version    : v1.11
+       Boot HART Base ISA        : rv64imafdcbx
+       Boot HART ISA Extensions  : none
+       Boot HART PMP Count       : 8
+       Boot HART PMP Granularity : 4096
+       Boot HART PMP Address Bits: 34
+       Boot HART MHPM Count      : 2
+       Boot HART MIDELEG         : 0x0000000000000222
+       Boot HART MEDELEG         : 0x000000000000b109
+
+
+       U-Boot 2023.04-rc2-00055-gfc43b9c51a-dirty (Mar 02 2023 - 10:51:39 +0800)
+
+       CPU:   rv64imac_zba_zbb
+       Model: StarFive VisionFive 2 v1.3B
+       DRAM:  8 GiB
+       Core:  107 devices, 18 uclasses, devicetree: separate
+       MMC:   mmc@16010000: 0, mmc@16020000: 1
+       Loading Environment from nowhere... OK
+       In:    serial@10000000
+       Out:   serial@10000000
+       Err:   serial@10000000
+       Net:   No ethernet found.
+       Working FDT set to ff74a340
+       Hit any key to stop autoboot:  0
+       StarFive #
+       StarFive #version
+       U-Boot 2023.04-rc2-00055-gfc43b9c51a-dirty (Mar 02 2023 - 10:51:39 +0800)
+
+       riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot VF2_515_v1.0.0_rc4) 10.3.0
+       GNU ld (GNU Binutils) 2.36.1
+       StarFive #
+       StarFive #mmc dev 1
+       switch to partitions #0, OK
+       mmc1 is current device
+       StarFive #mmc info
+       Device: mmc@16020000
+       Manufacturer ID: 9f
+       OEM: 5449
+       Name: SD64G
+       Bus Speed: 50000000
+       Mode: SD High Speed (50MHz)
+       Rd Block Len: 512
+       SD version 3.0
+       High Capacity: Yes
+       Capacity: 58.3 GiB
+       Bus Width: 4-bit
+       Erase Group Size: 512 Bytes
+       StarFive #
+       StarFive #mmc part
+
+       Partition Map for MMC device 1  --   Partition Type: EFI
+
+       Part    Start LBA       End LBA         Name
+                       Attributes
+                       Type GUID
+                       Partition GUID
+       1     0x00001000      0x00001fff      "spl"
+                       attrs:  0x0000000000000000
+                       type:   2e54b353-1271-4842-806f-e436d6af6985
+                                       (2e54b353-1271-4842-806f-e436d6af6985)
+                       guid:   d5ee2056-3020-475b-9a33-25b4257c9f12
+       2     0x00002000      0x00003fff      "uboot"
+                       attrs:  0x0000000000000000
+                       type:   bc13c2ff-59e6-4262-a352-b275fd6f7172
+                                       (bc13c2ff-59e6-4262-a352-b275fd6f7172)
+                       guid:   379ab7fe-fd0c-4149-b758-960c1cbfc0cc
+       3     0x00004000      0x00194000      "system"
+                       attrs:  0x0000000000000000
+                       type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
+                                       (data)
+                       guid:   539a6df9-4655-4953-8541-733ca36eb1db
+       StarFive #
+       StarFive #fatls mmc 1:3
+       6429424   Image.gz
+       717705   u-boot.itb
+       125437   u-boot-spl.bin.normal.out
+       152848495   initramfs.cpio.gz
+               11285   jh7110-starfive-visionfive-2-v1.3b.dtb
+
+       5 file(s), 0 dir(s)
+
+       StarFive #fatload mmc 1:3 ${kernel_addr_r} Image.gz
+       6429424 bytes read in 394 ms (15.6 MiB/s)
+       StarFive #fatload mmc 1:3 ${fdt_addr_r} jh7110-starfive-visionfive-2-v1.3b.dtb
+       11285 bytes read in 5 ms (2.2 MiB/s)
+       StarFive #fatload mmc 1:3 ${ramdisk_addr_r} initramfs.cpio.gz
+       152848495 bytes read in 9271 ms (15.7 MiB/s)
+       StarFive #booti ${kernel_addr_r} ${ramdisk_addr_r}:${filesize} ${fdt_addr_r}
+       Uncompressing Kernel Image
+       ## Flattened Device Tree blob at 46000000
+       Booting using the fdt blob at 0x46000000
+       Working FDT set to 46000000
+       Loading Ramdisk to f5579000, end fe73d86f ... OK
+       Loading Device Tree to 00000000f5573000, end 00000000f5578c14 ... OK
+       Working FDT set to f5573000
+
+       Starting kernel ...
+
+
+       ] Linux version 6.2.0-starfive-00026-g11934a315b67 (wyh@wyh-VirtualBox) (riscv64-linux-gnu-gcc (Ubuntu 7.5.0-3ubuntu1~18.04) 7.5.0, GNU ld (GNU Binutils for Ubuntu) 2.30) #1 SMP Thu Mar  2 14:51:36 CST 2023
+       [    0.000000] OF: fdt: Ignoring memory range 0x40000000 - 0x40200000
+       [    0.000000] Machine model: StarFive VisionFive 2 v1.3B
+       [    0.000000] efi: UEFI not found.
+       [    0.000000] Zone ranges:
+       [    0.000000]   DMA32    [mem 0x0000000040200000-0x00000000ffffffff]
+       [    0.000000]   Normal   [mem 0x0000000100000000-0x000000013fffffff]
+       [    0.000000] Movable zone start for each node
+       [    0.000000] Early memory node ranges
+       [    0.000000]   node   0: [mem 0x0000000040200000-0x000000013fffffff]
+       [    0.000000] Initmem setup node 0 [mem 0x0000000040200000-0x000000013fffffff]
+       [    0.000000] On node 0, zone DMA32: 512 pages in unavailable ranges
+       [    0.000000] SBI specification v1.0 detected
+       [    0.000000] SBI implementation ID=0x1 Version=0x10002
+       [    0.000000] SBI TIME extension detected
+       [    0.000000] SBI IPI extension detected
+       [    0.000000] SBI RFENCE extension detected
+       [    0.000000] SBI HSM extension detected
+       [    0.000000] CPU with hartid=0 is not available
+       [    0.000000] CPU with hartid=0 is not available
+       [    0.000000] CPU with hartid=0 is not available
+       [    0.000000] riscv: base ISA extensions acdfim
+       [    0.000000] riscv: ELF capabilities acdfim
+       [    0.000000] percpu: Embedded 18 pages/cpu s35960 r8192 d29576 u73728
+       [    0.000000] pcpu-alloc: s35960 r8192 d29576 u73728 alloc=18*4096
+       [    0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
+       [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 1031688
+       [    0.000000] Kernel command line: console=ttyS0,115200 debug rootwait earlycon=sbi
+       [    0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
+       [    0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
+       [    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
+       [    0.000000] software IO TLB: area num 4.
+       [    0.000000] software IO TLB: mapped [mem 0x00000000f1573000-0x00000000f5573000] (64MB)
+       [    0.000000] Virtual kernel memory layout:
+       [    0.000000]       fixmap : 0xffffffc6fee00000 - 0xffffffc6ff000000   (2048 kB)
+       [    0.000000]       pci io : 0xffffffc6ff000000 - 0xffffffc700000000   (  16 MB)
+       [    0.000000]      vmemmap : 0xffffffc700000000 - 0xffffffc800000000   (4096 MB)
+       [    0.000000]      vmalloc : 0xffffffc800000000 - 0xffffffd800000000   (  64 GB)
+       [    0.000000]      modules : 0xffffffff0136a000 - 0xffffffff80000000   (2028 MB)
+       [    0.000000]       lowmem : 0xffffffd800000000 - 0xffffffd8ffe00000   (4094 MB)
+       [    0.000000]       kernel : 0xffffffff80000000 - 0xffffffffffffffff   (2047 MB)
+       [    0.000000] Memory: 3867604K/4192256K available (8012K kernel code, 4919K rwdata, 4096K rodata, 2190K init, 476K bss, 324652K reserved, 0K cma-reserved)
+       [    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+       [    0.000000] rcu: Hierarchical RCU implementation.
+       [    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=4.
+       [    0.000000] rcu:     RCU debug extended QS entry/exit.
+       [    0.000000]  Tracing variant of Tasks RCU enabled.
+       [    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
+       [    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
+       [    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
+       [    0.000000] CPU with hartid=0 is not available
+       [    0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt-controller
+       [    0.000000] riscv-intc: 64 local interrupts mapped
+       [    0.000000] plic: interrupt-controller@c000000: mapped 136 interrupts with 4 handlers for 9 contexts.
+       [    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
+       [    0.000000] riscv-timer: riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [4]
+       [    0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 881590404240 ns
+       [    0.000003] sched_clock: 64 bits at 4MHz, resolution 250ns, wraps every 2199023255500ns
+       [    0.000437] Console: colour dummy device 80x25
+       [    0.000568] Calibrating delay loop (skipped), value calculated using timer frequency.. 8.00 BogoMIPS (lpj=16000)
+       [    0.000602] pid_max: default: 32768 minimum: 301
+       [    0.000752] LSM: initializing lsm=capability,integrity
+       [    0.001071] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
+       [    0.001189] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
+       [    0.004201] CPU node for /cpus/cpu@0 exist but the possible cpu range is :0-3
+       [    0.007426] cblist_init_generic: Setting adjustable number of callback queues.
+       [    0.007457] cblist_init_generic: Setting shift to 2 and lim to 1.
+       [    0.007875] riscv: ELF compat mode unsupported
+       [    0.007902] ASID allocator disabled (0 bits)
+       [    0.008405] rcu: Hierarchical SRCU implementation.
+       [    0.008426] rcu:     Max phase no-delay instances is 1000.
+       [    0.009247] EFI services will not be available.
+       [    0.010738] smp: Bringing up secondary CPUs ...
+       [    0.018358] smp: Brought up 1 node, 4 CPUs
+       [    0.021776] devtmpfs: initialized
+       [    0.027337] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
+       [    0.027389] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
+       [    0.027888] pinctrl core: initialized pinctrl subsystem
+       [    0.029881] NET: Registered PF_NETLINK/PF_ROUTE protocol family
+       [    0.030401] audit: initializing netlink subsys (disabled)
+       [    0.031041] audit: type=2000 audit(0.028:1): state=initialized audit_enabled=0 res=1
+       [    0.031943] cpuidle: using governor menu
+       [    0.043011] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
+       [    0.043033] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
+       [    0.044943] iommu: Default domain type: Translated
+       [    0.044965] iommu: DMA domain TLB invalidation policy: strict mode
+       [    0.046089] SCSI subsystem initialized
+       [    0.046733] libata version 3.00 loaded.
+       [    0.047231] usbcore: registered new interface driver usbfs
+       [    0.047315] usbcore: registered new interface driver hub
+       [    0.047420] usbcore: registered new device driver usb
+       [    0.049770] vgaarb: loaded
+       [    0.050277] clocksource: Switched to clocksource riscv_clocksource
+       [    0.084690] NET: Registered PF_INET protocol family
+       [    0.085561] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
+       [    0.093010] tcp_listen_portaddr_hash hash table entries: 2048 (order: 4, 65536 bytes, linear)
+       [    0.093152] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
+       [    0.093224] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
+       [    0.093821] TCP bind hash table entries: 32768 (order: 9, 2097152 bytes, linear)
+       [    0.117880] TCP: Hash tables configured (established 32768 bind 32768)
+       [    0.118500] UDP hash table entries: 2048 (order: 5, 196608 bytes, linear)
+       [    0.118881] UDP-Lite hash table entries: 2048 (order: 5, 196608 bytes, linear)
+       [    0.119675] NET: Registered PF_UNIX/PF_LOCAL protocol family
+       [    0.121749] RPC: Registered named UNIX socket transport module.
+       [    0.121776] RPC: Registered udp transport module.
+       [    0.121784] RPC: Registered tcp transport module.
+       [    0.121791] RPC: Registered tcp NFSv4.1 backchannel transport module.
+       [    0.121816] PCI: CLS 0 bytes, default 64
+       [    0.124101] Unpacking initramfs...
+       [    0.125468] workingset: timestamp_bits=46 max_order=20 bucket_order=0
+       [    0.128372] NFS: Registering the id_resolver key type
+       [    0.128498] Key type id_resolver registered
+       [    0.128525] Key type id_legacy registered
+       [    0.128625] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
+       [    0.128649] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
+       [    0.129358] 9p: Installing v9fs 9p2000 file system support
+       [    0.130179] NET: Registered PF_ALG protocol family
+       [    0.130499] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247)
+       [    0.130544] io scheduler mq-deadline registered
+       [    0.130556] io scheduler kyber registered
+       [    0.416754] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+       [    0.420857] SuperH (H)SCI(F) driver initialized
+       [    0.443735] loop: module loaded
+       [    0.448605] e1000e: Intel(R) PRO/1000 Network Driver
+       [    0.448627] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
+       [    0.450716] usbcore: registered new interface driver uas
+       [    0.450832] usbcore: registered new interface driver usb-storage
+       [    0.451638] mousedev: PS/2 mouse device common for all mice
+       [    0.453465] sdhci: Secure Digital Host Controller Interface driver
+       [    0.453487] sdhci: Copyright(c) Pierre Ossman
+       [    0.453584] sdhci-pltfm: SDHCI platform and OF driver helper
+       [    0.454140] usbcore: registered new interface driver usbhid
+       [    0.454174] usbhid: USB HID core driver
+       [    0.454833] riscv-pmu-sbi: SBI PMU extension is available
+       [    0.454920] riscv-pmu-sbi: 16 firmware and 4 hardware counters
+       [    0.454942] riscv-pmu-sbi: Perf sampling/filtering is not supported as sscof extension is not available
+       [    0.457071] NET: Registered PF_INET6 protocol family
+       [    0.460627] Segment Routing with IPv6
+       [    0.460821] In-situ OAM (IOAM) with IPv6
+       [    0.461005] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
+       [    0.462712] NET: Registered PF_PACKET protocol family
+       [    0.462933] 9pnet: Installing 9P2000 support
+       [    0.463141] Key type dns_resolver registered
+       [    0.463168] start plist test
+       [    0.469261] end plist test
+       [    0.506774] debug_vm_pgtable: [debug_vm_pgtable         ]: Validating architecture page table helpers
+       [    0.553683] gpio gpiochip0: Static allocation of GPIO base is deprecated, use dynamic allocation.
+       [    0.554741] starfive-jh7110-sys-pinctrl 13040000.pinctrl: StarFive GPIO chip registered 64 GPIOs
+       [    0.555900] gpio gpiochip1: Static allocation of GPIO base is deprecated, use dynamic allocation.
+       [    0.556772] starfive-jh7110-aon-pinctrl 17020000.pinctrl: StarFive GPIO chip registered 4 GPIOs
+       [    0.559454] printk: console [ttyS0] disabled
+       [    0.579948] 10000000.serial: ttyS0 at MMIO 0x10000000 (irq = 3, base_baud = 1500000) is a 16550A
+       [    0.580082] printk: console [ttyS0] enabled
+       [   13.642680] Freeing initrd memory: 149264K
+       [   13.651051] Freeing unused kernel image (initmem) memory: 2188K
+       [   13.666431] Run /init as init process
+       [   13.670116]   with arguments:
+       [   13.673168]     /init
+       [   13.675488]   with environment:
+       [   13.678668]     HOME=/
+       [   13.681038]     TERM=linux
+       Starting syslogd: OK
+       Starting klogd: OK
+       Running sysctl: OK
+       Populating /dev using udev: [   14.145944] udevd[93]: starting version 3.2.10
+       [   15.214287] random: crng init done
+       [   15.240816] udevd[94]: starting eudev-3.2.10
+       done
+       Saving random seed: OK
+       Starting system message bus: dbus[122]: Unknown username "pulse" in message bus configuration file
+       done
+       Starting rpcbind: OK
+       Starting iptables: OK
+       Starting bluetoothd: OK
+       Starting network: Waiting for interface eth0 to appear............... timeout!
+       run-parts: /etc/network/if-pre-up.d/wait_iface: exit status 1
+       FAIL
+       Starting dropbear sshd: OK
+       Starting NFS statd: OK
+       Starting NFS services: OK
+       Starting NFS daemon: rpc.nfsd: Unable to access /proc/fs/nfsd errno 2 (No such file or directory).
+       Please try, as root, 'mount -t nfsd nfsd /proc/fs/nfsd' and then restart rpc.nfsd to correct the problem
+       FAIL
+       Starting NFS mountd: OK
+       Starting DHCP server: FAIL
+
+       Welcome to Buildroot
+       buildroot login:
+
+Booting from SPI
+----------------
+
+Use Building steps from "Booting from MMC using U-Boot SPL" section.
+
+Partition the SPI in Linux via mtdblock. (Require to boot the board in
+SD boot mode by enabling MTD block in Linux)
+
+Use prebuilt image from here [1], which support to partition the SPI flash.
+
+
+Program the SPI (Require to boot the board in SD boot mode)
+
+Execute below steps on U-Boot proper,
+
+.. code-block:: none
+
+  sf probe
+  fatload mmc 1:3 $kernel_addr_r u-boot.itb
+  sf update $kernel_addr_r 0x100000 $filesize
+
+  fatload mmc 1:3 $kernel_addr_r u-boot-spl.bin.normal.out
+  sf update $kernel_addr_r 0x0 $filesize
+
+
+Power off the board
+
+Change DIP switches MSEL[1:0] are set to 00, select the boot mode to flash
+
+Power up the board.

diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst
index b1b7d99..27d7b52 100644 (file)
--- a/doc/board/ti/am62x_sk.rst
+++ b/doc/board/ti/am62x_sk.rst
@@ -229,3 +229,28 @@ Image formats:
                 | |   SPL DTB 1...N   | |
                 | +-------------------+ |
                 +-----------------------+
+
+Switch Setting for Boot Mode
+----------------------------
+
+Boot Mode pins provide means to select the boot mode and options before the
+device is powered up. After every POR, they are the main source to populate
+the Boot Parameter Tables.
+
+The following table shows some common boot modes used on AM62 platform. More
+details can be found in the Technical Reference Manual:
+https://www.ti.com/lit/pdf/spruiv7 under the `Boot Mode Pins` section.
+
+*Boot Modes*
+
+============ ============= =============
+Switch Label SW2: 12345678 SW3: 12345678
+============ ============= =============
+SD           01000000      11000010
+OSPI         00000000      11001110
+EMMC         00000000      11010010
+UART         00000000      11011100
+USB DFU      00000000      11001010
+============ ============= =============
+
+For SW2 and SW1, the switch state in the "ON" position = 1.

diff --git a/doc/build/documentation.rst b/doc/build/documentation.rst
index 896264d..011cd34 100644 (file)
--- a/doc/build/documentation.rst
+++ b/doc/build/documentation.rst
@@ -26,6 +26,9 @@ The *htmldocs* target is used to build the HTML documentation. It uses the
     # Display the documentation in a graphical web browser
     x-www-browser doc/output/index.html
 
+The HTML documentation is published at https://u-boot.readthedocs.io. The build
+process for that site is controlled by the file *.readthedocs.yml*.
+
 Infodoc documentation
 ---------------------
 

diff --git a/doc/develop/ci_testing.rst b/doc/develop/ci_testing.rst
index b9a9a51..ffaaced 100644 (file)
--- a/doc/develop/ci_testing.rst
+++ b/doc/develop/ci_testing.rst
@@ -50,6 +50,12 @@ runners you are able to provide.  While it is intended to be able to run this
 pipeline on the free public instances provided at https://gitlab.com/ a problem
 with our squashfs tests currently prevents this.
 
+To push to Gitlab without triggering a pipeline use:
+
+.. code-block:: bash
+
+    git push -o ci.skip
+
 Docker container
 ----------------
 

diff --git a/doc/develop/codingstyle.rst b/doc/develop/codingstyle.rst
index 1d5d019..3d05a6b 100644 (file)
--- a/doc/develop/codingstyle.rst
+++ b/doc/develop/codingstyle.rst
@@ -19,6 +19,10 @@ The following rules apply:
   applies only to Linux, not to U-Boot. Only large hunks which are copied
   unchanged from Linux may retain that comment format.
 
+* Python code shall conform to `PEP8 (Style Guide for Python Code)
+  <https://peps.python.org/pep-0008/>`_. Use `pylint
+  <https://github.com/pylint-dev/pylint>`_ for checking the code.
+
 * Use patman to send your patches (``tools/patman/patman -H`` for full
   instructions). With a few tags in your commits this will check your patches
   and take care of emailing them.
@@ -67,6 +71,9 @@ documentation is strongly advised. The Linux kernel `kernel-doc
 <https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html>`_
 documentation applies with no changes.
 
+Our Python code documentation follows `PEP257 (Docstring Conventions)
+<https://peps.python.org/pep-0257/>`_.
+
 Use structures for I/O access
 -----------------------------
 

diff --git a/doc/develop/docstyle.rst b/doc/develop/docstyle.rst
new file mode 100644 (file)
index 0000000..f9ba83a
--- /dev/null
+++ b/doc/develop/docstyle.rst
@@ -0,0 +1,29 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+Documentation Style
+===================
+
+Documentation is crucial for the U-Boot project. It has to encompass the needs
+of different reader groups from first time users to developers and maintainers.
+This requires different types of documentation like tutorials, how-to-guides,
+explanatory texts, and reference.
+
+We want to be able to generate documentation in different target formats. We
+therefore use `Sphinx <https://www.sphinx-doc.org>`_ for the generation of
+documents from reStructured text.
+
+We apply the following rules:
+
+* Documentation files are located in *doc/* or its sub-directories.
+* Each documentation file is added to an index page to allow navigation
+  to the document.
+* For documentation we use reStructured text conforming to the requirements
+  of `Sphinx <https://www.sphinx-doc.org>`_.
+* For documentation within code we follow the Linux kernel guide
+  `Writing kernel-doc comments <https://docs.kernel.org/doc-guide/kernel-doc.html>`_.
+* We try to stick to 80 columns per line in documents.
+* For tables we prefer simple tables over grid tables. We avoid list tables
+  as they make the reStructured text documents hard to read.
+* Before submitting documentation patches we build the HTML documentation and
+  fix all warnings. The build process is described in
+  :doc:`/build/documentation`.

diff --git a/doc/develop/driver-model/index.rst b/doc/develop/driver-model/index.rst
index 7366ef8..8e12bbd 100644 (file)
--- a/doc/develop/driver-model/index.rst
+++ b/doc/develop/driver-model/index.rst
@@ -20,6 +20,7 @@ subsystems
    livetree
    migration
    nvme
+   nvmxip
    of-plat
    pci-info
    pmic-framework

diff --git a/doc/develop/driver-model/nvmxip.rst b/doc/develop/driver-model/nvmxip.rst
new file mode 100644 (file)
index 0000000..e85dc22
--- /dev/null
+++ b/doc/develop/driver-model/nvmxip.rst
@@ -0,0 +1,91 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+NVM XIP Block Storage Emulation Driver
+=======================================
+
+Summary
+-------
+
+Non-Volatile Memory devices with addressable memory (e.g: QSPI NOR flash) could
+be used for block storage needs (e.g: parsing a GPT layout in a raw QSPI NOR flash).
+
+The NVMXIP Uclass provides this functionality and can be used for any 64-bit platform.
+
+The NVMXIP Uclass provides the following drivers:
+
+      nvmxip-blk block driver:
+
+        A generic block driver allowing to read from the XIP flash.
+       The driver belongs to UCLASS_BLK.
+       The driver implemented by drivers/mtd/nvmxip/nvmxip.c
+
+      nvmxip Uclass driver:
+
+        When a device is described in the DT and associated with UCLASS_NVMXIP,
+        the Uclass creates a block device and binds it with the nvmxip-blk.
+       The Uclass driver implemented by drivers/mtd/nvmxip/nvmxip-uclass.c
+
+      nvmxip_qspi driver :
+
+        The driver probed with the DT and is the parent of the blk#<id> device.
+        nvmxip_qspi can be reused by other platforms. If the platform
+        has custom settings to apply before using the flash, then the platform
+        can provide its own parent driver belonging to UCLASS_NVMXIP and reuse
+        nvmxip-blk. The custom driver can be implemented like nvmxip_qspi in
+        addition to the platform custom settings.
+       The nvmxip_qspi driver belongs to UCLASS_NVMXIP.
+       The driver implemented by drivers/mtd/nvmxip/nvmxip_qspi.c
+
+       For example, if we have two NVMXIP devices described in the DT
+       The devices hierarchy is as follows:
+
+::
+
+   => dm tree
+
+        Class     Index  Probed  Driver                Name
+    -----------------------------------------------------------
+    ...
+     nvmxip        0  [ + ]   nvmxip_qspi           |-- nvmxip-qspi1@08000000
+     blk           3  [ + ]   nvmxip-blk                    |   `-- nvmxip-qspi1@08000000.blk#1
+     nvmxip        1  [ + ]   nvmxip_qspi           |-- nvmxip-qspi2@08200000
+     blk           4  [ + ]   nvmxip-blk                    |   `-- nvmxip-qspi2@08200000.blk#2
+
+The implementation is generic and can be used by different platforms.
+
+Supported hardware
+--------------------------------
+
+Any plaform supporting readq().
+
+Configuration
+----------------------
+
+config NVMXIP
+         This option allows the emulation of a block storage device
+         on top of a direct access non volatile memory XIP flash devices.
+         This support provides the read operation.
+         This option provides the block storage driver nvmxip-blk which
+         handles the read operation. This driver is HW agnostic and can support
+         multiple flash devices at the same time.
+
+config NVMXIP_QSPI
+         This option allows the emulation of a block storage device on top of a QSPI XIP flash.
+         Any platform that needs to emulate one or multiple QSPI XIP flash devices can turn this
+         option on to enable the functionality. NVMXIP config is selected automatically.
+         Platforms that need to add custom treatments before accessing to the flash, can
+         write their own driver (same as nvmxip_qspi in addition to the custom settings).
+
+Device Tree nodes
+--------------------
+
+Multiple QSPI XIP flash devices can be used at the same time by describing them through DT
+nodes.
+
+Please refer to the documentation of the DT binding at:
+
+doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt
+
+Contributors
+------------
+   * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

diff --git a/doc/develop/index.rst b/doc/develop/index.rst
index a52ad63..ddbf8da 100644 (file)
--- a/doc/develop/index.rst
+++ b/doc/develop/index.rst
@@ -11,6 +11,7 @@ General
 
    codingstyle
    designprinciples
+   docstyle
    patman
    process
    release_cycle

diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index ea584ce..7d63cf4 100644 (file)
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -48,13 +48,14 @@ Examples::
 Current Status
 --------------
 
-* U-Boot v2023.01 was released on Mon 09 January 2023.
+* U-Boot v2023.04 was released on Mon 03 April 2023.
 
-* The Merge Window for the next release (v2023.04) is **closed**.
+* The Merge Window for the next release (v2023.07) is **open** until the -rc1
+  release on Mon 24 April 2023.
 
-* The next branch is now **open**.
+* The next branch is now **closed**.
 
-* Release "v2023.04" is scheduled for 03 April 2023.
+* Release "v2023.07" is scheduled for 03 July 2023.
 
 Future Releases
 ---------------
@@ -62,29 +63,29 @@ Future Releases
 .. The following commented out dates are for when release candidates are
    planned to be tagged.
 
-For the next scheduled release, release candidates were made on::
+.. For the next scheduled release, release candidates were made on::
 
-* U-Boot v2023.04-rc1 was released on Mon 30 January 2023.
+.. * U-Boot v2023.07-rc1 was released on Mon 24 April 2023.
 
-* U-Boot v2023.04-rc2 was released on Mon 13 February 2023.
+.. * U-Boot v2023.07-rc2 was released on Mon 08 May 2023.
 
-* U-Boot v2023.04-rc3 was released on Mon 27 February 2023.
+.. * U-Boot v2023.07-rc3 was released on Mon 22 May 2023.
 
-* U-Boot v2023.04-rc4 was released on Mon 13 March 2023.
+.. * U-Boot v2023.07-rc4 was released on Mon 05 June 2023.
 
-* U-Boot v2023.04-rc5 was released on Mon 27 March 2023.
+.. * U-Boot v2023.07-rc5 was released on Mon 19 June 2023.
 
 Please note that the following dates are planned only and may be deviated from
 as needed.
 
-* "v2023.04": end of MW = Mon, Jan 30, 2022; release = Mon, Apr 03, 2023
-
 * "v2023.07": end of MW = Mon, Apr 24, 2023; release = Mon, Jul 03, 2023 
 
 * "v2023.10": end of MW = Mon, Jul 24, 2023; release = Mon, Oct 02, 2023
 
 * "v2024.01": end of MW = Mon, Oct 23, 2023; release = Mon, Jan 08, 2024
 
+* "v2024.04": end of MW = Mon, Jan 29, 2024; release = Tue, Apr 02, 2024
+
 Previous Releases
 -----------------
 
@@ -92,6 +93,8 @@ Note: these statistics are generated by our fork of `gitdm
 <https://source.denx.de/u-boot/gitdm>`_, which was originally created by
 Jonathan Corbet.
 
+* :doc:`statistics/u-boot-stats-v2023.04` which was released on 03 April 2023.
+
 * :doc:`statistics/u-boot-stats-v2023.01` which was released on 09 January 2023.
 
 * :doc:`statistics/u-boot-stats-v2022.10` which was released on 03 October 2022.

diff --git a/doc/develop/statistics/u-boot-stats-v2023.04.rst b/doc/develop/statistics/u-boot-stats-v2023.04.rst
new file mode 100644 (file)
index 0000000..57f2efc
--- /dev/null
+++ b/doc/develop/statistics/u-boot-stats-v2023.04.rst
@@ -0,0 +1,767 @@
+:orphan:
+
+Release Statistics for U-Boot v2023.04
+======================================
+
+* Processed 1691 changesets from 157 developers
+
+* 29 employers found
+
+* A total of 174471 lines added, 78380 removed (delta 96091)
+
+.. table:: Developers with the most changesets
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Simon Glass                           381 (22.5%)
+   Tom Rini                              333 (19.7%)
+   Marek Vasut                           101 (6.0%)
+   Heinrich Schuchardt                   70 (4.1%)
+   Jagan Teki                            53 (3.1%)
+   Jonas Karlman                         36 (2.1%)
+   Patrick Delaunay                      35 (2.1%)
+   Hai Pham                              21 (1.2%)
+   Michal Simek                          20 (1.2%)
+   Maxim Cournoyer                       20 (1.2%)
+   Svyatoslav Ryhel                      17 (1.0%)
+   Sean Anderson                         15 (0.9%)
+   Fabio Estevam                         14 (0.8%)
+   Pali Rohár                            14 (0.8%)
+   Sumit Garg                            14 (0.8%)
+   Bryan Brattlof                        14 (0.8%)
+   Sinthu Raja                           13 (0.8%)
+   Andre Przywara                        13 (0.8%)
+   Heiko Schocher                        13 (0.8%)
+   Yu Chien Peter Lin                    12 (0.7%)
+   Tim Harvey                            12 (0.7%)
+   Peng Fan                              12 (0.7%)
+   Tony Dinh                             11 (0.7%)
+   Angelo Dureghello                     11 (0.7%)
+   Masahisa Kojima                       11 (0.7%)
+   Quentin Schulz                        11 (0.7%)
+   Roger Quadros                         11 (0.7%)
+   Marcel Ziswiler                       11 (0.7%)
+   Holger Brunck                         10 (0.6%)
+   Mark Kettenis                         10 (0.6%)
+   Sergiu Moga                           10 (0.6%)
+   Nikhil M Jain                         9 (0.5%)
+   Jim Liu                               9 (0.5%)
+   Christophe Leroy                      9 (0.5%)
+   Balamanikandan Gunasundar             9 (0.5%)
+   Dario Binacchi                        8 (0.5%)
+   Samuel Holland                        8 (0.5%)
+   Frieder Schrempf                      8 (0.5%)
+   Mikhail Ilin                          8 (0.5%)
+   Sjoerd Simons                         7 (0.4%)
+   Neil Armstrong                        7 (0.4%)
+   Eugen Hristev                         7 (0.4%)
+   Chris Morgan                          7 (0.4%)
+   Dzmitry Sankouski                     7 (0.4%)
+   Ioana Ciornei                         7 (0.4%)
+   Ilias Apalodimas                      6 (0.4%)
+   Peter Robinson                        6 (0.4%)
+   Paweł Anikiel                         6 (0.4%)
+   Andrejs Cainikovs                     6 (0.4%)
+   Rob Herring                           6 (0.4%)
+   John Keeping                          5 (0.3%)
+   Mihai Sain                            5 (0.3%)
+   Rick Chen                             5 (0.3%)
+   Sergei Antonov                        5 (0.3%)
+   Ashok Reddy Soma                      5 (0.3%)
+   Algapally Santosh Sagar               5 (0.3%)
+   Dhruva Gole                           5 (0.3%)
+   Brandon Maier                         5 (0.3%)
+   Alexey Romanov                        5 (0.3%)
+   Vasily Khoruzhick                     4 (0.2%)
+   Manoj Sai                             4 (0.2%)
+   Jan Kiszka                            4 (0.2%)
+   Ovidiu Panait                         4 (0.2%)
+   Takahiro Kuwano                       4 (0.2%)
+   Enric Balletbo i Serra                4 (0.2%)
+   Fabrice Gasnier                       4 (0.2%)
+   Victor Lim                            4 (0.2%)
+   Stefan Bosch                          4 (0.2%)
+   Vincent Stehlé                        3 (0.2%)
+   Tam Nguyen                            3 (0.2%)
+   Leo Yu-Chi Liang                      3 (0.2%)
+   Mattijs Korpershoek                   3 (0.2%)
+   Ye Li                                 3 (0.2%)
+   Oleksandr Suvorov                     3 (0.2%)
+   Max Krummenacher                      3 (0.2%)
+   Andrew Davis                          3 (0.2%)
+   Michael Walle                         3 (0.2%)
+   Andreas Kemnade                       3 (0.2%)
+   Kshitiz Varshney                      3 (0.2%)
+   Dai Okamura                           3 (0.2%)
+   Stefan Roese                          2 (0.1%)
+   Vincent Fazio                         2 (0.1%)
+   Kamlesh Gurudasani                    2 (0.1%)
+   Johan Jonker                          2 (0.1%)
+   Antoine Mazeas                        2 (0.1%)
+   Christopher Obbard                    2 (0.1%)
+   Akash Gajjar                          2 (0.1%)
+   Ilko Iliev                            2 (0.1%)
+   Qu Wenruo                             2 (0.1%)
+   Etienne Carriere                      2 (0.1%)
+   Thomas Fitzsimmons                    2 (0.1%)
+   Pei Yue Ho                            2 (0.1%)
+   Ryan Chen                             2 (0.1%)
+   Adam Ford                             2 (0.1%)
+   Philippe Schenker                     2 (0.1%)
+   Linus Walleij                         2 (0.1%)
+   Sean Edmond                           2 (0.1%)
+   Nikita Shubin                         2 (0.1%)
+   Ying-Chun Liu (PaulLiu)               2 (0.1%)
+   Loic Poulain                          2 (0.1%)
+   Pengfei Fan                           2 (0.1%)
+   Jernej Skrabec                        2 (0.1%)
+   Neha Malcom Francis                   2 (0.1%)
+   Harald Seiler                         2 (0.1%)
+   Shenlin Liang                         2 (0.1%)
+   Martyn Welch                          2 (0.1%)
+   Harini Katakam                        2 (0.1%)
+   Marc Kleine-Budde                     2 (0.1%)
+   David Sebek                           1 (0.1%)
+   Jonathan Liu                          1 (0.1%)
+   Vignesh Raghavendra                   1 (0.1%)
+   Sebastian Andrzej Siewior             1 (0.1%)
+   annsai01                              1 (0.1%)
+   Peter Geis                            1 (0.1%)
+   Ralph Siemsen                         1 (0.1%)
+   Robert Marko                          1 (0.1%)
+   Michal Suchanek                       1 (0.1%)
+   Jaehoon Chung                         1 (0.1%)
+   Christian Kohlschütter                1 (0.1%)
+   Ramin Khonsari                        1 (0.1%)
+   Maxim Schwalm                         1 (0.1%)
+   Venkatesh Yadav Abbarapu              1 (0.1%)
+   Ivan Khoronzhuk                       1 (0.1%)
+   Ulf Samuelsson                        1 (0.1%)
+   Jade Lovelace                         1 (0.1%)
+   Michael Trimarchi                     1 (0.1%)
+   Matwey V. Kornilov                    1 (0.1%)
+   KaDiWa                                1 (0.1%)
+   Christian Marangi                     1 (0.1%)
+   Ehsan Mohandesi                       1 (0.1%)
+   Aurelien Jarno                        1 (0.1%)
+   Mario Kicherer                        1 (0.1%)
+   Arnaud Ferraris                       1 (0.1%)
+   Detlev Casanova                       1 (0.1%)
+   Igor Opaniuk                          1 (0.1%)
+   Massimo Pegorer                       1 (0.1%)
+   Kunihiko Hayashi                      1 (0.1%)
+   Joost van Zwieten                     1 (0.1%)
+   Jorge Ramirez-Ortiz                   1 (0.1%)
+   Jay Buddhabhatti                      1 (0.1%)
+   Andrey Dolnikov                       1 (0.1%)
+   chenzhipeng                           1 (0.1%)
+   Olivier Moysan                        1 (0.1%)
+   Ville Skyttä                          1 (0.1%)
+   David Oberhollenzer                   1 (0.1%)
+   Haijun Qin                            1 (0.1%)
+   Neal Frager                           1 (0.1%)
+   Luca Ceresoli                         1 (0.1%)
+   Viacheslav Bocharov                   1 (0.1%)
+   Yuepeng Xing                          1 (0.1%)
+   Cristian Birsan                       1 (0.1%)
+   Lokanathan, Raaj                      1 (0.1%)
+   Christian Gmeiner                     1 (0.1%)
+   Daniel Golle                          1 (0.1%)
+   Manuel Traut                          1 (0.1%)
+   Ben Dooks                             1 (0.1%)
+   Kasper Revsbech                       1 (0.1%)
+   ====================================  =====
+
+
+.. table:: Developers with the most changed lines
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Bryan Brattlof                        38811 (18.1%)
+   Tom Rini                              36464 (17.0%)
+   Simon Glass                           30090 (14.0%)
+   Jagan Teki                            23918 (11.1%)
+   Marek Vasut                           14720 (6.9%)
+   Brandon Maier                         13759 (6.4%)
+   Tony Dinh                             7399 (3.4%)
+   Balamanikandan Gunasundar             4239 (2.0%)
+   Jim Liu                               4106 (1.9%)
+   Fabio Estevam                         3264 (1.5%)
+   Christophe Leroy                      2145 (1.0%)
+   Neil Armstrong                        2020 (0.9%)
+   Nikhil M Jain                         1681 (0.8%)
+   Sumit Garg                            1671 (0.8%)
+   Tim Harvey                            1524 (0.7%)
+   Jonas Karlman                         1439 (0.7%)
+   Roger Quadros                         1431 (0.7%)
+   Quentin Schulz                        1296 (0.6%)
+   Heinrich Schuchardt                   1277 (0.6%)
+   Michal Simek                          1274 (0.6%)
+   Svyatoslav Ryhel                      1259 (0.6%)
+   Akash Gajjar                          1057 (0.5%)
+   Mark Kettenis                         1042 (0.5%)
+   Sinthu Raja                           967 (0.5%)
+   Holger Brunck                         966 (0.5%)
+   Chris Morgan                          965 (0.4%)
+   Peter Robinson                        919 (0.4%)
+   Luca Ceresoli                         860 (0.4%)
+   Hai Pham                              712 (0.3%)
+   Andre Przywara                        702 (0.3%)
+   Kunihiko Hayashi                      695 (0.3%)
+   Dario Binacchi                        690 (0.3%)
+   Patrick Delaunay                      668 (0.3%)
+   Samuel Holland                        568 (0.3%)
+   Dhruva Gole                           527 (0.2%)
+   Ryan Chen                             504 (0.2%)
+   Sergei Antonov                        464 (0.2%)
+   Sean Anderson                         439 (0.2%)
+   Ashok Reddy Soma                      399 (0.2%)
+   Masahisa Kojima                       391 (0.2%)
+   Sergiu Moga                           382 (0.2%)
+   Maxim Cournoyer                       380 (0.2%)
+   Massimo Pegorer                       353 (0.2%)
+   Linus Walleij                         317 (0.1%)
+   Eugen Hristev                         295 (0.1%)
+   Alexey Romanov                        285 (0.1%)
+   Yu Chien Peter Lin                    267 (0.1%)
+   Stefan Bosch                          260 (0.1%)
+   Dzmitry Sankouski                     257 (0.1%)
+   Heiko Schocher                        221 (0.1%)
+   Enric Balletbo i Serra                214 (0.1%)
+   Kshitiz Varshney                      211 (0.1%)
+   Thomas Fitzsimmons                    205 (0.1%)
+   Mihai Sain                            191 (0.1%)
+   Angelo Dureghello                     167 (0.1%)
+   Adam Ford                             162 (0.1%)
+   Marcel Ziswiler                       160 (0.1%)
+   Mattijs Korpershoek                   154 (0.1%)
+   Etienne Carriere                      154 (0.1%)
+   Leo Yu-Chi Liang                      135 (0.1%)
+   Ramin Khonsari                        131 (0.1%)
+   Pali Rohár                            127 (0.1%)
+   Olivier Moysan                        116 (0.1%)
+   Vincent Fazio                         106 (0.0%)
+   Fabrice Gasnier                       98 (0.0%)
+   Max Krummenacher                      80 (0.0%)
+   Takahiro Kuwano                       76 (0.0%)
+   Victor Lim                            73 (0.0%)
+   Frieder Schrempf                      72 (0.0%)
+   Manoj Sai                             70 (0.0%)
+   Andrew Davis                          70 (0.0%)
+   Mikhail Ilin                          69 (0.0%)
+   Dai Okamura                           65 (0.0%)
+   Tam Nguyen                            63 (0.0%)
+   Peng Fan                              61 (0.0%)
+   Sjoerd Simons                         61 (0.0%)
+   Cristian Birsan                       59 (0.0%)
+   Antoine Mazeas                        51 (0.0%)
+   Rick Chen                             49 (0.0%)
+   Paweł Anikiel                         47 (0.0%)
+   Andreas Kemnade                       45 (0.0%)
+   Jan Kiszka                            43 (0.0%)
+   Andrejs Cainikovs                     41 (0.0%)
+   Michael Trimarchi                     41 (0.0%)
+   Rob Herring                           40 (0.0%)
+   Martyn Welch                          36 (0.0%)
+   Stefan Roese                          35 (0.0%)
+   Neha Malcom Francis                   35 (0.0%)
+   Algapally Santosh Sagar               34 (0.0%)
+   Jernej Skrabec                        34 (0.0%)
+   Maxim Schwalm                         30 (0.0%)
+   Qu Wenruo                             29 (0.0%)
+   Loic Poulain                          29 (0.0%)
+   Ioana Ciornei                         28 (0.0%)
+   Christian Kohlschütter                28 (0.0%)
+   Michael Walle                         23 (0.0%)
+   Vasily Khoruzhick                     22 (0.0%)
+   Pei Yue Ho                            22 (0.0%)
+   Vincent Stehlé                        19 (0.0%)
+   Venkatesh Yadav Abbarapu              19 (0.0%)
+   Pengfei Fan                           16 (0.0%)
+   Harald Seiler                         16 (0.0%)
+   Ville Skyttä                          16 (0.0%)
+   Sean Edmond                           14 (0.0%)
+   Harini Katakam                        14 (0.0%)
+   Robert Marko                          14 (0.0%)
+   John Keeping                          13 (0.0%)
+   Ovidiu Panait                         13 (0.0%)
+   Kamlesh Gurudasani                    13 (0.0%)
+   Nikita Shubin                         13 (0.0%)
+   Marc Kleine-Budde                     13 (0.0%)
+   Detlev Casanova                       13 (0.0%)
+   David Oberhollenzer                   11 (0.0%)
+   Ilias Apalodimas                      10 (0.0%)
+   Mario Kicherer                        10 (0.0%)
+   Yuepeng Xing                          10 (0.0%)
+   Jaehoon Chung                         9 (0.0%)
+   KaDiWa                                9 (0.0%)
+   Oleksandr Suvorov                     8 (0.0%)
+   Christian Gmeiner                     8 (0.0%)
+   Ye Li                                 7 (0.0%)
+   Christopher Obbard                    7 (0.0%)
+   Ying-Chun Liu (PaulLiu)               7 (0.0%)
+   Johan Jonker                          6 (0.0%)
+   Jonathan Liu                          6 (0.0%)
+   Andrey Dolnikov                       6 (0.0%)
+   Daniel Golle                          6 (0.0%)
+   Philippe Schenker                     5 (0.0%)
+   Michal Suchanek                       5 (0.0%)
+   Ivan Khoronzhuk                       5 (0.0%)
+   Ilko Iliev                            4 (0.0%)
+   Manuel Traut                          4 (0.0%)
+   Shenlin Liang                         3 (0.0%)
+   annsai01                              3 (0.0%)
+   Ulf Samuelsson                        3 (0.0%)
+   Matwey V. Kornilov                    3 (0.0%)
+   Jay Buddhabhatti                      3 (0.0%)
+   chenzhipeng                           3 (0.0%)
+   Ben Dooks                             3 (0.0%)
+   Peter Geis                            2 (0.0%)
+   Ralph Siemsen                         2 (0.0%)
+   Christian Marangi                     2 (0.0%)
+   Jorge Ramirez-Ortiz                   2 (0.0%)
+   David Sebek                           1 (0.0%)
+   Vignesh Raghavendra                   1 (0.0%)
+   Sebastian Andrzej Siewior             1 (0.0%)
+   Jade Lovelace                         1 (0.0%)
+   Ehsan Mohandesi                       1 (0.0%)
+   Aurelien Jarno                        1 (0.0%)
+   Arnaud Ferraris                       1 (0.0%)
+   Igor Opaniuk                          1 (0.0%)
+   Joost van Zwieten                     1 (0.0%)
+   Haijun Qin                            1 (0.0%)
+   Neal Frager                           1 (0.0%)
+   Viacheslav Bocharov                   1 (0.0%)
+   Lokanathan, Raaj                      1 (0.0%)
+   Kasper Revsbech                       1 (0.0%)
+   ====================================  =====
+
+
+.. table:: Developers with the most lines removed
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Tom Rini                              18089 (23.1%)
+   Simon Glass                           5998 (7.7%)
+   Luca Ceresoli                         860 (1.1%)
+   Holger Brunck                         532 (0.7%)
+   Leo Yu-Chi Liang                      90 (0.1%)
+   Mattijs Korpershoek                   83 (0.1%)
+   Andrew Davis                          43 (0.1%)
+   Pali Rohár                            28 (0.0%)
+   Maxim Schwalm                         27 (0.0%)
+   Dai Okamura                           12 (0.0%)
+   Michael Walle                         12 (0.0%)
+   Ovidiu Panait                         10 (0.0%)
+   Peng Fan                              7 (0.0%)
+   Ioana Ciornei                         6 (0.0%)
+   Michal Suchanek                       4 (0.0%)
+   Rob Herring                           3 (0.0%)
+   Johan Jonker                          3 (0.0%)
+   Ying-Chun Liu (PaulLiu)               2 (0.0%)
+   Ilko Iliev                            1 (0.0%)
+   ====================================  =====
+
+
+.. table:: Developers with the most signoffs (total 215)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Francesco Dolcini                     21 (9.8%)
+   Marek Vasut                           21 (9.8%)
+   Tom                                   19 (8.8%)
+   Michal Simek                          19 (8.8%)
+   Michael Trimarchi                     8 (3.7%)
+   Dario Binacchi                        8 (3.7%)
+   Neil Armstrong                        8 (3.7%)
+   Hai Pham                              7 (3.3%)
+   Kever Yang                            6 (2.8%)
+   Tom Rini                              5 (2.3%)
+   YouMin Chen                           5 (2.3%)
+   Jianqun Xu                            4 (1.9%)
+   Elaine Zhang                          4 (1.9%)
+   Mike Worsfold                         4 (1.9%)
+   Manoj Sai                             4 (1.9%)
+   Marcel Ziswiler                       4 (1.9%)
+   Ashok Reddy Soma                      4 (1.9%)
+   Peter Robinson                        4 (1.9%)
+   Peng Fan                              3 (1.4%)
+   Andre Przywara                        3 (1.4%)
+   Heinrich Schuchardt                   3 (1.4%)
+   Vignesh Raghavendra                   2 (0.9%)
+   Joseph Chen                           2 (0.9%)
+   Finley Xiao                           2 (0.9%)
+   Suniel Mahesh                         2 (0.9%)
+   FUKAUMI Naoki                         2 (0.9%)
+   Judith Mendez                         2 (0.9%)
+   Robert Hancock                        2 (0.9%)
+   Peter Geis                            2 (0.9%)
+   Andrejs Cainikovs                     2 (0.9%)
+   Samuel Holland                        2 (0.9%)
+   Jonas Karlman                         2 (0.9%)
+   Jagan Teki                            2 (0.9%)
+   Simon Glass                           1 (0.5%)
+   Mattijs Korpershoek                   1 (0.5%)
+   Pali Rohár                            1 (0.5%)
+   Michal Suchanek                       1 (0.5%)
+   Anand Gadiyar                         1 (0.5%)
+   Angelo Durgehello                     1 (0.5%)
+   Nam Nguyen                            1 (0.5%)
+   Steven Liu                            1 (0.5%)
+   Sebastian Reichel                     1 (0.5%)
+   Yifeng Zhao                           1 (0.5%)
+   Ren Jianing                           1 (0.5%)
+   Vladimir Oltean                       1 (0.5%)
+   Jonas Schwöbel                        1 (0.5%)
+   Shawn Guo                             1 (0.5%)
+   Jason Zhu                             1 (0.5%)
+   Jon Lin                               1 (0.5%)
+   Sugar Zhang                           1 (0.5%)
+   Valentine Barshak                     1 (0.5%)
+   Jit Loon Lim                          1 (0.5%)
+   Philippe Schenker                     1 (0.5%)
+   Ilias Apalodimas                      1 (0.5%)
+   Sjoerd Simons                         1 (0.5%)
+   Tam Nguyen                            1 (0.5%)
+   Ramin Khonsari                        1 (0.5%)
+   Sergiu Moga                           1 (0.5%)
+   Svyatoslav Ryhel                      1 (0.5%)
+   Quentin Schulz                        1 (0.5%)
+   ====================================  =====
+
+
+.. table:: Developers with the most reviews (total 767)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Simon Glass                           225 (29.3%)
+   Kever Yang                            112 (14.6%)
+   Fabio Estevam                         49 (6.4%)
+   Tom Rini                              33 (4.3%)
+   Patrice Chotard                       33 (4.3%)
+   Marek Vasut                           27 (3.5%)
+   Ramon Fried                           22 (2.9%)
+   Stefan Roese                          17 (2.2%)
+   Ilias Apalodimas                      16 (2.1%)
+   Leo Yu-Chi Liang                      15 (2.0%)
+   Rick Chen                             15 (2.0%)
+   Heinrich Schuchardt                   14 (1.8%)
+   Jagan Teki                            14 (1.8%)
+   Patrick Delaunay                      14 (1.8%)
+   Mattijs Korpershoek                   13 (1.7%)
+   Jaehoon Chung                         13 (1.7%)
+   Samuel Holland                        12 (1.6%)
+   Heiko Schocher                        9 (1.2%)
+   Neil Armstrong                        8 (1.0%)
+   Vladimir Oltean                       7 (0.9%)
+   Sean Anderson                         7 (0.9%)
+   Bin Meng                              6 (0.8%)
+   FRANJOU Stephane                      6 (0.8%)
+   Claudiu Beznea                        6 (0.8%)
+   Michael Trimarchi                     5 (0.7%)
+   Peng Fan                              5 (0.7%)
+   Jens Wiklander                        5 (0.7%)
+   Yu Chien Peter Lin                    4 (0.5%)
+   Andre Przywara                        3 (0.4%)
+   Pali Rohár                            3 (0.4%)
+   Viacheslav Mitrofanov                 3 (0.4%)
+   Ye Li                                 3 (0.4%)
+   Dhruva Gole                           3 (0.4%)
+   Marcel Ziswiler                       2 (0.3%)
+   Oleksandr Suvorov                     2 (0.3%)
+   Wei Liang Lim                         2 (0.3%)
+   Eng Lee Teh                           2 (0.3%)
+   Minkyu Kang                           2 (0.3%)
+   Tudor Ambarus                         2 (0.3%)
+   Philipp Tomsich                       2 (0.3%)
+   Etienne Carriere                      2 (0.3%)
+   Masahisa Kojima                       2 (0.3%)
+   Eugen Hristev                         2 (0.3%)
+   Francesco Dolcini                     1 (0.1%)
+   Michal Simek                          1 (0.1%)
+   Jonas Karlman                         1 (0.1%)
+   Nishanth Menon                        1 (0.1%)
+   Siddharth Vadapalli                   1 (0.1%)
+   Matthias Brugger                      1 (0.1%)
+   Chia-Wei Wang                         1 (0.1%)
+   Huang Jianan                          1 (0.1%)
+   Oliver Graute                         1 (0.1%)
+   Pratyush Yadav                        1 (0.1%)
+   Soeren Moch                           1 (0.1%)
+   Sunil V L                             1 (0.1%)
+   Miquel Raynal                         1 (0.1%)
+   Hector Palacios                       1 (0.1%)
+   Derald Woods                          1 (0.1%)
+   Nick Desaulniers                      1 (0.1%)
+   Frieder Schrempf                      1 (0.1%)
+   Adam Ford                             1 (0.1%)
+   Sumit Garg                            1 (0.1%)
+   Christophe Leroy                      1 (0.1%)
+   ====================================  =====
+
+
+.. table:: Developers with the most test credits (total 78)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Svyatoslav Ryhel                      12 (15.4%)
+   Andreas Westman Dorcsak               11 (14.1%)
+   Thierry Reding                        9 (11.5%)
+   Robert Eckelmann                      8 (10.3%)
+   Samuel Holland                        6 (7.7%)
+   Vagrant Cascadian                     3 (3.8%)
+   Jagan Teki                            2 (2.6%)
+   Eugen Hristev                         2 (2.6%)
+   Jonas Schwöbel                        2 (2.6%)
+   Quentin Schulz                        2 (2.6%)
+   Agneli                                2 (2.6%)
+   Lothar Waßmann                        2 (2.6%)
+   Simon Glass                           1 (1.3%)
+   Fabio Estevam                         1 (1.3%)
+   Ilias Apalodimas                      1 (1.3%)
+   Rick Chen                             1 (1.3%)
+   Patrick Delaunay                      1 (1.3%)
+   Mattijs Korpershoek                   1 (1.3%)
+   Andre Przywara                        1 (1.3%)
+   Dhruva Gole                           1 (1.3%)
+   Jonas Karlman                         1 (1.3%)
+   Suniel Mahesh                         1 (1.3%)
+   Sjoerd Simons                         1 (1.3%)
+   Matwey V. Kornilov                    1 (1.3%)
+   Anand Moon                            1 (1.3%)
+   Vaishnav Achath                       1 (1.3%)
+   Karsten Merker                        1 (1.3%)
+   Sean Nyekjaer                         1 (1.3%)
+   Mihai Sain                            1 (1.3%)
+   ====================================  =====
+
+
+.. table:: Developers who gave the most tested-by credits (total 78)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Svyatoslav Ryhel                      41 (52.6%)
+   Andre Przywara                        6 (7.7%)
+   Tom Rini                              5 (6.4%)
+   Simon Glass                           4 (5.1%)
+   Jonas Karlman                         3 (3.8%)
+   Loic Poulain                          3 (3.8%)
+   Ramin Khonsari                        2 (2.6%)
+   Jagan Teki                            1 (1.3%)
+   Patrick Delaunay                      1 (1.3%)
+   Dhruva Gole                           1 (1.3%)
+   Sjoerd Simons                         1 (1.3%)
+   Michael Trimarchi                     1 (1.3%)
+   Etienne Carriere                      1 (1.3%)
+   Peter Geis                            1 (1.3%)
+   Sergiu Moga                           1 (1.3%)
+   Maxim Schwalm                         1 (1.3%)
+   Kasper Revsbech                       1 (1.3%)
+   Neha Malcom Francis                   1 (1.3%)
+   Fabrice Gasnier                       1 (1.3%)
+   Maxim Cournoyer                       1 (1.3%)
+   Sergei Antonov                        1 (1.3%)
+   ====================================  =====
+
+
+.. table:: Developers with the most report credits (total 22)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Heinrich Schuchardt                   3 (13.6%)
+   Ilias Apalodimas                      2 (9.1%)
+   Patrick Delaunay                      1 (4.5%)
+   Sjoerd Simons                         1 (4.5%)
+   Samuel Holland                        1 (4.5%)
+   Quentin Schulz                        1 (4.5%)
+   Karsten Merker                        1 (4.5%)
+   Marek Vasut                           1 (4.5%)
+   Francesco Dolcini                     1 (4.5%)
+   Nishanth Menon                        1 (4.5%)
+   Oliver Graute                         1 (4.5%)
+   Anand Gadiyar                         1 (4.5%)
+   Philippe Schenker                     1 (4.5%)
+   Andreas Schwab                        1 (4.5%)
+   Stefan Herbrechtsmeier                1 (4.5%)
+   Carlos Rafael Giani                   1 (4.5%)
+   Dave Jones                            1 (4.5%)
+   Serge Bazanski                        1 (4.5%)
+   Sam Winchenbach                       1 (4.5%)
+   ====================================  =====
+
+
+.. table:: Developers who gave the most report credits (total 22)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Simon Glass                           6 (27.3%)
+   Tom Rini                              5 (22.7%)
+   Heinrich Schuchardt                   3 (13.6%)
+   Qu Wenruo                             2 (9.1%)
+   Ilias Apalodimas                      1 (4.5%)
+   Maxim Cournoyer                       1 (4.5%)
+   Fabio Estevam                         1 (4.5%)
+   Vignesh Raghavendra                   1 (4.5%)
+   Harald Seiler                         1 (4.5%)
+   Sinthu Raja                           1 (4.5%)
+   ====================================  =====
+
+
+.. table:: Top changeset contributors by employer
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   (Unknown)                             524 (31.0%)
+   Google, Inc.                          381 (22.5%)
+   Konsulko Group                        333 (19.7%)
+   DENX Software Engineering             72 (4.3%)
+   Texas Instruments                     49 (2.9%)
+   Linaro                                47 (2.8%)
+   Edgeble AI Technologies Pvt. Ltd.     46 (2.7%)
+   ST Microelectronics                   40 (2.4%)
+   AMD                                   34 (2.0%)
+   NXP                                   25 (1.5%)
+   Renesas Electronics                   24 (1.4%)
+   Toradex                               24 (1.4%)
+   Amarula Solutions                     20 (1.2%)
+   Collabora Ltd.                        20 (1.2%)
+   ARM                                   17 (1.0%)
+   Semihalf Embedded Systems             6 (0.4%)
+   Red Hat                               4 (0.2%)
+   Siemens                               4 (0.2%)
+   Socionext Inc.                        4 (0.2%)
+   BayLibre SAS                          3 (0.2%)
+   SUSE                                  3 (0.2%)
+   Pengutronix                           2 (0.1%)
+   Ronetix                               2 (0.1%)
+   Extreme Engineering Solutions         2 (0.1%)
+   Bootlin                               1 (0.1%)
+   Intel                                 1 (0.1%)
+   linutronix                            1 (0.1%)
+   Samsung                               1 (0.1%)
+   Xilinx                                1 (0.1%)
+   ====================================  =====
+
+
+.. table:: Top lines changed by employer
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   (Unknown)                             64681 (30.1%)
+   Texas Instruments                     42105 (19.6%)
+   Konsulko Group                        36464 (17.0%)
+   Google, Inc.                          30090 (14.0%)
+   Edgeble AI Technologies Pvt. Ltd.     23070 (10.7%)
+   Linaro                                4601 (2.1%)
+   DENX Software Engineering             4582 (2.1%)
+   AMD                                   1741 (0.8%)
+   Amarula Solutions                     1649 (0.8%)
+   ST Microelectronics                   882 (0.4%)
+   Bootlin                               860 (0.4%)
+   Renesas Electronics                   775 (0.4%)
+   Socionext Inc.                        760 (0.4%)
+   ARM                                   724 (0.3%)
+   Collabora Ltd.                        413 (0.2%)
+   NXP                                   307 (0.1%)
+   Toradex                               290 (0.1%)
+   Red Hat                               214 (0.1%)
+   BayLibre SAS                          154 (0.1%)
+   Extreme Engineering Solutions         106 (0.0%)
+   Semihalf Embedded Systems             47 (0.0%)
+   Siemens                               43 (0.0%)
+   SUSE                                  34 (0.0%)
+   Pengutronix                           13 (0.0%)
+   Samsung                               9 (0.0%)
+   Ronetix                               4 (0.0%)
+   Xilinx                                3 (0.0%)
+   Intel                                 1 (0.0%)
+   linutronix                            1 (0.0%)
+   ====================================  =====
+
+
+.. table:: Employers with the most signoffs (total 215)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   (Unknown)                             48 (22.3%)
+   Rockchip                              29 (13.5%)
+   Toradex                               28 (13.0%)
+   Amarula Solutions                     24 (11.2%)
+   AMD                                   23 (10.7%)
+   NVidia                                19 (8.8%)
+   Linaro                                9 (4.2%)
+   Renesas Electronics                   9 (4.2%)
+   Texas Instruments                     5 (2.3%)
+   Konsulko Group                        5 (2.3%)
+   NXP                                   4 (1.9%)
+   ARM                                   3 (1.4%)
+   Canonical                             3 (1.4%)
+   Collabora Ltd.                        2 (0.9%)
+   Google, Inc.                          1 (0.5%)
+   BayLibre SAS                          1 (0.5%)
+   SUSE                                  1 (0.5%)
+   Intel                                 1 (0.5%)
+   ====================================  =====
+
+
+.. table:: Employers with the most hackers (total 160)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   (Unknown)                             86 (53.8%)
+   Linaro                                9 (5.6%)
+   Texas Instruments                     8 (5.0%)
+   AMD                                   6 (3.8%)
+   Collabora Ltd.                        6 (3.8%)
+   Toradex                               5 (3.1%)
+   DENX Software Engineering             5 (3.1%)
+   Amarula Solutions                     4 (2.5%)
+   NXP                                   4 (2.5%)
+   ARM                                   3 (1.9%)
+   ST Microelectronics                   3 (1.9%)
+   Renesas Electronics                   2 (1.2%)
+   SUSE                                  2 (1.2%)
+   Socionext Inc.                        2 (1.2%)
+   Konsulko Group                        1 (0.6%)
+   Google, Inc.                          1 (0.6%)
+   BayLibre SAS                          1 (0.6%)
+   Intel                                 1 (0.6%)
+   Edgeble AI Technologies Pvt. Ltd.     1 (0.6%)
+   Bootlin                               1 (0.6%)
+   Red Hat                               1 (0.6%)
+   Extreme Engineering Solutions         1 (0.6%)
+   Semihalf Embedded Systems             1 (0.6%)
+   Siemens                               1 (0.6%)
+   Pengutronix                           1 (0.6%)
+   Samsung                               1 (0.6%)
+   Ronetix                               1 (0.6%)
+   Xilinx                                1 (0.6%)
+   linutronix                            1 (0.6%)
+   ====================================  =====
+

diff --git a/doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt b/doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt
new file mode 100644 (file)
index 0000000..882728d
--- /dev/null
+++ b/doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt
@@ -0,0 +1,56 @@
+Specifying NVMXIP information for devices
+======================================
+
+QSPI XIP flash device nodes
+---------------------------
+
+Each flash device should have its own node.
+
+Each node must specify the following fields:
+
+1)
+               compatible = "nvmxip,qspi";
+
+This allows to bind the flash device with the nvmxip_qspi driver
+If a platform has its own driver, please provide your own compatible
+string.
+
+2)
+               reg = /bits/ 64 <0x08000000 0x00200000>;
+
+The start address and size of the flash device. The values give here are an
+example (when the cell size is 2).
+
+When cell size is 1, the reg field looks like this:
+
+               reg = <0x08000000 0x00200000>;
+
+3)
+
+               lba_shift = <9>;
+
+The number of bit shifts used to calculate the size in bytes of one block.
+In this example the block size is 1 << 9 = 2 ^ 9 = 512 bytes
+
+4)
+
+               lba = <4096>;
+
+The number of blocks.
+
+Example of multiple flash devices
+----------------------------------------------------
+
+       nvmxip-qspi1@08000000 {
+               compatible = "nvmxip,qspi";
+               reg = /bits/ 64 <0x08000000 0x00200000>;
+               lba_shift = <9>;
+               lba = <4096>;
+       };
+
+       nvmxip-qspi2@08200000 {
+               compatible = "nvmxip,qspi";
+               reg = /bits/ 64 <0x08200000 0x00100000>;
+               lba_shift = <9>;
+               lba = <2048>;
+       };

diff --git a/doc/device-tree-bindings/serial/sh.txt b/doc/device-tree-bindings/serial/sh.txt
index 99634a5..7707a9c 100644 (file)
--- a/doc/device-tree-bindings/serial/sh.txt
+++ b/doc/device-tree-bindings/serial/sh.txt
@@ -1,6 +1,6 @@
 * Renesas SCI serial interface
 
 Required properties:
-- compatible: must be "renesas,scif", "renesas,scifa" or "renesas,sci"
+- compatible: must be "renesas,scif", "renesas,hscif", "renesas,scifa" or "renesas,sci"
 - reg: exactly one register range with length
 - clock: input clock frequency for the SCI unit

diff --git a/doc/usage/blkmap.rst b/doc/usage/blkmap.rst
new file mode 100644 (file)
index 0000000..dbfa8e5
--- /dev/null
+++ b/doc/usage/blkmap.rst
@@ -0,0 +1,111 @@
+.. SPDX-License-Identifier: GPL-2.0+
+..
+.. Copyright (c) 2023 Addiva Elektronik
+.. Author: Tobias Waldekranz <tobias@waldekranz.com>
+
+Block Maps (blkmap)
+===================
+
+Block maps are a way of looking at various sources of data through the
+lens of a regular block device. It lets you treat devices that are not
+block devices, like RAM, as if they were. It also lets you export a
+slice of an existing block device, which does not have to correspond
+to a partition boundary, as a new block device.
+
+This is primarily useful because U-Boot's filesystem drivers only
+operate on block devices, so a block map lets you access filesystems
+wherever they might be located.
+
+The implementation is loosely modeled on Linux's "Device Mapper"
+subsystem, see `kernel documentation`_ for more information.
+
+.. _kernel documentation: https://docs.kernel.org/admin-guide/device-mapper/index.html
+
+
+Example: Netbooting an Ext4 Image
+---------------------------------
+
+Say that our system is using an Ext4 filesystem as its rootfs, where
+the kernel is stored in ``/boot``. This image is then typically stored
+in an eMMC partition. In this configuration, we can use something like
+``load mmc 0 ${kernel_addr_r} /boot/Image`` to load the kernel image
+into the expected location, and then boot the system. No problems.
+
+Now imagine that during development, or as a recovery mechanism, we
+want to boot the same type of image by downloading it over the
+network. Getting the image to the target is easy enough:
+
+::
+
+   dhcp ${ramdisk_addr_r} rootfs.ext4
+
+But now we are faced with a predicament: how to we extract the kernel
+image? Block maps to the rescue!
+
+We start by creating a new device:
+
+::
+
+   blkmap create netboot
+
+Before setting up the mapping, we figure out the size of the
+downloaded file, in blocks:
+
+::
+
+   setexpr fileblks ${filesize} + 0x1ff
+   setexpr fileblks ${filesize} / 0x200
+
+Then we can add a mapping to the start of our device, backed by the
+memory at `${loadaddr}`:
+
+::
+
+   blkmap map netboot 0 ${fileblks} mem ${fileaddr}
+
+Now we can access the filesystem via the virtual device:
+
+::
+
+   blkmap get netboot dev devnum
+   load blkmap ${devnum} ${kernel_addr_r} /boot/Image
+
+
+Example: Accessing a filesystem inside an FIT image
+---------------------------------------------------
+
+In this example, an FIT image is stored in an eMMC partition. We would
+like to read the file ``/etc/version``, stored inside a Squashfs image
+in the FIT. Since the Squashfs image is not stored on a partition
+boundary, there is no way of accessing it via ``load mmc ...``.
+
+What we can to instead is to first figure out the offset and size of
+the filesystem:
+
+::
+
+   mmc dev 0
+   mmc read ${loadaddr} 0 0x100
+
+   fdt addr ${loadaddr}
+   fdt get value squashaddr /images/ramdisk data-position
+   fdt get value squashsize /images/ramdisk data-size
+
+   setexpr squashblk  ${squashaddr} / 0x200
+   setexpr squashsize ${squashsize} + 0x1ff
+   setexpr squashsize ${squashsize} / 0x200
+
+Then we can create a block map that maps to that slice of the full
+partition:
+
+::
+
+   blkmap create sq
+   blkmap map sq 0 ${squashsize} linear mmc 0 ${squashblk}
+
+Now we can access the filesystem:
+
+::
+
+   blkmap get sq dev devnum
+   load blkmap ${devnum} ${loadaddr} /etc/version

diff --git a/doc/usage/cmd/coninfo.rst b/doc/usage/cmd/coninfo.rst
new file mode 100644 (file)
index 0000000..f913148
--- /dev/null
+++ b/doc/usage/cmd/coninfo.rst
@@ -0,0 +1,55 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+coninfo command
+===============
+
+Synopsis
+--------
+
+::
+
+    coninfo
+
+Description
+-----------
+
+The coninfo command provides a list of available console input and output
+devices and their assignment as stdin, stdout, stderr console devices.
+
+If CONFIG_SYS_CONSOLE_IS_IN_ENV=y, the assignment is controlled by the
+environment variables stdin, stdout, stderr which contain a comma separated
+list of device names.
+
+Example
+--------
+
+.. code-block:: console
+
+    => coninfo
+    List of available devices
+    |-- pl011@9000000 (IO)
+    |   |-- stdin
+    |   |-- stdout
+    |   |-- stderr
+    |-- serial (IO)
+    |-- usbkbd (I)
+    => setenv stdin pl011@9000000,usbkbd
+    => coninfo
+    List of available devices
+    |-- pl011@9000000 (IO)
+    |   |-- stdin
+    |   |-- stdout
+    |   |-- stderr
+    |-- serial (IO)
+    |-- usbkbd (I)
+    |   |-- stdin
+
+Configuration
+-------------
+
+The coninfo command is only available if CONFIG_CMD_CONSOLE=y.
+
+Return value
+------------
+
+The return value $? is always 0 (true).

diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index bc85e1d..cdf7109 100644 (file)
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -4,6 +4,7 @@ Use U-Boot
 .. toctree::
    :maxdepth: 1
 
+   blkmap
    dfu
    environment
    fdt_overlays
@@ -38,6 +39,7 @@ Shell commands
    cmd/cbsysinfo
    cmd/cls
    cmd/cmp
+   cmd/coninfo
    cmd/conitrace
    cmd/cyclic
    cmd/dm

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 3fe53d6..049f7ef 100644 (file)
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -20,6 +20,14 @@ config SATA
 
          See also CMD_SATA which provides command-line support.
 
+config SYS_SATA_MAX_PORTS
+       int "Maximum supported SATA ports"
+       depends on SCSI_AHCI && !DM_SCSI
+       default 1
+       help
+         Sets the maximum number of ports to scan when looking for devices.
+         Ports from 0 to (this value - 1) are scanned.
+
 config LIBATA
        bool
        help
@@ -37,6 +45,7 @@ config AHCI_PCI
        bool "Support for PCI-based AHCI controller"
        depends on PCI
        depends on DM_SCSI
+       depends on SCSI_AHCI
        help
          Enables support for the PCI-based AHCI controller.
 

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 272c48b..cb2c648 100644 (file)
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -211,8 +211,8 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv)
              uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
 
 #if !defined(CONFIG_DM_SCSI)
-       if (uc_priv->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
-               uc_priv->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
+       if (uc_priv->n_ports > CONFIG_SYS_SATA_MAX_PORTS)
+               uc_priv->n_ports = CONFIG_SYS_SATA_MAX_PORTS;
 #endif
 
        for (i = 0; i < uc_priv->n_ports; i++) {
@@ -1152,7 +1152,12 @@ int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
 int ahci_probe_scsi_pci(struct udevice *ahci_dev)
 {
        ulong base;
-       u16 vendor, device;
+       u16 vendor, device, cmd;
+
+       /* Enable bus mastering */
+       dm_pci_read_config16(ahci_dev, PCI_COMMAND, &cmd);
+       cmd |= PCI_COMMAND_MASTER;
+       dm_pci_write_config16(ahci_dev, PCI_COMMAND, cmd);
 
        base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5, 0, 0,
                                     PCI_REGION_TYPE, PCI_REGION_MEM);

diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index e95da48..5a1aeb3 100644 (file)
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -67,6 +67,24 @@ config BLOCK_CACHE
          it will prevent repeated reads from directory structures and other
          filesystem data structures.
 
+config BLKMAP
+       bool "Composable virtual block devices (blkmap)"
+       depends on BLK
+       help
+         Create virtual block devices that are backed by various sources,
+         e.g. RAM, or parts of an existing block device. Though much more
+         rudimentary, it borrows a lot of ideas from Linux's device mapper
+         subsystem.
+
+         Example use-cases:
+         - Treat a region of RAM as a block device, i.e. a RAM disk. This let's
+            you extract files from filesystem images stored in RAM (perhaps as a
+            result of a TFTP transfer).
+         - Create a virtual partition on an existing device. This let's you
+            access filesystems that aren't stored at an exact partition
+            boundary. A common example is a filesystem image embedded in an FIT
+            image.
+
 config SPL_BLOCK_CACHE
        bool "Use block device cache in SPL"
        depends on SPL_BLK

diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index f12447d..a161d14 100644 (file)
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_IDE) += ide.o
 endif
 obj-$(CONFIG_SANDBOX) += sandbox.o host-uclass.o host_dev.o
 obj-$(CONFIG_$(SPL_TPL_)BLOCK_CACHE) += blkcache.o
+obj-$(CONFIG_BLKMAP) += blkmap.o
 
 obj-$(CONFIG_EFI_MEDIA) += efi-media-uclass.o
 obj-$(CONFIG_EFI_MEDIA_SANDBOX) += sb_efi_media.o

diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index c69fc4d..614b975 100644 (file)
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -28,10 +28,12 @@ static struct {
        { UCLASS_AHCI, "sata" },
        { UCLASS_HOST, "host" },
        { UCLASS_NVME, "nvme" },
+       { UCLASS_NVMXIP, "nvmxip" },
        { UCLASS_EFI_MEDIA, "efi" },
        { UCLASS_EFI_LOADER, "efiloader" },
        { UCLASS_VIRTIO, "virtio" },
        { UCLASS_PVBLOCK, "pvblock" },
+       { UCLASS_BLKMAP, "blkmap" },
 };
 
 static enum uclass_id uclass_name_to_iftype(const char *uclass_idname)

diff --git a/drivers/block/blkmap.c b/drivers/block/blkmap.c
new file mode 100644 (file)
index 0000000..2bb0acc
--- /dev/null
+++ b/drivers/block/blkmap.c
@@ -0,0 +1,519 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Addiva Elektronik
+ * Author: Tobias Waldekranz <tobias@waldekranz.com>
+ */
+
+#include <common.h>
+#include <blk.h>
+#include <blkmap.h>
+#include <dm.h>
+#include <malloc.h>
+#include <mapmem.h>
+#include <part.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/root.h>
+
+struct blkmap;
+
+/**
+ * struct blkmap_slice - Region mapped to a blkmap
+ *
+ * Common data for a region mapped to a blkmap, specialized by each
+ * map type.
+ *
+ * @node: List node used to associate this slice with a blkmap
+ * @blknr: Start block number of the mapping
+ * @blkcnt: Number of blocks covered by this mapping
+ */
+struct blkmap_slice {
+       struct list_head node;
+
+       lbaint_t blknr;
+       lbaint_t blkcnt;
+
+       /**
+        * @read: - Read from slice
+        *
+        * @read.bm: Blkmap to which this slice belongs
+        * @read.bms: This slice
+        * @read.blknr: Start block number to read from
+        * @read.blkcnt: Number of blocks to read
+        * @read.buffer: Buffer to store read data to
+        */
+       ulong (*read)(struct blkmap *bm, struct blkmap_slice *bms,
+                     lbaint_t blknr, lbaint_t blkcnt, void *buffer);
+
+       /**
+        * @write: - Write to slice
+        *
+        * @write.bm: Blkmap to which this slice belongs
+        * @write.bms: This slice
+        * @write.blknr: Start block number to write to
+        * @write.blkcnt: Number of blocks to write
+        * @write.buffer: Data to be written
+        */
+       ulong (*write)(struct blkmap *bm, struct blkmap_slice *bms,
+                      lbaint_t blknr, lbaint_t blkcnt, const void *buffer);
+
+       /**
+        * @destroy: - Tear down slice
+        *
+        * @read.bm: Blkmap to which this slice belongs
+        * @read.bms: This slice
+        */
+       void (*destroy)(struct blkmap *bm, struct blkmap_slice *bms);
+};
+
+/**
+ * struct blkmap - Block map
+ *
+ * Data associated with a blkmap.
+ *
+ * @label: Human readable name of this blkmap
+ * @blk: Underlying block device
+ * @slices: List of slices associated with this blkmap
+ */
+struct blkmap {
+       char *label;
+       struct udevice *blk;
+       struct list_head slices;
+};
+
+static bool blkmap_slice_contains(struct blkmap_slice *bms, lbaint_t blknr)
+{
+       return (blknr >= bms->blknr) && (blknr < (bms->blknr + bms->blkcnt));
+}
+
+static bool blkmap_slice_available(struct blkmap *bm, struct blkmap_slice *new)
+{
+       struct blkmap_slice *bms;
+       lbaint_t first, last;
+
+       first = new->blknr;
+       last = new->blknr + new->blkcnt - 1;
+
+       list_for_each_entry(bms, &bm->slices, node) {
+               if (blkmap_slice_contains(bms, first) ||
+                   blkmap_slice_contains(bms, last) ||
+                   blkmap_slice_contains(new, bms->blknr) ||
+                   blkmap_slice_contains(new, bms->blknr + bms->blkcnt - 1))
+                       return false;
+       }
+
+       return true;
+}
+
+static int blkmap_slice_add(struct blkmap *bm, struct blkmap_slice *new)
+{
+       struct blk_desc *bd = dev_get_uclass_plat(bm->blk);
+       struct list_head *insert = &bm->slices;
+       struct blkmap_slice *bms;
+
+       if (!blkmap_slice_available(bm, new))
+               return -EBUSY;
+
+       list_for_each_entry(bms, &bm->slices, node) {
+               if (bms->blknr < new->blknr)
+                       continue;
+
+               insert = &bms->node;
+               break;
+       }
+
+       list_add_tail(&new->node, insert);
+
+       /* Disk might have grown, update the size */
+       bms = list_last_entry(&bm->slices, struct blkmap_slice, node);
+       bd->lba = bms->blknr + bms->blkcnt;
+       return 0;
+}
+
+/**
+ * struct blkmap_linear - Linear mapping to other block device
+ *
+ * @slice: Common map data
+ * @blk: Target block device of this mapping
+ * @blknr: Start block number of the target device
+ */
+struct blkmap_linear {
+       struct blkmap_slice slice;
+
+       struct udevice *blk;
+       lbaint_t blknr;
+};
+
+static ulong blkmap_linear_read(struct blkmap *bm, struct blkmap_slice *bms,
+                               lbaint_t blknr, lbaint_t blkcnt, void *buffer)
+{
+       struct blkmap_linear *bml = container_of(bms, struct blkmap_linear, slice);
+
+       return blk_read(bml->blk, bml->blknr + blknr, blkcnt, buffer);
+}
+
+static ulong blkmap_linear_write(struct blkmap *bm, struct blkmap_slice *bms,
+                                lbaint_t blknr, lbaint_t blkcnt,
+                                const void *buffer)
+{
+       struct blkmap_linear *bml = container_of(bms, struct blkmap_linear, slice);
+
+       return blk_write(bml->blk, bml->blknr + blknr, blkcnt, buffer);
+}
+
+int blkmap_map_linear(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+                     struct udevice *lblk, lbaint_t lblknr)
+{
+       struct blkmap *bm = dev_get_plat(dev);
+       struct blkmap_linear *linear;
+       struct blk_desc *bd, *lbd;
+       int err;
+
+       bd = dev_get_uclass_plat(bm->blk);
+       lbd = dev_get_uclass_plat(lblk);
+       if (lbd->blksz != bd->blksz)
+               /* We could support block size translation, but we
+                * don't yet.
+                */
+               return -EINVAL;
+
+       linear = malloc(sizeof(*linear));
+       if (!linear)
+               return -ENOMEM;
+
+       *linear = (struct blkmap_linear) {
+               .slice = {
+                       .blknr = blknr,
+                       .blkcnt = blkcnt,
+
+                       .read = blkmap_linear_read,
+                       .write = blkmap_linear_write,
+               },
+
+               .blk = lblk,
+               .blknr = lblknr,
+       };
+
+       err = blkmap_slice_add(bm, &linear->slice);
+       if (err)
+               free(linear);
+
+       return err;
+}
+
+/**
+ * struct blkmap_mem - Memory mapping
+ *
+ * @slice: Common map data
+ * @addr: Target memory region of this mapping
+ * @remapped: True if @addr is backed by a physical to virtual memory
+ * mapping that must be torn down at the end of this mapping's
+ * lifetime.
+ */
+struct blkmap_mem {
+       struct blkmap_slice slice;
+       void *addr;
+       bool remapped;
+};
+
+static ulong blkmap_mem_read(struct blkmap *bm, struct blkmap_slice *bms,
+                            lbaint_t blknr, lbaint_t blkcnt, void *buffer)
+{
+       struct blkmap_mem *bmm = container_of(bms, struct blkmap_mem, slice);
+       struct blk_desc *bd = dev_get_uclass_plat(bm->blk);
+       char *src;
+
+       src = bmm->addr + (blknr << bd->log2blksz);
+       memcpy(buffer, src, blkcnt << bd->log2blksz);
+       return blkcnt;
+}
+
+static ulong blkmap_mem_write(struct blkmap *bm, struct blkmap_slice *bms,
+                             lbaint_t blknr, lbaint_t blkcnt,
+                             const void *buffer)
+{
+       struct blkmap_mem *bmm = container_of(bms, struct blkmap_mem, slice);
+       struct blk_desc *bd = dev_get_uclass_plat(bm->blk);
+       char *dst;
+
+       dst = bmm->addr + (blknr << bd->log2blksz);
+       memcpy(dst, buffer, blkcnt << bd->log2blksz);
+       return blkcnt;
+}
+
+static void blkmap_mem_destroy(struct blkmap *bm, struct blkmap_slice *bms)
+{
+       struct blkmap_mem *bmm = container_of(bms, struct blkmap_mem, slice);
+
+       if (bmm->remapped)
+               unmap_sysmem(bmm->addr);
+}
+
+int __blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+                    void *addr, bool remapped)
+{
+       struct blkmap *bm = dev_get_plat(dev);
+       struct blkmap_mem *bmm;
+       int err;
+
+       bmm = malloc(sizeof(*bmm));
+       if (!bmm)
+               return -ENOMEM;
+
+       *bmm = (struct blkmap_mem) {
+               .slice = {
+                       .blknr = blknr,
+                       .blkcnt = blkcnt,
+
+                       .read = blkmap_mem_read,
+                       .write = blkmap_mem_write,
+                       .destroy = blkmap_mem_destroy,
+               },
+
+               .addr = addr,
+               .remapped = remapped,
+       };
+
+       err = blkmap_slice_add(bm, &bmm->slice);
+       if (err)
+               free(bmm);
+
+       return err;
+}
+
+int blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+                  void *addr)
+{
+       return __blkmap_map_mem(dev, blknr, blkcnt, addr, false);
+}
+
+int blkmap_map_pmem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+                   phys_addr_t paddr)
+{
+       struct blkmap *bm = dev_get_plat(dev);
+       struct blk_desc *bd = dev_get_uclass_plat(bm->blk);
+       void *addr;
+       int err;
+
+       addr = map_sysmem(paddr, blkcnt << bd->log2blksz);
+       if (!addr)
+               return -ENOMEM;
+
+       err = __blkmap_map_mem(dev, blknr, blkcnt, addr, true);
+       if (err)
+               unmap_sysmem(addr);
+
+       return err;
+}
+
+static ulong blkmap_blk_read_slice(struct blkmap *bm, struct blkmap_slice *bms,
+                                  lbaint_t blknr, lbaint_t blkcnt,
+                                  void *buffer)
+{
+       lbaint_t nr, cnt;
+
+       nr = blknr - bms->blknr;
+       cnt = (blkcnt < bms->blkcnt) ? blkcnt : bms->blkcnt;
+       return bms->read(bm, bms, nr, cnt, buffer);
+}
+
+static ulong blkmap_blk_read(struct udevice *dev, lbaint_t blknr,
+                            lbaint_t blkcnt, void *buffer)
+{
+       struct blk_desc *bd = dev_get_uclass_plat(dev);
+       struct blkmap *bm = dev_get_plat(dev->parent);
+       struct blkmap_slice *bms;
+       lbaint_t cnt, total = 0;
+
+       list_for_each_entry(bms, &bm->slices, node) {
+               if (!blkmap_slice_contains(bms, blknr))
+                       continue;
+
+               cnt = blkmap_blk_read_slice(bm, bms, blknr, blkcnt, buffer);
+               blknr += cnt;
+               blkcnt -= cnt;
+               buffer += cnt << bd->log2blksz;
+               total += cnt;
+       }
+
+       return total;
+}
+
+static ulong blkmap_blk_write_slice(struct blkmap *bm, struct blkmap_slice *bms,
+                                   lbaint_t blknr, lbaint_t blkcnt,
+                                   const void *buffer)
+{
+       lbaint_t nr, cnt;
+
+       nr = blknr - bms->blknr;
+       cnt = (blkcnt < bms->blkcnt) ? blkcnt : bms->blkcnt;
+       return bms->write(bm, bms, nr, cnt, buffer);
+}
+
+static ulong blkmap_blk_write(struct udevice *dev, lbaint_t blknr,
+                             lbaint_t blkcnt, const void *buffer)
+{
+       struct blk_desc *bd = dev_get_uclass_plat(dev);
+       struct blkmap *bm = dev_get_plat(dev->parent);
+       struct blkmap_slice *bms;
+       lbaint_t cnt, total = 0;
+
+       list_for_each_entry(bms, &bm->slices, node) {
+               if (!blkmap_slice_contains(bms, blknr))
+                       continue;
+
+               cnt = blkmap_blk_write_slice(bm, bms, blknr, blkcnt, buffer);
+               blknr += cnt;
+               blkcnt -= cnt;
+               buffer += cnt << bd->log2blksz;
+               total += cnt;
+       }
+
+       return total;
+}
+
+static const struct blk_ops blkmap_blk_ops = {
+       .read   = blkmap_blk_read,
+       .write  = blkmap_blk_write,
+};
+
+U_BOOT_DRIVER(blkmap_blk) = {
+       .name           = "blkmap_blk",
+       .id             = UCLASS_BLK,
+       .ops            = &blkmap_blk_ops,
+};
+
+int blkmap_dev_bind(struct udevice *dev)
+{
+       struct blkmap *bm = dev_get_plat(dev);
+       struct blk_desc *bd;
+       int err;
+
+       err = blk_create_devicef(dev, "blkmap_blk", "blk", UCLASS_BLKMAP,
+                                dev_seq(dev), 512, 0, &bm->blk);
+       if (err)
+               return log_msg_ret("blk", err);
+
+       INIT_LIST_HEAD(&bm->slices);
+
+       bd = dev_get_uclass_plat(bm->blk);
+       snprintf(bd->vendor, BLK_VEN_SIZE, "U-Boot");
+       snprintf(bd->product, BLK_PRD_SIZE, "blkmap");
+       snprintf(bd->revision, BLK_REV_SIZE, "1.0");
+
+       /* EFI core isn't keen on zero-sized disks, so we lie. This is
+        * updated with the correct size once the user adds a
+        * mapping.
+        */
+       bd->lba = 1;
+
+       return 0;
+}
+
+int blkmap_dev_unbind(struct udevice *dev)
+{
+       struct blkmap *bm = dev_get_plat(dev);
+       struct blkmap_slice *bms, *tmp;
+       int err;
+
+       list_for_each_entry_safe(bms, tmp, &bm->slices, node) {
+               list_del(&bms->node);
+               free(bms);
+       }
+
+       err = device_remove(bm->blk, DM_REMOVE_NORMAL);
+       if (err)
+               return err;
+
+       return device_unbind(bm->blk);
+}
+
+U_BOOT_DRIVER(blkmap_root) = {
+       .name           = "blkmap_dev",
+       .id             = UCLASS_BLKMAP,
+       .bind           = blkmap_dev_bind,
+       .unbind         = blkmap_dev_unbind,
+       .plat_auto      = sizeof(struct blkmap),
+};
+
+struct udevice *blkmap_from_label(const char *label)
+{
+       struct udevice *dev;
+       struct uclass *uc;
+       struct blkmap *bm;
+
+       uclass_id_foreach_dev(UCLASS_BLKMAP, dev, uc) {
+               bm = dev_get_plat(dev);
+               if (bm->label && !strcmp(label, bm->label))
+                       return dev;
+       }
+
+       return NULL;
+}
+
+int blkmap_create(const char *label, struct udevice **devp)
+{
+       char *hname, *hlabel;
+       struct udevice *dev;
+       struct blkmap *bm;
+       size_t namelen;
+       int err;
+
+       dev = blkmap_from_label(label);
+       if (dev) {
+               err = -EBUSY;
+               goto err;
+       }
+
+       hlabel = strdup(label);
+       if (!hlabel) {
+               err = -ENOMEM;
+               goto err;
+       }
+
+       namelen = strlen("blkmap-") + strlen(label) + 1;
+       hname = malloc(namelen);
+       if (!hname) {
+               err = -ENOMEM;
+               goto err_free_hlabel;
+       }
+
+       strlcpy(hname, "blkmap-", namelen);
+       strlcat(hname, label, namelen);
+
+       err = device_bind_driver(dm_root(), "blkmap_dev", hname, &dev);
+       if (err)
+               goto err_free_hname;
+
+       device_set_name_alloced(dev);
+       bm = dev_get_plat(dev);
+       bm->label = hlabel;
+
+       if (devp)
+               *devp = dev;
+
+       return 0;
+
+err_free_hname:
+       free(hname);
+err_free_hlabel:
+       free(hlabel);
+err:
+       return err;
+}
+
+int blkmap_destroy(struct udevice *dev)
+{
+       int err;
+
+       err = device_remove(dev, DM_REMOVE_NORMAL);
+       if (err)
+               return err;
+
+       return device_unbind(dev);
+}
+
+UCLASS_DRIVER(blkmap) = {
+       .id             = UCLASS_BLKMAP,
+       .name           = "blkmap",
+};

diff --git a/drivers/block/host_dev.c b/drivers/block/host_dev.c
index 5885fc3..6442241 100644 (file)
--- a/drivers/block/host_dev.c
+++ b/drivers/block/host_dev.c
@@ -24,7 +24,8 @@ static int host_sb_attach_file(struct udevice *dev, const char *filename)
        struct host_sb_plat *plat = dev_get_plat(dev);
        struct blk_desc *desc;
        struct udevice *blk;
-       int ret, fd, size;
+       int ret, fd;
+       off_t size;
        char *fname;
 
        if (!filename)

diff --git a/drivers/block/ide.c b/drivers/block/ide.c
index 1ad9b6c..89201dd 100644 (file)
--- a/drivers/block/ide.c
+++ b/drivers/block/ide.c
@@ -36,9 +36,8 @@ ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS] = {
 #endif
 };
 
-static int ide_bus_ok[CONFIG_SYS_IDE_MAXBUS];
-
-struct blk_desc ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
+#define ATA_CURR_BASE(dev)     (CONFIG_SYS_ATA_BASE_ADDR + \
+               ide_bus_offset[IDE_BUS(dev)])
 
 #define IDE_TIME_OUT   2000    /* 2 sec timeout */
 
@@ -46,35 +45,57 @@ struct blk_desc ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
 
 #define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
 
-#ifdef CONFIG_IDE_RESET
-extern void ide_set_reset(int idereset);
-
 static void ide_reset(void)
 {
-       int i;
+       if (IS_ENABLED(CONFIG_IDE_RESET)) {
+               /* assert reset */
+               ide_set_reset(1);
 
-       for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; ++i)
-               ide_bus_ok[i] = 0;
-       for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i)
-               ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
+               /* the reset signal shall be asserted for et least 25 us */
+               udelay(25);
 
-       ide_set_reset(1);       /* assert reset */
+               schedule();
 
-       /* the reset signal shall be asserted for et least 25 us */
-       udelay(25);
+               /* de-assert RESET signal */
+               ide_set_reset(0);
 
-       schedule();
+               mdelay(250);
+       }
+}
 
-       /* de-assert RESET signal */
-       ide_set_reset(0);
+static void ide_outb(int dev, int port, u8 val)
+{
+       log_debug("(dev= %d, port= %#x, val= 0x%02x) : @ 0x%08lx\n",
+                 dev, port, val, ATA_CURR_BASE(dev) + port);
 
-       /* wait 250 ms */
-       for (i = 0; i < 250; ++i)
-               udelay(1000);
+       outb(val, ATA_CURR_BASE(dev) + port);
+}
+
+static u8 ide_inb(int dev, int port)
+{
+       uchar val;
+
+       val = inb(ATA_CURR_BASE(dev) + port);
+
+       log_debug("(dev= %d, port= %#x) : @ 0x%08lx -> 0x%02x\n",
+                 dev, port, ATA_CURR_BASE(dev) + port, val);
+       return val;
+}
+
+static void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+       uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG);
+       ushort *dbuf = (ushort *)sect_buf;
+
+       log_debug("in input swap data base for read is %p\n", (void *)paddr);
+
+       while (words--) {
+               EIEIO;
+               *dbuf++ = be16_to_cpu(inw(paddr));
+               EIEIO;
+               *dbuf++ = be16_to_cpu(inw(paddr));
+       }
 }
-#else
-#define ide_reset()    /* dummy */
-#endif /* CONFIG_IDE_RESET */
 
 /*
  * Wait until Busy bit is off, or timeout (in ms)
@@ -87,7 +108,7 @@ static uchar ide_wait(int dev, ulong t)
 
        while ((c = ide_inb(dev, ATA_STATUS)) & ATA_STAT_BUSY) {
                udelay(100);
-               if (delay-- == 0)
+               if (!delay--)
                        break;
        }
        return c;
@@ -98,10 +119,9 @@ static uchar ide_wait(int dev, ulong t)
  * terminate the string
  * "len" is the size of available memory including the terminating '\0'
  */
-static void ident_cpy(unsigned char *dst, unsigned char *src,
-                     unsigned int len)
+static void ident_cpy(u8 *dst, u8 *src, uint len)
 {
-       unsigned char *end, *last;
+       u8 *end, *last;
 
        last = dst;
        end = src + len - 1;
@@ -124,21 +144,20 @@ OUT:
        *last = '\0';
 }
 
-#ifdef CONFIG_ATAPI
 /****************************************************************************
  * ATAPI Support
  */
 
 /* since ATAPI may use commands with not 4 bytes alligned length
  * we have our own transfer functions, 2 bytes alligned */
-__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+static void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
 {
-       uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG);
+       uintptr_t paddr = ATA_CURR_BASE(dev) + ATA_DATA_REG;
        ushort *dbuf;
 
        dbuf = (ushort *)sect_buf;
 
-       debug("in output data shorts base for read is %p\n", (void *)paddr);
+       log_debug("in output data shorts base for read is %p\n", (void *)paddr);
 
        while (shorts--) {
                EIEIO;
@@ -146,14 +165,14 @@ __weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
        }
 }
 
-__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+static void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
 {
-       uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG);
+       uintptr_t paddr = ATA_CURR_BASE(dev) + ATA_DATA_REG;
        ushort *dbuf;
 
        dbuf = (ushort *)sect_buf;
 
-       debug("in input data shorts base for read is %p\n", (void *)paddr);
+       log_debug("in input data shorts base for read is %p\n", (void *)paddr);
 
        while (shorts--) {
                EIEIO;
@@ -175,12 +194,12 @@ static uchar atapi_wait_mask(int dev, ulong t, uchar mask, uchar res)
        /* prevents to read the status before valid */
        c = ide_inb(dev, ATA_DEV_CTL);
 
-       while (((c = ide_inb(dev, ATA_STATUS)) & mask) != res) {
+       while (c = ide_inb(dev, ATA_STATUS) & mask, c != res) {
                /* break if error occurs (doesn't make sense to wait more) */
                if ((c & ATA_STAT_ERR) == ATA_STAT_ERR)
                        break;
                udelay(100);
-               if (delay-- == 0)
+               if (!delay--)
                        break;
        }
        return c;
@@ -189,10 +208,9 @@ static uchar atapi_wait_mask(int dev, ulong t, uchar mask, uchar res)
 /*
  * issue an atapi command
  */
-unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
-                         unsigned char *buffer, int buflen)
+static u8 atapi_issue(int device, u8 *ccb, int ccblen, u8 *buffer, int buflen)
 {
-       unsigned char c, err, mask, res;
+       u8 c, err, mask, res;
        int n;
 
        /* Select device
@@ -202,18 +220,17 @@ unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
        ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
        c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
        if ((c & mask) != res) {
-               printf("ATAPI_ISSUE: device %d not ready status %X\n", device,
+               printf("ATAPI_ISSUE: device %d not ready status %x\n", device,
                       c);
-               err = 0xFF;
+               err = 0xff;
                goto AI_OUT;
        }
        /* write taskfile */
        ide_outb(device, ATA_ERROR_REG, 0);     /* no DMA, no overlaped */
        ide_outb(device, ATA_SECT_CNT, 0);
        ide_outb(device, ATA_SECT_NUM, 0);
-       ide_outb(device, ATA_CYL_LOW, (unsigned char) (buflen & 0xFF));
-       ide_outb(device, ATA_CYL_HIGH,
-                (unsigned char) ((buflen >> 8) & 0xFF));
+       ide_outb(device, ATA_CYL_LOW, (u8)(buflen & 0xff));
+       ide_outb(device, ATA_CYL_HIGH, (u8)((buflen >> 8) & 0xff));
        ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
 
        ide_outb(device, ATA_COMMAND, ATA_CMD_PACKET);
@@ -224,17 +241,17 @@ unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
        c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
 
        if ((c & mask) != res) {        /* DRQ must be 1, BSY 0 */
-               printf("ATAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status 0x%02x\n",
+               printf("ATAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status %#02x\n",
                       device, c);
-               err = 0xFF;
+               err = 0xff;
                goto AI_OUT;
        }
 
        /* write command block */
-       ide_output_data_shorts(device, (unsigned short *)ccb, ccblen / 2);
+       ide_output_data_shorts(device, (ushort *)ccb, ccblen / 2);
 
        /* ATAPI Command written wait for completition */
-       udelay(5000);           /* device must set bsy */
+       mdelay(5);              /* device must set bsy */
 
        mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
        /*
@@ -248,12 +265,12 @@ unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
        if ((c & mask) != res) {
                if (c & ATA_STAT_ERR) {
                        err = (ide_inb(device, ATA_ERROR_REG)) >> 4;
-                       debug("atapi_issue 1 returned sense key %X status %02X\n",
-                             err, c);
+                       log_debug("1 returned sense key %x status %02x\n",
+                                 err, c);
                } else {
-                       printf("ATAPI_ISSUE: (no DRQ) after sending ccb (%x)  status 0x%02x\n",
+                       printf("ATAPI_ISSUE: (no DRQ) after sending ccb (%x)  status %#02x\n",
                               ccb[0], c);
-                       err = 0xFF;
+                       err = 0xff;
                }
                goto AI_OUT;
        }
@@ -266,38 +283,36 @@ unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
                err = 0xff;
                goto AI_OUT;
        }
-       if ((n == 0) && (buflen < 0)) {
+       if (!n && buflen < 0) {
                printf("ERROR, transfer bytes %d requested %d\n", n, buflen);
                err = 0xff;
                goto AI_OUT;
        }
        if (n != buflen) {
-               debug("WARNING, transfer bytes %d not equal with requested %d\n",
-                     n, buflen);
+               log_debug("WARNING, transfer bytes %d not equal with requested %d\n",
+                         n, buflen);
        }
-       if (n != 0) {           /* data transfer */
-               debug("ATAPI_ISSUE: %d Bytes to transfer\n", n);
+       if (n) {                /* data transfer */
+               log_debug("ATAPI_ISSUE: %d Bytes to transfer\n", n);
                /* we transfer shorts */
                n >>= 1;
                /* ok now decide if it is an in or output */
-               if ((ide_inb(device, ATA_SECT_CNT) & 0x02) == 0) {
-                       debug("Write to device\n");
-                       ide_output_data_shorts(device, (unsigned short *)buffer,
-                                              n);
+               if (!(ide_inb(device, ATA_SECT_CNT) & 0x02)) {
+                       log_debug("Write to device\n");
+                       ide_output_data_shorts(device, (ushort *)buffer, n);
                } else {
-                       debug("Read from device @ %p shorts %d\n", buffer, n);
-                       ide_input_data_shorts(device, (unsigned short *)buffer,
-                                             n);
+                       log_debug("Read from device @ %p shorts %d\n", buffer,
+                                 n);
+                       ide_input_data_shorts(device, (ushort *)buffer, n);
                }
        }
-       udelay(5000);           /* seems that some CD ROMs need this... */
+       mdelay(5);              /* seems that some CD ROMs need this... */
        mask = ATA_STAT_BUSY | ATA_STAT_ERR;
        res = 0;
        c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
        if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
                err = (ide_inb(device, ATA_ERROR_REG) >> 4);
-               debug("atapi_issue 2 returned sense key %X status %X\n", err,
-                     c);
+               log_debug("2 returned sense key %x status %x\n", err, c);
        } else {
                err = 0;
        }
@@ -313,13 +328,11 @@ AI_OUT:
 #define ATAPI_DRIVE_NOT_READY  100
 #define ATAPI_UNIT_ATTN                10
 
-unsigned char atapi_issue_autoreq(int device,
-                                 unsigned char *ccb,
-                                 int ccblen,
-                                 unsigned char *buffer, int buflen)
+static u8 atapi_issue_autoreq(int device, u8 *ccb, int ccblen, u8 *buffer,
+                             int buflen)
 {
-       unsigned char sense_data[18], sense_ccb[12];
-       unsigned char res, key, asc, ascq;
+       u8 sense_data[18], sense_ccb[12];
+       u8 res, key, asc, ascq;
        int notready, unitattn;
 
        unitattn = ATAPI_UNIT_ATTN;
@@ -327,13 +340,13 @@ unsigned char atapi_issue_autoreq(int device,
 
 retry:
        res = atapi_issue(device, ccb, ccblen, buffer, buflen);
-       if (res == 0)
+       if (!res)
                return 0;       /* Ok */
 
-       if (res == 0xFF)
-               return 0xFF;    /* error */
+       if (res == 0xff)
+               return 0xff;    /* error */
 
-       debug("(auto_req)atapi_issue returned sense key %X\n", res);
+       log_debug("(auto_req)atapi_issue returned sense key %x\n", res);
 
        memset(sense_ccb, 0, sizeof(sense_ccb));
        memset(sense_data, 0, sizeof(sense_data));
@@ -341,29 +354,29 @@ retry:
        sense_ccb[4] = 18;      /* allocation Length */
 
        res = atapi_issue(device, sense_ccb, 12, sense_data, 18);
-       key = (sense_data[2] & 0xF);
+       key = (sense_data[2] & 0xf);
        asc = (sense_data[12]);
        ascq = (sense_data[13]);
 
-       debug("ATAPI_CMD_REQ_SENSE returned %x\n", res);
-       debug(" Sense page: %02X key %02X ASC %02X ASCQ %02X\n",
-             sense_data[0], key, asc, ascq);
+       log_debug("ATAPI_CMD_REQ_SENSE returned %x\n", res);
+       log_debug(" Sense page: %02X key %02X ASC %02X ASCQ %02X\n",
+                 sense_data[0], key, asc, ascq);
 
-       if ((key == 0))
+       if (!key)
                return 0;       /* ok device ready */
 
-       if ((key == 6) || (asc == 0x29) || (asc == 0x28)) { /* Unit Attention */
+       if (key == 6 || asc == 0x29 || asc == 0x28) { /* Unit Attention */
                if (unitattn-- > 0) {
-                       udelay(200 * 1000);
+                       mdelay(200);
                        goto retry;
                }
                printf("Unit Attention, tried %d\n", ATAPI_UNIT_ATTN);
                goto error;
        }
-       if ((asc == 0x4) && (ascq == 0x1)) {
+       if (asc == 0x4 && ascq == 0x1) {
                /* not ready, but will be ready soon */
                if (notready-- > 0) {
-                       udelay(200 * 1000);
+                       mdelay(200);
                        goto retry;
                }
                printf("Drive not ready, tried %d times\n",
@@ -371,15 +384,15 @@ retry:
                goto error;
        }
        if (asc == 0x3a) {
-               debug("Media not present\n");
+               log_debug("Media not present\n");
                goto error;
        }
 
        printf("ERROR: Unknown Sense key %02X ASC %02X ASCQ %02X\n", key, asc,
               ascq);
 error:
-       debug("ERROR Sense key %02X ASC %02X ASCQ %02X\n", key, asc, ascq);
-       return 0xFF;
+       log_debug("ERROR Sense key %02X ASC %02X ASCQ %02X\n", key, asc, ascq);
+       return 0xff;
 }
 
 /*
@@ -391,16 +404,17 @@ error:
 #define ATAPI_READ_BLOCK_SIZE  2048    /* assuming CD part */
 #define ATAPI_READ_MAX_BLOCK   (ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
 
-ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
-                void *buffer)
+static ulong atapi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+                       void *buffer)
 {
-       int device = block_dev->devnum;
+       struct blk_desc *desc = dev_get_uclass_plat(dev);
+       int device = desc->devnum;
        ulong n = 0;
-       unsigned char ccb[12];  /* Command descriptor block */
+       u8 ccb[12];     /* Command descriptor block */
        ulong cnt;
 
-       debug("atapi_read dev %d start " LBAF " blocks " LBAF
-             " buffer at %lX\n", device, blknr, blkcnt, (ulong) buffer);
+       log_debug("%d start " LBAF " blocks " LBAF " buffer at %lx\n", device,
+                 blknr, blkcnt, (ulong)buffer);
 
        do {
                if (blkcnt > ATAPI_READ_MAX_BLOCK)
@@ -410,143 +424,141 @@ ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
 
                ccb[0] = ATAPI_CMD_READ_12;
                ccb[1] = 0;     /* reserved */
-               ccb[2] = (unsigned char) (blknr >> 24) & 0xFF;  /* MSB Block */
-               ccb[3] = (unsigned char) (blknr >> 16) & 0xFF;  /*  */
-               ccb[4] = (unsigned char) (blknr >> 8) & 0xFF;
-               ccb[5] = (unsigned char) blknr & 0xFF;  /* LSB Block */
-               ccb[6] = (unsigned char) (cnt >> 24) & 0xFF; /* MSB Block cnt */
-               ccb[7] = (unsigned char) (cnt >> 16) & 0xFF;
-               ccb[8] = (unsigned char) (cnt >> 8) & 0xFF;
-               ccb[9] = (unsigned char) cnt & 0xFF;    /* LSB Block */
+               ccb[2] = (u8)(blknr >> 24) & 0xff;      /* MSB Block */
+               ccb[3] = (u8)(blknr >> 16) & 0xff;      /*  */
+               ccb[4] = (u8)(blknr >> 8) & 0xff;
+               ccb[5] = (u8)blknr & 0xff;      /* LSB Block */
+               ccb[6] = (u8)(cnt >> 24) & 0xff; /* MSB Block cnt */
+               ccb[7] = (u8)(cnt >> 16) & 0xff;
+               ccb[8] = (u8)(cnt >> 8) & 0xff;
+               ccb[9] = (u8)cnt & 0xff;        /* LSB Block */
                ccb[10] = 0;    /* reserved */
                ccb[11] = 0;    /* reserved */
 
                if (atapi_issue_autoreq(device, ccb, 12,
-                                       (unsigned char *)buffer,
-                                       cnt * ATAPI_READ_BLOCK_SIZE)
-                   == 0xFF) {
+                                       (u8 *)buffer,
+                                       cnt * ATAPI_READ_BLOCK_SIZE) == 0xff)
                        return n;
-               }
                n += cnt;
                blkcnt -= cnt;
                blknr += cnt;
-               buffer += (cnt * ATAPI_READ_BLOCK_SIZE);
+               buffer += cnt * ATAPI_READ_BLOCK_SIZE;
        } while (blkcnt > 0);
        return n;
 }
 
-static void atapi_inquiry(struct blk_desc *dev_desc)
+static void atapi_inquiry(struct blk_desc *desc)
 {
-       unsigned char ccb[12];  /* Command descriptor block */
-       unsigned char iobuf[64];        /* temp buf */
-       unsigned char c;
+       u8 ccb[12];     /* Command descriptor block */
+       u8 iobuf[64];   /* temp buf */
+       u8 c;
        int device;
 
-       device = dev_desc->devnum;
-       dev_desc->type = DEV_TYPE_UNKNOWN;      /* not yet valid */
+       device = desc->devnum;
+       desc->type = DEV_TYPE_UNKNOWN;  /* not yet valid */
 
        memset(ccb, 0, sizeof(ccb));
        memset(iobuf, 0, sizeof(iobuf));
 
        ccb[0] = ATAPI_CMD_INQUIRY;
        ccb[4] = 40;            /* allocation Legnth */
-       c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 40);
+       c = atapi_issue_autoreq(device, ccb, 12, (u8 *)iobuf, 40);
 
-       debug("ATAPI_CMD_INQUIRY returned %x\n", c);
-       if (c != 0)
+       log_debug("ATAPI_CMD_INQUIRY returned %x\n", c);
+       if (c)
                return;
 
        /* copy device ident strings */
-       ident_cpy((unsigned char *)dev_desc->vendor, &iobuf[8], 8);
-       ident_cpy((unsigned char *)dev_desc->product, &iobuf[16], 16);
-       ident_cpy((unsigned char *)dev_desc->revision, &iobuf[32], 5);
-
-       dev_desc->lun = 0;
-       dev_desc->lba = 0;
-       dev_desc->blksz = 0;
-       dev_desc->log2blksz = LOG2_INVALID(typeof(dev_desc->log2blksz));
-       dev_desc->type = iobuf[0] & 0x1f;
-
-       if ((iobuf[1] & 0x80) == 0x80)
-               dev_desc->removable = 1;
+       ident_cpy((u8 *)desc->vendor, &iobuf[8], 8);
+       ident_cpy((u8 *)desc->product, &iobuf[16], 16);
+       ident_cpy((u8 *)desc->revision, &iobuf[32], 5);
+
+       desc->lun = 0;
+       desc->lba = 0;
+       desc->blksz = 0;
+       desc->log2blksz = LOG2_INVALID(typeof(desc->log2blksz));
+       desc->type = iobuf[0] & 0x1f;
+
+       if (iobuf[1] & 0x80)
+               desc->removable = 1;
        else
-               dev_desc->removable = 0;
+               desc->removable = 0;
 
        memset(ccb, 0, sizeof(ccb));
        memset(iobuf, 0, sizeof(iobuf));
        ccb[0] = ATAPI_CMD_START_STOP;
        ccb[4] = 0x03;          /* start */
 
-       c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
+       c = atapi_issue_autoreq(device, ccb, 12, (u8 *)iobuf, 0);
 
-       debug("ATAPI_CMD_START_STOP returned %x\n", c);
-       if (c != 0)
+       log_debug("ATAPI_CMD_START_STOP returned %x\n", c);
+       if (c)
                return;
 
        memset(ccb, 0, sizeof(ccb));
        memset(iobuf, 0, sizeof(iobuf));
-       c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
+       c = atapi_issue_autoreq(device, ccb, 12, (u8 *)iobuf, 0);
 
-       debug("ATAPI_CMD_UNIT_TEST_READY returned %x\n", c);
-       if (c != 0)
+       log_debug("ATAPI_CMD_UNIT_TEST_READY returned %x\n", c);
+       if (c)
                return;
 
        memset(ccb, 0, sizeof(ccb));
        memset(iobuf, 0, sizeof(iobuf));
        ccb[0] = ATAPI_CMD_READ_CAP;
-       c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 8);
-       debug("ATAPI_CMD_READ_CAP returned %x\n", c);
-       if (c != 0)
+       c = atapi_issue_autoreq(device, ccb, 12, (u8 *)iobuf, 8);
+       log_debug("ATAPI_CMD_READ_CAP returned %x\n", c);
+       if (c)
                return;
 
-       debug("Read Cap: LBA %02X%02X%02X%02X blksize %02X%02X%02X%02X\n",
-             iobuf[0], iobuf[1], iobuf[2], iobuf[3],
-             iobuf[4], iobuf[5], iobuf[6], iobuf[7]);
-
-       dev_desc->lba = ((unsigned long) iobuf[0] << 24) +
-               ((unsigned long) iobuf[1] << 16) +
-               ((unsigned long) iobuf[2] << 8) + ((unsigned long) iobuf[3]);
-       dev_desc->blksz = ((unsigned long) iobuf[4] << 24) +
-               ((unsigned long) iobuf[5] << 16) +
-               ((unsigned long) iobuf[6] << 8) + ((unsigned long) iobuf[7]);
-       dev_desc->log2blksz = LOG2(dev_desc->blksz);
-#ifdef CONFIG_LBA48
+       log_debug("Read Cap: LBA %02X%02X%02X%02X blksize %02X%02X%02X%02X\n",
+                 iobuf[0], iobuf[1], iobuf[2], iobuf[3],
+                 iobuf[4], iobuf[5], iobuf[6], iobuf[7]);
+
+       desc->lba = (ulong)iobuf[0] << 24 | (ulong)iobuf[1] << 16 |
+               (ulong)iobuf[2] << 8 | (ulong)iobuf[3];
+       desc->blksz = (ulong)iobuf[4] << 24 | (ulong)iobuf[5] << 16 |
+               (ulong)iobuf[6] << 8 | (ulong)iobuf[7];
+       desc->log2blksz = LOG2(desc->blksz);
+
        /* ATAPI devices cannot use 48bit addressing (ATA/ATAPI v7) */
-       dev_desc->lba48 = 0;
-#endif
-       return;
+       desc->lba48 = false;
 }
 
-#endif /* CONFIG_ATAPI */
-
-static void ide_ident(struct blk_desc *dev_desc)
+/**
+ * ide_ident() - Identify an IDE device
+ *
+ * @device: Device number to use
+ * @desc: Block descriptor to fill in
+ * Returns: 0 if OK, -ENOENT if no device is found
+ */
+static int ide_ident(int device, struct blk_desc *desc)
 {
-       unsigned char c;
        hd_driveid_t iop;
-#ifdef CONFIG_ATAPI
        bool is_atapi = false;
-       int retries = 0;
-#endif
-       int device;
-
-       device = dev_desc->devnum;
+       int tries = 1;
+       u8 c;
+
+       memset(desc, '\0', sizeof(*desc));
+       desc->devnum = device;
+       desc->type = DEV_TYPE_UNKNOWN;
+       desc->uclass_id = UCLASS_IDE;
+       desc->log2blksz = LOG2_INVALID(typeof(desc->log2blksz));
        printf("  Device %d: ", device);
 
        /* Select device
         */
        ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-       dev_desc->uclass_id = UCLASS_IDE;
-#ifdef CONFIG_ATAPI
+       if (IS_ENABLED(CONFIG_ATAPI))
+               tries = 2;
 
-       retries = 0;
-
-       /* Warning: This will be tricky to read */
-       while (retries <= 1) {
+       while (tries) {
                /* check signature */
-               if ((ide_inb(device, ATA_SECT_CNT) == 0x01) &&
-                   (ide_inb(device, ATA_SECT_NUM) == 0x01) &&
-                   (ide_inb(device, ATA_CYL_LOW) == 0x14) &&
-                   (ide_inb(device, ATA_CYL_HIGH) == 0xEB)) {
+               if (IS_ENABLED(CONFIG_ATAPI) &&
+                   ide_inb(device, ATA_SECT_CNT) == 0x01 &&
+                   ide_inb(device, ATA_SECT_NUM) == 0x01 &&
+                   ide_inb(device, ATA_CYL_LOW) == 0x14 &&
+                   ide_inb(device, ATA_CYL_HIGH) == 0xeb) {
                        /* ATAPI Signature found */
                        is_atapi = true;
                        /*
@@ -558,9 +570,7 @@ static void ide_ident(struct blk_desc *dev_desc)
                         * to become ready
                         */
                        c = ide_wait(device, ATAPI_TIME_OUT);
-               } else
-#endif
-               {
+               } else {
                        /*
                         * Start Ident Command
                         */
@@ -572,86 +582,70 @@ static void ide_ident(struct blk_desc *dev_desc)
                        c = ide_wait(device, IDE_TIME_OUT);
                }
 
-               if (((c & ATA_STAT_DRQ) == 0) ||
-                   ((c & (ATA_STAT_FAULT | ATA_STAT_ERR)) != 0)) {
-#ifdef CONFIG_ATAPI
-                       {
-                               /*
-                                * Need to soft reset the device
-                                * in case it's an ATAPI...
-                                */
-                               debug("Retrying...\n");
-                               ide_outb(device, ATA_DEV_HD,
-                                        ATA_LBA | ATA_DEVICE(device));
-                               udelay(100000);
-                               ide_outb(device, ATA_COMMAND, 0x08);
-                               udelay(500000); /* 500 ms */
-                       }
+               if ((c & ATA_STAT_DRQ) &&
+                   !(c & (ATA_STAT_FAULT | ATA_STAT_ERR))) {
+                       break;
+               } else if (IS_ENABLED(CONFIG_ATAPI)) {
                        /*
-                        * Select device
+                        * Need to soft reset the device
+                        * in case it's an ATAPI...
                         */
+                       log_debug("Retrying...\n");
+                       ide_outb(device, ATA_DEV_HD,
+                                ATA_LBA | ATA_DEVICE(device));
+                       mdelay(100);
+                       ide_outb(device, ATA_COMMAND, 0x08);
+                       mdelay(500);
+                       /* Select device */
                        ide_outb(device, ATA_DEV_HD,
                                 ATA_LBA | ATA_DEVICE(device));
-                       retries++;
-#else
-                       return;
-#endif
                }
-#ifdef CONFIG_ATAPI
-               else
-                       break;
-       }                       /* see above - ugly to read */
+               tries--;
+       }
 
-       if (retries == 2)       /* Not found */
-               return;
-#endif
+       if (!tries)     /* Not found */
+               return -ENOENT;
 
        ide_input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS);
 
-       ident_cpy((unsigned char *)dev_desc->revision, iop.fw_rev,
-                 sizeof(dev_desc->revision));
-       ident_cpy((unsigned char *)dev_desc->vendor, iop.model,
-                 sizeof(dev_desc->vendor));
-       ident_cpy((unsigned char *)dev_desc->product, iop.serial_no,
-                 sizeof(dev_desc->product));
+       ident_cpy((u8 *)desc->revision, iop.fw_rev, sizeof(desc->revision));
+       ident_cpy((u8 *)desc->vendor, iop.model, sizeof(desc->vendor));
+       ident_cpy((u8 *)desc->product, iop.serial_no, sizeof(desc->product));
 
-       if ((iop.config & 0x0080) == 0x0080)
-               dev_desc->removable = 1;
+       if (iop.config & 0x0080)
+               desc->removable = 1;
        else
-               dev_desc->removable = 0;
+               desc->removable = 0;
 
-#ifdef CONFIG_ATAPI
-       if (is_atapi) {
-               atapi_inquiry(dev_desc);
-               return;
+       if (IS_ENABLED(CONFIG_ATAPI) && is_atapi) {
+               desc->atapi = true;
+               atapi_inquiry(desc);
+               return 0;
        }
-#endif /* CONFIG_ATAPI */
 
        iop.lba_capacity[0] = be16_to_cpu(iop.lba_capacity[0]);
        iop.lba_capacity[1] = be16_to_cpu(iop.lba_capacity[1]);
-       dev_desc->lba =
-                       ((unsigned long)iop.lba_capacity[0]) |
-                       ((unsigned long)iop.lba_capacity[1] << 16);
+       desc->lba = (ulong)iop.lba_capacity[0] |
+               (ulong)iop.lba_capacity[1] << 16;
 
-#ifdef CONFIG_LBA48
-       if (iop.command_set_2 & 0x0400) {       /* LBA 48 support */
-               dev_desc->lba48 = 1;
+       if (IS_ENABLED(CONFIG_LBA48) && (iop.command_set_2 & 0x0400)) {
+               /* LBA 48 support */
+               desc->lba48 = true;
                for (int i = 0; i < 4; i++)
                        iop.lba48_capacity[i] = be16_to_cpu(iop.lba48_capacity[i]);
-               dev_desc->lba =
-                       ((unsigned long long)iop.lba48_capacity[0] |
-                       ((unsigned long long)iop.lba48_capacity[1] << 16) |
-                       ((unsigned long long)iop.lba48_capacity[2] << 32) |
-                       ((unsigned long long)iop.lba48_capacity[3] << 48));
+               desc->lba = (unsigned long long)iop.lba48_capacity[0] |
+                       (unsigned long long)iop.lba48_capacity[1] << 16 |
+                       (unsigned long long)iop.lba48_capacity[2] << 32 |
+                       (unsigned long long)iop.lba48_capacity[3] << 48;
        } else {
-               dev_desc->lba48 = 0;
+               desc->lba48 = false;
        }
-#endif /* CONFIG_LBA48 */
+
        /* assuming HD */
-       dev_desc->type = DEV_TYPE_HARDDISK;
-       dev_desc->blksz = ATA_BLOCKSIZE;
-       dev_desc->log2blksz = LOG2(dev_desc->blksz);
-       dev_desc->lun = 0;      /* just to fill something in... */
+       desc->type = DEV_TYPE_HARDDISK;
+       desc->blksz = ATA_BLOCKSIZE;
+       desc->log2blksz = LOG2(desc->blksz);
+       desc->lun = 0;  /* just to fill something in... */
 
 #if 0                          /* only used to test the powersaving mode,
                                 * if enabled, the drive goes after 5 sec
@@ -667,123 +661,58 @@ static void ide_ident(struct blk_desc *dev_desc)
        udelay(50);
        c = ide_wait(device, IDE_TIME_OUT);     /* can't take over 500 ms */
 #endif
-}
 
-__weak void ide_outb(int dev, int port, unsigned char val)
-{
-       debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
-             dev, port, val, ATA_CURR_BASE(dev) + port);
-
-       outb(val, ATA_CURR_BASE(dev) + port);
-}
-
-__weak unsigned char ide_inb(int dev, int port)
-{
-       uchar val;
-
-       val = inb(ATA_CURR_BASE(dev) + port);
-
-       debug("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
-             dev, port, ATA_CURR_BASE(dev) + port, val);
-       return val;
+       return 0;
 }
 
-void ide_init(void)
+/**
+ * ide_init_one() - Init one IDE device
+ *
+ * @bus: Bus to use
+ * Return: 0 iuf OK, -EIO if not available, -ETIMEDOUT if timed out
+ */
+static int ide_init_one(int bus)
 {
-       struct udevice *dev;
-       unsigned char c;
-       int i, bus;
-
-       schedule();
-
-       /* ATAPI Drives seems to need a proper IDE Reset */
-       ide_reset();
-
-       /*
-        * Wait for IDE to get ready.
-        * According to spec, this can take up to 31 seconds!
-        */
-       for (bus = 0; bus < CONFIG_SYS_IDE_MAXBUS; ++bus) {
-               int dev =
-                       bus * (CONFIG_SYS_IDE_MAXDEVICE /
-                              CONFIG_SYS_IDE_MAXBUS);
+       int dev = bus * CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS;
+       int i;
+       u8 c;
 
-               printf("Bus %d: ", bus);
+       printf("Bus %d: ", bus);
 
-               ide_bus_ok[bus] = 0;
+       /* Select device */
+       mdelay(100);
+       ide_outb(dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev));
+       mdelay(100);
+       i = 0;
+       do {
+               mdelay(10);
 
-               /* Select device
-                */
-               udelay(100000); /* 100 ms */
-               ide_outb(dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev));
-               udelay(100000); /* 100 ms */
-               i = 0;
-               do {
-                       udelay(10000);  /* 10 ms */
-
-                       c = ide_inb(dev, ATA_STATUS);
-                       i++;
-                       if (i > (ATA_RESET_TIME * 100)) {
-                               puts("** Timeout **\n");
-                               return;
-                       }
-                       if ((i >= 100) && ((i % 100) == 0))
-                               putc('.');
-
-               } while (c & ATA_STAT_BUSY);
-
-               if (c & (ATA_STAT_BUSY | ATA_STAT_FAULT)) {
-                       puts("not available  ");
-                       debug("Status = 0x%02X ", c);
-#ifndef CONFIG_ATAPI           /* ATAPI Devices do not set DRDY */
-               } else if ((c & ATA_STAT_READY) == 0) {
-                       puts("not available  ");
-                       debug("Status = 0x%02X ", c);
-#endif
-               } else {
-                       puts("OK ");
-                       ide_bus_ok[bus] = 1;
+               c = ide_inb(dev, ATA_STATUS);
+               i++;
+               if (i > (ATA_RESET_TIME * 100)) {
+                       puts("** Timeout **\n");
+                       return -ETIMEDOUT;
                }
-               schedule();
-       }
-
-       putc('\n');
-
-       for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
-               ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
-               ide_dev_desc[i].uclass_id = UCLASS_IDE;
-               ide_dev_desc[i].devnum = i;
-               ide_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
-               ide_dev_desc[i].blksz = 0;
-               ide_dev_desc[i].log2blksz =
-                       LOG2_INVALID(typeof(ide_dev_desc[i].log2blksz));
-               ide_dev_desc[i].lba = 0;
-               if (!ide_bus_ok[IDE_BUS(i)])
-                       continue;
-               ide_ident(&ide_dev_desc[i]);
-               dev_print(&ide_dev_desc[i]);
+               if (i >= 100 && !(i % 100))
+                       putc('.');
+       } while (c & ATA_STAT_BUSY);
+
+       if (c & (ATA_STAT_BUSY | ATA_STAT_FAULT)) {
+               puts("not available  ");
+               log_debug("Status = %#02X ", c);
+               return -EIO;
+       } else if (IS_ENABLED(CONFIG_ATAPI) && !(c & ATA_STAT_READY)) {
+               /* ATAPI Devices do not set DRDY */
+               puts("not available  ");
+               log_debug("Status = %#02X ", c);
+               return -EIO;
        }
-       schedule();
-
-       uclass_first_device(UCLASS_IDE, &dev);
-}
+       puts("OK ");
 
-__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
-{
-       uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG);
-       ushort *dbuf = (ushort *)sect_buf;
-
-       debug("in input swap data base for read is %p\n", (void *)paddr);
-
-       while (words--) {
-               EIEIO;
-               *dbuf++ = be16_to_cpu(inw(paddr));
-               EIEIO;
-               *dbuf++ = be16_to_cpu(inw(paddr));
-       }
+       return 0;
 }
 
-__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
+static void ide_output_data(int dev, const ulong *sect_buf, int words)
 {
        uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG);
        ushort *dbuf;
@@ -797,14 +726,14 @@ __weak void ide_output_data(int dev, const ulong *sect_buf, int words)
        }
 }
 
-__weak void ide_input_data(int dev, ulong *sect_buf, int words)
+static void ide_input_data(int dev, ulong *sect_buf, int words)
 {
        uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG);
        ushort *dbuf;
 
        dbuf = (ushort *)sect_buf;
 
-       debug("in input data base for read is %p\n", (void *)paddr);
+       log_debug("in input data base for read is %p\n", (void *)paddr);
 
        while (words--) {
                EIEIO;
@@ -814,25 +743,23 @@ __weak void ide_input_data(int dev, ulong *sect_buf, int words)
        }
 }
 
-ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
-              void *buffer)
+static ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+                     void *buffer)
 {
-       struct blk_desc *block_dev = dev_get_uclass_plat(dev);
-       int device = block_dev->devnum;
+       struct blk_desc *desc = dev_get_uclass_plat(dev);
+       int device = desc->devnum;
+       bool lba48 = false;
        ulong n = 0;
-       unsigned char c;
-       unsigned char pwrsave = 0;      /* power save */
-
-#ifdef CONFIG_LBA48
-       unsigned char lba48 = 0;
+       u8 pwrsave = 0; /* power save */
+       u8 c;
 
-       if (blknr & 0x0000fffff0000000ULL) {
+       if (IS_ENABLED(CONFIG_LBA48) && (blknr & 0x0000fffff0000000ULL)) {
                /* more than 28 bits used, use 48bit mode */
-               lba48 = 1;
+               lba48 = true;
        }
-#endif
-       debug("ide_read dev %d start " LBAF ", blocks " LBAF " buffer at %lX\n",
-             device, blknr, blkcnt, (ulong) buffer);
+
+       log_debug("dev %d start " LBAF ", blocks " LBAF " buffer at %lx\n",
+                 device, blknr, blkcnt, (ulong)buffer);
 
        /* Select device
         */
@@ -856,11 +783,11 @@ ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
                goto IDE_READ_E;
        }
        if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
-               printf("No Powersaving mode %X\n", c);
+               printf("No Powersaving mode %x\n", c);
        } else {
                c = ide_inb(device, ATA_SECT_CNT);
-               debug("Powersaving %02X\n", c);
-               if (c == 0)
+               log_debug("Powersaving %02X\n", c);
+               if (!c)
                        pwrsave = 1;
        }
 
@@ -872,36 +799,31 @@ ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
                        printf("IDE read: device %d not ready\n", device);
                        break;
                }
-#ifdef CONFIG_LBA48
-               if (lba48) {
+               if (IS_ENABLED(CONFIG_LBA48) && lba48) {
                        /* write high bits */
                        ide_outb(device, ATA_SECT_CNT, 0);
-                       ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
+                       ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xff);
 #ifdef CONFIG_SYS_64BIT_LBA
-                       ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
-                       ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
+                       ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xff);
+                       ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xff);
 #else
                        ide_outb(device, ATA_LBA_MID, 0);
                        ide_outb(device, ATA_LBA_HIGH, 0);
 #endif
                }
-#endif
                ide_outb(device, ATA_SECT_CNT, 1);
-               ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
-               ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
-               ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
+               ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xff);
+               ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xff);
+               ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xff);
 
-#ifdef CONFIG_LBA48
-               if (lba48) {
+               if (IS_ENABLED(CONFIG_LBA48) && lba48) {
                        ide_outb(device, ATA_DEV_HD,
                                 ATA_LBA | ATA_DEVICE(device));
                        ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_READ_EXT);
 
-               } else
-#endif
-               {
+               } else {
                        ide_outb(device, ATA_DEV_HD, ATA_LBA |
-                                ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
+                                ATA_DEVICE(device) | ((blknr >> 24) & 0xf));
                        ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_READ);
                }
 
@@ -934,22 +856,19 @@ IDE_READ_E:
        return n;
 }
 
-ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
-               const void *buffer)
+static ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+                      const void *buffer)
 {
-       struct blk_desc *block_dev = dev_get_uclass_plat(dev);
-       int device = block_dev->devnum;
+       struct blk_desc *desc = dev_get_uclass_plat(dev);
+       int device = desc->devnum;
        ulong n = 0;
-       unsigned char c;
+       bool lba48 = false;
+       u8 c;
 
-#ifdef CONFIG_LBA48
-       unsigned char lba48 = 0;
-
-       if (blknr & 0x0000fffff0000000ULL) {
+       if (IS_ENABLED(CONFIG_LBA48) && (blknr & 0x0000fffff0000000ULL)) {
                /* more than 28 bits used, use 48bit mode */
-               lba48 = 1;
+               lba48 = true;
        }
-#endif
 
        /* Select device
         */
@@ -962,36 +881,31 @@ ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
                        printf("IDE read: device %d not ready\n", device);
                        goto WR_OUT;
                }
-#ifdef CONFIG_LBA48
-               if (lba48) {
+               if (IS_ENABLED(CONFIG_LBA48) && lba48) {
                        /* write high bits */
                        ide_outb(device, ATA_SECT_CNT, 0);
-                       ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
+                       ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xff);
 #ifdef CONFIG_SYS_64BIT_LBA
-                       ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
-                       ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
+                       ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xff);
+                       ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xff);
 #else
                        ide_outb(device, ATA_LBA_MID, 0);
                        ide_outb(device, ATA_LBA_HIGH, 0);
 #endif
                }
-#endif
                ide_outb(device, ATA_SECT_CNT, 1);
-               ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
-               ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
-               ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
+               ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xff);
+               ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xff);
+               ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xff);
 
-#ifdef CONFIG_LBA48
-               if (lba48) {
+               if (IS_ENABLED(CONFIG_LBA48) && lba48) {
                        ide_outb(device, ATA_DEV_HD,
                                 ATA_LBA | ATA_DEVICE(device));
                        ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_WRITE_EXT);
 
-               } else
-#endif
-               {
+               } else {
                        ide_outb(device, ATA_DEV_HD, ATA_LBA |
-                                ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
+                                ATA_DEVICE(device) | ((blknr >> 24) & 0xf));
                        ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_WRITE);
                }
 
@@ -1017,35 +931,19 @@ WR_OUT:
        return n;
 }
 
-#if defined(CONFIG_OF_IDE_FIXUP)
-int ide_device_present(int dev)
+ulong ide_or_atapi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+                       void *buffer)
 {
-       if (dev >= CONFIG_SYS_IDE_MAXBUS)
-               return 0;
-       return ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN ? 0 : 1;
-}
-#endif
+       struct blk_desc *desc = dev_get_uclass_plat(dev);
 
-static int ide_blk_probe(struct udevice *udev)
-{
-       struct blk_desc *desc = dev_get_uclass_plat(udev);
-
-       /* fill in device vendor/product/rev strings */
-       strncpy(desc->vendor, ide_dev_desc[desc->devnum].vendor,
-               BLK_VEN_SIZE);
-       desc->vendor[BLK_VEN_SIZE] = '\0';
-       strncpy(desc->product, ide_dev_desc[desc->devnum].product,
-               BLK_PRD_SIZE);
-       desc->product[BLK_PRD_SIZE] = '\0';
-       strncpy(desc->revision, ide_dev_desc[desc->devnum].revision,
-               BLK_REV_SIZE);
-       desc->revision[BLK_REV_SIZE] = '\0';
+       if (IS_ENABLED(CONFIG_ATAPI) && desc->atapi)
+               return atapi_read(dev, blknr, blkcnt, buffer);
 
-       return 0;
+       return ide_read(dev, blknr, blkcnt, buffer);
 }
 
 static const struct blk_ops ide_blk_ops = {
-       .read   = ide_read,
+       .read   = ide_or_atapi_read,
        .write  = ide_write,
 };
 
@@ -1053,7 +951,6 @@ U_BOOT_DRIVER(ide_blk) = {
        .name           = "ide_blk",
        .id             = UCLASS_BLK,
        .ops            = &ide_blk_ops,
-       .probe          = ide_blk_probe,
 };
 
 static int ide_bootdev_bind(struct udevice *dev)
@@ -1067,7 +964,9 @@ static int ide_bootdev_bind(struct udevice *dev)
 
 static int ide_bootdev_hunt(struct bootdev_hunter *info, bool show)
 {
-       ide_init();
+       struct udevice *dev;
+
+       uclass_first_device(UCLASS_IDE, &dev);
 
        return 0;
 }
@@ -1097,40 +996,72 @@ BOOTDEV_HUNTER(ide_bootdev_hunter) = {
 
 static int ide_probe(struct udevice *udev)
 {
-       struct udevice *blk_dev;
-       char name[20];
-       int blksz;
-       lbaint_t size;
-       int i;
-       int ret;
+       bool bus_ok[CONFIG_SYS_IDE_MAXBUS];
+       int i, bus;
+
+       schedule();
+
+       /* ATAPI Drives seems to need a proper IDE Reset */
+       ide_reset();
+
+       /*
+        * Wait for IDE to get ready.
+        * According to spec, this can take up to 31 seconds!
+        */
+       for (bus = 0; bus < CONFIG_SYS_IDE_MAXBUS; ++bus) {
+               bus_ok[bus] = !ide_init_one(bus);
+               schedule();
+       }
+
+       putc('\n');
+
+       schedule();
 
        for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; i++) {
-               if (ide_dev_desc[i].type != DEV_TYPE_UNKNOWN) {
-                       sprintf(name, "blk#%d", i);
+               struct blk_desc *desc, pdesc;
+               struct udevice *blk;
+               char name[20];
+               int ret;
 
-                       blksz = ide_dev_desc[i].blksz;
-                       size = blksz * ide_dev_desc[i].lba;
+               if (!bus_ok[IDE_BUS(i)])
+                       continue;
 
-                       /*
-                        * With CDROM, if there is no CD inserted, blksz will
-                        * be zero, don't bother to create IDE block device.
-                        */
-                       if (!blksz)
-                               continue;
-                       ret = blk_create_devicef(udev, "ide_blk", name,
-                                                UCLASS_IDE, i,
-                                                blksz, size, &blk_dev);
-                       if (ret)
-                               return ret;
-
-                       ret = blk_probe_or_unbind(blk_dev);
-                       if (ret)
-                               return ret;
-
-                       ret = bootdev_setup_for_dev(udev, "ide_bootdev");
-                       if (ret)
-                               return log_msg_ret("bootdev", ret);
-               }
+               ret = ide_ident(i, &pdesc);
+               dev_print(&pdesc);
+
+               if (ret)
+                       continue;
+
+               sprintf(name, "blk#%d", i);
+
+               /*
+                * With CDROM, if there is no CD inserted, blksz will
+                * be zero, don't bother to create IDE block device.
+                */
+               if (!pdesc.blksz)
+                       continue;
+               ret = blk_create_devicef(udev, "ide_blk", name, UCLASS_IDE, i,
+                                        pdesc.blksz, pdesc.lba, &blk);
+               if (ret)
+                       return ret;
+
+               ret = blk_probe_or_unbind(blk);
+               if (ret)
+                       return ret;
+
+               /* fill in device vendor/product/rev strings */
+               desc = dev_get_uclass_plat(blk);
+               strlcpy(desc->vendor, pdesc.vendor, BLK_VEN_SIZE);
+               strlcpy(desc->product, pdesc.product, BLK_PRD_SIZE);
+               strlcpy(desc->revision, pdesc.revision, BLK_REV_SIZE);
+               desc->removable = pdesc.removable;
+               desc->atapi = pdesc.atapi;
+               desc->lba48 = pdesc.lba48;
+               desc->type = pdesc.type;
+
+               ret = bootdev_setup_for_dev(udev, "ide_bootdev");
+               if (ret)
+                       return log_msg_ret("bootdev", ret);
        }
 
        return 0;

diff --git a/drivers/cache/cache-sifive-ccache.c b/drivers/cache/cache-sifive-ccache.c
index c8766f6..521df40 100644 (file)
--- a/drivers/cache/cache-sifive-ccache.c
+++ b/drivers/cache/cache-sifive-ccache.c
@@ -62,6 +62,7 @@ static int sifive_ccache_probe(struct udevice *dev)
 static const struct udevice_id sifive_ccache_ids[] = {
        { .compatible = "sifive,fu540-c000-ccache" },
        { .compatible = "sifive,fu740-c000-ccache" },
+       { .compatible = "sifive,ccache0" },
        {}
 };
 

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 42280cb..3ad5af9 100644 (file)
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -166,6 +166,14 @@ config CLK_SCMI
          by a SCMI agent based on SCMI clock protocol communication
          with a SCMI server.
 
+config SPL_CLK_SCMI
+       bool "Enable SCMI clock driver in SPL"
+       depends on SCMI_FIRMWARE && SPL_FIRMWARE
+       help
+         Enable this option if you want to support clock devices exposed
+         by a SCMI agent based on SCMI clock protocol communication
+         with a SCMI server in SPL.
+
 config CLK_HSDK
        bool "Enable cgu clock driver for HSDK boards"
        depends on CLK && TARGET_HSDK
@@ -235,6 +243,7 @@ source "drivers/clk/owl/Kconfig"
 source "drivers/clk/renesas/Kconfig"
 source "drivers/clk/sunxi/Kconfig"
 source "drivers/clk/sifive/Kconfig"
+source "drivers/clk/starfive/Kconfig"
 source "drivers/clk/stm32/Kconfig"
 source "drivers/clk/tegra/Kconfig"
 source "drivers/clk/ti/Kconfig"

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index c274cda..e22c8cf 100644 (file)
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o
 
 obj-y += analogbits/
 obj-y += imx/
+obj-$(CONFIG_CLK_JH7110) += starfive/
 obj-y += tegra/
 obj-y += ti/
 obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
@@ -39,7 +40,7 @@ obj-$(CONFIG_CLK_MVEBU) += mvebu/
 obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
 obj-$(CONFIG_CLK_OWL) += owl/
 obj-$(CONFIG_CLK_RENESAS) += renesas/
-obj-$(CONFIG_CLK_SCMI) += clk_scmi.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o
 obj-$(CONFIG_CLK_SIFIVE) += sifive/
 obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
 obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index d58e897..45671c6 100644 (file)
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -45,13 +45,13 @@ config CLK_R8A7794
          Enable this to support the clocks on Renesas R8A7794 SoC.
 
 config CLK_RCAR_GEN3
-       bool "Renesas RCar Gen3 clock driver"
-       def_bool y if RCAR_GEN3
+       bool "Renesas RCar Gen3 and Gen4 clock driver"
+       def_bool y if RCAR_64
        depends on CLK_RENESAS
        select CLK_RCAR_CPG_LIB
        select DM_RESET
        help
-         Enable this to support the clocks on Renesas RCar Gen3 SoC.
+         Enable this to support the clocks on Renesas RCar Gen3 and Gen4 SoCs.
 
 config CLK_R8A774A1
         bool "Renesas R8A774A1 clock driver"
@@ -131,3 +131,15 @@ config CLK_R8A779A0
        depends on CLK_RCAR_GEN3
        help
          Enable this to support the clocks on Renesas R8A779A0 SoC.
+
+config CLK_R8A779F0
+       bool "Renesas R8A779F0 clock driver"
+       depends on CLK_RCAR_GEN3
+       help
+         Enable this to support the clocks on Renesas R8A779F0 SoC.
+
+config CLK_R8A779G0
+       bool "Renesas R8A779G0 clock driver"
+       depends on CLK_RCAR_GEN3
+       help
+         Enable this to support the clocks on Renesas R8A779G0 SoC.

diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 8f82a7a..fe0391e 100644 (file)
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -20,3 +20,5 @@ obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o

diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index 1697867..c8a5512 100644 (file)
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -35,10 +35,16 @@
 #define CPG_PLL2CR             0x002c
 #define CPG_PLL4CR             0x01f4
 
-static const struct clk_div_table cpg_rpcsrc_div_table[] = {
+#define SD0CKCR1               0x08a4
+
+static const struct clk_div_table gen3_cpg_rpcsrc_div_table[] = {
        { 2, 5 }, { 3, 6 }, { 0, 0 },
 };
 
+static const struct clk_div_table gen4_cpg_rpcsrc_div_table[] = {
+       { 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 },
+};
+
 static const struct clk_div_table r8a77970_cpg_sd0h_div_table[] = {
        {  0,  2 }, {  1,  3 }, {  2,  4 }, {  3,  6 },
        {  4,  8 }, {  5, 12 }, {  6, 16 }, {  7, 18 },
@@ -181,8 +187,10 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
        struct cpg_mssr_info *info = priv->info;
        struct clk parent;
        const struct cpg_core_clk *core;
-       const struct rcar_gen3_cpg_pll_config *pll_config =
-                                       priv->cpg_pll_config;
+       const struct rcar_gen3_cpg_pll_config *gen3_pll_config =
+                                       priv->gen3_cpg_pll_config;
+       const struct rcar_gen4_cpg_pll_config *gen4_pll_config =
+                                       priv->gen4_cpg_pll_config;
        u32 value, div;
        u64 rate = 0;
        u8 shift;
@@ -227,7 +235,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
 
        case CLK_TYPE_GEN3_MAIN:
                return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
-                                               0, 1, pll_config->extal_div,
+                                               0, 1, gen3_pll_config->extal_div,
                                                "MAIN");
 
        case CLK_TYPE_GEN3_PLL0:
@@ -236,8 +244,9 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
 
        case CLK_TYPE_GEN3_PLL1:
                return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
-                                               0, pll_config->pll1_mult,
-                                               pll_config->pll1_div, "PLL1");
+                                               0, gen3_pll_config->pll1_mult,
+                                               gen3_pll_config->pll1_div,
+                                               "PLL1");
 
        case CLK_TYPE_GEN3_PLL2:
                return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
@@ -245,8 +254,9 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
 
        case CLK_TYPE_GEN3_PLL3:
                return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
-                                               0, pll_config->pll3_mult,
-                                               pll_config->pll3_div, "PLL3");
+                                               0, gen3_pll_config->pll3_mult,
+                                               gen3_pll_config->pll3_div,
+                                               "PLL3");
 
        case CLK_TYPE_GEN3_PLL4:
                return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
@@ -254,25 +264,48 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
 
        case CLK_TYPE_GEN4_MAIN:
                return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
-                                               0, 1, pll_config->extal_div,
-                                               "V3U_MAIN");
+                                               0, 1, gen4_pll_config->extal_div,
+                                               "MAIN");
 
        case CLK_TYPE_GEN4_PLL1:
                return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
-                                               0, pll_config->pll1_mult,
-                                               pll_config->pll1_div,
-                                               "V3U_PLL1");
+                                               0, gen4_pll_config->pll1_mult,
+                                               gen4_pll_config->pll1_div,
+                                               "PLL1");
+
+       case CLK_TYPE_GEN4_PLL2:
+               return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
+                                               0, gen4_pll_config->pll2_mult,
+                                               gen4_pll_config->pll2_div,
+                                               "PLL2");
 
        case CLK_TYPE_GEN4_PLL2X_3X:
                return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
-                                               core->offset, 0, 0,
-                                               "V3U_PLL2X_3X");
+                                               core->offset, 0, 0, "PLL2X_3X");
+
+       case CLK_TYPE_GEN4_PLL3:
+               return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
+                                               0, gen4_pll_config->pll3_mult,
+                                               gen4_pll_config->pll3_div,
+                                               "PLL3");
+
+       case CLK_TYPE_GEN4_PLL4:
+               return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
+                                               0, gen4_pll_config->pll4_mult,
+                                               gen4_pll_config->pll4_div,
+                                               "PLL4");
 
        case CLK_TYPE_GEN4_PLL5:
                return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
-                                               0, pll_config->pll5_mult,
-                                               pll_config->pll5_div,
-                                               "V3U_PLL5");
+                                               0, gen4_pll_config->pll5_mult,
+                                               gen4_pll_config->pll5_div,
+                                               "PLL5");
+
+       case CLK_TYPE_GEN4_PLL6:
+               return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
+                                               0, gen4_pll_config->pll6_mult,
+                                               gen4_pll_config->pll6_div,
+                                               "PLL6");
 
        case CLK_TYPE_FF:
                return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
@@ -288,6 +321,13 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
                      div, rate);
                return rate;
 
+       case CLK_TYPE_GEN4_SDSRC:
+               div = ((readl(priv->base + SD0CKCR1) >> 29) & 0x03) + 4;
+               rate = gen3_clk_get_rate64(&parent) / div;
+               debug("%s[%i] SDSRC clk: parent=%i div=%u => rate=%llu\n",
+                     __func__, __LINE__, core->parent, div, rate);
+               return rate;
+
        case CLK_TYPE_GEN3_SDH: /* Fixed factor 1:1 */
                fallthrough;
        case CLK_TYPE_GEN4_SDH: /* Fixed factor 1:1 */
@@ -321,7 +361,16 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
                                                     gen3_clk_get_rate64(&parent),
                                                     priv->base + CPG_RPCCKCR,
                                                     CPG_RPCCKCR_DIV_POST_MASK,
-                                                    cpg_rpcsrc_div_table, "RPCSRC");
+                                                    gen3_cpg_rpcsrc_div_table,
+                                                    "RPCSRC");
+
+       case CLK_TYPE_GEN4_RPCSRC:
+               return rcar_clk_get_rate64_div_table(core->parent,
+                                                    gen3_clk_get_rate64(&parent),
+                                                    priv->base + CPG_RPCCKCR,
+                                                    CPG_RPCCKCR_DIV_POST_MASK,
+                                                    gen4_cpg_rpcsrc_div_table,
+                                                    "RPCSRC");
 
        case CLK_TYPE_GEN3_D3_RPCSRC:
        case CLK_TYPE_GEN3_E3_RPCSRC:
@@ -409,6 +458,7 @@ static int gen3_clk_probe(struct udevice *dev)
        struct gen3_clk_priv *priv = dev_get_priv(dev);
        struct cpg_mssr_info *info =
                (struct cpg_mssr_info *)dev_get_driver_data(dev);
+       const void *pll_config;
        fdt_addr_t rst_base;
        int ret;
 
@@ -427,21 +477,24 @@ static int gen3_clk_probe(struct udevice *dev)
 
        priv->cpg_mode = readl(rst_base + info->reset_modemr_offset);
 
-       priv->cpg_pll_config =
-               (struct rcar_gen3_cpg_pll_config *)info->get_pll_config(priv->cpg_mode);
-       if (!priv->cpg_pll_config->extal_div)
-               return -EINVAL;
+       pll_config = info->get_pll_config(priv->cpg_mode);
 
        if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
                priv->info->status_regs = mstpsr;
                priv->info->control_regs = smstpcr;
                priv->info->reset_regs = srcr;
                priv->info->reset_clear_regs = srstclr;
-       } else if (info->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) {
-               priv->info->status_regs = mstpsr_for_v3u;
-               priv->info->control_regs = mstpcr_for_v3u;
-               priv->info->reset_regs = srcr_for_v3u;
-               priv->info->reset_clear_regs = srstclr_for_v3u;
+               priv->gen3_cpg_pll_config = pll_config;
+               if (!priv->gen3_cpg_pll_config->extal_div)
+                       return -EINVAL;
+       } else if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) {
+               priv->info->status_regs = mstpsr_for_gen4;
+               priv->info->control_regs = mstpcr_for_gen4;
+               priv->info->reset_regs = srcr_for_gen4;
+               priv->info->reset_clear_regs = srstclr_for_gen4;
+               priv->gen4_cpg_pll_config = pll_config;
+               if (!priv->gen4_cpg_pll_config->extal_div)
+                       return -EINVAL;
        } else {
                return -EINVAL;
        }

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index a9c941b..6b7ec36 100644 (file)
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -232,11 +232,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
 /*
  * CPG Clock Data
  */
-
 /*
  *   MD         EXTAL          PLL1    PLL20   PLL30   PLL4    PLL5    OSC
  * 14 13 (MHz)                    21      31
- * --------------------------------------------------------
+ * ----------------------------------------------------------------
  * 0  0         16.66 x 1      x128    x216    x128    x144    x192    /16
  * 0  1         20    x 1      x106    x180    x106    x120    x160    /19
  * 1  0         Prohibited setting
@@ -244,13 +243,12 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
  */
 #define CPG_PLL_CONFIG_INDEX(md)       ((((md) & BIT(14)) >> 13) | \
                                         (((md) & BIT(13)) >> 13))
-
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] = {
-       /* EXTAL div    PLL1 mult/div   Not used     OSC prediv PLL5 mult/div */
-       { 1,            128,    1,      128,    1,      16,     192,    1, },
-       { 1,            106,    1,      106,    1,      19,     160,    1, },
-       { 0,            0,      0,      0,      0,      0,      0,      0, },
-       { 2,            128,    1,      128,    1,      32,     192,    1, },
+static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
+       /* EXTAL div    PLL1 mult/div   PLL2 mult/div   PLL3 mult/div   PLL4 mult/div   PLL5 mult/div   PLL6 mult/div   OSC prediv */
+       { 1,            128,    1,      0,      0,      0,      0,      144,    1,      192,    1,      0,      0,      16,     },
+       { 1,            106,    1,      0,      0,      0,      0,      120,    1,      160,    1,      0,      0,      19,     },
+       { 0,            0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      },
+       { 2,            128,    1,      0,      0,      0,      0,      144,    1,      192,    1,      0,      0,      32,     },
 };
 
 /*
@@ -292,13 +290,13 @@ static const struct cpg_mssr_info r8a779a0_cpg_mssr_info = {
        .mstp_table             = r8a779a0_mstp_table,
        .mstp_table_size        = ARRAY_SIZE(r8a779a0_mstp_table),
        .reset_node             = "renesas,r8a779a0-rst",
-       .reset_modemr_offset    = 0x00,
+       .reset_modemr_offset    = CPG_RST_MODEMR0,
        .extalr_node            = "extalr",
        .mod_clk_base           = MOD_CLK_BASE,
        .clk_extal_id           = CLK_EXTAL,
        .clk_extalr_id          = CLK_EXTALR,
        .get_pll_config         = r8a779a0_get_pll_config,
-       .reg_layout             = CLK_REG_LAYOUT_RCAR_V3U,
+       .reg_layout             = CLK_REG_LAYOUT_RCAR_GEN4,
 };
 
 static const struct udevice_id r8a779a0_cpg_ids[] = {

diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
new file mode 100644 (file)
index 0000000..7aac28e
--- /dev/null
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a779f0 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ *
+ * Based on r8a779a0-cpg-mssr.c
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+       /* Core Clock Outputs exported to DT */
+       LAST_DT_CORE_CLK = R8A779F0_CLK_R,
+
+       /* External Input Clocks */
+       CLK_EXTAL,
+       CLK_EXTALR,
+
+       /* Internal Core Clocks */
+       CLK_MAIN,
+       CLK_PLL1,
+       CLK_PLL2,
+       CLK_PLL3,
+       CLK_PLL5,
+       CLK_PLL6,
+       CLK_PLL1_DIV2,
+       CLK_PLL2_DIV2,
+       CLK_PLL3_DIV2,
+       CLK_PLL5_DIV2,
+       CLK_PLL5_DIV4,
+       CLK_PLL6_DIV2,
+       CLK_S0,
+       CLK_SASYNCPER,
+       CLK_SDSRC,
+       CLK_RPCSRC,
+       CLK_OCO,
+
+       /* Module Clocks */
+       MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a779f0_core_clks[] = {
+       /* External Clock Inputs */
+       DEF_INPUT("extal",      CLK_EXTAL),
+       DEF_INPUT("extalr",     CLK_EXTALR),
+
+       /* Internal Core Clocks */
+       DEF_BASE(".main", CLK_MAIN,     CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
+       DEF_BASE(".pll1", CLK_PLL1,     CLK_TYPE_GEN4_PLL1, CLK_MAIN),
+       DEF_BASE(".pll2", CLK_PLL2,     CLK_TYPE_GEN4_PLL2, CLK_MAIN),
+       DEF_BASE(".pll3", CLK_PLL3,     CLK_TYPE_GEN4_PLL3, CLK_MAIN),
+       DEF_BASE(".pll5", CLK_PLL5,     CLK_TYPE_GEN4_PLL5, CLK_MAIN),
+       DEF_BASE(".pll6", CLK_PLL6,     CLK_TYPE_GEN4_PLL6, CLK_MAIN),
+
+       DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,  CLK_PLL1,       2, 1),
+       DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2,  CLK_PLL2,       2, 1),
+       DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2,  CLK_PLL3,       2, 1),
+       DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2,  CLK_PLL5,       2, 1),
+       DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4,  CLK_PLL5_DIV2,  2, 1),
+       DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2,  CLK_PLL6,       2, 1),
+       DEF_FIXED(".s0",        CLK_S0,         CLK_PLL1_DIV2,  2, 1),
+
+       DEF_FIXED(".sasyncper", CLK_SASYNCPER,  CLK_PLL5_DIV4,  3, 1),
+       DEF_BASE(".sdsrc",      CLK_SDSRC,      CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
+       DEF_RATE(".oco",        CLK_OCO,        32768),
+
+       DEF_BASE(".rpcsrc",     CLK_RPCSRC,     CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
+
+       /* Core Clock Outputs */
+       DEF_GEN4_Z("z0",        R8A779F0_CLK_Z0,        CLK_TYPE_GEN4_Z,        CLK_PLL2,       2, 0),
+       DEF_GEN4_Z("z1",        R8A779F0_CLK_Z1,        CLK_TYPE_GEN4_Z,        CLK_PLL2,       2, 8),
+       DEF_FIXED("s0d2",       R8A779F0_CLK_S0D2,      CLK_S0,         2, 1),
+       DEF_FIXED("s0d3",       R8A779F0_CLK_S0D3,      CLK_S0,         3, 1),
+       DEF_FIXED("s0d4",       R8A779F0_CLK_S0D4,      CLK_S0,         4, 1),
+       DEF_FIXED("cl16m",      R8A779F0_CLK_CL16M,     CLK_S0,         48, 1),
+       DEF_FIXED("s0d2_mm",    R8A779F0_CLK_S0D2_MM,   CLK_S0,         2, 1),
+       DEF_FIXED("s0d3_mm",    R8A779F0_CLK_S0D3_MM,   CLK_S0,         3, 1),
+       DEF_FIXED("s0d4_mm",    R8A779F0_CLK_S0D4_MM,   CLK_S0,         4, 1),
+       DEF_FIXED("cl16m_mm",   R8A779F0_CLK_CL16M_MM,  CLK_S0,         48, 1),
+       DEF_FIXED("s0d2_rt",    R8A779F0_CLK_S0D2_RT,   CLK_S0,         2, 1),
+       DEF_FIXED("s0d3_rt",    R8A779F0_CLK_S0D3_RT,   CLK_S0,         3, 1),
+       DEF_FIXED("s0d4_rt",    R8A779F0_CLK_S0D4_RT,   CLK_S0,         4, 1),
+       DEF_FIXED("s0d6_rt",    R8A779F0_CLK_S0D6_RT,   CLK_S0,         6, 1),
+       DEF_FIXED("cl16m_rt",   R8A779F0_CLK_CL16M_RT,  CLK_S0,         48, 1),
+       DEF_FIXED("s0d3_per",   R8A779F0_CLK_S0D3_PER,  CLK_S0,         3, 1),
+       DEF_FIXED("s0d6_per",   R8A779F0_CLK_S0D6_PER,  CLK_S0,         6, 1),
+       DEF_FIXED("s0d12_per",  R8A779F0_CLK_S0D12_PER, CLK_S0,         12, 1),
+       DEF_FIXED("s0d24_per",  R8A779F0_CLK_S0D24_PER, CLK_S0,         24, 1),
+       DEF_FIXED("cl16m_per",  R8A779F0_CLK_CL16M_PER, CLK_S0,         48, 1),
+       DEF_FIXED("s0d2_hsc",   R8A779F0_CLK_S0D2_HSC,  CLK_S0,         2, 1),
+       DEF_FIXED("s0d3_hsc",   R8A779F0_CLK_S0D3_HSC,  CLK_S0,         3, 1),
+       DEF_FIXED("s0d4_hsc",   R8A779F0_CLK_S0D4_HSC,  CLK_S0,         4, 1),
+       DEF_FIXED("s0d6_hsc",   R8A779F0_CLK_S0D6_HSC,  CLK_S0,         6, 1),
+       DEF_FIXED("s0d12_hsc",  R8A779F0_CLK_S0D12_HSC, CLK_S0,         12, 1),
+       DEF_FIXED("cl16m_hsc",  R8A779F0_CLK_CL16M_HSC, CLK_S0,         48, 1),
+       DEF_FIXED("s0d2_cc",    R8A779F0_CLK_S0D2_CC,   CLK_S0,         2, 1),
+       DEF_FIXED("rsw2",       R8A779F0_CLK_RSW2,      CLK_PLL5_DIV2,  5, 1),
+       DEF_FIXED("cbfusa",     R8A779F0_CLK_CBFUSA,    CLK_EXTAL,      2, 1),
+       DEF_FIXED("cpex",       R8A779F0_CLK_CPEX,      CLK_EXTAL,      2, 1),
+
+       DEF_FIXED("sasyncrt",   R8A779F0_CLK_SASYNCRT,  CLK_PLL5_DIV4,  48, 1),
+       DEF_FIXED("sasyncperd1",R8A779F0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),
+       DEF_FIXED("sasyncperd2",R8A779F0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
+       DEF_FIXED("sasyncperd4",R8A779F0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
+
+       DEF_GEN4_SDH("sd0h",    R8A779F0_CLK_SD0H,      CLK_SDSRC,         0x870),
+       DEF_GEN4_SD("sd0",      R8A779F0_CLK_SD0,       R8A779F0_CLK_SD0H, 0x870),
+
+       DEF_BASE("rpc",         R8A779F0_CLK_RPC,       CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
+       DEF_BASE("rpcd2",       R8A779F0_CLK_RPCD2,     CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC),
+
+       DEF_DIV6P1("mso",       R8A779F0_CLK_MSO,       CLK_PLL5_DIV4,  0x87c),
+
+       DEF_GEN4_OSC("osc",     R8A779F0_CLK_OSC,       CLK_EXTAL,      8),
+       DEF_GEN4_MDSEL("r",     R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
+};
+
+static const struct mssr_mod_clk r8a779f0_mod_clks[] = {
+       DEF_MOD("hscif0",       514,    R8A779F0_CLK_SASYNCPERD1),
+       DEF_MOD("hscif1",       515,    R8A779F0_CLK_SASYNCPERD1),
+       DEF_MOD("hscif2",       516,    R8A779F0_CLK_SASYNCPERD1),
+       DEF_MOD("hscif3",       517,    R8A779F0_CLK_SASYNCPERD1),
+       DEF_MOD("i2c0",         518,    R8A779F0_CLK_S0D6_PER),
+       DEF_MOD("i2c1",         519,    R8A779F0_CLK_S0D6_PER),
+       DEF_MOD("i2c2",         520,    R8A779F0_CLK_S0D6_PER),
+       DEF_MOD("i2c3",         521,    R8A779F0_CLK_S0D6_PER),
+       DEF_MOD("i2c4",         522,    R8A779F0_CLK_S0D6_PER),
+       DEF_MOD("i2c5",         523,    R8A779F0_CLK_S0D6_PER),
+       DEF_MOD("msiof0",       618,    R8A779F0_CLK_MSO),
+       DEF_MOD("msiof1",       619,    R8A779F0_CLK_MSO),
+       DEF_MOD("msiof2",       620,    R8A779F0_CLK_MSO),
+       DEF_MOD("msiof3",       621,    R8A779F0_CLK_MSO),
+       DEF_MOD("pcie0",        624,    R8A779F0_CLK_S0D2),
+       DEF_MOD("pcie1",        625,    R8A779F0_CLK_S0D2),
+       DEF_MOD("scif0",        702,    R8A779F0_CLK_SASYNCPERD4),
+       DEF_MOD("scif1",        703,    R8A779F0_CLK_SASYNCPERD4),
+       DEF_MOD("scif3",        704,    R8A779F0_CLK_SASYNCPERD4),
+       DEF_MOD("scif4",        705,    R8A779F0_CLK_SASYNCPERD4),
+       DEF_MOD("sdhi0",        706,    R8A779F0_CLK_SD0),
+       DEF_MOD("sys-dmac0",    709,    R8A779F0_CLK_S0D3_PER),
+       DEF_MOD("sys-dmac1",    710,    R8A779F0_CLK_S0D3_PER),
+       DEF_MOD("tmu0",         713,    R8A779F0_CLK_SASYNCRT),
+       DEF_MOD("tmu1",         714,    R8A779F0_CLK_SASYNCPERD2),
+       DEF_MOD("tmu2",         715,    R8A779F0_CLK_SASYNCPERD2),
+       DEF_MOD("tmu3",         716,    R8A779F0_CLK_SASYNCPERD2),
+       DEF_MOD("tmu4",         717,    R8A779F0_CLK_SASYNCPERD2),
+       DEF_MOD("wdt",          907,    R8A779F0_CLK_R),
+       DEF_MOD("cmt0",         910,    R8A779F0_CLK_R),
+       DEF_MOD("cmt1",         911,    R8A779F0_CLK_R),
+       DEF_MOD("cmt2",         912,    R8A779F0_CLK_R),
+       DEF_MOD("cmt3",         913,    R8A779F0_CLK_R),
+       DEF_MOD("pfc0",         915,    R8A779F0_CLK_CL16M),
+       DEF_MOD("tsc",          919,    R8A779F0_CLK_CL16M),
+       DEF_MOD("rswitch2",     1505,   R8A779F0_CLK_RSW2),
+       DEF_MOD("ether-serdes", 1506,   R8A779F0_CLK_S0D2_HSC),
+       DEF_MOD("ufs",          1514,   R8A779F0_CLK_S0D4_HSC),
+};
+
+/*
+ * CPG Clock Data
+ */
+/*
+ *   MD         EXTAL          PLL1    PLL2    PLL3    PLL4    PLL5    PLL6    OSC
+ * 14 13 (MHz)
+ * ------------------------------------------------------------------------
+ * 0  0         16    / 1      x200    x150    x200    n/a     x200    x134    /15
+ * 0  1         20    / 1      x160    x120    x160    n/a     x160    x106    /19
+ * 1  0         Prohibited setting
+ * 1  1         40    / 2      x160    x120    x160    n/a     x160    x106    /38
+ */
+#define CPG_PLL_CONFIG_INDEX(md)       ((((md) & BIT(14)) >> 13) | \
+                                        (((md) & BIT(13)) >> 13))
+
+static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
+       /* EXTAL div    PLL1 mult/div   PLL2 mult/div   PLL3 mult/div   PLL4 mult/div   PLL5 mult/div   PLL6 mult/div   OSC prediv */
+       { 1,            200,    1,      150,    1,      200,    1,      0,      0,      200,    1,      134,    1,      15,     },
+       { 1,            160,    1,      120,    1,      160,    1,      0,      0,      160,    1,      106,    1,      19,     },
+       { 0,            0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      },
+       { 2,            160,    1,      120,    1,      160,    1,      0,      0,      160,    1,      106,    1,      38,     },
+};
+
+/*
+ * Note that the only clock left running before booting Linux are now
+ * MFIS, INTC-AP, INTC-EX and HSCIF0/SCIF3 on S4
+ */
+#define MSTPCR5_HSCIF0 BIT(14)
+#define MSTPCR7_SCIF3  BIT(4) /* No information: MFIS, INTC-AP, INTC-EX */
+static const struct mstp_stop_table r8a779f0_mstp_table[] = {
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x00800000, 0x0, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x0003c000, MSTPCR5_HSCIF0, 0x0, 0x0 },
+       { 0x03000000, 0x0, 0x0, 0x0 },
+       { 0x1ffbe040, MSTPCR7_SCIF3, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x00003c78, 0x0, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x9e800000, 0x0, 0x0, 0x0 },
+       { 0x00000027, 0x0, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x00005800, 0x0, 0x0, 0x0 },
+};
+
+static const void *r8a779f0_get_pll_config(const u32 cpg_mode)
+{
+       return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+}
+
+static const struct cpg_mssr_info r8a779f0_cpg_mssr_info = {
+       .core_clk               = r8a779f0_core_clks,
+       .core_clk_size          = ARRAY_SIZE(r8a779f0_core_clks),
+       .mod_clk                = r8a779f0_mod_clks,
+       .mod_clk_size           = ARRAY_SIZE(r8a779f0_mod_clks),
+       .mstp_table             = r8a779f0_mstp_table,
+       .mstp_table_size        = ARRAY_SIZE(r8a779f0_mstp_table),
+       .reset_node             = "renesas,r8a779f0-rst",
+       .reset_modemr_offset    = CPG_RST_MODEMR0,
+       .extalr_node            = "extalr",
+       .mod_clk_base           = MOD_CLK_BASE,
+       .clk_extal_id           = CLK_EXTAL,
+       .clk_extalr_id          = CLK_EXTALR,
+       .get_pll_config         = r8a779f0_get_pll_config,
+       .reg_layout             = CLK_REG_LAYOUT_RCAR_GEN4,
+};
+
+static const struct udevice_id r8a779f0_cpg_ids[] = {
+       {
+               .compatible     = "renesas,r8a779f0-cpg-mssr",
+               .data           = (ulong)&r8a779f0_cpg_mssr_info
+       },
+       { }
+};
+
+U_BOOT_DRIVER(cpg_r8a779f0) = {
+       .name           = "cpg_r8a779f0",
+       .id             = UCLASS_NOP,
+       .of_match       = r8a779f0_cpg_ids,
+       .bind           = gen3_cpg_bind,
+};

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
new file mode 100644 (file)
index 0000000..8625e8a
--- /dev/null
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a779g0 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ *
+ * Based on r8a779f0-cpg-mssr.c
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+       /* Core Clock Outputs exported to DT */
+       LAST_DT_CORE_CLK = R8A779G0_CLK_R,
+
+       /* External Input Clocks */
+       CLK_EXTAL,
+       CLK_EXTALR,
+
+       /* Internal Core Clocks */
+       CLK_MAIN,
+       CLK_PLL1,
+       CLK_PLL2,
+       CLK_PLL3,
+       CLK_PLL4,
+       CLK_PLL5,
+       CLK_PLL6,
+       CLK_PLL1_DIV2,
+       CLK_PLL2_DIV2,
+       CLK_PLL3_DIV2,
+       CLK_PLL4_DIV2,
+       CLK_PLL5_DIV2,
+       CLK_PLL5_DIV4,
+       CLK_PLL6_DIV2,
+       CLK_S0,
+       CLK_S0_VIO,
+       CLK_S0_VC,
+       CLK_S0_HSC,
+       CLK_SASYNCPER,
+       CLK_SV_VIP,
+       CLK_SV_IR,
+       CLK_SDSRC,
+       CLK_RPCSRC,
+       CLK_VIO,
+       CLK_VC,
+       CLK_OCO,
+
+       /* Module Clocks */
+       MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a779g0_core_clks[] = {
+       /* External Clock Inputs */
+       DEF_INPUT("extal",      CLK_EXTAL),
+       DEF_INPUT("extalr",     CLK_EXTALR),
+
+       /* Internal Core Clocks */
+       DEF_BASE(".main", CLK_MAIN,     CLK_TYPE_GEN4_MAIN,     CLK_EXTAL),
+       DEF_BASE(".pll1", CLK_PLL1,     CLK_TYPE_GEN4_PLL1,     CLK_MAIN),
+       DEF_BASE(".pll2", CLK_PLL2,     CLK_TYPE_GEN4_PLL2,     CLK_MAIN),
+       DEF_BASE(".pll3", CLK_PLL3,     CLK_TYPE_GEN4_PLL3,     CLK_MAIN),
+       DEF_BASE(".pll4", CLK_PLL4,     CLK_TYPE_GEN4_PLL4,     CLK_MAIN),
+       DEF_BASE(".pll5", CLK_PLL5,     CLK_TYPE_GEN4_PLL5,     CLK_MAIN),
+       DEF_BASE(".pll6", CLK_PLL6,     CLK_TYPE_GEN4_PLL6,     CLK_MAIN),
+
+       DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,  CLK_PLL1,       2, 1),
+       DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2,  CLK_PLL2,       2, 1),
+       DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2,  CLK_PLL3,       2, 1),
+       DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2,  CLK_PLL4,       2, 1),
+       DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2,  CLK_PLL5,       2, 1),
+       DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4,  CLK_PLL5_DIV2,  2, 1),
+       DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2,  CLK_PLL6,       2, 1),
+       DEF_FIXED(".s0",        CLK_S0,         CLK_PLL1_DIV2,  2, 1),
+       DEF_FIXED(".s0_vio",    CLK_S0_VIO,     CLK_PLL1_DIV2,  2, 1),
+       DEF_FIXED(".s0_vc",     CLK_S0_VC,      CLK_PLL1_DIV2,  2, 1),
+       DEF_FIXED(".s0_hsc",    CLK_S0_HSC,     CLK_PLL1_DIV2,  2, 1),
+       DEF_FIXED(".sasyncper", CLK_SASYNCPER,  CLK_PLL5_DIV4,  3, 1),
+       DEF_FIXED(".sv_vip",    CLK_SV_VIP,     CLK_PLL1,       5, 1),
+       DEF_FIXED(".sv_ir",     CLK_SV_IR,      CLK_PLL1,       5, 1),
+       DEF_BASE(".sdsrc",      CLK_SDSRC,      CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
+       DEF_RATE(".oco",        CLK_OCO,        32768),
+
+       DEF_BASE(".rpcsrc",     CLK_RPCSRC,     CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
+       DEF_FIXED(".vio",       CLK_VIO,        CLK_PLL5_DIV2,  3, 1),
+       DEF_FIXED(".vc",        CLK_VC,         CLK_PLL5_DIV2,  3, 1),
+
+       /* Core Clock Outputs */
+       DEF_GEN4_Z("z0",        R8A779G0_CLK_Z0,        CLK_TYPE_GEN4_Z,        CLK_PLL2,       2, 0),
+       DEF_FIXED("s0d2",       R8A779G0_CLK_S0D2,      CLK_S0,         2, 1),
+       DEF_FIXED("s0d3",       R8A779G0_CLK_S0D3,      CLK_S0,         3, 1),
+       DEF_FIXED("s0d4",       R8A779G0_CLK_S0D4,      CLK_S0,         4, 1),
+       DEF_FIXED("cl16m",      R8A779G0_CLK_CL16M,     CLK_S0,         48, 1),
+       DEF_FIXED("s0d1_vio",   R8A779G0_CLK_S0D1_VIO,  CLK_S0_VIO,     1, 1),
+       DEF_FIXED("s0d2_vio",   R8A779G0_CLK_S0D2_VIO,  CLK_S0_VIO,     2, 1),
+       DEF_FIXED("s0d4_vio",   R8A779G0_CLK_S0D4_VIO,  CLK_S0_VIO,     4, 1),
+       DEF_FIXED("s0d8_vio",   R8A779G0_CLK_S0D8_VIO,  CLK_S0_VIO,     8, 1),
+       DEF_FIXED("s0d1_vc",    R8A779G0_CLK_S0D1_VC,   CLK_S0_VC,      1, 1),
+       DEF_FIXED("s0d2_vc",    R8A779G0_CLK_S0D2_VC,   CLK_S0_VC,      2, 1),
+       DEF_FIXED("s0d4_vc",    R8A779G0_CLK_S0D4_VC,   CLK_S0_VC,      4, 1),
+       DEF_FIXED("s0d2_mm",    R8A779G0_CLK_S0D2_MM,   CLK_S0,         2, 1),
+       DEF_FIXED("s0d4_mm",    R8A779G0_CLK_S0D4_MM,   CLK_S0,         4, 1),
+       DEF_FIXED("cl16m_mm",   R8A779G0_CLK_CL16M_MM,  CLK_S0,         48, 1),
+       DEF_FIXED("s0d2_u3dg",  R8A779G0_CLK_S0D2_U3DG, CLK_S0,         2, 1),
+       DEF_FIXED("s0d4_u3dg",  R8A779G0_CLK_S0D4_U3DG, CLK_S0,         4, 1),
+       DEF_FIXED("s0d2_rt",    R8A779G0_CLK_S0D2_RT,   CLK_S0,         2, 1),
+       DEF_FIXED("s0d3_rt",    R8A779G0_CLK_S0D3_RT,   CLK_S0,         3, 1),
+       DEF_FIXED("s0d4_rt",    R8A779G0_CLK_S0D4_RT,   CLK_S0,         4, 1),
+       DEF_FIXED("s0d6_rt",    R8A779G0_CLK_S0D6_RT,   CLK_S0,         6, 1),
+       DEF_FIXED("s0d24_rt",   R8A779G0_CLK_S0D24_RT,  CLK_S0,         24, 1),
+       DEF_FIXED("cl16m_rt",   R8A779G0_CLK_CL16M_RT,  CLK_S0,         48, 1),
+       DEF_FIXED("s0d2_per",   R8A779G0_CLK_S0D2_PER,  CLK_S0,         2, 1),
+       DEF_FIXED("s0d3_per",   R8A779G0_CLK_S0D3_PER,  CLK_S0,         3, 1),
+       DEF_FIXED("s0d4_per",   R8A779G0_CLK_S0D4_PER,  CLK_S0,         4, 1),
+       DEF_FIXED("s0d6_per",   R8A779G0_CLK_S0D6_PER,  CLK_S0,         6, 1),
+       DEF_FIXED("s0d12_per",  R8A779G0_CLK_S0D12_PER, CLK_S0,         12, 1),
+       DEF_FIXED("s0d24_per",  R8A779G0_CLK_S0D24_PER, CLK_S0,         24, 1),
+       DEF_FIXED("cl16m_per",  R8A779G0_CLK_CL16M_PER, CLK_S0,         48, 1),
+       DEF_FIXED("s0d1_hsc",   R8A779G0_CLK_S0D1_HSC,  CLK_S0_HSC,     1, 1),
+       DEF_FIXED("s0d2_hsc",   R8A779G0_CLK_S0D2_HSC,  CLK_S0_HSC,     2, 1),
+       DEF_FIXED("s0d4_hsc",   R8A779G0_CLK_S0D4_HSC,  CLK_S0_HSC,     4, 1),
+       DEF_FIXED("cl16m_hsc",  R8A779G0_CLK_CL16M_HSC, CLK_S0_HSC,     48, 1),
+       DEF_FIXED("s0d2_cc",    R8A779G0_CLK_S0D2_CC,   CLK_S0,         2, 1),
+       DEF_FIXED("sasyncrt",   R8A779G0_CLK_SASYNCRT,  CLK_PLL5_DIV4,  48, 1),
+       DEF_FIXED("sasyncperd1",R8A779G0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),
+       DEF_FIXED("sasyncperd2",R8A779G0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
+       DEF_FIXED("sasyncperd4",R8A779G0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
+       DEF_FIXED("svd1_ir",    R8A779G0_CLK_SVD1_IR,   CLK_SV_IR,      1, 1),
+       DEF_FIXED("svd2_ir",    R8A779G0_CLK_SVD2_IR,   CLK_SV_IR,      2, 1),
+       DEF_FIXED("svd1_vip",   R8A779G0_CLK_SVD1_VIP,  CLK_SV_VIP,     1, 1),
+       DEF_FIXED("svd2_vip",   R8A779G0_CLK_SVD2_VIP,  CLK_SV_VIP,     2, 1),
+       DEF_FIXED("cbfusa",     R8A779G0_CLK_CBFUSA,    CLK_EXTAL,      2, 1),
+       DEF_FIXED("cpex",       R8A779G0_CLK_CPEX,      CLK_EXTAL,      2, 1),
+       DEF_FIXED("viobus",     R8A779G0_CLK_VIOBUS,    CLK_VIO,        1, 1),
+       DEF_FIXED("viobusd2",   R8A779G0_CLK_VIOBUSD2,  CLK_VIO,        2, 1),
+       DEF_FIXED("vcbus",      R8A779G0_CLK_VCBUS,     CLK_VC,         1, 1),
+       DEF_FIXED("vcbusd2",    R8A779G0_CLK_VCBUSD2,   CLK_VC,         2, 1),
+       DEF_DIV6P1("canfd",     R8A779G0_CLK_CANFD,     CLK_PLL5_DIV4,  0x878),
+       DEF_FIXED("dsiref",     R8A779G0_CLK_DSIREF,    CLK_PLL5_DIV4,  48, 1),
+       DEF_DIV6P1("dsiext",    R8A779G0_CLK_DSIEXT,    CLK_PLL5_DIV4,  0x884),
+
+       DEF_GEN4_SDH("sd0h",    R8A779G0_CLK_SD0H,      CLK_SDSRC,         0x870),
+       DEF_GEN4_SD("sd0",      R8A779G0_CLK_SD0,       R8A779G0_CLK_SD0H, 0x870),
+       DEF_DIV6P1("mso",       R8A779G0_CLK_MSO,       CLK_PLL5_DIV4,  0x87c),
+
+       DEF_BASE("rpc",         R8A779G0_CLK_RPC,       CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
+       DEF_BASE("rpcd2",       R8A779G0_CLK_RPCD2,     CLK_TYPE_GEN4_RPCD2, R8A779G0_CLK_RPC),
+
+       DEF_GEN4_OSC("osc",     R8A779G0_CLK_OSC,       CLK_EXTAL,      8),
+       DEF_GEN4_MDSEL("r",     R8A779G0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
+};
+
+static const struct mssr_mod_clk r8a779g0_mod_clks[] = {
+       DEF_MOD("avb0",         211,    R8A779G0_CLK_S0D4_HSC),
+       DEF_MOD("avb1",         212,    R8A779G0_CLK_S0D4_HSC),
+       DEF_MOD("avb2",         213,    R8A779G0_CLK_S0D4_HSC),
+       DEF_MOD("canfd0",       328,    R8A779G0_CLK_SASYNCPERD2),
+       DEF_MOD("dis0",         411,    R8A779G0_CLK_VIOBUSD2),
+       DEF_MOD("dsitxlink0",   415,    R8A779G0_CLK_VIOBUSD2),
+       DEF_MOD("dsitxlink1",   416,    R8A779G0_CLK_VIOBUSD2),
+       DEF_MOD("fcpvd0",       508,    R8A779G0_CLK_VIOBUSD2),
+       DEF_MOD("fcpvd1",       509,    R8A779G0_CLK_VIOBUSD2),
+       DEF_MOD("hscif0",       514,    R8A779G0_CLK_SASYNCPERD1),
+       DEF_MOD("hscif1",       515,    R8A779G0_CLK_SASYNCPERD1),
+       DEF_MOD("hscif2",       516,    R8A779G0_CLK_SASYNCPERD1),
+       DEF_MOD("hscif3",       517,    R8A779G0_CLK_SASYNCPERD1),
+       DEF_MOD("i2c0",         518,    R8A779G0_CLK_S0D6_PER),
+       DEF_MOD("i2c1",         519,    R8A779G0_CLK_S0D6_PER),
+       DEF_MOD("i2c2",         520,    R8A779G0_CLK_S0D6_PER),
+       DEF_MOD("i2c3",         521,    R8A779G0_CLK_S0D6_PER),
+       DEF_MOD("i2c4",         522,    R8A779G0_CLK_S0D6_PER),
+       DEF_MOD("i2c5",         523,    R8A779G0_CLK_S0D6_PER),
+       DEF_MOD("irqc",         611,    R8A779G0_CLK_CL16M),
+       DEF_MOD("msi0",         618,    R8A779G0_CLK_MSO),
+       DEF_MOD("msi1",         619,    R8A779G0_CLK_MSO),
+       DEF_MOD("msi2",         620,    R8A779G0_CLK_MSO),
+       DEF_MOD("msi3",         621,    R8A779G0_CLK_MSO),
+       DEF_MOD("msi4",         622,    R8A779G0_CLK_MSO),
+       DEF_MOD("msi5",         623,    R8A779G0_CLK_MSO),
+       DEF_MOD("pwm",          628,    R8A779G0_CLK_SASYNCPERD4),
+       DEF_MOD("rpc-if",       629,    R8A779G0_CLK_RPCD2),
+       DEF_MOD("scif0",        702,    R8A779G0_CLK_SASYNCPERD4),
+       DEF_MOD("scif1",        703,    R8A779G0_CLK_SASYNCPERD4),
+       DEF_MOD("scif3",        704,    R8A779G0_CLK_SASYNCPERD4),
+       DEF_MOD("scif4",        705,    R8A779G0_CLK_SASYNCPERD4),
+       DEF_MOD("sdhi",         706,    R8A779G0_CLK_SD0),
+       DEF_MOD("sys-dmac0",    709,    R8A779G0_CLK_S0D6_PER),
+       DEF_MOD("sys-dmac1",    710,    R8A779G0_CLK_S0D6_PER),
+       DEF_MOD("tmu0",         713,    R8A779G0_CLK_SASYNCRT),
+       DEF_MOD("tmu1",         714,    R8A779G0_CLK_SASYNCPERD2),
+       DEF_MOD("tmu2",         715,    R8A779G0_CLK_SASYNCPERD2),
+       DEF_MOD("tmu3",         716,    R8A779G0_CLK_SASYNCPERD2),
+       DEF_MOD("tmu4",         717,    R8A779G0_CLK_SASYNCPERD2),
+       DEF_MOD("tpu0",         718,    R8A779G0_CLK_SASYNCPERD4),
+       DEF_MOD("vspd0",        830,    R8A779G0_CLK_VIOBUSD2),
+       DEF_MOD("vspd1",        831,    R8A779G0_CLK_VIOBUSD2),
+       DEF_MOD("wdt1:wdt0",    907,    R8A779G0_CLK_R),
+       DEF_MOD("cmt0",         910,    R8A779G0_CLK_R),
+       DEF_MOD("cmt1",         911,    R8A779G0_CLK_R),
+       DEF_MOD("cmt2",         912,    R8A779G0_CLK_R),
+       DEF_MOD("cmt3",         913,    R8A779G0_CLK_R),
+       DEF_MOD("pfc0",         915,    R8A779G0_CLK_CL16M),
+       DEF_MOD("pfc1",         916,    R8A779G0_CLK_CL16M),
+       DEF_MOD("pfc2",         917,    R8A779G0_CLK_CL16M),
+       DEF_MOD("pfc3",         918,    R8A779G0_CLK_CL16M),
+};
+
+/*
+ * CPG Clock Data
+ */
+/*
+ *   MD         EXTAL          PLL1    PLL2    PLL3    PLL4    PLL5    PLL6    OSC
+ * 14 13 (MHz)
+ * ------------------------------------------------------------------------
+ * 0  0         16.66 / 1      x192    x204    x192    x144    x192    x168    /16
+ * 0  1         20    / 1      x160    x170    x160    x120    x160    x140    /19
+ * 1  0         Prohibited setting
+ * 1  1         33.33 / 2      x192    x204    x192    x144    x192    x168    /32
+ */
+#define CPG_PLL_CONFIG_INDEX(md)       ((((md) & BIT(14)) >> 13) | \
+                                        (((md) & BIT(13)) >> 13))
+
+static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
+       /* EXTAL div    PLL1 mult/div   PLL2 mult/div   PLL3 mult/div   PLL4 mult/div   PLL5 mult/div   PLL6 mult/div   OSC prediv */
+       { 1,            192,    1,      204,    1,      192,    1,      144,    1,      192,    1,      168,    1,      16,     },
+       { 1,            160,    1,      170,    1,      160,    1,      120,    1,      160,    1,      140,    1,      19,     },
+       { 0,            0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      },
+       { 2,            192,    1,      204,    1,      192,    1,      144,    1,      192,    1,      168,    1,      32,     },
+};
+
+/*
+ * Note that the only clock left running before booting Linux are now
+ * MFIS, INTC-AP, INTC-EX, SCIF0, HSCIF0 on V4H
+ */
+#define MSTPCR5_HSCIF0 BIT(14) /* No information: MFIS, INTC-AP */
+#define MSTPCR6_INTCEX BIT(11) /* No information: MFIS, INTC-AP */
+#define MSTPCR7_SCIF0  BIT(2) /* No information: MFIS, INTC-AP */
+static const struct mstp_stop_table r8a779g0_mstp_table[] = {
+       { 0x0FC302A1, 0x0, 0x0, 0x0 },
+       { 0x00D50038, 0x0, 0x0, 0x0 },
+       { 0x00003800, 0x0, 0x0, 0x0 },
+       { 0xF0000000, 0x0, 0x0, 0x0 },
+       { 0x0001CE01, 0x0, 0x0, 0x0 },
+       { 0xEEFFE380, MSTPCR5_HSCIF0, 0x0, 0x0 },
+       { 0xF3FD3901, MSTPCR6_INTCEX, 0x0, 0x0 },
+       { 0xE007E6FF, MSTPCR7_SCIF0, 0x0, 0x0 },
+       { 0xC0003FFF, 0x0, 0x0, 0x0 },
+       { 0x001FBCF8, 0x0, 0x0, 0x0 },
+       { 0x30000000, 0x0, 0x0, 0x0 },
+       { 0x000000C3, 0x0, 0x0, 0x0 },
+       { 0xDE800000, 0x0, 0x0, 0x0 },
+       { 0x00000017, 0x0, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x00000000, 0x0, 0x0, 0x0 },
+       { 0x000033C0, 0x0, 0x0, 0x0 },
+       { 0x402A001E, 0x0, 0x0, 0x0 },
+       { 0x0C010080, 0x0, 0x0, 0x0 },
+};
+
+static const void *r8a779g0_get_pll_config(const u32 cpg_mode)
+{
+       return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+}
+
+static const struct cpg_mssr_info r8a779g0_cpg_mssr_info = {
+       .core_clk               = r8a779g0_core_clks,
+       .core_clk_size          = ARRAY_SIZE(r8a779g0_core_clks),
+       .mod_clk                = r8a779g0_mod_clks,
+       .mod_clk_size           = ARRAY_SIZE(r8a779g0_mod_clks),
+       .mstp_table             = r8a779g0_mstp_table,
+       .mstp_table_size        = ARRAY_SIZE(r8a779g0_mstp_table),
+       .reset_node             = "renesas,r8a779g0-rst",
+       .reset_modemr_offset    = CPG_RST_MODEMR0,
+       .extalr_node            = "extalr",
+       .mod_clk_base           = MOD_CLK_BASE,
+       .clk_extal_id           = CLK_EXTAL,
+       .clk_extalr_id          = CLK_EXTALR,
+       .get_pll_config         = r8a779g0_get_pll_config,
+       .reg_layout             = CLK_REG_LAYOUT_RCAR_GEN4,
+};
+
+static const struct udevice_id r8a779g0_cpg_ids[] = {
+       {
+               .compatible     = "renesas,r8a779g0-cpg-mssr",
+               .data           = (ulong)&r8a779g0_cpg_mssr_info
+       },
+       { }
+};
+
+U_BOOT_DRIVER(cpg_r8a779g0) = {
+       .name           = "cpg_r8a779g0",
+       .id             = UCLASS_NOP,
+       .of_match       = r8a779g0_cpg_ids,
+       .bind           = gen3_cpg_bind,
+};

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 894e376..06318c8 100644 (file)
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -34,8 +34,13 @@ enum rcar_gen3_clk_types {
 
        CLK_TYPE_GEN4_MAIN,
        CLK_TYPE_GEN4_PLL1,
-       CLK_TYPE_GEN4_PLL2X_3X, /* PLL[23][01] */
+       CLK_TYPE_GEN4_PLL2,
+       CLK_TYPE_GEN4_PLL2X_3X, /* R8A779A0 only */
+       CLK_TYPE_GEN4_PLL3,
        CLK_TYPE_GEN4_PLL5,
+       CLK_TYPE_GEN4_PLL4,
+       CLK_TYPE_GEN4_PLL6,
+       CLK_TYPE_GEN4_SDSRC,
        CLK_TYPE_GEN4_SDH,
        CLK_TYPE_GEN4_SD,
        CLK_TYPE_GEN4_MDSEL,    /* Select parent/divider using mode pin */
@@ -107,11 +112,27 @@ struct rcar_gen3_cpg_pll_config {
        u8 pll3_mult;
        u8 pll3_div;
        u8 osc_prediv;
+};
+
+struct rcar_gen4_cpg_pll_config {
+       u8 extal_div;
+       u8 pll1_mult;
+       u8 pll1_div;
+       u8 pll2_mult;
+       u8 pll2_div;
+       u8 pll3_mult;
+       u8 pll3_div;
+       u8 pll4_mult;
+       u8 pll4_div;
        u8 pll5_mult;
        u8 pll5_div;
+       u8 pll6_mult;
+       u8 pll6_div;
+       u8 osc_prediv;
 };
 
 #define CPG_RST_MODEMR 0x060
+#define CPG_RST_MODEMR0        0x000
 
 #define CPG_SDCKCR_STPnHCK             BIT(9)
 #define CPG_SDCKCR_STPnCK              BIT(8)
@@ -133,7 +154,10 @@ struct gen3_clk_priv {
        struct clk              clk_extal;
        struct clk              clk_extalr;
        u32                     cpg_mode;
-       const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
+       union {
+               const struct rcar_gen3_cpg_pll_config *gen3_cpg_pll_config;
+               const struct rcar_gen4_cpg_pll_config *gen4_cpg_pll_config;
+       };
 };
 
 int gen3_cpg_bind(struct udevice *parent);

diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index e0895d2..10bd54d 100644 (file)
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -128,7 +128,7 @@ int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info)
                                info->mstp_table[i].sdis,
                                info->mstp_table[i].sen);
 
-               if (info->reg_layout == CLK_REG_LAYOUT_RCAR_V3U)
+               if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4)
                        continue;
 
                clrsetbits_le32(base + RMSTPCR(i),

diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 519f885..71e409f 100644 (file)
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -17,7 +17,7 @@
 
 enum clk_reg_layout {
        CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
-       CLK_REG_LAYOUT_RCAR_V3U,
+       CLK_REG_LAYOUT_RCAR_GEN4,
 };
 
 struct cpg_mssr_info {
@@ -134,7 +134,7 @@ int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
  * Module Standby and Software Reset register offets.
  *
  * If the registers exist, these are valid for SH-Mobile, R-Mobile,
- * R-Car Gen2, R-Car Gen3, and RZ/G1.
+ * R-Car Gen2, R-Car Gen3, R-Car Gen4 and RZ/G1.
  * These are NOT valid for R-Car Gen1 and RZ/A1!
  */
 
@@ -147,9 +147,11 @@ static const u16 mstpsr[] = {
        0x9A0, 0x9A4, 0x9A8, 0x9AC,
 };
 
-static const u16 mstpsr_for_v3u[] = {
+static const u16 mstpsr_for_gen4[] = {
        0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
-       0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
+       0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, 0x2E3C,
+       0x2E40, 0x2E44, 0x2E48, 0x2E4C, 0x2E50, 0x2E54, 0x2E58, 0x2E5C,
+       0x2E60, 0x2E64, 0x2E68, 0x2E6C,
 };
 
 /*
@@ -161,9 +163,11 @@ static const u16 smstpcr[] = {
        0x990, 0x994, 0x998, 0x99C,
 };
 
-static const u16 mstpcr_for_v3u[] = {
+static const u16 mstpcr_for_gen4[] = {
        0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
-       0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38,
+       0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, 0x2D3C,
+       0x2D40, 0x2D44, 0x2D48, 0x2D4C, 0x2D50, 0x2D54, 0x2D58, 0x2D5C,
+       0x2D60, 0x2D64, 0x2D68, 0x2D6C,
 };
 
 /*
@@ -175,9 +179,11 @@ static const u16 srcr[] = {
        0x920, 0x924, 0x928, 0x92C,
 };
 
-static const u16 srcr_for_v3u[] = {
+static const u16 srcr_for_gen4[] = {
        0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
-       0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38,
+       0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, 0x2C3C,
+       0x2C40, 0x2C44, 0x2C48, 0x2C4C, 0x2C50, 0x2C54, 0x2C58, 0x2C5C,
+       0x2C60, 0x2C64, 0x2C68, 0x2C6C,
 };
 
 /* Realtime Module Stop Control Register offsets */
@@ -193,9 +199,11 @@ static const u16 srstclr[] = {
        0x960, 0x964, 0x968, 0x96C,
 };
 
-static const u16 srstclr_for_v3u[] = {
+static const u16 srstclr_for_gen4[] = {
        0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
-       0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8,
+       0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, 0x2CBC,
+       0x2CC0, 0x2CC4, 0x2CC8, 0x2CCC, 0x2CD0, 0x2CD4, 0x2CD8, 0x2CDC,
+       0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC,
 };
 
 #endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */

diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index 3b29992..ef744c0 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -778,6 +778,7 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
        case PCLK_I2C5:
                return gclk_rate;
        case PCLK_PWM:
+       case PCLK_RKPWM:
                return PD_BUS_PCLK_HZ;
        case SCLK_SARADC:
                new_rate = rockchip_saradc_get_clk(priv->cru);

diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
index 1c6adc5..cefc263 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -2838,6 +2838,8 @@ static int rk3568_clk_set_parent(struct clk *clk, struct clk *parent)
        case ACLK_RKVDEC_PRE:
        case CLK_RKVDEC_CORE:
                return rk3568_rkvdec_set_parent(clk, parent);
+       case I2S1_MCLKOUT_TX:
+               break;
        default:
                return -ENOENT;
        }

diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
index a7df553..d0cc19b 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -9,6 +9,7 @@
 #include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
+#include <scmi_protocols.h>
 #include <syscon.h>
 #include <asm/arch-rockchip/cru_rk3588.h>
 #include <asm/arch-rockchip/clock.h>
@@ -1552,6 +1553,7 @@ static ulong rk3588_clk_get_rate(struct clk *clk)
        case DCLK_DECOM:
                rate = rk3588_mmc_get_clk(priv, clk->id);
                break;
+       case TMCLK_EMMC:
        case TCLK_WDT0:
                rate = OSC_HZ;
                break;
@@ -1701,6 +1703,7 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate)
        case DCLK_DECOM:
                ret = rk3588_mmc_set_clk(priv, clk->id, rate);
                break;
+       case TMCLK_EMMC:
        case TCLK_WDT0:
                ret = OSC_HZ;
                break;
@@ -1994,3 +1997,127 @@ U_BOOT_DRIVER(rockchip_rk3588_cru) = {
        .bind           = rk3588_clk_bind,
        .probe          = rk3588_clk_probe,
 };
+
+#ifdef CONFIG_SPL_BUILD
+#define SCRU_BASE                      0xfd7d0000
+
+static ulong rk3588_scru_clk_get_rate(struct clk *clk)
+{
+       u32 con, div, sel, parent;
+
+       switch (clk->id) {
+       case SCMI_CCLK_SD:
+               con = readl(SCRU_BASE + RK3588_CLKSEL_CON(3));
+               sel = (con & SCMI_CCLK_SD_SEL_MASK) >> SCMI_CCLK_SD_SEL_SHIFT;
+               div = (con & SCMI_CCLK_SD_DIV_MASK) >> SCMI_CCLK_SD_DIV_SHIFT;
+               if (sel == SCMI_CCLK_SD_SEL_GPLL)
+                       parent = GPLL_HZ;
+               else if (sel == SCMI_CCLK_SD_SEL_SPLL)
+                       parent = SPLL_HZ;
+               else
+                       parent = OSC_HZ;
+               return DIV_TO_RATE(parent, div);
+       case SCMI_HCLK_SD:
+               con = readl(SCRU_BASE + RK3588_CLKSEL_CON(1));
+               sel = (con & SCMI_HCLK_SD_SEL_MASK) >> SCMI_HCLK_SD_SEL_SHIFT;
+               if (sel == SCMI_HCLK_SD_SEL_150M)
+                       return 150 * MHz;
+               else if (sel == SCMI_HCLK_SD_SEL_100M)
+                       return 100 * MHz;
+               else if (sel == SCMI_HCLK_SD_SEL_50M)
+                       return 50 * MHz;
+               else
+                       return OSC_HZ;
+       default:
+               return -ENOENT;
+       }
+}
+
+static ulong rk3588_scru_clk_set_rate(struct clk *clk, ulong rate)
+{
+       u32 div, sel;
+
+       switch (clk->id) {
+       case SCMI_CCLK_SD:
+               if ((OSC_HZ % rate) == 0) {
+                       sel = SCMI_CCLK_SD_SEL_24M;
+                       div = DIV_ROUND_UP(OSC_HZ, rate);
+               } else if ((SPLL_HZ % rate) == 0) {
+                       sel = SCMI_CCLK_SD_SEL_SPLL;
+                       div = DIV_ROUND_UP(SPLL_HZ, rate);
+               } else {
+                       sel = SCMI_CCLK_SD_SEL_GPLL;
+                       div = DIV_ROUND_UP(GPLL_HZ, rate);
+               }
+               rk_clrsetreg(SCRU_BASE + RK3588_CLKSEL_CON(3),
+                            SCMI_CCLK_SD_SEL_MASK | SCMI_CCLK_SD_DIV_MASK,
+                            sel << SCMI_CCLK_SD_SEL_SHIFT |
+                            (div - 1) << SCMI_CCLK_SD_DIV_SHIFT);
+               break;
+       case SCMI_HCLK_SD:
+               if (rate >= 150 * MHz)
+                       sel = SCMI_HCLK_SD_SEL_150M;
+               else if (rate >= 100 * MHz)
+                       sel = SCMI_HCLK_SD_SEL_100M;
+               else if (rate >= 50 * MHz)
+                       sel = SCMI_HCLK_SD_SEL_50M;
+               else
+                       sel = SCMI_HCLK_SD_SEL_24M;
+               rk_clrsetreg(SCRU_BASE + RK3588_CLKSEL_CON(1),
+                            SCMI_HCLK_SD_SEL_MASK,
+                            sel << SCMI_HCLK_SD_SEL_SHIFT);
+               break;
+       default:
+               return -ENOENT;
+       }
+
+       return rk3588_scru_clk_get_rate(clk);
+}
+
+static const struct clk_ops rk3588_scru_clk_ops = {
+       .get_rate = rk3588_scru_clk_get_rate,
+       .set_rate = rk3588_scru_clk_set_rate,
+};
+
+U_BOOT_DRIVER(rockchip_rk3588_scru) = {
+       .name = "rockchip_rk3588_scru",
+       .id = UCLASS_CLK,
+       .ops = &rk3588_scru_clk_ops,
+};
+
+static int rk3588_scmi_spl_glue_bind(struct udevice *dev)
+{
+       ofnode node;
+       u32 protocol_id;
+       const char *name;
+
+       dev_for_each_subnode(node, dev) {
+               if (!ofnode_is_enabled(node))
+                       continue;
+
+               if (ofnode_read_u32(node, "reg", &protocol_id))
+                       continue;
+
+               if (protocol_id != SCMI_PROTOCOL_ID_CLOCK)
+                       continue;
+
+               name = ofnode_get_name(node);
+               return device_bind_driver_to_node(dev, "rockchip_rk3588_scru",
+                                                 name, node, NULL);
+       }
+
+       return -ENOENT;
+}
+
+static const struct udevice_id rk3588_scmi_spl_glue_ids[] = {
+       { .compatible = "arm,scmi-smc" },
+       { }
+};
+
+U_BOOT_DRIVER(rk3588_scmi_spl_glue) = {
+       .name           = "rk3588_scmi_spl_glue",
+       .id             = UCLASS_NOP,
+       .of_match       = rk3588_scmi_spl_glue_ids,
+       .bind           = rk3588_scmi_spl_glue_bind,
+};
+#endif

diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
new file mode 100644 (file)
index 0000000..9399ef6
--- /dev/null
+++ b/drivers/clk/starfive/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+config SPL_CLK_JH7110
+       bool "SPL clock support for JH7110"
+       depends on STARFIVE_JH7110 && SPL
+       select SPL_CLK
+       select SPL_CLK_CCF
+       help
+         This enables SPL DM support for clock driver in JH7110.
+
+config CLK_JH7110
+       bool "StarFive JH7110 clock support"
+       depends on STARFIVE_JH7110
+       select CLK
+       select CLK_CCF
+       help
+         This enables support clock driver for StarFive JH7110 SoC platform.

diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
new file mode 100644 (file)
index 0000000..ec0d157
--- /dev/null
+++ b/drivers/clk/starfive/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += clk-jh7110.o
+obj-y += clk-jh7110-pll.o

diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c
new file mode 100644 (file)
index 0000000..02e6d90
--- /dev/null
+++ b/drivers/clk/starfive/clk-jh7110-pll.c
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022-23 StarFive Technology Co., Ltd.
+ *
+ * Author:     Yanhong Wang <yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm/device.h>
+#include <linux/bitops.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include "clk.h"
+
+#define UBOOT_DM_CLK_JH7110_PLLX "jh7110_clk_pllx"
+
+#define PLL_PD_OFF             1
+#define PLL_PD_ON              0
+
+#define CLK_DDR_BUS_MASK       GENMASK(29, 24)
+#define CLK_DDR_BUS_OFFSET     0xAC
+#define CLK_DDR_BUS_OSC_DIV2   0
+#define CLK_DDR_BUS_PLL1_DIV2  1
+#define CLK_DDR_BUS_PLL1_DIV4  2
+#define CLK_DDR_BUS_PLL1_DIV8  3
+
+struct clk_jh7110_pllx {
+       struct clk              clk;
+       void __iomem    *base;
+       void __iomem    *sysreg;
+       enum starfive_pll_type  type;
+       const struct starfive_pllx_offset *offset;
+       const struct starfive_pllx_rate *rate_table;
+       int rate_count;
+};
+
+#define getbits_le32(addr, mask) ((in_le32(addr) & (mask)) >> __ffs((mask)))
+
+#define PLLX_SET(offset, mask, val) do {\
+               reg = readl((ulong *)((ulong)pll->base + (offset))); \
+               reg &= ~(mask); \
+               reg |= (mask) & ((val) << __ffs(mask)); \
+               writel(reg, (ulong *)((ulong)pll->base + (offset))); \
+       } while (0)
+
+#define PLLX_RATE(_rate, _pd, _fd)     \
+       {                                               \
+               .rate           = (_rate),      \
+               .prediv         = (_pd),        \
+               .fbdiv          = (_fd),        \
+       }
+
+#define to_clk_pllx(_clk) container_of(_clk, struct clk_jh7110_pllx, clk)
+
+static const struct starfive_pllx_rate jh7110_pll0_tbl[] = {
+       PLLX_RATE(375000000UL, 8, 125),
+       PLLX_RATE(500000000UL, 6, 125),
+       PLLX_RATE(625000000UL, 24, 625),
+       PLLX_RATE(750000000UL, 4, 125),
+       PLLX_RATE(875000000UL, 24, 875),
+       PLLX_RATE(1000000000UL, 3, 125),
+       PLLX_RATE(1250000000UL, 12, 625),
+       PLLX_RATE(1375000000UL, 24, 1375),
+       PLLX_RATE(1500000000UL, 2, 125),
+       PLLX_RATE(1625000000UL, 24, 1625),
+       PLLX_RATE(1750000000UL, 12, 875),
+       PLLX_RATE(1800000000UL, 3, 225),
+};
+
+static const struct starfive_pllx_rate jh7110_pll1_tbl[] = {
+       PLLX_RATE(1066000000UL, 12, 533),
+       PLLX_RATE(1200000000UL, 1, 50),
+       PLLX_RATE(1400000000UL, 6, 350),
+       PLLX_RATE(1600000000UL, 3, 200),
+};
+
+static const struct starfive_pllx_rate jh7110_pll2_tbl[] = {
+       PLLX_RATE(1228800000UL, 15, 768),
+       PLLX_RATE(1188000000UL, 2, 99),
+};
+
+static const struct starfive_pllx_offset jh7110_pll0_offset = {
+       .pd = 0x20,
+       .prediv = 0x24,
+       .fbdiv = 0x1c,
+       .frac = 0x20,
+       .postdiv1 = 0x20,
+       .dacpd = 0x18,
+       .dsmpd = 0x18,
+       .pd_mask = BIT(27),
+       .prediv_mask = GENMASK(5, 0),
+       .fbdiv_mask = GENMASK(11, 0),
+       .frac_mask = GENMASK(23, 0),
+       .postdiv1_mask = GENMASK(29, 28),
+       .dacpd_mask = BIT(24),
+       .dsmpd_mask = BIT(25)
+};
+
+static const struct starfive_pllx_offset jh7110_pll1_offset = {
+       .pd = 0x28,
+       .prediv = 0x2c,
+       .fbdiv = 0x24,
+       .frac = 0x28,
+       .postdiv1 = 0x28,
+       .dacpd = 0x24,
+       .dsmpd = 0x24,
+       .pd_mask = BIT(27),
+       .prediv_mask = GENMASK(5, 0),
+       .fbdiv_mask = GENMASK(28, 17),
+       .frac_mask = GENMASK(23, 0),
+       .postdiv1_mask = GENMASK(29, 28),
+       .dacpd_mask = BIT(15),
+       .dsmpd_mask = BIT(16)
+};
+
+static const struct starfive_pllx_offset jh7110_pll2_offset = {
+       .pd = 0x30,
+       .prediv = 0x34,
+       .fbdiv = 0x2c,
+       .frac = 0x30,
+       .postdiv1 = 0x30,
+       .dacpd = 0x2c,
+       .dsmpd = 0x2c,
+       .pd_mask = BIT(27),
+       .prediv_mask = GENMASK(5, 0),
+       .fbdiv_mask = GENMASK(28, 17),
+       .frac_mask = GENMASK(23, 0),
+       .postdiv1_mask = GENMASK(29, 28),
+       .dacpd_mask = BIT(15),
+       .dsmpd_mask = BIT(16)
+};
+
+struct starfive_pllx_clk starfive_jh7110_pll0 __initdata = {
+       .type = PLL0,
+       .offset = &jh7110_pll0_offset,
+       .rate_table = jh7110_pll0_tbl,
+       .rate_count = ARRAY_SIZE(jh7110_pll0_tbl),
+};
+
+struct starfive_pllx_clk starfive_jh7110_pll1 __initdata = {
+       .type = PLL1,
+       .offset = &jh7110_pll1_offset,
+       .rate_table = jh7110_pll1_tbl,
+       .rate_count = ARRAY_SIZE(jh7110_pll1_tbl),
+};
+
+struct starfive_pllx_clk starfive_jh7110_pll2 __initdata = {
+       .type = PLL2,
+       .offset = &jh7110_pll2_offset,
+       .rate_table = jh7110_pll2_tbl,
+       .rate_count = ARRAY_SIZE(jh7110_pll2_tbl),
+};
+
+static const struct starfive_pllx_rate *
+jh7110_get_pll_settings(struct clk_jh7110_pllx *pll, unsigned long rate)
+{
+       for (int i = 0; i < pll->rate_count; i++)
+               if (rate == pll->rate_table[i].rate)
+                       return &pll->rate_table[i];
+
+       return NULL;
+}
+
+static void jh7110_pll_set_rate(struct clk_jh7110_pllx *pll,
+                               const struct starfive_pllx_rate *rate)
+{
+       u32 reg;
+       bool set = (pll->type == PLL1) ? true : false;
+
+       if (set) {
+               reg = readl((ulong *)((ulong)pll->sysreg + CLK_DDR_BUS_OFFSET));
+               reg &= ~CLK_DDR_BUS_MASK;
+               reg |= CLK_DDR_BUS_OSC_DIV2 << __ffs(CLK_DDR_BUS_MASK);
+               writel(reg, (ulong *)((ulong)pll->sysreg + CLK_DDR_BUS_OFFSET));
+       }
+
+       PLLX_SET(pll->offset->pd, pll->offset->pd_mask, PLL_PD_OFF);
+       PLLX_SET(pll->offset->dacpd, pll->offset->dacpd_mask, 1);
+       PLLX_SET(pll->offset->dsmpd, pll->offset->dsmpd_mask, 1);
+       PLLX_SET(pll->offset->prediv, pll->offset->prediv_mask, rate->prediv);
+       PLLX_SET(pll->offset->fbdiv, pll->offset->fbdiv_mask, rate->fbdiv);
+       PLLX_SET(pll->offset->postdiv1, pll->offset->postdiv1, 0);
+       PLLX_SET(pll->offset->pd, pll->offset->pd_mask, PLL_PD_ON);
+
+       if (set) {
+               udelay(100);
+               reg = readl((ulong *)((ulong)pll->sysreg + CLK_DDR_BUS_OFFSET));
+               reg &= ~CLK_DDR_BUS_MASK;
+               reg |= CLK_DDR_BUS_PLL1_DIV2 << __ffs(CLK_DDR_BUS_MASK);
+               writel(reg, (ulong *)((ulong)pll->sysreg + CLK_DDR_BUS_OFFSET));
+       }
+}
+
+static ulong jh7110_pllx_recalc_rate(struct clk *clk)
+{
+       struct clk_jh7110_pllx *pll = to_clk_pllx(dev_get_clk_ptr(clk->dev));
+       u64 refclk = clk_get_parent_rate(clk);
+       u32 dacpd, dsmpd;
+       u32 prediv, fbdiv, postdiv1;
+       u64 frac;
+
+       dacpd = getbits_le32((ulong)pll->base + pll->offset->dacpd,
+                            pll->offset->dacpd_mask);
+       dsmpd = getbits_le32((ulong)pll->base + pll->offset->dsmpd,
+                            pll->offset->dsmpd_mask);
+       prediv = getbits_le32((ulong)pll->base + pll->offset->prediv,
+                             pll->offset->prediv_mask);
+       fbdiv = getbits_le32((ulong)pll->base + pll->offset->fbdiv,
+                            pll->offset->fbdiv_mask);
+       postdiv1 = 1 << getbits_le32((ulong)pll->base + pll->offset->postdiv1,
+                       pll->offset->postdiv1_mask);
+       frac = (u64)getbits_le32((ulong)pll->base + pll->offset->frac,
+                       pll->offset->frac_mask);
+
+       /* Integer Multiple Mode
+        * Both dacpd and dsmpd should be set as 1 while integer multiple mode.
+        *
+        * The frequency of outputs can be figured out as below.
+        *
+     *       Fvco = Fref*Nl/M
+        * NI is integer frequency dividing ratio of feedback divider, set by fbdiv1[11:0] ,
+        *    NI = 8, 9, 10, 12.13....4095
+        * M is frequency dividing ratio of pre-divider, set by prediv[5:0],M = 1,2...63
+        *
+     *      Fclko1 = Fvco/Q1
+        * Q1 is frequency dividing ratio of post divider, set by postdiv1[1:0],Q1= 1,2,4,8
+        *
+        * Fraction Multiple Mode
+        *
+        *  Both dacpd and dsmpd should be set as 0 while integer multiple mode.
+        *
+     *      Fvco = Fref*(NI+NF)/M
+        * NI is integer frequency dividing ratio of feedback divider, set by fbdiv[11:0] ,
+        *     NI = 8, 9, 10, 12.13....4095
+        * NF is fractional frequency dividing ratio, set by frac[23:0],  NF =frac[23:0]/2^24= 0~0.99999994
+        * M is frequency dividing ratio of pre-divider, set by prediv[5:0],M = 1,2...63
+        *
+     *     Fclko1 = Fvco/Q1
+        * Q1 is frequency dividing ratio of post divider, set by postdivl[1:0],Q1= 1,2,4,8
+        */
+       if (dacpd == 1 && dsmpd == 1)
+               frac = 0;
+       else if (dacpd == 0 && dsmpd == 0)
+               do_div(frac, 1 << 24);
+       else
+               return -EINVAL;
+
+       refclk *= (fbdiv + frac);
+       do_div(refclk, prediv * postdiv1);
+
+       return refclk;
+}
+
+static ulong jh7110_pllx_set_rate(struct clk *clk, ulong drate)
+{
+       struct clk_jh7110_pllx *pll = to_clk_pllx(dev_get_clk_ptr(clk->dev));
+       const struct starfive_pllx_rate *rate;
+
+       rate = jh7110_get_pll_settings(pll, drate);
+       if (!rate)
+               return -EINVAL;
+
+       jh7110_pll_set_rate(pll, rate);
+
+       return jh7110_pllx_recalc_rate(clk);
+}
+
+static const struct clk_ops clk_jh7110_ops = {
+       .set_rate       = jh7110_pllx_set_rate,
+       .get_rate       = jh7110_pllx_recalc_rate,
+};
+
+struct clk *starfive_jh7110_pll(const char *name, const char *parent_name,
+                               void __iomem *base, void __iomem *sysreg,
+                               const struct starfive_pllx_clk *pll_clk)
+{
+       struct clk_jh7110_pllx *pll;
+       struct clk *clk;
+       int ret;
+
+       if (!pll_clk || !base || !sysreg)
+               return ERR_PTR(-EINVAL);
+
+       pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+       if (!pll)
+               return ERR_PTR(-ENOMEM);
+
+       pll->base = base;
+       pll->sysreg = sysreg;
+       pll->type = pll_clk->type;
+       pll->offset = pll_clk->offset;
+       pll->rate_table = pll_clk->rate_table;
+       pll->rate_count = pll_clk->rate_count;
+
+       clk = &pll->clk;
+       ret = clk_register(clk, UBOOT_DM_CLK_JH7110_PLLX, name, parent_name);
+       if (ret) {
+               kfree(pll);
+               return ERR_PTR(ret);
+       }
+
+       if (IS_ENABLED(CONFIG_SPL_BUILD) && pll->type == PLL0)
+               jh7110_pllx_set_rate(clk, 1000000000);
+
+       if (IS_ENABLED(CONFIG_SPL_BUILD) && pll->type == PLL2)
+               jh7110_pllx_set_rate(clk, 1188000000);
+
+       return clk;
+}
+
+U_BOOT_DRIVER(jh7110_clk_pllx) = {
+       .name   = UBOOT_DM_CLK_JH7110_PLLX,
+       .id     = UCLASS_CLK,
+       .ops    = &clk_jh7110_ops,
+};

diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c
new file mode 100644 (file)
index 0000000..a74b709
--- /dev/null
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -0,0 +1,603 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022-23 StarFive Technology Co., Ltd.
+ *
+ * Author:     Yanhong Wang <yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/device.h>
+#include <dm/devres.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+#include <log.h>
+#include <linux/clk-provider.h>
+
+#include "clk.h"
+
+#define STARFIVE_CLK_ENABLE_SHIFT      31 /* [31] */
+#define STARFIVE_CLK_INVERT_SHIFT      30 /* [30] */
+#define STARFIVE_CLK_MUX_SHIFT         24 /* [29:24] */
+#define STARFIVE_CLK_DIV_SHIFT         0  /* [23:0] */
+
+#define OFFSET(id) ((id) * 4)
+#define AONOFFSET(id) (((id) - JH7110_SYSCLK_END) * 4)
+#define STGOFFSET(id) (((id) - JH7110_AONCLK_END) * 4)
+
+typedef int (*jh1710_init_fn)(struct udevice *dev);
+
+struct jh7110_clk_priv {
+       void __iomem *reg;
+       jh1710_init_fn init;
+};
+
+static const char *cpu_root_sels[2] = {
+       [0] = "oscillator",
+       [1] = "pll0_out",
+};
+
+static const char *perh_root_sels[2] = {
+       [0] = "pll0_out",
+       [1] = "pll2_out",
+};
+
+static const char *bus_root_sels[2] = {
+       [0] = "oscillator",
+       [1] = "pll2_out",
+};
+
+static const char *qspi_ref_sels[2] = {
+       [0] = "oscillator",
+       [1] = "qspi_ref_src",
+};
+
+static const char *gmac1_tx_sels[2] = {
+       [0] = "gmac1_gtxclk",
+       [1] = "gmac1_rmii_rtx",
+};
+
+static const char *gmac0_tx_sels[2] = {
+       [0] = "gmac0_gtxclk",
+       [1] = "gmac0_rmii_rtx",
+};
+
+static const char *apb_func_sels[2] = {
+       [0] = "osc_div4",
+       [1] = "oscillator",
+};
+
+static const char *gmac1_rx_sels[2] = {
+       [0] = "gmac1-rgmii-rxin-clock",
+       [1] = "gmac1_rmii_rtx",
+};
+
+static struct clk *starfive_clk_mux(void __iomem *reg,
+                                   const char *name,
+                                   unsigned int offset,
+                                   u8 width,
+                                   const char * const *parent_names,
+                                   u8 num_parents)
+{
+       return  clk_register_mux(NULL, name, parent_names, num_parents, 0,
+                               reg + offset, STARFIVE_CLK_MUX_SHIFT,
+                               width, 0);
+}
+
+static struct clk *starfive_clk_gate(void __iomem *reg,
+                                    const char *name,
+                                    const char *parent_name,
+                                    unsigned int offset)
+{
+       return clk_register_gate(NULL, name, parent_name, 0, reg + offset,
+                               STARFIVE_CLK_ENABLE_SHIFT, 0, NULL);
+}
+
+static struct clk *starfive_clk_inv(void __iomem *reg,
+                                   const char *name,
+                                   const char *parent_name,
+                                   unsigned int offset)
+{
+       return clk_register_gate(NULL, name, parent_name, 0, reg + offset,
+                               STARFIVE_CLK_INVERT_SHIFT, 0, NULL);
+}
+
+static struct clk *starfive_clk_divider(void __iomem *reg,
+                                       const char *name,
+                                       const char *parent_name,
+                                       unsigned int offset,
+                                       u8 width)
+{
+       return clk_register_divider(NULL, name, parent_name, 0, reg + offset,
+                               0, width, CLK_DIVIDER_ONE_BASED);
+}
+
+static struct clk *starfive_clk_composite(void __iomem *reg,
+                                         const char *name,
+                                         const char * const *parent_names,
+                                         unsigned int num_parents,
+                                         unsigned int offset,
+                                         unsigned int mux_width,
+                                         unsigned int gate_width,
+                                         unsigned int div_width)
+{
+       struct clk *clk = ERR_PTR(-ENOMEM);
+       struct clk_divider *div = NULL;
+       struct clk_gate *gate = NULL;
+       struct clk_mux *mux = NULL;
+       int mask_arry[4] = {0x1, 0x3, 0x7, 0xF};
+       int mask;
+
+       if (mux_width) {
+               if (mux_width > 4)
+                       goto fail;
+               else
+                       mask = mask_arry[mux_width - 1];
+
+               mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+               if (!mux)
+                       goto fail;
+
+               mux->reg = reg + offset;
+               mux->mask = mask;
+               mux->shift = STARFIVE_CLK_MUX_SHIFT;
+               mux->num_parents = num_parents;
+               mux->flags = 0;
+               mux->parent_names = parent_names;
+       }
+
+       if (gate_width) {
+               gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+
+               if (!gate)
+                       goto fail;
+
+               gate->reg = reg + offset;
+               gate->bit_idx = STARFIVE_CLK_ENABLE_SHIFT;
+               gate->flags = 0;
+       }
+
+       if (div_width) {
+               div = kzalloc(sizeof(*div), GFP_KERNEL);
+               if (!div)
+                       goto fail;
+
+               div->reg = reg + offset;
+
+               if (offset == OFFSET(JH7110_SYSCLK_UART3_CORE) ||
+                   offset == OFFSET(JH7110_SYSCLK_UART4_CORE) ||
+                   offset == OFFSET(JH7110_SYSCLK_UART5_CORE)) {
+                       div->shift = 8;
+                       div->width = 8;
+               } else {
+                       div->shift = STARFIVE_CLK_DIV_SHIFT;
+                       div->width = div_width;
+               }
+               div->flags = CLK_DIVIDER_ONE_BASED;
+               div->table = NULL;
+       }
+
+       clk = clk_register_composite(NULL, name,
+                                    parent_names, num_parents,
+                                    &mux->clk, &clk_mux_ops,
+                                    &div->clk, &clk_divider_ops,
+                                    &gate->clk, &clk_gate_ops, 0);
+
+       if (IS_ERR(clk))
+               goto fail;
+
+       return clk;
+
+fail:
+       kfree(gate);
+       kfree(div);
+       kfree(mux);
+       return ERR_CAST(clk);
+}
+
+static struct clk *starfive_clk_fix_parent_composite(void __iomem *reg,
+                                                    const char *name,
+                                                    const char *parent_names,
+                                                    unsigned int offset,
+                                                    unsigned int mux_width,
+                                                    unsigned int gate_width,
+                                                    unsigned int div_width)
+{
+       const char * const *parents;
+
+       parents  = &parent_names;
+
+       return starfive_clk_composite(reg, name, parents, 1, offset,
+                       mux_width, gate_width, div_width);
+}
+
+static struct clk *starfive_clk_gate_divider(void __iomem *reg,
+                                            const char *name,
+                                            const char *parent,
+                                            unsigned int offset,
+                                            unsigned int width)
+{
+       const char * const *parent_names;
+
+       parent_names  = &parent;
+
+       return starfive_clk_composite(reg, name, parent_names, 1,
+                               offset, 0, 1, width);
+}
+
+static int jh7110_syscrg_init(struct udevice *dev)
+{
+       struct jh7110_clk_priv *priv = dev_get_priv(dev);
+       struct ofnode_phandle_args args;
+       fdt_addr_t addr;
+       struct clk *pclk;
+       int ret;
+
+       ret = ofnode_parse_phandle_with_args(dev->node_, "starfive,sys-syscon", NULL, 0, 0, &args);
+       if (ret)
+               return ret;
+
+       addr =  ofnode_get_addr(args.node);
+       if (addr == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       clk_dm(JH7110_SYSCLK_PLL0_OUT,
+              starfive_jh7110_pll("pll0_out", "oscillator", (void __iomem *)addr,
+                                  priv->reg, &starfive_jh7110_pll0));
+       clk_dm(JH7110_SYSCLK_PLL1_OUT,
+              starfive_jh7110_pll("pll1_out", "oscillator", (void __iomem *)addr,
+                                  priv->reg, &starfive_jh7110_pll1));
+       clk_dm(JH7110_SYSCLK_PLL2_OUT,
+              starfive_jh7110_pll("pll2_out", "oscillator", (void __iomem *)addr,
+                                  priv->reg, &starfive_jh7110_pll2));
+       clk_dm(JH7110_SYSCLK_CPU_ROOT,
+              starfive_clk_mux(priv->reg, "cpu_root",
+                               OFFSET(JH7110_SYSCLK_CPU_ROOT), 1,
+                               cpu_root_sels, ARRAY_SIZE(cpu_root_sels)));
+       clk_dm(JH7110_SYSCLK_CPU_CORE,
+              starfive_clk_divider(priv->reg,
+                                   "cpu_core", "cpu_root",
+                                   OFFSET(JH7110_SYSCLK_CPU_CORE), 3));
+       clk_dm(JH7110_SYSCLK_CPU_BUS,
+              starfive_clk_divider(priv->reg,
+                                   "cpu_bus", "cpu_core",
+                                   OFFSET(JH7110_SYSCLK_CPU_BUS), 2));
+       clk_dm(JH7110_SYSCLK_PERH_ROOT,
+              starfive_clk_composite(priv->reg,
+                                     "perh_root",
+                                     perh_root_sels, ARRAY_SIZE(perh_root_sels),
+                                     OFFSET(JH7110_SYSCLK_PERH_ROOT), 1, 0, 2));
+       clk_dm(JH7110_SYSCLK_BUS_ROOT,
+              starfive_clk_mux(priv->reg, "bus_root",
+                               OFFSET(JH7110_SYSCLK_BUS_ROOT), 1,
+                               bus_root_sels,  ARRAY_SIZE(bus_root_sels)));
+       clk_dm(JH7110_SYSCLK_NOCSTG_BUS,
+              starfive_clk_divider(priv->reg,
+                                   "nocstg_bus", "bus_root",
+                                   OFFSET(JH7110_SYSCLK_NOCSTG_BUS), 3));
+       clk_dm(JH7110_SYSCLK_AXI_CFG0,
+              starfive_clk_divider(priv->reg,
+                                   "axi_cfg0", "bus_root",
+                                   OFFSET(JH7110_SYSCLK_AXI_CFG0), 2));
+       clk_dm(JH7110_SYSCLK_STG_AXIAHB,
+              starfive_clk_divider(priv->reg,
+                                   "stg_axiahb", "axi_cfg0",
+                                   OFFSET(JH7110_SYSCLK_STG_AXIAHB), 2));
+       clk_dm(JH7110_SYSCLK_AHB0,
+              starfive_clk_gate(priv->reg,
+                                "ahb0", "stg_axiahb",
+                                OFFSET(JH7110_SYSCLK_AHB0)));
+       clk_dm(JH7110_SYSCLK_AHB1,
+              starfive_clk_gate(priv->reg,
+                                "ahb1", "stg_axiahb",
+                                OFFSET(JH7110_SYSCLK_AHB1)));
+       clk_dm(JH7110_SYSCLK_APB_BUS,
+              starfive_clk_divider(priv->reg,
+                                   "apb_bus", "stg_axiahb",
+                                   OFFSET(JH7110_SYSCLK_APB_BUS), 4));
+       clk_dm(JH7110_SYSCLK_APB0,
+              starfive_clk_gate(priv->reg,
+                                "apb0", "apb_bus",
+                                OFFSET(JH7110_SYSCLK_APB0)));
+       clk_dm(JH7110_SYSCLK_QSPI_AHB,
+              starfive_clk_gate(priv->reg,
+                                "qspi_ahb", "ahb1",
+                                OFFSET(JH7110_SYSCLK_QSPI_AHB)));
+       clk_dm(JH7110_SYSCLK_QSPI_APB,
+              starfive_clk_gate(priv->reg,
+                                "qspi_apb", "apb_bus",
+                                OFFSET(JH7110_SYSCLK_QSPI_APB)));
+       clk_dm(JH7110_SYSCLK_QSPI_REF_SRC,
+              starfive_clk_divider(priv->reg,
+                                   "qspi_ref_src", "pll0_out",
+                                   OFFSET(JH7110_SYSCLK_QSPI_REF_SRC), 5));
+       clk_dm(JH7110_SYSCLK_QSPI_REF,
+              starfive_clk_composite(priv->reg,
+                                     "qspi_ref",
+                                     qspi_ref_sels, ARRAY_SIZE(qspi_ref_sels),
+                                     OFFSET(JH7110_SYSCLK_QSPI_REF), 1, 1, 0));
+       clk_dm(JH7110_SYSCLK_SDIO0_AHB,
+              starfive_clk_gate(priv->reg,
+                                "sdio0_ahb", "ahb0",
+                                OFFSET(JH7110_SYSCLK_SDIO0_AHB)));
+       clk_dm(JH7110_SYSCLK_SDIO1_AHB,
+              starfive_clk_gate(priv->reg,
+                                "sdio1_ahb", "ahb0",
+                                OFFSET(JH7110_SYSCLK_SDIO1_AHB)));
+       clk_dm(JH7110_SYSCLK_SDIO0_SDCARD,
+              starfive_clk_fix_parent_composite(priv->reg,
+                                                "sdio0_sdcard", "axi_cfg0",
+                                                OFFSET(JH7110_SYSCLK_SDIO0_SDCARD), 0, 1, 4));
+       clk_dm(JH7110_SYSCLK_SDIO1_SDCARD,
+              starfive_clk_fix_parent_composite(priv->reg,
+                                                "sdio1_sdcard", "axi_cfg0",
+                                                OFFSET(JH7110_SYSCLK_SDIO1_SDCARD), 0, 1, 4));
+       clk_dm(JH7110_SYSCLK_USB_125M,
+              starfive_clk_divider(priv->reg,
+                                   "usb_125m", "pll0_out",
+                                   OFFSET(JH7110_SYSCLK_USB_125M), 4));
+       clk_dm(JH7110_SYSCLK_NOC_BUS_STG_AXI,
+              starfive_clk_gate(priv->reg,
+                                "noc_bus_stg_axi", "nocstg_bus",
+                                OFFSET(JH7110_SYSCLK_NOC_BUS_STG_AXI)));
+       clk_dm(JH7110_SYSCLK_GMAC1_AHB,
+              starfive_clk_gate(priv->reg,
+                                "gmac1_ahb", "ahb0",
+                                OFFSET(JH7110_SYSCLK_GMAC1_AHB)));
+       clk_dm(JH7110_SYSCLK_GMAC1_AXI,
+              starfive_clk_gate(priv->reg,
+                                "gmac1_axi", "stg_axiahb",
+                                OFFSET(JH7110_SYSCLK_GMAC1_AXI)));
+       clk_dm(JH7110_SYSCLK_GMAC_SRC,
+              starfive_clk_divider(priv->reg,
+                                   "gmac_src", "pll0_out",
+                                   OFFSET(JH7110_SYSCLK_GMAC_SRC), 3));
+       clk_dm(JH7110_SYSCLK_GMAC1_GTXCLK,
+              starfive_clk_divider(priv->reg,
+                                   "gmac1_gtxclk", "pll0_out",
+                                   OFFSET(JH7110_SYSCLK_GMAC1_GTXCLK), 4));
+       clk_dm(JH7110_SYSCLK_GMAC1_GTXC,
+              starfive_clk_gate(priv->reg,
+                                "gmac1_gtxc", "gmac1_gtxclk",
+                                OFFSET(JH7110_SYSCLK_GMAC1_GTXC)));
+       clk_dm(JH7110_SYSCLK_GMAC1_RMII_RTX,
+              starfive_clk_divider(priv->reg,
+                                   "gmac1_rmii_rtx", "gmac1-rmii-refin-clock",
+                                   OFFSET(JH7110_SYSCLK_GMAC1_RMII_RTX), 5));
+       clk_dm(JH7110_SYSCLK_GMAC1_PTP,
+              starfive_clk_gate_divider(priv->reg,
+                                        "gmac1_ptp", "gmac_src",
+                                        OFFSET(JH7110_SYSCLK_GMAC1_PTP), 5));
+       clk_dm(JH7110_SYSCLK_GMAC1_RX,
+              starfive_clk_mux(priv->reg, "gmac1_rx",
+                               OFFSET(JH7110_SYSCLK_GMAC1_RX), 1,
+                               gmac1_rx_sels,  ARRAY_SIZE(gmac1_rx_sels)));
+       clk_dm(JH7110_SYSCLK_GMAC1_TX,
+              starfive_clk_composite(priv->reg,
+                                     "gmac1_tx",
+                                     gmac1_tx_sels, ARRAY_SIZE(gmac1_tx_sels),
+                                     OFFSET(JH7110_SYSCLK_GMAC1_TX), 1, 1, 0));
+       clk_dm(JH7110_SYSCLK_GMAC1_TX_INV,
+              starfive_clk_inv(priv->reg,
+                               "gmac1_tx_inv", "gmac1_tx",
+                               OFFSET(JH7110_SYSCLK_GMAC1_TX_INV)));
+       clk_dm(JH7110_SYSCLK_GMAC0_GTXCLK,
+              starfive_clk_gate_divider(priv->reg,
+                                        "gmac0_gtxclk", "pll0_out",
+                                        OFFSET(JH7110_SYSCLK_GMAC0_GTXCLK), 4));
+       clk_dm(JH7110_SYSCLK_GMAC0_PTP,
+              starfive_clk_gate_divider(priv->reg,
+                                        "gmac0_ptp", "gmac_src",
+                                        OFFSET(JH7110_SYSCLK_GMAC0_PTP), 5));
+       clk_dm(JH7110_SYSCLK_GMAC0_GTXC,
+              starfive_clk_gate(priv->reg,
+                                "gmac0_gtxc", "gmac0_gtxclk",
+                                OFFSET(JH7110_SYSCLK_GMAC0_GTXC)));
+       clk_dm(JH7110_SYSCLK_UART0_APB,
+              starfive_clk_gate(priv->reg,
+                                "uart0_apb", "apb0",
+                                OFFSET(JH7110_SYSCLK_UART0_APB)));
+       clk_dm(JH7110_SYSCLK_UART0_CORE,
+              starfive_clk_gate(priv->reg,
+                                "uart0_core", "oscillator",
+                                OFFSET(JH7110_SYSCLK_UART0_CORE)));
+       clk_dm(JH7110_SYSCLK_UART1_APB,
+              starfive_clk_gate(priv->reg,
+                                "uart1_apb", "apb0",
+                                OFFSET(JH7110_SYSCLK_UART1_APB)));
+       clk_dm(JH7110_SYSCLK_UART1_CORE,
+              starfive_clk_gate(priv->reg,
+                                "uart1_core", "oscillator",
+                                OFFSET(JH7110_SYSCLK_UART1_CORE)));
+       clk_dm(JH7110_SYSCLK_UART2_APB,
+              starfive_clk_gate(priv->reg,
+                                "uart2_apb", "apb0",
+                                OFFSET(JH7110_SYSCLK_UART2_APB)));
+       clk_dm(JH7110_SYSCLK_UART2_CORE,
+              starfive_clk_gate(priv->reg,
+                                "uart2_core", "oscillator",
+                                OFFSET(JH7110_SYSCLK_UART2_CORE)));
+       clk_dm(JH7110_SYSCLK_UART3_APB,
+              starfive_clk_gate(priv->reg,
+                                "uart3_apb", "apb0",
+                                OFFSET(JH7110_SYSCLK_UART3_APB)));
+       clk_dm(JH7110_SYSCLK_UART3_CORE,
+              starfive_clk_gate_divider(priv->reg,
+                                        "uart3_core", "perh_root",
+                                        OFFSET(JH7110_SYSCLK_UART3_CORE), 8));
+       clk_dm(JH7110_SYSCLK_UART4_APB,
+              starfive_clk_gate(priv->reg,
+                                "uart4_apb", "apb0",
+                                OFFSET(JH7110_SYSCLK_UART4_APB)));
+       clk_dm(JH7110_SYSCLK_UART4_CORE,
+              starfive_clk_gate_divider(priv->reg,
+                                        "uart4_core", "perh_root",
+                                        OFFSET(JH7110_SYSCLK_UART4_CORE), 8));
+       clk_dm(JH7110_SYSCLK_UART5_APB,
+              starfive_clk_gate(priv->reg,
+                                "uart5_apb", "apb0",
+                                OFFSET(JH7110_SYSCLK_UART5_APB)));
+       clk_dm(JH7110_SYSCLK_UART5_CORE,
+              starfive_clk_gate_divider(priv->reg,
+                                        "uart5_core", "perh_root",
+                                        OFFSET(JH7110_SYSCLK_UART5_CORE), 8));
+       clk_dm(JH7110_SYSCLK_I2C2_APB,
+              starfive_clk_gate(priv->reg,
+                                "i2c2_apb", "apb0",
+                                OFFSET(JH7110_SYSCLK_I2C2_APB)));
+       clk_dm(JH7110_SYSCLK_I2C5_APB,
+              starfive_clk_gate(priv->reg,
+                                "i2c5_apb", "apb0",
+                                OFFSET(JH7110_SYSCLK_I2C5_APB)));
+
+       /* enable noc_bus_stg_axi clock */
+       if (!clk_get_by_id(JH7110_SYSCLK_NOC_BUS_STG_AXI, &pclk))
+               clk_enable(pclk);
+
+       return 0;
+}
+
+static int jh7110_aoncrg_init(struct udevice *dev)
+{
+       struct jh7110_clk_priv *priv = dev_get_priv(dev);
+
+       clk_dm(JH7110_AONCLK_OSC_DIV4,
+              starfive_clk_divider(priv->reg,
+                                   "osc_div4", "oscillator",
+                                   AONOFFSET(JH7110_AONCLK_OSC_DIV4), 5));
+       clk_dm(JH7110_AONCLK_APB_FUNC,
+              starfive_clk_mux(priv->reg, "apb_func",
+                               AONOFFSET(JH7110_AONCLK_APB_FUNC), 1,
+                               apb_func_sels,  ARRAY_SIZE(apb_func_sels)));
+       clk_dm(JH7110_AONCLK_GMAC0_AHB,
+              starfive_clk_gate(priv->reg,
+                                "gmac0_ahb", "stg_axiahb",
+                                AONOFFSET(JH7110_AONCLK_GMAC0_AHB)));
+       clk_dm(JH7110_AONCLK_GMAC0_AXI,
+              starfive_clk_gate(priv->reg,
+                                "gmac0_axi", "stg_axiahb",
+                                AONOFFSET(JH7110_AONCLK_GMAC0_AXI)));
+       clk_dm(JH7110_AONCLK_GMAC0_RMII_RTX,
+              starfive_clk_divider(priv->reg,
+                                   "gmac0_rmii_rtx", "gmac0-rmii-refin-clock",
+                                   AONOFFSET(JH7110_AONCLK_GMAC0_RMII_RTX), 5));
+       clk_dm(JH7110_AONCLK_GMAC0_TX,
+              starfive_clk_composite(priv->reg,
+                                     "gmac0_tx", gmac0_tx_sels,
+                                     ARRAY_SIZE(gmac0_tx_sels),
+                                     AONOFFSET(JH7110_AONCLK_GMAC0_TX), 1, 1, 0));
+       clk_dm(JH7110_AONCLK_GMAC0_TX_INV,
+              starfive_clk_inv(priv->reg,
+                               "gmac0_tx_inv", "gmac0_tx",
+                               AONOFFSET(JH7110_AONCLK_GMAC0_TX_INV)));
+       clk_dm(JH7110_AONCLK_OTPC_APB,
+              starfive_clk_gate(priv->reg,
+                                "otpc_apb", "apb_bus",
+                                AONOFFSET(JH7110_AONCLK_OTPC_APB)));
+
+       return 0;
+}
+
+static int jh7110_stgcrg_init(struct udevice *dev)
+{
+       struct jh7110_clk_priv *priv = dev_get_priv(dev);
+
+       clk_dm(JH7110_STGCLK_USB_APB,
+              starfive_clk_gate(priv->reg,
+                                "usb_apb", "apb_bus",
+                                STGOFFSET(JH7110_STGCLK_USB_APB)));
+       clk_dm(JH7110_STGCLK_USB_UTMI_APB,
+              starfive_clk_gate(priv->reg,
+                                "usb_utmi_apb", "apb_bus",
+                                STGOFFSET(JH7110_STGCLK_USB_UTMI_APB)));
+       clk_dm(JH7110_STGCLK_USB_AXI,
+              starfive_clk_gate(priv->reg,
+                                "usb_axi", "stg_axiahb",
+                                STGOFFSET(JH7110_STGCLK_USB_AXI)));
+       clk_dm(JH7110_STGCLK_USB_LPM,
+              starfive_clk_gate_divider(priv->reg,
+                                        "usb_lpm", "oscillator",
+                                        STGOFFSET(JH7110_STGCLK_USB_LPM), 2));
+       clk_dm(JH7110_STGCLK_USB_STB,
+              starfive_clk_gate_divider(priv->reg,
+                                        "usb_stb", "oscillator",
+                                        STGOFFSET(JH7110_STGCLK_USB_STB), 3));
+       clk_dm(JH7110_STGCLK_USB_APP_125,
+              starfive_clk_gate(priv->reg,
+                                "usb_app_125", "usb_125m",
+                                STGOFFSET(JH7110_STGCLK_USB_APP_125)));
+       clk_dm(JH7110_STGCLK_USB_REFCLK,
+              starfive_clk_divider(priv->reg, "usb_refclk", "oscillator",
+                                   STGOFFSET(JH7110_STGCLK_USB_REFCLK), 2));
+       clk_dm(JH7110_STGCLK_PCIE0_AXI,
+              starfive_clk_gate(priv->reg,
+                                "pcie0_axi", "stg_axiahb",
+                                STGOFFSET(JH7110_STGCLK_PCIE0_AXI)));
+       clk_dm(JH7110_STGCLK_PCIE0_APB,
+              starfive_clk_gate(priv->reg,
+                                "pcie0_apb", "apb_bus",
+                                STGOFFSET(JH7110_STGCLK_PCIE0_APB)));
+       clk_dm(JH7110_STGCLK_PCIE0_TL,
+              starfive_clk_gate(priv->reg,
+                                "pcie0_tl", "stg_axiahb",
+                                STGOFFSET(JH7110_STGCLK_PCIE0_TL)));
+       clk_dm(JH7110_STGCLK_PCIE1_AXI,
+              starfive_clk_gate(priv->reg,
+                                "pcie1_axi", "stg_axiahb",
+                                STGOFFSET(JH7110_STGCLK_PCIE1_AXI)));
+       clk_dm(JH7110_STGCLK_PCIE1_APB,
+              starfive_clk_gate(priv->reg,
+                                "pcie1_apb", "apb_bus",
+                                STGOFFSET(JH7110_STGCLK_PCIE1_APB)));
+       clk_dm(JH7110_STGCLK_PCIE1_TL,
+              starfive_clk_gate(priv->reg,
+                                "pcie1_tl", "stg_axiahb",
+                                STGOFFSET(JH7110_STGCLK_PCIE1_TL)));
+
+       return 0;
+}
+
+static int jh7110_clk_probe(struct udevice *dev)
+{
+       struct jh7110_clk_priv *priv = dev_get_priv(dev);
+
+       priv->init = (jh1710_init_fn)dev_get_driver_data(dev);
+       priv->reg =  (void __iomem *)dev_read_addr_ptr(dev);
+
+       if (priv->init)
+               return priv->init(dev);
+
+       return 0;
+}
+
+static int jh7110_clk_bind(struct udevice *dev)
+{
+       /* The reset driver does not have a device node, so bind it here */
+       return device_bind_driver_to_node(dev, "jh7110_reset", dev->name,
+                                                       dev_ofnode(dev), NULL);
+}
+
+static const struct udevice_id jh7110_clk_of_match[] = {
+       { .compatible = "starfive,jh7110-syscrg",
+         .data = (ulong)&jh7110_syscrg_init
+       },
+       { .compatible = "starfive,jh7110-stgcrg",
+         .data = (ulong)&jh7110_stgcrg_init
+       },
+       { .compatible = "starfive,jh7110-aoncrg",
+         .data = (ulong)&jh7110_aoncrg_init
+       },
+       { }
+};
+
+U_BOOT_DRIVER(jh7110_clk) = {
+       .name = "jh7110_clk",
+       .id = UCLASS_CLK,
+       .of_match = jh7110_clk_of_match,
+       .probe = jh7110_clk_probe,
+       .ops = &ccf_clk_ops,
+       .priv_auto = sizeof(struct jh7110_clk_priv),
+       .bind           = jh7110_clk_bind,
+};

diff --git a/drivers/clk/starfive/clk.h b/drivers/clk/starfive/clk.h
new file mode 100644 (file)
index 0000000..4dee12f
--- /dev/null
+++ b/drivers/clk/starfive/clk.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 Starfive, Inc.
+ * Author:     Yanhong Wang <yanhong.wang@starfivetech.com>
+ *
+ */
+
+#ifndef __CLK_STARFIVE_H
+#define __CLK_STARFIVE_H
+
+enum starfive_pll_type {
+       PLL0 = 0,
+       PLL1,
+       PLL2,
+       PLL_MAX = PLL2
+};
+
+struct starfive_pllx_rate {
+       u64 rate;
+       u32 prediv;
+       u32 fbdiv;
+       u32 frac;
+};
+
+struct starfive_pllx_offset {
+       u32 pd;
+       u32 prediv;
+       u32 fbdiv;
+       u32 frac;
+       u32 postdiv1;
+       u32 dacpd;
+       u32 dsmpd;
+       u32 pd_mask;
+       u32 prediv_mask;
+       u32 fbdiv_mask;
+       u32 frac_mask;
+       u32 postdiv1_mask;
+       u32 dacpd_mask;
+       u32 dsmpd_mask;
+};
+
+struct starfive_pllx_clk {
+       enum starfive_pll_type type;
+       const struct starfive_pllx_offset *offset;
+       const struct starfive_pllx_rate *rate_table;
+       int rate_count;
+       int flags;
+};
+
+extern struct starfive_pllx_clk starfive_jh7110_pll0;
+extern struct starfive_pllx_clk starfive_jh7110_pll1;
+extern struct starfive_pllx_clk starfive_jh7110_pll2;
+
+struct clk *starfive_jh7110_pll(const char *name, const char *parent_name,
+                               void __iomem *base, void __iomem *sysreg,
+                               const struct starfive_pllx_clk *pll_clk);
+#endif

diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c
index 91bcd1a..b9b0c28 100644 (file)
--- a/drivers/core/fdtaddr.c
+++ b/drivers/core/fdtaddr.c
@@ -12,6 +12,7 @@
 #include <dm.h>
 #include <fdt_support.h>
 #include <log.h>
+#include <mapmem.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <dm/device-internal.h>
@@ -97,7 +98,10 @@ void *devfdt_get_addr_index_ptr(const struct udevice *dev, int index)
 {
        fdt_addr_t addr = devfdt_get_addr_index(dev, index);
 
-       return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr;
+       if (addr == FDT_ADDR_T_NONE)
+               return NULL;
+
+       return map_sysmem(addr, 0);
 }
 
 fdt_addr_t devfdt_get_addr_size_index(const struct udevice *dev, int index,

diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c
index 85f7da5..81a3079 100644 (file)
--- a/drivers/core/of_access.c
+++ b/drivers/core/of_access.c
@@ -33,7 +33,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* list of struct alias_prop aliases */
-LIST_HEAD(aliases_lookup);
+static LIST_HEAD(aliases_lookup);
 
 /* "/aliaes" node */
 static struct device_node *of_aliases;

diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 1762a07..e46d571 100644 (file)
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -411,18 +411,14 @@ done:
 }
 
 #if CONFIG_IS_ENABLED(OF_REAL)
-int uclass_find_device_by_phandle(enum uclass_id id, struct udevice *parent,
-                                 const char *name, struct udevice **devp)
+static int uclass_find_device_by_phandle_id(enum uclass_id id,
+                                           uint find_phandle,
+                                           struct udevice **devp)
 {
        struct udevice *dev;
        struct uclass *uc;
-       int find_phandle;
        int ret;
 
-       *devp = NULL;
-       find_phandle = dev_read_u32_default(parent, name, -1);
-       if (find_phandle <= 0)
-               return -ENOENT;
        ret = uclass_get(id, &uc);
        if (ret)
                return ret;
@@ -440,6 +436,19 @@ int uclass_find_device_by_phandle(enum uclass_id id, struct udevice *parent,
 
        return -ENODEV;
 }
+
+int uclass_find_device_by_phandle(enum uclass_id id, struct udevice *parent,
+                                 const char *name, struct udevice **devp)
+{
+       int find_phandle;
+
+       *devp = NULL;
+       find_phandle = dev_read_u32_default(parent, name, -1);
+       if (find_phandle <= 0)
+               return -ENOENT;
+
+       return uclass_find_device_by_phandle_id(id, find_phandle, devp);
+}
 #endif
 
 int uclass_get_device_by_driver(enum uclass_id id,
@@ -535,31 +544,22 @@ int uclass_get_device_by_ofnode(enum uclass_id id, ofnode node,
        return uclass_get_device_tail(dev, ret, devp);
 }
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_REAL)
+int uclass_get_device_by_of_path(enum uclass_id id, const char *path,
+                                struct udevice **devp)
+{
+       return uclass_get_device_by_ofnode(id, ofnode_path(path), devp);
+}
+
 int uclass_get_device_by_phandle_id(enum uclass_id id, uint phandle_id,
                                    struct udevice **devp)
 {
        struct udevice *dev;
-       struct uclass *uc;
        int ret;
 
        *devp = NULL;
-       ret = uclass_get(id, &uc);
-       if (ret)
-               return ret;
-
-       uclass_foreach_dev(dev, uc) {
-               uint phandle;
-
-               phandle = dev_read_phandle(dev);
-
-               if (phandle == phandle_id) {
-                       *devp = dev;
-                       return uclass_get_device_tail(dev, ret, devp);
-               }
-       }
-
-       return -ENODEV;
+       ret = uclass_find_device_by_phandle_id(id, phandle_id, &dev);
+       return uclass_get_device_tail(dev, ret, devp);
 }
 
 int uclass_get_device_by_phandle(enum uclass_id id, struct udevice *parent,

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
index 6e7949a..8ec9fb0 100644 (file)
--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
@@ -1363,13 +1363,6 @@ int mv_ddr_pre_training_soc_config(const char *ddr_type)
                            DRAM_RESET_MASK_MASKED << DRAM_RESET_MASK_OFFS);
        }
 
-       /* Check if DRAM is already initialized  */
-       if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
-           (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
-               printf("%s Training Sequence - 2nd boot - Skip\n", ddr_type);
-               return MV_OK;
-       }
-
        /* Fix read ready phases for all SOC in reg 0x15c8 */
        reg_val = reg_read(TRAINING_DBG_3_REG);
 

diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c
index a06c590..9d25c40 100644 (file)
--- a/drivers/fastboot/fb_mmc.c
+++ b/drivers/fastboot/fb_mmc.c
@@ -287,7 +287,7 @@ static void fb_mmc_boot_ops(struct blk_desc *dev_desc, void *buffer,
  */
 static lbaint_t fb_mmc_get_boot_header(struct blk_desc *dev_desc,
                                       struct disk_partition *info,
-                                      struct andr_img_hdr *hdr,
+                                      struct andr_boot_img_hdr_v0 *hdr,
                                       char *response)
 {
        ulong sector_size;              /* boot partition sector size */
@@ -296,7 +296,7 @@ static lbaint_t fb_mmc_get_boot_header(struct blk_desc *dev_desc,
 
        /* Calculate boot image sectors count */
        sector_size = info->blksz;
-       hdr_sectors = DIV_ROUND_UP(sizeof(struct andr_img_hdr), sector_size);
+       hdr_sectors = DIV_ROUND_UP(sizeof(struct andr_boot_img_hdr_v0), sector_size);
        if (hdr_sectors == 0) {
                pr_err("invalid number of boot sectors: 0\n");
                fastboot_fail("invalid number of boot sectors: 0", response);
@@ -313,8 +313,7 @@ static lbaint_t fb_mmc_get_boot_header(struct blk_desc *dev_desc,
        }
 
        /* Check boot header magic string */
-       res = android_image_check_header(hdr);
-       if (res != 0) {
+       if (!is_android_boot_image_header(hdr)) {
                pr_err("bad boot image magic\n");
                fastboot_fail("boot partition not initialized", response);
                return 0;
@@ -338,7 +337,7 @@ static int fb_mmc_update_zimage(struct blk_desc *dev_desc,
                                char *response)
 {
        uintptr_t hdr_addr;                     /* boot image header address */
-       struct andr_img_hdr *hdr;               /* boot image header */
+       struct andr_boot_img_hdr_v0 *hdr;               /* boot image header */
        lbaint_t hdr_sectors;                   /* boot image header sectors */
        u8 *ramdisk_buffer;
        u32 ramdisk_sector_start;
@@ -361,7 +360,7 @@ static int fb_mmc_update_zimage(struct blk_desc *dev_desc,
 
        /* Put boot image header in fastboot buffer after downloaded zImage */
        hdr_addr = (uintptr_t)download_buffer + ALIGN(download_bytes, PAGE_SIZE);
-       hdr = (struct andr_img_hdr *)hdr_addr;
+       hdr = (struct andr_boot_img_hdr_v0 *)hdr_addr;
 
        /* Read boot image header */
        hdr_sectors = fb_mmc_get_boot_header(dev_desc, &info, hdr, response);
@@ -371,6 +370,14 @@ static int fb_mmc_update_zimage(struct blk_desc *dev_desc,
                return -1;
        }
 
+       /* Check if boot image header version is 2 or less */
+       if (hdr->header_version > 2) {
+               pr_err("zImage flashing supported only for boot images v2 and less\n");
+               fastboot_fail("zImage flashing supported only for boot images v2 and less",
+                             response);
+               return -EOPNOTSUPP;
+       }
+
        /* Check if boot image has second stage in it (we don't support it) */
        if (hdr->second_size > 0) {
                pr_err("moving second stage is not supported yet\n");

diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
index ef3e983..c6b9efa 100644 (file)
--- a/drivers/firmware/psci.c
+++ b/drivers/firmware/psci.c
@@ -319,4 +319,5 @@ U_BOOT_DRIVER(psci) = {
 #ifdef CONFIG_ARM_SMCCC_FEATURES
        .plat_auto = sizeof(struct psci_plat_data),
 #endif
+       .flags = DM_FLAG_PRE_RELOC,
 };

diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c
index 9a32678..54d563d 100644 (file)
--- a/drivers/firmware/scmi/scmi_agent-uclass.c
+++ b/drivers/firmware/scmi/scmi_agent-uclass.c
@@ -75,7 +75,7 @@ static int scmi_bind_protocols(struct udevice *dev)
                name = ofnode_get_name(node);
                switch (protocol_id) {
                case SCMI_PROTOCOL_ID_CLOCK:
-                       if (IS_ENABLED(CONFIG_CLK_SCMI))
+                       if (CONFIG_IS_ENABLED(CLK_SCMI))
                                drv = DM_DRIVER_GET(scmi_clock);
                        break;
                case SCMI_PROTOCOL_ID_RESET_DOMAIN:

diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 1388018..9ffb4a5 100644 (file)
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -195,6 +195,7 @@ static const struct udevice_id rcar_gpio_ids[] = {
        { .compatible = "renesas,gpio-r8a779a0", .data = RCAR_GPIO_HAS_INEN },
        { .compatible = "renesas,rcar-gen2-gpio" },
        { .compatible = "renesas,rcar-gen3-gpio" },
+       { .compatible = "renesas,rcar-gen4-gpio", .data = RCAR_GPIO_HAS_INEN },
        { /* sentinel */ }
 };
 

diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index c8be5a4..712119c 100644 (file)
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -1219,7 +1219,7 @@ int gpio_request_list_by_name_nodev(ofnode node, const char *list_name,
        return count;
 
 err:
-       gpio_free_list_nodev(desc, count - 1);
+       gpio_free_list_nodev(desc, count);
 
        return ret;
 }

diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index f7ad4d6..4a6ae55 100644 (file)
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -13,83 +13,118 @@
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/hardware.h>
 #include <asm/arch-rockchip/gpio.h>
 #include <dm/pinctrl.h>
-#include <dt-bindings/clock/rk3288-cru.h>
+#include <dm/read.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+#define SWPORT_DR              0x0000
+#define SWPORT_DDR             0x0004
+#define EXT_PORT               0x0050
+#define SWPORT_DR_L            0x0000
+#define SWPORT_DR_H            0x0004
+#define SWPORT_DDR_L           0x0008
+#define SWPORT_DDR_H           0x000C
+#define EXT_PORT_V2            0x0070
+#define VER_ID_V2              0x0078
 
 enum {
        ROCKCHIP_GPIOS_PER_BANK         = 32,
 };
 
-#define OFFSET_TO_BIT(bit)     (1UL << (bit))
-
 struct rockchip_gpio_priv {
-       struct rockchip_gpio_regs *regs;
+       void __iomem *regs;
        struct udevice *pinctrl;
        int bank;
        char name[2];
+       u32 version;
 };
 
-static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset)
+static int rockchip_gpio_get_value(struct udevice *dev, unsigned offset)
 {
        struct rockchip_gpio_priv *priv = dev_get_priv(dev);
-       struct rockchip_gpio_regs *regs = priv->regs;
+       u32 mask = BIT(offset), data;
 
-       clrbits_le32(&regs->swport_ddr, OFFSET_TO_BIT(offset));
+       if (priv->version)
+               data = readl(priv->regs + EXT_PORT_V2);
+       else
+               data = readl(priv->regs + EXT_PORT);
 
-       return 0;
+       return (data & mask) ? 1 : 0;
 }
 
-static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset,
-                                         int value)
+static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
+                                  int value)
 {
        struct rockchip_gpio_priv *priv = dev_get_priv(dev);
-       struct rockchip_gpio_regs *regs = priv->regs;
-       int mask = OFFSET_TO_BIT(offset);
+       u32 mask = BIT(offset), data = value ? mask : 0;
 
-       clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0);
-       setbits_le32(&regs->swport_ddr, mask);
+       if (priv->version && offset >= 16)
+               rk_clrsetreg(priv->regs + SWPORT_DR_H, mask >> 16, data >> 16);
+       else if (priv->version)
+               rk_clrsetreg(priv->regs + SWPORT_DR_L, mask, data);
+       else
+               clrsetbits_le32(priv->regs + SWPORT_DR, mask, data);
 
        return 0;
 }
 
-static int rockchip_gpio_get_value(struct udevice *dev, unsigned offset)
+static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset)
 {
        struct rockchip_gpio_priv *priv = dev_get_priv(dev);
-       struct rockchip_gpio_regs *regs = priv->regs;
+       u32 mask = BIT(offset);
+
+       if (priv->version && offset >= 16)
+               rk_clrreg(priv->regs + SWPORT_DDR_H, mask >> 16);
+       else if (priv->version)
+               rk_clrreg(priv->regs + SWPORT_DDR_L, mask);
+       else
+               clrbits_le32(priv->regs + SWPORT_DDR, mask);
 
-       return readl(&regs->ext_port) & OFFSET_TO_BIT(offset) ? 1 : 0;
+       return 0;
 }
 
-static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
-                                  int value)
+static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset,
+                                         int value)
 {
        struct rockchip_gpio_priv *priv = dev_get_priv(dev);
-       struct rockchip_gpio_regs *regs = priv->regs;
-       int mask = OFFSET_TO_BIT(offset);
+       u32 mask = BIT(offset);
+
+       rockchip_gpio_set_value(dev, offset, value);
 
-       clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0);
+       if (priv->version && offset >= 16)
+               rk_setreg(priv->regs + SWPORT_DDR_H, mask >> 16);
+       else if (priv->version)
+               rk_setreg(priv->regs + SWPORT_DDR_L, mask);
+       else
+               setbits_le32(priv->regs + SWPORT_DDR, mask);
 
        return 0;
 }
 
 static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
 {
-#ifdef CONFIG_SPL_BUILD
-       return -ENODATA;
-#else
        struct rockchip_gpio_priv *priv = dev_get_priv(dev);
-       struct rockchip_gpio_regs *regs = priv->regs;
-       bool is_output;
+       u32 mask = BIT(offset), data;
        int ret;
 
-       ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
-       if (ret)
-               return ret;
-       is_output = readl(&regs->swport_ddr) & OFFSET_TO_BIT(offset);
+       if (CONFIG_IS_ENABLED(PINCTRL)) {
+               ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
+               if (ret < 0)
+                       return ret;
+               else if (ret != RK_FUNC_GPIO)
+                       return GPIOF_FUNC;
+       }
+
+       if (priv->version && offset >= 16)
+               data = readl(priv->regs + SWPORT_DDR_H) << 16;
+       else if (priv->version)
+               data = readl(priv->regs + SWPORT_DDR_L);
+       else
+               data = readl(priv->regs + SWPORT_DDR);
 
-       return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
-#endif
+       return (data & mask) ? GPIOF_OUTPUT : GPIOF_INPUT;
 }
 
 /* Simple SPL interface to GPIOs */
@@ -147,9 +182,12 @@ static int rockchip_gpio_probe(struct udevice *dev)
        int ret;
 
        priv->regs = dev_read_addr_ptr(dev);
-       ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);
-       if (ret)
-               return ret;
+
+       if (CONFIG_IS_ENABLED(PINCTRL)) {
+               ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);
+               if (ret)
+                       return ret;
+       }
 
        /*
         * If "gpio-ranges" is present in the devicetree use it to parse
@@ -160,7 +198,7 @@ static int rockchip_gpio_probe(struct udevice *dev)
                                             0, &args);
        if (!ret || ret != -ENOENT) {
                uc_priv->gpio_count = args.args[2];
-               priv->bank = args.args[1] / args.args[2];
+               priv->bank = args.args[1] / ROCKCHIP_GPIOS_PER_BANK;
        } else {
                uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
                end = strrchr(dev->name, '@');
@@ -170,6 +208,8 @@ static int rockchip_gpio_probe(struct udevice *dev)
        priv->name[0] = 'A' + priv->bank;
        uc_priv->bank_name = priv->name;
 
+       priv->version = readl(priv->regs + VER_ID_V2);
+
        return 0;
 }
 

diff --git a/drivers/gpio/sh_pfc.c b/drivers/gpio/sh_pfc.c
index 92522b6..2495d6c 100644 (file)
--- a/drivers/gpio/sh_pfc.c
+++ b/drivers/gpio/sh_pfc.c
@@ -569,7 +569,7 @@ static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
        if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
                return -1;
 
-       if (IS_ENABLED(CONFIG_RCAR_GEN3) &&
+       if (IS_ENABLED(CONFIG_RCAR_64) &&
            ((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_INPUT))
                offset += 4;
 

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 2eae33c..05b14d2 100644 (file)
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -496,7 +496,7 @@ config SYS_I2C_OMAP24XX
 
 config SYS_I2C_RCAR_I2C
        bool "Renesas RCar I2C driver"
-       depends on (RCAR_GEN2 || RCAR_GEN3) && DM_I2C
+       depends on (RCAR_GEN2 || RCAR_64) && DM_I2C
        help
          Support for Renesas RCar I2C controller.
 

diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c
index 46c2545..28495a3 100644 (file)
--- a/drivers/i2c/designware_i2c_pci.c
+++ b/drivers/i2c/designware_i2c_pci.c
@@ -147,9 +147,7 @@ static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev,
 {
        struct dw_i2c_speed_config config;
        char path[ACPI_PATH_MAX];
-       u32 speeds[4];
        uint speed;
-       int size;
        int ret;
 
        /* If no device-tree node, ignore this since we assume it isn't used */
@@ -160,18 +158,6 @@ static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev,
        if (ret)
                return log_msg_ret("path", ret);
 
-       size = dev_read_size(dev, "i2c,speeds");
-       if (size < 0)
-               return log_msg_ret("i2c,speeds", -EINVAL);
-
-       size /= sizeof(u32);
-       if (size > ARRAY_SIZE(speeds))
-               return log_msg_ret("array", -E2BIG);
-
-       ret = dev_read_u32_array(dev, "i2c,speeds", speeds, size);
-       if (ret)
-               return log_msg_ret("read", -E2BIG);
-
        speed = dev_read_u32_default(dev, "clock-frequency", 100000);
        acpigen_write_scope(ctx, path);
        ret = dw_i2c_gen_speed_config(dev, speed, &config);

diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index d312f35..d9d8ee8 100644 (file)
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -278,7 +278,8 @@ static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
        set_i2c_bus_speed(base, i2c_clk, speed);
        writeb(slaveadd << 1, &base->adr);/* write slave address */
        writeb(0x0, &base->sr);         /* clear status register */
-       writeb(I2C_CR_MEN, &base->cr);  /* start I2C controller */
+       /* start I2C controller */
+       writeb(I2C_CR_MEN | I2C_CR_MIEN, &base->cr);
 
        timeval = get_ticks();
        while (readb(&base->sr) & I2C_SR_MBB) {
@@ -346,7 +347,7 @@ static int i2c_wait(const struct fsl_i2c_base *base, int write)
 static int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev,
                          u8 dir, int rsta)
 {
-       writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
+       writeb(I2C_CR_MEN | I2C_CR_MIEN | I2C_CR_MSTA | I2C_CR_MTX
               | (rsta ? I2C_CR_RSTA : 0),
               &base->cr);
 
@@ -378,7 +379,8 @@ static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data,
 {
        int i;
 
-       writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
+       writeb(I2C_CR_MEN | I2C_CR_MIEN |
+              I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
               &base->cr);
 
        /* dummy read */
@@ -390,13 +392,13 @@ static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data,
 
                /* Generate ack on last next to last byte */
                if (i == length - 2)
-                       writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
-                              &base->cr);
+                       writeb(I2C_CR_MEN | I2C_CR_MIEN | I2C_CR_MSTA |
+                              I2C_CR_TXAK, &base->cr);
 
                /* Do not generate stop on last byte */
                if (i == length - 1)
-                       writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
-                              &base->cr);
+                       writeb(I2C_CR_MEN | I2C_CR_MIEN | I2C_CR_MSTA |
+                              I2C_CR_MTX, &base->cr);
 
                data[i] = readb(&base->dr);
        }

diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index 8d9a89e..8867a56 100644 (file)
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
@@ -508,13 +508,13 @@ static void i2c_gpio_set_pin(struct gpio_desc *pin, int bit)
                dm_gpio_set_dir_flags(pin, GPIOD_IS_IN);
        else
                dm_gpio_set_dir_flags(pin, GPIOD_IS_OUT |
-                                          GPIOD_ACTIVE_LOW |
                                           GPIOD_IS_OUT_ACTIVE);
 }
 
 static int i2c_gpio_get_pin(struct gpio_desc *pin)
 {
-       return dm_gpio_get_value(pin);
+       /* DTS need config GPIO_ACTIVE_LOW */
+       return !dm_gpio_get_value(pin);
 }
 
 int i2c_deblock_gpio_loop(struct gpio_desc *sda_pin,

diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c
index 92c5003..ad9293c 100644 (file)
--- a/drivers/i2c/imx_lpi2c.c
+++ b/drivers/i2c/imx_lpi2c.c
@@ -282,7 +282,7 @@ static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
        bool mode;
        int i;
 
-       if (IS_ENABLED(CONFIG_CLK)) {
+       if (CONFIG_IS_ENABLED(CLK)) {
                clock_rate = clk_get_rate(&i2c_bus->per_clk);
                if (clock_rate <= 0) {
                        dev_err(bus, "Failed to get i2c clk: %d\n", clock_rate);
@@ -462,7 +462,7 @@ static int imx_lpi2c_probe(struct udevice *bus)
                return ret;
        }
 
-       if (IS_ENABLED(CONFIG_CLK)) {
+       if (CONFIG_IS_ENABLED(CLK)) {
                ret = clk_get_by_name(bus, "per", &i2c_bus->per_clk);
                if (ret) {
                        dev_err(bus, "Failed to get per clk\n");

diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c
index d9ece5e..ff9a2d8 100644 (file)
--- a/drivers/i2c/rcar_i2c.c
+++ b/drivers/i2c/rcar_i2c.c
@@ -369,6 +369,7 @@ static const struct dm_i2c_ops rcar_i2c_ops = {
 static const struct udevice_id rcar_i2c_ids[] = {
        { .compatible = "renesas,rcar-gen2-i2c", .data = RCAR_I2C_TYPE_GEN2 },
        { .compatible = "renesas,rcar-gen3-i2c", .data = RCAR_I2C_TYPE_GEN3 },
+       { .compatible = "renesas,rcar-gen4-i2c", .data = RCAR_I2C_TYPE_GEN3 },
        { }
 };
 

diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c
index 60931a5..2f96b79 100644 (file)
--- a/drivers/misc/rockchip-efuse.c
+++ b/drivers/misc/rockchip-efuse.c
@@ -73,7 +73,7 @@ static int dump_efuse(struct cmd_tbl *cmdtp, int flag,
 
        for (i = 0; true; i += sizeof(data)) {
                ret = misc_read(dev, i, &data, sizeof(data));
-               if (ret < 0)
+               if (ret <= 0)
                        return 0;
 
                print_buffer(i, data, 1, sizeof(data), sizeof(data));
@@ -238,8 +238,10 @@ static int rockchip_efuse_read(struct udevice *dev, int offset,
 
        offset += data->offset;
 
-       if (data->block_size <= 1)
-               return data->read(dev, offset, buf, size);
+       if (data->block_size <= 1) {
+               ret = data->read(dev, offset, buf, size);
+               goto done;
+       }
 
        block_start = offset / data->block_size;
        block_offset = offset % data->block_size;
@@ -255,7 +257,9 @@ static int rockchip_efuse_read(struct udevice *dev, int offset,
                memcpy(buf, buffer + block_offset, size);
 
        free(buffer);
-       return ret;
+
+done:
+       return ret < 0 ? ret : size;
 }
 
 static const struct misc_ops rockchip_efuse_ops = {

diff --git a/drivers/misc/rockchip-otp.c b/drivers/misc/rockchip-otp.c
index c19cd5c..4814e0e 100644 (file)
--- a/drivers/misc/rockchip-otp.c
+++ b/drivers/misc/rockchip-otp.c
@@ -89,7 +89,7 @@ static int dump_otp(struct cmd_tbl *cmdtp, int flag,
 
        for (i = 0; true; i += sizeof(data)) {
                ret = misc_read(dev, i, &data, sizeof(data));
-               if (ret < 0)
+               if (ret <= 0)
                        return 0;
 
                print_buffer(i, data, 1, sizeof(data), sizeof(data));
@@ -249,8 +249,10 @@ static int rockchip_otp_read(struct udevice *dev, int offset,
 
        offset += data->offset;
 
-       if (data->block_size <= 1)
-               return data->read(dev, offset, buf, size);
+       if (data->block_size <= 1) {
+               ret = data->read(dev, offset, buf, size);
+               goto done;
+       }
 
        block_start = offset / data->block_size;
        block_offset = offset % data->block_size;
@@ -266,7 +268,9 @@ static int rockchip_otp_read(struct udevice *dev, int offset,
                memcpy(buf, buffer + block_offset, size);
 
        free(buffer);
-       return ret;
+
+done:
+       return ret < 0 ? ret : size;
 }
 
 static const struct misc_ops rockchip_otp_ops = {

diff --git a/drivers/misc/usb251xb.c b/drivers/misc/usb251xb.c
index a78ad18..92e92ba 100644 (file)
--- a/drivers/misc/usb251xb.c
+++ b/drivers/misc/usb251xb.c
@@ -334,7 +334,7 @@ static int usb251xb_probe(struct udevice *dev)
        struct usb251xb *hub = dev_get_priv(dev);
        int err;
 
-       if (IS_ENABLED(CONFIG_DM_REGULATOR) && hub->vdd) {
+       if (CONFIG_IS_ENABLED(DM_REGULATOR) && hub->vdd) {
                err = regulator_set_enable(hub->vdd, true);
                if (err)
                        return err;
@@ -391,7 +391,7 @@ static int usb251xb_of_to_plat(struct udevice *dev)
                return err;
        }
 
-       if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
+       if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
                err = device_get_supply_regulator(dev, "vdd-supply",
                                                  &hub->vdd);
                if (err && err != -ENOENT) {

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 80641e1..de01b96 100644 (file)
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -476,6 +476,14 @@ config MMC_SDHCI_SDMA
          This enables support for the SDMA (Single Operation DMA) defined
          in the SD Host Controller Standard Specification Version 1.00 .
 
+config SPL_MMC_SDHCI_SDMA
+       bool "Support SDHCI SDMA in SPL"
+       depends on SPL_MMC && MMC_SDHCI
+       default y if MMC_SDHCI_SDMA
+       help
+         This enables support for the SDMA (Single Operation DMA) defined
+         in the SD Host Controller Standard Specification Version 1.00 in SPL.
+
 config MMC_SDHCI_ADMA
        bool "Support SDHCI ADMA2"
        depends on MMC_SDHCI
@@ -621,6 +629,7 @@ config MMC_SDHCI_MV
        bool "SDHCI support on Marvell platform"
        depends on ARCH_MVEBU
        depends on MMC_SDHCI
+       depends on DM_MMC
        help
          This selects the Secure Digital Host Controller Interface on
          Marvell platform.

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index dde251c..1af6af8 100644 (file)
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -2432,6 +2432,9 @@ static int mmc_startup_v4(struct mmc *mmc)
 
        mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
 
+       mmc->can_trim =
+               !!(ext_csd[EXT_CSD_SEC_FEATURE] & EXT_CSD_SEC_FEATURE_TRIM_EN);
+
        return 0;
 error:
        if (mmc->ext_csd) {

diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index 5b7aeeb..a6f9338 100644 (file)
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -15,7 +15,7 @@
 #include <linux/math64.h>
 #include "mmc_private.h"
 
-static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt)
+static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt, u32 args)
 {
        struct mmc_cmd cmd;
        ulong end;
@@ -52,7 +52,7 @@ static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt)
                goto err_out;
 
        cmd.cmdidx = MMC_CMD_ERASE;
-       cmd.cmdarg = MMC_ERASE_ARG;
+       cmd.cmdarg = args ? args : MMC_ERASE_ARG;
        cmd.resp_type = MMC_RSP_R1b;
 
        err = mmc_send_cmd(mmc, &cmd, NULL);
@@ -77,7 +77,7 @@ ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt)
 #endif
        int dev_num = block_dev->devnum;
        int err = 0;
-       u32 start_rem, blkcnt_rem;
+       u32 start_rem, blkcnt_rem, erase_args = 0;
        struct mmc *mmc = find_mmc_device(dev_num);
        lbaint_t blk = 0, blk_r = 0;
        int timeout_ms = 1000;
@@ -97,13 +97,25 @@ ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt)
         */
        err = div_u64_rem(start, mmc->erase_grp_size, &start_rem);
        err = div_u64_rem(blkcnt, mmc->erase_grp_size, &blkcnt_rem);
-       if (start_rem || blkcnt_rem)
-               printf("\n\nCaution! Your devices Erase group is 0x%x\n"
-                      "The erase range would be change to "
-                      "0x" LBAF "~0x" LBAF "\n\n",
-                      mmc->erase_grp_size, start & ~(mmc->erase_grp_size - 1),
-                      ((start + blkcnt + mmc->erase_grp_size - 1)
-                      & ~(mmc->erase_grp_size - 1)) - 1);
+       if (start_rem || blkcnt_rem) {
+               if (mmc->can_trim) {
+                       /* Trim function applies the erase operation to write
+                        * blocks instead of erase groups.
+                        */
+                       erase_args = MMC_TRIM_ARG;
+               } else {
+                       /* The card ignores all LSB's below the erase group
+                        * size, rounding down the addess to a erase group
+                        * boundary.
+                        */
+                       printf("\n\nCaution! Your devices Erase group is 0x%x\n"
+                              "The erase range would be change to "
+                              "0x" LBAF "~0x" LBAF "\n\n",
+                              mmc->erase_grp_size, start & ~(mmc->erase_grp_size - 1),
+                              ((start + blkcnt + mmc->erase_grp_size - 1)
+                              & ~(mmc->erase_grp_size - 1)) - 1);
+               }
+       }
 
        while (blk < blkcnt) {
                if (IS_SD(mmc) && mmc->ssr.au) {
@@ -113,7 +125,7 @@ ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt)
                        blk_r = ((blkcnt - blk) > mmc->erase_grp_size) ?
                                mmc->erase_grp_size : (blkcnt - blk);
                }
-               err = mmc_erase_t(mmc, start + blk, blk_r);
+               err = mmc_erase_t(mmc, start + blk, blk_r, erase_args);
                if (err)
                        break;
 

diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c
index 336ebf1..dbdd671 100644 (file)
--- a/drivers/mmc/mv_sdhci.c
+++ b/drivers/mmc/mv_sdhci.c
@@ -15,6 +15,13 @@
 #define SDHCI_WINDOW_CTRL(win)         (0x4080 + ((win) << 4))
 #define SDHCI_WINDOW_BASE(win)         (0x4084 + ((win) << 4))
 
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mv_sdhci_plat {
+       struct mmc_config cfg;
+       struct mmc mmc;
+};
+
 static void sdhci_mvebu_mbus_config(void __iomem *base)
 {
        const struct mbus_dram_target_info *dram;
@@ -40,47 +47,6 @@ static void sdhci_mvebu_mbus_config(void __iomem *base)
        }
 }
 
-#ifndef CONFIG_DM_MMC
-
-#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
-static struct sdhci_ops mv_ops;
-#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
-
-int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
-{
-       struct sdhci_host *host = NULL;
-       host = calloc(1, sizeof(*host));
-       if (!host) {
-               printf("sdh_host malloc fail!\n");
-               return -ENOMEM;
-       }
-
-       host->name = MVSDH_NAME;
-       host->ioaddr = (void *)regbase;
-       host->quirks = quirks;
-       host->max_clk = max_clk;
-#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
-       memset(&mv_ops, 0, sizeof(struct sdhci_ops));
-       host->ops = &mv_ops;
-#endif
-
-       if (CONFIG_IS_ENABLED(ARCH_MVEBU)) {
-               /* Configure SDHCI MBUS mbus bridge windows */
-               sdhci_mvebu_mbus_config((void __iomem *)regbase);
-       }
-
-       return add_sdhci(host, 0, min_clk);
-}
-
-#else
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct mv_sdhci_plat {
-       struct mmc_config cfg;
-       struct mmc mmc;
-};
-
 static int mv_sdhci_probe(struct udevice *dev)
 {
        struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
@@ -103,10 +69,8 @@ static int mv_sdhci_probe(struct udevice *dev)
        if (ret)
                return ret;
 
-       if (CONFIG_IS_ENABLED(ARCH_MVEBU)) {
-               /* Configure SDHCI MBUS mbus bridge windows */
-               sdhci_mvebu_mbus_config(host->ioaddr);
-       }
+       /* Configure SDHCI MBUS mbus bridge windows */
+       sdhci_mvebu_mbus_config(host->ioaddr);
 
        upriv->mmc = host->mmc;
 
@@ -135,4 +99,3 @@ U_BOOT_DRIVER(mv_sdhci_drv) = {
        .priv_auto      = sizeof(struct sdhci_host),
        .plat_auto      = sizeof(struct mv_sdhci_plat),
 };
-#endif /* CONFIG_DM_MMC */

diff --git a/drivers/mmc/npcm_sdhci.c b/drivers/mmc/npcm_sdhci.c
index 7eb17cc..d63521d 100644 (file)
--- a/drivers/mmc/npcm_sdhci.c
+++ b/drivers/mmc/npcm_sdhci.c
@@ -36,7 +36,7 @@ static int npcm_sdhci_probe(struct udevice *dev)
                        return ret;
        }
 
-       if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
+       if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
                device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_supply);
                vqmmc_uv = dev_read_u32_default(dev, "vqmmc-microvolt", 0);
                /* Set IO voltage */

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 34119f9..280d96d 100644 (file)
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -843,6 +843,7 @@ static const struct udevice_id renesas_sdhi_match[] = {
        { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
        { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
        { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
+       { .compatible = "renesas,rcar-gen4-sdhi", .data = RENESAS_GEN3_QUIRKS },
        { /* sentinel */ }
 };
 

diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index e1409dd..4f11097 100644 (file)
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -47,51 +47,51 @@
 #define ARASAN_VENDOR_REGISTER         0x78
 #define ARASAN_VENDOR_ENHANCED_STROBE  BIT(0)
 
-/* DWC IP vendor area 1 pointer */
-#define DWCMSHC_P_VENDOR_AREA1         0xe8
-#define DWCMSHC_AREA1_MASK             GENMASK(11, 0)
-/* Offset inside the vendor area 1 */
-#define DWCMSHC_EMMC_CONTROL           0x2c
+/* Rockchip specific Registers */
+#define DWCMSHC_EMMC_EMMC_CTRL         0x52c
 #define DWCMSHC_CARD_IS_EMMC           BIT(0)
 #define DWCMSHC_ENHANCED_STROBE                BIT(8)
-
-/* Rockchip specific Registers */
 #define DWCMSHC_EMMC_DLL_CTRL          0x800
 #define DWCMSHC_EMMC_DLL_CTRL_RESET    BIT(1)
 #define DWCMSHC_EMMC_DLL_RXCLK         0x804
 #define DWCMSHC_EMMC_DLL_TXCLK         0x808
 #define DWCMSHC_EMMC_DLL_STRBIN                0x80c
-#define DECMSHC_EMMC_DLL_CMDOUT                0x810
+#define DWCMSHC_EMMC_DLL_CMDOUT                0x810
 #define DWCMSHC_EMMC_DLL_STATUS0       0x840
 #define DWCMSHC_EMMC_DLL_STATUS1       0x844
 #define DWCMSHC_EMMC_DLL_START         BIT(0)
-#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL  29
+#define DWCMSHC_EMMC_DLL_LOCKED                BIT(8)
+#define DWCMSHC_EMMC_DLL_TIMEOUT       BIT(9)
 #define DWCMSHC_EMMC_DLL_START_POINT   16
 #define DWCMSHC_EMMC_DLL_START_DEFAULT 5
 #define DWCMSHC_EMMC_DLL_INC_VALUE     2
 #define DWCMSHC_EMMC_DLL_INC           8
 #define DWCMSHC_EMMC_DLL_BYPASS                BIT(24)
 #define DWCMSHC_EMMC_DLL_DLYENA                BIT(27)
-#define DLL_TXCLK_TAPNUM_DEFAULT       0xA
-
-#define DLL_STRBIN_TAPNUM_DEFAULT      0x8
+#define DLL_RXCLK_NO_INVERTER          BIT(29)
+#define DLL_RXCLK_ORI_GATE             BIT(31)
+#define DLL_TXCLK_TAPNUM_DEFAULT       0x10
+#define DLL_TXCLK_TAPNUM_90_DEGREES    0x9
+#define DLL_TXCLK_TAPNUM_FROM_SW       BIT(24)
+#define DLL_TXCLK_NO_INVERTER          BIT(29)
+#define DLL_STRBIN_TAPNUM_DEFAULT      0x4
 #define DLL_STRBIN_TAPNUM_FROM_SW      BIT(24)
 #define DLL_STRBIN_DELAY_NUM_SEL       BIT(26)
 #define DLL_STRBIN_DELAY_NUM_OFFSET    16
-#define DLL_STRBIN_DELAY_NUM_DEFAULT   0x16
+#define DLL_STRBIN_DELAY_NUM_DEFAULT   0x10
+#define DLL_CMDOUT_TAPNUM_90_DEGREES   0x8
+#define DLL_CMDOUT_TAPNUM_FROM_SW      BIT(24)
+#define DLL_CMDOUT_SRC_CLK_NEG         BIT(28)
+#define DLL_CMDOUT_EN_SRC_CLK_NEG      BIT(29)
+#define DLL_CMDOUT_BOTH_CLK_EDGE       BIT(30)
 
-#define DLL_TXCLK_TAPNUM_FROM_SW       BIT(24)
-#define DWCMSHC_EMMC_DLL_LOCKED                BIT(8)
-#define DWCMSHC_EMMC_DLL_TIMEOUT       BIT(9)
-#define DLL_RXCLK_NO_INVERTER          1
-#define DLL_RXCLK_INVERTER             0
-#define DLL_RXCLK_ORI_GATE             BIT(31)
-#define DWCMSHC_ENHANCED_STROBE                BIT(8)
 #define DLL_LOCK_WO_TMOUT(x) \
        ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
        (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
 #define ROCKCHIP_MAX_CLKS              3
 
+#define FLAG_INVERTER_FLAG_IN_RXCLK    BIT(0)
+
 struct rockchip_sdhc_plat {
        struct mmc_config cfg;
        struct mmc mmc;
@@ -112,7 +112,6 @@ struct rockchip_sdhc {
 };
 
 struct sdhci_data {
-       int (*emmc_phy_init)(struct udevice *dev);
        int (*get_phy)(struct udevice *dev);
 
        /**
@@ -140,6 +139,9 @@ struct sdhci_data {
         */
        int (*set_ios_post)(struct sdhci_host *host);
 
+       void (*set_clock)(struct sdhci_host *host, u32 div);
+       int (*config_dll)(struct sdhci_host *host, u32 clock, bool enable);
+
        /**
         * set_enhanced_strobe() - Set HS400 Enhanced Strobe config
         *
@@ -152,12 +154,11 @@ struct sdhci_data {
         * Return: 0 if successful, -ve on error
         */
        int (*set_enhanced_strobe)(struct sdhci_host *host);
-};
 
-static int rk3399_emmc_phy_init(struct udevice *dev)
-{
-       return 0;
-}
+       u32 flags;
+       u8 hs200_txclk_tapnum;
+       u8 hs400_txclk_tapnum;
+};
 
 static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock)
 {
@@ -294,30 +295,27 @@ static int rk3399_sdhci_set_ios_post(struct sdhci_host *host)
        return 0;
 }
 
-static int rk3568_emmc_phy_init(struct udevice *dev)
+static void rk3568_sdhci_set_clock(struct sdhci_host *host, u32 div)
 {
-       struct rockchip_sdhc *prv = dev_get_priv(dev);
-       struct sdhci_host *host = &prv->host;
-       u32 extra;
-
-       extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
-       sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
+       struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
+       struct mmc *mmc = host->mmc;
+       ulong rate;
 
-       return 0;
+       rate = clk_set_rate(&priv->emmc_clk, mmc->clock);
+       if (IS_ERR_VALUE(rate))
+               printf("%s: Set clock rate failed: %ld\n", __func__, (long)rate);
 }
 
-static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock)
+static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enable)
 {
        struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
+       struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
+       struct mmc *mmc = host->mmc;
        int val, ret;
-       u32 extra;
-
-       if (clock > host->max_clk)
-               clock = host->max_clk;
-       if (clock)
-               clk_set_rate(&priv->emmc_clk, clock);
+       u32 extra, txclk_tapnum;
 
-       sdhci_set_clock(host->mmc, clock);
+       if (!enable)
+               return 0;
 
        if (clock >= 100 * MHz) {
                /* reset DLL */
@@ -337,13 +335,28 @@ static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo
                if (ret)
                        return ret;
 
-               extra = DWCMSHC_EMMC_DLL_DLYENA |
-                       DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
+               extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_ORI_GATE;
+               if (data->flags & FLAG_INVERTER_FLAG_IN_RXCLK)
+                       extra |= DLL_RXCLK_NO_INVERTER;
                sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
 
+               txclk_tapnum = data->hs200_txclk_tapnum;
+               if (mmc->selected_mode == MMC_HS_400 ||
+                   mmc->selected_mode == MMC_HS_400_ES) {
+                       txclk_tapnum = data->hs400_txclk_tapnum;
+
+                       extra = DLL_CMDOUT_SRC_CLK_NEG |
+                               DLL_CMDOUT_BOTH_CLK_EDGE |
+                               DWCMSHC_EMMC_DLL_DLYENA |
+                               DLL_CMDOUT_TAPNUM_90_DEGREES |
+                               DLL_CMDOUT_TAPNUM_FROM_SW;
+                       sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CMDOUT);
+               }
+
                extra = DWCMSHC_EMMC_DLL_DLYENA |
-                       DLL_TXCLK_TAPNUM_DEFAULT |
-                       DLL_TXCLK_TAPNUM_FROM_SW;
+                       DLL_TXCLK_TAPNUM_FROM_SW |
+                       DLL_TXCLK_NO_INVERTER |
+                       txclk_tapnum;
                sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
 
                extra = DWCMSHC_EMMC_DLL_DLYENA |
@@ -355,11 +368,11 @@ static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo
                 * Disable DLL and reset both of sample and drive clock.
                 * The bypass bit and start bit need to be set if DLL is not locked.
                 */
-               sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START,
-                            DWCMSHC_EMMC_DLL_CTRL);
+               extra = DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START;
+               sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
                sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
-               sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
                sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
+               sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CMDOUT);
                /*
                 * Before switching to hs400es mode, the driver will enable
                 * enhanced strobe first. PHY needs to configure the parameters
@@ -374,56 +387,54 @@ static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo
        return 0;
 }
 
-static int rk3568_emmc_get_phy(struct udevice *dev)
-{
-       return 0;
-}
-
-static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host)
-{
-       struct mmc *mmc = host->mmc;
-       u32 vendor;
-       int reg;
-
-       reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK)
-             + DWCMSHC_EMMC_CONTROL;
-
-       vendor = sdhci_readl(host, reg);
-       if (mmc->selected_mode == MMC_HS_400_ES)
-               vendor |= DWCMSHC_ENHANCED_STROBE;
-       else
-               vendor &= ~DWCMSHC_ENHANCED_STROBE;
-       sdhci_writel(host, vendor, reg);
-
-       return 0;
-}
-
 static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
 {
        struct mmc *mmc = host->mmc;
-       uint clock = mmc->tran_speed;
-       u32 reg, vendor_reg;
-
-       if (!clock)
-               clock = mmc->clock;
+       u32 reg;
+
+       reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+       reg &= ~SDHCI_CTRL_UHS_MASK;
+
+       switch (mmc->selected_mode) {
+       case UHS_SDR25:
+       case MMC_HS:
+       case MMC_HS_52:
+               reg |= SDHCI_CTRL_UHS_SDR25;
+               break;
+       case UHS_SDR50:
+               reg |= SDHCI_CTRL_UHS_SDR50;
+               break;
+       case UHS_DDR50:
+       case MMC_DDR_52:
+               reg |= SDHCI_CTRL_UHS_DDR50;
+               break;
+       case UHS_SDR104:
+       case MMC_HS_200:
+               reg |= SDHCI_CTRL_UHS_SDR104;
+               break;
+       case MMC_HS_400:
+       case MMC_HS_400_ES:
+               reg |= DWCMSHC_CTRL_HS400;
+               break;
+       default:
+               reg |= SDHCI_CTRL_UHS_SDR12;
+       }
 
-       rk3568_sdhci_emmc_set_clock(host, clock);
+       sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 
-       if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) {
-               reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
-               reg &= ~SDHCI_CTRL_UHS_MASK;
-               reg |= DWCMSHC_CTRL_HS400;
-               sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
+       reg = sdhci_readw(host, DWCMSHC_EMMC_EMMC_CTRL);
 
-               vendor_reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK)
-                            + DWCMSHC_EMMC_CONTROL;
-               /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
-               reg = sdhci_readw(host, vendor_reg);
+       if (IS_MMC(mmc))
                reg |= DWCMSHC_CARD_IS_EMMC;
-               sdhci_writew(host, reg, vendor_reg);
-       } else {
-               sdhci_set_uhs_timing(host);
-       }
+       else
+               reg &= ~DWCMSHC_CARD_IS_EMMC;
+
+       if (mmc->selected_mode == MMC_HS_400_ES)
+               reg |= DWCMSHC_ENHANCED_STROBE;
+       else
+               reg &= ~DWCMSHC_ENHANCED_STROBE;
+
+       sdhci_writew(host, reg, DWCMSHC_EMMC_EMMC_CTRL);
 
        return 0;
 }
@@ -448,23 +459,32 @@ static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
        return 0;
 }
 
+static void rockchip_sdhci_set_clock(struct sdhci_host *host, u32 div)
+{
+       struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
+       struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
+
+       if (data->set_clock)
+               data->set_clock(host, div);
+}
+
 static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
 {
-       struct sdhci_host *host = dev_get_priv(mmc->dev);
+       struct rockchip_sdhc *priv = dev_get_priv(mmc->dev);
+       struct sdhci_host *host = &priv->host;
        char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
        struct mmc_cmd cmd;
        u32 ctrl, blk_size;
-       int ret = 0;
+       int ret;
 
        ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
        ctrl |= SDHCI_CTRL_EXEC_TUNING;
        sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 
        sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
-       sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
 
        blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64);
-       if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && host->mmc->bus_width == 8)
+       if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && mmc->bus_width == 8)
                blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128);
        sdhci_writew(host, blk_size, SDHCI_BLOCK_SIZE);
        sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
@@ -474,40 +494,39 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
        cmd.cmdarg = 0;
 
        do {
-               if (tuning_loop_counter-- == 0)
-                       break;
-
-               mmc_send_cmd(mmc, &cmd, NULL);
-
-               if (opcode == MMC_CMD_SEND_TUNING_BLOCK)
-                       /*
-                        * For tuning command, do not do busy loop. As tuning
-                        * is happening (CLK-DATA latching for setup/hold time
-                        * requirements), give time to complete
-                        */
-                       udelay(1);
-
+               ret = mmc_send_cmd(mmc, &cmd, NULL);
                ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+               if (ret || tuning_loop_counter-- == 0)
+                       break;
        } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
 
-       if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
-               printf("%s:Tuning failed\n", __func__);
-               ret = -EIO;
-       }
+       if (ret || tuning_loop_counter < 0 || !(ctrl & SDHCI_CTRL_TUNED_CLK)) {
+               if (!ret)
+                       ret = -EIO;
+               printf("%s: Tuning failed: %d\n", __func__, ret);
 
-       if (tuning_loop_counter < 0) {
                ctrl &= ~SDHCI_CTRL_TUNED_CLK;
-               sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
+               ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
+               sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
        }
 
        /* Enable only interrupts served by the SD controller */
        sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, SDHCI_INT_ENABLE);
-       /* Mask all sdhci interrupt sources */
-       sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 
        return ret;
 }
 
+static int rockchip_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enable)
+{
+       struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
+       struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
+
+       if (data->config_dll)
+               return data->config_dll(host, clock, enable);
+
+       return 0;
+}
+
 static int rockchip_sdhci_set_enhanced_strobe(struct sdhci_host *host)
 {
        struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
@@ -516,13 +535,15 @@ static int rockchip_sdhci_set_enhanced_strobe(struct sdhci_host *host)
        if (data->set_enhanced_strobe)
                return data->set_enhanced_strobe(host);
 
-       return -ENOTSUPP;
+       return 0;
 }
 
 static struct sdhci_ops rockchip_sdhci_ops = {
-       .set_ios_post   = rockchip_sdhci_set_ios_post,
-       .platform_execute_tuning = &rockchip_sdhci_execute_tuning,
        .set_control_reg = rockchip_sdhci_set_control_reg,
+       .set_ios_post = rockchip_sdhci_set_ios_post,
+       .set_clock = rockchip_sdhci_set_clock,
+       .platform_execute_tuning = rockchip_sdhci_execute_tuning,
+       .config_dll = rockchip_sdhci_config_dll,
        .set_enhanced_strobe = rockchip_sdhci_set_enhanced_strobe,
 };
 
@@ -531,9 +552,9 @@ static int rockchip_sdhci_probe(struct udevice *dev)
        struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(dev);
        struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
        struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
-       struct rockchip_sdhc *prv = dev_get_priv(dev);
+       struct rockchip_sdhc *priv = dev_get_priv(dev);
        struct mmc_config *cfg = &plat->cfg;
-       struct sdhci_host *host = &prv->host;
+       struct sdhci_host *host = &priv->host;
        struct clk clk;
        int ret;
 
@@ -547,8 +568,8 @@ static int rockchip_sdhci_probe(struct udevice *dev)
                printf("%s fail to get clk\n", __func__);
        }
 
-       prv->emmc_clk = clk;
-       prv->dev = dev;
+       priv->emmc_clk = clk;
+       priv->dev = dev;
 
        if (data->get_phy) {
                ret = data->get_phy(dev);
@@ -556,17 +577,11 @@ static int rockchip_sdhci_probe(struct udevice *dev)
                        return ret;
        }
 
-       if (data->emmc_phy_init) {
-               ret = data->emmc_phy_init(dev);
-               if (ret)
-                       return ret;
-       }
-
        host->ops = &rockchip_sdhci_ops;
        host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
 
        host->mmc = &plat->mmc;
-       host->mmc->priv = &prv->host;
+       host->mmc->priv = &priv->host;
        host->mmc->dev = dev;
        upriv->mmc = host->mmc;
 
@@ -574,14 +589,23 @@ static int rockchip_sdhci_probe(struct udevice *dev)
        if (ret)
                return ret;
 
+       /*
+        * Reading more than 4 blocks with a single CMD18 command in PIO mode
+        * triggers Data End Bit Error on RK3568 and RK3588. Limit to reading
+        * max 4 blocks in one command when using PIO mode.
+        */
+       if (!(host->flags & USE_DMA))
+               cfg->b_max = 4;
+
        return sdhci_probe(dev);
 }
 
 static int rockchip_sdhci_of_to_plat(struct udevice *dev)
 {
        struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
-       struct sdhci_host *host = dev_get_priv(dev);
+       struct rockchip_sdhc *priv = dev_get_priv(dev);
        struct mmc_config *cfg = &plat->cfg;
+       struct sdhci_host *host = &priv->host;
        int ret;
 
        host->name = dev->name;
@@ -603,17 +627,26 @@ static int rockchip_sdhci_bind(struct udevice *dev)
 
 static const struct sdhci_data rk3399_data = {
        .get_phy = rk3399_emmc_get_phy,
-       .emmc_phy_init = rk3399_emmc_phy_init,
        .set_control_reg = rk3399_sdhci_set_control_reg,
        .set_ios_post = rk3399_sdhci_set_ios_post,
        .set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe,
 };
 
 static const struct sdhci_data rk3568_data = {
-       .get_phy = rk3568_emmc_get_phy,
-       .emmc_phy_init = rk3568_emmc_phy_init,
        .set_ios_post = rk3568_sdhci_set_ios_post,
-       .set_enhanced_strobe = rk3568_sdhci_set_enhanced_strobe,
+       .set_clock = rk3568_sdhci_set_clock,
+       .config_dll = rk3568_sdhci_config_dll,
+       .flags = FLAG_INVERTER_FLAG_IN_RXCLK,
+       .hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
+       .hs400_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
+};
+
+static const struct sdhci_data rk3588_data = {
+       .set_ios_post = rk3568_sdhci_set_ios_post,
+       .set_clock = rk3568_sdhci_set_clock,
+       .config_dll = rk3568_sdhci_config_dll,
+       .hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
+       .hs400_txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES,
 };
 
 static const struct udevice_id sdhci_ids[] = {
@@ -625,6 +658,10 @@ static const struct udevice_id sdhci_ids[] = {
                .compatible = "rockchip,rk3568-dwcmshc",
                .data = (ulong)&rk3568_data,
        },
+       {
+               .compatible = "rockchip,rk3588-dwcmshc",
+               .data = (ulong)&rk3588_data,
+       },
        { }
 };
 

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index c6b250b..9cbe126 100644 (file)
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -70,7 +70,7 @@ static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
        }
 }
 
-#if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
+#if (CONFIG_IS_ENABLED(MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
                              int *is_aligned, int trans_bytes)
 {
@@ -177,7 +177,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
                }
        } while (!(stat & SDHCI_INT_DATA_END));
 
-#if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
+#if (CONFIG_IS_ENABLED(MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
        dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
                         mmc_get_dma_dir(data));
 #endif
@@ -518,6 +518,10 @@ void sdhci_set_uhs_timing(struct sdhci_host *host)
        reg &= ~SDHCI_CTRL_UHS_MASK;
 
        switch (mmc->selected_mode) {
+       case UHS_SDR25:
+       case MMC_HS:
+               reg |= SDHCI_CTRL_UHS_SDR25;
+               break;
        case UHS_SDR50:
        case MMC_HS_52:
                reg |= SDHCI_CTRL_UHS_SDR50;
@@ -682,6 +686,7 @@ static int sdhci_set_ios(struct mmc *mmc)
        if (!no_hispd_bit) {
                if (mmc->selected_mode == MMC_HS ||
                    mmc->selected_mode == SD_HS ||
+                   mmc->selected_mode == MMC_HS_52 ||
                    mmc->selected_mode == MMC_DDR_52 ||
                    mmc->selected_mode == MMC_HS_200 ||
                    mmc->selected_mode == MMC_HS_400 ||
@@ -872,7 +877,7 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 #endif
        debug("%s, caps: 0x%x\n", __func__, caps);
 
-#ifdef CONFIG_MMC_SDHCI_SDMA
+#if CONFIG_IS_ENABLED(MMC_SDHCI_SDMA)
        if ((caps & SDHCI_CAN_DO_SDMA)) {
                host->flags |= USE_SDMA;
        } else {
@@ -882,7 +887,7 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 #endif
 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
        if (!(caps & SDHCI_CAN_DO_ADMA2)) {
-               printf("%s: Your controller doesn't support SDMA!!\n",
+               printf("%s: Your controller doesn't support ADMA!!\n",
                       __func__);
                return -EINVAL;
        }

diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c
index e9c7d3a..d1e2681 100644 (file)
--- a/drivers/mmc/tmio-common.c
+++ b/drivers/mmc/tmio-common.c
@@ -369,22 +369,23 @@ static bool tmio_sd_addr_is_dmaable(struct mmc_data *data)
        if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
                return false;
 
-#if defined(CONFIG_RCAR_GEN3)
-       if (!(data->flags & MMC_DATA_READ) && !IS_ALIGNED(addr, 128))
-               return false;
-       /* Gen3 DMA has 32bit limit */
-       if (addr >> 32)
-               return false;
-#endif
+       if (IS_ENABLED(CONFIG_RCAR_64)) {
+               if (!(data->flags & MMC_DATA_READ) && !IS_ALIGNED(addr, 128))
+                       return false;
+               /* Gen3 DMA has 32bit limit */
+               if (sizeof(addr) > 4 && addr >> 32)
+                       return false;
+       }
 
-#if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
-       defined(CONFIG_SPL_BUILD)
-       /*
-        * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
-        * of L2, which is unreachable from the DMA engine.
-        */
-       if (addr < CONFIG_SPL_STACK)
-               return false;
+#ifdef CONFIG_SPL_BUILD
+       if (IS_ENABLED(CONFIG_ARCH_UNIPHIER) && !IS_ENABLED(CONFIG_ARM64)) {
+               /*
+                * For UniPhier ARMv7 SoCs, the stack is allocated in locked
+                * ways of L2, which is unreachable from the DMA engine.
+                */
+               if (addr < CONFIG_SPL_STACK)
+                       return false;
+       }
 #endif
 
        return true;
@@ -622,25 +623,22 @@ static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, struct mmc *mmc)
 static void tmio_sd_set_pins(struct udevice *dev)
 {
        __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
-
-#ifdef CONFIG_DM_REGULATOR
        struct tmio_sd_priv *priv = dev_get_priv(dev);
 
-       if (priv->vqmmc_dev) {
+       if (CONFIG_IS_ENABLED(DM_REGULATOR) && priv->vqmmc_dev) {
                if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
                        regulator_set_value(priv->vqmmc_dev, 1800000);
                else
                        regulator_set_value(priv->vqmmc_dev, 3300000);
                regulator_set_enable(priv->vqmmc_dev, true);
        }
-#endif
 
-#ifdef CONFIG_PINCTRL
-       if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
-               pinctrl_select_state(dev, "state_uhs");
-       else
-               pinctrl_select_state(dev, "default");
-#endif
+       if (CONFIG_IS_ENABLED(PINCTRL)) {
+               if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
+                       pinctrl_select_state(dev, "state_uhs");
+               else
+                       pinctrl_select_state(dev, "default");
+       }
 }
 
 int tmio_sd_set_ios(struct udevice *dev)
@@ -734,11 +732,12 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks)
        if (!priv->regbase)
                return -ENOMEM;
 
-#ifdef CONFIG_DM_REGULATOR
-       device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
-       if (priv->vqmmc_dev)
-               regulator_set_value(priv->vqmmc_dev, 3300000);
-#endif
+       if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
+               device_get_supply_regulator(dev, "vqmmc-supply",
+                                           &priv->vqmmc_dev);
+               if (priv->vqmmc_dev)
+                       regulator_set_value(priv->vqmmc_dev, 3300000);
+       }
 
        ret = mmc_of_parse(dev, &plat->cfg);
        if (ret < 0) {

diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h
index 4d717d8..f489fb7 100644 (file)
--- a/drivers/mmc/tmio-common.h
+++ b/drivers/mmc/tmio-common.h
@@ -133,9 +133,7 @@ struct tmio_sd_priv {
 #define TMIO_SD_CAP_RCAR_UHS           BIT(7)  /* Renesas RCar UHS/SDR modes */
 #define TMIO_SD_CAP_RCAR               \
        (TMIO_SD_CAP_RCAR_GEN2 | TMIO_SD_CAP_RCAR_GEN3)
-#ifdef CONFIG_DM_REGULATOR
        struct udevice *vqmmc_dev;
-#endif
 #if CONFIG_IS_ENABLED(CLK)
        struct clk                      clk;
        struct clk                      clkh;

diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index af45ef0..5fa88da 100644 (file)
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -270,4 +270,6 @@ source "drivers/mtd/spi/Kconfig"
 
 source "drivers/mtd/ubi/Kconfig"
 
+source "drivers/mtd/nvmxip/Kconfig"
+
 endmenu

diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 3a78590..c638980 100644 (file)
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -25,6 +25,7 @@ obj-y += nand/
 obj-y += onenand/
 obj-y += spi/
 obj-$(CONFIG_MTD_UBI) += ubi/
+obj-$(CONFIG_NVMXIP) += nvmxip/
 
 #SPL/TPL build
 else

diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 5c7b0d9..d115fcf 100644 (file)
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -156,6 +156,13 @@ config NAND_BRCMNAND_63158
        help
          Enable support for broadcom nand driver on bcm63158.
 
+config NAND_BRCMNAND_IPROC
+       bool "Support Broadcom NAND controller on the iproc family"
+       depends on NAND_BRCMNAND
+       help
+         Enable support for broadcom nand driver on the Broadcom
+         iproc family such as Northstar (BCM5301x, BCM4708...)
+
 config NAND_DAVINCI
        bool "Support TI Davinci NAND controller"
        select SYS_NAND_SELF_INIT if TARGET_DA850EVM

diff --git a/drivers/mtd/nand/raw/brcmnand/Makefile b/drivers/mtd/nand/raw/brcmnand/Makefile
index f46a7ed..0c6325a 100644 (file)
--- a/drivers/mtd/nand/raw/brcmnand/Makefile
+++ b/drivers/mtd/nand/raw/brcmnand/Makefile
@@ -6,5 +6,6 @@ obj-$(CONFIG_NAND_BRCMNAND_6753) += bcm6753_nand.o
 obj-$(CONFIG_NAND_BRCMNAND_68360) += bcm68360_nand.o
 obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o
 obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o
+obj-$(CONFIG_NAND_BRCMNAND_IPROC) += iproc_nand.o
 obj-$(CONFIG_NAND_BRCMNAND) += brcmnand.o
 obj-$(CONFIG_NAND_BRCMNAND) += brcmnand_compat.o

diff --git a/drivers/mtd/nand/raw/brcmnand/iproc_nand.c b/drivers/mtd/nand/raw/brcmnand/iproc_nand.c
new file mode 100644 (file)
index 0000000..69711d9
--- /dev/null
+++ b/drivers/mtd/nand/raw/brcmnand/iproc_nand.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Code borrowed from the Linux driver
+ * Copyright (C) 2015 Broadcom Corporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <memalign.h>
+#include <nand.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <dm.h>
+
+#include "brcmnand.h"
+
+struct iproc_nand_soc {
+       struct brcmnand_soc soc;
+       void __iomem *idm_base;
+       void __iomem *ext_base;
+};
+
+#define IPROC_NAND_CTLR_READY_OFFSET   0x10
+#define IPROC_NAND_CTLR_READY          BIT(0)
+
+#define IPROC_NAND_IO_CTRL_OFFSET      0x00
+#define IPROC_NAND_APB_LE_MODE         BIT(24)
+#define IPROC_NAND_INT_CTRL_READ_ENABLE        BIT(6)
+
+static bool iproc_nand_intc_ack(struct brcmnand_soc *soc)
+{
+       struct iproc_nand_soc *priv =
+                       container_of(soc, struct iproc_nand_soc, soc);
+       void __iomem *mmio = priv->ext_base + IPROC_NAND_CTLR_READY_OFFSET;
+       u32 val = brcmnand_readl(mmio);
+
+       if (val & IPROC_NAND_CTLR_READY) {
+               brcmnand_writel(IPROC_NAND_CTLR_READY, mmio);
+               return true;
+       }
+
+       return false;
+}
+
+static void iproc_nand_intc_set(struct brcmnand_soc *soc, bool en)
+{
+       struct iproc_nand_soc *priv =
+                       container_of(soc, struct iproc_nand_soc, soc);
+       void __iomem *mmio = priv->idm_base + IPROC_NAND_IO_CTRL_OFFSET;
+       u32 val = brcmnand_readl(mmio);
+
+       if (en)
+               val |= IPROC_NAND_INT_CTRL_READ_ENABLE;
+       else
+               val &= ~IPROC_NAND_INT_CTRL_READ_ENABLE;
+
+       brcmnand_writel(val, mmio);
+}
+
+static void iproc_nand_apb_access(struct brcmnand_soc *soc, bool prepare,
+                                 bool is_param)
+{
+       struct iproc_nand_soc *priv =
+               container_of(soc, struct iproc_nand_soc, soc);
+       void __iomem *mmio = priv->idm_base + IPROC_NAND_IO_CTRL_OFFSET;
+       u32 val;
+
+       val = brcmnand_readl(mmio);
+
+       /*
+        * In the case of BE or when dealing with NAND data, always configure
+        * the APB bus to LE mode before accessing the FIFO and back to BE mode
+        * after the access is done
+        */
+       if (IS_ENABLED(CONFIG_SYS_BIG_ENDIAN) || !is_param) {
+               if (prepare)
+                       val |= IPROC_NAND_APB_LE_MODE;
+               else
+                       val &= ~IPROC_NAND_APB_LE_MODE;
+       } else { /* when in LE accessing the parameter page, keep APB in BE */
+               val &= ~IPROC_NAND_APB_LE_MODE;
+       }
+
+       brcmnand_writel(val, mmio);
+}
+
+static int iproc_nand_probe(struct udevice *dev)
+{
+       struct udevice *pdev = dev;
+       struct iproc_nand_soc *priv = dev_get_priv(dev);
+       struct brcmnand_soc *soc;
+       struct resource res;
+       int ret;
+
+       soc = &priv->soc;
+
+       ret = dev_read_resource_byname(pdev, "iproc-idm", &res);
+       if (ret)
+               return ret;
+
+       priv->idm_base = devm_ioremap(dev, res.start, resource_size(&res));
+       if (IS_ERR(priv->idm_base))
+               return PTR_ERR(priv->idm_base);
+
+       ret = dev_read_resource_byname(pdev, "iproc-ext", &res);
+       if (ret)
+               return ret;
+
+       priv->ext_base = devm_ioremap(dev, res.start, resource_size(&res));
+       if (IS_ERR(priv->ext_base))
+               return PTR_ERR(priv->ext_base);
+
+       soc->ctlrdy_ack = iproc_nand_intc_ack;
+       soc->ctlrdy_set_enabled = iproc_nand_intc_set;
+       soc->prepare_data_bus = iproc_nand_apb_access;
+
+       return brcmnand_probe(pdev, soc);
+}
+
+static const struct udevice_id iproc_nand_dt_ids[] = {
+       {
+               .compatible = "brcm,nand-iproc",
+       },
+       { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(iproc_nand) = {
+       .name = "iproc-nand",
+       .id = UCLASS_MTD,
+       .of_match = iproc_nand_dt_ids,
+       .probe = iproc_nand_probe,
+       .priv_auto = sizeof(struct iproc_nand_soc),
+};
+
+void board_nand_init(void)
+{
+       struct udevice *dev;
+       int ret;
+
+       ret = uclass_get_device_by_driver(UCLASS_MTD,
+                                         DM_DRIVER_GET(iproc_nand), &dev);
+       if (ret && ret != -ENODEV)
+               pr_err("Failed to initialize %s. (error %d)\n", dev->name,
+                      ret);
+}

diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 9eba360..6b4adcf 100644 (file)
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -4487,6 +4487,7 @@ EXPORT_SYMBOL(nand_detect);
 static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode node)
 {
        int ret, ecc_mode = -1, ecc_strength, ecc_step;
+       int ecc_algo = NAND_ECC_UNKNOWN;
        const char *str;
 
        ret = ofnode_read_s32_default(node, "nand-bus-width", -1);
@@ -4512,10 +4513,22 @@ static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode nod
                        ecc_mode = NAND_ECC_SOFT_BCH;
        }
 
-       if (ecc_mode == NAND_ECC_SOFT) {
-               str = ofnode_read_string(node, "nand-ecc-algo");
-               if (str && !strcmp(str, "bch"))
-                       ecc_mode = NAND_ECC_SOFT_BCH;
+       str = ofnode_read_string(node, "nand-ecc-algo");
+       if (str) {
+               /*
+                * If we are in NAND_ECC_SOFT mode, just alter the
+                * soft mode to BCH here. No change of algorithm.
+                */
+               if (ecc_mode == NAND_ECC_SOFT) {
+                       if (!strcmp(str, "bch"))
+                               ecc_mode = NAND_ECC_SOFT_BCH;
+               } else {
+                       if (!strcmp(str, "bch")) {
+                               ecc_algo = NAND_ECC_BCH;
+                       } else if (!strcmp(str, "hamming")) {
+                               ecc_algo = NAND_ECC_HAMMING;
+                       }
+               }
        }
 
        ecc_strength = ofnode_read_s32_default(node,
@@ -4529,6 +4542,14 @@ static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode nod
                return -EINVAL;
        }
 
+       /*
+        * Chip drivers may have assigned default algorithms here,
+        * onlt override it if we have found something explicitly
+        * specified in the device tree.
+        */
+       if (ecc_algo != NAND_ECC_UNKNOWN)
+               chip->ecc.algo = ecc_algo;
+
        if (ecc_mode >= 0)
                chip->ecc.mode = ecc_mode;
 

diff --git a/drivers/mtd/nand/raw/octeontx_bch.c b/drivers/mtd/nand/raw/octeontx_bch.c
index fc16b77..056a685 100644 (file)
--- a/drivers/mtd/nand/raw/octeontx_bch.c
+++ b/drivers/mtd/nand/raw/octeontx_bch.c
@@ -27,7 +27,7 @@
 #include <asm/arch/clock.h>
 #include "octeontx_bch.h"
 
-LIST_HEAD(octeontx_bch_devices);
+static LIST_HEAD(octeontx_bch_devices);
 static unsigned int num_vfs = BCH_NR_VF;
 static void *bch_pf;
 static void *bch_vf;

diff --git a/drivers/mtd/nand/raw/octeontx_nand.c b/drivers/mtd/nand/raw/octeontx_nand.c
index 1ffadad..65a03d2 100644 (file)
--- a/drivers/mtd/nand/raw/octeontx_nand.c
+++ b/drivers/mtd/nand/raw/octeontx_nand.c
@@ -354,7 +354,7 @@ struct octeontx_probe_device {
 
 static struct bch_vf *bch_vf;
 /** Deferred devices due to BCH not being ready */
-LIST_HEAD(octeontx_pci_nand_deferred_devices);
+static LIST_HEAD(octeontx_pci_nand_deferred_devices);
 
 /** default parameters used for probing chips */
 #define MAX_ONFI_MODE  5

diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
index fb3279b..69dbb62 100644 (file)
--- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c
+++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
@@ -735,6 +735,9 @@ static int stm32_fmc2_nfc_setup_interface(struct mtd_info *mtd, int chipnr,
        if (IS_ERR(sdrt))
                return PTR_ERR(sdrt);
 
+       if (sdrt->tRC_min < 30000)
+               return -EOPNOTSUPP;
+
        if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
                return 0;
 

diff --git a/drivers/mtd/nvmxip/Kconfig b/drivers/mtd/nvmxip/Kconfig
new file mode 100644 (file)
index 0000000..3ef7105
--- /dev/null
+++ b/drivers/mtd/nvmxip/Kconfig
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# Authors:
+#   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+
+config NVMXIP
+       bool "NVM XIP devices support"
+       select BLK
+       help
+         This option allows the emulation of a block storage device
+         on top of a direct access non volatile memory XIP flash devices.
+         This support provides the read operation.
+
+config NVMXIP_QSPI
+       bool "QSPI XIP  support"
+       select NVMXIP
+       help
+         This option allows the emulation of a block storage device on top of a QSPI XIP flash

diff --git a/drivers/mtd/nvmxip/Makefile b/drivers/mtd/nvmxip/Makefile
new file mode 100644 (file)
index 0000000..54eacc1
--- /dev/null
+++ b/drivers/mtd/nvmxip/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# Authors:
+#   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+
+obj-y += nvmxip-uclass.o nvmxip.o
+obj-$(CONFIG_NVMXIP_QSPI) += nvmxip_qspi.o

diff --git a/drivers/mtd/nvmxip/nvmxip-uclass.c b/drivers/mtd/nvmxip/nvmxip-uclass.c
new file mode 100644 (file)
index 0000000..6d8eb17
--- /dev/null
+++ b/drivers/mtd/nvmxip/nvmxip-uclass.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#if CONFIG_IS_ENABLED(SANDBOX64)
+#include <asm/test.h>
+#endif
+#include <linux/bitops.h>
+#include "nvmxip.h"
+
+/* LBA Macros */
+
+#define DEFAULT_LBA_SHIFT 10 /* 1024 bytes per block */
+#define DEFAULT_LBA_COUNT 1024 /* block count */
+
+#define DEFAULT_LBA_SZ BIT(DEFAULT_LBA_SHIFT)
+
+/**
+ * nvmxip_post_bind() - post binding treatments
+ * @dev:       the NVMXIP device
+ *
+ * Create and probe a child block device.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int nvmxip_post_bind(struct udevice *udev)
+{
+       int ret;
+       struct udevice *bdev = NULL;
+       char bdev_name[NVMXIP_BLKDEV_NAME_SZ + 1];
+       int devnum;
+
+#if CONFIG_IS_ENABLED(SANDBOX64)
+       sandbox_set_enable_memio(true);
+#endif
+
+       devnum = uclass_id_count(UCLASS_NVMXIP);
+       snprintf(bdev_name, NVMXIP_BLKDEV_NAME_SZ, "blk#%d", devnum);
+
+       ret = blk_create_devicef(udev, NVMXIP_BLKDRV_NAME, bdev_name, UCLASS_NVMXIP,
+                                devnum, DEFAULT_LBA_SZ,
+                                DEFAULT_LBA_COUNT, &bdev);
+       if (ret) {
+               log_err("[%s]: failure during creation of the block device %s, error %d\n",
+                       udev->name, bdev_name, ret);
+               return ret;
+       }
+
+       ret = blk_probe_or_unbind(bdev);
+       if (ret) {
+               log_err("[%s]: failure during probing the block device %s, error %d\n",
+                       udev->name, bdev_name, ret);
+               return ret;
+       }
+
+       log_info("[%s]: the block device %s ready for use\n", udev->name, bdev_name);
+
+       return 0;
+}
+
+UCLASS_DRIVER(nvmxip) = {
+       .name      = "nvmxip",
+       .id        = UCLASS_NVMXIP,
+       .post_bind = nvmxip_post_bind,
+};

diff --git a/drivers/mtd/nvmxip/nvmxip.c b/drivers/mtd/nvmxip/nvmxip.c
new file mode 100644 (file)
index 0000000..a359e3b
--- /dev/null
+++ b/drivers/mtd/nvmxip/nvmxip.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <mapmem.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include "nvmxip.h"
+
+/**
+ * nvmxip_mmio_rawread() - read from the XIP flash
+ * @address:   address of the data
+ * @value:     pointer to where storing the value read
+ *
+ * Read raw data from the XIP flash.
+ *
+ * Return:
+ *
+ * Always return 0.
+ */
+static int nvmxip_mmio_rawread(const phys_addr_t address, u64 *value)
+{
+       *value = readq(address);
+       return 0;
+}
+
+/**
+ * nvmxip_blk_read() - block device read operation
+ * @dev:       the block device
+ * @blknr:     first block number to read from
+ * @blkcnt:    number of blocks to read
+ * @buffer:    destination buffer
+ *
+ * Read data from the block storage device.
+ *
+ * Return:
+ *
+ * number of blocks read on success. Otherwise, failure
+ */
+static ulong nvmxip_blk_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, void *buffer)
+{
+       struct nvmxip_plat *plat = dev_get_plat(dev->parent);
+       struct blk_desc *desc = dev_get_uclass_plat(dev);
+       /* number of the u64 words to read */
+       u32 qwords = (blkcnt * desc->blksz) / sizeof(u64);
+       /* physical address of the first block to read */
+       phys_addr_t blkaddr = plat->phys_base + blknr * desc->blksz;
+       u64 *virt_blkaddr;
+       u64 *pdst = buffer;
+       uint qdata_idx;
+
+       if (!pdst)
+               return -EINVAL;
+
+       log_debug("[%s]: reading from blknr: %lu , blkcnt: %lu\n", dev->name, blknr, blkcnt);
+
+       virt_blkaddr = map_sysmem(blkaddr, 0);
+
+       /* assumption: the data is virtually contiguous */
+
+       for (qdata_idx = 0 ; qdata_idx < qwords ; qdata_idx++)
+               nvmxip_mmio_rawread((phys_addr_t)(virt_blkaddr + qdata_idx), pdst++);
+
+       log_debug("[%s]:     src[0]: 0x%llx , dst[0]: 0x%llx , src[-1]: 0x%llx , dst[-1]: 0x%llx\n",
+                 dev->name,
+                 *virt_blkaddr,
+                 *(u64 *)buffer,
+                 *(u64 *)((u8 *)virt_blkaddr + desc->blksz * blkcnt - sizeof(u64)),
+                 *(u64 *)((u8 *)buffer + desc->blksz * blkcnt - sizeof(u64)));
+
+       unmap_sysmem(virt_blkaddr);
+
+       return blkcnt;
+}
+
+/**
+ * nvmxip_blk_probe() - block storage device probe
+ * @dev:       the block storage device
+ *
+ * Initialize the block storage descriptor.
+ *
+ * Return:
+ *
+ * Always return 0.
+ */
+static int nvmxip_blk_probe(struct udevice *dev)
+{
+       struct nvmxip_plat *plat = dev_get_plat(dev->parent);
+       struct blk_desc *desc = dev_get_uclass_plat(dev);
+
+       desc->lba = plat->lba;
+       desc->log2blksz = plat->lba_shift;
+       desc->blksz = BIT(plat->lba_shift);
+       desc->bdev = dev;
+
+       log_debug("[%s]: block storage layout\n    lbas: %lu , log2blksz: %d, blksz: %lu\n",
+                 dev->name, desc->lba, desc->log2blksz, desc->blksz);
+
+       return 0;
+}
+
+static const struct blk_ops nvmxip_blk_ops = {
+       .read   = nvmxip_blk_read,
+};
+
+U_BOOT_DRIVER(nvmxip_blk) = {
+       .name   = NVMXIP_BLKDRV_NAME,
+       .id     = UCLASS_BLK,
+       .probe  = nvmxip_blk_probe,
+       .ops    = &nvmxip_blk_ops,
+};

diff --git a/drivers/mtd/nvmxip/nvmxip.h b/drivers/mtd/nvmxip/nvmxip.h
new file mode 100644 (file)
index 0000000..f4ef377
--- /dev/null
+++ b/drivers/mtd/nvmxip/nvmxip.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#ifndef __DRIVER_NVMXIP_H__
+#define __DRIVER_NVMXIP_H__
+
+#include <blk.h>
+
+#define NVMXIP_BLKDRV_NAME    "nvmxip-blk"
+#define NVMXIP_BLKDEV_NAME_SZ 20
+
+/**
+ * struct nvmxip_plat - the NVMXIP driver plat
+ *
+ * @phys_base: NVM XIP device base address
+ * @lba_shift: block size shift count
+ * @lba:       number of blocks
+ *
+ * The NVMXIP information read from the DT.
+ */
+struct nvmxip_plat {
+       phys_addr_t phys_base;
+       u32 lba_shift;
+       lbaint_t lba;
+};
+
+#endif /* __DRIVER_NVMXIP_H__ */

diff --git a/drivers/mtd/nvmxip/nvmxip_qspi.c b/drivers/mtd/nvmxip/nvmxip_qspi.c
new file mode 100644 (file)
index 0000000..7221fd1
--- /dev/null
+++ b/drivers/mtd/nvmxip/nvmxip_qspi.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <linux/errno.h>
+#include "nvmxip.h"
+
+#include <asm/global_data.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define NVMXIP_QSPI_DRV_NAME "nvmxip_qspi"
+
+/**
+ * nvmxip_qspi_of_to_plat() -read from DT
+ * @dev:       the NVMXIP device
+ *
+ * Read from the DT the NVMXIP information.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int nvmxip_qspi_of_to_plat(struct udevice *dev)
+{
+       struct nvmxip_plat *plat = dev_get_plat(dev);
+       int ret;
+
+       plat->phys_base = (phys_addr_t)dev_read_addr(dev);
+       if (plat->phys_base == FDT_ADDR_T_NONE) {
+               log_err("[%s]: can not get base address from device tree\n", dev->name);
+               return -EINVAL;
+       }
+
+       ret = dev_read_u32(dev, "lba_shift", &plat->lba_shift);
+       if (ret) {
+               log_err("[%s]: can not get lba_shift from device tree\n", dev->name);
+               return -EINVAL;
+       }
+
+       ret = dev_read_u32(dev, "lba", (u32 *)&plat->lba);
+       if (ret) {
+               log_err("[%s]: can not get lba from device tree\n", dev->name);
+               return -EINVAL;
+       }
+
+       log_debug("[%s]: XIP device base addr: 0x%llx , lba_shift: %d , lbas: %lu\n",
+                 dev->name, plat->phys_base, plat->lba_shift, plat->lba);
+
+       return 0;
+}
+
+static const struct udevice_id nvmxip_qspi_ids[] = {
+       { .compatible = "nvmxip,qspi" },
+       { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(nvmxip_qspi) = {
+       .name = NVMXIP_QSPI_DRV_NAME,
+       .id = UCLASS_NVMXIP,
+       .of_match = nvmxip_qspi_ids,
+       .of_to_plat = nvmxip_qspi_of_to_plat,
+       .plat_auto = sizeof(struct nvmxip_plat),
+};

diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index 3c01e3b..4fe5471 100644 (file)
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -248,6 +248,7 @@ static int sandbox_sf_process_cmd(struct sandbox_spi_flash *sbsf, const u8 *rx,
                break;
        case SPINOR_OP_READ_FAST:
                sbsf->pad_addr_bytes = 1;
+               fallthrough;
        case SPINOR_OP_READ:
        case SPINOR_OP_PP:
                sbsf->state = SF_ADDR;

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index ceadee9..09039a2 100644 (file)
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -752,9 +752,17 @@ config GMAC_ROCKCHIP
          This driver provides Rockchip SoCs network support based on the
          Synopsys Designware driver.
 
+config RENESAS_ETHER_SWITCH
+       bool "Renesas Ethernet Switch support"
+       depends on DM_ETH && R8A779F0
+       select PHYLIB
+       help
+         This driver implements support for the Renesas Ethernet Switch
+         which is available on R-Car S4 SoC (r8a779f0).
+
 config RENESAS_RAVB
        bool "Renesas Ethernet AVB MAC"
-       depends on RCAR_GEN3
+       depends on RCAR_64
        select PHYLIB
        help
          This driver implements support for the Ethernet AVB block in

diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 75daa5e..46a40e2 100644 (file)
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_OCTEONTX_SMI) += octeontx/smi.o
 obj-$(CONFIG_PCH_GBE) += pch_gbe.o
 obj-$(CONFIG_PCNET) += pcnet.o
 obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
+obj-$(CONFIG_RENESAS_ETHER_SWITCH) += rswitch.o
 obj-$(CONFIG_RENESAS_RAVB) += ravb.o
 obj-$(CONFIG_RTL8139) += rtl8139.o
 obj-$(CONFIG_RTL8169) += rtl8169.o

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 1bad50d..f407d8f 100644 (file)
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -2871,7 +2871,6 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port)
 
        switch (port->phy_interface) {
        case PHY_INTERFACE_MODE_SGMII:
-       case PHY_INTERFACE_MODE_SGMII_2500:
                val |= MVPP2_GMAC_INBAND_AN_MASK;
                break;
        case PHY_INTERFACE_MODE_1000BASEX:
@@ -2939,7 +2938,6 @@ static void mvpp2_port_loopback_set(struct mvpp2_port *port)
                val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
 
        if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
-           port->phy_interface == PHY_INTERFACE_MODE_SGMII_2500 ||
            port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
            port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
                val |= MVPP2_GMAC_PCS_LB_EN_MASK;
@@ -3027,48 +3025,6 @@ static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en)
        return 0;
 }
 
-static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
-{
-       u32 val, thresh;
-
-       /*
-        * Configure minimal level of the Tx FIFO before the lower part
-        * starts to read a packet
-        */
-       thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
-       val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
-       val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
-       val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
-       writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
-
-       /* Disable bypass of sync module */
-       val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
-       val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
-       /* configure DP clock select according to mode */
-       val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
-       /* configure QSGMII bypass according to mode */
-       val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
-       writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
-
-       val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
-       /*
-        * Configure GIG MAC to SGMII mode connected to a fiber
-        * transceiver
-        */
-       val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
-       writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
-
-       /* configure AN 0x9268 */
-       val = MVPP2_GMAC_EN_PCS_AN |
-               MVPP2_GMAC_AN_BYPASS_EN |
-               MVPP2_GMAC_CONFIG_MII_SPEED  |
-               MVPP2_GMAC_CONFIG_GMII_SPEED     |
-               MVPP2_GMAC_FC_ADV_EN    |
-               MVPP2_GMAC_CONFIG_FULL_DUPLEX |
-               MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
-       writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
-}
-
 static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
 {
        u32 val, thresh;
@@ -3239,9 +3195,6 @@ static int gop_gmac_mode_cfg(struct mvpp2_port *port)
        case PHY_INTERFACE_MODE_SGMII:
                gop_gmac_sgmii_cfg(port);
                break;
-       case PHY_INTERFACE_MODE_SGMII_2500:
-               gop_gmac_sgmii2_5_cfg(port);
-               break;
        case PHY_INTERFACE_MODE_1000BASEX:
                gop_gmac_1000basex_cfg(port);
                break;
@@ -3422,7 +3375,6 @@ static int gop_port_init(struct mvpp2_port *port)
                break;
 
        case PHY_INTERFACE_MODE_SGMII:
-       case PHY_INTERFACE_MODE_SGMII_2500:
        case PHY_INTERFACE_MODE_1000BASEX:
        case PHY_INTERFACE_MODE_2500BASEX:
                /* configure PCS */
@@ -3439,7 +3391,9 @@ static int gop_port_init(struct mvpp2_port *port)
                gop_gmac_reset(port, 0);
                break;
 
-       case PHY_INTERFACE_MODE_SFI:
+       case PHY_INTERFACE_MODE_10GBASER:
+       case PHY_INTERFACE_MODE_5GBASER:
+       case PHY_INTERFACE_MODE_XAUI:
                num_of_act_lanes = 2;
                mac_num = 0;
                /* configure PCS */
@@ -3482,7 +3436,6 @@ static void gop_port_enable(struct mvpp2_port *port, int enable)
        case PHY_INTERFACE_MODE_RGMII:
        case PHY_INTERFACE_MODE_RGMII_ID:
        case PHY_INTERFACE_MODE_SGMII:
-       case PHY_INTERFACE_MODE_SGMII_2500:
        case PHY_INTERFACE_MODE_1000BASEX:
        case PHY_INTERFACE_MODE_2500BASEX:
                if (enable)
@@ -3491,7 +3444,9 @@ static void gop_port_enable(struct mvpp2_port *port, int enable)
                        mvpp2_port_disable(port);
                break;
 
-       case PHY_INTERFACE_MODE_SFI:
+       case PHY_INTERFACE_MODE_10GBASER:
+       case PHY_INTERFACE_MODE_5GBASER:
+       case PHY_INTERFACE_MODE_XAUI:
                gop_xlg_mac_port_enable(port, enable);
 
                break;
@@ -3519,7 +3474,6 @@ static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
 
        if (gop_id == 2) {
                if (phy_type == PHY_INTERFACE_MODE_SGMII ||
-                   phy_type == PHY_INTERFACE_MODE_SGMII_2500 ||
                    phy_type == PHY_INTERFACE_MODE_1000BASEX ||
                    phy_type == PHY_INTERFACE_MODE_2500BASEX)
                        val |= MV_NETC_GE_MAC2_SGMII;
@@ -3530,7 +3484,6 @@ static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
 
        if (gop_id == 3) {
                if (phy_type == PHY_INTERFACE_MODE_SGMII ||
-                   phy_type == PHY_INTERFACE_MODE_SGMII_2500 ||
                    phy_type == PHY_INTERFACE_MODE_1000BASEX ||
                    phy_type == PHY_INTERFACE_MODE_2500BASEX)
                        val |= MV_NETC_GE_MAC3_SGMII;
@@ -4529,7 +4482,6 @@ static void mvpp2_start_dev(struct mvpp2_port *port)
        case PHY_INTERFACE_MODE_RGMII:
        case PHY_INTERFACE_MODE_RGMII_ID:
        case PHY_INTERFACE_MODE_SGMII:
-       case PHY_INTERFACE_MODE_SGMII_2500:
        case PHY_INTERFACE_MODE_1000BASEX:
        case PHY_INTERFACE_MODE_2500BASEX:
                mvpp2_gmac_max_rx_size_set(port);
@@ -5263,7 +5215,6 @@ static int mvpp2_start(struct udevice *dev)
        case PHY_INTERFACE_MODE_RGMII:
        case PHY_INTERFACE_MODE_RGMII_ID:
        case PHY_INTERFACE_MODE_SGMII:
-       case PHY_INTERFACE_MODE_SGMII_2500:
        case PHY_INTERFACE_MODE_1000BASEX:
        case PHY_INTERFACE_MODE_2500BASEX:
                mvpp2_port_power_up(port);

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 6806e3c..2415877 100644 (file)
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -174,6 +174,11 @@ config PHY_LXT
 config PHY_MARVELL
        bool "Marvell Ethernet PHYs support"
 
+config PHY_MARVELL_10G
+       bool "Marvell Alaska 10Gbit PHYs"
+       help
+         Support for the Marvell Alaska MV88X3310 and compatible PHYs.
+
 config PHY_MESON_GXL
        bool "Amlogic Meson GXL Internal PHY support"
 

diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index d38e99e..85d17f1 100644 (file)
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PHY_DAVICOM) += davicom.o
 obj-$(CONFIG_PHY_ET1011C) += et1011c.o
 obj-$(CONFIG_PHY_LXT) += lxt.o
 obj-$(CONFIG_PHY_MARVELL) += marvell.o
+obj-$(CONFIG_PHY_MARVELL_10G) += marvell10g.o
 obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o
 obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
 obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o
@@ -29,7 +30,7 @@ obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o
 obj-$(CONFIG_PHY_REALTEK) += realtek.o
 obj-$(CONFIG_PHY_SMSC) += smsc.o
 obj-$(CONFIG_PHY_TERANETICS) += teranetics.o
-obj-$(CONFIG_PHY_TI) += ti_phy_init.o
+obj-$(CONFIG_PHY_TI_GENERIC) += ti_phy_init.o
 obj-$(CONFIG_PHY_TI_DP83867) += dp83867.o
 obj-$(CONFIG_PHY_TI_DP83869) += dp83869.o
 obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o

diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
index a5bfd96..fb9f1e4 100644 (file)
--- a/drivers/net/phy/adin.c
+++ b/drivers/net/phy/adin.c
@@ -252,7 +252,7 @@ static int adin1300_config(struct phy_device *phydev)
        return genphy_config(phydev);
 }
 
-static struct phy_driver ADIN1300_driver =  {
+U_BOOT_PHY_DRIVER(ADIN1300) = {
        .name = "ADIN1300",
        .uid = PHY_ID_ADIN1300,
        .mask = 0xffffffff,
@@ -261,10 +261,3 @@ static struct phy_driver ADIN1300_driver =  {
        .startup = genphy_startup,
        .shutdown = genphy_shutdown,
 };
-
-int phy_adin_init(void)
-{
-       phy_register(&ADIN1300_driver);
-
-       return 0;
-}

diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index 8eb6024..a958e88 100644 (file)
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -598,7 +598,7 @@ int aquantia_startup(struct phy_device *phydev)
        return 0;
 }
 
-struct phy_driver aq1202_driver = {
+U_BOOT_PHY_DRIVER(aq1202) = {
        .name = "Aquantia AQ1202",
        .uid = 0x3a1b445,
        .mask = 0xfffffff0,
@@ -611,7 +611,7 @@ struct phy_driver aq1202_driver = {
        .shutdown = &gen10g_shutdown,
 };
 
-struct phy_driver aq2104_driver = {
+U_BOOT_PHY_DRIVER(aq2104) = {
        .name = "Aquantia AQ2104",
        .uid = 0x3a1b460,
        .mask = 0xfffffff0,
@@ -624,7 +624,7 @@ struct phy_driver aq2104_driver = {
        .shutdown = &gen10g_shutdown,
 };
 
-struct phy_driver aqr105_driver = {
+U_BOOT_PHY_DRIVER(aqr105) = {
        .name = "Aquantia AQR105",
        .uid = 0x3a1b4a2,
        .mask = 0xfffffff0,
@@ -638,7 +638,7 @@ struct phy_driver aqr105_driver = {
        .data = AQUANTIA_GEN1,
 };
 
-struct phy_driver aqr106_driver = {
+U_BOOT_PHY_DRIVER(aqr106) = {
        .name = "Aquantia AQR106",
        .uid = 0x3a1b4d0,
        .mask = 0xfffffff0,
@@ -651,7 +651,7 @@ struct phy_driver aqr106_driver = {
        .shutdown = &gen10g_shutdown,
 };
 
-struct phy_driver aqr107_driver = {
+U_BOOT_PHY_DRIVER(aqr107) = {
        .name = "Aquantia AQR107",
        .uid = 0x3a1b4e0,
        .mask = 0xfffffff0,
@@ -665,7 +665,7 @@ struct phy_driver aqr107_driver = {
        .data = AQUANTIA_GEN2,
 };
 
-struct phy_driver aqr112_driver = {
+U_BOOT_PHY_DRIVER(aqr112) = {
        .name = "Aquantia AQR112",
        .uid = 0x3a1b660,
        .mask = 0xfffffff0,
@@ -679,7 +679,7 @@ struct phy_driver aqr112_driver = {
        .data = AQUANTIA_GEN3,
 };
 
-struct phy_driver aqr113c_driver = {
+U_BOOT_PHY_DRIVER(aqr113c) = {
        .name = "Aquantia AQR113C",
        .uid = 0x31c31c12,
        .mask = 0xfffffff0,
@@ -693,7 +693,7 @@ struct phy_driver aqr113c_driver = {
        .data = AQUANTIA_GEN3,
 };
 
-struct phy_driver aqr405_driver = {
+U_BOOT_PHY_DRIVER(aqr405) = {
        .name = "Aquantia AQR405",
        .uid = 0x3a1b4b2,
        .mask = 0xfffffff0,
@@ -707,7 +707,7 @@ struct phy_driver aqr405_driver = {
        .data = AQUANTIA_GEN1,
 };
 
-struct phy_driver aqr412_driver = {
+U_BOOT_PHY_DRIVER(aqr412) = {
        .name = "Aquantia AQR412",
        .uid = 0x3a1b710,
        .mask = 0xfffffff0,
@@ -720,18 +720,3 @@ struct phy_driver aqr412_driver = {
        .shutdown = &gen10g_shutdown,
        .data = AQUANTIA_GEN3,
 };
-
-int phy_aquantia_init(void)
-{
-       phy_register(&aq1202_driver);
-       phy_register(&aq2104_driver);
-       phy_register(&aqr105_driver);
-       phy_register(&aqr106_driver);
-       phy_register(&aqr107_driver);
-       phy_register(&aqr112_driver);
-       phy_register(&aqr113c_driver);
-       phy_register(&aqr405_driver);
-       phy_register(&aqr412_driver);
-
-       return 0;
-}

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index c6f9f91..abb7bdf 100644 (file)
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -333,7 +333,7 @@ static int ar803x_config(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver AR8021_driver =  {
+U_BOOT_PHY_DRIVER(AR8021) = {
        .name = "AR8021",
        .uid = AR8021_PHY_ID,
        .mask = 0xfffffff0,
@@ -343,7 +343,7 @@ static struct phy_driver AR8021_driver =  {
        .shutdown = genphy_shutdown,
 };
 
-static struct phy_driver AR8031_driver =  {
+U_BOOT_PHY_DRIVER(AR8031) = {
        .name = "AR8031/AR8033",
        .uid = AR8031_PHY_ID,
        .mask = 0xffffffef,
@@ -353,7 +353,7 @@ static struct phy_driver AR8031_driver =  {
        .shutdown = genphy_shutdown,
 };
 
-static struct phy_driver AR8035_driver =  {
+U_BOOT_PHY_DRIVER(AR8035) = {
        .name = "AR8035",
        .uid = AR8035_PHY_ID,
        .mask = 0xffffffef,
@@ -362,12 +362,3 @@ static struct phy_driver AR8035_driver =  {
        .startup = genphy_startup,
        .shutdown = genphy_shutdown,
 };
-
-int phy_atheros_init(void)
-{
-       phy_register(&AR8021_driver);
-       phy_register(&AR8031_driver);
-       phy_register(&AR8035_driver);
-
-       return 0;
-}

diff --git a/drivers/net/phy/b53.c b/drivers/net/phy/b53.c
index c706e2b..26e8e2f 100644 (file)
--- a/drivers/net/phy/b53.c
+++ b/drivers/net/phy/b53.c
@@ -612,7 +612,7 @@ static int b53_phy_startup(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver b53_driver = {
+U_BOOT_PHY_DRIVER(b53) = {
        .name = "Broadcom BCM53125",
        .uid = 0x03625c00,
        .mask = 0xfffffc00,
@@ -623,13 +623,6 @@ static struct phy_driver b53_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-int phy_b53_init(void)
-{
-       phy_register(&b53_driver);
-
-       return 0;
-}
-
 int do_b53_reg_read(const char *name, int argc, char *const argv[])
 {
        u8 page, offset, width;

diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 566fcb8..ea98cfc 100644 (file)
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -323,7 +323,7 @@ static int bcm5482_startup(struct phy_device *phydev)
        return bcm54xx_parse_status(phydev);
 }
 
-static struct phy_driver BCM5461S_driver = {
+U_BOOT_PHY_DRIVER(bcm5461s) = {
        .name = "Broadcom BCM5461S",
        .uid = 0x2060c0,
        .mask = 0xfffff0,
@@ -333,7 +333,7 @@ static struct phy_driver BCM5461S_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver BCM5464S_driver = {
+U_BOOT_PHY_DRIVER(bcm5464s) = {
        .name = "Broadcom BCM5464S",
        .uid = 0x2060b0,
        .mask = 0xfffff0,
@@ -343,7 +343,7 @@ static struct phy_driver BCM5464S_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver BCM5482S_driver = {
+U_BOOT_PHY_DRIVER(bcm5482s) = {
        .name = "Broadcom BCM5482S",
        .uid = 0x143bcb0,
        .mask = 0xffffff0,
@@ -353,7 +353,7 @@ static struct phy_driver BCM5482S_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver BCM_CYGNUS_driver = {
+U_BOOT_PHY_DRIVER(bcm_cygnus) = {
        .name = "Broadcom CYGNUS GPHY",
        .uid = 0xae025200,
        .mask = 0xfffff0,
@@ -362,13 +362,3 @@ static struct phy_driver BCM_CYGNUS_driver = {
        .startup = &bcm_cygnus_startup,
        .shutdown = &genphy_shutdown,
 };
-
-int phy_broadcom_init(void)
-{
-       phy_register(&BCM5482S_driver);
-       phy_register(&BCM5464S_driver);
-       phy_register(&BCM5461S_driver);
-       phy_register(&BCM_CYGNUS_driver);
-
-       return 0;
-}

diff --git a/drivers/net/phy/ca_phy.c b/drivers/net/phy/ca_phy.c
index 16851a6..edef218 100644 (file)
--- a/drivers/net/phy/ca_phy.c
+++ b/drivers/net/phy/ca_phy.c
@@ -104,7 +104,7 @@ static int rtl8211_probe(struct phy_device *phydev)
 }
 
 /* Support for RTL8211 External PHY */
-struct phy_driver rtl8211_external_driver = {
+U_BOOT_PHY_DRIVER(rtl8211_external) = {
        .name = "Cortina RTL8211 External",
        .uid = PHY_ID_RTL8211_EXT,
        .mask = PHY_ID_MASK,
@@ -115,7 +115,7 @@ struct phy_driver rtl8211_external_driver = {
 };
 
 /* Support for RTL8211 Internal PHY */
-struct phy_driver rtl8211_internal_driver = {
+U_BOOT_PHY_DRIVER(rtl8211_internal) = {
        .name = "Cortina RTL8211 Inrernal",
        .uid = PHY_ID_RTL8211_INT,
        .mask = PHY_ID_MASK,
@@ -124,10 +124,3 @@ struct phy_driver rtl8211_internal_driver = {
        .probe = &rtl8211_probe,
        .startup = &genphy_startup,
 };
-
-int phy_cortina_access_init(void)
-{
-       phy_register(&rtl8211_external_driver);
-       phy_register(&rtl8211_internal_driver);
-       return 0;
-}

diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
index 778d93e..1cf8b28 100644 (file)
--- a/drivers/net/phy/cortina.c
+++ b/drivers/net/phy/cortina.c
@@ -382,7 +382,7 @@ int cs4223_startup(struct phy_device *phydev)
        return 0;
 }
 
-struct phy_driver cs4340_driver = {
+U_BOOT_PHY_DRIVER(cs4340) = {
        .name = "Cortina CS4315/CS4340",
        .uid = PHY_UID_CS4340,
        .mask = 0xfffffff0,
@@ -396,7 +396,7 @@ struct phy_driver cs4340_driver = {
        .shutdown = &gen10g_shutdown,
 };
 
-struct phy_driver cs4223_driver = {
+U_BOOT_PHY_DRIVER(cs4223) = {
        .name = "Cortina CS4223",
        .uid = PHY_UID_CS4223,
        .mask = 0x0ffff00f,
@@ -409,13 +409,6 @@ struct phy_driver cs4223_driver = {
        .shutdown = &gen10g_shutdown,
 };
 
-int phy_cortina_init(void)
-{
-       phy_register(&cs4340_driver);
-       phy_register(&cs4223_driver);
-       return 0;
-}
-
 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
 {
        int phy_reg;

diff --git a/drivers/net/phy/davicom.c b/drivers/net/phy/davicom.c
index 4666497..31ffa1a 100644 (file)
--- a/drivers/net/phy/davicom.c
+++ b/drivers/net/phy/davicom.c
@@ -69,7 +69,7 @@ static int dm9161_startup(struct phy_device *phydev)
        return dm9161_parse_status(phydev);
 }
 
-static struct phy_driver DM9161_driver = {
+U_BOOT_PHY_DRIVER(dm9161) = {
        .name = "Davicom DM9161E",
        .uid = 0x181b880,
        .mask = 0xffffff0,
@@ -78,10 +78,3 @@ static struct phy_driver DM9161_driver = {
        .startup = &dm9161_startup,
        .shutdown = &genphy_shutdown,
 };
-
-int phy_davicom_init(void)
-{
-       phy_register(&DM9161_driver);
-
-       return 0;
-}

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index a45152b..b861bf7 100644 (file)
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -409,7 +409,7 @@ static int dp83867_probe(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver DP83867_driver = {
+U_BOOT_PHY_DRIVER(dp83867) = {
        .name = "TI DP83867",
        .uid = 0x2000a231,
        .mask = 0xfffffff0,
@@ -419,9 +419,3 @@ static struct phy_driver DP83867_driver = {
        .startup = &genphy_startup,
        .shutdown = &genphy_shutdown,
 };
-
-int phy_dp83867_init(void)
-{
-       phy_register(&DP83867_driver);
-       return 0;
-}

diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 23dbf42..8d32d73 100644 (file)
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -473,7 +473,7 @@ static int dp83869_probe(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver DP83869_driver = {
+U_BOOT_PHY_DRIVER(dp83869) = {
        .name = "TI DP83869",
        .uid = 0x2000a0f1,
        .mask = 0xfffffff0,
@@ -485,9 +485,3 @@ static struct phy_driver DP83869_driver = {
        .readext = dp83869_readext,
        .writeext = dp83869_writeext
 };
-
-int phy_dp83869_init(void)
-{
-       phy_register(&DP83869_driver);
-       return 0;
-}

diff --git a/drivers/net/phy/et1011c.c b/drivers/net/phy/et1011c.c
index 7eff5ec..fa48314 100644 (file)
--- a/drivers/net/phy/et1011c.c
+++ b/drivers/net/phy/et1011c.c
@@ -87,7 +87,7 @@ static int et1011c_startup(struct phy_device *phydev)
        return et1011c_parse_status(phydev);
 }
 
-static struct phy_driver et1011c_driver = {
+U_BOOT_PHY_DRIVER(et1011c) = {
        .name           = "ET1011C",
        .uid            = 0x0282f014,
        .mask           = 0xfffffff0,
@@ -95,10 +95,3 @@ static struct phy_driver et1011c_driver = {
        .config         = &et1011c_config,
        .startup        = &et1011c_startup,
 };
-
-int phy_et1011c_init(void)
-{
-       phy_register(&et1011c_driver);
-
-       return 0;
-}

diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c
index 1192915..2f0823b 100644 (file)
--- a/drivers/net/phy/fixed.c
+++ b/drivers/net/phy/fixed.c
@@ -93,7 +93,7 @@ static int fixedphy_shutdown(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver fixedphy_driver = {
+U_BOOT_PHY_DRIVER(fixedphy) = {
        .uid            = PHY_FIXED_ID,
        .mask           = 0xffffffff,
        .name           = "Fixed PHY",
@@ -103,9 +103,3 @@ static struct phy_driver fixedphy_driver = {
        .startup        = fixedphy_startup,
        .shutdown       = fixedphy_shutdown,
 };
-
-int phy_fixed_init(void)
-{
-       phy_register(&fixedphy_driver);
-       return 0;
-}

diff --git a/drivers/net/phy/generic_10g.c b/drivers/net/phy/generic_10g.c
index b4384e1..34ac51e 100644 (file)
--- a/drivers/net/phy/generic_10g.c
+++ b/drivers/net/phy/generic_10g.c
@@ -80,7 +80,7 @@ int gen10g_config(struct phy_device *phydev)
        return gen10g_discover_mmds(phydev);
 }
 
-struct phy_driver gen10g_driver = {
+U_BOOT_PHY_DRIVER(gen10g) = {
        .uid            = 0xffffffff,
        .mask           = 0xffffffff,
        .name           = "Generic 10G PHY",

diff --git a/drivers/net/phy/intel_xway.c b/drivers/net/phy/intel_xway.c
index dfce3f8..9d1b97d 100644 (file)
--- a/drivers/net/phy/intel_xway.c
+++ b/drivers/net/phy/intel_xway.c
@@ -30,7 +30,7 @@ static int xway_config(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver XWAY_driver = {
+U_BOOT_PHY_DRIVER(xway) = {
        .name = "XWAY",
        .uid = 0xD565A400,
        .mask = 0xffffff00,
@@ -39,10 +39,3 @@ static struct phy_driver XWAY_driver = {
        .startup = genphy_startup,
        .shutdown = genphy_shutdown,
 };
-
-int phy_xway_init(void)
-{
-       phy_register(&XWAY_driver);
-
-       return 0;
-}

diff --git a/drivers/net/phy/lxt.c b/drivers/net/phy/lxt.c
index 2618deb..2094003 100644 (file)
--- a/drivers/net/phy/lxt.c
+++ b/drivers/net/phy/lxt.c
@@ -58,7 +58,7 @@ static int lxt971_startup(struct phy_device *phydev)
        return lxt971_parse_status(phydev);
 }
 
-static struct phy_driver LXT971_driver = {
+U_BOOT_PHY_DRIVER(lxt971) = {
        .name = "LXT971",
        .uid = 0x1378e0,
        .mask = 0xfffff0,
@@ -67,10 +67,3 @@ static struct phy_driver LXT971_driver = {
        .startup = &lxt971_startup,
        .shutdown = &genphy_shutdown,
 };
-
-int phy_lxt_init(void)
-{
-       phy_register(&LXT971_driver);
-
-       return 0;
-}

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 1a25775..0a90f71 100644 (file)
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -7,6 +7,7 @@
  */
 #include <common.h>
 #include <errno.h>
+#include <marvell_phy.h>
 #include <phy.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
@@ -693,90 +694,90 @@ static int m88e1680_config(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver M88E1011S_driver = {
+U_BOOT_PHY_DRIVER(m88e1011s) = {
        .name = "Marvell 88E1011S",
-       .uid = 0x1410c60,
-       .mask = 0xffffff0,
+       .uid = MARVELL_PHY_ID_88E1101,
+       .mask = MARVELL_PHY_ID_MASK,
        .features = PHY_GBIT_FEATURES,
        .config = &m88e1011s_config,
        .startup = &m88e1011s_startup,
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver M88E1111S_driver = {
+U_BOOT_PHY_DRIVER(m88e1111s) = {
        .name = "Marvell 88E1111S",
-       .uid = 0x1410cc0,
-       .mask = 0xffffff0,
+       .uid = MARVELL_PHY_ID_88E1111,
+       .mask = MARVELL_PHY_ID_MASK,
        .features = PHY_GBIT_FEATURES,
        .config = &m88e1111s_config,
        .startup = &m88e1011s_startup,
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver M88E1118_driver = {
+U_BOOT_PHY_DRIVER(m88e1118) = {
        .name = "Marvell 88E1118",
-       .uid = 0x1410e10,
-       .mask = 0xffffff0,
+       .uid = MARVELL_PHY_ID_88E1118,
+       .mask = MARVELL_PHY_ID_MASK,
        .features = PHY_GBIT_FEATURES,
        .config = &m88e1118_config,
        .startup = &m88e1118_startup,
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver M88E1118R_driver = {
+U_BOOT_PHY_DRIVER(m88e1118r) = {
        .name = "Marvell 88E1118R",
-       .uid = 0x1410e40,
-       .mask = 0xffffff0,
+       .uid = MARVELL_PHY_ID_88E1116R,
+       .mask = MARVELL_PHY_ID_MASK,
        .features = PHY_GBIT_FEATURES,
        .config = &m88e1118_config,
        .startup = &m88e1118_startup,
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver M88E1121R_driver = {
+U_BOOT_PHY_DRIVER(m88e1121r) = {
        .name = "Marvell 88E1121R",
-       .uid = 0x1410cb0,
-       .mask = 0xffffff0,
+       .uid = MARVELL_PHY_ID_88E1121R,
+       .mask = MARVELL_PHY_ID_MASK,
        .features = PHY_GBIT_FEATURES,
        .config = &m88e1121_config,
        .startup = &genphy_startup,
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver M88E1145_driver = {
+U_BOOT_PHY_DRIVER(m88e1145) = {
        .name = "Marvell 88E1145",
-       .uid = 0x1410cd0,
-       .mask = 0xffffff0,
+       .uid = MARVELL_PHY_ID_88E1145,
+       .mask = MARVELL_PHY_ID_MASK,
        .features = PHY_GBIT_FEATURES,
        .config = &m88e1145_config,
        .startup = &m88e1145_startup,
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver M88E1149S_driver = {
+U_BOOT_PHY_DRIVER(m88e1149s) = {
        .name = "Marvell 88E1149S",
-       .uid = 0x1410ca0,
-       .mask = 0xffffff0,
+       .uid = 0x01410ca0,
+       .mask = MARVELL_PHY_ID_MASK,
        .features = PHY_GBIT_FEATURES,
        .config = &m88e1149_config,
        .startup = &m88e1011s_startup,
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver M88E1240_driver = {
+U_BOOT_PHY_DRIVER(m88e1240) = {
        .name = "Marvell 88E1240",
-       .uid = 0x1410e30,
-       .mask = 0xffffff0,
+       .uid = MARVELL_PHY_ID_88E1240,
+       .mask = MARVELL_PHY_ID_MASK,
        .features = PHY_GBIT_FEATURES,
        .config = &m88e1240_config,
        .startup = &m88e1011s_startup,
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver M88E151x_driver = {
+U_BOOT_PHY_DRIVER(m88e151x) = {
        .name = "Marvell 88E151x",
-       .uid = 0x1410dd0,
-       .mask = 0xffffff0,
+       .uid = MARVELL_PHY_ID_88E1510,
+       .mask = MARVELL_PHY_ID_MASK,
        .features = PHY_GBIT_FEATURES,
        .config = &m88e151x_config,
        .startup = &m88e1011s_startup,
@@ -785,39 +786,22 @@ static struct phy_driver M88E151x_driver = {
        .writeext = &m88e1xxx_phy_extwrite,
 };
 
-static struct phy_driver M88E1310_driver = {
+U_BOOT_PHY_DRIVER(m88e1310) = {
        .name = "Marvell 88E1310",
-       .uid = 0x01410e90,
-       .mask = 0xffffff0,
+       .uid = MARVELL_PHY_ID_88E1318S,
+       .mask = MARVELL_PHY_ID_MASK,
        .features = PHY_GBIT_FEATURES,
        .config = &m88e1310_config,
        .startup = &m88e1011s_startup,
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver M88E1680_driver = {
+U_BOOT_PHY_DRIVER(m88e1680) = {
        .name = "Marvell 88E1680",
-       .uid = 0x1410ed0,
-       .mask = 0xffffff0,
+       .uid = 0x01410ed0,
+       .mask = MARVELL_PHY_ID_MASK,
        .features = PHY_GBIT_FEATURES,
        .config = &m88e1680_config,
        .startup = &genphy_startup,
        .shutdown = &genphy_shutdown,
 };
-
-int phy_marvell_init(void)
-{
-       phy_register(&M88E1310_driver);
-       phy_register(&M88E1149S_driver);
-       phy_register(&M88E1145_driver);
-       phy_register(&M88E1121R_driver);
-       phy_register(&M88E1118_driver);
-       phy_register(&M88E1118R_driver);
-       phy_register(&M88E1111S_driver);
-       phy_register(&M88E1011S_driver);
-       phy_register(&M88E1240_driver);
-       phy_register(&M88E151x_driver);
-       phy_register(&M88E1680_driver);
-
-       return 0;
-}

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
new file mode 100644 (file)
index 0000000..9e64672
--- /dev/null
+++ b/drivers/net/phy/marvell10g.c
@@ -0,0 +1,605 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Marvell 10G 88x3310 PHY driver
+ *
+ * Based upon the ID registers, this PHY appears to be a mixture of IPs
+ * from two different companies.
+ *
+ * There appears to be several different data paths through the PHY which
+ * are automatically managed by the PHY.  The following has been determined
+ * via observation and experimentation for a setup using single-lane Serdes:
+ *
+ *       SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
+ *  10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
+ *  10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
+ *
+ * With XAUI, observation shows:
+ *
+ *        XAUI PHYXS -- <appropriate PCS as above>
+ *
+ * and no switching of the host interface mode occurs.
+ *
+ * If both the fiber and copper ports are connected, the first to gain
+ * link takes priority and the other port is completely locked out.
+ */
+#include <common.h>
+#include <console.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <errno.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include <marvell_phy.h>
+#include <phy.h>
+
+#define MV_PHY_ALASKA_NBT_QUIRK_MASK   0xfffffffe
+#define MV_PHY_ALASKA_NBT_QUIRK_REV    (MARVELL_PHY_ID_88X3310 | 0xa)
+
+#define MV_VERSION(a, b, c, d) ((a) << 24 | (b) << 16 | (c) << 8 | (d))
+
+enum {
+       MV_PMA_FW_VER0          = 0xc011,
+       MV_PMA_FW_VER1          = 0xc012,
+       MV_PMA_21X0_PORT_CTRL   = 0xc04a,
+       MV_PMA_21X0_PORT_CTRL_SWRST                             = BIT(15),
+       MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK                      = 0x7,
+       MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII                   = 0x0,
+       MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII                    = 0x1,
+       MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII                    = 0x2,
+       MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER                   = 0x4,
+       MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN       = 0x5,
+       MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH       = 0x6,
+       MV_PMA_BOOT             = 0xc050,
+       MV_PMA_BOOT_FATAL       = BIT(0),
+
+       MV_PCS_BASE_T           = 0x0000,
+       MV_PCS_BASE_R           = 0x1000,
+       MV_PCS_1000BASEX        = 0x2000,
+
+       MV_PCS_CSCR1            = 0x8000,
+       MV_PCS_CSCR1_ED_MASK    = 0x0300,
+       MV_PCS_CSCR1_ED_OFF     = 0x0000,
+       MV_PCS_CSCR1_ED_RX      = 0x0200,
+       MV_PCS_CSCR1_ED_NLP     = 0x0300,
+       MV_PCS_CSCR1_MDIX_MASK  = 0x0060,
+       MV_PCS_CSCR1_MDIX_MDI   = 0x0000,
+       MV_PCS_CSCR1_MDIX_MDIX  = 0x0020,
+       MV_PCS_CSCR1_MDIX_AUTO  = 0x0060,
+
+       MV_PCS_DSC1             = 0x8003,
+       MV_PCS_DSC1_ENABLE      = BIT(9),
+       MV_PCS_DSC1_10GBT       = 0x01c0,
+       MV_PCS_DSC1_1GBR        = 0x0038,
+       MV_PCS_DSC1_100BTX      = 0x0007,
+       MV_PCS_DSC2             = 0x8004,
+       MV_PCS_DSC2_2P5G        = 0xf000,
+       MV_PCS_DSC2_5G          = 0x0f00,
+
+       MV_PCS_CSSR1            = 0x8008,
+       MV_PCS_CSSR1_SPD1_MASK  = 0xc000,
+       MV_PCS_CSSR1_SPD1_SPD2  = 0xc000,
+       MV_PCS_CSSR1_SPD1_1000  = 0x8000,
+       MV_PCS_CSSR1_SPD1_100   = 0x4000,
+       MV_PCS_CSSR1_SPD1_10    = 0x0000,
+       MV_PCS_CSSR1_DUPLEX_FULL = BIT(13),
+       MV_PCS_CSSR1_RESOLVED   = BIT(11),
+       MV_PCS_CSSR1_MDIX       = BIT(6),
+       MV_PCS_CSSR1_SPD2_MASK  = 0x000c,
+       MV_PCS_CSSR1_SPD2_5000  = 0x0008,
+       MV_PCS_CSSR1_SPD2_2500  = 0x0004,
+       MV_PCS_CSSR1_SPD2_10000 = 0x0000,
+
+       /* Temperature read register (88E2110 only) */
+       MV_PCS_TEMP             = 0x8042,
+
+       /* Number of ports on the device */
+       MV_PCS_PORT_INFO        = 0xd00d,
+       MV_PCS_PORT_INFO_NPORTS_MASK    = 0x0380,
+       MV_PCS_PORT_INFO_NPORTS_SHIFT   = 7,
+
+       /* SerDes reinitialization 88E21X0 */
+       MV_AN_21X0_SERDES_CTRL2 = 0x800f,
+       MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS   = BIT(13),
+       MV_AN_21X0_SERDES_CTRL2_RUN_INIT        = BIT(15),
+
+       /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
+        * registers appear to set themselves to the 0x800X when AN is
+        * restarted, but status registers appear readable from either.
+        */
+       MV_AN_CTRL1000          = 0x8000, /* 1000base-T control register */
+       MV_AN_STAT1000          = 0x8001, /* 1000base-T status register */
+
+       /* Vendor2 MMD registers */
+       MV_V2_PORT_CTRL         = 0xf001,
+       MV_V2_PORT_CTRL_PWRDOWN                                 = BIT(11),
+       MV_V2_33X0_PORT_CTRL_SWRST                              = BIT(15),
+       MV_V2_33X0_PORT_CTRL_MACTYPE_MASK                       = 0x7,
+       MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI                      = 0x0,
+       MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH            = 0x1,
+       MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN          = 0x1,
+       MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH           = 0x2,
+       MV_V2_3310_PORT_CTRL_MACTYPE_XAUI                       = 0x3,
+       MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER                   = 0x4,
+       MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN       = 0x5,
+       MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH        = 0x6,
+       MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII                    = 0x7,
+       MV_V2_PORT_INTR_STS             = 0xf040,
+       MV_V2_PORT_INTR_MASK            = 0xf043,
+       MV_V2_PORT_INTR_STS_WOL_EN      = BIT(8),
+       MV_V2_MAGIC_PKT_WORD0           = 0xf06b,
+       MV_V2_MAGIC_PKT_WORD1           = 0xf06c,
+       MV_V2_MAGIC_PKT_WORD2           = 0xf06d,
+       /* Wake on LAN registers */
+       MV_V2_WOL_CTRL                  = 0xf06e,
+       MV_V2_WOL_CTRL_CLEAR_STS        = BIT(15),
+       MV_V2_WOL_CTRL_MAGIC_PKT_EN     = BIT(0),
+       /* Temperature control/read registers (88X3310 only) */
+       MV_V2_TEMP_CTRL         = 0xf08a,
+       MV_V2_TEMP_CTRL_MASK    = 0xc000,
+       MV_V2_TEMP_CTRL_SAMPLE  = 0x0000,
+       MV_V2_TEMP_CTRL_DISABLE = 0xc000,
+       MV_V2_TEMP              = 0xf08c,
+       MV_V2_TEMP_UNKNOWN      = 0x9600, /* unknown function */
+};
+
+struct mv3310_chip {
+       bool (*has_downshift)(struct phy_device *phydev);
+       int (*test_supported_interfaces)(struct phy_device *phydev);
+       int (*get_mactype)(struct phy_device *phydev);
+       int (*set_mactype)(struct phy_device *phydev, int mactype);
+       int (*select_mactype)(struct phy_device *phydev);
+       int (*init_interface)(struct phy_device *phydev, int mactype);
+};
+
+struct mv3310_priv {
+       DECLARE_BITMAP(supported_interfaces, PHY_INTERFACE_MODE_MAX);
+
+       u32 firmware_ver;
+       bool has_downshift;
+       bool rate_match;
+};
+
+static const struct mv3310_chip *to_mv3310_chip(struct phy_device *phydev)
+{
+       return (const struct mv3310_chip *)phydev->drv->data;
+}
+
+static int mv3310_power_down(struct phy_device *phydev)
+{
+       return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
+                               MV_V2_PORT_CTRL_PWRDOWN);
+}
+
+static int mv3310_power_up(struct phy_device *phydev)
+{
+       struct mv3310_priv *priv = (struct mv3310_priv *)phydev->priv;
+       int ret;
+
+       ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
+                                MV_V2_PORT_CTRL_PWRDOWN);
+
+       if (phydev->drv->uid != MARVELL_PHY_ID_88X3310 ||
+           priv->firmware_ver < 0x00030000)
+               return ret;
+
+       return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
+                               MV_V2_33X0_PORT_CTRL_SWRST);
+}
+
+static int mv3310_reset(struct phy_device *phydev, u32 unit)
+{
+       int val, err;
+
+       err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
+                            MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
+       if (err < 0)
+               return err;
+
+       return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS,
+                                        unit + MDIO_CTRL1, val,
+                                        !(val & MDIO_CTRL1_RESET),
+                                        5000, 100000, true);
+}
+
+static int mv3310_set_downshift(struct phy_device *phydev)
+{
+       struct mv3310_priv *priv = (struct mv3310_priv *)phydev->priv;
+       const u8 ds = 1;
+       u16 val;
+       int err;
+
+       if (!priv->has_downshift)
+               return -EOPNOTSUPP;
+
+       val = FIELD_PREP(MV_PCS_DSC2_2P5G, ds);
+       val |= FIELD_PREP(MV_PCS_DSC2_5G, ds);
+       err = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC2,
+                            MV_PCS_DSC2_2P5G | MV_PCS_DSC2_5G, val);
+       if (err < 0)
+               return err;
+
+       val = MV_PCS_DSC1_ENABLE;
+       val |= FIELD_PREP(MV_PCS_DSC1_10GBT, ds);
+       val |= FIELD_PREP(MV_PCS_DSC1_1GBR, ds);
+       val |= FIELD_PREP(MV_PCS_DSC1_100BTX, ds);
+
+       return phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
+                             MV_PCS_DSC1_ENABLE | MV_PCS_DSC1_10GBT |
+                             MV_PCS_DSC1_1GBR | MV_PCS_DSC1_100BTX, val);
+}
+
+static int mv3310_set_edpd(struct phy_device *phydev)
+{
+       int err;
+
+       err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
+                                    MV_PCS_CSCR1_ED_MASK,
+                                    MV_PCS_CSCR1_ED_NLP);
+       if (err > 0)
+               err = mv3310_reset(phydev, MV_PCS_BASE_T);
+
+       return err;
+}
+
+static int mv3310_probe(struct phy_device *phydev)
+{
+       const struct mv3310_chip *chip = to_mv3310_chip(phydev);
+       struct mv3310_priv *priv;
+       u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
+       int ret;
+
+       if (!phydev->is_c45 ||
+           (phydev->mmds & mmd_mask) != mmd_mask)
+               return -ENODEV;
+
+       ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
+       if (ret < 0)
+               return ret;
+
+       if (ret & MV_PMA_BOOT_FATAL) {
+               dev_warn(phydev->dev,
+                        "PHY failed to boot firmware, status=%04x\n", ret);
+               return -ENODEV;
+       }
+
+       priv = devm_kzalloc(phydev->dev, sizeof(*priv), GFP_KERNEL);
+       if (!priv)
+               return -ENOMEM;
+
+       phydev->priv = priv;
+
+       ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0);
+       if (ret < 0)
+               return ret;
+
+       priv->firmware_ver = ret << 16;
+
+       ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1);
+       if (ret < 0)
+               return ret;
+
+       priv->firmware_ver |= ret;
+
+       dev_info(phydev->dev, "Firmware version %u.%u.%u.%u\n",
+                priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255,
+                (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255);
+
+       if (chip->has_downshift)
+               priv->has_downshift = chip->has_downshift(phydev);
+
+       /* Powering down the port when not in use saves about 600mW */
+       ret = mv3310_power_down(phydev);
+       if (ret)
+               return ret;
+
+       return 0;
+}
+
+static int mv2110_get_mactype(struct phy_device *phydev)
+{
+       int mactype;
+
+       mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL);
+       if (mactype < 0)
+               return mactype;
+
+       return mactype & MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
+}
+
+static int mv2110_set_mactype(struct phy_device *phydev, int mactype)
+{
+       int err, val;
+
+       mactype &= MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
+       err = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL,
+                            MV_PMA_21X0_PORT_CTRL_SWRST |
+                            MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK,
+                            MV_PMA_21X0_PORT_CTRL_SWRST | mactype);
+       if (err)
+               return err;
+
+       err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
+                              MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS |
+                              MV_AN_21X0_SERDES_CTRL2_RUN_INIT);
+       if (err)
+               return err;
+
+       err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_AN,
+                                       MV_AN_21X0_SERDES_CTRL2, val,
+                                       !(val &
+                                         MV_AN_21X0_SERDES_CTRL2_RUN_INIT),
+                                       5000, 100000, true);
+       if (err)
+               return err;
+
+       return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
+                                 MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS);
+}
+
+static int mv2110_select_mactype(struct phy_device *phydev)
+{
+       if (phydev->interface == PHY_INTERFACE_MODE_USXGMII)
+               return MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII;
+       else if (phydev->interface == PHY_INTERFACE_MODE_SGMII &&
+                !(phydev->interface == PHY_INTERFACE_MODE_10GBASER))
+               return MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER;
+       else if (phydev->interface == PHY_INTERFACE_MODE_10GBASER)
+               return MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH;
+       else
+               return -1;
+}
+
+static int mv3310_get_mactype(struct phy_device *phydev)
+{
+       int mactype;
+
+       mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
+       if (mactype < 0)
+               return mactype;
+
+       return mactype & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
+}
+
+static int mv3310_set_mactype(struct phy_device *phydev, int mactype)
+{
+       int ret;
+
+       mactype &= MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
+       ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
+                                    MV_V2_33X0_PORT_CTRL_MACTYPE_MASK,
+                                    mactype);
+       if (ret <= 0)
+               return ret;
+
+       return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
+                               MV_V2_33X0_PORT_CTRL_SWRST);
+}
+
+static int mv3310_select_mactype(struct phy_device *phydev)
+{
+       if (phydev->interface == PHY_INTERFACE_MODE_USXGMII)
+               return MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII;
+       else if (phydev->interface == PHY_INTERFACE_MODE_SGMII &&
+                phydev->interface == PHY_INTERFACE_MODE_10GBASER)
+               return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER;
+       else if (phydev->interface == PHY_INTERFACE_MODE_SGMII &&
+                phydev->interface == PHY_INTERFACE_MODE_RXAUI)
+               return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI;
+       else if (phydev->interface == PHY_INTERFACE_MODE_SGMII &&
+                phydev->interface == PHY_INTERFACE_MODE_XAUI)
+               return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI;
+       else if (phydev->interface == PHY_INTERFACE_MODE_10GBASER)
+               return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH;
+       else if (phydev->interface == PHY_INTERFACE_MODE_RXAUI)
+               return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH;
+       else if (phydev->interface == PHY_INTERFACE_MODE_XAUI)
+               return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH;
+       else if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
+               return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER;
+       else
+               return -1;
+}
+
+static int mv2110_init_interface(struct phy_device *phydev, int mactype)
+{
+       struct mv3310_priv *priv = (struct mv3310_priv *)phydev->priv;
+
+       priv->rate_match = false;
+
+       if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
+               priv->rate_match = true;
+
+       return 0;
+}
+
+static int mv3310_init_interface(struct phy_device *phydev, int mactype)
+{
+       struct mv3310_priv *priv = (struct mv3310_priv *)phydev->priv;
+
+       priv->rate_match = false;
+
+       if (mactype != MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN)
+               return 0;
+
+       if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
+           mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
+           mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)
+               priv->rate_match = true;
+
+       return 0;
+}
+
+static int mv3310_config_init(struct phy_device *phydev)
+{
+       const struct mv3310_chip *chip = to_mv3310_chip(phydev);
+       int err, mactype;
+
+       /* Check that the PHY interface type is compatible */
+       err = chip->test_supported_interfaces(phydev);
+       if (err)
+               return err;
+
+       /* Power up so reset works */
+       err = mv3310_power_up(phydev);
+       if (err)
+               return err;
+
+       /* If host provided host supported interface modes, try to select the
+        * best one
+        */
+       mactype = chip->select_mactype(phydev);
+       if (mactype >= 0) {
+               dev_info(phydev->dev, "Changing MACTYPE to %i\n",
+                        mactype);
+               err = chip->set_mactype(phydev, mactype);
+               if (err)
+                       return err;
+       }
+
+       mactype = chip->get_mactype(phydev);
+       if (mactype < 0)
+               return mactype;
+
+       err = chip->init_interface(phydev, mactype);
+       if (err) {
+               dev_err(phydev->dev, "MACTYPE configuration invalid\n");
+               return err;
+       }
+
+       /* Enable EDPD mode - saving 600mW */
+       err = mv3310_set_edpd(phydev);
+       if (err)
+               return err;
+
+       /* Allow downshift */
+       err = mv3310_set_downshift(phydev);
+       if (err && err != -EOPNOTSUPP)
+               return err;
+
+       return 0;
+}
+
+static int mv3310_config(struct phy_device *phydev)
+{
+       int err;
+
+       err = mv3310_probe(phydev);
+       if (!err)
+               err = mv3310_config_init(phydev);
+
+       return err;
+}
+
+static int mv3310_get_number_of_ports(struct phy_device *phydev)
+{
+       int ret;
+
+       ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PORT_INFO);
+       if (ret < 0)
+               return ret;
+
+       ret &= MV_PCS_PORT_INFO_NPORTS_MASK;
+       ret >>= MV_PCS_PORT_INFO_NPORTS_SHIFT;
+
+       return ret + 1;
+}
+
+static int mv3310_match_phy_device(struct phy_device *phydev)
+{
+       if ((phydev->phy_id & MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310)
+               return 0;
+
+       return mv3310_get_number_of_ports(phydev) == 1;
+}
+
+static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g)
+{
+       int val;
+
+       if ((phydev->phy_id & MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88E2110)
+               return 0;
+
+       val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED);
+       if (val < 0)
+               return val;
+
+       return !!(val & MDIO_PCS_SPEED_5G) == has_5g;
+}
+
+static int mv2110_match_phy_device(struct phy_device *phydev)
+{
+       return mv211x_match_phy_device(phydev, true);
+}
+
+static bool mv3310_has_downshift(struct phy_device *phydev)
+{
+       struct mv3310_priv *priv = (struct mv3310_priv *)phydev->priv;
+
+       /* Fails to downshift with firmware older than v0.3.5.0 */
+       return priv->firmware_ver >= MV_VERSION(0, 3, 5, 0);
+}
+
+#define mv_test_bit(iface, phydev)     \
+       ({ if ((phydev)->interface & (iface)) return 0; })
+
+static int mv3310_mv3340_test_supported_interfaces(struct phy_device *phydev)
+{
+       mv_test_bit(PHY_INTERFACE_MODE_SGMII, phydev);
+       mv_test_bit(PHY_INTERFACE_MODE_2500BASEX, phydev);
+       mv_test_bit(PHY_INTERFACE_MODE_5GBASER, phydev);
+       if (mv3310_match_phy_device(phydev))
+               mv_test_bit(PHY_INTERFACE_MODE_XAUI, phydev);
+       mv_test_bit(PHY_INTERFACE_MODE_RXAUI, phydev);
+       mv_test_bit(PHY_INTERFACE_MODE_10GBASER, phydev);
+       mv_test_bit(PHY_INTERFACE_MODE_USXGMII, phydev);
+       return -ENODEV;
+}
+
+static int mv2110_mv2111_test_supported_interfaces(struct phy_device *phydev)
+{
+       mv_test_bit(PHY_INTERFACE_MODE_SGMII, phydev);
+       mv_test_bit(PHY_INTERFACE_MODE_2500BASEX, phydev);
+       if (mv2110_match_phy_device(phydev))
+               mv_test_bit(PHY_INTERFACE_MODE_5GBASER, phydev);
+       mv_test_bit(PHY_INTERFACE_MODE_10GBASER, phydev);
+       mv_test_bit(PHY_INTERFACE_MODE_USXGMII, phydev);
+       return -ENODEV;
+}
+
+static const struct mv3310_chip mv3310_mv3340_type = {
+       .has_downshift = mv3310_has_downshift,
+       .test_supported_interfaces = mv3310_mv3340_test_supported_interfaces,
+       .get_mactype = mv3310_get_mactype,
+       .set_mactype = mv3310_set_mactype,
+       .select_mactype = mv3310_select_mactype,
+       .init_interface = mv3310_init_interface,
+};
+
+static const struct mv3310_chip mv2110_mv2111_type = {
+       .test_supported_interfaces = mv2110_mv2111_test_supported_interfaces,
+       .get_mactype = mv2110_get_mactype,
+       .set_mactype = mv2110_set_mactype,
+       .select_mactype = mv2110_select_mactype,
+       .init_interface = mv2110_init_interface,
+};
+
+U_BOOT_PHY_DRIVER(mv88e3310_mv88e3340) = {
+       .name           = "mv88x3310",
+       .uid            = MARVELL_PHY_ID_88X3310,
+       .mask           = MARVELL_PHY_ID_MASK,
+       .features       = PHY_10G_FEATURES,
+       .data           = (ulong)&mv3310_mv3340_type,
+       .config         = mv3310_config,
+};
+
+U_BOOT_PHY_DRIVER(mv88e2110_mv88e2111) = {
+       .name           = "mv88e2110",
+       .uid            = MARVELL_PHY_ID_88E2110,
+       .mask           = MARVELL_PHY_ID_MASK,
+       .features       = PHY_10G_FEATURES,
+       .data           = (ulong)&mv2110_mv2111_type,
+       .config         = mv3310_config,
+};

diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c
index 753ca72..b49c9b5 100644 (file)
--- a/drivers/net/phy/meson-gxl.c
+++ b/drivers/net/phy/meson-gxl.c
@@ -124,7 +124,7 @@ static int meson_gxl_phy_config(struct phy_device *phydev)
        return genphy_config(phydev);
 }
 
-static struct phy_driver meson_gxl_phy_driver = {
+U_BOOT_PHY_DRIVER(meson_gxl_phy) = {
        .name = "Meson GXL Internal PHY",
        .uid = 0x01814400,
        .mask = 0xfffffff0,
@@ -133,10 +133,3 @@ static struct phy_driver meson_gxl_phy_driver = {
        .startup = &meson_gxl_startup,
        .shutdown = &genphy_shutdown,
 };
-
-int phy_meson_gxl_init(void)
-{
-       phy_register(&meson_gxl_phy_driver);
-
-       return 0;
-}

diff --git a/drivers/net/phy/micrel_ksz8xxx.c b/drivers/net/phy/micrel_ksz8xxx.c
index 60d42fe..b0f3abc 100644 (file)
--- a/drivers/net/phy/micrel_ksz8xxx.c
+++ b/drivers/net/phy/micrel_ksz8xxx.c
@@ -14,7 +14,7 @@
 #include <phy.h>
 #include <linux/bitops.h>
 
-static struct phy_driver KSZ804_driver = {
+U_BOOT_PHY_DRIVER(ksz804) = {
        .name = "Micrel KSZ804",
        .uid = 0x221510,
        .mask = 0xfffff0,
@@ -44,7 +44,7 @@ static int ksz_genconfig_bcastoff(struct phy_device *phydev)
        return genphy_config(phydev);
 }
 
-static struct phy_driver KSZ8031_driver = {
+U_BOOT_PHY_DRIVER(ksz8031) = {
        .name = "Micrel KSZ8021/KSZ8031",
        .uid = 0x221550,
        .mask = 0xfffff0,
@@ -72,7 +72,7 @@ static int ksz8051_config(struct phy_device *phydev)
        return genphy_config(phydev);
 }
 
-static struct phy_driver KSZ8051_driver = {
+U_BOOT_PHY_DRIVER(ksz8051) = {
        .name = "Micrel KSZ8051",
        .uid = 0x221550,
        .mask = 0xfffff0,
@@ -87,7 +87,7 @@ static int ksz8061_config(struct phy_device *phydev)
        return phy_write(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
 }
 
-static struct phy_driver KSZ8061_driver = {
+U_BOOT_PHY_DRIVER(ksz8061) = {
        .name = "Micrel KSZ8061",
        .uid = 0x00221570,
        .mask = 0xfffff0,
@@ -115,7 +115,7 @@ static int ksz8081_config(struct phy_device *phydev)
        return genphy_config(phydev);
 }
 
-static struct phy_driver KSZ8081_driver = {
+U_BOOT_PHY_DRIVER(ksz8081) = {
        .name = "Micrel KSZ8081",
        .uid = 0x221560,
        .mask = 0xfffff0,
@@ -172,7 +172,7 @@ static int ksz8895_startup(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver ksz8895_driver = {
+U_BOOT_PHY_DRIVER(ksz8895) = {
        .name = "Micrel KSZ8895/KSZ8864",
        .uid  = 0x221450,
        .mask = 0xffffe1,
@@ -185,7 +185,7 @@ static struct phy_driver ksz8895_driver = {
 /* Micrel used the exact same model number for the KSZ9021,
  * so the revision number is used to distinguish them.
  */
-static struct phy_driver KS8721_driver = {
+U_BOOT_PHY_DRIVER(ks8721) = {
        .name = "Micrel KS8721BL",
        .uid = 0x221618,
        .mask = 0xfffffc,
@@ -210,7 +210,7 @@ static int ksz886x_startup(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver ksz886x_driver = {
+U_BOOT_PHY_DRIVER(ksz886x) = {
        .name = "Micrel KSZ886x Switch",
        .uid  = 0x00221430,
        .mask = 0xfffff0,
@@ -219,16 +219,3 @@ static struct phy_driver ksz886x_driver = {
        .startup = &ksz886x_startup,
        .shutdown = &genphy_shutdown,
 };
-
-int phy_micrel_ksz8xxx_init(void)
-{
-       phy_register(&KSZ804_driver);
-       phy_register(&KSZ8031_driver);
-       phy_register(&KSZ8051_driver);
-       phy_register(&KSZ8061_driver);
-       phy_register(&KSZ8081_driver);
-       phy_register(&KS8721_driver);
-       phy_register(&ksz8895_driver);
-       phy_register(&ksz886x_driver);
-       return 0;
-}

diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c
index 79ebdb5..ffc3c98 100644 (file)
--- a/drivers/net/phy/micrel_ksz90x1.c
+++ b/drivers/net/phy/micrel_ksz90x1.c
@@ -270,7 +270,7 @@ static int ksz9021_config(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver ksz9021_driver = {
+U_BOOT_PHY_DRIVER(ksz9021) = {
        .name = "Micrel ksz9021",
        .uid  = 0x221610,
        .mask = 0xfffffe,
@@ -368,7 +368,7 @@ static int ksz9031_config(struct phy_device *phydev)
        return genphy_config(phydev);
 }
 
-static struct phy_driver ksz9031_driver = {
+U_BOOT_PHY_DRIVER(ksz9031) = {
        .name = "Micrel ksz9031",
        .uid  = PHY_ID_KSZ9031,
        .mask = MII_KSZ9x31_SILICON_REV_MASK,
@@ -477,7 +477,7 @@ static int ksz9131_config(struct phy_device *phydev)
        return genphy_config(phydev);
 }
 
-static struct phy_driver ksz9131_driver = {
+U_BOOT_PHY_DRIVER(ksz9131) = {
        .name = "Micrel ksz9131",
        .uid  = PHY_ID_KSZ9131,
        .mask = MII_KSZ9x31_SILICON_REV_MASK,
@@ -497,11 +497,3 @@ int ksz9xx1_phy_get_id(struct phy_device *phydev)
 
        return phyid;
 }
-
-int phy_micrel_ksz90x1_init(void)
-{
-       phy_register(&ksz9021_driver);
-       phy_register(&ksz9031_driver);
-       phy_register(&ksz9131_driver);
-       return 0;
-}

diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index f9482b2..ef1761a 100644 (file)
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -1558,7 +1558,7 @@ static int vsc8502_config(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver VSC8530_driver = {
+U_BOOT_PHY_DRIVER(vsc8530) = {
        .name = "Microsemi VSC8530",
        .uid = PHY_ID_VSC8530,
        .mask = 0x000ffff0,
@@ -1568,7 +1568,7 @@ static struct phy_driver VSC8530_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver VSC8531_driver = {
+U_BOOT_PHY_DRIVER(vsc8531) = {
        .name = "Microsemi VSC8531",
        .uid = PHY_ID_VSC8531,
        .mask = 0x000ffff0,
@@ -1578,7 +1578,7 @@ static struct phy_driver VSC8531_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver VSC8502_driver = {
+U_BOOT_PHY_DRIVER(vsc8502) = {
        .name = "Microsemi VSC8502",
        .uid = PHY_ID_VSC8502,
        .mask = 0x000ffff0,
@@ -1588,7 +1588,7 @@ static struct phy_driver VSC8502_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver VSC8540_driver = {
+U_BOOT_PHY_DRIVER(vsc8540) = {
        .name = "Microsemi VSC8540",
        .uid = PHY_ID_VSC8540,
        .mask = 0x000ffff0,
@@ -1598,7 +1598,7 @@ static struct phy_driver VSC8540_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver VSC8541_driver = {
+U_BOOT_PHY_DRIVER(vsc8541) = {
        .name = "Microsemi VSC8541",
        .uid = PHY_ID_VSC8541,
        .mask = 0x000ffff0,
@@ -1608,7 +1608,7 @@ static struct phy_driver VSC8541_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver VSC8574_driver = {
+U_BOOT_PHY_DRIVER(vsc8574) = {
        .name = "Microsemi VSC8574",
        .uid = PHY_ID_VSC8574,
        .mask = 0x000ffff0,
@@ -1618,7 +1618,7 @@ static struct phy_driver VSC8574_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver VSC8584_driver = {
+U_BOOT_PHY_DRIVER(vsc8584) = {
        .name = "Microsemi VSC8584",
        .uid = PHY_ID_VSC8584,
        .mask = 0x000ffff0,
@@ -1627,16 +1627,3 @@ static struct phy_driver VSC8584_driver = {
        .startup = &mscc_startup,
        .shutdown = &genphy_shutdown,
 };
-
-int phy_mscc_init(void)
-{
-       phy_register(&VSC8530_driver);
-       phy_register(&VSC8531_driver);
-       phy_register(&VSC8502_driver);
-       phy_register(&VSC8540_driver);
-       phy_register(&VSC8541_driver);
-       phy_register(&VSC8574_driver);
-       phy_register(&VSC8584_driver);
-
-       return 0;
-}

diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c
index 7ab6016..8577810 100644 (file)
--- a/drivers/net/phy/mv88e61xx.c
+++ b/drivers/net/phy/mv88e61xx.c
@@ -1127,7 +1127,7 @@ static int mv88e61xx_phy_startup(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver mv88e61xx_driver = {
+U_BOOT_PHY_DRIVER(mv88e61xx) = {
        .name = "Marvell MV88E61xx",
        .uid = 0x01410eb1,
        .mask = 0xfffffff0,
@@ -1138,7 +1138,7 @@ static struct phy_driver mv88e61xx_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver mv88e609x_driver = {
+U_BOOT_PHY_DRIVER(mv88e609x) = {
        .name = "Marvell MV88E609x",
        .uid = 0x1410c89,
        .mask = 0xfffffff0,
@@ -1149,7 +1149,7 @@ static struct phy_driver mv88e609x_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver mv88e6071_driver = {
+U_BOOT_PHY_DRIVER(mv88e6071) = {
        .name = "Marvell MV88E6071",
        .uid = 0x1410db0,
        .mask = 0xfffffff0,
@@ -1160,15 +1160,6 @@ static struct phy_driver mv88e6071_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-int phy_mv88e61xx_init(void)
-{
-       phy_register(&mv88e61xx_driver);
-       phy_register(&mv88e609x_driver);
-       phy_register(&mv88e6071_driver);
-
-       return 0;
-}
-
 /*
  * Overload weak get_phy_id definition since we need non-standard functions
  * to read PHY registers

diff --git a/drivers/net/phy/natsemi.c b/drivers/net/phy/natsemi.c
index efde457..6b9e99e 100644 (file)
--- a/drivers/net/phy/natsemi.c
+++ b/drivers/net/phy/natsemi.c
@@ -33,7 +33,7 @@ static int dp83630_config(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver DP83630_driver = {
+U_BOOT_PHY_DRIVER(dp83630) = {
        .name = "NatSemi DP83630",
        .uid = 0x20005ce1,
        .mask = 0xfffffff0,
@@ -103,7 +103,7 @@ static int dp83865_startup(struct phy_device *phydev)
 }
 
 
-static struct phy_driver DP83865_driver = {
+U_BOOT_PHY_DRIVER(dp83865) = {
        .name = "NatSemi DP83865",
        .uid = 0x20005c70,
        .mask = 0xfffffff0,
@@ -146,7 +146,7 @@ static int dp83848_startup(struct phy_device *phydev)
        return dp83848_parse_status(phydev);
 }
 
-static struct phy_driver DP83848_driver = {
+U_BOOT_PHY_DRIVER(dp83848) = {
        .name = "NatSemi DP83848",
        .uid = 0x20005c90,
        .mask = 0x2000ff90,
@@ -155,12 +155,3 @@ static struct phy_driver DP83848_driver = {
        .startup = &dp83848_startup,
        .shutdown = &genphy_shutdown,
 };
-
-int phy_natsemi_init(void)
-{
-       phy_register(&DP83630_driver);
-       phy_register(&DP83865_driver);
-       phy_register(&DP83848_driver);
-
-       return 0;
-}

diff --git a/drivers/net/phy/ncsi.c b/drivers/net/phy/ncsi.c
index bb7eceb..eb3fd65 100644 (file)
--- a/drivers/net/phy/ncsi.c
+++ b/drivers/net/phy/ncsi.c
@@ -881,7 +881,7 @@ int ncsi_shutdown(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver ncsi_driver = {
+U_BOOT_PHY_DRIVER(ncsi) = {
        .uid            = PHY_NCSI_ID,
        .mask           = 0xffffffff,
        .name           = "NC-SI",
@@ -891,9 +891,3 @@ static struct phy_driver ncsi_driver = {
        .startup        = ncsi_startup,
        .shutdown       = ncsi_shutdown,
 };
-
-int phy_ncsi_init(void)
-{
-       phy_register(&ncsi_driver);
-       return 0;
-}

diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c
index a0f41fa..f701790 100644 (file)
--- a/drivers/net/phy/nxp-c45-tja11xx.c
+++ b/drivers/net/phy/nxp-c45-tja11xx.c
@@ -330,7 +330,7 @@ static int nxp_c45_probe(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver nxp_c45_tja11xx = {
+U_BOOT_PHY_DRIVER(nxp_c45_tja11xx) = {
        .name = "NXP C45 TJA1103",
        .uid  = PHY_ID_TJA_1103,
        .mask = 0xfffff0,
@@ -340,9 +340,3 @@ static struct phy_driver nxp_c45_tja11xx = {
        .startup = &nxp_c45_startup,
        .shutdown = &genphy_shutdown,
 };
-
-int phy_nxp_c45_tja11xx_init(void)
-{
-       phy_register(&nxp_c45_tja11xx);
-       return 0;
-}

diff --git a/drivers/net/phy/nxp-tja11xx.c b/drivers/net/phy/nxp-tja11xx.c
index 30dec5e..471b0e3 100644 (file)
--- a/drivers/net/phy/nxp-tja11xx.c
+++ b/drivers/net/phy/nxp-tja11xx.c
@@ -248,7 +248,7 @@ static int tja11xx_startup(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver TJA1100_driver = {
+U_BOOT_PHY_DRIVER(tja1100) = {
        .name = "NXP TJA1100",
        .uid = PHY_ID_TJA1100,
        .mask = PHY_ID_MASK,
@@ -258,7 +258,7 @@ static struct phy_driver TJA1100_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver TJA1101_driver = {
+U_BOOT_PHY_DRIVER(tja1101) = {
        .name = "NXP TJA1101",
        .uid = PHY_ID_TJA1101,
        .mask = PHY_ID_MASK,
@@ -267,11 +267,3 @@ static struct phy_driver TJA1101_driver = {
        .startup = &tja11xx_startup,
        .shutdown = &genphy_shutdown,
 };
-
-int phy_nxp_tja11xx_init(void)
-{
-       phy_register(&TJA1100_driver);
-       phy_register(&TJA1101_driver);
-
-       return 0;
-}

diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 80230b9..0eeb0cb 100644 (file)
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -451,7 +451,7 @@ int genphy_shutdown(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver genphy_driver = {
+U_BOOT_PHY_DRIVER(genphy) = {
        .uid            = 0xffffffff,
        .mask           = 0xffffffff,
        .name           = "Generic PHY",
@@ -463,144 +463,36 @@ static struct phy_driver genphy_driver = {
        .shutdown       = genphy_shutdown,
 };
 
-static int genphy_init(void)
-{
-       return phy_register(&genphy_driver);
-}
-
-static LIST_HEAD(phy_drivers);
-
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
 int phy_init(void)
 {
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-       /*
-        * The pointers inside phy_drivers also needs to be updated incase of
-        * manual reloc, without which these points to some invalid
-        * pre reloc address and leads to invalid accesses, hangs.
-        */
-       struct list_head *head = &phy_drivers;
-
-       head->next = (void *)head->next + gd->reloc_off;
-       head->prev = (void *)head->prev + gd->reloc_off;
-#endif
-
-#ifdef CONFIG_B53_SWITCH
-       phy_b53_init();
-#endif
-#ifdef CONFIG_MV88E61XX_SWITCH
-       phy_mv88e61xx_init();
-#endif
-#ifdef CONFIG_PHY_ADIN
-       phy_adin_init();
-#endif
-#ifdef CONFIG_PHY_AQUANTIA
-       phy_aquantia_init();
-#endif
-#ifdef CONFIG_PHY_ATHEROS
-       phy_atheros_init();
-#endif
-#ifdef CONFIG_PHY_BROADCOM
-       phy_broadcom_init();
-#endif
-#ifdef CONFIG_PHY_CORTINA
-       phy_cortina_init();
-#endif
-#ifdef CONFIG_PHY_CORTINA_ACCESS
-       phy_cortina_access_init();
-#endif
-#ifdef CONFIG_PHY_DAVICOM
-       phy_davicom_init();
-#endif
-#ifdef CONFIG_PHY_ET1011C
-       phy_et1011c_init();
-#endif
-#ifdef CONFIG_PHY_LXT
-       phy_lxt_init();
-#endif
-#ifdef CONFIG_PHY_MARVELL
-       phy_marvell_init();
-#endif
-#ifdef CONFIG_PHY_MICREL_KSZ8XXX
-       phy_micrel_ksz8xxx_init();
-#endif
-#ifdef CONFIG_PHY_MICREL_KSZ90X1
-       phy_micrel_ksz90x1_init();
-#endif
-#ifdef CONFIG_PHY_MESON_GXL
-       phy_meson_gxl_init();
-#endif
-#ifdef CONFIG_PHY_NATSEMI
-       phy_natsemi_init();
-#endif
-#ifdef CONFIG_NXP_C45_TJA11XX_PHY
-       phy_nxp_c45_tja11xx_init();
-#endif
-#ifdef CONFIG_PHY_NXP_TJA11XX
-       phy_nxp_tja11xx_init();
-#endif
-#ifdef CONFIG_PHY_REALTEK
-       phy_realtek_init();
-#endif
-#ifdef CONFIG_PHY_SMSC
-       phy_smsc_init();
-#endif
-#ifdef CONFIG_PHY_TERANETICS
-       phy_teranetics_init();
-#endif
-#ifdef CONFIG_PHY_TI
-       phy_ti_init();
-#endif
-#ifdef CONFIG_PHY_VITESSE
-       phy_vitesse_init();
-#endif
-#ifdef CONFIG_PHY_XILINX
-       phy_xilinx_init();
-#endif
-#ifdef CONFIG_PHY_XWAY
-       phy_xway_init();
-#endif
-#ifdef CONFIG_PHY_MSCC
-       phy_mscc_init();
-#endif
-#ifdef CONFIG_PHY_FIXED
-       phy_fixed_init();
-#endif
-#ifdef CONFIG_PHY_NCSI
-       phy_ncsi_init();
-#endif
-#ifdef CONFIG_PHY_XILINX_GMII2RGMII
-       phy_xilinx_gmii2rgmii_init();
-#endif
-       genphy_init();
+       const int ll_n_ents = ll_entry_count(struct phy_driver, phy_driver);
+       struct phy_driver *drv, *ll_entry;
+
+       /* Perform manual relocation on linker list based PHY drivers */
+       ll_entry = ll_entry_start(struct phy_driver, phy_driver);
+       for (drv = ll_entry; drv != ll_entry + ll_n_ents; drv++) {
+               if (drv->probe)
+                       drv->probe += gd->reloc_off;
+               if (drv->config)
+                       drv->config += gd->reloc_off;
+               if (drv->startup)
+                       drv->startup += gd->reloc_off;
+               if (drv->shutdown)
+                       drv->shutdown += gd->reloc_off;
+               if (drv->readext)
+                       drv->readext += gd->reloc_off;
+               if (drv->writeext)
+                       drv->writeext += gd->reloc_off;
+               if (drv->read_mmd)
+                       drv->read_mmd += gd->reloc_off;
+               if (drv->write_mmd)
+                       drv->write_mmd += gd->reloc_off;
+       }
 
        return 0;
 }
-
-int phy_register(struct phy_driver *drv)
-{
-       INIT_LIST_HEAD(&drv->list);
-       list_add_tail(&drv->list, &phy_drivers);
-
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-       if (drv->probe)
-               drv->probe += gd->reloc_off;
-       if (drv->config)
-               drv->config += gd->reloc_off;
-       if (drv->startup)
-               drv->startup += gd->reloc_off;
-       if (drv->shutdown)
-               drv->shutdown += gd->reloc_off;
-       if (drv->readext)
-               drv->readext += gd->reloc_off;
-       if (drv->writeext)
-               drv->writeext += gd->reloc_off;
-       if (drv->read_mmd)
-               drv->read_mmd += gd->reloc_off;
-       if (drv->write_mmd)
-               drv->write_mmd += gd->reloc_off;
 #endif
-       return 0;
-}
 
 int phy_set_supported(struct phy_device *phydev, u32 max_speed)
 {
@@ -645,23 +537,23 @@ static struct phy_driver *generic_for_phy(struct phy_device *phydev)
 {
 #ifdef CONFIG_PHYLIB_10G
        if (phydev->is_c45)
-               return &gen10g_driver;
+               return ll_entry_get(struct phy_driver, gen10g, phy_driver);
 #endif
 
-       return &genphy_driver;
+       return ll_entry_get(struct phy_driver, genphy, phy_driver);
 }
 
 static struct phy_driver *get_phy_driver(struct phy_device *phydev)
 {
-       struct list_head *entry;
+       const int ll_n_ents = ll_entry_count(struct phy_driver, phy_driver);
        int phy_id = phydev->phy_id;
-       struct phy_driver *drv = NULL;
+       struct phy_driver *ll_entry;
+       struct phy_driver *drv;
 
-       list_for_each(entry, &phy_drivers) {
-               drv = list_entry(entry, struct phy_driver, list);
+       ll_entry = ll_entry_start(struct phy_driver, phy_driver);
+       for (drv = ll_entry; drv != ll_entry + ll_n_ents; drv++)
                if ((drv->uid & drv->mask) == (phy_id & drv->mask))
                        return drv;
-       }
 
        /* If we made it here, there's no driver for this PHY */
        return generic_for_phy(phydev);
@@ -1266,9 +1158,67 @@ int phy_clear_bits_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val
        return 0;
 }
 
+/**
+ * phy_modify_mmd_changed - Function for modifying a register on MMD
+ * @phydev: the phy_device struct
+ * @devad: the MMD containing register to modify
+ * @regnum: register number to modify
+ * @mask: bit mask of bits to clear
+ * @set: new value of bits set in mask to write to @regnum
+ *
+ * NOTE: MUST NOT be called from interrupt context,
+ * because the bus read/write functions may wait for an interrupt
+ * to conclude the operation.
+ *
+ * Returns negative errno, 0 if there was no change, and 1 in case of change
+ */
+int phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum,
+                          u16 mask, u16 set)
+{
+       int new, ret;
+
+       ret = phy_read_mmd(phydev, devad, regnum);
+       if (ret < 0)
+               return ret;
+
+       new = (ret & ~mask) | set;
+       if (new == ret)
+               return 0;
+
+       ret = phy_write_mmd(phydev, devad, regnum, new);
+
+       return ret < 0 ? ret : 1;
+}
+
+/**
+ * phy_modify_mmd - Convenience function for modifying a register on MMD
+ * @phydev: the phy_device struct
+ * @devad: the MMD containing register to modify
+ * @regnum: register number to modify
+ * @mask: bit mask of bits to clear
+ * @set: new value of bits set in mask to write to @regnum
+ *
+ * NOTE: MUST NOT be called from interrupt context,
+ * because the bus read/write functions may wait for an interrupt
+ * to conclude the operation.
+ */
+int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
+                  u16 mask, u16 set)
+{
+       int ret;
+
+       ret = phy_modify_mmd_changed(phydev, devad, regnum, mask, set);
+
+       return ret < 0 ? ret : 0;
+}
+
 bool phy_interface_is_ncsi(void)
 {
+#ifdef CONFIG_PHY_NCSI
        struct eth_pdata *pdata = dev_get_plat(eth_get_dev());
 
        return pdata->phy_interface == PHY_INTERFACE_MODE_NCSI;
+#else
+       return 0;
+#endif
 }

diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 24c3ea5..247d975 100644 (file)
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -409,7 +409,7 @@ static int rtl8211f_startup(struct phy_device *phydev)
 }
 
 /* Support for RTL8211B PHY */
-static struct phy_driver RTL8211B_driver = {
+U_BOOT_PHY_DRIVER(rtl8211b) = {
        .name = "RealTek RTL8211B",
        .uid = 0x1cc912,
        .mask = 0xffffff,
@@ -421,7 +421,7 @@ static struct phy_driver RTL8211B_driver = {
 };
 
 /* Support for RTL8211E-VB-CG, RTL8211E-VL-CG and RTL8211EG-VB-CG PHYs */
-static struct phy_driver RTL8211E_driver = {
+U_BOOT_PHY_DRIVER(rtl8211e) = {
        .name = "RealTek RTL8211E",
        .uid = 0x1cc915,
        .mask = 0xffffff,
@@ -433,7 +433,7 @@ static struct phy_driver RTL8211E_driver = {
 };
 
 /* Support for RTL8211DN PHY */
-static struct phy_driver RTL8211DN_driver = {
+U_BOOT_PHY_DRIVER(rtl8211dn) = {
        .name = "RealTek RTL8211DN",
        .uid = 0x1cc914,
        .mask = 0xffffff,
@@ -444,7 +444,7 @@ static struct phy_driver RTL8211DN_driver = {
 };
 
 /* Support for RTL8211F PHY */
-static struct phy_driver RTL8211F_driver = {
+U_BOOT_PHY_DRIVER(rtl8211f) = {
        .name = "RealTek RTL8211F",
        .uid = 0x1cc916,
        .mask = 0xffffff,
@@ -458,7 +458,7 @@ static struct phy_driver RTL8211F_driver = {
 };
 
 /* Support for RTL8201F PHY */
-static struct phy_driver RTL8201F_driver = {
+U_BOOT_PHY_DRIVER(rtl8201f) = {
        .name = "RealTek RTL8201F 10/100Mbps Ethernet",
        .uid = 0x1cc816,
        .mask = 0xffffff,
@@ -468,14 +468,3 @@ static struct phy_driver RTL8201F_driver = {
        .startup = &rtl8211e_startup,
        .shutdown = &genphy_shutdown,
 };
-
-int phy_realtek_init(void)
-{
-       phy_register(&RTL8211B_driver);
-       phy_register(&RTL8211E_driver);
-       phy_register(&RTL8211F_driver);
-       phy_register(&RTL8211DN_driver);
-       phy_register(&RTL8201F_driver);
-
-       return 0;
-}

diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index 7740a25..056b607 100644 (file)
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -43,7 +43,7 @@ static int smsc_startup(struct phy_device *phydev)
        return smsc_parse_status(phydev);
 }
 
-static struct phy_driver lan8700_driver = {
+U_BOOT_PHY_DRIVER(lan8700) = {
        .name = "SMSC LAN8700",
        .uid = 0x0007c0c0,
        .mask = 0xffff0,
@@ -53,7 +53,7 @@ static struct phy_driver lan8700_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver lan911x_driver = {
+U_BOOT_PHY_DRIVER(lan911x) = {
        .name = "SMSC LAN911x Internal PHY",
        .uid = 0x0007c0d0,
        .mask = 0xffff0,
@@ -63,7 +63,7 @@ static struct phy_driver lan911x_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver lan8710_driver = {
+U_BOOT_PHY_DRIVER(lan8710) = {
        .name = "SMSC LAN8710/LAN8720",
        .uid = 0x0007c0f0,
        .mask = 0xffff0,
@@ -73,7 +73,7 @@ static struct phy_driver lan8710_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver lan8740_driver = {
+U_BOOT_PHY_DRIVER(lan8740) = {
        .name = "SMSC LAN8740",
        .uid = 0x0007c110,
        .mask = 0xffff0,
@@ -83,7 +83,7 @@ static struct phy_driver lan8740_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver lan8741_driver = {
+U_BOOT_PHY_DRIVER(lan8741) = {
        .name = "SMSC LAN8741",
        .uid = 0x0007c120,
        .mask = 0xffff0,
@@ -93,7 +93,7 @@ static struct phy_driver lan8741_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver lan8742_driver = {
+U_BOOT_PHY_DRIVER(lan8742) = {
        .name = "SMSC LAN8742",
        .uid = 0x0007c130,
        .mask = 0xffff0,
@@ -102,15 +102,3 @@ static struct phy_driver lan8742_driver = {
        .startup = &genphy_startup,
        .shutdown = &genphy_shutdown,
 };
-
-int phy_smsc_init(void)
-{
-       phy_register(&lan8710_driver);
-       phy_register(&lan911x_driver);
-       phy_register(&lan8700_driver);
-       phy_register(&lan8740_driver);
-       phy_register(&lan8741_driver);
-       phy_register(&lan8742_driver);
-
-       return 0;
-}

diff --git a/drivers/net/phy/teranetics.c b/drivers/net/phy/teranetics.c
index 60049c2..15f2c12 100644 (file)
--- a/drivers/net/phy/teranetics.c
+++ b/drivers/net/phy/teranetics.c
@@ -90,7 +90,7 @@ int tn2020_startup(struct phy_device *phydev)
        return 0;
 }
 
-struct phy_driver tn2020_driver = {
+U_BOOT_PHY_DRIVER(tn2020) = {
        .name = "Teranetics TN2020",
        .uid = PHY_UID_TN2020,
        .mask = 0xfffffff0,
@@ -102,10 +102,3 @@ struct phy_driver tn2020_driver = {
        .startup = &tn2020_startup,
        .shutdown = &gen10g_shutdown,
 };
-
-int phy_teranetics_init(void)
-{
-       phy_register(&tn2020_driver);
-
-       return 0;
-}

diff --git a/drivers/net/phy/ti_phy_init.c b/drivers/net/phy/ti_phy_init.c
index 075b19a..a087819 100644 (file)
--- a/drivers/net/phy/ti_phy_init.c
+++ b/drivers/net/phy/ti_phy_init.c
@@ -10,8 +10,7 @@
 #include <phy.h>
 #include "ti_phy_init.h"
 
-#ifdef CONFIG_PHY_TI_GENERIC
-static struct phy_driver dp83822_driver = {
+U_BOOT_PHY_DRIVER(dp83822) = {
        .name = "TI DP83822",
        .uid = 0x2000a240,
        .mask = 0xfffffff0,
@@ -21,7 +20,7 @@ static struct phy_driver dp83822_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver dp83826nc_driver = {
+U_BOOT_PHY_DRIVER(dp83826nc) = {
        .name = "TI DP83826NC",
        .uid = 0x2000a110,
        .mask = 0xfffffff0,
@@ -31,7 +30,7 @@ static struct phy_driver dp83826nc_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver dp83826c_driver = {
+U_BOOT_PHY_DRIVER(dp83826c) = {
        .name = "TI DP83826C",
        .uid = 0x2000a130,
        .mask = 0xfffffff0,
@@ -41,7 +40,7 @@ static struct phy_driver dp83826c_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver dp83825s_driver = {
+U_BOOT_PHY_DRIVER(dp83825s) = {
        .name = "TI DP83825S",
        .uid = 0x2000a140,
        .mask = 0xfffffff0,
@@ -51,7 +50,7 @@ static struct phy_driver dp83825s_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver dp83825i_driver = {
+U_BOOT_PHY_DRIVER(dp83825i) = {
        .name = "TI DP83825I",
        .uid = 0x2000a150,
        .mask = 0xfffffff0,
@@ -61,7 +60,7 @@ static struct phy_driver dp83825i_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver dp83825m_driver = {
+U_BOOT_PHY_DRIVER(dp83825m) = {
        .name = "TI DP83825M",
        .uid = 0x2000a160,
        .mask = 0xfffffff0,
@@ -71,7 +70,7 @@ static struct phy_driver dp83825m_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver dp83825cs_driver = {
+U_BOOT_PHY_DRIVER(dp83825cs) = {
        .name = "TI DP83825CS",
        .uid = 0x2000a170,
        .mask = 0xfffffff0,
@@ -80,26 +79,3 @@ static struct phy_driver dp83825cs_driver = {
        .startup = &genphy_startup,
        .shutdown = &genphy_shutdown,
 };
-#endif /* CONFIG_PHY_TI_GENERIC */
-
-int phy_ti_init(void)
-{
-#ifdef CONFIG_PHY_TI_DP83867
-       phy_dp83867_init();
-#endif
-
-#ifdef CONFIG_PHY_TI_DP83869
-       phy_dp83869_init();
-#endif
-
-#ifdef CONFIG_PHY_TI_GENERIC
-       phy_register(&dp83822_driver);
-       phy_register(&dp83825s_driver);
-       phy_register(&dp83825i_driver);
-       phy_register(&dp83825m_driver);
-       phy_register(&dp83825cs_driver);
-       phy_register(&dp83826c_driver);
-       phy_register(&dp83826nc_driver);
-#endif
-       return 0;
-}

diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index eca26c9..c5cf0d7 100644 (file)
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -293,7 +293,7 @@ static int vsc8664_config(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver VSC8211_driver = {
+U_BOOT_PHY_DRIVER(vsc8211) = {
        .name   = "Vitesse VSC8211",
        .uid    = 0xfc4b0,
        .mask   = 0xffff0,
@@ -303,7 +303,7 @@ static struct phy_driver VSC8211_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver VSC8221_driver = {
+U_BOOT_PHY_DRIVER(vsc8221) = {
        .name = "Vitesse VSC8221",
        .uid = 0xfc550,
        .mask = 0xffff0,
@@ -313,7 +313,7 @@ static struct phy_driver VSC8221_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver VSC8244_driver = {
+U_BOOT_PHY_DRIVER(vsc8244) = {
        .name = "Vitesse VSC8244",
        .uid = 0xfc6c0,
        .mask = 0xffff0,
@@ -323,7 +323,7 @@ static struct phy_driver VSC8244_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver VSC8234_driver = {
+U_BOOT_PHY_DRIVER(vsc8234) = {
        .name = "Vitesse VSC8234",
        .uid = 0xfc620,
        .mask = 0xffff0,
@@ -333,7 +333,7 @@ static struct phy_driver VSC8234_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver VSC8574_driver = {
+U_BOOT_PHY_DRIVER(vsc8574) = {
        .name = "Vitesse VSC8574",
        .uid = 0x704a0,
        .mask = 0xffff0,
@@ -343,7 +343,7 @@ static struct phy_driver VSC8574_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver VSC8514_driver = {
+U_BOOT_PHY_DRIVER(vsc8514) = {
        .name = "Vitesse VSC8514",
        .uid = 0x70670,
        .mask = 0xffff0,
@@ -353,7 +353,7 @@ static struct phy_driver VSC8514_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver VSC8584_driver = {
+U_BOOT_PHY_DRIVER(vsc8584) = {
        .name = "Vitesse VSC8584",
        .uid = 0x707c0,
        .mask = 0xffff0,
@@ -363,7 +363,7 @@ static struct phy_driver VSC8584_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver VSC8601_driver = {
+U_BOOT_PHY_DRIVER(vsc8601) = {
        .name = "Vitesse VSC8601",
        .uid = 0x70420,
        .mask = 0xffff0,
@@ -373,7 +373,7 @@ static struct phy_driver VSC8601_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver VSC8641_driver = {
+U_BOOT_PHY_DRIVER(vsc8641) = {
        .name = "Vitesse VSC8641",
        .uid = 0x70430,
        .mask = 0xffff0,
@@ -383,7 +383,7 @@ static struct phy_driver VSC8641_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver VSC8662_driver = {
+U_BOOT_PHY_DRIVER(vsc8662) = {
        .name = "Vitesse VSC8662",
        .uid = 0x70660,
        .mask = 0xffff0,
@@ -393,7 +393,7 @@ static struct phy_driver VSC8662_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver VSC8664_driver = {
+U_BOOT_PHY_DRIVER(vsc8664) = {
        .name = "Vitesse VSC8664",
        .uid = 0x70660,
        .mask = 0xffff0,
@@ -404,7 +404,7 @@ static struct phy_driver VSC8664_driver = {
 };
 
 /* Vitesse bought Cicada, so we'll put these here */
-static struct phy_driver cis8201_driver = {
+U_BOOT_PHY_DRIVER(cis8201) = {
        .name = "CIS8201",
        .uid = 0xfc410,
        .mask = 0xffff0,
@@ -414,7 +414,7 @@ static struct phy_driver cis8201_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver cis8204_driver = {
+U_BOOT_PHY_DRIVER(cis8204) = {
        .name = "Cicada Cis8204",
        .uid = 0xfc440,
        .mask = 0xffff0,
@@ -423,22 +423,3 @@ static struct phy_driver cis8204_driver = {
        .startup = &vitesse_startup,
        .shutdown = &genphy_shutdown,
 };
-
-int phy_vitesse_init(void)
-{
-       phy_register(&VSC8641_driver);
-       phy_register(&VSC8601_driver);
-       phy_register(&VSC8234_driver);
-       phy_register(&VSC8244_driver);
-       phy_register(&VSC8211_driver);
-       phy_register(&VSC8221_driver);
-       phy_register(&VSC8574_driver);
-       phy_register(&VSC8584_driver);
-       phy_register(&VSC8514_driver);
-       phy_register(&VSC8662_driver);
-       phy_register(&VSC8664_driver);
-       phy_register(&cis8201_driver);
-       phy_register(&cis8204_driver);
-
-       return 0;
-}

diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c b/drivers/net/phy/xilinx_gmii2rgmii.c
index 7376283..0b7436a 100644 (file)
--- a/drivers/net/phy/xilinx_gmii2rgmii.c
+++ b/drivers/net/phy/xilinx_gmii2rgmii.c
@@ -124,7 +124,7 @@ static int xilinxgmiitorgmii_probe(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver gmii2rgmii_driver = {
+U_BOOT_PHY_DRIVER(gmii2rgmii) = {
        .name = "XILINX GMII2RGMII",
        .uid = PHY_GMII2RGMII_ID,
        .mask = 0xffffffff,
@@ -135,10 +135,3 @@ static struct phy_driver gmii2rgmii_driver = {
        .writeext = xilinxgmiitorgmii_extwrite,
        .readext = xilinxgmiitorgmii_extread,
 };
-
-int phy_xilinx_gmii2rgmii_init(void)
-{
-       phy_register(&gmii2rgmii_driver);
-
-       return 0;
-}

diff --git a/drivers/net/phy/xilinx_phy.c b/drivers/net/phy/xilinx_phy.c
index 39dbfdb..1df639d 100644 (file)
--- a/drivers/net/phy/xilinx_phy.c
+++ b/drivers/net/phy/xilinx_phy.c
@@ -127,7 +127,7 @@ static int xilinxphy_config(struct phy_device *phydev)
        return 0;
 }
 
-static struct phy_driver xilinxphy_driver = {
+U_BOOT_PHY_DRIVER(xilinxphy) = {
        .uid = XILINX_PHY_ID,
        .mask = XILINX_PHY_ID_MASK,
        .name = "Xilinx PCS/PMA PHY",
@@ -136,11 +136,3 @@ static struct phy_driver xilinxphy_driver = {
        .startup = &xilinxphy_startup,
        .shutdown = &genphy_shutdown,
 };
-
-int phy_xilinx_init(void)
-{
-       debug("%s\n", __func__);
-       phy_register(&xilinxphy_driver);
-
-       return 0;
-}

diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index 0bc50dc..c74c8a8 100644 (file)
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -692,6 +692,7 @@ int ravb_of_to_plat(struct udevice *dev)
 
 static const struct udevice_id ravb_ids[] = {
        { .compatible = "renesas,etheravb-rcar-gen3" },
+       { .compatible = "renesas,etheravb-rcar-gen4" },
        { }
 };
 

diff --git a/drivers/net/rswitch.c b/drivers/net/rswitch.c
new file mode 100644 (file)
index 0000000..5a69ca1
--- /dev/null
+++ b/drivers/net/rswitch.c
@@ -0,0 +1,1139 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for Renesas Ethernet RSwitch2 (Ethernet-TSN).
+ *
+ * Copyright (C) 2021 Renesas Electronics Corporation
+ *
+ * Based on the Renesas Ethernet AVB driver.
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include <linux/mii.h>
+#include <eth_phy.h>
+#include <log.h>
+#include <malloc.h>
+#include <miiphy.h>
+
+#define RSWITCH_SLEEP_US       1000
+#define RSWITCH_TIMEOUT_US     1000000
+
+#define RSWITCH_NUM_HW         5
+
+#define ETHA_TO_GWCA(i)                ((i) % 2)
+#define GWCA_TO_HW_INDEX(i)    ((i) + 3)
+#define HW_INDEX_TO_GWCA(i)    ((i) - 3)
+
+#define RSWITCH_MAX_CTAG_PCP   7
+
+/* Registers */
+#define RSWITCH_COMA_OFFSET     0x00009000
+#define RSWITCH_ETHA_OFFSET     0x0000a000      /* with RMAC */
+#define RSWITCH_ETHA_SIZE       0x00002000      /* with RMAC */
+#define RSWITCH_GWCA_OFFSET    0x00010000
+#define RSWITCH_GWCA_SIZE      0x00002000
+
+#define FWRO    0
+#define CARO    RSWITCH_COMA_OFFSET
+#define GWRO    0
+#define TARO    0
+#define RMRO    0x1000
+
+enum rswitch_reg {
+       EAMC            = TARO + 0x0000,
+       EAMS            = TARO + 0x0004,
+       EATDQDC         = TARO + 0x0060,
+       EATTFC          = TARO + 0x0138,
+       EATASRIRM       = TARO + 0x03E4,
+
+       GWMC            = GWRO + 0x0000,
+       GWMS            = GWRO + 0x0004,
+       GWMTIRM         = GWRO + 0x0100,
+       GWVCC           = GWRO + 0x0130,
+       GWTTFC          = GWRO + 0x0138,
+       GWDCBAC0        = GWRO + 0x0194,
+       GWDCBAC1        = GWRO + 0x0198,
+       GWTRC           = GWRO + 0x0200,
+       GWARIRM         = GWRO + 0x0380,
+       GWDCC           = GWRO + 0x0400,
+
+       RRC             = CARO + 0x0004,
+       RCEC            = CARO + 0x0008,
+       RCDC            = CARO + 0x000C,
+       CABPIRM         = CARO + 0x0140,
+
+       FWPC0           = FWRO + 0x0100,
+       FWPBFC          = FWRO + 0x4A00,
+       FWPBFCSDC       = FWRO + 0x4A04,
+
+       MPSM            = RMRO + 0x0000,
+       MPIC            = RMRO + 0x0004,
+       MRMAC0          = RMRO + 0x0084,
+       MRMAC1          = RMRO + 0x0088,
+       MRAFC           = RMRO + 0x008C,
+       MRSCE           = RMRO + 0x0090,
+       MRSCP           = RMRO + 0x0094,
+       MLVC            = RMRO + 0x0180,
+       MLBC            = RMRO + 0x0188,
+       MXGMIIC         = RMRO + 0x0190,
+       MPCH            = RMRO + 0x0194,
+       MANM            = RMRO + 0x019C,
+       MMIS0           = RMRO + 0x0210,
+       MMIS1           = RMRO + 0x0220,
+};
+
+/* COMA */
+#define RRC_RR         BIT(0)
+#define RCEC_RCE       BIT(16)
+
+#define CABPIRM_BPIOG  BIT(0)
+#define CABPIRM_BPR    BIT(1)
+
+/* MFWD */
+#define FWPC0(i)       (FWPC0 + (i) * 0x10)
+#define FWPC0_LTHTA     BIT(0)
+#define FWPC0_IP4UE     BIT(3)
+#define FWPC0_IP4TE     BIT(4)
+#define FWPC0_IP4OE     BIT(5)
+#define FWPC0_L2SE      BIT(9)
+#define FWPC0_IP4EA     BIT(10)
+#define FWPC0_IPDSA     BIT(12)
+#define FWPC0_IPHLA     BIT(18)
+#define FWPC0_MACSDA    BIT(20)
+#define FWPC0_MACHLA    BIT(26)
+#define FWPC0_MACHMA    BIT(27)
+#define FWPC0_VLANSA    BIT(28)
+
+#define FWPC0_DEFAULT   (FWPC0_LTHTA | FWPC0_IP4UE | FWPC0_IP4TE | \
+                        FWPC0_IP4OE | FWPC0_L2SE | FWPC0_IP4EA | \
+                        FWPC0_IPDSA | FWPC0_IPHLA | FWPC0_MACSDA | \
+                        FWPC0_MACHLA | FWPC0_MACHMA | FWPC0_VLANSA)
+
+#define FWPBFC(i)      (FWPBFC + (i) * 0x10)
+#define FWPBFCSDC(j, i)        (FWPBFCSDC + (i) * 0x10 + (j) * 0x04)
+
+/* ETHA */
+#define EATASRIRM_TASRIOG      BIT(0)
+#define EATASRIRM_TASRR                BIT(1)
+#define EATDQDC(q)             (EATDQDC + (q) * 0x04)
+#define EATDQDC_DQD            (0xff)
+
+/* RMAC */
+#define MPIC_PIS_GMII          0x02
+#define MPIC_LSC_MASK          (0x07 << 3)
+#define MPIC_LSC_100           (0x01 << 3)
+#define MPIC_LSC_1000          (0x02 << 3)
+#define MPIC_LSC_2500          (0x03 << 3)
+#define MLVC_PLV               BIT(16)
+#define MLVC_LVT               0x09
+#define MMIS0_LVSS             0x02
+
+#define MPIC_PSMCS_MASK                (0x7f << 16)
+#define MPIC_PSMHT_MASK                (0x06 << 24)
+#define MPIC_MDC_CLK_SET       (0x06050000)
+
+#define MPSM_MFF_C45           BIT(2)
+#define MPSM_MFF_C22           0x0
+#define MPSM_PSME              BIT(0)
+
+#define MDIO_READ_C45          0x03
+#define MDIO_WRITE_C45         0x01
+#define MDIO_ADDR_C45          0x00
+
+#define MDIO_READ_C22           0x02
+#define MDIO_WRITE_C22          0x01
+
+#define MPSM_POP_MASK          (0x03 << 13)
+#define MPSM_PRA_MASK          (0x1f << 8)
+#define MPSM_PDA_MASK          (0x1f << 3)
+#define MPSM_PRD_MASK          (0xffff << 16)
+
+/* Completion flags */
+#define MMIS1_PAACS            BIT(2) /* Address */
+#define MMIS1_PWACS            BIT(1) /* Write */
+#define MMIS1_PRACS            BIT(0) /* Read */
+#define MMIS1_CLEAR_FLAGS      0xf
+
+/* ETHA */
+enum rswitch_etha_mode {
+       EAMC_OPC_RESET,
+       EAMC_OPC_DISABLE,
+       EAMC_OPC_CONFIG,
+       EAMC_OPC_OPERATION,
+};
+
+#define EAMS_OPS_MASK  EAMC_OPC_OPERATION
+
+/* GWCA */
+enum rswitch_gwca_mode {
+       GWMC_OPC_RESET,
+       GWMC_OPC_DISABLE,
+       GWMC_OPC_CONFIG,
+       GWMC_OPC_OPERATION,
+};
+
+#define GWMS_OPS_MASK  GWMC_OPC_OPERATION
+
+#define GWMTIRM_MTIOG          BIT(0)
+#define GWMTIRM_MTR            BIT(1)
+#define GWARIRM_ARIOG          BIT(0)
+#define GWARIRM_ARR            BIT(1)
+#define GWVCC_VEM_SC_TAG       (0x3 << 16)
+#define GWDCBAC0_DCBAUP                (0xff)
+#define GWTRC(i)               (GWTRC + (i) * 0x04)
+#define GWDCC(i)               (GWDCC + (i) * 0x04)
+#define        GWDCC_DQT               BIT(11)
+#define GWDCC_BALR             BIT(24)
+
+struct rswitch_etha {
+       int                     index;
+       void __iomem            *addr;
+       struct phy_device       *phydev;
+       struct mii_dev          *bus;
+       unsigned char           *enetaddr;
+};
+
+struct rswitch_gwca {
+       int                     index;
+       void __iomem            *addr;
+       int                     num_chain;
+};
+
+/* Setting value */
+#define LINK_SPEED_100         100
+#define LINK_SPEED_1000                1000
+#define LINK_SPEED_2500                2500
+
+/* Decriptor */
+#define RSWITCH_NUM_BASE_DESC          2
+#define RSWITCH_TX_CHAIN_INDEX         0
+#define RSWITCH_RX_CHAIN_INDEX         1
+#define RSWITCH_NUM_TX_DESC            8
+#define RSWITCH_NUM_RX_DESC            8
+
+enum RX_DS_CC_BIT {
+       RX_DS   = 0x0fff, /* Data size */
+       RX_TR   = 0x1000, /* Truncation indication */
+       RX_EI   = 0x2000, /* Error indication */
+       RX_PS   = 0xc000, /* Padding selection */
+};
+
+enum DIE_DT {
+       /* Frame data */
+       DT_FSINGLE      = 0x80,
+       DT_FSTART       = 0x90,
+       DT_FMID         = 0xa0,
+       DT_FEND         = 0xb8,
+
+       /* Chain control */
+       DT_LEMPTY       = 0xc0,
+       DT_EEMPTY       = 0xd0,
+       DT_LINKFIX      = 0x00,
+       DT_LINK         = 0xe0,
+       DT_EOS          = 0xf0,
+       /* HW/SW arbitration */
+       DT_FEMPTY       = 0x40,
+       DT_FEMPTY_IS    = 0x10,
+       DT_FEMPTY_IC    = 0x20,
+       DT_FEMPTY_ND    = 0x38,
+       DT_FEMPTY_START = 0x50,
+       DT_FEMPTY_MID   = 0x60,
+       DT_FEMPTY_END   = 0x70,
+
+       DT_MASK         = 0xf0,
+       DIE             = 0x08, /* Descriptor Interrupt Enable */
+};
+
+struct rswitch_desc {
+       __le16 info_ds; /* Descriptor size */
+       u8 die_dt;      /* Descriptor interrupt enable and type */
+       __u8  dptrh;    /* Descriptor pointer MSB */
+       __le32 dptrl;   /* Descriptor pointer LSW */
+} __packed;
+
+struct rswitch_rxdesc {
+       struct rswitch_desc     data;
+       struct rswitch_desc     link;
+       u8                      __pad[48];
+       u8                      packet[PKTSIZE_ALIGN];
+} __packed;
+
+struct rswitch_port_priv {
+       void __iomem            *addr;
+       struct phy              serdes;
+       struct rswitch_etha     etha;
+       struct rswitch_gwca     gwca;
+       struct rswitch_desc     bat_desc[RSWITCH_NUM_BASE_DESC];
+       struct rswitch_desc     tx_desc[RSWITCH_NUM_TX_DESC];
+       struct rswitch_rxdesc   rx_desc[RSWITCH_NUM_RX_DESC];
+       u32                     rx_desc_index;
+       u32                     tx_desc_index;
+};
+
+struct rswitch_priv {
+       void __iomem            *addr;
+       struct clk              *rsw_clk;
+};
+
+static inline void rswitch_flush_dcache(u32 addr, u32 len)
+{
+       flush_dcache_range(addr, addr + len);
+}
+
+static inline void rswitch_invalidate_dcache(u32 addr, u32 len)
+{
+       u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
+       u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
+
+       invalidate_dcache_range(start, end);
+}
+
+static void rswitch_agent_clock_ctrl(struct rswitch_port_priv *priv, int port, int enable)
+{
+       u32 val;
+
+       if (enable) {
+               val = readl(priv->addr + RCEC);
+               if ((val & (RCEC_RCE | BIT(port))) != (RCEC_RCE | BIT(port)))
+                       writel(val | RCEC_RCE | BIT(port), priv->addr + RCEC);
+       } else {
+               setbits_le32(priv->addr + RCDC, BIT(port));
+       }
+}
+
+static int rswitch_etha_change_mode(struct rswitch_port_priv *priv,
+                                   enum rswitch_etha_mode mode)
+{
+       struct rswitch_etha *etha = &priv->etha;
+       u32 pval;
+       int ret;
+
+       /* Enable clock */
+       rswitch_agent_clock_ctrl(priv, etha->index, 1);
+
+       writel(mode, etha->addr + EAMC);
+
+       ret = readl_poll_sleep_timeout(etha->addr + EAMS, pval,
+                                      (pval & EAMS_OPS_MASK) == mode,
+                                      RSWITCH_SLEEP_US, RSWITCH_TIMEOUT_US);
+
+       /* Disable clock */
+       if (mode == EAMC_OPC_DISABLE)
+               rswitch_agent_clock_ctrl(priv, etha->index, 0);
+
+       return ret;
+}
+
+static int rswitch_gwca_change_mode(struct rswitch_port_priv *priv,
+                                   enum rswitch_gwca_mode mode)
+{
+       struct rswitch_gwca *gwca = &priv->gwca;
+       u32 pval;
+       int ret;
+
+       /* Enable clock */
+       rswitch_agent_clock_ctrl(priv, gwca->index, 1);
+
+       writel(mode, gwca->addr + GWMC);
+
+       ret = readl_poll_sleep_timeout(gwca->addr + GWMS, pval,
+                                      (pval & GWMS_OPS_MASK) == mode,
+                                      RSWITCH_SLEEP_US, RSWITCH_TIMEOUT_US);
+
+       /* Disable clock */
+       if (mode == GWMC_OPC_DISABLE)
+               rswitch_agent_clock_ctrl(priv, gwca->index, 0);
+
+       return ret;
+}
+
+static int rswitch_mii_access_c45(struct rswitch_etha *etha, bool read,
+                                 int phyad, int devad, int regad, int data)
+{
+       u32 pval, val;
+       int ret;
+
+       /* No match device */
+       if (devad == 0xffffffff)
+               return 0;
+
+       /* Clear completion flags */
+       writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1);
+
+       /* Submit address to PHY (MDIO_ADDR_C45 << 13) */
+       val = MPSM_PSME | MPSM_MFF_C45 | (devad << 8) | (phyad << 3);
+       writel((regad << 16) | val, etha->addr + MPSM);
+
+       ret = readl_poll_sleep_timeout(etha->addr + MMIS1, pval,
+                                      pval & MMIS1_PAACS,
+                                      RSWITCH_SLEEP_US, RSWITCH_TIMEOUT_US);
+       if (ret)
+               return ret;
+
+       /* Clear address completion flag */
+       setbits_le32(etha->addr + MMIS1, MMIS1_PAACS);
+
+       /* Read/Write PHY register */
+       if (read) {
+               val |= MDIO_READ_C45 << 13;
+               writel(val, etha->addr + MPSM);
+
+               ret = readl_poll_sleep_timeout(etha->addr + MMIS1, pval,
+                                              pval & MMIS1_PRACS,
+                                              RSWITCH_SLEEP_US,
+                                              RSWITCH_TIMEOUT_US);
+               if (ret)
+                       return ret;
+
+               /* Read data */
+               ret = (readl(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16;
+
+               /* Clear read completion flag */
+               setbits_le32(etha->addr + MMIS1, MMIS1_PRACS);
+       } else {
+               val |= MDIO_WRITE_C45 << 13;
+               val |= data << 16;
+               writel(val, etha->addr + MPSM);
+
+               ret = readl_poll_sleep_timeout(etha->addr + MMIS1, pval,
+                                              pval & MMIS1_PWACS,
+                                              RSWITCH_SLEEP_US,
+                                              RSWITCH_TIMEOUT_US);
+       }
+
+       return ret;
+}
+
+static int rswitch_mii_read_c45(struct mii_dev *miidev, int phyad, int devad, int regad)
+{
+       struct rswitch_port_priv *priv = miidev->priv;
+       struct rswitch_etha *etha = &priv->etha;
+       int val;
+       int reg;
+
+       /* Change to disable mode */
+       rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE);
+
+       /* Change to config mode */
+       rswitch_etha_change_mode(priv, EAMC_OPC_CONFIG);
+
+       /* Enable Station Management clock */
+       reg = readl(etha->addr + MPIC);
+       reg &= ~MPIC_PSMCS_MASK & ~MPIC_PSMHT_MASK;
+       writel(reg | MPIC_MDC_CLK_SET, etha->addr + MPIC);
+
+       /* Set Station Management Mode : Clause 45 */
+       setbits_le32(etha->addr + MPSM, MPSM_MFF_C45);
+
+       /* Access PHY register */
+       val = rswitch_mii_access_c45(etha, true, phyad, devad, regad, 0);
+
+       /* Disable Station Management Clock */
+       clrbits_le32(etha->addr + MPIC, MPIC_PSMCS_MASK);
+
+       /* Change to disable mode */
+       rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE);
+
+       return val;
+}
+
+int rswitch_mii_write_c45(struct mii_dev *miidev, int phyad, int devad, int regad, u16 data)
+{
+       struct rswitch_port_priv *priv = miidev->priv;
+       struct rswitch_etha *etha = &priv->etha;
+       int reg;
+
+       /* Change to disable mode */
+       rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE);
+
+       /* Change to config mode */
+       rswitch_etha_change_mode(priv, EAMC_OPC_CONFIG);
+
+       /* Enable Station Management clock */
+       reg = readl(etha->addr + MPIC);
+       reg &= ~MPIC_PSMCS_MASK & ~MPIC_PSMHT_MASK;
+       writel(reg | MPIC_MDC_CLK_SET, etha->addr + MPIC);
+
+       /* Set Station Management Mode : Clause 45 */
+       setbits_le32(etha->addr + MPSM, MPSM_MFF_C45);
+
+       /* Access PHY register */
+       rswitch_mii_access_c45(etha, false, phyad, devad, regad, data);
+
+       /* Disable Station Management Clock */
+       clrbits_le32(etha->addr + MPIC, MPIC_PSMCS_MASK);
+
+       /* Change to disable mode */
+       rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE);
+
+       return 0;
+}
+
+static int rswitch_check_link(struct rswitch_etha *etha)
+{
+       u32 pval;
+       int ret;
+
+       /* Request Link Verification */
+       writel(MLVC_PLV, etha->addr + MLVC);
+
+       /* Complete Link Verification */
+       ret = readl_poll_sleep_timeout(etha->addr + MLVC, pval,
+                                      !(pval & MLVC_PLV),
+                                      RSWITCH_SLEEP_US, RSWITCH_TIMEOUT_US);
+       if (ret) {
+               debug("\n%s: Link verification timeout!", __func__);
+               return ret;
+       }
+
+       return 0;
+}
+
+static int rswitch_reset(struct rswitch_port_priv *priv)
+{
+       int ret;
+
+       setbits_le32(priv->addr + RRC, RRC_RR);
+       clrbits_le32(priv->addr + RRC, RRC_RR);
+
+       ret = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE);
+       if (ret)
+               return ret;
+
+       ret = rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE);
+       if (ret)
+               return ret;
+
+       return 0;
+}
+
+static void rswitch_bat_desc_init(struct rswitch_port_priv *priv)
+{
+       const u32 desc_size = RSWITCH_NUM_BASE_DESC * sizeof(struct rswitch_desc);
+       int i;
+
+       /* Initialize all descriptors */
+       memset(priv->bat_desc, 0x0, desc_size);
+
+       for (i = 0; i < RSWITCH_NUM_BASE_DESC; i++)
+               priv->bat_desc[i].die_dt = DT_EOS;
+
+       rswitch_flush_dcache((uintptr_t)priv->bat_desc, desc_size);
+}
+
+static void rswitch_tx_desc_init(struct rswitch_port_priv *priv)
+{
+       const u32 desc_size = RSWITCH_NUM_TX_DESC * sizeof(struct rswitch_desc);
+       u64 tx_desc_addr;
+       int i;
+
+       /* Initialize all descriptor */
+       memset(priv->tx_desc, 0x0, desc_size);
+       priv->tx_desc_index = 0;
+
+       for (i = 0; i < RSWITCH_NUM_TX_DESC; i++)
+               priv->tx_desc[i].die_dt = DT_EEMPTY;
+
+       /* Mark the end of the descriptors */
+       priv->tx_desc[RSWITCH_NUM_TX_DESC - 1].die_dt = DT_LINKFIX;
+       tx_desc_addr = (uintptr_t)priv->tx_desc;
+       priv->tx_desc[RSWITCH_NUM_TX_DESC - 1].dptrl = lower_32_bits(tx_desc_addr);
+       priv->tx_desc[RSWITCH_NUM_TX_DESC - 1].dptrh = upper_32_bits(tx_desc_addr);
+       rswitch_flush_dcache(tx_desc_addr, desc_size);
+
+       /* Point the controller to the TX descriptor list */
+       priv->bat_desc[RSWITCH_TX_CHAIN_INDEX].die_dt = DT_LINKFIX;
+       priv->bat_desc[RSWITCH_TX_CHAIN_INDEX].dptrl = lower_32_bits(tx_desc_addr);
+       priv->bat_desc[RSWITCH_TX_CHAIN_INDEX].dptrh = upper_32_bits(tx_desc_addr);
+       rswitch_flush_dcache((uintptr_t)&priv->bat_desc[RSWITCH_TX_CHAIN_INDEX],
+                            sizeof(struct rswitch_desc));
+}
+
+static void rswitch_rx_desc_init(struct rswitch_port_priv *priv)
+{
+       const u32 desc_size = RSWITCH_NUM_RX_DESC * sizeof(struct rswitch_rxdesc);
+       int i;
+       u64 packet_addr;
+       u64 next_rx_desc_addr;
+       u64 rx_desc_addr;
+
+       /* Initialize all descriptor */
+       memset(priv->rx_desc, 0x0, desc_size);
+       priv->rx_desc_index = 0;
+
+       for (i = 0; i < RSWITCH_NUM_RX_DESC; i++) {
+               priv->rx_desc[i].data.die_dt = DT_EEMPTY;
+               priv->rx_desc[i].data.info_ds = PKTSIZE_ALIGN;
+               packet_addr = (uintptr_t)priv->rx_desc[i].packet;
+               priv->rx_desc[i].data.dptrl = lower_32_bits(packet_addr);
+               priv->rx_desc[i].data.dptrh = upper_32_bits(packet_addr);
+
+               priv->rx_desc[i].link.die_dt = DT_LINKFIX;
+               next_rx_desc_addr = (uintptr_t)&priv->rx_desc[i + 1];
+               priv->rx_desc[i].link.dptrl = lower_32_bits(next_rx_desc_addr);
+               priv->rx_desc[i].link.dptrh = upper_32_bits(next_rx_desc_addr);
+       }
+
+       /* Mark the end of the descriptors */
+       priv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.die_dt = DT_LINKFIX;
+       rx_desc_addr = (uintptr_t)priv->rx_desc;
+       priv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.dptrl = lower_32_bits(rx_desc_addr);
+       priv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.dptrh = upper_32_bits(rx_desc_addr);
+       rswitch_flush_dcache(rx_desc_addr, desc_size);
+
+       /* Point the controller to the rx descriptor list */
+       priv->bat_desc[RSWITCH_RX_CHAIN_INDEX].die_dt = DT_LINKFIX;
+       priv->bat_desc[RSWITCH_RX_CHAIN_INDEX].dptrl = lower_32_bits(rx_desc_addr);
+       priv->bat_desc[RSWITCH_RX_CHAIN_INDEX].dptrh = upper_32_bits(rx_desc_addr);
+       rswitch_flush_dcache((uintptr_t)&priv->bat_desc[RSWITCH_RX_CHAIN_INDEX],
+                            sizeof(struct rswitch_desc));
+}
+
+static void rswitch_clock_enable(struct rswitch_port_priv *priv)
+{
+       struct rswitch_etha *etha = &priv->etha;
+       struct rswitch_gwca *gwca = &priv->gwca;
+
+       setbits_le32(priv->addr + RCEC, BIT(etha->index) | BIT(gwca->index) | RCEC_RCE);
+}
+
+static int rswitch_bpool_init(struct rswitch_port_priv *priv)
+{
+       u32 pval;
+
+       writel(CABPIRM_BPIOG, priv->addr + CABPIRM);
+
+       return readl_poll_sleep_timeout(priv->addr + CABPIRM, pval,
+                                       pval & CABPIRM_BPR,
+                                       RSWITCH_SLEEP_US, RSWITCH_TIMEOUT_US);
+}
+
+static void rswitch_mfwd_init(struct rswitch_port_priv *priv)
+{
+       struct rswitch_etha *etha = &priv->etha;
+       struct rswitch_gwca *gwca = &priv->gwca;
+
+       writel(FWPC0_DEFAULT, priv->addr + FWPC0(etha->index));
+       writel(FWPC0_DEFAULT, priv->addr + FWPC0(gwca->index));
+
+       writel(RSWITCH_RX_CHAIN_INDEX,
+              priv->addr + FWPBFCSDC(HW_INDEX_TO_GWCA(gwca->index), etha->index));
+
+       writel(BIT(gwca->index),
+              priv->addr + FWPBFC(etha->index));
+
+       writel(BIT(etha->index),
+              priv->addr + FWPBFC(gwca->index));
+}
+
+static void rswitch_rmac_init(struct rswitch_etha *etha)
+{
+       unsigned char *mac = etha->enetaddr;
+
+       /* Set MAC address */
+       writel((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
+              etha->addr + MRMAC1);
+
+       writel((mac[0] << 8) | mac[1], etha->addr + MRMAC0);
+
+       /* Set MIIx */
+       writel(MPIC_PIS_GMII | MPIC_LSC_1000, etha->addr + MPIC);
+
+       writel(0x07E707E7, etha->addr + MRAFC);
+}
+
+static int rswitch_gwca_mcast_table_reset(struct rswitch_gwca *gwca)
+{
+       u32 pval;
+
+       writel(GWMTIRM_MTIOG, gwca->addr + GWMTIRM);
+
+       return readl_poll_sleep_timeout(gwca->addr + GWMTIRM, pval,
+                                       pval & GWMTIRM_MTR,
+                                       RSWITCH_SLEEP_US, RSWITCH_TIMEOUT_US);
+}
+
+static int rswitch_gwca_axi_ram_reset(struct rswitch_gwca *gwca)
+{
+       u32 pval;
+
+       writel(GWARIRM_ARIOG, gwca->addr + GWARIRM);
+
+       return readl_poll_sleep_timeout(gwca->addr + GWARIRM, pval,
+                                       pval & GWARIRM_ARR,
+                                       RSWITCH_SLEEP_US, RSWITCH_TIMEOUT_US);
+}
+
+static int rswitch_gwca_init(struct rswitch_port_priv *priv)
+{
+       struct rswitch_gwca *gwca = &priv->gwca;
+       int ret;
+
+       ret = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE);
+       if (ret)
+               return ret;
+
+       ret = rswitch_gwca_change_mode(priv, GWMC_OPC_CONFIG);
+       if (ret)
+               return ret;
+
+       ret = rswitch_gwca_mcast_table_reset(gwca);
+       if (ret)
+               return ret;
+
+       ret = rswitch_gwca_axi_ram_reset(gwca);
+       if (ret)
+               return ret;
+
+       /* Setting flow */
+       writel(GWVCC_VEM_SC_TAG, gwca->addr + GWVCC);
+       writel(0, gwca->addr + GWTTFC);
+       writel(upper_32_bits((uintptr_t)priv->bat_desc) & GWDCBAC0_DCBAUP, gwca->addr + GWDCBAC0);
+       writel(lower_32_bits((uintptr_t)priv->bat_desc), gwca->addr + GWDCBAC1);
+       writel(GWDCC_DQT | GWDCC_BALR, gwca->addr + GWDCC(RSWITCH_TX_CHAIN_INDEX));
+       writel(GWDCC_BALR, gwca->addr + GWDCC(RSWITCH_RX_CHAIN_INDEX));
+
+       ret = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE);
+       if (ret)
+               return ret;
+
+       ret = rswitch_gwca_change_mode(priv, GWMC_OPC_OPERATION);
+       if (ret)
+               return ret;
+
+       return 0;
+}
+
+static int rswitch_etha_tas_ram_reset(struct rswitch_etha *etha)
+{
+       u32 pval;
+
+       writel(EATASRIRM_TASRIOG, etha->addr + EATASRIRM);
+
+       return readl_poll_sleep_timeout(etha->addr + EATASRIRM, pval,
+                                       pval & EATASRIRM_TASRR,
+                                       RSWITCH_SLEEP_US, RSWITCH_TIMEOUT_US);
+}
+
+static int rswitch_etha_init(struct rswitch_port_priv *priv)
+{
+       struct rswitch_etha *etha = &priv->etha;
+       int ret;
+       u32 prio;
+
+       ret = rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE);
+       if (ret)
+               return ret;
+
+       ret = rswitch_etha_change_mode(priv, EAMC_OPC_CONFIG);
+       if (ret)
+               return ret;
+
+       ret = rswitch_etha_tas_ram_reset(etha);
+       if (ret)
+               return ret;
+
+       /* Setting flow */
+       writel(0, etha->addr + EATTFC);
+
+       for (prio = 0; prio < RSWITCH_MAX_CTAG_PCP; prio++)
+               writel(EATDQDC_DQD, etha->addr + EATDQDC(prio));
+
+       rswitch_rmac_init(etha);
+
+       ret = rswitch_etha_change_mode(priv, EAMC_OPC_OPERATION);
+       if (ret)
+               return ret;
+
+       /* Link Verification */
+       ret = rswitch_check_link(etha);
+       if (ret)
+               return ret;
+
+       return 0;
+}
+
+static int rswitch_init(struct rswitch_port_priv *priv)
+{
+       struct rswitch_etha *etha = &priv->etha;
+       int ret;
+
+       ret = rswitch_reset(priv);
+       if (ret)
+               return ret;
+
+       ret = generic_phy_set_mode(&priv->serdes, PHY_MODE_ETHERNET,
+                                  etha->phydev->interface);
+       if (ret)
+               return ret;
+
+       ret = generic_phy_set_speed(&priv->serdes, etha->phydev->speed);
+       if (ret)
+               return ret;
+
+       ret = generic_phy_init(&priv->serdes);
+       if (ret)
+               return ret;
+
+       ret = generic_phy_power_on(&priv->serdes);
+       if (ret)
+               return ret;
+
+       ret = phy_startup(etha->phydev);
+       if (ret)
+               return ret;
+
+       rswitch_bat_desc_init(priv);
+       rswitch_tx_desc_init(priv);
+       rswitch_rx_desc_init(priv);
+
+       rswitch_clock_enable(priv);
+
+       ret = rswitch_bpool_init(priv);
+       if (ret)
+               return ret;
+
+       rswitch_mfwd_init(priv);
+
+       ret = rswitch_gwca_init(priv);
+       if (ret)
+               return ret;
+
+       ret = rswitch_etha_init(priv);
+       if (ret)
+               return ret;
+
+       return 0;
+}
+
+static int rswitch_start(struct udevice *dev)
+{
+       struct rswitch_port_priv *priv = dev_get_priv(dev);
+       int ret;
+
+       ret = rswitch_init(priv);
+       if (ret)
+               return ret;
+
+       return 0;
+}
+
+#define RSWITCH_TX_TIMEOUT_MS  1000
+static int rswitch_send(struct udevice *dev, void *packet, int len)
+{
+       struct rswitch_port_priv *priv = dev_get_priv(dev);
+       struct rswitch_desc *desc = &priv->tx_desc[priv->tx_desc_index];
+       struct rswitch_gwca *gwca = &priv->gwca;
+       u32 gwtrc_index, start;
+
+       /* Update TX descriptor */
+       rswitch_flush_dcache((uintptr_t)packet, len);
+       memset(desc, 0x0, sizeof(*desc));
+       desc->die_dt = DT_FSINGLE;
+       desc->info_ds = len;
+       desc->dptrl = lower_32_bits((uintptr_t)packet);
+       desc->dptrh = upper_32_bits((uintptr_t)packet);
+       rswitch_flush_dcache((uintptr_t)desc, sizeof(*desc));
+
+       /* Start transmission */
+       gwtrc_index = RSWITCH_TX_CHAIN_INDEX / 32;
+       setbits_le32(gwca->addr + GWTRC(gwtrc_index), BIT(RSWITCH_TX_CHAIN_INDEX));
+
+       /* Wait until packet is transmitted */
+       start = get_timer(0);
+       while (get_timer(start) < RSWITCH_TX_TIMEOUT_MS) {
+               rswitch_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
+               if ((desc->die_dt & DT_MASK) != DT_FSINGLE)
+                       break;
+               udelay(10);
+       }
+
+       if (get_timer(start) >= RSWITCH_TX_TIMEOUT_MS) {
+               dev_dbg(dev, "\n%s: Timeout", __func__);
+               return -ETIMEDOUT;
+       }
+
+       priv->tx_desc_index = (priv->tx_desc_index + 1) % (RSWITCH_NUM_TX_DESC - 1);
+
+       return 0;
+}
+
+static int rswitch_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+       struct rswitch_port_priv *priv = dev_get_priv(dev);
+       struct rswitch_rxdesc *desc = &priv->rx_desc[priv->rx_desc_index];
+       u8 *packet;
+       int len;
+
+       /* Check if the rx descriptor is ready */
+       rswitch_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
+       if ((desc->data.die_dt & DT_MASK) == DT_FEMPTY)
+               return -EAGAIN;
+
+       len = desc->data.info_ds & RX_DS;
+       packet = (u8 *)(((uintptr_t)(desc->data.dptrh) << 32) | (uintptr_t)desc->data.dptrl);
+       rswitch_invalidate_dcache((uintptr_t)packet, len);
+
+       *packetp = packet;
+
+       return len;
+}
+
+static int rswitch_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+       struct rswitch_port_priv *priv = dev_get_priv(dev);
+       struct rswitch_rxdesc *desc = &priv->rx_desc[priv->rx_desc_index];
+
+       /* Make current descritor available again */
+       desc->data.die_dt = DT_FEMPTY;
+       desc->data.info_ds = PKTSIZE_ALIGN;
+       rswitch_flush_dcache((uintptr_t)desc, sizeof(*desc));
+
+       /* Point to the next descriptor */
+       priv->rx_desc_index = (priv->rx_desc_index + 1) % RSWITCH_NUM_RX_DESC;
+       desc = &priv->rx_desc[priv->rx_desc_index];
+       rswitch_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
+
+       return 0;
+}
+
+static void rswitch_stop(struct udevice *dev)
+{
+       struct rswitch_port_priv *priv = dev_get_priv(dev);
+
+       phy_shutdown(priv->etha.phydev);
+
+       generic_phy_power_off(&priv->serdes);
+}
+
+static int rswitch_write_hwaddr(struct udevice *dev)
+{
+       struct rswitch_port_priv *priv = dev_get_priv(dev);
+       struct rswitch_etha *etha = &priv->etha;
+       struct eth_pdata *pdata = dev_get_plat(dev);
+       unsigned char *mac = pdata->enetaddr;
+
+       writel((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
+              etha->addr + MRMAC1);
+
+       writel((mac[0] << 8) | mac[1], etha->addr + MRMAC0);
+
+       return 0;
+}
+
+static int rswitch_phy_config(struct udevice *dev)
+{
+       struct rswitch_port_priv *priv = dev_get_priv(dev);
+       struct rswitch_etha *etha = &priv->etha;
+       struct eth_pdata *pdata = dev_get_plat(dev);
+       struct phy_device *phydev;
+       int phy_addr;
+
+       phy_addr = eth_phy_get_addr(dev);
+       if (phy_addr < 0)
+               return phy_addr;
+
+       phydev = phy_connect(etha->bus, phy_addr, dev, pdata->phy_interface);
+       if (!phydev)
+               return -ENODEV;
+
+       etha->phydev = phydev;
+       phydev->speed = SPEED_1000;
+
+       phy_config(phydev);
+
+       return 0;
+}
+
+static int rswitch_port_probe(struct udevice *dev)
+{
+       struct rswitch_priv *rpriv =
+               (struct rswitch_priv *)dev_get_driver_data(dev);
+       struct eth_pdata *pdata = dev_get_plat(dev);
+       struct rswitch_port_priv *priv = dev_get_priv(dev);
+       struct rswitch_etha *etha = &priv->etha;
+       struct rswitch_gwca *gwca = &priv->gwca;
+       struct mii_dev *mdiodev;
+       int ret;
+
+       priv->addr = rpriv->addr;
+
+       etha->enetaddr = pdata->enetaddr;
+
+       etha->index = dev_read_u32_default(dev, "reg", 0);
+       etha->addr = priv->addr + RSWITCH_ETHA_OFFSET + etha->index * RSWITCH_ETHA_SIZE;
+
+       gwca->index = 1;
+       gwca->addr = priv->addr + RSWITCH_GWCA_OFFSET + gwca->index * RSWITCH_GWCA_SIZE;
+       gwca->index = GWCA_TO_HW_INDEX(gwca->index);
+
+       ret = generic_phy_get_by_index(dev, 0, &priv->serdes);
+       if (ret)
+               return ret;
+
+       /* Toggle the reset so we can access the PHYs */
+       ret = rswitch_reset(priv);
+       if (ret)
+               return ret;
+
+       mdiodev = mdio_alloc();
+       if (!mdiodev)
+               return -ENOMEM;
+
+       mdiodev->priv = priv;
+       mdiodev->read = rswitch_mii_read_c45;
+       mdiodev->write = rswitch_mii_write_c45;
+       snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
+
+       ret = mdio_register(mdiodev);
+       if (ret)
+               goto err_mdio_register;
+
+       priv->etha.bus = miiphy_get_dev_by_name(dev->name);
+
+       ret = rswitch_phy_config(dev);
+       if (ret)
+               goto err_mdio_register;
+
+       return 0;
+
+err_mdio_register:
+       mdio_free(mdiodev);
+       return ret;
+}
+
+static int rswitch_port_remove(struct udevice *dev)
+{
+       struct rswitch_port_priv *priv = dev_get_priv(dev);
+
+       mdio_unregister(priv->etha.bus);
+       free(priv->etha.phydev);
+
+       return 0;
+}
+
+int rswitch_ofdata_to_platdata(struct udevice *dev)
+{
+       struct eth_pdata *pdata = dev_get_plat(dev);
+
+       pdata->phy_interface = dev_read_phy_mode(dev);
+       if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
+               return -EINVAL;
+
+       pdata->max_speed = dev_read_u32_default(dev, "max-speed", 1000);
+
+       return 0;
+}
+
+static const struct eth_ops rswitch_port_ops = {
+       .start          = rswitch_start,
+       .send           = rswitch_send,
+       .recv           = rswitch_recv,
+       .free_pkt       = rswitch_free_pkt,
+       .stop           = rswitch_stop,
+       .write_hwaddr   = rswitch_write_hwaddr,
+};
+
+U_BOOT_DRIVER(rswitch_port) = {
+       .name           = "rswitch-port",
+       .id             = UCLASS_ETH,
+       .of_to_plat     = rswitch_ofdata_to_platdata,
+       .probe          = rswitch_port_probe,
+       .remove         = rswitch_port_remove,
+       .ops            = &rswitch_port_ops,
+       .priv_auto      = sizeof(struct rswitch_port_priv),
+       .plat_auto      = sizeof(struct eth_pdata),
+       .flags          = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_OS_PREPARE,
+};
+
+static int rswitch_probe(struct udevice *dev)
+{
+       struct rswitch_priv *priv = dev_get_plat(dev);
+       fdt_addr_t secure_base;
+       fdt_size_t size;
+       int ret;
+
+       secure_base = dev_read_addr_size_name(dev, "secure_base", &size);
+       if (!secure_base)
+               return -EINVAL;
+
+       priv->addr = map_physmem(secure_base, size, MAP_NOCACHE);
+       if (!priv->addr)
+               return -EINVAL;
+
+       priv->rsw_clk = devm_clk_get(dev, NULL);
+       if (ret)
+               goto err_map;
+
+       ret = clk_prepare_enable(priv->rsw_clk);
+       if (ret)
+               goto err_map;
+
+       return 0;
+
+err_map:
+       unmap_physmem(priv->addr, MAP_NOCACHE);
+       return ret;
+}
+
+static int rswitch_remove(struct udevice *dev)
+{
+       struct rswitch_priv *priv = dev_get_plat(dev);
+
+       clk_disable_unprepare(priv->rsw_clk);
+       unmap_physmem(priv->addr, MAP_NOCACHE);
+
+       return 0;
+}
+
+static int rswitch_bind(struct udevice *parent)
+{
+       struct rswitch_port_priv *priv = dev_get_plat(parent);
+       ofnode ports_np, node;
+       struct udevice *dev;
+       struct driver *drv;
+       int ret;
+
+       drv = lists_driver_lookup_name("rswitch-port");
+       if (!drv)
+               return -ENOENT;
+
+       ports_np = dev_read_subnode(parent, "ethernet-ports");
+       if (!ofnode_valid(ports_np))
+               return -ENOENT;
+
+       ofnode_for_each_subnode(node, ports_np) {
+               ret = device_bind_with_driver_data(parent, drv,
+                                                  ofnode_get_name(node),
+                                                  (ulong)priv, node, &dev);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+
+static const struct udevice_id rswitch_ids[] = {
+       { .compatible = "renesas,r8a779f0-ether-switch" },
+       { }
+};
+
+U_BOOT_DRIVER(rswitch) = {
+       .name           = "rswitch",
+       .id             = UCLASS_NOP,
+       .of_match       = rswitch_ids,
+       .bind           = rswitch_bind,
+       .probe          = rswitch_probe,
+       .remove         = rswitch_remove,
+       .plat_auto      = sizeof(struct rswitch_priv),
+};

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index e800a32..04c3274 100644 (file)
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -127,12 +127,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-enum emac_variant {
-       A83T_EMAC = 1,
-       H3_EMAC,
-       A64_EMAC,
-       R40_GMAC,
-       H6_EMAC,
+struct emac_variant {
+       uint                    syscon_offset;
+       bool                    soc_has_internal_phy;
+       bool                    support_rmii;
 };
 
 struct emac_dma_desc {
@@ -160,9 +158,9 @@ struct emac_eth_dev {
        u32 tx_slot;
        bool use_internal_phy;
 
-       enum emac_variant variant;
+       const struct emac_variant *variant;
        void *mac_reg;
-       phys_addr_t sysctl_reg;
+       void *sysctl_reg;
        struct phy_device *phydev;
        struct mii_dev *bus;
        struct clk tx_clk;
@@ -317,25 +315,12 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
 {
        u32 reg;
 
-       if (priv->variant == R40_GMAC) {
-               /* Select RGMII for R40 */
-               reg = readl(priv->sysctl_reg + 0x164);
-               reg |= SC_ETCS_INT_GMII |
-                      SC_EPIT |
-                      (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);
-
-               writel(reg, priv->sysctl_reg + 0x164);
-               return 0;
-       }
-
-       reg = readl(priv->sysctl_reg + 0x30);
+       reg = readl(priv->sysctl_reg);
 
        reg = sun8i_emac_set_syscon_ephy(priv, reg);
 
        reg &= ~(SC_ETCS_MASK | SC_EPIT);
-       if (priv->variant == H3_EMAC ||
-           priv->variant == A64_EMAC ||
-           priv->variant == H6_EMAC)
+       if (priv->variant->support_rmii)
                reg &= ~SC_RMII_EN;
 
        switch (priv->interface) {
@@ -349,13 +334,10 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
                reg |= SC_EPIT | SC_ETCS_INT_GMII;
                break;
        case PHY_INTERFACE_MODE_RMII:
-               if (priv->variant == H3_EMAC ||
-                   priv->variant == A64_EMAC ||
-                   priv->variant == H6_EMAC) {
+               if (priv->variant->support_rmii) {
                        reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
-               break;
+                       break;
                }
-               /* RMII not supported on A83T */
        default:
                debug("%s: Invalid PHY interface\n", __func__);
                return -EINVAL;
@@ -369,7 +351,7 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
                reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
                         & SC_ERXDC_MASK;
 
-       writel(reg, priv->sysctl_reg + 0x30);
+       writel(reg, priv->sysctl_reg);
 
        return 0;
 }
@@ -792,6 +774,7 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
        struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
        struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
        struct emac_eth_dev *priv = dev_get_priv(dev);
+       phys_addr_t syscon_base;
        const fdt32_t *reg;
        int node = dev_of_offset(dev);
        int offset = 0;
@@ -806,7 +789,7 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
                return -EINVAL;
        }
 
-       priv->variant = dev_get_driver_data(dev);
+       priv->variant = (const void *)dev_get_driver_data(dev);
 
        if (!priv->variant) {
                printf("%s: Missing variant\n", __func__);
@@ -837,13 +820,15 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
                      __func__);
                return -EINVAL;
        }
-       priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
-                                                offset, reg);
-       if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
+
+       syscon_base = fdt_translate_address((void *)gd->fdt_blob, offset, reg);
+       if (syscon_base == FDT_ADDR_T_NONE) {
                debug("%s: Cannot find syscon base address\n", __func__);
                return -EINVAL;
        }
 
+       priv->sysctl_reg = (void *)syscon_base + priv->variant->syscon_offset;
+
        pdata->phy_interface = -1;
        priv->phyaddr = -1;
        priv->use_internal_phy = false;
@@ -860,7 +845,7 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
        if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
                return -EINVAL;
 
-       if (priv->variant == H3_EMAC) {
+       if (priv->variant->soc_has_internal_phy) {
                ret = sun8i_handle_internal_phy(dev, priv);
                if (ret)
                        return ret;
@@ -900,16 +885,41 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
        return 0;
 }
 
+static const struct emac_variant emac_variant_a83t = {
+       .syscon_offset          = 0x30,
+};
+
+static const struct emac_variant emac_variant_h3 = {
+       .syscon_offset          = 0x30,
+       .soc_has_internal_phy   = true,
+       .support_rmii           = true,
+};
+
+static const struct emac_variant emac_variant_r40 = {
+       .syscon_offset          = 0x164,
+};
+
+static const struct emac_variant emac_variant_a64 = {
+       .syscon_offset          = 0x30,
+       .support_rmii           = true,
+};
+
+static const struct emac_variant emac_variant_h6 = {
+       .syscon_offset          = 0x30,
+       .support_rmii           = true,
+};
+
 static const struct udevice_id sun8i_emac_eth_ids[] = {
-       {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
-       {.compatible = "allwinner,sun50i-a64-emac",
-               .data = (uintptr_t)A64_EMAC },
-       {.compatible = "allwinner,sun8i-a83t-emac",
-               .data = (uintptr_t)A83T_EMAC },
-       {.compatible = "allwinner,sun8i-r40-gmac",
-               .data = (uintptr_t)R40_GMAC },
-       {.compatible = "allwinner,sun50i-h6-emac",
-               .data = (uintptr_t)H6_EMAC },
+       { .compatible = "allwinner,sun8i-a83t-emac",
+         .data = (ulong)&emac_variant_a83t },
+       { .compatible = "allwinner,sun8i-h3-emac",
+         .data = (ulong)&emac_variant_h3 },
+       { .compatible = "allwinner,sun8i-r40-gmac",
+         .data = (ulong)&emac_variant_r40 },
+       { .compatible = "allwinner,sun50i-a64-emac",
+         .data = (ulong)&emac_variant_a64 },
+       { .compatible = "allwinner,sun50i-h6-emac",
+         .data = (ulong)&emac_variant_h6 },
        { }
 };
 

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index cf4d590..7a2d54f 100644 (file)
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -285,5 +285,6 @@ source "drivers/phy/rockchip/Kconfig"
 source "drivers/phy/cadence/Kconfig"
 source "drivers/phy/ti/Kconfig"
 source "drivers/phy/qcom/Kconfig"
+source "drivers/phy/renesas/Kconfig"
 
 endmenu

diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index a3b9f3c..aca365d 100644 (file)
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -41,3 +41,4 @@ obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o
 obj-y += cadence/
 obj-y += ti/
 obj-y += qcom/
+obj-y += renesas/

diff --git a/drivers/phy/phy-ti-am654.c b/drivers/phy/phy-ti-am654.c
index 27a3122..70a746d 100644 (file)
--- a/drivers/phy/phy-ti-am654.c
+++ b/drivers/phy/phy-ti-am654.c
@@ -16,7 +16,6 @@
 #include <dt-bindings/phy/phy.h>
 #include <generic-phy.h>
 #include <asm/io.h>
-#include <asm/arch/sys_proto.h>
 #include <power-domain.h>
 #include <regmap.h>
 #include <syscon.h>

diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c
index 3fef513..83e4b63 100644 (file)
--- a/drivers/phy/phy-uclass.c
+++ b/drivers/phy/phy-uclass.c
@@ -351,6 +351,28 @@ int generic_phy_configure(struct phy *phy, void *params)
        return ops->configure ? ops->configure(phy, params) : 0;
 }
 
+int generic_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
+{
+       struct phy_ops const *ops;
+
+       if (!generic_phy_valid(phy))
+               return 0;
+       ops = phy_dev_ops(phy->dev);
+
+       return ops->set_mode ? ops->set_mode(phy, mode, submode) : 0;
+}
+
+int generic_phy_set_speed(struct phy *phy, int speed)
+{
+       struct phy_ops const *ops;
+
+       if (!generic_phy_valid(phy))
+               return 0;
+       ops = phy_dev_ops(phy->dev);
+
+       return ops->set_speed ? ops->set_speed(phy, speed) : 0;
+}
+
 int generic_phy_get_bulk(struct udevice *dev, struct phy_bulk *bulk)
 {
        int i, ret, count;

diff --git a/drivers/phy/renesas/Kconfig b/drivers/phy/renesas/Kconfig
new file mode 100644 (file)
index 0000000..0efb0f8
--- /dev/null
+++ b/drivers/phy/renesas/Kconfig
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Phy drivers for Renesas platforms
+
+config PHY_R8A779F0_ETHERNET_SERDES
+       tristate "Renesas R-Car S4-8 Ethernet SERDES driver"
+       depends on RCAR_64 && PHY
+       help
+         Support for Ethernet SERDES found on Renesas R-Car S4-8 SoCs.

diff --git a/drivers/phy/renesas/Makefile b/drivers/phy/renesas/Makefile
new file mode 100644 (file)
index 0000000..fd6b8d9
--- /dev/null
+++ b/drivers/phy/renesas/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PHY_R8A779F0_ETHERNET_SERDES)     += r8a779f0-ether-serdes.o

diff --git a/drivers/phy/renesas/r8a779f0-ether-serdes.c b/drivers/phy/renesas/r8a779f0-ether-serdes.c
new file mode 100644 (file)
index 0000000..bd1fdd3
--- /dev/null
+++ b/drivers/phy/renesas/r8a779f0-ether-serdes.c
@@ -0,0 +1,384 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Renesas Ethernet SERDES device driver
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <clk.h>
+#include <common.h>
+#include <div64.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <dm/of_access.h>
+#include <generic-phy.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include <log.h>
+#include <reset.h>
+#include <syscon.h>
+
+#define R8A779F0_ETH_SERDES_NUM                        3
+#define R8A779F0_ETH_SERDES_OFFSET             0x0400
+#define R8A779F0_ETH_SERDES_BANK_SELECT                0x03fc
+#define R8A779F0_ETH_SERDES_TIMEOUT_US         100000
+#define R8A779F0_ETH_SERDES_NUM_RETRY_LINKUP   3
+
+struct r8a779f0_eth_serdes_drv_data;
+struct r8a779f0_eth_serdes_channel {
+       struct r8a779f0_eth_serdes_drv_data *dd;
+       struct phy *phy;
+       void __iomem *addr;
+       phy_interface_t phy_interface;
+       int speed;
+       int index;
+};
+
+struct r8a779f0_eth_serdes_drv_data {
+       void __iomem *addr;
+       struct reset_ctl *reset;
+       struct r8a779f0_eth_serdes_channel channel[R8A779F0_ETH_SERDES_NUM];
+       bool initialized;
+};
+
+/*
+ * The datasheet describes initialization procedure without any information
+ * about registers' name/bits. So, this is all black magic to initialize
+ * the hardware.
+ */
+static void r8a779f0_eth_serdes_write32(void __iomem *addr, u32 offs, u32 bank, u32 data)
+{
+       writel(bank, addr + R8A779F0_ETH_SERDES_BANK_SELECT);
+       writel(data, addr + offs);
+}
+
+static int
+r8a779f0_eth_serdes_reg_wait(struct r8a779f0_eth_serdes_channel *channel,
+                            u32 offs, u32 bank, u32 mask, u32 expected)
+{
+       u32 val = 0;
+       int ret;
+
+       writel(bank, channel->addr + R8A779F0_ETH_SERDES_BANK_SELECT);
+
+       ret = readl_poll_timeout(channel->addr + offs, val,
+                                (val & mask) == expected,
+                                R8A779F0_ETH_SERDES_TIMEOUT_US);
+       if (ret)
+               dev_dbg(channel->phy->dev,
+                       "%s: index %d, offs %x, bank %x, mask %x, expected %x\n",
+                        __func__, channel->index, offs, bank, mask, expected);
+
+       return ret;
+}
+
+static int
+r8a779f0_eth_serdes_common_init_ram(struct r8a779f0_eth_serdes_drv_data *dd)
+{
+       struct r8a779f0_eth_serdes_channel *channel;
+       int i, ret;
+
+       for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) {
+               channel = &dd->channel[i];
+               ret = r8a779f0_eth_serdes_reg_wait(channel, 0x026c, 0x180, BIT(0), 0x01);
+               if (ret)
+                       return ret;
+       }
+
+       r8a779f0_eth_serdes_write32(dd->addr, 0x026c, 0x180, 0x03);
+
+       return ret;
+}
+
+static int
+r8a779f0_eth_serdes_common_setting(struct r8a779f0_eth_serdes_channel *channel)
+{
+       struct r8a779f0_eth_serdes_drv_data *dd = channel->dd;
+
+       switch (channel->phy_interface) {
+       case PHY_INTERFACE_MODE_SGMII:
+               r8a779f0_eth_serdes_write32(dd->addr, 0x0244, 0x180, 0x0097);
+               r8a779f0_eth_serdes_write32(dd->addr, 0x01d0, 0x180, 0x0060);
+               r8a779f0_eth_serdes_write32(dd->addr, 0x01d8, 0x180, 0x2200);
+               r8a779f0_eth_serdes_write32(dd->addr, 0x01d4, 0x180, 0x0000);
+               r8a779f0_eth_serdes_write32(dd->addr, 0x01e0, 0x180, 0x003d);
+               return 0;
+       default:
+               return -EOPNOTSUPP;
+       }
+}
+
+static int
+r8a779f0_eth_serdes_chan_setting(struct r8a779f0_eth_serdes_channel *channel)
+{
+       int ret;
+
+       switch (channel->phy_interface) {
+       case PHY_INTERFACE_MODE_SGMII:
+               r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2000);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x01c0, 0x180, 0x0011);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x0248, 0x180, 0x0540);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x0258, 0x180, 0x0015);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x0144, 0x180, 0x0100);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x01a0, 0x180, 0x0000);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x00d0, 0x180, 0x0002);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x0150, 0x180, 0x0003);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x00c8, 0x180, 0x0100);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x0148, 0x180, 0x0100);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x0174, 0x180, 0x0000);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x0160, 0x180, 0x0007);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x01ac, 0x180, 0x0000);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x00c4, 0x180, 0x0310);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x00c8, 0x180, 0x0101);
+               ret = r8a779f0_eth_serdes_reg_wait(channel, 0x00c8, 0x0180, BIT(0), 0);
+               if (ret)
+                       return ret;
+
+               r8a779f0_eth_serdes_write32(channel->addr, 0x0148, 0x180, 0x0101);
+               ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0148, 0x0180, BIT(0), 0);
+               if (ret)
+                       return ret;
+
+               r8a779f0_eth_serdes_write32(channel->addr, 0x00c4, 0x180, 0x1310);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x00d8, 0x180, 0x1800);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x00dc, 0x180, 0x0000);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x001c, 0x300, 0x0001);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2100);
+               ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0000, 0x0380, BIT(8), 0);
+               if (ret)
+                       return ret;
+
+               if (channel->speed == 1000)
+                       r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x0140);
+               else if (channel->speed == 100)
+                       r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x2100);
+
+               /* For AN_ON */
+               r8a779f0_eth_serdes_write32(channel->addr, 0x0004, 0x1f80, 0x0005);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x0028, 0x1f80, 0x07a1);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f80, 0x0208);
+               break;
+       default:
+               return -EOPNOTSUPP;
+       }
+
+       return 0;
+}
+
+static int
+r8a779f0_eth_serdes_chan_speed(struct r8a779f0_eth_serdes_channel *channel)
+{
+       int ret;
+
+       switch (channel->phy_interface) {
+       case PHY_INTERFACE_MODE_SGMII:
+               /* For AN_ON */
+               if (channel->speed == 1000)
+                       r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x1140);
+               else if (channel->speed == 100)
+                       r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x3100);
+               ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0008, 0x1f80, BIT(0), 1);
+               if (ret)
+                       return ret;
+               r8a779f0_eth_serdes_write32(channel->addr, 0x0008, 0x1f80, 0x0000);
+               break;
+       default:
+               return -EOPNOTSUPP;
+       }
+
+       return 0;
+}
+
+static int r8a779f0_eth_serdes_monitor_linkup(struct r8a779f0_eth_serdes_channel *channel)
+{
+       int i, ret;
+
+       for (i = 0; i < R8A779F0_ETH_SERDES_NUM_RETRY_LINKUP; i++) {
+               ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0004, 0x300,
+                                                  BIT(2), BIT(2));
+               if (!ret)
+                       break;
+
+               /* restart */
+               r8a779f0_eth_serdes_write32(channel->addr, 0x0144, 0x180, 0x0100);
+               udelay(1);
+               r8a779f0_eth_serdes_write32(channel->addr, 0x0144, 0x180, 0x0000);
+       }
+
+       return ret;
+}
+
+static int r8a779f0_eth_serdes_hw_init(struct r8a779f0_eth_serdes_channel *channel)
+{
+       struct r8a779f0_eth_serdes_drv_data *dd = channel->dd;
+       int i, ret;
+
+       if (dd->initialized)
+               return 0;
+
+       ret = r8a779f0_eth_serdes_common_init_ram(dd);
+       if (ret)
+               return ret;
+
+       for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) {
+               ret = r8a779f0_eth_serdes_reg_wait(&dd->channel[i], 0x0000,
+                                                  0x300, BIT(15), 0);
+               if (ret)
+                       return ret;
+       }
+
+       for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++)
+               r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03d4, 0x380, 0x0443);
+
+       ret = r8a779f0_eth_serdes_common_setting(channel);
+       if (ret)
+               return ret;
+
+       for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++)
+               r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03d0, 0x380, 0x0001);
+
+       r8a779f0_eth_serdes_write32(dd->addr, 0x0000, 0x380, 0x8000);
+
+       ret = r8a779f0_eth_serdes_common_init_ram(dd);
+       if (ret)
+               return ret;
+
+       return r8a779f0_eth_serdes_reg_wait(&dd->channel[0], 0x0000, 0x380, BIT(15), 0);
+}
+
+static int r8a779f0_eth_serdes_init(struct phy *p)
+{
+       struct r8a779f0_eth_serdes_drv_data *dd = dev_get_priv(p->dev);
+       struct r8a779f0_eth_serdes_channel *channel = dd->channel + p->id;
+       int ret;
+
+       ret = r8a779f0_eth_serdes_hw_init(channel);
+       if (!ret)
+               channel->dd->initialized = true;
+
+       return ret;
+}
+
+static int r8a779f0_eth_serdes_hw_init_late(struct r8a779f0_eth_serdes_channel *channel)
+{
+       int ret;
+
+       ret = r8a779f0_eth_serdes_chan_setting(channel);
+       if (ret)
+               return ret;
+
+       ret = r8a779f0_eth_serdes_chan_speed(channel);
+       if (ret)
+               return ret;
+
+       r8a779f0_eth_serdes_write32(channel->addr, 0x03c0, 0x380, 0x0000);
+
+       r8a779f0_eth_serdes_write32(channel->addr, 0x03d0, 0x380, 0x0000);
+
+       return r8a779f0_eth_serdes_monitor_linkup(channel);
+}
+
+static int r8a779f0_eth_serdes_power_on(struct phy *p)
+{
+       struct r8a779f0_eth_serdes_drv_data *dd = dev_get_priv(p->dev);
+       struct r8a779f0_eth_serdes_channel *channel = dd->channel + p->id;
+
+       return r8a779f0_eth_serdes_hw_init_late(channel);
+}
+
+static int r8a779f0_eth_serdes_set_mode(struct phy *p, enum phy_mode mode,
+                                       int submode)
+{
+       struct r8a779f0_eth_serdes_drv_data *dd = dev_get_priv(p->dev);
+       struct r8a779f0_eth_serdes_channel *channel = dd->channel + p->id;
+
+       if (mode != PHY_MODE_ETHERNET)
+               return -EOPNOTSUPP;
+
+       switch (submode) {
+       case PHY_INTERFACE_MODE_GMII:
+       case PHY_INTERFACE_MODE_SGMII:
+       case PHY_INTERFACE_MODE_USXGMII:
+               channel->phy_interface = submode;
+               return 0;
+       default:
+               return -EOPNOTSUPP;
+       }
+}
+
+static int r8a779f0_eth_serdes_set_speed(struct phy *p, int speed)
+{
+       struct r8a779f0_eth_serdes_drv_data *dd = dev_get_priv(p->dev);
+       struct r8a779f0_eth_serdes_channel *channel = dd->channel + p->id;
+
+       channel->speed = speed;
+
+       return 0;
+}
+
+static int r8a779f0_eth_serdes_of_xlate(struct phy *phy,
+                                       struct ofnode_phandle_args *args)
+{
+       if (args->args_count < 1)
+               return -ENODEV;
+
+       if (args->args[0] >= R8A779F0_ETH_SERDES_NUM)
+               return -ENODEV;
+
+       phy->id = args->args[0];
+
+       return 0;
+}
+
+static const struct phy_ops r8a779f0_eth_serdes_ops = {
+       .init           = r8a779f0_eth_serdes_init,
+       .power_on       = r8a779f0_eth_serdes_power_on,
+       .set_mode       = r8a779f0_eth_serdes_set_mode,
+       .set_speed      = r8a779f0_eth_serdes_set_speed,
+       .of_xlate       = r8a779f0_eth_serdes_of_xlate,
+};
+
+static const struct udevice_id r8a779f0_eth_serdes_of_table[] = {
+       { .compatible = "renesas,r8a779f0-ether-serdes", },
+       { }
+};
+
+static int r8a779f0_eth_serdes_probe(struct udevice *dev)
+{
+       struct r8a779f0_eth_serdes_drv_data *dd = dev_get_priv(dev);
+       int i;
+
+       dd->addr = dev_read_addr_ptr(dev);
+       if (!dd->addr)
+               return -EINVAL;
+
+       dd->reset = devm_reset_control_get(dev, NULL);
+       if (IS_ERR(dd->reset))
+               return PTR_ERR(dd->reset);
+
+       reset_assert(dd->reset);
+       reset_deassert(dd->reset);
+
+       for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) {
+               struct r8a779f0_eth_serdes_channel *channel = &dd->channel[i];
+
+               channel->addr = dd->addr + R8A779F0_ETH_SERDES_OFFSET * i;
+               channel->dd = dd;
+               channel->index = i;
+       }
+
+       return 0;
+}
+
+U_BOOT_DRIVER(r8a779f0_eth_serdes_driver_platform) = {
+       .name           = "r8a779f0_eth_serdes",
+       .id             = UCLASS_PHY,
+       .of_match       = r8a779f0_eth_serdes_of_table,
+       .probe          = r8a779f0_eth_serdes_probe,
+       .ops            = &r8a779f0_eth_serdes_ops,
+       .priv_auto      = sizeof(struct r8a779f0_eth_serdes_drv_data),
+};

diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index 1305763..f87ca8c 100644 (file)
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -4,6 +4,14 @@
 
 menu "Rockchip PHY driver"
 
+config PHY_ROCKCHIP_INNO_DSIDPHY
+       bool "Rockchip INNO DSIDPHY Driver"
+       depends on ARCH_ROCKCHIP
+       select PHY
+       select MIPI_DPHY_HELPERS
+       help
+         Support for Rockchip MIPI DPHY with Innosilicon IP block.
+
 config PHY_ROCKCHIP_INNO_USB2
        bool "Rockchip INNO USB2PHY Driver"
        depends on ARCH_ROCKCHIP

diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index a236877..25a803a 100644 (file)
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY) += phy-rockchip-naneng-combphy.o
 obj-$(CONFIG_PHY_ROCKCHIP_PCIE)                += phy-rockchip-pcie.o
 obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3)  += phy-rockchip-snps-pcie3.o
 obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)       += phy-rockchip-typec.o
+obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)        += phy-rockchip-inno-dsidphy.o

diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
new file mode 100644 (file)
index 0000000..9ed7af0
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
@@ -0,0 +1,680 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
+ *
+ * Author: Wyon Bi <bivvy.bi@rock-chips.com>
+ */
+
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <div64.h>
+#include <generic-phy.h>
+#include <linux/kernel.h>
+#include <linux/iopoll.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/math64.h>
+#include <phy-mipi-dphy.h>
+#include <reset.h>
+
+#define UPDATE(x, h, l)        (((x) << (l)) & GENMASK((h), (l)))
+
+/*
+ * The offset address[7:0] is distributed two parts, one from the bit7 to bit5
+ * is the first address, the other from the bit4 to bit0 is the second address.
+ * when you configure the registers, you must set both of them. The Clock Lane
+ * and Data Lane use the same registers with the same second address, but the
+ * first address is different.
+ */
+#define FIRST_ADDRESS(x)               (((x) & 0x7) << 5)
+#define SECOND_ADDRESS(x)              (((x) & 0x1f) << 0)
+#define PHY_REG(first, second)         (FIRST_ADDRESS(first) | \
+                                        SECOND_ADDRESS(second))
+
+/* Analog Register Part: reg00 */
+#define BANDGAP_POWER_MASK                     BIT(7)
+#define BANDGAP_POWER_DOWN                     BIT(7)
+#define BANDGAP_POWER_ON                       0
+#define LANE_EN_MASK                           GENMASK(6, 2)
+#define LANE_EN_CK                             BIT(6)
+#define LANE_EN_3                              BIT(5)
+#define LANE_EN_2                              BIT(4)
+#define LANE_EN_1                              BIT(3)
+#define LANE_EN_0                              BIT(2)
+#define POWER_WORK_MASK                                GENMASK(1, 0)
+#define POWER_WORK_ENABLE                      UPDATE(1, 1, 0)
+#define POWER_WORK_DISABLE                     UPDATE(2, 1, 0)
+/* Analog Register Part: reg01 */
+#define REG_SYNCRST_MASK                       BIT(2)
+#define REG_SYNCRST_RESET                      BIT(2)
+#define REG_SYNCRST_NORMAL                     0
+#define REG_LDOPD_MASK                         BIT(1)
+#define REG_LDOPD_POWER_DOWN                   BIT(1)
+#define REG_LDOPD_POWER_ON                     0
+#define REG_PLLPD_MASK                         BIT(0)
+#define REG_PLLPD_POWER_DOWN                   BIT(0)
+#define REG_PLLPD_POWER_ON                     0
+/* Analog Register Part: reg03 */
+#define REG_FBDIV_HI_MASK                      BIT(5)
+#define REG_FBDIV_HI(x)                                UPDATE((x >> 8), 5, 5)
+#define REG_PREDIV_MASK                                GENMASK(4, 0)
+#define REG_PREDIV(x)                          UPDATE(x, 4, 0)
+/* Analog Register Part: reg04 */
+#define REG_FBDIV_LO_MASK                      GENMASK(7, 0)
+#define REG_FBDIV_LO(x)                                UPDATE(x, 7, 0)
+/* Analog Register Part: reg05 */
+#define SAMPLE_CLOCK_PHASE_MASK                        GENMASK(6, 4)
+#define SAMPLE_CLOCK_PHASE(x)                  UPDATE(x, 6, 4)
+#define CLOCK_LANE_SKEW_PHASE_MASK             GENMASK(2, 0)
+#define CLOCK_LANE_SKEW_PHASE(x)               UPDATE(x, 2, 0)
+/* Analog Register Part: reg06 */
+#define DATA_LANE_3_SKEW_PHASE_MASK            GENMASK(6, 4)
+#define DATA_LANE_3_SKEW_PHASE(x)              UPDATE(x, 6, 4)
+#define DATA_LANE_2_SKEW_PHASE_MASK            GENMASK(2, 0)
+#define DATA_LANE_2_SKEW_PHASE(x)              UPDATE(x, 2, 0)
+/* Analog Register Part: reg07 */
+#define DATA_LANE_1_SKEW_PHASE_MASK            GENMASK(6, 4)
+#define DATA_LANE_1_SKEW_PHASE(x)              UPDATE(x, 6, 4)
+#define DATA_LANE_0_SKEW_PHASE_MASK            GENMASK(2, 0)
+#define DATA_LANE_0_SKEW_PHASE(x)              UPDATE(x, 2, 0)
+/* Analog Register Part: reg08 */
+#define PLL_POST_DIV_ENABLE_MASK               BIT(5)
+#define PLL_POST_DIV_ENABLE                    BIT(5)
+#define SAMPLE_CLOCK_DIRECTION_MASK            BIT(4)
+#define SAMPLE_CLOCK_DIRECTION_REVERSE         BIT(4)
+#define SAMPLE_CLOCK_DIRECTION_FORWARD         0
+#define LOWFRE_EN_MASK                         BIT(5)
+#define PLL_OUTPUT_FREQUENCY_DIV_BY_1          0
+#define PLL_OUTPUT_FREQUENCY_DIV_BY_2          1
+/* Analog Register Part: reg0b */
+#define CLOCK_LANE_VOD_RANGE_SET_MASK          GENMASK(3, 0)
+#define CLOCK_LANE_VOD_RANGE_SET(x)            UPDATE(x, 3, 0)
+#define VOD_MIN_RANGE                          0x1
+#define VOD_MID_RANGE                          0x3
+#define VOD_BIG_RANGE                          0x7
+#define VOD_MAX_RANGE                          0xf
+/* Analog Register Part: reg1E */
+#define PLL_MODE_SEL_MASK                      GENMASK(6, 5)
+#define PLL_MODE_SEL_LVDS_MODE                 0
+#define PLL_MODE_SEL_MIPI_MODE                 BIT(5)
+/* Digital Register Part: reg00 */
+#define REG_DIG_RSTN_MASK                      BIT(0)
+#define REG_DIG_RSTN_NORMAL                    BIT(0)
+#define REG_DIG_RSTN_RESET                     0
+/* Digital Register Part: reg01 */
+#define INVERT_TXCLKESC_MASK                   BIT(1)
+#define INVERT_TXCLKESC_ENABLE                 BIT(1)
+#define INVERT_TXCLKESC_DISABLE                        0
+#define INVERT_TXBYTECLKHS_MASK                        BIT(0)
+#define INVERT_TXBYTECLKHS_ENABLE              BIT(0)
+#define INVERT_TXBYTECLKHS_DISABLE             0
+/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */
+#define T_LPX_CNT_MASK                         GENMASK(5, 0)
+#define T_LPX_CNT(x)                           UPDATE(x, 5, 0)
+/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */
+#define T_HS_ZERO_CNT_HI_MASK                  BIT(7)
+#define T_HS_ZERO_CNT_HI(x)                    UPDATE(x, 7, 7)
+#define T_HS_PREPARE_CNT_MASK                  GENMASK(6, 0)
+#define T_HS_PREPARE_CNT(x)                    UPDATE(x, 6, 0)
+/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */
+#define T_HS_ZERO_CNT_LO_MASK                  GENMASK(5, 0)
+#define T_HS_ZERO_CNT_LO(x)                    UPDATE(x, 5, 0)
+/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */
+#define T_HS_TRAIL_CNT_MASK                    GENMASK(6, 0)
+#define T_HS_TRAIL_CNT(x)                      UPDATE(x, 6, 0)
+/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */
+#define T_HS_EXIT_CNT_LO_MASK                  GENMASK(4, 0)
+#define T_HS_EXIT_CNT_LO(x)                    UPDATE(x, 4, 0)
+/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */
+#define T_CLK_POST_CNT_LO_MASK                 GENMASK(3, 0)
+#define T_CLK_POST_CNT_LO(x)                   UPDATE(x, 3, 0)
+/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */
+#define LPDT_TX_PPI_SYNC_MASK                  BIT(2)
+#define LPDT_TX_PPI_SYNC_ENABLE                        BIT(2)
+#define LPDT_TX_PPI_SYNC_DISABLE               0
+#define T_WAKEUP_CNT_HI_MASK                   GENMASK(1, 0)
+#define T_WAKEUP_CNT_HI(x)                     UPDATE(x, 1, 0)
+/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */
+#define T_WAKEUP_CNT_LO_MASK                   GENMASK(7, 0)
+#define T_WAKEUP_CNT_LO(x)                     UPDATE(x, 7, 0)
+/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */
+#define T_CLK_PRE_CNT_MASK                     GENMASK(3, 0)
+#define T_CLK_PRE_CNT(x)                       UPDATE(x, 3, 0)
+/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */
+#define T_CLK_POST_CNT_HI_MASK                 GENMASK(7, 6)
+#define T_CLK_POST_CNT_HI(x)                   UPDATE(x, 7, 6)
+#define T_TA_GO_CNT_MASK                       GENMASK(5, 0)
+#define T_TA_GO_CNT(x)                         UPDATE(x, 5, 0)
+/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */
+#define T_HS_EXIT_CNT_HI_MASK                  BIT(6)
+#define T_HS_EXIT_CNT_HI(x)                    UPDATE(x, 6, 6)
+#define T_TA_SURE_CNT_MASK                     GENMASK(5, 0)
+#define T_TA_SURE_CNT(x)                       UPDATE(x, 5, 0)
+/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */
+#define T_TA_WAIT_CNT_MASK                     GENMASK(5, 0)
+#define T_TA_WAIT_CNT(x)                       UPDATE(x, 5, 0)
+/* LVDS Register Part: reg00 */
+#define LVDS_DIGITAL_INTERNAL_RESET_MASK       BIT(2)
+#define LVDS_DIGITAL_INTERNAL_RESET_DISABLE    BIT(2)
+#define LVDS_DIGITAL_INTERNAL_RESET_ENABLE     0
+/* LVDS Register Part: reg01 */
+#define LVDS_DIGITAL_INTERNAL_ENABLE_MASK      BIT(7)
+#define LVDS_DIGITAL_INTERNAL_ENABLE           BIT(7)
+#define LVDS_DIGITAL_INTERNAL_DISABLE          0
+/* LVDS Register Part: reg03 */
+#define MODE_ENABLE_MASK                       GENMASK(2, 0)
+#define TTL_MODE_ENABLE                                BIT(2)
+#define LVDS_MODE_ENABLE                       BIT(1)
+#define MIPI_MODE_ENABLE                       BIT(0)
+/* LVDS Register Part: reg0b */
+#define LVDS_LANE_EN_MASK                      GENMASK(7, 3)
+#define LVDS_DATA_LANE0_EN                     BIT(7)
+#define LVDS_DATA_LANE1_EN                     BIT(6)
+#define LVDS_DATA_LANE2_EN                     BIT(5)
+#define LVDS_DATA_LANE3_EN                     BIT(4)
+#define LVDS_CLK_LANE_EN                       BIT(3)
+#define LVDS_PLL_POWER_MASK                    BIT(2)
+#define LVDS_PLL_POWER_OFF                     BIT(2)
+#define LVDS_PLL_POWER_ON                      0
+#define LVDS_BANDGAP_POWER_MASK                        BIT(0)
+#define LVDS_BANDGAP_POWER_DOWN                        BIT(0)
+#define LVDS_BANDGAP_POWER_ON                  0
+
+#define DSI_PHY_RSTZ                           0xa0
+#define PHY_ENABLECLK                          BIT(2)
+#define DSI_PHY_STATUS                         0xb0
+#define PHY_LOCK                               BIT(0)
+
+#define PSEC_PER_SEC                           1000000000000LL
+
+#define msleep(a)                              udelay(a * 1000)
+
+enum phy_max_rate {
+       MAX_1GHZ,
+       MAX_2_5GHZ,
+};
+
+struct clk_hw {
+       struct clk_core *core;
+       struct clk *clk;
+       const struct clk_init_data *init;
+};
+
+struct inno_video_phy_plat_data {
+       const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table;
+       const unsigned int num_timings;
+       enum phy_max_rate max_rate;
+};
+
+struct inno_dsidphy {
+       struct udevice *dev;
+       struct clk *ref_clk;
+       struct clk *pclk_phy;
+       struct clk *pclk_host;
+       const struct inno_video_phy_plat_data *pdata;
+       void __iomem *phy_base;
+       void __iomem *host_base;
+       struct reset_ctl *rst;
+       struct phy_configure_opts_mipi_dphy dphy_cfg;
+
+       struct clk *pll_clk;
+       struct {
+               struct clk_hw hw;
+               u8 prediv;
+               u16 fbdiv;
+               unsigned long rate;
+       } pll;
+};
+
+enum {
+       REGISTER_PART_ANALOG,
+       REGISTER_PART_DIGITAL,
+       REGISTER_PART_CLOCK_LANE,
+       REGISTER_PART_DATA0_LANE,
+       REGISTER_PART_DATA1_LANE,
+       REGISTER_PART_DATA2_LANE,
+       REGISTER_PART_DATA3_LANE,
+       REGISTER_PART_LVDS,
+};
+
+struct inno_mipi_dphy_timing {
+       unsigned long rate;
+       u8 lpx;
+       u8 hs_prepare;
+       u8 clk_lane_hs_zero;
+       u8 data_lane_hs_zero;
+       u8 hs_trail;
+};
+
+static const
+struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1ghz[] = {
+       { 110000000, 0x0, 0x20, 0x16, 0x02, 0x22},
+       { 150000000, 0x0, 0x06, 0x16, 0x03, 0x45},
+       { 200000000, 0x0, 0x18, 0x17, 0x04, 0x0b},
+       { 250000000, 0x0, 0x05, 0x17, 0x05, 0x16},
+       { 300000000, 0x0, 0x51, 0x18, 0x06, 0x2c},
+       { 400000000, 0x0, 0x64, 0x19, 0x07, 0x33},
+       { 500000000, 0x0, 0x20, 0x1b, 0x07, 0x4e},
+       { 600000000, 0x0, 0x6a, 0x1d, 0x08, 0x3a},
+       { 700000000, 0x0, 0x3e, 0x1e, 0x08, 0x6a},
+       { 800000000, 0x0, 0x21, 0x1f, 0x09, 0x29},
+       {1000000000, 0x0, 0x09, 0x20, 0x09, 0x27},
+};
+
+static const
+struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5ghz[] = {
+       { 110000000, 0x02, 0x7f, 0x16, 0x02, 0x02},
+       { 150000000, 0x02, 0x7f, 0x16, 0x03, 0x02},
+       { 200000000, 0x02, 0x7f, 0x17, 0x04, 0x02},
+       { 250000000, 0x02, 0x7f, 0x17, 0x05, 0x04},
+       { 300000000, 0x02, 0x7f, 0x18, 0x06, 0x04},
+       { 400000000, 0x03, 0x7e, 0x19, 0x07, 0x04},
+       { 500000000, 0x03, 0x7c, 0x1b, 0x07, 0x08},
+       { 600000000, 0x03, 0x70, 0x1d, 0x08, 0x10},
+       { 700000000, 0x05, 0x40, 0x1e, 0x08, 0x30},
+       { 800000000, 0x05, 0x02, 0x1f, 0x09, 0x30},
+       {1000000000, 0x05, 0x08, 0x20, 0x09, 0x30},
+       {1200000000, 0x06, 0x03, 0x32, 0x14, 0x0f},
+       {1400000000, 0x09, 0x03, 0x32, 0x14, 0x0f},
+       {1600000000, 0x0d, 0x42, 0x36, 0x0e, 0x0f},
+       {1800000000, 0x0e, 0x47, 0x7a, 0x0e, 0x0f},
+       {2000000000, 0x11, 0x64, 0x7a, 0x0e, 0x0b},
+       {2200000000, 0x13, 0x64, 0x7e, 0x15, 0x0b},
+       {2400000000, 0x13, 0x33, 0x7f, 0x15, 0x6a},
+       {2500000000, 0x15, 0x54, 0x7f, 0x15, 0x6a},
+};
+
+static void phy_update_bits(struct inno_dsidphy *inno,
+                           u8 first, u8 second, u8 mask, u8 val)
+{
+       u32 reg = PHY_REG(first, second) << 2;
+       unsigned int tmp, orig;
+
+       orig = readl(inno->phy_base + reg);
+       tmp = orig & ~mask;
+       tmp |= val & mask;
+       writel(tmp, inno->phy_base + reg);
+}
+
+static unsigned long inno_dsidphy_pll_calc_rate(struct inno_dsidphy *inno,
+                                               unsigned long rate)
+{
+       unsigned long prate;
+       unsigned long best_freq = 0;
+       unsigned long fref, fout;
+       u8 min_prediv, max_prediv;
+       u8 _prediv, best_prediv = 1;
+       u16 _fbdiv, best_fbdiv = 1;
+       u32 min_delta = UINT_MAX;
+
+       /*
+        * Upstream Linux tries to read the ref_clk, while the BSP
+        * U-Boot hard-codes this as 24MHz. Try the first, and if that
+        * fails do the second.
+        */
+       prate = clk_get_rate(inno->ref_clk);
+       if (IS_ERR_VALUE(prate))
+               prate = 24000000;
+
+       /*
+        * The PLL output frequency can be calculated using a simple formula:
+        * PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2
+        * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2
+        */
+       fref = prate / 2;
+       if (rate > 1000000000UL)
+               fout = 1000000000UL;
+       else
+               fout = rate;
+
+       /* 5Mhz < Fref / prediv < 40MHz */
+       min_prediv = DIV_ROUND_UP(fref, 40000000);
+       max_prediv = fref / 5000000;
+
+       for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
+               u64 tmp;
+               u32 delta;
+
+               tmp = (u64)fout * _prediv;
+               do_div(tmp, fref);
+               _fbdiv = tmp;
+
+               /*
+                * The possible settings of feedback divider are
+                * 12, 13, 14, 16, ~ 511
+                */
+               if (_fbdiv == 15)
+                       continue;
+
+               if (_fbdiv < 12 || _fbdiv > 511)
+                       continue;
+
+               tmp = (u64)_fbdiv * fref;
+               do_div(tmp, _prediv);
+
+               delta = abs(fout - tmp);
+               if (!delta) {
+                       best_prediv = _prediv;
+                       best_fbdiv = _fbdiv;
+                       best_freq = tmp;
+                       break;
+               } else if (delta < min_delta) {
+                       best_prediv = _prediv;
+                       best_fbdiv = _fbdiv;
+                       best_freq = tmp;
+                       min_delta = delta;
+               }
+       }
+
+       if (best_freq) {
+               inno->pll.prediv = best_prediv;
+               inno->pll.fbdiv = best_fbdiv;
+               inno->pll.rate = best_freq;
+       }
+
+       return best_freq;
+}
+
+static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
+{
+       struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg;
+       const struct inno_mipi_dphy_timing *timings;
+       u32 t_txbyteclkhs, t_txclkesc;
+       u32 txbyteclkhs, txclkesc, esc_clk_div;
+       u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
+       u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero;
+       unsigned int i;
+
+       timings = inno->pdata->inno_mipi_dphy_timing_table;
+
+       inno_dsidphy_pll_calc_rate(inno, cfg->hs_clk_rate);
+
+       /* Select MIPI mode */
+       phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
+                       MODE_ENABLE_MASK, MIPI_MODE_ENABLE);
+       /* Configure PLL */
+       phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
+                       REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
+       phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
+                       REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv));
+       phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
+                       REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
+       if (inno->pdata->max_rate == MAX_2_5GHZ) {
+               phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
+                               PLL_POST_DIV_ENABLE_MASK, PLL_POST_DIV_ENABLE);
+               phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
+                               CLOCK_LANE_VOD_RANGE_SET_MASK,
+                               CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
+       }
+       /* Enable PLL and LDO */
+       phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
+                       REG_LDOPD_MASK | REG_PLLPD_MASK,
+                       REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
+       /* Reset analog */
+       phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
+                       REG_SYNCRST_MASK, REG_SYNCRST_RESET);
+       udelay(1);
+       phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
+                       REG_SYNCRST_MASK, REG_SYNCRST_NORMAL);
+       /* Reset digital */
+       phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
+                       REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET);
+       udelay(1);
+       phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
+                       REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL);
+
+       txbyteclkhs = inno->pll.rate / 8;
+       t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs);
+
+       esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000);
+       txclkesc = txbyteclkhs / esc_clk_div;
+       t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc);
+
+       /*
+        * The value of counter for HS Ths-exit
+        * Ths-exit = Tpin_txbyteclkhs * value
+        */
+       hs_exit = DIV_ROUND_UP(cfg->hs_exit, t_txbyteclkhs);
+       /*
+        * The value of counter for HS Tclk-post
+        * Tclk-post = Tpin_txbyteclkhs * value
+        */
+       clk_post = DIV_ROUND_UP(cfg->clk_post, t_txbyteclkhs);
+       /*
+        * The value of counter for HS Tclk-pre
+        * Tclk-pre = Tpin_txbyteclkhs * value
+        */
+       clk_pre = DIV_ROUND_UP(cfg->clk_pre, BITS_PER_BYTE);
+
+       /*
+        * The value of counter for HS Tta-go
+        * Tta-go for turnaround
+        * Tta-go = Ttxclkesc * value
+        */
+       ta_go = DIV_ROUND_UP(cfg->ta_go, t_txclkesc);
+       /*
+        * The value of counter for HS Tta-sure
+        * Tta-sure for turnaround
+        * Tta-sure = Ttxclkesc * value
+        */
+       ta_sure = DIV_ROUND_UP(cfg->ta_sure, t_txclkesc);
+       /*
+        * The value of counter for HS Tta-wait
+        * Tta-wait for turnaround
+        * Tta-wait = Ttxclkesc * value
+        */
+       ta_wait = DIV_ROUND_UP(cfg->ta_get, t_txclkesc);
+
+       for (i = 0; i < inno->pdata->num_timings; i++)
+               if (inno->pll.rate <= timings[i].rate)
+                       break;
+
+       if (i == inno->pdata->num_timings)
+               --i;
+
+       /*
+        * The value of counter for HS Tlpx Time
+        * Tlpx = Tpin_txbyteclkhs * (2 + value)
+        */
+       if (inno->pdata->max_rate == MAX_1GHZ) {
+               lpx = DIV_ROUND_UP(cfg->lpx, t_txbyteclkhs);
+               if (lpx >= 2)
+                       lpx -= 2;
+       } else {
+               lpx = timings[i].lpx;
+       }
+
+       hs_prepare = timings[i].hs_prepare;
+       hs_trail = timings[i].hs_trail;
+       clk_lane_hs_zero = timings[i].clk_lane_hs_zero;
+       data_lane_hs_zero = timings[i].data_lane_hs_zero;
+       wakeup = 0x3ff;
+
+       for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) {
+               if (i == REGISTER_PART_CLOCK_LANE)
+                       hs_zero = clk_lane_hs_zero;
+               else
+                       hs_zero = data_lane_hs_zero;
+
+               phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,
+                               T_LPX_CNT(lpx));
+               phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
+                               T_HS_PREPARE_CNT(hs_prepare));
+               if (inno->pdata->max_rate == MAX_2_5GHZ)
+                       phy_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK,
+                                       T_HS_ZERO_CNT_HI(hs_zero >> 6));
+               phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK,
+                               T_HS_ZERO_CNT_LO(hs_zero));
+               phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
+                               T_HS_TRAIL_CNT(hs_trail));
+               if (inno->pdata->max_rate == MAX_2_5GHZ)
+                       phy_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK,
+                                       T_HS_EXIT_CNT_HI(hs_exit >> 5));
+               phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK,
+                               T_HS_EXIT_CNT_LO(hs_exit));
+               if (inno->pdata->max_rate == MAX_2_5GHZ)
+                       phy_update_bits(inno, i, 0x10, T_CLK_POST_CNT_HI_MASK,
+                                       T_CLK_POST_CNT_HI(clk_post >> 4));
+               phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK,
+                               T_CLK_POST_CNT_LO(clk_post));
+               phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
+                               T_CLK_PRE_CNT(clk_pre));
+               phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
+                               T_WAKEUP_CNT_HI(wakeup >> 8));
+               phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,
+                               T_WAKEUP_CNT_LO(wakeup));
+               phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,
+                               T_TA_GO_CNT(ta_go));
+               phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,
+                               T_TA_SURE_CNT(ta_sure));
+               phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,
+                               T_TA_WAIT_CNT(ta_wait));
+       }
+
+       /* Enable all lanes on analog part */
+       phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
+                       LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 |
+                       LANE_EN_1 | LANE_EN_0);
+}
+
+static int inno_dsidphy_power_on(struct phy *phy)
+{
+       struct inno_dsidphy *inno = dev_get_priv(phy->dev);
+
+       clk_prepare_enable(inno->pclk_phy);
+       clk_prepare_enable(inno->ref_clk);
+
+       /* Bandgap power on */
+       phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
+                       BANDGAP_POWER_MASK, BANDGAP_POWER_ON);
+       /* Enable power work */
+       phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
+                       POWER_WORK_MASK, POWER_WORK_ENABLE);
+
+       inno_dsidphy_mipi_mode_enable(inno);
+
+       return 0;
+}
+
+static int inno_dsidphy_power_off(struct phy *phy)
+{
+       struct inno_dsidphy *inno = dev_get_priv(phy->dev);
+
+       phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0);
+       phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
+                       REG_LDOPD_MASK | REG_PLLPD_MASK,
+                       REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN);
+       phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
+                       POWER_WORK_MASK, POWER_WORK_DISABLE);
+       phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
+                       BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN);
+
+       phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0);
+       phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
+                       LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
+                       LVDS_DIGITAL_INTERNAL_DISABLE);
+       phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
+                       LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
+                       LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN);
+
+       clk_disable_unprepare(inno->ref_clk);
+       clk_disable_unprepare(inno->pclk_phy);
+
+       return 0;
+}
+
+static int inno_dsidphy_configure(struct phy *phy, void *params)
+{
+       struct inno_dsidphy *inno = dev_get_priv(phy->dev);
+       struct phy_configure_opts_mipi_dphy *config = params;
+       int ret;
+
+       ret = phy_mipi_dphy_config_validate(config);
+       if (ret)
+               return ret;
+
+       memcpy(&inno->dphy_cfg, config, sizeof(inno->dphy_cfg));
+
+       return 0;
+}
+
+static const struct phy_ops inno_dsidphy_ops = {
+       .configure = inno_dsidphy_configure,
+       .power_on = inno_dsidphy_power_on,
+       .power_off = inno_dsidphy_power_off,
+};
+
+static const struct inno_video_phy_plat_data max_1ghz_video_phy_plat_data = {
+       .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1ghz,
+       .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1ghz),
+       .max_rate = MAX_1GHZ,
+};
+
+static const struct inno_video_phy_plat_data max_2_5ghz_video_phy_plat_data = {
+       .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5ghz,
+       .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5ghz),
+       .max_rate = MAX_2_5GHZ,
+};
+
+static int inno_dsidphy_probe(struct udevice *dev)
+{
+       struct inno_dsidphy *inno = dev_get_priv(dev);
+       int ret;
+
+       inno->dev = dev;
+       inno->pdata = (const struct inno_video_phy_plat_data *)dev_get_driver_data(dev);
+
+       inno->phy_base = dev_read_addr_ptr(dev);
+       if (IS_ERR(inno->phy_base))
+               return PTR_ERR(inno->phy_base);
+
+       inno->ref_clk = devm_clk_get(dev, "ref");
+       if (IS_ERR(inno->ref_clk)) {
+               ret = PTR_ERR(inno->ref_clk);
+               dev_err(dev, "failed to get ref clock: %d\n", ret);
+               return ret;
+       }
+
+       inno->pclk_phy = devm_clk_get(dev, "pclk");
+       if (IS_ERR(inno->pclk_phy)) {
+               ret = PTR_ERR(inno->pclk_phy);
+               dev_err(dev, "failed to get phy pclk: %d\n", ret);
+               return ret;
+       }
+
+       inno->rst = devm_reset_control_get(dev, "apb");
+       if (IS_ERR(inno->rst)) {
+               ret = PTR_ERR(inno->rst);
+               dev_err(dev, "failed to get system reset control: %d\n", ret);
+               return ret;
+       }
+
+       return 0;
+}
+
+static const struct udevice_id inno_dsidphy_of_match[] = {
+       {
+               .compatible = "rockchip,px30-dsi-dphy",
+               .data = (long)&max_1ghz_video_phy_plat_data,
+       }, {
+               .compatible = "rockchip,rk3128-dsi-dphy",
+               .data = (long)&max_1ghz_video_phy_plat_data,
+       }, {
+               .compatible = "rockchip,rk3368-dsi-dphy",
+               .data = (long)&max_1ghz_video_phy_plat_data,
+       }, {
+               .compatible = "rockchip,rk3568-dsi-dphy",
+               .data = (long)&max_2_5ghz_video_phy_plat_data,
+       },
+       {}
+};
+
+U_BOOT_DRIVER(rockchip_inno_dsidphy) = {
+       .name = "rockchip-inno-dsidphy",
+       .id = UCLASS_PHY,
+       .of_match = inno_dsidphy_of_match,
+       .probe = inno_dsidphy_probe,
+       .ops = &inno_dsidphy_ops,
+       .priv_auto = sizeof(struct inno_dsidphy),
+};

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index b6ef2ac..75b3ff4 100644 (file)
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -359,5 +359,6 @@ source "drivers/pinctrl/renesas/Kconfig"
 source "drivers/pinctrl/rockchip/Kconfig"
 source "drivers/pinctrl/sunxi/Kconfig"
 source "drivers/pinctrl/uniphier/Kconfig"
+source "drivers/pinctrl/starfive/Kconfig"
 
 endmenu

diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 3b167d0..852adee 100644 (file)
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -32,3 +32,4 @@ obj-$(CONFIG_PINCTRL_STM32)   += pinctrl_stm32.o
 obj-$(CONFIG_$(SPL_)PINCTRL_STMFX)     += pinctrl-stmfx.o
 obj-y                          += broadcom/
 obj-$(CONFIG_PINCTRL_ZYNQMP)   += pinctrl-zynqmp.o
+obj-$(CONFIG_PINCTRL_STARFIVE) += starfive/

diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c
index 8837726..73dd7b1 100644 (file)
--- a/drivers/pinctrl/pinctrl-uclass.c
+++ b/drivers/pinctrl/pinctrl-uclass.c
@@ -169,34 +169,33 @@ pinctrl_gpio_get_pinctrl_and_offset(struct udevice *dev, unsigned offset,
 {
        struct ofnode_phandle_args args;
        unsigned gpio_offset, pfc_base, pfc_pins;
-       int ret;
+       int ret = 0;
+       int i = 0;
 
-       ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
-                                        0, &args);
-       if (ret) {
-               dev_dbg(dev, "%s: dev_read_phandle_with_args: err=%d\n",
-                       __func__, ret);
-               return ret;
-       }
+       while (ret == 0) {
+               ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
+                                                i++, &args);
+               if (ret) {
+                       dev_dbg(dev, "%s: dev_read_phandle_with_args: err=%d\n",
+                               __func__, ret);
+                       return ret;
+               }
 
-       ret = uclass_get_device_by_ofnode(UCLASS_PINCTRL,
-                                         args.node, pctldev);
-       if (ret) {
-               dev_dbg(dev,
-                       "%s: uclass_get_device_by_of_offset failed: err=%d\n",
-                       __func__, ret);
-               return ret;
-       }
+               ret = uclass_get_device_by_ofnode(UCLASS_PINCTRL,
+                                                 args.node, pctldev);
+               if (ret) {
+                       dev_dbg(dev,
+                               "%s: uclass_get_device_by_of_offset failed: err=%d\n",
+                               __func__, ret);
+                       return ret;
+               }
 
-       gpio_offset = args.args[0];
-       pfc_base = args.args[1];
-       pfc_pins = args.args[2];
+               gpio_offset = args.args[0];
+               pfc_base = args.args[1];
+               pfc_pins = args.args[2];
 
-       if (offset < gpio_offset || offset > gpio_offset + pfc_pins) {
-               dev_dbg(dev,
-                       "%s: GPIO can not be mapped to pincontrol pin\n",
-                       __func__);
-               return -EINVAL;
+               if (offset >= gpio_offset && offset <= gpio_offset + pfc_pins)
+                       break;
        }
 
        offset -= gpio_offset;

diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index b755fa4..b06da50 100644 (file)
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -61,6 +61,13 @@ static const char * const pinmux_otype[] = {
        [STM32_GPIO_OTYPE_OD] = "open-drain",
 };
 
+static const char * const pinmux_speed[] = {
+       [STM32_GPIO_SPEED_2M] = "Low speed",
+       [STM32_GPIO_SPEED_25M] = "Medium speed",
+       [STM32_GPIO_SPEED_50M] = "High speed",
+       [STM32_GPIO_SPEED_100M] = "Very-high speed",
+};
+
 static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
 {
        struct stm32_gpio_priv *priv = dev_get_priv(dev);
@@ -201,6 +208,7 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
        int af_num;
        unsigned int gpio_idx;
        u32 pupd, otype;
+       u8 speed;
 
        /* look up for the bank which owns the requested pin */
        gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
@@ -214,6 +222,7 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
        priv = dev_get_priv(gpio_dev);
        pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK;
        otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
+       speed = (readl(&priv->regs->ospeedr) >> gpio_idx * 2) & OSPEED_MASK;
 
        switch (mode) {
        case GPIOF_UNKNOWN:
@@ -222,13 +231,15 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
                break;
        case GPIOF_FUNC:
                af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
-               snprintf(buf, size, "%s %d %s %s", pinmux_mode[mode], af_num,
-                        pinmux_otype[otype], pinmux_bias[pupd]);
+               snprintf(buf, size, "%s %d %s %s %s", pinmux_mode[mode], af_num,
+                        pinmux_otype[otype], pinmux_bias[pupd],
+                        pinmux_speed[speed]);
                break;
        case GPIOF_OUTPUT:
-               snprintf(buf, size, "%s %s %s %s",
+               snprintf(buf, size, "%s %s %s %s %s",
                         pinmux_mode[mode], pinmux_otype[otype],
-                        pinmux_bias[pupd], label ? label : "");
+                        pinmux_bias[pupd], label ? label : "",
+                        pinmux_speed[speed]);
                break;
        case GPIOF_INPUT:
                snprintf(buf, size, "%s %s %s", pinmux_mode[mode],

diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 8f994d8..509cdd3 100644 (file)
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -119,6 +119,18 @@ config PINCTRL_PFC_R8A779A0
        help
          Support pin multiplexing control on Renesas RCar Gen3 R8A779A0 SoCs.
 
+config PINCTRL_PFC_R8A779F0
+       bool "Renesas RCar Gen4 R8A779F0 pin control driver"
+       depends on PINCTRL_PFC
+       help
+         Support pin multiplexing control on Renesas RCar Gen4 R8A779F0 SoCs.
+
+config PINCTRL_PFC_R8A779G0
+       bool "Renesas RCar Gen4 R8A779G0 pin control driver"
+       depends on PINCTRL_PFC
+       help
+         Support pin multiplexing control on Renesas RCar Gen4 R8A779G0 SoCs.
+
 config PINCTRL_PFC_R7S72100
        bool "Renesas RZ/A1 R7S72100 pin control driver"
        depends on CPU_RZA1

diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 1198c86..5cea142 100644 (file)
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -17,4 +17,6 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
 obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
+obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o
+obj-$(CONFIG_PINCTRL_PFC_R8A779G0) += pfc-r8a779g0.o
 obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o

diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c
new file mode 100644 (file)
index 0000000..e2ac9d1
--- /dev/null
+++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
@@ -0,0 +1,2106 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R8A779F0 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ *
+ * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/pinctrl.h>
+#include <linux/bitops.h>
+#include <linux/kernel.h>
+
+#include "sh_pfc.h"
+
+#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
+
+#define CPU_ALL_GP(fn, sfx)    \
+       PORT_GP_CFG_21(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),        \
+       PORT_GP_CFG_25(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),        \
+       PORT_GP_CFG_17(2, fn, sfx, CFG_FLAGS),  \
+       PORT_GP_CFG_19(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
+
+#define CPU_ALL_NOGP(fn)                                                               \
+       PIN_NOGP_CFG(PRESETOUT0_N, "PRESETOUT0#", fn, SH_PFC_PIN_CFG_PULL_DOWN),        \
+       PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
+
+/*
+ * F_() : just information
+ * FM() : macro for FN_xxx / xxx_MARK
+ */
+
+/* GPSR0 */
+#define GPSR0_20       F_(IRQ3,        IP2SR0_19_16)
+#define GPSR0_19       F_(IRQ2,        IP2SR0_15_12)
+#define GPSR0_18       F_(IRQ1,        IP2SR0_11_8)
+#define GPSR0_17       F_(IRQ0,        IP2SR0_7_4)
+#define GPSR0_16       F_(MSIOF0_SS2,  IP2SR0_3_0)
+#define GPSR0_15       F_(MSIOF0_SS1,  IP1SR0_31_28)
+#define GPSR0_14       F_(MSIOF0_SCK,  IP1SR0_27_24)
+#define GPSR0_13       F_(MSIOF0_TXD,  IP1SR0_23_20)
+#define GPSR0_12       F_(MSIOF0_RXD,  IP1SR0_19_16)
+#define GPSR0_11       F_(MSIOF0_SYNC, IP1SR0_15_12)
+#define GPSR0_10       F_(CTS0_N,      IP1SR0_11_8)
+#define GPSR0_9                F_(RTS0_N,      IP1SR0_7_4)
+#define GPSR0_8                F_(SCK0,        IP1SR0_3_0)
+#define GPSR0_7                F_(TX0,         IP0SR0_31_28)
+#define GPSR0_6                F_(RX0,         IP0SR0_27_24)
+#define GPSR0_5                F_(HRTS0_N,     IP0SR0_23_20)
+#define GPSR0_4                F_(HCTS0_N,     IP0SR0_19_16)
+#define GPSR0_3                F_(HTX0,        IP0SR0_15_12)
+#define GPSR0_2                F_(HRX0,        IP0SR0_11_8)
+#define GPSR0_1                F_(HSCK0,       IP0SR0_7_4)
+#define GPSR0_0                F_(SCIF_CLK,    IP0SR0_3_0)
+
+/* GPSR1 */
+#define GPSR1_24       FM(SD_WP)
+#define GPSR1_23       FM(SD_CD)
+#define GPSR1_22       FM(MMC_SD_CMD)
+#define GPSR1_21       FM(MMC_D7)
+#define GPSR1_20       FM(MMC_DS)
+#define GPSR1_19       FM(MMC_D6)
+#define GPSR1_18       FM(MMC_D4)
+#define GPSR1_17       FM(MMC_D5)
+#define GPSR1_16       FM(MMC_SD_D3)
+#define GPSR1_15       FM(MMC_SD_D2)
+#define GPSR1_14       FM(MMC_SD_D1)
+#define GPSR1_13       FM(MMC_SD_D0)
+#define GPSR1_12       FM(MMC_SD_CLK)
+#define GPSR1_11       FM(GP1_11)
+#define GPSR1_10       FM(GP1_10)
+#define GPSR1_9                FM(GP1_09)
+#define GPSR1_8                FM(GP1_08)
+#define GPSR1_7                F_(GP1_07,      IP0SR1_31_28)
+#define GPSR1_6                F_(GP1_06,      IP0SR1_27_24)
+#define GPSR1_5                F_(GP1_05,      IP0SR1_23_20)
+#define GPSR1_4                F_(GP1_04,      IP0SR1_19_16)
+#define GPSR1_3                F_(GP1_03,      IP0SR1_15_12)
+#define GPSR1_2                F_(GP1_02,      IP0SR1_11_8)
+#define GPSR1_1                F_(GP1_01,      IP0SR1_7_4)
+#define GPSR1_0                F_(GP1_00,      IP0SR1_3_0)
+
+/* GPSR2 */
+#define GPSR2_16       FM(PCIE1_CLKREQ_N)
+#define GPSR2_15       FM(PCIE0_CLKREQ_N)
+#define GPSR2_14       FM(QSPI0_IO3)
+#define GPSR2_13       FM(QSPI0_SSL)
+#define GPSR2_12       FM(QSPI0_MISO_IO1)
+#define GPSR2_11       FM(QSPI0_IO2)
+#define GPSR2_10       FM(QSPI0_SPCLK)
+#define GPSR2_9                FM(QSPI0_MOSI_IO0)
+#define GPSR2_8                FM(QSPI1_SPCLK)
+#define GPSR2_7                FM(QSPI1_MOSI_IO0)
+#define GPSR2_6                FM(QSPI1_IO2)
+#define GPSR2_5                FM(QSPI1_MISO_IO1)
+#define GPSR2_4                FM(QSPI1_IO3)
+#define GPSR2_3                FM(QSPI1_SSL)
+#define GPSR2_2                FM(RPC_RESET_N)
+#define GPSR2_1                FM(RPC_WP_N)
+#define GPSR2_0                FM(RPC_INT_N)
+
+/* GPSR3 */
+#define GPSR3_18       FM(TSN0_AVTP_CAPTURE_B)
+#define GPSR3_17       FM(TSN0_AVTP_MATCH_B)
+#define GPSR3_16       FM(TSN0_AVTP_PPS)
+#define GPSR3_15       FM(TSN1_AVTP_CAPTURE_B)
+#define GPSR3_14       FM(TSN1_AVTP_MATCH_B)
+#define GPSR3_13       FM(TSN1_AVTP_PPS)
+#define GPSR3_12       FM(TSN0_MAGIC_B)
+#define GPSR3_11       FM(TSN1_PHY_INT_B)
+#define GPSR3_10       FM(TSN0_PHY_INT_B)
+#define GPSR3_9                FM(TSN2_PHY_INT_B)
+#define GPSR3_8                FM(TSN0_LINK_B)
+#define GPSR3_7                FM(TSN2_LINK_B)
+#define GPSR3_6                FM(TSN1_LINK_B)
+#define GPSR3_5                FM(TSN1_MDC_B)
+#define GPSR3_4                FM(TSN0_MDC_B)
+#define GPSR3_3                FM(TSN2_MDC_B)
+#define GPSR3_2                FM(TSN0_MDIO_B)
+#define GPSR3_1                FM(TSN2_MDIO_B)
+#define GPSR3_0                FM(TSN1_MDIO_B)
+
+/* IP0SR0 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */         /* 5 */                 /* 6 */                 /* 7 - F */
+#define IP0SR0_3_0     FM(SCIF_CLK)            F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_7_4     FM(HSCK0)               FM(SCK3)                FM(MSIOF3_SCK)          F_(0, 0)                F_(0, 0)        FM(TSN0_AVTP_CAPTURE_A) F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_11_8    FM(HRX0)                FM(RX3)                 FM(MSIOF3_RXD)          F_(0, 0)                F_(0, 0)        FM(TSN0_AVTP_MATCH_A)   F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_15_12   FM(HTX0)                FM(TX3)                 FM(MSIOF3_TXD)          F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_19_16   FM(HCTS0_N)             FM(CTS3_N)              FM(MSIOF3_SS1)          F_(0, 0)                F_(0, 0)        FM(TSN0_MDC_A)          F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_23_20   FM(HRTS0_N)             FM(RTS3_N)              FM(MSIOF3_SS2)          F_(0, 0)                F_(0, 0)        FM(TSN0_MDIO_A)         F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_27_24   FM(RX0)                 FM(HRX1)                F_(0, 0)                FM(MSIOF1_RXD)          F_(0, 0)        FM(TSN1_AVTP_MATCH_A)   F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_31_28   FM(TX0)                 FM(HTX1)                F_(0, 0)                FM(MSIOF1_TXD)          F_(0, 0)        FM(TSN1_AVTP_CAPTURE_A) F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP1SR0 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */         /* 5 */                 /* 6 */                 /* 7 - F */
+#define IP1SR0_3_0     FM(SCK0)                FM(HSCK1)               F_(0, 0)                FM(MSIOF1_SCK)          F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_7_4     FM(RTS0_N)              FM(HRTS1_N)             FM(MSIOF3_SYNC)         F_(0, 0)                F_(0, 0)        FM(TSN1_MDIO_A)         F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_11_8    FM(CTS0_N)              FM(HCTS1_N)             F_(0, 0)                FM(MSIOF1_SYNC)         F_(0, 0)        FM(TSN1_MDC_A)          F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_15_12   FM(MSIOF0_SYNC)         FM(HCTS3_N)             FM(CTS1_N)              FM(IRQ4)                F_(0, 0)        FM(TSN0_LINK_A)         F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_19_16   FM(MSIOF0_RXD)          FM(HRX3)                FM(RX1)                 F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_23_20   FM(MSIOF0_TXD)          FM(HTX3)                FM(TX1)                 F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_27_24   FM(MSIOF0_SCK)          FM(HSCK3)               FM(SCK1)                F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_31_28   FM(MSIOF0_SS1)          FM(HRTS3_N)             FM(RTS1_N)              FM(IRQ5)                F_(0, 0)        FM(TSN1_LINK_A)         F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IP2SR0 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */         /* 5 */                 /* 6 */                 /* 7 - F */
+#define IP2SR0_3_0     FM(MSIOF0_SS2)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(TSN2_LINK_A)         F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR0_7_4     FM(IRQ0)                F_(0, 0)                F_(0, 0)                FM(MSIOF1_SS1)          F_(0, 0)        FM(TSN0_MAGIC_A)        F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR0_11_8    FM(IRQ1)                F_(0, 0)                F_(0, 0)                FM(MSIOF1_SS2)          F_(0, 0)        FM(TSN0_PHY_INT_A)      F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR0_15_12   FM(IRQ2)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(TSN1_PHY_INT_A)      F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR0_19_16   FM(IRQ3)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(TSN2_PHY_INT_A)      F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP0SR1 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */         /* 5 */                 /* 6 */                 /* 7 - F */
+#define IP0SR1_3_0     FM(GP1_00)              FM(TCLK1)               FM(HSCK2)               F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_7_4     FM(GP1_01)              FM(TCLK4)               FM(HRX2)                F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_11_8    FM(GP1_02)              F_(0, 0)                FM(HTX2)                FM(MSIOF2_SS1)          F_(0, 0)        FM(TSN2_MDC_A)          F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_15_12   FM(GP1_03)              FM(TCLK2)               FM(HCTS2_N)             FM(MSIOF2_SS2)          FM(CTS4_N)      FM(TSN2_MDIO_A)         F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_19_16   FM(GP1_04)              FM(TCLK3)               FM(HRTS2_N)             FM(MSIOF2_SYNC)         FM(RTS4_N)      F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_23_20   FM(GP1_05)              FM(MSIOF2_SCK)          FM(SCK4)                F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_27_24   FM(GP1_06)              FM(MSIOF2_RXD)          FM(RX4)                 F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_31_28   FM(GP1_07)              FM(MSIOF2_TXD)          FM(TX4)                 F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+#define PINMUX_GPSR    \
+               GPSR1_24                                        \
+               GPSR1_23                                        \
+               GPSR1_22                                        \
+               GPSR1_21                                        \
+GPSR0_20       GPSR1_20                                        \
+GPSR0_19       GPSR1_19                                        \
+GPSR0_18       GPSR1_18                        GPSR3_18        \
+GPSR0_17       GPSR1_17                        GPSR3_17        \
+GPSR0_16       GPSR1_16        GPSR2_16        GPSR3_16        \
+GPSR0_15       GPSR1_15        GPSR2_15        GPSR3_15        \
+GPSR0_14       GPSR1_14        GPSR2_14        GPSR3_14        \
+GPSR0_13       GPSR1_13        GPSR2_13        GPSR3_13        \
+GPSR0_12       GPSR1_12        GPSR2_12        GPSR3_12        \
+GPSR0_11       GPSR1_11        GPSR2_11        GPSR3_11        \
+GPSR0_10       GPSR1_10        GPSR2_10        GPSR3_10        \
+GPSR0_9                GPSR1_9         GPSR2_9         GPSR3_9         \
+GPSR0_8                GPSR1_8         GPSR2_8         GPSR3_8         \
+GPSR0_7                GPSR1_7         GPSR2_7         GPSR3_7         \
+GPSR0_6                GPSR1_6         GPSR2_6         GPSR3_6         \
+GPSR0_5                GPSR1_5         GPSR2_5         GPSR3_5         \
+GPSR0_4                GPSR1_4         GPSR2_4         GPSR3_4         \
+GPSR0_3                GPSR1_3         GPSR2_3         GPSR3_3         \
+GPSR0_2                GPSR1_2         GPSR2_2         GPSR3_2         \
+GPSR0_1                GPSR1_1         GPSR2_1         GPSR3_1         \
+GPSR0_0                GPSR1_0         GPSR2_0         GPSR3_0
+
+#define PINMUX_IPSR    \
+\
+FM(IP0SR0_3_0)         IP0SR0_3_0      FM(IP1SR0_3_0)          IP1SR0_3_0      FM(IP2SR0_3_0)          IP2SR0_3_0      \
+FM(IP0SR0_7_4)         IP0SR0_7_4      FM(IP1SR0_7_4)          IP1SR0_7_4      FM(IP2SR0_7_4)          IP2SR0_7_4      \
+FM(IP0SR0_11_8)                IP0SR0_11_8     FM(IP1SR0_11_8)         IP1SR0_11_8     FM(IP2SR0_11_8)         IP2SR0_11_8     \
+FM(IP0SR0_15_12)       IP0SR0_15_12    FM(IP1SR0_15_12)        IP1SR0_15_12    FM(IP2SR0_15_12)        IP2SR0_15_12    \
+FM(IP0SR0_19_16)       IP0SR0_19_16    FM(IP1SR0_19_16)        IP1SR0_19_16    FM(IP2SR0_19_16)        IP2SR0_19_16    \
+FM(IP0SR0_23_20)       IP0SR0_23_20    FM(IP1SR0_23_20)        IP1SR0_23_20    \
+FM(IP0SR0_27_24)       IP0SR0_27_24    FM(IP1SR0_27_24)        IP1SR0_27_24    \
+FM(IP0SR0_31_28)       IP0SR0_31_28    FM(IP1SR0_31_28)        IP1SR0_31_28    \
+\
+FM(IP0SR1_3_0)         IP0SR1_3_0      \
+FM(IP0SR1_7_4)         IP0SR1_7_4      \
+FM(IP0SR1_11_8)                IP0SR1_11_8     \
+FM(IP0SR1_15_12)       IP0SR1_15_12    \
+FM(IP0SR1_19_16)       IP0SR1_19_16    \
+FM(IP0SR1_23_20)       IP0SR1_23_20    \
+FM(IP0SR1_27_24)       IP0SR1_27_24    \
+FM(IP0SR1_31_28)       IP0SR1_31_28
+
+/* MOD_SEL1 */                 /* 0 */         /* 1 */         /* 2 */         /* 3 */
+#define MOD_SEL1_11_10         FM(SEL_I2C5_0)  F_(0, 0)        F_(0, 0)        FM(SEL_I2C5_3)
+#define MOD_SEL1_9_8           FM(SEL_I2C4_0)  F_(0, 0)        F_(0, 0)        FM(SEL_I2C4_3)
+#define MOD_SEL1_7_6           FM(SEL_I2C3_0)  F_(0, 0)        F_(0, 0)        FM(SEL_I2C3_3)
+#define MOD_SEL1_5_4           FM(SEL_I2C2_0)  F_(0, 0)        F_(0, 0)        FM(SEL_I2C2_3)
+#define MOD_SEL1_3_2           FM(SEL_I2C1_0)  F_(0, 0)        F_(0, 0)        FM(SEL_I2C1_3)
+#define MOD_SEL1_1_0           FM(SEL_I2C0_0)  F_(0, 0)        F_(0, 0)        FM(SEL_I2C0_3)
+
+#define PINMUX_MOD_SELS \
+\
+MOD_SEL1_11_10 \
+MOD_SEL1_9_8 \
+MOD_SEL1_7_6 \
+MOD_SEL1_5_4 \
+MOD_SEL1_3_2 \
+MOD_SEL1_1_0
+
+#define PINMUX_PHYS \
+       FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \
+       FM(SCL4) FM(SDA4) FM(SCL5) FM(SDA5)
+
+enum {
+       PINMUX_RESERVED = 0,
+
+       PINMUX_DATA_BEGIN,
+       GP_ALL(DATA),
+       PINMUX_DATA_END,
+
+#define F_(x, y)
+#define FM(x)   FN_##x,
+       PINMUX_FUNCTION_BEGIN,
+       GP_ALL(FN),
+       PINMUX_GPSR
+       PINMUX_IPSR
+       PINMUX_MOD_SELS
+       PINMUX_FUNCTION_END,
+#undef F_
+#undef FM
+
+#define F_(x, y)
+#define FM(x)  x##_MARK,
+       PINMUX_MARK_BEGIN,
+       PINMUX_GPSR
+       PINMUX_IPSR
+       PINMUX_MOD_SELS
+       PINMUX_PHYS
+       PINMUX_MARK_END,
+#undef F_
+#undef FM
+};
+
+static const u16 pinmux_data[] = {
+/* Using GP_1_[0-9] requires disabling I2C in MOD_SEL1 */
+#define GP_1_0_FN      GP_1_0_FN,      FN_SEL_I2C0_0
+#define GP_1_1_FN      GP_1_1_FN,      FN_SEL_I2C0_0
+#define GP_1_2_FN      GP_1_2_FN,      FN_SEL_I2C1_0
+#define GP_1_3_FN      GP_1_3_FN,      FN_SEL_I2C1_0
+#define GP_1_4_FN      GP_1_4_FN,      FN_SEL_I2C2_0
+#define GP_1_5_FN      GP_1_5_FN,      FN_SEL_I2C2_0
+#define GP_1_6_FN      GP_1_6_FN,      FN_SEL_I2C3_0
+#define GP_1_7_FN      GP_1_7_FN,      FN_SEL_I2C3_0
+#define GP_1_8_FN      GP_1_8_FN,      FN_SEL_I2C4_0
+#define GP_1_9_FN      GP_1_9_FN,      FN_SEL_I2C4_0
+       PINMUX_DATA_GP_ALL(),
+#undef GP_1_0_FN
+#undef GP_1_1_FN
+#undef GP_1_2_FN
+#undef GP_1_3_FN
+#undef GP_1_4_FN
+#undef GP_1_5_FN
+#undef GP_1_6_FN
+#undef GP_1_7_FN
+#undef GP_1_8_FN
+#undef GP_1_9_FN
+
+       PINMUX_SINGLE(SD_WP),
+       PINMUX_SINGLE(SD_CD),
+       PINMUX_SINGLE(MMC_SD_CMD),
+       PINMUX_SINGLE(MMC_D7),
+       PINMUX_SINGLE(MMC_DS),
+       PINMUX_SINGLE(MMC_D6),
+       PINMUX_SINGLE(MMC_D4),
+       PINMUX_SINGLE(MMC_D5),
+       PINMUX_SINGLE(MMC_SD_D3),
+       PINMUX_SINGLE(MMC_SD_D2),
+       PINMUX_SINGLE(MMC_SD_D1),
+       PINMUX_SINGLE(MMC_SD_D0),
+       PINMUX_SINGLE(MMC_SD_CLK),
+       PINMUX_SINGLE(PCIE1_CLKREQ_N),
+       PINMUX_SINGLE(PCIE0_CLKREQ_N),
+       PINMUX_SINGLE(QSPI0_IO3),
+       PINMUX_SINGLE(QSPI0_SSL),
+       PINMUX_SINGLE(QSPI0_MISO_IO1),
+       PINMUX_SINGLE(QSPI0_IO2),
+       PINMUX_SINGLE(QSPI0_SPCLK),
+       PINMUX_SINGLE(QSPI0_MOSI_IO0),
+       PINMUX_SINGLE(QSPI1_SPCLK),
+       PINMUX_SINGLE(QSPI1_MOSI_IO0),
+       PINMUX_SINGLE(QSPI1_IO2),
+       PINMUX_SINGLE(QSPI1_MISO_IO1),
+       PINMUX_SINGLE(QSPI1_IO3),
+       PINMUX_SINGLE(QSPI1_SSL),
+       PINMUX_SINGLE(RPC_RESET_N),
+       PINMUX_SINGLE(RPC_WP_N),
+       PINMUX_SINGLE(RPC_INT_N),
+
+       PINMUX_SINGLE(TSN0_AVTP_CAPTURE_B),
+       PINMUX_SINGLE(TSN0_AVTP_MATCH_B),
+       PINMUX_SINGLE(TSN0_AVTP_PPS),
+       PINMUX_SINGLE(TSN1_AVTP_CAPTURE_B),
+       PINMUX_SINGLE(TSN1_AVTP_MATCH_B),
+       PINMUX_SINGLE(TSN1_AVTP_PPS),
+       PINMUX_SINGLE(TSN0_MAGIC_B),
+       PINMUX_SINGLE(TSN1_PHY_INT_B),
+       PINMUX_SINGLE(TSN0_PHY_INT_B),
+       PINMUX_SINGLE(TSN2_PHY_INT_B),
+       PINMUX_SINGLE(TSN0_LINK_B),
+       PINMUX_SINGLE(TSN2_LINK_B),
+       PINMUX_SINGLE(TSN1_LINK_B),
+       PINMUX_SINGLE(TSN1_MDC_B),
+       PINMUX_SINGLE(TSN0_MDC_B),
+       PINMUX_SINGLE(TSN2_MDC_B),
+       PINMUX_SINGLE(TSN0_MDIO_B),
+       PINMUX_SINGLE(TSN2_MDIO_B),
+       PINMUX_SINGLE(TSN1_MDIO_B),
+
+       /* IP0SR0 */
+       PINMUX_IPSR_GPSR(IP0SR0_3_0,    SCIF_CLK),
+
+       PINMUX_IPSR_GPSR(IP0SR0_7_4,    HSCK0),
+       PINMUX_IPSR_GPSR(IP0SR0_7_4,    SCK3),
+       PINMUX_IPSR_GPSR(IP0SR0_7_4,    MSIOF3_SCK),
+       PINMUX_IPSR_GPSR(IP0SR0_7_4,    TSN0_AVTP_CAPTURE_A),
+
+       PINMUX_IPSR_GPSR(IP0SR0_11_8,   HRX0),
+       PINMUX_IPSR_GPSR(IP0SR0_11_8,   RX3),
+       PINMUX_IPSR_GPSR(IP0SR0_11_8,   MSIOF3_RXD),
+       PINMUX_IPSR_GPSR(IP0SR0_11_8,   TSN0_AVTP_MATCH_A),
+
+       PINMUX_IPSR_GPSR(IP0SR0_15_12,  HTX0),
+       PINMUX_IPSR_GPSR(IP0SR0_15_12,  TX3),
+       PINMUX_IPSR_GPSR(IP0SR0_15_12,  MSIOF3_TXD),
+
+       PINMUX_IPSR_GPSR(IP0SR0_19_16,  HCTS0_N),
+       PINMUX_IPSR_GPSR(IP0SR0_19_16,  CTS3_N),
+       PINMUX_IPSR_GPSR(IP0SR0_19_16,  MSIOF3_SS1),
+       PINMUX_IPSR_GPSR(IP0SR0_19_16,  TSN0_MDC_A),
+
+       PINMUX_IPSR_GPSR(IP0SR0_23_20,  HRTS0_N),
+       PINMUX_IPSR_GPSR(IP0SR0_23_20,  RTS3_N),
+       PINMUX_IPSR_GPSR(IP0SR0_23_20,  MSIOF3_SS2),
+       PINMUX_IPSR_GPSR(IP0SR0_23_20,  TSN0_MDIO_A),
+
+       PINMUX_IPSR_GPSR(IP0SR0_27_24,  RX0),
+       PINMUX_IPSR_GPSR(IP0SR0_27_24,  HRX1),
+       PINMUX_IPSR_GPSR(IP0SR0_27_24,  MSIOF1_RXD),
+       PINMUX_IPSR_GPSR(IP0SR0_27_24,  TSN1_AVTP_MATCH_A),
+
+       PINMUX_IPSR_GPSR(IP0SR0_31_28,  TX0),
+       PINMUX_IPSR_GPSR(IP0SR0_31_28,  HTX1),
+       PINMUX_IPSR_GPSR(IP0SR0_31_28,  MSIOF1_TXD),
+       PINMUX_IPSR_GPSR(IP0SR0_31_28,  TSN1_AVTP_CAPTURE_A),
+
+       /* IP1SR0 */
+       PINMUX_IPSR_GPSR(IP1SR0_3_0,    SCK0),
+       PINMUX_IPSR_GPSR(IP1SR0_3_0,    HSCK1),
+       PINMUX_IPSR_GPSR(IP1SR0_3_0,    MSIOF1_SCK),
+
+       PINMUX_IPSR_GPSR(IP1SR0_7_4,    RTS0_N),
+       PINMUX_IPSR_GPSR(IP1SR0_7_4,    HRTS1_N),
+       PINMUX_IPSR_GPSR(IP1SR0_7_4,    MSIOF3_SYNC),
+       PINMUX_IPSR_GPSR(IP1SR0_7_4,    TSN1_MDIO_A),
+
+       PINMUX_IPSR_GPSR(IP1SR0_11_8,   CTS0_N),
+       PINMUX_IPSR_GPSR(IP1SR0_11_8,   HCTS1_N),
+       PINMUX_IPSR_GPSR(IP1SR0_11_8,   MSIOF1_SYNC),
+       PINMUX_IPSR_GPSR(IP1SR0_11_8,   TSN1_MDC_A),
+
+       PINMUX_IPSR_GPSR(IP1SR0_15_12,  MSIOF0_SYNC),
+       PINMUX_IPSR_GPSR(IP1SR0_15_12,  HCTS3_N),
+       PINMUX_IPSR_GPSR(IP1SR0_15_12,  CTS1_N),
+       PINMUX_IPSR_GPSR(IP1SR0_15_12,  IRQ4),
+       PINMUX_IPSR_GPSR(IP1SR0_15_12,  TSN0_LINK_A),
+
+       PINMUX_IPSR_GPSR(IP1SR0_19_16,  MSIOF0_RXD),
+       PINMUX_IPSR_GPSR(IP1SR0_19_16,  HRX3),
+       PINMUX_IPSR_GPSR(IP1SR0_19_16,  RX1),
+
+       PINMUX_IPSR_GPSR(IP1SR0_23_20,  MSIOF0_TXD),
+       PINMUX_IPSR_GPSR(IP1SR0_23_20,  HTX3),
+       PINMUX_IPSR_GPSR(IP1SR0_23_20,  TX1),
+
+       PINMUX_IPSR_GPSR(IP1SR0_27_24,  MSIOF0_SCK),
+       PINMUX_IPSR_GPSR(IP1SR0_27_24,  HSCK3),
+       PINMUX_IPSR_GPSR(IP1SR0_27_24,  SCK1),
+
+       PINMUX_IPSR_GPSR(IP1SR0_31_28,  MSIOF0_SS1),
+       PINMUX_IPSR_GPSR(IP1SR0_31_28,  HRTS3_N),
+       PINMUX_IPSR_GPSR(IP1SR0_31_28,  RTS1_N),
+       PINMUX_IPSR_GPSR(IP1SR0_31_28,  IRQ5),
+       PINMUX_IPSR_GPSR(IP1SR0_31_28,  TSN1_LINK_A),
+
+       /* IP2SR0 */
+       PINMUX_IPSR_GPSR(IP2SR0_3_0,    MSIOF0_SS2),
+       PINMUX_IPSR_GPSR(IP2SR0_3_0,    TSN2_LINK_A),
+
+       PINMUX_IPSR_GPSR(IP2SR0_7_4,    IRQ0),
+       PINMUX_IPSR_GPSR(IP2SR0_7_4,    MSIOF1_SS1),
+       PINMUX_IPSR_GPSR(IP2SR0_7_4,    TSN0_MAGIC_A),
+
+       PINMUX_IPSR_GPSR(IP2SR0_11_8,   IRQ1),
+       PINMUX_IPSR_GPSR(IP2SR0_11_8,   MSIOF1_SS2),
+       PINMUX_IPSR_GPSR(IP2SR0_11_8,   TSN0_PHY_INT_A),
+
+       PINMUX_IPSR_GPSR(IP2SR0_15_12,  IRQ2),
+       PINMUX_IPSR_GPSR(IP2SR0_15_12,  TSN1_PHY_INT_A),
+
+       PINMUX_IPSR_GPSR(IP2SR0_19_16,  IRQ3),
+       PINMUX_IPSR_GPSR(IP2SR0_19_16,  TSN2_PHY_INT_A),
+
+       /* IP0SR1 */
+       /* GP1_00 = SCL0 */
+       PINMUX_IPSR_MSEL(IP0SR1_3_0,    GP1_00,         SEL_I2C0_0),
+       PINMUX_IPSR_MSEL(IP0SR1_3_0,    TCLK1,          SEL_I2C0_0),
+       PINMUX_IPSR_MSEL(IP0SR1_3_0,    HSCK2,          SEL_I2C0_0),
+       PINMUX_IPSR_PHYS(IP0SR1_3_0,    SCL0,           SEL_I2C0_3),
+
+       /* GP1_01 = SDA0 */
+       PINMUX_IPSR_MSEL(IP0SR1_7_4,    GP1_01,         SEL_I2C0_0),
+       PINMUX_IPSR_MSEL(IP0SR1_7_4,    TCLK4,          SEL_I2C0_0),
+       PINMUX_IPSR_MSEL(IP0SR1_7_4,    HRX2,           SEL_I2C0_0),
+       PINMUX_IPSR_PHYS(IP0SR1_7_4,    SDA0,           SEL_I2C0_3),
+
+       /* GP1_02 = SCL1 */
+       PINMUX_IPSR_MSEL(IP0SR1_11_8,   GP1_02,         SEL_I2C1_0),
+       PINMUX_IPSR_MSEL(IP0SR1_11_8,   HTX2,           SEL_I2C1_0),
+       PINMUX_IPSR_MSEL(IP0SR1_11_8,   MSIOF2_SS1,     SEL_I2C1_0),
+       PINMUX_IPSR_MSEL(IP0SR1_11_8,   TSN2_MDC_A,     SEL_I2C1_0),
+       PINMUX_IPSR_PHYS(IP0SR1_11_8,   SCL1,           SEL_I2C1_3),
+
+       /* GP1_03 = SDA1 */
+       PINMUX_IPSR_MSEL(IP0SR1_15_12,  GP1_03,         SEL_I2C1_0),
+       PINMUX_IPSR_MSEL(IP0SR1_15_12,  TCLK2,          SEL_I2C1_0),
+       PINMUX_IPSR_MSEL(IP0SR1_15_12,  HCTS2_N,        SEL_I2C1_0),
+       PINMUX_IPSR_MSEL(IP0SR1_15_12,  MSIOF2_SS2,     SEL_I2C1_0),
+       PINMUX_IPSR_MSEL(IP0SR1_15_12,  CTS4_N,         SEL_I2C1_0),
+       PINMUX_IPSR_MSEL(IP0SR1_15_12,  TSN2_MDIO_A,    SEL_I2C1_0),
+       PINMUX_IPSR_PHYS(IP0SR1_15_12,  SDA1,           SEL_I2C1_3),
+
+       /* GP1_04 = SCL2 */
+       PINMUX_IPSR_MSEL(IP0SR1_19_16,  GP1_04,         SEL_I2C2_0),
+       PINMUX_IPSR_MSEL(IP0SR1_19_16,  TCLK3,          SEL_I2C2_0),
+       PINMUX_IPSR_MSEL(IP0SR1_19_16,  HRTS2_N,        SEL_I2C2_0),
+       PINMUX_IPSR_MSEL(IP0SR1_19_16,  MSIOF2_SYNC,    SEL_I2C2_0),
+       PINMUX_IPSR_MSEL(IP0SR1_19_16,  RTS4_N,         SEL_I2C2_0),
+       PINMUX_IPSR_PHYS(IP0SR1_19_16,  SCL2,           SEL_I2C2_3),
+
+       /* GP1_05 = SDA2 */
+       PINMUX_IPSR_MSEL(IP0SR1_23_20,  GP1_05,         SEL_I2C2_0),
+       PINMUX_IPSR_MSEL(IP0SR1_23_20,  MSIOF2_SCK,     SEL_I2C2_0),
+       PINMUX_IPSR_MSEL(IP0SR1_23_20,  SCK4,           SEL_I2C2_0),
+       PINMUX_IPSR_PHYS(IP0SR1_23_20,  SDA2,           SEL_I2C2_3),
+
+       /* GP1_06 = SCL3 */
+       PINMUX_IPSR_MSEL(IP0SR1_27_24,  GP1_06,         SEL_I2C3_0),
+       PINMUX_IPSR_MSEL(IP0SR1_27_24,  MSIOF2_RXD,     SEL_I2C3_0),
+       PINMUX_IPSR_MSEL(IP0SR1_27_24,  RX4,            SEL_I2C3_0),
+       PINMUX_IPSR_PHYS(IP0SR1_27_24,  SCL3,           SEL_I2C3_3),
+
+       /* GP1_07 = SDA3 */
+       PINMUX_IPSR_MSEL(IP0SR1_31_28,  GP1_07,         SEL_I2C3_0),
+       PINMUX_IPSR_MSEL(IP0SR1_31_28,  MSIOF2_TXD,     SEL_I2C3_0),
+       PINMUX_IPSR_MSEL(IP0SR1_31_28,  TX4,            SEL_I2C3_0),
+       PINMUX_IPSR_PHYS(IP0SR1_31_28,  SDA3,           SEL_I2C3_3),
+
+       /* GP1_08 = SCL4 */
+       PINMUX_IPSR_NOGM(0,             GP1_08,         SEL_I2C4_0),
+       PINMUX_IPSR_NOFN(GP1_08,        SCL4,           SEL_I2C4_3),
+
+       /* GP1_09 = SDA4 */
+       PINMUX_IPSR_NOGM(0,             GP1_09,         SEL_I2C4_0),
+       PINMUX_IPSR_NOFN(GP1_09,        SDA4,           SEL_I2C4_3),
+
+       /* GP1_10 = SCL5 */
+       PINMUX_IPSR_NOGM(0,             GP1_10,         SEL_I2C5_0),
+       PINMUX_IPSR_NOFN(GP1_10,        SCL5,           SEL_I2C5_3),
+
+       /* GP1_11 = SDA5 */
+       PINMUX_IPSR_NOGM(0,             GP1_11,         SEL_I2C5_0),
+       PINMUX_IPSR_NOFN(GP1_11,        SDA5,           SEL_I2C5_3),
+};
+
+/*
+ * Pins not associated with a GPIO port.
+ */
+enum {
+       GP_ASSIGN_LAST(),
+       NOGP_ALL(),
+};
+
+static const struct sh_pfc_pin pinmux_pins[] = {
+       PINMUX_GPIO_GP_ALL(),
+};
+
+/* - HSCIF0 ----------------------------------------------------------------- */
+static const unsigned int hscif0_data_pins[] = {
+       /* HRX0, HTX0 */
+       RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+};
+static const unsigned int hscif0_data_mux[] = {
+       HRX0_MARK, HTX0_MARK,
+};
+static const unsigned int hscif0_clk_pins[] = {
+       /* HSCK0 */
+       RCAR_GP_PIN(0, 1),
+};
+static const unsigned int hscif0_clk_mux[] = {
+       HSCK0_MARK,
+};
+static const unsigned int hscif0_ctrl_pins[] = {
+       /* HRTS0#, HCTS0# */
+       RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
+};
+static const unsigned int hscif0_ctrl_mux[] = {
+       HRTS0_N_MARK, HCTS0_N_MARK,
+};
+
+/* - HSCIF1 ----------------------------------------------------------------- */
+static const unsigned int hscif1_data_pins[] = {
+       /* HRX1, HTX1 */
+       RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int hscif1_data_mux[] = {
+       HRX1_MARK, HTX1_MARK,
+};
+static const unsigned int hscif1_clk_pins[] = {
+       /* HSCK1 */
+       RCAR_GP_PIN(0, 8),
+};
+static const unsigned int hscif1_clk_mux[] = {
+       HSCK1_MARK,
+};
+static const unsigned int hscif1_ctrl_pins[] = {
+       /* HRTS1#, HCTS1# */
+       RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+};
+static const unsigned int hscif1_ctrl_mux[] = {
+       HRTS1_N_MARK, HCTS1_N_MARK,
+};
+
+/* - HSCIF2 ----------------------------------------------------------------- */
+static const unsigned int hscif2_data_pins[] = {
+       /* HRX2, HTX2 */
+       RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
+};
+static const unsigned int hscif2_data_mux[] = {
+       HRX2_MARK, HTX2_MARK,
+};
+static const unsigned int hscif2_clk_pins[] = {
+       /* HSCK2 */
+       RCAR_GP_PIN(1, 0),
+};
+static const unsigned int hscif2_clk_mux[] = {
+       HSCK2_MARK,
+};
+static const unsigned int hscif2_ctrl_pins[] = {
+       /* HRTS2#, HCTS2# */
+       RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
+};
+static const unsigned int hscif2_ctrl_mux[] = {
+       HRTS2_N_MARK, HCTS2_N_MARK,
+};
+
+/* - HSCIF3 ----------------------------------------------------------------- */
+static const unsigned int hscif3_data_pins[] = {
+       /* HRX3, HTX3 */
+       RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+};
+static const unsigned int hscif3_data_mux[] = {
+       HRX3_MARK, HTX3_MARK,
+};
+static const unsigned int hscif3_clk_pins[] = {
+       /* HSCK3 */
+       RCAR_GP_PIN(0, 14),
+};
+static const unsigned int hscif3_clk_mux[] = {
+       HSCK3_MARK,
+};
+static const unsigned int hscif3_ctrl_pins[] = {
+       /* HRTS3#, HCTS3# */
+       RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
+};
+static const unsigned int hscif3_ctrl_mux[] = {
+       HRTS3_N_MARK, HCTS3_N_MARK,
+};
+
+/* - I2C0 ------------------------------------------------------------------- */
+static const unsigned int i2c0_pins[] = {
+       /* SDA0, SCL0 */
+       RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
+};
+static const unsigned int i2c0_mux[] = {
+       SDA0_MARK, SCL0_MARK,
+};
+
+/* - I2C1 ------------------------------------------------------------------- */
+static const unsigned int i2c1_pins[] = {
+       /* SDA1, SCL1 */
+       RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
+};
+static const unsigned int i2c1_mux[] = {
+       SDA1_MARK, SCL1_MARK,
+};
+
+/* - I2C2 ------------------------------------------------------------------- */
+static const unsigned int i2c2_pins[] = {
+       /* SDA2, SCL2 */
+       RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4),
+};
+static const unsigned int i2c2_mux[] = {
+       SDA2_MARK, SCL2_MARK,
+};
+
+/* - I2C3 ------------------------------------------------------------------- */
+static const unsigned int i2c3_pins[] = {
+       /* SDA3, SCL3 */
+       RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int i2c3_mux[] = {
+       SDA3_MARK, SCL3_MARK,
+};
+
+/* - I2C4 ------------------------------------------------------------------- */
+static const unsigned int i2c4_pins[] = {
+       /* SDA4, SCL4 */
+       RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
+};
+static const unsigned int i2c4_mux[] = {
+       SDA4_MARK, SCL4_MARK,
+};
+
+/* - I2C5 ------------------------------------------------------------------- */
+static const unsigned int i2c5_pins[] = {
+       /* SDA5, SCL5 */
+       RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
+};
+static const unsigned int i2c5_mux[] = {
+       SDA5_MARK, SCL5_MARK,
+};
+
+
+/* - INTC-EX ---------------------------------------------------------------- */
+static const unsigned int intc_ex_irq0_pins[] = {
+       /* IRQ0 */
+       RCAR_GP_PIN(0, 17),
+};
+static const unsigned int intc_ex_irq0_mux[] = {
+       IRQ0_MARK,
+};
+static const unsigned int intc_ex_irq1_pins[] = {
+       /* IRQ1 */
+       RCAR_GP_PIN(0, 18),
+};
+static const unsigned int intc_ex_irq1_mux[] = {
+       IRQ1_MARK,
+};
+static const unsigned int intc_ex_irq2_pins[] = {
+       /* IRQ2 */
+       RCAR_GP_PIN(0, 19),
+};
+static const unsigned int intc_ex_irq2_mux[] = {
+       IRQ2_MARK,
+};
+static const unsigned int intc_ex_irq3_pins[] = {
+       /* IRQ3 */
+       RCAR_GP_PIN(0, 20),
+};
+static const unsigned int intc_ex_irq3_mux[] = {
+       IRQ3_MARK,
+};
+static const unsigned int intc_ex_irq4_pins[] = {
+       /* IRQ4 */
+       RCAR_GP_PIN(0, 11),
+};
+static const unsigned int intc_ex_irq4_mux[] = {
+       IRQ4_MARK,
+};
+static const unsigned int intc_ex_irq5_pins[] = {
+       /* IRQ5 */
+       RCAR_GP_PIN(0, 15),
+};
+static const unsigned int intc_ex_irq5_mux[] = {
+       IRQ5_MARK,
+};
+
+/* - MMC -------------------------------------------------------------------- */
+static const unsigned int mmc_data_pins[] = {
+       /* MMC_SD_D[0:3], MMC_D[4:7] */
+       RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
+       RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
+       RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
+       RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 21),
+};
+static const unsigned int mmc_data_mux[] = {
+       MMC_SD_D0_MARK, MMC_SD_D1_MARK,
+       MMC_SD_D2_MARK, MMC_SD_D3_MARK,
+       MMC_D4_MARK, MMC_D5_MARK,
+       MMC_D6_MARK, MMC_D7_MARK,
+};
+static const unsigned int mmc_ctrl_pins[] = {
+       /* MMC_SD_CLK, MMC_SD_CMD */
+       RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 22),
+};
+static const unsigned int mmc_ctrl_mux[] = {
+       MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
+};
+static const unsigned int mmc_cd_pins[] = {
+       /* SD_CD */
+       RCAR_GP_PIN(1, 23),
+};
+static const unsigned int mmc_cd_mux[] = {
+       SD_CD_MARK,
+};
+static const unsigned int mmc_wp_pins[] = {
+       /* SD_WP */
+       RCAR_GP_PIN(1, 24),
+};
+static const unsigned int mmc_wp_mux[] = {
+       SD_WP_MARK,
+};
+static const unsigned int mmc_ds_pins[] = {
+       /* MMC_DS */
+       RCAR_GP_PIN(1, 20),
+};
+static const unsigned int mmc_ds_mux[] = {
+       MMC_DS_MARK,
+};
+
+/* - MSIOF0 ----------------------------------------------------------------- */
+static const unsigned int msiof0_clk_pins[] = {
+       /* MSIOF0_SCK */
+       RCAR_GP_PIN(0, 14),
+};
+static const unsigned int msiof0_clk_mux[] = {
+       MSIOF0_SCK_MARK,
+};
+static const unsigned int msiof0_sync_pins[] = {
+       /* MSIOF0_SYNC */
+       RCAR_GP_PIN(0, 11),
+};
+static const unsigned int msiof0_sync_mux[] = {
+       MSIOF0_SYNC_MARK,
+};
+static const unsigned int msiof0_ss1_pins[] = {
+       /* MSIOF0_SS1 */
+       RCAR_GP_PIN(0, 15),
+};
+static const unsigned int msiof0_ss1_mux[] = {
+       MSIOF0_SS1_MARK,
+};
+static const unsigned int msiof0_ss2_pins[] = {
+       /* MSIOF0_SS2 */
+       RCAR_GP_PIN(0, 16),
+};
+static const unsigned int msiof0_ss2_mux[] = {
+       MSIOF0_SS2_MARK,
+};
+static const unsigned int msiof0_txd_pins[] = {
+       /* MSIOF0_TXD */
+       RCAR_GP_PIN(0, 13),
+};
+static const unsigned int msiof0_txd_mux[] = {
+       MSIOF0_TXD_MARK,
+};
+static const unsigned int msiof0_rxd_pins[] = {
+       /* MSIOF0_RXD */
+       RCAR_GP_PIN(0, 12),
+};
+static const unsigned int msiof0_rxd_mux[] = {
+       MSIOF0_RXD_MARK,
+};
+
+/* - MSIOF1 ----------------------------------------------------------------- */
+static const unsigned int msiof1_clk_pins[] = {
+       /* MSIOF1_SCK */
+       RCAR_GP_PIN(0, 8),
+};
+static const unsigned int msiof1_clk_mux[] = {
+       MSIOF1_SCK_MARK,
+};
+static const unsigned int msiof1_sync_pins[] = {
+       /* MSIOF1_SYNC */
+       RCAR_GP_PIN(0, 10),
+};
+static const unsigned int msiof1_sync_mux[] = {
+       MSIOF1_SYNC_MARK,
+};
+static const unsigned int msiof1_ss1_pins[] = {
+       /* MSIOF1_SS1 */
+       RCAR_GP_PIN(0, 17),
+};
+static const unsigned int msiof1_ss1_mux[] = {
+       MSIOF1_SS1_MARK,
+};
+static const unsigned int msiof1_ss2_pins[] = {
+       /* MSIOF1_SS2 */
+       RCAR_GP_PIN(0, 18),
+};
+static const unsigned int msiof1_ss2_mux[] = {
+       MSIOF1_SS2_MARK,
+};
+static const unsigned int msiof1_txd_pins[] = {
+       /* MSIOF1_TXD */
+       RCAR_GP_PIN(0, 7),
+};
+static const unsigned int msiof1_txd_mux[] = {
+       MSIOF1_TXD_MARK,
+};
+static const unsigned int msiof1_rxd_pins[] = {
+       /* MSIOF1_RXD */
+       RCAR_GP_PIN(0, 6),
+};
+static const unsigned int msiof1_rxd_mux[] = {
+       MSIOF1_RXD_MARK,
+};
+
+/* - MSIOF2 ----------------------------------------------------------------- */
+static const unsigned int msiof2_clk_pins[] = {
+       /* MSIOF2_SCK */
+       RCAR_GP_PIN(1, 5),
+};
+static const unsigned int msiof2_clk_mux[] = {
+       MSIOF2_SCK_MARK,
+};
+static const unsigned int msiof2_sync_pins[] = {
+       /* MSIOF2_SYNC */
+       RCAR_GP_PIN(1, 4),
+};
+static const unsigned int msiof2_sync_mux[] = {
+       MSIOF2_SYNC_MARK,
+};
+static const unsigned int msiof2_ss1_pins[] = {
+       /* MSIOF2_SS1 */
+       RCAR_GP_PIN(1, 2),
+};
+static const unsigned int msiof2_ss1_mux[] = {
+       MSIOF2_SS1_MARK,
+};
+static const unsigned int msiof2_ss2_pins[] = {
+       /* MSIOF2_SS2 */
+       RCAR_GP_PIN(1, 3),
+};
+static const unsigned int msiof2_ss2_mux[] = {
+       MSIOF2_SS2_MARK,
+};
+static const unsigned int msiof2_txd_pins[] = {
+       /* MSIOF2_TXD */
+       RCAR_GP_PIN(1, 7),
+};
+static const unsigned int msiof2_txd_mux[] = {
+       MSIOF2_TXD_MARK,
+};
+static const unsigned int msiof2_rxd_pins[] = {
+       /* MSIOF2_RXD */
+       RCAR_GP_PIN(1, 6),
+};
+static const unsigned int msiof2_rxd_mux[] = {
+       MSIOF2_RXD_MARK,
+};
+
+/* - MSIOF3 ----------------------------------------------------------------- */
+static const unsigned int msiof3_clk_pins[] = {
+       /* MSIOF3_SCK */
+       RCAR_GP_PIN(0, 1),
+};
+static const unsigned int msiof3_clk_mux[] = {
+       MSIOF3_SCK_MARK,
+};
+static const unsigned int msiof3_sync_pins[] = {
+       /* MSIOF3_SYNC */
+       RCAR_GP_PIN(0, 9),
+};
+static const unsigned int msiof3_sync_mux[] = {
+       MSIOF3_SYNC_MARK,
+};
+static const unsigned int msiof3_ss1_pins[] = {
+       /* MSIOF3_SS1 */
+       RCAR_GP_PIN(0, 4),
+};
+static const unsigned int msiof3_ss1_mux[] = {
+       MSIOF3_SS1_MARK,
+};
+static const unsigned int msiof3_ss2_pins[] = {
+       /* MSIOF3_SS2 */
+       RCAR_GP_PIN(0, 5),
+};
+static const unsigned int msiof3_ss2_mux[] = {
+       MSIOF3_SS2_MARK,
+};
+static const unsigned int msiof3_txd_pins[] = {
+       /* MSIOF3_TXD */
+       RCAR_GP_PIN(0, 3),
+};
+static const unsigned int msiof3_txd_mux[] = {
+       MSIOF3_TXD_MARK,
+};
+static const unsigned int msiof3_rxd_pins[] = {
+       /* MSIOF3_RXD */
+       RCAR_GP_PIN(0, 2),
+};
+static const unsigned int msiof3_rxd_mux[] = {
+       MSIOF3_RXD_MARK,
+};
+
+/* - PCIE ------------------------------------------------------------------- */
+static const unsigned int pcie0_clkreq_n_pins[] = {
+       /* PCIE0_CLKREQ# */
+       RCAR_GP_PIN(2, 15),
+};
+
+static const unsigned int pcie0_clkreq_n_mux[] = {
+       PCIE0_CLKREQ_N_MARK,
+};
+
+static const unsigned int pcie1_clkreq_n_pins[] = {
+       /* PCIE1_CLKREQ# */
+       RCAR_GP_PIN(2, 16),
+};
+
+static const unsigned int pcie1_clkreq_n_mux[] = {
+       PCIE1_CLKREQ_N_MARK,
+};
+
+/* - QSPI0 ------------------------------------------------------------------ */
+static const unsigned int qspi0_ctrl_pins[] = {
+       /* SPCLK, SSL */
+       RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+       QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int qspi0_data_pins[] = {
+       /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+       RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 12),
+       RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 14),
+};
+static const unsigned int qspi0_data_mux[] = {
+       QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+       QSPI0_IO2_MARK, QSPI0_IO3_MARK
+};
+
+/* - QSPI1 ------------------------------------------------------------------ */
+static const unsigned int qspi1_ctrl_pins[] = {
+       /* SPCLK, SSL */
+       RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 3),
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+       QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int qspi1_data_pins[] = {
+       /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+       RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 5),
+       RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 4),
+};
+static const unsigned int qspi1_data_mux[] = {
+       QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+       QSPI1_IO2_MARK, QSPI1_IO3_MARK
+};
+
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+       /* RX0, TX0 */
+       RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int scif0_data_mux[] = {
+       RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+       /* SCK0 */
+       RCAR_GP_PIN(0, 8),
+};
+static const unsigned int scif0_clk_mux[] = {
+       SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+       /* RTS0#, CTS0# */
+       RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+       RTS0_N_MARK, CTS0_N_MARK,
+};
+
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_pins[] = {
+       /* RX1, TX1 */
+       RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+};
+static const unsigned int scif1_data_mux[] = {
+       RX1_MARK, TX1_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+       /* SCK1 */
+       RCAR_GP_PIN(0, 14),
+};
+static const unsigned int scif1_clk_mux[] = {
+       SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+       /* RTS1#, CTS1# */
+       RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+       RTS1_N_MARK, CTS1_N_MARK,
+};
+
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_pins[] = {
+       /* RX3, TX3 */
+       RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+};
+static const unsigned int scif3_data_mux[] = {
+       RX3_MARK, TX3_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+       /* SCK3 */
+       RCAR_GP_PIN(0, 1),
+};
+static const unsigned int scif3_clk_mux[] = {
+       SCK3_MARK,
+};
+static const unsigned int scif3_ctrl_pins[] = {
+       /* RTS3#, CTS3# */
+       RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
+};
+static const unsigned int scif3_ctrl_mux[] = {
+       RTS3_N_MARK, CTS3_N_MARK,
+};
+
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_pins[] = {
+       /* RX4, TX4 */
+       RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+};
+static const unsigned int scif4_data_mux[] = {
+       RX4_MARK, TX4_MARK,
+};
+static const unsigned int scif4_clk_pins[] = {
+       /* SCK4 */
+       RCAR_GP_PIN(1, 5),
+};
+static const unsigned int scif4_clk_mux[] = {
+       SCK4_MARK,
+};
+static const unsigned int scif4_ctrl_pins[] = {
+       /* RTS4#, CTS4# */
+       RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
+};
+static const unsigned int scif4_ctrl_mux[] = {
+       RTS4_N_MARK, CTS4_N_MARK,
+};
+
+/* - SCIF Clock ------------------------------------------------------------- */
+static const unsigned int scif_clk_pins[] = {
+       /* SCIF_CLK */
+       RCAR_GP_PIN(0, 0),
+};
+static const unsigned int scif_clk_mux[] = {
+       SCIF_CLK_MARK,
+};
+
+/* - TSN0 ------------------------------------------------ */
+static const unsigned int tsn0_link_a_pins[] = {
+       /* TSN0_LINK_A */
+       RCAR_GP_PIN(0, 11),
+};
+static const unsigned int tsn0_link_a_mux[] = {
+       TSN0_LINK_A_MARK,
+};
+static const unsigned int tsn0_magic_a_pins[] = {
+       /* TSN0_MAGIC_A */
+       RCAR_GP_PIN(0, 17),
+};
+static const unsigned int tsn0_magic_a_mux[] = {
+       TSN0_MAGIC_A_MARK,
+};
+static const unsigned int tsn0_phy_int_a_pins[] = {
+       /* TSN0_PHY_INT_A */
+       RCAR_GP_PIN(0, 18),
+};
+static const unsigned int tsn0_phy_int_a_mux[] = {
+       TSN0_PHY_INT_A_MARK,
+};
+static const unsigned int tsn0_mdio_a_pins[] = {
+       /* TSN0_MDC_A, TSN0_MDIO_A */
+       RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int tsn0_mdio_a_mux[] = {
+       TSN0_MDC_A_MARK, TSN0_MDIO_A_MARK,
+};
+static const unsigned int tsn0_link_b_pins[] = {
+       /* TSN0_LINK_B */
+       RCAR_GP_PIN(3, 8),
+};
+static const unsigned int tsn0_link_b_mux[] = {
+       TSN0_LINK_B_MARK,
+};
+static const unsigned int tsn0_magic_b_pins[] = {
+       /* TSN0_MAGIC_B */
+       RCAR_GP_PIN(3, 12),
+};
+static const unsigned int tsn0_magic_b_mux[] = {
+       TSN0_MAGIC_B_MARK,
+};
+static const unsigned int tsn0_phy_int_b_pins[] = {
+       /* TSN0_PHY_INT_B */
+       RCAR_GP_PIN(3, 10),
+};
+static const unsigned int tsn0_phy_int_b_mux[] = {
+       TSN0_PHY_INT_B_MARK,
+};
+static const unsigned int tsn0_mdio_b_pins[] = {
+       /* TSN0_MDC_B, TSN0_MDIO_B */
+       RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 2),
+};
+static const unsigned int tsn0_mdio_b_mux[] = {
+       TSN0_MDC_B_MARK, TSN0_MDIO_B_MARK,
+};
+static const unsigned int tsn0_avtp_pps_pins[] = {
+       /* TSN0_AVTP_PPS */
+       RCAR_GP_PIN(3, 16),
+};
+static const unsigned int tsn0_avtp_pps_mux[] = {
+       TSN0_AVTP_PPS_MARK,
+};
+static const unsigned int tsn0_avtp_capture_a_pins[] = {
+       /* TSN0_AVTP_CAPTURE_A */
+       RCAR_GP_PIN(0, 1),
+};
+static const unsigned int tsn0_avtp_capture_a_mux[] = {
+       TSN0_AVTP_CAPTURE_A_MARK,
+};
+static const unsigned int tsn0_avtp_match_a_pins[] = {
+       /* TSN0_AVTP_MATCH_A */
+       RCAR_GP_PIN(0, 2),
+};
+static const unsigned int tsn0_avtp_match_a_mux[] = {
+       TSN0_AVTP_MATCH_A_MARK,
+};
+static const unsigned int tsn0_avtp_capture_b_pins[] = {
+       /* TSN0_AVTP_CAPTURE_B */
+       RCAR_GP_PIN(3, 18),
+};
+static const unsigned int tsn0_avtp_capture_b_mux[] = {
+       TSN0_AVTP_CAPTURE_B_MARK,
+};
+static const unsigned int tsn0_avtp_match_b_pins[] = {
+       /* TSN0_AVTP_MATCH_B */
+       RCAR_GP_PIN(3, 17),
+};
+static const unsigned int tsn0_avtp_match_b_mux[] = {
+       TSN0_AVTP_MATCH_B_MARK,
+};
+
+/* - TSN1 ------------------------------------------------ */
+static const unsigned int tsn1_link_a_pins[] = {
+       /* TSN1_LINK_A */
+       RCAR_GP_PIN(0, 15),
+};
+static const unsigned int tsn1_link_a_mux[] = {
+       TSN1_LINK_A_MARK,
+};
+static const unsigned int tsn1_phy_int_a_pins[] = {
+       /* TSN1_PHY_INT_A */
+       RCAR_GP_PIN(0, 19),
+};
+static const unsigned int tsn1_phy_int_a_mux[] = {
+       TSN1_PHY_INT_A_MARK,
+};
+static const unsigned int tsn1_mdio_a_pins[] = {
+       /* TSN1_MDC_A, TSN1_MDIO_A */
+       RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
+};
+static const unsigned int tsn1_mdio_a_mux[] = {
+       TSN1_MDC_A_MARK, TSN1_MDIO_A_MARK,
+};
+static const unsigned int tsn1_link_b_pins[] = {
+       /* TSN1_LINK_B */
+       RCAR_GP_PIN(3, 6),
+};
+static const unsigned int tsn1_link_b_mux[] = {
+       TSN1_LINK_B_MARK,
+};
+static const unsigned int tsn1_phy_int_b_pins[] = {
+       /* TSN1_PHY_INT_B */
+       RCAR_GP_PIN(3, 11),
+};
+static const unsigned int tsn1_phy_int_b_mux[] = {
+       TSN1_PHY_INT_B_MARK,
+};
+static const unsigned int tsn1_mdio_b_pins[] = {
+       /* TSN1_MDC_B, TSN1_MDIO_B */
+       RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
+};
+static const unsigned int tsn1_mdio_b_mux[] = {
+       TSN1_MDC_B_MARK, TSN1_MDIO_B_MARK,
+};
+static const unsigned int tsn1_avtp_pps_pins[] = {
+       /* TSN1_AVTP_PPS */
+       RCAR_GP_PIN(3, 13),
+};
+static const unsigned int tsn1_avtp_pps_mux[] = {
+       TSN0_AVTP_PPS_MARK,
+};
+static const unsigned int tsn1_avtp_capture_a_pins[] = {
+       /* TSN1_AVTP_CAPTURE_A */
+       RCAR_GP_PIN(0, 7),
+};
+static const unsigned int tsn1_avtp_capture_a_mux[] = {
+       TSN1_AVTP_CAPTURE_A_MARK,
+};
+static const unsigned int tsn1_avtp_match_a_pins[] = {
+       /* TSN1_AVTP_MATCH_A */
+       RCAR_GP_PIN(0, 6),
+};
+static const unsigned int tsn1_avtp_match_a_mux[] = {
+       TSN1_AVTP_MATCH_A_MARK,
+};
+static const unsigned int tsn1_avtp_capture_b_pins[] = {
+       /* TSN1_AVTP_CAPTURE_B */
+       RCAR_GP_PIN(3, 15),
+};
+static const unsigned int tsn1_avtp_capture_b_mux[] = {
+       TSN1_AVTP_CAPTURE_B_MARK,
+};
+static const unsigned int tsn1_avtp_match_b_pins[] = {
+       /* TSN1_AVTP_MATCH_B */
+       RCAR_GP_PIN(3, 14),
+};
+static const unsigned int tsn1_avtp_match_b_mux[] = {
+       TSN1_AVTP_MATCH_B_MARK,
+};
+
+/* - TSN2 ------------------------------------------------ */
+static const unsigned int tsn2_link_a_pins[] = {
+       /* TSN2_LINK_A */
+       RCAR_GP_PIN(0, 16),
+};
+static const unsigned int tsn2_link_a_mux[] = {
+       TSN2_LINK_A_MARK,
+};
+static const unsigned int tsn2_phy_int_a_pins[] = {
+       /* TSN2_PHY_INT_A */
+       RCAR_GP_PIN(0, 20),
+};
+static const unsigned int tsn2_phy_int_a_mux[] = {
+       TSN2_PHY_INT_A_MARK,
+};
+static const unsigned int tsn2_mdio_a_pins[] = {
+       /* TSN2_MDC_A, TSN2_MDIO_A */
+       RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+};
+static const unsigned int tsn2_mdio_a_mux[] = {
+       TSN2_MDC_A_MARK, TSN2_MDIO_A_MARK,
+};
+static const unsigned int tsn2_link_b_pins[] = {
+       /* TSN2_LINK_B */
+       RCAR_GP_PIN(3, 7),
+};
+static const unsigned int tsn2_link_b_mux[] = {
+       TSN2_LINK_B_MARK,
+};
+static const unsigned int tsn2_phy_int_b_pins[] = {
+       /* TSN2_PHY_INT_B */
+       RCAR_GP_PIN(3, 9),
+};
+static const unsigned int tsn2_phy_int_b_mux[] = {
+       TSN2_PHY_INT_B_MARK,
+};
+static const unsigned int tsn2_mdio_b_pins[] = {
+       /* TSN2_MDC_B, TSN2_MDIO_B */
+       RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 1),
+};
+static const unsigned int tsn2_mdio_b_mux[] = {
+       TSN2_MDC_B_MARK, TSN2_MDIO_B_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+       SH_PFC_PIN_GROUP(hscif0_data),
+       SH_PFC_PIN_GROUP(hscif0_clk),
+       SH_PFC_PIN_GROUP(hscif0_ctrl),
+       SH_PFC_PIN_GROUP(hscif1_data),
+       SH_PFC_PIN_GROUP(hscif1_clk),
+       SH_PFC_PIN_GROUP(hscif1_ctrl),
+       SH_PFC_PIN_GROUP(hscif2_data),
+       SH_PFC_PIN_GROUP(hscif2_clk),
+       SH_PFC_PIN_GROUP(hscif2_ctrl),
+       SH_PFC_PIN_GROUP(hscif3_data),
+       SH_PFC_PIN_GROUP(hscif3_clk),
+       SH_PFC_PIN_GROUP(hscif3_ctrl),
+       SH_PFC_PIN_GROUP(i2c0),
+       SH_PFC_PIN_GROUP(i2c1),
+       SH_PFC_PIN_GROUP(i2c2),
+       SH_PFC_PIN_GROUP(i2c3),
+       SH_PFC_PIN_GROUP(i2c4),
+       SH_PFC_PIN_GROUP(i2c5),
+       SH_PFC_PIN_GROUP(intc_ex_irq0),
+       SH_PFC_PIN_GROUP(intc_ex_irq1),
+       SH_PFC_PIN_GROUP(intc_ex_irq2),
+       SH_PFC_PIN_GROUP(intc_ex_irq3),
+       SH_PFC_PIN_GROUP(intc_ex_irq4),
+       SH_PFC_PIN_GROUP(intc_ex_irq5),
+       BUS_DATA_PIN_GROUP(mmc_data, 1),
+       BUS_DATA_PIN_GROUP(mmc_data, 4),
+       BUS_DATA_PIN_GROUP(mmc_data, 8),
+       SH_PFC_PIN_GROUP(mmc_ctrl),
+       SH_PFC_PIN_GROUP(mmc_cd),
+       SH_PFC_PIN_GROUP(mmc_wp),
+       SH_PFC_PIN_GROUP(mmc_ds),
+       SH_PFC_PIN_GROUP(msiof0_clk),
+       SH_PFC_PIN_GROUP(msiof0_sync),
+       SH_PFC_PIN_GROUP(msiof0_ss1),
+       SH_PFC_PIN_GROUP(msiof0_ss2),
+       SH_PFC_PIN_GROUP(msiof0_txd),
+       SH_PFC_PIN_GROUP(msiof0_rxd),
+       SH_PFC_PIN_GROUP(msiof1_clk),
+       SH_PFC_PIN_GROUP(msiof1_sync),
+       SH_PFC_PIN_GROUP(msiof1_ss1),
+       SH_PFC_PIN_GROUP(msiof1_ss2),
+       SH_PFC_PIN_GROUP(msiof1_txd),
+       SH_PFC_PIN_GROUP(msiof1_rxd),
+       SH_PFC_PIN_GROUP(msiof2_clk),
+       SH_PFC_PIN_GROUP(msiof2_sync),
+       SH_PFC_PIN_GROUP(msiof2_ss1),
+       SH_PFC_PIN_GROUP(msiof2_ss2),
+       SH_PFC_PIN_GROUP(msiof2_txd),
+       SH_PFC_PIN_GROUP(msiof2_rxd),
+       SH_PFC_PIN_GROUP(msiof3_clk),
+       SH_PFC_PIN_GROUP(msiof3_sync),
+       SH_PFC_PIN_GROUP(msiof3_ss1),
+       SH_PFC_PIN_GROUP(msiof3_ss2),
+       SH_PFC_PIN_GROUP(msiof3_txd),
+       SH_PFC_PIN_GROUP(msiof3_rxd),
+       SH_PFC_PIN_GROUP(pcie0_clkreq_n),
+       SH_PFC_PIN_GROUP(pcie1_clkreq_n),
+       SH_PFC_PIN_GROUP(qspi0_ctrl),
+       BUS_DATA_PIN_GROUP(qspi0_data, 2),
+       BUS_DATA_PIN_GROUP(qspi0_data, 4),
+       SH_PFC_PIN_GROUP(qspi1_ctrl),
+       BUS_DATA_PIN_GROUP(qspi1_data, 2),
+       BUS_DATA_PIN_GROUP(qspi1_data, 4),
+       SH_PFC_PIN_GROUP(scif0_data),
+       SH_PFC_PIN_GROUP(scif0_clk),
+       SH_PFC_PIN_GROUP(scif0_ctrl),
+       SH_PFC_PIN_GROUP(scif1_data),
+       SH_PFC_PIN_GROUP(scif1_clk),
+       SH_PFC_PIN_GROUP(scif1_ctrl),
+       SH_PFC_PIN_GROUP(scif3_data),
+       SH_PFC_PIN_GROUP(scif3_clk),
+       SH_PFC_PIN_GROUP(scif3_ctrl),
+       SH_PFC_PIN_GROUP(scif4_data),
+       SH_PFC_PIN_GROUP(scif4_clk),
+       SH_PFC_PIN_GROUP(scif4_ctrl),
+       SH_PFC_PIN_GROUP(scif_clk),
+       SH_PFC_PIN_GROUP(tsn0_link_a),
+       SH_PFC_PIN_GROUP(tsn0_magic_a),
+       SH_PFC_PIN_GROUP(tsn0_phy_int_a),
+       SH_PFC_PIN_GROUP(tsn0_mdio_a),
+       SH_PFC_PIN_GROUP(tsn0_link_b),
+       SH_PFC_PIN_GROUP(tsn0_magic_b),
+       SH_PFC_PIN_GROUP(tsn0_phy_int_b),
+       SH_PFC_PIN_GROUP(tsn0_mdio_b),
+       SH_PFC_PIN_GROUP(tsn0_avtp_pps),
+       SH_PFC_PIN_GROUP(tsn0_avtp_capture_a),
+       SH_PFC_PIN_GROUP(tsn0_avtp_match_a),
+       SH_PFC_PIN_GROUP(tsn0_avtp_capture_b),
+       SH_PFC_PIN_GROUP(tsn0_avtp_match_b),
+       SH_PFC_PIN_GROUP(tsn1_link_a),
+       SH_PFC_PIN_GROUP(tsn1_phy_int_a),
+       SH_PFC_PIN_GROUP(tsn1_mdio_a),
+       SH_PFC_PIN_GROUP(tsn1_link_b),
+       SH_PFC_PIN_GROUP(tsn1_phy_int_b),
+       SH_PFC_PIN_GROUP(tsn1_mdio_b),
+       SH_PFC_PIN_GROUP(tsn1_avtp_pps),
+       SH_PFC_PIN_GROUP(tsn1_avtp_capture_a),
+       SH_PFC_PIN_GROUP(tsn1_avtp_match_a),
+       SH_PFC_PIN_GROUP(tsn1_avtp_capture_b),
+       SH_PFC_PIN_GROUP(tsn1_avtp_match_b),
+       SH_PFC_PIN_GROUP(tsn2_link_a),
+       SH_PFC_PIN_GROUP(tsn2_phy_int_a),
+       SH_PFC_PIN_GROUP(tsn2_mdio_a),
+       SH_PFC_PIN_GROUP(tsn2_link_b),
+       SH_PFC_PIN_GROUP(tsn2_phy_int_b),
+       SH_PFC_PIN_GROUP(tsn2_mdio_b),
+};
+
+static const char * const hscif0_groups[] = {
+       "hscif0_data",
+       "hscif0_clk",
+       "hscif0_ctrl",
+};
+
+static const char * const hscif1_groups[] = {
+       "hscif1_data",
+       "hscif1_clk",
+       "hscif1_ctrl",
+};
+
+static const char * const hscif2_groups[] = {
+       "hscif2_data",
+       "hscif2_clk",
+       "hscif2_ctrl",
+};
+
+static const char * const hscif3_groups[] = {
+       "hscif3_data",
+       "hscif3_clk",
+       "hscif3_ctrl",
+};
+
+static const char * const i2c0_groups[] = {
+       "i2c0",
+};
+
+static const char * const i2c1_groups[] = {
+       "i2c1",
+};
+
+static const char * const i2c2_groups[] = {
+       "i2c2",
+};
+
+static const char * const i2c3_groups[] = {
+       "i2c3",
+};
+
+static const char * const i2c4_groups[] = {
+       "i2c4",
+};
+
+static const char * const i2c5_groups[] = {
+       "i2c5",
+};
+
+static const char * const intc_ex_groups[] = {
+       "intc_ex_irq0",
+       "intc_ex_irq1",
+       "intc_ex_irq2",
+       "intc_ex_irq3",
+       "intc_ex_irq4",
+       "intc_ex_irq5",
+};
+
+static const char * const mmc_groups[] = {
+       "mmc_data1",
+       "mmc_data4",
+       "mmc_data8",
+       "mmc_ctrl",
+       "mmc_cd",
+       "mmc_wp",
+       "mmc_ds",
+};
+
+static const char * const msiof0_groups[] = {
+       "msiof0_clk",
+       "msiof0_sync",
+       "msiof0_ss1",
+       "msiof0_ss2",
+       "msiof0_txd",
+       "msiof0_rxd",
+};
+
+static const char * const msiof1_groups[] = {
+       "msiof1_clk",
+       "msiof1_sync",
+       "msiof1_ss1",
+       "msiof1_ss2",
+       "msiof1_txd",
+       "msiof1_rxd",
+};
+
+static const char * const msiof2_groups[] = {
+       "msiof2_clk",
+       "msiof2_sync",
+       "msiof2_ss1",
+       "msiof2_ss2",
+       "msiof2_txd",
+       "msiof2_rxd",
+};
+
+static const char * const msiof3_groups[] = {
+       "msiof3_clk",
+       "msiof3_sync",
+       "msiof3_ss1",
+       "msiof3_ss2",
+       "msiof3_txd",
+       "msiof3_rxd",
+};
+
+static const char * const pcie_groups[] = {
+       "pcie0_clkreq_n",
+       "pcie1_clkreq_n",
+};
+
+static const char * const qspi0_groups[] = {
+       "qspi0_ctrl",
+       "qspi0_data2",
+       "qspi0_data4",
+};
+
+static const char * const qspi1_groups[] = {
+       "qspi1_ctrl",
+       "qspi1_data2",
+       "qspi1_data4",
+};
+
+static const char * const scif0_groups[] = {
+       "scif0_data",
+       "scif0_clk",
+       "scif0_ctrl",
+};
+
+static const char * const scif1_groups[] = {
+       "scif1_data",
+       "scif1_clk",
+       "scif1_ctrl",
+};
+
+static const char * const scif3_groups[] = {
+       "scif3_data",
+       "scif3_clk",
+       "scif3_ctrl",
+};
+
+static const char * const scif4_groups[] = {
+       "scif4_data",
+       "scif4_clk",
+       "scif4_ctrl",
+};
+
+static const char * const scif_clk_groups[] = {
+       "scif_clk",
+};
+
+static const char * const tsn0_groups[] = {
+       "tsn0_link_a",
+       "tsn0_magic_a",
+       "tsn0_phy_int_a",
+       "tsn0_mdio_a",
+       "tsn0_link_b",
+       "tsn0_magic_b",
+       "tsn0_phy_int_b",
+       "tsn0_mdio_b",
+       "tsn0_avtp_pps",
+       "tsn0_avtp_capture_a",
+       "tsn0_avtp_match_a",
+       "tsn0_avtp_capture_b",
+       "tsn0_avtp_match_b",
+};
+
+static const char * const tsn1_groups[] = {
+       "tsn1_link_a",
+       "tsn1_phy_int_a",
+       "tsn1_mdio_a",
+       "tsn1_link_b",
+       "tsn1_phy_int_b",
+       "tsn1_mdio_b",
+       "tsn1_avtp_pps",
+       "tsn1_avtp_capture_a",
+       "tsn1_avtp_match_a",
+       "tsn1_avtp_capture_b",
+       "tsn1_avtp_match_b",
+};
+
+static const char * const tsn2_groups[] = {
+       "tsn2_link_a",
+       "tsn2_phy_int_a",
+       "tsn2_mdio_a",
+       "tsn2_link_b",
+       "tsn2_phy_int_b",
+       "tsn2_mdio_b",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+       SH_PFC_FUNCTION(hscif0),
+       SH_PFC_FUNCTION(hscif1),
+       SH_PFC_FUNCTION(hscif2),
+       SH_PFC_FUNCTION(hscif3),
+       SH_PFC_FUNCTION(i2c0),
+       SH_PFC_FUNCTION(i2c1),
+       SH_PFC_FUNCTION(i2c2),
+       SH_PFC_FUNCTION(i2c3),
+       SH_PFC_FUNCTION(i2c4),
+       SH_PFC_FUNCTION(i2c5),
+       SH_PFC_FUNCTION(intc_ex),
+       SH_PFC_FUNCTION(mmc),
+       SH_PFC_FUNCTION(msiof0),
+       SH_PFC_FUNCTION(msiof1),
+       SH_PFC_FUNCTION(msiof2),
+       SH_PFC_FUNCTION(msiof3),
+       SH_PFC_FUNCTION(pcie),
+       SH_PFC_FUNCTION(qspi0),
+       SH_PFC_FUNCTION(qspi1),
+       SH_PFC_FUNCTION(scif0),
+       SH_PFC_FUNCTION(scif1),
+       SH_PFC_FUNCTION(scif3),
+       SH_PFC_FUNCTION(scif4),
+       SH_PFC_FUNCTION(scif_clk),
+       SH_PFC_FUNCTION(tsn0),
+       SH_PFC_FUNCTION(tsn1),
+       SH_PFC_FUNCTION(tsn2),
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+#define F_(x, y)       FN_##y
+#define FM(x)          FN_##x
+       { PINMUX_CFG_REG_VAR("GPSR0", 0xe6050040, 32,
+                            GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                                  1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+                            GROUP(
+               /* GP0_31_21 RESERVED */
+               GP_0_20_FN,     GPSR0_20,
+               GP_0_19_FN,     GPSR0_19,
+               GP_0_18_FN,     GPSR0_18,
+               GP_0_17_FN,     GPSR0_17,
+               GP_0_16_FN,     GPSR0_16,
+               GP_0_15_FN,     GPSR0_15,
+               GP_0_14_FN,     GPSR0_14,
+               GP_0_13_FN,     GPSR0_13,
+               GP_0_12_FN,     GPSR0_12,
+               GP_0_11_FN,     GPSR0_11,
+               GP_0_10_FN,     GPSR0_10,
+               GP_0_9_FN,      GPSR0_9,
+               GP_0_8_FN,      GPSR0_8,
+               GP_0_7_FN,      GPSR0_7,
+               GP_0_6_FN,      GPSR0_6,
+               GP_0_5_FN,      GPSR0_5,
+               GP_0_4_FN,      GPSR0_4,
+               GP_0_3_FN,      GPSR0_3,
+               GP_0_2_FN,      GPSR0_2,
+               GP_0_1_FN,      GPSR0_1,
+               GP_0_0_FN,      GPSR0_0, ))
+       },
+       { PINMUX_CFG_REG_VAR("GPSR1", 0xe6050840, 32,
+                            GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                                  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+                            GROUP(
+               /* GP1_31_25 RESERVED */
+               GP_1_24_FN,     GPSR1_24,
+               GP_1_23_FN,     GPSR1_23,
+               GP_1_22_FN,     GPSR1_22,
+               GP_1_21_FN,     GPSR1_21,
+               GP_1_20_FN,     GPSR1_20,
+               GP_1_19_FN,     GPSR1_19,
+               GP_1_18_FN,     GPSR1_18,
+               GP_1_17_FN,     GPSR1_17,
+               GP_1_16_FN,     GPSR1_16,
+               GP_1_15_FN,     GPSR1_15,
+               GP_1_14_FN,     GPSR1_14,
+               GP_1_13_FN,     GPSR1_13,
+               GP_1_12_FN,     GPSR1_12,
+               GP_1_11_FN,     GPSR1_11,
+               GP_1_10_FN,     GPSR1_10,
+               GP_1_9_FN,      GPSR1_9,
+               GP_1_8_FN,      GPSR1_8,
+               GP_1_7_FN,      GPSR1_7,
+               GP_1_6_FN,      GPSR1_6,
+               GP_1_5_FN,      GPSR1_5,
+               GP_1_4_FN,      GPSR1_4,
+               GP_1_3_FN,      GPSR1_3,
+               GP_1_2_FN,      GPSR1_2,
+               GP_1_1_FN,      GPSR1_1,
+               GP_1_0_FN,      GPSR1_0, ))
+       },
+       { PINMUX_CFG_REG_VAR("GPSR2", 0xe6051040, 32,
+                            GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                                  1, 1, 1, 1, 1, 1),
+                            GROUP(
+               /* GP2_31_17 RESERVED */
+               GP_2_16_FN,     GPSR2_16,
+               GP_2_15_FN,     GPSR2_15,
+               GP_2_14_FN,     GPSR2_14,
+               GP_2_13_FN,     GPSR2_13,
+               GP_2_12_FN,     GPSR2_12,
+               GP_2_11_FN,     GPSR2_11,
+               GP_2_10_FN,     GPSR2_10,
+               GP_2_9_FN,      GPSR2_9,
+               GP_2_8_FN,      GPSR2_8,
+               GP_2_7_FN,      GPSR2_7,
+               GP_2_6_FN,      GPSR2_6,
+               GP_2_5_FN,      GPSR2_5,
+               GP_2_4_FN,      GPSR2_4,
+               GP_2_3_FN,      GPSR2_3,
+               GP_2_2_FN,      GPSR2_2,
+               GP_2_1_FN,      GPSR2_1,
+               GP_2_0_FN,      GPSR2_0, ))
+       },
+       { PINMUX_CFG_REG_VAR("GPSR3", 0xe6051840, 32,
+                            GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                                  1, 1, 1, 1, 1, 1, 1, 1),
+                            GROUP(
+               /* GP3_31_19 RESERVED */
+               GP_3_18_FN,     GPSR3_18,
+               GP_3_17_FN,     GPSR3_17,
+               GP_3_16_FN,     GPSR3_16,
+               GP_3_15_FN,     GPSR3_15,
+               GP_3_14_FN,     GPSR3_14,
+               GP_3_13_FN,     GPSR3_13,
+               GP_3_12_FN,     GPSR3_12,
+               GP_3_11_FN,     GPSR3_11,
+               GP_3_10_FN,     GPSR3_10,
+               GP_3_9_FN,      GPSR3_9,
+               GP_3_8_FN,      GPSR3_8,
+               GP_3_7_FN,      GPSR3_7,
+               GP_3_6_FN,      GPSR3_6,
+               GP_3_5_FN,      GPSR3_5,
+               GP_3_4_FN,      GPSR3_4,
+               GP_3_3_FN,      GPSR3_3,
+               GP_3_2_FN,      GPSR3_2,
+               GP_3_1_FN,      GPSR3_1,
+               GP_3_0_FN,      GPSR3_0, ))
+       },
+#undef F_
+#undef FM
+
+#define F_(x, y)       x,
+#define FM(x)          FN_##x,
+       { PINMUX_CFG_REG("IP0SR0", 0xe6050060, 32, 4, GROUP(
+               IP0SR0_31_28
+               IP0SR0_27_24
+               IP0SR0_23_20
+               IP0SR0_19_16
+               IP0SR0_15_12
+               IP0SR0_11_8
+               IP0SR0_7_4
+               IP0SR0_3_0))
+       },
+       { PINMUX_CFG_REG("IP1SR0", 0xe6050064, 32, 4, GROUP(
+               IP1SR0_31_28
+               IP1SR0_27_24
+               IP1SR0_23_20
+               IP1SR0_19_16
+               IP1SR0_15_12
+               IP1SR0_11_8
+               IP1SR0_7_4
+               IP1SR0_3_0))
+       },
+       { PINMUX_CFG_REG_VAR("IP2SR0", 0xe6050068, 32,
+                            GROUP(-12, 4, 4, 4, 4, 4),
+                            GROUP(
+               /* IP2SR0_31_20 RESERVED */
+               IP2SR0_19_16
+               IP2SR0_15_12
+               IP2SR0_11_8
+               IP2SR0_7_4
+               IP2SR0_3_0))
+       },
+       { PINMUX_CFG_REG("IP0SR1", 0xe6050860, 32, 4, GROUP(
+               IP0SR1_31_28
+               IP0SR1_27_24
+               IP0SR1_23_20
+               IP0SR1_19_16
+               IP0SR1_15_12
+               IP0SR1_11_8
+               IP0SR1_7_4
+               IP0SR1_3_0))
+       },
+#undef F_
+#undef FM
+
+#define F_(x, y)       x,
+#define FM(x)          FN_##x,
+       { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6050900, 32,
+                            GROUP(-20, 2, 2, 2, 2, 2, 2),
+                            GROUP(
+               /* RESERVED 31-12 */
+               MOD_SEL1_11_10
+               MOD_SEL1_9_8
+               MOD_SEL1_7_6
+               MOD_SEL1_5_4
+               MOD_SEL1_3_2
+               MOD_SEL1_1_0))
+       },
+       { /* sentinel */ },
+};
+
+static const struct pinmux_drive_reg pinmux_drive_regs[] = {
+       { PINMUX_DRIVE_REG("DRV0CTRL0", 0xe6050080) {
+               { RCAR_GP_PIN(0,  7), 28, 3 },  /* TX0 */
+               { RCAR_GP_PIN(0,  6), 24, 3 },  /* RX0 */
+               { RCAR_GP_PIN(0,  5), 20, 3 },  /* HRTS0_N */
+               { RCAR_GP_PIN(0,  4), 16, 3 },  /* HCTS0_N */
+               { RCAR_GP_PIN(0,  3), 12, 3 },  /* HTX0 */
+               { RCAR_GP_PIN(0,  2),  8, 3 },  /* HRX0 */
+               { RCAR_GP_PIN(0,  1),  4, 3 },  /* HSCK0 */
+               { RCAR_GP_PIN(0,  0),  0, 3 },  /* SCIF_CLK */
+       } },
+       { PINMUX_DRIVE_REG("DRV1CTRL0", 0xe6050084) {
+               { RCAR_GP_PIN(0, 15), 28, 3 },  /* MSIOF0_SS1 */
+               { RCAR_GP_PIN(0, 14), 24, 3 },  /* MSIOF0_SCK */
+               { RCAR_GP_PIN(0, 13), 20, 3 },  /* MSIOF0_TXD */
+               { RCAR_GP_PIN(0, 12), 16, 3 },  /* MSIOF0_RXD */
+               { RCAR_GP_PIN(0, 11), 12, 3 },  /* MSIOF0_SYNC */
+               { RCAR_GP_PIN(0, 10),  8, 3 },  /* CTS0_N */
+               { RCAR_GP_PIN(0,  9),  4, 3 },  /* RTS0_N */
+               { RCAR_GP_PIN(0,  8),  0, 3 },  /* SCK0 */
+       } },
+       { PINMUX_DRIVE_REG("DRV2CTRL0", 0xe6050088) {
+               { RCAR_GP_PIN(0, 20), 16, 3 },  /* IRQ3 */
+               { RCAR_GP_PIN(0, 19), 12, 3 },  /* IRQ2 */
+               { RCAR_GP_PIN(0, 18),  8, 3 },  /* IRQ1 */
+               { RCAR_GP_PIN(0, 17),  4, 3 },  /* IRQ0 */
+               { RCAR_GP_PIN(0, 16),  0, 3 },  /* MSIOF0_SS2 */
+       } },
+       { PINMUX_DRIVE_REG("DRV0CTRL1", 0xe6050880) {
+               { RCAR_GP_PIN(1,  7), 28, 3 },  /* GP1_07 */
+               { RCAR_GP_PIN(1,  6), 24, 3 },  /* GP1_06 */
+               { RCAR_GP_PIN(1,  5), 20, 3 },  /* GP1_05 */
+               { RCAR_GP_PIN(1,  4), 16, 3 },  /* GP1_04 */
+               { RCAR_GP_PIN(1,  3), 12, 3 },  /* GP1_03 */
+               { RCAR_GP_PIN(1,  2),  8, 3 },  /* GP1_02 */
+               { RCAR_GP_PIN(1,  1),  4, 3 },  /* GP1_01 */
+               { RCAR_GP_PIN(1,  0),  0, 3 },  /* GP1_00 */
+       } },
+       { PINMUX_DRIVE_REG("DRV1CTRL1", 0xe6050884) {
+               { RCAR_GP_PIN(1, 15), 28, 3 },  /* MMC_SD_D2 */
+               { RCAR_GP_PIN(1, 14), 24, 3 },  /* MMC_SD_D1 */
+               { RCAR_GP_PIN(1, 13), 20, 3 },  /* MMC_SD_D0 */
+               { RCAR_GP_PIN(1, 12), 16, 3 },  /* MMC_SD_CLK */
+               { RCAR_GP_PIN(1, 11), 12, 3 },  /* GP1_11 */
+               { RCAR_GP_PIN(1, 10),  8, 3 },  /* GP1_10 */
+               { RCAR_GP_PIN(1,  9),  4, 3 },  /* GP1_09 */
+               { RCAR_GP_PIN(1,  8),  0, 3 },  /* GP1_08 */
+       } },
+       { PINMUX_DRIVE_REG("DRV2CTRL1", 0xe6050888) {
+               { RCAR_GP_PIN(1, 23), 28, 3 },  /* SD_CD */
+               { RCAR_GP_PIN(1, 22), 24, 3 },  /* MMC_SD_CMD */
+               { RCAR_GP_PIN(1, 21), 20, 3 },  /* MMC_D7 */
+               { RCAR_GP_PIN(1, 20), 16, 3 },  /* MMC_DS */
+               { RCAR_GP_PIN(1, 19), 12, 3 },  /* MMC_D6 */
+               { RCAR_GP_PIN(1, 18),  8, 3 },  /* MMC_D4 */
+               { RCAR_GP_PIN(1, 17),  4, 3 },  /* MMC_D5 */
+               { RCAR_GP_PIN(1, 16),  0, 3 },  /* MMC_SD_D3 */
+       } },
+       { PINMUX_DRIVE_REG("DRV3CTRL1", 0xe605088c) {
+               { RCAR_GP_PIN(1, 24),  0, 3 },  /* SD_WP */
+       } },
+       { PINMUX_DRIVE_REG("DRV0CTRL2", 0xe6051080) {
+               { RCAR_GP_PIN(2,  7), 28, 2 },  /* QSPI1_MOSI_IO0 */
+               { RCAR_GP_PIN(2,  6), 24, 2 },  /* QSPI1_IO2 */
+               { RCAR_GP_PIN(2,  5), 20, 2 },  /* QSPI1_MISO_IO1 */
+               { RCAR_GP_PIN(2,  4), 16, 2 },  /* QSPI1_IO3 */
+               { RCAR_GP_PIN(2,  3), 12, 2 },  /* QSPI1_SSL */
+               { RCAR_GP_PIN(2,  2),  8, 2 },  /* RPC_RESET_N */
+               { RCAR_GP_PIN(2,  1),  4, 2 },  /* RPC_WP_N */
+               { RCAR_GP_PIN(2,  0),  0, 2 },  /* RPC_INT_N */
+       } },
+       { PINMUX_DRIVE_REG("DRV1CTRL2", 0xe6051084) {
+               { RCAR_GP_PIN(2, 15), 28, 3 },  /* PCIE0_CLKREQ_N */
+               { RCAR_GP_PIN(2, 14), 24, 2 },  /* QSPI0_IO3 */
+               { RCAR_GP_PIN(2, 13), 20, 2 },  /* QSPI0_SSL */
+               { RCAR_GP_PIN(2, 12), 16, 2 },  /* QSPI0_MISO_IO1 */
+               { RCAR_GP_PIN(2, 11), 12, 2 },  /* QSPI0_IO2 */
+               { RCAR_GP_PIN(2, 10),  8, 2 },  /* QSPI0_SPCLK */
+               { RCAR_GP_PIN(2,  9),  4, 2 },  /* QSPI0_MOSI_IO0 */
+               { RCAR_GP_PIN(2,  8),  0, 2 },  /* QSPI1_SPCLK */
+       } },
+       { PINMUX_DRIVE_REG("DRV2CTRL2", 0xe6051088) {
+               { RCAR_GP_PIN(2, 16),  0, 3 },  /* PCIE1_CLKREQ_N */
+       } },
+       { PINMUX_DRIVE_REG("DRV0CTRL3", 0xe6051880) {
+               { RCAR_GP_PIN(3,  7), 28, 3 },  /* TSN2_LINK_B */
+               { RCAR_GP_PIN(3,  6), 24, 3 },  /* TSN1_LINK_B */
+               { RCAR_GP_PIN(3,  5), 20, 3 },  /* TSN1_MDC_B */
+               { RCAR_GP_PIN(3,  4), 16, 3 },  /* TSN0_MDC_B */
+               { RCAR_GP_PIN(3,  3), 12, 3 },  /* TSN2_MDC_B */
+               { RCAR_GP_PIN(3,  2),  8, 3 },  /* TSN0_MDIO_B */
+               { RCAR_GP_PIN(3,  1),  4, 3 },  /* TSN2_MDIO_B */
+               { RCAR_GP_PIN(3,  0),  0, 3 },  /* TSN1_MDIO_B */
+       } },
+       { PINMUX_DRIVE_REG("DRV1CTRL3", 0xe6051884) {
+               { RCAR_GP_PIN(3, 15), 28, 3 },  /* TSN1_AVTP_CAPTURE_B */
+               { RCAR_GP_PIN(3, 14), 24, 3 },  /* TSN1_AVTP_MATCH_B */
+               { RCAR_GP_PIN(3, 13), 20, 3 },  /* TSN1_AVTP_PPS */
+               { RCAR_GP_PIN(3, 12), 16, 3 },  /* TSN0_MAGIC_B */
+               { RCAR_GP_PIN(3, 11), 12, 3 },  /* TSN1_PHY_INT_B */
+               { RCAR_GP_PIN(3, 10),  8, 3 },  /* TSN0_PHY_INT_B */
+               { RCAR_GP_PIN(3,  9),  4, 3 },  /* TSN2_PHY_INT_B */
+               { RCAR_GP_PIN(3,  8),  0, 3 },  /* TSN0_LINK_B */
+       } },
+       { PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6051888) {
+               { RCAR_GP_PIN(3, 18),  8, 3 },  /* TSN0_AVTP_CAPTURE_B */
+               { RCAR_GP_PIN(3, 17),  4, 3 },  /* TSN0_AVTP_MATCH_B */
+               { RCAR_GP_PIN(3, 16),  0, 3 },  /* TSN0_AVTP_PPS */
+       } },
+       { /* sentinel */ },
+};
+
+enum ioctrl_regs {
+       POC0,
+       POC1,
+       POC3,
+       TD0SEL1,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+       [POC0] = { 0xe60500a0, },
+       [POC1] = { 0xe60508a0, },
+       [POC3] = { 0xe60518a0, },
+       [TD0SEL1] = { 0xe6050920, },
+       { /* sentinel */ },
+};
+
+static int r8a779f0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
+{
+       int bit = pin & 0x1f;
+
+       *pocctrl = pinmux_ioctrl_regs[POC0].reg;
+       if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 20))
+               return bit;
+
+       *pocctrl = pinmux_ioctrl_regs[POC1].reg;
+       if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 24))
+               return bit;
+
+       *pocctrl = pinmux_ioctrl_regs[POC3].reg;
+       if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 18))
+               return bit;
+
+       return -EINVAL;
+}
+
+static const struct pinmux_bias_reg pinmux_bias_regs[] = {
+       { PINMUX_BIAS_REG("PUEN0", 0xe60500c0, "PUD0", 0xe60500e0) {
+               [ 0] = RCAR_GP_PIN(0,  0),      /* SCIF_CLK */
+               [ 1] = RCAR_GP_PIN(0,  1),      /* HSCK0 */
+               [ 2] = RCAR_GP_PIN(0,  2),      /* HRX0 */
+               [ 3] = RCAR_GP_PIN(0,  3),      /* HTX0 */
+               [ 4] = RCAR_GP_PIN(0,  4),      /* HCTS0_N */
+               [ 5] = RCAR_GP_PIN(0,  5),      /* HRTS0_N */
+               [ 6] = RCAR_GP_PIN(0,  6),      /* RX0 */
+               [ 7] = RCAR_GP_PIN(0,  7),      /* TX0 */
+               [ 8] = RCAR_GP_PIN(0,  8),      /* SCK0 */
+               [ 9] = RCAR_GP_PIN(0,  9),      /* RTS0_N */
+               [10] = RCAR_GP_PIN(0, 10),      /* CTS0_N */
+               [11] = RCAR_GP_PIN(0, 11),      /* MSIOF0_SYNC */
+               [12] = RCAR_GP_PIN(0, 12),      /* MSIOF0_RXD */
+               [13] = RCAR_GP_PIN(0, 13),      /* MSIOF0_TXD */
+               [14] = RCAR_GP_PIN(0, 14),      /* MSIOF0_SCK */
+               [15] = RCAR_GP_PIN(0, 15),      /* MSIOF0_SS1 */
+               [16] = RCAR_GP_PIN(0, 16),      /* MSIOF0_SS2 */
+               [17] = RCAR_GP_PIN(0, 17),      /* IRQ0 */
+               [18] = RCAR_GP_PIN(0, 18),      /* IRQ1 */
+               [19] = RCAR_GP_PIN(0, 19),      /* IRQ2 */
+               [20] = RCAR_GP_PIN(0, 20),      /* IRQ3 */
+               [21] = SH_PFC_PIN_NONE,
+               [22] = SH_PFC_PIN_NONE,
+               [23] = SH_PFC_PIN_NONE,
+               [24] = SH_PFC_PIN_NONE,
+               [25] = SH_PFC_PIN_NONE,
+               [26] = SH_PFC_PIN_NONE,
+               [27] = SH_PFC_PIN_NONE,
+               [28] = SH_PFC_PIN_NONE,
+               [29] = SH_PFC_PIN_NONE,
+               [30] = SH_PFC_PIN_NONE,
+               [31] = SH_PFC_PIN_NONE,
+       } },
+       { PINMUX_BIAS_REG("PUEN1", 0xe60508c0, "PUD1", 0xe60508e0) {
+               [ 0] = RCAR_GP_PIN(1,  0),      /* GP1_00 */
+               [ 1] = RCAR_GP_PIN(1,  1),      /* GP1_01 */
+               [ 2] = RCAR_GP_PIN(1,  2),      /* GP1_02 */
+               [ 3] = RCAR_GP_PIN(1,  3),      /* GP1_03 */
+               [ 4] = RCAR_GP_PIN(1,  4),      /* GP1_04 */
+               [ 5] = RCAR_GP_PIN(1,  5),      /* GP1_05 */
+               [ 6] = RCAR_GP_PIN(1,  6),      /* GP1_06 */
+               [ 7] = RCAR_GP_PIN(1,  7),      /* GP1_07 */
+               [ 8] = RCAR_GP_PIN(1,  8),      /* GP1_08 */
+               [ 9] = RCAR_GP_PIN(1,  9),      /* GP1_09 */
+               [10] = RCAR_GP_PIN(1, 10),      /* GP1_10 */
+               [11] = RCAR_GP_PIN(1, 11),      /* GP1_11 */
+               [12] = RCAR_GP_PIN(1, 12),      /* MMC_SD_CLK */
+               [13] = RCAR_GP_PIN(1, 13),      /* MMC_SD_D0 */
+               [14] = RCAR_GP_PIN(1, 14),      /* MMC_SD_D1 */
+               [15] = RCAR_GP_PIN(1, 15),      /* MMC_SD_D2 */
+               [16] = RCAR_GP_PIN(1, 16),      /* MMC_SD_D3 */
+               [17] = RCAR_GP_PIN(1, 17),      /* MMC_D5 */
+               [18] = RCAR_GP_PIN(1, 18),      /* MMC_D4 */
+               [19] = RCAR_GP_PIN(1, 19),      /* MMC_D6 */
+               [20] = RCAR_GP_PIN(1, 20),      /* MMC_DS */
+               [21] = RCAR_GP_PIN(1, 21),      /* MMC_D7 */
+               [22] = RCAR_GP_PIN(1, 22),      /* MMC_SD_CMD */
+               [23] = RCAR_GP_PIN(1, 23),      /* SD_CD */
+               [24] = RCAR_GP_PIN(1, 24),      /* SD_WP */
+               [25] = SH_PFC_PIN_NONE,
+               [26] = SH_PFC_PIN_NONE,
+               [27] = SH_PFC_PIN_NONE,
+               [28] = SH_PFC_PIN_NONE,
+               [29] = SH_PFC_PIN_NONE,
+               [30] = SH_PFC_PIN_NONE,
+               [31] = SH_PFC_PIN_NONE,
+       } },
+       { PINMUX_BIAS_REG("PUEN2", 0xe60510c0, "PUD2", 0xe60510e0) {
+               [ 0] = RCAR_GP_PIN(2,  0),      /* RPC_INT_N */
+               [ 1] = RCAR_GP_PIN(2,  1),      /* RPC_WP_N */
+               [ 2] = RCAR_GP_PIN(2,  2),      /* RPC_RESET_N */
+               [ 3] = RCAR_GP_PIN(2,  3),      /* QSPI1_SSL */
+               [ 4] = RCAR_GP_PIN(2,  4),      /* QSPI1_IO3 */
+               [ 5] = RCAR_GP_PIN(2,  5),      /* QSPI1_MISO_IO1 */
+               [ 6] = RCAR_GP_PIN(2,  6),      /* QSPI1_IO2 */
+               [ 7] = RCAR_GP_PIN(2,  7),      /* QSPI1_MOSI_IO0 */
+               [ 8] = RCAR_GP_PIN(2,  8),      /* QSPI1_SPCLK */
+               [ 9] = RCAR_GP_PIN(2,  9),      /* QSPI0_MOSI_IO0 */
+               [10] = RCAR_GP_PIN(2, 10),      /* QSPI0_SPCLK */
+               [11] = RCAR_GP_PIN(2, 11),      /* QSPI0_IO2 */
+               [12] = RCAR_GP_PIN(2, 12),      /* QSPI0_MISO_IO1 */
+               [13] = RCAR_GP_PIN(2, 13),      /* QSPI0_SSL */
+               [14] = RCAR_GP_PIN(2, 14),      /* QSPI0_IO3 */
+               [15] = RCAR_GP_PIN(2, 15),      /* PCIE0_CLKREQ_N */
+               [16] = RCAR_GP_PIN(2, 16),      /* PCIE1_CLKREQ_N */
+               [17] = SH_PFC_PIN_NONE,
+               [18] = SH_PFC_PIN_NONE,
+               [19] = SH_PFC_PIN_NONE,
+               [20] = SH_PFC_PIN_NONE,
+               [21] = SH_PFC_PIN_NONE,
+               [22] = SH_PFC_PIN_NONE,
+               [23] = SH_PFC_PIN_NONE,
+               [24] = SH_PFC_PIN_NONE,
+               [25] = SH_PFC_PIN_NONE,
+               [26] = SH_PFC_PIN_NONE,
+               [27] = SH_PFC_PIN_NONE,
+               [28] = SH_PFC_PIN_NONE,
+               [29] = SH_PFC_PIN_NONE,
+               [30] = SH_PFC_PIN_NONE,
+               [31] = SH_PFC_PIN_NONE,
+       } },
+       { PINMUX_BIAS_REG("PUEN3", 0xe60518c0, "PUD3", 0xe60518e0) {
+               [ 0] = RCAR_GP_PIN(3,  0),      /* TSN1_MDIO_B */
+               [ 1] = RCAR_GP_PIN(3,  1),      /* TSN2_MDIO_B */
+               [ 2] = RCAR_GP_PIN(3,  2),      /* TSN0_MDIO_B */
+               [ 3] = RCAR_GP_PIN(3,  3),      /* TSN2_MDC_B */
+               [ 4] = RCAR_GP_PIN(3,  4),      /* TSN0_MDC_B */
+               [ 5] = RCAR_GP_PIN(3,  5),      /* TSN1_MDC_B */
+               [ 6] = RCAR_GP_PIN(3,  6),      /* TSN1_LINK_B */
+               [ 7] = RCAR_GP_PIN(3,  7),      /* TSN2_LINK_B */
+               [ 8] = RCAR_GP_PIN(3,  8),      /* TSN0_LINK_B */
+               [ 9] = RCAR_GP_PIN(3,  9),      /* TSN2_PHY_INT_B */
+               [10] = RCAR_GP_PIN(3, 10),      /* TSN0_PHY_INT_B */
+               [11] = RCAR_GP_PIN(3, 11),      /* TSN1_PHY_INT_B */
+               [12] = RCAR_GP_PIN(3, 12),      /* TSN0_MAGIC_B */
+               [13] = RCAR_GP_PIN(3, 13),      /* TSN1_AVTP_PPS */
+               [14] = RCAR_GP_PIN(3, 14),      /* TSN1_AVTP_MATCH_B */
+               [15] = RCAR_GP_PIN(3, 15),      /* TSN1_AVTP_CAPTURE_B */
+               [16] = RCAR_GP_PIN(3, 16),      /* TSN0_AVTP_PPS */
+               [17] = RCAR_GP_PIN(3, 17),      /* TSN0_AVTP_MATCH_B */
+               [18] = RCAR_GP_PIN(3, 18),      /* TSN0_AVTP_CAPTURE_B */
+               [19] = SH_PFC_PIN_NONE,
+               [20] = SH_PFC_PIN_NONE,
+               [21] = SH_PFC_PIN_NONE,
+               [22] = SH_PFC_PIN_NONE,
+               [23] = SH_PFC_PIN_NONE,
+               [24] = SH_PFC_PIN_NONE,
+               [25] = SH_PFC_PIN_NONE,
+               [26] = SH_PFC_PIN_NONE,
+               [27] = SH_PFC_PIN_NONE,
+               [28] = SH_PFC_PIN_NONE,
+               [29] = SH_PFC_PIN_NONE,
+               [30] = SH_PFC_PIN_NONE,
+               [31] = SH_PFC_PIN_NONE,
+       } },
+       { /* sentinel */ },
+};
+
+static const struct sh_pfc_soc_operations r8a779f0_pfc_ops = {
+       .pin_to_pocctrl = r8a779f0_pin_to_pocctrl,
+       .get_bias = rcar_pinmux_get_bias,
+       .set_bias = rcar_pinmux_set_bias,
+};
+
+const struct sh_pfc_soc_info r8a779f0_pinmux_info = {
+       .name = "r8a779f0_pfc",
+       .ops = &r8a779f0_pfc_ops,
+       .unlock_reg = 0x1ff,    /* PMMRn mask */
+
+       .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+       .pins = pinmux_pins,
+       .nr_pins = ARRAY_SIZE(pinmux_pins),
+       .groups = pinmux_groups,
+       .nr_groups = ARRAY_SIZE(pinmux_groups),
+       .functions = pinmux_functions,
+       .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+       .cfg_regs = pinmux_config_regs,
+       .drive_regs = pinmux_drive_regs,
+       .bias_regs = pinmux_bias_regs,
+       .ioctrl_regs = pinmux_ioctrl_regs,
+
+       .pinmux_data = pinmux_data,
+       .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};

diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
new file mode 100644 (file)
index 0000000..78a91f4
--- /dev/null
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -0,0 +1,4265 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R8A779A0 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ *
+ * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/pinctrl.h>
+#include <linux/bitops.h>
+#include <linux/kernel.h>
+
+#include "sh_pfc.h"
+
+#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
+
+#define CPU_ALL_GP(fn, sfx)                                                            \
+       PORT_GP_CFG_19(0,       fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),  \
+       PORT_GP_CFG_23(1,       fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),  \
+       PORT_GP_CFG_1(1, 23,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(1, 24,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(1, 25,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(1, 26,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(1, 27,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(1, 28,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_20(2,       fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_13(3,       fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),  \
+       PORT_GP_CFG_1(3, 13,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(3, 14,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(3, 15,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(3, 16,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(3, 17,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(3, 18,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(3, 19,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(3, 20,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(3, 21,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(3, 22,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(3, 23,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(3, 24,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(3, 25,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(3, 26,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(3, 27,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(3, 28,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_1(3, 29,    fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_25(4,       fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_21(5,       fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_21(6,       fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_21(7,       fn, sfx, CFG_FLAGS),                                    \
+       PORT_GP_CFG_14(8,       fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
+
+/* GPSR0 */
+#define GPSR0_18       F_(MSIOF2_RXD,          IP2SR0_11_8)
+#define GPSR0_17       F_(MSIOF2_SCK,          IP2SR0_7_4)
+#define GPSR0_16       F_(MSIOF2_TXD,          IP2SR0_3_0)
+#define GPSR0_15       F_(MSIOF2_SYNC,         IP1SR0_31_28)
+#define GPSR0_14       F_(MSIOF2_SS1,          IP1SR0_27_24)
+#define GPSR0_13       F_(MSIOF2_SS2,          IP1SR0_23_20)
+#define GPSR0_12       F_(MSIOF5_RXD,          IP1SR0_19_16)
+#define GPSR0_11       F_(MSIOF5_SCK,          IP1SR0_15_12)
+#define GPSR0_10       F_(MSIOF5_TXD,          IP1SR0_11_8)
+#define GPSR0_9                F_(MSIOF5_SYNC,         IP1SR0_7_4)
+#define GPSR0_8                F_(MSIOF5_SS1,          IP1SR0_3_0)
+#define GPSR0_7                F_(MSIOF5_SS2,          IP0SR0_31_28)
+#define GPSR0_6                F_(IRQ0,                IP0SR0_27_24)
+#define GPSR0_5                F_(IRQ1,                IP0SR0_23_20)
+#define GPSR0_4                F_(IRQ2,                IP0SR0_19_16)
+#define GPSR0_3                F_(IRQ3,                IP0SR0_15_12)
+#define GPSR0_2                F_(GP0_02,              IP0SR0_11_8)
+#define GPSR0_1                F_(GP0_01,              IP0SR0_7_4)
+#define GPSR0_0                F_(GP0_00,              IP0SR0_3_0)
+
+/* GPSR1 */
+#define GPSR1_28       F_(HTX3,                IP3SR1_19_16)
+#define GPSR1_27       F_(HCTS3_N,             IP3SR1_15_12)
+#define GPSR1_26       F_(HRTS3_N,             IP3SR1_11_8)
+#define GPSR1_25       F_(HSCK3,               IP3SR1_7_4)
+#define GPSR1_24       F_(HRX3,                IP3SR1_3_0)
+#define GPSR1_23       F_(GP1_23,              IP2SR1_31_28)
+#define GPSR1_22       F_(AUDIO_CLKIN,         IP2SR1_27_24)
+#define GPSR1_21       F_(AUDIO_CLKOUT,        IP2SR1_23_20)
+#define GPSR1_20       F_(SSI_SD,              IP2SR1_19_16)
+#define GPSR1_19       F_(SSI_WS,              IP2SR1_15_12)
+#define GPSR1_18       F_(SSI_SCK,             IP2SR1_11_8)
+#define GPSR1_17       F_(SCIF_CLK,            IP2SR1_7_4)
+#define GPSR1_16       F_(HRX0,                IP2SR1_3_0)
+#define GPSR1_15       F_(HSCK0,               IP1SR1_31_28)
+#define GPSR1_14       F_(HRTS0_N,             IP1SR1_27_24)
+#define GPSR1_13       F_(HCTS0_N,             IP1SR1_23_20)
+#define GPSR1_12       F_(HTX0,                IP1SR1_19_16)
+#define GPSR1_11       F_(MSIOF0_RXD,          IP1SR1_15_12)
+#define GPSR1_10       F_(MSIOF0_SCK,          IP1SR1_11_8)
+#define GPSR1_9                F_(MSIOF0_TXD,          IP1SR1_7_4)
+#define GPSR1_8                F_(MSIOF0_SYNC,         IP1SR1_3_0)
+#define GPSR1_7                F_(MSIOF0_SS1,          IP0SR1_31_28)
+#define GPSR1_6                F_(MSIOF0_SS2,          IP0SR1_27_24)
+#define GPSR1_5                F_(MSIOF1_RXD,          IP0SR1_23_20)
+#define GPSR1_4                F_(MSIOF1_TXD,          IP0SR1_19_16)
+#define GPSR1_3                F_(MSIOF1_SCK,          IP0SR1_15_12)
+#define GPSR1_2                F_(MSIOF1_SYNC,         IP0SR1_11_8)
+#define GPSR1_1                F_(MSIOF1_SS1,          IP0SR1_7_4)
+#define GPSR1_0                F_(MSIOF1_SS2,          IP0SR1_3_0)
+
+/* GPSR2 */
+#define GPSR2_19       F_(CANFD7_RX,           IP2SR2_15_12)
+#define GPSR2_18       F_(CANFD7_TX,           IP2SR2_11_8)
+#define GPSR2_17       F_(CANFD4_RX,           IP2SR2_7_4)
+#define GPSR2_16       F_(CANFD4_TX,           IP2SR2_3_0)
+#define GPSR2_15       F_(CANFD3_RX,           IP1SR2_31_28)
+#define GPSR2_14       F_(CANFD3_TX,           IP1SR2_27_24)
+#define GPSR2_13       F_(CANFD2_RX,           IP1SR2_23_20)
+#define GPSR2_12       F_(CANFD2_TX,           IP1SR2_19_16)
+#define GPSR2_11       F_(CANFD0_RX,           IP1SR2_15_12)
+#define GPSR2_10       F_(CANFD0_TX,           IP1SR2_11_8)
+#define GPSR2_9                F_(CAN_CLK,             IP1SR2_7_4)
+#define GPSR2_8                F_(TPU0TO0,             IP1SR2_3_0)
+#define GPSR2_7                F_(TPU0TO1,             IP0SR2_31_28)
+#define GPSR2_6                F_(FXR_TXDB,            IP0SR2_27_24)
+#define GPSR2_5                F_(FXR_TXENB_N,         IP0SR2_23_20)
+#define GPSR2_4                F_(RXDB_EXTFXR,         IP0SR2_19_16)
+#define GPSR2_3                F_(CLK_EXTFXR,          IP0SR2_15_12)
+#define GPSR2_2                F_(RXDA_EXTFXR,         IP0SR2_11_8)
+#define GPSR2_1                F_(FXR_TXENA_N,         IP0SR2_7_4)
+#define GPSR2_0                F_(FXR_TXDA,            IP0SR2_3_0)
+
+/* GPSR3 */
+#define GPSR3_29       F_(RPC_INT_N,           IP3SR3_23_20)
+#define GPSR3_28       F_(RPC_WP_N,            IP3SR3_19_16)
+#define GPSR3_27       F_(RPC_RESET_N,         IP3SR3_15_12)
+#define GPSR3_26       F_(QSPI1_IO3,           IP3SR3_11_8)
+#define GPSR3_25       F_(QSPI1_SSL,           IP3SR3_7_4)
+#define GPSR3_24       F_(QSPI1_IO2,           IP3SR3_3_0)
+#define GPSR3_23       F_(QSPI1_MISO_IO1,      IP2SR3_31_28)
+#define GPSR3_22       F_(QSPI1_SPCLK,         IP2SR3_27_24)
+#define GPSR3_21       F_(QSPI1_MOSI_IO0,      IP2SR3_23_20)
+#define GPSR3_20       F_(QSPI0_SPCLK,         IP2SR3_19_16)
+#define GPSR3_19       F_(QSPI0_MOSI_IO0,      IP2SR3_15_12)
+#define GPSR3_18       F_(QSPI0_MISO_IO1,      IP2SR3_11_8)
+#define GPSR3_17       F_(QSPI0_IO2,           IP2SR3_7_4)
+#define GPSR3_16       F_(QSPI0_IO3,           IP2SR3_3_0)
+#define GPSR3_15       F_(QSPI0_SSL,           IP1SR3_31_28)
+#define GPSR3_14       F_(IPC_CLKOUT,          IP1SR3_27_24)
+#define GPSR3_13       F_(IPC_CLKIN,           IP1SR3_23_20)
+#define GPSR3_12       F_(SD_WP,               IP1SR3_19_16)
+#define GPSR3_11       F_(SD_CD,               IP1SR3_15_12)
+#define GPSR3_10       F_(MMC_SD_CMD,          IP1SR3_11_8)
+#define GPSR3_9                F_(MMC_D6,              IP1SR3_7_4)
+#define GPSR3_8                F_(MMC_D7,              IP1SR3_3_0)
+#define GPSR3_7                F_(MMC_D4,              IP0SR3_31_28)
+#define GPSR3_6                F_(MMC_D5,              IP0SR3_27_24)
+#define GPSR3_5                F_(MMC_SD_D3,           IP0SR3_23_20)
+#define GPSR3_4                F_(MMC_DS,              IP0SR3_19_16)
+#define GPSR3_3                F_(MMC_SD_CLK,          IP0SR3_15_12)
+#define GPSR3_2                F_(MMC_SD_D2,           IP0SR3_11_8)
+#define GPSR3_1                F_(MMC_SD_D0,           IP0SR3_7_4)
+#define GPSR3_0                F_(MMC_SD_D1,           IP0SR3_3_0)
+
+/* GPSR4 */
+#define GPSR4_24       FM(AVS1)
+#define GPSR4_23       FM(AVS0)
+#define GPSR4_22       FM(PCIE1_CLKREQ_N)
+#define GPSR4_21       FM(PCIE0_CLKREQ_N)
+#define GPSR4_20       FM(TSN0_TXCREFCLK)
+#define GPSR4_19       FM(TSN0_TD2)
+#define GPSR4_18       FM(TSN0_TD3)
+#define GPSR4_17       FM(TSN0_RD2)
+#define GPSR4_16       FM(TSN0_RD3)
+#define GPSR4_15       FM(TSN0_TD0)
+#define GPSR4_14       FM(TSN0_TD1)
+#define GPSR4_13       FM(TSN0_RD1)
+#define GPSR4_12       FM(TSN0_TXC)
+#define GPSR4_11       FM(TSN0_RXC)
+#define GPSR4_10       FM(TSN0_RD0)
+#define GPSR4_9                FM(TSN0_TX_CTL)
+#define GPSR4_8                FM(TSN0_AVTP_PPS0)
+#define GPSR4_7                FM(TSN0_RX_CTL)
+#define GPSR4_6                FM(TSN0_AVTP_CAPTURE)
+#define GPSR4_5                FM(TSN0_AVTP_MATCH)
+#define GPSR4_4                FM(TSN0_LINK)
+#define GPSR4_3                FM(TSN0_PHY_INT)
+#define GPSR4_2                FM(TSN0_AVTP_PPS1)
+#define GPSR4_1                FM(TSN0_MDC)
+#define GPSR4_0                FM(TSN0_MDIO)
+
+/* GPSR 5 */
+#define GPSR5_20       FM(AVB2_RX_CTL)
+#define GPSR5_19       FM(AVB2_TX_CTL)
+#define GPSR5_18       FM(AVB2_RXC)
+#define GPSR5_17       FM(AVB2_RD0)
+#define GPSR5_16       FM(AVB2_TXC)
+#define GPSR5_15       FM(AVB2_TD0)
+#define GPSR5_14       FM(AVB2_RD1)
+#define GPSR5_13       FM(AVB2_RD2)
+#define GPSR5_12       FM(AVB2_TD1)
+#define GPSR5_11       FM(AVB2_TD2)
+#define GPSR5_10       FM(AVB2_MDIO)
+#define GPSR5_9                FM(AVB2_RD3)
+#define GPSR5_8                FM(AVB2_TD3)
+#define GPSR5_7                FM(AVB2_TXCREFCLK)
+#define GPSR5_6                FM(AVB2_MDC)
+#define GPSR5_5                FM(AVB2_MAGIC)
+#define GPSR5_4                FM(AVB2_PHY_INT)
+#define GPSR5_3                FM(AVB2_LINK)
+#define GPSR5_2                FM(AVB2_AVTP_MATCH)
+#define GPSR5_1                FM(AVB2_AVTP_CAPTURE)
+#define GPSR5_0                FM(AVB2_AVTP_PPS)
+
+/* GPSR 6 */
+#define GPSR6_20       F_(AVB1_TXCREFCLK,      IP2SR6_19_16)
+#define GPSR6_19       F_(AVB1_RD3,            IP2SR6_15_12)
+#define GPSR6_18       F_(AVB1_TD3,            IP2SR6_11_8)
+#define GPSR6_17       F_(AVB1_RD2,            IP2SR6_7_4)
+#define GPSR6_16       F_(AVB1_TD2,            IP2SR6_3_0)
+#define GPSR6_15       F_(AVB1_RD0,            IP1SR6_31_28)
+#define GPSR6_14       F_(AVB1_RD1,            IP1SR6_27_24)
+#define GPSR6_13       F_(AVB1_TD0,            IP1SR6_23_20)
+#define GPSR6_12       F_(AVB1_TD1,            IP1SR6_19_16)
+#define GPSR6_11       F_(AVB1_AVTP_CAPTURE,   IP1SR6_15_12)
+#define GPSR6_10       F_(AVB1_AVTP_PPS,       IP1SR6_11_8)
+#define GPSR6_9                F_(AVB1_RX_CTL,         IP1SR6_7_4)
+#define GPSR6_8                F_(AVB1_RXC,            IP1SR6_3_0)
+#define GPSR6_7                F_(AVB1_TX_CTL,         IP0SR6_31_28)
+#define GPSR6_6                F_(AVB1_TXC,            IP0SR6_27_24)
+#define GPSR6_5                F_(AVB1_AVTP_MATCH,     IP0SR6_23_20)
+#define GPSR6_4                F_(AVB1_LINK,           IP0SR6_19_16)
+#define GPSR6_3                F_(AVB1_PHY_INT,        IP0SR6_15_12)
+#define GPSR6_2                F_(AVB1_MDC,            IP0SR6_11_8)
+#define GPSR6_1                F_(AVB1_MAGIC,          IP0SR6_7_4)
+#define GPSR6_0                F_(AVB1_MDIO,           IP0SR6_3_0)
+
+/* GPSR7 */
+#define GPSR7_20       F_(AVB0_RX_CTL,         IP2SR7_19_16)
+#define GPSR7_19       F_(AVB0_RXC,            IP2SR7_15_12)
+#define GPSR7_18       F_(AVB0_RD0,            IP2SR7_11_8)
+#define GPSR7_17       F_(AVB0_RD1,            IP2SR7_7_4)
+#define GPSR7_16       F_(AVB0_TX_CTL,         IP2SR7_3_0)
+#define GPSR7_15       F_(AVB0_TXC,            IP1SR7_31_28)
+#define GPSR7_14       F_(AVB0_MDIO,           IP1SR7_27_24)
+#define GPSR7_13       F_(AVB0_MDC,            IP1SR7_23_20)
+#define GPSR7_12       F_(AVB0_RD2,            IP1SR7_19_16)
+#define GPSR7_11       F_(AVB0_TD0,            IP1SR7_15_12)
+#define GPSR7_10       F_(AVB0_MAGIC,          IP1SR7_11_8)
+#define GPSR7_9                F_(AVB0_TXCREFCLK,      IP1SR7_7_4)
+#define GPSR7_8                F_(AVB0_RD3,            IP1SR7_3_0)
+#define GPSR7_7                F_(AVB0_TD1,            IP0SR7_31_28)
+#define GPSR7_6                F_(AVB0_TD2,            IP0SR7_27_24)
+#define GPSR7_5                F_(AVB0_PHY_INT,        IP0SR7_23_20)
+#define GPSR7_4                F_(AVB0_LINK,           IP0SR7_19_16)
+#define GPSR7_3                F_(AVB0_TD3,            IP0SR7_15_12)
+#define GPSR7_2                F_(AVB0_AVTP_MATCH,     IP0SR7_11_8)
+#define GPSR7_1                F_(AVB0_AVTP_CAPTURE,   IP0SR7_7_4)
+#define GPSR7_0                F_(AVB0_AVTP_PPS,       IP0SR7_3_0)
+
+/* GPSR8 */
+#define GPSR8_13       F_(GP8_13,              IP1SR8_23_20)
+#define GPSR8_12       F_(GP8_12,              IP1SR8_19_16)
+#define GPSR8_11       F_(SDA5,                IP1SR8_15_12)
+#define GPSR8_10       F_(SCL5,                IP1SR8_11_8)
+#define GPSR8_9                F_(SDA4,                IP1SR8_7_4)
+#define GPSR8_8                F_(SCL4,                IP1SR8_3_0)
+#define GPSR8_7                F_(SDA3,                IP0SR8_31_28)
+#define GPSR8_6                F_(SCL3,                IP0SR8_27_24)
+#define GPSR8_5                F_(SDA2,                IP0SR8_23_20)
+#define GPSR8_4                F_(SCL2,                IP0SR8_19_16)
+#define GPSR8_3                F_(SDA1,                IP0SR8_15_12)
+#define GPSR8_2                F_(SCL1,                IP0SR8_11_8)
+#define GPSR8_1                F_(SDA0,                IP0SR8_7_4)
+#define GPSR8_0                F_(SCL0,                IP0SR8_3_0)
+
+/* SR0 */
+/* IP0SR0 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP0SR0_3_0     F_(0, 0)                FM(ERROROUTC_B)         FM(TCLK2_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_7_4     F_(0, 0)                FM(MSIOF3_SS1)          F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_11_8    F_(0, 0)                FM(MSIOF3_SS2)          F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_15_12   FM(IRQ3)                FM(MSIOF3_SCK)          F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_19_16   FM(IRQ2)                FM(MSIOF3_TXD)          F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_23_20   FM(IRQ1)                FM(MSIOF3_RXD)          F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_27_24   FM(IRQ0)                FM(MSIOF3_SYNC)         F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_31_28   FM(MSIOF5_SS2)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP1SR0 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP1SR0_3_0     FM(MSIOF5_SS1)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_7_4     FM(MSIOF5_SYNC)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_11_8    FM(MSIOF5_TXD)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_15_12   FM(MSIOF5_SCK)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_19_16   FM(MSIOF5_RXD)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_23_20   FM(MSIOF2_SS2)          FM(TCLK1)               FM(IRQ2_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_27_24   FM(MSIOF2_SS1)          FM(HTX1)                FM(TX1)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_31_28   FM(MSIOF2_SYNC)         FM(HRX1)                FM(RX1)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP2SR0 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP2SR0_3_0     FM(MSIOF2_TXD)          FM(HCTS1_N)             FM(CTS1_N)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR0_7_4     FM(MSIOF2_SCK)          FM(HRTS1_N)             FM(RTS1_N)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR0_11_8    FM(MSIOF2_RXD)          FM(HSCK1)               FM(SCK1)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* SR1 */
+/* IP0SR1 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP0SR1_3_0     FM(MSIOF1_SS2)          FM(HTX3_A)              FM(TX3)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_7_4     FM(MSIOF1_SS1)          FM(HCTS3_N_A)           FM(RX3)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_11_8    FM(MSIOF1_SYNC)         FM(HRTS3_N_A)           FM(RTS3_N)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_15_12   FM(MSIOF1_SCK)          FM(HSCK3_A)             FM(CTS3_N)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_19_16   FM(MSIOF1_TXD)          FM(HRX3_A)              FM(SCK3)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_23_20   FM(MSIOF1_RXD)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_27_24   FM(MSIOF0_SS2)          FM(HTX1_X)              FM(TX1_X)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_31_28   FM(MSIOF0_SS1)          FM(HRX1_X)              FM(RX1_X)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP1SR1 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP1SR1_3_0     FM(MSIOF0_SYNC)         FM(HCTS1_N_X)           FM(CTS1_N_X)    FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_7_4     FM(MSIOF0_TXD)          FM(HRTS1_N_X)           FM(RTS1_N_X)    FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_11_8    FM(MSIOF0_SCK)          FM(HSCK1_X)             FM(SCK1_X)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_15_12   FM(MSIOF0_RXD)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_19_16   FM(HTX0)                FM(TX0)                 F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_23_20   FM(HCTS0_N)             FM(CTS0_N)              FM(PWM8_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_27_24   FM(HRTS0_N)             FM(RTS0_N)              FM(PWM9_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_31_28   FM(HSCK0)               FM(SCK0)                FM(PWM0_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP2SR1 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP2SR1_3_0     FM(HRX0)                FM(RX0)                 F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_7_4     FM(SCIF_CLK)            FM(IRQ4_A)              F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_11_8    FM(SSI_SCK)             FM(TCLK3)               F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_15_12   FM(SSI_WS)              FM(TCLK4)               F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_19_16   FM(SSI_SD)              FM(IRQ0_A)              F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_23_20   FM(AUDIO_CLKOUT)        FM(IRQ1_A)              F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_27_24   FM(AUDIO_CLKIN)         FM(PWM3_A)              F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_31_28   F_(0, 0)                FM(TCLK2)               FM(MSIOF4_SS1)  FM(IRQ3_B)      F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP3SR1 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP3SR1_3_0     FM(HRX3)                FM(SCK3_A)              FM(MSIOF4_SS2)  F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_7_4     FM(HSCK3)               FM(CTS3_N_A)            FM(MSIOF4_SCK)  FM(TPU0TO0_A)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_11_8    FM(HRTS3_N)             FM(RTS3_N_A)            FM(MSIOF4_TXD)  FM(TPU0TO1_A)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_15_12   FM(HCTS3_N)             FM(RX3_A)               FM(MSIOF4_RXD)  F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_19_16   FM(HTX3)                FM(TX3_A)               FM(MSIOF4_SYNC) F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* SR2 */
+/* IP0SR2 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP0SR2_3_0     FM(FXR_TXDA)            FM(CANFD1_TX)           FM(TPU0TO2_A)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_7_4     FM(FXR_TXENA_N)         FM(CANFD1_RX)           FM(TPU0TO3_A)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_11_8    FM(RXDA_EXTFXR)         FM(CANFD5_TX)           FM(IRQ5)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_15_12   FM(CLK_EXTFXR)          FM(CANFD5_RX)           FM(IRQ4_B)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_19_16   FM(RXDB_EXTFXR)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_23_20   FM(FXR_TXENB_N)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_27_24   FM(FXR_TXDB)            F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_31_28   FM(TPU0TO1)             FM(CANFD6_TX)           F_(0, 0)        FM(TCLK2_B)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP1SR2 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP1SR2_3_0     FM(TPU0TO0)             FM(CANFD6_RX)           F_(0, 0)        FM(TCLK1_A)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_7_4     FM(CAN_CLK)             FM(FXR_TXENA_N_X)       F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_11_8    FM(CANFD0_TX)           FM(FXR_TXENB_N_X)       F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_15_12   FM(CANFD0_RX)           FM(STPWT_EXTFXR)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_19_16   FM(CANFD2_TX)           FM(TPU0TO2)             F_(0, 0)        FM(TCLK3_A)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_23_20   FM(CANFD2_RX)           FM(TPU0TO3)             FM(PWM1_B)      FM(TCLK4_A)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_27_24   FM(CANFD3_TX)           F_(0, 0)                FM(PWM2_B)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_31_28   FM(CANFD3_RX)           F_(0, 0)                FM(PWM3_B)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP2SR2 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP2SR2_3_0     FM(CANFD4_TX)           F_(0, 0)                FM(PWM4)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR2_7_4     FM(CANFD4_RX)           F_(0, 0)                FM(PWM5)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR2_11_8    FM(CANFD7_TX)           F_(0, 0)                FM(PWM6)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR2_15_12   FM(CANFD7_RX)           F_(0, 0)                FM(PWM7)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* SR3 */
+/* IP0SR3 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP0SR3_3_0     FM(MMC_SD_D1)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_7_4     FM(MMC_SD_D0)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_11_8    FM(MMC_SD_D2)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_15_12   FM(MMC_SD_CLK)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_19_16   FM(MMC_DS)              F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_23_20   FM(MMC_SD_D3)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_27_24   FM(MMC_D5)              F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR3_31_28   FM(MMC_D4)              F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP1SR3 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP1SR3_3_0     FM(MMC_D7)              F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_7_4     FM(MMC_D6)              F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_11_8    FM(MMC_SD_CMD)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_15_12   FM(SD_CD)               F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_19_16   FM(SD_WP)               F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_23_20   FM(IPC_CLKIN)           FM(IPC_CLKEN_IN)        FM(PWM1_A)      FM(TCLK3_X)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_27_24   FM(IPC_CLKOUT)          FM(IPC_CLKEN_OUT)       FM(ERROROUTC_A) FM(TCLK4_X)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_31_28   FM(QSPI0_SSL)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP2SR3 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP2SR3_3_0     FM(QSPI0_IO3)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_7_4     FM(QSPI0_IO2)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_11_8    FM(QSPI0_MISO_IO1)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_15_12   FM(QSPI0_MOSI_IO0)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_19_16   FM(QSPI0_SPCLK)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_23_20   FM(QSPI1_MOSI_IO0)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_27_24   FM(QSPI1_SPCLK)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR3_31_28   FM(QSPI1_MISO_IO1)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP3SR3 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP3SR3_3_0     FM(QSPI1_IO2)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR3_7_4     FM(QSPI1_SSL)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR3_11_8    FM(QSPI1_IO3)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR3_15_12   FM(RPC_RESET_N)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR3_19_16   FM(RPC_WP_N)            F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR3_23_20   FM(RPC_INT_N)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* SR6 */
+/* IP0SR6 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP0SR6_3_0     FM(AVB1_MDIO)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_7_4     FM(AVB1_MAGIC)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_11_8    FM(AVB1_MDC)            F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_15_12   FM(AVB1_PHY_INT)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_19_16   FM(AVB1_LINK)           FM(AVB1_MII_TX_ER)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_23_20   FM(AVB1_AVTP_MATCH)     FM(AVB1_MII_RX_ER)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_27_24   FM(AVB1_TXC)            FM(AVB1_MII_TXC)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR6_31_28   FM(AVB1_TX_CTL)         FM(AVB1_MII_TX_EN)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP1SR6 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP1SR6_3_0     FM(AVB1_RXC)            FM(AVB1_MII_RXC)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_7_4     FM(AVB1_RX_CTL)         FM(AVB1_MII_RX_DV)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_11_8    FM(AVB1_AVTP_PPS)       FM(AVB1_MII_COL)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_15_12   FM(AVB1_AVTP_CAPTURE)   FM(AVB1_MII_CRS)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_19_16   FM(AVB1_TD1)            FM(AVB1_MII_TD1)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_23_20   FM(AVB1_TD0)            FM(AVB1_MII_TD0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_27_24   FM(AVB1_RD1)            FM(AVB1_MII_RD1)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR6_31_28   FM(AVB1_RD0)            FM(AVB1_MII_RD0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP2SR6 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP2SR6_3_0     FM(AVB1_TD2)            FM(AVB1_MII_TD2)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR6_7_4     FM(AVB1_RD2)            FM(AVB1_MII_RD2)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR6_11_8    FM(AVB1_TD3)            FM(AVB1_MII_TD3)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR6_15_12   FM(AVB1_RD3)            FM(AVB1_MII_RD3)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR6_19_16   FM(AVB1_TXCREFCLK)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* SR7 */
+/* IP0SR7 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP0SR7_3_0     FM(AVB0_AVTP_PPS)       FM(AVB0_MII_COL)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_7_4     FM(AVB0_AVTP_CAPTURE)   FM(AVB0_MII_CRS)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_11_8    FM(AVB0_AVTP_MATCH)     FM(AVB0_MII_RX_ER)      FM(CC5_OSCOUT)  F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_15_12   FM(AVB0_TD3)            FM(AVB0_MII_TD3)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_19_16   FM(AVB0_LINK)           FM(AVB0_MII_TX_ER)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_23_20   FM(AVB0_PHY_INT)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_27_24   FM(AVB0_TD2)            FM(AVB0_MII_TD2)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR7_31_28   FM(AVB0_TD1)            FM(AVB0_MII_TD1)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP1SR7 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP1SR7_3_0     FM(AVB0_RD3)            FM(AVB0_MII_RD3)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_7_4     FM(AVB0_TXCREFCLK)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_11_8    FM(AVB0_MAGIC)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_15_12   FM(AVB0_TD0)            FM(AVB0_MII_TD0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_19_16   FM(AVB0_RD2)            FM(AVB0_MII_RD2)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_23_20   FM(AVB0_MDC)            F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_27_24   FM(AVB0_MDIO)           F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR7_31_28   FM(AVB0_TXC)            FM(AVB0_MII_TXC)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP2SR7 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP2SR7_3_0     FM(AVB0_TX_CTL)         FM(AVB0_MII_TX_EN)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR7_7_4     FM(AVB0_RD1)            FM(AVB0_MII_RD1)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR7_11_8    FM(AVB0_RD0)            FM(AVB0_MII_RD0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR7_15_12   FM(AVB0_RXC)            FM(AVB0_MII_RXC)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR7_19_16   FM(AVB0_RX_CTL)         FM(AVB0_MII_RX_DV)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* SR8 */
+/* IP0SR8 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP0SR8_3_0     FM(SCL0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_7_4     FM(SDA0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_11_8    FM(SCL1)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_15_12   FM(SDA1)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_19_16   FM(SCL2)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_23_20   FM(SDA2)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_27_24   FM(SCL3)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR8_31_28   FM(SDA3)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IP1SR8 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
+#define IP1SR8_3_0     FM(SCL4)                FM(HRX2)                FM(SCK4)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR8_7_4     FM(SDA4)                FM(HTX2)                FM(CTS4_N)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR8_11_8    FM(SCL5)                FM(HRTS2_N)             FM(RTS4_N)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR8_15_12   FM(SDA5)                FM(SCIF_CLK2)           F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR8_19_16   F_(0, 0)                FM(HCTS2_N)             FM(TX4)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR8_23_20   F_(0, 0)                FM(HSCK2)               FM(RX4)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+#define PINMUX_GPSR    \
+                                               GPSR3_29                                                                                        \
+               GPSR1_28                        GPSR3_28                                                                                        \
+               GPSR1_27                        GPSR3_27                                                                                        \
+               GPSR1_26                        GPSR3_26                                                                                        \
+               GPSR1_25                        GPSR3_25                                                                                        \
+               GPSR1_24                        GPSR3_24        GPSR4_24                                                                        \
+               GPSR1_23                        GPSR3_23        GPSR4_23                                                                        \
+               GPSR1_22                        GPSR3_22        GPSR4_22                                                                        \
+               GPSR1_21                        GPSR3_21        GPSR4_21                                                                        \
+               GPSR1_20                        GPSR3_20        GPSR4_20        GPSR5_20        GPSR6_20        GPSR7_20                        \
+               GPSR1_19        GPSR2_19        GPSR3_19        GPSR4_19        GPSR5_19        GPSR6_19        GPSR7_19                        \
+GPSR0_18       GPSR1_18        GPSR2_18        GPSR3_18        GPSR4_18        GPSR5_18        GPSR6_18        GPSR7_18                        \
+GPSR0_17       GPSR1_17        GPSR2_17        GPSR3_17        GPSR4_17        GPSR5_17        GPSR6_17        GPSR7_17                        \
+GPSR0_16       GPSR1_16        GPSR2_16        GPSR3_16        GPSR4_16        GPSR5_16        GPSR6_16        GPSR7_16                        \
+GPSR0_15       GPSR1_15        GPSR2_15        GPSR3_15        GPSR4_15        GPSR5_15        GPSR6_15        GPSR7_15                        \
+GPSR0_14       GPSR1_14        GPSR2_14        GPSR3_14        GPSR4_14        GPSR5_14        GPSR6_14        GPSR7_14                        \
+GPSR0_13       GPSR1_13        GPSR2_13        GPSR3_13        GPSR4_13        GPSR5_13        GPSR6_13        GPSR7_13        GPSR8_13        \
+GPSR0_12       GPSR1_12        GPSR2_12        GPSR3_12        GPSR4_12        GPSR5_12        GPSR6_12        GPSR7_12        GPSR8_12        \
+GPSR0_11       GPSR1_11        GPSR2_11        GPSR3_11        GPSR4_11        GPSR5_11        GPSR6_11        GPSR7_11        GPSR8_11        \
+GPSR0_10       GPSR1_10        GPSR2_10        GPSR3_10        GPSR4_10        GPSR5_10        GPSR6_10        GPSR7_10        GPSR8_10        \
+GPSR0_9                GPSR1_9         GPSR2_9         GPSR3_9         GPSR4_9         GPSR5_9         GPSR6_9         GPSR7_9         GPSR8_9         \
+GPSR0_8                GPSR1_8         GPSR2_8         GPSR3_8         GPSR4_8         GPSR5_8         GPSR6_8         GPSR7_8         GPSR8_8         \
+GPSR0_7                GPSR1_7         GPSR2_7         GPSR3_7         GPSR4_7         GPSR5_7         GPSR6_7         GPSR7_7         GPSR8_7         \
+GPSR0_6                GPSR1_6         GPSR2_6         GPSR3_6         GPSR4_6         GPSR5_6         GPSR6_6         GPSR7_6         GPSR8_6         \
+GPSR0_5                GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5         GPSR6_5         GPSR7_5         GPSR8_5         \
+GPSR0_4                GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4         GPSR6_4         GPSR7_4         GPSR8_4         \
+GPSR0_3                GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3         GPSR6_3         GPSR7_3         GPSR8_3         \
+GPSR0_2                GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2         GPSR6_2         GPSR7_2         GPSR8_2         \
+GPSR0_1                GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1         GPSR6_1         GPSR7_1         GPSR8_1         \
+GPSR0_0                GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0         GPSR7_0         GPSR8_0
+
+#define PINMUX_IPSR    \
+\
+FM(IP0SR0_3_0)         IP0SR0_3_0      FM(IP1SR0_3_0)          IP1SR0_3_0      FM(IP2SR0_3_0)          IP2SR0_3_0      \
+FM(IP0SR0_7_4)         IP0SR0_7_4      FM(IP1SR0_7_4)          IP1SR0_7_4      FM(IP2SR0_7_4)          IP2SR0_7_4      \
+FM(IP0SR0_11_8)                IP0SR0_11_8     FM(IP1SR0_11_8)         IP1SR0_11_8     FM(IP2SR0_11_8)         IP2SR0_11_8     \
+FM(IP0SR0_15_12)       IP0SR0_15_12    FM(IP1SR0_15_12)        IP1SR0_15_12    \
+FM(IP0SR0_19_16)       IP0SR0_19_16    FM(IP1SR0_19_16)        IP1SR0_19_16    \
+FM(IP0SR0_23_20)       IP0SR0_23_20    FM(IP1SR0_23_20)        IP1SR0_23_20    \
+FM(IP0SR0_27_24)       IP0SR0_27_24    FM(IP1SR0_27_24)        IP1SR0_27_24    \
+FM(IP0SR0_31_28)       IP0SR0_31_28    FM(IP1SR0_31_28)        IP1SR0_31_28    \
+\
+FM(IP0SR1_3_0)         IP0SR1_3_0      FM(IP1SR1_3_0)          IP1SR1_3_0      FM(IP2SR1_3_0)          IP2SR1_3_0      FM(IP3SR1_3_0)          IP3SR1_3_0      \
+FM(IP0SR1_7_4)         IP0SR1_7_4      FM(IP1SR1_7_4)          IP1SR1_7_4      FM(IP2SR1_7_4)          IP2SR1_7_4      FM(IP3SR1_7_4)          IP3SR1_7_4      \
+FM(IP0SR1_11_8)                IP0SR1_11_8     FM(IP1SR1_11_8)         IP1SR1_11_8     FM(IP2SR1_11_8)         IP2SR1_11_8     FM(IP3SR1_11_8)         IP3SR1_11_8     \
+FM(IP0SR1_15_12)       IP0SR1_15_12    FM(IP1SR1_15_12)        IP1SR1_15_12    FM(IP2SR1_15_12)        IP2SR1_15_12    FM(IP3SR1_15_12)        IP3SR1_15_12    \
+FM(IP0SR1_19_16)       IP0SR1_19_16    FM(IP1SR1_19_16)        IP1SR1_19_16    FM(IP2SR1_19_16)        IP2SR1_19_16    FM(IP3SR1_19_16)        IP3SR1_19_16    \
+FM(IP0SR1_23_20)       IP0SR1_23_20    FM(IP1SR1_23_20)        IP1SR1_23_20    FM(IP2SR1_23_20)        IP2SR1_23_20    \
+FM(IP0SR1_27_24)       IP0SR1_27_24    FM(IP1SR1_27_24)        IP1SR1_27_24    FM(IP2SR1_27_24)        IP2SR1_27_24    \
+FM(IP0SR1_31_28)       IP0SR1_31_28    FM(IP1SR1_31_28)        IP1SR1_31_28    FM(IP2SR1_31_28)        IP2SR1_31_28    \
+\
+FM(IP0SR2_3_0)         IP0SR2_3_0      FM(IP1SR2_3_0)          IP1SR2_3_0      FM(IP2SR2_3_0)          IP2SR2_3_0      \
+FM(IP0SR2_7_4)         IP0SR2_7_4      FM(IP1SR2_7_4)          IP1SR2_7_4      FM(IP2SR2_7_4)          IP2SR2_7_4      \
+FM(IP0SR2_11_8)                IP0SR2_11_8     FM(IP1SR2_11_8)         IP1SR2_11_8     FM(IP2SR2_11_8)         IP2SR2_11_8     \
+FM(IP0SR2_15_12)       IP0SR2_15_12    FM(IP1SR2_15_12)        IP1SR2_15_12    FM(IP2SR2_15_12)        IP2SR2_15_12    \
+FM(IP0SR2_19_16)       IP0SR2_19_16    FM(IP1SR2_19_16)        IP1SR2_19_16    \
+FM(IP0SR2_23_20)       IP0SR2_23_20    FM(IP1SR2_23_20)        IP1SR2_23_20    \
+FM(IP0SR2_27_24)       IP0SR2_27_24    FM(IP1SR2_27_24)        IP1SR2_27_24    \
+FM(IP0SR2_31_28)       IP0SR2_31_28    FM(IP1SR2_31_28)        IP1SR2_31_28    \
+\
+FM(IP0SR3_3_0)         IP0SR3_3_0      FM(IP1SR3_3_0)          IP1SR3_3_0      FM(IP2SR3_3_0)          IP2SR3_3_0      FM(IP3SR3_3_0)          IP3SR3_3_0      \
+FM(IP0SR3_7_4)         IP0SR3_7_4      FM(IP1SR3_7_4)          IP1SR3_7_4      FM(IP2SR3_7_4)          IP2SR3_7_4      FM(IP3SR3_7_4)          IP3SR3_7_4      \
+FM(IP0SR3_11_8)                IP0SR3_11_8     FM(IP1SR3_11_8)         IP1SR3_11_8     FM(IP2SR3_11_8)         IP2SR3_11_8     FM(IP3SR3_11_8)         IP3SR3_11_8     \
+FM(IP0SR3_15_12)       IP0SR3_15_12    FM(IP1SR3_15_12)        IP1SR3_15_12    FM(IP2SR3_15_12)        IP2SR3_15_12    FM(IP3SR3_15_12)        IP3SR3_15_12    \
+FM(IP0SR3_19_16)       IP0SR3_19_16    FM(IP1SR3_19_16)        IP1SR3_19_16    FM(IP2SR3_19_16)        IP2SR3_19_16    FM(IP3SR3_19_16)        IP3SR3_19_16    \
+FM(IP0SR3_23_20)       IP0SR3_23_20    FM(IP1SR3_23_20)        IP1SR3_23_20    FM(IP2SR3_23_20)        IP2SR3_23_20    FM(IP3SR3_23_20)        IP3SR3_23_20    \
+FM(IP0SR3_27_24)       IP0SR3_27_24    FM(IP1SR3_27_24)        IP1SR3_27_24    FM(IP2SR3_27_24)        IP2SR3_27_24                                            \
+FM(IP0SR3_31_28)       IP0SR3_31_28    FM(IP1SR3_31_28)        IP1SR3_31_28    FM(IP2SR3_31_28)        IP2SR3_31_28                                            \
+\
+FM(IP0SR6_3_0)         IP0SR6_3_0      FM(IP1SR6_3_0)          IP1SR6_3_0      FM(IP2SR6_3_0)          IP2SR6_3_0      \
+FM(IP0SR6_7_4)         IP0SR6_7_4      FM(IP1SR6_7_4)          IP1SR6_7_4      FM(IP2SR6_7_4)          IP2SR6_7_4      \
+FM(IP0SR6_11_8)                IP0SR6_11_8     FM(IP1SR6_11_8)         IP1SR6_11_8     FM(IP2SR6_11_8)         IP2SR6_11_8     \
+FM(IP0SR6_15_12)       IP0SR6_15_12    FM(IP1SR6_15_12)        IP1SR6_15_12    FM(IP2SR6_15_12)        IP2SR6_15_12    \
+FM(IP0SR6_19_16)       IP0SR6_19_16    FM(IP1SR6_19_16)        IP1SR6_19_16    FM(IP2SR6_19_16)        IP2SR6_19_16    \
+FM(IP0SR6_23_20)       IP0SR6_23_20    FM(IP1SR6_23_20)        IP1SR6_23_20    \
+FM(IP0SR6_27_24)       IP0SR6_27_24    FM(IP1SR6_27_24)        IP1SR6_27_24    \
+FM(IP0SR6_31_28)       IP0SR6_31_28    FM(IP1SR6_31_28)        IP1SR6_31_28    \
+\
+FM(IP0SR7_3_0)         IP0SR7_3_0      FM(IP1SR7_3_0)          IP1SR7_3_0      FM(IP2SR7_3_0)          IP2SR7_3_0      \
+FM(IP0SR7_7_4)         IP0SR7_7_4      FM(IP1SR7_7_4)          IP1SR7_7_4      FM(IP2SR7_7_4)          IP2SR7_7_4      \
+FM(IP0SR7_11_8)                IP0SR7_11_8     FM(IP1SR7_11_8)         IP1SR7_11_8     FM(IP2SR7_11_8)         IP2SR7_11_8     \
+FM(IP0SR7_15_12)       IP0SR7_15_12    FM(IP1SR7_15_12)        IP1SR7_15_12    FM(IP2SR7_15_12)        IP2SR7_15_12    \
+FM(IP0SR7_19_16)       IP0SR7_19_16    FM(IP1SR7_19_16)        IP1SR7_19_16    FM(IP2SR7_19_16)        IP2SR7_19_16    \
+FM(IP0SR7_23_20)       IP0SR7_23_20    FM(IP1SR7_23_20)        IP1SR7_23_20    \
+FM(IP0SR7_27_24)       IP0SR7_27_24    FM(IP1SR7_27_24)        IP1SR7_27_24    \
+FM(IP0SR7_31_28)       IP0SR7_31_28    FM(IP1SR7_31_28)        IP1SR7_31_28    \
+\
+FM(IP0SR8_3_0)         IP0SR8_3_0      FM(IP1SR8_3_0)          IP1SR8_3_0      \
+FM(IP0SR8_7_4)         IP0SR8_7_4      FM(IP1SR8_7_4)          IP1SR8_7_4      \
+FM(IP0SR8_11_8)                IP0SR8_11_8     FM(IP1SR8_11_8)         IP1SR8_11_8     \
+FM(IP0SR8_15_12)       IP0SR8_15_12    FM(IP1SR8_15_12)        IP1SR8_15_12    \
+FM(IP0SR8_19_16)       IP0SR8_19_16    FM(IP1SR8_19_16)        IP1SR8_19_16    \
+FM(IP0SR8_23_20)       IP0SR8_23_20    FM(IP1SR8_23_20)        IP1SR8_23_20    \
+FM(IP0SR8_27_24)       IP0SR8_27_24    \
+FM(IP0SR8_31_28)       IP0SR8_31_28
+
+/* MOD_SEL4 */                 /* 0 */                         /* 1 */
+#define MOD_SEL4_19            FM(SEL_TSN0_TD2_0)              FM(SEL_TSN0_TD2_1)
+#define MOD_SEL4_18            FM(SEL_TSN0_TD3_0)              FM(SEL_TSN0_TD3_1)
+#define MOD_SEL4_15            FM(SEL_TSN0_TD0_0)              FM(SEL_TSN0_TD0_1)
+#define MOD_SEL4_14            FM(SEL_TSN0_TD1_0)              FM(SEL_TSN0_TD1_1)
+#define MOD_SEL4_12            FM(SEL_TSN0_TXC_0)              FM(SEL_TSN0_TXC_1)
+#define MOD_SEL4_9             FM(SEL_TSN0_TX_CTL_0)           FM(SEL_TSN0_TX_CTL_1)
+#define MOD_SEL4_8             FM(SEL_TSN0_AVTP_PPS0_0)        FM(SEL_TSN0_AVTP_PPS0_1)
+#define MOD_SEL4_5             FM(SEL_TSN0_AVTP_MATCH_0)       FM(SEL_TSN0_AVTP_MATCH_1)
+#define MOD_SEL4_2             FM(SEL_TSN0_AVTP_PPS1_0)        FM(SEL_TSN0_AVTP_PPS1_1)
+#define MOD_SEL4_1             FM(SEL_TSN0_MDC_0)              FM(SEL_TSN0_MDC_1)
+
+/* MOD_SEL5 */                 /* 0 */                         /* 1 */
+#define MOD_SEL5_19            FM(SEL_AVB2_TX_CTL_0)           FM(SEL_AVB2_TX_CTL_1)
+#define MOD_SEL5_16            FM(SEL_AVB2_TXC_0)              FM(SEL_AVB2_TXC_1)
+#define MOD_SEL5_15            FM(SEL_AVB2_TD0_0)              FM(SEL_AVB2_TD0_1)
+#define MOD_SEL5_12            FM(SEL_AVB2_TD1_0)              FM(SEL_AVB2_TD1_1)
+#define MOD_SEL5_11            FM(SEL_AVB2_TD2_0)              FM(SEL_AVB2_TD2_1)
+#define MOD_SEL5_8             FM(SEL_AVB2_TD3_0)              FM(SEL_AVB2_TD3_1)
+#define MOD_SEL5_6             FM(SEL_AVB2_MDC_0)              FM(SEL_AVB2_MDC_1)
+#define MOD_SEL5_5             FM(SEL_AVB2_MAGIC_0)            FM(SEL_AVB2_MAGIC_1)
+#define MOD_SEL5_2             FM(SEL_AVB2_AVTP_MATCH_0)       FM(SEL_AVB2_AVTP_MATCH_1)
+#define MOD_SEL5_0             FM(SEL_AVB2_AVTP_PPS_0)         FM(SEL_AVB2_AVTP_PPS_1)
+
+/* MOD_SEL6 */                 /* 0 */                         /* 1 */
+#define MOD_SEL6_18            FM(SEL_AVB1_TD3_0)              FM(SEL_AVB1_TD3_1)
+#define MOD_SEL6_16            FM(SEL_AVB1_TD2_0)              FM(SEL_AVB1_TD2_1)
+#define MOD_SEL6_13            FM(SEL_AVB1_TD0_0)              FM(SEL_AVB1_TD0_1)
+#define MOD_SEL6_12            FM(SEL_AVB1_TD1_0)              FM(SEL_AVB1_TD1_1)
+#define MOD_SEL6_10            FM(SEL_AVB1_AVTP_PPS_0)         FM(SEL_AVB1_AVTP_PPS_1)
+#define MOD_SEL6_7             FM(SEL_AVB1_TX_CTL_0)           FM(SEL_AVB1_TX_CTL_1)
+#define MOD_SEL6_6             FM(SEL_AVB1_TXC_0)              FM(SEL_AVB1_TXC_1)
+#define MOD_SEL6_5             FM(SEL_AVB1_AVTP_MATCH_0)       FM(SEL_AVB1_AVTP_MATCH_1)
+#define MOD_SEL6_2             FM(SEL_AVB1_MDC_0)              FM(SEL_AVB1_MDC_1)
+#define MOD_SEL6_1             FM(SEL_AVB1_MAGIC_0)            FM(SEL_AVB1_MAGIC_1)
+
+/* MOD_SEL7 */                 /* 0 */                         /* 1 */
+#define MOD_SEL7_16            FM(SEL_AVB0_TX_CTL_0)           FM(SEL_AVB0_TX_CTL_1)
+#define MOD_SEL7_15            FM(SEL_AVB0_TXC_0)              FM(SEL_AVB0_TXC_1)
+#define MOD_SEL7_13            FM(SEL_AVB0_MDC_0)              FM(SEL_AVB0_MDC_1)
+#define MOD_SEL7_11            FM(SEL_AVB0_TD0_0)              FM(SEL_AVB0_TD0_1)
+#define MOD_SEL7_10            FM(SEL_AVB0_MAGIC_0)            FM(SEL_AVB0_MAGIC_1)
+#define MOD_SEL7_7             FM(SEL_AVB0_TD1_0)              FM(SEL_AVB0_TD1_1)
+#define MOD_SEL7_6             FM(SEL_AVB0_TD2_0)              FM(SEL_AVB0_TD2_1)
+#define MOD_SEL7_3             FM(SEL_AVB0_TD3_0)              FM(SEL_AVB0_TD3_1)
+#define MOD_SEL7_2             FM(SEL_AVB0_AVTP_MATCH_0)       FM(SEL_AVB0_AVTP_MATCH_1)
+#define MOD_SEL7_0             FM(SEL_AVB0_AVTP_PPS_0)         FM(SEL_AVB0_AVTP_PPS_1)
+
+/* MOD_SEL8 */                 /* 0 */                         /* 1 */
+#define MOD_SEL8_11            FM(SEL_SDA5_0)                  FM(SEL_SDA5_1)
+#define MOD_SEL8_10            FM(SEL_SCL5_0)                  FM(SEL_SCL5_1)
+#define MOD_SEL8_9             FM(SEL_SDA4_0)                  FM(SEL_SDA4_1)
+#define MOD_SEL8_8             FM(SEL_SCL4_0)                  FM(SEL_SCL4_1)
+#define MOD_SEL8_7             FM(SEL_SDA3_0)                  FM(SEL_SDA3_1)
+#define MOD_SEL8_6             FM(SEL_SCL3_0)                  FM(SEL_SCL3_1)
+#define MOD_SEL8_5             FM(SEL_SDA2_0)                  FM(SEL_SDA2_1)
+#define MOD_SEL8_4             FM(SEL_SCL2_0)                  FM(SEL_SCL2_1)
+#define MOD_SEL8_3             FM(SEL_SDA1_0)                  FM(SEL_SDA1_1)
+#define MOD_SEL8_2             FM(SEL_SCL1_0)                  FM(SEL_SCL1_1)
+#define MOD_SEL8_1             FM(SEL_SDA0_0)                  FM(SEL_SDA0_1)
+#define MOD_SEL8_0             FM(SEL_SCL0_0)                  FM(SEL_SCL0_1)
+
+#define PINMUX_MOD_SELS \
+\
+MOD_SEL4_19            MOD_SEL5_19                                                                             \
+MOD_SEL4_18                                    MOD_SEL6_18                                                     \
+                                                                                                               \
+                       MOD_SEL5_16             MOD_SEL6_16             MOD_SEL7_16                             \
+MOD_SEL4_15            MOD_SEL5_15                                     MOD_SEL7_15                             \
+MOD_SEL4_14                                                                                                    \
+                                               MOD_SEL6_13             MOD_SEL7_13                             \
+MOD_SEL4_12            MOD_SEL5_12             MOD_SEL6_12                                                     \
+                       MOD_SEL5_11                                     MOD_SEL7_11             MOD_SEL8_11     \
+                                               MOD_SEL6_10             MOD_SEL7_10             MOD_SEL8_10     \
+MOD_SEL4_9                                                                                     MOD_SEL8_9      \
+MOD_SEL4_8             MOD_SEL5_8                                                              MOD_SEL8_8      \
+                                               MOD_SEL6_7              MOD_SEL7_7              MOD_SEL8_7      \
+                       MOD_SEL5_6              MOD_SEL6_6              MOD_SEL7_6              MOD_SEL8_6      \
+MOD_SEL4_5             MOD_SEL5_5              MOD_SEL6_5                                      MOD_SEL8_5      \
+                                                                                               MOD_SEL8_4      \
+                                                                       MOD_SEL7_3              MOD_SEL8_3      \
+MOD_SEL4_2             MOD_SEL5_2              MOD_SEL6_2              MOD_SEL7_2              MOD_SEL8_2      \
+MOD_SEL4_1                                     MOD_SEL6_1                                      MOD_SEL8_1      \
+                       MOD_SEL5_0                                      MOD_SEL7_0              MOD_SEL8_0
+
+enum {
+       PINMUX_RESERVED = 0,
+
+       PINMUX_DATA_BEGIN,
+       GP_ALL(DATA),
+       PINMUX_DATA_END,
+
+#define F_(x, y)
+#define FM(x)   FN_##x,
+       PINMUX_FUNCTION_BEGIN,
+       GP_ALL(FN),
+       PINMUX_GPSR
+       PINMUX_IPSR
+       PINMUX_MOD_SELS
+       PINMUX_FUNCTION_END,
+#undef F_
+#undef FM
+
+#define F_(x, y)
+#define FM(x)  x##_MARK,
+       PINMUX_MARK_BEGIN,
+       PINMUX_GPSR
+       PINMUX_IPSR
+       PINMUX_MOD_SELS
+       PINMUX_MARK_END,
+#undef F_
+#undef FM
+};
+
+static const u16 pinmux_data[] = {
+       PINMUX_DATA_GP_ALL(),
+
+       PINMUX_SINGLE(AVS1),
+       PINMUX_SINGLE(AVS0),
+       PINMUX_SINGLE(PCIE1_CLKREQ_N),
+       PINMUX_SINGLE(PCIE0_CLKREQ_N),
+
+       /* TSN0 without MODSEL4 */
+       PINMUX_SINGLE(TSN0_TXCREFCLK),
+       PINMUX_SINGLE(TSN0_RD2),
+       PINMUX_SINGLE(TSN0_RD3),
+       PINMUX_SINGLE(TSN0_RD1),
+       PINMUX_SINGLE(TSN0_RXC),
+       PINMUX_SINGLE(TSN0_RD0),
+       PINMUX_SINGLE(TSN0_RX_CTL),
+       PINMUX_SINGLE(TSN0_AVTP_CAPTURE),
+       PINMUX_SINGLE(TSN0_LINK),
+       PINMUX_SINGLE(TSN0_PHY_INT),
+       PINMUX_SINGLE(TSN0_MDIO),
+       /* TSN0 with MODSEL4 */
+       PINMUX_IPSR_NOGM(0, TSN0_TD2,           SEL_TSN0_TD2_1),
+       PINMUX_IPSR_NOGM(0, TSN0_TD3,           SEL_TSN0_TD3_1),
+       PINMUX_IPSR_NOGM(0, TSN0_TD0,           SEL_TSN0_TD0_1),
+       PINMUX_IPSR_NOGM(0, TSN0_TD1,           SEL_TSN0_TD1_1),
+       PINMUX_IPSR_NOGM(0, TSN0_TXC,           SEL_TSN0_TXC_1),
+       PINMUX_IPSR_NOGM(0, TSN0_TX_CTL,        SEL_TSN0_TX_CTL_1),
+       PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS0,     SEL_TSN0_AVTP_PPS0_1),
+       PINMUX_IPSR_NOGM(0, TSN0_AVTP_MATCH,    SEL_TSN0_AVTP_MATCH_1),
+       PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS1,     SEL_TSN0_AVTP_PPS1_1),
+       PINMUX_IPSR_NOGM(0, TSN0_MDC,           SEL_TSN0_MDC_1),
+
+       /* TSN0 without MODSEL5 */
+       PINMUX_SINGLE(AVB2_RX_CTL),
+       PINMUX_SINGLE(AVB2_RXC),
+       PINMUX_SINGLE(AVB2_RD0),
+       PINMUX_SINGLE(AVB2_RD1),
+       PINMUX_SINGLE(AVB2_RD2),
+       PINMUX_SINGLE(AVB2_MDIO),
+       PINMUX_SINGLE(AVB2_RD3),
+       PINMUX_SINGLE(AVB2_TXCREFCLK),
+       PINMUX_SINGLE(AVB2_PHY_INT),
+       PINMUX_SINGLE(AVB2_LINK),
+       PINMUX_SINGLE(AVB2_AVTP_CAPTURE),
+       /* TSN0 with MODSEL5 */
+       PINMUX_IPSR_NOGM(0, AVB2_TX_CTL,        SEL_AVB2_TX_CTL_1),
+       PINMUX_IPSR_NOGM(0, AVB2_TXC,           SEL_AVB2_TXC_1),
+       PINMUX_IPSR_NOGM(0, AVB2_TD0,           SEL_AVB2_TD0_1),
+       PINMUX_IPSR_NOGM(0, AVB2_TD1,           SEL_AVB2_TD1_1),
+       PINMUX_IPSR_NOGM(0, AVB2_TD2,           SEL_AVB2_TD2_1),
+       PINMUX_IPSR_NOGM(0, AVB2_TD3,           SEL_AVB2_TD3_1),
+       PINMUX_IPSR_NOGM(0, AVB2_MDC,           SEL_AVB2_MDC_1),
+       PINMUX_IPSR_NOGM(0, AVB2_MAGIC,         SEL_AVB2_MAGIC_1),
+       PINMUX_IPSR_NOGM(0, AVB2_AVTP_MATCH,    SEL_AVB2_AVTP_MATCH_1),
+       PINMUX_IPSR_NOGM(0, AVB2_AVTP_PPS,      SEL_AVB2_AVTP_PPS_1),
+
+       /* IP0SR0 */
+       PINMUX_IPSR_GPSR(IP0SR0_3_0,    ERROROUTC_B),
+       PINMUX_IPSR_GPSR(IP0SR0_3_0,    TCLK2_A),
+
+       PINMUX_IPSR_GPSR(IP0SR0_7_4,    MSIOF3_SS1),
+
+       PINMUX_IPSR_GPSR(IP0SR0_11_8,   MSIOF3_SS2),
+
+       PINMUX_IPSR_GPSR(IP0SR0_15_12,  IRQ3),
+       PINMUX_IPSR_GPSR(IP0SR0_15_12,  MSIOF3_SCK),
+
+       PINMUX_IPSR_GPSR(IP0SR0_19_16,  IRQ2),
+       PINMUX_IPSR_GPSR(IP0SR0_19_16,  MSIOF3_TXD),
+
+       PINMUX_IPSR_GPSR(IP0SR0_23_20,  IRQ1),
+       PINMUX_IPSR_GPSR(IP0SR0_23_20,  MSIOF3_RXD),
+
+       PINMUX_IPSR_GPSR(IP0SR0_27_24,  IRQ0),
+       PINMUX_IPSR_GPSR(IP0SR0_27_24,  MSIOF3_SYNC),
+
+       PINMUX_IPSR_GPSR(IP0SR0_31_28,  MSIOF5_SS2),
+
+       /* IP1SR0 */
+       PINMUX_IPSR_GPSR(IP1SR0_3_0,    MSIOF5_SS1),
+
+       PINMUX_IPSR_GPSR(IP1SR0_7_4,    MSIOF5_SYNC),
+
+       PINMUX_IPSR_GPSR(IP1SR0_11_8,   MSIOF5_TXD),
+
+       PINMUX_IPSR_GPSR(IP1SR0_15_12,  MSIOF5_SCK),
+
+       PINMUX_IPSR_GPSR(IP1SR0_19_16,  MSIOF5_RXD),
+
+       PINMUX_IPSR_GPSR(IP1SR0_23_20,  MSIOF2_SS2),
+       PINMUX_IPSR_GPSR(IP1SR0_23_20,  TCLK1),
+       PINMUX_IPSR_GPSR(IP1SR0_23_20,  IRQ2_A),
+
+       PINMUX_IPSR_GPSR(IP1SR0_27_24,  MSIOF2_SS1),
+       PINMUX_IPSR_GPSR(IP1SR0_27_24,  HTX1),
+       PINMUX_IPSR_GPSR(IP1SR0_27_24,  TX1),
+
+       PINMUX_IPSR_GPSR(IP1SR0_31_28,  MSIOF2_SYNC),
+       PINMUX_IPSR_GPSR(IP1SR0_31_28,  HRX1),
+       PINMUX_IPSR_GPSR(IP1SR0_31_28,  RX1),
+
+       /* IP2SR0 */
+       PINMUX_IPSR_GPSR(IP2SR0_3_0,    MSIOF2_TXD),
+       PINMUX_IPSR_GPSR(IP2SR0_3_0,    HCTS1_N),
+       PINMUX_IPSR_GPSR(IP2SR0_3_0,    CTS1_N),
+
+       PINMUX_IPSR_GPSR(IP2SR0_7_4,    MSIOF2_SCK),
+       PINMUX_IPSR_GPSR(IP2SR0_7_4,    HRTS1_N),
+       PINMUX_IPSR_GPSR(IP2SR0_7_4,    RTS1_N),
+
+       PINMUX_IPSR_GPSR(IP2SR0_11_8,   MSIOF2_RXD),
+       PINMUX_IPSR_GPSR(IP2SR0_11_8,   HSCK1),
+       PINMUX_IPSR_GPSR(IP2SR0_11_8,   SCK1),
+
+       /* IP0SR1 */
+       PINMUX_IPSR_GPSR(IP0SR1_3_0,    MSIOF1_SS2),
+       PINMUX_IPSR_GPSR(IP0SR1_3_0,    HTX3_A),
+       PINMUX_IPSR_GPSR(IP0SR1_3_0,    TX3),
+
+       PINMUX_IPSR_GPSR(IP0SR1_7_4,    MSIOF1_SS1),
+       PINMUX_IPSR_GPSR(IP0SR1_7_4,    HCTS3_N_A),
+       PINMUX_IPSR_GPSR(IP0SR1_7_4,    RX3),
+
+       PINMUX_IPSR_GPSR(IP0SR1_11_8,   MSIOF1_SYNC),
+       PINMUX_IPSR_GPSR(IP0SR1_11_8,   HRTS3_N_A),
+       PINMUX_IPSR_GPSR(IP0SR1_11_8,   RTS3_N),
+
+       PINMUX_IPSR_GPSR(IP0SR1_15_12,  MSIOF1_SCK),
+       PINMUX_IPSR_GPSR(IP0SR1_15_12,  HSCK3_A),
+       PINMUX_IPSR_GPSR(IP0SR1_15_12,  CTS3_N),
+
+       PINMUX_IPSR_GPSR(IP0SR1_19_16,  MSIOF1_TXD),
+       PINMUX_IPSR_GPSR(IP0SR1_19_16,  HRX3_A),
+       PINMUX_IPSR_GPSR(IP0SR1_19_16,  SCK3),
+
+       PINMUX_IPSR_GPSR(IP0SR1_23_20,  MSIOF1_RXD),
+
+       PINMUX_IPSR_GPSR(IP0SR1_27_24,  MSIOF0_SS2),
+       PINMUX_IPSR_GPSR(IP0SR1_27_24,  HTX1_X),
+       PINMUX_IPSR_GPSR(IP0SR1_27_24,  TX1_X),
+
+       PINMUX_IPSR_GPSR(IP0SR1_31_28,  MSIOF0_SS1),
+       PINMUX_IPSR_GPSR(IP0SR1_31_28,  HRX1_X),
+       PINMUX_IPSR_GPSR(IP0SR1_31_28,  RX1_X),
+
+       /* IP1SR1 */
+       PINMUX_IPSR_GPSR(IP1SR1_3_0,    MSIOF0_SYNC),
+       PINMUX_IPSR_GPSR(IP1SR1_3_0,    HCTS1_N_X),
+       PINMUX_IPSR_GPSR(IP1SR1_3_0,    CTS1_N_X),
+       PINMUX_IPSR_GPSR(IP1SR1_3_0,    CANFD5_TX_B),
+
+       PINMUX_IPSR_GPSR(IP1SR1_7_4,    MSIOF0_TXD),
+       PINMUX_IPSR_GPSR(IP1SR1_7_4,    HRTS1_N_X),
+       PINMUX_IPSR_GPSR(IP1SR1_7_4,    RTS1_N_X),
+       PINMUX_IPSR_GPSR(IP1SR1_7_4,    CANFD5_RX_B),
+
+       PINMUX_IPSR_GPSR(IP1SR1_11_8,   MSIOF0_SCK),
+       PINMUX_IPSR_GPSR(IP1SR1_11_8,   HSCK1_X),
+       PINMUX_IPSR_GPSR(IP1SR1_11_8,   SCK1_X),
+
+       PINMUX_IPSR_GPSR(IP1SR1_15_12,  MSIOF0_RXD),
+
+       PINMUX_IPSR_GPSR(IP1SR1_19_16,  HTX0),
+       PINMUX_IPSR_GPSR(IP1SR1_19_16,  TX0),
+
+       PINMUX_IPSR_GPSR(IP1SR1_23_20,  HCTS0_N),
+       PINMUX_IPSR_GPSR(IP1SR1_23_20,  CTS0_N),
+       PINMUX_IPSR_GPSR(IP1SR1_23_20,  PWM8_A),
+
+       PINMUX_IPSR_GPSR(IP1SR1_27_24,  HRTS0_N),
+       PINMUX_IPSR_GPSR(IP1SR1_27_24,  RTS0_N),
+       PINMUX_IPSR_GPSR(IP1SR1_27_24,  PWM9_A),
+
+       PINMUX_IPSR_GPSR(IP1SR1_31_28,  HSCK0),
+       PINMUX_IPSR_GPSR(IP1SR1_31_28,  SCK0),
+       PINMUX_IPSR_GPSR(IP1SR1_31_28,  PWM0_A),
+
+       /* IP2SR1 */
+       PINMUX_IPSR_GPSR(IP2SR1_3_0,    HRX0),
+       PINMUX_IPSR_GPSR(IP2SR1_3_0,    RX0),
+
+       PINMUX_IPSR_GPSR(IP2SR1_7_4,    SCIF_CLK),
+       PINMUX_IPSR_GPSR(IP2SR1_7_4,    IRQ4_A),
+
+       PINMUX_IPSR_GPSR(IP2SR1_11_8,   SSI_SCK),
+       PINMUX_IPSR_GPSR(IP2SR1_11_8,   TCLK3),
+
+       PINMUX_IPSR_GPSR(IP2SR1_15_12,  SSI_WS),
+       PINMUX_IPSR_GPSR(IP2SR1_15_12,  TCLK4),
+
+       PINMUX_IPSR_GPSR(IP2SR1_19_16,  SSI_SD),
+       PINMUX_IPSR_GPSR(IP2SR1_19_16,  IRQ0_A),
+
+       PINMUX_IPSR_GPSR(IP2SR1_23_20,  AUDIO_CLKOUT),
+       PINMUX_IPSR_GPSR(IP2SR1_23_20,  IRQ1_A),
+
+       PINMUX_IPSR_GPSR(IP2SR1_27_24,  AUDIO_CLKIN),
+       PINMUX_IPSR_GPSR(IP2SR1_27_24,  PWM3_A),
+
+       PINMUX_IPSR_GPSR(IP2SR1_31_28,  TCLK2),
+       PINMUX_IPSR_GPSR(IP2SR1_31_28,  MSIOF4_SS1),
+       PINMUX_IPSR_GPSR(IP2SR1_31_28,  IRQ3_B),
+
+       /* IP3SR1 */
+       PINMUX_IPSR_GPSR(IP3SR1_3_0,    HRX3),
+       PINMUX_IPSR_GPSR(IP3SR1_3_0,    SCK3_A),
+       PINMUX_IPSR_GPSR(IP3SR1_3_0,    MSIOF4_SS2),
+
+       PINMUX_IPSR_GPSR(IP3SR1_7_4,    HSCK3),
+       PINMUX_IPSR_GPSR(IP3SR1_7_4,    CTS3_N_A),
+       PINMUX_IPSR_GPSR(IP3SR1_7_4,    MSIOF4_SCK),
+       PINMUX_IPSR_GPSR(IP3SR1_7_4,    TPU0TO0_A),
+
+       PINMUX_IPSR_GPSR(IP3SR1_11_8,   HRTS3_N),
+       PINMUX_IPSR_GPSR(IP3SR1_11_8,   RTS3_N_A),
+       PINMUX_IPSR_GPSR(IP3SR1_11_8,   MSIOF4_TXD),
+       PINMUX_IPSR_GPSR(IP3SR1_11_8,   TPU0TO1_A),
+
+       PINMUX_IPSR_GPSR(IP3SR1_15_12,  HCTS3_N),
+       PINMUX_IPSR_GPSR(IP3SR1_15_12,  RX3_A),
+       PINMUX_IPSR_GPSR(IP3SR1_15_12,  MSIOF4_RXD),
+
+       PINMUX_IPSR_GPSR(IP3SR1_19_16,  HTX3),
+       PINMUX_IPSR_GPSR(IP3SR1_19_16,  TX3_A),
+       PINMUX_IPSR_GPSR(IP3SR1_19_16,  MSIOF4_SYNC),
+
+       /* IP0SR2 */
+       PINMUX_IPSR_GPSR(IP0SR2_3_0,    FXR_TXDA),
+       PINMUX_IPSR_GPSR(IP0SR2_3_0,    CANFD1_TX),
+       PINMUX_IPSR_GPSR(IP0SR2_3_0,    TPU0TO2_A),
+
+       PINMUX_IPSR_GPSR(IP0SR2_7_4,    FXR_TXENA_N),
+       PINMUX_IPSR_GPSR(IP0SR2_7_4,    CANFD1_RX),
+       PINMUX_IPSR_GPSR(IP0SR2_7_4,    TPU0TO3_A),
+
+       PINMUX_IPSR_GPSR(IP0SR2_11_8,   RXDA_EXTFXR),
+       PINMUX_IPSR_GPSR(IP0SR2_11_8,   CANFD5_TX),
+       PINMUX_IPSR_GPSR(IP0SR2_11_8,   IRQ5),
+
+       PINMUX_IPSR_GPSR(IP0SR2_15_12,  CLK_EXTFXR),
+       PINMUX_IPSR_GPSR(IP0SR2_15_12,  CANFD5_RX),
+       PINMUX_IPSR_GPSR(IP0SR2_15_12,  IRQ4_B),
+
+       PINMUX_IPSR_GPSR(IP0SR2_19_16,  RXDB_EXTFXR),
+
+       PINMUX_IPSR_GPSR(IP0SR2_23_20,  FXR_TXENB_N),
+
+       PINMUX_IPSR_GPSR(IP0SR2_27_24,  FXR_TXDB),
+
+       PINMUX_IPSR_GPSR(IP0SR2_31_28,  TPU0TO1),
+       PINMUX_IPSR_GPSR(IP0SR2_31_28,  CANFD6_TX),
+       PINMUX_IPSR_GPSR(IP0SR2_31_28,  TCLK2_B),
+
+       /* IP1SR2 */
+       PINMUX_IPSR_GPSR(IP1SR2_3_0,    TPU0TO0),
+       PINMUX_IPSR_GPSR(IP1SR2_3_0,    CANFD6_RX),
+       PINMUX_IPSR_GPSR(IP1SR2_3_0,    TCLK1_A),
+
+       PINMUX_IPSR_GPSR(IP1SR2_7_4,    CAN_CLK),
+       PINMUX_IPSR_GPSR(IP1SR2_7_4,    FXR_TXENA_N_X),
+
+       PINMUX_IPSR_GPSR(IP1SR2_11_8,   CANFD0_TX),
+       PINMUX_IPSR_GPSR(IP1SR2_11_8,   FXR_TXENB_N_X),
+
+       PINMUX_IPSR_GPSR(IP1SR2_15_12,  CANFD0_RX),
+       PINMUX_IPSR_GPSR(IP1SR2_15_12,  STPWT_EXTFXR),
+
+       PINMUX_IPSR_GPSR(IP1SR2_19_16,  CANFD2_TX),
+       PINMUX_IPSR_GPSR(IP1SR2_19_16,  TPU0TO2),
+       PINMUX_IPSR_GPSR(IP1SR2_19_16,  TCLK3_A),
+
+       PINMUX_IPSR_GPSR(IP1SR2_23_20,  CANFD2_RX),
+       PINMUX_IPSR_GPSR(IP1SR2_23_20,  TPU0TO3),
+       PINMUX_IPSR_GPSR(IP1SR2_23_20,  PWM1_B),
+       PINMUX_IPSR_GPSR(IP1SR2_23_20,  TCLK4_A),
+
+       PINMUX_IPSR_GPSR(IP1SR2_27_24,  CANFD3_TX),
+       PINMUX_IPSR_GPSR(IP1SR2_27_24,  PWM2_B),
+
+       PINMUX_IPSR_GPSR(IP1SR2_31_28,  CANFD3_RX),
+       PINMUX_IPSR_GPSR(IP1SR2_31_28,  PWM3_B),
+
+       /* IP2SR2 */
+       PINMUX_IPSR_GPSR(IP2SR2_3_0,    CANFD4_TX),
+       PINMUX_IPSR_GPSR(IP2SR2_3_0,    PWM4),
+
+       PINMUX_IPSR_GPSR(IP2SR2_7_4,    CANFD4_RX),
+       PINMUX_IPSR_GPSR(IP2SR2_7_4,    PWM5),
+
+       PINMUX_IPSR_GPSR(IP2SR2_11_8,   CANFD7_TX),
+       PINMUX_IPSR_GPSR(IP2SR2_11_8,   PWM6),
+
+       PINMUX_IPSR_GPSR(IP2SR2_15_12,  CANFD7_RX),
+       PINMUX_IPSR_GPSR(IP2SR2_15_12,  PWM7),
+
+       /* IP0SR3 */
+       PINMUX_IPSR_GPSR(IP0SR3_3_0,    MMC_SD_D1),
+       PINMUX_IPSR_GPSR(IP0SR3_7_4,    MMC_SD_D0),
+       PINMUX_IPSR_GPSR(IP0SR3_11_8,   MMC_SD_D2),
+       PINMUX_IPSR_GPSR(IP0SR3_15_12,  MMC_SD_CLK),
+       PINMUX_IPSR_GPSR(IP0SR3_19_16,  MMC_DS),
+       PINMUX_IPSR_GPSR(IP0SR3_23_20,  MMC_SD_D3),
+       PINMUX_IPSR_GPSR(IP0SR3_27_24,  MMC_D5),
+       PINMUX_IPSR_GPSR(IP0SR3_31_28,  MMC_D4),
+
+       /* IP1SR3 */
+       PINMUX_IPSR_GPSR(IP1SR3_3_0,    MMC_D7),
+
+       PINMUX_IPSR_GPSR(IP1SR3_7_4,    MMC_D6),
+
+       PINMUX_IPSR_GPSR(IP1SR3_11_8,   MMC_SD_CMD),
+
+       PINMUX_IPSR_GPSR(IP1SR3_15_12,  SD_CD),
+
+       PINMUX_IPSR_GPSR(IP1SR3_19_16,  SD_WP),
+
+       PINMUX_IPSR_GPSR(IP1SR3_23_20,  IPC_CLKIN),
+       PINMUX_IPSR_GPSR(IP1SR3_23_20,  IPC_CLKEN_IN),
+       PINMUX_IPSR_GPSR(IP1SR3_23_20,  PWM1_A),
+       PINMUX_IPSR_GPSR(IP1SR3_23_20,  TCLK3_X),
+
+       PINMUX_IPSR_GPSR(IP1SR3_27_24,  IPC_CLKOUT),
+       PINMUX_IPSR_GPSR(IP1SR3_27_24,  IPC_CLKEN_OUT),
+       PINMUX_IPSR_GPSR(IP1SR3_27_24,  ERROROUTC_A),
+       PINMUX_IPSR_GPSR(IP1SR3_27_24,  TCLK4_X),
+
+       PINMUX_IPSR_GPSR(IP1SR3_31_28,  QSPI0_SSL),
+
+       /* IP2SR3 */
+       PINMUX_IPSR_GPSR(IP2SR3_3_0,    QSPI0_IO3),
+       PINMUX_IPSR_GPSR(IP2SR3_7_4,    QSPI0_IO2),
+       PINMUX_IPSR_GPSR(IP2SR3_11_8,   QSPI0_MISO_IO1),
+       PINMUX_IPSR_GPSR(IP2SR3_15_12,  QSPI0_MOSI_IO0),
+       PINMUX_IPSR_GPSR(IP2SR3_19_16,  QSPI0_SPCLK),
+       PINMUX_IPSR_GPSR(IP2SR3_23_20,  QSPI1_MOSI_IO0),
+       PINMUX_IPSR_GPSR(IP2SR3_27_24,  QSPI1_SPCLK),
+       PINMUX_IPSR_GPSR(IP2SR3_31_28,  QSPI1_MISO_IO1),
+
+       /* IP3SR3 */
+       PINMUX_IPSR_GPSR(IP3SR3_3_0,    QSPI1_IO2),
+       PINMUX_IPSR_GPSR(IP3SR3_7_4,    QSPI1_SSL),
+       PINMUX_IPSR_GPSR(IP3SR3_11_8,   QSPI1_IO3),
+       PINMUX_IPSR_GPSR(IP3SR3_15_12,  RPC_RESET_N),
+       PINMUX_IPSR_GPSR(IP3SR3_19_16,  RPC_WP_N),
+       PINMUX_IPSR_GPSR(IP3SR3_23_20,  RPC_INT_N),
+
+       /* IP0SR6 */
+       PINMUX_IPSR_GPSR(IP0SR6_3_0,    AVB1_MDIO),
+
+       PINMUX_IPSR_MSEL(IP0SR6_7_4,    AVB1_MAGIC,             SEL_AVB1_MAGIC_1),
+
+       PINMUX_IPSR_MSEL(IP0SR6_11_8,   AVB1_MDC,               SEL_AVB1_MDC_1),
+
+       PINMUX_IPSR_GPSR(IP0SR6_15_12,  AVB1_PHY_INT),
+
+       PINMUX_IPSR_GPSR(IP0SR6_19_16,  AVB1_LINK),
+       PINMUX_IPSR_GPSR(IP0SR6_19_16,  AVB1_MII_TX_ER),
+
+       PINMUX_IPSR_MSEL(IP0SR6_23_20,  AVB1_AVTP_MATCH,        SEL_AVB1_AVTP_MATCH_1),
+       PINMUX_IPSR_MSEL(IP0SR6_23_20,  AVB1_MII_RX_ER,         SEL_AVB1_AVTP_MATCH_0),
+
+       PINMUX_IPSR_MSEL(IP0SR6_27_24,  AVB1_TXC,               SEL_AVB1_TXC_1),
+       PINMUX_IPSR_MSEL(IP0SR6_27_24,  AVB1_MII_TXC,           SEL_AVB1_TXC_0),
+
+       PINMUX_IPSR_MSEL(IP0SR6_31_28,  AVB1_TX_CTL,            SEL_AVB1_TX_CTL_1),
+       PINMUX_IPSR_MSEL(IP0SR6_31_28,  AVB1_MII_TX_EN,         SEL_AVB1_TX_CTL_0),
+
+       /* IP1SR6 */
+       PINMUX_IPSR_GPSR(IP1SR6_3_0,    AVB1_RXC),
+       PINMUX_IPSR_GPSR(IP1SR6_3_0,    AVB1_MII_RXC),
+
+       PINMUX_IPSR_GPSR(IP1SR6_7_4,    AVB1_RX_CTL),
+       PINMUX_IPSR_GPSR(IP1SR6_7_4,    AVB1_MII_RX_DV),
+
+       PINMUX_IPSR_MSEL(IP1SR6_11_8,   AVB1_AVTP_PPS,          SEL_AVB1_AVTP_PPS_1),
+       PINMUX_IPSR_MSEL(IP1SR6_11_8,   AVB1_MII_COL,           SEL_AVB1_AVTP_PPS_0),
+
+       PINMUX_IPSR_GPSR(IP1SR6_15_12,  AVB1_AVTP_CAPTURE),
+       PINMUX_IPSR_GPSR(IP1SR6_15_12,  AVB1_MII_CRS),
+
+       PINMUX_IPSR_MSEL(IP1SR6_19_16,  AVB1_TD1,               SEL_AVB1_TD1_1),
+       PINMUX_IPSR_MSEL(IP1SR6_19_16,  AVB1_MII_TD1,           SEL_AVB1_TD1_0),
+
+       PINMUX_IPSR_MSEL(IP1SR6_23_20,  AVB1_TD0,               SEL_AVB1_TD0_1),
+       PINMUX_IPSR_MSEL(IP1SR6_23_20,  AVB1_MII_TD0,           SEL_AVB1_TD0_0),
+
+       PINMUX_IPSR_GPSR(IP1SR6_27_24,  AVB1_RD1),
+       PINMUX_IPSR_GPSR(IP1SR6_27_24,  AVB1_MII_RD1),
+
+       PINMUX_IPSR_GPSR(IP1SR6_31_28,  AVB1_RD0),
+       PINMUX_IPSR_GPSR(IP1SR6_31_28,  AVB1_MII_RD0),
+
+       /* IP2SR6 */
+       PINMUX_IPSR_MSEL(IP2SR6_3_0,    AVB1_TD2,               SEL_AVB1_TD2_1),
+       PINMUX_IPSR_MSEL(IP2SR6_3_0,    AVB1_MII_TD2,           SEL_AVB1_TD2_0),
+
+       PINMUX_IPSR_GPSR(IP2SR6_7_4,    AVB1_RD2),
+       PINMUX_IPSR_GPSR(IP2SR6_7_4,    AVB1_MII_RD2),
+
+       PINMUX_IPSR_MSEL(IP2SR6_11_8,   AVB1_TD3,               SEL_AVB1_TD3_1),
+       PINMUX_IPSR_MSEL(IP2SR6_11_8,   AVB1_MII_TD3,           SEL_AVB1_TD3_0),
+
+       PINMUX_IPSR_GPSR(IP2SR6_15_12,  AVB1_RD3),
+       PINMUX_IPSR_GPSR(IP2SR6_15_12,  AVB1_MII_RD3),
+
+       PINMUX_IPSR_GPSR(IP2SR6_19_16,  AVB1_TXCREFCLK),
+
+       /* IP0SR7 */
+       PINMUX_IPSR_MSEL(IP0SR7_3_0,    AVB0_AVTP_PPS,          SEL_AVB0_AVTP_PPS_1),
+       PINMUX_IPSR_MSEL(IP0SR7_3_0,    AVB0_MII_COL,           SEL_AVB0_AVTP_PPS_0),
+
+       PINMUX_IPSR_GPSR(IP0SR7_7_4,    AVB0_AVTP_CAPTURE),
+       PINMUX_IPSR_GPSR(IP0SR7_7_4,    AVB0_MII_CRS),
+
+       PINMUX_IPSR_MSEL(IP0SR7_11_8,   AVB0_AVTP_MATCH,        SEL_AVB0_AVTP_MATCH_1),
+       PINMUX_IPSR_MSEL(IP0SR7_11_8,   AVB0_MII_RX_ER,         SEL_AVB0_AVTP_MATCH_0),
+       PINMUX_IPSR_MSEL(IP0SR7_11_8,   CC5_OSCOUT,             SEL_AVB0_AVTP_MATCH_0),
+
+       PINMUX_IPSR_MSEL(IP0SR7_15_12,  AVB0_TD3,               SEL_AVB0_TD3_1),
+       PINMUX_IPSR_MSEL(IP0SR7_15_12,  AVB0_MII_TD3,           SEL_AVB0_TD3_0),
+
+       PINMUX_IPSR_GPSR(IP0SR7_19_16,  AVB0_LINK),
+       PINMUX_IPSR_GPSR(IP0SR7_19_16,  AVB0_MII_TX_ER),
+
+       PINMUX_IPSR_GPSR(IP0SR7_23_20,  AVB0_PHY_INT),
+
+       PINMUX_IPSR_MSEL(IP0SR7_27_24,  AVB0_TD2,               SEL_AVB0_TD2_1),
+       PINMUX_IPSR_MSEL(IP0SR7_27_24,  AVB0_MII_TD2,           SEL_AVB0_TD2_0),
+
+       PINMUX_IPSR_MSEL(IP0SR7_31_28,  AVB0_TD1,               SEL_AVB0_TD1_1),
+       PINMUX_IPSR_MSEL(IP0SR7_31_28,  AVB0_MII_TD1,           SEL_AVB0_TD1_0),
+
+       /* IP1SR7 */
+       PINMUX_IPSR_GPSR(IP1SR7_3_0,    AVB0_RD3),
+       PINMUX_IPSR_GPSR(IP1SR7_3_0,    AVB0_MII_RD3),
+
+       PINMUX_IPSR_GPSR(IP1SR7_7_4,    AVB0_TXCREFCLK),
+
+       PINMUX_IPSR_MSEL(IP1SR7_11_8,   AVB0_MAGIC,             SEL_AVB0_MAGIC_1),
+
+       PINMUX_IPSR_MSEL(IP1SR7_15_12,  AVB0_TD0,               SEL_AVB0_TD0_1),
+       PINMUX_IPSR_MSEL(IP1SR7_15_12,  AVB0_MII_TD0,           SEL_AVB0_TD0_0),
+
+       PINMUX_IPSR_GPSR(IP1SR7_19_16,  AVB0_RD2),
+       PINMUX_IPSR_GPSR(IP1SR7_19_16,  AVB0_MII_RD2),
+
+       PINMUX_IPSR_MSEL(IP1SR7_23_20,  AVB0_MDC,               SEL_AVB0_MDC_1),
+
+       PINMUX_IPSR_GPSR(IP1SR7_27_24,  AVB0_MDIO),
+
+       PINMUX_IPSR_MSEL(IP1SR7_31_28,  AVB0_TXC,               SEL_AVB0_TXC_1),
+       PINMUX_IPSR_MSEL(IP1SR7_31_28,  AVB0_MII_TXC,           SEL_AVB0_TXC_0),
+
+       /* IP2SR7 */
+       PINMUX_IPSR_MSEL(IP2SR7_3_0,    AVB0_TX_CTL,            SEL_AVB0_TX_CTL_1),
+       PINMUX_IPSR_MSEL(IP2SR7_3_0,    AVB0_MII_TX_EN,         SEL_AVB0_TX_CTL_0),
+
+       PINMUX_IPSR_GPSR(IP2SR7_7_4,    AVB0_RD1),
+       PINMUX_IPSR_GPSR(IP2SR7_7_4,    AVB0_MII_RD1),
+
+       PINMUX_IPSR_GPSR(IP2SR7_11_8,   AVB0_RD0),
+       PINMUX_IPSR_GPSR(IP2SR7_11_8,   AVB0_MII_RD0),
+
+       PINMUX_IPSR_GPSR(IP2SR7_15_12,  AVB0_RXC),
+       PINMUX_IPSR_GPSR(IP2SR7_15_12,  AVB0_MII_RXC),
+
+       PINMUX_IPSR_GPSR(IP2SR7_19_16,  AVB0_RX_CTL),
+       PINMUX_IPSR_GPSR(IP2SR7_19_16,  AVB0_MII_RX_DV),
+
+       /* IP0SR8 */
+       PINMUX_IPSR_MSEL(IP0SR8_3_0,    SCL0,                   SEL_SCL0_0),
+       PINMUX_IPSR_MSEL(IP0SR8_7_4,    SDA0,                   SEL_SDA0_0),
+       PINMUX_IPSR_MSEL(IP0SR8_11_8,   SCL1,                   SEL_SCL1_0),
+       PINMUX_IPSR_MSEL(IP0SR8_15_12,  SDA1,                   SEL_SDA1_0),
+       PINMUX_IPSR_MSEL(IP0SR8_19_16,  SCL2,                   SEL_SCL2_0),
+       PINMUX_IPSR_MSEL(IP0SR8_23_20,  SDA2,                   SEL_SDA2_0),
+       PINMUX_IPSR_MSEL(IP0SR8_27_24,  SCL3,                   SEL_SCL3_0),
+       PINMUX_IPSR_MSEL(IP0SR8_31_28,  SDA3,                   SEL_SDA3_0),
+
+       /* IP1SR8 */
+       PINMUX_IPSR_MSEL(IP1SR8_3_0,    SCL4,                   SEL_SCL4_0),
+       PINMUX_IPSR_MSEL(IP1SR8_3_0,    HRX2,                   SEL_SCL4_0),
+       PINMUX_IPSR_MSEL(IP1SR8_3_0,    SCK4,                   SEL_SCL4_0),
+
+       PINMUX_IPSR_MSEL(IP1SR8_7_4,    SDA4,                   SEL_SDA4_0),
+       PINMUX_IPSR_MSEL(IP1SR8_7_4,    HTX2,                   SEL_SDA4_0),
+       PINMUX_IPSR_MSEL(IP1SR8_7_4,    CTS4_N,                 SEL_SDA4_0),
+
+       PINMUX_IPSR_MSEL(IP1SR8_11_8,   SCL5,                   SEL_SCL5_0),
+       PINMUX_IPSR_MSEL(IP1SR8_11_8,   HRTS2_N,                SEL_SCL5_0),
+       PINMUX_IPSR_MSEL(IP1SR8_11_8,   RTS4_N,                 SEL_SCL5_0),
+
+       PINMUX_IPSR_MSEL(IP1SR8_15_12,  SDA5,                   SEL_SDA5_0),
+       PINMUX_IPSR_MSEL(IP1SR8_15_12,  SCIF_CLK2,              SEL_SDA5_0),
+
+       PINMUX_IPSR_GPSR(IP1SR8_19_16,  HCTS2_N),
+       PINMUX_IPSR_GPSR(IP1SR8_19_16,  TX4),
+
+       PINMUX_IPSR_GPSR(IP1SR8_23_20,  HSCK2),
+       PINMUX_IPSR_GPSR(IP1SR8_23_20,  RX4),
+};
+
+/*
+ * Pins not associated with a GPIO port.
+ */
+enum {
+       GP_ASSIGN_LAST(),
+};
+
+static const struct sh_pfc_pin pinmux_pins[] = {
+       PINMUX_GPIO_GP_ALL(),
+};
+
+/* - AVB0 ------------------------------------------------ */
+static const unsigned int avb0_link_pins[] = {
+       /* AVB0_LINK */
+       RCAR_GP_PIN(7, 4),
+};
+static const unsigned int avb0_link_mux[] = {
+       AVB0_LINK_MARK,
+};
+static const unsigned int avb0_magic_pins[] = {
+       /* AVB0_MAGIC */
+       RCAR_GP_PIN(7, 10),
+};
+static const unsigned int avb0_magic_mux[] = {
+       AVB0_MAGIC_MARK,
+};
+static const unsigned int avb0_phy_int_pins[] = {
+       /* AVB0_PHY_INT */
+       RCAR_GP_PIN(7, 5),
+};
+static const unsigned int avb0_phy_int_mux[] = {
+       AVB0_PHY_INT_MARK,
+};
+static const unsigned int avb0_mdio_pins[] = {
+       /* AVB0_MDC, AVB0_MDIO */
+       RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
+};
+static const unsigned int avb0_mdio_mux[] = {
+       AVB0_MDC_MARK, AVB0_MDIO_MARK,
+};
+static const unsigned int avb0_rgmii_pins[] = {
+       /*
+        * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
+        * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,
+        */
+       RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15),
+       RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7,  7),
+       RCAR_GP_PIN(7,  6), RCAR_GP_PIN(7,  3),
+       RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19),
+       RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
+       RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7,  8),
+};
+static const unsigned int avb0_rgmii_mux[] = {
+       AVB0_TX_CTL_MARK,       AVB0_TXC_MARK,
+       AVB0_TD0_MARK,          AVB0_TD1_MARK,
+       AVB0_TD2_MARK,          AVB0_TD3_MARK,
+       AVB0_RX_CTL_MARK,       AVB0_RXC_MARK,
+       AVB0_RD0_MARK,          AVB0_RD1_MARK,
+       AVB0_RD2_MARK,          AVB0_RD3_MARK,
+};
+static const unsigned int avb0_txcrefclk_pins[] = {
+       /* AVB0_TXCREFCLK */
+       RCAR_GP_PIN(7, 9),
+};
+static const unsigned int avb0_txcrefclk_mux[] = {
+       AVB0_TXCREFCLK_MARK,
+};
+static const unsigned int avb0_avtp_pps_pins[] = {
+       /* AVB0_AVTP_PPS */
+       RCAR_GP_PIN(7, 0),
+};
+static const unsigned int avb0_avtp_pps_mux[] = {
+       AVB0_AVTP_PPS_MARK,
+};
+static const unsigned int avb0_avtp_capture_pins[] = {
+       /* AVB0_AVTP_CAPTURE */
+       RCAR_GP_PIN(7, 1),
+};
+static const unsigned int avb0_avtp_capture_mux[] = {
+       AVB0_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb0_avtp_match_pins[] = {
+       /* AVB0_AVTP_MATCH */
+       RCAR_GP_PIN(7, 2),
+};
+static const unsigned int avb0_avtp_match_mux[] = {
+       AVB0_AVTP_MATCH_MARK,
+};
+
+/* - AVB1 ------------------------------------------------ */
+static const unsigned int avb1_link_pins[] = {
+       /* AVB1_LINK */
+       RCAR_GP_PIN(6, 4),
+};
+static const unsigned int avb1_link_mux[] = {
+       AVB1_LINK_MARK,
+};
+static const unsigned int avb1_magic_pins[] = {
+       /* AVB1_MAGIC */
+       RCAR_GP_PIN(6, 1),
+};
+static const unsigned int avb1_magic_mux[] = {
+       AVB1_MAGIC_MARK,
+};
+static const unsigned int avb1_phy_int_pins[] = {
+       /* AVB1_PHY_INT */
+       RCAR_GP_PIN(6, 3),
+};
+static const unsigned int avb1_phy_int_mux[] = {
+       AVB1_PHY_INT_MARK,
+};
+static const unsigned int avb1_mdio_pins[] = {
+       /* AVB1_MDC, AVB1_MDIO */
+       RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0),
+};
+static const unsigned int avb1_mdio_mux[] = {
+       AVB1_MDC_MARK, AVB1_MDIO_MARK,
+};
+static const unsigned int avb1_rgmii_pins[] = {
+       /*
+        * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
+        * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,
+        */
+       RCAR_GP_PIN(6,  7), RCAR_GP_PIN(6,  6),
+       RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12),
+       RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18),
+       RCAR_GP_PIN(6,  9), RCAR_GP_PIN(6,  8),
+       RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
+       RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19),
+};
+static const unsigned int avb1_rgmii_mux[] = {
+       AVB1_TX_CTL_MARK,       AVB1_TXC_MARK,
+       AVB1_TD0_MARK,          AVB1_TD1_MARK,
+       AVB1_TD2_MARK,          AVB1_TD3_MARK,
+       AVB1_RX_CTL_MARK,       AVB1_RXC_MARK,
+       AVB1_RD0_MARK,          AVB1_RD1_MARK,
+       AVB1_RD2_MARK,          AVB1_RD3_MARK,
+};
+static const unsigned int avb1_txcrefclk_pins[] = {
+       /* AVB1_TXCREFCLK */
+       RCAR_GP_PIN(6, 20),
+};
+static const unsigned int avb1_txcrefclk_mux[] = {
+       AVB1_TXCREFCLK_MARK,
+};
+static const unsigned int avb1_avtp_pps_pins[] = {
+       /* AVB1_AVTP_PPS */
+       RCAR_GP_PIN(6, 10),
+};
+static const unsigned int avb1_avtp_pps_mux[] = {
+       AVB1_AVTP_PPS_MARK,
+};
+static const unsigned int avb1_avtp_capture_pins[] = {
+       /* AVB1_AVTP_CAPTURE */
+       RCAR_GP_PIN(6, 11),
+};
+static const unsigned int avb1_avtp_capture_mux[] = {
+       AVB1_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb1_avtp_match_pins[] = {
+       /* AVB1_AVTP_MATCH */
+       RCAR_GP_PIN(6, 5),
+};
+static const unsigned int avb1_avtp_match_mux[] = {
+       AVB1_AVTP_MATCH_MARK,
+};
+
+/* - AVB2 ------------------------------------------------ */
+static const unsigned int avb2_link_pins[] = {
+       /* AVB2_LINK */
+       RCAR_GP_PIN(5, 3),
+};
+static const unsigned int avb2_link_mux[] = {
+       AVB2_LINK_MARK,
+};
+static const unsigned int avb2_magic_pins[] = {
+       /* AVB2_MAGIC */
+       RCAR_GP_PIN(5, 5),
+};
+static const unsigned int avb2_magic_mux[] = {
+       AVB2_MAGIC_MARK,
+};
+static const unsigned int avb2_phy_int_pins[] = {
+       /* AVB2_PHY_INT */
+       RCAR_GP_PIN(5, 4),
+};
+static const unsigned int avb2_phy_int_mux[] = {
+       AVB2_PHY_INT_MARK,
+};
+static const unsigned int avb2_mdio_pins[] = {
+       /* AVB2_MDC, AVB2_MDIO */
+       RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10),
+};
+static const unsigned int avb2_mdio_mux[] = {
+       AVB2_MDC_MARK, AVB2_MDIO_MARK,
+};
+static const unsigned int avb2_rgmii_pins[] = {
+       /*
+        * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,
+        * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,
+        */
+       RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16),
+       RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12),
+       RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5,  8),
+       RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18),
+       RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14),
+       RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5,  9),
+};
+static const unsigned int avb2_rgmii_mux[] = {
+       AVB2_TX_CTL_MARK,       AVB2_TXC_MARK,
+       AVB2_TD0_MARK,          AVB2_TD1_MARK,
+       AVB2_TD2_MARK,          AVB2_TD3_MARK,
+       AVB2_RX_CTL_MARK,       AVB2_RXC_MARK,
+       AVB2_RD0_MARK,          AVB2_RD1_MARK,
+       AVB2_RD2_MARK,          AVB2_RD3_MARK,
+};
+static const unsigned int avb2_txcrefclk_pins[] = {
+       /* AVB2_TXCREFCLK */
+       RCAR_GP_PIN(5, 7),
+};
+static const unsigned int avb2_txcrefclk_mux[] = {
+       AVB2_TXCREFCLK_MARK,
+};
+static const unsigned int avb2_avtp_pps_pins[] = {
+       /* AVB2_AVTP_PPS */
+       RCAR_GP_PIN(5, 0),
+};
+static const unsigned int avb2_avtp_pps_mux[] = {
+       AVB2_AVTP_PPS_MARK,
+};
+static const unsigned int avb2_avtp_capture_pins[] = {
+       /* AVB2_AVTP_CAPTURE */
+       RCAR_GP_PIN(5, 1),
+};
+static const unsigned int avb2_avtp_capture_mux[] = {
+       AVB2_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb2_avtp_match_pins[] = {
+       /* AVB2_AVTP_MATCH */
+       RCAR_GP_PIN(5, 2),
+};
+static const unsigned int avb2_avtp_match_mux[] = {
+       AVB2_AVTP_MATCH_MARK,
+};
+
+/* - CANFD0 ----------------------------------------------------------------- */
+static const unsigned int canfd0_data_pins[] = {
+       /* CANFD0_TX, CANFD0_RX */
+       RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+};
+static const unsigned int canfd0_data_mux[] = {
+       CANFD0_TX_MARK, CANFD0_RX_MARK,
+};
+
+/* - CANFD1 ----------------------------------------------------------------- */
+static const unsigned int canfd1_data_pins[] = {
+       /* CANFD1_TX, CANFD1_RX */
+       RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+};
+static const unsigned int canfd1_data_mux[] = {
+       CANFD1_TX_MARK, CANFD1_RX_MARK,
+};
+
+/* - CANFD2 ----------------------------------------------------------------- */
+static const unsigned int canfd2_data_pins[] = {
+       /* CANFD2_TX, CANFD2_RX */
+       RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int canfd2_data_mux[] = {
+       CANFD2_TX_MARK, CANFD2_RX_MARK,
+};
+
+/* - CANFD3 ----------------------------------------------------------------- */
+static const unsigned int canfd3_data_pins[] = {
+       /* CANFD3_TX, CANFD3_RX */
+       RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
+};
+static const unsigned int canfd3_data_mux[] = {
+       CANFD3_TX_MARK, CANFD3_RX_MARK,
+};
+
+/* - CANFD4 ----------------------------------------------------------------- */
+static const unsigned int canfd4_data_pins[] = {
+       /* CANFD4_TX, CANFD4_RX */
+       RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
+};
+static const unsigned int canfd4_data_mux[] = {
+       CANFD4_TX_MARK, CANFD4_RX_MARK,
+};
+
+/* - CANFD5 ----------------------------------------------------------------- */
+static const unsigned int canfd5_data_pins[] = {
+       /* CANFD5_TX, CANFD5_RX */
+       RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+};
+static const unsigned int canfd5_data_mux[] = {
+       CANFD5_TX_MARK, CANFD5_RX_MARK,
+};
+
+/* - CANFD5_B ----------------------------------------------------------------- */
+static const unsigned int canfd5_data_b_pins[] = {
+       /* CANFD5_TX_B, CANFD5_RX_B */
+       RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
+};
+static const unsigned int canfd5_data_b_mux[] = {
+       CANFD5_TX_B_MARK, CANFD5_RX_B_MARK,
+};
+
+/* - CANFD6 ----------------------------------------------------------------- */
+static const unsigned int canfd6_data_pins[] = {
+       /* CANFD6_TX, CANFD6_RX */
+       RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+};
+static const unsigned int canfd6_data_mux[] = {
+       CANFD6_TX_MARK, CANFD6_RX_MARK,
+};
+
+/* - CANFD7 ----------------------------------------------------------------- */
+static const unsigned int canfd7_data_pins[] = {
+       /* CANFD7_TX, CANFD7_RX */
+       RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
+};
+static const unsigned int canfd7_data_mux[] = {
+       CANFD7_TX_MARK, CANFD7_RX_MARK,
+};
+
+/* - CANFD Clock ------------------------------------------------------------ */
+static const unsigned int can_clk_pins[] = {
+       /* CAN_CLK */
+       RCAR_GP_PIN(2, 9),
+};
+static const unsigned int can_clk_mux[] = {
+       CAN_CLK_MARK,
+};
+
+/* - HSCIF0 ----------------------------------------------------------------- */
+static const unsigned int hscif0_data_pins[] = {
+       /* HRX0, HTX0 */
+       RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
+};
+static const unsigned int hscif0_data_mux[] = {
+       HRX0_MARK, HTX0_MARK,
+};
+static const unsigned int hscif0_clk_pins[] = {
+       /* HSCK0 */
+       RCAR_GP_PIN(1, 15),
+};
+static const unsigned int hscif0_clk_mux[] = {
+       HSCK0_MARK,
+};
+static const unsigned int hscif0_ctrl_pins[] = {
+       /* HRTS0_N, HCTS0_N */
+       RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
+};
+static const unsigned int hscif0_ctrl_mux[] = {
+       HRTS0_N_MARK, HCTS0_N_MARK,
+};
+
+/* - HSCIF1 ----------------------------------------------------------------- */
+static const unsigned int hscif1_data_pins[] = {
+       /* HRX1, HTX1 */
+       RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
+};
+static const unsigned int hscif1_data_mux[] = {
+       HRX1_MARK, HTX1_MARK,
+};
+static const unsigned int hscif1_clk_pins[] = {
+       /* HSCK1 */
+       RCAR_GP_PIN(0, 18),
+};
+static const unsigned int hscif1_clk_mux[] = {
+       HSCK1_MARK,
+};
+static const unsigned int hscif1_ctrl_pins[] = {
+       /* HRTS1_N, HCTS1_N */
+       RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
+};
+static const unsigned int hscif1_ctrl_mux[] = {
+       HRTS1_N_MARK, HCTS1_N_MARK,
+};
+
+/* - HSCIF1_X---------------------------------------------------------------- */
+static const unsigned int hscif1_data_x_pins[] = {
+       /* HRX1_X, HTX1_X */
+       RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int hscif1_data_x_mux[] = {
+       HRX1_X_MARK, HTX1_X_MARK,
+};
+static const unsigned int hscif1_clk_x_pins[] = {
+       /* HSCK1_X */
+       RCAR_GP_PIN(1, 10),
+};
+static const unsigned int hscif1_clk_x_mux[] = {
+       HSCK1_X_MARK,
+};
+static const unsigned int hscif1_ctrl_x_pins[] = {
+       /* HRTS1_N_X, HCTS1_N_X */
+       RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
+};
+static const unsigned int hscif1_ctrl_x_mux[] = {
+       HRTS1_N_X_MARK, HCTS1_N_X_MARK,
+};
+
+/* - HSCIF2 ----------------------------------------------------------------- */
+static const unsigned int hscif2_data_pins[] = {
+       /* HRX2, HTX2 */
+       RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
+};
+static const unsigned int hscif2_data_mux[] = {
+       HRX2_MARK, HTX2_MARK,
+};
+static const unsigned int hscif2_clk_pins[] = {
+       /* HSCK2 */
+       RCAR_GP_PIN(8, 13),
+};
+static const unsigned int hscif2_clk_mux[] = {
+       HSCK2_MARK,
+};
+static const unsigned int hscif2_ctrl_pins[] = {
+       /* HRTS2_N, HCTS2_N */
+       RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 12),
+};
+static const unsigned int hscif2_ctrl_mux[] = {
+       HRTS2_N_MARK, HCTS2_N_MARK,
+};
+
+/* - HSCIF3 ----------------------------------------------------------------- */
+static const unsigned int hscif3_data_pins[] = {
+       /* HRX3, HTX3 */
+       RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
+};
+static const unsigned int hscif3_data_mux[] = {
+       HRX3_MARK, HTX3_MARK,
+};
+static const unsigned int hscif3_clk_pins[] = {
+       /* HSCK3 */
+       RCAR_GP_PIN(1, 25),
+};
+static const unsigned int hscif3_clk_mux[] = {
+       HSCK3_MARK,
+};
+static const unsigned int hscif3_ctrl_pins[] = {
+       /* HRTS3_N, HCTS3_N */
+       RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
+};
+static const unsigned int hscif3_ctrl_mux[] = {
+       HRTS3_N_MARK, HCTS3_N_MARK,
+};
+
+/* - HSCIF3_A ----------------------------------------------------------------- */
+static const unsigned int hscif3_data_a_pins[] = {
+       /* HRX3_A, HTX3_A */
+       RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
+};
+static const unsigned int hscif3_data_a_mux[] = {
+       HRX3_A_MARK, HTX3_A_MARK,
+};
+static const unsigned int hscif3_clk_a_pins[] = {
+       /* HSCK3_A */
+       RCAR_GP_PIN(1, 3),
+};
+static const unsigned int hscif3_clk_a_mux[] = {
+       HSCK3_A_MARK,
+};
+static const unsigned int hscif3_ctrl_a_pins[] = {
+       /* HRTS3_N_A, HCTS3_N_A */
+       RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
+};
+static const unsigned int hscif3_ctrl_a_mux[] = {
+       HRTS3_N_A_MARK, HCTS3_N_A_MARK,
+};
+
+/* - I2C0 ------------------------------------------------------------------- */
+static const unsigned int i2c0_pins[] = {
+       /* SDA0, SCL0 */
+       RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 0),
+};
+static const unsigned int i2c0_mux[] = {
+       SDA0_MARK, SCL0_MARK,
+};
+
+/* - I2C1 ------------------------------------------------------------------- */
+static const unsigned int i2c1_pins[] = {
+       /* SDA1, SCL1 */
+       RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 2),
+};
+static const unsigned int i2c1_mux[] = {
+       SDA1_MARK, SCL1_MARK,
+};
+
+/* - I2C2 ------------------------------------------------------------------- */
+static const unsigned int i2c2_pins[] = {
+       /* SDA2, SCL2 */
+       RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 4),
+};
+static const unsigned int i2c2_mux[] = {
+       SDA2_MARK, SCL2_MARK,
+};
+
+/* - I2C3 ------------------------------------------------------------------- */
+static const unsigned int i2c3_pins[] = {
+       /* SDA3, SCL3 */
+       RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 6),
+};
+static const unsigned int i2c3_mux[] = {
+       SDA3_MARK, SCL3_MARK,
+};
+
+/* - I2C4 ------------------------------------------------------------------- */
+static const unsigned int i2c4_pins[] = {
+       /* SDA4, SCL4 */
+       RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 8),
+};
+static const unsigned int i2c4_mux[] = {
+       SDA4_MARK, SCL4_MARK,
+};
+
+/* - I2C5 ------------------------------------------------------------------- */
+static const unsigned int i2c5_pins[] = {
+       /* SDA5, SCL5 */
+       RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 10),
+};
+static const unsigned int i2c5_mux[] = {
+       SDA5_MARK, SCL5_MARK,
+};
+
+/* - MMC -------------------------------------------------------------------- */
+static const unsigned int mmc_data_pins[] = {
+       /* MMC_SD_D[0:3], MMC_D[4:7] */
+       RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
+       RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5),
+       RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6),
+       RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
+};
+static const unsigned int mmc_data_mux[] = {
+       MMC_SD_D0_MARK, MMC_SD_D1_MARK,
+       MMC_SD_D2_MARK, MMC_SD_D3_MARK,
+       MMC_D4_MARK, MMC_D5_MARK,
+       MMC_D6_MARK, MMC_D7_MARK,
+};
+static const unsigned int mmc_ctrl_pins[] = {
+       /* MMC_SD_CLK, MMC_SD_CMD */
+       RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10),
+};
+static const unsigned int mmc_ctrl_mux[] = {
+       MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
+};
+static const unsigned int mmc_cd_pins[] = {
+       /* SD_CD */
+       RCAR_GP_PIN(3, 11),
+};
+static const unsigned int mmc_cd_mux[] = {
+       SD_CD_MARK,
+};
+static const unsigned int mmc_wp_pins[] = {
+       /* SD_WP */
+       RCAR_GP_PIN(3, 12),
+};
+static const unsigned int mmc_wp_mux[] = {
+       SD_WP_MARK,
+};
+static const unsigned int mmc_ds_pins[] = {
+       /* MMC_DS */
+       RCAR_GP_PIN(3, 4),
+};
+static const unsigned int mmc_ds_mux[] = {
+       MMC_DS_MARK,
+};
+
+/* - MSIOF0 ----------------------------------------------------------------- */
+static const unsigned int msiof0_clk_pins[] = {
+       /* MSIOF0_SCK */
+       RCAR_GP_PIN(1, 10),
+};
+static const unsigned int msiof0_clk_mux[] = {
+       MSIOF0_SCK_MARK,
+};
+static const unsigned int msiof0_sync_pins[] = {
+       /* MSIOF0_SYNC */
+       RCAR_GP_PIN(1, 8),
+};
+static const unsigned int msiof0_sync_mux[] = {
+       MSIOF0_SYNC_MARK,
+};
+static const unsigned int msiof0_ss1_pins[] = {
+       /* MSIOF0_SS1 */
+       RCAR_GP_PIN(1, 7),
+};
+static const unsigned int msiof0_ss1_mux[] = {
+       MSIOF0_SS1_MARK,
+};
+static const unsigned int msiof0_ss2_pins[] = {
+       /* MSIOF0_SS2 */
+       RCAR_GP_PIN(1, 6),
+};
+static const unsigned int msiof0_ss2_mux[] = {
+       MSIOF0_SS2_MARK,
+};
+static const unsigned int msiof0_txd_pins[] = {
+       /* MSIOF0_TXD */
+       RCAR_GP_PIN(1, 9),
+};
+static const unsigned int msiof0_txd_mux[] = {
+       MSIOF0_TXD_MARK,
+};
+static const unsigned int msiof0_rxd_pins[] = {
+       /* MSIOF0_RXD */
+       RCAR_GP_PIN(1, 11),
+};
+static const unsigned int msiof0_rxd_mux[] = {
+       MSIOF0_RXD_MARK,
+};
+
+/* - MSIOF1 ----------------------------------------------------------------- */
+static const unsigned int msiof1_clk_pins[] = {
+       /* MSIOF1_SCK */
+       RCAR_GP_PIN(1, 3),
+};
+static const unsigned int msiof1_clk_mux[] = {
+       MSIOF1_SCK_MARK,
+};
+static const unsigned int msiof1_sync_pins[] = {
+       /* MSIOF1_SYNC */
+       RCAR_GP_PIN(1, 2),
+};
+static const unsigned int msiof1_sync_mux[] = {
+       MSIOF1_SYNC_MARK,
+};
+static const unsigned int msiof1_ss1_pins[] = {
+       /* MSIOF1_SS1 */
+       RCAR_GP_PIN(1, 1),
+};
+static const unsigned int msiof1_ss1_mux[] = {
+       MSIOF1_SS1_MARK,
+};
+static const unsigned int msiof1_ss2_pins[] = {
+       /* MSIOF1_SS2 */
+       RCAR_GP_PIN(1, 0),
+};
+static const unsigned int msiof1_ss2_mux[] = {
+       MSIOF1_SS2_MARK,
+};
+static const unsigned int msiof1_txd_pins[] = {
+       /* MSIOF1_TXD */
+       RCAR_GP_PIN(1, 4),
+};
+static const unsigned int msiof1_txd_mux[] = {
+       MSIOF1_TXD_MARK,
+};
+static const unsigned int msiof1_rxd_pins[] = {
+       /* MSIOF1_RXD */
+       RCAR_GP_PIN(1, 5),
+};
+static const unsigned int msiof1_rxd_mux[] = {
+       MSIOF1_RXD_MARK,
+};
+
+/* - MSIOF2 ----------------------------------------------------------------- */
+static const unsigned int msiof2_clk_pins[] = {
+       /* MSIOF2_SCK */
+       RCAR_GP_PIN(0, 17),
+};
+static const unsigned int msiof2_clk_mux[] = {
+       MSIOF2_SCK_MARK,
+};
+static const unsigned int msiof2_sync_pins[] = {
+       /* MSIOF2_SYNC */
+       RCAR_GP_PIN(0, 15),
+};
+static const unsigned int msiof2_sync_mux[] = {
+       MSIOF2_SYNC_MARK,
+};
+static const unsigned int msiof2_ss1_pins[] = {
+       /* MSIOF2_SS1 */
+       RCAR_GP_PIN(0, 14),
+};
+static const unsigned int msiof2_ss1_mux[] = {
+       MSIOF2_SS1_MARK,
+};
+static const unsigned int msiof2_ss2_pins[] = {
+       /* MSIOF2_SS2 */
+       RCAR_GP_PIN(0, 13),
+};
+static const unsigned int msiof2_ss2_mux[] = {
+       MSIOF2_SS2_MARK,
+};
+static const unsigned int msiof2_txd_pins[] = {
+       /* MSIOF2_TXD */
+       RCAR_GP_PIN(0, 16),
+};
+static const unsigned int msiof2_txd_mux[] = {
+       MSIOF2_TXD_MARK,
+};
+static const unsigned int msiof2_rxd_pins[] = {
+       /* MSIOF2_RXD */
+       RCAR_GP_PIN(0, 18),
+};
+static const unsigned int msiof2_rxd_mux[] = {
+       MSIOF2_RXD_MARK,
+};
+
+/* - MSIOF3 ----------------------------------------------------------------- */
+static const unsigned int msiof3_clk_pins[] = {
+       /* MSIOF3_SCK */
+       RCAR_GP_PIN(0, 3),
+};
+static const unsigned int msiof3_clk_mux[] = {
+       MSIOF3_SCK_MARK,
+};
+static const unsigned int msiof3_sync_pins[] = {
+       /* MSIOF3_SYNC */
+       RCAR_GP_PIN(0, 6),
+};
+static const unsigned int msiof3_sync_mux[] = {
+       MSIOF3_SYNC_MARK,
+};
+static const unsigned int msiof3_ss1_pins[] = {
+       /* MSIOF3_SS1 */
+       RCAR_GP_PIN(0, 1),
+};
+static const unsigned int msiof3_ss1_mux[] = {
+       MSIOF3_SS1_MARK,
+};
+static const unsigned int msiof3_ss2_pins[] = {
+       /* MSIOF3_SS2 */
+       RCAR_GP_PIN(0, 2),
+};
+static const unsigned int msiof3_ss2_mux[] = {
+       MSIOF3_SS2_MARK,
+};
+static const unsigned int msiof3_txd_pins[] = {
+       /* MSIOF3_TXD */
+       RCAR_GP_PIN(0, 4),
+};
+static const unsigned int msiof3_txd_mux[] = {
+       MSIOF3_TXD_MARK,
+};
+static const unsigned int msiof3_rxd_pins[] = {
+       /* MSIOF3_RXD */
+       RCAR_GP_PIN(0, 5),
+};
+static const unsigned int msiof3_rxd_mux[] = {
+       MSIOF3_RXD_MARK,
+};
+
+/* - MSIOF4 ----------------------------------------------------------------- */
+static const unsigned int msiof4_clk_pins[] = {
+       /* MSIOF4_SCK */
+       RCAR_GP_PIN(1, 25),
+};
+static const unsigned int msiof4_clk_mux[] = {
+       MSIOF4_SCK_MARK,
+};
+static const unsigned int msiof4_sync_pins[] = {
+       /* MSIOF4_SYNC */
+       RCAR_GP_PIN(1, 28),
+};
+static const unsigned int msiof4_sync_mux[] = {
+       MSIOF4_SYNC_MARK,
+};
+static const unsigned int msiof4_ss1_pins[] = {
+       /* MSIOF4_SS1 */
+       RCAR_GP_PIN(1, 23),
+};
+static const unsigned int msiof4_ss1_mux[] = {
+       MSIOF4_SS1_MARK,
+};
+static const unsigned int msiof4_ss2_pins[] = {
+       /* MSIOF4_SS2 */
+       RCAR_GP_PIN(1, 24),
+};
+static const unsigned int msiof4_ss2_mux[] = {
+       MSIOF4_SS2_MARK,
+};
+static const unsigned int msiof4_txd_pins[] = {
+       /* MSIOF4_TXD */
+       RCAR_GP_PIN(1, 26),
+};
+static const unsigned int msiof4_txd_mux[] = {
+       MSIOF4_TXD_MARK,
+};
+static const unsigned int msiof4_rxd_pins[] = {
+       /* MSIOF4_RXD */
+       RCAR_GP_PIN(1, 27),
+};
+static const unsigned int msiof4_rxd_mux[] = {
+       MSIOF4_RXD_MARK,
+};
+
+/* - MSIOF5 ----------------------------------------------------------------- */
+static const unsigned int msiof5_clk_pins[] = {
+       /* MSIOF5_SCK */
+       RCAR_GP_PIN(0, 11),
+};
+static const unsigned int msiof5_clk_mux[] = {
+       MSIOF5_SCK_MARK,
+};
+static const unsigned int msiof5_sync_pins[] = {
+       /* MSIOF5_SYNC */
+       RCAR_GP_PIN(0, 9),
+};
+static const unsigned int msiof5_sync_mux[] = {
+       MSIOF5_SYNC_MARK,
+};
+static const unsigned int msiof5_ss1_pins[] = {
+       /* MSIOF5_SS1 */
+       RCAR_GP_PIN(0, 8),
+};
+static const unsigned int msiof5_ss1_mux[] = {
+       MSIOF5_SS1_MARK,
+};
+static const unsigned int msiof5_ss2_pins[] = {
+       /* MSIOF5_SS2 */
+       RCAR_GP_PIN(0, 7),
+};
+static const unsigned int msiof5_ss2_mux[] = {
+       MSIOF5_SS2_MARK,
+};
+static const unsigned int msiof5_txd_pins[] = {
+       /* MSIOF5_TXD */
+       RCAR_GP_PIN(0, 10),
+};
+static const unsigned int msiof5_txd_mux[] = {
+       MSIOF5_TXD_MARK,
+};
+static const unsigned int msiof5_rxd_pins[] = {
+       /* MSIOF5_RXD */
+       RCAR_GP_PIN(0, 12),
+};
+static const unsigned int msiof5_rxd_mux[] = {
+       MSIOF5_RXD_MARK,
+};
+
+/* - PCIE ------------------------------------------------------------------- */
+static const unsigned int pcie0_clkreq_n_pins[] = {
+       /* PCIE0_CLKREQ_N */
+       RCAR_GP_PIN(4, 21),
+};
+
+static const unsigned int pcie0_clkreq_n_mux[] = {
+       PCIE0_CLKREQ_N_MARK,
+};
+
+static const unsigned int pcie1_clkreq_n_pins[] = {
+       /* PCIE1_CLKREQ_N */
+       RCAR_GP_PIN(4, 22),
+};
+
+static const unsigned int pcie1_clkreq_n_mux[] = {
+       PCIE1_CLKREQ_N_MARK,
+};
+
+/* - PWM0_A ------------------------------------------------------------------- */
+static const unsigned int pwm0_a_pins[] = {
+       /* PWM0_A */
+       RCAR_GP_PIN(1, 15),
+};
+static const unsigned int pwm0_a_mux[] = {
+       PWM0_A_MARK,
+};
+
+/* - PWM1_A ------------------------------------------------------------------- */
+static const unsigned int pwm1_a_pins[] = {
+       /* PWM1_A */
+       RCAR_GP_PIN(3, 13),
+};
+static const unsigned int pwm1_a_mux[] = {
+       PWM1_A_MARK,
+};
+
+/* - PWM1_B ------------------------------------------------------------------- */
+static const unsigned int pwm1_b_pins[] = {
+       /* PWM1_B */
+       RCAR_GP_PIN(2, 13),
+};
+static const unsigned int pwm1_b_mux[] = {
+       PWM1_B_MARK,
+};
+
+/* - PWM2_B ------------------------------------------------------------------- */
+static const unsigned int pwm2_b_pins[] = {
+       /* PWM2_B */
+       RCAR_GP_PIN(2, 14),
+};
+static const unsigned int pwm2_b_mux[] = {
+       PWM2_B_MARK,
+};
+
+/* - PWM3_A ------------------------------------------------------------------- */
+static const unsigned int pwm3_a_pins[] = {
+       /* PWM3_A */
+       RCAR_GP_PIN(1, 22),
+};
+static const unsigned int pwm3_a_mux[] = {
+       PWM3_A_MARK,
+};
+
+/* - PWM3_B ------------------------------------------------------------------- */
+static const unsigned int pwm3_b_pins[] = {
+       /* PWM3_B */
+       RCAR_GP_PIN(2, 15),
+};
+static const unsigned int pwm3_b_mux[] = {
+       PWM3_B_MARK,
+};
+
+/* - PWM4 ------------------------------------------------------------------- */
+static const unsigned int pwm4_pins[] = {
+       /* PWM4 */
+       RCAR_GP_PIN(2, 16),
+};
+static const unsigned int pwm4_mux[] = {
+       PWM4_MARK,
+};
+
+/* - PWM5 ------------------------------------------------------------------- */
+static const unsigned int pwm5_pins[] = {
+       /* PWM5 */
+       RCAR_GP_PIN(2, 17),
+};
+static const unsigned int pwm5_mux[] = {
+       PWM5_MARK,
+};
+
+/* - PWM6 ------------------------------------------------------------------- */
+static const unsigned int pwm6_pins[] = {
+       /* PWM6 */
+       RCAR_GP_PIN(2, 18),
+};
+static const unsigned int pwm6_mux[] = {
+       PWM6_MARK,
+};
+
+/* - PWM7 ------------------------------------------------------------------- */
+static const unsigned int pwm7_pins[] = {
+       /* PWM7 */
+       RCAR_GP_PIN(2, 19),
+};
+static const unsigned int pwm7_mux[] = {
+       PWM7_MARK,
+};
+
+/* - PWM8_A ------------------------------------------------------------------- */
+static const unsigned int pwm8_a_pins[] = {
+       /* PWM8_A */
+       RCAR_GP_PIN(1, 13),
+};
+static const unsigned int pwm8_a_mux[] = {
+       PWM8_A_MARK,
+};
+
+/* - PWM9_A ------------------------------------------------------------------- */
+static const unsigned int pwm9_a_pins[] = {
+       /* PWM9_A */
+       RCAR_GP_PIN(1, 14),
+};
+static const unsigned int pwm9_a_mux[] = {
+       PWM9_A_MARK,
+};
+
+/* - QSPI0 ------------------------------------------------------------------ */
+static const unsigned int qspi0_ctrl_pins[] = {
+       /* SPCLK, SSL */
+       RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15),
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+       QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int qspi0_data_pins[] = {
+       /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+       RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
+       RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
+};
+static const unsigned int qspi0_data_mux[] = {
+       QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+       QSPI0_IO2_MARK, QSPI0_IO3_MARK
+};
+
+/* - QSPI1 ------------------------------------------------------------------ */
+static const unsigned int qspi1_ctrl_pins[] = {
+       /* SPCLK, SSL */
+       RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25),
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+       QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int qspi1_data_pins[] = {
+       /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+       RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23),
+       RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26),
+};
+static const unsigned int qspi1_data_mux[] = {
+       QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+       QSPI1_IO2_MARK, QSPI1_IO3_MARK
+};
+
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+       /* RX0, TX0 */
+       RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
+};
+static const unsigned int scif0_data_mux[] = {
+       RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+       /* SCK0 */
+       RCAR_GP_PIN(1, 15),
+};
+static const unsigned int scif0_clk_mux[] = {
+       SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+       /* RTS0_N, CTS0_N */
+       RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+       RTS0_N_MARK, CTS0_N_MARK,
+};
+
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_pins[] = {
+       /* RX1, TX1 */
+       RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
+};
+static const unsigned int scif1_data_mux[] = {
+       RX1_MARK, TX1_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+       /* SCK1 */
+       RCAR_GP_PIN(0, 18),
+};
+static const unsigned int scif1_clk_mux[] = {
+       SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+       /* RTS1_N, CTS1_N */
+       RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+       RTS1_N_MARK, CTS1_N_MARK,
+};
+
+/* - SCIF1_X ------------------------------------------------------------------ */
+static const unsigned int scif1_data_x_pins[] = {
+       /* RX1_X, TX1_X */
+       RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int scif1_data_x_mux[] = {
+       RX1_X_MARK, TX1_X_MARK,
+};
+static const unsigned int scif1_clk_x_pins[] = {
+       /* SCK1_X */
+       RCAR_GP_PIN(1, 10),
+};
+static const unsigned int scif1_clk_x_mux[] = {
+       SCK1_X_MARK,
+};
+static const unsigned int scif1_ctrl_x_pins[] = {
+       /* RTS1_N_X, CTS1_N_X */
+       RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
+};
+static const unsigned int scif1_ctrl_x_mux[] = {
+       RTS1_N_X_MARK, CTS1_N_X_MARK,
+};
+
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_pins[] = {
+       /* RX3, TX3 */
+       RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
+};
+static const unsigned int scif3_data_mux[] = {
+       RX3_MARK, TX3_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+       /* SCK3 */
+       RCAR_GP_PIN(1, 4),
+};
+static const unsigned int scif3_clk_mux[] = {
+       SCK3_MARK,
+};
+static const unsigned int scif3_ctrl_pins[] = {
+       /* RTS3_N, CTS3_N */
+       RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+};
+static const unsigned int scif3_ctrl_mux[] = {
+       RTS3_N_MARK, CTS3_N_MARK,
+};
+
+/* - SCIF3_A ------------------------------------------------------------------ */
+static const unsigned int scif3_data_a_pins[] = {
+       /* RX3_A, TX3_A */
+       RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
+};
+static const unsigned int scif3_data_a_mux[] = {
+       RX3_A_MARK, TX3_A_MARK,
+};
+static const unsigned int scif3_clk_a_pins[] = {
+       /* SCK3_A */
+       RCAR_GP_PIN(1, 24),
+};
+static const unsigned int scif3_clk_a_mux[] = {
+       SCK3_A_MARK,
+};
+static const unsigned int scif3_ctrl_a_pins[] = {
+       /* RTS3_N_A, CTS3_N_A */
+       RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
+};
+static const unsigned int scif3_ctrl_a_mux[] = {
+       RTS3_N_A_MARK, CTS3_N_A_MARK,
+};
+
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_pins[] = {
+       /* RX4, TX4 */
+       RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 12),
+};
+static const unsigned int scif4_data_mux[] = {
+       RX4_MARK, TX4_MARK,
+};
+static const unsigned int scif4_clk_pins[] = {
+       /* SCK4 */
+       RCAR_GP_PIN(8, 8),
+};
+static const unsigned int scif4_clk_mux[] = {
+       SCK4_MARK,
+};
+static const unsigned int scif4_ctrl_pins[] = {
+       /* RTS4_N, CTS4_N */
+       RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 9),
+};
+static const unsigned int scif4_ctrl_mux[] = {
+       RTS4_N_MARK, CTS4_N_MARK,
+};
+
+/* - SCIF Clock ------------------------------------------------------------- */
+static const unsigned int scif_clk_pins[] = {
+       /* SCIF_CLK */
+       RCAR_GP_PIN(1, 17),
+};
+static const unsigned int scif_clk_mux[] = {
+       SCIF_CLK_MARK,
+};
+
+/* - TPU ------------------------------------------------------------------- */
+static const unsigned int tpu_to0_pins[] = {
+       /* TPU0TO0 */
+       RCAR_GP_PIN(2, 8),
+};
+static const unsigned int tpu_to0_mux[] = {
+       TPU0TO0_MARK,
+};
+static const unsigned int tpu_to1_pins[] = {
+       /* TPU0TO1 */
+       RCAR_GP_PIN(2, 7),
+};
+static const unsigned int tpu_to1_mux[] = {
+       TPU0TO1_MARK,
+};
+static const unsigned int tpu_to2_pins[] = {
+       /* TPU0TO2 */
+       RCAR_GP_PIN(2, 12),
+};
+static const unsigned int tpu_to2_mux[] = {
+       TPU0TO2_MARK,
+};
+static const unsigned int tpu_to3_pins[] = {
+       /* TPU0TO3 */
+       RCAR_GP_PIN(2, 13),
+};
+static const unsigned int tpu_to3_mux[] = {
+       TPU0TO3_MARK,
+};
+
+/* - TPU_A ------------------------------------------------------------------- */
+static const unsigned int tpu_to0_a_pins[] = {
+       /* TPU0TO0_A */
+       RCAR_GP_PIN(1, 25),
+};
+static const unsigned int tpu_to0_a_mux[] = {
+       TPU0TO0_A_MARK,
+};
+static const unsigned int tpu_to1_a_pins[] = {
+       /* TPU0TO1_A */
+       RCAR_GP_PIN(1, 26),
+};
+static const unsigned int tpu_to1_a_mux[] = {
+       TPU0TO1_A_MARK,
+};
+static const unsigned int tpu_to2_a_pins[] = {
+       /* TPU0TO2_A */
+       RCAR_GP_PIN(2, 0),
+};
+static const unsigned int tpu_to2_a_mux[] = {
+       TPU0TO2_A_MARK,
+};
+static const unsigned int tpu_to3_a_pins[] = {
+       /* TPU0TO3_A */
+       RCAR_GP_PIN(2, 1),
+};
+static const unsigned int tpu_to3_a_mux[] = {
+       TPU0TO3_A_MARK,
+};
+
+/* - TSN0 ------------------------------------------------ */
+static const unsigned int tsn0_link_pins[] = {
+       /* TSN0_LINK */
+       RCAR_GP_PIN(4, 4),
+};
+static const unsigned int tsn0_link_mux[] = {
+       TSN0_LINK_MARK,
+};
+static const unsigned int tsn0_phy_int_pins[] = {
+       /* TSN0_PHY_INT */
+       RCAR_GP_PIN(4, 3),
+};
+static const unsigned int tsn0_phy_int_mux[] = {
+       TSN0_PHY_INT_MARK,
+};
+static const unsigned int tsn0_mdio_pins[] = {
+       /* TSN0_MDC, TSN0_MDIO */
+       RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
+};
+static const unsigned int tsn0_mdio_mux[] = {
+       TSN0_MDC_MARK, TSN0_MDIO_MARK,
+};
+static const unsigned int tsn0_rgmii_pins[] = {
+       /*
+        * TSN0_TX_CTL, TSN0_TXC, TSN0_TD0, TSN0_TD1, TSN0_TD2, TSN0_TD3,
+        * TSN0_RX_CTL, TSN0_RXC, TSN0_RD0, TSN0_RD1, TSN0_RD2, TSN0_RD3,
+        */
+       RCAR_GP_PIN(4,  9), RCAR_GP_PIN(4, 12),
+       RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14),
+       RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
+       RCAR_GP_PIN(4,  7), RCAR_GP_PIN(4, 11),
+       RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 13),
+       RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
+};
+static const unsigned int tsn0_rgmii_mux[] = {
+       TSN0_TX_CTL_MARK,       TSN0_TXC_MARK,
+       TSN0_TD0_MARK,          TSN0_TD1_MARK,
+       TSN0_TD2_MARK,          TSN0_TD3_MARK,
+       TSN0_RX_CTL_MARK,       TSN0_RXC_MARK,
+       TSN0_RD0_MARK,          TSN0_RD1_MARK,
+       TSN0_RD2_MARK,          TSN0_RD3_MARK,
+};
+static const unsigned int tsn0_txcrefclk_pins[] = {
+       /* TSN0_TXCREFCLK */
+       RCAR_GP_PIN(4, 20),
+};
+static const unsigned int tsn0_txcrefclk_mux[] = {
+       TSN0_TXCREFCLK_MARK,
+};
+static const unsigned int tsn0_avtp_pps_pins[] = {
+       /* TSN0_AVTP_PPS0, TSN0_AVTP_PPS1 */
+       RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int tsn0_avtp_pps_mux[] = {
+       TSN0_AVTP_PPS0_MARK, TSN0_AVTP_PPS1_MARK,
+};
+static const unsigned int tsn0_avtp_capture_pins[] = {
+       /* TSN0_AVTP_CAPTURE */
+       RCAR_GP_PIN(4, 6),
+};
+static const unsigned int tsn0_avtp_capture_mux[] = {
+       TSN0_AVTP_CAPTURE_MARK,
+};
+static const unsigned int tsn0_avtp_match_pins[] = {
+       /* TSN0_AVTP_MATCH */
+       RCAR_GP_PIN(4, 5),
+};
+static const unsigned int tsn0_avtp_match_mux[] = {
+       TSN0_AVTP_MATCH_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+       SH_PFC_PIN_GROUP(avb0_link),
+       SH_PFC_PIN_GROUP(avb0_magic),
+       SH_PFC_PIN_GROUP(avb0_phy_int),
+       SH_PFC_PIN_GROUP(avb0_mdio),
+       SH_PFC_PIN_GROUP(avb0_rgmii),
+       SH_PFC_PIN_GROUP(avb0_txcrefclk),
+       SH_PFC_PIN_GROUP(avb0_avtp_pps),
+       SH_PFC_PIN_GROUP(avb0_avtp_capture),
+       SH_PFC_PIN_GROUP(avb0_avtp_match),
+
+       SH_PFC_PIN_GROUP(avb1_link),
+       SH_PFC_PIN_GROUP(avb1_magic),
+       SH_PFC_PIN_GROUP(avb1_phy_int),
+       SH_PFC_PIN_GROUP(avb1_mdio),
+       SH_PFC_PIN_GROUP(avb1_rgmii),
+       SH_PFC_PIN_GROUP(avb1_txcrefclk),
+       SH_PFC_PIN_GROUP(avb1_avtp_pps),
+       SH_PFC_PIN_GROUP(avb1_avtp_capture),
+       SH_PFC_PIN_GROUP(avb1_avtp_match),
+
+       SH_PFC_PIN_GROUP(avb2_link),
+       SH_PFC_PIN_GROUP(avb2_magic),
+       SH_PFC_PIN_GROUP(avb2_phy_int),
+       SH_PFC_PIN_GROUP(avb2_mdio),
+       SH_PFC_PIN_GROUP(avb2_rgmii),
+       SH_PFC_PIN_GROUP(avb2_txcrefclk),
+       SH_PFC_PIN_GROUP(avb2_avtp_pps),
+       SH_PFC_PIN_GROUP(avb2_avtp_capture),
+       SH_PFC_PIN_GROUP(avb2_avtp_match),
+
+       SH_PFC_PIN_GROUP(canfd0_data),
+       SH_PFC_PIN_GROUP(canfd1_data),
+       SH_PFC_PIN_GROUP(canfd2_data),
+       SH_PFC_PIN_GROUP(canfd3_data),
+       SH_PFC_PIN_GROUP(canfd4_data),
+       SH_PFC_PIN_GROUP(canfd5_data),          /* suffix might be updated */
+       SH_PFC_PIN_GROUP(canfd5_data_b),        /* suffix might be updated */
+       SH_PFC_PIN_GROUP(canfd6_data),
+       SH_PFC_PIN_GROUP(canfd7_data),
+       SH_PFC_PIN_GROUP(can_clk),
+
+       SH_PFC_PIN_GROUP(hscif0_data),
+       SH_PFC_PIN_GROUP(hscif0_clk),
+       SH_PFC_PIN_GROUP(hscif0_ctrl),
+       SH_PFC_PIN_GROUP(hscif1_data),          /* suffix might be updated */
+       SH_PFC_PIN_GROUP(hscif1_clk),           /* suffix might be updated */
+       SH_PFC_PIN_GROUP(hscif1_ctrl),          /* suffix might be updated */
+       SH_PFC_PIN_GROUP(hscif1_data_x),        /* suffix might be updated */
+       SH_PFC_PIN_GROUP(hscif1_clk_x),         /* suffix might be updated */
+       SH_PFC_PIN_GROUP(hscif1_ctrl_x),        /* suffix might be updated */
+       SH_PFC_PIN_GROUP(hscif2_data),
+       SH_PFC_PIN_GROUP(hscif2_clk),
+       SH_PFC_PIN_GROUP(hscif2_ctrl),
+       SH_PFC_PIN_GROUP(hscif3_data),          /* suffix might be updated */
+       SH_PFC_PIN_GROUP(hscif3_clk),           /* suffix might be updated */
+       SH_PFC_PIN_GROUP(hscif3_ctrl),          /* suffix might be updated */
+       SH_PFC_PIN_GROUP(hscif3_data_a),        /* suffix might be updated */
+       SH_PFC_PIN_GROUP(hscif3_clk_a),         /* suffix might be updated */
+       SH_PFC_PIN_GROUP(hscif3_ctrl_a),        /* suffix might be updated */
+
+       SH_PFC_PIN_GROUP(i2c0),
+       SH_PFC_PIN_GROUP(i2c1),
+       SH_PFC_PIN_GROUP(i2c2),
+       SH_PFC_PIN_GROUP(i2c3),
+       SH_PFC_PIN_GROUP(i2c4),
+       SH_PFC_PIN_GROUP(i2c5),
+
+       BUS_DATA_PIN_GROUP(mmc_data, 1),
+       BUS_DATA_PIN_GROUP(mmc_data, 4),
+       BUS_DATA_PIN_GROUP(mmc_data, 8),
+       SH_PFC_PIN_GROUP(mmc_ctrl),
+       SH_PFC_PIN_GROUP(mmc_cd),
+       SH_PFC_PIN_GROUP(mmc_wp),
+       SH_PFC_PIN_GROUP(mmc_ds),
+
+       SH_PFC_PIN_GROUP(msiof0_clk),
+       SH_PFC_PIN_GROUP(msiof0_sync),
+       SH_PFC_PIN_GROUP(msiof0_ss1),
+       SH_PFC_PIN_GROUP(msiof0_ss2),
+       SH_PFC_PIN_GROUP(msiof0_txd),
+       SH_PFC_PIN_GROUP(msiof0_rxd),
+
+       SH_PFC_PIN_GROUP(msiof1_clk),
+       SH_PFC_PIN_GROUP(msiof1_sync),
+       SH_PFC_PIN_GROUP(msiof1_ss1),
+       SH_PFC_PIN_GROUP(msiof1_ss2),
+       SH_PFC_PIN_GROUP(msiof1_txd),
+       SH_PFC_PIN_GROUP(msiof1_rxd),
+
+       SH_PFC_PIN_GROUP(msiof2_clk),
+       SH_PFC_PIN_GROUP(msiof2_sync),
+       SH_PFC_PIN_GROUP(msiof2_ss1),
+       SH_PFC_PIN_GROUP(msiof2_ss2),
+       SH_PFC_PIN_GROUP(msiof2_txd),
+       SH_PFC_PIN_GROUP(msiof2_rxd),
+
+       SH_PFC_PIN_GROUP(msiof3_clk),
+       SH_PFC_PIN_GROUP(msiof3_sync),
+       SH_PFC_PIN_GROUP(msiof3_ss1),
+       SH_PFC_PIN_GROUP(msiof3_ss2),
+       SH_PFC_PIN_GROUP(msiof3_txd),
+       SH_PFC_PIN_GROUP(msiof3_rxd),
+
+       SH_PFC_PIN_GROUP(msiof4_clk),
+       SH_PFC_PIN_GROUP(msiof4_sync),
+       SH_PFC_PIN_GROUP(msiof4_ss1),
+       SH_PFC_PIN_GROUP(msiof4_ss2),
+       SH_PFC_PIN_GROUP(msiof4_txd),
+       SH_PFC_PIN_GROUP(msiof4_rxd),
+
+       SH_PFC_PIN_GROUP(msiof5_clk),
+       SH_PFC_PIN_GROUP(msiof5_sync),
+       SH_PFC_PIN_GROUP(msiof5_ss1),
+       SH_PFC_PIN_GROUP(msiof5_ss2),
+       SH_PFC_PIN_GROUP(msiof5_txd),
+       SH_PFC_PIN_GROUP(msiof5_rxd),
+
+       SH_PFC_PIN_GROUP(pcie0_clkreq_n),
+       SH_PFC_PIN_GROUP(pcie1_clkreq_n),
+
+       SH_PFC_PIN_GROUP(pwm0_a),               /* suffix might be updated */
+       SH_PFC_PIN_GROUP(pwm1_a),
+       SH_PFC_PIN_GROUP(pwm1_b),
+       SH_PFC_PIN_GROUP(pwm2_b),               /* suffix might be updated */
+       SH_PFC_PIN_GROUP(pwm3_a),
+       SH_PFC_PIN_GROUP(pwm3_b),
+       SH_PFC_PIN_GROUP(pwm4),
+       SH_PFC_PIN_GROUP(pwm5),
+       SH_PFC_PIN_GROUP(pwm6),
+       SH_PFC_PIN_GROUP(pwm7),
+       SH_PFC_PIN_GROUP(pwm8_a),               /* suffix might be updated */
+       SH_PFC_PIN_GROUP(pwm9_a),               /* suffix might be updated */
+
+       SH_PFC_PIN_GROUP(qspi0_ctrl),
+       BUS_DATA_PIN_GROUP(qspi0_data, 2),
+       BUS_DATA_PIN_GROUP(qspi0_data, 4),
+       SH_PFC_PIN_GROUP(qspi1_ctrl),
+       BUS_DATA_PIN_GROUP(qspi1_data, 2),
+       BUS_DATA_PIN_GROUP(qspi1_data, 4),
+
+       SH_PFC_PIN_GROUP(scif0_data),
+       SH_PFC_PIN_GROUP(scif0_clk),
+       SH_PFC_PIN_GROUP(scif0_ctrl),
+       SH_PFC_PIN_GROUP(scif1_data),           /* suffix might be updated */
+       SH_PFC_PIN_GROUP(scif1_clk),            /* suffix might be updated */
+       SH_PFC_PIN_GROUP(scif1_ctrl),           /* suffix might be updated */
+       SH_PFC_PIN_GROUP(scif1_data_x),         /* suffix might be updated */
+       SH_PFC_PIN_GROUP(scif1_clk_x),          /* suffix might be updated */
+       SH_PFC_PIN_GROUP(scif1_ctrl_x),         /* suffix might be updated */
+       SH_PFC_PIN_GROUP(scif3_data),           /* suffix might be updated */
+       SH_PFC_PIN_GROUP(scif3_clk),            /* suffix might be updated */
+       SH_PFC_PIN_GROUP(scif3_ctrl),           /* suffix might be updated */
+       SH_PFC_PIN_GROUP(scif3_data_a),         /* suffix might be updated */
+       SH_PFC_PIN_GROUP(scif3_clk_a),          /* suffix might be updated */
+       SH_PFC_PIN_GROUP(scif3_ctrl_a),         /* suffix might be updated */
+       SH_PFC_PIN_GROUP(scif4_data),
+       SH_PFC_PIN_GROUP(scif4_clk),
+       SH_PFC_PIN_GROUP(scif4_ctrl),
+       SH_PFC_PIN_GROUP(scif_clk),
+
+       SH_PFC_PIN_GROUP(tpu_to0),              /* suffix might be updated */
+       SH_PFC_PIN_GROUP(tpu_to0_a),            /* suffix might be updated */
+       SH_PFC_PIN_GROUP(tpu_to1),              /* suffix might be updated */
+       SH_PFC_PIN_GROUP(tpu_to1_a),            /* suffix might be updated */
+       SH_PFC_PIN_GROUP(tpu_to2),              /* suffix might be updated */
+       SH_PFC_PIN_GROUP(tpu_to2_a),            /* suffix might be updated */
+       SH_PFC_PIN_GROUP(tpu_to3),              /* suffix might be updated */
+       SH_PFC_PIN_GROUP(tpu_to3_a),            /* suffix might be updated */
+
+       SH_PFC_PIN_GROUP(tsn0_link),
+       SH_PFC_PIN_GROUP(tsn0_phy_int),
+       SH_PFC_PIN_GROUP(tsn0_mdio),
+       SH_PFC_PIN_GROUP(tsn0_rgmii),
+       SH_PFC_PIN_GROUP(tsn0_txcrefclk),
+       SH_PFC_PIN_GROUP(tsn0_avtp_pps),
+       SH_PFC_PIN_GROUP(tsn0_avtp_capture),
+       SH_PFC_PIN_GROUP(tsn0_avtp_match),
+};
+
+static const char * const avb0_groups[] = {
+       "avb0_link",
+       "avb0_magic",
+       "avb0_phy_int",
+       "avb0_mdio",
+       "avb0_rgmii",
+       "avb0_txcrefclk",
+       "avb0_avtp_pps",
+       "avb0_avtp_capture",
+       "avb0_avtp_match",
+};
+
+static const char * const avb1_groups[] = {
+       "avb1_link",
+       "avb1_magic",
+       "avb1_phy_int",
+       "avb1_mdio",
+       "avb1_rgmii",
+       "avb1_txcrefclk",
+       "avb1_avtp_pps",
+       "avb1_avtp_capture",
+       "avb1_avtp_match",
+};
+
+static const char * const avb2_groups[] = {
+       "avb2_link",
+       "avb2_magic",
+       "avb2_phy_int",
+       "avb2_mdio",
+       "avb2_rgmii",
+       "avb2_txcrefclk",
+       "avb2_avtp_pps",
+       "avb2_avtp_capture",
+       "avb2_avtp_match",
+};
+
+static const char * const canfd0_groups[] = {
+       "canfd0_data",
+};
+
+static const char * const canfd1_groups[] = {
+       "canfd1_data",
+};
+
+static const char * const canfd2_groups[] = {
+       "canfd2_data",
+};
+
+static const char * const canfd3_groups[] = {
+       "canfd3_data",
+};
+
+static const char * const canfd4_groups[] = {
+       "canfd4_data",
+};
+
+static const char * const canfd5_groups[] = {
+       /* suffix might be updated */
+       "canfd5_data",
+       "canfd5_data_b",
+};
+
+static const char * const canfd6_groups[] = {
+       "canfd6_data",
+};
+
+static const char * const canfd7_groups[] = {
+       "canfd7_data",
+};
+
+static const char * const can_clk_groups[] = {
+       "can_clk",
+};
+
+static const char * const hscif0_groups[] = {
+       "hscif0_data",
+       "hscif0_clk",
+       "hscif0_ctrl",
+};
+
+static const char * const hscif1_groups[] = {
+       /* suffix might be updated */
+       "hscif1_data",
+       "hscif1_clk",
+       "hscif1_ctrl",
+       "hscif1_data_x",
+       "hscif1_clk_x",
+       "hscif1_ctrl_x",
+};
+
+static const char * const hscif2_groups[] = {
+       "hscif2_data",
+       "hscif2_clk",
+       "hscif2_ctrl",
+};
+
+static const char * const hscif3_groups[] = {
+       /* suffix might be updated */
+       "hscif3_data",
+       "hscif3_clk",
+       "hscif3_ctrl",
+       "hscif3_data_a",
+       "hscif3_clk_a",
+       "hscif3_ctrl_a",
+};
+
+static const char * const i2c0_groups[] = {
+       "i2c0",
+};
+
+static const char * const i2c1_groups[] = {
+       "i2c1",
+};
+
+static const char * const i2c2_groups[] = {
+       "i2c2",
+};
+
+static const char * const i2c3_groups[] = {
+       "i2c3",
+};
+
+static const char * const i2c4_groups[] = {
+       "i2c4",
+};
+
+static const char * const i2c5_groups[] = {
+       "i2c5",
+};
+
+static const char * const mmc_groups[] = {
+       "mmc_data1",
+       "mmc_data4",
+       "mmc_data8",
+       "mmc_ctrl",
+       "mmc_cd",
+       "mmc_wp",
+       "mmc_ds",
+};
+
+static const char * const msiof0_groups[] = {
+       "msiof0_clk",
+       "msiof0_sync",
+       "msiof0_ss1",
+       "msiof0_ss2",
+       "msiof0_txd",
+       "msiof0_rxd",
+};
+
+static const char * const msiof1_groups[] = {
+       "msiof1_clk",
+       "msiof1_sync",
+       "msiof1_ss1",
+       "msiof1_ss2",
+       "msiof1_txd",
+       "msiof1_rxd",
+};
+
+static const char * const msiof2_groups[] = {
+       "msiof2_clk",
+       "msiof2_sync",
+       "msiof2_ss1",
+       "msiof2_ss2",
+       "msiof2_txd",
+       "msiof2_rxd",
+};
+
+static const char * const msiof3_groups[] = {
+       "msiof3_clk",
+       "msiof3_sync",
+       "msiof3_ss1",
+       "msiof3_ss2",
+       "msiof3_txd",
+       "msiof3_rxd",
+};
+
+static const char * const msiof4_groups[] = {
+       "msiof4_clk",
+       "msiof4_sync",
+       "msiof4_ss1",
+       "msiof4_ss2",
+       "msiof4_txd",
+       "msiof4_rxd",
+};
+
+static const char * const msiof5_groups[] = {
+       "msiof5_clk",
+       "msiof5_sync",
+       "msiof5_ss1",
+       "msiof5_ss2",
+       "msiof5_txd",
+       "msiof5_rxd",
+};
+
+static const char * const pcie_groups[] = {
+       "pcie0_clkreq_n",
+       "pcie1_clkreq_n",
+};
+
+static const char * const pwm0_groups[] = {
+       /* suffix might be updated */
+       "pwm0_a",
+};
+
+static const char * const pwm1_groups[] = {
+       "pwm1_a",
+       "pwm1_b",
+};
+
+static const char * const pwm2_groups[] = {
+       /* suffix might be updated */
+       "pwm2_b",
+};
+
+static const char * const pwm3_groups[] = {
+       "pwm3_a",
+       "pwm3_b",
+};
+
+static const char * const pwm4_groups[] = {
+       "pwm4",
+};
+
+static const char * const pwm5_groups[] = {
+       "pwm5",
+};
+
+static const char * const pwm6_groups[] = {
+       "pwm6",
+};
+
+static const char * const pwm7_groups[] = {
+       "pwm7",
+};
+
+static const char * const pwm8_groups[] = {
+       /* suffix might be updated */
+       "pwm8_a",
+};
+
+static const char * const pwm9_groups[] = {
+       /* suffix might be updated */
+       "pwm9_a",
+};
+
+static const char * const qspi0_groups[] = {
+       "qspi0_ctrl",
+       "qspi0_data2",
+       "qspi0_data4",
+};
+
+static const char * const qspi1_groups[] = {
+       "qspi1_ctrl",
+       "qspi1_data2",
+       "qspi1_data4",
+};
+
+static const char * const scif0_groups[] = {
+       "scif0_data",
+       "scif0_clk",
+       "scif0_ctrl",
+};
+
+static const char * const scif1_groups[] = {
+       /* suffix might be updated */
+       "scif1_data",
+       "scif1_clk",
+       "scif1_ctrl",
+       "scif1_data_x",
+       "scif1_clk_x",
+       "scif1_ctrl_x",
+};
+
+static const char * const scif3_groups[] = {
+       /* suffix might be updated */
+       "scif3_data",
+       "scif3_clk",
+       "scif3_ctrl",
+       "scif3_data_a",
+       "scif3_clk_a",
+       "scif3_ctrl_a",
+};
+
+static const char * const scif4_groups[] = {
+       "scif4_data",
+       "scif4_clk",
+       "scif4_ctrl",
+};
+
+static const char * const scif_clk_groups[] = {
+       "scif_clk",
+};
+
+static const char * const tpu_groups[] = {
+       /* suffix might be updated */
+       "tpu_to0",
+       "tpu_to0_a",
+       "tpu_to1",
+       "tpu_to1_a",
+       "tpu_to2",
+       "tpu_to2_a",
+       "tpu_to3",
+       "tpu_to3_a",
+};
+
+static const char * const tsn0_groups[] = {
+       "tsn0_link",
+       "tsn0_phy_int",
+       "tsn0_mdio",
+       "tsn0_rgmii",
+       "tsn0_txcrefclk",
+       "tsn0_avtp_pps",
+       "tsn0_avtp_capture",
+       "tsn0_avtp_match",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+       SH_PFC_FUNCTION(avb0),
+       SH_PFC_FUNCTION(avb1),
+       SH_PFC_FUNCTION(avb2),
+
+       SH_PFC_FUNCTION(canfd0),
+       SH_PFC_FUNCTION(canfd1),
+       SH_PFC_FUNCTION(canfd2),
+       SH_PFC_FUNCTION(canfd3),
+       SH_PFC_FUNCTION(canfd4),
+       SH_PFC_FUNCTION(canfd5),
+       SH_PFC_FUNCTION(canfd6),
+       SH_PFC_FUNCTION(canfd7),
+       SH_PFC_FUNCTION(can_clk),
+
+       SH_PFC_FUNCTION(hscif0),
+       SH_PFC_FUNCTION(hscif1),
+       SH_PFC_FUNCTION(hscif2),
+       SH_PFC_FUNCTION(hscif3),
+
+       SH_PFC_FUNCTION(i2c0),
+       SH_PFC_FUNCTION(i2c1),
+       SH_PFC_FUNCTION(i2c2),
+       SH_PFC_FUNCTION(i2c3),
+       SH_PFC_FUNCTION(i2c4),
+       SH_PFC_FUNCTION(i2c5),
+
+       SH_PFC_FUNCTION(mmc),
+
+       SH_PFC_FUNCTION(msiof0),
+       SH_PFC_FUNCTION(msiof1),
+       SH_PFC_FUNCTION(msiof2),
+       SH_PFC_FUNCTION(msiof3),
+       SH_PFC_FUNCTION(msiof4),
+       SH_PFC_FUNCTION(msiof5),
+
+       SH_PFC_FUNCTION(pcie),
+
+       SH_PFC_FUNCTION(pwm0),
+       SH_PFC_FUNCTION(pwm1),
+       SH_PFC_FUNCTION(pwm2),
+       SH_PFC_FUNCTION(pwm3),
+       SH_PFC_FUNCTION(pwm4),
+       SH_PFC_FUNCTION(pwm5),
+       SH_PFC_FUNCTION(pwm6),
+       SH_PFC_FUNCTION(pwm7),
+       SH_PFC_FUNCTION(pwm8),
+       SH_PFC_FUNCTION(pwm9),
+
+       SH_PFC_FUNCTION(qspi0),
+       SH_PFC_FUNCTION(qspi1),
+
+       SH_PFC_FUNCTION(scif0),
+       SH_PFC_FUNCTION(scif1),
+       SH_PFC_FUNCTION(scif3),
+       SH_PFC_FUNCTION(scif4),
+       SH_PFC_FUNCTION(scif_clk),
+
+       SH_PFC_FUNCTION(tpu),
+
+       SH_PFC_FUNCTION(tsn0),
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+#define F_(x, y)       FN_##y
+#define FM(x)          FN_##x
+       { PINMUX_CFG_REG_VAR("GPSR0", 0xE6050040, 32,
+                            GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                                  1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+                            GROUP(
+               /* GP0_31_19 RESERVED */
+               GP_0_18_FN,     GPSR0_18,
+               GP_0_17_FN,     GPSR0_17,
+               GP_0_16_FN,     GPSR0_16,
+               GP_0_15_FN,     GPSR0_15,
+               GP_0_14_FN,     GPSR0_14,
+               GP_0_13_FN,     GPSR0_13,
+               GP_0_12_FN,     GPSR0_12,
+               GP_0_11_FN,     GPSR0_11,
+               GP_0_10_FN,     GPSR0_10,
+               GP_0_9_FN,      GPSR0_9,
+               GP_0_8_FN,      GPSR0_8,
+               GP_0_7_FN,      GPSR0_7,
+               GP_0_6_FN,      GPSR0_6,
+               GP_0_5_FN,      GPSR0_5,
+               GP_0_4_FN,      GPSR0_4,
+               GP_0_3_FN,      GPSR0_3,
+               GP_0_2_FN,      GPSR0_2,
+               GP_0_1_FN,      GPSR0_1,
+               GP_0_0_FN,      GPSR0_0, ))
+       },
+       { PINMUX_CFG_REG("GPSR1", 0xE6050840, 32, 1, GROUP(
+               0, 0,
+               0, 0,
+               0, 0,
+               GP_1_28_FN,     GPSR1_28,
+               GP_1_27_FN,     GPSR1_27,
+               GP_1_26_FN,     GPSR1_26,
+               GP_1_25_FN,     GPSR1_25,
+               GP_1_24_FN,     GPSR1_24,
+               GP_1_23_FN,     GPSR1_23,
+               GP_1_22_FN,     GPSR1_22,
+               GP_1_21_FN,     GPSR1_21,
+               GP_1_20_FN,     GPSR1_20,
+               GP_1_19_FN,     GPSR1_19,
+               GP_1_18_FN,     GPSR1_18,
+               GP_1_17_FN,     GPSR1_17,
+               GP_1_16_FN,     GPSR1_16,
+               GP_1_15_FN,     GPSR1_15,
+               GP_1_14_FN,     GPSR1_14,
+               GP_1_13_FN,     GPSR1_13,
+               GP_1_12_FN,     GPSR1_12,
+               GP_1_11_FN,     GPSR1_11,
+               GP_1_10_FN,     GPSR1_10,
+               GP_1_9_FN,      GPSR1_9,
+               GP_1_8_FN,      GPSR1_8,
+               GP_1_7_FN,      GPSR1_7,
+               GP_1_6_FN,      GPSR1_6,
+               GP_1_5_FN,      GPSR1_5,
+               GP_1_4_FN,      GPSR1_4,
+               GP_1_3_FN,      GPSR1_3,
+               GP_1_2_FN,      GPSR1_2,
+               GP_1_1_FN,      GPSR1_1,
+               GP_1_0_FN,      GPSR1_0, ))
+       },
+       { PINMUX_CFG_REG_VAR("GPSR2", 0xE6058040, 32,
+                            GROUP(-12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                                  1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+                            GROUP(
+               /* GP2_31_20 RESERVED */
+               GP_2_19_FN,     GPSR2_19,
+               GP_2_18_FN,     GPSR2_18,
+               GP_2_17_FN,     GPSR2_17,
+               GP_2_16_FN,     GPSR2_16,
+               GP_2_15_FN,     GPSR2_15,
+               GP_2_14_FN,     GPSR2_14,
+               GP_2_13_FN,     GPSR2_13,
+               GP_2_12_FN,     GPSR2_12,
+               GP_2_11_FN,     GPSR2_11,
+               GP_2_10_FN,     GPSR2_10,
+               GP_2_9_FN,      GPSR2_9,
+               GP_2_8_FN,      GPSR2_8,
+               GP_2_7_FN,      GPSR2_7,
+               GP_2_6_FN,      GPSR2_6,
+               GP_2_5_FN,      GPSR2_5,
+               GP_2_4_FN,      GPSR2_4,
+               GP_2_3_FN,      GPSR2_3,
+               GP_2_2_FN,      GPSR2_2,
+               GP_2_1_FN,      GPSR2_1,
+               GP_2_0_FN,      GPSR2_0, ))
+       },
+       { PINMUX_CFG_REG("GPSR3", 0xE6058840, 32, 1, GROUP(
+               0, 0,
+               0, 0,
+               GP_3_29_FN,     GPSR3_29,
+               GP_3_28_FN,     GPSR3_28,
+               GP_3_27_FN,     GPSR3_27,
+               GP_3_26_FN,     GPSR3_26,
+               GP_3_25_FN,     GPSR3_25,
+               GP_3_24_FN,     GPSR3_24,
+               GP_3_23_FN,     GPSR3_23,
+               GP_3_22_FN,     GPSR3_22,
+               GP_3_21_FN,     GPSR3_21,
+               GP_3_20_FN,     GPSR3_20,
+               GP_3_19_FN,     GPSR3_19,
+               GP_3_18_FN,     GPSR3_18,
+               GP_3_17_FN,     GPSR3_17,
+               GP_3_16_FN,     GPSR3_16,
+               GP_3_15_FN,     GPSR3_15,
+               GP_3_14_FN,     GPSR3_14,
+               GP_3_13_FN,     GPSR3_13,
+               GP_3_12_FN,     GPSR3_12,
+               GP_3_11_FN,     GPSR3_11,
+               GP_3_10_FN,     GPSR3_10,
+               GP_3_9_FN,      GPSR3_9,
+               GP_3_8_FN,      GPSR3_8,
+               GP_3_7_FN,      GPSR3_7,
+               GP_3_6_FN,      GPSR3_6,
+               GP_3_5_FN,      GPSR3_5,
+               GP_3_4_FN,      GPSR3_4,
+               GP_3_3_FN,      GPSR3_3,
+               GP_3_2_FN,      GPSR3_2,
+               GP_3_1_FN,      GPSR3_1,
+               GP_3_0_FN,      GPSR3_0, ))
+       },
+       { PINMUX_CFG_REG("GPSR4", 0xE6060040, 32, 1, GROUP(
+               0, 0,
+               0, 0,
+               0, 0,
+               0, 0,
+               0, 0,
+               0, 0,
+               0, 0,
+               GP_4_24_FN,     GPSR4_24,
+               GP_4_23_FN,     GPSR4_23,
+               GP_4_22_FN,     GPSR4_22,
+               GP_4_21_FN,     GPSR4_21,
+               GP_4_20_FN,     GPSR4_20,
+               GP_4_19_FN,     GPSR4_19,
+               GP_4_18_FN,     GPSR4_18,
+               GP_4_17_FN,     GPSR4_17,
+               GP_4_16_FN,     GPSR4_16,
+               GP_4_15_FN,     GPSR4_15,
+               GP_4_14_FN,     GPSR4_14,
+               GP_4_13_FN,     GPSR4_13,
+               GP_4_12_FN,     GPSR4_12,
+               GP_4_11_FN,     GPSR4_11,
+               GP_4_10_FN,     GPSR4_10,
+               GP_4_9_FN,      GPSR4_9,
+               GP_4_8_FN,      GPSR4_8,
+               GP_4_7_FN,      GPSR4_7,
+               GP_4_6_FN,      GPSR4_6,
+               GP_4_5_FN,      GPSR4_5,
+               GP_4_4_FN,      GPSR4_4,
+               GP_4_3_FN,      GPSR4_3,
+               GP_4_2_FN,      GPSR4_2,
+               GP_4_1_FN,      GPSR4_1,
+               GP_4_0_FN,      GPSR4_0, ))
+       },
+       { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060840, 32,
+                            GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                                  1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+                            GROUP(
+               /* GP5_31_21 RESERVED */
+               GP_5_20_FN,     GPSR5_20,
+               GP_5_19_FN,     GPSR5_19,
+               GP_5_18_FN,     GPSR5_18,
+               GP_5_17_FN,     GPSR5_17,
+               GP_5_16_FN,     GPSR5_16,
+               GP_5_15_FN,     GPSR5_15,
+               GP_5_14_FN,     GPSR5_14,
+               GP_5_13_FN,     GPSR5_13,
+               GP_5_12_FN,     GPSR5_12,
+               GP_5_11_FN,     GPSR5_11,
+               GP_5_10_FN,     GPSR5_10,
+               GP_5_9_FN,      GPSR5_9,
+               GP_5_8_FN,      GPSR5_8,
+               GP_5_7_FN,      GPSR5_7,
+               GP_5_6_FN,      GPSR5_6,
+               GP_5_5_FN,      GPSR5_5,
+               GP_5_4_FN,      GPSR5_4,
+               GP_5_3_FN,      GPSR5_3,
+               GP_5_2_FN,      GPSR5_2,
+               GP_5_1_FN,      GPSR5_1,
+               GP_5_0_FN,      GPSR5_0, ))
+       },
+       { PINMUX_CFG_REG_VAR("GPSR6", 0xE6061040, 32,
+                            GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                                  1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+                            GROUP(
+               /* GP6_31_21 RESERVED */
+               GP_6_20_FN,     GPSR6_20,
+               GP_6_19_FN,     GPSR6_19,
+               GP_6_18_FN,     GPSR6_18,
+               GP_6_17_FN,     GPSR6_17,
+               GP_6_16_FN,     GPSR6_16,
+               GP_6_15_FN,     GPSR6_15,
+               GP_6_14_FN,     GPSR6_14,
+               GP_6_13_FN,     GPSR6_13,
+               GP_6_12_FN,     GPSR6_12,
+               GP_6_11_FN,     GPSR6_11,
+               GP_6_10_FN,     GPSR6_10,
+               GP_6_9_FN,      GPSR6_9,
+               GP_6_8_FN,      GPSR6_8,
+               GP_6_7_FN,      GPSR6_7,
+               GP_6_6_FN,      GPSR6_6,
+               GP_6_5_FN,      GPSR6_5,
+               GP_6_4_FN,      GPSR6_4,
+               GP_6_3_FN,      GPSR6_3,
+               GP_6_2_FN,      GPSR6_2,
+               GP_6_1_FN,      GPSR6_1,
+               GP_6_0_FN,      GPSR6_0, ))
+       },
+       { PINMUX_CFG_REG_VAR("GPSR7", 0xE6061840, 32,
+                            GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                                  1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+                            GROUP(
+               /* GP7_31_21 RESERVED */
+               GP_7_20_FN,     GPSR7_20,
+               GP_7_19_FN,     GPSR7_19,
+               GP_7_18_FN,     GPSR7_18,
+               GP_7_17_FN,     GPSR7_17,
+               GP_7_16_FN,     GPSR7_16,
+               GP_7_15_FN,     GPSR7_15,
+               GP_7_14_FN,     GPSR7_14,
+               GP_7_13_FN,     GPSR7_13,
+               GP_7_12_FN,     GPSR7_12,
+               GP_7_11_FN,     GPSR7_11,
+               GP_7_10_FN,     GPSR7_10,
+               GP_7_9_FN,      GPSR7_9,
+               GP_7_8_FN,      GPSR7_8,
+               GP_7_7_FN,      GPSR7_7,
+               GP_7_6_FN,      GPSR7_6,
+               GP_7_5_FN,      GPSR7_5,
+               GP_7_4_FN,      GPSR7_4,
+               GP_7_3_FN,      GPSR7_3,
+               GP_7_2_FN,      GPSR7_2,
+               GP_7_1_FN,      GPSR7_1,
+               GP_7_0_FN,      GPSR7_0, ))
+       },
+       { PINMUX_CFG_REG_VAR("GPSR8", 0xE6068040, 32,
+                            GROUP(-18, 1, 1, 1, 1,
+                                  1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+                            GROUP(
+               /* GP8_31_14 RESERVED */
+               GP_8_13_FN,     GPSR8_13,
+               GP_8_12_FN,     GPSR8_12,
+               GP_8_11_FN,     GPSR8_11,
+               GP_8_10_FN,     GPSR8_10,
+               GP_8_9_FN,      GPSR8_9,
+               GP_8_8_FN,      GPSR8_8,
+               GP_8_7_FN,      GPSR8_7,
+               GP_8_6_FN,      GPSR8_6,
+               GP_8_5_FN,      GPSR8_5,
+               GP_8_4_FN,      GPSR8_4,
+               GP_8_3_FN,      GPSR8_3,
+               GP_8_2_FN,      GPSR8_2,
+               GP_8_1_FN,      GPSR8_1,
+               GP_8_0_FN,      GPSR8_0, ))
+       },
+#undef F_
+#undef FM
+
+#define F_(x, y)       x,
+#define FM(x)          FN_##x,
+       { PINMUX_CFG_REG("IP0SR0", 0xE6050060, 32, 4, GROUP(
+               IP0SR0_31_28
+               IP0SR0_27_24
+               IP0SR0_23_20
+               IP0SR0_19_16
+               IP0SR0_15_12
+               IP0SR0_11_8
+               IP0SR0_7_4
+               IP0SR0_3_0))
+       },
+       { PINMUX_CFG_REG("IP1SR0", 0xE6050064, 32, 4, GROUP(
+               IP1SR0_31_28
+               IP1SR0_27_24
+               IP1SR0_23_20
+               IP1SR0_19_16
+               IP1SR0_15_12
+               IP1SR0_11_8
+               IP1SR0_7_4
+               IP1SR0_3_0))
+       },
+       { PINMUX_CFG_REG_VAR("IP2SR0", 0xE6050068, 32,
+                            GROUP(-20, 4, 4, 4),
+                            GROUP(
+               /* IP2SR0_31_12 RESERVED */
+               IP2SR0_11_8
+               IP2SR0_7_4
+               IP2SR0_3_0))
+       },
+       { PINMUX_CFG_REG("IP0SR1", 0xE6050860, 32, 4, GROUP(
+               IP0SR1_31_28
+               IP0SR1_27_24
+               IP0SR1_23_20
+               IP0SR1_19_16
+               IP0SR1_15_12
+               IP0SR1_11_8
+               IP0SR1_7_4
+               IP0SR1_3_0))
+       },
+       { PINMUX_CFG_REG("IP1SR1", 0xE6050864, 32, 4, GROUP(
+               IP1SR1_31_28
+               IP1SR1_27_24
+               IP1SR1_23_20
+               IP1SR1_19_16
+               IP1SR1_15_12
+               IP1SR1_11_8
+               IP1SR1_7_4
+               IP1SR1_3_0))
+       },
+       { PINMUX_CFG_REG("IP2SR1", 0xE6050868, 32, 4, GROUP(
+               IP2SR1_31_28
+               IP2SR1_27_24
+               IP2SR1_23_20
+               IP2SR1_19_16
+               IP2SR1_15_12
+               IP2SR1_11_8
+               IP2SR1_7_4
+               IP2SR1_3_0))
+       },
+       { PINMUX_CFG_REG_VAR("IP3SR1", 0xE605086C, 32,
+                            GROUP(-12, 4, 4, 4, 4, 4),
+                            GROUP(
+               /* IP3SR1_31_20 RESERVED */
+               IP3SR1_19_16
+               IP3SR1_15_12
+               IP3SR1_11_8
+               IP3SR1_7_4
+               IP3SR1_3_0))
+       },
+       { PINMUX_CFG_REG("IP0SR2", 0xE6058060, 32, 4, GROUP(
+               IP0SR2_31_28
+               IP0SR2_27_24
+               IP0SR2_23_20
+               IP0SR2_19_16
+               IP0SR2_15_12
+               IP0SR2_11_8
+               IP0SR2_7_4
+               IP0SR2_3_0))
+       },
+       { PINMUX_CFG_REG("IP1SR2", 0xE6058064, 32, 4, GROUP(
+               IP1SR2_31_28
+               IP1SR2_27_24
+               IP1SR2_23_20
+               IP1SR2_19_16
+               IP1SR2_15_12
+               IP1SR2_11_8
+               IP1SR2_7_4
+               IP1SR2_3_0))
+       },
+       { PINMUX_CFG_REG_VAR("IP2SR2", 0xE6058068, 32,
+                            GROUP(-16, 4, 4, 4, 4),
+                            GROUP(
+               /* IP2SR2_31_16 RESERVED */
+               IP2SR2_15_12
+               IP2SR2_11_8
+               IP2SR2_7_4
+               IP2SR2_3_0))
+       },
+       { PINMUX_CFG_REG("IP0SR3", 0xE6058860, 32, 4, GROUP(
+               IP0SR3_31_28
+               IP0SR3_27_24
+               IP0SR3_23_20
+               IP0SR3_19_16
+               IP0SR3_15_12
+               IP0SR3_11_8
+               IP0SR3_7_4
+               IP0SR3_3_0))
+       },
+       { PINMUX_CFG_REG("IP1SR3", 0xE6058864, 32, 4, GROUP(
+               IP1SR3_31_28
+               IP1SR3_27_24
+               IP1SR3_23_20
+               IP1SR3_19_16
+               IP1SR3_15_12
+               IP1SR3_11_8
+               IP1SR3_7_4
+               IP1SR3_3_0))
+       },
+       { PINMUX_CFG_REG("IP2SR3", 0xE6058868, 32, 4, GROUP(
+               IP2SR3_31_28
+               IP2SR3_27_24
+               IP2SR3_23_20
+               IP2SR3_19_16
+               IP2SR3_15_12
+               IP2SR3_11_8
+               IP2SR3_7_4
+               IP2SR3_3_0))
+       },
+       { PINMUX_CFG_REG_VAR("IP3SR3", 0xE605886C, 32,
+                            GROUP(-8, 4, 4, 4, 4, 4, 4),
+                            GROUP(
+               /* IP3SR3_31_24 RESERVED */
+               IP3SR3_23_20
+               IP3SR3_19_16
+               IP3SR3_15_12
+               IP3SR3_11_8
+               IP3SR3_7_4
+               IP3SR3_3_0))
+       },
+       { PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP(
+               IP0SR6_31_28
+               IP0SR6_27_24
+               IP0SR6_23_20
+               IP0SR6_19_16
+               IP0SR6_15_12
+               IP0SR6_11_8
+               IP0SR6_7_4
+               IP0SR6_3_0))
+       },
+       { PINMUX_CFG_REG("IP1SR6", 0xE6061064, 32, 4, GROUP(
+               IP1SR6_31_28
+               IP1SR6_27_24
+               IP1SR6_23_20
+               IP1SR6_19_16
+               IP1SR6_15_12
+               IP1SR6_11_8
+               IP1SR6_7_4
+               IP1SR6_3_0))
+       },
+       { PINMUX_CFG_REG_VAR("IP2SR6", 0xE6061068, 32,
+                            GROUP(-12, 4, 4, 4, 4, 4),
+                            GROUP(
+               /* IP2SR6_31_20 RESERVED */
+               IP2SR6_19_16
+               IP2SR6_15_12
+               IP2SR6_11_8
+               IP2SR6_7_4
+               IP2SR6_3_0))
+       },
+       { PINMUX_CFG_REG("IP0SR7", 0xE6061860, 32, 4, GROUP(
+               IP0SR7_31_28
+               IP0SR7_27_24
+               IP0SR7_23_20
+               IP0SR7_19_16
+               IP0SR7_15_12
+               IP0SR7_11_8
+               IP0SR7_7_4
+               IP0SR7_3_0))
+       },
+       { PINMUX_CFG_REG("IP1SR7", 0xE6061864, 32, 4, GROUP(
+               IP1SR7_31_28
+               IP1SR7_27_24
+               IP1SR7_23_20
+               IP1SR7_19_16
+               IP1SR7_15_12
+               IP1SR7_11_8
+               IP1SR7_7_4
+               IP1SR7_3_0))
+       },
+       { PINMUX_CFG_REG_VAR("IP2SR7", 0xE6061868, 32,
+                            GROUP(-12, 4, 4, 4, 4, 4),
+                            GROUP(
+               /* IP2SR7_31_20 RESERVED */
+               IP2SR7_19_16
+               IP2SR7_15_12
+               IP2SR7_11_8
+               IP2SR7_7_4
+               IP2SR7_3_0))
+       },
+       { PINMUX_CFG_REG("IP0SR8", 0xE6068060, 32, 4, GROUP(
+               IP0SR8_31_28
+               IP0SR8_27_24
+               IP0SR8_23_20
+               IP0SR8_19_16
+               IP0SR8_15_12
+               IP0SR8_11_8
+               IP0SR8_7_4
+               IP0SR8_3_0))
+       },
+       { PINMUX_CFG_REG_VAR("IP1SR8", 0xE6068064, 32,
+                            GROUP(-8, 4, 4, 4, 4, 4, 4),
+                            GROUP(
+               /* IP1SR8_31_24 RESERVED */
+               IP1SR8_23_20
+               IP1SR8_19_16
+               IP1SR8_15_12
+               IP1SR8_11_8
+               IP1SR8_7_4
+               IP1SR8_3_0))
+       },
+#undef F_
+#undef FM
+
+#define F_(x, y)       x,
+#define FM(x)          FN_##x,
+       { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE6060100, 32,
+                            GROUP(-12, 1, 1, -2, 1, 1, -1, 1, -2, 1, 1, -2, 1,
+                                  -2, 1, 1, -1),
+                            GROUP(
+               /* RESERVED 31-20 */
+               MOD_SEL4_19
+               MOD_SEL4_18
+               /* RESERVED 17-16 */
+               MOD_SEL4_15
+               MOD_SEL4_14
+               /* RESERVED 13 */
+               MOD_SEL4_12
+               /* RESERVED 11-10 */
+               MOD_SEL4_9
+               MOD_SEL4_8
+               /* RESERVED 7-6 */
+               MOD_SEL4_5
+               /* RESERVED 4-3 */
+               MOD_SEL4_2
+               MOD_SEL4_1
+               /* RESERVED 0 */
+               ))
+       },
+       { PINMUX_CFG_REG_VAR("MOD_SEL5", 0xE6060900, 32,
+                            GROUP(-12, 1, -2, 1, 1, -2, 1, 1, -2, 1, -1,
+                                  1, 1, -2, 1, -1, 1),
+                            GROUP(
+               /* RESERVED 31-20 */
+               MOD_SEL5_19
+               /* RESERVED 18-17 */
+               MOD_SEL5_16
+               MOD_SEL5_15
+               /* RESERVED 14-13 */
+               MOD_SEL5_12
+               MOD_SEL5_11
+               /* RESERVED 10-9 */
+               MOD_SEL5_8
+               /* RESERVED 7 */
+               MOD_SEL5_6
+               MOD_SEL5_5
+               /* RESERVED 4-3 */
+               MOD_SEL5_2
+               /* RESERVED 1 */
+               MOD_SEL5_0))
+       },
+       { PINMUX_CFG_REG_VAR("MOD_SEL6", 0xE6061100, 32,
+                            GROUP(-13, 1, -1, 1, -2, 1, 1,
+                                  -1, 1, -2, 1, 1, 1, -2, 1, 1, -1),
+                            GROUP(
+               /* RESERVED 31-19 */
+               MOD_SEL6_18
+               /* RESERVED 17 */
+               MOD_SEL6_16
+               /* RESERVED 15-14 */
+               MOD_SEL6_13
+               MOD_SEL6_12
+               /* RESERVED 11 */
+               MOD_SEL6_10
+               /* RESERVED 9-8 */
+               MOD_SEL6_7
+               MOD_SEL6_6
+               MOD_SEL6_5
+               /* RESERVED 4-3 */
+               MOD_SEL6_2
+               MOD_SEL6_1
+               /* RESERVED 0 */
+               ))
+       },
+       { PINMUX_CFG_REG_VAR("MOD_SEL7", 0xE6061900, 32,
+                            GROUP(-15, 1, 1, -1, 1, -1, 1, 1, -2, 1, 1,
+                                  -2, 1, 1, -1, 1),
+                            GROUP(
+               /* RESERVED 31-17 */
+               MOD_SEL7_16
+               MOD_SEL7_15
+               /* RESERVED 14 */
+               MOD_SEL7_13
+               /* RESERVED 12 */
+               MOD_SEL7_11
+               MOD_SEL7_10
+               /* RESERVED 9-8 */
+               MOD_SEL7_7
+               MOD_SEL7_6
+               /* RESERVED 5-4 */
+               MOD_SEL7_3
+               MOD_SEL7_2
+               /* RESERVED 1 */
+               MOD_SEL7_0))
+       },
+       { PINMUX_CFG_REG_VAR("MOD_SEL8", 0xE6068100, 32,
+                            GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+                            GROUP(
+               /* RESERVED 31-12 */
+               MOD_SEL8_11
+               MOD_SEL8_10
+               MOD_SEL8_9
+               MOD_SEL8_8
+               MOD_SEL8_7
+               MOD_SEL8_6
+               MOD_SEL8_5
+               MOD_SEL8_4
+               MOD_SEL8_3
+               MOD_SEL8_2
+               MOD_SEL8_1
+               MOD_SEL8_0))
+       },
+       { },
+};
+
+static const struct pinmux_drive_reg pinmux_drive_regs[] = {
+       { PINMUX_DRIVE_REG("DRV0CTRL0", 0xE6050080) {
+               { RCAR_GP_PIN(0,  7), 28, 3 },  /* MSIOF5_SS2 */
+               { RCAR_GP_PIN(0,  6), 24, 3 },  /* IRQ0 */
+               { RCAR_GP_PIN(0,  5), 20, 3 },  /* IRQ1 */
+               { RCAR_GP_PIN(0,  4), 16, 3 },  /* IRQ2 */
+               { RCAR_GP_PIN(0,  3), 12, 3 },  /* IRQ3 */
+               { RCAR_GP_PIN(0,  2),  8, 3 },  /* GP0_02 */
+               { RCAR_GP_PIN(0,  1),  4, 3 },  /* GP0_01 */
+               { RCAR_GP_PIN(0,  0),  0, 3 },  /* GP0_00 */
+       } },
+       { PINMUX_DRIVE_REG("DRV1CTRL0", 0xE6050084) {
+               { RCAR_GP_PIN(0, 15), 28, 3 },  /* MSIOF2_SYNC */
+               { RCAR_GP_PIN(0, 14), 24, 3 },  /* MSIOF2_SS1 */
+               { RCAR_GP_PIN(0, 13), 20, 3 },  /* MSIOF2_SS2 */
+               { RCAR_GP_PIN(0, 12), 16, 3 },  /* MSIOF5_RXD */
+               { RCAR_GP_PIN(0, 11), 12, 3 },  /* MSIOF5_SCK */
+               { RCAR_GP_PIN(0, 10),  8, 3 },  /* MSIOF5_TXD */
+               { RCAR_GP_PIN(0,  9),  4, 3 },  /* MSIOF5_SYNC */
+               { RCAR_GP_PIN(0,  8),  0, 3 },  /* MSIOF5_SS1 */
+       } },
+       { PINMUX_DRIVE_REG("DRV2CTRL0", 0xE6050088) {
+               { RCAR_GP_PIN(0, 18),  8, 3 },  /* MSIOF2_RXD */
+               { RCAR_GP_PIN(0, 17),  4, 3 },  /* MSIOF2_SCK */
+               { RCAR_GP_PIN(0, 16),  0, 3 },  /* MSIOF2_TXD */
+       } },
+       { PINMUX_DRIVE_REG("DRV0CTRL1", 0xE6050880) {
+               { RCAR_GP_PIN(1,  7), 28, 3 },  /* MSIOF0_SS1 */
+               { RCAR_GP_PIN(1,  6), 24, 3 },  /* MSIOF0_SS2 */
+               { RCAR_GP_PIN(1,  5), 20, 3 },  /* MSIOF1_RXD */
+               { RCAR_GP_PIN(1,  4), 16, 3 },  /* MSIOF1_TXD */
+               { RCAR_GP_PIN(1,  3), 12, 3 },  /* MSIOF1_SCK */
+               { RCAR_GP_PIN(1,  2),  8, 3 },  /* MSIOF1_SYNC */
+               { RCAR_GP_PIN(1,  1),  4, 3 },  /* MSIOF1_SS1 */
+               { RCAR_GP_PIN(1,  0),  0, 3 },  /* MSIOF1_SS2 */
+       } },
+       { PINMUX_DRIVE_REG("DRV1CTRL1", 0xE6050884) {
+               { RCAR_GP_PIN(1, 15), 28, 3 },  /* HSCK0 */
+               { RCAR_GP_PIN(1, 14), 24, 3 },  /* HRTS0_N */
+               { RCAR_GP_PIN(1, 13), 20, 3 },  /* HCTS0_N */
+               { RCAR_GP_PIN(1, 12), 16, 3 },  /* HTX0 */
+               { RCAR_GP_PIN(1, 11), 12, 3 },  /* MSIOF0_RXD */
+               { RCAR_GP_PIN(1, 10),  8, 3 },  /* MSIOF0_SCK */
+               { RCAR_GP_PIN(1,  9),  4, 3 },  /* MSIOF0_TXD */
+               { RCAR_GP_PIN(1,  8),  0, 3 },  /* MSIOF0_SYNC */
+       } },
+       { PINMUX_DRIVE_REG("DRV2CTRL1", 0xE6050888) {
+               { RCAR_GP_PIN(1, 23), 28, 3 },  /* GP1_23 */
+               { RCAR_GP_PIN(1, 22), 24, 3 },  /* AUDIO_CLKIN */
+               { RCAR_GP_PIN(1, 21), 20, 3 },  /* AUDIO_CLKOUT */
+               { RCAR_GP_PIN(1, 20), 16, 3 },  /* SSI_SD */
+               { RCAR_GP_PIN(1, 19), 12, 3 },  /* SSI_WS */
+               { RCAR_GP_PIN(1, 18),  8, 3 },  /* SSI_SCK */
+               { RCAR_GP_PIN(1, 17),  4, 3 },  /* SCIF_CLK */
+               { RCAR_GP_PIN(1, 16),  0, 3 },  /* HRX0 */
+       } },
+       { PINMUX_DRIVE_REG("DRV3CTRL1", 0xE605088C) {
+               { RCAR_GP_PIN(1, 28), 16, 3 },  /* HTX3 */
+               { RCAR_GP_PIN(1, 27), 12, 3 },  /* HCTS3_N */
+               { RCAR_GP_PIN(1, 26),  8, 3 },  /* HRTS3_N */
+               { RCAR_GP_PIN(1, 25),  4, 3 },  /* HSCK3 */
+               { RCAR_GP_PIN(1, 24),  0, 3 },  /* HRX3 */
+       } },
+       { PINMUX_DRIVE_REG("DRV0CTRL2", 0xE6058080) {
+               { RCAR_GP_PIN(2,  7), 28, 3 },  /* TPU0TO1 */
+               { RCAR_GP_PIN(2,  6), 24, 3 },  /* FXR_TXDB */
+               { RCAR_GP_PIN(2,  5), 20, 3 },  /* FXR_TXENB_N */
+               { RCAR_GP_PIN(2,  4), 16, 3 },  /* RXDB_EXTFXR */
+               { RCAR_GP_PIN(2,  3), 12, 3 },  /* CLK_EXTFXR */
+               { RCAR_GP_PIN(2,  2),  8, 3 },  /* RXDA_EXTFXR */
+               { RCAR_GP_PIN(2,  1),  4, 3 },  /* FXR_TXENA_N */
+               { RCAR_GP_PIN(2,  0),  0, 3 },  /* FXR_TXDA */
+       } },
+       { PINMUX_DRIVE_REG("DRV1CTRL2", 0xE6058084) {
+               { RCAR_GP_PIN(2, 15), 28, 3 },  /* CANFD3_RX */
+               { RCAR_GP_PIN(2, 14), 24, 3 },  /* CANFD3_TX */
+               { RCAR_GP_PIN(2, 13), 20, 3 },  /* CANFD2_RX */
+               { RCAR_GP_PIN(2, 12), 16, 3 },  /* CANFD2_TX */
+               { RCAR_GP_PIN(2, 11), 12, 3 },  /* CANFD0_RX */
+               { RCAR_GP_PIN(2, 10),  8, 3 },  /* CANFD0_TX */
+               { RCAR_GP_PIN(2,  9),  4, 3 },  /* CAN_CLK */
+               { RCAR_GP_PIN(2,  8),  0, 3 },  /* TPU0TO0 */
+       } },
+       { PINMUX_DRIVE_REG("DRV2CTRL2", 0xE6058088) {
+               { RCAR_GP_PIN(2, 19), 12, 3 },  /* CANFD7_RX */
+               { RCAR_GP_PIN(2, 18),  8, 3 },  /* CANFD7_TX */
+               { RCAR_GP_PIN(2, 17),  4, 3 },  /* CANFD4_RX */
+               { RCAR_GP_PIN(2, 16),  0, 3 },  /* CANFD4_TX */
+       } },
+       { PINMUX_DRIVE_REG("DRV0CTRL3", 0xE6058880) {
+               { RCAR_GP_PIN(3,  7), 28, 3 },  /* MMC_D4 */
+               { RCAR_GP_PIN(3,  6), 24, 3 },  /* MMC_D5 */
+               { RCAR_GP_PIN(3,  5), 20, 3 },  /* MMC_SD_D3 */
+               { RCAR_GP_PIN(3,  4), 16, 3 },  /* MMC_DS */
+               { RCAR_GP_PIN(3,  3), 12, 3 },  /* MMC_SD_CLK */
+               { RCAR_GP_PIN(3,  2),  8, 3 },  /* MMC_SD_D2 */
+               { RCAR_GP_PIN(3,  1),  4, 3 },  /* MMC_SD_D0 */
+               { RCAR_GP_PIN(3,  0),  0, 3 },  /* MMC_SD_D1 */
+       } },
+       { PINMUX_DRIVE_REG("DRV1CTRL3", 0xE6058884) {
+               { RCAR_GP_PIN(3, 15), 28, 2 },  /* QSPI0_SSL */
+               { RCAR_GP_PIN(3, 14), 24, 2 },  /* IPC_CLKOUT */
+               { RCAR_GP_PIN(3, 13), 20, 2 },  /* IPC_CLKIN */
+               { RCAR_GP_PIN(3, 12), 16, 3 },  /* SD_WP */
+               { RCAR_GP_PIN(3, 11), 12, 3 },  /* SD_CD */
+               { RCAR_GP_PIN(3, 10),  8, 3 },  /* MMC_SD_CMD */
+               { RCAR_GP_PIN(3,  9),  4, 3 },  /* MMC_D6*/
+               { RCAR_GP_PIN(3,  8),  0, 3 },  /* MMC_D7 */
+       } },
+       { PINMUX_DRIVE_REG("DRV2CTRL3", 0xE6058888) {
+               { RCAR_GP_PIN(3, 23), 28, 2 },  /* QSPI1_MISO_IO1 */
+               { RCAR_GP_PIN(3, 22), 24, 2 },  /* QSPI1_SPCLK */
+               { RCAR_GP_PIN(3, 21), 20, 2 },  /* QSPI1_MOSI_IO0 */
+               { RCAR_GP_PIN(3, 20), 16, 2 },  /* QSPI0_SPCLK */
+               { RCAR_GP_PIN(3, 19), 12, 2 },  /* QSPI0_MOSI_IO0 */
+               { RCAR_GP_PIN(3, 18),  8, 2 },  /* QSPI0_MISO_IO1 */
+               { RCAR_GP_PIN(3, 17),  4, 2 },  /* QSPI0_IO2 */
+               { RCAR_GP_PIN(3, 16),  0, 2 },  /* QSPI0_IO3 */
+       } },
+       { PINMUX_DRIVE_REG("DRV3CTRL3", 0xE605888C) {
+               { RCAR_GP_PIN(3, 29), 20, 2 },  /* RPC_INT_N */
+               { RCAR_GP_PIN(3, 28), 16, 2 },  /* RPC_WP_N */
+               { RCAR_GP_PIN(3, 27), 12, 2 },  /* RPC_RESET_N */
+               { RCAR_GP_PIN(3, 26),  8, 2 },  /* QSPI1_IO3 */
+               { RCAR_GP_PIN(3, 25),  4, 2 },  /* QSPI1_SSL */
+               { RCAR_GP_PIN(3, 24),  0, 2 },  /* QSPI1_IO2 */
+       } },
+       { PINMUX_DRIVE_REG("DRV0CTRL4", 0xE6060080) {
+               { RCAR_GP_PIN(4,  7), 28, 3 },  /* TSN0_RX_CTL */
+               { RCAR_GP_PIN(4,  6), 24, 3 },  /* TSN0_AVTP_CAPTURE */
+               { RCAR_GP_PIN(4,  5), 20, 3 },  /* TSN0_AVTP_MATCH */
+               { RCAR_GP_PIN(4,  4), 16, 3 },  /* TSN0_LINK */
+               { RCAR_GP_PIN(4,  3), 12, 3 },  /* TSN0_PHY_INT */
+               { RCAR_GP_PIN(4,  2),  8, 3 },  /* TSN0_AVTP_PPS1 */
+               { RCAR_GP_PIN(4,  1),  4, 3 },  /* TSN0_MDC */
+               { RCAR_GP_PIN(4,  0),  0, 3 },  /* TSN0_MDIO */
+       } },
+       { PINMUX_DRIVE_REG("DRV1CTRL4", 0xE6060084) {
+               { RCAR_GP_PIN(4, 15), 28, 3 },  /* TSN0_TD0 */
+               { RCAR_GP_PIN(4, 14), 24, 3 },  /* TSN0_TD1 */
+               { RCAR_GP_PIN(4, 13), 20, 3 },  /* TSN0_RD1 */
+               { RCAR_GP_PIN(4, 12), 16, 3 },  /* TSN0_TXC */
+               { RCAR_GP_PIN(4, 11), 12, 3 },  /* TSN0_RXC */
+               { RCAR_GP_PIN(4, 10),  8, 3 },  /* TSN0_RD0 */
+               { RCAR_GP_PIN(4,  9),  4, 3 },  /* TSN0_TX_CTL */
+               { RCAR_GP_PIN(4,  8),  0, 3 },  /* TSN0_AVTP_PPS0 */
+       } },
+       { PINMUX_DRIVE_REG("DRV2CTRL4", 0xE6060088) {
+               { RCAR_GP_PIN(4, 23), 28, 3 },  /* AVS0 */
+               { RCAR_GP_PIN(4, 22), 24, 3 },  /* PCIE1_CLKREQ_N */
+               { RCAR_GP_PIN(4, 21), 20, 3 },  /* PCIE0_CLKREQ_N */
+               { RCAR_GP_PIN(4, 20), 16, 3 },  /* TSN0_TXCREFCLK */
+               { RCAR_GP_PIN(4, 19), 12, 3 },  /* TSN0_TD2 */
+               { RCAR_GP_PIN(4, 18),  8, 3 },  /* TSN0_TD3 */
+               { RCAR_GP_PIN(4, 17),  4, 3 },  /* TSN0_RD2 */
+               { RCAR_GP_PIN(4, 16),  0, 3 },  /* TSN0_RD3 */
+       } },
+       { PINMUX_DRIVE_REG("DRV3CTRL4", 0xE606008C) {
+               { RCAR_GP_PIN(4, 24),  0, 3 },  /* AVS1 */
+       } },
+       { PINMUX_DRIVE_REG("DRV0CTRL5", 0xE6060880) {
+               { RCAR_GP_PIN(5,  7), 28, 3 },  /* AVB2_TXCREFCLK */
+               { RCAR_GP_PIN(5,  6), 24, 3 },  /* AVB2_MDC */
+               { RCAR_GP_PIN(5,  5), 20, 3 },  /* AVB2_MAGIC */
+               { RCAR_GP_PIN(5,  4), 16, 3 },  /* AVB2_PHY_INT */
+               { RCAR_GP_PIN(5,  3), 12, 3 },  /* AVB2_LINK */
+               { RCAR_GP_PIN(5,  2),  8, 3 },  /* AVB2_AVTP_MATCH */
+               { RCAR_GP_PIN(5,  1),  4, 3 },  /* AVB2_AVTP_CAPTURE */
+               { RCAR_GP_PIN(5,  0),  0, 3 },  /* AVB2_AVTP_PPS */
+       } },
+       { PINMUX_DRIVE_REG("DRV1CTRL5", 0xE6060884) {
+               { RCAR_GP_PIN(5, 15), 28, 3 },  /* AVB2_TD0 */
+               { RCAR_GP_PIN(5, 14), 24, 3 },  /* AVB2_RD1 */
+               { RCAR_GP_PIN(5, 13), 20, 3 },  /* AVB2_RD2 */
+               { RCAR_GP_PIN(5, 12), 16, 3 },  /* AVB2_TD1 */
+               { RCAR_GP_PIN(5, 11), 12, 3 },  /* AVB2_TD2 */
+               { RCAR_GP_PIN(5, 10),  8, 3 },  /* AVB2_MDIO */
+               { RCAR_GP_PIN(5,  9),  4, 3 },  /* AVB2_RD3 */
+               { RCAR_GP_PIN(5,  8),  0, 3 },  /* AVB2_TD3 */
+       } },
+       { PINMUX_DRIVE_REG("DRV2CTRL5", 0xE6060888) {
+               { RCAR_GP_PIN(5, 20), 16, 3 },  /* AVB2_RX_CTL */
+               { RCAR_GP_PIN(5, 19), 12, 3 },  /* AVB2_TX_CTL */
+               { RCAR_GP_PIN(5, 18),  8, 3 },  /* AVB2_RXC */
+               { RCAR_GP_PIN(5, 17),  4, 3 },  /* AVB2_RD0 */
+               { RCAR_GP_PIN(5, 16),  0, 3 },  /* AVB2_TXC */
+       } },
+       { PINMUX_DRIVE_REG("DRV0CTRL6", 0xE6061080) {
+               { RCAR_GP_PIN(6,  7), 28, 3 },  /* AVB1_TX_CTL */
+               { RCAR_GP_PIN(6,  6), 24, 3 },  /* AVB1_TXC */
+               { RCAR_GP_PIN(6,  5), 20, 3 },  /* AVB1_AVTP_MATCH */
+               { RCAR_GP_PIN(6,  4), 16, 3 },  /* AVB1_LINK */
+               { RCAR_GP_PIN(6,  3), 12, 3 },  /* AVB1_PHY_INT */
+               { RCAR_GP_PIN(6,  2),  8, 3 },  /* AVB1_MDC */
+               { RCAR_GP_PIN(6,  1),  4, 3 },  /* AVB1_MAGIC */
+               { RCAR_GP_PIN(6,  0),  0, 3 },  /* AVB1_MDIO */
+       } },
+       { PINMUX_DRIVE_REG("DRV1CTRL6", 0xE6061084) {
+               { RCAR_GP_PIN(6, 15), 28, 3 },  /* AVB1_RD0 */
+               { RCAR_GP_PIN(6, 14), 24, 3 },  /* AVB1_RD1 */
+               { RCAR_GP_PIN(6, 13), 20, 3 },  /* AVB1_TD0 */
+               { RCAR_GP_PIN(6, 12), 16, 3 },  /* AVB1_TD1 */
+               { RCAR_GP_PIN(6, 11), 12, 3 },  /* AVB1_AVTP_CAPTURE */
+               { RCAR_GP_PIN(6, 10),  8, 3 },  /* AVB1_AVTP_PPS */
+               { RCAR_GP_PIN(6,  9),  4, 3 },  /* AVB1_RX_CTL */
+               { RCAR_GP_PIN(6,  8),  0, 3 },  /* AVB1_RXC */
+       } },
+       { PINMUX_DRIVE_REG("DRV2CTRL6", 0xE6061088) {
+               { RCAR_GP_PIN(6, 20), 16, 3 },  /* AVB1_TXCREFCLK */
+               { RCAR_GP_PIN(6, 19), 12, 3 },  /* AVB1_RD3 */
+               { RCAR_GP_PIN(6, 18),  8, 3 },  /* AVB1_TD3 */
+               { RCAR_GP_PIN(6, 17),  4, 3 },  /* AVB1_RD2 */
+               { RCAR_GP_PIN(6, 16),  0, 3 },  /* AVB1_TD2 */
+       } },
+       { PINMUX_DRIVE_REG("DRV0CTRL7", 0xE6061880) {
+               { RCAR_GP_PIN(7,  7), 28, 3 },  /* AVB0_TD1 */
+               { RCAR_GP_PIN(7,  6), 24, 3 },  /* AVB0_TD2 */
+               { RCAR_GP_PIN(7,  5), 20, 3 },  /* AVB0_PHY_INT */
+               { RCAR_GP_PIN(7,  4), 16, 3 },  /* AVB0_LINK */
+               { RCAR_GP_PIN(7,  3), 12, 3 },  /* AVB0_TD3 */
+               { RCAR_GP_PIN(7,  2),  8, 3 },  /* AVB0_AVTP_MATCH */
+               { RCAR_GP_PIN(7,  1),  4, 3 },  /* AVB0_AVTP_CAPTURE */
+               { RCAR_GP_PIN(7,  0),  0, 3 },  /* AVB0_AVTP_PPS */
+       } },
+       { PINMUX_DRIVE_REG("DRV1CTRL7", 0xE6061884) {
+               { RCAR_GP_PIN(7, 15), 28, 3 },  /* AVB0_TXC */
+               { RCAR_GP_PIN(7, 14), 24, 3 },  /* AVB0_MDIO */
+               { RCAR_GP_PIN(7, 13), 20, 3 },  /* AVB0_MDC */
+               { RCAR_GP_PIN(7, 12), 16, 3 },  /* AVB0_RD2 */
+               { RCAR_GP_PIN(7, 11), 12, 3 },  /* AVB0_TD0 */
+               { RCAR_GP_PIN(7, 10),  8, 3 },  /* AVB0_MAGIC */
+               { RCAR_GP_PIN(7,  9),  4, 3 },  /* AVB0_TXCREFCLK */
+               { RCAR_GP_PIN(7,  8),  0, 3 },  /* AVB0_RD3 */
+       } },
+       { PINMUX_DRIVE_REG("DRV2CTRL7", 0xE6061888) {
+               { RCAR_GP_PIN(7, 20), 16, 3 },  /* AVB0_RX_CTL */
+               { RCAR_GP_PIN(7, 19), 12, 3 },  /* AVB0_RXC */
+               { RCAR_GP_PIN(7, 18),  8, 3 },  /* AVB0_RD0 */
+               { RCAR_GP_PIN(7, 17),  4, 3 },  /* AVB0_RD1 */
+               { RCAR_GP_PIN(7, 16),  0, 3 },  /* AVB0_TX_CTL */
+       } },
+       { PINMUX_DRIVE_REG("DRV0CTRL8", 0xE6068080) {
+               { RCAR_GP_PIN(8,  7), 28, 3 },  /* SDA3 */
+               { RCAR_GP_PIN(8,  6), 24, 3 },  /* SCL3 */
+               { RCAR_GP_PIN(8,  5), 20, 3 },  /* SDA2 */
+               { RCAR_GP_PIN(8,  4), 16, 3 },  /* SCL2 */
+               { RCAR_GP_PIN(8,  3), 12, 3 },  /* SDA1 */
+               { RCAR_GP_PIN(8,  2),  8, 3 },  /* SCL1 */
+               { RCAR_GP_PIN(8,  1),  4, 3 },  /* SDA0 */
+               { RCAR_GP_PIN(8,  0),  0, 3 },  /* SCL0 */
+       } },
+       { PINMUX_DRIVE_REG("DRV1CTRL8", 0xE6068084) {
+               { RCAR_GP_PIN(8, 13), 20, 3 },  /* GP8_13 */
+               { RCAR_GP_PIN(8, 12), 16, 3 },  /* GP8_12 */
+               { RCAR_GP_PIN(8, 11), 12, 3 },  /* SDA5 */
+               { RCAR_GP_PIN(8, 10),  8, 3 },  /* SCL5 */
+               { RCAR_GP_PIN(8,  9),  4, 3 },  /* SDA4 */
+               { RCAR_GP_PIN(8,  8),  0, 3 },  /* SCL4 */
+       } },
+       { },
+};
+
+enum ioctrl_regs {
+       POC0,
+       POC1,
+       POC3,
+       POC4,
+       POC5,
+       POC6,
+       POC7,
+       POC8,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+       [POC0]          = { 0xE60500A0, },
+       [POC1]          = { 0xE60508A0, },
+       [POC3]          = { 0xE60588A0, },
+       [POC4]          = { 0xE60600A0, },
+       [POC5]          = { 0xE60608A0, },
+       [POC6]          = { 0xE60610A0, },
+       [POC7]          = { 0xE60618A0, },
+       [POC8]          = { 0xE60680A0, },
+       { /* sentinel */ },
+};
+
+static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
+{
+       int bit = pin & 0x1f;
+
+       *pocctrl = pinmux_ioctrl_regs[POC0].reg;
+       if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 18))
+               return bit;
+
+       *pocctrl = pinmux_ioctrl_regs[POC1].reg;
+       if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 22))
+               return bit;
+
+       *pocctrl = pinmux_ioctrl_regs[POC3].reg;
+       if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 12))
+               return bit;
+
+       *pocctrl = pinmux_ioctrl_regs[POC8].reg;
+       if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 13))
+               return bit;
+
+       return -EINVAL;
+}
+
+static const struct pinmux_bias_reg pinmux_bias_regs[] = {
+       { PINMUX_BIAS_REG("PUEN0", 0xE60500C0, "PUD0", 0xE60500E0) {
+               [ 0] = RCAR_GP_PIN(0,  0),      /* GP0_00 */
+               [ 1] = RCAR_GP_PIN(0,  1),      /* GP0_01 */
+               [ 2] = RCAR_GP_PIN(0,  2),      /* GP0_02 */
+               [ 3] = RCAR_GP_PIN(0,  3),      /* IRQ3 */
+               [ 4] = RCAR_GP_PIN(0,  4),      /* IRQ2 */
+               [ 5] = RCAR_GP_PIN(0,  5),      /* IRQ1 */
+               [ 6] = RCAR_GP_PIN(0,  6),      /* IRQ0 */
+               [ 7] = RCAR_GP_PIN(0,  7),      /* MSIOF5_SS2 */
+               [ 8] = RCAR_GP_PIN(0,  8),      /* MSIOF5_SS1 */
+               [ 9] = RCAR_GP_PIN(0,  9),      /* MSIOF5_SYNC */
+               [10] = RCAR_GP_PIN(0, 10),      /* MSIOF5_TXD */
+               [11] = RCAR_GP_PIN(0, 11),      /* MSIOF5_SCK */
+               [12] = RCAR_GP_PIN(0, 12),      /* MSIOF5_RXD */
+               [13] = RCAR_GP_PIN(0, 13),      /* MSIOF2_SS2 */
+               [14] = RCAR_GP_PIN(0, 14),      /* MSIOF2_SS1 */
+               [15] = RCAR_GP_PIN(0, 15),      /* MSIOF2_SYNC */
+               [16] = RCAR_GP_PIN(0, 16),      /* MSIOF2_TXD */
+               [17] = RCAR_GP_PIN(0, 17),      /* MSIOF2_SCK */
+               [18] = RCAR_GP_PIN(0, 18),      /* MSIOF2_RXD */
+               [19] = SH_PFC_PIN_NONE,
+               [20] = SH_PFC_PIN_NONE,
+               [21] = SH_PFC_PIN_NONE,
+               [22] = SH_PFC_PIN_NONE,
+               [23] = SH_PFC_PIN_NONE,
+               [24] = SH_PFC_PIN_NONE,
+               [25] = SH_PFC_PIN_NONE,
+               [26] = SH_PFC_PIN_NONE,
+               [27] = SH_PFC_PIN_NONE,
+               [28] = SH_PFC_PIN_NONE,
+               [29] = SH_PFC_PIN_NONE,
+               [30] = SH_PFC_PIN_NONE,
+               [31] = SH_PFC_PIN_NONE,
+       } },
+       { PINMUX_BIAS_REG("PUEN1", 0xE60508C0, "PUD1", 0xE60508E0) {
+               [ 0] = RCAR_GP_PIN(1,  0),      /* MSIOF1_SS2 */
+               [ 1] = RCAR_GP_PIN(1,  1),      /* MSIOF1_SS1 */
+               [ 2] = RCAR_GP_PIN(1,  2),      /* MSIOF1_SYNC */
+               [ 3] = RCAR_GP_PIN(1,  3),      /* MSIOF1_SCK */
+               [ 4] = RCAR_GP_PIN(1,  4),      /* MSIOF1_TXD */
+               [ 5] = RCAR_GP_PIN(1,  5),      /* MSIOF1_RXD */
+               [ 6] = RCAR_GP_PIN(1,  6),      /* MSIOF0_SS2 */
+               [ 7] = RCAR_GP_PIN(1,  7),      /* MSIOF0_SS1 */
+               [ 8] = RCAR_GP_PIN(1,  8),      /* MSIOF0_SYNC */
+               [ 9] = RCAR_GP_PIN(1,  9),      /* MSIOF0_TXD */
+               [10] = RCAR_GP_PIN(1, 10),      /* MSIOF0_SCK */
+               [11] = RCAR_GP_PIN(1, 11),      /* MSIOF0_RXD */
+               [12] = RCAR_GP_PIN(1, 12),      /* HTX0 */
+               [13] = RCAR_GP_PIN(1, 13),      /* HCTS0_N */
+               [14] = RCAR_GP_PIN(1, 14),      /* HRTS0_N */
+               [15] = RCAR_GP_PIN(1, 15),      /* HSCK0 */
+               [16] = RCAR_GP_PIN(1, 16),      /* HRX0 */
+               [17] = RCAR_GP_PIN(1, 17),      /* SCIF_CLK */
+               [18] = RCAR_GP_PIN(1, 18),      /* SSI_SCK */
+               [19] = RCAR_GP_PIN(1, 19),      /* SSI_WS */
+               [20] = RCAR_GP_PIN(1, 20),      /* SSI_SD */
+               [21] = RCAR_GP_PIN(1, 21),      /* AUDIO_CLKOUT */
+               [22] = RCAR_GP_PIN(1, 22),      /* AUDIO_CLKIN */
+               [23] = RCAR_GP_PIN(1, 23),      /* GP1_23 */
+               [24] = RCAR_GP_PIN(1, 24),      /* HRX3 */
+               [25] = RCAR_GP_PIN(1, 25),      /* HSCK3 */
+               [26] = RCAR_GP_PIN(1, 26),      /* HRTS3_N */
+               [27] = RCAR_GP_PIN(1, 27),      /* HCTS3_N */
+               [28] = RCAR_GP_PIN(1, 28),      /* HTX3 */
+               [29] = SH_PFC_PIN_NONE,
+               [30] = SH_PFC_PIN_NONE,
+               [31] = SH_PFC_PIN_NONE,
+       } },
+       { PINMUX_BIAS_REG("PUEN2", 0xE60580C0, "PUD2", 0xE60580E0) {
+               [ 0] = RCAR_GP_PIN(2,  0),      /* FXR_TXDA */
+               [ 1] = RCAR_GP_PIN(2,  1),      /* FXR_TXENA_N */
+               [ 2] = RCAR_GP_PIN(2,  2),      /* RXDA_EXTFXR */
+               [ 3] = RCAR_GP_PIN(2,  3),      /* CLK_EXTFXR */
+               [ 4] = RCAR_GP_PIN(2,  4),      /* RXDB_EXTFXR */
+               [ 5] = RCAR_GP_PIN(2,  5),      /* FXR_TXENB_N */
+               [ 6] = RCAR_GP_PIN(2,  6),      /* FXR_TXDB */
+               [ 7] = RCAR_GP_PIN(2,  7),      /* TPU0TO1 */
+               [ 8] = RCAR_GP_PIN(2,  8),      /* TPU0TO0 */
+               [ 9] = RCAR_GP_PIN(2,  9),      /* CAN_CLK */
+               [10] = RCAR_GP_PIN(2, 10),      /* CANFD0_TX */
+               [11] = RCAR_GP_PIN(2, 11),      /* CANFD0_RX */
+               [12] = RCAR_GP_PIN(2, 12),      /* CANFD2_TX */
+               [13] = RCAR_GP_PIN(2, 13),      /* CANFD2_RX */
+               [14] = RCAR_GP_PIN(2, 14),      /* CANFD3_TX */
+               [15] = RCAR_GP_PIN(2, 15),      /* CANFD3_RX */
+               [16] = RCAR_GP_PIN(2, 16),      /* CANFD4_TX */
+               [17] = RCAR_GP_PIN(2, 17),      /* CANFD4_RX */
+               [18] = RCAR_GP_PIN(2, 18),      /* CANFD7_TX */
+               [19] = RCAR_GP_PIN(2, 19),      /* CANFD7_RX */
+               [20] = SH_PFC_PIN_NONE,
+               [21] = SH_PFC_PIN_NONE,
+               [22] = SH_PFC_PIN_NONE,
+               [23] = SH_PFC_PIN_NONE,
+               [24] = SH_PFC_PIN_NONE,
+               [25] = SH_PFC_PIN_NONE,
+               [26] = SH_PFC_PIN_NONE,
+               [27] = SH_PFC_PIN_NONE,
+               [28] = SH_PFC_PIN_NONE,
+               [29] = SH_PFC_PIN_NONE,
+               [30] = SH_PFC_PIN_NONE,
+               [31] = SH_PFC_PIN_NONE,
+       } },
+       { PINMUX_BIAS_REG("PUEN3", 0xE60588C0, "PUD3", 0xE60588E0) {
+               [ 0] = RCAR_GP_PIN(3,  0),      /* MMC_SD_D1 */
+               [ 1] = RCAR_GP_PIN(3,  1),      /* MMC_SD_D0 */
+               [ 2] = RCAR_GP_PIN(3,  2),      /* MMC_SD_D2 */
+               [ 3] = RCAR_GP_PIN(3,  3),      /* MMC_SD_CLK */
+               [ 4] = RCAR_GP_PIN(3,  4),      /* MMC_DS */
+               [ 5] = RCAR_GP_PIN(3,  5),      /* MMC_SD_D3 */
+               [ 6] = RCAR_GP_PIN(3,  6),      /* MMC_D5 */
+               [ 7] = RCAR_GP_PIN(3,  7),      /* MMC_D4 */
+               [ 8] = RCAR_GP_PIN(3,  8),      /* MMC_D7 */
+               [ 9] = RCAR_GP_PIN(3,  9),      /* MMC_D6 */
+               [10] = RCAR_GP_PIN(3, 10),      /* MMC_SD_CMD */
+               [11] = RCAR_GP_PIN(3, 11),      /* SD_CD */
+               [12] = RCAR_GP_PIN(3, 12),      /* SD_WP */
+               [13] = RCAR_GP_PIN(3, 13),      /* IPC_CLKIN */
+               [14] = RCAR_GP_PIN(3, 14),      /* IPC_CLKOUT */
+               [15] = RCAR_GP_PIN(3, 15),      /* QSPI0_SSL */
+               [16] = RCAR_GP_PIN(3, 16),      /* QSPI0_IO3 */
+               [17] = RCAR_GP_PIN(3, 17),      /* QSPI0_IO2 */
+               [18] = RCAR_GP_PIN(3, 18),      /* QSPI0_MISO_IO1 */
+               [19] = RCAR_GP_PIN(3, 19),      /* QSPI0_MOSI_IO0 */
+               [20] = RCAR_GP_PIN(3, 20),      /* QSPI0_SPCLK */
+               [21] = RCAR_GP_PIN(3, 21),      /* QSPI1_MOSI_IO0 */
+               [22] = RCAR_GP_PIN(3, 22),      /* QSPI1_SPCLK */
+               [23] = RCAR_GP_PIN(3, 23),      /* QSPI1_MISO_IO1 */
+               [24] = RCAR_GP_PIN(3, 24),      /* QSPI1_IO2 */
+               [25] = RCAR_GP_PIN(3, 25),      /* QSPI1_SSL */
+               [26] = RCAR_GP_PIN(3, 26),      /* QSPI1_IO3 */
+               [27] = RCAR_GP_PIN(3, 27),      /* RPC_RESET_N */
+               [28] = RCAR_GP_PIN(3, 28),      /* RPC_WP_N */
+               [29] = RCAR_GP_PIN(3, 29),      /* RPC_INT_N */
+               [30] = SH_PFC_PIN_NONE,
+               [31] = SH_PFC_PIN_NONE,
+       } },
+       { PINMUX_BIAS_REG("PUEN4", 0xE60600C0, "PUD4", 0xE60600E0) {
+               [ 0] = RCAR_GP_PIN(4,  0),      /* TSN0_MDIO */
+               [ 1] = RCAR_GP_PIN(4,  1),      /* TSN0_MDC */
+               [ 2] = RCAR_GP_PIN(4,  2),      /* TSN0_AVTP_PPS1 */
+               [ 3] = RCAR_GP_PIN(4,  3),      /* TSN0_PHY_INT */
+               [ 4] = RCAR_GP_PIN(4,  4),      /* TSN0_LINK */
+               [ 5] = RCAR_GP_PIN(4,  5),      /* TSN0_AVTP_MATCH */
+               [ 6] = RCAR_GP_PIN(4,  6),      /* TSN0_AVTP_CAPTURE */
+               [ 7] = RCAR_GP_PIN(4,  7),      /* TSN0_RX_CTL */
+               [ 8] = RCAR_GP_PIN(4,  8),      /* TSN0_AVTP_PPS0 */
+               [ 9] = RCAR_GP_PIN(4,  9),      /* TSN0_TX_CTL */
+               [10] = RCAR_GP_PIN(4, 10),      /* TSN0_RD0 */
+               [11] = RCAR_GP_PIN(4, 11),      /* TSN0_RXC */
+               [12] = RCAR_GP_PIN(4, 12),      /* TSN0_TXC */
+               [13] = RCAR_GP_PIN(4, 13),      /* TSN0_RD1 */
+               [14] = RCAR_GP_PIN(4, 14),      /* TSN0_TD1 */
+               [15] = RCAR_GP_PIN(4, 15),      /* TSN0_TD0 */
+               [16] = RCAR_GP_PIN(4, 16),      /* TSN0_RD3 */
+               [17] = RCAR_GP_PIN(4, 17),      /* TSN0_RD2 */
+               [18] = RCAR_GP_PIN(4, 18),      /* TSN0_TD3 */
+               [19] = RCAR_GP_PIN(4, 19),      /* TSN0_TD2 */
+               [20] = RCAR_GP_PIN(4, 20),      /* TSN0_TXCREFCLK */
+               [21] = RCAR_GP_PIN(4, 21),      /* PCIE0_CLKREQ_N */
+               [22] = RCAR_GP_PIN(4, 22),      /* PCIE1_CLKREQ_N */
+               [23] = RCAR_GP_PIN(4, 23),      /* AVS0 */
+               [24] = RCAR_GP_PIN(4, 24),      /* AVS1 */
+               [25] = SH_PFC_PIN_NONE,
+               [26] = SH_PFC_PIN_NONE,
+               [27] = SH_PFC_PIN_NONE,
+               [28] = SH_PFC_PIN_NONE,
+               [29] = SH_PFC_PIN_NONE,
+               [30] = SH_PFC_PIN_NONE,
+               [31] = SH_PFC_PIN_NONE,
+       } },
+       { PINMUX_BIAS_REG("PUEN5", 0xE60608C0, "PUD5", 0xE60608E0) {
+               [ 0] = RCAR_GP_PIN(5,  0),      /* AVB2_AVTP_PPS */
+               [ 1] = RCAR_GP_PIN(5,  1),      /* AVB0_AVTP_CAPTURE */
+               [ 2] = RCAR_GP_PIN(5,  2),      /* AVB2_AVTP_MATCH */
+               [ 3] = RCAR_GP_PIN(5,  3),      /* AVB2_LINK */
+               [ 4] = RCAR_GP_PIN(5,  4),      /* AVB2_PHY_INT */
+               [ 5] = RCAR_GP_PIN(5,  5),      /* AVB2_MAGIC */
+               [ 6] = RCAR_GP_PIN(5,  6),      /* AVB2_MDC */
+               [ 7] = RCAR_GP_PIN(5,  7),      /* AVB2_TXCREFCLK */
+               [ 8] = RCAR_GP_PIN(5,  8),      /* AVB2_TD3 */
+               [ 9] = RCAR_GP_PIN(5,  9),      /* AVB2_RD3 */
+               [10] = RCAR_GP_PIN(5, 10),      /* AVB2_MDIO */
+               [11] = RCAR_GP_PIN(5, 11),      /* AVB2_TD2 */
+               [12] = RCAR_GP_PIN(5, 12),      /* AVB2_TD1 */
+               [13] = RCAR_GP_PIN(5, 13),      /* AVB2_RD2 */
+               [14] = RCAR_GP_PIN(5, 14),      /* AVB2_RD1 */
+               [15] = RCAR_GP_PIN(5, 15),      /* AVB2_TD0 */
+               [16] = RCAR_GP_PIN(5, 16),      /* AVB2_TXC */
+               [17] = RCAR_GP_PIN(5, 17),      /* AVB2_RD0 */
+               [18] = RCAR_GP_PIN(5, 18),      /* AVB2_RXC */
+               [19] = RCAR_GP_PIN(5, 19),      /* AVB2_TX_CTL */
+               [20] = RCAR_GP_PIN(5, 20),      /* AVB2_RX_CTL */
+               [21] = SH_PFC_PIN_NONE,
+               [22] = SH_PFC_PIN_NONE,
+               [23] = SH_PFC_PIN_NONE,
+               [24] = SH_PFC_PIN_NONE,
+               [25] = SH_PFC_PIN_NONE,
+               [26] = SH_PFC_PIN_NONE,
+               [27] = SH_PFC_PIN_NONE,
+               [28] = SH_PFC_PIN_NONE,
+               [29] = SH_PFC_PIN_NONE,
+               [30] = SH_PFC_PIN_NONE,
+               [31] = SH_PFC_PIN_NONE,
+       } },
+       { PINMUX_BIAS_REG("PUEN6", 0xE60610C0, "PUD6", 0xE60610E0) {
+               [ 0] = RCAR_GP_PIN(6,  0),      /* AVB1_MDIO */
+               [ 1] = RCAR_GP_PIN(6,  1),      /* AVB1_MAGIC */
+               [ 2] = RCAR_GP_PIN(6,  2),      /* AVB1_MDC */
+               [ 3] = RCAR_GP_PIN(6,  3),      /* AVB1_PHY_INT */
+               [ 4] = RCAR_GP_PIN(6,  4),      /* AVB1_LINK */
+               [ 5] = RCAR_GP_PIN(6,  5),      /* AVB1_AVTP_MATCH */
+               [ 6] = RCAR_GP_PIN(6,  6),      /* AVB1_TXC */
+               [ 7] = RCAR_GP_PIN(6,  7),      /* AVB1_TX_CTL */
+               [ 8] = RCAR_GP_PIN(6,  8),      /* AVB1_RXC */
+               [ 9] = RCAR_GP_PIN(6,  9),      /* AVB1_RX_CTL */
+               [10] = RCAR_GP_PIN(6, 10),      /* AVB1_AVTP_PPS */
+               [11] = RCAR_GP_PIN(6, 11),      /* AVB1_AVTP_CAPTURE */
+               [12] = RCAR_GP_PIN(6, 12),      /* AVB1_TD1 */
+               [13] = RCAR_GP_PIN(6, 13),      /* AVB1_TD0 */
+               [14] = RCAR_GP_PIN(6, 14),      /* AVB1_RD1*/
+               [15] = RCAR_GP_PIN(6, 15),      /* AVB1_RD0 */
+               [16] = RCAR_GP_PIN(6, 16),      /* AVB1_TD2 */
+               [17] = RCAR_GP_PIN(6, 17),      /* AVB1_RD2 */
+               [18] = RCAR_GP_PIN(6, 18),      /* AVB1_TD3 */
+               [19] = RCAR_GP_PIN(6, 19),      /* AVB1_RD3 */
+               [20] = RCAR_GP_PIN(6, 20),      /* AVB1_TXCREFCLK */
+               [21] = SH_PFC_PIN_NONE,
+               [22] = SH_PFC_PIN_NONE,
+               [23] = SH_PFC_PIN_NONE,
+               [24] = SH_PFC_PIN_NONE,
+               [25] = SH_PFC_PIN_NONE,
+               [26] = SH_PFC_PIN_NONE,
+               [27] = SH_PFC_PIN_NONE,
+               [28] = SH_PFC_PIN_NONE,
+               [29] = SH_PFC_PIN_NONE,
+               [30] = SH_PFC_PIN_NONE,
+               [31] = SH_PFC_PIN_NONE,
+       } },
+       { PINMUX_BIAS_REG("PUEN7", 0xE60618C0, "PUD7", 0xE60618E0) {
+               [ 0] = RCAR_GP_PIN(7,  0),      /* AVB0_AVTP_PPS */
+               [ 1] = RCAR_GP_PIN(7,  1),      /* AVB0_AVTP_CAPTURE */
+               [ 2] = RCAR_GP_PIN(7,  2),      /* AVB0_AVTP_MATCH */
+               [ 3] = RCAR_GP_PIN(7,  3),      /* AVB0_TD3 */
+               [ 4] = RCAR_GP_PIN(7,  4),      /* AVB0_LINK */
+               [ 5] = RCAR_GP_PIN(7,  5),      /* AVB0_PHY_INT */
+               [ 6] = RCAR_GP_PIN(7,  6),      /* AVB0_TD2 */
+               [ 7] = RCAR_GP_PIN(7,  7),      /* AVB0_TD1 */
+               [ 8] = RCAR_GP_PIN(7,  8),      /* AVB0_RD3 */
+               [ 9] = RCAR_GP_PIN(7,  9),      /* AVB0_TXCREFCLK */
+               [10] = RCAR_GP_PIN(7, 10),      /* AVB0_MAGIC */
+               [11] = RCAR_GP_PIN(7, 11),      /* AVB0_TD0 */
+               [12] = RCAR_GP_PIN(7, 12),      /* AVB0_RD2 */
+               [13] = RCAR_GP_PIN(7, 13),      /* AVB0_MDC */
+               [14] = RCAR_GP_PIN(7, 14),      /* AVB0_MDIO */
+               [15] = RCAR_GP_PIN(7, 15),      /* AVB0_TXC */
+               [16] = RCAR_GP_PIN(7, 16),      /* AVB0_TX_CTL */
+               [17] = RCAR_GP_PIN(7, 17),      /* AVB0_RD1 */
+               [18] = RCAR_GP_PIN(7, 18),      /* AVB0_RD0 */
+               [19] = RCAR_GP_PIN(7, 19),      /* AVB0_RXC */
+               [20] = RCAR_GP_PIN(7, 20),      /* AVB0_RX_CTL */
+               [21] = SH_PFC_PIN_NONE,
+               [22] = SH_PFC_PIN_NONE,
+               [23] = SH_PFC_PIN_NONE,
+               [24] = SH_PFC_PIN_NONE,
+               [25] = SH_PFC_PIN_NONE,
+               [26] = SH_PFC_PIN_NONE,
+               [27] = SH_PFC_PIN_NONE,
+               [28] = SH_PFC_PIN_NONE,
+               [29] = SH_PFC_PIN_NONE,
+               [30] = SH_PFC_PIN_NONE,
+               [31] = SH_PFC_PIN_NONE,
+       } },
+       { PINMUX_BIAS_REG("PUEN8", 0xE60680C0, "PUD8", 0xE60680E0) {
+               [ 0] = RCAR_GP_PIN(8,  0),      /* SCL0 */
+               [ 1] = RCAR_GP_PIN(8,  1),      /* SDA0 */
+               [ 2] = RCAR_GP_PIN(8,  2),      /* SCL1 */
+               [ 3] = RCAR_GP_PIN(8,  3),      /* SDA1 */
+               [ 4] = RCAR_GP_PIN(8,  4),      /* SCL2 */
+               [ 5] = RCAR_GP_PIN(8,  5),      /* SDA2 */
+               [ 6] = RCAR_GP_PIN(8,  6),      /* SCL3 */
+               [ 7] = RCAR_GP_PIN(8,  7),      /* SDA3 */
+               [ 8] = RCAR_GP_PIN(8,  8),      /* SCL4 */
+               [ 9] = RCAR_GP_PIN(8,  9),      /* SDA4 */
+               [10] = RCAR_GP_PIN(8, 10),      /* SCL5 */
+               [11] = RCAR_GP_PIN(8, 11),      /* SDA5 */
+               [12] = RCAR_GP_PIN(8, 12),      /* GP8_12 */
+               [13] = RCAR_GP_PIN(8, 13),      /* GP8_13 */
+               [14] = SH_PFC_PIN_NONE,
+               [15] = SH_PFC_PIN_NONE,
+               [16] = SH_PFC_PIN_NONE,
+               [17] = SH_PFC_PIN_NONE,
+               [18] = SH_PFC_PIN_NONE,
+               [19] = SH_PFC_PIN_NONE,
+               [20] = SH_PFC_PIN_NONE,
+               [21] = SH_PFC_PIN_NONE,
+               [22] = SH_PFC_PIN_NONE,
+               [23] = SH_PFC_PIN_NONE,
+               [24] = SH_PFC_PIN_NONE,
+               [25] = SH_PFC_PIN_NONE,
+               [26] = SH_PFC_PIN_NONE,
+               [27] = SH_PFC_PIN_NONE,
+               [28] = SH_PFC_PIN_NONE,
+               [29] = SH_PFC_PIN_NONE,
+               [30] = SH_PFC_PIN_NONE,
+               [31] = SH_PFC_PIN_NONE,
+       } },
+       { /* sentinel */ },
+};
+
+static const struct sh_pfc_soc_operations r8a779g0_pin_ops = {
+       .pin_to_pocctrl = r8a779g0_pin_to_pocctrl,
+       .get_bias = rcar_pinmux_get_bias,
+       .set_bias = rcar_pinmux_set_bias,
+};
+
+const struct sh_pfc_soc_info r8a779g0_pinmux_info = {
+       .name = "r8a779g0_pfc",
+       .ops = &r8a779g0_pin_ops,
+       .unlock_reg = 0x1ff,    /* PMMRn mask */
+
+       .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+       .pins = pinmux_pins,
+       .nr_pins = ARRAY_SIZE(pinmux_pins),
+       .groups = pinmux_groups,
+       .nr_groups = ARRAY_SIZE(pinmux_groups),
+       .functions = pinmux_functions,
+       .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+       .cfg_regs = pinmux_config_regs,
+       .drive_regs = pinmux_drive_regs,
+       .bias_regs = pinmux_bias_regs,
+       .ioctrl_regs = pinmux_ioctrl_regs,
+
+       .pinmux_data = pinmux_data,
+       .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};

diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index 8f7f9a7..f6e8dd9 100644 (file)
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -43,6 +43,8 @@ enum sh_pfc_model {
        SH_PFC_R8A77990,
        SH_PFC_R8A77995,
        SH_PFC_R8A779A0,
+       SH_PFC_R8A779F0,
+       SH_PFC_R8A779G0,
 };
 
 struct sh_pfc_pin_config {
@@ -810,6 +812,8 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
        void __iomem *pocctrl;
        u32 addr, val;
        int bit, ret;
+       int idx = sh_pfc_get_pin_index(pfc, _pin);
+       const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
 
        if (!sh_pfc_pinconf_validate(pfc, _pin, param))
                return -ENOTSUPP;
@@ -842,13 +846,13 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
                        return bit;
                }
 
-               if (arg != 1800 && arg != 3300)
+               if (arg != 1800 && arg != 2500 && arg != 3300)
                        return -EINVAL;
 
                pocctrl = (void __iomem *)(uintptr_t)addr;
 
                val = sh_pfc_read_raw_reg(pocctrl, 32);
-               if (arg == 3300)
+               if (arg == ((pin->configs & SH_PFC_PIN_VOLTAGE_18_25) ? 2500 : 3300))
                        val |= BIT(bit);
                else
                        val &= ~BIT(bit);
@@ -1025,6 +1029,14 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev)
        if (model == SH_PFC_R8A779A0)
                priv->pfc.info = &r8a779a0_pinmux_info;
 #endif
+#ifdef CONFIG_PINCTRL_PFC_R8A779F0
+       if (model == SH_PFC_R8A779F0)
+               priv->pfc.info = &r8a779f0_pinmux_info;
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A779G0
+       if (model == SH_PFC_R8A779G0)
+               priv->pfc.info = &r8a779g0_pinmux_info;
+#endif
 
        priv->pmx.pfc = &priv->pfc;
        sh_pfc_init_ranges(&priv->pfc);
@@ -1142,6 +1154,18 @@ static const struct udevice_id sh_pfc_pinctrl_ids[] = {
                .data = SH_PFC_R8A779A0,
        },
 #endif
+#ifdef CONFIG_PINCTRL_PFC_R8A779F0
+       {
+               .compatible = "renesas,pfc-r8a779f0",
+               .data = SH_PFC_R8A779F0,
+       },
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A779G0
+       {
+               .compatible = "renesas,pfc-r8a779g0",
+               .data = SH_PFC_R8A779G0,
+       },
+#endif
 
        { },
 };

diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index 0ab743e..f35fd33 100644 (file)
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -31,11 +31,14 @@ enum {
 
 #define SH_PFC_PIN_VOLTAGE_18_33       (0 << 6)
 #define SH_PFC_PIN_VOLTAGE_25_33       (1 << 6)
+#define SH_PFC_PIN_VOLTAGE_18_25       (2 << 6)
 
 #define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33        (SH_PFC_PIN_CFG_IO_VOLTAGE | \
                                         SH_PFC_PIN_VOLTAGE_18_33)
 #define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33        (SH_PFC_PIN_CFG_IO_VOLTAGE | \
                                         SH_PFC_PIN_VOLTAGE_25_33)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_25        (SH_PFC_PIN_CFG_IO_VOLTAGE | \
+                                        SH_PFC_PIN_VOLTAGE_18_25)
 
 #define SH_PFC_PIN_CFG_NO_GPIO         (1 << 31)
 
@@ -309,6 +312,8 @@ extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
 extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
 extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
 extern const struct sh_pfc_soc_info r8a779a0_pinmux_info;
+extern const struct sh_pfc_soc_info r8a779f0_pinmux_info;
+extern const struct sh_pfc_soc_info r8a779g0_pinmux_info;
 
 /* -----------------------------------------------------------------------------
  * Helper macros to create pin and port lists

diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index 90461ae..c91f650 100644 (file)
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -15,5 +15,6 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
 obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
 obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
+obj-$(CONFIG_ROCKCHIP_RK3588) += pinctrl-rk3588.o
 obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
 obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o

diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
index 935aed9..314edb5 100644 (file)
--- a/drivers/pinctrl/rockchip/pinctrl-rk3568.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
@@ -13,6 +13,12 @@
 #include "pinctrl-rockchip.h"
 
 static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
+       MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(1, 0, 0)), /* PWM0 IO mux selection M0 */
+       MR_PMUGRF(RK_GPIO0, RK_PC7, RK_FUNC_2, 0x0110, RK_GENMASK_VAL(1, 0, 1)), /* PWM0 IO mux selection M1 */
+       MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(3, 2, 0)), /* PWM1 IO mux selection M0 */
+       MR_PMUGRF(RK_GPIO0, RK_PB5, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(3, 2, 1)), /* PWM1 IO mux selection M1 */
+       MR_PMUGRF(RK_GPIO0, RK_PC1, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(5, 4, 0)), /* PWM2 IO mux selection M0 */
+       MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(5, 4, 1)), /* PWM2 IO mux selection M1 */
        MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */
        MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */
        MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */
@@ -33,30 +39,22 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
        MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */
        MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */
        MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)), /* PWM4 IO mux selection M0 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)), /* PWM4 IO mux selection M1 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)), /* PWM5 IO mux selection M0 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)), /* PWM5 IO mux selection M1 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)), /* PWM6 IO mux selection M0 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)), /* PWM6 IO mux selection M1 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)), /* PWM7 IO mux selection M0 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)), /* PWM7 IO mux selection M1 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */
+       MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_5, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */
+       MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */
+       MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */
+       MR_TOPGRF(RK_GPIO1, RK_PD6, RK_FUNC_4, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */
+       MR_TOPGRF(RK_GPIO3, RK_PB5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */
+       MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */
+       MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */
+       MR_TOPGRF(RK_GPIO4, RK_PC0, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */
+       MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */
+       MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */
+       MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */
+       MR_TOPGRF(RK_GPIO4, RK_PC6, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */
+       MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */
+       MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */
+       MR_TOPGRF(RK_GPIO3, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */
+       MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */
        MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */
        MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */
        MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */
@@ -68,7 +66,7 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
        MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */
        MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */
        MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */
-       MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */
+       MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */
        MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */
        MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */
        MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */
@@ -81,7 +79,7 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
        MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */
        MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */
        MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */
-       MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */
+       MR_TOPGRF(RK_GPIO4, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */
        MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */
        MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */
        MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */
@@ -94,8 +92,11 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
        MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */
        MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */
        MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */
-       MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)), /* PDM IO mux selection M0 */
-       MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)), /* PDM IO mux selection M1 */
+       MR_TOPGRF(RK_GPIO1, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */
+       MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */
+       MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */
+       MR_TOPGRF(RK_GPIO4, RK_PA0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */
+       MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 2)), /* PDM IO mux selection M2 */
        MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */
        MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */
        MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */
@@ -237,6 +238,15 @@ static int rk3568_set_pull(struct rockchip_pin_bank *bank,
                return ret;
        }
 
+       /*
+        * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
+        * where that pull up value becomes 3.
+        */
+       if (bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
+               if (ret == 1)
+                       ret = 3;
+       }
+
        /* enable the write to the equivalent lower bits */
        data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
 

diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3588.c b/drivers/pinctrl/rockchip/pinctrl-rk3588.c
new file mode 100644 (file)
index 0000000..548cf09
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3588.c
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#include "pinctrl-rockchip.h"
+#include <dt-bindings/pinctrl/rockchip.h>
+
+static int rk3588_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+       struct rockchip_pinctrl_priv *priv = bank->priv;
+       struct regmap *regmap;
+       int iomux_num = (pin / 8);
+       int reg, ret, mask;
+       u8 bit;
+       u32 data;
+
+       debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
+
+       regmap = priv->regmap_base;
+       reg = bank->iomux[iomux_num].offset;
+       if ((pin % 8) >= 4)
+               reg += 0x4;
+       bit = (pin % 4) * 4;
+       mask = 0xf;
+
+       if (bank->bank_num == 0) {
+               if (pin >= RK_PB4 && pin <= RK_PD7) {
+                       if (mux < 8) {
+                               reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */
+                               data = (mask << (bit + 16));
+                               data |= (mux & mask) << bit;
+                               ret = regmap_write(regmap, reg, data);
+                       } else {
+                               u32 reg0 = 0;
+
+                               reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
+                               data = (mask << (bit + 16));
+                               data |= 8 << bit;
+                               ret = regmap_write(regmap, reg0, data);
+
+                               reg0 = reg + 0x8000; /* BUS_IOC_BASE */
+                               data = (mask << (bit + 16));
+                               data |= mux << bit;
+                               regmap = priv->regmap_base;
+                               regmap_write(regmap, reg0, data);
+                       }
+               } else {
+                       data = (mask << (bit + 16));
+                       data |= (mux & mask) << bit;
+                       ret = regmap_write(regmap, reg, data);
+               }
+               return ret;
+       } else if (bank->bank_num > 0) {
+               reg += 0x8000; /* BUS_IOC_BASE */
+       }
+
+       data = (mask << (bit + 16));
+       data |= (mux & mask) << bit;
+
+       return regmap_write(regmap, reg, data);
+}
+
+#define RK3588_PMU1_IOC_REG            (0x0000)
+#define RK3588_PMU2_IOC_REG            (0x4000)
+#define RK3588_BUS_IOC_REG             (0x8000)
+#define RK3588_VCCIO1_4_IOC_REG                (0x9000)
+#define RK3588_VCCIO3_5_IOC_REG                (0xA000)
+#define RK3588_VCCIO2_IOC_REG          (0xB000)
+#define RK3588_VCCIO6_IOC_REG          (0xC000)
+#define RK3588_EMMC_IOC_REG            (0xD000)
+
+static const u32 rk3588_ds_regs[][2] = {
+       {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
+       {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
+       {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
+       {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
+       {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
+       {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C},
+       {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020},
+       {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024},
+       {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020},
+       {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024},
+       {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028},
+       {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C},
+       {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030},
+       {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034},
+       {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038},
+       {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C},
+       {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040},
+       {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044},
+       {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048},
+       {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C},
+       {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050},
+       {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054},
+       {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058},
+       {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C},
+       {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060},
+       {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064},
+       {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068},
+       {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C},
+       {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070},
+       {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074},
+       {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078},
+       {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C},
+       {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080},
+       {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084},
+       {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088},
+       {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C},
+       {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090},
+       {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090},
+       {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094},
+       {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098},
+       {RK_GPIO4_D4, RK3588_VCCIO2_IOC_REG + 0x009C},
+};
+
+static const u32 rk3588_p_regs[][2] = {
+       {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020},
+       {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024},
+       {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028},
+       {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C},
+       {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030},
+       {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110},
+       {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114},
+       {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118},
+       {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C},
+       {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120},
+       {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0120},
+       {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124},
+       {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128},
+       {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C},
+       {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130},
+       {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134},
+       {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138},
+       {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C},
+       {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140},
+       {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144},
+       {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148},
+       {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148},
+       {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C},
+};
+
+static const u32 rk3588_smt_regs[][2] = {
+       {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030},
+       {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034},
+       {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040},
+       {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044},
+       {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048},
+       {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210},
+       {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214},
+       {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218},
+       {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C},
+       {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220},
+       {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0220},
+       {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224},
+       {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228},
+       {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C},
+       {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230},
+       {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234},
+       {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238},
+       {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C},
+       {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240},
+       {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244},
+       {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248},
+       {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248},
+       {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C},
+};
+
+#define RK3588_PULL_BITS_PER_PIN               2
+#define RK3588_PULL_PINS_PER_REG               8
+
+static void rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+                                        int pin_num, struct regmap **regmap,
+                                        int *reg, u8 *bit)
+{
+       struct rockchip_pinctrl_priv *info = bank->priv;
+       u8 bank_num = bank->bank_num;
+       u32 pin = bank_num * 32 + pin_num;
+       int i;
+
+       for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) {
+               if (pin >= rk3588_p_regs[i][0]) {
+                       *reg = rk3588_p_regs[i][1];
+                       break;
+               }
+       }
+
+       assert(i >= 0);
+
+       *regmap = info->regmap_base;
+       *bit = pin_num % RK3588_PULL_PINS_PER_REG;
+       *bit *= RK3588_PULL_BITS_PER_PIN;
+}
+
+#define RK3588_DRV_BITS_PER_PIN                4
+#define RK3588_DRV_PINS_PER_REG                4
+
+static void rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+                                       int pin_num, struct regmap **regmap,
+                                       int *reg, u8 *bit)
+{
+       struct rockchip_pinctrl_priv *info = bank->priv;
+       u8 bank_num = bank->bank_num;
+       u32 pin = bank_num * 32 + pin_num;
+       int i;
+
+       for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) {
+               if (pin >= rk3588_ds_regs[i][0]) {
+                       *reg = rk3588_ds_regs[i][1];
+                       break;
+               }
+       }
+
+       assert(i >= 0);
+
+       *regmap = info->regmap_base;
+       *bit = pin_num % RK3588_DRV_PINS_PER_REG;
+       *bit *= RK3588_DRV_BITS_PER_PIN;
+}
+
+#define RK3588_SMT_BITS_PER_PIN                1
+#define RK3588_SMT_PINS_PER_REG                8
+
+static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+                                          int pin_num, struct regmap **regmap,
+                                          int *reg, u8 *bit)
+{
+       struct rockchip_pinctrl_priv *info = bank->priv;
+       u8 bank_num = bank->bank_num;
+       u32 pin = bank_num * 32 + pin_num;
+       int i;
+
+       for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) {
+               if (pin >= rk3588_smt_regs[i][0]) {
+                       *reg = rk3588_smt_regs[i][1];
+                       break;
+               }
+       }
+
+       assert(i >= 0);
+
+       *regmap = info->regmap_base;
+       *bit = pin_num % RK3588_SMT_PINS_PER_REG;
+       *bit *= RK3588_SMT_BITS_PER_PIN;
+
+       return 0;
+}
+
+static int rk3588_set_pull(struct rockchip_pin_bank *bank,
+                          int pin_num, int pull)
+{
+       struct regmap *regmap;
+       int reg, translated_pull;
+       u8 bit, type;
+       u32 data;
+
+       rk3588_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+       type = bank->pull_type[pin_num / 8];
+       translated_pull = rockchip_translate_pull_value(type, pull);
+       if (translated_pull < 0) {
+               debug("unsupported pull setting %d\n", pull);
+               return -EINVAL;
+       }
+
+       /* enable the write to the equivalent lower bits */
+       data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+       data |= (translated_pull << bit);
+
+       return regmap_write(regmap, reg, data);
+}
+
+static int rk3588_set_drive(struct rockchip_pin_bank *bank,
+                           int pin_num, int strength)
+{
+       struct regmap *regmap;
+       int reg;
+       u32 data;
+       u8 bit;
+
+       rk3588_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+
+       /* enable the write to the equivalent lower bits */
+       data = ((1 << RK3588_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+       data |= (strength << bit);
+
+       return regmap_write(regmap, reg, data);
+}
+
+static int rk3588_set_schmitt(struct rockchip_pin_bank *bank,
+                             int pin_num, int enable)
+{
+       struct regmap *regmap;
+       int reg;
+       u32 data;
+       u8 bit;
+
+       rk3588_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+
+       /* enable the write to the equivalent lower bits */
+       data = ((1 << RK3588_SMT_BITS_PER_PIN) - 1) << (bit + 16);
+       data |= (enable << bit);
+
+       return regmap_write(regmap, reg, data);
+}
+
+static struct rockchip_pin_bank rk3588_pin_banks[] = {
+       RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
+                             IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
+       RK3588_PIN_BANK_FLAGS(1, 32, "gpio1",
+                             IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
+       RK3588_PIN_BANK_FLAGS(2, 32, "gpio2",
+                             IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
+       RK3588_PIN_BANK_FLAGS(3, 32, "gpio3",
+                             IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
+       RK3588_PIN_BANK_FLAGS(4, 32, "gpio4",
+                             IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
+};
+
+static const struct rockchip_pin_ctrl rk3588_pin_ctrl = {
+       .pin_banks              = rk3588_pin_banks,
+       .nr_banks               = ARRAY_SIZE(rk3588_pin_banks),
+       .nr_pins                = 160,
+       .set_mux                = rk3588_set_mux,
+       .set_pull               = rk3588_set_pull,
+       .set_drive              = rk3588_set_drive,
+       .set_schmitt            = rk3588_set_schmitt,
+};
+
+static const struct udevice_id rk3588_pinctrl_ids[] = {
+       {
+               .compatible = "rockchip,rk3588-pinctrl",
+               .data = (ulong)&rk3588_pin_ctrl
+       },
+       { }
+};
+
+U_BOOT_DRIVER(pinctrl_rk3588) = {
+       .name           = "rockchip_rk3588_pinctrl",
+       .id             = UCLASS_PINCTRL,
+       .of_match       = rk3588_pinctrl_ids,
+       .priv_auto      = sizeof(struct rockchip_pinctrl_priv),
+       .ops            = &rockchip_pinctrl_ops,
+#if CONFIG_IS_ENABLED(OF_REAL)
+       .bind           = dm_scan_fdt_dev,
+#endif
+       .probe          = rockchip_pinctrl_probe,
+};

diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
index 8dfaba5..df7bc68 100644 (file)
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
@@ -9,6 +9,171 @@
 #include <linux/bitops.h>
 #include <linux/types.h>
 
+#define RK_GPIO0_A0    0
+#define RK_GPIO0_A1    1
+#define RK_GPIO0_A2    2
+#define RK_GPIO0_A3    3
+#define RK_GPIO0_A4    4
+#define RK_GPIO0_A5    5
+#define RK_GPIO0_A6    6
+#define RK_GPIO0_A7    7
+#define RK_GPIO0_B0    8
+#define RK_GPIO0_B1    9
+#define RK_GPIO0_B2    10
+#define RK_GPIO0_B3    11
+#define RK_GPIO0_B4    12
+#define RK_GPIO0_B5    13
+#define RK_GPIO0_B6    14
+#define RK_GPIO0_B7    15
+#define RK_GPIO0_C0    16
+#define RK_GPIO0_C1    17
+#define RK_GPIO0_C2    18
+#define RK_GPIO0_C3    19
+#define RK_GPIO0_C4    20
+#define RK_GPIO0_C5    21
+#define RK_GPIO0_C6    22
+#define RK_GPIO0_C7    23
+#define RK_GPIO0_D0    24
+#define RK_GPIO0_D1    25
+#define RK_GPIO0_D2    26
+#define RK_GPIO0_D3    27
+#define RK_GPIO0_D4    28
+#define RK_GPIO0_D5    29
+#define RK_GPIO0_D6    30
+#define RK_GPIO0_D7    31
+
+#define RK_GPIO1_A0    32
+#define RK_GPIO1_A1    33
+#define RK_GPIO1_A2    34
+#define RK_GPIO1_A3    35
+#define RK_GPIO1_A4    36
+#define RK_GPIO1_A5    37
+#define RK_GPIO1_A6    38
+#define RK_GPIO1_A7    39
+#define RK_GPIO1_B0    40
+#define RK_GPIO1_B1    41
+#define RK_GPIO1_B2    42
+#define RK_GPIO1_B3    43
+#define RK_GPIO1_B4    44
+#define RK_GPIO1_B5    45
+#define RK_GPIO1_B6    46
+#define RK_GPIO1_B7    47
+#define RK_GPIO1_C0    48
+#define RK_GPIO1_C1    49
+#define RK_GPIO1_C2    50
+#define RK_GPIO1_C3    51
+#define RK_GPIO1_C4    52
+#define RK_GPIO1_C5    53
+#define RK_GPIO1_C6    54
+#define RK_GPIO1_C7    55
+#define RK_GPIO1_D0    56
+#define RK_GPIO1_D1    57
+#define RK_GPIO1_D2    58
+#define RK_GPIO1_D3    59
+#define RK_GPIO1_D4    60
+#define RK_GPIO1_D5    61
+#define RK_GPIO1_D6    62
+#define RK_GPIO1_D7    63
+
+#define RK_GPIO2_A0    64
+#define RK_GPIO2_A1    65
+#define RK_GPIO2_A2    66
+#define RK_GPIO2_A3    67
+#define RK_GPIO2_A4    68
+#define RK_GPIO2_A5    69
+#define RK_GPIO2_A6    70
+#define RK_GPIO2_A7    71
+#define RK_GPIO2_B0    72
+#define RK_GPIO2_B1    73
+#define RK_GPIO2_B2    74
+#define RK_GPIO2_B3    75
+#define RK_GPIO2_B4    76
+#define RK_GPIO2_B5    77
+#define RK_GPIO2_B6    78
+#define RK_GPIO2_B7    79
+#define RK_GPIO2_C0    80
+#define RK_GPIO2_C1    81
+#define RK_GPIO2_C2    82
+#define RK_GPIO2_C3    83
+#define RK_GPIO2_C4    84
+#define RK_GPIO2_C5    85
+#define RK_GPIO2_C6    86
+#define RK_GPIO2_C7    87
+#define RK_GPIO2_D0    88
+#define RK_GPIO2_D1    89
+#define RK_GPIO2_D2    90
+#define RK_GPIO2_D3    91
+#define RK_GPIO2_D4    92
+#define RK_GPIO2_D5    93
+#define RK_GPIO2_D6    94
+#define RK_GPIO2_D7    95
+
+#define RK_GPIO3_A0    96
+#define RK_GPIO3_A1    97
+#define RK_GPIO3_A2    98
+#define RK_GPIO3_A3    99
+#define RK_GPIO3_A4    100
+#define RK_GPIO3_A5    101
+#define RK_GPIO3_A6    102
+#define RK_GPIO3_A7    103
+#define RK_GPIO3_B0    104
+#define RK_GPIO3_B1    105
+#define RK_GPIO3_B2    106
+#define RK_GPIO3_B3    107
+#define RK_GPIO3_B4    108
+#define RK_GPIO3_B5    109
+#define RK_GPIO3_B6    110
+#define RK_GPIO3_B7    111
+#define RK_GPIO3_C0    112
+#define RK_GPIO3_C1    113
+#define RK_GPIO3_C2    114
+#define RK_GPIO3_C3    115
+#define RK_GPIO3_C4    116
+#define RK_GPIO3_C5    117
+#define RK_GPIO3_C6    118
+#define RK_GPIO3_C7    119
+#define RK_GPIO3_D0    120
+#define RK_GPIO3_D1    121
+#define RK_GPIO3_D2    122
+#define RK_GPIO3_D3    123
+#define RK_GPIO3_D4    124
+#define RK_GPIO3_D5    125
+#define RK_GPIO3_D6    126
+#define RK_GPIO3_D7    127
+
+#define RK_GPIO4_A0    128
+#define RK_GPIO4_A1    129
+#define RK_GPIO4_A2    130
+#define RK_GPIO4_A3    131
+#define RK_GPIO4_A4    132
+#define RK_GPIO4_A5    133
+#define RK_GPIO4_A6    134
+#define RK_GPIO4_A7    135
+#define RK_GPIO4_B0    136
+#define RK_GPIO4_B1    137
+#define RK_GPIO4_B2    138
+#define RK_GPIO4_B3    139
+#define RK_GPIO4_B4    140
+#define RK_GPIO4_B5    141
+#define RK_GPIO4_B6    142
+#define RK_GPIO4_B7    143
+#define RK_GPIO4_C0    144
+#define RK_GPIO4_C1    145
+#define RK_GPIO4_C2    146
+#define RK_GPIO4_C3    147
+#define RK_GPIO4_C4    148
+#define RK_GPIO4_C5    149
+#define RK_GPIO4_C6    150
+#define RK_GPIO4_C7    151
+#define RK_GPIO4_D0    152
+#define RK_GPIO4_D1    153
+#define RK_GPIO4_D2    154
+#define RK_GPIO4_D3    155
+#define RK_GPIO4_D4    156
+#define RK_GPIO4_D5    157
+#define RK_GPIO4_D6    158
+#define RK_GPIO4_D7    159
+
 #define RK_GENMASK_VAL(h, l, v) \
        (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
 
@@ -180,6 +345,25 @@ struct rockchip_pin_bank {
                },                                                      \
        }
 
+#define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1,   \
+                                       iom2, iom3, pull0, pull1,       \
+                                       pull2, pull3)                   \
+       {                                                               \
+               .bank_num       = id,                                   \
+               .nr_pins        = pins,                                 \
+               .name           = label,                                \
+               .iomux          = {                                     \
+                       { .type = iom0, .offset = -1 },                 \
+                       { .type = iom1, .offset = -1 },                 \
+                       { .type = iom2, .offset = -1 },                 \
+                       { .type = iom3, .offset = -1 },                 \
+               },                                                      \
+               .pull_type[0] = pull0,                                  \
+               .pull_type[1] = pull1,                                  \
+               .pull_type[2] = pull2,                                  \
+               .pull_type[3] = pull3,                                  \
+       }
+
 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1,     \
                                      drv2, drv3, pull0, pull1,         \
                                      pull2, pull3)                     \
@@ -274,6 +458,9 @@ struct rockchip_pin_bank {
 #define MR_PMUGRF(ID, PIN, FUNC, REG, VAL)     \
        PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF)
 
+#define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P)                    \
+       PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
+
 /**
  * struct rockchip_mux_recalced_data: recalculate a pin iomux data.
  * @num: bank number.

diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
new file mode 100644 (file)
index 0000000..1b859c8
--- /dev/null
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config SPL_PINCTRL_STARFIVE
+       bool "Support Pinctrl driver for StarFive SoC in SPL"
+       depends on SPL_PINCTRL_FULL && STARFIVE_JH7110
+       help
+         Enable support pin control driver for StarFive SoC.
+
+config SPL_PINCTRL_STARFIVE_JH7110
+       bool "Support Pinctrl and GPIO driver for StarFive JH7110 SoC in SPL"
+       depends on  SPL_PINCTRL_STARFIVE
+       help
+         Enable support pinctrl and gpio driver for StarFive JH7110 in SPL.
+
+config PINCTRL_STARFIVE
+       bool "Pinctrl driver for StarFive SoC"
+       depends on PINCTRL_FULL && STARFIVE_JH7110
+       help
+         Say yes here to support pin control on the StarFive RISC-V SoC.
+         This also provides an interface to the GPIO pins not used by other
+         peripherals supporting inputs, outputs, configuring pull-up/pull-down
+         and interrupts on input changes.
+
+config PINCTRL_STARFIVE_JH7110
+       bool "Pinctrl and GPIO driver for StarFive JH7110 SoC"
+       depends on  PINCTRL_STARFIVE
+       help
+         This selects the pinctrl driver for JH7110 starfive.

diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
new file mode 100644 (file)
index 0000000..a4a1206
--- /dev/null
+++ b/drivers/pinctrl/starfive/Makefile
@@ -0,0 +1,6 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_$(SPL_TPL_)PINCTRL_STARFIVE) += pinctrl-starfive.o
+# SoC Drivers
+obj-$(CONFIG_$(SPL_TPL_)PINCTRL_STARFIVE_JH7110)       += pinctrl-jh7110-sys.o pinctrl-jh7110-aon.o

diff --git a/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c b/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
new file mode 100644 (file)
index 0000000..2d73990
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ *   Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
+ *   Author: Jianlong Huang <jianlong.huang@starfivetech.com>
+ */
+
+#include <dm/read.h>
+#include <dm/device_compat.h>
+#include <linux/io.h>
+
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+#include "pinctrl-starfive.h"
+
+#define JH7110_AON_NGPIO               4
+#define JH7110_AON_GC_BASE             64
+
+/* registers */
+#define JH7110_AON_DOEN                0x0
+#define JH7110_AON_DOUT                0x4
+#define JH7110_AON_GPI                 0x8
+#define JH7110_AON_GPIOIN              0x2c
+
+#define JH7110_AON_GPIOEN              0xc
+#define JH7110_AON_GPIOIS              0x10
+#define JH7110_AON_GPIOIC              0x14
+#define JH7110_AON_GPIOIBE             0x18
+#define JH7110_AON_GPIOIEV             0x1c
+#define JH7110_AON_GPIOIE              0x20
+#define JH7110_AON_GPIORIS             0x28
+#define JH7110_AON_GPIOMIS             0x28
+
+#define AON_GPO_PDA_0_5_CFG            0x30
+
+static int jh7110_aon_set_one_pin_mux(struct udevice *dev, unsigned int pin,
+                                     unsigned int din, u32 dout,
+                                     u32 doen, u32 func)
+{
+       struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+
+       if (pin < priv->info->ngpios && func == 0)
+               starfive_set_gpiomux(dev, pin, din, dout, doen);
+
+       return 0;
+}
+
+static int jh7110_aon_get_padcfg_base(struct udevice *dev,
+                                     unsigned int pin)
+{
+       if (pin < PAD_GMAC0_MDC)
+               return AON_GPO_PDA_0_5_CFG;
+
+       return -1;
+}
+
+static void jh7110_aon_init_hw(struct udevice *dev)
+{
+       struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+
+       /* mask all GPIO interrupts */
+       writel(0, priv->base + JH7110_AON_GPIOIE);
+       /* clear edge interrupt flags */
+       writel(0, priv->base + JH7110_AON_GPIOIC);
+       writel(0x0f, priv->base + JH7110_AON_GPIOIC);
+       /* enable GPIO interrupts */
+       writel(1, priv->base + JH7110_AON_GPIOEN);
+}
+
+const struct starfive_pinctrl_soc_info jh7110_aon_pinctrl_info = {
+       /* pin conf */
+       .set_one_pinmux = jh7110_aon_set_one_pin_mux,
+       .get_padcfg_base  = jh7110_aon_get_padcfg_base,
+
+       /* gpio dout/doen/din/gpioinput register */
+       .dout_reg_base = JH7110_AON_DOUT,
+       .dout_mask = GENMASK(3, 0),
+       .doen_reg_base = JH7110_AON_DOEN,
+       .doen_mask = GENMASK(2, 0),
+       .gpi_reg_base = JH7110_AON_GPI,
+       .gpi_mask = GENMASK(3, 0),
+       .gpioin_reg_base = JH7110_AON_GPIOIN,
+
+       /* gpio */
+       .gpio_bank_name = "RGPIO",
+       .ngpios = JH7110_AON_NGPIO,
+       .gpio_init_hw = jh7110_aon_init_hw,
+};
+
+static int jh7110_aon_pinctrl_probe(struct udevice *dev)
+{
+       struct starfive_pinctrl_soc_info *info =
+               (struct starfive_pinctrl_soc_info *)dev_get_driver_data(dev);
+
+       return starfive_pinctrl_probe(dev, info);
+}
+
+static const struct udevice_id jh7110_aon_pinctrl_ids[] = {
+       /* JH7110 aon pinctrl */
+       { .compatible = "starfive,jh7110-aon-pinctrl",
+         .data = (ulong)&jh7110_aon_pinctrl_info, },
+       { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(jh7110_aon_pinctrl) = {
+       .name           = "jh7110-aon-pinctrl",
+       .id             = UCLASS_PINCTRL,
+       .of_match       = jh7110_aon_pinctrl_ids,
+       .priv_auto      = sizeof(struct starfive_pinctrl_priv),
+       .ops            = &starfive_pinctrl_ops,
+       .probe          = jh7110_aon_pinctrl_probe,
+};

diff --git a/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
new file mode 100644 (file)
index 0000000..dafba65
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
@@ -0,0 +1,399 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ *   Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
+ *   Author: Jianlong Huang <jianlong.huang@starfivetech.com>
+ */
+
+#include <dm/read.h>
+#include <dm/device_compat.h>
+#include <linux/io.h>
+
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+#include "pinctrl-starfive.h"
+
+#define JH7110_SYS_NGPIO               64
+#define JH7110_SYS_GC_BASE             0
+
+/* registers */
+#define JH7110_SYS_DOEN                0x000
+#define JH7110_SYS_DOUT                0x040
+#define JH7110_SYS_GPI                 0x080
+#define JH7110_SYS_GPIOIN              0x118
+
+#define JH7110_SYS_GPIOEN              0x0dc
+#define JH7110_SYS_GPIOIS0             0x0e0
+#define JH7110_SYS_GPIOIS1             0x0e4
+#define JH7110_SYS_GPIOIC0             0x0e8
+#define JH7110_SYS_GPIOIC1             0x0ec
+#define JH7110_SYS_GPIOIBE0            0x0f0
+#define JH7110_SYS_GPIOIBE1            0x0f4
+#define JH7110_SYS_GPIOIEV0            0x0f8
+#define JH7110_SYS_GPIOIEV1            0x0fc
+#define JH7110_SYS_GPIOIE0             0x100
+#define JH7110_SYS_GPIOIE1             0x104
+#define JH7110_SYS_GPIORIS0            0x108
+#define JH7110_SYS_GPIORIS1            0x10c
+#define JH7110_SYS_GPIOMIS0            0x110
+#define JH7110_SYS_GPIOMIS1            0x114
+
+#define SYS_GPO_PDA_0_74_CFG           0x120
+#define SYS_GPO_PDA_89_94_CFG          0x284
+
+static const struct starfive_pinctrl_pin jh7110_sys_pins[] = {
+       STARFIVE_PINCTRL(PAD_GPIO0,             "GPIO0"),
+       STARFIVE_PINCTRL(PAD_GPIO1,             "GPIO1"),
+       STARFIVE_PINCTRL(PAD_GPIO2,             "GPIO2"),
+       STARFIVE_PINCTRL(PAD_GPIO3,             "GPIO3"),
+       STARFIVE_PINCTRL(PAD_GPIO4,             "GPIO4"),
+       STARFIVE_PINCTRL(PAD_GPIO5,             "GPIO5"),
+       STARFIVE_PINCTRL(PAD_GPIO6,             "GPIO6"),
+       STARFIVE_PINCTRL(PAD_GPIO7,             "GPIO7"),
+       STARFIVE_PINCTRL(PAD_GPIO8,             "GPIO8"),
+       STARFIVE_PINCTRL(PAD_GPIO9,             "GPIO9"),
+       STARFIVE_PINCTRL(PAD_GPIO10,            "GPIO10"),
+       STARFIVE_PINCTRL(PAD_GPIO11,            "GPIO11"),
+       STARFIVE_PINCTRL(PAD_GPIO12,            "GPIO12"),
+       STARFIVE_PINCTRL(PAD_GPIO13,            "GPIO13"),
+       STARFIVE_PINCTRL(PAD_GPIO14,            "GPIO14"),
+       STARFIVE_PINCTRL(PAD_GPIO15,            "GPIO15"),
+       STARFIVE_PINCTRL(PAD_GPIO16,            "GPIO16"),
+       STARFIVE_PINCTRL(PAD_GPIO17,            "GPIO17"),
+       STARFIVE_PINCTRL(PAD_GPIO18,            "GPIO18"),
+       STARFIVE_PINCTRL(PAD_GPIO19,            "GPIO19"),
+       STARFIVE_PINCTRL(PAD_GPIO20,            "GPIO20"),
+       STARFIVE_PINCTRL(PAD_GPIO21,            "GPIO21"),
+       STARFIVE_PINCTRL(PAD_GPIO22,            "GPIO22"),
+       STARFIVE_PINCTRL(PAD_GPIO23,            "GPIO23"),
+       STARFIVE_PINCTRL(PAD_GPIO24,            "GPIO24"),
+       STARFIVE_PINCTRL(PAD_GPIO25,            "GPIO25"),
+       STARFIVE_PINCTRL(PAD_GPIO26,            "GPIO26"),
+       STARFIVE_PINCTRL(PAD_GPIO27,            "GPIO27"),
+       STARFIVE_PINCTRL(PAD_GPIO28,            "GPIO28"),
+       STARFIVE_PINCTRL(PAD_GPIO29,            "GPIO29"),
+       STARFIVE_PINCTRL(PAD_GPIO30,            "GPIO30"),
+       STARFIVE_PINCTRL(PAD_GPIO31,            "GPIO31"),
+       STARFIVE_PINCTRL(PAD_GPIO32,            "GPIO32"),
+       STARFIVE_PINCTRL(PAD_GPIO33,            "GPIO33"),
+       STARFIVE_PINCTRL(PAD_GPIO34,            "GPIO34"),
+       STARFIVE_PINCTRL(PAD_GPIO35,            "GPIO35"),
+       STARFIVE_PINCTRL(PAD_GPIO36,            "GPIO36"),
+       STARFIVE_PINCTRL(PAD_GPIO37,            "GPIO37"),
+       STARFIVE_PINCTRL(PAD_GPIO38,            "GPIO38"),
+       STARFIVE_PINCTRL(PAD_GPIO39,            "GPIO39"),
+       STARFIVE_PINCTRL(PAD_GPIO40,            "GPIO40"),
+       STARFIVE_PINCTRL(PAD_GPIO41,            "GPIO41"),
+       STARFIVE_PINCTRL(PAD_GPIO42,            "GPIO42"),
+       STARFIVE_PINCTRL(PAD_GPIO43,            "GPIO43"),
+       STARFIVE_PINCTRL(PAD_GPIO44,            "GPIO44"),
+       STARFIVE_PINCTRL(PAD_GPIO45,            "GPIO45"),
+       STARFIVE_PINCTRL(PAD_GPIO46,            "GPIO46"),
+       STARFIVE_PINCTRL(PAD_GPIO47,            "GPIO47"),
+       STARFIVE_PINCTRL(PAD_GPIO48,            "GPIO48"),
+       STARFIVE_PINCTRL(PAD_GPIO49,            "GPIO49"),
+       STARFIVE_PINCTRL(PAD_GPIO50,            "GPIO50"),
+       STARFIVE_PINCTRL(PAD_GPIO51,            "GPIO51"),
+       STARFIVE_PINCTRL(PAD_GPIO52,            "GPIO52"),
+       STARFIVE_PINCTRL(PAD_GPIO53,            "GPIO53"),
+       STARFIVE_PINCTRL(PAD_GPIO54,            "GPIO54"),
+       STARFIVE_PINCTRL(PAD_GPIO55,            "GPIO55"),
+       STARFIVE_PINCTRL(PAD_GPIO56,            "GPIO56"),
+       STARFIVE_PINCTRL(PAD_GPIO57,            "GPIO57"),
+       STARFIVE_PINCTRL(PAD_GPIO58,            "GPIO58"),
+       STARFIVE_PINCTRL(PAD_GPIO59,            "GPIO59"),
+       STARFIVE_PINCTRL(PAD_GPIO60,            "GPIO60"),
+       STARFIVE_PINCTRL(PAD_GPIO61,            "GPIO61"),
+       STARFIVE_PINCTRL(PAD_GPIO62,            "GPIO62"),
+       STARFIVE_PINCTRL(PAD_GPIO63,            "GPIO63"),
+       STARFIVE_PINCTRL(PAD_SD0_CLK,           "SD0_CLK"),
+       STARFIVE_PINCTRL(PAD_SD0_CMD,           "SD0_CMD"),
+       STARFIVE_PINCTRL(PAD_SD0_DATA0,         "SD0_DATA0"),
+       STARFIVE_PINCTRL(PAD_SD0_DATA1,         "SD0_DATA1"),
+       STARFIVE_PINCTRL(PAD_SD0_DATA2,         "SD0_DATA2"),
+       STARFIVE_PINCTRL(PAD_SD0_DATA3,         "SD0_DATA3"),
+       STARFIVE_PINCTRL(PAD_SD0_DATA4,         "SD0_DATA4"),
+       STARFIVE_PINCTRL(PAD_SD0_DATA5,         "SD0_DATA5"),
+       STARFIVE_PINCTRL(PAD_SD0_DATA6,         "SD0_DATA6"),
+       STARFIVE_PINCTRL(PAD_SD0_DATA7,         "SD0_DATA7"),
+       STARFIVE_PINCTRL(PAD_SD0_STRB,          "SD0_STRB"),
+       STARFIVE_PINCTRL(PAD_GMAC1_MDC,         "GMAC1_MDC"),
+       STARFIVE_PINCTRL(PAD_GMAC1_MDIO,        "GMAC1_MDIO"),
+       STARFIVE_PINCTRL(PAD_GMAC1_RXD0,        "GMAC1_RXD0"),
+       STARFIVE_PINCTRL(PAD_GMAC1_RXD1,        "GMAC1_RXD1"),
+       STARFIVE_PINCTRL(PAD_GMAC1_RXD2,        "GMAC1_RXD2"),
+       STARFIVE_PINCTRL(PAD_GMAC1_RXD3,        "GMAC1_RXD3"),
+       STARFIVE_PINCTRL(PAD_GMAC1_RXDV,        "GMAC1_RXDV"),
+       STARFIVE_PINCTRL(PAD_GMAC1_RXC,         "GMAC1_RXC"),
+       STARFIVE_PINCTRL(PAD_GMAC1_TXD0,        "GMAC1_TXD0"),
+       STARFIVE_PINCTRL(PAD_GMAC1_TXD1,        "GMAC1_TXD1"),
+       STARFIVE_PINCTRL(PAD_GMAC1_TXD2,        "GMAC1_TXD2"),
+       STARFIVE_PINCTRL(PAD_GMAC1_TXD3,        "GMAC1_TXD3"),
+       STARFIVE_PINCTRL(PAD_GMAC1_TXEN,        "GMAC1_TXEN"),
+       STARFIVE_PINCTRL(PAD_GMAC1_TXC,         "GMAC1_TXC"),
+       STARFIVE_PINCTRL(PAD_QSPI_SCLK,         "QSPI_SCLK"),
+       STARFIVE_PINCTRL(PAD_QSPI_CS0,          "QSPI_CS0"),
+       STARFIVE_PINCTRL(PAD_QSPI_DATA0,        "QSPI_DATA0"),
+       STARFIVE_PINCTRL(PAD_QSPI_DATA1,        "QSPI_DATA1"),
+       STARFIVE_PINCTRL(PAD_QSPI_DATA2,        "QSPI_DATA2"),
+       STARFIVE_PINCTRL(PAD_QSPI_DATA3,        "QSPI_DATA3"),
+};
+
+struct jh7110_func_sel {
+       u16 offset;
+       u8 shift;
+       u8 max;
+};
+
+static const struct jh7110_func_sel
+       jh7110_sys_func_sel[ARRAY_SIZE(jh7110_sys_pins)] = {
+       [PAD_GMAC1_RXC] = { 0x29c,  0, 1 },
+       [PAD_GPIO10]    = { 0x29c,  2, 3 },
+       [PAD_GPIO11]    = { 0x29c,  5, 3 },
+       [PAD_GPIO12]    = { 0x29c,  8, 3 },
+       [PAD_GPIO13]    = { 0x29c, 11, 3 },
+       [PAD_GPIO14]    = { 0x29c, 14, 3 },
+       [PAD_GPIO15]    = { 0x29c, 17, 3 },
+       [PAD_GPIO16]    = { 0x29c, 20, 3 },
+       [PAD_GPIO17]    = { 0x29c, 23, 3 },
+       [PAD_GPIO18]    = { 0x29c, 26, 3 },
+       [PAD_GPIO19]    = { 0x29c, 29, 3 },
+
+       [PAD_GPIO20]    = { 0x2a0,  0, 3 },
+       [PAD_GPIO21]    = { 0x2a0,  3, 3 },
+       [PAD_GPIO22]    = { 0x2a0,  6, 3 },
+       [PAD_GPIO23]    = { 0x2a0,  9, 3 },
+       [PAD_GPIO24]    = { 0x2a0, 12, 3 },
+       [PAD_GPIO25]    = { 0x2a0, 15, 3 },
+       [PAD_GPIO26]    = { 0x2a0, 18, 3 },
+       [PAD_GPIO27]    = { 0x2a0, 21, 3 },
+       [PAD_GPIO28]    = { 0x2a0, 24, 3 },
+       [PAD_GPIO29]    = { 0x2a0, 27, 3 },
+
+       [PAD_GPIO30]    = { 0x2a4,  0, 3 },
+       [PAD_GPIO31]    = { 0x2a4,  3, 3 },
+       [PAD_GPIO32]    = { 0x2a4,  6, 3 },
+       [PAD_GPIO33]    = { 0x2a4,  9, 3 },
+       [PAD_GPIO34]    = { 0x2a4, 12, 3 },
+       [PAD_GPIO35]    = { 0x2a4, 15, 3 },
+       [PAD_GPIO36]    = { 0x2a4, 17, 3 },
+       [PAD_GPIO37]    = { 0x2a4, 20, 3 },
+       [PAD_GPIO38]    = { 0x2a4, 23, 3 },
+       [PAD_GPIO39]    = { 0x2a4, 26, 3 },
+       [PAD_GPIO40]    = { 0x2a4, 29, 3 },
+
+       [PAD_GPIO41]    = { 0x2a8,  0, 3 },
+       [PAD_GPIO42]    = { 0x2a8,  3, 3 },
+       [PAD_GPIO43]    = { 0x2a8,  6, 3 },
+       [PAD_GPIO44]    = { 0x2a8,  9, 3 },
+       [PAD_GPIO45]    = { 0x2a8, 12, 3 },
+       [PAD_GPIO46]    = { 0x2a8, 15, 3 },
+       [PAD_GPIO47]    = { 0x2a8, 18, 3 },
+       [PAD_GPIO48]    = { 0x2a8, 21, 3 },
+       [PAD_GPIO49]    = { 0x2a8, 24, 3 },
+       [PAD_GPIO50]    = { 0x2a8, 27, 3 },
+       [PAD_GPIO51]    = { 0x2a8, 30, 3 },
+
+       [PAD_GPIO52]    = { 0x2ac,  0, 3 },
+       [PAD_GPIO53]    = { 0x2ac,  2, 3 },
+       [PAD_GPIO54]    = { 0x2ac,  4, 3 },
+       [PAD_GPIO55]    = { 0x2ac,  6, 3 },
+       [PAD_GPIO56]    = { 0x2ac,  9, 3 },
+       [PAD_GPIO57]    = { 0x2ac, 12, 3 },
+       [PAD_GPIO58]    = { 0x2ac, 15, 3 },
+       [PAD_GPIO59]    = { 0x2ac, 18, 3 },
+       [PAD_GPIO60]    = { 0x2ac, 21, 3 },
+       [PAD_GPIO61]    = { 0x2ac, 24, 3 },
+       [PAD_GPIO62]    = { 0x2ac, 27, 3 },
+       [PAD_GPIO63]    = { 0x2ac, 30, 3 },
+
+       [PAD_GPIO6]     = { 0x2b0,  0, 3 },
+       [PAD_GPIO7]     = { 0x2b0,  2, 3 },
+       [PAD_GPIO8]     = { 0x2b0,  5, 3 },
+       [PAD_GPIO9]     = { 0x2b0,  8, 3 },
+};
+
+struct jh7110_vin_group_sel {
+       u16 offset;
+       u8 shift;
+       u8 group;
+};
+
+static const struct jh7110_vin_group_sel
+       jh7110_sys_vin_group_sel[ARRAY_SIZE(jh7110_sys_pins)] = {
+       [PAD_GPIO6]     = { 0x2b4, 21, 0 },
+       [PAD_GPIO7]     = { 0x2b4, 18, 0 },
+       [PAD_GPIO8]     = { 0x2b4, 15, 0 },
+       [PAD_GPIO9]     = { 0x2b0, 11, 0 },
+       [PAD_GPIO10]    = { 0x2b0, 20, 0 },
+       [PAD_GPIO11]    = { 0x2b0, 23, 0 },
+       [PAD_GPIO12]    = { 0x2b0, 26, 0 },
+       [PAD_GPIO13]    = { 0x2b0, 29, 0 },
+       [PAD_GPIO14]    = { 0x2b4,  0, 0 },
+       [PAD_GPIO15]    = { 0x2b4,  3, 0 },
+       [PAD_GPIO16]    = { 0x2b4,  6, 0 },
+       [PAD_GPIO17]    = { 0x2b4,  9, 0 },
+       [PAD_GPIO18]    = { 0x2b4, 12, 0 },
+       [PAD_GPIO19]    = { 0x2b0, 14, 0 },
+       [PAD_GPIO20]    = { 0x2b0, 17, 0 },
+
+       [PAD_GPIO21]    = { 0x2b4, 21, 1 },
+       [PAD_GPIO22]    = { 0x2b4, 18, 1 },
+       [PAD_GPIO23]    = { 0x2b4, 15, 1 },
+       [PAD_GPIO24]    = { 0x2b0, 11, 1 },
+       [PAD_GPIO25]    = { 0x2b0, 20, 1 },
+       [PAD_GPIO26]    = { 0x2b0, 23, 1 },
+       [PAD_GPIO27]    = { 0x2b0, 26, 1 },
+       [PAD_GPIO28]    = { 0x2b0, 29, 1 },
+       [PAD_GPIO29]    = { 0x2b4,  0, 1 },
+       [PAD_GPIO30]    = { 0x2b4,  3, 1 },
+       [PAD_GPIO31]    = { 0x2b4,  6, 1 },
+       [PAD_GPIO32]    = { 0x2b4,  9, 1 },
+       [PAD_GPIO33]    = { 0x2b4, 12, 1 },
+       [PAD_GPIO34]    = { 0x2b0, 14, 1 },
+       [PAD_GPIO35]    = { 0x2b0, 17, 1 },
+
+       [PAD_GPIO36]    = { 0x2b4, 21, 2 },
+       [PAD_GPIO37]    = { 0x2b4, 18, 2 },
+       [PAD_GPIO38]    = { 0x2b4, 15, 2 },
+       [PAD_GPIO39]    = { 0x2b0, 11, 2 },
+       [PAD_GPIO40]    = { 0x2b0, 20, 2 },
+       [PAD_GPIO41]    = { 0x2b0, 23, 2 },
+       [PAD_GPIO42]    = { 0x2b0, 26, 2 },
+       [PAD_GPIO43]    = { 0x2b0, 29, 2 },
+       [PAD_GPIO44]    = { 0x2b4,  0, 2 },
+       [PAD_GPIO45]    = { 0x2b4,  3, 2 },
+       [PAD_GPIO46]    = { 0x2b4,  6, 2 },
+       [PAD_GPIO47]    = { 0x2b4,  9, 2 },
+       [PAD_GPIO48]    = { 0x2b4, 12, 2 },
+       [PAD_GPIO49]    = { 0x2b0, 14, 2 },
+       [PAD_GPIO50]    = { 0x2b0, 17, 2 },
+};
+
+static void jh7110_set_function(struct udevice *dev,
+                               unsigned int pin, u32 func)
+{
+       const struct jh7110_func_sel *fs = &jh7110_sys_func_sel[pin];
+       struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+       void __iomem *reg;
+       u32 mask;
+
+       if (!fs->offset)
+               return;
+
+       if (func > fs->max)
+               return;
+
+       reg = priv->base + fs->offset;
+       func = func << fs->shift;
+       mask = 0x3U << fs->shift;
+
+       func |= readl(reg) & ~mask;
+       writel(func, reg);
+}
+
+static void jh7110_set_vin_group(struct udevice *dev, unsigned int pin)
+{
+       const struct jh7110_vin_group_sel *gs =
+               &jh7110_sys_vin_group_sel[pin];
+       struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+       void __iomem *reg;
+       u32 mask;
+       u32 grp;
+
+       if (!gs->offset)
+               return;
+
+       reg = priv->base + gs->offset;
+       grp = gs->group << gs->shift;
+       mask = 0x3U << gs->shift;
+
+       grp |= readl(reg) & ~mask;
+       writel(grp, reg);
+}
+
+static int jh7110_sys_set_one_pin_mux(struct udevice *dev, unsigned int pin,
+                                     unsigned int din, u32 dout, u32 doen, u32 func)
+{
+       struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+
+       if (pin < priv->info->ngpios && func == 0)
+               starfive_set_gpiomux(dev, pin, din, dout, doen);
+
+       jh7110_set_function(dev, pin, func);
+
+       if (pin < priv->info->ngpios && func == 2)
+               jh7110_set_vin_group(dev, pin);
+
+       return 0;
+}
+
+static int jh7110_sys_get_padcfg_base(struct udevice *dev,
+                                     unsigned int pin)
+{
+       if (pin < PAD_GMAC1_MDC)
+               return SYS_GPO_PDA_0_74_CFG;
+       else if (pin > PAD_GMAC1_TXC && pin <= PAD_QSPI_DATA3)
+               return SYS_GPO_PDA_89_94_CFG;
+       else
+               return -1;
+}
+
+static void jh7110_sys_init_hw(struct udevice *dev)
+{
+       struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+
+       /* mask all GPIO interrupts */
+       writel(0U, priv->base + JH7110_SYS_GPIOIE0);
+       writel(0U, priv->base + JH7110_SYS_GPIOIE1);
+       /* clear edge interrupt flags */
+       writel(~0U, priv->base + JH7110_SYS_GPIOIC0);
+       writel(~0U, priv->base + JH7110_SYS_GPIOIC1);
+       /* enable GPIO interrupts */
+       writel(1U, priv->base + JH7110_SYS_GPIOEN);
+}
+
+const struct starfive_pinctrl_soc_info jh7110_sys_pinctrl_info = {
+       /* pin conf */
+       .set_one_pinmux = jh7110_sys_set_one_pin_mux,
+       .get_padcfg_base = jh7110_sys_get_padcfg_base,
+
+       /* gpio dout/doen/din/gpioinput register */
+       .dout_reg_base = JH7110_SYS_DOUT,
+       .dout_mask = GENMASK(6, 0),
+       .doen_reg_base = JH7110_SYS_DOEN,
+       .doen_mask = GENMASK(5, 0),
+       .gpi_reg_base = JH7110_SYS_GPI,
+       .gpi_mask = GENMASK(6, 0),
+       .gpioin_reg_base = JH7110_SYS_GPIOIN,
+
+       /* gpio */
+       .gpio_bank_name = "GPIO",
+       .ngpios = JH7110_SYS_NGPIO,
+       .gpio_init_hw = jh7110_sys_init_hw,
+};
+
+static int jh7110_sys_pinctrl_probe(struct udevice *dev)
+{
+       struct starfive_pinctrl_soc_info *info =
+               (struct starfive_pinctrl_soc_info *)dev_get_driver_data(dev);
+
+       return starfive_pinctrl_probe(dev, info);
+}
+
+static const struct udevice_id jh7110_sys_pinctrl_ids[] = {
+       /* JH7110 sys pinctrl */
+       { .compatible = "starfive,jh7110-sys-pinctrl",
+         .data = (ulong)&jh7110_sys_pinctrl_info, },
+       { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(jh7110_sys_pinctrl) = {
+       .name           = "jh7110-sys-pinctrl",
+       .id             = UCLASS_PINCTRL,
+       .of_match       = jh7110_sys_pinctrl_ids,
+       .priv_auto      = sizeof(struct starfive_pinctrl_priv),
+       .ops            = &starfive_pinctrl_ops,
+       .probe          = jh7110_sys_pinctrl_probe,
+};

diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.c b/drivers/pinctrl/starfive/pinctrl-starfive.c
new file mode 100644 (file)
index 0000000..9b09cc2
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive.c
@@ -0,0 +1,398 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7100 SoC
+ *
+ * Copyright (C) 2022 Shanghai StarFive Technology Co., Ltd.
+ *   Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
+ *   Author: Jianlong Huang <jianlong.huang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <asm-generic/gpio.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <dm/device_compat.h>
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+
+#include "pinctrl-starfive.h"
+
+/* pad control bits */
+#define STARFIVE_PADCFG_POS    BIT(7)
+#define STARFIVE_PADCFG_SMT    BIT(6)
+#define STARFIVE_PADCFG_SLEW   BIT(5)
+#define STARFIVE_PADCFG_PD     BIT(4)
+#define STARFIVE_PADCFG_PU     BIT(3)
+#define STARFIVE_PADCFG_BIAS   (STARFIVE_PADCFG_PD | STARFIVE_PADCFG_PU)
+#define STARFIVE_PADCFG_DS_MASK        GENMASK(2, 1)
+#define STARFIVE_PADCFG_DS_2MA (0U << 1)
+#define STARFIVE_PADCFG_DS_4MA BIT(1)
+#define STARFIVE_PADCFG_DS_8MA (2U << 1)
+#define STARFIVE_PADCFG_DS_12MA        (3U << 1)
+#define STARFIVE_PADCFG_IE     BIT(0)
+#define GPIO_NUM_PER_WORD      32
+
+/*
+ * The packed pinmux values from the device tree look like this:
+ *
+ *  | 31 - 24 | 23 - 16 | 15 - 10 |  9 - 8   | 7 - 0 |
+ *  |   din   |  dout   |  doen   | function |  pin  |
+ */
+static unsigned int starfive_pinmux_din(u32 v)
+{
+       return (v & GENMASK(31, 24)) >> 24;
+}
+
+static u32 starfive_pinmux_dout(u32 v)
+{
+       return (v & GENMASK(23, 16)) >> 16;
+}
+
+static u32 starfive_pinmux_doen(u32 v)
+{
+       return (v & GENMASK(15, 10)) >> 10;
+}
+
+static u32 starfive_pinmux_function(u32 v)
+{
+       return (v & GENMASK(9, 8)) >> 8;
+}
+
+static unsigned int starfive_pinmux_pin(u32 v)
+{
+       return v & GENMASK(7, 0);
+}
+
+void starfive_set_gpiomux(struct udevice *dev, unsigned int pin,
+                         unsigned int din, u32 dout, u32 doen)
+{
+       struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+       const struct starfive_pinctrl_soc_info *info = priv->info;
+
+       unsigned int offset = 4 * (pin / 4);
+       unsigned int shift  = 8 * (pin % 4);
+       u32 dout_mask = info->dout_mask << shift;
+       u32 done_mask = info->doen_mask << shift;
+       u32 ival, imask;
+       void __iomem *reg_dout;
+       void __iomem *reg_doen;
+       void __iomem *reg_din;
+
+       reg_dout = priv->base + info->dout_reg_base + offset;
+       reg_doen = priv->base + info->doen_reg_base + offset;
+       dout <<= shift;
+       doen <<= shift;
+       if (din != GPI_NONE) {
+               unsigned int ioffset = 4 * (din / 4);
+               unsigned int ishift  = 8 * (din % 4);
+
+               reg_din = priv->base + info->gpi_reg_base + ioffset;
+               ival = (pin + 2) << ishift;
+               imask = info->gpi_mask << ishift;
+       } else {
+               reg_din = NULL;
+       }
+
+       dout |= readl(reg_dout) & ~dout_mask;
+       writel(dout, reg_dout);
+       doen |= readl(reg_doen) & ~done_mask;
+       writel(doen, reg_doen);
+       if (reg_din) {
+               ival |= readl(reg_din) & ~imask;
+               writel(ival, reg_din);
+       }
+}
+
+static const struct pinconf_param starfive_pinconf_params[] = {
+       { "bias-disable",       PIN_CONFIG_BIAS_DISABLE,        0 },
+       { "bias-pull-up",       PIN_CONFIG_BIAS_PULL_UP,        1 },
+       { "bias-pull-down",     PIN_CONFIG_BIAS_PULL_DOWN,      1 },
+       { "drive-strength",     PIN_CONFIG_DRIVE_STRENGTH,      0 },
+       { "input-schmitt-enable",  PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
+       { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
+       { "input-enable",       PIN_CONFIG_INPUT_ENABLE,        1 },
+       { "input-disable",      PIN_CONFIG_INPUT_ENABLE,        0 },
+       { "slew-rate",          PIN_CONFIG_SLEW_RATE,           0 },
+};
+
+static const u8 starfive_drive_strength_mA[4] = { 2, 4, 8, 12 };
+
+static u32 starfive_padcfg_ds_from_mA(u32 v)
+{
+       int i;
+
+       for (i = 0; i < 3; i++) {
+               if (v <= starfive_drive_strength_mA[i])
+                       break;
+       }
+       return i << 1;
+}
+
+static void starfive_padcfg_rmw(struct udevice *dev,
+                               unsigned int pin, u32 mask, u32 value)
+{
+       struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+       struct starfive_pinctrl_soc_info *info = priv->info;
+       void __iomem *reg;
+       int padcfg_base;
+
+       if (!info->get_padcfg_base)
+               return;
+
+       padcfg_base = info->get_padcfg_base(dev, pin);
+       if (padcfg_base < 0)
+               return;
+
+       reg = priv->base + padcfg_base + 4 * pin;
+       value &= mask;
+
+       value |= readl(reg) & ~mask;
+       writel(value, reg);
+}
+
+static int starfive_pinconf_set(struct udevice *dev, unsigned int pin,
+                               unsigned int param, unsigned int arg)
+{
+       u16 mask = 0;
+       u16 value = 0;
+
+       switch (param) {
+       case PIN_CONFIG_BIAS_DISABLE:
+               mask |= STARFIVE_PADCFG_BIAS;
+               value &= ~STARFIVE_PADCFG_BIAS;
+               break;
+       case PIN_CONFIG_BIAS_PULL_DOWN:
+               if (arg == 0)
+                       return -EINVAL;
+               mask |= STARFIVE_PADCFG_BIAS;
+               value = (value & ~STARFIVE_PADCFG_BIAS) | STARFIVE_PADCFG_PD;
+               break;
+       case PIN_CONFIG_BIAS_PULL_UP:
+               if (arg == 0)
+                       return -EINVAL;
+               mask |= STARFIVE_PADCFG_BIAS;
+               value = (value & ~STARFIVE_PADCFG_BIAS) | STARFIVE_PADCFG_PU;
+               break;
+       case PIN_CONFIG_DRIVE_STRENGTH:
+               mask |= STARFIVE_PADCFG_DS_MASK;
+               value = (value & ~STARFIVE_PADCFG_DS_MASK) |
+                       starfive_padcfg_ds_from_mA(arg);
+               break;
+       case PIN_CONFIG_INPUT_ENABLE:
+               mask |= STARFIVE_PADCFG_IE;
+               if (arg)
+                       value |= STARFIVE_PADCFG_IE;
+               else
+                       value &= ~STARFIVE_PADCFG_IE;
+               break;
+       case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+               mask |= STARFIVE_PADCFG_SMT;
+               if (arg)
+                       value |= STARFIVE_PADCFG_SMT;
+               else
+                       value &= ~STARFIVE_PADCFG_SMT;
+               break;
+       case PIN_CONFIG_SLEW_RATE:
+               mask |= STARFIVE_PADCFG_SLEW;
+               if (arg)
+                       value |= STARFIVE_PADCFG_SLEW;
+               else
+                       value &= ~STARFIVE_PADCFG_SLEW;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       starfive_padcfg_rmw(dev, pin, mask, value);
+
+       return 0;
+}
+
+static int starfive_property_set(struct udevice *dev, u32 pinmux_group)
+{
+       struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+       struct starfive_pinctrl_soc_info *info = priv->info;
+
+       if (info->set_one_pinmux)
+               info->set_one_pinmux(dev,
+                       starfive_pinmux_pin(pinmux_group),
+                       starfive_pinmux_din(pinmux_group),
+                       starfive_pinmux_dout(pinmux_group),
+                       starfive_pinmux_doen(pinmux_group),
+                       starfive_pinmux_function(pinmux_group));
+
+       return starfive_pinmux_pin(pinmux_group);
+}
+
+const struct pinctrl_ops starfive_pinctrl_ops = {
+       .set_state = pinctrl_generic_set_state,
+       .pinconf_num_params     = ARRAY_SIZE(starfive_pinconf_params),
+       .pinconf_params         = starfive_pinconf_params,
+       .pinconf_set            = starfive_pinconf_set,
+       .pinmux_property_set = starfive_property_set,
+};
+
+static int starfive_gpio_get_direction(struct udevice *dev, unsigned int off)
+{
+       struct udevice *pdev = dev->parent;
+       struct starfive_pinctrl_priv *priv = dev_get_priv(pdev);
+       struct starfive_pinctrl_soc_info *info = priv->info;
+
+       unsigned int offset = 4 * (off / 4);
+       unsigned int shift  = 8 * (off % 4);
+       u32 doen = readl(priv->base + info->doen_reg_base + offset);
+
+       doen = (doen >> shift) & info->doen_mask;
+
+       return doen == GPOEN_ENABLE ? GPIOF_OUTPUT : GPIOF_INPUT;
+}
+
+static int starfive_gpio_direction_input(struct udevice *dev, unsigned int off)
+{
+       struct udevice *pdev = dev->parent;
+       struct starfive_pinctrl_priv *priv = dev_get_priv(pdev);
+       struct starfive_pinctrl_soc_info *info = priv->info;
+
+       /* enable input and schmitt trigger */
+       starfive_padcfg_rmw(pdev, off,
+                           STARFIVE_PADCFG_IE | STARFIVE_PADCFG_SMT,
+                           STARFIVE_PADCFG_IE | STARFIVE_PADCFG_SMT);
+
+       if (info->set_one_pinmux)
+               info->set_one_pinmux(pdev, off,
+                               GPI_NONE, GPOUT_LOW, GPOEN_DISABLE, 0);
+
+       return 0;
+}
+
+static int starfive_gpio_direction_output(struct udevice *dev,
+                                         unsigned int off, int val)
+{
+       struct udevice *pdev = dev->parent;
+       struct starfive_pinctrl_priv *priv = dev_get_priv(pdev);
+       struct starfive_pinctrl_soc_info *info = priv->info;
+
+       if (info->set_one_pinmux)
+               info->set_one_pinmux(pdev, off,
+                               GPI_NONE, val ? GPOUT_HIGH : GPOUT_LOW,
+                               GPOEN_ENABLE, 0);
+
+       /* disable input, schmitt trigger and bias */
+       starfive_padcfg_rmw(pdev, off,
+                           STARFIVE_PADCFG_IE | STARFIVE_PADCFG_SMT
+                           | STARFIVE_PADCFG_BIAS,
+                           0);
+
+       return 0;
+}
+
+static int starfive_gpio_get_value(struct udevice *dev, unsigned int off)
+{
+       struct udevice *pdev = dev->parent;
+       struct starfive_pinctrl_priv *priv = dev_get_priv(pdev);
+       struct starfive_pinctrl_soc_info *info = priv->info;
+
+       void __iomem *reg = priv->base + info->gpioin_reg_base
+                       + 4 * (off / GPIO_NUM_PER_WORD);
+
+       return !!(readl(reg) & BIT(off % GPIO_NUM_PER_WORD));
+}
+
+static int starfive_gpio_set_value(struct udevice *dev,
+                                  unsigned int off, int val)
+{
+       struct udevice *pdev = dev->parent;
+       struct starfive_pinctrl_priv *priv = dev_get_priv(pdev);
+       struct starfive_pinctrl_soc_info *info = priv->info;
+
+       unsigned int offset = 4 * (off / 4);
+       unsigned int shift  = 8 * (off % 4);
+       void __iomem *reg_dout = priv->base + info->dout_reg_base + offset;
+       u32 dout = (val ? GPOUT_HIGH : GPOUT_LOW) << shift;
+       u32 mask = info->dout_mask << shift;
+
+       dout |= readl(reg_dout) & ~mask;
+       writel(dout, reg_dout);
+
+       return 0;
+}
+
+static int starfive_gpio_probe(struct udevice *dev)
+{
+       struct gpio_dev_priv *uc_priv;
+       struct udevice *pdev = dev->parent;
+       struct starfive_pinctrl_priv *priv = dev_get_priv(pdev);
+       struct starfive_pinctrl_soc_info *info = priv->info;
+
+       uc_priv = dev_get_uclass_priv(dev);
+       uc_priv->bank_name = info->gpio_bank_name;
+       uc_priv->gpio_count = info->ngpios;
+
+       if (!info->gpio_init_hw)
+               return -ENXIO;
+
+       info->gpio_init_hw(pdev);
+
+       return 0;
+}
+
+static const struct dm_gpio_ops starfive_gpio_ops = {
+       .get_function = starfive_gpio_get_direction,
+       .direction_input = starfive_gpio_direction_input,
+       .direction_output = starfive_gpio_direction_output,
+       .get_value = starfive_gpio_get_value,
+       .set_value = starfive_gpio_set_value,
+};
+
+static struct driver starfive_gpio_driver = {
+       .name = "starfive_gpio",
+       .id = UCLASS_GPIO,
+       .probe = starfive_gpio_probe,
+       .ops = &starfive_gpio_ops,
+};
+
+static int starfive_gpiochip_register(struct udevice *parent)
+{
+       struct uclass_driver *drv;
+       struct udevice *dev;
+       int ret;
+       ofnode node;
+
+       drv = lists_uclass_lookup(UCLASS_GPIO);
+       if (!drv)
+               return -ENOENT;
+
+       node = dev_ofnode(parent);
+       ret = device_bind_with_driver_data(parent, &starfive_gpio_driver,
+                                          "starfive_gpio", 0, node, &dev);
+
+       return (ret == 0) ? 0 : ret;
+}
+
+int starfive_pinctrl_probe(struct udevice *dev,
+                          const struct starfive_pinctrl_soc_info *info)
+{
+       struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+       int ret;
+
+       /* Bind pinctrl_info from .data to priv */
+       priv->info =
+               (struct starfive_pinctrl_soc_info *)dev_get_driver_data(dev);
+
+       if (!priv->info)
+               return -EINVAL;
+
+       priv->base = dev_read_addr_ptr(dev);
+       if (!priv->base)
+               return -EINVAL;
+
+       /* gpiochip register */
+       ret = starfive_gpiochip_register(dev);
+
+       return (ret == 0) ? 0 : ret;
+}

diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.h b/drivers/pinctrl/starfive/pinctrl-starfive.h
new file mode 100644 (file)
index 0000000..5721c3c
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Pinctrl / GPIO driver for StarFive SoC
+ *
+ * Copyright (C) 2022 Shanghai StarFive Technology Co., Ltd.
+ *   Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
+ *   Author: Jianlong Huang <jianlong.huang@starfivetech.com>
+ */
+
+#define STARFIVE_PINCTRL(a, b) { .number = a, .name = b }
+
+extern const struct pinctrl_ops starfive_pinctrl_ops;
+
+struct starfive_pinctrl_pin {
+       unsigned int number;
+       const char *name;
+};
+
+struct starfive_pinctrl_soc_info {
+       /* pinctrl */
+       int (*set_one_pinmux)(struct udevice *dev, unsigned int pin,
+                             unsigned int din, u32 dout, u32 doen, u32 func);
+       int (*get_padcfg_base)(struct udevice *dev,
+                              unsigned int pin);
+
+       /* gpio dout/doen/din/gpioinput register */
+       unsigned int dout_reg_base;
+       unsigned int dout_mask;
+       unsigned int doen_reg_base;
+       unsigned int doen_mask;
+       unsigned int gpi_reg_base;
+       unsigned int gpi_mask;
+       unsigned int gpioin_reg_base;
+
+       /* gpio */
+       const char *gpio_bank_name;
+       int ngpios;
+       void (*gpio_init_hw)(struct udevice *dev);
+};
+
+/*
+ * struct starfive_pinctrl_priv - private data for Starfive pinctrl driver
+ *
+ * @padctl_base: base address of the pinctrl device
+ * @info: SoC specific data & function
+ */
+struct starfive_pinctrl_priv {
+       void __iomem *base;
+       struct starfive_pinctrl_soc_info *info;
+};
+
+void starfive_set_gpiomux(struct udevice *dev, unsigned int pin,
+                         unsigned int din, u32 dout, u32 doen);
+int starfive_pinctrl_probe(struct udevice *dev,
+                          const struct starfive_pinctrl_soc_info *info);

diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index e085119..1acf212 100644 (file)
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -112,3 +112,4 @@ source "drivers/ram/rockchip/Kconfig"
 source "drivers/ram/sifive/Kconfig"
 source "drivers/ram/stm32mp1/Kconfig"
 source "drivers/ram/octeon/Kconfig"
+source "drivers/ram/starfive/Kconfig"

diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 83948e2..2b9429c 100644 (file)
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -20,5 +20,7 @@ obj-$(CONFIG_K3_DDRSS) += k3-ddrss/
 obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
 
 obj-$(CONFIG_RAM_SIFIVE) += sifive/
-
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/
+endif
 obj-$(CONFIG_ARCH_OCTEON) += octeon/

diff --git a/drivers/ram/k3-am654-ddrss.c b/drivers/ram/k3-am654-ddrss.c
index 4453c24..b8338f8 100644 (file)
--- a/drivers/ram/k3-am654-ddrss.c
+++ b/drivers/ram/k3-am654-ddrss.c
@@ -13,11 +13,14 @@
 #include <ram.h>
 #include <asm/io.h>
 #include <power-domain.h>
-#include <asm/arch/sys_proto.h>
 #include <dm/device_compat.h>
 #include <power/regulator.h>
 #include "k3-am654-ddrss.h"
 
+void sdelay(unsigned long loops);
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
+                 u32 bound);
+
 #define LDELAY 10000
 
 /* DDRSS PHY configuration register fixed values */

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index b1fea04..8993245 100644 (file)
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -2749,6 +2749,8 @@ static u64 dram_detect_cap(struct dram_info *dram,
        /* detect cs1 row */
        sdram_detect_cs1_row(cap_info, params->base.dramtype);
 
+       sdram_detect_high_row(cap_info);
+
        /* detect die bw */
        sdram_detect_dbw(cap_info, params->base.dramtype);
 
@@ -2954,7 +2956,7 @@ static int sdram_init(struct dram_info *dram,
                params->ch[ch].cap_info.rank = rank;
        }
 
-#if defined(CONFIG_RAM_RK3399_LPDDR4)
+#if defined(CONFIG_RAM_ROCKCHIP_LPDDR4)
        /* LPDDR4 needs to be trained at 400MHz */
        lpddr4_set_rate(dram, params, 0);
        params->base.ddr_freq = dfs_cfgs_lpddr4[0].base.ddr_freq / MHz;

diff --git a/drivers/ram/starfive/Kconfig b/drivers/ram/starfive/Kconfig
new file mode 100644 (file)
index 0000000..80c7900
--- /dev/null
+++ b/drivers/ram/starfive/Kconfig
@@ -0,0 +1,5 @@
+config SPL_STARFIVE_DDR
+       bool "StarFive DDR driver in SPL"
+       depends on SPL_RAM && STARFIVE_JH7110
+       help
+         This enables DDR support for the platforms based on StarFive JH7110 SoC.

diff --git a/drivers/ram/starfive/Makefile b/drivers/ram/starfive/Makefile
new file mode 100644 (file)
index 0000000..1df42c3
--- /dev/null
+++ b/drivers/ram/starfive/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2022 StarFive, Inc
+#
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_start.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_train.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive_ddr.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_utils.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrcsr_boot.o
+endif
\ No newline at end of file

diff --git a/drivers/ram/starfive/ddrcsr_boot.c b/drivers/ram/starfive/ddrcsr_boot.c
new file mode 100644 (file)
index 0000000..f2dd55f
--- /dev/null
+++ b/drivers/ram/starfive/ddrcsr_boot.c
@@ -0,0 +1,339 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/regs.h>
+#include <linux/delay.h>
+#include <wait_bit.h>
+
+#include "starfive_ddr.h"
+
+#define REGOFFSET(offset)      ((offset) / 4)
+
+static const struct ddr_reg_cfg ddr_csr_cfg[] = {
+       {0x0,           0x0,    0x00000001,     REGSETALL},
+       {0xf00,         0x0,    0x40001030,     (OFFSET_SEL | F_SET | REG4G | REG8G)},
+       {0xf00,         0x0,    0x40001030,     (OFFSET_SEL | F_SET | REG2G)},
+       {0xf04,         0x0,    0x00000001,     (OFFSET_SEL | F_SET | REG4G | REG8G)},
+       {0xf04,         0x0,    0x00800001,     (OFFSET_SEL | F_SET | REG2G)},
+       {0xf10,         0x0,    0x00400000,     (OFFSET_SEL | REGSETALL)},
+       {0xf14,         0x0,    0x043fffff,     (OFFSET_SEL | REGSETALL)},
+       {0xf18,         0x0,    0x00000000,     (OFFSET_SEL | REGSETALL)},
+       {0xf30,         0x0,    0x1f000041,     (OFFSET_SEL | REGSETALL)},
+       {0xf34,         0x0,    0x1f000041,     (OFFSET_SEL | F_SET | REG4G | REG8G)},
+       {0x110,         0x0,    0xc0000001,     (OFFSET_SEL | REGSETALL)},
+       {0x114,         0x0,    0xffffffff,     (OFFSET_SEL | REGSETALL)},
+       {0x10c,         0x0,    0x00000505,     REGSETALL},
+       {0x11c,         0x0,    0x00000000,     REGSETALL},
+       {0x500,         0x0,    0x00000201,     REGSETALL},
+       {0x514,         0x0,    0x00000100,     REGSETALL},
+       {0x6a8,         0x0,    0x00040000,     REGSETALL},
+       {0xea8,         0x0,    0x00040000,     REGSETALL},
+       {0x504,         0x0,    0x40000000,     REGSETALL}
+};
+
+static const struct ddr_reg_cfg ddr_csr_cfg1[] = {
+       {0x310,         0x0,    0x00020000,     REGSETALL},
+       {0x310,         0x0,    0x00020001,     REGSETALL},
+       {0x600,         0x0,    0x002e0176,     REGSETALL},
+       {0x604,         0x0,    0x002e0176,     REGSETALL},
+       {0x608,         0x0,    0x001700bb,     REGSETALL},
+       {0x60c,         0x0,    0x000b005d,     REGSETALL},
+       {0x610,         0x0,    0x0005002e,     REGSETALL},
+       {0x614,         0x0,    0x00020017,     REGSETALL},
+       {0x618,         0x0,    0x00020017,     REGSETALL},
+       {0x61c,         0x0,    0x00020017,     REGSETALL},
+       {0x678,         0x0,    0x00000019,     REGSETALL},
+       {0x100,         0x0,    0x000000f8,     REGSETALL},
+       {0x620,         0x0,    0x03030404,     REGSETALL},
+       {0x624,         0x0,    0x04030505,     REGSETALL},
+       {0x628,         0x0,    0x07030884,     REGSETALL},
+       {0x62c,         0x0,    0x13150401,     REGSETALL},
+       {0x630,         0x0,    0x17150604,     REGSETALL},
+       {0x634,         0x0,    0x00110000,     REGSETALL},
+       {0x638,         0x0,    0x200a0a08,     REGSETALL},
+       {0x63c,         0x0,    0x1730f803,     REGSETALL},
+       {0x640,         0x0,    0x000a0c00,     REGSETALL},
+       {0x644,         0x0,    0xa005000a,     REGSETALL},
+       {0x648,         0x0,    0x00000000,     REGSETALL},
+       {0x64c,         0x0,    0x00081306,     REGSETALL},
+       {0x650,         0x0,    0x04070304,     REGSETALL},
+       {0x654,         0x0,    0x00000404,     REGSETALL},
+       {0x658,         0x0,    0x00000060,     REGSETALL},
+       {0x65c,         0x0,    0x00030008,     REGSETALL},
+       {0x660,         0x0,    0x00000000,     REGSETALL},
+       {0x680,         0x0,    0x00000603,     REGSETALL},
+       {0x684,         0x0,    0x01000202,     REGSETALL},
+       {0x688,         0x0,    0x0413040d,     REGSETALL},
+       {0x68c,         0x0,    0x20002420,     REGSETALL},
+       {0x690,         0x0,    0x00140000,     REGSETALL},
+       {0x69c,         0x0,    0x01240074,     REGSETALL},
+       {0x6a0,         0x0,    0x00000000,     REGSETALL},
+       {0x6a4,         0x0,    0x20240c00,     REGSETALL},
+       {0x6a8,         0x0,    0x00040000,     REGSETALL},
+       {0x4,           0x0,    0x30010006,     (F_SET | REG4G | REG8G)},
+       {0x4,           0x0,    0x10010006,     (F_SET | REG2G)},
+       {0xc,           0x0,    0x00000002,     REGSETALL},
+       {0x4,           0x0,    0x30020000,     (F_SET | REG4G | REG8G)},
+       {0x4,           0x0,    0x10020000,     (F_SET | REG2G)},
+       {0xc,           0x0,    0x00000002,     REGSETALL},
+       {0x4,           0x0,    0x30030031,     (F_SET | REG4G | REG8G)},
+       {0x4,           0x0,    0x10030031,     (F_SET | REG2G)},
+       {0xc,           0x0,    0x00000002,     REGSETALL},
+       {0x4,           0x0,    0x300b0033,     (F_SET | REG4G | REG8G)},
+       {0x4,           0x0,    0x100b0033,     (F_SET | REG2G)},
+       {0xc,           0x0,    0x00000002,     REGSETALL},
+       {0x4,           0x0,    0x30160016,     (F_SET | REG4G | REG8G)},
+       {0x4,           0x0,    0x10160016,     (F_SET | REG2G)},
+       {0xc,           0x0,    0x00000002,     REGSETALL},
+       {0x10,          0x0,    0x00000010,     REGSETALL},
+       {0x14,          0x0,    0x00000001,     REGSETALL},
+};
+
+static const struct ddr_reg_cfg ddr_csr_cfg2[] = {
+       {0xb8,          0xf0ffffff,             0x3000000,      REGCLRSETALL},
+       {0x84,          0xFEFFFFFF,             0x0,            REGCLRSETALL},
+       {0xb0,          0xFFFEFFFF,             0x0,            REGCLRSETALL},
+       {0xb0,          0xFEFFFFFF,             0x0,            REGCLRSETALL},
+       {0xb4,          0xffffffff,             0x1,            REGCLRSETALL},
+       {0x248,         0xffffffff,             0x3000000,      REGCLRSETALL},
+       {0x24c,         0xffffffff,             0x300,          REGCLRSETALL},
+       {0x24c,         0xffffffff,             0x3000000,      REGCLRSETALL},
+       {0xb0,          0xffffffff,             0x100,          REGCLRSETALL},
+       {0xb8,          0xFFF0FFFF,             0x30000,        REGCLRSETALL},
+       {0x84,          0xFFFEFFFF,             0x0,            REGCLRSETALL},
+       {0xac,          0xFFFEFFFF,             0x0,            REGCLRSETALL},
+       {0xac,          0xFEFFFFFF,             0x0,            REGCLRSETALL},
+       {0xb0,          0xffffffff,             0x1,            REGCLRSETALL},
+       {0x248,         0xffffffff,             0x30000,        REGCLRSETALL},
+       {0x24c,         0xffffffff,             0x3,            REGCLRSETALL},
+       {0x24c,         0xffffffff,             0x30000,        REGCLRSETALL},
+       {0x250,         0xffffffff,             0x3000000,      REGCLRSETALL},
+       {0x254,         0xffffffff,             0x3000000,      REGCLRSETALL},
+       {0x258,         0xffffffff,             0x3000000,      REGCLRSETALL},
+       {0xac,          0xffffffff,             0x100,          REGCLRSETALL},
+       {0x10c,         0xFFFFF0FF,             0x300,          REGCLRSETALL},
+       {0x110,         0xFFFFFEFF,             0x0,            REGCLRSETALL},
+       {0x11c,         0xFFFEFFFF,             0x0,            REGCLRSETALL},
+       {0x11c,         0xFEFFFFFF,             0x0,            REGCLRSETALL},
+       {0x120,         0xffffffff,             0x100,          REGCLRSETALL},
+       {0x2d0,         0xffffffff,             0x300,          REGCLRSETALL},
+       {0x2dc,         0xffffffff,             0x300,          REGCLRSETALL},
+       {0x2e8,         0xffffffff,             0x300,          REGCLRSETALL},
+};
+
+static const struct ddr_reg_cfg ddr_csr_cfg3[] = {
+       {0x100,         0x0,    0x000000e0,     REGSETALL},
+       {0x620,         0x0,    0x04041417,     REGSETALL},
+       {0x624,         0x0,    0x09110609,     REGSETALL},
+       {0x628,         0x0,    0x442d0994,     REGSETALL},
+       {0x62c,         0x0,    0x271e102b,     REGSETALL},
+       {0x630,         0x0,    0x291b140a,     REGSETALL},
+       {0x634,         0x0,    0x001c0000,     REGSETALL},
+       {0x638,         0x0,    0x200f0f08,     REGSETALL},
+       {0x63c,         0x0,    0x29420a06,     REGSETALL},
+       {0x640,         0x0,    0x019e1fc1,     REGSETALL},
+       {0x644,         0x0,    0x10cb0196,     REGSETALL},
+       {0x648,         0x0,    0x00000000,     REGSETALL},
+       {0x64c,         0x0,    0x00082714,     REGSETALL},
+       {0x650,         0x0,    0x16442f0d,     REGSETALL},
+       {0x654,         0x0,    0x00001916,     REGSETALL},
+       {0x658,         0x0,    0x00000060,     REGSETALL},
+       {0x65c,         0x0,    0x00600020,     REGSETALL},
+       {0x660,         0x0,    0x00000000,     REGSETALL},
+       {0x680,         0x0,    0x0c00040f,     REGSETALL},
+       {0x684,         0x0,    0x03000604,     REGSETALL},
+       {0x688,         0x0,    0x0515040d,     REGSETALL},
+       {0x68c,         0x0,    0x20002c20,     REGSETALL},
+       {0x690,         0x0,    0x00140000,     REGSETALL},
+       {0x69c,         0x0,    0x01240074,     REGSETALL},
+       {0x6a0,         0x0,    0x00000000,     REGSETALL},
+       {0x6a4,         0x0,    0x202c0c00,     REGSETALL},
+       {0x6a8,         0x0,    0x00040000,     REGSETALL},
+       {0x4,           0x0,    0x30010036,     (F_SET | REG4G | REG8G)},
+       {0x4,           0x0,    0x10010036,     (F_SET | REG2G)},
+       {0xc,           0x0,    0x00000002,     REGSETALL},
+       {0x4,           0x0,    0x3002001b,     (F_SET | REG4G | REG8G)},
+       {0x4,           0x0,    0x10010036,     (F_SET | REG2G)},
+       {0xc,           0x0,    0x00000002,     REGSETALL},
+       {0x4,           0x0,    0x30030031,     (F_SET | REG4G | REG8G)},
+       {0x4,           0x0,    0x10030031,     (F_SET | REG2G)},
+       {0xc,           0x0,    0x00000002,     REGSETALL},
+       {0x4,           0x0,    0x300b0066,     (F_SET | REG4G)},
+       {0x4,           0x0,    0x300b0036,     (F_SET | REG8G)},
+       {0x4,           0x0,    0x100b0066,     (F_SET | REG2G)},
+       {0xc,           0x0,    0x00000002,     REGSETALL},
+       {0x4,           0x0,    0x30160016,     (F_SET | REG4G | REG8G)},
+       {0x4,           0x0,    0x10160016,     (F_SET | REG2G)},
+       {0xc,           0x0,    0x00000002,     REGSETALL},
+       {0x410,         0x0,    0x00101010,     REGSETALL},
+       {0x420,         0x0,    0x0c181006,     REGSETALL},
+       {0x424,         0x0,    0x20200820,     REGSETALL},
+       {0x428,         0x0,    0x80000020,     REGSETALL},
+       {0x0,           0x0,    0x00000001,     REGSETALL},
+       {0x108,         0x0,    0x00003000,     REGSETALL},
+       {0x704,         0x0,    0x00000007,     REGSETALL | OFFSET_SEL},
+       {0x330,         0x0,    0x09313fff,     (F_SET | REG4G | REG8G)},
+       {0x330,         0x0,    0x09311fff,     (F_SET | REG2G)},
+       {0x508,         0x0,    0x00000033,     (F_SET | REG4G | REG8G)},
+       {0x508,         0x0,    0x00000013,     (F_SET | REG2G)},
+       {0x324,         0x0,    0x00002000,     REGSETALL},
+       {0x104,         0x0,    0x90000000,     REGSETALL},
+       {0x510,         0x0,    0x00000100,     REGSETALL},
+       {0x514,         0x0,    0x00000000,     REGSETALL},
+       {0x700,         0x0,    0x00000003,     REGSETALL | OFFSET_SEL},
+       {0x514,         0x0,    0x00000600,     REGSETALL},
+       {0x20,          0x0,    0x00000001,     REGSETALL},
+};
+
+static void ddr_csr_set(u32 *csrreg, u32 *secreg, const struct ddr_reg_cfg *data,
+                       u32 len, u32 mask)
+{
+       u32 *addr;
+       u32 i;
+
+       for (i = 0; i < len; i++) {
+               if (!(data[i].flag & mask))
+                       continue;
+
+               if (data[i].flag & OFFSET_SEL)
+                       addr = secreg + REGOFFSET(data[i].offset);
+               else
+                       addr = csrreg + REGOFFSET(data[i].offset);
+
+               if (data[i].flag & F_CLRSET)
+                       DDR_REG_TRIGGER(addr, data[i].mask, data[i].val);
+               else
+                       out_le32(addr, data[i].val);
+       }
+}
+
+void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size)
+{
+       u32 len;
+       u32 val;
+       u32 mask;
+       int ret;
+
+       switch (size) {
+       case DDR_SIZE_2G:
+               mask = REG2G;
+               break;
+
+       case DDR_SIZE_4G:
+               mask = REG4G;
+               break;
+
+       case DDR_SIZE_8G:
+               mask = REG8G;
+               break;
+
+       case DDR_SIZE_16G:
+       default:
+               return;
+       };
+
+       len = ARRAY_SIZE(ddr_csr_cfg);
+       ddr_csr_set(csrreg, secreg, ddr_csr_cfg, len, mask);
+
+       ret = wait_for_bit_le32(csrreg + REGOFFSET(0x504), BIT(31),
+                               true, 1000, false);
+       if (ret)
+               return;
+
+       out_le32(csrreg + REGOFFSET(0x504), 0x0);
+       out_le32(csrreg + REGOFFSET(0x50c), 0x0);
+       udelay(300);
+       out_le32(csrreg + REGOFFSET(0x50c), 0x1);
+       mdelay(3);
+
+       switch (size) {
+       case DDR_SIZE_2G:
+               out_le32(csrreg + REGOFFSET(0x10), 0x1c);
+               break;
+
+       case DDR_SIZE_8G:
+       case DDR_SIZE_4G:
+               out_le32(csrreg + REGOFFSET(0x10), 0x3c);
+               break;
+
+       case DDR_SIZE_16G:
+       default:
+               break;
+       };
+
+       out_le32(csrreg + REGOFFSET(0x14), 0x1);
+       udelay(4);
+
+       len = ARRAY_SIZE(ddr_csr_cfg1);
+       ddr_csr_set(csrreg, secreg, ddr_csr_cfg1, len, mask);
+
+       udelay(4);
+       out_le32(csrreg + REGOFFSET(0x10), 0x11);
+       out_le32(csrreg + REGOFFSET(0x14), 0x1);
+
+       switch (size) {
+       case DDR_SIZE_4G:
+       case DDR_SIZE_8G:
+               out_le32(csrreg + REGOFFSET(0x10), 0x20);
+               out_le32(csrreg + REGOFFSET(0x14), 0x1);
+               udelay(4);
+               out_le32(csrreg + REGOFFSET(0x10), 0x21);
+               out_le32(csrreg + REGOFFSET(0x14), 0x1);
+               break;
+
+       case DDR_SIZE_2G:
+       case DDR_SIZE_16G:
+       default:
+               break;
+       };
+
+       out_le32(csrreg + REGOFFSET(0x514), 0x0);
+       ret = wait_for_bit_le32(csrreg + REGOFFSET(0x518), BIT(1),
+                               true, 1000, false);
+       if (ret)
+               return;
+
+       val = in_le32(csrreg + REGOFFSET(0x518));
+       while ((val & 0x2) != 0x0) {
+               val = in_le32(phyreg + 1);
+
+               if ((val & 0x20) == 0x20) {
+                       switch (val & 0x1f) {
+                       case 0: /* ddrc_clock=12M */
+                               DDR_REG_SET(BUS, DDR_BUS_OSC_DIV2);
+                               break;
+                       case 1: /* ddrc_clock=200M */
+                               DDR_REG_SET(BUS, DDR_BUS_PLL1_DIV8);
+                               break;
+                       case 2: /* ddrc_clock=800M */
+                               DDR_REG_SET(BUS, DDR_BUS_PLL1_DIV2);
+                               break;
+                       default:
+                               break;
+                       };
+
+                       out_le32(phyreg + 2, 0x1);
+                       ret = wait_for_bit_le32(phyreg + 2, BIT(0), false, 1000, false);
+                       if (ret)
+                               return;
+               }
+
+               udelay(1);
+               val = in_le32(csrreg + REGOFFSET(0x518));
+       };
+
+       val = in_le32(phyreg + 2048 + 83);
+       val = in_le32(phyreg + 2048 + 84);
+       out_le32(phyreg + 2048 + 84, val & 0xF8000000);
+
+       len = ARRAY_SIZE(ddr_csr_cfg2);
+       ddr_csr_set(phyreg + PHY_BASE_ADDR, secreg, ddr_csr_cfg2, len, mask);
+
+       len = ARRAY_SIZE(ddr_csr_cfg3);
+       ddr_csr_set(csrreg, secreg, ddr_csr_cfg3, len, mask);
+}

diff --git a/drivers/ram/starfive/ddrphy_start.c b/drivers/ram/starfive/ddrphy_start.c
new file mode 100644 (file)
index 0000000..479b6ef
--- /dev/null
+++ b/drivers/ram/starfive/ddrphy_start.c
@@ -0,0 +1,279 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include "starfive_ddr.h"
+
+static const struct ddr_reg_cfg ddr_start_cfg[] = {
+       {89,    0xffffff00,     0x00000051,     (OFFSET_SEL | REGCLRSETALL)},
+       {78,    0xfffffcff,     0x0,            (OFFSET_SEL | REGCLRSETALL)},
+       {345,   0xffffff00,     0x00000051,     (OFFSET_SEL | REGCLRSETALL)},
+       {334,   0xfffffcff,     0x0,            (OFFSET_SEL | REGCLRSETALL)},
+       {601,   0xffffff00,     0x00000051,     (OFFSET_SEL | REGCLRSETALL)},
+       {590,   0xfffffcff,     0x0,            (OFFSET_SEL | REGCLRSETALL)},
+       {857,   0xffffff00,     0x00000051,     (OFFSET_SEL | REGCLRSETALL)},
+       {846,   0xfffffcff,     0x0,            (OFFSET_SEL | REGCLRSETALL)},
+       {1793,  0xfffffeff,     0x0,            (OFFSET_SEL | REGCLRSETALL)},
+       {1793,  0xfffcffff,     0x0,            (OFFSET_SEL | REGCLRSETALL)},
+       {125,   0xfff0ffff,     0x00010000,     (OFFSET_SEL | REGCLRSETALL)},
+       {102,   0xfffffffc,     0x00000001,     (OFFSET_SEL | REGCLRSETALL)},
+       {105,   0xffffffe0,     0x00000001,     (OFFSET_SEL | REGCLRSETALL)},
+       {92,    0xfffffffe,     0x00000001,     (OFFSET_SEL | REGCLRSETALL)},
+       {94,    0xffffe0ff,     0x00000200,     (OFFSET_SEL | REGCLRSETALL)},
+       {96,    0xfffff0ff,     0x00000400,     (OFFSET_SEL | REGCLRSETALL)},
+       {89,    0xffffff00,     0x00000051,     (OFFSET_SEL | REGCLRSETALL)},
+       {381,   0xfff0ffff,     0x00010000,     (OFFSET_SEL | REGCLRSETALL)},
+       {358,   0xfffffffc,     0x00000001,     (OFFSET_SEL | REGCLRSETALL)},
+       {361,   0xffffffe0,     0x00000001,     (OFFSET_SEL | REGCLRSETALL)},
+       {348,   0xfffffffe,     0x00000001,     (OFFSET_SEL | REGCLRSETALL)},
+       {350,   0xffffe0ff,     0x00000200,     (OFFSET_SEL | REGCLRSETALL)},
+       {352,   0xfffff0ff,     0x00000400,     (OFFSET_SEL | REGCLRSETALL)},
+       {345,   0xffffff00,     0x00000051,     (OFFSET_SEL | REGCLRSETALL)},
+       {637,   0xfff0ffff,     0x00010000,     (OFFSET_SEL | REGCLRSETALL)},
+       {614,   0xfffffffc,     0x00000001,     (OFFSET_SEL | REGCLRSETALL)},
+       {617,   0xffffffe0,     0x00000001,     (OFFSET_SEL | REGCLRSETALL)},
+       {604,   0xfffffffe,     0x00000001,     (OFFSET_SEL | REGCLRSETALL)},
+       {606,   0xffffe0ff,     0x00000200,     (OFFSET_SEL | REGCLRSETALL)},
+       {608,   0xfffff0ff,     0x00000400,     (OFFSET_SEL | REGCLRSETALL)},
+       {601,   0xffffff00,     0x00000051,     (OFFSET_SEL | REGCLRSETALL)},
+       {893,   0xfff0ffff,     0x00010000,     (OFFSET_SEL | REGCLRSETALL)},
+       {870,   0xfffffffc,     0x00000001,     (OFFSET_SEL | REGCLRSETALL)},
+       {873,   0xffffffe0,     0x00000001,     (OFFSET_SEL | REGCLRSETALL)},
+       {860,   0xfffffffe,     0x00000001,     (OFFSET_SEL | REGCLRSETALL)},
+       {862,   0xffffe0ff,     0x00000200,     (OFFSET_SEL | REGCLRSETALL)},
+       {864,   0xfffff0ff,     0x00000400,     (OFFSET_SEL | REGCLRSETALL)},
+       {857,   0xffffff00,     0x00000051,     (OFFSET_SEL | REGCLRSETALL)},
+       {1895,  0xffffe000,     0x00001342,     (OFFSET_SEL | REGCLRSETALL)},
+       {1835,  0xfffff0ff,     0x00000200,     (OFFSET_SEL | REGCLRSETALL)},
+       {1793,  0xfffffeff,     0x00000100,     (OFFSET_SEL | REGCLRSETALL)},
+       {62,    0xfffffeff,     0x0,            REGCLRSETALL},
+       {66,    0xfffffeff,     0x0,            REGCLRSETALL},
+       {166,   0xffffff80,     0x00000001,     REGCLRSETALL},
+       {62,    0xfff0ffff,     0x00010000,     REGCLRSETALL},
+       {62,    0xf0ffffff,     0x01000000,     REGCLRSETALL},
+       {166,   0xffff80ff,     0x00000100,     REGCLRSETALL},
+       {179,   0xff80ffff,     0x00010000,     REGCLRSETALL},
+       {67,    0xffe0ffff,     0x00010000,     REGCLRSETALL},
+       {67,    0xe0ffffff,     0x01000000,     REGCLRSETALL},
+       {179,   0x80ffffff,     0x01000000,     REGCLRSETALL},
+       {166,   0xff80ffff,     0x00010000,     REGCLRSETALL},
+       {62,    0xfff0ffff,     0x00010000,     REGCLRSETALL},
+       {62,    0xf0ffffff,     0x01000000,     REGCLRSETALL},
+       {166,   0x80ffffff,     0x01000000,     REGCLRSETALL},
+       {182,   0xff80ffff,     0x00010000,     REGCLRSETALL},
+       {67,    0xffe0ffff,     0x00010000,     REGCLRSETALL},
+       {67,    0xe0ffffff,     0x01000000,     REGCLRSETALL},
+       {182,   0x80ffffff,     0x01000000,     REGCLRSETALL},
+       {167,   0xffffff80,     0x00000017,     REGCLRSETALL},
+       {62,    0xfff0ffff,     0x00010000,     REGCLRSETALL},
+       {62,    0xf0ffffff,     0x01000000,     REGCLRSETALL},
+       {167,   0xffff80ff,     0x00001700,     REGCLRSETALL},
+       {185,   0xff80ffff,     0x00200000,     REGCLRSETALL},
+       {67,    0xffe0ffff,     0x00010000,     REGCLRSETALL},
+       {67,    0xe0ffffff,     0x01000000,     REGCLRSETALL},
+       {185,   0x80ffffff,     0x20000000,     REGCLRSETALL},
+       {10,    0xffffffe0,     0x00000002,     REGCLRSETALL},
+       {0,     0xfffffffe,     0x00000001,     REGCLRSETALL},
+       {11,    0xfffffff0,     0x00000005,     (F_CLRSET | REG2G)},
+       {247,   0xffffffff,     0x00000008,     REGCLRSETALL},
+       {249,   0xffffffff,     0x00000800,     REGCLRSETALL},
+       {252,   0xffffffff,     0x00000008,     REGCLRSETALL},
+       {254,   0xffffffff,     0x00000800,     REGCLRSETALL},
+       {281,   0xffffffff,     0x33000000,     REGCLRSETALL},
+       {305,   0xffffffff,     0x33000000,     REGCLRSETALL},
+       {329,   0xffffffff,     0x33000000,     REGCLRSETALL},
+       {353,   0xffffffff,     0x33000000,     REGCLRSETALL},
+       {289,   0xffffffff,     0x36000000,     (F_CLRSET | REG8G)},
+       {313,   0xffffffff,     0x36000000,     (F_CLRSET | REG8G)},
+       {337,   0xffffffff,     0x36000000,     (F_CLRSET | REG8G)},
+       {361,   0xffffffff,     0x36000000,     (F_CLRSET | REG8G)},
+       {289,   0xffffffff,     0x66000000,     (F_CLRSET | REG2G | REG4G)},
+       {313,   0xffffffff,     0x66000000,     (F_CLRSET | REG2G | REG4G)},
+       {337,   0xffffffff,     0x66000000,     (F_CLRSET | REG2G | REG4G)},
+       {361,   0xffffffff,     0x66000000,     (F_CLRSET | REG2G | REG4G)},
+       {282,   0xffffffff,     0x00160000,     REGCLRSETALL},
+       {306,   0xffffffff,     0x00160000,     REGCLRSETALL},
+       {330,   0xffffffff,     0x00160000,     REGCLRSETALL},
+       {354,   0xffffffff,     0x00160000,     REGCLRSETALL},
+       {290,   0xffffffff,     0x00160000,     REGCLRSETALL},
+       {314,   0xffffffff,     0x00160000,     REGCLRSETALL},
+       {338,   0xffffffff,     0x00160000,     REGCLRSETALL},
+       {362,   0xffffffff,     0x00160000,     REGCLRSETALL},
+       {282,   0xffffff00,     0x17,           REGCLRSETALL},
+       {306,   0xffffff00,     0x17,           REGCLRSETALL},
+       {330,   0xffffff00,     0x17,           REGCLRSETALL},
+       {354,   0xffffff00,     0x17,           REGCLRSETALL},
+       {290,   0xffffff00,     0x17,           REGCLRSETALL},
+       {314,   0xffffff00,     0x17,           REGCLRSETALL},
+       {338,   0xffffff00,     0x17,           REGCLRSETALL},
+       {362,   0xffffff00,     0x17,           REGCLRSETALL},
+       {282,   0xffff00ff,     0x2000,         REGCLRSETALL},
+       {306,   0xffff00ff,     0x2000,         REGCLRSETALL},
+       {330,   0xffff00ff,     0x2000,         REGCLRSETALL},
+       {354,   0xffff00ff,     0x2000,         REGCLRSETALL},
+       {290,   0xffff00ff,     0x2000,         REGCLRSETALL},
+       {314,   0xffff00ff,     0x2000,         REGCLRSETALL},
+       {338,   0xffff00ff,     0x2000,         REGCLRSETALL},
+       {362,   0xffff00ff,     0x2000,         REGCLRSETALL},
+       {65,    0xffffffff,     0x00000100,     (OFFSET_SEL | REGCLRSETALL)},
+       {321,   0xffffffff,     0x00000100,     (OFFSET_SEL | REGCLRSETALL)},
+       {577,   0xffffffff,     0x00000100,     (OFFSET_SEL | REGCLRSETALL)},
+       {833,   0xffffffff,     0x00000100,     (OFFSET_SEL | REGCLRSETALL)},
+       {96,    0x0,            0x300,          (OFFSET_SEL | REGADDSETALL)},
+       {352,   0x0,            0x300,          (OFFSET_SEL | REGADDSETALL)},
+       {608,   0x0,            0x300,          (OFFSET_SEL | REGADDSETALL)},
+       {864,   0x0,            0x300,          (OFFSET_SEL | REGADDSETALL)},
+       {96,    0xff00ffff,     0x00120000,     (OFFSET_SEL | REGCLRSETALL)},
+       {352,   0xff00ffff,     0x00120000,     (OFFSET_SEL | REGCLRSETALL)},
+       {608,   0xff00ffff,     0x00120000,     (OFFSET_SEL | REGCLRSETALL)},
+       {864,   0xff00ffff,     0x00120000,     (OFFSET_SEL | REGCLRSETALL)},
+       {33,    0xffffff00,     0x0040,         (OFFSET_SEL | REGCLRSETALL)},
+       {289,   0xffffff00,     0x0040,         (OFFSET_SEL | REGCLRSETALL)},
+       {545,   0xffffff00,     0x0040,         (OFFSET_SEL | REGCLRSETALL)},
+       {801,   0xffffff00,     0x0040,         (OFFSET_SEL | REGCLRSETALL)},
+       {1038,  0xfcffffff,     0x03000000,     (OFFSET_SEL | REGCLRSETALL)},
+       {1294,  0xfcffffff,     0x03000000,     (OFFSET_SEL | REGCLRSETALL)},
+       {1550,  0xfcffffff,     0x03000000,     (OFFSET_SEL | REGCLRSETALL)},
+       {83,    0xffc0ffff,     0x70000,        (OFFSET_SEL | REGCLRSETALL)},
+       {339,   0xffc0ffff,     0x70000,        (OFFSET_SEL | REGCLRSETALL)},
+       {595,   0xffc0ffff,     0x70000,        (OFFSET_SEL | REGCLRSETALL)},
+       {851,   0xffc0ffff,     0x70000,        (OFFSET_SEL | REGCLRSETALL)},
+       {1062,  0xf800ffff,     0x70000,        (OFFSET_SEL | REGCLRSETALL)},
+       {1318,  0xf800ffff,     0x70000,        (OFFSET_SEL | REGCLRSETALL)},
+       {1574,  0xf800ffff,     0x70000,        (OFFSET_SEL | REGCLRSETALL)},
+       {1892,  0xfffc0000,     0x15547,        (OFFSET_SEL | REGCLRSETALL)},
+       {1893,  0xfffc0000,     0x7,            (OFFSET_SEL | REGCLRSETALL)},
+       {1852,  0xffffe000,     0x07a,          (OFFSET_SEL | REGCLRSETALL)},
+       {1853,  0xffffffff,     0x0100,         (OFFSET_SEL | REGCLRSETALL)},
+       {1822,  0xffffffff,     0xFF,           (OFFSET_SEL | REGCLRSETALL)},
+       {1896,  0xfffffc00,     0x03d5,         (OFFSET_SEL | REGCLRSETALL)},
+       {91,    0xfc00ffff,     0x03d50000,     (OFFSET_SEL | REGCLRSETALL)},
+       {347,   0xfc00ffff,     0x03d50000,     (OFFSET_SEL | REGCLRSETALL)},
+       {603,   0xfc00ffff,     0x03d50000,     (OFFSET_SEL | REGCLRSETALL)},
+       {859,   0xfc00ffff,     0x03d50000,     (OFFSET_SEL | REGCLRSETALL)},
+       {1912,  0x0,            0xcc3bfc7,      (OFFSET_SEL | REGSETALL)},
+       {1913,  0x0,            0xff8f,         (OFFSET_SEL | REGSETALL)},
+       {1914,  0x0,            0x33f07ff,      (OFFSET_SEL | REGSETALL)},
+       {1915,  0x0,            0xc3c37ff,      (OFFSET_SEL | REGSETALL)},
+       {1916,  0x0,            0x1fffff10,     (OFFSET_SEL | REGSETALL)},
+       {1917,  0x0,            0x230070,       (OFFSET_SEL | REGSETALL)},
+       {1918,  0x0,            0x3ff7ffff,     (OFFSET_SEL | REG4G | REG2G | F_SET)},
+       {1918,  0x0,            0x3ff7ffff,     (OFFSET_SEL | REG8G | F_SET)},
+       {1919,  0x0,            0xe10,          (OFFSET_SEL | REGSETALL)},
+       {1920,  0x0,            0x1fffffff,     (OFFSET_SEL | REGSETALL)},
+       {1921,  0x0,            0x188411,       (OFFSET_SEL | REGSETALL)},
+       {1922,  0x0,            0x1fffffff,     (OFFSET_SEL | REGSETALL)},
+       {1923,  0x0,            0x180400,       (OFFSET_SEL | REGSETALL)},
+       {1924,  0x0,            0x1fffffff,     (OFFSET_SEL | REGSETALL)},
+       {1925,  0x0,            0x180400,       (OFFSET_SEL | REGSETALL)},
+       {1926,  0x0,            0x1fffffcf,     (OFFSET_SEL | REGSETALL)},
+       {1927,  0x0,            0x188400,       (OFFSET_SEL | REGSETALL)},
+       {1928,  0x0,            0x1fffffff,     (OFFSET_SEL | REGSETALL)},
+       {1929,  0x0,            0x4188411,      (OFFSET_SEL | REGSETALL)},
+       {1837,  0x0,            0x24410,        (OFFSET_SEL | REGSETALL)},
+       {1840,  0x0,            0x24410,        (OFFSET_SEL | REGSETALL)},
+       {1842,  0x0,            0x2ffff,        (OFFSET_SEL | REGSETALL)},
+       {76,    0xff0000f8,     0x00ff8f07,     (OFFSET_SEL | REGCLRSETALL)},
+       {332,   0xff0000f8,     0x00ff8f07,     (OFFSET_SEL | REGCLRSETALL)},
+       {588,   0xff0000f8,     0x00ff8f07,     (OFFSET_SEL | REGCLRSETALL)},
+       {844,   0xff0000f8,     0x00ff8f07,     (OFFSET_SEL | REGCLRSETALL)},
+       {77,    0xffff0000,     0xff8f,         (OFFSET_SEL | REGCLRSETALL)},
+       {333,   0xffff0000,     0xff8f,         (OFFSET_SEL | REGCLRSETALL)},
+       {589,   0xffff0000,     0xff8f,         (OFFSET_SEL | REGCLRSETALL)},
+       {845,   0xffff0000,     0xff8f,         (OFFSET_SEL | REGCLRSETALL)},
+       {1062,  0xffffff00,     0xff,           (OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
+       {1318,  0xffffff00,     0xff,           (OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
+       {1574,  0xffffff00,     0xff,           (OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
+       {1062,  0xffffff00,     0xfb,           (OFFSET_SEL | REG8G | F_CLRSET)},
+       {1318,  0xffffff00,     0xfb,           (OFFSET_SEL | REG8G | F_CLRSET)},
+       {1574,  0xffffff00,     0xfb,           (OFFSET_SEL | REG8G | F_CLRSET)},
+       {1028,  0xffffffff,     0x1000000,      (OFFSET_SEL | REGCLRSETALL)},
+       {1284,  0xffffffff,     0x1000000,      (OFFSET_SEL | REGCLRSETALL)},
+       {1540,  0xffffffff,     0x1000000,      (OFFSET_SEL | REGCLRSETALL)},
+       {1848,  0x0,            0x3cf07f8,      (OFFSET_SEL | REGSETALL)},
+       {1849,  0x0,            0x3f,           (OFFSET_SEL | REGSETALL)},
+       {1850,  0x0,            0x1fffff,       (OFFSET_SEL | REGSETALL)},
+       {1851,  0x0,            0x060000,       (OFFSET_SEL | REGSETALL)},
+       {130,   0x0000ffff,     0xffff0000,     (OFFSET_SEL | REGCLRSETALL)},
+       {386,   0x0000ffff,     0xffff0000,     (OFFSET_SEL | REGCLRSETALL)},
+       {642,   0x0000ffff,     0xffff0000,     (OFFSET_SEL | REGCLRSETALL)},
+       {898,   0x0000ffff,     0xffff0000,     (OFFSET_SEL | REGCLRSETALL)},
+       {131,   0xfffffff0,     0xf,            (OFFSET_SEL | REGCLRSETALL)},
+       {387,   0xfffffff0,     0xf,            (OFFSET_SEL | REGCLRSETALL)},
+       {643,   0xfffffff0,     0xf,            (OFFSET_SEL | REGCLRSETALL)},
+       {899,   0xfffffff0,     0xf,            (OFFSET_SEL | REGCLRSETALL)},
+       {29,    0xc0ffffff,     0x10000000,     (OFFSET_SEL | REGCLRSETALL)},
+       {285,   0xc0ffffff,     0x10000000,     (OFFSET_SEL | REGCLRSETALL)},
+       {541,   0xc0ffffff,     0x10000000,     (OFFSET_SEL | REGCLRSETALL)},
+       {797,   0xc0ffffff,     0x10000000,     (OFFSET_SEL | REGCLRSETALL)},
+       {30,    0xffffffff,     0x00080000,     (OFFSET_SEL | REGCLRSETALL)},
+       {286,   0xffffffff,     0x00080000,     (OFFSET_SEL | REGCLRSETALL)},
+       {542,   0xffffffff,     0x00080000,     (OFFSET_SEL | REGCLRSETALL)},
+       {798,   0xffffffff,     0x00080000,     (OFFSET_SEL | REGCLRSETALL)},
+       {31,    0xffffffc0,     0x00000010,     (OFFSET_SEL | REGCLRSETALL)},
+       {287,   0xffffffc0,     0x00000010,     (OFFSET_SEL | REGCLRSETALL)},
+       {543,   0xffffffc0,     0x00000010,     (OFFSET_SEL | REGCLRSETALL)},
+       {799,   0xffffffc0,     0x00000010,     (OFFSET_SEL | REGCLRSETALL)},
+       {1071,  0xfffffff0,     0x00000008,     (OFFSET_SEL | REGCLRSETALL)},
+       {1327,  0xfffffff0,     0x00000008,     (OFFSET_SEL | REGCLRSETALL)},
+       {1583,  0xfffffff0,     0x00000008,     (OFFSET_SEL | REGCLRSETALL)},
+       {1808,  0xfffffff0,     0x00000008,     (OFFSET_SEL | REGCLRSETALL)},
+       {1896,  0xfff0ffff,     0x00080000,     (OFFSET_SEL | REGCLRSETALL)},
+};
+
+void ddr_reg_set(u32 *reg, const struct ddr_reg_cfg *data,
+                u32 len, u32 mask)
+{
+       u32 *addr;
+       u32 i;
+
+       for (i = 0; i < len; i++) {
+               if (!(data[i].flag & mask))
+                       continue;
+
+               if (data[i].flag & OFFSET_SEL)
+                       addr = reg + PHY_AC_BASE_ADDR + data[i].offset;
+               else
+                       addr = reg + PHY_BASE_ADDR + data[i].offset;
+
+               if (data[i].flag & F_CLRSET)
+                       DDR_REG_TRIGGER(addr, data[i].mask, data[i].val);
+               else if (data[i].flag & F_SET)
+                       out_le32(addr, data[i].val);
+               else
+                       out_le32(addr, in_le32(addr) + data[i].val);
+       }
+}
+
+void ddr_phy_start(u32 *phyreg, enum ddr_size_t size)
+{
+       u32 len;
+       u32 mask;
+
+       switch (size) {
+       case DDR_SIZE_2G:
+               mask = REG2G;
+               break;
+
+       case DDR_SIZE_4G:
+               mask = REG4G;
+               break;
+
+       case DDR_SIZE_8G:
+               mask = REG8G;
+               break;
+
+       case DDR_SIZE_16G:
+       default:
+               return;
+       };
+
+       len = ARRAY_SIZE(ddr_start_cfg);
+       ddr_reg_set(phyreg, ddr_start_cfg, len, mask);
+       out_le32(phyreg, 0x01);
+}

diff --git a/drivers/ram/starfive/ddrphy_train.c b/drivers/ram/starfive/ddrphy_train.c
new file mode 100644 (file)
index 0000000..0740f49
--- /dev/null
+++ b/drivers/ram/starfive/ddrphy_train.c
@@ -0,0 +1,383 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+static const u32 ddr_train_data[] = {
+       0xb00,
+       0x101,
+       0x640000,
+       0x1,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x1,
+       0x7,
+       0x10002,
+       0x300080f,
+       0x1,
+       0x5,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x1010000,
+       0x280a0000,
+       0x0,
+       0x1,
+       0x3200000f,
+       0x0,
+       0x0,
+       0x10102,
+       0x1,
+       0x0,
+       0x0,
+       0x0,
+       0xaa,
+       0x55,
+       0xb5,
+       0x4a,
+       0x56,
+       0xa9,
+       0xa9,
+       0xb5,
+       0x1000000,
+       0x1000000,
+       0x0,
+       0xf0f0000,
+       0x14,
+       0x7d0,
+       0x300,
+       0x0,
+       0x0,
+       0x1000000,
+       0x10101,
+       0x0,
+       0x30000,
+       0x100,
+       0x170f,
+       0x0,
+       0x0,
+       0x0,
+       0xa140a01,
+       0x204010a,
+       0x2080510,
+       0x40400,
+       0x1000101,
+       0x10100,
+       0x2040f00,
+       0x34000000,
+       0x0,
+       0x0,
+       0x1000000,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x10100,
+       0x80101,
+       0x2000200,
+       0x1000100,
+       0x1000000,
+       0x2000200,
+       0x200,
+       0x0,
+       0x0,
+       0x0,
+       0xe000004,
+       0xc0d100f,
+       0xa09080b,
+       0x2010000,
+       0x80103,
+       0x200,
+       0x0,
+       0xf000000,
+       0x4,
+       0xa,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x30100,
+       0x1010001,
+       0x10200,
+       0x4000103,
+       0x1050001,
+       0x10600,
+       0x107,
+       0x0,
+       0x0,
+       0x10001,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x10000,
+       0x4,
+       0x0,
+       0x10000,
+       0x0,
+       0x3c0003,
+       0x80100a0,
+       0x16,
+       0x2c,
+       0x33,
+       0x20043,
+       0x2000200,
+       0x4,
+       0x60c,
+       0xa1400,
+       0x280000,
+       0x6,
+       0x46,
+       0x70,
+       0x610,
+       0x12b,
+       0x4001035,
+       0x1010404,
+       0x1e01,
+       0x1e001e,
+       0x1000100,
+       0x100,
+       0x0,
+       0x5060403,
+       0x1011108,
+       0x1010101,
+       0xf0a0a,
+       0x0,
+       0x0,
+       0x4000000,
+       0x4021008,
+       0x4020206,
+       0xc0034,
+       0x100038,
+       0x17003f,
+       0x10001,
+       0x10001,
+       0x10005,
+       0x20064,
+       0x100010b,
+       0x60006,
+       0x650100,
+       0x1000065,
+       0x10c010c,
+       0x1e1a1e1a,
+       0x1011e1a,
+       0xa070601,
+       0xa07060d,
+       0x100b080d,
+       0xc00f,
+       0xc01000,
+       0xc01000,
+       0x21000,
+       0x120005,
+       0x190064,
+       0x10b,
+       0x1100,
+       0x1e1a0056,
+       0x6000101,
+       0x130204,
+       0x1e1a0058,
+       0x1000101,
+       0x230408,
+       0x1e1a005e,
+       0x9000101,
+       0x610,
+       0x4040800,
+       0x40100,
+       0x3000277,
+       0xa032001,
+       0xa0a,
+       0x80908,
+       0x901,
+       0x1100315c,
+       0xa062002,
+       0xa0a,
+       0x141708,
+       0x150d,
+       0x2d00838e,
+       0xf102004,
+       0xf0b,
+       0x8c,
+       0x578,
+       0xc20,
+       0x7940,
+       0x206a,
+       0x14424,
+       0x730006,
+       0x3030133,
+       0x4,
+       0x0,
+       0x4,
+       0x1,
+       0x5,
+       0x2,
+       0x6,
+       0x50,
+       0x1,
+       0x5,
+       0x28,
+       0x73,
+       0xd6,
+       0x1,
+       0x5,
+       0x6b,
+       0x1000133,
+       0x140040,
+       0x10001,
+       0x1900040,
+       0x1000c,
+       0x42b0040,
+       0x320,
+       0x360014,
+       0x1010101,
+       0x2020101,
+       0x8080404,
+       0x67676767,
+       0x67676767,
+       0x67676767,
+       0x67676767,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x5500,
+       0x5a00,
+       0x55003c,
+       0x0,
+       0x3c00005a,
+       0x5500,
+       0x5a00,
+       0x55003c,
+       0x0,
+       0x3c00005a,
+       0x18171615,
+       0x14131211,
+       0x7060504,
+       0x3020100,
+       0x0,
+       0x0,
+       0x0,
+       0x1000000,
+       0x4020201,
+       0x80804,
+       0x0,
+       0x4,
+       0x0,
+       0x31,
+       0x31,
+       0x0,
+       0x0,
+       0x4d4d,
+       0x0,
+       0x14,
+       0x9,
+       0x31,
+       0x31,
+       0x0,
+       0x0,
+       0x4d4d,
+       0x0,
+       0x34,
+       0x1b,
+       0x31,
+       0x31,
+       0x0,
+       0x0,
+       0x4d4d,
+       0x0,
+       0x4,
+       0x0,
+       0x31,
+       0x31,
+       0x0,
+       0x0,
+       0x4d4d,
+       0x0,
+       0x14,
+       0x9,
+       0x31,
+       0x31,
+       0x0,
+       0x0,
+       0x4d4d,
+       0x0,
+       0x34,
+       0x1b,
+       0x31,
+       0x31,
+       0x0,
+       0x0,
+       0x4d4d,
+       0x0,
+       0x4,
+       0x0,
+       0x31,
+       0x31,
+       0x0,
+       0x0,
+       0x4d4d,
+       0x0,
+       0x14,
+       0x9,
+       0x31,
+       0x31,
+       0x0,
+       0x0,
+       0x4d4d,
+       0x0,
+       0x34,
+       0x1b,
+       0x31,
+       0x31,
+       0x0,
+       0x0,
+       0x4d4d,
+       0x0,
+       0x4,
+       0x0,
+       0x31,
+       0x31,
+       0x0,
+       0x0,
+       0x4d4d,
+       0x0,
+       0x14,
+       0x9,
+       0x31,
+       0x31,
+       0x0,
+       0x0,
+       0x4d4d,
+       0x0,
+       0x34,
+       0x1b,
+       0x31,
+       0x31,
+       0x0,
+       0x0,
+       0x4d4d,
+};
+
+void ddr_phy_train(u32 *phyreg)
+{
+       u32 i, len;
+
+       len = ARRAY_SIZE(ddr_train_data);
+       for (i = 0; i < len; i++)
+               out_le32(phyreg + i, ddr_train_data[i]);
+}

diff --git a/drivers/ram/starfive/ddrphy_utils.c b/drivers/ram/starfive/ddrphy_utils.c
new file mode 100644 (file)
index 0000000..1c9fe0a
--- /dev/null
+++ b/drivers/ram/starfive/ddrphy_utils.c
@@ -0,0 +1,1955 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+static const  u32 ddr_phy_data[] = {
+       0x4f0,
+       0x0,
+       0x1030200,
+       0x0,
+       0x0,
+       0x3000000,
+       0x1000001,
+       0x3000400,
+       0x1000001,
+       0x0,
+       0x0,
+       0x1000001,
+       0x0,
+       0xc00004,
+       0xcc0008,
+       0x660601,
+       0x3,
+       0x0,
+       0x1,
+       0xaaaa,
+       0x5555,
+       0xb5b5,
+       0x4a4a,
+       0x5656,
+       0xa9a9,
+       0xa9a9,
+       0xb5b5,
+       0x0,
+       0x0,
+       0x8000000,
+       0x4000008,
+       0x408,
+       0xe4e400,
+       0x71020,
+       0xc0020,
+       0x620,
+       0x100,
+       0x55555555,
+       0xaaaaaaaa,
+       0x55555555,
+       0xaaaaaaaa,
+       0x5555,
+       0x1000100,
+       0x800180,
+       0x1,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x4,
+       0x20,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x7ff0000,
+       0x20008008,
+       0x810,
+       0x40100,
+       0x0,
+       0x1880c01,
+       0x2003880c,
+       0x20000125,
+       0x7ff0200,
+       0x101,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x20000,
+       0x51515052,
+       0x31c06000,
+       0x11f0004,
+       0xc0c001,
+       0x3000000,
+       0x30202,
+       0x42100010,
+       0x10c053e,
+       0xf0c20,
+       0x1000140,
+       0xa30120,
+       0xc00,
+       0x210,
+       0x200,
+       0x2800000,
+       0x80800101,
+       0x3,
+       0x76543210,
+       0x8,
+       0x2800280,
+       0x2800280,
+       0x2800280,
+       0x2800280,
+       0x280,
+       0x8000,
+       0x800080,
+       0x800080,
+       0x800080,
+       0x800080,
+       0x800080,
+       0x800080,
+       0x800080,
+       0x800080,
+       0x6e0080,
+       0x1a00003,
+       0x0,
+       0x30000,
+       0x80200,
+       0x0,
+       0x20202020,
+       0x20202020,
+       0x2020,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x4f0,
+       0x0,
+       0x1030200,
+       0x0,
+       0x0,
+       0x3000000,
+       0x1000001,
+       0x3000400,
+       0x1000001,
+       0x0,
+       0x0,
+       0x1000001,
+       0x0,
+       0xc00004,
+       0xcc0008,
+       0x660601,
+       0x3,
+       0x0,
+       0x1,
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+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x100,
+       0x200,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x400000,
+       0x80,
+       0xdcba98,
+       0x3000000,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x2a,
+       0x15,
+       0x15,
+       0x2a,
+       0x33,
+       0xc,
+       0xc,
+       0x33,
+       0x0,
+       0x0,
+       0x0,
+       0x20202000,
+       0x202020,
+       0x20008008,
+       0x810,
+       0x0,
+       0x255,
+       0x30000,
+       0x300,
+       0x300,
+       0x300,
+       0x300,
+       0x300,
+       0x42080010,
+       0x33e,
+       0x1010002,
+       0x80,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x100,
+       0x200,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x400000,
+       0x80,
+       0xdcba98,
+       0x3000000,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x2a,
+       0x15,
+       0x15,
+       0x2a,
+       0x33,
+       0xc,
+       0xc,
+       0x33,
+       0x0,
+       0x10000000,
+       0x0,
+       0x20202000,
+       0x202020,
+       0x20008008,
+       0x810,
+       0x0,
+       0x255,
+       0x30000,
+       0x300,
+       0x300,
+       0x300,
+       0x300,
+       0x300,
+       0x42080010,
+       0x33e,
+       0x1010002,
+       0x80,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x100,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x50000,
+       0x4000000,
+       0x55,
+       0x0,
+       0x0,
+       0x0,
+       0xf0001,
+       0x280040,
+       0x5002,
+       0x10101,
+       0x8008,
+       0x81020,
+       0x0,
+       0x0,
+       0x1000000,
+       0x1,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x64,
+       0x0,
+       0x0,
+       0x1010000,
+       0x2020101,
+       0x4040202,
+       0x8080404,
+       0xf0f0808,
+       0xf0f0f0f,
+       0x20200f0f,
+       0x1b428000,
+       0x4,
+       0x1010000,
+       0x1070501,
+       0x54,
+       0x4410,
+       0x4410,
+       0x4410,
+       0x4410,
+       0x4410,
+       0x4410,
+       0x4410,
+       0x4410,
+       0x4410,
+       0x4410,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x64,
+       0x0,
+       0x108,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x3000000,
+       0x0,
+       0x0,
+       0x0,
+       0x4102035,
+       0x41020,
+       0x1c98c98,
+       0x3f400000,
+       0x3f3f1f3f,
+       0x1f3f3f1f,
+       0x1f3f3f,
+       0x0,
+       0x0,
+       0x1,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x76543210,
+       0x6010198,
+       0x0,
+       0x0,
+       0x0,
+       0x40700,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x2,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x1142,
+       0x3020100,
+       0x3000300,
+       0x3000300,
+       0x3000300,
+       0x3000300,
+       0x3000300,
+       0x3000300,
+       0x3000300,
+       0x3000300,
+       0x3000300,
+       0x3000300,
+       0x300,
+       0x300,
+       0x300,
+       0x300,
+       0x2,
+       0x4011,
+       0x4011,
+       0x40,
+       0x40,
+       0x4011,
+       0x1fff00,
+       0x4011,
+       0x4011,
+       0x4011,
+       0x4011,
+       0x4011,
+       0x4011,
+       0x4011,
+       0x4011,
+       0x4011,
+       0x4011,
+       0x4011,
+       0x1004011,
+       0x200400,
+
+};
+
+void ddr_phy_util(u32 *phyreg)
+{
+       u32 i, len;
+
+       len = ARRAY_SIZE(ddr_phy_data);
+       for (i = 1792; i < len; i++)
+               out_le32(phyreg + i, ddr_phy_data[i]);
+
+       for (i = 0; i < 1792; i++)
+               out_le32(phyreg + i, ddr_phy_data[i]);
+}

diff --git a/drivers/ram/starfive/starfive_ddr.c b/drivers/ram/starfive/starfive_ddr.c
new file mode 100644 (file)
index 0000000..553f2ce
--- /dev/null
+++ b/drivers/ram/starfive/starfive_ddr.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/arch/regs.h>
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/bitops.h>
+#include <linux/sizes.h>
+#include <linux/delay.h>
+#include <ram.h>
+#include <reset.h>
+
+#include "starfive_ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct starfive_ddr_priv {
+       struct udevice  *dev;
+       struct ram_info info;
+       void __iomem    *ctrlreg;
+       void __iomem    *phyreg;
+       struct reset_ctl_bulk rst;
+       struct clk      clk;
+       u32     fre;
+};
+
+static int starfive_ddr_setup(struct udevice *dev, struct starfive_ddr_priv *priv)
+{
+       enum ddr_size_t size;
+
+       switch (priv->info.size) {
+       case SZ_2G:
+               size = DDR_SIZE_2G;
+               break;
+
+       case SZ_4G:
+               size = DDR_SIZE_4G;
+               break;
+
+       case 0x200000000:
+               size = DDR_SIZE_8G;
+               break;
+
+       case 0x400000000:
+       default:
+               pr_err("unsupport size %lx\n", priv->info.size);
+               return -EINVAL;
+       }
+
+       ddr_phy_train(priv->phyreg + (PHY_BASE_ADDR << 2));
+       ddr_phy_util(priv->phyreg + (PHY_AC_BASE_ADDR << 2));
+       ddr_phy_start(priv->phyreg, size);
+
+       DDR_REG_SET(BUS, DDR_BUS_OSC_DIV2);
+       ddrcsr_boot(priv->ctrlreg, priv->ctrlreg + SEC_CTRL_ADDR,
+                   priv->phyreg, size);
+
+       return 0;
+}
+
+static int starfive_ddr_probe(struct udevice *dev)
+{
+       struct starfive_ddr_priv *priv = dev_get_priv(dev);
+       fdt_addr_t addr;
+       u64 rate;
+       int ret;
+
+       /* Read memory base and size from DT */
+       fdtdec_setup_mem_size_base();
+       priv->info.base = gd->ram_base;
+       priv->info.size = gd->ram_size;
+
+       priv->dev = dev;
+       addr = dev_read_addr_index(dev, 0);
+       if (addr == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       priv->ctrlreg = (void __iomem *)addr;
+       addr = dev_read_addr_index(dev, 1);
+       if (addr == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       priv->phyreg = (void __iomem *)addr;
+       ret = dev_read_u32(dev, "clock-frequency", &priv->fre);
+       if (ret)
+               return ret;
+
+       switch (priv->fre) {
+       case 2133:
+               rate = 1066000000;
+               break;
+
+       case 2800:
+               rate = 1400000000;
+               break;
+
+       default:
+               pr_err("Unknown DDR frequency %d\n", priv->fre);
+               return  -EINVAL;
+       };
+
+       ret = reset_get_bulk(dev, &priv->rst);
+       if (ret)
+               return ret;
+
+       ret = reset_deassert_bulk(&priv->rst);
+       if (ret < 0)
+               return ret;
+
+       ret = clk_get_by_index(dev, 0, &priv->clk);
+       if (ret)
+               goto err_free_reset;
+
+       ret = clk_set_rate(&priv->clk, rate);
+       if (ret < 0)
+               goto err_free_reset;
+
+       ret = starfive_ddr_setup(dev, priv);
+       printf("DDR version: dc2e84f0.\n");
+
+       return ret;
+
+err_free_reset:
+       reset_release_bulk(&priv->rst);
+
+       return ret;
+}
+
+static int starfive_ddr_get_info(struct udevice *dev, struct ram_info *info)
+{
+       struct starfive_ddr_priv *priv = dev_get_priv(dev);
+
+       *info = priv->info;
+
+       return 0;
+}
+
+static struct ram_ops starfive_ddr_ops = {
+       .get_info = starfive_ddr_get_info,
+};
+
+static const struct udevice_id starfive_ddr_ids[] = {
+       { .compatible = "starfive,jh7110-dmc" },
+       { }
+};
+
+U_BOOT_DRIVER(starfive_ddr) = {
+       .name = "starfive_ddr",
+       .id = UCLASS_RAM,
+       .of_match = starfive_ddr_ids,
+       .ops = &starfive_ddr_ops,
+       .probe = starfive_ddr_probe,
+       .priv_auto = sizeof(struct starfive_ddr_priv),
+};

diff --git a/drivers/ram/starfive/starfive_ddr.h b/drivers/ram/starfive/starfive_ddr.h
new file mode 100644 (file)
index 0000000..d0ec1c1
--- /dev/null
+++ b/drivers/ram/starfive/starfive_ddr.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#ifndef __STARFIVE_DDR_H__
+#define __STARFIVE_DDR_H__
+
+#define SEC_CTRL_ADDR          0x1000
+#define PHY_BASE_ADDR          0x800
+#define PHY_AC_BASE_ADDR       0x1000
+
+#define DDR_BUS_MASK           GENMASK(29, 24)
+#define DDR_AXI_MASK           BIT(31)
+#define DDR_BUS_OFFSET         0xAC
+#define DDR_AXI_OFFSET         0xB0
+
+#define DDR_BUS_OSC_DIV2       0
+#define DDR_BUS_PLL1_DIV2      1
+#define DDR_BUS_PLL1_DIV4      2
+#define DDR_BUS_PLL1_DIV8      3
+#define DDR_AXI_DISABLE                0
+#define DDR_AXI_ENABLE         1
+
+#define OFFSET_SEL             BIT(31)
+#define REG2G                  BIT(30)
+#define REG4G                  BIT(29)
+#define REG8G                  BIT(28)
+#define F_ADDSET               BIT(2)
+#define F_SET                  BIT(1)
+#define F_CLRSET               BIT(0)
+#define REGALL                 (REG2G | REG4G | REG8G)
+#define REGSETALL              (F_SET | REGALL)
+#define REGCLRSETALL           (F_CLRSET | REGALL)
+#define REGADDSETALL           (F_ADDSET | REGALL)
+
+struct ddr_reg_cfg {
+       u32 offset;
+       u32 mask;
+       u32 val;
+       u32 flag;
+};
+
+enum ddr_size_t {
+       DDR_SIZE_2G,
+       DDR_SIZE_4G,
+       DDR_SIZE_8G,
+       DDR_SIZE_16G,
+};
+
+void ddr_phy_train(u32 *phyreg);
+void ddr_phy_util(u32 *phyreg);
+void ddr_phy_start(u32 *phyreg, enum ddr_size_t size);
+void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size);
+
+#define DDR_REG_TRIGGER(addr, mask, value) \
+       out_le32((addr), (in_le32(addr) & (mask)) | (value))
+
+#define DDR_REG_SET(type, val) \
+       clrsetbits_le32(JH7110_SYS_CRG + DDR_##type##_OFFSET, \
+               DDR_##type##_MASK, \
+               ((val) << __ffs(DDR_##type##_MASK)) & DDR_##type##_MASK)
+
+#endif /*__STARFIVE_DDR_H__*/

diff --git a/drivers/ram/stm32mp1/stm32mp1_interactive.c b/drivers/ram/stm32mp1/stm32mp1_interactive.c
index f0fe7e6..2c19847 100644 (file)
--- a/drivers/ram/stm32mp1/stm32mp1_interactive.c
+++ b/drivers/ram/stm32mp1/stm32mp1_interactive.c
@@ -391,7 +391,7 @@ bool stm32mp1_ddr_interactive(void *priv,
        if (next_step < 0)
                return false;
 
-       if (step < 0 || step > ARRAY_SIZE(step_str)) {
+       if (step < 0 || step >= ARRAY_SIZE(step_str)) {
                printf("** step %d ** INVALID\n", step);
                return false;
        }

diff --git a/drivers/remoteproc/ti_k3_arm64_rproc.c b/drivers/remoteproc/ti_k3_arm64_rproc.c
index 1f2415d..99f1100 100644 (file)
--- a/drivers/remoteproc/ti_k3_arm64_rproc.c
+++ b/drivers/remoteproc/ti_k3_arm64_rproc.c
@@ -36,6 +36,8 @@
  * @gtc_base:          Timer base address.
  */
 struct k3_arm64_privdata {
+       bool has_cluster_node;
+       struct power_domain cluster_pwrdmn;
        struct power_domain rproc_pwrdmn;
        struct power_domain gtc_pwrdmn;
        struct reset_ctl rproc_rst;
@@ -55,6 +57,7 @@ struct k3_arm64_privdata {
 static int k3_arm64_load(struct udevice *dev, ulong addr, ulong size)
 {
        struct k3_arm64_privdata *rproc = dev_get_priv(dev);
+       ulong gtc_rate;
        int ret;
 
        dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size);
@@ -64,26 +67,10 @@ static int k3_arm64_load(struct udevice *dev, ulong addr, ulong size)
        if (ret)
                return ret;
 
-       return ti_sci_proc_set_config(&rproc->tsp, addr, 0, 0);
-}
-
-/**
- * k3_arm64_start() - Start the remote processor
- * @dev:       rproc device pointer
- *
- * Return: 0 if all went ok, else return appropriate error
- */
-static int k3_arm64_start(struct udevice *dev)
-{
-       struct k3_arm64_privdata *rproc = dev_get_priv(dev);
-       ulong gtc_rate;
-       int ret;
-
-       dev_dbg(dev, "%s\n", __func__);
-
        ret = power_domain_on(&rproc->gtc_pwrdmn);
        if (ret) {
-               dev_err(dev, "power_domain_on() failed: %d\n", ret);
+               dev_err(dev, "power_domain_on(&rproc->gtc_pwrdmn) failed: %d\n",
+                       ret);
                return ret;
        }
 
@@ -100,9 +87,36 @@ static int k3_arm64_start(struct udevice *dev)
         * assigned-clock-rates during the device probe. So no need to
         * set the frequency again here.
         */
+       if (rproc->has_cluster_node) {
+               ret = power_domain_on(&rproc->cluster_pwrdmn);
+               if (ret) {
+                       dev_err(dev,
+                               "power_domain_on(&rproc->cluster_pwrdmn) failed: %d\n",
+                               ret);
+                       return ret;
+               }
+       }
+
+       return ti_sci_proc_set_config(&rproc->tsp, addr, 0, 0);
+}
+
+/**
+ * k3_arm64_start() - Start the remote processor
+ * @dev:       rproc device pointer
+ *
+ * Return: 0 if all went ok, else return appropriate error
+ */
+static int k3_arm64_start(struct udevice *dev)
+{
+       struct k3_arm64_privdata *rproc = dev_get_priv(dev);
+       int ret;
+
+       dev_dbg(dev, "%s\n", __func__);
        ret = power_domain_on(&rproc->rproc_pwrdmn);
        if (ret) {
-               dev_err(dev, "power_domain_on() failed: %d\n", ret);
+               dev_err(dev,
+                       "power_domain_on(&rproc->rproc_pwrdmn) failed: %d\n",
+                       ret);
                return ret;
        }
 
@@ -166,9 +180,17 @@ static int k3_arm64_of_to_priv(struct udevice *dev,
 
        dev_dbg(dev, "%s\n", __func__);
 
+       /* Cluster needs to be powered on if firewalls are being configured */
+       rproc->has_cluster_node = true;
+       ret = power_domain_get_by_index(dev, &rproc->cluster_pwrdmn, 2);
+       if (ret) {
+               dev_dbg(dev, "warning: power_domain_get_cluster() failed: %d\n", ret);
+               rproc->has_cluster_node = false;
+       }
+
        ret = power_domain_get_by_index(dev, &rproc->rproc_pwrdmn, 1);
        if (ret) {
-               dev_err(dev, "power_domain_get() failed: %d\n", ret);
+               dev_err(dev, "power_domain_get_rproc() failed: %d\n", ret);
                return ret;
        }
 

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index e4039d7..73bbd30 100644 (file)
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -172,6 +172,22 @@ config RESET_SIFIVE
          different hw blocks like DDR, gemgxl. With this driver we leverage
          U-Boot's reset framework to reset these hardware blocks.
 
+config RESET_JH7110
+       bool "Reset driver for StarFive JH7110 SoC"
+       depends on DM_RESET && STARFIVE_JH7110
+       default y
+       help
+         Support for reset controller on StarFive
+         JH7110 SoCs.
+
+config SPL_RESET_JH7110
+       bool "SPL Reset driver for StarFive JH7110 SoC"
+       depends on SPL && STARFIVE_JH7110
+       default y
+       help
+         Support for reset controller on StarFive
+         JH7110 SoCs in SPL.
+
 config RESET_SYSCON
        bool "Enable generic syscon reset driver support"
        depends on DM_RESET

diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 6c8b45e..6801268 100644 (file)
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -32,3 +32,4 @@ obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
 obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o
 obj-$(CONFIG_RESET_DRA7) += reset-dra7.o
 obj-$(CONFIG_RESET_AT91) += reset-at91.o
+obj-$(CONFIG_$(SPL_TPL_)RESET_JH7110) += reset-jh7110.o

diff --git a/drivers/reset/reset-jh7110.c b/drivers/reset/reset-jh7110.c
new file mode 100644 (file)
index 0000000..d6bdf6b
--- /dev/null
+++ b/drivers/reset/reset-jh7110.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author:     Yanhong Wang <yanhong.wang@starfivetech.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/ofnode.h>
+#include <dt-bindings/reset/starfive,jh7110-crg.h>
+#include <errno.h>
+#include <linux/iopoll.h>
+#include <reset-uclass.h>
+
+struct jh7110_reset_priv {
+       void __iomem *reg;
+       u32     assert;
+       u32     status;
+       u32     resets;
+};
+
+struct reset_info {
+       const char *compat;
+       const u32 nr_resets;
+       const u32 assert_offset;
+       const u32 status_offset;
+};
+
+static const struct reset_info jh7110_rst_info[] = {
+       {
+               .compat = "starfive,jh7110-syscrg",
+               .nr_resets = JH7110_SYSRST_END,
+               .assert_offset = 0x2F8,
+               .status_offset = 0x308,
+       },
+       {
+               .compat = "starfive,jh7110-aoncrg",
+               .nr_resets = JH7110_AONRST_END,
+               .assert_offset = 0x38,
+               .status_offset = 0x3C,
+       },
+       {
+               .compat = "starfive,jh7110-stgcrg",
+               .nr_resets = JH7110_STGRST_END,
+               .assert_offset = 0x74,
+               .status_offset = 0x78,
+       }
+};
+
+static const struct reset_info *jh7110_reset_get_cfg(const char *compat)
+{
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(jh7110_rst_info); i++)
+               if (!strcmp(compat, jh7110_rst_info[i].compat))
+                       return &jh7110_rst_info[i];
+
+       return NULL;
+}
+
+static int jh7110_reset_trigger(struct jh7110_reset_priv *priv,
+                               unsigned long id, bool assert)
+{
+       ulong group;
+       u32 mask, value, done = 0;
+       ulong addr;
+
+       group = id / 32;
+       mask = BIT(id % 32);
+
+       if (!assert)
+               done ^= mask;
+
+       addr = (ulong)priv->reg + priv->assert + group * sizeof(u32);
+       value = readl((ulong *)addr);
+
+       if (assert)
+               value |= mask;
+       else
+               value &= ~mask;
+
+       writel(value, (ulong *)addr);
+       addr = (ulong)priv->reg + priv->status + group * sizeof(u32);
+
+       return readl_poll_timeout((ulong *)addr, value,
+                                               (value & mask) == done, 1000);
+}
+
+static int jh7110_reset_assert(struct reset_ctl *rst)
+{
+       struct jh7110_reset_priv *priv = dev_get_priv(rst->dev);
+
+       jh7110_reset_trigger(priv, rst->id, true);
+
+       return 0;
+}
+
+static int jh7110_reset_deassert(struct reset_ctl *rst)
+{
+       struct jh7110_reset_priv *priv = dev_get_priv(rst->dev);
+
+       jh7110_reset_trigger(priv, rst->id, false);
+
+       return 0;
+}
+
+static int jh7110_reset_free(struct reset_ctl *rst)
+{
+       return 0;
+}
+
+static int jh7110_reset_request(struct reset_ctl *rst)
+{
+       struct jh7110_reset_priv *priv = dev_get_priv(rst->dev);
+
+       if (rst->id >= priv->resets)
+               return -EINVAL;
+
+       return 0;
+}
+
+static int jh7110_reset_probe(struct udevice *dev)
+{
+       struct jh7110_reset_priv *priv = dev_get_priv(dev);
+       const struct reset_info *cfg;
+       const char *compat;
+
+       compat = ofnode_get_property(dev_ofnode(dev), "compatible", NULL);
+       if (!compat)
+               return -EINVAL;
+
+       cfg = jh7110_reset_get_cfg(compat);
+       if (!cfg)
+               return -EINVAL;
+
+       priv->assert = cfg->assert_offset;
+       priv->status = cfg->status_offset;
+       priv->resets = cfg->nr_resets;
+       priv->reg = (void __iomem *)dev_read_addr_index(dev, 0);
+
+       return 0;
+}
+
+const struct reset_ops jh7110_reset_reset_ops = {
+       .rfree = jh7110_reset_free,
+       .request = jh7110_reset_request,
+       .rst_assert = jh7110_reset_assert,
+       .rst_deassert = jh7110_reset_deassert,
+};
+
+U_BOOT_DRIVER(jh7110_reset) = {
+       .name = "jh7110_reset",
+       .id = UCLASS_RESET,
+       .ops = &jh7110_reset_reset_ops,
+       .probe = jh7110_reset_probe,
+       .priv_auto = sizeof(struct jh7110_reset_priv),
+};

diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index 5dcf681..5deb5db 100644 (file)
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -58,8 +58,9 @@ config RNG_ROCKCHIP
        bool "Enable random number generator for rockchip crypto rng"
        depends on ARCH_ROCKCHIP && DM_RNG
        help
-         Enable random number generator for rockchip.This driver is
-         support rng module of crypto v1 and crypto v2.
+         Enable random number generator for rockchip. This driver
+         supports the rng module of crypto v1, crypto v2, and the
+         trng module of the rk3588 series.
 
 config RNG_IPROC200
        bool "Broadcom iProc RNG200 random number generator"

diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c
index 800150f..705b424 100644 (file)
--- a/drivers/rng/rockchip_rng.c
+++ b/drivers/rng/rockchip_rng.c
@@ -43,9 +43,41 @@
 #define CRYPTO_V2_RNG_DOUT_0                   0x0410
 /* end of CRYPTO V2 register define */
 
+/* start of TRNG V1 register define */
+#define TRNG_V1_CTRL                           0x0000
+#define TRNG_V1_CTRL_NOP                       _SBF(0, 0x00)
+#define TRNG_V1_CTRL_RAND                      _SBF(0, 0x01)
+#define TRNG_V1_CTRL_SEED                      _SBF(0, 0x02)
+
+#define TRNG_V1_MODE                           0x0008
+#define TRNG_V1_MODE_128_BIT                   _SBF(3, 0x00)
+#define TRNG_V1_MODE_256_BIT                   _SBF(3, 0x01)
+
+#define TRNG_V1_IE                             0x0010
+#define TRNG_V1_IE_GLBL_EN                     BIT(31)
+#define TRNG_V1_IE_SEED_DONE_EN                        BIT(1)
+#define TRNG_V1_IE_RAND_RDY_EN                 BIT(0)
+
+#define TRNG_V1_ISTAT                          0x0014
+#define TRNG_V1_ISTAT_RAND_RDY                 BIT(0)
+
+/* RAND0 ~ RAND7 */
+#define TRNG_V1_RAND0                          0x0020
+#define TRNG_V1_RAND7                          0x003C
+
+#define TRNG_V1_AUTO_RQSTS                     0x0060
+
+#define TRNG_V1_VERSION                                0x00F0
+#define TRNG_v1_VERSION_CODE                   0x46BC
+/* end of TRNG V1 register define */
+
 #define RK_RNG_TIME_OUT        50000  /* max 50ms */
 
+#define trng_write(pdata, pos, val)    writel(val, (pdata)->base + (pos))
+#define trng_read(pdata, pos)          readl((pdata)->base + (pos))
+
 struct rk_rng_soc_data {
+       int (*rk_rng_init)(struct udevice *dev);
        int (*rk_rng_read)(struct udevice *dev, void *data, size_t len);
 };
 
@@ -75,7 +107,7 @@ static int rk_rng_read_regs(fdt_addr_t addr, void *buf, size_t size)
        return 0;
 }
 
-static int rk_v1_rng_read(struct udevice *dev, void *data, size_t len)
+static int rk_cryptov1_rng_read(struct udevice *dev, void *data, size_t len)
 {
        struct rk_rng_plat *pdata = dev_get_priv(dev);
        u32 reg = 0;
@@ -106,7 +138,7 @@ exit:
        return 0;
 }
 
-static int rk_v2_rng_read(struct udevice *dev, void *data, size_t len)
+static int rk_cryptov2_rng_read(struct udevice *dev, void *data, size_t len)
 {
        struct rk_rng_plat *pdata = dev_get_priv(dev);
        u32 reg = 0;
@@ -140,6 +172,63 @@ exit:
        return retval;
 }
 
+static int rk_trngv1_init(struct udevice *dev)
+{
+       u32 status, version;
+       u32 auto_reseed_cnt = 1000;
+       struct rk_rng_plat *pdata = dev_get_priv(dev);
+
+       version = trng_read(pdata, TRNG_V1_VERSION);
+       if (version != TRNG_v1_VERSION_CODE) {
+               printf("wrong trng version, expected = %08x, actual = %08x",
+                      TRNG_V1_VERSION, version);
+               return -EFAULT;
+       }
+
+       /* wait in case of RND_RDY triggered at firs power on */
+       readl_poll_timeout(pdata->base + TRNG_V1_ISTAT, status,
+                          (status & TRNG_V1_ISTAT_RAND_RDY),
+                          RK_RNG_TIME_OUT);
+
+       /* clear RAND_RDY flag for first power on */
+       trng_write(pdata, TRNG_V1_ISTAT, status);
+
+       /* auto reseed after (auto_reseed_cnt * 16) byte rand generate */
+       trng_write(pdata, TRNG_V1_AUTO_RQSTS, auto_reseed_cnt);
+
+       return 0;
+}
+
+static int rk_trngv1_rng_read(struct udevice *dev, void *data, size_t len)
+{
+       struct rk_rng_plat *pdata = dev_get_priv(dev);
+       u32 reg = 0;
+       int retval;
+
+       if (len > RK_HW_RNG_MAX)
+               return -EINVAL;
+
+       trng_write(pdata, TRNG_V1_MODE, TRNG_V1_MODE_256_BIT);
+       trng_write(pdata, TRNG_V1_CTRL, TRNG_V1_CTRL_RAND);
+
+       retval = readl_poll_timeout(pdata->base + TRNG_V1_ISTAT, reg,
+                                   (reg & TRNG_V1_ISTAT_RAND_RDY),
+                                   RK_RNG_TIME_OUT);
+       /* clear ISTAT */
+       trng_write(pdata, TRNG_V1_ISTAT, reg);
+
+       if (retval)
+               goto exit;
+
+       rk_rng_read_regs(pdata->base + TRNG_V1_RAND0, data, len);
+
+exit:
+       /* close TRNG */
+       trng_write(pdata, TRNG_V1_CTRL, TRNG_V1_CTRL_NOP);
+
+       return retval;
+}
+
 static int rockchip_rng_read(struct udevice *dev, void *data, size_t len)
 {
        unsigned char *buf = data;
@@ -184,18 +273,27 @@ static int rockchip_rng_of_to_plat(struct udevice *dev)
 static int rockchip_rng_probe(struct udevice *dev)
 {
        struct rk_rng_plat *pdata = dev_get_priv(dev);
+       int ret = 0;
 
        pdata->soc_data = (struct rk_rng_soc_data *)dev_get_driver_data(dev);
 
-       return 0;
+       if (pdata->soc_data->rk_rng_init)
+               ret = pdata->soc_data->rk_rng_init(dev);
+
+       return ret;
 }
 
-static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
-       .rk_rng_read = rk_v1_rng_read,
+static const struct rk_rng_soc_data rk_cryptov1_soc_data = {
+       .rk_rng_read = rk_cryptov1_rng_read,
+};
+
+static const struct rk_rng_soc_data rk_cryptov2_soc_data = {
+       .rk_rng_read = rk_cryptov2_rng_read,
 };
 
-static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
-       .rk_rng_read = rk_v2_rng_read,
+static const struct rk_rng_soc_data rk_trngv1_soc_data = {
+       .rk_rng_init = rk_trngv1_init,
+       .rk_rng_read = rk_trngv1_rng_read,
 };
 
 static const struct dm_rng_ops rockchip_rng_ops = {
@@ -205,11 +303,15 @@ static const struct dm_rng_ops rockchip_rng_ops = {
 static const struct udevice_id rockchip_rng_match[] = {
        {
                .compatible = "rockchip,cryptov1-rng",
-               .data = (ulong)&rk_rng_v1_soc_data,
+               .data = (ulong)&rk_cryptov1_soc_data,
        },
        {
                .compatible = "rockchip,cryptov2-rng",
-               .data = (ulong)&rk_rng_v2_soc_data,
+               .data = (ulong)&rk_cryptov2_soc_data,
+       },
+       {
+               .compatible = "rockchip,trngv1",
+               .data = (ulong)&rk_trngv1_soc_data,
        },
        {},
 };

diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig
index ad484ce..a801412 100644 (file)
--- a/drivers/scsi/Kconfig
+++ b/drivers/scsi/Kconfig
@@ -26,7 +26,7 @@ config SCSI_AHCI_PLAT
          This is deprecated. An AHCI driver should be provided instead.
 
 config SYS_SCSI_MAX_SCSI_ID
-       int "Maximum supporedt SCSI ID"
+       int "Maximum supported SCSI ID"
        default 1
        help
          Sets the maximum number of SCSI IDs to scan when looking for devices.

diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 77d3f37..067fae2 100644 (file)
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -31,7 +31,7 @@ static const unsigned long baudrate_table[] = CFG_SYS_BAUDRATE_TABLE;
 static int serial_check_stdout(const void *blob, struct udevice **devp)
 {
        int node = -1;
-       const char *str, *p, *name;
+       const char *str, *p;
        int namelen;
 
        /* Check for a chosen console */
@@ -39,20 +39,16 @@ static int serial_check_stdout(const void *blob, struct udevice **devp)
        if (str) {
                p = strchr(str, ':');
                namelen = p ? p - str : strlen(str);
+               /*
+                * This also deals with things like
+                *
+                *      stdout-path = "serial0:115200n8";
+                *
+                * since fdt_path_offset_namelen() treats a str not
+                * beginning with '/' as an alias and thus applies
+                * fdt_get_alias_namelen() to it.
+                */
                node = fdt_path_offset_namelen(blob, str, namelen);
-
-               if (node < 0) {
-                       /*
-                        * Deal with things like
-                        *      stdout-path = "serial0:115200n8";
-                        *
-                        * We need to look up the alias and then follow it to
-                        * the correct node.
-                        */
-                       name = fdt_get_alias_namelen(blob, str, namelen);
-                       if (name)
-                               node = fdt_path_offset(blob, name);
-               }
        }
 
        if (node < 0)

diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index e08bdca..20cda5d 100644 (file)
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -57,6 +57,9 @@ static void sh_serial_init_generic(struct uart_port *port)
 #if defined(CONFIG_RZA1)
        sci_out(port, SCSPTR, 0x0003);
 #endif
+
+       if (port->type == PORT_HSCIF)
+               sci_out(port, HSSRR, HSSRR_SRE | HSSRR_SRCYC8);
 }
 
 static void
@@ -205,6 +208,7 @@ static const struct udevice_id sh_serial_id[] ={
        {.compatible = "renesas,sci", .data = PORT_SCI},
        {.compatible = "renesas,scif", .data = PORT_SCIF},
        {.compatible = "renesas,scifa", .data = PORT_SCIFA},
+       {.compatible = "renesas,hscif", .data = PORT_HSCIF},
        {}
 };
 
@@ -257,6 +261,8 @@ U_BOOT_DRIVER(serial_sh) = {
        #define SCIF_BASE_PORT  PORT_SCIFA
 #elif defined(CFG_SCI)
        #define SCIF_BASE_PORT  PORT_SCI
+#elif defined(CFG_HSCIF)
+       #define SCIF_BASE_PORT  PORT_HSCIF
 #else
        #define SCIF_BASE_PORT  PORT_SCIF
 #endif

diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index eb8523d..149ec1f 100644 (file)
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -89,7 +89,7 @@ struct uart_port {
 # define SCSPTR7 0xe800a820 /* 16 bit SCIF */
 # define SCSCR_INIT(port)      0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 # define SCIF_ORER 0x0001  /* overrun error bit */
-#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || \
+#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_64) || \
       defined(CONFIG_R7S72100)
 # if defined(CFG_SCIF_A)
 #  define SCIF_ORER    0x0200
@@ -213,6 +213,10 @@ struct uart_port {
 #define SCFCR_TCRST 0x4000
 #define SCFCR_MCE   0x0008
 
+/* HSSRR */
+#define HSSRR_SRE      BIT(15)
+#define HSSRR_SRCYC8   0x0007
+
 #define SCI_MAJOR              204
 #define SCI_MINOR_START                8
 
@@ -242,7 +246,8 @@ struct uart_port {
 
 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
        static inline unsigned int sci_##name##_in(struct uart_port *port) {\
-               if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
+               if (port->type == PORT_SCIF || port->type == PORT_SCIFB ||\
+                   port->type == PORT_HSCIF) {\
                        SCI_IN(scif_size, scif_offset)\
                } else { /* PORT_SCI or PORT_SCIFA */\
                        SCI_IN(sci_size, sci_offset);\
@@ -250,7 +255,8 @@ struct uart_port {
        }\
 static inline void sci_##name##_out(struct uart_port *port,\
                                unsigned int value) {\
-       if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
+       if (port->type == PORT_SCIF || port->type == PORT_SCIFB ||\
+           port->type == PORT_HSCIF) {\
                SCI_OUT(scif_size, scif_offset, value)\
        } else {        /* PORT_SCI or PORT_SCIFA */\
                SCI_OUT(sci_size, sci_offset, value);\
@@ -375,6 +381,7 @@ SCIF_FNS(SCFDR,  0,  0, 0x1C, 16)
 SCIF_FNS(SCSPTR, 0,  0, 0x20, 16)
 SCIF_FNS(DL,     0,  0, 0x30, 16)
 SCIF_FNS(CKS,    0,  0, 0x34, 16)
+SCIF_FNS(HSSRR,  0,  0, 0x40, 16) /* HSCIF only */
 #if defined(CFG_SCIF_A)
 SCIF_FNS(SCLSR,  0,  0, 0x14, 16)
 #else
@@ -414,7 +421,9 @@ SCIF_FNS(SCSPTR,                    0,  0, 0x20, 16)
 #endif
 SCIF_FNS(SCLSR,                                0,  0, 0x24, 16)
 #endif
-SCIF_FNS(DL,                           0,  0, 0x0,  0) /* dummy */
+SCIF_FNS(DL,                           0,  0, 0x30, 16)
+SCIF_FNS(CKS,                          0,  0, 0x34, 16)
+SCIF_FNS(HSSRR,                                0,  0, 0x40, 16) /* HSCIF only */
 #endif
 #define sci_in(port, reg) sci_##reg##_in(port)
 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
@@ -485,11 +494,20 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
 #elif defined(CONFIG_RCAR_GEN2)
 #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
- #if defined(CFG_SCIF_A)
+ #if defined(CFG_SCIF_A) || defined(CFG_HSCIF)
   #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */
  #else
   #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
  #endif
+#elif defined(CONFIG_RCAR_64)
+static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
+{
+       if (port->type == PORT_SCIF)
+               return (clk + 16 * bps) / (32 * bps) - 1;
+       else /* PORT_HSCIF */
+               return clk / bps / 8 / 2 - 1; /* Internal Clock, Sampling rate = 8 */
+}
+#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
 #else /* Generic SH */
 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 #endif

diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index acf555b..85dac9d 100644 (file)
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -10,7 +10,7 @@ config SOC_DEVICE
          specific device variant in use.
 
 config SOC_DEVICE_TI_K3
-       depends on SOC_DEVICE
+       depends on SOC_DEVICE && ARCH_K3
        bool "Enable SoC Device ID driver for TI K3 SoCs"
        help
          This allows Texas Instruments Keystone 3 SoCs to identify

diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index 8af0ac7..b720131 100644 (file)
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -8,21 +8,9 @@
 #include <dm.h>
 #include <soc.h>
 
+#include <asm/arch/hardware.h>
 #include <asm/io.h>
 
-#define AM65X                  0xbb5a
-#define J721E                  0xbb64
-#define J7200                  0xbb6d
-#define AM64X                  0xbb38
-#define J721S2                 0xbb75
-#define AM62X                  0xbb7e
-#define AM62AX                 0xbb8d
-
-#define JTAG_ID_VARIANT_SHIFT  28
-#define JTAG_ID_VARIANT_MASK   (0xf << 28)
-#define JTAG_ID_PARTNO_SHIFT   12
-#define JTAG_ID_PARTNO_MASK    (0xffff << 12)
-
 struct soc_ti_k3_plat {
        const char *family;
        const char *revision;
@@ -36,25 +24,25 @@ static const char *get_family_string(u32 idreg)
        soc = (idreg & JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
 
        switch (soc) {
-       case AM65X:
+       case JTAG_ID_PARTNO_AM65X:
                family = "AM65X";
                break;
-       case J721E:
+       case JTAG_ID_PARTNO_J721E:
                family = "J721E";
                break;
-       case J7200:
+       case JTAG_ID_PARTNO_J7200:
                family = "J7200";
                break;
-       case AM64X:
+       case JTAG_ID_PARTNO_AM64X:
                family = "AM64X";
                break;
-       case J721S2:
+       case JTAG_ID_PARTNO_J721S2:
                family = "J721S2";
                break;
-       case AM62X:
+       case JTAG_ID_PARTNO_AM62X:
                family = "AM62X";
                break;
-       case AM62AX:
+       case JTAG_ID_PARTNO_AM62AX:
                family = "AM62AX";
                break;
        default:
@@ -81,13 +69,13 @@ static const char *get_rev_string(u32 idreg)
        soc = (idreg & JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
 
        switch (soc) {
-       case J721E:
-               if (rev > ARRAY_SIZE(j721e_rev_string_map))
+       case JTAG_ID_PARTNO_J721E:
+               if (rev >= ARRAY_SIZE(j721e_rev_string_map))
                        goto bail;
                return j721e_rev_string_map[rev];
 
        default:
-               if (rev > ARRAY_SIZE(typical_rev_string_map))
+               if (rev >= ARRAY_SIZE(typical_rev_string_map))
                        goto bail;
                return typical_rev_string_map[rev];
        };

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index cdd2304..4f435fd 100644 (file)
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -381,7 +381,7 @@ config SPI_QUP
 
 config RENESAS_RPC_SPI
        bool "Renesas RPC SPI driver"
-       depends on RCAR_GEN3 || RZA1
+       depends on RCAR_64 || RZA1
        imply SPI_FLASH_BAR
        help
          Enable the Renesas RPC SPI driver, used to access SPI NOR flash
@@ -573,6 +573,7 @@ endif # if DM_SPI
 
 config FSL_ESPI
        bool "Freescale eSPI driver"
+       depends on MPC85xx
        imply SPI_FLASH_BAR
        help
          Enable the Freescale eSPI driver. This driver can be used to

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 90c207d..eb52ff7 100644 (file)
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -115,15 +115,8 @@ struct stm32_qspi_regs {
 #define STM32_BUSY_TIMEOUT_US          100000
 #define STM32_ABT_TIMEOUT_US           100000
 
-struct stm32_qspi_flash {
-       u32 cr;
-       u32 dcr;
-       bool initialized;
-};
-
 struct stm32_qspi_priv {
        struct stm32_qspi_regs *regs;
-       struct stm32_qspi_flash flash[STM32_QSPI_MAX_CHIP];
        void __iomem *mm_base;
        resource_size_t mm_size;
        ulong clock_rate;
@@ -407,25 +400,11 @@ static int stm32_qspi_claim_bus(struct udevice *dev)
                return -ENODEV;
 
        if (priv->cs_used != slave_cs) {
-               struct stm32_qspi_flash *flash = &priv->flash[slave_cs];
-
                priv->cs_used = slave_cs;
 
-               if (flash->initialized) {
-                       /* Set the configuration: speed + cs */
-                       writel(flash->cr, &priv->regs->cr);
-                       writel(flash->dcr, &priv->regs->dcr);
-               } else {
-                       /* Set chip select */
-                       clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
-                                       priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
-
-                       /* Save the configuration: speed + cs */
-                       flash->cr = readl(&priv->regs->cr);
-                       flash->dcr = readl(&priv->regs->dcr);
-
-                       flash->initialized = true;
-               }
+               /* Set chip select */
+               clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
+                               priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
        }
 
        setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);

diff --git a/drivers/sysreset/sysreset_gpio.c b/drivers/sysreset/sysreset_gpio.c
index dfca10c..de42b59 100644 (file)
--- a/drivers/sysreset/sysreset_gpio.c
+++ b/drivers/sysreset/sysreset_gpio.c
@@ -17,6 +17,7 @@ struct gpio_reboot_priv {
 static int gpio_reboot_request(struct udevice *dev, enum sysreset_t type)
 {
        struct gpio_reboot_priv *priv = dev_get_priv(dev);
+       int ret;
 
        /*
         * When debug log is enabled please make sure that chars won't end up
@@ -26,7 +27,11 @@ static int gpio_reboot_request(struct udevice *dev, enum sysreset_t type)
        debug("GPIO reset\n");
 
        /* Writing 1 respects polarity (active high/low) based on gpio->flags */
-       return dm_gpio_set_value(&priv->gpio, 1);
+       ret = dm_gpio_set_value(&priv->gpio, 1);
+       if (ret < 0)
+               return ret;
+
+       return -EINPROGRESS;
 }
 
 static struct sysreset_ops gpio_reboot_ops = {

diff --git a/drivers/sysreset/sysreset_psci.c b/drivers/sysreset/sysreset_psci.c
index 83ecbcb..a8a4152 100644 (file)
--- a/drivers/sysreset/sysreset_psci.c
+++ b/drivers/sysreset/sysreset_psci.c
@@ -9,6 +9,11 @@
 #include <linux/errno.h>
 #include <linux/psci.h>
 
+__weak int psci_sysreset_get_status(struct udevice *dev, char *buf, int size)
+{
+       return -EOPNOTSUPP;
+}
+
 static int psci_sysreset_request(struct udevice *dev, enum sysreset_t type)
 {
        switch (type) {
@@ -28,10 +33,12 @@ static int psci_sysreset_request(struct udevice *dev, enum sysreset_t type)
 
 static struct sysreset_ops psci_sysreset_ops = {
        .request = psci_sysreset_request,
+       .get_status = psci_sysreset_get_status,
 };
 
 U_BOOT_DRIVER(psci_sysreset) = {
        .name = "psci-sysreset",
        .id = UCLASS_SYSRESET,
        .ops = &psci_sysreset_ops,
+       .flags = DM_FLAG_PRE_RELOC,
 };

diff --git a/drivers/sysreset/sysreset_sandbox.c b/drivers/sysreset/sysreset_sandbox.c
index 0ee286c..3750c60 100644 (file)
--- a/drivers/sysreset/sysreset_sandbox.c
+++ b/drivers/sysreset/sysreset_sandbox.c
@@ -65,7 +65,6 @@ static int sandbox_sysreset_request(struct udevice *dev, enum sysreset_t type)
                if (!state->sysreset_allowed[type])
                        return -EACCES;
                sandbox_exit();
-               break;
        case SYSRESET_POWER:
                if (!state->sysreset_allowed[type])
                        return -EACCES;

diff --git a/drivers/tee/sandbox.c b/drivers/tee/sandbox.c
index 35e8542..86219a9 100644 (file)
--- a/drivers/tee/sandbox.c
+++ b/drivers/tee/sandbox.c
@@ -119,6 +119,7 @@ static u32 pta_scp03_invoke_func(struct udevice *dev, u32 func, uint num_params,
 {
        u32 res;
        static bool enabled;
+       static bool provisioned;
 
        switch (func) {
        case PTA_CMD_ENABLE_SCP03:
@@ -130,12 +131,18 @@ static u32 pta_scp03_invoke_func(struct udevice *dev, u32 func, uint num_params,
                if (res)
                        return res;
 
-               if (!enabled) {
+               /* If SCP03 was not enabled, enable it */
+               if (!enabled)
                        enabled = true;
-               } else {
-               }
 
-               if (params[0].u.value.a)
+               /* If SCP03 was not provisioned, provision new keys */
+               if (params[0].u.value.a && !provisioned)
+                       provisioned = true;
+
+               /*
+                * Either way, we asume both operations succeeded and that
+                * the communication channel has now been stablished
+                */
 
                return TEE_SUCCESS;
        default:

diff --git a/drivers/usb/emul/sandbox_flash.c b/drivers/usb/emul/sandbox_flash.c
index 01ccc4b..7c5c1ab 100644 (file)
--- a/drivers/usb/emul/sandbox_flash.c
+++ b/drivers/usb/emul/sandbox_flash.c
@@ -266,6 +266,7 @@ static int sandbox_flash_bulk(struct udevice *dev, struct usb_device *udev,
                default:
                        break;
                }
+               break;
        case SANDBOX_FLASH_EP_IN:
                switch (info->phase) {
                case SCSIPH_DATA:

diff --git a/drivers/usb/emul/sandbox_hub.c b/drivers/usb/emul/sandbox_hub.c
index 041ec37..084cc16 100644 (file)
--- a/drivers/usb/emul/sandbox_hub.c
+++ b/drivers/usb/emul/sandbox_hub.c
@@ -220,13 +220,9 @@ static int sandbox_hub_submit_control_msg(struct udevice *bus,
                                udev->status = 0;
                                udev->act_len = sizeof(*hubsts);
                                return 0;
+                           }
                        }
-                       default:
-                               debug("%s: rx ctl requesttype=%x, request=%x\n",
-                                     __func__, setup->requesttype,
-                                     setup->request);
-                               break;
-                       }
+                       break;
                case USB_RT_PORT | USB_DIR_IN:
                        switch (setup->request) {
                        case USB_REQ_GET_STATUS: {
@@ -239,13 +235,12 @@ static int sandbox_hub_submit_control_msg(struct udevice *bus,
                                udev->status = 0;
                                udev->act_len = sizeof(*portsts);
                                return 0;
+                           }
                        }
-                       }
-               default:
-                       debug("%s: rx ctl requesttype=%x, request=%x\n",
-                             __func__, setup->requesttype, setup->request);
                        break;
                }
+               debug("%s: rx ctl requesttype=%x, request=%x\n",
+                     __func__, setup->requesttype, setup->request);
        } else if (pipe == usb_sndctrlpipe(udev, 0)) {
                switch (setup->requesttype) {
                case USB_RT_PORT:
@@ -263,7 +258,7 @@ static int sandbox_hub_submit_control_msg(struct udevice *bus,
                                        debug("  ** Invalid feature\n");
                                }
                                return ret;
-                       }
+                           }
                        case USB_REQ_CLEAR_FEATURE: {
                                int port;
 
@@ -279,18 +274,11 @@ static int sandbox_hub_submit_control_msg(struct udevice *bus,
                                }
                                udev->status = 0;
                                return 0;
+                           }
                        }
-                       default:
-                               debug("%s: tx ctl requesttype=%x, request=%x\n",
-                                     __func__, setup->requesttype,
-                                     setup->request);
-                               break;
-                       }
-               default:
-                       debug("%s: tx ctl requesttype=%x, request=%x\n",
-                             __func__, setup->requesttype, setup->request);
-                       break;
                }
+               debug("%s: tx ctl requesttype=%x, request=%x\n",
+                     __func__, setup->requesttype, setup->request);
        }
        debug("pipe=%lx\n", pipe);
 

diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index 2a309e6..04b8541 100644 (file)
--- a/drivers/usb/gadget/composite.c
+++ b/drivers/usb/gadget/composite.c
@@ -1068,7 +1068,7 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
                        if (!gadget_is_dualspeed(gadget) ||
                            gadget->speed >= USB_SPEED_SUPER)
                                break;
-
+                       fallthrough;
                case USB_DT_CONFIG:
                        value = config_desc(cdev, w_value);
                        if (value >= 0)

diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
index 45f0504..f46829e 100644 (file)
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -1117,7 +1117,7 @@ static int do_request_sense(struct fsg_common *common, struct fsg_buffhd *bh)
 {
        struct fsg_lun  *curlun = &common->luns[common->lun];
        u8              *buf = (u8 *) bh->buf;
-       u32             sd, sdinfo;
+       u32             sd, sdinfo = 0;
        int             valid;
 
        /*
@@ -1145,7 +1145,6 @@ static int do_request_sense(struct fsg_common *common, struct fsg_buffhd *bh)
        if (!curlun) {          /* Unsupported LUNs are okay */
                common->bad_lun_okay = 1;
                sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
-               sdinfo = 0;
                valid = 0;
        } else {
                sd = curlun->sense_data;

diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c
index 9ea43f2..4da5a16 100644 (file)
--- a/drivers/usb/gadget/f_sdp.c
+++ b/drivers/usb/gadget/f_sdp.c
@@ -865,6 +865,7 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image,
                        struct spl_image_info spl_image = {};
                        struct spl_boot_device bootdev = {};
                        spl_parse_image_header(&spl_image, &bootdev, header);
+                       spl_board_prepare_for_boot();
                        jump_to_image_no_args(&spl_image);
 #else
                        /* In U-Boot, allow jumps to scripts */

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 60f4a4b..334d64c 100644 (file)
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -668,15 +668,6 @@ source "drivers/video/stm32/Kconfig"
 
 source "drivers/video/tidss/Kconfig"
 
-config VIDEO_TEGRA20
-       bool "Enable LCD support on Tegra20"
-       depends on OF_CONTROL
-       help
-          Tegra20 supports video output to an attached LCD panel as well as
-          other options such as HDMI. Only the LCD is supported in U-Boot.
-          This option enables this support which can be used on devices which
-          have an LCD display connected.
-
 config VIDEO_TEGRA124
        bool "Enable video support on Tegra124"
        help
@@ -687,6 +678,8 @@ config VIDEO_TEGRA124
 
 source "drivers/video/bridge/Kconfig"
 
+source "drivers/video/tegra20/Kconfig"
+
 source "drivers/video/imx/Kconfig"
 
 config VIDEO_MXS

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index cb3f373..4d75771 100644 (file)
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -67,10 +67,10 @@ obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
 obj-$(CONFIG_VIDEO_DSI_HOST_SANDBOX) += sandbox_dsi_host.o
 obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
 obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
-obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o
 obj-$(CONFIG_VIDEO_VESA) += vesa.o
 obj-$(CONFIG_VIDEO_SEPS525) += seps525.o
 obj-$(CONFIG_VIDEO_ZYNQMP_DPSUB) += zynqmp_dpsub.o
 
 obj-y += bridge/
 obj-y += sunxi/
+obj-y += tegra20/

diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c
index 6d9c5a9..a460692 100644 (file)
--- a/drivers/video/dw_mipi_dsi.c
+++ b/drivers/video/dw_mipi_dsi.c
@@ -806,6 +806,15 @@ static int dw_mipi_dsi_init(struct udevice *dev,
                return -EINVAL;
        }
 
+       /*
+        * The Rockchip based devices don't have px_clk, so simply move
+        * on.
+        */
+       if (IS_ENABLED(CONFIG_DISPLAY_ROCKCHIP_DW_MIPI)) {
+               dw_mipi_dsi_bridge_set(dsi, timings);
+               return 0;
+       }
+
        ret = clk_get_by_name(device->dev, "px_clk", &clk);
        if (ret) {
                dev_err(device->dev, "peripheral clock get error %d\n", ret);

diff --git a/drivers/video/orisetech_otm8009a.c b/drivers/video/orisetech_otm8009a.c
index 95738e3..848f174 100644 (file)
--- a/drivers/video/orisetech_otm8009a.c
+++ b/drivers/video/orisetech_otm8009a.c
@@ -300,7 +300,7 @@ static int otm8009a_panel_of_to_plat(struct udevice *dev)
        struct otm8009a_panel_priv *priv = dev_get_priv(dev);
        int ret;
 
-       if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
+       if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
                ret =  device_get_supply_regulator(dev, "power-supply",
                                                   &priv->reg);
                if (ret && ret != -ENOENT) {
@@ -326,7 +326,7 @@ static int otm8009a_panel_probe(struct udevice *dev)
        struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
        int ret;
 
-       if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
+       if (CONFIG_IS_ENABLED(DM_REGULATOR) && priv->reg) {
                dev_dbg(dev, "enable regulator '%s'\n", priv->reg->name);
                ret = regulator_set_enable(priv->reg, true);
                if (ret)

diff --git a/drivers/video/raydium-rm68200.c b/drivers/video/raydium-rm68200.c
index 373668d..f1fce55 100644 (file)
--- a/drivers/video/raydium-rm68200.c
+++ b/drivers/video/raydium-rm68200.c
@@ -266,7 +266,7 @@ static int rm68200_panel_of_to_plat(struct udevice *dev)
        struct rm68200_panel_priv *priv = dev_get_priv(dev);
        int ret;
 
-       if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
+       if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
                ret =  device_get_supply_regulator(dev, "power-supply",
                                                   &priv->reg);
                if (ret && ret != -ENOENT) {
@@ -299,7 +299,7 @@ static int rm68200_panel_probe(struct udevice *dev)
        struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
        int ret;
 
-       if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
+       if (CONFIG_IS_ENABLED(DM_REGULATOR) && priv->reg) {
                ret = regulator_set_enable(priv->reg, true);
                if (ret)
                        return ret;

diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig
index b038663..01804dc 100644 (file)
--- a/drivers/video/rockchip/Kconfig
+++ b/drivers/video/rockchip/Kconfig
@@ -69,4 +69,12 @@ config DISPLAY_ROCKCHIP_MIPI
          support. The mipi controller and dphy on rk3288& rk3399 support
          16,18, 24 bits per pixel with up to 2k resolution ratio.
 
+config DISPLAY_ROCKCHIP_DW_MIPI
+       bool "Rockchip Designware MIPI"
+       depends on VIDEO_ROCKCHIP
+       select VIDEO_DW_MIPI_DSI
+       help
+         Select the Designware MIPI DSI controller in use on some Rockchip
+         SOCs.
+
 endif

diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile
index 9aced5e..8128289 100644 (file)
--- a/drivers/video/rockchip/Makefile
+++ b/drivers/video/rockchip/Makefile
@@ -15,4 +15,5 @@ obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o $(obj-hdmi-y)
 obj-mipi-$(CONFIG_ROCKCHIP_RK3288) += rk3288_mipi.o
 obj-mipi-$(CONFIG_ROCKCHIP_RK3399) += rk3399_mipi.o
 obj-$(CONFIG_DISPLAY_ROCKCHIP_MIPI) += rk_mipi.o $(obj-mipi-y)
+obj-$(CONFIG_DISPLAY_ROCKCHIP_DW_MIPI) += dw_mipi_dsi_rockchip.o
 endif

diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
new file mode 100644 (file)
index 0000000..ca548a6
--- /dev/null
+++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
@@ -0,0 +1,898 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Author(s): Chris Morgan <macromorgan@hotmail.com>
+ *
+ * This MIPI DSI controller driver is heavily based on the Linux Kernel
+ * driver from drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c and the
+ * U-Boot driver from drivers/video/stm32/stm32_dsi.c.
+ */
+
+#define LOG_CATEGORY UCLASS_VIDEO_BRIDGE
+
+#include <clk.h>
+#include <dm.h>
+#include <div64.h>
+#include <dsi_host.h>
+#include <generic-phy.h>
+#include <mipi_dsi.h>
+#include <panel.h>
+#include <phy-mipi-dphy.h>
+#include <reset.h>
+#include <video_bridge.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <linux/iopoll.h>
+
+#include <common.h>
+#include <log.h>
+#include <video.h>
+#include <asm/io.h>
+#include <dm/device-internal.h>
+#include <linux/bitops.h>
+
+#define USEC_PER_SEC   1000000L
+
+/*
+ * DSI wrapper registers & bit definitions
+ * Note: registers are named as in the Reference Manual
+ */
+#define DSI_WCR                0x0404          /* Wrapper Control Reg */
+#define WCR_DSIEN      BIT(3)          /* DSI ENable */
+
+#define DSI_PHY_TST_CTRL0              0xb4
+#define PHY_TESTCLK                    BIT(1)
+#define PHY_UNTESTCLK                  0
+#define PHY_TESTCLR                    BIT(0)
+#define PHY_UNTESTCLR                  0
+
+#define DSI_PHY_TST_CTRL1              0xb8
+#define PHY_TESTEN                     BIT(16)
+#define PHY_UNTESTEN                   0
+#define PHY_TESTDOUT(n)                        (((n) & 0xff) << 8)
+#define PHY_TESTDIN(n)                 (((n) & 0xff) << 0)
+
+#define BYPASS_VCO_RANGE       BIT(7)
+#define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3)
+#define VCO_IN_CAP_CON_DEFAULT (0x0 << 1)
+#define VCO_IN_CAP_CON_LOW     (0x1 << 1)
+#define VCO_IN_CAP_CON_HIGH    (0x2 << 1)
+#define REF_BIAS_CUR_SEL       BIT(0)
+
+#define CP_CURRENT_3UA 0x1
+#define CP_CURRENT_4_5UA       0x2
+#define CP_CURRENT_7_5UA       0x6
+#define CP_CURRENT_6UA 0x9
+#define CP_CURRENT_12UA        0xb
+#define CP_CURRENT_SEL(val)    ((val) & 0xf)
+#define CP_PROGRAM_EN          BIT(7)
+
+#define LPF_RESISTORS_15_5KOHM 0x1
+#define LPF_RESISTORS_13KOHM   0x2
+#define LPF_RESISTORS_11_5KOHM 0x4
+#define LPF_RESISTORS_10_5KOHM 0x8
+#define LPF_RESISTORS_8KOHM    0x10
+#define LPF_PROGRAM_EN         BIT(6)
+#define LPF_RESISTORS_SEL(val) ((val) & 0x3f)
+
+#define HSFREQRANGE_SEL(val)   (((val) & 0x3f) << 1)
+
+#define INPUT_DIVIDER(val)     (((val) - 1) & 0x7f)
+#define LOW_PROGRAM_EN         0
+#define HIGH_PROGRAM_EN                BIT(7)
+#define LOOP_DIV_LOW_SEL(val)  (((val) - 1) & 0x1f)
+#define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
+#define PLL_LOOP_DIV_EN                BIT(5)
+#define PLL_INPUT_DIV_EN       BIT(4)
+
+#define POWER_CONTROL          BIT(6)
+#define INTERNAL_REG_CURRENT   BIT(3)
+#define BIAS_BLOCK_ON          BIT(2)
+#define BANDGAP_ON             BIT(0)
+
+#define TER_RESISTOR_HIGH      BIT(7)
+#define        TER_RESISTOR_LOW        0
+#define LEVEL_SHIFTERS_ON      BIT(6)
+#define TER_CAL_DONE           BIT(5)
+#define SETRD_MAX              (0x7 << 2)
+#define POWER_MANAGE           BIT(1)
+#define TER_RESISTORS_ON       BIT(0)
+
+#define BIASEXTR_SEL(val)      ((val) & 0x7)
+#define BANDGAP_SEL(val)       ((val) & 0x7)
+#define TLP_PROGRAM_EN         BIT(7)
+#define THS_PRE_PROGRAM_EN     BIT(7)
+#define THS_ZERO_PROGRAM_EN    BIT(6)
+
+#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL               0x10
+#define PLL_CP_CONTROL_PLL_LOCK_BYPASS                 0x11
+#define PLL_LPF_AND_CP_CONTROL                         0x12
+#define PLL_INPUT_DIVIDER_RATIO                                0x17
+#define PLL_LOOP_DIVIDER_RATIO                         0x18
+#define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL      0x19
+#define BANDGAP_AND_BIAS_CONTROL                       0x20
+#define TERMINATION_RESISTER_CONTROL                   0x21
+#define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY                0x22
+#define HS_RX_CONTROL_OF_LANE_CLK                      0x34
+#define HS_RX_CONTROL_OF_LANE_0                                0x44
+#define HS_RX_CONTROL_OF_LANE_1                                0x54
+#define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL    0x60
+#define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL    0x61
+#define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL    0x62
+#define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL      0x63
+#define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL       0x64
+#define HS_TX_CLOCK_LANE_POST_TIME_CONTROL             0x65
+#define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL     0x70
+#define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL     0x71
+#define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL     0x72
+#define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL       0x73
+#define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL                0x74
+#define HS_RX_DATA_LANE_THS_SETTLE_CONTROL             0x75
+#define HS_RX_CONTROL_OF_LANE_2                                0x84
+#define HS_RX_CONTROL_OF_LANE_3                                0x94
+
+#define RK3568_GRF_VO_CON2             0x0368
+#define RK3568_DSI0_SKEWCALHS          (0x1f << 11)
+#define RK3568_DSI0_FORCETXSTOPMODE    (0xf << 4)
+#define RK3568_DSI0_TURNDISABLE                BIT(2)
+#define RK3568_DSI0_FORCERXMODE                BIT(0)
+
+/*
+ * Note these registers do not appear in the datasheet, they are
+ * however present in the BSP driver which is where these values
+ * come from. Name GRF_VO_CON3 is assumed.
+ */
+#define RK3568_GRF_VO_CON3             0x36c
+#define RK3568_DSI1_SKEWCALHS          (0x1f << 11)
+#define RK3568_DSI1_FORCETXSTOPMODE    (0xf << 4)
+#define RK3568_DSI1_TURNDISABLE                BIT(2)
+#define RK3568_DSI1_FORCERXMODE                BIT(0)
+
+#define HIWORD_UPDATE(val, mask)       (val | (mask) << 16)
+
+/* Timeout for regulator on/off, pll lock/unlock & fifo empty */
+#define TIMEOUT_US     200000
+
+enum {
+       BANDGAP_97_07,
+       BANDGAP_98_05,
+       BANDGAP_99_02,
+       BANDGAP_100_00,
+       BANDGAP_93_17,
+       BANDGAP_94_15,
+       BANDGAP_95_12,
+       BANDGAP_96_10,
+};
+
+enum {
+       BIASEXTR_87_1,
+       BIASEXTR_91_5,
+       BIASEXTR_95_9,
+       BIASEXTR_100,
+       BIASEXTR_105_94,
+       BIASEXTR_111_88,
+       BIASEXTR_118_8,
+       BIASEXTR_127_7,
+};
+
+struct rockchip_dw_dsi_chip_data {
+       u32 reg;
+
+       u32 lcdsel_grf_reg;
+       u32 lcdsel_big;
+       u32 lcdsel_lit;
+
+       u32 enable_grf_reg;
+       u32 enable;
+
+       u32 lanecfg1_grf_reg;
+       u32 lanecfg1;
+       u32 lanecfg2_grf_reg;
+       u32 lanecfg2;
+
+       unsigned int flags;
+       unsigned int max_data_lanes;
+};
+
+struct dw_rockchip_dsi_priv {
+       struct mipi_dsi_device device;
+       void __iomem *base;
+       struct udevice *panel;
+
+       /* Optional external dphy */
+       struct phy phy;
+       struct phy_configure_opts_mipi_dphy phy_opts;
+
+       struct clk *pclk;
+       struct clk *ref;
+       struct reset_ctl *rst;
+       unsigned int lane_mbps; /* per lane */
+       u16 input_div;
+       u16 feedback_div;
+       const struct rockchip_dw_dsi_chip_data *cdata;
+       struct udevice *dsi_host;
+};
+
+static inline void dsi_write(struct dw_rockchip_dsi_priv *dsi, u32 reg, u32 val)
+{
+       writel(val, dsi->base + reg);
+}
+
+static inline u32 dsi_read(struct dw_rockchip_dsi_priv *dsi, u32 reg)
+{
+       return readl(dsi->base + reg);
+}
+
+static inline void dsi_set(struct dw_rockchip_dsi_priv *dsi, u32 reg, u32 mask)
+{
+       dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
+}
+
+static inline void dsi_clear(struct dw_rockchip_dsi_priv *dsi, u32 reg, u32 mask)
+{
+       dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask);
+}
+
+static inline void dsi_update_bits(struct dw_rockchip_dsi_priv *dsi, u32 reg,
+                                  u32 mask, u32 val)
+{
+       dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
+}
+
+static void dw_mipi_dsi_phy_write(struct dw_rockchip_dsi_priv *dsi,
+                                 u8 test_code,
+                                 u8 test_data)
+{
+       /*
+        * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
+        * is latched internally as the current test code. Test data is
+        * programmed internally by rising edge on TESTCLK.
+        */
+       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
+
+       dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
+                                         PHY_TESTDIN(test_code));
+
+       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
+
+       dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
+                                         PHY_TESTDIN(test_data));
+
+       dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
+}
+
+struct dphy_pll_parameter_map {
+       unsigned int max_mbps;
+       u8 hsfreqrange;
+       u8 icpctrl;
+       u8 lpfctrl;
+};
+
+/* The table is based on 27MHz DPHY pll reference clock. */
+static const struct dphy_pll_parameter_map dppa_map[] = {
+       {  89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
+       {  99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
+       { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
+       { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
+       { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
+       { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
+       { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
+       { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
+       { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
+       { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
+       { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
+       { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
+       { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
+       { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
+       { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
+       { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
+       { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
+       { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
+       { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
+       { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
+       { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
+       { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
+       { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
+       { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
+       { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
+       { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
+       { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
+       { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
+       { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
+       {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
+       {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
+       {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
+       {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
+       {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
+       {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
+       {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
+       {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
+       {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
+       {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }
+};
+
+static int max_mbps_to_parameter(unsigned int max_mbps)
+{
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(dppa_map); i++)
+               if (dppa_map[i].max_mbps >= max_mbps)
+                       return i;
+
+       return -EINVAL;
+}
+
+/*
+ * ns2bc - Nanoseconds to byte clock cycles
+ */
+static inline unsigned int ns2bc(struct dw_rockchip_dsi_priv *dsi, int ns)
+{
+       return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
+}
+
+/*
+ * ns2ui - Nanoseconds to UI time periods
+ */
+static inline unsigned int ns2ui(struct dw_rockchip_dsi_priv *dsi, int ns)
+{
+       return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
+}
+
+static int dsi_phy_init(void *priv_data)
+{
+       struct mipi_dsi_device *device = priv_data;
+       struct udevice *dev = device->dev;
+       struct dw_rockchip_dsi_priv *dsi = dev_get_priv(dev);
+       int ret, i, vco;
+
+       if (&dsi->phy) {
+               ret = generic_phy_configure(&dsi->phy, &dsi->phy_opts);
+               if (ret) {
+                       dev_err(dsi->dsi_host,
+                               "Configure external dphy fail %d\n",
+                               ret);
+                       return ret;
+               }
+
+               ret = generic_phy_power_on(&dsi->phy);
+               if (ret) {
+                       dev_err(dsi->dsi_host,
+                               "Generic phy power on fail %d\n", ret);
+                       return ret;
+               }
+
+               return 0;
+       }
+
+       /*
+        * Get vco from frequency(lane_mbps)
+        * vco  frequency table
+        * 000 - between   80 and  200 MHz
+        * 001 - between  200 and  300 MHz
+        * 010 - between  300 and  500 MHz
+        * 011 - between  500 and  700 MHz
+        * 100 - between  700 and  900 MHz
+        * 101 - between  900 and 1100 MHz
+        * 110 - between 1100 and 1300 MHz
+        * 111 - between 1300 and 1500 MHz
+        */
+       vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
+
+       i = max_mbps_to_parameter(dsi->lane_mbps);
+       if (i < 0) {
+               dev_err(dsi->dsi_host,
+                       "failed to get parameter for %dmbps clock\n",
+                       dsi->lane_mbps);
+               return i;
+       }
+
+       dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,
+                             BYPASS_VCO_RANGE |
+                             VCO_RANGE_CON_SEL(vco) |
+                             VCO_IN_CAP_CON_LOW |
+                             REF_BIAS_CUR_SEL);
+
+       dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
+                             CP_CURRENT_SEL(dppa_map[i].icpctrl));
+       dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
+                             CP_PROGRAM_EN | LPF_PROGRAM_EN |
+                             LPF_RESISTORS_SEL(dppa_map[i].lpfctrl));
+
+       dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
+                             HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
+
+       dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
+                             INPUT_DIVIDER(dsi->input_div));
+       dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
+                             LOOP_DIV_LOW_SEL(dsi->feedback_div) |
+                             LOW_PROGRAM_EN);
+       /*
+        * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately
+        * to make the configured LSB effective according to IP simulation
+        * and lab test results.
+        * Only in this way can we get correct mipi phy pll frequency.
+        */
+       dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
+                             PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
+       dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
+                             LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
+                             HIGH_PROGRAM_EN);
+       dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
+                             PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
+
+       dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
+                             LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7));
+       dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
+                             HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10));
+
+       dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL,
+                             POWER_CONTROL | INTERNAL_REG_CURRENT |
+                             BIAS_BLOCK_ON | BANDGAP_ON);
+
+       dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
+                             TER_RESISTOR_LOW | TER_CAL_DONE |
+                             SETRD_MAX | TER_RESISTORS_ON);
+       dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
+                             TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
+                             SETRD_MAX | POWER_MANAGE |
+                             TER_RESISTORS_ON);
+
+       dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,
+                             TLP_PROGRAM_EN | ns2bc(dsi, 500));
+       dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,
+                             THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
+       dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,
+                             THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
+       dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,
+                             THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
+       dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,
+                             BIT(5) | ns2bc(dsi, 100));
+       dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,
+                             BIT(5) | (ns2bc(dsi, 60) + 7));
+
+       dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,
+                             TLP_PROGRAM_EN | ns2bc(dsi, 500));
+       dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,
+                             THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20));
+       dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,
+                             THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
+       dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,
+                             THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
+       dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,
+                             BIT(5) | ns2bc(dsi, 100));
+
+       return ret;
+}
+
+static void dsi_phy_post_set_mode(void *priv_data, unsigned long mode_flags)
+{
+       struct mipi_dsi_device *device = priv_data;
+       struct udevice *dev = device->dev;
+       struct dw_rockchip_dsi_priv *dsi = dev_get_priv(dev);
+
+       dev_dbg(dev, "Set mode %p enable %ld\n", dsi,
+               mode_flags & MIPI_DSI_MODE_VIDEO);
+
+       if (!dsi)
+               return;
+
+       /*
+        * DSI wrapper must be enabled in video mode & disabled in command mode.
+        * If wrapper is enabled in command mode, the display controller
+        * register access will hang. Note that this was carried over from the
+        * stm32 dsi driver and is unknown if necessary for Rockchip.
+        */
+
+       if (mode_flags & MIPI_DSI_MODE_VIDEO)
+               dsi_set(dsi, DSI_WCR, WCR_DSIEN);
+       else
+               dsi_clear(dsi, DSI_WCR, WCR_DSIEN);
+}
+
+static int
+dw_mipi_dsi_get_lane_mbps(void *priv_data, struct display_timing *timings,
+                         u32 lanes, u32 format, unsigned int *lane_mbps)
+{
+       struct mipi_dsi_device *device = priv_data;
+       struct udevice *dev = device->dev;
+       struct dw_rockchip_dsi_priv *dsi = dev_get_priv(dev);
+       int bpp;
+       unsigned long mpclk, tmp;
+       unsigned int target_mbps = 1000;
+       unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps;
+       unsigned long best_freq = 0;
+       unsigned long fvco_min, fvco_max, fin, fout;
+       unsigned int min_prediv, max_prediv;
+       unsigned int _prediv, best_prediv;
+       unsigned long _fbdiv, best_fbdiv;
+       unsigned long min_delta = ULONG_MAX;
+       unsigned int pllref_clk;
+
+       bpp = mipi_dsi_pixel_format_to_bpp(format);
+       if (bpp < 0) {
+               dev_err(dsi->dsi_host,
+                       "failed to get bpp for pixel format %d\n",
+                       format);
+               return bpp;
+       }
+
+       mpclk = DIV_ROUND_UP(timings->pixelclock.typ, 1000);
+       if (mpclk) {
+               /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
+               tmp = (mpclk * (bpp / lanes) * 10 / 8) / 1000;
+               if (tmp < max_mbps)
+                       target_mbps = tmp;
+               else
+                       dev_err(dsi->dsi_host,
+                               "DPHY clock frequency is out of range\n");
+       }
+
+       /* for external phy only the mipi_dphy_config is necessary */
+       if (&dsi->phy) {
+               phy_mipi_dphy_get_default_config(timings->pixelclock.typ  * 10 / 8,
+                                                bpp, lanes,
+                                                &dsi->phy_opts);
+               dsi->lane_mbps = target_mbps;
+               *lane_mbps = dsi->lane_mbps;
+
+               return 0;
+       }
+
+       pllref_clk = clk_get_rate(dsi->ref);
+       fout = target_mbps * USEC_PER_SEC;
+
+       /* constraint: 5Mhz <= Fref / N <= 40MHz */
+       min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
+       max_prediv = fin / (5 * USEC_PER_SEC);
+
+       /* constraint: 80MHz <= Fvco <= 1500Mhz */
+       fvco_min = 80 * USEC_PER_SEC;
+       fvco_max = 1500 * USEC_PER_SEC;
+
+       for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
+               u64 tmp;
+               u32 delta;
+               /* Fvco = Fref * M / N */
+               tmp = (u64)fout * _prediv;
+               do_div(tmp, fin);
+               _fbdiv = tmp;
+               /*
+                * Due to the use of a "by 2 pre-scaler," the range of the
+                * feedback multiplication value M is limited to even division
+                * numbers, and m must be greater than 6, not bigger than 512.
+                */
+               if (_fbdiv < 6 || _fbdiv > 512)
+                       continue;
+
+               _fbdiv += _fbdiv % 2;
+
+               tmp = (u64)_fbdiv * fin;
+               do_div(tmp, _prediv);
+               if (tmp < fvco_min || tmp > fvco_max)
+                       continue;
+
+               delta = abs(fout - tmp);
+               if (delta < min_delta) {
+                       best_prediv = _prediv;
+                       best_fbdiv = _fbdiv;
+                       min_delta = delta;
+                       best_freq = tmp;
+               }
+       }
+
+       if (best_freq) {
+               dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC);
+               *lane_mbps = dsi->lane_mbps;
+               dsi->input_div = best_prediv;
+               dsi->feedback_div = best_fbdiv;
+       } else {
+               dev_err(dsi->dsi_host, "Can not find best_freq for DPHY\n");
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+struct hstt {
+       unsigned int maxfreq;
+       struct mipi_dsi_phy_timing timing;
+};
+
+#define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) \
+{                                      \
+       .maxfreq = _maxfreq,            \
+       .timing = {                     \
+               .clk_lp2hs = _c_lp2hs,  \
+               .clk_hs2lp = _c_hs2lp,  \
+               .data_lp2hs = _d_lp2hs, \
+               .data_hs2lp = _d_hs2lp, \
+       }                               \
+}
+
+/*
+ * Table A-3 High-Speed Transition Times
+ * (Note spacing is deliberate for readability).
+ */
+static struct hstt hstt_table[] = {
+       HSTT(  90,  32, 20,  26, 13),
+       HSTT( 100,  35, 23,  28, 14),
+       HSTT( 110,  32, 22,  26, 13),
+       HSTT( 130,  31, 20,  27, 13),
+       HSTT( 140,  33, 22,  26, 14),
+       HSTT( 150,  33, 21,  26, 14),
+       HSTT( 170,  32, 20,  27, 13),
+       HSTT( 180,  36, 23,  30, 15),
+       HSTT( 200,  40, 22,  33, 15),
+       HSTT( 220,  40, 22,  33, 15),
+       HSTT( 240,  44, 24,  36, 16),
+       HSTT( 250,  48, 24,  38, 17),
+       HSTT( 270,  48, 24,  38, 17),
+       HSTT( 300,  50, 27,  41, 18),
+       HSTT( 330,  56, 28,  45, 18),
+       HSTT( 360,  59, 28,  48, 19),
+       HSTT( 400,  61, 30,  50, 20),
+       HSTT( 450,  67, 31,  55, 21),
+       HSTT( 500,  73, 31,  59, 22),
+       HSTT( 550,  79, 36,  63, 24),
+       HSTT( 600,  83, 37,  68, 25),
+       HSTT( 650,  90, 38,  73, 27),
+       HSTT( 700,  95, 40,  77, 28),
+       HSTT( 750, 102, 40,  84, 28),
+       HSTT( 800, 106, 42,  87, 30),
+       HSTT( 850, 113, 44,  93, 31),
+       HSTT( 900, 118, 47,  98, 32),
+       HSTT( 950, 124, 47, 102, 34),
+       HSTT(1000, 130, 49, 107, 35),
+       HSTT(1050, 135, 51, 111, 37),
+       HSTT(1100, 139, 51, 114, 38),
+       HSTT(1150, 146, 54, 120, 40),
+       HSTT(1200, 153, 57, 125, 41),
+       HSTT(1250, 158, 58, 130, 42),
+       HSTT(1300, 163, 58, 135, 44),
+       HSTT(1350, 168, 60, 140, 45),
+       HSTT(1400, 172, 64, 144, 47),
+       HSTT(1450, 176, 65, 148, 48),
+       HSTT(1500, 181, 66, 153, 50)
+};
+
+static int dw_mipi_dsi_rockchip_get_timing(void *priv_data,
+                                          unsigned int lane_mbps,
+                                          struct mipi_dsi_phy_timing *timing)
+{
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(hstt_table); i++)
+               if (lane_mbps < hstt_table[i].maxfreq)
+                       break;
+
+       if (i == ARRAY_SIZE(hstt_table))
+               i--;
+
+       *timing = hstt_table[i].timing;
+
+       return 0;
+}
+
+static const struct mipi_dsi_phy_ops dsi_rockchip_phy_ops = {
+       .init = dsi_phy_init,
+       .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
+       .get_timing = dw_mipi_dsi_rockchip_get_timing,
+       .post_set_mode = dsi_phy_post_set_mode,
+};
+
+static int dw_mipi_dsi_rockchip_attach(struct udevice *dev)
+{
+       struct dw_rockchip_dsi_priv *priv = dev_get_priv(dev);
+       struct mipi_dsi_device *device = &priv->device;
+       struct mipi_dsi_panel_plat *mplat;
+       struct display_timing timings;
+       int ret;
+
+       ret = uclass_first_device_err(UCLASS_PANEL, &priv->panel);
+       if (ret) {
+               dev_err(dev, "panel device error %d\n", ret);
+               return ret;
+       }
+
+       mplat = dev_get_plat(priv->panel);
+       mplat->device = &priv->device;
+       device->lanes = mplat->lanes;
+       device->format = mplat->format;
+       device->mode_flags = mplat->mode_flags;
+
+       ret = panel_get_display_timing(priv->panel, &timings);
+       if (ret) {
+               ret = ofnode_decode_display_timing(dev_ofnode(priv->panel),
+                                                  0, &timings);
+               if (ret) {
+                       dev_err(dev, "decode display timing error %d\n", ret);
+                       return ret;
+               }
+       }
+
+       ret = uclass_get_device(UCLASS_DSI_HOST, 0, &priv->dsi_host);
+       if (ret) {
+               dev_err(dev, "No video dsi host detected %d\n", ret);
+               return ret;
+       }
+
+       ret = dsi_host_init(priv->dsi_host, device, &timings, 4,
+                           &dsi_rockchip_phy_ops);
+       if (ret) {
+               dev_err(dev, "failed to initialize mipi dsi host\n");
+               return ret;
+       }
+
+       return 0;
+}
+
+static int dw_mipi_dsi_rockchip_set_bl(struct udevice *dev, int percent)
+{
+       struct dw_rockchip_dsi_priv *priv = dev_get_priv(dev);
+       int ret;
+
+       /*
+        * Allow backlight to be optional, since this driver may be
+        * used to simply detect a panel rather than bring one up.
+        */
+       ret = panel_enable_backlight(priv->panel);
+       if ((ret) && (ret != -ENOSYS)) {
+               dev_err(dev, "panel %s enable backlight error %d\n",
+                       priv->panel->name, ret);
+               return ret;
+       }
+
+       ret = dsi_host_enable(priv->dsi_host);
+       if (ret) {
+               dev_err(dev, "failed to enable mipi dsi host\n");
+               return ret;
+       }
+
+       return 0;
+}
+
+static void dw_mipi_dsi_rockchip_config(struct dw_rockchip_dsi_priv *dsi)
+{
+       if (dsi->cdata->lanecfg1_grf_reg)
+               dsi_write(dsi, dsi->cdata->lanecfg1_grf_reg,
+                         dsi->cdata->lanecfg1);
+
+       if (dsi->cdata->lanecfg2_grf_reg)
+               dsi_write(dsi, dsi->cdata->lanecfg2_grf_reg,
+                         dsi->cdata->lanecfg2);
+
+       if (dsi->cdata->enable_grf_reg)
+               dsi_write(dsi, dsi->cdata->enable_grf_reg,
+                         dsi->cdata->enable);
+}
+
+static int dw_mipi_dsi_rockchip_bind(struct udevice *dev)
+{
+       int ret;
+
+       ret = device_bind_driver_to_node(dev, "dw_mipi_dsi", "dsihost",
+                                        dev_ofnode(dev), NULL);
+       if (ret) {
+               dev_err(dev, "failed to bind driver to node\n");
+               return ret;
+       }
+
+       return dm_scan_fdt_dev(dev);
+}
+
+static int dw_mipi_dsi_rockchip_probe(struct udevice *dev)
+{
+       struct dw_rockchip_dsi_priv *priv = dev_get_priv(dev);
+       struct mipi_dsi_device *device = &priv->device;
+       int ret, i;
+       const struct rockchip_dw_dsi_chip_data *cdata =
+                       (const struct rockchip_dw_dsi_chip_data *)dev_get_driver_data(dev);
+
+       device->dev = dev;
+
+       priv->base = (void *)dev_read_addr(dev);
+       if ((fdt_addr_t)priv->base == FDT_ADDR_T_NONE) {
+               dev_err(dev, "dsi dt register address error\n");
+               return -EINVAL;
+       }
+
+       i = 0;
+       while (cdata[i].reg) {
+               if (cdata[i].reg == (fdt_addr_t)priv->base) {
+                       priv->cdata = &cdata[i];
+                       break;
+               }
+
+               i++;
+       }
+
+       if (!priv->cdata) {
+               dev_err(dev, "no dsi-config for %s node\n", dev->name);
+               return -EINVAL;
+       }
+
+       /*
+        * Get an optional external dphy. The external dphy stays as
+        * NULL if it's not initialized.
+        */
+       ret = generic_phy_get_by_name(dev, "dphy", &priv->phy);
+       if ((ret) && (ret != -ENODEV)) {
+               dev_err(dev, "failed to get mipi dphy: %d\n", ret);
+               return -EINVAL;
+       }
+
+       priv->pclk = devm_clk_get(dev, "pclk");
+       if (IS_ERR(priv->pclk)) {
+               dev_err(dev, "peripheral clock get error %d\n", ret);
+               return ret;
+       }
+
+       /* Get a ref clock only if not using an external phy. */
+       if (&priv->phy) {
+               dev_dbg(dev, "setting priv->ref to NULL\n");
+               priv->ref = NULL;
+
+       } else {
+               priv->ref = devm_clk_get(dev, "ref");
+               if (ret) {
+                       dev_err(dev, "pll reference clock get error %d\n", ret);
+                       return ret;
+               }
+       }
+
+       priv->rst = devm_reset_control_get_by_index(device->dev, 0);
+       if (IS_ERR(priv->rst)) {
+               dev_err(dev, "missing dsi hardware reset\n");
+               return ret;
+       }
+
+       /* Reset */
+       reset_deassert(priv->rst);
+
+       dw_mipi_dsi_rockchip_config(priv);
+
+       return 0;
+}
+
+struct video_bridge_ops dw_mipi_dsi_rockchip_ops = {
+       .attach = dw_mipi_dsi_rockchip_attach,
+       .set_backlight = dw_mipi_dsi_rockchip_set_bl,
+};
+
+static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = {
+       {
+               .reg = 0xfe060000,
+               .lanecfg1_grf_reg = RK3568_GRF_VO_CON2,
+               .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI0_SKEWCALHS |
+                                         RK3568_DSI0_FORCETXSTOPMODE |
+                                         RK3568_DSI0_TURNDISABLE |
+                                         RK3568_DSI0_FORCERXMODE),
+               .max_data_lanes = 4,
+       },
+       {
+               .reg = 0xfe070000,
+               .lanecfg1_grf_reg = RK3568_GRF_VO_CON3,
+               .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI1_SKEWCALHS |
+                                         RK3568_DSI1_FORCETXSTOPMODE |
+                                         RK3568_DSI1_TURNDISABLE |
+                                         RK3568_DSI1_FORCERXMODE),
+               .max_data_lanes = 4,
+       },
+       { /* sentinel */ }
+};
+
+static const struct udevice_id dw_mipi_dsi_rockchip_dt_ids[] = {
+       { .compatible = "rockchip,rk3568-mipi-dsi",
+         .data = (long)&rk3568_chip_data,
+       },
+       { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(dw_mipi_dsi_rockchip) = {
+       .name                   = "dw-mipi-dsi-rockchip",
+       .id                     = UCLASS_VIDEO_BRIDGE,
+       .of_match               = dw_mipi_dsi_rockchip_dt_ids,
+       .bind                   = dw_mipi_dsi_rockchip_bind,
+       .probe                  = dw_mipi_dsi_rockchip_probe,
+       .ops                    = &dw_mipi_dsi_rockchip_ops,
+       .priv_auto              = sizeof(struct dw_rockchip_dsi_priv),
+};

diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index bc98ab6..e21ac7e 100644 (file)
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -307,7 +307,8 @@ static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
                      __func__, dev_read_name(dev));
                return -EINVAL;
        }
-       if (strstr(compat, "edp")) {
+       if (strstr(compat, "edp") ||
+           strstr(compat, "rk3288-dp")) {
                vop_id = VOP_MODE_EDP;
        } else if (strstr(compat, "mipi")) {
                vop_id = VOP_MODE_MIPI;

diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c
index 91c91ee..6a6473e 100644 (file)
--- a/drivers/video/simple_panel.c
+++ b/drivers/video/simple_panel.c
@@ -8,6 +8,7 @@
 #include <backlight.h>
 #include <dm.h>
 #include <log.h>
+#include <mipi_dsi.h>
 #include <panel.h>
 #include <asm/gpio.h>
 #include <power/regulator.h>
@@ -18,6 +19,19 @@ struct simple_panel_priv {
        struct gpio_desc enable;
 };
 
+/* List of supported DSI panels */
+enum {
+       PANEL_NON_DSI,
+       PANASONIC_VVX10F004B00,
+};
+
+static const struct mipi_dsi_panel_plat panasonic_vvx10f004b00 = {
+       .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+                     MIPI_DSI_CLOCK_NON_CONTINUOUS,
+       .format = MIPI_DSI_FMT_RGB888,
+       .lanes = 4,
+};
+
 static int simple_panel_enable_backlight(struct udevice *dev)
 {
        struct simple_panel_priv *priv = dev_get_priv(dev);
@@ -48,12 +62,21 @@ static int simple_panel_set_backlight(struct udevice *dev, int percent)
        return 0;
 }
 
+static int simple_panel_get_display_timing(struct udevice *dev,
+                                          struct display_timing *timings)
+{
+       const void *blob = gd->fdt_blob;
+
+       return fdtdec_decode_display_timing(blob, dev_of_offset(dev),
+                                           0, timings);
+}
+
 static int simple_panel_of_to_plat(struct udevice *dev)
 {
        struct simple_panel_priv *priv = dev_get_priv(dev);
        int ret;
 
-       if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
+       if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
                ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
                                                   "power-supply", &priv->reg);
                if (ret) {
@@ -87,21 +110,34 @@ static int simple_panel_of_to_plat(struct udevice *dev)
 static int simple_panel_probe(struct udevice *dev)
 {
        struct simple_panel_priv *priv = dev_get_priv(dev);
+       struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+       const u32 dsi_data = dev_get_driver_data(dev);
        int ret;
 
-       if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
+       if (CONFIG_IS_ENABLED(DM_REGULATOR) && priv->reg) {
                debug("%s: Enable regulator '%s'\n", __func__, priv->reg->name);
                ret = regulator_set_enable(priv->reg, true);
                if (ret)
                        return ret;
        }
 
+       switch (dsi_data) {
+       case PANASONIC_VVX10F004B00:
+               memcpy(plat, &panasonic_vvx10f004b00,
+                      sizeof(panasonic_vvx10f004b00));
+               break;
+       case PANEL_NON_DSI:
+       default:
+               break;
+       }
+
        return 0;
 }
 
 static const struct panel_ops simple_panel_ops = {
        .enable_backlight       = simple_panel_enable_backlight,
        .set_backlight          = simple_panel_set_backlight,
+       .get_display_timing     = simple_panel_get_display_timing,
 };
 
 static const struct udevice_id simple_panel_ids[] = {
@@ -113,15 +149,18 @@ static const struct udevice_id simple_panel_ids[] = {
        { .compatible = "lg,lb070wv8" },
        { .compatible = "sharp,lq123p1jx31" },
        { .compatible = "boe,nv101wxmn51" },
+       { .compatible = "panasonic,vvx10f004b00",
+         .data = PANASONIC_VVX10F004B00 },
        { }
 };
 
 U_BOOT_DRIVER(simple_panel) = {
-       .name   = "simple_panel",
-       .id     = UCLASS_PANEL,
-       .of_match = simple_panel_ids,
-       .ops    = &simple_panel_ops,
+       .name           = "simple_panel",
+       .id             = UCLASS_PANEL,
+       .of_match       = simple_panel_ids,
+       .ops            = &simple_panel_ops,
        .of_to_plat     = simple_panel_of_to_plat,
        .probe          = simple_panel_probe,
        .priv_auto      = sizeof(struct simple_panel_priv),
+       .plat_auto      = sizeof(struct mipi_dsi_panel_plat),
 };

diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
index 4f5d098..0324a05 100644 (file)
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -5,21 +5,27 @@
  * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
  */
 
+#include <clk.h>
 #include <common.h>
 #include <display.h>
 #include <dm.h>
 #include <dw_hdmi.h>
 #include <edid.h>
 #include <log.h>
+#include <reset.h>
 #include <time.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/lcdc.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
+#include <power/regulator.h>
 
 struct sunxi_dw_hdmi_priv {
        struct dw_hdmi hdmi;
+       struct reset_ctl_bulk resets;
+       struct clk_bulk clocks;
+       struct udevice *hvcc;
 };
 
 struct sunxi_hdmi_phy {
@@ -329,6 +335,9 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
        int ret;
 
+       if (priv->hvcc)
+               regulator_set_enable(priv->hvcc, true);
+
        /* Set pll3 to 297 MHz */
        clock_set_pll3(297000000);
 
@@ -336,14 +345,16 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
        clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
                        CCM_HDMI_CTRL_PLL3);
 
-       /* Set ahb gating to pass */
-       setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
+       /* This reset is referenced from the PHY devicetree node. */
        setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
-       setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
-       setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);
 
-       /* Clock on */
-       setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
+       ret = reset_deassert_bulk(&priv->resets);
+       if (ret)
+               return ret;
+
+       ret = clk_enable_bulk(&priv->clocks);
+       if (ret)
+               return ret;
 
        sunxi_dw_hdmi_phy_init(&priv->hdmi);
 
@@ -362,6 +373,7 @@ static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev)
 {
        struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
        struct dw_hdmi *hdmi = &priv->hdmi;
+       int ret;
 
        hdmi->ioaddr = (ulong)dev_read_addr(dev);
        hdmi->i2c_clk_high = 0xd8;
@@ -369,6 +381,18 @@ static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev)
        hdmi->reg_io_width = 1;
        hdmi->phy_set = sunxi_dw_hdmi_phy_cfg;
 
+       ret = reset_get_bulk(dev, &priv->resets);
+       if (ret)
+               return ret;
+
+       ret = clk_get_bulk(dev, &priv->clocks);
+       if (ret)
+               return ret;
+
+       ret = device_get_supply_regulator(dev, "hvcc-supply", &priv->hvcc);
+       if (ret)
+               priv->hvcc = NULL;
+
        return 0;
 }
 

diff --git a/drivers/video/tdo-tl070wsh30.c b/drivers/video/tdo-tl070wsh30.c
index 7ad0af7..273672d 100644 (file)
--- a/drivers/video/tdo-tl070wsh30.c
+++ b/drivers/video/tdo-tl070wsh30.c
@@ -75,7 +75,7 @@ static int tl070wsh30_panel_of_to_plat(struct udevice *dev)
        struct tl070wsh30_panel_priv *priv = dev_get_priv(dev);
        int ret;
 
-       if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
+       if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
                ret =  device_get_supply_regulator(dev, "power-supply",
                                                   &priv->reg);
                if (ret && ret != -ENOENT) {
@@ -108,7 +108,7 @@ static int tl070wsh30_panel_probe(struct udevice *dev)
        struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
        int ret;
 
-       if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
+       if (CONFIG_IS_ENABLED(DM_REGULATOR) && priv->reg) {
                ret = regulator_set_enable(priv->reg, true);
                if (ret)
                        return ret;

diff --git a/drivers/video/tegra20/Kconfig b/drivers/video/tegra20/Kconfig
new file mode 100644 (file)
index 0000000..5b1dfbf
--- /dev/null
+++ b/drivers/video/tegra20/Kconfig
@@ -0,0 +1,17 @@
+config VIDEO_TEGRA20
+       bool "Enable Display Controller support on Tegra20 and Tegra 30"
+       depends on OF_CONTROL
+       help
+          T20/T30 support video output to an attached LCD panel as well as
+          other options such as HDMI. Only the LCD is supported in U-Boot.
+          This option enables this support which can be used on devices which
+          have an LCD display connected.
+
+config VIDEO_DSI_TEGRA30
+       bool "Enable Tegra 30 DSI support"
+       depends on PANEL && DM_GPIO
+       select VIDEO_TEGRA20
+       select VIDEO_MIPI_DSI
+       help
+          T30 has native support for DSI panels. This option enables support
+          for such panels which can be used on endeavoru and tf600t.

diff --git a/drivers/video/tegra20/Makefile b/drivers/video/tegra20/Makefile
new file mode 100644 (file)
index 0000000..e82ee96
--- /dev/null
+++ b/drivers/video/tegra20/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_VIDEO_TEGRA20) += tegra-dc.o
+obj-$(CONFIG_VIDEO_DSI_TEGRA30) += tegra-dsi.o mipi-phy.o

diff --git a/drivers/video/tegra20/mipi-phy.c b/drivers/video/tegra20/mipi-phy.c
new file mode 100644 (file)
index 0000000..c3ebc40
--- /dev/null
+++ b/drivers/video/tegra20/mipi-phy.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2013 NVIDIA Corporation
+ */
+
+#include <common.h>
+#include <linux/err.h>
+
+#include "mipi-phy.h"
+
+/*
+ * Default D-PHY timings based on MIPI D-PHY specification. Derived from the
+ * valid ranges specified in Section 6.9, Table 14, Page 40 of the D-PHY
+ * specification (v1.2) with minor adjustments.
+ */
+int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
+                                unsigned long period)
+{
+       timing->clkmiss = 0;
+       timing->clkpost = 70 + 52 * period;
+       timing->clkpre = 8;
+       timing->clkprepare = 65;
+       timing->clksettle = 95;
+       timing->clktermen = 0;
+       timing->clktrail = 80;
+       timing->clkzero = 260;
+       timing->dtermen = 0;
+       timing->eot = 0;
+       timing->hsexit = 120;
+       timing->hsprepare = 65 + 5 * period;
+       timing->hszero = 145 + 5 * period;
+       timing->hssettle = 85 + 6 * period;
+       timing->hsskip = 40;
+
+       /*
+        * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40)
+        * contains this formula as:
+        *
+        *     T_HS-TRAIL = max(n * 8 * period, 60 + n * 4 * period)
+        *
+        * where n = 1 for forward-direction HS mode and n = 4 for reverse-
+        * direction HS mode. There's only one setting and this function does
+        * not parameterize on anything other that period, so this code will
+        * assumes that reverse-direction HS mode is supported and uses n = 4.
+        */
+       timing->hstrail = max(4 * 8 * period, 60 + 4 * 4 * period);
+
+       timing->init = 100000;
+       timing->lpx = 60;
+       timing->taget = 5 * timing->lpx;
+       timing->tago = 4 * timing->lpx;
+       timing->tasure = 2 * timing->lpx;
+       timing->wakeup = 1000000;
+
+       return 0;
+}
+
+/*
+ * Validate D-PHY timing according to MIPI D-PHY specification
+ * (v1.2, Section 6.9 "Global Operation Timing Parameters").
+ */
+int mipi_dphy_timing_validate(struct mipi_dphy_timing *timing,
+                             unsigned long period)
+{
+       if (timing->clkmiss > 60)
+               return -EINVAL;
+
+       if (timing->clkpost < (60 + 52 * period))
+               return -EINVAL;
+
+       if (timing->clkpre < 8)
+               return -EINVAL;
+
+       if (timing->clkprepare < 38 || timing->clkprepare > 95)
+               return -EINVAL;
+
+       if (timing->clksettle < 95 || timing->clksettle > 300)
+               return -EINVAL;
+
+       if (timing->clktermen > 38)
+               return -EINVAL;
+
+       if (timing->clktrail < 60)
+               return -EINVAL;
+
+       if (timing->clkprepare + timing->clkzero < 300)
+               return -EINVAL;
+
+       if (timing->dtermen > 35 + 4 * period)
+               return -EINVAL;
+
+       if (timing->eot > 105 + 12 * period)
+               return -EINVAL;
+
+       if (timing->hsexit < 100)
+               return -EINVAL;
+
+       if (timing->hsprepare < 40 + 4 * period ||
+           timing->hsprepare > 85 + 6 * period)
+               return -EINVAL;
+
+       if (timing->hsprepare + timing->hszero < 145 + 10 * period)
+               return -EINVAL;
+
+       if ((timing->hssettle < 85 + 6 * period) ||
+           (timing->hssettle > 145 + 10 * period))
+               return -EINVAL;
+
+       if (timing->hsskip < 40 || timing->hsskip > 55 + 4 * period)
+               return -EINVAL;
+
+       if (timing->hstrail < max(8 * period, 60 + 4 * period))
+               return -EINVAL;
+
+       if (timing->init < 100000)
+               return -EINVAL;
+
+       if (timing->lpx < 50)
+               return -EINVAL;
+
+       if (timing->taget != 5 * timing->lpx)
+               return -EINVAL;
+
+       if (timing->tago != 4 * timing->lpx)
+               return -EINVAL;
+
+       if (timing->tasure < timing->lpx || timing->tasure > 2 * timing->lpx)
+               return -EINVAL;
+
+       if (timing->wakeup < 1000000)
+               return -EINVAL;
+
+       return 0;
+}

diff --git a/drivers/video/tegra20/mipi-phy.h b/drivers/video/tegra20/mipi-phy.h
new file mode 100644 (file)
index 0000000..41889a7
--- /dev/null
+++ b/drivers/video/tegra20/mipi-phy.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2013 NVIDIA Corporation
+ */
+
+#ifndef DRM_TEGRA_MIPI_PHY_H
+#define DRM_TEGRA_MIPI_PHY_H
+
+/*
+ * D-PHY timing parameters
+ *
+ * A detailed description of these parameters can be found in the  MIPI
+ * Alliance Specification for D-PHY, Section 5.9 "Global Operation Timing
+ * Parameters".
+ *
+ * All parameters are specified in nanoseconds.
+ */
+struct mipi_dphy_timing {
+       unsigned int clkmiss;
+       unsigned int clkpost;
+       unsigned int clkpre;
+       unsigned int clkprepare;
+       unsigned int clksettle;
+       unsigned int clktermen;
+       unsigned int clktrail;
+       unsigned int clkzero;
+       unsigned int dtermen;
+       unsigned int eot;
+       unsigned int hsexit;
+       unsigned int hsprepare;
+       unsigned int hszero;
+       unsigned int hssettle;
+       unsigned int hsskip;
+       unsigned int hstrail;
+       unsigned int init;
+       unsigned int lpx;
+       unsigned int taget;
+       unsigned int tago;
+       unsigned int tasure;
+       unsigned int wakeup;
+};
+
+int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
+                                unsigned long period);
+int mipi_dphy_timing_validate(struct mipi_dphy_timing *timing,
+                             unsigned long period);
+
+#endif

diff --git a/drivers/video/tegra.c b/drivers/video/tegra20/tegra-dc.c
similarity index 82%
rename from drivers/video/tegra.c
rename to drivers/video/tegra20/tegra-dc.c
index 3f9fcd0..f53ad46 100644 (file)
--- a/drivers/video/tegra.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <backlight.h>
 #include <dm.h>
 #include <fdtdec.h>
 #include <log.h>
@@ -33,20 +34,24 @@ struct tegra_lcd_priv {
        enum video_log2_bpp log2_bpp;   /* colour depth */
        struct display_timing timing;
        struct udevice *panel;
-       struct disp_ctlr *disp;         /* Display controller to use */
+       struct dc_ctlr *dc;             /* Display controller regmap */
        fdt_addr_t frame_buffer;        /* Address of frame buffer */
        unsigned pixel_clock;           /* Pixel clock in Hz */
+       int dc_clk[2];                  /* Contains clk and its parent */
+       bool rotation;                  /* 180 degree panel turn */
 };
 
 enum {
        /* Maximum LCD size we support */
-       LCD_MAX_WIDTH           = 1366,
-       LCD_MAX_HEIGHT          = 768,
+       LCD_MAX_WIDTH           = 1920,
+       LCD_MAX_HEIGHT          = 1200,
        LCD_MAX_LOG2_BPP        = VIDEO_BPP16,
 };
 
-static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
+static void update_window(struct tegra_lcd_priv *priv,
+                         struct disp_ctl_win *win)
 {
+       struct dc_ctlr *dc = priv->dc;
        unsigned h_dda, v_dda;
        unsigned long val;
 
@@ -87,6 +92,10 @@ static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
        val = WIN_ENABLE;
        if (win->bpp < 24)
                val |= COLOR_EXPAND;
+
+       if (priv->rotation)
+               val |= H_DIRECTION | V_DIRECTION;
+
        writel(val, &dc->win.win_opt);
 
        writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
@@ -134,7 +143,7 @@ static int update_display_mode(struct dc_disp_reg *disp,
         * the display clock (typically 600MHz) to the pixel clock. We round
         * up or down as requried.
         */
-       rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
+       rate = clock_get_periph_rate(priv->dc_clk[0], priv->dc_clk[1]);
        div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2;
        debug("Display clock %lu, divider %lu\n", rate, div);
 
@@ -223,8 +232,14 @@ static void rgb_enable(struct dc_com_reg *com)
 static int setup_window(struct disp_ctl_win *win,
                        struct tegra_lcd_priv *priv)
 {
-       win->x = 0;
-       win->y = 0;
+       if (priv->rotation) {
+               win->x = priv->width * 2;
+               win->y = priv->height;
+       } else {
+               win->x = 0;
+               win->y = 0;
+       }
+
        win->w = priv->width;
        win->h = priv->height;
        win->out_x = 0;
@@ -268,32 +283,36 @@ static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv,
                               void *default_lcd_base)
 {
        struct disp_ctl_win window;
-       struct dc_ctlr *dc;
+       unsigned long rate = clock_get_rate(priv->dc_clk[1]);
 
        priv->frame_buffer = (u32)default_lcd_base;
 
-       dc = (struct dc_ctlr *)priv->disp;
+       /*
+        * We halve the rate if DISP1 paret is PLLD, since actual parent
+        * is plld_out0 which is PLLD divided by 2.
+        */
+       if (priv->dc_clk[1] == CLOCK_ID_DISPLAY)
+               rate /= 2;
 
        /*
-        * A header file for clock constants was NAKed upstream.
-        * TODO: Put this into the FDT and fdt_lcd struct when we have clock
-        * support there
+        * HOST1X is init by default at 150MHz with PLLC as parent
         */
-       clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
-                              144 * 1000000);
-       clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
-                              600 * 1000000);
-       basic_init(&dc->cmd);
-       basic_init_timer(&dc->disp);
-       rgb_enable(&dc->com);
+       clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_CGENERAL,
+                              150 * 1000000);
+       clock_start_periph_pll(priv->dc_clk[0], priv->dc_clk[1],
+                              rate);
+
+       basic_init(&priv->dc->cmd);
+       basic_init_timer(&priv->dc->disp);
+       rgb_enable(&priv->dc->com);
 
        if (priv->pixel_clock)
-               update_display_mode(&dc->disp, priv);
+               update_display_mode(&priv->dc->disp, priv);
 
        if (setup_window(&window, priv))
                return -1;
 
-       update_window(dc, &window);
+       update_window(priv, &window);
 
        return 0;
 }
@@ -307,14 +326,19 @@ static int tegra_lcd_probe(struct udevice *dev)
        int ret;
 
        /* Initialize the Tegra display controller */
+#ifdef CONFIG_TEGRA20
        funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
+#endif
+
        if (tegra_display_probe(blob, priv, (void *)plat->base)) {
                printf("%s: Failed to probe display driver\n", __func__);
                return -1;
        }
 
+#ifdef CONFIG_TEGRA20
        pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
        pinmux_tristate_disable(PMUX_PINGRP_GPU);
+#endif
 
        ret = panel_enable_backlight(priv->panel);
        if (ret) {
@@ -322,6 +346,12 @@ static int tegra_lcd_probe(struct udevice *dev)
                return ret;
        }
 
+       ret = panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT);
+       if (ret) {
+               debug("%s: Cannot set backlight to default, ret=%d\n", __func__, ret);
+               return ret;
+       }
+
        mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
                                        DCACHE_WRITETHROUGH);
 
@@ -347,12 +377,21 @@ static int tegra_lcd_of_to_plat(struct udevice *dev)
        int rgb;
        int ret;
 
-       priv->disp = dev_read_addr_ptr(dev);
-       if (!priv->disp) {
+       priv->dc = (struct dc_ctlr *)dev_read_addr_ptr(dev);
+       if (!priv->dc) {
                debug("%s: No display controller address\n", __func__);
                return -EINVAL;
        }
 
+       ret = clock_decode_pair(dev, priv->dc_clk);
+       if (ret < 0) {
+               debug("%s: Cannot decode clocks for '%s' (ret = %d)\n",
+                     __func__, dev->name, ret);
+               return -EINVAL;
+       }
+
+       priv->rotation = dev_read_bool(dev, "nvidia,180-rotation");
+
        rgb = fdt_subnode_offset(blob, node, "rgb");
        if (rgb < 0) {
                debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
@@ -360,18 +399,6 @@ static int tegra_lcd_of_to_plat(struct udevice *dev)
                return -EINVAL;
        }
 
-       ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
-       if (ret) {
-               debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
-                     __func__, dev->name, ret);
-               return -EINVAL;
-       }
-       timing = &priv->timing;
-       priv->width = timing->hactive.typ;
-       priv->height = timing->vactive.typ;
-       priv->pixel_clock = timing->pixelclock.typ;
-       priv->log2_bpp = VIDEO_BPP16;
-
        /*
         * Sadly the panel phandle is in an rgb subnode so we cannot use
         * uclass_get_device_by_phandle().
@@ -381,6 +408,7 @@ static int tegra_lcd_of_to_plat(struct udevice *dev)
                debug("%s: Cannot find panel information\n", __func__);
                return -EINVAL;
        }
+
        ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node,
                                             &priv->panel);
        if (ret) {
@@ -389,6 +417,30 @@ static int tegra_lcd_of_to_plat(struct udevice *dev)
                return ret;
        }
 
+       if (!strcmp(priv->panel->name, TEGRA_DSI_A) ||
+           !strcmp(priv->panel->name, TEGRA_DSI_B)) {
+               struct tegra_dc_plat *dc_plat = dev_get_plat(priv->panel);
+
+               dc_plat->dev = dev;
+               dc_plat->dc = priv->dc;
+       }
+
+       ret = panel_get_display_timing(priv->panel, &priv->timing);
+       if (ret) {
+               ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
+               if (ret) {
+                       debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
+                             __func__, dev->name, ret);
+                       return -EINVAL;
+               }
+       }
+
+       timing = &priv->timing;
+       priv->width = timing->hactive.typ;
+       priv->height = timing->vactive.typ;
+       priv->pixel_clock = timing->pixelclock.typ;
+       priv->log2_bpp = VIDEO_BPP16;
+
        return 0;
 }
 
@@ -414,6 +466,7 @@ static const struct video_ops tegra_lcd_ops = {
 
 static const struct udevice_id tegra_lcd_ids[] = {
        { .compatible = "nvidia,tegra20-dc" },
+       { .compatible = "nvidia,tegra30-dc" },
        { }
 };
 

diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra20/tegra-dsi.c
new file mode 100644 (file)
index 0000000..8c3404e
--- /dev/null
+++ b/drivers/video/tegra20/tegra-dsi.c
@@ -0,0 +1,864 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 NVIDIA Corporation
+ * Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <misc.h>
+#include <mipi_display.h>
+#include <mipi_dsi.h>
+#include <backlight.h>
+#include <panel.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <power/regulator.h>
+
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/display.h>
+#include <asm/arch-tegra30/dsi.h>
+
+#include "mipi-phy.h"
+
+#define USEC_PER_SEC   1000000L
+#define NSEC_PER_SEC   1000000000L
+
+struct tegra_dsi_priv {
+       struct mipi_dsi_host host;
+       struct mipi_dsi_device device;
+       struct mipi_dphy_timing dphy_timing;
+
+       struct udevice *panel;
+       struct display_timing timing;
+
+       struct dsi_ctlr *dsi;
+       struct udevice *avdd;
+
+       enum tegra_dsi_format format;
+
+       int dsi_clk;
+       int video_fifo_depth;
+       int host_fifo_depth;
+};
+
+static void tegra_dc_enable_controller(struct udevice *dev)
+{
+       struct tegra_dc_plat *dc_plat = dev_get_plat(dev);
+       struct dc_ctlr *dc = dc_plat->dc;
+       u32 value;
+
+       value = readl(&dc->disp.disp_win_opt);
+       value |= DSI_ENABLE;
+       writel(value, &dc->disp.disp_win_opt);
+
+       writel(GENERAL_UPDATE, &dc->cmd.state_ctrl);
+       writel(GENERAL_ACT_REQ, &dc->cmd.state_ctrl);
+}
+
+static const char * const error_report[16] = {
+       "SoT Error",
+       "SoT Sync Error",
+       "EoT Sync Error",
+       "Escape Mode Entry Command Error",
+       "Low-Power Transmit Sync Error",
+       "Peripheral Timeout Error",
+       "False Control Error",
+       "Contention Detected",
+       "ECC Error, single-bit",
+       "ECC Error, multi-bit",
+       "Checksum Error",
+       "DSI Data Type Not Recognized",
+       "DSI VC ID Invalid",
+       "Invalid Transmission Length",
+       "Reserved",
+       "DSI Protocol Violation",
+};
+
+static ssize_t tegra_dsi_read_response(struct dsi_misc_reg *misc,
+                                      const struct mipi_dsi_msg *msg,
+                                      size_t count)
+{
+       u8 *rx = msg->rx_buf;
+       unsigned int i, j, k;
+       size_t size = 0;
+       u16 errors;
+       u32 value;
+
+       /* read and parse packet header */
+       value = readl(&misc->dsi_rd_data);
+
+       switch (value & 0x3f) {
+       case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
+               errors = (value >> 8) & 0xffff;
+               printf("%s: Acknowledge and error report: %04x\n",
+                      __func__, errors);
+               for (i = 0; i < ARRAY_SIZE(error_report); i++)
+                       if (errors & BIT(i))
+                               printf("%s:  %2u: %s\n", __func__, i,
+                                      error_report[i]);
+               break;
+
+       case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
+               rx[0] = (value >> 8) & 0xff;
+               size = 1;
+               break;
+
+       case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
+               rx[0] = (value >>  8) & 0xff;
+               rx[1] = (value >> 16) & 0xff;
+               size = 2;
+               break;
+
+       case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
+               size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
+               break;
+
+       case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
+               size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
+               break;
+
+       default:
+               printf("%s: unhandled response type: %02x\n",
+                      __func__, value & 0x3f);
+               return -EPROTO;
+       }
+
+       size = min(size, msg->rx_len);
+
+       if (msg->rx_buf && size > 0) {
+               for (i = 0, j = 0; i < count - 1; i++, j += 4) {
+                       u8 *rx = msg->rx_buf + j;
+
+                       value = readl(&misc->dsi_rd_data);
+
+                       for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
+                               rx[j + k] = (value >> (k << 3)) & 0xff;
+               }
+       }
+
+       return size;
+}
+
+static int tegra_dsi_transmit(struct dsi_misc_reg *misc,
+                             unsigned long timeout)
+{
+       writel(DSI_TRIGGER_HOST, &misc->dsi_trigger);
+
+       while (timeout--) {
+               u32 value = readl(&misc->dsi_trigger);
+
+               if ((value & DSI_TRIGGER_HOST) == 0)
+                       return 0;
+
+               udelay(1000);
+       }
+
+       debug("timeout waiting for transmission to complete\n");
+       return -ETIMEDOUT;
+}
+
+static int tegra_dsi_wait_for_response(struct dsi_misc_reg *misc,
+                                      unsigned long timeout)
+{
+       while (timeout--) {
+               u32 value = readl(&misc->dsi_status);
+               u8 count = value & 0x1f;
+
+               if (count > 0)
+                       return count;
+
+               udelay(1000);
+       }
+
+       debug("peripheral returned no data\n");
+       return -ETIMEDOUT;
+}
+
+static void tegra_dsi_writesl(struct dsi_misc_reg *misc,
+                             const void *buffer, size_t size)
+{
+       const u8 *buf = buffer;
+       size_t i, j;
+       u32 value;
+
+       for (j = 0; j < size; j += 4) {
+               value = 0;
+
+               for (i = 0; i < 4 && j + i < size; i++)
+                       value |= buf[j + i] << (i << 3);
+
+               writel(value, &misc->dsi_wr_data);
+       }
+}
+
+static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
+                                      const struct mipi_dsi_msg *msg)
+{
+       struct udevice *dev = (struct udevice *)host->dev;
+       struct tegra_dsi_priv *priv = dev_get_priv(dev);
+       struct dsi_misc_reg *misc = &priv->dsi->misc;
+       struct mipi_dsi_packet packet;
+       const u8 *header;
+       size_t count;
+       ssize_t err;
+       u32 value;
+
+       err = mipi_dsi_create_packet(&packet, msg);
+       if (err < 0)
+               return err;
+
+       header = packet.header;
+
+       /* maximum FIFO depth is 1920 words */
+       if (packet.size > priv->video_fifo_depth * 4)
+               return -ENOSPC;
+
+       /* reset underflow/overflow flags */
+       value = readl(&misc->dsi_status);
+       if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
+               value = DSI_HOST_CONTROL_FIFO_RESET;
+               writel(value, &misc->host_dsi_ctrl);
+               udelay(10);
+       }
+
+       value = readl(&misc->dsi_pwr_ctrl);
+       value |= DSI_POWER_CONTROL_ENABLE;
+       writel(value, &misc->dsi_pwr_ctrl);
+
+       mdelay(5);
+
+       value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
+               DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
+
+       /*
+        * The host FIFO has a maximum of 64 words, so larger transmissions
+        * need to use the video FIFO.
+        */
+       if (packet.size > priv->host_fifo_depth * 4)
+               value |= DSI_HOST_CONTROL_FIFO_SEL;
+
+       writel(value, &misc->host_dsi_ctrl);
+
+       /*
+        * For reads and messages with explicitly requested ACK, generate a
+        * BTA sequence after the transmission of the packet.
+        */
+       if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
+           (msg->rx_buf && msg->rx_len > 0)) {
+               value = readl(&misc->host_dsi_ctrl);
+               value |= DSI_HOST_CONTROL_PKT_BTA;
+               writel(value, &misc->host_dsi_ctrl);
+       }
+
+       value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
+       writel(value, &misc->dsi_ctrl);
+
+       /* write packet header, ECC is generated by hardware */
+       value = header[2] << 16 | header[1] << 8 | header[0];
+       writel(value, &misc->dsi_wr_data);
+
+       /* write payload (if any) */
+       if (packet.payload_length > 0)
+               tegra_dsi_writesl(misc, packet.payload,
+                                 packet.payload_length);
+
+       err = tegra_dsi_transmit(misc, 250);
+       if (err < 0)
+               return err;
+
+       if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
+           (msg->rx_buf && msg->rx_len > 0)) {
+               err = tegra_dsi_wait_for_response(misc, 250);
+               if (err < 0)
+                       return err;
+
+               count = err;
+
+               value = readl(&misc->dsi_rd_data);
+               switch (value) {
+               case 0x84:
+                       debug("%s: ACK\n", __func__);
+                       break;
+
+               case 0x87:
+                       debug("%s: ESCAPE\n", __func__);
+                       break;
+
+               default:
+                       printf("%s: unknown status: %08x\n", __func__, value);
+                       break;
+               }
+
+               if (count > 1) {
+                       err = tegra_dsi_read_response(misc, msg, count);
+                       if (err < 0) {
+                               printf("%s: failed to parse response: %zd\n",
+                                      __func__, err);
+                       } else {
+                               /*
+                                * For read commands, return the number of
+                                * bytes returned by the peripheral.
+                                */
+                               count = err;
+                       }
+               }
+       } else {
+               /*
+                * For write commands, we have transmitted the 4-byte header
+                * plus the variable-length payload.
+                */
+               count = 4 + packet.payload_length;
+       }
+
+       return count;
+}
+
+struct mipi_dsi_host_ops tegra_dsi_bridge_host_ops = {
+       .transfer       = tegra_dsi_host_transfer,
+};
+
+#define PKT_ID0(id)    ((((id) & 0x3f) <<  3) | (1 <<  9))
+#define PKT_LEN0(len)  (((len) & 0x07) <<  0)
+#define PKT_ID1(id)    ((((id) & 0x3f) << 13) | (1 << 19))
+#define PKT_LEN1(len)  (((len) & 0x07) << 10)
+#define PKT_ID2(id)    ((((id) & 0x3f) << 23) | (1 << 29))
+#define PKT_LEN2(len)  (((len) & 0x07) << 20)
+
+#define PKT_LP         BIT(30)
+#define NUM_PKT_SEQ    12
+
+/*
+ * non-burst mode with sync pulses
+ */
+static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
+       [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
+              PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
+              PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
+              PKT_LP,
+       [ 1] = 0,
+       [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
+              PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
+              PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
+              PKT_LP,
+       [ 3] = 0,
+       [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
+              PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
+              PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
+              PKT_LP,
+       [ 5] = 0,
+       [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
+              PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
+              PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
+       [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
+              PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
+              PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
+       [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
+              PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
+              PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
+              PKT_LP,
+       [ 9] = 0,
+       [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
+              PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
+              PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
+       [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
+              PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
+              PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
+};
+
+/*
+ * non-burst mode with sync events
+ */
+static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
+       [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
+              PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
+              PKT_LP,
+       [ 1] = 0,
+       [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
+              PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
+              PKT_LP,
+       [ 3] = 0,
+       [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
+              PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
+              PKT_LP,
+       [ 5] = 0,
+       [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
+              PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
+              PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
+       [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
+       [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
+              PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
+              PKT_LP,
+       [ 9] = 0,
+       [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
+              PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
+              PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
+       [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
+};
+
+static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
+       [ 0] = 0,
+       [ 1] = 0,
+       [ 2] = 0,
+       [ 3] = 0,
+       [ 4] = 0,
+       [ 5] = 0,
+       [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
+       [ 7] = 0,
+       [ 8] = 0,
+       [ 9] = 0,
+       [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
+       [11] = 0,
+};
+
+static void tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
+                                unsigned int *mulp, unsigned int *divp)
+{
+       switch (format) {
+       case MIPI_DSI_FMT_RGB666_PACKED:
+       case MIPI_DSI_FMT_RGB888:
+               *mulp = 3;
+               *divp = 1;
+               break;
+
+       case MIPI_DSI_FMT_RGB565:
+               *mulp = 2;
+               *divp = 1;
+               break;
+
+       case MIPI_DSI_FMT_RGB666:
+               *mulp = 9;
+               *divp = 4;
+               break;
+
+       default:
+               break;
+       }
+}
+
+static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
+                               enum tegra_dsi_format *fmt)
+{
+       switch (format) {
+       case MIPI_DSI_FMT_RGB888:
+               *fmt = TEGRA_DSI_FORMAT_24P;
+               break;
+
+       case MIPI_DSI_FMT_RGB666:
+               *fmt = TEGRA_DSI_FORMAT_18NP;
+               break;
+
+       case MIPI_DSI_FMT_RGB666_PACKED:
+               *fmt = TEGRA_DSI_FORMAT_18P;
+               break;
+
+       case MIPI_DSI_FMT_RGB565:
+               *fmt = TEGRA_DSI_FORMAT_16P;
+               break;
+
+       default:
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static void tegra_dsi_pad_calibrate(struct dsi_pad_ctrl_reg *pad)
+{
+       u32 value;
+
+       /* start calibration */
+       value = DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
+               DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
+               DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
+               DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
+               DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6) |
+               DSI_PAD_CONTROL_PAD_PDIO(0) |
+               DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
+               DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0);
+       writel(value, &pad->pad_ctrl);
+
+       clock_enable(PERIPH_ID_VI);
+       clock_enable(PERIPH_ID_CSI);
+       udelay(2);
+       reset_set_enable(PERIPH_ID_VI, 0);
+       reset_set_enable(PERIPH_ID_CSI, 0);
+
+       value = MIPI_CAL_TERMOSA(0x4);
+       writel(value, TEGRA_VI_BASE + (CSI_CILA_MIPI_CAL_CONFIG_0 << 2));
+
+       value = MIPI_CAL_TERMOSB(0x4);
+       writel(value, TEGRA_VI_BASE + (CSI_CILB_MIPI_CAL_CONFIG_0 << 2));
+
+       value = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
+       writel(value, TEGRA_VI_BASE + (CSI_DSI_MIPI_CAL_CONFIG << 2));
+
+       value = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
+       writel(value, TEGRA_VI_BASE + (CSI_MIPIBIAS_PAD_CONFIG << 2));
+
+       value = PAD_CIL_PDVREG(0x0);
+       writel(value, TEGRA_VI_BASE + (CSI_CIL_PAD_CONFIG << 2));
+}
+
+static void tegra_dsi_set_timeout(struct dsi_timeout_reg *rtimeout,
+                                 unsigned long bclk,
+                                 unsigned int vrefresh)
+{
+       unsigned int timeout;
+       u32 value;
+
+       /* one frame high-speed transmission timeout */
+       timeout = (bclk / vrefresh) / 512;
+       value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
+       writel(value, &rtimeout->dsi_timeout_0);
+
+       /* 2 ms peripheral timeout for panel */
+       timeout = 2 * bclk / 512 * 1000;
+       value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
+       writel(value, &rtimeout->dsi_timeout_1);
+
+       value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
+       writel(value, &rtimeout->dsi_to_tally);
+}
+
+static void tegra_dsi_set_phy_timing(struct dsi_timing_reg *ptiming,
+                                    unsigned long period,
+                                    const struct mipi_dphy_timing *dphy_timing)
+{
+       u32 value;
+
+       value = DSI_TIMING_FIELD(dphy_timing->hsexit, period, 1) << 24 |
+               DSI_TIMING_FIELD(dphy_timing->hstrail, period, 0) << 16 |
+               DSI_TIMING_FIELD(dphy_timing->hszero, period, 3) << 8 |
+               DSI_TIMING_FIELD(dphy_timing->hsprepare, period, 1);
+       writel(value, &ptiming->dsi_phy_timing_0);
+
+       value = DSI_TIMING_FIELD(dphy_timing->clktrail, period, 1) << 24 |
+               DSI_TIMING_FIELD(dphy_timing->clkpost, period, 1) << 16 |
+               DSI_TIMING_FIELD(dphy_timing->clkzero, period, 1) << 8 |
+               DSI_TIMING_FIELD(dphy_timing->lpx, period, 1);
+       writel(value, &ptiming->dsi_phy_timing_1);
+
+       value = DSI_TIMING_FIELD(dphy_timing->clkprepare, period, 1) << 16 |
+               DSI_TIMING_FIELD(dphy_timing->clkpre, period, 1) << 8 |
+               DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
+       writel(value, &ptiming->dsi_phy_timing_2);
+
+       value = DSI_TIMING_FIELD(dphy_timing->taget, period, 1) << 16 |
+               DSI_TIMING_FIELD(dphy_timing->tasure, period, 1) << 8 |
+               DSI_TIMING_FIELD(dphy_timing->tago, period, 1);
+       writel(value, &ptiming->dsi_bta_timing);
+}
+
+static void tegra_dsi_configure(struct udevice *dev,
+                               unsigned long mode_flags)
+{
+       struct tegra_dsi_priv *priv = dev_get_priv(dev);
+       struct mipi_dsi_device *device = &priv->device;
+       struct display_timing *timing = &priv->timing;
+
+       struct dsi_misc_reg *misc = &priv->dsi->misc;
+       struct dsi_pkt_seq_reg *pkt = &priv->dsi->pkt;
+       struct dsi_pkt_len_reg *len = &priv->dsi->len;
+
+       unsigned int hact, hsw, hbp, hfp, i, mul, div;
+       const u32 *pkt_seq;
+       u32 value;
+
+       tegra_dsi_get_muldiv(device->format, &mul, &div);
+
+       if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
+               printf("[DSI] Non-burst video mode with sync pulses\n");
+               pkt_seq = pkt_seq_video_non_burst_sync_pulses;
+       } else if (mode_flags & MIPI_DSI_MODE_VIDEO) {
+               printf("[DSI] Non-burst video mode with sync events\n");
+               pkt_seq = pkt_seq_video_non_burst_sync_events;
+       } else {
+               printf("[DSI] Command mode\n");
+               pkt_seq = pkt_seq_command_mode;
+       }
+
+       value = DSI_CONTROL_CHANNEL(0) |
+               DSI_CONTROL_FORMAT(priv->format) |
+               DSI_CONTROL_LANES(device->lanes - 1) |
+               DSI_CONTROL_SOURCE(0);
+       writel(value, &misc->dsi_ctrl);
+
+       writel(priv->video_fifo_depth, &misc->dsi_max_threshold);
+
+       value = DSI_HOST_CONTROL_HS;
+       writel(value, &misc->host_dsi_ctrl);
+
+       value = readl(&misc->dsi_ctrl);
+
+       if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
+               value |= DSI_CONTROL_HS_CLK_CTRL;
+
+       value &= ~DSI_CONTROL_TX_TRIG(3);
+
+       /* enable DCS commands for command mode */
+       if (mode_flags & MIPI_DSI_MODE_VIDEO)
+               value &= ~DSI_CONTROL_DCS_ENABLE;
+       else
+               value |= DSI_CONTROL_DCS_ENABLE;
+
+       value |= DSI_CONTROL_VIDEO_ENABLE;
+       value &= ~DSI_CONTROL_HOST_ENABLE;
+       writel(value, &misc->dsi_ctrl);
+
+       for (i = 0; i < NUM_PKT_SEQ; i++)
+               writel(pkt_seq[i], &pkt->dsi_pkt_seq_0_lo + i);
+
+       if (mode_flags & MIPI_DSI_MODE_VIDEO) {
+               /* horizontal active pixels */
+               hact = timing->hactive.typ * mul / div;
+
+               /* horizontal sync width */
+               hsw = timing->hsync_len.typ * mul / div;
+
+               /* horizontal back porch */
+               hbp = timing->hback_porch.typ * mul / div;
+
+               if ((mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
+                       hbp += hsw;
+
+               /* horizontal front porch */
+               hfp = timing->hfront_porch.typ * mul / div;
+
+               /* subtract packet overhead */
+               hsw -= 10;
+               hbp -= 14;
+               hfp -= 8;
+
+               writel(hsw << 16 | 0, &len->dsi_pkt_len_0_1);
+               writel(hact << 16 | hbp, &len->dsi_pkt_len_2_3);
+               writel(hfp, &len->dsi_pkt_len_4_5);
+               writel(0x0f0f << 16, &len->dsi_pkt_len_6_7);
+       } else {
+               /* 1 byte (DCS command) + pixel data */
+               value = 1 + timing->hactive.typ * mul / div;
+
+               writel(0, &len->dsi_pkt_len_0_1);
+               writel(value << 16, &len->dsi_pkt_len_2_3);
+               writel(value << 16, &len->dsi_pkt_len_4_5);
+               writel(0, &len->dsi_pkt_len_6_7);
+
+               value = MIPI_DCS_WRITE_MEMORY_START << 8 |
+                       MIPI_DCS_WRITE_MEMORY_CONTINUE;
+               writel(value, &len->dsi_dcs_cmds);
+       }
+
+       /* set SOL delay (for non-burst mode only) */
+       writel(8 * mul / div, &misc->dsi_sol_delay);
+}
+
+static int tegra_dsi_encoder_enable(struct udevice *dev)
+{
+       struct tegra_dsi_priv *priv = dev_get_priv(dev);
+       struct mipi_dsi_device *device = &priv->device;
+       struct display_timing *timing = &priv->timing;
+       struct dsi_misc_reg *misc = &priv->dsi->misc;
+       unsigned int mul, div;
+       unsigned long bclk, plld, period;
+       u32 value;
+       int ret;
+
+       /* Disable interrupt */
+       writel(0, &misc->int_enable);
+
+       tegra_dsi_pad_calibrate(&priv->dsi->pad);
+
+       tegra_dsi_get_muldiv(device->format, &mul, &div);
+
+       /* compute byte clock */
+       bclk = (timing->pixelclock.typ * mul) / (div * device->lanes);
+
+       tegra_dsi_set_timeout(&priv->dsi->timeout, bclk, 60);
+
+       /*
+        * Compute bit clock and round up to the next MHz.
+        */
+       plld = DIV_ROUND_UP(bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
+       period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
+
+       ret = mipi_dphy_timing_get_default(&priv->dphy_timing, period);
+       if (ret < 0) {
+               printf("%s: failed to get D-PHY timing: %d\n", __func__, ret);
+               return ret;
+       }
+
+       ret = mipi_dphy_timing_validate(&priv->dphy_timing, period);
+       if (ret < 0) {
+               printf("%s: failed to validate D-PHY timing: %d\n", __func__, ret);
+               return ret;
+       }
+
+       /*
+        * The D-PHY timing fields are expressed in byte-clock cycles, so
+        * multiply the period by 8.
+        */
+       tegra_dsi_set_phy_timing(&priv->dsi->ptiming,
+                                period * 8, &priv->dphy_timing);
+
+       /* Perform panel HW setup */
+       ret = panel_enable_backlight(priv->panel);
+       if (ret)
+               return ret;
+
+       tegra_dsi_configure(dev, 0);
+
+       ret = panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT);
+       if (ret)
+               return ret;
+
+       tegra_dsi_configure(dev, device->mode_flags);
+
+       tegra_dc_enable_controller(dev);
+
+       /* enable DSI controller */
+       value = readl(&misc->dsi_pwr_ctrl);
+       value |= DSI_POWER_CONTROL_ENABLE;
+       writel(value, &misc->dsi_pwr_ctrl);
+
+       return 0;
+}
+
+static int tegra_dsi_bridge_set_panel(struct udevice *dev, int percent)
+{
+       /* Is not used in tegra dc */
+       return 0;
+}
+
+static int tegra_dsi_panel_timings(struct udevice *dev,
+                                  struct display_timing *timing)
+{
+       struct tegra_dsi_priv *priv = dev_get_priv(dev);
+
+       memcpy(timing, &priv->timing, sizeof(*timing));
+
+       return 0;
+}
+
+static void tegra_dsi_init_clocks(struct udevice *dev)
+{
+       struct tegra_dsi_priv *priv = dev_get_priv(dev);
+       struct mipi_dsi_device *device = &priv->device;
+       unsigned int mul, div;
+       unsigned long bclk, plld;
+
+       tegra_dsi_get_muldiv(device->format, &mul, &div);
+
+       bclk = (priv->timing.pixelclock.typ * mul) /
+                                       (div * device->lanes);
+
+       plld = DIV_ROUND_UP(bclk * 8, USEC_PER_SEC);
+
+       switch (clock_get_osc_freq()) {
+       case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+       case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
+               clock_set_rate(CLOCK_ID_DISPLAY, plld, 12, 0, 8);
+               break;
+
+       case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+               clock_set_rate(CLOCK_ID_DISPLAY, plld, 26, 0, 8);
+               break;
+
+       case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+       case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
+               clock_set_rate(CLOCK_ID_DISPLAY, plld, 13, 0, 8);
+               break;
+
+       case CLOCK_OSC_FREQ_19_2:
+       case CLOCK_OSC_FREQ_38_4:
+       default:
+               /*
+                * These are not supported.
+                */
+               break;
+       }
+
+       priv->dsi_clk = clock_decode_periph_id(dev);
+
+       clock_enable(priv->dsi_clk);
+       udelay(2);
+       reset_set_enable(priv->dsi_clk, 0);
+}
+
+static int tegra_dsi_bridge_probe(struct udevice *dev)
+{
+       struct tegra_dsi_priv *priv = dev_get_priv(dev);
+       struct mipi_dsi_device *device = &priv->device;
+       struct mipi_dsi_panel_plat *mipi_plat;
+       int ret;
+
+       priv->dsi = (struct dsi_ctlr *)dev_read_addr_ptr(dev);
+       if (!priv->dsi) {
+               printf("%s: No display controller address\n", __func__);
+               return -EINVAL;
+       }
+
+       priv->video_fifo_depth = 480;
+       priv->host_fifo_depth = 64;
+
+       ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
+                                          "avdd-dsi-csi-supply", &priv->avdd);
+       if (ret)
+               debug("%s: Cannot get avdd-dsi-csi-supply: error %d\n",
+                     __func__, ret);
+
+       ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev,
+                                          "panel", &priv->panel);
+       if (ret) {
+               printf("%s: Cannot get panel: error %d\n", __func__, ret);
+               return log_ret(ret);
+       }
+
+       panel_get_display_timing(priv->panel, &priv->timing);
+
+       mipi_plat = dev_get_plat(priv->panel);
+       mipi_plat->device = device;
+
+       priv->host.dev = (struct device *)dev;
+       priv->host.ops = &tegra_dsi_bridge_host_ops;
+
+       device->host = &priv->host;
+       device->lanes = mipi_plat->lanes;
+       device->format = mipi_plat->format;
+       device->mode_flags = mipi_plat->mode_flags;
+
+       tegra_dsi_get_format(device->format, &priv->format);
+
+       if (priv->avdd) {
+               ret = regulator_set_enable(priv->avdd, true);
+               if (ret)
+                       return ret;
+       }
+
+       tegra_dsi_init_clocks(dev);
+
+       return 0;
+}
+
+static const struct panel_ops tegra_dsi_bridge_ops = {
+       .enable_backlight       = tegra_dsi_encoder_enable,
+       .set_backlight          = tegra_dsi_bridge_set_panel,
+       .get_display_timing     = tegra_dsi_panel_timings,
+};
+
+static const struct udevice_id tegra_dsi_bridge_ids[] = {
+       { .compatible = "nvidia,tegra30-dsi" },
+       { }
+};
+
+U_BOOT_DRIVER(tegra_dsi) = {
+       .name           = "tegra_dsi",
+       .id             = UCLASS_PANEL,
+       .of_match       = tegra_dsi_bridge_ids,
+       .ops            = &tegra_dsi_bridge_ops,
+       .probe          = tegra_dsi_bridge_probe,
+       .plat_auto      = sizeof(struct tegra_dc_plat),
+       .priv_auto      = sizeof(struct tegra_dsi_priv),
+};

diff --git a/drivers/virtio/virtio-uclass.c b/drivers/virtio/virtio-uclass.c
index de9bc90..31bb21c 100644 (file)
--- a/drivers/virtio/virtio-uclass.c
+++ b/drivers/virtio/virtio-uclass.c
@@ -336,7 +336,7 @@ static int virtio_uclass_child_pre_probe(struct udevice *vdev)
        /* Transport features always preserved to pass to finalize_features */
        for (i = VIRTIO_TRANSPORT_F_START; i < VIRTIO_TRANSPORT_F_END; i++)
                if ((device_features & (1ULL << i)) &&
-                   (i == VIRTIO_F_VERSION_1))
+                   (i == VIRTIO_F_VERSION_1 || i == VIRTIO_F_IOMMU_PLATFORM))
                        __virtio_set_bit(vdev->parent, i);
 
        debug("(%s) final negotiated features supported %016llx\n",
@@ -373,6 +373,12 @@ static int virtio_bootdev_hunt(struct bootdev_hunter *info, bool show)
 {
        int ret;
 
+       if (IS_ENABLED(CONFIG_PCI)) {
+               ret = uclass_probe_all(UCLASS_PCI);
+               if (ret && ret != -ENOENT)
+                       return log_msg_ret("pci", ret);
+       }
+
        ret = uclass_probe_all(UCLASS_VIRTIO);
        if (ret && ret != -ENOENT)
                return log_msg_ret("vir", ret);

diff --git a/drivers/virtio/virtio_pci_modern.c b/drivers/virtio/virtio_pci_modern.c
index cfde400..3cdc2d2 100644 (file)
--- a/drivers/virtio/virtio_pci_modern.c
+++ b/drivers/virtio/virtio_pci_modern.c
@@ -218,25 +218,6 @@ static int virtio_pci_set_status(struct udevice *udev, u8 status)
        return 0;
 }
 
-static int virtio_pci_reset(struct udevice *udev)
-{
-       struct virtio_pci_priv *priv = dev_get_priv(udev);
-
-       /* 0 status means a reset */
-       iowrite8(0, &priv->common->device_status);
-
-       /*
-        * After writing 0 to device_status, the driver MUST wait for a read
-        * of device_status to return 0 before reinitializing the device.
-        * This will flush out the status write, and flush in device writes,
-        * including MSI-X interrupts, if any.
-        */
-       while (ioread8(&priv->common->device_status))
-               udelay(1000);
-
-       return 0;
-}
-
 static int virtio_pci_get_features(struct udevice *udev, u64 *features)
 {
        struct virtio_pci_priv *priv = dev_get_priv(udev);
@@ -363,6 +344,25 @@ static int virtio_pci_find_vqs(struct udevice *udev, unsigned int nvqs,
        return 0;
 }
 
+static int virtio_pci_reset(struct udevice *udev)
+{
+       struct virtio_pci_priv *priv = dev_get_priv(udev);
+
+       /* 0 status means a reset */
+       iowrite8(0, &priv->common->device_status);
+
+       /*
+        * After writing 0 to device_status, the driver MUST wait for a read
+        * of device_status to return 0 before reinitializing the device.
+        * This will flush out the status write, and flush in device writes,
+        * including MSI-X interrupts, if any.
+        */
+       while (ioread8(&priv->common->device_status))
+               udelay(1000);
+
+       return virtio_pci_del_vqs(udev);
+}
+
 static int virtio_pci_notify(struct udevice *udev, struct virtqueue *vq)
 {
        struct virtio_pci_priv *priv = dev_get_priv(udev);

diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c
index f71bab7..c9adcce 100644 (file)
--- a/drivers/virtio/virtio_ring.c
+++ b/drivers/virtio/virtio_ring.c
@@ -6,6 +6,7 @@
  * virtio ring implementation
  */
 
+#include <bouncebuf.h>
 #include <common.h>
 #include <dm.h>
 #include <log.h>
@@ -15,15 +16,63 @@
 #include <virtio_ring.h>
 #include <linux/bug.h>
 #include <linux/compat.h>
+#include <linux/kernel.h>
+
+static void *virtio_alloc_pages(struct udevice *vdev, u32 npages)
+{
+       return memalign(PAGE_SIZE, npages * PAGE_SIZE);
+}
+
+static void virtio_free_pages(struct udevice *vdev, void *ptr, u32 npages)
+{
+       free(ptr);
+}
+
+static int __bb_force_page_align(struct bounce_buffer *state)
+{
+       const ulong align_mask = PAGE_SIZE - 1;
+
+       if ((ulong)state->user_buffer & align_mask)
+               return 0;
+
+       if (state->len != state->len_aligned)
+               return 0;
+
+       return 1;
+}
 
 static unsigned int virtqueue_attach_desc(struct virtqueue *vq, unsigned int i,
                                          struct virtio_sg *sg, u16 flags)
 {
        struct vring_desc_shadow *desc_shadow = &vq->vring_desc_shadow[i];
        struct vring_desc *desc = &vq->vring.desc[i];
+       void *addr;
+
+       if (IS_ENABLED(CONFIG_BOUNCE_BUFFER) && vq->vring.bouncebufs) {
+               struct bounce_buffer *bb = &vq->vring.bouncebufs[i];
+               unsigned int bbflags;
+               int ret;
+
+               if (flags & VRING_DESC_F_WRITE)
+                       bbflags = GEN_BB_WRITE;
+               else
+                       bbflags = GEN_BB_READ;
+
+               ret = bounce_buffer_start_extalign(bb, sg->addr, sg->length,
+                                                  bbflags, PAGE_SIZE,
+                                                  __bb_force_page_align);
+               if (ret) {
+                       debug("%s: failed to allocate bounce buffer (length 0x%zx)\n",
+                             vq->vdev->name, sg->length);
+               }
+
+               addr = bb->bounce_buffer;
+       } else {
+               addr = sg->addr;
+       }
 
        /* Update the shadow descriptor. */
-       desc_shadow->addr = (u64)(uintptr_t)sg->addr;
+       desc_shadow->addr = (u64)(uintptr_t)addr;
        desc_shadow->len = sg->length;
        desc_shadow->flags = flags;
 
@@ -36,6 +85,19 @@ static unsigned int virtqueue_attach_desc(struct virtqueue *vq, unsigned int i,
        return desc_shadow->next;
 }
 
+static void virtqueue_detach_desc(struct virtqueue *vq, unsigned int idx)
+{
+       struct vring_desc *desc = &vq->vring.desc[idx];
+       struct bounce_buffer *bb;
+
+       if (!IS_ENABLED(CONFIG_BOUNCE_BUFFER) || !vq->vring.bouncebufs)
+               return;
+
+       bb = &vq->vring.bouncebufs[idx];
+       bounce_buffer_stop(bb);
+       desc->addr = cpu_to_virtio64(vq->vdev, (u64)(uintptr_t)bb->user_buffer);
+}
+
 int virtqueue_add(struct virtqueue *vq, struct virtio_sg *sgs[],
                  unsigned int out_sgs, unsigned int in_sgs)
 {
@@ -154,10 +216,12 @@ static void detach_buf(struct virtqueue *vq, unsigned int head)
        i = head;
 
        while (vq->vring_desc_shadow[i].flags & VRING_DESC_F_NEXT) {
+               virtqueue_detach_desc(vq, i);
                i = vq->vring_desc_shadow[i].next;
                vq->num_free++;
        }
 
+       virtqueue_detach_desc(vq, i);
        vq->vring_desc_shadow[i].next = vq->free_head;
        vq->free_head = head;
 
@@ -271,8 +335,11 @@ struct virtqueue *vring_create_virtqueue(unsigned int index, unsigned int num,
                                         unsigned int vring_align,
                                         struct udevice *udev)
 {
+       struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
+       struct udevice *vdev = uc_priv->vdev;
        struct virtqueue *vq;
        void *queue = NULL;
+       struct bounce_buffer *bbs = NULL;
        struct vring vring;
 
        /* We assume num is a power of 2 */
@@ -283,7 +350,9 @@ struct virtqueue *vring_create_virtqueue(unsigned int index, unsigned int num,
 
        /* TODO: allocate each queue chunk individually */
        for (; num && vring_size(num, vring_align) > PAGE_SIZE; num /= 2) {
-               queue = memalign(PAGE_SIZE, vring_size(num, vring_align));
+               size_t sz = vring_size(num, vring_align);
+
+               queue = virtio_alloc_pages(vdev, DIV_ROUND_UP(sz, PAGE_SIZE));
                if (queue)
                        break;
        }
@@ -293,30 +362,44 @@ struct virtqueue *vring_create_virtqueue(unsigned int index, unsigned int num,
 
        if (!queue) {
                /* Try to get a single page. You are my only hope! */
-               queue = memalign(PAGE_SIZE, vring_size(num, vring_align));
+               queue = virtio_alloc_pages(vdev, 1);
        }
        if (!queue)
                return NULL;
 
        memset(queue, 0, vring_size(num, vring_align));
-       vring_init(&vring, num, queue, vring_align);
 
-       vq = __vring_new_virtqueue(index, vring, udev);
-       if (!vq) {
-               free(queue);
-               return NULL;
+       if (virtio_has_feature(vdev, VIRTIO_F_IOMMU_PLATFORM)) {
+               bbs = calloc(num, sizeof(*bbs));
+               if (!bbs)
+                       goto err_free_queue;
        }
+
+       vring_init(&vring, num, queue, vring_align, bbs);
+
+       vq = __vring_new_virtqueue(index, vring, udev);
+       if (!vq)
+               goto err_free_bbs;
+
        debug("(%s): created vring @ %p for vq @ %p with num %u\n", udev->name,
              queue, vq, num);
 
        return vq;
+
+err_free_bbs:
+       free(bbs);
+err_free_queue:
+       virtio_free_pages(vdev, queue, DIV_ROUND_UP(vring.size, PAGE_SIZE));
+       return NULL;
 }
 
 void vring_del_virtqueue(struct virtqueue *vq)
 {
-       free(vq->vring.desc);
+       virtio_free_pages(vq->vdev, vq->vring.desc,
+                         DIV_ROUND_UP(vq->vring.size, PAGE_SIZE));
        free(vq->vring_desc_shadow);
        list_del(&vq->list);
+       free(vq->vring.bouncebufs);
        free(vq);
 }
 

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index f776759..6466635 100644 (file)
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -31,6 +31,7 @@ config WATCHDOG_TIMEOUT_MSECS
        default 30000 if ARCH_SOCFPGA
        default 16000 if ARCH_SUNXI
        default 5376 if ULP_WATCHDOG
+       default 15000 if ARCH_BCM283X
        default 60000
        help
          Watchdog timeout in msec
@@ -343,6 +344,14 @@ config WDT_SUNXI
        help
          Enable support for the watchdog timer in Allwinner sunxi SoCs.
 
+config WDT_BCM2835
+       bool "Broadcom 2835 watchdog timer support"
+       depends on WDT && ARCH_BCM283X
+       default y
+       help
+         Enable support for the watchdog timer in Broadcom 283X SoCs such
+         as Raspberry Pi boards.
+
 config XILINX_TB_WATCHDOG
        bool "Xilinx Axi watchdog timer support"
        depends on WDT
@@ -368,6 +377,14 @@ config WDT_TANGIER
          Intel Tangier SoC. If you're using a board with Intel Tangier
          SoC, say Y here.
 
+config WDT_ARM_SMC
+       bool "ARM SMC watchdog timer support"
+       depends on WDT && ARM_SMCCC
+       imply WATCHDOG
+       help
+         Select this to enable Arm SMC watchdog timer. This watchdog will manage
+         a watchdog based on ARM SMCCC communication.
+
 config SPL_WDT
        bool "Enable driver model for watchdog timer drivers in SPL"
        depends on SPL_DM
@@ -375,4 +392,11 @@ config SPL_WDT
          Enable driver model for watchdog timer in SPL.
          This is similar to CONFIG_WDT in U-Boot.
 
+config WDT_FTWDT010
+       bool "Faraday Technology ftwdt010 watchdog timer support"
+       depends on WDT
+       imply WATCHDOG
+       help
+         Faraday Technology ftwdt010 watchdog is an architecture independent
+         watchdog. It is usually used in SoC chip design.
 endmenu

diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index aba1df2..fd5d9c7 100644 (file)
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -18,14 +18,17 @@ obj-$(CONFIG_$(SPL_TPL_)WDT) += wdt-uclass.o
 obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o
 obj-$(CONFIG_WDT_ALARM_SANDBOX) += sandbox_alarm-wdt.o
 obj-$(CONFIG_WDT_APPLE) += apple_wdt.o
+obj-$(CONFIG_WDT_ARM_SMC) += arm_smc_wdt.o
 obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
 obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
 obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o
+obj-$(CONFIG_WDT_BCM2835) += bcm2835_wdt.o
 obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
 obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o
 obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o
 obj-$(CONFIG_WDT_ORION) += orion_wdt.o
 obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
+obj-$(CONFIG_WDT_FTWDT010) += ftwdt010_wdt.o
 obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o
 obj-$(CONFIG_WDT_MAX6370) += max6370_wdt.o
 obj-$(CONFIG_WDT_MESON_GXBB) += meson_gxbb_wdt.o

diff --git a/drivers/watchdog/arm_smc_wdt.c b/drivers/watchdog/arm_smc_wdt.c
new file mode 100644 (file)
index 0000000..0ea4444
--- /dev/null
+++ b/drivers/watchdog/arm_smc_wdt.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * ARM Secure Monitor Call watchdog driver
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ * This file is based on Linux driver drivers/watchdog/arm_smc_wdt.c
+ */
+
+#define LOG_CATEGORY UCLASS_WDT
+
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <linux/arm-smccc.h>
+#include <linux/psci.h>
+#include <wdt.h>
+
+#define DRV_NAME               "arm_smc_wdt"
+
+#define WDT_TIMEOUT_SECS(TIMEOUT)      ((TIMEOUT) / 1000)
+
+enum smcwd_call {
+       SMCWD_INIT              = 0,
+       SMCWD_SET_TIMEOUT       = 1,
+       SMCWD_ENABLE            = 2,
+       SMCWD_PET               = 3,
+       SMCWD_GET_TIMELEFT      = 4,
+};
+
+struct smcwd_priv_data {
+       u32 smc_id;
+       unsigned int min_timeout;
+       unsigned int max_timeout;
+};
+
+static int smcwd_call(struct udevice *dev, enum smcwd_call call,
+                     unsigned long arg, struct arm_smccc_res *res)
+{
+       struct smcwd_priv_data *priv = dev_get_priv(dev);
+       struct arm_smccc_res local_res;
+
+       if (!res)
+               res = &local_res;
+
+       arm_smccc_smc(priv->smc_id, call, arg, 0, 0, 0, 0, 0, res);
+
+       if (res->a0 == PSCI_RET_NOT_SUPPORTED)
+               return -ENODEV;
+       if (res->a0 == PSCI_RET_INVALID_PARAMS)
+               return -EINVAL;
+       if (res->a0 != PSCI_RET_SUCCESS)
+               return -EIO;
+
+       return 0;
+}
+
+static int smcwd_reset(struct udevice *dev)
+{
+       return smcwd_call(dev, SMCWD_PET, 0, NULL);
+}
+
+static int smcwd_stop(struct udevice *dev)
+{
+       return smcwd_call(dev, SMCWD_ENABLE, 0, NULL);
+}
+
+static int smcwd_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+       struct smcwd_priv_data *priv = dev_get_priv(dev);
+       u64 timeout_sec = WDT_TIMEOUT_SECS(timeout_ms);
+       int err;
+
+       if (timeout_sec < priv->min_timeout || timeout_sec > priv->max_timeout) {
+               dev_err(dev, "Timeout value not supported\n");
+               return -EINVAL;
+       }
+
+       err = smcwd_call(dev, SMCWD_SET_TIMEOUT, timeout_sec, NULL);
+       if (err) {
+               dev_err(dev, "Timeout out configuration failed\n");
+               return err;
+       }
+
+       return smcwd_call(dev, SMCWD_ENABLE, 1, NULL);
+}
+
+static int smcwd_probe(struct udevice *dev)
+{
+       struct smcwd_priv_data *priv = dev_get_priv(dev);
+       struct arm_smccc_res res;
+       int err;
+
+       priv->smc_id = dev_read_u32_default(dev, "arm,smc-id", 0x82003D06);
+
+       err = smcwd_call(dev, SMCWD_INIT, 0, &res);
+       if (err < 0) {
+               dev_err(dev, "Init failed %i\n", err);
+               return err;
+       }
+
+       priv->min_timeout = res.a1;
+       priv->max_timeout = res.a2;
+
+       return 0;
+}
+
+static const struct wdt_ops smcwd_ops = {
+       .start          = smcwd_start,
+       .stop           = smcwd_stop,
+       .reset          = smcwd_reset,
+};
+
+static const struct udevice_id smcwd_dt_ids[] = {
+       { .compatible = "arm,smc-wdt" },
+       {}
+};
+
+U_BOOT_DRIVER(wdt_sandbox) = {
+       .name = "smcwd",
+       .id = UCLASS_WDT,
+       .of_match = smcwd_dt_ids,
+       .priv_auto = sizeof(struct smcwd_priv_data),
+       .probe = smcwd_probe,
+       .ops = &smcwd_ops,
+};

diff --git a/drivers/watchdog/bcm2835_wdt.c b/drivers/watchdog/bcm2835_wdt.c
new file mode 100644 (file)
index 0000000..3c1ead3
--- /dev/null
+++ b/drivers/watchdog/bcm2835_wdt.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 Lubomir Rintel <lkundrak@v3.sk>
+ * Copyright (C) 2023 Etienne Dublé (CNRS) <etienne.duble@imag.fr>
+ *
+ * This code is mostly derived from the linux driver.
+ */
+
+#include <dm.h>
+#include <wdt.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+#define PM_RSTC                                        0x1c
+#define PM_WDOG                                        0x24
+
+#define PM_PASSWORD                            0x5a000000
+
+/* The hardware supports a maximum timeout value of 0xfffff ticks
+ * (just below 16 seconds).
+ */
+#define PM_WDOG_MAX_TICKS                      0x000fffff
+#define PM_RSTC_WRCFG_CLR                      0xffffffcf
+#define PM_RSTC_WRCFG_FULL_RESET               0x00000020
+#define PM_RSTC_RESET                          0x00000102
+
+#define MS_TO_WDOG_TICKS(x) (((x) << 16) / 1000)
+
+struct bcm2835_wdt_priv {
+       void __iomem *base;
+       u64 timeout_ticks;
+};
+
+static int bcm2835_wdt_start_ticks(struct udevice *dev,
+                                  u64 timeout_ticks, ulong flags)
+{
+       struct bcm2835_wdt_priv *priv = dev_get_priv(dev);
+       void __iomem *base = priv->base;
+       u32 cur;
+
+       writel(PM_PASSWORD | timeout_ticks, base + PM_WDOG);
+       cur = readl(base + PM_RSTC);
+       writel(PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET,
+              base + PM_RSTC);
+
+       return 0;
+}
+
+static int bcm2835_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+       struct bcm2835_wdt_priv *priv = dev_get_priv(dev);
+
+       priv->timeout_ticks = MS_TO_WDOG_TICKS(timeout_ms);
+
+       if (priv->timeout_ticks > PM_WDOG_MAX_TICKS) {
+               printf("bcm2835_wdt: the timeout value is too high, using ~16s instead.\n");
+               priv->timeout_ticks = PM_WDOG_MAX_TICKS;
+       }
+
+       return bcm2835_wdt_start_ticks(dev, priv->timeout_ticks, flags);
+}
+
+static int bcm2835_wdt_reset(struct udevice *dev)
+{
+       struct bcm2835_wdt_priv *priv = dev_get_priv(dev);
+
+       /* restart the timer with the value of priv->timeout_ticks
+        * saved from the last bcm2835_wdt_start() call.
+        */
+       return bcm2835_wdt_start_ticks(dev, priv->timeout_ticks, 0);
+}
+
+static int bcm2835_wdt_stop(struct udevice *dev)
+{
+       struct bcm2835_wdt_priv *priv = dev_get_priv(dev);
+       void __iomem *base = priv->base;
+
+       writel(PM_PASSWORD | PM_RSTC_RESET, base + PM_RSTC);
+
+       return 0;
+}
+
+static int bcm2835_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+       int ret;
+
+       /* use a timeout of 10 ticks (~150us) */
+       ret = bcm2835_wdt_start_ticks(dev, 10, flags);
+       if (ret)
+               return ret;
+
+       mdelay(500);
+
+       return 0;
+}
+
+static const struct wdt_ops bcm2835_wdt_ops = {
+       .reset          = bcm2835_wdt_reset,
+       .start          = bcm2835_wdt_start,
+       .stop           = bcm2835_wdt_stop,
+       .expire_now     = bcm2835_wdt_expire_now,
+};
+
+static const struct udevice_id bcm2835_wdt_ids[] = {
+       { .compatible = "brcm,bcm2835-pm" },
+       { .compatible = "brcm,bcm2835-pm-wdt" },
+       { /* sentinel */ }
+};
+
+static int bcm2835_wdt_probe(struct udevice *dev)
+{
+       struct bcm2835_wdt_priv *priv = dev_get_priv(dev);
+
+       priv->base = dev_remap_addr(dev);
+       if (!priv->base)
+               return -EINVAL;
+
+       priv->timeout_ticks = PM_WDOG_MAX_TICKS;
+
+       bcm2835_wdt_stop(dev);
+
+       return 0;
+}
+
+U_BOOT_DRIVER(bcm2835_wdt) = {
+       .name           = "bcm2835_wdt",
+       .id             = UCLASS_WDT,
+       .of_match       = bcm2835_wdt_ids,
+       .probe          = bcm2835_wdt_probe,
+       .priv_auto      = sizeof(struct bcm2835_wdt_priv),
+       .ops            = &bcm2835_wdt_ops,
+};

diff --git a/drivers/watchdog/ftwdt010_wdt.c b/drivers/watchdog/ftwdt010_wdt.c
new file mode 100644 (file)
index 0000000..a6b33b1
--- /dev/null
+++ b/drivers/watchdog/ftwdt010_wdt.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Watchdog driver for the FTWDT010 Watch Dog Driver
+ *
+ * (c) Copyright 2004 Faraday Technology Corp. (www.faraday-tech.com)
+ * Based on sa1100_wdt.c by Oleg Drokin <green@crimea.edu>
+ * Based on SoftDog driver by Alan Cox <alan@redhat.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * 27/11/2004 Initial release, Faraday.
+ * 12/01/2011 Port to u-boot, Macpaul Lin.
+ * 22/08/2022 Port to DM
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <wdt.h>
+#include <log.h>
+#include <asm/io.h>
+#include <faraday/ftwdt010_wdt.h>
+
+struct ftwdt010_wdt_priv {
+       struct ftwdt010_wdt __iomem *regs;
+};
+
+/*
+ * Set the watchdog time interval.
+ * Counter is 32 bit.
+ */
+static int ftwdt010_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+       struct ftwdt010_wdt_priv *priv = dev_get_priv(dev);
+       struct ftwdt010_wdt *wd = priv->regs;
+       unsigned int reg;
+
+       debug("Activating WDT %llu ms\n", timeout_ms);
+
+       /* Check if disabled */
+       if (readl(&wd->wdcr) & ~FTWDT010_WDCR_ENABLE) {
+               printf("sorry, watchdog is disabled\n");
+               return -1;
+       }
+
+       /*
+        * In a 66MHz system,
+        * if you set WDLOAD as 0x03EF1480 (66000000)
+        * the reset timer is 1 second.
+        */
+       reg = FTWDT010_WDLOAD(timeout_ms * FTWDT010_TIMEOUT_FACTOR);
+
+       writel(reg, &wd->wdload);
+
+       return 0;
+}
+
+static int ftwdt010_wdt_reset(struct udevice *dev)
+{
+       struct ftwdt010_wdt_priv *priv = dev_get_priv(dev);
+       struct ftwdt010_wdt *wd = priv->regs;
+
+       /* clear control register */
+       writel(0, &wd->wdcr);
+
+       /* Write Magic number */
+       writel(FTWDT010_WDRESTART_MAGIC, &wd->wdrestart);
+
+       /* Enable WDT */
+       writel((FTWDT010_WDCR_RST | FTWDT010_WDCR_ENABLE), &wd->wdcr);
+
+       return 0;
+}
+
+static int ftwdt010_wdt_stop(struct udevice *dev)
+{
+       struct ftwdt010_wdt_priv *priv = dev_get_priv(dev);
+       struct ftwdt010_wdt *wd = priv->regs;
+
+       debug("Deactivating WDT..\n");
+
+       /*
+        * It was defined with CONFIG_WATCHDOG_NOWAYOUT in Linux
+        *
+        * Shut off the timer.
+        * Lock it in if it's a module and we defined ...NOWAYOUT
+        */
+       writel(0, &wd->wdcr);
+       return 0;
+}
+
+static int ftwdt010_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+       struct ftwdt010_wdt_priv *priv = dev_get_priv(dev);
+       struct ftwdt010_wdt *wd = priv->regs;
+
+       debug("Expiring WDT..\n");
+       writel(FTWDT010_WDLOAD(0), &wd->wdload);
+       return ftwdt010_wdt_reset(dev);
+}
+
+static int ftwdt010_wdt_probe(struct udevice *dev)
+{
+       struct ftwdt010_wdt_priv *priv = dev_get_priv(dev);
+
+       priv->regs = dev_read_addr_ptr(dev);
+       if (!priv->regs)
+               return -EINVAL;
+
+       return 0;
+}
+
+static const struct wdt_ops ftwdt010_wdt_ops = {
+       .start = ftwdt010_wdt_start,
+       .reset = ftwdt010_wdt_reset,
+       .stop = ftwdt010_wdt_stop,
+       .expire_now = ftwdt010_wdt_expire_now,
+};
+
+static const struct udevice_id ftwdt010_wdt_ids[] = {
+       { .compatible = "faraday,ftwdt010" },
+       {}
+};
+
+U_BOOT_DRIVER(ftwdt010_wdt) = {
+       .name = "ftwdt010_wdt",
+       .id = UCLASS_WDT,
+       .of_match = ftwdt010_wdt_ids,
+       .ops = &ftwdt010_wdt_ops,
+       .probe = ftwdt010_wdt_probe,
+       .priv_auto = sizeof(struct ftwdt010_wdt_priv),
+};

diff --git a/drivers/xen/Kconfig b/drivers/xen/Kconfig
index 0ee74d0..6cb9149 100644 (file)
--- a/drivers/xen/Kconfig
+++ b/drivers/xen/Kconfig
@@ -1,6 +1,6 @@
 config PVBLOCK
        bool "Xen para-virtualized block device"
-       depends on DM
+       depends on DM && XEN
        select BLK
        help
          This driver implements the front-end of the Xen virtual

diff --git a/drivers/xen/hypervisor.c b/drivers/xen/hypervisor.c
index 16c7c96..0b2311b 100644 (file)
--- a/drivers/xen/hypervisor.c
+++ b/drivers/xen/hypervisor.c
@@ -264,8 +264,15 @@ void clear_evtchn(uint32_t port)
 
 int xen_init(void)
 {
+       int el = current_el();
+
        debug("%s\n", __func__);
 
+       if (el != 1) {
+               puts("XEN:\tnot running from EL1\n");
+               return 0;
+       }
+
        map_shared_info(NULL);
        init_events();
        init_xenbus();

diff --git a/fs/yaffs2/yaffsfs.c b/fs/yaffs2/yaffsfs.c
index 510faae..d615f02 100644 (file)
--- a/fs/yaffs2/yaffsfs.c
+++ b/fs/yaffs2/yaffsfs.c
@@ -468,7 +468,7 @@ static int yaffsfs_alt_dir_path(const YCHAR *path, YCHAR **ret_path)
        return 0;
 }
 
-LIST_HEAD(yaffsfs_deviceList);
+static LIST_HEAD(yaffsfs_deviceList);
 
 /*
  * yaffsfs_FindDevice

diff --git a/include/android_image.h b/include/android_image.h
index 54d25af..d503c98 100644 (file)
--- a/include/android_image.h
+++ b/include/android_image.h
@@ -3,7 +3,7 @@
  * This is from the Android Project,
  * Repository: https://android.googlesource.com/platform/system/tools/mkbootimg
  * File: include/bootimg/bootimg.h
- * Commit: e55998a0f2b61b685d5eb4a486ca3a0c680b1a2f
+ * Commit: cce5b1923e3cd2fcb765b512610bdc5c42bc501d
  *
  * Copyright (C) 2007 The Android Open Source Project
  */
@@ -14,15 +14,70 @@
 #include <linux/compiler.h>
 #include <linux/types.h>
 
+#define ANDR_GKI_PAGE_SIZE 4096
 #define ANDR_BOOT_MAGIC "ANDROID!"
 #define ANDR_BOOT_MAGIC_SIZE 8
 #define ANDR_BOOT_NAME_SIZE 16
 #define ANDR_BOOT_ARGS_SIZE 512
 #define ANDR_BOOT_EXTRA_ARGS_SIZE 1024
+#define VENDOR_BOOT_MAGIC "VNDRBOOT"
+#define ANDR_VENDOR_BOOT_MAGIC_SIZE 8
+#define ANDR_VENDOR_BOOT_ARGS_SIZE 2048
+#define ANDR_VENDOR_BOOT_NAME_SIZE 16
 
-/* The bootloader expects the structure of andr_img_hdr with header
+#define BOOTCONFIG_MAGIC "#BOOTCONFIG\n"
+#define BOOTCONFIG_MAGIC_SIZE 12
+#define BOOTCONFIG_SIZE_SIZE 4
+#define BOOTCONFIG_CHECKSUM_SIZE 4
+#define BOOTCONFIG_TRAILER_SIZE BOOTCONFIG_MAGIC_SIZE + \
+                               BOOTCONFIG_SIZE_SIZE + \
+                               BOOTCONFIG_CHECKSUM_SIZE
+
+struct andr_boot_img_hdr_v3 {
+       u8 magic[ANDR_BOOT_MAGIC_SIZE];
+
+       u32 kernel_size;    /* size in bytes */
+       u32 ramdisk_size;   /* size in bytes */
+
+       u32 os_version;
+
+       u32 header_size;    /* size of boot image header in bytes */
+       u32 reserved[4];
+       u32 header_version; /* offset remains constant for version check */
+
+       u8 cmdline[ANDR_BOOT_ARGS_SIZE + ANDR_BOOT_EXTRA_ARGS_SIZE];
+       /* for boot image header v4 only */
+       u32 signature_size; /* size in bytes */
+};
+
+struct andr_vnd_boot_img_hdr {
+       u8 magic[ANDR_VENDOR_BOOT_MAGIC_SIZE];
+       u32 header_version;
+       u32 page_size;           /* flash page size we assume */
+
+       u32 kernel_addr;         /* physical load addr */
+       u32 ramdisk_addr;        /* physical load addr */
+
+       u32 vendor_ramdisk_size; /* size in bytes */
+
+       u8 cmdline[ANDR_VENDOR_BOOT_ARGS_SIZE];
+
+       u32 tags_addr;           /* physical addr for kernel tags */
+
+       u8 name[ANDR_VENDOR_BOOT_NAME_SIZE]; /* asciiz product name */
+       u32 header_size;         /* size of vendor boot image header in bytes */
+       u32 dtb_size;            /* size of dtb image */
+       u64 dtb_addr;            /* physical load address */
+       /* for boot image header v4 only */
+       u32 vendor_ramdisk_table_size; /* size in bytes for the vendor ramdisk table */
+       u32 vendor_ramdisk_table_entry_num; /* number of entries in the vendor ramdisk table */
+       u32 vendor_ramdisk_table_entry_size; /* size in bytes for a vendor ramdisk table entry */
+       u32 bootconfig_size; /* size in bytes for the bootconfig section */
+};
+
+/* The bootloader expects the structure of andr_boot_img_hdr_v0 with header
  * version 0 to be as follows: */
-struct andr_img_hdr {
+struct andr_boot_img_hdr_v0 {
     /* Must be ANDR_BOOT_MAGIC. */
     char magic[ANDR_BOOT_MAGIC_SIZE];
 
@@ -136,4 +191,171 @@ struct andr_img_hdr {
  *    else: jump to kernel_addr
  */
 
+/* When the boot image header has a version of 3, the structure of the boot
+ * image is as follows:
+ *
+ * +---------------------+
+ * | boot header         | 4096 bytes
+ * +---------------------+
+ * | kernel              | m pages
+ * +---------------------+
+ * | ramdisk             | n pages
+ * +---------------------+
+ *
+ * m = (kernel_size + 4096 - 1) / 4096
+ * n = (ramdisk_size + 4096 - 1) / 4096
+ *
+ * Note that in version 3 of the boot image header, page size is fixed at 4096 bytes.
+ *
+ * The structure of the vendor boot image (introduced with version 3 and
+ * required to be present when a v3 boot image is used) is as follows:
+ *
+ * +---------------------+
+ * | vendor boot header  | o pages
+ * +---------------------+
+ * | vendor ramdisk      | p pages
+ * +---------------------+
+ * | dtb                 | q pages
+ * +---------------------+
+ * o = (2112 + page_size - 1) / page_size
+ * p = (vendor_ramdisk_size + page_size - 1) / page_size
+ * q = (dtb_size + page_size - 1) / page_size
+ *
+ * 0. all entities in the boot image are 4096-byte aligned in flash, all
+ *    entities in the vendor boot image are page_size (determined by the vendor
+ *    and specified in the vendor boot image header) aligned in flash
+ * 1. kernel, ramdisk, vendor ramdisk, and DTB are required (size != 0)
+ * 2. load the kernel and DTB at the specified physical address (kernel_addr,
+ *    dtb_addr)
+ * 3. load the vendor ramdisk at ramdisk_addr
+ * 4. load the generic ramdisk immediately following the vendor ramdisk in
+ *    memory
+ * 5. set up registers for kernel entry as required by your architecture
+ * 6. if the platform has a second stage bootloader jump to it (must be
+ *    contained outside boot and vendor boot partitions), otherwise
+ *    jump to kernel_addr
+ */
+
+/* When the boot image header has a version of 4, the structure of the boot
+ * image is as follows:
+ *
+ * +---------------------+
+ * | boot header         | 4096 bytes
+ * +---------------------+
+ * | kernel              | m pages
+ * +---------------------+
+ * | ramdisk             | n pages
+ * +---------------------+
+ * | boot signature      | g pages
+ * +---------------------+
+ *
+ * m = (kernel_size + 4096 - 1) / 4096
+ * n = (ramdisk_size + 4096 - 1) / 4096
+ * g = (signature_size + 4096 - 1) / 4096
+ *
+ * Note that in version 4 of the boot image header, page size is fixed at 4096
+ * bytes.
+ *
+ * The structure of the vendor boot image version 4, which is required to be
+ * present when a version 4 boot image is used, is as follows:
+ *
+ * +------------------------+
+ * | vendor boot header     | o pages
+ * +------------------------+
+ * | vendor ramdisk section | p pages
+ * +------------------------+
+ * | dtb                    | q pages
+ * +------------------------+
+ * | vendor ramdisk table   | r pages
+ * +------------------------+
+ * | bootconfig             | s pages
+ * +------------------------+
+ *
+ * o = (2128 + page_size - 1) / page_size
+ * p = (vendor_ramdisk_size + page_size - 1) / page_size
+ * q = (dtb_size + page_size - 1) / page_size
+ * r = (vendor_ramdisk_table_size + page_size - 1) / page_size
+ * s = (vendor_bootconfig_size + page_size - 1) / page_size
+ *
+ * Note that in version 4 of the vendor boot image, multiple vendor ramdisks can
+ * be included in the vendor boot image. The bootloader can select a subset of
+ * ramdisks to load at runtime. To help the bootloader select the ramdisks, each
+ * ramdisk is tagged with a type tag and a set of hardware identifiers
+ * describing the board, soc or platform that this ramdisk is intended for.
+ *
+ * The vendor ramdisk section is consist of multiple ramdisk images concatenated
+ * one after another, and vendor_ramdisk_size is the size of the section, which
+ * is the total size of all the ramdisks included in the vendor boot image.
+ *
+ * The vendor ramdisk table holds the size, offset, type, name and hardware
+ * identifiers of each ramdisk. The type field denotes the type of its content.
+ * The vendor ramdisk names are unique. The hardware identifiers are specified
+ * in the board_id field in each table entry. The board_id field is consist of a
+ * vector of unsigned integer words, and the encoding scheme is defined by the
+ * hardware vendor.
+ *
+ * For the different type of ramdisks, there are:
+ *    - VENDOR_RAMDISK_TYPE_NONE indicates the value is unspecified.
+ *    - VENDOR_RAMDISK_TYPE_PLATFORM ramdisks contain platform specific bits, so
+ *      the bootloader should always load these into memory.
+ *    - VENDOR_RAMDISK_TYPE_RECOVERY ramdisks contain recovery resources, so
+ *      the bootloader should load these when booting into recovery.
+ *    - VENDOR_RAMDISK_TYPE_DLKM ramdisks contain dynamic loadable kernel
+ *      modules.
+ *
+ * Version 4 of the vendor boot image also adds a bootconfig section to the end
+ * of the image. This section contains Boot Configuration parameters known at
+ * build time. The bootloader is responsible for placing this section directly
+ * after the generic ramdisk, followed by the bootconfig trailer, before
+ * entering the kernel.
+ *
+ * 0. all entities in the boot image are 4096-byte aligned in flash, all
+ *    entities in the vendor boot image are page_size (determined by the vendor
+ *    and specified in the vendor boot image header) aligned in flash
+ * 1. kernel, ramdisk, and DTB are required (size != 0)
+ * 2. load the kernel and DTB at the specified physical address (kernel_addr,
+ *    dtb_addr)
+ * 3. load the vendor ramdisks at ramdisk_addr
+ * 4. load the generic ramdisk immediately following the vendor ramdisk in
+ *    memory
+ * 5. load the bootconfig immediately following the generic ramdisk. Add
+ *    additional bootconfig parameters followed by the bootconfig trailer.
+ * 6. set up registers for kernel entry as required by your architecture
+ * 7. if the platform has a second stage bootloader jump to it (must be
+ *    contained outside boot and vendor boot partitions), otherwise
+ *    jump to kernel_addr
+ */
+
+/* Private struct */
+struct andr_image_data {
+       ulong kernel_ptr;  /* kernel address */
+       u32 kernel_size;  /* size in bytes */
+       u32 ramdisk_size;  /* size in bytes */
+       ulong vendor_ramdisk_ptr;  /* vendor ramdisk address */
+       u32 vendor_ramdisk_size;  /* vendor ramdisk size*/
+       u32 boot_ramdisk_size;  /* size in bytes */
+       ulong second_ptr;  /* secondary bootloader address */
+       u32 second_size;  /* secondary bootloader size */
+       ulong dtb_ptr;  /* address of dtb image */
+       u32 dtb_size;  /* size of dtb image */
+       ulong recovery_dtbo_ptr;  /* size in bytes for recovery DTBO/ACPIO image */
+       u32 recovery_dtbo_size;  /* offset to recovery dtbo/acpio in boot image */
+
+       const char *kcmdline;  /* boot kernel cmdline */
+       const char *kcmdline_extra;  /* vendor-boot extra kernel cmdline */
+       const char *image_name;  /* asciiz product name */
+
+       ulong bootconfig_addr;  /* bootconfig image address */
+       ulong bootconfig_size;  /* bootconfig image size */
+
+       u32 kernel_addr;  /* physical load addr */
+       ulong ramdisk_addr;  /* physical load addr */
+       ulong ramdisk_ptr;  /* ramdisk address */
+       ulong dtb_load_addr;  /* physical load address for DTB image */
+       ulong tags_addr;  /* physical addr for kernel tags */
+       u32 header_version;  /* version of the boot image header */
+       u32 boot_img_total_size;  /* boot image size */
+       u32 vendor_boot_img_total_size;  /* vendor boot image size */
+};
+
 #endif

diff --git a/include/binman_sym.h b/include/binman_sym.h
index 528d7e4..49a95ea 100644 (file)
--- a/include/binman_sym.h
+++ b/include/binman_sym.h
@@ -71,7 +71,7 @@
  * value #defined above. This is used to check at runtime if the
  * symbol values were filled in and are OK to use.
  */
-extern ulong _binman_sym_magic;
+extern unsigned long _binman_sym_magic;
 
 /**
  * DECLARE_BINMAN_MAGIC_SYM - Declare the internal magic symbol
@@ -81,7 +81,7 @@ extern ulong _binman_sym_magic;
  * definitions of the symbol.
  */
 #define DECLARE_BINMAN_MAGIC_SYM \
-       ulong _binman_sym_magic \
+       unsigned long _binman_sym_magic \
                __attribute__((aligned(4), section(".binman_sym")))
 
 /**
@@ -93,14 +93,14 @@ extern ulong _binman_sym_magic;
  * Return: 1 if binman symbol values are usable, 0 if not
  */
 #define BINMAN_SYMS_OK \
-       (*(ulong *)&_binman_sym_magic == BINMAN_SYM_MAGIC_VALUE)
+       (*(unsigned long *)&_binman_sym_magic == BINMAN_SYM_MAGIC_VALUE)
 
 /**
  * binman_sym() - Access a previously declared symbol
  *
  * This is used to get the value of a symbol. E.g.:
  *
- *    ulong address = binman_sym(ulong, u_boot_spl, pos);
+ *    unsigned long address = binman_sym(unsigned long, u_boot_spl, pos);
  *
  * @_type: Type f the symbol (e.g. unsigned long)
  * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl')

diff --git a/include/blk.h b/include/blk.h
index 1db203c..2c9c798 100644 (file)
--- a/include/blk.h
+++ b/include/blk.h
@@ -62,10 +62,9 @@ struct blk_desc {
        unsigned char   hwpart;         /* HW partition, e.g. for eMMC */
        unsigned char   type;           /* device type */
        unsigned char   removable;      /* removable device */
-#ifdef CONFIG_LBA48
        /* device can use 48bit addr (ATA/ATAPI v7) */
-       unsigned char   lba48;
-#endif
+       bool    lba48;
+       unsigned char   atapi;          /* Use ATAPI protocol */
        lbaint_t        lba;            /* number of blocks */
        unsigned long   blksz;          /* block size */
        int             log2blksz;      /* for convenience: log2(blksz) */

diff --git a/include/blkmap.h b/include/blkmap.h
new file mode 100644 (file)
index 0000000..af54583
--- /dev/null
+++ b/include/blkmap.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 Addiva Elektronik
+ * Author: Tobias Waldekranz <tobias@waldekranz.com>
+ */
+
+#ifndef _BLKMAP_H
+#define _BLKMAP_H
+
+/**
+ * blkmap_map_linear() - Map region of other block device
+ *
+ * @dev: Blkmap to create the mapping on
+ * @blknr: Start block number of the mapping
+ * @blkcnt: Number of blocks to map
+ * @lblk: The target block device of the mapping
+ * @lblknr: The start block number of the target device
+ * Returns: 0 on success, negative error code on failure
+ */
+int blkmap_map_linear(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+                     struct udevice *lblk, lbaint_t lblknr);
+
+/**
+ * blkmap_map_mem() - Map region of memory
+ *
+ * @dev: Blkmap to create the mapping on
+ * @blknr: Start block number of the mapping
+ * @blkcnt: Number of blocks to map
+ * @addr: The target memory address of the mapping
+ * Returns: 0 on success, negative error code on failure
+ */
+int blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+                  void *addr);
+
+/**
+ * blkmap_map_pmem() - Map region of physical memory
+ *
+ * Ensures that a valid physical to virtual memory mapping for the
+ * requested region is valid for the lifetime of the mapping, on
+ * architectures that require it (sandbox).
+ *
+ * @dev: Blkmap to create the mapping on
+ * @blknr: Start block number of the mapping
+ * @blkcnt: Number of blocks to map
+ * @paddr: The target physical memory address of the mapping
+ * Returns: 0 on success, negative error code on failure
+ */
+int blkmap_map_pmem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+                   phys_addr_t paddr);
+
+
+/**
+ * blkmap_from_label() - Find blkmap from label
+ *
+ * @label: Label of the requested blkmap
+ * Returns: A pointer to the blkmap on success, NULL on failure
+ */
+struct udevice *blkmap_from_label(const char *label);
+
+/**
+ * blkmap_create() - Create new blkmap
+ *
+ * @label: Label of the new blkmap
+ * @devp: If not NULL, updated with the address of the resulting device
+ * Returns: 0 on success, negative error code on failure
+ */
+int blkmap_create(const char *label, struct udevice **devp);
+
+/**
+ * blkmap_destroy() - Destroy blkmap
+ *
+ * @dev: The blkmap to be destroyed
+ * Returns: 0 on success, negative error code on failure
+ */
+int blkmap_destroy(struct udevice *dev);
+
+#endif /* _BLKMAP_H */

diff --git a/include/bootdev.h b/include/bootdev.h
index b92ff4d..e72ef36 100644 (file)
--- a/include/bootdev.h
+++ b/include/bootdev.h
@@ -258,7 +258,7 @@ int bootdev_find_by_label(const char *label, struct udevice **devp,
  * @devp: returns the device found, on success
  * @method_flagsp: If non-NULL, returns any flags implied by the label
  * (enum bootflow_meth_flags_t), 0 if none. Unset if function fails
- * Return: 0 if OK, -EINVAL if the uclass is not supported by this board,
+ * Return: 0 if OK, -EPFNOSUPPORT if the uclass is not supported by this board,
  * -ENOENT if there is no device with that number
  */
 int bootdev_find_by_any(const char *name, struct udevice **devp,

diff --git a/include/cli.h b/include/cli.h
index c777c90..094a660 100644 (file)
--- a/include/cli.h
+++ b/include/cli.h
@@ -98,8 +98,8 @@ int cli_readline(const char *const prompt);
  *
  * @prompt:    Prompt to display
  * @buffer:    Place to put the line that is entered
- * @timeout:   Timeout in milliseconds, 0 if none
- * Return: command line length excluding terminator, or -ve on error: of the
+ * @timeout:   Timeout in seconds, 0 if none
+ * Return: command line length excluding terminator, or -ve on error: if the
  * timeout is exceeded (either CONFIG_BOOT_RETRY_TIME or the timeout
  * parameter), then -2 is returned. If a break is detected (Ctrl-C) then
  * -1 is returned.

diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index 4b89f31..d4c1e06 100644 (file)
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -111,6 +111,5 @@
 #define CFG_SYS_CS0_MASK               0x007F0001
 #define CFG_SYS_CS0_CTRL               0x00001FA0
 
-#define CFG_MCFTMR
 
 #endif                         /* _M5208EVBE_H */

diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index 14d4617..e542818 100644 (file)
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -130,6 +130,5 @@
 #      define CFG_SYS_CS0_CTRL 0x00001D80
 #endif
 
-#define CFG_MCFTMR
 
 #endif                         /* _M5329EVB_H */

diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index b240423..2f4743c 100644 (file)
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -120,6 +120,5 @@
 #define        CFG_SYS_GPIO1_OUT               0x00c70000      /* Set outputs to default state */
 #define CFG_SYS_GPIO1_LED              0x00400000      /* user led                     */
 
-#define CFG_MCFTMR
 
 #endif /* M5249 */

diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index 008c725..0ff0bfc 100644 (file)
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -132,6 +132,5 @@
 #define CFG_SYS_GPIO1_OUT              0x00c70000      /* Set outputs to default state */
 #define CFG_SYS_GPIO1_LED              0x00400000      /* user led */
 
-#define CFG_MCFTMR
 
 #endif                         /* _M5253DEMO_H */

diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index 49cf3e8..98a1718 100644 (file)
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -107,6 +107,5 @@
 #define CFG_SYS_PBDAT          0x0000
 #define CFG_SYS_PDCNT          0x00000000
 
-#define CFG_MCFTMR
 
 #endif                         /* _M5272C3_H */

diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 965327d..77ddf71 100644 (file)
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -116,6 +116,5 @@
 #define CFG_SYS_CS1_CTRL               0x00001900
 #define CFG_SYS_CS1_MASK               0x00070001
 
-#define CFG_MCFTMR
 
 #endif /* _M5275EVB_H */

diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index f04d9b1..e289a23 100644 (file)
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -127,6 +127,5 @@
 #define CFG_SYS_DDRUA          0x05
 #define CFG_SYS_PJPAR          0xFF
 
-#define CFG_MCFTMR
 
 #endif                         /* _CONFIG_M5282EVB_H */

diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index 04c456f..dcc5701 100644 (file)
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -132,6 +132,5 @@
 #define CFG_SYS_CS1_MASK               0x00070001
 #define CFG_SYS_CS1_CTRL               0x00001FA0
 
-#define CFG_MCFTMR
 
 #endif                         /* _M53017EVB_H */

diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 0aa1ffd..dd5d4c9 100644 (file)
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -138,6 +138,5 @@
 #define CFG_SYS_CS2_CTRL               0x00001f60
 #endif
 
-#define CFG_MCFTMR
 
 #endif                         /* _M5329EVB_H */

diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index 8b9e65d..4bb9948 100644 (file)
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -136,6 +136,5 @@
 #define CFG_SYS_CS2_MASK               (16 << 20)
 #define CFG_SYS_CS2_CTRL               0x00001f60
 
-#define CFG_MCFTMR
 
 #endif                         /* _M5373EVB_H */

diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 70b1c39..3967cc2 100644 (file)
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -140,7 +140,9 @@
 /*
  * Serial Port
  */
+#if !CONFIG_IS_ENABLED(DM_SERIAL) && !CONFIG_IS_ENABLED(DM_CLK)
 #define CFG_SYS_NS16550_CLK            get_bus_freq(0)
+#endif
 
 #define CFG_SYS_BAUDRATE_TABLE \
                {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h
index 26a7f25..1e37ab4 100644 (file)
--- a/include/configs/am64x_evm.h
+++ b/include/configs/am64x_evm.h
@@ -18,91 +18,6 @@
 /* DDR Configuration */
 #define CFG_SYS_SDRAM_BASE1            0x880000000
 
-#define PARTS_DEFAULT \
-       /* Linux partitions */ \
-       "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
-
-/* U-Boot general configuration */
-#define EXTRA_ENV_AM642_BOARD_SETTINGS                                 \
-       "findfdt="                                                      \
-               "if test $board_name = am64x_gpevm; then " \
-                       "setenv fdtfile k3-am642-evm.dtb; fi; " \
-               "if test $board_name = am64x_skevm; then " \
-                       "setenv fdtfile k3-am642-sk.dtb; fi;" \
-               "if test $fdtfile = undefined; then " \
-                       "echo WARNING: Could not determine device tree to use; fi; \0" \
-       "name_kern=Image\0"                                             \
-       "console=ttyS2,115200n8\0"                                      \
-       "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 "  \
-               "${mtdparts}\0"                                         \
-       "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
-
-/* U-Boot MMC-specific configuration */
-#define EXTRA_ENV_AM642_BOARD_SETTINGS_MMC                             \
-       "boot=mmc\0"                                                    \
-       "mmcdev=1\0"                                                    \
-       "bootpart=1:2\0"                                                \
-       "bootdir=/boot\0"                                               \
-       "rd_spec=-\0"                                                   \
-       "init_mmc=run args_all args_mmc\0"                              \
-       "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
-       "get_overlay_mmc="                                              \
-               "fdt address ${fdtaddr};"                               \
-               "fdt resize 0x100000;"                                  \
-               "for overlay in $name_overlays;"                        \
-               "do;"                                                   \
-               "load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && "    \
-               "fdt apply ${dtboaddr};"                                \
-               "done;\0"                                               \
-       "get_kern_mmc=load mmc ${bootpart} ${loadaddr} "                \
-               "${bootdir}/${name_kern}\0"                             \
-       "get_fit_mmc=load mmc ${bootpart} ${addr_fit} "                 \
-               "${bootdir}/${name_fit}\0"                              \
-       "partitions=" PARTS_DEFAULT
-
-#define EXTRA_ENV_AM642_BOARD_SETTING_USBMSC                           \
-       "args_usb=run finduuid;setenv bootargs console=${console} "     \
-               "${optargs} "                                           \
-               "root=PARTUUID=${uuid} rw "                             \
-               "rootfstype=${mmcrootfstype}\0"                         \
-       "init_usb=run args_all args_usb\0"                              \
-       "get_fdt_usb=load usb ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
-       "get_overlay_usb="                                              \
-               "fdt address ${fdtaddr};"                               \
-               "fdt resize 0x100000;"                                  \
-               "for overlay in $name_overlays;"                        \
-               "do;"                                                   \
-               "load usb ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && "    \
-               "fdt apply ${dtboaddr};"                                \
-               "done;\0"                                               \
-       "get_kern_usb=load usb ${bootpart} ${loadaddr} "                \
-               "${bootdir}/${name_kern}\0"                             \
-       "get_fit_usb=load usb ${bootpart} ${addr_fit} "                 \
-               "${bootdir}/${name_fit}\0"                              \
-       "usbboot=setenv boot usb;"                                      \
-               "setenv bootpart 0:2;"                                  \
-               "usb start;"                                            \
-               "run findfdt;"                                          \
-               "run init_usb;"                                         \
-               "run get_kern_usb;"                                     \
-               "run get_fdt_usb;"                                      \
-               "run run_kern\0"
-
-#define EXTRA_ENV_DFUARGS \
-       DFU_ALT_INFO_MMC \
-       DFU_ALT_INFO_EMMC \
-       DFU_ALT_INFO_RAM \
-       DFU_ALT_INFO_OSPI
-
-/* Incorporate settings into the U-Boot environment */
-#define CFG_EXTRA_ENV_SETTINGS                                 \
-       DEFAULT_LINUX_BOOT_ENV                                          \
-       DEFAULT_MMC_TI_ARGS                                             \
-       EXTRA_ENV_AM642_BOARD_SETTINGS                                  \
-       EXTRA_ENV_AM642_BOARD_SETTINGS_MMC                              \
-       EXTRA_ENV_DFUARGS                                               \
-       EXTRA_ENV_AM642_BOARD_SETTING_USBMSC
-
 /* Now for the remaining common defines */
 #include <configs/ti_armv7_common.h>
 

diff --git a/include/configs/amcore.h b/include/configs/amcore.h
index ca8d17b..4c695fb 100644 (file)
--- a/include/configs/amcore.h
+++ b/include/configs/amcore.h
@@ -10,7 +10,6 @@
 
 #define CFG_SYS_UART_PORT              0
 
-#define CFG_MCFTMR
 #define CFG_SYS_UART_PORT              0
 #define CFG_SYS_BAUDRATE_TABLE         { 9600, 19200, 38400, 57600, 115200 }
 

diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index 80f8c41..f3bfefa 100644 (file)
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -184,6 +184,5 @@
 #define CFG_SYS_CACHE_ICACR            (CF_CACR_EC | CF_CACR_CINVA | \
                                         CF_CACR_DCM_P)
 
-#define CFG_MCFTMR
 
 #endif /* _CONFIG_ASTRO_MCF5373L_H */

diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 276ecc3..556705f 100644 (file)
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -184,6 +184,5 @@ configuration */
 #define CFG_SYS_PBDAT          0x0000                  /* PortB value reg. */
 #define CFG_SYS_PDCNT          0x00000000              /* PortD control reg. */
 
-#define CFG_MCFTMR
 
 #endif /* _CONFIG_COBRA5272_H */

diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index ba45ee4..561a61e 100644 (file)
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -99,7 +99,7 @@
                "${board}/flash_blk.img && source ${loadaddr}\0" \
        "setup=setenv setupargs " \
                "console=tty1 console=${console}" \
-               ",${baudrate}n8 ${memargs} consoleblank=0\0" \
+               ",${baudrate}n8 ${memargs} ${mtdparts} consoleblank=0\0" \
        "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
        "setusbupdate=usb start && setenv interface usb && " \
                "fatload ${interface} 0:1 ${loadaddr} " \

diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index c568643..03f8ed1 100644 (file)
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -141,7 +141,7 @@
                "${board}/flash_blk.img && source ${loadaddr}\0" \
        "setup=setenv setupargs " \
                "console=tty1 console=${console}" \
-               ",${baudrate}n8 ${memargs} consoleblank=0\0" \
+               ",${baudrate}n8 ${memargs} ${mtdparts} consoleblank=0\0" \
        "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
        "setusbupdate=usb start && setenv interface usb && " \
                "fatload ${interface} 0:1 ${loadaddr} " \

diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index e9b382a..4b5ef4a 100644 (file)
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -31,7 +31,6 @@
 #define CFG_MXC_UART_BASE              UART1_BASE
 
 /* USB Configs */
-#ifdef CONFIG_CMD_USB
 #define CFG_MXC_USB_PORTSC             (PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CFG_MXC_USB_FLAGS              0
 
@@ -39,7 +38,6 @@
 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 #define DFU_DEFAULT_POLL_TIMEOUT       300
 #endif
-#endif
 
 #define CFG_EXTRA_ENV_SETTINGS \
        "console=ttymxc0,115200\0"      \

diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h
index 9503ab6..e2c9d9c 100644 (file)
--- a/include/configs/eb_cpu5282.h
+++ b/include/configs/eb_cpu5282.h
@@ -138,7 +138,6 @@
 #define CFG_SYS_DDRUA          0x05
 #define CFG_SYS_PJPAR          0xFF
 
-#define CFG_MCFTMR
 
 #endif /* _CONFIG_M5282EVB_H */
 /*---------------------------------------------------------------------*/

diff --git a/include/configs/evb_rk3588.h b/include/configs/evb_rk3588.h
new file mode 100644 (file)
index 0000000..4568e2c
--- /dev/null
+++ b/include/configs/evb_rk3588.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __EVB_RK3588_H
+#define __EVB_RK3588_H
+
+#include <configs/rk3588_common.h>
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+               "stdout=serial,vidconsole\0" \
+               "stderr=serial,vidconsole\0"
+
+#endif

diff --git a/include/configs/falcon.h b/include/configs/falcon.h
index 446261c..0b62ff9 100644 (file)
--- a/include/configs/falcon.h
+++ b/include/configs/falcon.h
@@ -9,17 +9,7 @@
 #ifndef __FALCON_H
 #define __FALCON_H
 
-#include "rcar-gen3-common.h"
-
-/*
- * Generic Interrupt Controller Definitions.  Undefine v2 locations and define
- * v3 locations.
- */
-#undef GICD_BASE
-#undef GICC_BASE
-#undef GICR_BASE
-#define GICD_BASE      0xF1000000
-#define GICR_BASE      0xF1060000
+#include "rcar-gen4-common.h"
 
 /* Board Clock */
 /* XTAL_CLK : 16.66MHz */

diff --git a/include/configs/imx8mn_bsh_smm_s2.h b/include/configs/imx8mn_bsh_smm_s2.h
index e97b8e8..deeed9c 100644 (file)
--- a/include/configs/imx8mn_bsh_smm_s2.h
+++ b/include/configs/imx8mn_bsh_smm_s2.h
@@ -14,7 +14,7 @@
 #include <config_distro_bootcmd.h>
 
 #define NANDARGS \
-       "nandargs=setenv bootargs console=${console} " \
+       "nandargs=setenv bootargs " \
                "${optargs} " \
                "mtdparts=${mtdparts} " \
                "root=${nandroot} " \

diff --git a/include/configs/imx8mp_beacon.h b/include/configs/imx8mp_beacon.h
new file mode 100644 (file)
index 0000000..ee0fd07
--- /dev/null
+++ b/include/configs/imx8mp_beacon.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks
+ */
+
+#ifndef __IMX8MP_BEACON_H
+#define __IMX8MP_BEACON_H
+
+#include <asm/arch/imx-regs.h>
+
+#define CFG_SYS_UBOOT_BASE     (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#if defined(CONFIG_CMD_NET)
+#define PHY_ANEG_TIMEOUT 20000
+#endif
+
+/* Link Definitions */
+
+#define CFG_SYS_INIT_RAM_ADDR  0x40000000
+#define CFG_SYS_INIT_RAM_SIZE  0x80000
+
+/* Totally 6GB DDR */
+#define CFG_SYS_SDRAM_BASE             0x40000000
+#define PHYS_SDRAM                     0x40000000
+#define PHYS_SDRAM_SIZE                        0xC0000000      /* 3 GB */
+#define PHYS_SDRAM_2                   0x100000000
+#define PHYS_SDRAM_2_SIZE              0xC0000000      /* 3 GB */
+
+#endif

diff --git a/include/configs/imx8mp_data_modul_edm_sbc.h b/include/configs/imx8mp_data_modul_edm_sbc.h
new file mode 100644 (file)
index 0000000..11ac3c0
--- /dev/null
+++ b/include/configs/imx8mp_data_modul_edm_sbc.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __IMX8MP_DATA_MODUL_EDM_SBC_H
+#define __IMX8MP_DATA_MODUL_EDM_SBC_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+/* Link Definitions */
+#define CFG_SYS_INIT_RAM_ADDR          0x40000000
+#define CFG_SYS_INIT_RAM_SIZE          0x200000
+
+#define CFG_SYS_SDRAM_BASE             0x40000000
+#define PHYS_SDRAM                     0x40000000
+#define PHYS_SDRAM_SIZE                        0x40000000 /* Minimum 1 GiB DDR */
+
+#define CFG_MXC_UART_BASE              UART3_BASE_ADDR
+
+/* PHY needs a longer autonegotiation timeout after reset */
+#define PHY_ANEG_TIMEOUT               20000
+#define FEC_QUIRK_ENET_MAC
+
+#define CFG_EXTRA_ENV_SETTINGS                                         \
+       "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0"          \
+       "bootlimit=3\0"                                                 \
+       "devtype=mmc\0"                                                 \
+       "devpart=1\0"                                                   \
+       /* Give slow devices beyond USB HUB chance to come up. */       \
+       "usb_pgood_delay=2000\0"                                        \
+       "dmo_update_env="                                               \
+               "setenv dmo_update_env true ; saveenv ; saveenv\0"      \
+       "dmo_update_sf_write_data="                                     \
+               "sf probe && sf update ${loadaddr} 0 ${filesize}\0"     \
+       "dmo_update_emmc_to_sf="                                        \
+               "load mmc 0:1 ${loadaddr} boot/flash.bin && "           \
+               "run dmo_update_sf_write_data\0"                        \
+       "dmo_update_sd_to_sf="                                          \
+               "load mmc 1:1 ${loadaddr} boot/flash.bin && "           \
+               "run dmo_update_sf_write_data\0"
+
+#endif

diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h
index 2fa93b7..1e0da9f 100644 (file)
--- a/include/configs/j721s2_evm.h
+++ b/include/configs/j721s2_evm.h
@@ -16,7 +16,7 @@
 #define CFG_SYS_SDRAM_BASE1            0x880000000
 
 /* SPL Loader Configuration */
-#if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
+#if defined(CONFIG_TARGET_J721S2_A72_EVM)
 #define CFG_SYS_UBOOT_BASE             0x50280000
 /* Image load address in RAM for DFU boot*/
 #else

diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h
index 8df481b..6fbd267 100644 (file)
--- a/include/configs/px30_common.h
+++ b/include/configs/px30_common.h
@@ -24,12 +24,11 @@
        "kernel_addr_c=0x03e80000\0" \
        "ramdisk_addr_r=0x0a200000\0"
 
-#include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
        ENV_MEM_LAYOUT_SETTINGS \
        "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
        "partitions=" PARTS_DEFAULT \
        ROCKCHIP_DEVICE_SETTINGS \
-       BOOTENV
+       "boot_targets=" BOOT_TARGETS "\0"
 
 #endif

diff --git a/include/configs/rcar-gen4-common.h b/include/configs/rcar-gen4-common.h
new file mode 100644 (file)
index 0000000..c4f506d
--- /dev/null
+++ b/include/configs/rcar-gen4-common.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/rcar-gen4-common.h
+ *     This file is R-Car Gen4 common configuration file.
+ *
+ * Copyright (C) 2021 Renesas Electronics Corporation
+ */
+
+#ifndef __RCAR_GEN4_COMMON_H
+#define __RCAR_GEN4_COMMON_H
+
+#include <asm/arch/rmobile.h>
+
+/* Console */
+#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200 }
+
+/* Memory */
+#define DRAM_RSV_SIZE                  0x08000000
+#define CFG_SYS_SDRAM_BASE             (0x40000000 + DRAM_RSV_SIZE)
+#define CFG_SYS_SDRAM_SIZE             (0x80000000u - DRAM_RSV_SIZE)
+#define CFG_MAX_MEM_MAPPED             (0x80000000u - DRAM_RSV_SIZE)
+
+/* PHY needs a longer autoneg timeout */
+#define PHY_ANEG_TIMEOUT               20000
+
+/* Environment setting */
+#define CFG_EXTRA_ENV_SETTINGS                                 \
+       "bootm_size=0x10000000\0"
+
+#endif /* __RCAR_GEN4_COMMON_H */

diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index ea6073f..c2abd14 100644 (file)
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -21,8 +21,6 @@
        "kernel_addr_r=0x62000000\0" \
        "ramdisk_addr_r=0x64000000\0"
 
-#include <config_distro_bootcmd.h>
-
 /* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board,
  * so limit the fdt reallocation to that */
 #define CFG_EXTRA_ENV_SETTINGS \
@@ -30,6 +28,6 @@
        "fdt_high=0x7fffffff\0" \
        "partitions=" PARTS_DEFAULT \
        ENV_MEM_LAYOUT_SETTINGS \
-       BOOTENV
+       "boot_targets=" BOOT_TARGETS "\0"
 
 #endif

diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h
index 1a6d367..d70c8f7 100644 (file)
--- a/include/configs/rk3066_common.h
+++ b/include/configs/rk3066_common.h
@@ -22,14 +22,12 @@
        "kernel_addr_r=0x62000000\0" \
        "ramdisk_addr_r=0x64000000\0"
 
-#include <config_distro_bootcmd.h>
-
 #define CFG_EXTRA_ENV_SETTINGS \
        "fdt_high=0x6fffffff\0" \
        "initrd_high=0x6fffffff\0" \
        "partitions=" PARTS_DEFAULT \
        ENV_MEM_LAYOUT_SETTINGS \
        ROCKCHIP_DEVICE_SETTINGS \
-       BOOTENV
+       "boot_targets=" BOOT_TARGETS "\0"
 
 #endif

diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h
index 8736b14..d8269b0 100644 (file)
--- a/include/configs/rk3128_common.h
+++ b/include/configs/rk3128_common.h
@@ -22,11 +22,10 @@
        "kernel_addr_r=0x62000000\0" \
        "ramdisk_addr_r=0x64000000\0"
 
-#include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
        ENV_MEM_LAYOUT_SETTINGS \
        "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
        "partitions=" PARTS_DEFAULT \
-       BOOTENV
+       "boot_targets=" BOOT_TARGETS "\0"
 
 #endif

diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index fcb2745..a8cee1e 100644 (file)
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@@ -21,8 +21,6 @@
        "kernel_addr_r=0x62000000\0" \
        "ramdisk_addr_r=0x64000000\0"
 
-#include <config_distro_bootcmd.h>
-
 /* Linux fails to load the fdt if it's loaded above 256M on a Rock board,
  * so limit the fdt reallocation to that */
 #define CFG_EXTRA_ENV_SETTINGS \
@@ -32,6 +30,6 @@
        "partitions=" PARTS_DEFAULT \
        ENV_MEM_LAYOUT_SETTINGS \
        ROCKCHIP_DEVICE_SETTINGS \
-       BOOTENV
+       "boot_targets=" BOOT_TARGETS "\0"
 
 #endif

diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
index 39a40f4..15f77df 100644 (file)
--- a/include/configs/rk322x_common.h
+++ b/include/configs/rk322x_common.h
@@ -22,8 +22,6 @@
        "kernel_addr_r=0x62000000\0" \
        "ramdisk_addr_r=0x64000000\0"
 
-#include <config_distro_bootcmd.h>
-
 /* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board,
  * so limit the fdt reallocation to that */
 #define CFG_EXTRA_ENV_SETTINGS \
@@ -31,6 +29,6 @@
        "fdt_high=0x7fffffff\0" \
        "partitions=" PARTS_DEFAULT \
        ENV_MEM_LAYOUT_SETTINGS \
-       BOOTENV
+       "boot_targets=" BOOT_TARGETS "\0"
 
 #endif

diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 71d2426..3063076 100644 (file)
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -23,8 +23,6 @@
        "kernel_addr_r=0x02000000\0" \
        "ramdisk_addr_r=0x04000000\0"
 
-#include <config_distro_bootcmd.h>
-
 /* Linux fails to load the fdt if it's loaded above 256M on a Rock 2 board, so
  * limit the fdt reallocation to that */
 #define CFG_EXTRA_ENV_SETTINGS \
@@ -34,6 +32,6 @@
        "partitions=" PARTS_DEFAULT \
        ENV_MEM_LAYOUT_SETTINGS \
        ROCKCHIP_DEVICE_SETTINGS \
-       BOOTENV
+       "boot_targets=" BOOT_TARGETS "\0"
 
 #endif

diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index ba9ee11..7d55fcd 100644 (file)
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h
@@ -20,11 +20,10 @@
        "kernel_addr_r=0x00680000\0" \
        "ramdisk_addr_r=0x04000000\0"
 
-#include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
        ENV_MEM_LAYOUT_SETTINGS \
        "partitions=" PARTS_DEFAULT \
        ROCKCHIP_DEVICE_SETTINGS \
-       BOOTENV
+       "boot_targets=" BOOT_TARGETS "\0"
 
 #endif

diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index e565ccf..e920ec7 100644 (file)
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -22,11 +22,10 @@
        "kernel_comp_addr_r=0x08000000\0" \
        "kernel_comp_size=0x2000000\0"
 
-#include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
        ENV_MEM_LAYOUT_SETTINGS \
        "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
        "partitions=" PARTS_DEFAULT \
-       BOOTENV
+       "boot_targets=" BOOT_TARGETS "\0"
 
 #endif

diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index 9aa256b..ccb5369 100644 (file)
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -23,11 +23,9 @@
        "kernel_addr_r=0x280000\0" \
        "ramdisk_addr_r=0x5bf0000\0"
 
-#include <config_distro_bootcmd.h>
-
 #define CFG_EXTRA_ENV_SETTINGS \
        "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
-       ENV_MEM_LAYOUT_SETTINGS \
-       BOOTENV
+       ENV_MEM_LAYOUT_SETTINGS \
+       "boot_targets=" BOOT_TARGETS "\0"
 
 #endif

diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h
index a5e1dde..1b7d343 100644 (file)
--- a/include/configs/rk3568_common.h
+++ b/include/configs/rk3568_common.h
@@ -17,17 +17,21 @@
 
 #define ENV_MEM_LAYOUT_SETTINGS                \
        "scriptaddr=0x00c00000\0"       \
+       "script_offset_f=0xffe000\0"    \
+       "script_size_f=0x2000\0"        \
        "pxefile_addr_r=0x00e00000\0"   \
        "fdt_addr_r=0x0a100000\0"       \
+       "fdtoverlay_addr_r=0x02000000\0"        \
        "kernel_addr_r=0x02080000\0"    \
-       "ramdisk_addr_r=0x0a200000\0"
+       "ramdisk_addr_r=0x0a200000\0"   \
+       "kernel_comp_addr_r=0x08000000\0"       \
+       "kernel_comp_size=0x2000000\0"
 
-#include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS         \
        ENV_MEM_LAYOUT_SETTINGS                 \
        "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
        "partitions=" PARTS_DEFAULT             \
-       ROCKCHIP_DEVICE_SETTINGS                \
-       BOOTENV
+       ROCKCHIP_DEVICE_SETTINGS \
+       "boot_targets=" BOOT_TARGETS "\0"
 
 #endif

diff --git a/include/configs/rk3588_common.h b/include/configs/rk3588_common.h
index abd2013..46389d0 100644 (file)
--- a/include/configs/rk3588_common.h
+++ b/include/configs/rk3588_common.h
@@ -16,17 +16,21 @@
 
 #define ENV_MEM_LAYOUT_SETTINGS                \
        "scriptaddr=0x00c00000\0"       \
+       "script_offset_f=0xffe000\0"    \
+       "script_size_f=0x2000\0"        \
        "pxefile_addr_r=0x00e00000\0"   \
        "fdt_addr_r=0x0a100000\0"       \
+       "fdtoverlay_addr_r=0x02000000\0"        \
        "kernel_addr_r=0x02080000\0"    \
-       "ramdisk_addr_r=0x0a200000\0"
+       "ramdisk_addr_r=0x0a200000\0"   \
+       "kernel_comp_addr_r=0x08000000\0"       \
+       "kernel_comp_size=0x2000000\0"
 
-#include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
        "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
        "partitions=" PARTS_DEFAULT             \
        ENV_MEM_LAYOUT_SETTINGS                 \
-       ROCKCHIP_DEVICE_SETTINGS                \
-       BOOTENV
+       ROCKCHIP_DEVICE_SETTINGS \
+       "boot_targets=" BOOT_TARGETS "\0"
 
 #endif /* __CONFIG_RK3588_COMMON_H */

diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
index 18544d7..9121bba 100644 (file)
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@@ -13,69 +13,7 @@
 
 #ifndef CONFIG_SPL_BUILD
 
-/* First try to boot from SD (index 1), then eMMC (index 0) */
-#if IS_ENABLED(CONFIG_CMD_MMC)
-       #define BOOT_TARGET_MMC(func) \
-               func(MMC, mmc, 1) \
-               func(MMC, mmc, 0)
-#else
-       #define BOOT_TARGET_MMC(func)
-#endif
-
-#if IS_ENABLED(CONFIG_CMD_NVME)
-       #define BOOT_TARGET_NVME(func) func(NVME, nvme, 0)
-#else
-       #define BOOT_TARGET_NVME(func)
-#endif
-
-#if IS_ENABLED(CONFIG_CMD_SCSI)
-       #define BOOT_TARGET_SCSI(func) func(SCSI, scsi, 0)
-#else
-       #define BOOT_TARGET_SCSI(func)
-#endif
-
-#if IS_ENABLED(CONFIG_CMD_USB)
-       #define BOOT_TARGET_USB(func) func(USB, usb, 0)
-#else
-       #define BOOT_TARGET_USB(func)
-#endif
-
-#if CONFIG_IS_ENABLED(CMD_PXE)
-       #define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
-#else
-       #define BOOT_TARGET_PXE(func)
-#endif
-
-#if CONFIG_IS_ENABLED(CMD_DHCP)
-       #define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
-#else
-       #define BOOT_TARGET_DHCP(func)
-#endif
-
-#if IS_ENABLED(CONFIG_CMD_SF)
-       #define BOOT_TARGET_SF(func)    func(SF, sf, 0)
-#else
-       #define BOOT_TARGET_SF(func)
-#endif
-
-#ifdef CONFIG_ROCKCHIP_RK3399
-#define BOOT_TARGET_DEVICES(func) \
-       BOOT_TARGET_MMC(func) \
-       BOOT_TARGET_NVME(func) \
-       BOOT_TARGET_SCSI(func) \
-       BOOT_TARGET_USB(func) \
-       BOOT_TARGET_PXE(func) \
-       BOOT_TARGET_DHCP(func) \
-       BOOT_TARGET_SF(func)
 #define BOOT_TARGETS   "mmc1 mmc0 nvme scsi usb pxe dhcp spi"
-#else
-#define BOOT_TARGET_DEVICES(func) \
-       BOOT_TARGET_MMC(func) \
-       BOOT_TARGET_USB(func) \
-       BOOT_TARGET_PXE(func) \
-       BOOT_TARGET_DHCP(func)
-#define BOOT_TARGETS   "mmc1 mmc0 usb pxe dhcp"
-#endif
 
 #ifdef CONFIG_ARM64
 #define ROOT_UUID "B921B045-1DF0-41C3-AF44-4C6F280D3FAE;\0"

diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index 050d37b..3bf70a0 100644 (file)
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h
@@ -28,6 +28,6 @@
        ENV_MEM_LAYOUT_SETTINGS \
        "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
        "partitions=" PARTS_DEFAULT \
-       BOOTENV
+       "boot_targets=" BOOT_TARGETS "\0"
 
 #endif

diff --git a/include/configs/spider.h b/include/configs/spider.h
new file mode 100644 (file)
index 0000000..e9b7d6b
--- /dev/null
+++ b/include/configs/spider.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/spider.h
+ *     This file is Spider board configuration.
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#ifndef __SPIDER_H
+#define __SPIDER_H
+
+#include "rcar-gen4-common.h"
+
+#endif /* __SPIDER_H */

diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h
new file mode 100644 (file)
index 0000000..93dcc22
--- /dev/null
+++ b/include/configs/starfive-visionfive2.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author:     Yanhong Wang<yanhong.wang@starfivetech.com>
+ *
+ */
+
+#ifndef _STARFIVE_VISIONFIVE2_H
+#define _STARFIVE_VISIONFIVE2_H
+
+#define RISCV_MMODE_TIMERBASE          0x2000000
+#define RISCV_MMODE_TIMER_FREQ         4000000
+#define RISCV_SMODE_TIMER_FREQ         4000000
+
+#define __io
+
+/* Environment options */
+
+#define BOOT_TARGET_DEVICES(func) \
+       func(MMC, mmc, 1) \
+       func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define TYPE_GUID_SPL          "2E54B353-1271-4842-806F-E436D6AF6985"
+#define TYPE_GUID_UBOOT        "BC13C2FF-59E6-4262-A352-B275FD6F7172"
+#define TYPE_GUID_SYSTEM       "EBD0A0A2-B9E5-4433-87C0-68B6B72699C7"
+
+#define PARTS_DEFAULT                                                  \
+               "name=spl,start=2M,size=2M,type=${type_guid_gpt_loader1};" \
+               "name=uboot,size=4MB,type=${type_guid_gpt_loader2};"            \
+               "name=system,size=-,bootable,type=${type_guid_gpt_system};"
+
+#define CFG_EXTRA_ENV_SETTINGS \
+       "kernel_addr_r=0x40200000\0" \
+       "kernel_comp_addr_r=0x88000000\0" \
+       "kernel_comp_size=0x4000000\0" \
+       "fdt_addr_r=0x46000000\0" \
+       "scriptaddr=0x43900000\0" \
+       "pxefile_addr_r=0x45900000\0" \
+       "ramdisk_addr_r=0x46100000\0" \
+       "type_guid_gpt_loader1=" TYPE_GUID_SPL "\0" \
+       "type_guid_gpt_loader2=" TYPE_GUID_UBOOT "\0" \
+       "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
+       "partitions=" PARTS_DEFAULT "\0" \
+       "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+       BOOTENV
+
+#endif /* _STARFIVE_VISIONFIVE2_H */

diff --git a/include/configs/stm32mp13_st_common.h b/include/configs/stm32mp13_st_common.h
index ad8126f..20ec114 100644 (file)
--- a/include/configs/stm32mp13_st_common.h
+++ b/include/configs/stm32mp13_st_common.h
@@ -9,7 +9,7 @@
 #define __CONFIG_STM32MP13_ST_COMMON_H__
 
 #define STM32MP_BOARD_EXTRA_ENV \
-       "usb_pgood_delay=1000\0" \
+       "usb_pgood_delay=2000\0" \
        "console=ttySTM0\0"
 
 #include <configs/stm32mp13_common.h>

diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h
index d0cd413..866cd7a 100644 (file)
--- a/include/configs/stm32mp15_st_common.h
+++ b/include/configs/stm32mp15_st_common.h
@@ -9,6 +9,7 @@
 #define __CONFIG_STM32MP15_ST_COMMON_H__
 
 #define STM32MP_BOARD_EXTRA_ENV \
+       "usb_pgood_delay=2000\0" \
        "console=ttySTM0\0"
 
 #include <configs/stm32mp15_common.h>

diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h
index 05de376..af5da09 100644 (file)
--- a/include/configs/stmark2.h
+++ b/include/configs/stmark2.h
@@ -95,6 +95,7 @@
 #define CACR_STATUS                    (CFG_SYS_INIT_RAM_ADDR + \
                                        CFG_SYS_INIT_RAM_SIZE - 12)
 
-#define CFG_MCFTMR
+
+#define CFG_SYS_I2C_0
 
 #endif /* __STMARK2_CONFIG_H */

diff --git a/include/configs/whitehawk.h b/include/configs/whitehawk.h
new file mode 100644 (file)
index 0000000..4b4cf63
--- /dev/null
+++ b/include/configs/whitehawk.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/whitehawk.h
+ *     This file is White Hawk board configuration.
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#ifndef __WHITEHAWK_H
+#define __WHITEHAWK_H
+
+#include "rcar-gen4-common.h"
+
+#endif /* __WHITEHAWK_H */

diff --git a/include/dm/platform_data/serial_sh.h b/include/dm/platform_data/serial_sh.h
index 69cd012..1a20285 100644 (file)
--- a/include/dm/platform_data/serial_sh.h
+++ b/include/dm/platform_data/serial_sh.h
@@ -17,6 +17,7 @@ enum sh_serial_type {
        PORT_SCIF,
        PORT_SCIFA,
        PORT_SCIFB,
+       PORT_HSCIF,
 };
 
 /*

diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 33e43c2..5386c3f 100644 (file)
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -37,6 +37,7 @@ enum uclass_id {
        UCLASS_AUDIO_CODEC,     /* Audio codec with control and data path */
        UCLASS_AXI,             /* AXI bus */
        UCLASS_BLK,             /* Block device */
+       UCLASS_BLKMAP,          /* Composable virtual block device */
        UCLASS_BOOTCOUNT,       /* Bootcount backing store */
        UCLASS_BOOTDEV,         /* Boot device for locating an OS to boot */
        UCLASS_BOOTMETH,        /* Bootmethod for booting an OS */
@@ -88,6 +89,7 @@ enum uclass_id {
        UCLASS_NOP,             /* No-op devices */
        UCLASS_NORTHBRIDGE,     /* Intel Northbridge / SDRAM controller */
        UCLASS_NVME,            /* NVM Express device */
+       UCLASS_NVMXIP,          /* NVM XIP devices */
        UCLASS_P2SB,            /* (x86) Primary-to-Sideband Bus */
        UCLASS_PANEL,           /* Display panel, such as an LCD */
        UCLASS_PANEL_BACKLIGHT, /* Backlight controller for panel */

diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index ee15c92..5c5fb9a 100644 (file)
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -265,6 +265,23 @@ int uclass_get_device_by_ofnode(enum uclass_id id, ofnode node,
                                struct udevice **devp);
 
 /**
+ * uclass_get_device_by_of_path() - Get a uclass device by device tree path
+ *
+ * This searches the devices in the uclass for one attached to the
+ * device tree node corresponding to the given path (which may also be
+ * an alias).
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @id: ID to look up
+ * @node: Device tree path to search for (if no such path then -ENODEV is returned)
+ * @devp: Returns pointer to device (there is only one for each node)
+ * Return: 0 if OK, -ve on error
+ */
+int uclass_get_device_by_of_path(enum uclass_id id, const char *path,
+                                struct udevice **devp);
+
+/**
  * uclass_get_device_by_phandle_id() - Get a uclass device by phandle id
  *
  * This searches the devices in the uclass for one with the given phandle id.

diff --git a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
new file mode 100644 (file)
index 0000000..f2ae1c6
--- /dev/null
+++ b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
+/*
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a779f0 CPG Core Clocks */
+
+#define R8A779F0_CLK_ZX                        0
+#define R8A779F0_CLK_ZS                        1
+#define R8A779F0_CLK_ZT                        2
+#define R8A779F0_CLK_ZTR               3
+#define R8A779F0_CLK_S0D2              4
+#define R8A779F0_CLK_S0D3              5
+#define R8A779F0_CLK_S0D4              6
+#define R8A779F0_CLK_S0D2_MM           7
+#define R8A779F0_CLK_S0D3_MM           8
+#define R8A779F0_CLK_S0D4_MM           9
+#define R8A779F0_CLK_S0D2_RT           10
+#define R8A779F0_CLK_S0D3_RT           11
+#define R8A779F0_CLK_S0D4_RT           12
+#define R8A779F0_CLK_S0D6_RT           13
+#define R8A779F0_CLK_S0D3_PER          14
+#define R8A779F0_CLK_S0D6_PER          15
+#define R8A779F0_CLK_S0D12_PER         16
+#define R8A779F0_CLK_S0D24_PER         17
+#define R8A779F0_CLK_S0D2_HSC          18
+#define R8A779F0_CLK_S0D3_HSC          19
+#define R8A779F0_CLK_S0D4_HSC          20
+#define R8A779F0_CLK_S0D6_HSC          21
+#define R8A779F0_CLK_S0D12_HSC         22
+#define R8A779F0_CLK_S0D2_CC           23
+#define R8A779F0_CLK_CL                        24
+#define R8A779F0_CLK_CL16M             25
+#define R8A779F0_CLK_CL16M_MM          26
+#define R8A779F0_CLK_CL16M_RT          27
+#define R8A779F0_CLK_CL16M_PER         28
+#define R8A779F0_CLK_CL16M_HSC         29
+#define R8A779F0_CLK_Z0                        30
+#define R8A779F0_CLK_Z1                        31
+#define R8A779F0_CLK_ZB3               32
+#define R8A779F0_CLK_ZB3D2             33
+#define R8A779F0_CLK_ZB3D4             34
+#define R8A779F0_CLK_SD0H              35
+#define R8A779F0_CLK_SD0               36
+#define R8A779F0_CLK_RPC               37
+#define R8A779F0_CLK_RPCD2             38
+#define R8A779F0_CLK_MSO               39
+#define R8A779F0_CLK_SASYNCRT          40
+#define R8A779F0_CLK_SASYNCPERD1       41
+#define R8A779F0_CLK_SASYNCPERD2       42
+#define R8A779F0_CLK_SASYNCPERD4       43
+#define R8A779F0_CLK_DBGSOC_HSC                44
+#define R8A779F0_CLK_RSW2              45
+#define R8A779F0_CLK_OSC               46
+#define R8A779F0_CLK_ZR                        47
+#define R8A779F0_CLK_CPEX              48
+#define R8A779F0_CLK_CBFUSA            49
+#define R8A779F0_CLK_R                 50
+
+#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */

diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
new file mode 100644 (file)
index 0000000..754c54a
--- /dev/null
+++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a779g0 CPG Core Clocks */
+
+#define R8A779G0_CLK_ZX                        0
+#define R8A779G0_CLK_ZS                        1
+#define R8A779G0_CLK_ZT                        2
+#define R8A779G0_CLK_ZTR               3
+#define R8A779G0_CLK_S0D2              4
+#define R8A779G0_CLK_S0D3              5
+#define R8A779G0_CLK_S0D4              6
+#define R8A779G0_CLK_S0D1_VIO          7
+#define R8A779G0_CLK_S0D2_VIO          8
+#define R8A779G0_CLK_S0D4_VIO          9
+#define R8A779G0_CLK_S0D8_VIO          10
+#define R8A779G0_CLK_S0D1_VC           11
+#define R8A779G0_CLK_S0D2_VC           12
+#define R8A779G0_CLK_S0D4_VC           13
+#define R8A779G0_CLK_S0D2_MM           14
+#define R8A779G0_CLK_S0D4_MM           15
+#define R8A779G0_CLK_S0D2_U3DG         16
+#define R8A779G0_CLK_S0D4_U3DG         17
+#define R8A779G0_CLK_S0D2_RT           18
+#define R8A779G0_CLK_S0D3_RT           19
+#define R8A779G0_CLK_S0D4_RT           20
+#define R8A779G0_CLK_S0D6_RT           21
+#define R8A779G0_CLK_S0D24_RT          22
+#define R8A779G0_CLK_S0D2_PER          23
+#define R8A779G0_CLK_S0D3_PER          24
+#define R8A779G0_CLK_S0D4_PER          25
+#define R8A779G0_CLK_S0D6_PER          26
+#define R8A779G0_CLK_S0D12_PER         27
+#define R8A779G0_CLK_S0D24_PER         28
+#define R8A779G0_CLK_S0D1_HSC          29
+#define R8A779G0_CLK_S0D2_HSC          30
+#define R8A779G0_CLK_S0D4_HSC          31
+#define R8A779G0_CLK_S0D2_CC           32
+#define R8A779G0_CLK_SVD1_IR           33
+#define R8A779G0_CLK_SVD2_IR           34
+#define R8A779G0_CLK_SVD1_VIP          35
+#define R8A779G0_CLK_SVD2_VIP          36
+#define R8A779G0_CLK_CL                        37
+#define R8A779G0_CLK_CL16M             38
+#define R8A779G0_CLK_CL16M_MM          39
+#define R8A779G0_CLK_CL16M_RT          40
+#define R8A779G0_CLK_CL16M_PER         41
+#define R8A779G0_CLK_CL16M_HSC         42
+#define R8A779G0_CLK_Z0                        43
+#define R8A779G0_CLK_ZB3               44
+#define R8A779G0_CLK_ZB3D2             45
+#define R8A779G0_CLK_ZB3D4             46
+#define R8A779G0_CLK_ZG                        47
+#define R8A779G0_CLK_SD0H              48
+#define R8A779G0_CLK_SD0               49
+#define R8A779G0_CLK_RPC               50
+#define R8A779G0_CLK_RPCD2             51
+#define R8A779G0_CLK_MSO               52
+#define R8A779G0_CLK_CANFD             53
+#define R8A779G0_CLK_CSI               54
+#define R8A779G0_CLK_FRAY              55
+#define R8A779G0_CLK_IPC               56
+#define R8A779G0_CLK_SASYNCRT          57
+#define R8A779G0_CLK_SASYNCPERD1       58
+#define R8A779G0_CLK_SASYNCPERD2       59
+#define R8A779G0_CLK_SASYNCPERD4       60
+#define R8A779G0_CLK_VIOBUS            61
+#define R8A779G0_CLK_VIOBUSD2          62
+#define R8A779G0_CLK_VCBUS             63
+#define R8A779G0_CLK_VCBUSD2           64
+#define R8A779G0_CLK_DSIEXT            65
+#define R8A779G0_CLK_DSIREF            66
+#define R8A779G0_CLK_ADGH              67
+#define R8A779G0_CLK_OSC               68
+#define R8A779G0_CLK_ZR0               69
+#define R8A779G0_CLK_ZR1               70
+#define R8A779G0_CLK_ZR2               71
+#define R8A779G0_CLK_IMPA              72
+#define R8A779G0_CLK_IMPAD4            73
+#define R8A779G0_CLK_CPEX              74
+#define R8A779G0_CLK_CBFUSA            75
+#define R8A779G0_CLK_R                 76
+
+#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */

diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
new file mode 100644 (file)
index 0000000..77b70e7
--- /dev/null
+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
@@ -0,0 +1,257 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ *
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__
+#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__
+
+#define JH7110_SYSCLK_CPU_ROOT                 0
+#define JH7110_SYSCLK_CPU_CORE                 1
+#define JH7110_SYSCLK_CPU_BUS                  2
+#define JH7110_SYSCLK_GPU_ROOT                 3
+#define JH7110_SYSCLK_PERH_ROOT                4
+#define JH7110_SYSCLK_BUS_ROOT                 5
+#define JH7110_SYSCLK_NOCSTG_BUS               6
+#define JH7110_SYSCLK_AXI_CFG0                 7
+#define JH7110_SYSCLK_STG_AXIAHB               8
+#define JH7110_SYSCLK_AHB0                     9
+#define JH7110_SYSCLK_AHB1                     10
+#define JH7110_SYSCLK_APB_BUS                  11
+#define JH7110_SYSCLK_APB0                     12
+#define JH7110_SYSCLK_PLL0_DIV2                13
+#define JH7110_SYSCLK_PLL1_DIV2                14
+#define JH7110_SYSCLK_PLL2_DIV2                15
+#define JH7110_SYSCLK_AUDIO_ROOT               16
+#define JH7110_SYSCLK_MCLK_INNER               17
+#define JH7110_SYSCLK_MCLK                     18
+#define JH7110_SYSCLK_MCLK_OUT                 19
+#define JH7110_SYSCLK_ISP_2X                   20
+#define JH7110_SYSCLK_ISP_AXI                  21
+#define JH7110_SYSCLK_GCLK0                    22
+#define JH7110_SYSCLK_GCLK1                    23
+#define JH7110_SYSCLK_GCLK2                    24
+#define JH7110_SYSCLK_CORE                     25
+#define JH7110_SYSCLK_CORE1                    26
+#define JH7110_SYSCLK_CORE2                    27
+#define JH7110_SYSCLK_CORE3                    28
+#define JH7110_SYSCLK_CORE4                    29
+#define JH7110_SYSCLK_DEBUG                    30
+#define JH7110_SYSCLK_RTC_TOGGLE               31
+#define JH7110_SYSCLK_TRACE0                   32
+#define JH7110_SYSCLK_TRACE1                   33
+#define JH7110_SYSCLK_TRACE2                   34
+#define JH7110_SYSCLK_TRACE3                   35
+#define JH7110_SYSCLK_TRACE4                   36
+#define JH7110_SYSCLK_TRACE_COM                37
+#define JH7110_SYSCLK_NOC_BUS_CPU_AXI          38
+#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI      39
+#define JH7110_SYSCLK_OSC_DIV2                 40
+#define JH7110_SYSCLK_PLL1_DIV4                41
+#define JH7110_SYSCLK_PLL1_DIV8                42
+#define JH7110_SYSCLK_DDR_BUS                  43
+#define JH7110_SYSCLK_DDR_AXI                  44
+#define JH7110_SYSCLK_GPU_CORE                 45
+#define JH7110_SYSCLK_GPU_CORE_CLK             46
+#define JH7110_SYSCLK_GPU_SYS_CLK              47
+#define JH7110_SYSCLK_GPU_APB                  48
+#define JH7110_SYSCLK_GPU_RTC_TOGGLE           49
+#define JH7110_SYSCLK_NOC_BUS_GPU_AXI          50
+#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X   51
+#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI      52
+#define JH7110_SYSCLK_NOC_BUS_ISP_AXI          53
+#define JH7110_SYSCLK_HIFI4_CORE               54
+#define JH7110_SYSCLK_HIFI4_AXI                55
+#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN        56
+#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB         57
+#define JH7110_SYSCLK_VOUT_SRC                 58
+#define JH7110_SYSCLK_VOUT_AXI                 59
+#define JH7110_SYSCLK_NOC_BUS_DISP_AXI         60
+#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB            61
+#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI            62
+#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK        63
+#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF         64
+#define JH7110_SYSCLK_JPEGC_AXI                65
+#define JH7110_SYSCLK_CODAJ12_AXI              66
+#define JH7110_SYSCLK_CODAJ12_CORE             67
+#define JH7110_SYSCLK_CODAJ12_APB              68
+#define JH7110_SYSCLK_VDEC_AXI                 69
+#define JH7110_SYSCLK_WAVE511_AXI              70
+#define JH7110_SYSCLK_WAVE511_BPU              71
+#define JH7110_SYSCLK_WAVE511_VCE              72
+#define JH7110_SYSCLK_WAVE511_APB              73
+#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG         74
+#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN        75
+#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI         76
+#define JH7110_SYSCLK_VENC_AXI                 77
+#define JH7110_SYSCLK_WAVE420L_AXI             78
+#define JH7110_SYSCLK_WAVE420L_BPU             79
+#define JH7110_SYSCLK_WAVE420L_VCE             80
+#define JH7110_SYSCLK_WAVE420L_APB             81
+#define JH7110_SYSCLK_NOC_BUS_VENC_AXI         82
+#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV    83
+#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN        84
+#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4       85
+#define JH7110_SYSCLK_AXIMEM2_AXI              86
+#define JH7110_SYSCLK_QSPI_AHB                 87
+#define JH7110_SYSCLK_QSPI_APB                 88
+#define JH7110_SYSCLK_QSPI_REF_SRC             89
+#define JH7110_SYSCLK_QSPI_REF                 90
+#define JH7110_SYSCLK_SDIO0_AHB                91
+#define JH7110_SYSCLK_SDIO1_AHB                92
+#define JH7110_SYSCLK_SDIO0_SDCARD             93
+#define JH7110_SYSCLK_SDIO1_SDCARD             94
+#define JH7110_SYSCLK_USB_125M                 95
+#define JH7110_SYSCLK_NOC_BUS_STG_AXI          96
+#define JH7110_SYSCLK_GMAC1_AHB                97
+#define JH7110_SYSCLK_GMAC1_AXI                98
+#define JH7110_SYSCLK_GMAC_SRC                 99
+#define JH7110_SYSCLK_GMAC1_GTXCLK             100
+#define JH7110_SYSCLK_GMAC1_RMII_RTX           101
+#define JH7110_SYSCLK_GMAC1_PTP                102
+#define JH7110_SYSCLK_GMAC1_RX                 103
+#define JH7110_SYSCLK_GMAC1_RX_INV             104
+#define JH7110_SYSCLK_GMAC1_TX                 105
+#define JH7110_SYSCLK_GMAC1_TX_INV             106
+#define JH7110_SYSCLK_GMAC1_GTXC               107
+#define JH7110_SYSCLK_GMAC0_GTXCLK             108
+#define JH7110_SYSCLK_GMAC0_PTP                109
+#define JH7110_SYSCLK_GMAC_PHY                 110
+#define JH7110_SYSCLK_GMAC0_GTXC               111
+#define JH7110_SYSCLK_IOMUX_APB                112
+#define JH7110_SYSCLK_MAILBOX                  113
+#define JH7110_SYSCLK_INT_CTRL_APB             114
+#define JH7110_SYSCLK_CAN0_APB                 115
+#define JH7110_SYSCLK_CAN0_TIMER               116
+#define JH7110_SYSCLK_CAN0_CAN                 117
+#define JH7110_SYSCLK_CAN1_APB                 118
+#define JH7110_SYSCLK_CAN1_TIMER               119
+#define JH7110_SYSCLK_CAN1_CAN                 120
+#define JH7110_SYSCLK_PWM_APB                  121
+#define JH7110_SYSCLK_WDT_APB                  122
+#define JH7110_SYSCLK_WDT_CORE                 123
+#define JH7110_SYSCLK_TIMER_APB                124
+#define JH7110_SYSCLK_TIMER0                   125
+#define JH7110_SYSCLK_TIMER1                   126
+#define JH7110_SYSCLK_TIMER2                   127
+#define JH7110_SYSCLK_TIMER3                   128
+#define JH7110_SYSCLK_TEMP_APB                 129
+#define JH7110_SYSCLK_TEMP_CORE                130
+#define JH7110_SYSCLK_SPI0_APB                 131
+#define JH7110_SYSCLK_SPI1_APB                 132
+#define JH7110_SYSCLK_SPI2_APB                 133
+#define JH7110_SYSCLK_SPI3_APB                 134
+#define JH7110_SYSCLK_SPI4_APB                 135
+#define JH7110_SYSCLK_SPI5_APB                 136
+#define JH7110_SYSCLK_SPI6_APB                 137
+#define JH7110_SYSCLK_I2C0_APB                 138
+#define JH7110_SYSCLK_I2C1_APB                 139
+#define JH7110_SYSCLK_I2C2_APB                 140
+#define JH7110_SYSCLK_I2C3_APB                 141
+#define JH7110_SYSCLK_I2C4_APB                 142
+#define JH7110_SYSCLK_I2C5_APB                 143
+#define JH7110_SYSCLK_I2C6_APB                 144
+#define JH7110_SYSCLK_UART0_APB                145
+#define JH7110_SYSCLK_UART0_CORE               146
+#define JH7110_SYSCLK_UART1_APB                147
+#define JH7110_SYSCLK_UART1_CORE               148
+#define JH7110_SYSCLK_UART2_APB                149
+#define JH7110_SYSCLK_UART2_CORE               150
+#define JH7110_SYSCLK_UART3_APB                151
+#define JH7110_SYSCLK_UART3_CORE               152
+#define JH7110_SYSCLK_UART4_APB                153
+#define JH7110_SYSCLK_UART4_CORE               154
+#define JH7110_SYSCLK_UART5_APB                155
+#define JH7110_SYSCLK_UART5_CORE               156
+#define JH7110_SYSCLK_PWMDAC_APB               157
+#define JH7110_SYSCLK_PWMDAC_CORE              158
+#define JH7110_SYSCLK_SPDIF_APB                159
+#define JH7110_SYSCLK_SPDIF_CORE               160
+#define JH7110_SYSCLK_I2STX0_APB               161
+#define JH7110_SYSCLK_I2STX0_BCLK_MST          162
+#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV      163
+#define JH7110_SYSCLK_I2STX0_LRCK_MST          164
+#define JH7110_SYSCLK_I2STX0_BCLK              165
+#define JH7110_SYSCLK_I2STX0_BCLK_INV          166
+#define JH7110_SYSCLK_I2STX0_LRCK              167
+#define JH7110_SYSCLK_I2STX1_APB               168
+#define JH7110_SYSCLK_I2STX1_BCLK_MST          169
+#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV      170
+#define JH7110_SYSCLK_I2STX1_LRCK_MST          171
+#define JH7110_SYSCLK_I2STX1_BCLK              172
+#define JH7110_SYSCLK_I2STX1_BCLK_INV          173
+#define JH7110_SYSCLK_I2STX1_LRCK              174
+#define JH7110_SYSCLK_I2SRX_APB                175
+#define JH7110_SYSCLK_I2SRX_BCLK_MST           176
+#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV       177
+#define JH7110_SYSCLK_I2SRX_LRCK_MST           178
+#define JH7110_SYSCLK_I2SRX_BCLK               179
+#define JH7110_SYSCLK_I2SRX_BCLK_INV           180
+#define JH7110_SYSCLK_I2SRX_LRCK               181
+#define JH7110_SYSCLK_PDM_DMIC                 182
+#define JH7110_SYSCLK_PDM_APB                  183
+#define JH7110_SYSCLK_TDM_AHB                  184
+#define JH7110_SYSCLK_TDM_APB                  185
+#define JH7110_SYSCLK_TDM_INTERNAL             186
+#define JH7110_SYSCLK_TDM_CLK_TDM              187
+#define JH7110_SYSCLK_TDM_CLK_TDM_N            188
+#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG  189
+
+#define JH7110_SYSCLK_PLL0_OUT                 190
+#define JH7110_SYSCLK_PLL1_OUT                 191
+#define JH7110_SYSCLK_PLL2_OUT                 192
+
+#define JH7110_SYSCLK_END                      193
+
+#define JH7110_AONCLK_OSC_DIV4         (JH7110_SYSCLK_END + 0)
+#define JH7110_AONCLK_APB_FUNC         (JH7110_SYSCLK_END + 1)
+#define JH7110_AONCLK_GMAC0_AHB        (JH7110_SYSCLK_END + 2)
+#define JH7110_AONCLK_GMAC0_AXI        (JH7110_SYSCLK_END + 3)
+#define JH7110_AONCLK_GMAC0_RMII_RTX   (JH7110_SYSCLK_END + 4)
+#define JH7110_AONCLK_GMAC0_TX         (JH7110_SYSCLK_END + 5)
+#define JH7110_AONCLK_GMAC0_TX_INV     (JH7110_SYSCLK_END + 6)
+#define JH7110_AONCLK_GMAC0_RX         (JH7110_SYSCLK_END + 7)
+#define JH7110_AONCLK_GMAC0_RX_INV     (JH7110_SYSCLK_END + 8)
+#define JH7110_AONCLK_OTPC_APB         (JH7110_SYSCLK_END  + 9)
+#define JH7110_AONCLK_RTC_APB          (JH7110_SYSCLK_END + 10)
+#define JH7110_AONCLK_RTC_INTERNAL     (JH7110_SYSCLK_END + 11)
+#define JH7110_AONCLK_RTC_32K          (JH7110_SYSCLK_END + 12)
+#define JH7110_AONCLK_RTC_CAL          (JH7110_SYSCLK_END + 13)
+
+#define JH7110_AONCLK_END              (JH7110_SYSCLK_END + 14)
+
+#define JH7110_STGCLK_HIFI4_CORE       (JH7110_AONCLK_END + 0)
+#define JH7110_STGCLK_USB_APB          (JH7110_AONCLK_END + 1)
+#define JH7110_STGCLK_USB_UTMI_APB     (JH7110_AONCLK_END + 2)
+#define JH7110_STGCLK_USB_AXI          (JH7110_AONCLK_END + 3)
+#define JH7110_STGCLK_USB_LPM          (JH7110_AONCLK_END + 4)
+#define JH7110_STGCLK_USB_STB          (JH7110_AONCLK_END + 5)
+#define JH7110_STGCLK_USB_APP_125      (JH7110_AONCLK_END + 6)
+#define JH7110_STGCLK_USB_REFCLK       (JH7110_AONCLK_END + 7)
+#define JH7110_STGCLK_PCIE0_AXI        (JH7110_AONCLK_END + 8)
+#define JH7110_STGCLK_PCIE0_APB        (JH7110_AONCLK_END + 9)
+#define JH7110_STGCLK_PCIE0_TL         (JH7110_AONCLK_END + 10)
+#define JH7110_STGCLK_PCIE1_AXI        (JH7110_AONCLK_END + 11)
+#define JH7110_STGCLK_PCIE1_APB        (JH7110_AONCLK_END + 12)
+#define JH7110_STGCLK_PCIE1_TL         (JH7110_AONCLK_END + 13)
+#define JH7110_STGCLK_PCIE01_MAIN      (JH7110_AONCLK_END + 14)
+#define JH7110_STGCLK_SEC_HCLK         (JH7110_AONCLK_END + 15)
+#define JH7110_STGCLK_SEC_MISCAHB      (JH7110_AONCLK_END + 16)
+#define JH7110_STGCLK_MTRX_GRP0_MAIN   (JH7110_AONCLK_END + 17)
+#define JH7110_STGCLK_MTRX_GRP0_BUS    (JH7110_AONCLK_END + 18)
+#define JH7110_STGCLK_MTRX_GRP0_STG    (JH7110_AONCLK_END + 19)
+#define JH7110_STGCLK_MTRX_GRP1_MAIN   (JH7110_AONCLK_END + 20)
+#define JH7110_STGCLK_MTRX_GRP1_BUS    (JH7110_AONCLK_END + 21)
+#define JH7110_STGCLK_MTRX_GRP1_STG    (JH7110_AONCLK_END + 22)
+#define JH7110_STGCLK_MTRX_GRP1_HIFI   (JH7110_AONCLK_END + 23)
+#define JH7110_STGCLK_E2_RTC           (JH7110_AONCLK_END + 24)
+#define JH7110_STGCLK_E2_CORE          (JH7110_AONCLK_END + 25)
+#define JH7110_STGCLK_E2_DBG           (JH7110_AONCLK_END + 26)
+#define JH7110_STGCLK_DMA1P_AXI        (JH7110_AONCLK_END + 27)
+#define JH7110_STGCLK_DMA1P_AHB        (JH7110_AONCLK_END + 28)
+
+#define JH7110_STGCLK_END              (JH7110_AONCLK_END + 29)
+
+#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */

diff --git a/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
new file mode 100644 (file)
index 0000000..f273547
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
@@ -0,0 +1,427 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
+#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
+
+/*
+ * mux bits:
+ *  | 31 - 24 | 23 - 16 | 15 - 10 |  9 - 8   |  7 - 0  |
+ *  |  din    |  dout   |  doen   | function | gpio nr |
+ *
+ * dout:     output signal
+ * doen:     output enable signal
+ * din:      optional input signal, 0xff = none
+ * function:
+ * gpio nr:  gpio number, 0 - 63
+ */
+#define GPIOMUX(n, dout, doen, din) ( \
+               (((din)  & 0xff) << 24) | \
+               (((dout) & 0xff) << 16) | \
+               (((doen) & 0x3f) << 10) | \
+               ((n) & 0x3f))
+
+#define PINMUX(n, func) ((1 << 10) | (((func) & 0x3) << 8) | ((n) & 0xff))
+
+/* sys_iomux pin */
+#define        PAD_GPIO0        0
+#define        PAD_GPIO1        1
+#define        PAD_GPIO2        2
+#define        PAD_GPIO3        3
+#define        PAD_GPIO4        4
+#define        PAD_GPIO5        5
+#define        PAD_GPIO6        6
+#define        PAD_GPIO7        7
+#define        PAD_GPIO8        8
+#define        PAD_GPIO9        9
+#define        PAD_GPIO10      10
+#define        PAD_GPIO11      11
+#define        PAD_GPIO12      12
+#define        PAD_GPIO13      13
+#define        PAD_GPIO14      14
+#define        PAD_GPIO15      15
+#define        PAD_GPIO16      16
+#define        PAD_GPIO17      17
+#define        PAD_GPIO18      18
+#define        PAD_GPIO19      19
+#define        PAD_GPIO20      20
+#define        PAD_GPIO21      21
+#define        PAD_GPIO22      22
+#define        PAD_GPIO23      23
+#define        PAD_GPIO24      24
+#define        PAD_GPIO25      25
+#define        PAD_GPIO26      26
+#define        PAD_GPIO27      27
+#define        PAD_GPIO28      28
+#define        PAD_GPIO29      29
+#define        PAD_GPIO30      30
+#define        PAD_GPIO31      31
+#define        PAD_GPIO32      32
+#define        PAD_GPIO33      33
+#define        PAD_GPIO34      34
+#define        PAD_GPIO35      35
+#define        PAD_GPIO36      36
+#define        PAD_GPIO37      37
+#define        PAD_GPIO38      38
+#define        PAD_GPIO39      39
+#define        PAD_GPIO40      40
+#define        PAD_GPIO41      41
+#define        PAD_GPIO42      42
+#define        PAD_GPIO43      43
+#define        PAD_GPIO44      44
+#define        PAD_GPIO45      45
+#define        PAD_GPIO46      46
+#define        PAD_GPIO47      47
+#define        PAD_GPIO48      48
+#define        PAD_GPIO49      49
+#define        PAD_GPIO50      50
+#define        PAD_GPIO51      51
+#define        PAD_GPIO52      52
+#define        PAD_GPIO53      53
+#define        PAD_GPIO54      54
+#define        PAD_GPIO55      55
+#define        PAD_GPIO56      56
+#define        PAD_GPIO57      57
+#define        PAD_GPIO58      58
+#define        PAD_GPIO59      59
+#define        PAD_GPIO60      60
+#define        PAD_GPIO61      61
+#define        PAD_GPIO62      62
+#define        PAD_GPIO63      63
+#define        PAD_SD0_CLK     64
+#define        PAD_SD0_CMD     65
+#define        PAD_SD0_DATA0   66
+#define        PAD_SD0_DATA1   67
+#define        PAD_SD0_DATA2   68
+#define        PAD_SD0_DATA3   69
+#define        PAD_SD0_DATA4   70
+#define        PAD_SD0_DATA5   71
+#define        PAD_SD0_DATA6   72
+#define        PAD_SD0_DATA7   73
+#define        PAD_SD0_STRB    74
+#define        PAD_GMAC1_MDC   75
+#define        PAD_GMAC1_MDIO  76
+#define        PAD_GMAC1_RXD0  77
+#define        PAD_GMAC1_RXD1  78
+#define        PAD_GMAC1_RXD2  79
+#define        PAD_GMAC1_RXD3  80
+#define        PAD_GMAC1_RXDV  81
+#define        PAD_GMAC1_RXC   82
+#define        PAD_GMAC1_TXD0  83
+#define        PAD_GMAC1_TXD1  84
+#define        PAD_GMAC1_TXD2  85
+#define        PAD_GMAC1_TXD3  86
+#define        PAD_GMAC1_TXEN  87
+#define        PAD_GMAC1_TXC   88
+#define        PAD_QSPI_SCLK   89
+#define        PAD_QSPI_CS0    90
+#define        PAD_QSPI_DATA0  91
+#define        PAD_QSPI_DATA1  92
+#define        PAD_QSPI_DATA2  93
+#define        PAD_QSPI_DATA3  94
+
+/* aon_iomux pin */
+#define        PAD_TESTEN      0
+#define        PAD_RGPIO0      1
+#define        PAD_RGPIO1      2
+#define        PAD_RGPIO2      3
+#define        PAD_RGPIO3      4
+#define        PAD_RSTN        5
+#define        PAD_GMAC0_MDC   6
+#define        PAD_GMAC0_MDIO  7
+#define        PAD_GMAC0_RXD0  8
+#define        PAD_GMAC0_RXD1  9
+#define        PAD_GMAC0_RXD2  10
+#define        PAD_GMAC0_RXD3  11
+#define        PAD_GMAC0_RXDV  12
+#define        PAD_GMAC0_RXC   13
+#define        PAD_GMAC0_TXD0  14
+#define        PAD_GMAC0_TXD1  15
+#define        PAD_GMAC0_TXD2  16
+#define        PAD_GMAC0_TXD3  17
+#define        PAD_GMAC0_TXEN  18
+#define        PAD_GMAC0_TXC   19
+
+/* sys_iomux dout */
+#define GPOUT_LOW                                0
+#define GPOUT_HIGH                               1
+#define GPOUT_SYS_WAVE511_UART_TX                2
+#define GPOUT_SYS_CAN0_STBY                      3
+#define GPOUT_SYS_CAN0_TST_NEXT_BIT              4
+#define GPOUT_SYS_CAN0_TST_SAMPLE_POINT          5
+#define GPOUT_SYS_CAN0_TXD                       6
+#define GPOUT_SYS_USB_DRIVE_VBUS                 7
+#define GPOUT_SYS_QSPI_CS1                       8
+#define GPOUT_SYS_SPDIF                         9
+#define GPOUT_SYS_HDMI_CEC_SDA                  10
+#define GPOUT_SYS_HDMI_DDC_SCL                  11
+#define GPOUT_SYS_HDMI_DDC_SDA                  12
+#define GPOUT_SYS_WATCHDOG                      13
+#define GPOUT_SYS_I2C0_CLK                      14
+#define GPOUT_SYS_I2C0_DATA                     15
+#define GPOUT_SYS_SDIO0_BACK_END_POWER          16
+#define GPOUT_SYS_SDIO0_CARD_POWER_EN           17
+#define GPOUT_SYS_SDIO0_CCMD_OD_PULLUP_EN       18
+#define GPOUT_SYS_SDIO0_RST                     19
+#define GPOUT_SYS_UART0_TX                      20
+#define GPOUT_SYS_HIFI4_JTAG_TDO                21
+#define GPOUT_SYS_JTAG_TDO                      22
+#define GPOUT_SYS_PDM_MCLK                      23
+#define GPOUT_SYS_PWM_CHANNEL0                  24
+#define GPOUT_SYS_PWM_CHANNEL1                  25
+#define GPOUT_SYS_PWM_CHANNEL2                  26
+#define GPOUT_SYS_PWM_CHANNEL3                  27
+#define GPOUT_SYS_PWMDAC_LEFT                   28
+#define GPOUT_SYS_PWMDAC_RIGHT                  29
+#define GPOUT_SYS_SPI0_CLK                      30
+#define GPOUT_SYS_SPI0_FSS                      31
+#define GPOUT_SYS_SPI0_TXD                      32
+#define GPOUT_SYS_GMAC_PHYCLK                   33
+#define GPOUT_SYS_I2SRX_BCLK                    34
+#define GPOUT_SYS_I2SRX_LRCK                    35
+#define GPOUT_SYS_I2STX0_BCLK                   36
+#define GPOUT_SYS_I2STX0_LRCK                   37
+#define GPOUT_SYS_MCLK                          38
+#define GPOUT_SYS_TDM_CLK                       39
+#define GPOUT_SYS_TDM_SYNC                      40
+#define GPOUT_SYS_TDM_TXD                       41
+#define GPOUT_SYS_TRACE_DATA0                   42
+#define GPOUT_SYS_TRACE_DATA1                   43
+#define GPOUT_SYS_TRACE_DATA2                   44
+#define GPOUT_SYS_TRACE_DATA3                   45
+#define GPOUT_SYS_TRACE_REF                     46
+#define GPOUT_SYS_CAN1_STBY                     47
+#define GPOUT_SYS_CAN1_TST_NEXT_BIT             48
+#define GPOUT_SYS_CAN1_TST_SAMPLE_POINT         49
+#define GPOUT_SYS_CAN1_TXD                      50
+#define GPOUT_SYS_I2C1_CLK                      51
+#define GPOUT_SYS_I2C1_DATA                     52
+#define GPOUT_SYS_SDIO1_BACK_END_POWER          53
+#define GPOUT_SYS_SDIO1_CARD_POWER_EN           54
+#define GPOUT_SYS_SDIO1_CLK                     55
+#define GPOUT_SYS_SDIO1_CMD_OD_PULLUP_EN        56
+#define GPOUT_SYS_SDIO1_CMD                     57
+#define GPOUT_SYS_SDIO1_DATA0                   58
+#define GPOUT_SYS_SDIO1_DATA1                   59
+#define GPOUT_SYS_SDIO1_DATA2                   60
+#define GPOUT_SYS_SDIO1_DATA3                   61
+#define GPOUT_SYS_SDIO1_DATA4                   63
+#define GPOUT_SYS_SDIO1_DATA5                   63
+#define GPOUT_SYS_SDIO1_DATA6                   64
+#define GPOUT_SYS_SDIO1_DATA7                   65
+#define GPOUT_SYS_SDIO1_RST                     66
+#define GPOUT_SYS_UART1_RTS                     67
+#define GPOUT_SYS_UART1_TX                      68
+#define GPOUT_SYS_I2STX1_SDO0                   69
+#define GPOUT_SYS_I2STX1_SDO1                   70
+#define GPOUT_SYS_I2STX1_SDO2                   71
+#define GPOUT_SYS_I2STX1_SDO3                   72
+#define GPOUT_SYS_SPI1_CLK                      73
+#define GPOUT_SYS_SPI1_FSS                      74
+#define GPOUT_SYS_SPI1_TXD                      75
+#define GPOUT_SYS_I2C2_CLK                      76
+#define GPOUT_SYS_I2C2_DATA                     77
+#define GPOUT_SYS_UART2_RTS                     78
+#define GPOUT_SYS_UART2_TX                      79
+#define GPOUT_SYS_SPI2_CLK                      80
+#define GPOUT_SYS_SPI2_FSS                      81
+#define GPOUT_SYS_SPI2_TXD                      82
+#define GPOUT_SYS_I2C3_CLK                      83
+#define GPOUT_SYS_I2C3_DATA                     84
+#define GPOUT_SYS_UART3_TX                      85
+#define GPOUT_SYS_SPI3_CLK                      86
+#define GPOUT_SYS_SPI3_FSS                      87
+#define GPOUT_SYS_SPI3_TXD                      88
+#define GPOUT_SYS_I2C4_CLK                      89
+#define GPOUT_SYS_I2C4_DATA                     90
+#define GPOUT_SYS_UART4_RTS                     91
+#define GPOUT_SYS_UART4_TX                      92
+#define GPOUT_SYS_SPI4_CLK                      93
+#define GPOUT_SYS_SPI4_FSS                      94
+#define GPOUT_SYS_SPI4_TXD                      95
+#define GPOUT_SYS_I2C5_CLK                      96
+#define GPOUT_SYS_I2C5_DATA                     97
+#define GPOUT_SYS_UART5_RTS                     98
+#define GPOUT_SYS_UART5_TX                      99
+#define GPOUT_SYS_SPI5_CLK                     100
+#define GPOUT_SYS_SPI5_FSS                     101
+#define GPOUT_SYS_SPI5_TXD                     102
+#define GPOUT_SYS_I2C6_CLK                     103
+#define GPOUT_SYS_I2C6_DATA                    104
+#define GPOUT_SYS_SPI6_CLK                     105
+#define GPOUT_SYS_SPI6_FSS                     106
+#define GPOUT_SYS_SPI6_TXD                     107
+
+/* aon_iomux dout */
+#define GPOUT_AON_CLK_32K_OUT                  2
+#define GPOUT_AON_PTC0_PWM4                    3
+#define GPOUT_AON_PTC0_PWM5                    4
+#define GPOUT_AON_PTC0_PWM6                    5
+#define GPOUT_AON_PTC0_PWM7                    6
+#define GPOUT_AON_CLK_GCLK0                    7
+#define GPOUT_AON_CLK_GCLK1                    8
+#define GPOUT_AON_CLK_GCLK2                    9
+
+/* sys_iomux doen */
+#define GPOEN_ENABLE                            0
+#define GPOEN_DISABLE                           1
+#define GPOEN_SYS_HDMI_CEC_SDA                  2
+#define GPOEN_SYS_HDMI_DDC_SCL                  3
+#define GPOEN_SYS_HDMI_DDC_SDA                  4
+#define GPOEN_SYS_I2C0_CLK                      5
+#define GPOEN_SYS_I2C0_DATA                     6
+#define GPOEN_SYS_HIFI4_JTAG_TDO                7
+#define GPOEN_SYS_JTAG_TDO                      8
+#define GPOEN_SYS_PWM0_CHANNEL0                9
+#define GPOEN_SYS_PWM0_CHANNEL1                10
+#define GPOEN_SYS_PWM0_CHANNEL2                11
+#define GPOEN_SYS_PWM0_CHANNEL3                12
+#define GPOEN_SYS_SPI0_NSSPCTL                 13
+#define GPOEN_SYS_SPI0_NSSP                    14
+#define GPOEN_SYS_TDM_SYNC                     15
+#define GPOEN_SYS_TDM_TXD                      16
+#define GPOEN_SYS_I2C1_CLK                     17
+#define GPOEN_SYS_I2C1_DATA                    18
+#define GPOEN_SYS_SDIO1_CMD                    19
+#define GPOEN_SYS_SDIO1_DATA0                  20
+#define GPOEN_SYS_SDIO1_DATA1                  21
+#define GPOEN_SYS_SDIO1_DATA2                  22
+#define GPOEN_SYS_SDIO1_DATA3                  23
+#define GPOEN_SYS_SDIO1_DATA4                  24
+#define GPOEN_SYS_SDIO1_DATA5                  25
+#define GPOEN_SYS_SDIO1_DATA6                  26
+#define GPOEN_SYS_SDIO1_DATA7                  27
+#define GPOEN_SYS_SPI1_NSSPCTL                 28
+#define GPOEN_SYS_SPI1_NSSP                    29
+#define GPOEN_SYS_I2C2_CLK                     30
+#define GPOEN_SYS_I2C2_DATA                    31
+#define GPOEN_SYS_SPI2_NSSPCTL                 32
+#define GPOEN_SYS_SPI2_NSSP                    33
+#define GPOEN_SYS_I2C3_CLK                     34
+#define GPOEN_SYS_I2C3_DATA                    35
+#define GPOEN_SYS_SPI3_NSSPCTL                 36
+#define GPOEN_SYS_SPI3_NSSP                    37
+#define GPOEN_SYS_I2C4_CLK                     38
+#define GPOEN_SYS_I2C4_DATA                    39
+#define GPOEN_SYS_SPI4_NSSPCTL                 40
+#define GPOEN_SYS_SPI4_NSSP                    41
+#define GPOEN_SYS_I2C5_CLK                     42
+#define GPOEN_SYS_I2C5_DATA                    43
+#define GPOEN_SYS_SPI5_NSSPCTL                 44
+#define GPOEN_SYS_SPI5_NSSP                    45
+#define GPOEN_SYS_I2C6_CLK                     46
+#define GPOEN_SYS_I2C6_DATA                    47
+#define GPOEN_SYS_SPI6_NSSPCTL                 48
+#define GPOEN_SYS_SPI6_NSSP                    49
+
+/* aon_iomux doen */
+#define GPOEN_AON_PTC0_OE_N_4                  2
+#define GPOEN_AON_PTC0_OE_N_5                  3
+#define GPOEN_AON_PTC0_OE_N_6                  4
+#define GPOEN_AON_PTC0_OE_N_7                  5
+
+/* sys_iomux gin */
+#define GPI_NONE                               255
+
+#define GPI_SYS_WAVE511_UART_RX                 0
+#define GPI_SYS_CAN0_RXD                        1
+#define GPI_SYS_USB_OVERCURRENT                 2
+#define GPI_SYS_SPDIF                           3
+#define GPI_SYS_JTAG_RST                        4
+#define GPI_SYS_HDMI_CEC_SDA                    5
+#define GPI_SYS_HDMI_DDC_SCL                    6
+#define GPI_SYS_HDMI_DDC_SDA                    7
+#define GPI_SYS_HDMI_HPD                        8
+#define GPI_SYS_I2C0_CLK                        9
+#define GPI_SYS_I2C0_DATA                      10
+#define GPI_SYS_SDIO0_CD                       11
+#define GPI_SYS_SDIO0_INT                      12
+#define GPI_SYS_SDIO0_WP                       13
+#define GPI_SYS_UART0_RX                       14
+#define GPI_SYS_HIFI4_JTAG_TCK                 15
+#define GPI_SYS_HIFI4_JTAG_TDI                 16
+#define GPI_SYS_HIFI4_JTAG_TMS                 17
+#define GPI_SYS_HIFI4_JTAG_RST                 18
+#define GPI_SYS_JTAG_TDI                       19
+#define GPI_SYS_JTAG_TMS                       20
+#define GPI_SYS_PDM_DMIC0                      21
+#define GPI_SYS_PDM_DMIC1                      22
+#define GPI_SYS_I2SRX_SDIN0                    23
+#define GPI_SYS_I2SRX_SDIN1                    24
+#define GPI_SYS_I2SRX_SDIN2                    25
+#define GPI_SYS_SPI0_CLK                       26
+#define GPI_SYS_SPI0_FSS                       27
+#define GPI_SYS_SPI0_RXD                       28
+#define GPI_SYS_JTAG_TCK                       29
+#define GPI_SYS_MCLK_EXT                       30
+#define GPI_SYS_I2SRX_BCLK                     31
+#define GPI_SYS_I2SRX_LRCK                     32
+#define GPI_SYS_I2STX0_BCLK                    33
+#define GPI_SYS_I2STX0_LRCK                    34
+#define GPI_SYS_TDM_CLK                        35
+#define GPI_SYS_TDM_RXD                        36
+#define GPI_SYS_TDM_SYNC                       37
+#define GPI_SYS_CAN1_RXD                       38
+#define GPI_SYS_I2C1_CLK                       39
+#define GPI_SYS_I2C1_DATA                      40
+#define GPI_SYS_SDIO1_CD                       41
+#define GPI_SYS_SDIO1_INT                      42
+#define GPI_SYS_SDIO1_WP                       43
+#define GPI_SYS_SDIO1_CMD                      44
+#define GPI_SYS_SDIO1_DATA0                    45
+#define GPI_SYS_SDIO1_DATA1                    46
+#define GPI_SYS_SDIO1_DATA2                    47
+#define GPI_SYS_SDIO1_DATA3                    48
+#define GPI_SYS_SDIO1_DATA4                    49
+#define GPI_SYS_SDIO1_DATA5                    50
+#define GPI_SYS_SDIO1_DATA6                    51
+#define GPI_SYS_SDIO1_DATA7                    52
+#define GPI_SYS_SDIO1_STRB                     53
+#define GPI_SYS_UART1_CTS                      54
+#define GPI_SYS_UART1_RX                       55
+#define GPI_SYS_SPI1_CLK                       56
+#define GPI_SYS_SPI1_FSS                       57
+#define GPI_SYS_SPI1_RXD                       58
+#define GPI_SYS_I2C2_CLK                       59
+#define GPI_SYS_I2C2_DATA                      60
+#define GPI_SYS_UART2_CTS                      61
+#define GPI_SYS_UART2_RX                       62
+#define GPI_SYS_SPI2_CLK                       63
+#define GPI_SYS_SPI2_FSS                       64
+#define GPI_SYS_SPI2_RXD                       65
+#define GPI_SYS_I2C3_CLK                       66
+#define GPI_SYS_I2C3_DATA                      67
+#define GPI_SYS_UART3_RX                       68
+#define GPI_SYS_SPI3_CLK                       69
+#define GPI_SYS_SPI3_FSS                       70
+#define GPI_SYS_SPI3_RXD                       71
+#define GPI_SYS_I2C4_CLK                       72
+#define GPI_SYS_I2C4_DATA                      73
+#define GPI_SYS_UART4_CTS                      74
+#define GPI_SYS_UART4_RX                       75
+#define GPI_SYS_SPI4_CLK                       76
+#define GPI_SYS_SPI4_FSS                       77
+#define GPI_SYS_SPI4_RXD                       78
+#define GPI_SYS_I2C5_CLK                       79
+#define GPI_SYS_I2C5_DATA                      80
+#define GPI_SYS_UART5_CTS                      81
+#define GPI_SYS_UART5_RX                       82
+#define GPI_SYS_SPI5_CLK                       83
+#define GPI_SYS_SPI5_FSS                       84
+#define GPI_SYS_SPI5_RXD                       85
+#define GPI_SYS_I2C6_CLK                       86
+#define GPI_SYS_I2C6_DATA                      87
+#define GPI_SYS_SPI6_CLK                       88
+#define GPI_SYS_SPI6_FSS                       89
+#define GPI_SYS_SPI6_RXD                       90
+
+/* aon_iomux gin */
+#define GPI_AON_PMU_GPIO_WAKEUP_0              0
+#define GPI_AON_PMU_GPIO_WAKEUP_1              1
+#define GPI_AON_PMU_GPIO_WAKEUP_2              2
+#define GPI_AON_PMU_GPIO_WAKEUP_3              3
+
+#endif

diff --git a/include/dt-bindings/power/r8a779f0-sysc.h b/include/dt-bindings/power/r8a779f0-sysc.h
new file mode 100644 (file)
index 0000000..0ec8ad7
--- /dev/null
+++ b/include/dt-bindings/power/r8a779f0-sysc.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
+/*
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A779F0_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A779F0_SYSC_H__
+
+/*
+ * These power domain indices match the Power Domain Register Numbers (PDR)
+ */
+
+#define R8A779F0_PD_A1E0D0C0           0
+#define R8A779F0_PD_A1E0D0C1           1
+#define R8A779F0_PD_A1E0D1C0           2
+#define R8A779F0_PD_A1E0D1C1           3
+#define R8A779F0_PD_A1E1D0C0           4
+#define R8A779F0_PD_A1E1D0C1           5
+#define R8A779F0_PD_A1E1D1C0           6
+#define R8A779F0_PD_A1E1D1C1           7
+#define R8A779F0_PD_A2E0D0             16
+#define R8A779F0_PD_A2E0D1             17
+#define R8A779F0_PD_A2E1D0             18
+#define R8A779F0_PD_A2E1D1             19
+#define R8A779F0_PD_A3E0               20
+#define R8A779F0_PD_A3E1               21
+
+/* Always-on power area */
+#define R8A779F0_PD_ALWAYS_ON          64
+
+#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__*/

diff --git a/include/dt-bindings/power/r8a779g0-sysc.h b/include/dt-bindings/power/r8a779g0-sysc.h
new file mode 100644 (file)
index 0000000..c7b139f
--- /dev/null
+++ b/include/dt-bindings/power/r8a779g0-sysc.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
+
+/*
+ * These power domain indices match the Power Domain Register Numbers (PDR)
+ */
+
+#define R8A779G0_PD_A1E0D0C0           0
+#define R8A779G0_PD_A1E0D0C1           1
+#define R8A779G0_PD_A1E0D1C0           2
+#define R8A779G0_PD_A1E0D1C1           3
+#define R8A779G0_PD_A2E0D0             16
+#define R8A779G0_PD_A2E0D1             17
+#define R8A779G0_PD_A3E0               20
+#define R8A779G0_PD_A33DGA             24
+#define R8A779G0_PD_A23DGB             25
+#define R8A779G0_PD_A1DSP0             33
+#define R8A779G0_PD_A2IMP01            34
+#define R8A779G0_PD_A2PSC              35
+#define R8A779G0_PD_A2CV0              36
+#define R8A779G0_PD_A2CV1              37
+#define R8A779G0_PD_A1CNN0             41
+#define R8A779G0_PD_A2CN0              42
+#define R8A779G0_PD_A3IR               43
+#define R8A779G0_PD_A1DSP1             45
+#define R8A779G0_PD_A2IMP23            46
+#define R8A779G0_PD_A2DMA              47
+#define R8A779G0_PD_A2CV2              48
+#define R8A779G0_PD_A2CV3              49
+#define R8A779G0_PD_A1DSP2             53
+#define R8A779G0_PD_A1DSP3             54
+#define R8A779G0_PD_A3VIP0             56
+#define R8A779G0_PD_A3VIP1             57
+#define R8A779G0_PD_A3VIP2             58
+#define R8A779G0_PD_A3ISP0             60
+#define R8A779G0_PD_A3ISP1             61
+#define R8A779G0_PD_A3DUL              62
+
+/* Always-on power area */
+#define R8A779G0_PD_ALWAYS_ON          64
+
+#endif /* __DT_BINDINGS_POWER_R8A779G0_SYSC_H__*/

diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h
new file mode 100644 (file)
index 0000000..1d59658
--- /dev/null
+++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
@@ -0,0 +1,183 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ *
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ */
+
+#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
+#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
+
+/* SYSCRG resets */
+#define JH7110_SYSRST_JTAG2APB                 0
+#define JH7110_SYSRST_SYSCON                   1
+#define JH7110_SYSRST_IOMUX_APB                2
+#define JH7110_SYSRST_BUS                      3
+#define JH7110_SYSRST_DEBUG                    4
+#define JH7110_SYSRST_CORE0                    5
+#define JH7110_SYSRST_CORE1                    6
+#define JH7110_SYSRST_CORE2                    7
+#define JH7110_SYSRST_CORE3                    8
+#define JH7110_SYSRST_CORE4                    9
+#define JH7110_SYSRST_CORE0_ST                 10
+#define JH7110_SYSRST_CORE1_ST                 11
+#define JH7110_SYSRST_CORE2_ST                 12
+#define JH7110_SYSRST_CORE3_ST                 13
+#define JH7110_SYSRST_CORE4_ST                 14
+#define JH7110_SYSRST_TRACE0                   15
+#define JH7110_SYSRST_TRACE1                   16
+#define JH7110_SYSRST_TRACE2                   17
+#define JH7110_SYSRST_TRACE3                   18
+#define JH7110_SYSRST_TRACE4                   19
+#define JH7110_SYSRST_TRACE_COM                20
+#define JH7110_SYSRST_GPU_APB                  21
+#define JH7110_SYSRST_GPU_DOMA                 22
+#define JH7110_SYSRST_NOC_BUS_APB_BUS          23
+#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI      24
+#define JH7110_SYSRST_NOC_BUS_CPU_AXI          25
+#define JH7110_SYSRST_NOC_BUS_DISP_AXI         26
+#define JH7110_SYSRST_NOC_BUS_GPU_AXI          27
+#define JH7110_SYSRST_NOC_BUS_ISP_AXI          28
+#define JH7110_SYSRST_NOC_BUS_DDRC             29
+#define JH7110_SYSRST_NOC_BUS_STG_AXI          30
+#define JH7110_SYSRST_NOC_BUS_VDEC_AXI         31
+
+#define JH7110_SYSRST_NOC_BUS_VENC_AXI         32
+#define JH7110_SYSRST_AXI_CFG1_DEC_AHB         33
+#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN        34
+#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN        35
+#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV    36
+#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4       37
+#define JH7110_SYSRST_DDR_AXI                  38
+#define JH7110_SYSRST_DDR_OSC                  39
+#define JH7110_SYSRST_DDR_APB                  40
+#define JH7110_SYSRST_DOM_ISP_TOP_N            41
+#define JH7110_SYSRST_DOM_ISP_TOP_AXI          42
+#define JH7110_SYSRST_DOM_VOUT_TOP_SRC         43
+#define JH7110_SYSRST_CODAJ12_AXI              44
+#define JH7110_SYSRST_CODAJ12_CORE             45
+#define JH7110_SYSRST_CODAJ12_APB              46
+#define JH7110_SYSRST_WAVE511_AXI              47
+#define JH7110_SYSRST_WAVE511_BPU              48
+#define JH7110_SYSRST_WAVE511_VCE              49
+#define JH7110_SYSRST_WAVE511_APB              50
+#define JH7110_SYSRST_VDEC_JPG_ARB_JPG         51
+#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN        52
+#define JH7110_SYSRST_AXIMEM0_AXI              53
+#define JH7110_SYSRST_WAVE420L_AXI             54
+#define JH7110_SYSRST_WAVE420L_BPU             55
+#define JH7110_SYSRST_WAVE420L_VCE             56
+#define JH7110_SYSRST_WAVE420L_APB             57
+#define JH7110_SYSRST_AXIMEM1_AXI              58
+#define JH7110_SYSRST_AXIMEM2_AXI              59
+#define JH7110_SYSRST_INTMEM                   60
+#define JH7110_SYSRST_QSPI_AHB                 61
+#define JH7110_SYSRST_QSPI_APB                 62
+#define JH7110_SYSRST_QSPI_REF                 63
+
+#define JH7110_SYSRST_SDIO0_AHB                64
+#define JH7110_SYSRST_SDIO1_AHB                65
+#define JH7110_SYSRST_GMAC1_AXI                66
+#define JH7110_SYSRST_GMAC1_AHB                67
+#define JH7110_SYSRST_MAILBOX                  68
+#define JH7110_SYSRST_SPI0_APB                 69
+#define JH7110_SYSRST_SPI1_APB                 70
+#define JH7110_SYSRST_SPI2_APB                 71
+#define JH7110_SYSRST_SPI3_APB                 72
+#define JH7110_SYSRST_SPI4_APB                 73
+#define JH7110_SYSRST_SPI5_APB                 74
+#define JH7110_SYSRST_SPI6_APB                 75
+#define JH7110_SYSRST_I2C0_APB                 76
+#define JH7110_SYSRST_I2C1_APB                 77
+#define JH7110_SYSRST_I2C2_APB                 78
+#define JH7110_SYSRST_I2C3_APB                 79
+#define JH7110_SYSRST_I2C4_APB                 80
+#define JH7110_SYSRST_I2C5_APB                 81
+#define JH7110_SYSRST_I2C6_APB                 82
+#define JH7110_SYSRST_UART0_APB                83
+#define JH7110_SYSRST_UART0_CORE               84
+#define JH7110_SYSRST_UART1_APB                85
+#define JH7110_SYSRST_UART1_CORE               86
+#define JH7110_SYSRST_UART2_APB                87
+#define JH7110_SYSRST_UART2_CORE               88
+#define JH7110_SYSRST_UART3_APB                89
+#define JH7110_SYSRST_UART3_CORE               90
+#define JH7110_SYSRST_UART4_APB                91
+#define JH7110_SYSRST_UART4_CORE               92
+#define JH7110_SYSRST_UART5_APB                93
+#define JH7110_SYSRST_UART5_CORE               94
+#define JH7110_SYSRST_SPDIF_APB                95
+
+#define JH7110_SYSRST_PWMDAC_APB               96
+#define JH7110_SYSRST_PDM_DMIC                 97
+#define JH7110_SYSRST_PDM_APB                  98
+#define JH7110_SYSRST_I2SRX_APB                99
+#define JH7110_SYSRST_I2SRX_BCLK               100
+#define JH7110_SYSRST_I2STX0_APB               101
+#define JH7110_SYSRST_I2STX0_BCLK              102
+#define JH7110_SYSRST_I2STX1_APB               103
+#define JH7110_SYSRST_I2STX1_BCLK              104
+#define JH7110_SYSRST_TDM_AHB                  105
+#define JH7110_SYSRST_TDM_CORE                 106
+#define JH7110_SYSRST_TDM_APB                  107
+#define JH7110_SYSRST_PWM_APB                  108
+#define JH7110_SYSRST_WDT_APB                  109
+#define JH7110_SYSRST_WDT_CORE                 110
+#define JH7110_SYSRST_CAN0_APB                 111
+#define JH7110_SYSRST_CAN0_CORE                112
+#define JH7110_SYSRST_CAN0_TIMER               113
+#define JH7110_SYSRST_CAN1_APB                 114
+#define JH7110_SYSRST_CAN1_CORE                115
+#define JH7110_SYSRST_CAN1_TIMER               116
+#define JH7110_SYSRST_TIMER_APB                117
+#define JH7110_SYSRST_TIMER0                   118
+#define JH7110_SYSRST_TIMER1                   119
+#define JH7110_SYSRST_TIMER2                   120
+#define JH7110_SYSRST_TIMER3                   121
+#define JH7110_SYSRST_INT_CTRL_APB             122
+#define JH7110_SYSRST_TEMP_APB                 123
+#define JH7110_SYSRST_TEMP_CORE                124
+#define JH7110_SYSRST_JTAG_CERTIFICATION       125
+
+#define JH7110_SYSRST_END                      126
+
+/* AONCRG resets */
+#define JH7110_AONRST_GMAC0_AXI                0
+#define JH7110_AONRST_GMAC0_AHB                1
+#define JH7110_AONRST_IOMUX                    2
+#define JH7110_AONRST_PMU_APB                  3
+#define JH7110_AONRST_PMU_WKUP                 4
+#define JH7110_AONRST_RTC_APB                  5
+#define JH7110_AONRST_RTC_CAL                  6
+#define JH7110_AONRST_RTC_32K                  7
+
+#define JH7110_AONRST_END                      8
+
+/* STGCRG resets */
+#define JH7110_STGRST_SYSCON_PRESETN           0
+#define JH7110_STGRST_HIFI4_CORE               1
+#define JH7110_STGRST_HIFI4_AXI                2
+#define JH7110_STGRST_SEC_TOP_HRESETN          3
+#define JH7110_STGRST_E24_CORE                 4
+#define JH7110_STGRST_DMA1P_AXI                5
+#define JH7110_STGRST_DMA1P_AHB                6
+#define JH7110_STGRST_USB_AXI                  7
+#define JH7110_STGRST_USB_APB                  8
+#define JH7110_STGRST_USB_UTMI_APB             9
+#define JH7110_STGRST_USB_PWRUP                10
+#define JH7110_STGRST_PCIE0_MST0               11
+#define JH7110_STGRST_PCIE0_SLV0               12
+#define JH7110_STGRST_PCIE0_SLV                13
+#define JH7110_STGRST_PCIE0_BRG                14
+#define JH7110_STGRST_PCIE0_CORE               15
+#define JH7110_STGRST_PCIE0_APB                16
+#define JH7110_STGRST_PCIE1_MST0               17
+#define JH7110_STGRST_PCIE1_SLV0               18
+#define JH7110_STGRST_PCIE1_SLV                19
+#define JH7110_STGRST_PCIE1_BRG                20
+#define JH7110_STGRST_PCIE1_CORE               21
+#define JH7110_STGRST_PCIE1_APB                22
+
+#define JH7110_STGRST_END                      23
+
+#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */

diff --git a/include/efi_api.h b/include/efi_api.h
index c4512ee..2fd0221 100644 (file)
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -604,6 +604,7 @@ struct efi_device_path_acpi_path {
 #  define DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR    0x0b
 #  define DEVICE_PATH_SUB_TYPE_MSG_UART                0x0e
 #  define DEVICE_PATH_SUB_TYPE_MSG_USB_CLASS   0x0f
+#  define DEVICE_PATH_SUB_TYPE_MSG_USB_WWI     0x10
 #  define DEVICE_PATH_SUB_TYPE_MSG_SATA                0x12
 #  define DEVICE_PATH_SUB_TYPE_MSG_NVME                0x17
 #  define DEVICE_PATH_SUB_TYPE_MSG_URI         0x18
@@ -1172,7 +1173,7 @@ struct efi_hii_keyboard_layout {
        efi_guid_t guid;
        u32 layout_descriptor_string_offset;
        u8 descriptor_count;
-       struct efi_key_descriptor descriptors[];
+       /* struct efi_key_descriptor descriptors[]; follows here */
 } __packed;
 
 struct efi_hii_keyboard_package {

diff --git a/include/efi_loader.h b/include/efi_loader.h
index cee04cb..b395eef 100644 (file)
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -134,6 +134,10 @@ static inline efi_status_t efi_launch_capsules(void)
 #define U_BOOT_GUID \
        EFI_GUID(0xe61d73b9, 0xa384, 0x4acc, \
                 0xae, 0xab, 0x82, 0xe8, 0x28, 0xf3, 0x62, 0x8b)
+/* GUID used as root for blkmap devices */
+#define U_BOOT_BLKMAP_DEV_GUID \
+       EFI_GUID(0x4cad859d, 0xd644, 0x42ff,    \
+                0x87, 0x0b, 0xc0, 0x2e, 0xac, 0x05, 0x58, 0x63)
 /* GUID used as host device on sandbox */
 #define U_BOOT_HOST_DEV_GUID \
        EFI_GUID(0xbbe4e671, 0x5773, 0x4ea1, \
@@ -509,9 +513,6 @@ struct efi_register_notify_event {
        struct list_head handles;
 };
 
-/* List of all events registered by RegisterProtocolNotify() */
-extern struct list_head efi_register_notify_events;
-
 /* called at pre-initialization */
 int efi_init_early(void);
 /* Initialize efi execution environment */

diff --git a/include/faraday/ftwdt010_wdt.h b/include/faraday/ftwdt010_wdt.h
index 804907d..d4c11e3 100644 (file)
--- a/include/faraday/ftwdt010_wdt.h
+++ b/include/faraday/ftwdt010_wdt.h
@@ -89,7 +89,4 @@ struct ftwdt010_wdt {
  */
 #define FTWDT010_TIMEOUT_FACTOR                (get_board_sys_clk() / 1000) /* 1 ms */
 
-void ftwdt010_wdt_reset(void);
-void ftwdt010_wdt_disable(void);
-
 #endif /* __FTWDT010_H */

diff --git a/include/fdt_simplefb.h b/include/fdt_simplefb.h
index 41cd740..af93e3b 100644 (file)
--- a/include/fdt_simplefb.h
+++ b/include/fdt_simplefb.h
@@ -9,6 +9,5 @@
 #ifndef _FDT_SIMPLEFB_H_
 #define _FDT_SIMPLEFB_H_
 int fdt_simplefb_add_node(void *blob);
-int fdt_simplefb_enable_existing_node(void *blob);
 int fdt_simplefb_enable_and_mem_rsv(void *blob);
 #endif

diff --git a/include/generic-phy.h b/include/generic-phy.h
index f8eddef..bee4de8 100644 (file)
--- a/include/generic-phy.h
+++ b/include/generic-phy.h
@@ -11,6 +11,29 @@
 
 struct ofnode_phandle_args;
 
+enum phy_mode {
+       PHY_MODE_INVALID,
+       PHY_MODE_USB_HOST,
+       PHY_MODE_USB_HOST_LS,
+       PHY_MODE_USB_HOST_FS,
+       PHY_MODE_USB_HOST_HS,
+       PHY_MODE_USB_HOST_SS,
+       PHY_MODE_USB_DEVICE,
+       PHY_MODE_USB_DEVICE_LS,
+       PHY_MODE_USB_DEVICE_FS,
+       PHY_MODE_USB_DEVICE_HS,
+       PHY_MODE_USB_DEVICE_SS,
+       PHY_MODE_USB_OTG,
+       PHY_MODE_UFS_HS_A,
+       PHY_MODE_UFS_HS_B,
+       PHY_MODE_PCIE,
+       PHY_MODE_ETHERNET,
+       PHY_MODE_MIPI_DPHY,
+       PHY_MODE_SATA,
+       PHY_MODE_LVDS,
+       PHY_MODE_DP
+};
+
 /**
  * struct phy - A handle to (allowing control of) a single phy port.
  *
@@ -69,73 +92,99 @@ struct phy_ops {
        int     (*init)(struct phy *phy);
 
        /**
-       * exit - de-initialize the PHY device
-       *
-       * Hardware de-intialization should be done here. Every step done in
-       * init() should be undone here.
-       * This could be used to suspend the phy to reduce power consumption or
-       * to put the phy in a known condition before booting the OS (though it
-       * is NOT called automatically before booting the OS)
-       * If power_off() is not implemented, it must power down the phy.
-       *
-       * @phy: PHY port to be de-initialized
-       * Return: 0 if OK, or a negative error code
-       */
+        * exit - de-initialize the PHY device
+        *
+        * Hardware de-intialization should be done here. Every step done in
+        * init() should be undone here.
+        * This could be used to suspend the phy to reduce power consumption or
+        * to put the phy in a known condition before booting the OS (though it
+        * is NOT called automatically before booting the OS)
+        * If power_off() is not implemented, it must power down the phy.
+        *
+        * @phy:        PHY port to be de-initialized
+        * Return: 0 if OK, or a negative error code
+        */
        int     (*exit)(struct phy *phy);
 
        /**
-       * reset - resets a PHY device without shutting down
-       *
-       * @phy: PHY port to be reset
-       *
-       * During runtime, the PHY may need to be reset in order to
-       * re-establish connection etc without being shut down or exit.
-       *
-       * Return: 0 if OK, or a negative error code
-       */
+        * reset - resets a PHY device without shutting down
+        *
+        * @phy:        PHY port to be reset
+        *
+        * During runtime, the PHY may need to be reset in order to
+        * re-establish connection etc without being shut down or exit.
+        *
+        * Return: 0 if OK, or a negative error code
+        */
        int     (*reset)(struct phy *phy);
 
        /**
-       * power_on - power on a PHY device
-       *
-       * @phy: PHY port to be powered on
-       *
-       * During runtime, the PHY may need to be powered on or off several
-       * times. This function is used to power on the PHY. It relies on the
-       * setup done in init(). If init() is not implemented, it must take care
-       * of setting up the context (PLLs, ...)
-       *
-       * Return: 0 if OK, or a negative error code
-       */
+        * power_on - power on a PHY device
+        *
+        * @phy:        PHY port to be powered on
+        *
+        * During runtime, the PHY may need to be powered on or off several
+        * times. This function is used to power on the PHY. It relies on the
+        * setup done in init(). If init() is not implemented, it must take care
+        * of setting up the context (PLLs, ...)
+        *
+        * Return: 0 if OK, or a negative error code
+        */
        int     (*power_on)(struct phy *phy);
 
        /**
-       * power_off - power off a PHY device
-       *
-       * @phy: PHY port to be powered off
-       *
-       * During runtime, the PHY may need to be powered on or off several
-       * times. This function is used to power off the PHY. Except if
-       * init()/deinit() are not implemented, it must not de-initialize
-       * everything.
-       *
-       * Return: 0 if OK, or a negative error code
-       */
+        * power_off - power off a PHY device
+        *
+        * @phy:        PHY port to be powered off
+        *
+        * During runtime, the PHY may need to be powered on or off several
+        * times. This function is used to power off the PHY. Except if
+        * init()/deinit() are not implemented, it must not de-initialize
+        * everything.
+        *
+        * Return: 0 if OK, or a negative error code
+        */
        int     (*power_off)(struct phy *phy);
 
        /**
-       * configure - configure a PHY device
-       *
-       * @phy: PHY port to be configured
-       * @params: PHY Parameters, underlying data is specific to the PHY function
-       *
-       * During runtime, the PHY may need to be configured for it's main function.
-       * This function configures the PHY for it's main function following
-       * power_on/off() after beeing initialized.
-       *
-       * Return: 0 if OK, or a negative error code
-       */
+        * configure - configure a PHY device
+        *
+        * @phy:        PHY port to be configured
+        * @params: PHY Parameters, underlying data is specific to the PHY function
+        *
+        * During runtime, the PHY may need to be configured for it's main function.
+        * This function configures the PHY for it's main function following
+        * power_on/off() after being initialized.
+        *
+        * Return: 0 if OK, or a negative error code
+        */
        int     (*configure)(struct phy *phy, void *params);
+
+       /**
+        * set_mode - set PHY device mode
+        *
+        * @phy:        PHY port to be configured
+        * @mode: PHY mode
+        * @submode: PHY submode
+        *
+        * Configure PHY mode (e.g. USB, Ethernet, ...) and submode
+        * (e.g. for Ethernet this can be RGMII).
+        *
+        * Return: 0 if OK, or a negative error code
+        */
+       int     (*set_mode)(struct phy *phy, enum phy_mode mode, int submode);
+
+       /**
+        * set_speed - set PHY device speed
+        *
+        * @phy:        PHY port to be configured
+        * @speed: PHY speed
+        *
+        * Configure PHY speed (e.g. for Ethernet, this could be 10 or 100 ...).
+        *
+        * Return: 0 if OK, or a negative error code
+        */
+       int     (*set_speed)(struct phy *phy, int speed);
 };
 
 /**
@@ -206,6 +255,24 @@ int generic_phy_power_off(struct phy *phy);
  */
 int generic_phy_configure(struct phy *phy, void *params);
 
+/**
+ * generic_phy_set_mode() - set PHY device mode
+ *
+ * @phy:       PHY port to be configured
+ * @mode: PHY mode
+ * @submode: PHY submode
+ * Return: 0 if OK, or a negative error code
+ */
+int generic_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode);
+
+/**
+ * generic_phy_set_speed() - set PHY device speed
+ *
+ * @phy:       PHY port to be configured
+ * @speed: PHY speed
+ * Return: 0 if OK, or a negative error code
+ */
+int generic_phy_set_speed(struct phy *phy, int speed);
 
 /**
  * generic_phy_get_by_index() - Get a PHY device by integer index.
@@ -389,6 +456,21 @@ static inline int generic_phy_power_off(struct phy *phy)
        return 0;
 }
 
+static inline int generic_phy_configure(struct phy *phy, void *params)
+{
+       return 0;
+}
+
+static inline int generic_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
+{
+       return 0;
+}
+
+static inline int generic_phy_set_speed(struct phy *phy, int speed)
+{
+       return 0;
+}
+
 static inline int generic_phy_get_by_index(struct udevice *user, int index,
                             struct phy *phy)
 {

diff --git a/include/ide.h b/include/ide.h
index 426cef4..2c25e74 100644 (file)
--- a/include/ide.h
+++ b/include/ide.h
@@ -11,50 +11,14 @@
 
 #define IDE_BUS(dev)   (dev / (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS))
 
-#define        ATA_CURR_BASE(dev)      (CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])
-extern ulong ide_bus_offset[];
-
-/*
- * Function Prototypes
- */
-
-void ide_init(void);
-struct blk_desc;
-struct udevice;
-#ifdef CONFIG_BLK
-ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
-              void *buffer);
-ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
-               const void *buffer);
-#else
-ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
-              void *buffer);
-ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
-               const void *buffer);
-#endif
-
-#if defined(CONFIG_OF_IDE_FIXUP)
-int ide_device_present(int dev);
-#endif
-
-/*
- * I/O function overrides
- */
-unsigned char ide_inb(int dev, int port);
-void ide_outb(int dev, int port, unsigned char val);
-void ide_input_swap_data(int dev, ulong *sect_buf, int words);
-void ide_input_data(int dev, ulong *sect_buf, int words);
-void ide_output_data(int dev, const ulong *sect_buf, int words);
-void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts);
-void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts);
-
-void ide_led(uchar led, uchar status);
-
 /**
- * board_start_ide() - Start up the board IDE interfac
+ * ide_set_reset() - Assert or de-assert reset for the IDE device
+ *
+ * This is provided by boards which need to reset the device through another
+ * means, e.g. a GPIO.
  *
- * Return: 0 if ok
+ * @idereset: 1 to assert reset, 0 to de-assert it
  */
-int board_start_ide(void);
+void ide_set_reset(int idereset);
 
 #endif /* _IDE_H */

diff --git a/include/image.h b/include/image.h
index 7717a4c..456197d 100644 (file)
--- a/include/image.h
+++ b/include/image.h
@@ -1733,25 +1733,174 @@ struct cipher_algo {
 int fit_image_cipher_get_algo(const void *fit, int noffset, char **algo);
 
 struct cipher_algo *image_get_cipher_algo(const char *full_name);
+struct andr_image_data;
 
-struct andr_img_hdr;
-int android_image_check_header(const struct andr_img_hdr *hdr);
-int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
+/**
+ * android_image_get_data() - Parse Android boot images
+ *
+ * This is used to parse boot and vendor-boot header into
+ * andr_image_data generic structure.
+ *
+ * @boot_hdr: Pointer to boot image header
+ * @vendor_boot_hdr: Pointer to vendor boot image header
+ * @data: Pointer to generic boot format structure
+ * Return: true if succeeded, false otherwise
+ */
+bool android_image_get_data(const void *boot_hdr, const void *vendor_boot_hdr,
+                           struct andr_image_data *data);
+
+struct andr_boot_img_hdr_v0;
+
+/**
+ * android_image_get_kernel() - Processes kernel part of Android boot images
+ *
+ * This function returns the os image's start address and length. Also,
+ * it appends the kernel command line to the bootargs env variable.
+ *
+ * @hdr:       Pointer to image header, which is at the start
+ *                     of the image.
+ * @vendor_boot_img : Pointer to vendor boot image header
+ * @verify:    Checksum verification flag. Currently unimplemented.
+ * @os_data:   Pointer to a ulong variable, will hold os data start
+ *                     address.
+ * @os_len:    Pointer to a ulong variable, will hold os data length.
+ * Return: Zero, os start address and length on success,
+ *             otherwise on failure.
+ */
+int android_image_get_kernel(const void *hdr,
+                            const void *vendor_boot_img, int verify,
                             ulong *os_data, ulong *os_len);
-int android_image_get_ramdisk(const struct andr_img_hdr *hdr,
+
+/**
+ * android_image_get_ramdisk() - Extracts the ramdisk load address and its size
+ *
+ * This extracts the load address of the ramdisk and its size
+ *
+ * @hdr:       Pointer to image header
+ * @vendor_boot_img : Pointer to vendor boot image header
+ * @rd_data:   Pointer to a ulong variable, will hold ramdisk address
+ * @rd_len:    Pointer to a ulong variable, will hold ramdisk length
+ * Return: 0 if succeeded, -1 if ramdisk size is 0
+ */
+int android_image_get_ramdisk(const void *hdr, const void *vendor_boot_img,
                              ulong *rd_data, ulong *rd_len);
-int android_image_get_second(const struct andr_img_hdr *hdr,
-                             ulong *second_data, ulong *second_len);
+
+/**
+ * android_image_get_second() - Extracts the secondary bootloader address
+ * and its size
+ *
+ * This extracts the address of the secondary bootloader and its size
+ *
+ * @hdr:        Pointer to image header
+ * @second_data: Pointer to a ulong variable, will hold secondary bootloader address
+ * @second_len : Pointer to a ulong variable, will hold secondary bootloader length
+ * Return: 0 if succeeded, -1 if secondary bootloader size is 0
+ */
+int android_image_get_second(const void *hdr, ulong *second_data, ulong *second_len);
 bool android_image_get_dtbo(ulong hdr_addr, ulong *addr, u32 *size);
-bool android_image_get_dtb_by_index(ulong hdr_addr, u32 index, ulong *addr,
-                                   u32 *size);
-ulong android_image_get_end(const struct andr_img_hdr *hdr);
-ulong android_image_get_kload(const struct andr_img_hdr *hdr);
-ulong android_image_get_kcomp(const struct andr_img_hdr *hdr);
-void android_print_contents(const struct andr_img_hdr *hdr);
+
+/**
+ * android_image_get_dtb_by_index() - Get address and size of blob in DTB area.
+ * @hdr_addr: Boot image header address
+ * @vendor_boot_img: Pointer to vendor boot image header, which is at the start of the image.
+ * @index: Index of desired DTB in DTB area (starting from 0)
+ * @addr: If not NULL, will contain address to specified DTB
+ * @size: If not NULL, will contain size of specified DTB
+ *
+ * Get the address and size of DTB blob by its index in DTB area of Android
+ * Boot Image in RAM.
+ *
+ * Return: true on success or false on error.
+ */
+bool android_image_get_dtb_by_index(ulong hdr_addr, ulong vendor_boot_img,
+                                   u32 index, ulong *addr, u32 *size);
+
+/**
+ * android_image_get_end() - Get the end of Android boot image
+ *
+ * This returns the end address of Android boot image address
+ *
+ * @hdr: Pointer to image header
+ * @vendor_boot_img : Pointer to vendor boot image header
+ * Return: The end address of Android boot image
+ */
+ulong android_image_get_end(const struct andr_boot_img_hdr_v0 *hdr,
+                           const void *vendor_boot_img);
+
+/**
+ * android_image_get_kload() - Get the kernel load address
+ *
+ * This returns the kernel load address. The load address is extracted
+ * from the boot image header or the "kernel_addr_r" environment variable
+ *
+ * @hdr: Pointer to image header
+ * @vendor_boot_img : Pointer to vendor boot image header
+ * Return: The kernel load address
+ */
+ulong android_image_get_kload(const void *hdr,
+                             const void *vendor_boot_img);
+
+/**
+ * android_image_get_kcomp() - Get kernel compression type
+ *
+ * This gets the kernel compression type from the boot image header
+ *
+ * @hdr: Pointer to image header
+ * @vendor_boot_img : Pointer to vendor boot image header
+ * Return: Kernel compression type
+ */
+ulong android_image_get_kcomp(const void *hdr,
+                             const void *vendor_boot_img);
+
+/**
+ * android_print_contents() - Prints out the contents of the Android format image
+ *
+ * This formats a multi line Android image contents description.
+ * The routine prints out Android image properties
+ *
+ * @hdr: Pointer to the Android format image header
+ * Return: no returned results
+ */
+void android_print_contents(const struct andr_boot_img_hdr_v0 *hdr);
 bool android_image_print_dtb_contents(ulong hdr_addr);
 
 /**
+ * is_android_boot_image_header() - Check the magic of boot image
+ *
+ * This checks the header of Android boot image and verifies the
+ * magic is "ANDROID!"
+ *
+ * @hdr: Pointer to boot image
+ * Return: non-zero if the magic is correct, zero otherwise
+ */
+bool is_android_boot_image_header(const void *hdr);
+
+/**
+ * is_android_vendor_boot_image_header() - Check the magic of vendor boot image
+ *
+ * This checks the header of Android vendor boot image and verifies the magic
+ * is "VNDRBOOT"
+ *
+ * @vendor_boot_img: Pointer to boot image
+ * Return: non-zero if the magic is correct, zero otherwise
+ */
+bool is_android_vendor_boot_image_header(const void *vendor_boot_img);
+
+/**
+ * get_abootimg_addr() - Get Android boot image address
+ *
+ * Return: Android boot image address
+ */
+ulong get_abootimg_addr(void);
+
+/**
+ * get_avendor_bootimg_addr() - Get Android vendor boot image address
+ *
+ * Return: Android vendor boot image address
+ */
+ulong get_avendor_bootimg_addr(void);
+
+/**
  * board_fit_config_name_match() - Check for a matching board name
  *
  * This is used when SPL loads a FIT containing multiple device tree files

diff --git a/include/linker_lists.h b/include/linker_lists.h
index d3da9d4..f9a2ee0 100644 (file)
--- a/include/linker_lists.h
+++ b/include/linker_lists.h
@@ -127,7 +127,9 @@
        static char start[0] __aligned(CONFIG_LINKER_LIST_ALIGN)        \
                __attribute__((unused))                                 \
                __section("__u_boot_list_2_"#_list"_1");                        \
-       (_type *)&start;                                                \
+       _type * tmp = (_type *)&start;                                  \
+       asm("":"+r"(tmp));                                              \
+       tmp;                                                            \
 })
 
 /**
@@ -153,7 +155,9 @@
 ({                                                                     \
        static char end[0] __aligned(4) __attribute__((unused))         \
                __section("__u_boot_list_2_"#_list"_3");                        \
-       (_type *)&end;                                                  \
+       _type * tmp = (_type *)&end;                                    \
+       asm("":"+r"(tmp));                                              \
+       tmp;                                                            \
 })
 /**
  * ll_entry_count() - Return the number of elements in linker-generated array
@@ -247,7 +251,9 @@
 ({                                                                     \
        static char start[0] __aligned(4) __attribute__((unused))       \
                __section("__u_boot_list_1");                           \
-       (_type *)&start;                                                \
+       _type * tmp = (_type *)&start;                                  \
+       asm("":"+r"(tmp));                                              \
+       tmp;                                                            \
 })
 
 /**
@@ -270,7 +276,9 @@
 ({                                                                     \
        static char end[0] __aligned(4) __attribute__((unused))         \
                __section("__u_boot_list_3");                           \
-       (_type *)&end;                                                  \
+       _type * tmp = (_type *)&end;                                    \
+       asm("":"+r"(tmp));                                              \
+       tmp;                                                            \
 })
 
 #endif /* __ASSEMBLY__ */

diff --git a/include/linux/mdio.h b/include/linux/mdio.h
index 6e821d9..b7c8451 100644 (file)
--- a/include/linux/mdio.h
+++ b/include/linux/mdio.h
@@ -44,6 +44,7 @@
 #define MDIO_AN_ADVERTISE      16      /* AN advertising (base page) */
 #define MDIO_AN_LPA            19      /* AN LP abilities (base page) */
 #define MDIO_PCS_EEE_ABLE      20      /* EEE Capability register */
+#define MDIO_PMA_NG_EXTABLE    21      /* 2.5G/5G PMA/PMD extended ability */
 #define MDIO_PCS_EEE_WK_ERR    22      /* EEE wake error counter */
 #define MDIO_PHYXS_LNSTAT      24      /* PHY XGXS lane state */
 #define MDIO_AN_EEE_ADV                60      /* EEE advertisement */
@@ -91,6 +92,10 @@
 #define MDIO_CTRL1_SPEED10G            (MDIO_CTRL1_SPEEDSELEXT | 0x00)
 /* 10PASS-TS/2BASE-TL */
 #define MDIO_CTRL1_SPEED10P2B          (MDIO_CTRL1_SPEEDSELEXT | 0x04)
+/* 2.5 Gb/s */
+#define MDIO_CTRL1_SPEED2_5G           (MDIO_CTRL1_SPEEDSELEXT | 0x18)
+/* 5 Gb/s */
+#define MDIO_CTRL1_SPEED5G             (MDIO_CTRL1_SPEEDSELEXT | 0x1c)
 
 /* Status register 1. */
 #define MDIO_STAT1_LPOWERABLE          0x0002  /* Low-power ability */
@@ -111,6 +116,8 @@
 #define MDIO_PMA_SPEED_100             0x0020  /* 100M capable */
 #define MDIO_PMA_SPEED_10              0x0040  /* 10M capable */
 #define MDIO_PCS_SPEED_10P2B           0x0002  /* 10PASS-TS/2BASE-TL capable */
+#define MDIO_PCS_SPEED_2_5G            0x0040  /* 2.5G capable */
+#define MDIO_PCS_SPEED_5G              0x0080  /* 5G capable */
 
 /* Device present registers. */
 #define MDIO_DEVS_PRESENT(devad)       (1 << (devad))
@@ -150,6 +157,8 @@
 #define MDIO_PMA_CTRL2_1000BKX         0x000d  /* 1000BASE-KX type */
 #define MDIO_PMA_CTRL2_100BTX          0x000e  /* 100BASE-TX type */
 #define MDIO_PMA_CTRL2_10BT            0x000f  /* 10BASE-T type */
+#define MDIO_PMA_CTRL2_2_5GBT          0x0030  /* 2.5GBaseT type */
+#define MDIO_PMA_CTRL2_5GBT            0x0031  /* 5GBaseT type */
 #define MDIO_PCS_CTRL2_TYPE            0x0003  /* PCS type selection */
 #define MDIO_PCS_CTRL2_10GBR           0x0000  /* 10GBASE-R type */
 #define MDIO_PCS_CTRL2_10GBX           0x0001  /* 10GBASE-X type */
@@ -203,6 +212,7 @@
 #define MDIO_PMA_EXTABLE_1000BKX       0x0040  /* 1000BASE-KX ability */
 #define MDIO_PMA_EXTABLE_100BTX                0x0080  /* 100BASE-TX ability */
 #define MDIO_PMA_EXTABLE_10BT          0x0100  /* 10BASE-T ability */
+#define MDIO_PMA_EXTABLE_NBT           0x4000  /* 2.5/5GBASE-T ability */
 
 /* PHY XGXS lane state register. */
 #define MDIO_PHYXS_LNSTAT_SYNC0                0x0001
@@ -239,9 +249,13 @@
 #define MDIO_PCS_10GBRT_STAT2_BER      0x3f00
 
 /* AN 10GBASE-T control register. */
+#define MDIO_AN_10GBT_CTRL_ADV2_5G     0x0080  /* Advertise 2.5GBASE-T */
+#define MDIO_AN_10GBT_CTRL_ADV5G       0x0100  /* Advertise 5GBASE-T */
 #define MDIO_AN_10GBT_CTRL_ADV10G      0x1000  /* Advertise 10GBASE-T */
 
 /* AN 10GBASE-T status register. */
+#define MDIO_AN_10GBT_STAT_LP2_5G      0x0020  /* LP is 2.5GBT capable */
+#define MDIO_AN_10GBT_STAT_LP5G                0x0040  /* LP is 5GBT capable */
 #define MDIO_AN_10GBT_STAT_LPTRR       0x0200  /* LP training reset req. */
 #define MDIO_AN_10GBT_STAT_LPLTABLE    0x0400  /* LP loop timing ability */
 #define MDIO_AN_10GBT_STAT_LP10G       0x0800  /* LP is 10GBT capable */
@@ -270,6 +284,10 @@
 #define MDIO_EEE_10GKX4                0x0020  /* 10G KX4 EEE cap */
 #define MDIO_EEE_10GKR         0x0040  /* 10G KR EEE cap */
 
+/* 2.5G/5G Extended abilities register. */
+#define MDIO_PMA_NG_EXTABLE_2_5GBT     0x0001  /* 2.5GBASET ability */
+#define MDIO_PMA_NG_EXTABLE_5GBT       0x0002  /* 5GBASET ability */
+
 /* LASI RX_ALARM control/status registers. */
 #define MDIO_PMA_LASI_RX_PHYXSLFLT     0x0001  /* PHY XS RX local fault */
 #define MDIO_PMA_LASI_RX_PCSLFLT       0x0008  /* PCS RX local fault */

diff --git a/include/lmb.h b/include/lmb.h
index 7298c2c..07bf221 100644 (file)
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -35,6 +35,24 @@ struct lmb_property {
        enum lmb_flags flags;
 };
 
+/*
+ * For regions size management, see LMB configuration in KConfig
+ * all the #if test are done with CONFIG_LMB_USE_MAX_REGIONS (boolean)
+ *
+ * case 1. CONFIG_LMB_USE_MAX_REGIONS is defined (legacy mode)
+ *         => CONFIG_LMB_MAX_REGIONS is used to configure the region size,
+ *         directly in the array lmb_region.region[], with the same
+ *         configuration for memory and reserved regions.
+ *
+ * case 2. CONFIG_LMB_USE_MAX_REGIONS is not defined, the size of each
+ *         region is configurated *independently* with
+ *         => CONFIG_LMB_MEMORY_REGIONS: struct lmb.memory_regions
+ *         => CONFIG_LMB_RESERVED_REGIONS: struct lmb.reserved_regions
+ *         lmb_region.region is only a pointer to the correct buffer,
+ *         initialized in lmb_init(). This configuration is useful to manage
+ *         more reserved memory regions with CONFIG_LMB_RESERVED_REGIONS.
+ */
+
 /**
  * struct lmb_region - Description of a set of region.
  *
@@ -68,7 +86,7 @@ struct lmb_region {
 struct lmb {
        struct lmb_region memory;
        struct lmb_region reserved;
-#ifdef CONFIG_LMB_MEMORY_REGIONS
+#if !IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS)
        struct lmb_property memory_regions[CONFIG_LMB_MEMORY_REGIONS];
        struct lmb_property reserved_regions[CONFIG_LMB_RESERVED_REGIONS];
 #endif

diff --git a/include/marvell_phy.h b/include/marvell_phy.h
new file mode 100644 (file)
index 0000000..0f06c22
--- /dev/null
+++ b/include/marvell_phy.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _MARVELL_PHY_H
+#define _MARVELL_PHY_H
+
+/* Mask used for ID comparisons */
+#define MARVELL_PHY_ID_MASK            0xfffffff0
+
+/* Known PHY IDs */
+#define MARVELL_PHY_ID_88E1101         0x01410c60
+#define MARVELL_PHY_ID_88E1112         0x01410c90
+#define MARVELL_PHY_ID_88E1111         0x01410cc0
+#define MARVELL_PHY_ID_88E1118         0x01410e10
+#define MARVELL_PHY_ID_88E1121R                0x01410cb0
+#define MARVELL_PHY_ID_88E1145         0x01410cd0
+#define MARVELL_PHY_ID_88E1149R                0x01410e50
+#define MARVELL_PHY_ID_88E1240         0x01410e30
+#define MARVELL_PHY_ID_88E1318S                0x01410e90
+#define MARVELL_PHY_ID_88E1340S                0x01410dc0
+#define MARVELL_PHY_ID_88E1116R                0x01410e40
+#define MARVELL_PHY_ID_88E1510         0x01410dd0
+#define MARVELL_PHY_ID_88E1540         0x01410eb0
+#define MARVELL_PHY_ID_88E1545         0x01410ea0
+#define MARVELL_PHY_ID_88E1548P                0x01410ec0
+#define MARVELL_PHY_ID_88E3016         0x01410e60
+#define MARVELL_PHY_ID_88X3310         0x002b09a0
+#define MARVELL_PHY_ID_88E2110         0x002b09b0
+#define MARVELL_PHY_ID_88X2222         0x01410f10
+
+/* Marvel 88E1111 in Finisar SFP module with modified PHY ID */
+#define MARVELL_PHY_ID_88E1111_FINISAR 0x01ff0cc0
+
+/* These Ethernet switch families contain embedded PHYs, but they do
+ * not have a model ID. So the switch driver traps reads to the ID2
+ * register and returns the switch family ID
+ */
+#define MARVELL_PHY_ID_88E6341_FAMILY  0x01410f41
+#define MARVELL_PHY_ID_88E6390_FAMILY  0x01410f90
+#define MARVELL_PHY_ID_88E6393_FAMILY  0x002b0b9b
+
+#define MARVELL_PHY_FAMILY_ID(id)      ((id) >> 4)
+
+/* struct phy_device dev_flags definitions */
+#define MARVELL_PHY_M1145_FLAGS_RESISTANCE     0x00000001
+#define MARVELL_PHY_M1118_DNS323_LEDS          0x00000002
+#define MARVELL_PHY_LED0_LINK_LED1_ACTIVE      0x00000004
+
+#endif /* _MARVELL_PHY_H */

diff --git a/include/mmc.h b/include/mmc.h
index 36dd841..b8fbff1 100644 (file)
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -241,6 +241,7 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx)
 #define EXT_CSD_HC_WP_GRP_SIZE         221     /* RO */
 #define EXT_CSD_HC_ERASE_GRP_SIZE      224     /* RO */
 #define EXT_CSD_BOOT_MULT              226     /* RO */
+#define EXT_CSD_SEC_FEATURE            231     /* RO */
 #define EXT_CSD_GENERIC_CMD6_TIME       248     /* RO */
 #define EXT_CSD_BKOPS_SUPPORT          502     /* RO */
 
@@ -315,6 +316,8 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx)
 #define EXT_CSD_WR_DATA_REL_USR                (1 << 0)        /* user data area WR_REL */
 #define EXT_CSD_WR_DATA_REL_GP(x)      (1 << ((x)+1))  /* GP part (x+1) WR_REL */
 
+#define EXT_CSD_SEC_FEATURE_TRIM_EN    (1 << 4) /* Support secure & insecure trim */
+
 #define R1_ILLEGAL_COMMAND             (1 << 22)
 #define R1_APP_CMD                     (1 << 5)
 
@@ -687,6 +690,7 @@ struct mmc {
        uint tran_speed;
        uint legacy_speed; /* speed for the legacy mode provided by the card */
        uint read_bl_len;
+       bool can_trim;
 #if CONFIG_IS_ENABLED(MMC_WRITE)
        uint write_bl_len;
        uint erase_grp_size;    /* in 512-byte sectors */

diff --git a/include/os.h b/include/os.h
index 0415f0f..968412b 100644 (file)
--- a/include/os.h
+++ b/include/os.h
@@ -64,7 +64,7 @@ off_t os_lseek(int fd, off_t offset, int whence);
  * @fd:                File descriptor as returned by os_open()
  * Return:     file size or negative error code
  */
-int os_filesize(int fd);
+off_t os_filesize(int fd);
 
 /**
  * Access to the OS open() system call

diff --git a/include/phy.h b/include/phy.h
index 87aa86c..a837fed 100644 (file)
--- a/include/phy.h
+++ b/include/phy.h
@@ -125,8 +125,6 @@ struct phy_driver {
        int (*write_mmd)(struct phy_device *phydev, int devad, int reg,
                         u16 val);
 
-       struct list_head list;
-
        /* driver private data */
        ulong data;
 };
@@ -173,10 +171,6 @@ struct fixed_link {
        int asym_pause;
 };
 
-#ifdef CONFIG_PHYLIB_10G
-extern struct phy_driver gen10g_driver;
-#endif
-
 /**
  * phy_init() - Initializes the PHY drivers
  * This function registers all available PHY drivers
@@ -288,6 +282,37 @@ static inline ofnode phy_get_ofnode(struct phy_device *phydev)
                return dev_ofnode(phydev->dev);
 }
 
+/**
+ * phy_read_mmd_poll_timeout - Periodically poll a PHY register until a
+ *                             condition is met or a timeout occurs
+ *
+ * @phydev: The phy_device struct
+ * @devaddr: The MMD to read from
+ * @regnum: The register on the MMD to read
+ * @val: Variable to read the register into
+ * @cond: Break condition (usually involving @val)
+ * @sleep_us: Maximum time to sleep between reads in us (0
+ *            tight-loops).  Should be less than ~20ms since usleep_range
+ *            is used (see Documentation/timers/timers-howto.rst).
+ * @timeout_us: Timeout in us, 0 means never timeout
+ * @sleep_before_read: if it is true, sleep @sleep_us before read.
+ * Returns 0 on success and -ETIMEDOUT upon a timeout. In either
+ * case, the last read value at @args is stored in @val. Must not
+ * be called from atomic context if sleep_us or timeout_us are used.
+ */
+#define phy_read_mmd_poll_timeout(phydev, devaddr, regnum, val, cond, \
+                                 sleep_us, timeout_us, sleep_before_read) \
+({ \
+       int __ret = read_poll_timeout(phy_read_mmd, val, (cond) || val < 0, \
+                                 sleep_us, timeout_us, \
+                                 phydev, devaddr, regnum); \
+       if (val <  0) \
+               __ret = val; \
+       if (__ret) \
+               dev_err(phydev->dev, "%s failed: %d\n", __func__, __ret); \
+       __ret; \
+})
+
 int phy_read(struct phy_device *phydev, int devad, int regnum);
 int phy_write(struct phy_device *phydev, int devad, int regnum, u16 val);
 void phy_mmd_start_indirect(struct phy_device *phydev, int devad, int regnum);
@@ -295,11 +320,14 @@ int phy_read_mmd(struct phy_device *phydev, int devad, int regnum);
 int phy_write_mmd(struct phy_device *phydev, int devad, int regnum, u16 val);
 int phy_set_bits_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
 int phy_clear_bits_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
+int phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum,
+                          u16 mask, u16 set);
+int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
+                  u16 mask, u16 set);
 
 int phy_startup(struct phy_device *phydev);
 int phy_config(struct phy_device *phydev);
 int phy_shutdown(struct phy_device *phydev);
-int phy_register(struct phy_driver *drv);
 int phy_set_supported(struct phy_device *phydev, u32 max_speed);
 int phy_modify(struct phy_device *phydev, int devad, int regnum, u16 mask,
               u16 set);
@@ -315,35 +343,12 @@ int gen10g_startup(struct phy_device *phydev);
 int gen10g_shutdown(struct phy_device *phydev);
 int gen10g_discover_mmds(struct phy_device *phydev);
 
-int phy_b53_init(void);
-int phy_mv88e61xx_init(void);
-int phy_adin_init(void);
-int phy_aquantia_init(void);
-int phy_atheros_init(void);
-int phy_broadcom_init(void);
-int phy_cortina_init(void);
-int phy_cortina_access_init(void);
-int phy_davicom_init(void);
-int phy_et1011c_init(void);
-int phy_lxt_init(void);
-int phy_marvell_init(void);
-int phy_micrel_ksz8xxx_init(void);
-int phy_micrel_ksz90x1_init(void);
-int phy_meson_gxl_init(void);
-int phy_natsemi_init(void);
-int phy_nxp_c45_tja11xx_init(void);
-int phy_nxp_tja11xx_init(void);
-int phy_realtek_init(void);
-int phy_smsc_init(void);
-int phy_teranetics_init(void);
-int phy_ti_init(void);
-int phy_vitesse_init(void);
-int phy_xilinx_init(void);
-int phy_xway_init(void);
-int phy_mscc_init(void);
-int phy_fixed_init(void);
-int phy_ncsi_init(void);
-int phy_xilinx_gmii2rgmii_init(void);
+/**
+ * U_BOOT_PHY_DRIVER() - Declare a new U-Boot driver
+ * @__name: name of the driver
+ */
+#define U_BOOT_PHY_DRIVER(__name)                                      \
+       ll_entry_declare(struct phy_driver, __name, phy_driver)
 
 int board_phy_config(struct phy_device *phydev);
 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);

diff --git a/include/phy_interface.h b/include/phy_interface.h
index fed3357..31be322 100644 (file)
--- a/include/phy_interface.h
+++ b/include/phy_interface.h
@@ -14,63 +14,95 @@
 
 typedef enum {
        PHY_INTERFACE_MODE_NA, /* don't touch */
+       PHY_INTERFACE_MODE_INTERNAL,
        PHY_INTERFACE_MODE_MII,
        PHY_INTERFACE_MODE_GMII,
        PHY_INTERFACE_MODE_SGMII,
-       PHY_INTERFACE_MODE_SGMII_2500,
-       PHY_INTERFACE_MODE_QSGMII,
        PHY_INTERFACE_MODE_TBI,
+       PHY_INTERFACE_MODE_REVMII,
        PHY_INTERFACE_MODE_RMII,
+       PHY_INTERFACE_MODE_REVRMII,
        PHY_INTERFACE_MODE_RGMII,
        PHY_INTERFACE_MODE_RGMII_ID,
        PHY_INTERFACE_MODE_RGMII_RXID,
        PHY_INTERFACE_MODE_RGMII_TXID,
        PHY_INTERFACE_MODE_RTBI,
+       PHY_INTERFACE_MODE_SMII,
+       PHY_INTERFACE_MODE_XGMII,
+       PHY_INTERFACE_MODE_XLGMII,
+       PHY_INTERFACE_MODE_MOCA,
+       PHY_INTERFACE_MODE_QSGMII,
+       PHY_INTERFACE_MODE_TRGMII,
+       PHY_INTERFACE_MODE_100BASEX,
        PHY_INTERFACE_MODE_1000BASEX,
        PHY_INTERFACE_MODE_2500BASEX,
-       PHY_INTERFACE_MODE_XGMII,
-       PHY_INTERFACE_MODE_XAUI,
+       PHY_INTERFACE_MODE_5GBASER,
        PHY_INTERFACE_MODE_RXAUI,
-       PHY_INTERFACE_MODE_SFI,
-       PHY_INTERFACE_MODE_INTERNAL,
+       PHY_INTERFACE_MODE_XAUI,
+       /* 10GBASE-R, XFI, SFI - single lane 10G Serdes */
+       PHY_INTERFACE_MODE_10GBASER,
+       PHY_INTERFACE_MODE_25GBASER,
+       PHY_INTERFACE_MODE_USXGMII,
+       /* 10GBASE-KR - with Clause 73 AN */
+       PHY_INTERFACE_MODE_10GKR,
+       PHY_INTERFACE_MODE_QUSGMII,
+       PHY_INTERFACE_MODE_1000BASEKX,
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
+       /* LX2160A SERDES modes */
        PHY_INTERFACE_MODE_25G_AUI,
        PHY_INTERFACE_MODE_XLAUI,
        PHY_INTERFACE_MODE_CAUI2,
        PHY_INTERFACE_MODE_CAUI4,
+#endif
+#if defined(CONFIG_PHY_NCSI)
        PHY_INTERFACE_MODE_NCSI,
-       PHY_INTERFACE_MODE_10GBASER,
-       PHY_INTERFACE_MODE_USXGMII,
+#endif
        PHY_INTERFACE_MODE_MAX,
 } phy_interface_t;
 
 static const char * const phy_interface_strings[] = {
-       [PHY_INTERFACE_MODE_NA]         = "",
+       [PHY_INTERFACE_MODE_NA]                 = "",
+       [PHY_INTERFACE_MODE_INTERNAL]           = "internal",
        [PHY_INTERFACE_MODE_MII]                = "mii",
        [PHY_INTERFACE_MODE_GMII]               = "gmii",
        [PHY_INTERFACE_MODE_SGMII]              = "sgmii",
-       [PHY_INTERFACE_MODE_SGMII_2500]         = "sgmii-2500",
-       [PHY_INTERFACE_MODE_QSGMII]             = "qsgmii",
        [PHY_INTERFACE_MODE_TBI]                = "tbi",
+       [PHY_INTERFACE_MODE_REVMII]             = "rev-mii",
        [PHY_INTERFACE_MODE_RMII]               = "rmii",
+       [PHY_INTERFACE_MODE_REVRMII]            = "rev-rmii",
        [PHY_INTERFACE_MODE_RGMII]              = "rgmii",
        [PHY_INTERFACE_MODE_RGMII_ID]           = "rgmii-id",
        [PHY_INTERFACE_MODE_RGMII_RXID]         = "rgmii-rxid",
        [PHY_INTERFACE_MODE_RGMII_TXID]         = "rgmii-txid",
        [PHY_INTERFACE_MODE_RTBI]               = "rtbi",
+       [PHY_INTERFACE_MODE_SMII]               = "smii",
+       [PHY_INTERFACE_MODE_XGMII]              = "xgmii",
+       [PHY_INTERFACE_MODE_XLGMII]             = "xlgmii",
+       [PHY_INTERFACE_MODE_MOCA]               = "moca",
+       [PHY_INTERFACE_MODE_QSGMII]             = "qsgmii",
+       [PHY_INTERFACE_MODE_TRGMII]             = "trgmii",
        [PHY_INTERFACE_MODE_1000BASEX]          = "1000base-x",
+       [PHY_INTERFACE_MODE_1000BASEKX]         = "1000base-kx",
        [PHY_INTERFACE_MODE_2500BASEX]          = "2500base-x",
-       [PHY_INTERFACE_MODE_XGMII]              = "xgmii",
-       [PHY_INTERFACE_MODE_XAUI]               = "xaui",
+       [PHY_INTERFACE_MODE_5GBASER]            = "5gbase-r",
        [PHY_INTERFACE_MODE_RXAUI]              = "rxaui",
-       [PHY_INTERFACE_MODE_SFI]                = "sfi",
-       [PHY_INTERFACE_MODE_INTERNAL]           = "internal",
+       [PHY_INTERFACE_MODE_XAUI]               = "xaui",
+       [PHY_INTERFACE_MODE_10GBASER]           = "10gbase-r",
+       [PHY_INTERFACE_MODE_25GBASER]           = "25gbase-r",
+       [PHY_INTERFACE_MODE_USXGMII]            = "usxgmii",
+       [PHY_INTERFACE_MODE_10GKR]              = "10gbase-kr",
+       [PHY_INTERFACE_MODE_100BASEX]           = "100base-x",
+       [PHY_INTERFACE_MODE_QUSGMII]            = "qusgmii",
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
+       /* LX2160A SERDES modes */
        [PHY_INTERFACE_MODE_25G_AUI]            = "25g-aui",
        [PHY_INTERFACE_MODE_XLAUI]              = "xlaui4",
        [PHY_INTERFACE_MODE_CAUI2]              = "caui2",
        [PHY_INTERFACE_MODE_CAUI4]              = "caui4",
+#endif
+#if defined(CONFIG_PHY_NCSI)
        [PHY_INTERFACE_MODE_NCSI]               = "NC-SI",
-       [PHY_INTERFACE_MODE_10GBASER]           = "10gbase-r",
-       [PHY_INTERFACE_MODE_USXGMII]            = "usxgmii",
+#endif
 };
 
 /* Backplane modes:

diff --git a/include/virtio_ring.h b/include/virtio_ring.h
index c77c212..e8e9104 100644 (file)
--- a/include/virtio_ring.h
+++ b/include/virtio_ring.h
@@ -86,6 +86,8 @@ struct vring_used {
 
 struct vring {
        unsigned int num;
+       size_t size;
+       struct bounce_buffer *bouncebufs;
        struct vring_desc *desc;
        struct vring_avail *avail;
        struct vring_used *used;
@@ -137,23 +139,26 @@ struct virtqueue {
 #define vring_used_event(vr)   ((vr)->avail->ring[(vr)->num])
 #define vring_avail_event(vr)  (*(__virtio16 *)&(vr)->used->ring[(vr)->num])
 
+static inline unsigned int vring_size(unsigned int num, unsigned long align)
+{
+       return ((sizeof(struct vring_desc) * num +
+               sizeof(__virtio16) * (3 + num)  + align - 1) & ~(align - 1)) +
+               sizeof(__virtio16) * 3 + sizeof(struct vring_used_elem) * num;
+}
+
 static inline void vring_init(struct vring *vr, unsigned int num, void *p,
-                             unsigned long align)
+                             unsigned long align,
+                             struct bounce_buffer *bouncebufs)
 {
        vr->num = num;
+       vr->size = vring_size(num, align);
+       vr->bouncebufs = bouncebufs;
        vr->desc = p;
        vr->avail = p + num * sizeof(struct vring_desc);
        vr->used = (void *)(((uintptr_t)&vr->avail->ring[num] +
                   sizeof(__virtio16) + align - 1) & ~(align - 1));
 }
 
-static inline unsigned int vring_size(unsigned int num, unsigned long align)
-{
-       return ((sizeof(struct vring_desc) * num +
-               sizeof(__virtio16) * (3 + num)  + align - 1) & ~(align - 1)) +
-               sizeof(__virtio16) * 3 + sizeof(struct vring_used_elem) * num;
-}
-
 /*
  * The following is used with USED_EVENT_IDX and AVAIL_EVENT_IDX.
  * Assuming a given event_idx value from the other side, if we have just

diff --git a/lib/Kconfig b/lib/Kconfig
index 202a34a..d8dac09 100644 (file)
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -1057,7 +1057,6 @@ config LMB
 
 config LMB_USE_MAX_REGIONS
        bool "Use a common number of memory and reserved regions in lmb lib"
-       depends on LMB
        default y
        help
          Define the number of supported memory regions in the library logical
@@ -1067,7 +1066,7 @@ config LMB_USE_MAX_REGIONS
 
 config LMB_MAX_REGIONS
        int "Number of memory and reserved regions in lmb lib"
-       depends on LMB && LMB_USE_MAX_REGIONS
+       depends on LMB_USE_MAX_REGIONS
        default 16
        help
          Define the number of supported regions, memory and reserved, in the
@@ -1075,7 +1074,7 @@ config LMB_MAX_REGIONS
 
 config LMB_MEMORY_REGIONS
        int "Number of memory regions in lmb lib"
-       depends on LMB && !LMB_USE_MAX_REGIONS
+       depends on !LMB_USE_MAX_REGIONS
        default 8
        help
          Define the number of supported memory regions in the library logical
@@ -1084,7 +1083,7 @@ config LMB_MEMORY_REGIONS
 
 config LMB_RESERVED_REGIONS
        int "Number of reserved regions in lmb lib"
-       depends on LMB && !LMB_USE_MAX_REGIONS
+       depends on !LMB_USE_MAX_REGIONS
        default 8
        help
          Define the number of supported reserved regions in the library logical

diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index caaab68..d5065f2 100644 (file)
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -35,7 +35,7 @@ LIST_HEAD(efi_obj_list);
 __efi_runtime_data LIST_HEAD(efi_events);
 
 /* List of queued events */
-LIST_HEAD(efi_event_queue);
+static LIST_HEAD(efi_event_queue);
 
 /* Flag to disable timer activity in ExitBootServices() */
 static bool timers_enabled = true;
@@ -44,7 +44,7 @@ static bool timers_enabled = true;
 bool efi_st_keep_devices;
 
 /* List of all events registered by RegisterProtocolNotify() */
-LIST_HEAD(efi_register_notify_events);
+static LIST_HEAD(efi_register_notify_events);
 
 /* Handle of the currently executing image */
 static efi_handle_t current_image;

diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index d5d3ede..7a6f195 100644 (file)
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -404,12 +404,6 @@ out:
 
        return status;
 }
-#else
-efi_status_t efi_capsule_authenticate(const void *capsule, efi_uintn_t capsule_size,
-                                     void **image, efi_uintn_t *image_size)
-{
-       return EFI_UNSUPPORTED;
-}
 #endif /* CONFIG_EFI_CAPSULE_AUTHENTICATE */
 
 static __maybe_unused bool fwu_empty_capsule(struct efi_capsule_header *capsule)

diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index d5cc495..e2e98a3 100644 (file)
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -21,6 +21,9 @@
 #include <asm-generic/unaligned.h>
 #include <linux/compat.h> /* U16_MAX */
 
+#ifdef CONFIG_BLKMAP
+const efi_guid_t efi_guid_blkmap_dev = U_BOOT_BLKMAP_DEV_GUID;
+#endif
 #ifdef CONFIG_SANDBOX
 const efi_guid_t efi_guid_host_dev = U_BOOT_HOST_DEV_GUID;
 #endif
@@ -110,17 +113,13 @@ int efi_dp_match(const struct efi_device_path *a,
 /**
  * efi_dp_shorten() - shorten device-path
  *
- * We can have device paths that start with a USB WWID or a USB Class node,
- * and a few other cases which don't encode the full device path with bus
- * hierarchy:
+ * When creating a short boot option we want to use a device-path that is
+ * independent of the location where the block device is plugged in.
  *
- * * MESSAGING:USB_WWID
- * * MESSAGING:USB_CLASS
- * * MEDIA:FILE_PATH
- * * MEDIA:HARD_DRIVE
- * * MESSAGING:URI
+ * UsbWwi() nodes contain a serial number, hard drive paths a partition
+ * UUID. Both should be unique.
  *
- * See UEFI spec (section 3.1.2, about short-form device-paths)
+ * See UEFI spec, section 3.1.2 for "short-form device path".
  *
  * @dp:                original device-path
  * @Return:    shortened device-path or NULL
@@ -128,12 +127,7 @@ int efi_dp_match(const struct efi_device_path *a,
 struct efi_device_path *efi_dp_shorten(struct efi_device_path *dp)
 {
        while (dp) {
-               /*
-                * TODO: Add MESSAGING:USB_WWID and MESSAGING:URI..
-                * in practice fallback.efi just uses MEDIA:HARD_DRIVE
-                * so not sure when we would see these other cases.
-                */
-               if (EFI_DP_TYPE(dp, MESSAGING_DEVICE, MSG_USB) ||
+               if (EFI_DP_TYPE(dp, MESSAGING_DEVICE, MSG_USB_WWI) ||
                    EFI_DP_TYPE(dp, MEDIA_DEVICE, HARD_DRIVE_PATH) ||
                    EFI_DP_TYPE(dp, MEDIA_DEVICE, FILE_PATH))
                        return dp;
@@ -565,6 +559,16 @@ __maybe_unused static unsigned int dp_size(struct udevice *dev)
                        return dp_size(dev->parent)
                                + sizeof(struct efi_device_path_vendor) + 1;
 #endif
+#ifdef CONFIG_BLKMAP
+               case UCLASS_BLKMAP:
+                        /*
+                         * blkmap devices will be represented as a vendor
+                         * device node with an extra byte for the device
+                         * number.
+                         */
+                       return dp_size(dev->parent)
+                               + sizeof(struct efi_device_path_vendor) + 1;
+#endif
                default:
                        return dp_size(dev->parent);
                }
@@ -622,6 +626,23 @@ __maybe_unused static void *dp_fill(void *buf, struct udevice *dev)
 #endif
        case UCLASS_BLK:
                switch (dev->parent->uclass->uc_drv->id) {
+#ifdef CONFIG_BLKMAP
+               case UCLASS_BLKMAP: {
+                       struct efi_device_path_vendor *dp;
+                       struct blk_desc *desc = dev_get_uclass_plat(dev);
+
+                       dp_fill(buf, dev->parent);
+                       dp = buf;
+                       ++dp;
+                       dp->dp.type = DEVICE_PATH_TYPE_HARDWARE_DEVICE;
+                       dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_VENDOR;
+                       dp->dp.length = sizeof(*dp) + 1;
+                       memcpy(&dp->guid, &efi_guid_blkmap_dev,
+                              sizeof(efi_guid_t));
+                       dp->vendor_data[0] = desc->devnum;
+                       return &dp->vendor_data[1];
+                       }
+#endif
 #ifdef CONFIG_SANDBOX
                case UCLASS_HOST: {
                        /* stop traversing parents at this point: */
@@ -735,7 +756,7 @@ __maybe_unused static void *dp_fill(void *buf, struct udevice *dev)
 #endif
 #if defined(CONFIG_USB)
                case UCLASS_MASS_STORAGE: {
-                       struct blk_desc *desc = desc = dev_get_uclass_plat(dev);
+                       struct blk_desc *desc = dev_get_uclass_plat(dev);
                        struct efi_device_path_controller *dp =
                                dp_fill(buf, dev->parent);
 

diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index 8f82496..e2ca78d 100644 (file)
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -36,7 +36,7 @@ struct efi_mem_list {
 #define EFI_CARVE_OVERLAPS_NONRAM      -3
 
 /* This list contains all memory map items */
-LIST_HEAD(efi_mem);
+static LIST_HEAD(efi_mem);
 
 #ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
 void *efi_bounce_buffer;

diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index cee96bf..bf54d6a 100644 (file)
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -32,7 +32,7 @@ struct efi_runtime_mmio_list {
 };
 
 /* This list contains all runtime available mmio regions */
-LIST_HEAD(efi_runtime_mmio);
+static LIST_HEAD(efi_runtime_mmio);
 
 static efi_status_t __efi_runtime EFIAPI efi_unimplemented(void);
 

diff --git a/lib/efi_loader/helloworld.c b/lib/efi_loader/helloworld.c
index 49fa8cc..6405f58 100644 (file)
--- a/lib/efi_loader/helloworld.c
+++ b/lib/efi_loader/helloworld.c
@@ -197,8 +197,10 @@ efi_status_t EFIAPI efi_main(efi_handle_t handle,
        print_config_tables();
 
        /* Get the loaded image protocol */
-       ret = boottime->handle_protocol(handle, &loaded_image_guid,
-                                       (void **)&loaded_image);
+       ret = boottime->open_protocol(handle, &loaded_image_guid,
+                                     (void **)&loaded_image, NULL, NULL,
+                                     EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+
        if (ret != EFI_SUCCESS) {
                con_out->output_string
                        (con_out, u"Cannot open loaded image protocol\r\n");
@@ -219,9 +221,10 @@ efi_status_t EFIAPI efi_main(efi_handle_t handle,
                        (con_out, u"Missing device handle\r\n");
                goto out;
        }
-       ret = boottime->handle_protocol(loaded_image->device_handle,
-                                       &device_path_guid,
-                                       (void **)&device_path);
+       ret = boottime->open_protocol(loaded_image->device_handle,
+                                     &device_path_guid,
+                                     (void **)&device_path, NULL, NULL,
+                                     EFI_OPEN_PROTOCOL_GET_PROTOCOL);
        if (ret != EFI_SUCCESS) {
                con_out->output_string
                        (con_out, u"Missing device path for device handle\r\n");

diff --git a/lib/efi_loader/initrddump.c b/lib/efi_loader/initrddump.c
index 971a3b6..5b470f4 100644 (file)
--- a/lib/efi_loader/initrddump.c
+++ b/lib/efi_loader/initrddump.c
@@ -291,8 +291,9 @@ static efi_status_t get_initrd(void **initrd, efi_uintn_t *initrd_size)
                error(u"Load File2 protocol not found\r\n");
                return ret;
        }
-       ret = bs->handle_protocol(handle, &load_file2_guid,
-                                (void **)&load_file2_prot);
+       ret = bs->open_protocol(handle, &load_file2_guid,
+                               (void **)&load_file2_prot, NULL, NULL,
+                               EFI_OPEN_PROTOCOL_GET_PROTOCOL);
        ret = load_file2_prot->load_file(load_file2_prot, dp, false,
                                         initrd_size, NULL);
        if (ret != EFI_BUFFER_TOO_SMALL) {

diff --git a/lib/efi_selftest/efi_selftest_exitbootservices.c b/lib/efi_selftest/efi_selftest_exitbootservices.c
index 11b43fd..b090ce7 100644 (file)
--- a/lib/efi_selftest/efi_selftest_exitbootservices.c
+++ b/lib/efi_selftest/efi_selftest_exitbootservices.c
@@ -27,7 +27,7 @@ struct notification_context {
 
 static struct efi_boot_services *boottime;
 static struct efi_event *efi_st_event_notify;
-struct notification_record record;
+static struct notification_record record;
 
 struct notification_context context_before = {
        .record = &record,

diff --git a/lib/efi_selftest/efi_selftest_load_file.c b/lib/efi_selftest/efi_selftest_load_file.c
index 8784a76..14df761 100644 (file)
--- a/lib/efi_selftest/efi_selftest_load_file.c
+++ b/lib/efi_selftest/efi_selftest_load_file.c
@@ -206,11 +206,11 @@ static efi_status_t decompress(u8 **image)
  * @buffer_size:       (required) buffer size
  * @buffer:            buffer to which the file is to be loaded
  */
-efi_status_t EFIAPI load_file(struct efi_load_file_protocol *this,
-                             struct efi_device_path *file_path,
-                             bool boot_policy,
-                             efi_uintn_t *buffer_size,
-                             void *buffer)
+static efi_status_t EFIAPI load_file(struct efi_load_file_protocol *this,
+                                    struct efi_device_path *file_path,
+                                    bool boot_policy,
+                                    efi_uintn_t *buffer_size,
+                                    void *buffer)
 {
        ++load_file_call_count;
        if (memcmp(file_path, dp_lf_file_remainder,
@@ -243,11 +243,11 @@ efi_status_t EFIAPI load_file(struct efi_load_file_protocol *this,
  * @buffer_size:       (required) buffer size
  * @buffer:            buffer to which the file is to be loaded
  */
-efi_status_t EFIAPI load_file2(struct efi_load_file_protocol *this,
-                              struct efi_device_path *file_path,
-                              bool boot_policy,
-                              efi_uintn_t *buffer_size,
-                              void *buffer)
+static efi_status_t EFIAPI load_file2(struct efi_load_file_protocol *this,
+                                     struct efi_device_path *file_path,
+                                     bool boot_policy,
+                                     efi_uintn_t *buffer_size,
+                                     void *buffer)
 {
        ++load_file2_call_count;
        if (memcmp(file_path, dp_lf2_file_remainder,

diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 0827e16..55cc95d 100644 (file)
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1,6 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * NOTE: Please do not add new devicetree-reading functionality into this file.
+ * Add it to the ofnode API instead, since that is compatible with livetree.
  */
 
 #ifndef USE_HOSTCC

diff --git a/lib/lmb.c b/lib/lmb.c
index 2444b2a..b2c233e 100644 (file)
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -27,7 +27,7 @@ static void lmb_dump_region(struct lmb_region *rgn, char *name)
        enum lmb_flags flags;
        int i;
 
-       printf(" %s.cnt  = 0x%lx\n", name, rgn->cnt);
+       printf(" %s.cnt = 0x%lx / max = 0x%lx\n", name, rgn->cnt, rgn->max);
 
        for (i = 0; i < rgn->cnt; i++) {
                base = rgn->region[i].base;
@@ -110,7 +110,7 @@ void lmb_init(struct lmb *lmb)
 #if IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS)
        lmb->memory.max = CONFIG_LMB_MAX_REGIONS;
        lmb->reserved.max = CONFIG_LMB_MAX_REGIONS;
-#elif defined(CONFIG_LMB_MEMORY_REGIONS)
+#else
        lmb->memory.max = CONFIG_LMB_MEMORY_REGIONS;
        lmb->reserved.max = CONFIG_LMB_RESERVED_REGIONS;
        lmb->memory.region = lmb->memory_regions;

diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index 2d13e68..e87503e 100644 (file)
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -674,6 +674,7 @@ repeat:
 
                case 'x':
                        flags |= SMALL;
+               /* fallthrough */
                case 'X':
                        base = 16;
                        break;
@@ -681,8 +682,10 @@ repeat:
                case 'd':
                        if (fmt[1] == 'E')
                                flags |= ERRSTR;
+               /* fallthrough */
                case 'i':
                        flags |= SIGN;
+               /* fallthrough */
                case 'u':
                        break;
 

diff --git a/net/eth_common.c b/net/eth_common.c
index 82d527a..c94a7ba 100644 (file)
--- a/net/eth_common.c
+++ b/net/eth_common.c
@@ -37,7 +37,7 @@ void eth_common_init(void)
        miiphy_init();
 #endif
 
-#ifdef CONFIG_PHYLIB
+#if defined(CONFIG_NEEDS_MANUAL_RELOC) && defined(CONFIG_PHYLIB)
        phy_init();
 #endif
 #endif

diff --git a/py/travis-ci/u_boot_boardenv_M5208EVBE_qemu.py b/py/travis-ci/u_boot_boardenv_M5208EVBE_qemu.py
new file mode 100644 (file)
index 0000000..4e100cd
--- /dev/null
+++ b/py/travis-ci/u_boot_boardenv_M5208EVBE_qemu.py
@@ -0,0 +1,6 @@
+import os
+import travis_tftp
+
+env__net_uses_pci = False
+env__net_dhcp_server = True
+env__net_tftp_readable_file = travis_tftp.file2env('u-boot')

diff --git a/test/Kconfig b/test/Kconfig
index 4650282..6e859fb 100644 (file)
--- a/test/Kconfig
+++ b/test/Kconfig
@@ -3,7 +3,9 @@ config POST
        help
          See doc/README.POST for more details
 
-menuconfig UNIT_TEST
+menu "Unit tests"
+
+config UNIT_TEST
        bool "Unit tests"
        help
          Select this to compile in unit tests for various parts of
@@ -107,3 +109,5 @@ source "test/env/Kconfig"
 source "test/lib/Kconfig"
 source "test/optee/Kconfig"
 source "test/overlay/Kconfig"
+
+endmenu

diff --git a/test/boot/bootdev.c b/test/boot/bootdev.c
index 4fe9fd7..8cf3f30 100644 (file)
--- a/test/boot/bootdev.c
+++ b/test/boot/bootdev.c
@@ -124,7 +124,8 @@ static int bootdev_test_labels(struct unit_test_state *uts)
                    mflags);
 
        /* Check invalid uclass */
-       ut_asserteq(-EINVAL, bootdev_find_by_label("fred0", &dev, &mflags));
+       ut_asserteq(-EPFNOSUPPORT,
+                   bootdev_find_by_label("fred0", &dev, &mflags));
 
        /* Check unknown sequence number */
        ut_asserteq(-ENOENT, bootdev_find_by_label("mmc6", &dev, &mflags));
@@ -179,9 +180,8 @@ static int bootdev_test_any(struct unit_test_state *uts)
 
        /* Check invalid uclass */
        mflags = 123;
-       ut_asserteq(-EINVAL, bootdev_find_by_any("fred0", &dev, &mflags));
-       ut_assert_nextline("Unknown uclass 'fred0' in label");
-       ut_assert_nextline("Cannot find bootdev 'fred0' (err=-22)");
+       ut_asserteq(-EPFNOSUPPORT, bootdev_find_by_any("fred0", &dev, &mflags));
+       ut_assert_nextline("Cannot find bootdev 'fred0' (err=-96)");
        ut_asserteq(123, mflags);
        ut_assert_console_end();
 
@@ -376,7 +376,6 @@ static int bootdev_test_cmd_hunt(struct unit_test_state *uts)
        ut_assert_nextline("Hunting with: simple_bus");
        ut_assert_nextline("Found 2 extension board(s).");
        ut_assert_nextline("Hunting with: ide");
-       ut_assert_nextline("Bus 0: not available  ");
 
        /* mmc hunter has already been used so should not run again */
 
@@ -487,7 +486,6 @@ static int bootdev_test_hunt_prio(struct unit_test_state *uts)
        /* now try a different priority, verbosely */
        ut_assertok(bootdev_hunt_prio(BOOTDEVP_5_SCAN_SLOW, true));
        ut_assert_nextline("Hunting with: ide");
-       ut_assert_nextline("Bus 0: not available  ");
        ut_assert_nextline("Hunting with: usb");
        ut_assert_nextline(
                "Bus usb@1: scanning bus usb@1 for devices... 5 USB Device(s) found");
@@ -512,9 +510,8 @@ static int bootdev_test_hunt_label(struct unit_test_state *uts)
        old = (void *)&mflags;   /* arbitrary pointer to check against dev */
        dev = old;
        mflags = 123;
-       ut_asserteq(-EINVAL,
+       ut_asserteq(-EPFNOSUPPORT,
                    bootdev_hunt_and_find_by_label("fred", &dev, &mflags));
-       ut_assert_nextline("Unknown uclass 'fred' in label");
        ut_asserteq_ptr(old, dev);
        ut_asserteq(123, mflags);
        ut_assert_console_end();
@@ -525,7 +522,6 @@ static int bootdev_test_hunt_label(struct unit_test_state *uts)
                    bootdev_hunt_and_find_by_label("mmc4", &dev, &mflags));
        ut_asserteq_ptr(old, dev);
        ut_asserteq(123, mflags);
-       ut_assert_nextline("Unknown seq 4 for label 'mmc4'");
        ut_assert_console_end();
 
        ut_assertok(bootstd_test_check_mmc_hunter(uts));

diff --git a/test/cmd/fdt.c b/test/cmd/fdt.c
index 597fecb..1f103a1 100644 (file)
--- a/test/cmd/fdt.c
+++ b/test/cmd/fdt.c
@@ -2,7 +2,7 @@
 /*
  * Tests for fdt command
  *
- * Copyright 2022 Google LLCmap_to_sysmem(fdt));
+ * Copyright 2022 Google LLC
  */
 
 #include <common.h>
@@ -236,7 +236,6 @@ static int fdt_test_addr_resize(struct unit_test_state *uts)
 
        /* ...quietly */
        ut_assertok(run_commandf("fdt addr -q %08lx %zx", addr, sizeof(fdt) / 4));
-       ut_assert_nextline("Working FDT set to %lx", addr);
        ut_assertok(ut_check_console_end(uts));
 
        /* We cannot easily provoke errors in fdt_open_into(), so ignore that */

diff --git a/test/common/Makefile b/test/common/Makefile
index cc918f6..a5ab10f 100644 (file)
--- a/test/common/Makefile
+++ b/test/common/Makefile
@@ -3,3 +3,4 @@ obj-y += cmd_ut_common.o
 obj-$(CONFIG_AUTOBOOT) += test_autoboot.o
 obj-$(CONFIG_CYCLIC) += cyclic.o
 obj-$(CONFIG_EVENT) += event.o
+obj-y += cread.o

diff --git a/test/common/cread.c b/test/common/cread.c
new file mode 100644 (file)
index 0000000..2fdd29a
--- /dev/null
+++ b/test/common/cread.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Google LLC
+ */
+
+#include <common.h>
+#include <cli.h>
+#include <test/common.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+static int cli_ch_test(struct unit_test_state *uts)
+{
+       struct cli_ch_state s_cch, *cch = &s_cch;
+
+       cli_ch_init(cch);
+
+       /* should be nothing to return at first */
+       ut_asserteq(0, cli_ch_process(cch, 0));
+
+       /* check normal entry */
+       ut_asserteq('a', cli_ch_process(cch, 'a'));
+       ut_asserteq('b', cli_ch_process(cch, 'b'));
+       ut_asserteq('c', cli_ch_process(cch, 'c'));
+       ut_asserteq(0, cli_ch_process(cch, 0));
+
+       /* send an invalid escape sequence */
+       ut_asserteq(0, cli_ch_process(cch, '\e'));
+       ut_asserteq(0, cli_ch_process(cch, '['));
+
+       /*
+        * with the next char it sees that the sequence is invalid, so starts
+        * emitting it
+        */
+       ut_asserteq('\e', cli_ch_process(cch, 'X'));
+
+       /* now we set 0 bytes to empty the buffer */
+       ut_asserteq('[', cli_ch_process(cch, 0));
+       ut_asserteq('X', cli_ch_process(cch, 0));
+       ut_asserteq(0, cli_ch_process(cch, 0));
+
+       /* things are normal again */
+       ut_asserteq('a', cli_ch_process(cch, 'a'));
+       ut_asserteq(0, cli_ch_process(cch, 0));
+
+       return 0;
+}
+COMMON_TEST(cli_ch_test, 0);
+
+static int cread_test(struct unit_test_state *uts)
+{
+       int duration;
+       ulong start;
+       char buf[10];
+
+       /*
+        * useful for debugging
+        *
+        * gd->flags &= ~GD_FLG_RECORD;
+        * print_buffer(0, buf, 1, 7, 0);
+        */
+
+       console_record_reset_enable();
+
+       /* simple input */
+       *buf = '\0';
+       ut_asserteq(4, console_in_puts("abc\n"));
+       ut_asserteq(3, cli_readline_into_buffer("-> ", buf, 1));
+       ut_asserteq_str("abc", buf);
+
+       /* try an escape sequence (cursor left after the 'c') */
+       *buf = '\0';
+       ut_asserteq(8, console_in_puts("abc\e[Dx\n"));
+       ut_asserteq(4, cli_readline_into_buffer("-> ", buf, 1));
+       ut_asserteq_str("abxc", buf);
+
+       /* invalid escape sequence */
+       *buf = '\0';
+       ut_asserteq(8, console_in_puts("abc\e[Xx\n"));
+       ut_asserteq(7, cli_readline_into_buffer("-> ", buf, 1));
+       ut_asserteq_str("abc\e[Xx", buf);
+
+       /* check timeout, should be between 1000 and 1050ms */
+       start = get_timer(0);
+       *buf = '\0';
+       ut_asserteq(-2, cli_readline_into_buffer("-> ", buf, 1));
+       duration = get_timer(start) - 1000;
+       ut_assert(duration >= 0);
+       ut_assert(duration < 50);
+
+       return 0;
+}
+COMMON_TEST(cread_test, 0);

diff --git a/test/dm/Makefile b/test/dm/Makefile
index 7a79b6e..c8534b5 100644 (file)
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 # Copyright (c) 2013 Google, Inc
+# Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
 
 obj-$(CONFIG_UT_DM) += test-dm.o
 
@@ -17,6 +18,10 @@ obj-$(CONFIG_UT_DM) += test-uclass.o
 obj-$(CONFIG_UT_DM) += core.o
 obj-$(CONFIG_UT_DM) += read.o
 obj-$(CONFIG_UT_DM) += phys2bus.o
+ifeq ($(CONFIG_NVMXIP_QSPI)$(CONFIG_SANDBOX64),yy)
+obj-y += nvmxip.o
+endif
+
 ifneq ($(CONFIG_SANDBOX),)
 ifeq ($(CONFIG_ACPIGEN),y)
 obj-y += acpi.o
@@ -29,6 +34,7 @@ obj-$(CONFIG_ADC) += adc.o
 obj-$(CONFIG_SOUND) += audio.o
 obj-$(CONFIG_AXI) += axi.o
 obj-$(CONFIG_BLK) += blk.o
+obj-$(CONFIG_BLKMAP) += blkmap.o
 obj-$(CONFIG_BUTTON) += button.o
 obj-$(CONFIG_DM_BOOTCOUNT) += bootcount.o
 obj-$(CONFIG_DM_REBOOT_MODE) += reboot-mode.o

diff --git a/test/dm/blkmap.c b/test/dm/blkmap.c
new file mode 100644 (file)
index 0000000..7a163d6
--- /dev/null
+++ b/test/dm/blkmap.c
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Addiva Elektronik
+ * Author: Tobias Waldekranz <tobias@waldekranz.com>
+ */
+
+#include <common.h>
+#include <blk.h>
+#include <blkmap.h>
+#include <dm.h>
+#include <asm/test.h>
+#include <dm/test.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+#define BLKSZ 0x200
+
+struct mapping {
+       int src;
+       int cnt;
+       int dst;
+};
+
+const struct mapping unordered_mapping[] = {
+       { 0, 1, 3 },
+       { 1, 3, 0 },
+       { 4, 2, 6 },
+       { 6, 2, 4 },
+
+       { 0, 0, 0 }
+};
+
+const struct mapping identity_mapping[] = {
+       { 0, 8, 0 },
+
+       { 0, 0, 0 }
+};
+
+static char identity[8 * BLKSZ];
+static char unordered[8 * BLKSZ];
+static char buffer[8 * BLKSZ];
+
+static void mkblob(void *base, const struct mapping *m)
+{
+       int nr;
+
+       for (; m->cnt; m++) {
+               for (nr = 0; nr < m->cnt; nr++) {
+                       memset(base + (m->dst + nr) * BLKSZ,
+                              m->src + nr, BLKSZ);
+               }
+       }
+}
+
+static int dm_test_blkmap_read(struct unit_test_state *uts)
+{
+       struct udevice *dev, *blk;
+       const struct mapping *m;
+
+       ut_assertok(blkmap_create("rdtest", &dev));
+       ut_assertok(blk_get_from_parent(dev, &blk));
+
+       /* Generate an ordered and an unordered pattern in memory */
+       mkblob(unordered, unordered_mapping);
+       mkblob(identity, identity_mapping);
+
+       /* Create a blkmap that cancels out the disorder */
+       for (m = unordered_mapping; m->cnt; m++) {
+               ut_assertok(blkmap_map_mem(dev, m->src, m->cnt,
+                                          unordered + m->dst * BLKSZ));
+       }
+
+       /* Read out the data via the blkmap device to another area,
+        * and verify that it matches the ordered pattern.
+        */
+       ut_asserteq(8, blk_read(blk, 0, 8, buffer));
+       ut_assertok(memcmp(buffer, identity, sizeof(buffer)));
+
+       ut_assertok(blkmap_destroy(dev));
+       return 0;
+}
+DM_TEST(dm_test_blkmap_read, 0);
+
+static int dm_test_blkmap_write(struct unit_test_state *uts)
+{
+       struct udevice *dev, *blk;
+       const struct mapping *m;
+
+       ut_assertok(blkmap_create("wrtest", &dev));
+       ut_assertok(blk_get_from_parent(dev, &blk));
+
+       /* Generate an ordered and an unordered pattern in memory */
+       mkblob(unordered, unordered_mapping);
+       mkblob(identity, identity_mapping);
+
+       /* Create a blkmap that mimics the disorder */
+       for (m = unordered_mapping; m->cnt; m++) {
+               ut_assertok(blkmap_map_mem(dev, m->src, m->cnt,
+                                          buffer + m->dst * BLKSZ));
+       }
+
+       /* Write the ordered data via the blkmap device to another
+        * area, and verify that the result matches the unordered
+        * pattern.
+        */
+       ut_asserteq(8, blk_write(blk, 0, 8, identity));
+       ut_assertok(memcmp(buffer, unordered, sizeof(buffer)));
+
+       ut_assertok(blkmap_destroy(dev));
+       return 0;
+}
+DM_TEST(dm_test_blkmap_write, 0);
+
+static int dm_test_blkmap_slicing(struct unit_test_state *uts)
+{
+       struct udevice *dev;
+
+       ut_assertok(blkmap_create("slicetest", &dev));
+
+       ut_assertok(blkmap_map_mem(dev, 8, 8, NULL));
+
+       /* Can't overlap on the low end */
+       ut_asserteq(-EBUSY, blkmap_map_mem(dev,  4, 5, NULL));
+       /* Can't be inside */
+       ut_asserteq(-EBUSY, blkmap_map_mem(dev, 10, 2, NULL));
+       /* Can't overlap on the high end */
+       ut_asserteq(-EBUSY, blkmap_map_mem(dev, 15, 4, NULL));
+
+       /* But we should be able to add slices right before and
+        * after
+        */
+       ut_assertok(blkmap_map_mem(dev,  4, 4, NULL));
+       ut_assertok(blkmap_map_mem(dev, 16, 4, NULL));
+
+       ut_assertok(blkmap_destroy(dev));
+       return 0;
+}
+DM_TEST(dm_test_blkmap_slicing, 0);
+
+static int dm_test_blkmap_creation(struct unit_test_state *uts)
+{
+       struct udevice *first, *second;
+
+       ut_assertok(blkmap_create("first", &first));
+
+       /* Can't have two "first"s */
+       ut_asserteq(-EBUSY, blkmap_create("first", &second));
+
+       /* But "second" should be fine */
+       ut_assertok(blkmap_create("second", &second));
+
+       /* Once "first" is destroyed, we should be able to create it
+        * again
+        */
+       ut_assertok(blkmap_destroy(first));
+       ut_assertok(blkmap_create("first", &first));
+
+       ut_assertok(blkmap_destroy(first));
+       ut_assertok(blkmap_destroy(second));
+       return 0;
+}
+DM_TEST(dm_test_blkmap_creation, 0);
+
+static int dm_test_cmd_blkmap(struct unit_test_state *uts)
+{
+       ulong loadaddr = env_get_hex("loadaddr", 0);
+       struct udevice *dev;
+
+       console_record_reset();
+
+       ut_assertok(run_command("blkmap info", 0));
+       ut_assert_console_end();
+
+       ut_assertok(run_command("blkmap create ramdisk", 0));
+       ut_assert_nextline("Created \"ramdisk\"");
+       ut_assert_console_end();
+
+       ut_assertnonnull((dev = blkmap_from_label("ramdisk")));
+
+       ut_assertok(run_commandf("blkmap map ramdisk 0 800 mem 0x%lx", loadaddr));
+       ut_assert_nextline("Block 0x0+0x800 mapped to 0x%lx", loadaddr);
+       ut_assert_console_end();
+
+       ut_assertok(run_command("blkmap info", 0));
+       ut_assert_nextline("Device 0: Vendor: U-Boot Rev: 1.0 Prod: blkmap");
+       ut_assert_nextline("            Type: Hard Disk");
+       ut_assert_nextline("            Capacity: 1.0 MB = 0.0 GB (2048 x 512)");
+       ut_assert_console_end();
+
+       ut_assertok(run_command("blkmap get ramdisk dev devnum", 0));
+       ut_asserteq(dev_seq(dev), env_get_hex("devnum", 0xdeadbeef));
+
+       ut_assertok(run_command("blkmap destroy ramdisk", 0));
+       ut_assert_nextline("Destroyed \"ramdisk\"");
+       ut_assert_console_end();
+
+       ut_assertok(run_command("blkmap info", 0));
+       ut_assert_console_end();
+       return 0;
+}
+DM_TEST(dm_test_cmd_blkmap, 0);

diff --git a/test/dm/mmc.c b/test/dm/mmc.c
index f744452..b1eb8be 100644 (file)
--- a/test/dm/mmc.c
+++ b/test/dm/mmc.c
@@ -30,7 +30,7 @@ static int dm_test_mmc_blk(struct unit_test_state *uts)
        struct udevice *dev;
        struct blk_desc *dev_desc;
        int i;
-       char write[1024], read[1024];
+       char write[4 * 512], read[4 * 512];
 
        ut_assertok(uclass_get_device(UCLASS_MMC, 0, &dev));
        ut_assertok(blk_get_device_by_str("mmc", "0", &dev_desc));
@@ -39,14 +39,14 @@ static int dm_test_mmc_blk(struct unit_test_state *uts)
        ut_asserteq(512, dev_desc->blksz);
        for (i = 0; i < sizeof(write); i++)
                write[i] = i;
-       ut_asserteq(2, blk_dwrite(dev_desc, 0, 2, write));
-       ut_asserteq(2, blk_dread(dev_desc, 0, 2, read));
+       ut_asserteq(4, blk_dwrite(dev_desc, 0, 4, write));
+       ut_asserteq(4, blk_dread(dev_desc, 0, 4, read));
        ut_asserteq_mem(write, read, sizeof(write));
 
-       /* Now erase them */
-       memset(write, '\0', sizeof(write));
-       ut_asserteq(2, blk_derase(dev_desc, 0, 2));
-       ut_asserteq(2, blk_dread(dev_desc, 0, 2, read));
+       /* Now erase two of them [1 - 2] and verify all blocks */
+       memset(&write[512], '\0', 2 * 512);
+       ut_asserteq(2, blk_derase(dev_desc, 1, 2));
+       ut_asserteq(4, blk_dread(dev_desc, 0, 4, read));
        ut_asserteq_mem(write, read, sizeof(write));
 
        return 0;

diff --git a/test/dm/nvmxip.c b/test/dm/nvmxip.c
new file mode 100644 (file)
index 0000000..e934748
--- /dev/null
+++ b/test/dm/nvmxip.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Functional tests for UCLASS_FFA  class
+ *
+ * Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#include <common.h>
+#include <blk.h>
+#include <console.h>
+#include <dm.h>
+#include <mapmem.h>
+#include <dm/test.h>
+#include <linux/bitops.h>
+#include <test/test.h>
+#include <test/ut.h>
+#include "../../drivers/mtd/nvmxip/nvmxip.h"
+
+/* NVMXIP devices described in the device tree */
+#define SANDBOX_NVMXIP_DEVICES 2
+
+/* reference device tree data for the probed devices */
+static struct nvmxip_plat nvmqspi_refdata[SANDBOX_NVMXIP_DEVICES] = {
+       {0x08000000, 9, 4096}, {0x08200000, 9, 2048}
+};
+
+#define NVMXIP_BLK_START_PATTERN 0x1122334455667788ULL
+#define NVMXIP_BLK_END_PATTERN 0xa1a2a3a4a5a6a7a8ULL
+
+/**
+ * dm_nvmxip_flash_sanity() - check flash data
+ * @uts: test state
+ * @device_idx:        the NVMXIP device index
+ * @buffer:    the user buffer where the blocks data is copied to
+ *
+ * Mode 1: When buffer is NULL, initialize the flash with pattern data at the start
+ * and at the end of each block. This pattern data will be used to check data consistency
+ * when verifying the data read.
+ * Mode 2: When the user buffer is provided in the argument (not NULL), compare the data
+ * of the start and the end of each block in the user buffer with the expected pattern data.
+ * Return an error when the check fails.
+ *
+ * Return:
+ *
+ * 0 on success. Otherwise, failure
+ */
+static int dm_nvmxip_flash_sanity(struct unit_test_state *uts, u8 device_idx, void *buffer)
+{
+       int i;
+       u64 *ptr;
+       u8 *base;
+       unsigned long blksz;
+
+       blksz = BIT(nvmqspi_refdata[device_idx].lba_shift);
+
+       if (!buffer) {
+               /* Mode 1: point at the flash start address. Pattern data will be written */
+               base = map_sysmem(nvmqspi_refdata[device_idx].phys_base, 0);
+       } else {
+               /* Mode 2: point at the user buffer containing the data read and to be verified */
+               base = buffer;
+       }
+
+       for (i = 0; i < nvmqspi_refdata[device_idx].lba ; i++) {
+               ptr = (u64 *)(base + i * blksz);
+
+               /* write an 8 bytes pattern at the start of the current block */
+               if (!buffer)
+                       *ptr = NVMXIP_BLK_START_PATTERN;
+               else
+                       ut_asserteq_64(NVMXIP_BLK_START_PATTERN, *ptr);
+
+               ptr = (u64 *)((u8 *)ptr + blksz - sizeof(u64));
+
+               /* write an 8 bytes pattern at the end of the current block */
+               if (!buffer)
+                       *ptr = NVMXIP_BLK_END_PATTERN;
+               else
+                       ut_asserteq_64(NVMXIP_BLK_END_PATTERN, *ptr);
+       }
+
+       if (!buffer)
+               unmap_sysmem(base);
+
+       return 0;
+}
+
+/**
+ * dm_test_nvmxip() - check flash data
+ * @uts: test state
+ * Return:
+ *
+ * CMD_RET_SUCCESS on success. Otherwise, failure
+ */
+static int dm_test_nvmxip(struct unit_test_state *uts)
+{
+       struct nvmxip_plat *plat_data = NULL;
+       struct udevice *dev = NULL, *bdev = NULL;
+       u8 device_idx;
+       void *buffer = NULL;
+       unsigned long flashsz;
+
+       /* set the flash content first for both devices */
+       dm_nvmxip_flash_sanity(uts, 0, NULL);
+       dm_nvmxip_flash_sanity(uts, 1, NULL);
+
+       /* probing all NVM XIP QSPI devices */
+       for (device_idx = 0, uclass_first_device(UCLASS_NVMXIP, &dev);
+            dev;
+            uclass_next_device(&dev), device_idx++) {
+               plat_data = dev_get_plat(dev);
+
+               /* device tree entries checks */
+               ut_assertok(nvmqspi_refdata[device_idx].phys_base != plat_data->phys_base);
+               ut_assertok(nvmqspi_refdata[device_idx].lba_shift != plat_data->lba_shift);
+               ut_assertok(nvmqspi_refdata[device_idx].lba != plat_data->lba);
+
+               /* before reading all the flash blocks, let's calculate the flash size */
+               flashsz = plat_data->lba << plat_data->lba_shift;
+
+               /* allocate the user buffer where to copy the blocks data to */
+               buffer = calloc(flashsz, 1);
+               ut_assertok(!buffer);
+
+               /* the block device is the child of the parent device probed with DT */
+               ut_assertok(device_find_first_child(dev, &bdev));
+
+               /* reading all the flash blocks */
+               ut_asserteq(plat_data->lba, blk_read(bdev, 0, plat_data->lba, buffer));
+
+               /* compare the data read from flash with the expected data */
+               dm_nvmxip_flash_sanity(uts, device_idx, buffer);
+
+               free(buffer);
+       }
+
+       ut_assertok(device_idx != SANDBOX_NVMXIP_DEVICES);
+
+       return CMD_RET_SUCCESS;
+}
+
+DM_TEST(dm_test_nvmxip, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);

diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c
index 8e6e42e..eeecd1d 100644 (file)
--- a/test/dm/test-fdt.c
+++ b/test/dm/test-fdt.c
@@ -617,6 +617,7 @@ static int dm_test_fdt_get_addr_ptr_flat(struct unit_test_state *uts)
 {
        struct udevice *gpio, *dev;
        void *ptr;
+       void *paddr;
 
        /* Test for missing reg property */
        ut_assertok(uclass_first_device_err(UCLASS_GPIO, &gpio));
@@ -624,7 +625,9 @@ static int dm_test_fdt_get_addr_ptr_flat(struct unit_test_state *uts)
 
        ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 0, &dev));
        ptr = devfdt_get_addr_ptr(dev);
-       ut_asserteq_ptr((void *)0x8000, ptr);
+
+       paddr = map_sysmem(0x8000, 0);
+       ut_asserteq_ptr(paddr, ptr);
 
        return 0;
 }

diff --git a/test/lib/Kconfig b/test/lib/Kconfig
index dbb03e4..ae0aa2f 100644 (file)
--- a/test/lib/Kconfig
+++ b/test/lib/Kconfig
@@ -1,23 +1,24 @@
 # SPDX-License-Identifier: GPL-2.0+
 # Copyright 2022 Google LLC
 
-if SANDBOX
-
 config TEST_KCONFIG
        bool "Enable detection of Kconfig macro errors"
+       depends on SANDBOX
        help
          This is used to test that the IF_ENABLED_INT() macro causes a build error
-         if the value is used when the CONFIG Is not enabled.
+         if the value is used when the CONFIG is not enabled.
+
+if TEST_KCONFIG
 
 config TEST_KCONFIG_ENABLE
-       bool "Option to enable"
+       bool "Provide a value for the Kconfig test"
        help
          This is the option that controls whether the value is present.
 
 config TEST_KCONFIG_VALUE
-       int "Value associated with the option"
+       int "Value used in Kconfig test"
        depends on TEST_KCONFIG_ENABLE
        help
-         This is the value whgch is present if TEST_KCONFIG_ENABLE is enabled.
+         This is the value which is present if TEST_KCONFIG_ENABLE is enabled.
 
-endif # SANDBOX
+endif # TEST_KCONFIG

diff --git a/test/py/requirements.txt b/test/py/requirements.txt
index e241780..86d6266 100644 (file)
--- a/test/py/requirements.txt
+++ b/test/py/requirements.txt
@@ -8,21 +8,21 @@ fixtures==3.0.0
 importlib-metadata==0.23
 linecache2==1.0.0
 more-itertools==7.2.0
-packaging==19.2
+packaging==21.3
 pbr==5.4.3
 pluggy==0.13.0
 py==1.10.0
 pycryptodomex==3.9.8
 pyelftools==0.27
 pygit2==1.9.2
-pyparsing==2.4.2
+pyparsing==3.0.7
 pytest==6.2.5
 pytest-xdist==2.5.0
 python-mimeparse==1.6.0
 python-subunit==1.3.0
-requests==2.25.1
+requests==2.27.1
 setuptools==58.3.0
-six==1.12.0
+six==1.16.0
 testtools==2.3.0
 traceback2==1.4.0
 unittest2==1.1.0

diff --git a/test/py/tests/test_android/test_abootimg.py b/test/py/tests/test_android/test_abootimg.py
index 43a7099..6a8ff34 100644 (file)
--- a/test/py/tests/test_android/test_abootimg.py
+++ b/test/py/tests/test_android/test_abootimg.py
@@ -32,6 +32,23 @@ Now one can obtain original boot.img from this hex dump like this:
 
     $ xxd -r -p boot.img.gz.hex boot.img.gz
     $ gunzip -9 boot.img.gz
+
+For boot image header version 4, these tests rely on two images that are generated
+using the same steps above :
+
+1- boot.img :
+    $ mkbootimg --kernel ./kernel --ramdisk ./ramdisk.img  \
+                --cmdline "cmdline test" --dtb ./dtb.img   \
+                --os_version R --os_patch_level 2019-06-05 \
+                --header_version 4 --output ./boot.img
+
+2- vendor_boot.img
+    $ mkbootimg --kernel ./kernel --ramdisk ./ramdisk.img  \
+                --cmdline "cmdline test" --dtb ./dtb.img   \
+                --os_version R --os_patch_level 2019-06-05 \
+                --pagesize 4096  --vendor_ramdisk ./ramdisk.img \
+                --header_version 4 --vendor_boot ./vboot.img \
+
 """
 
 # boot.img.gz hex dump
@@ -44,6 +61,24 @@ b7762ffff07d345446c1281805e8a0868d81e117a45e111c0d8dc101b253
 9c03c41a0c90f17fe85400986d82452b6c3680198a192a0ce17c3610ae34
 d4a9820881a70f3873f35352731892f3730b124b32937252a96bb9119ae5
 463a5546f82c1f05a360148c8251300a462e000085bf67f200200000"""
+
+# boot img v4 hex dump
+boot_img_hex = """1f8b080827b0cd630203626f6f742e696d6700edd8bd0d82601885d1d7c4
+58d8c808b88195bd098d8d246e40e42b083f1aa0717be99d003d277916b8
+e5bddc8a7b792d8e8788c896ce9b88d32ebe6c971e7ddd3543cae734cd01
+c0ffc84c0000b0766d1a87d4e5afeadd3dab7a6f10000000f84163d5d7cd
+d43a000000000000000060c53e7544995700400000"""
+
+# vendor boot image v4 hex dump
+vboot_img_hex = """1f8b0808baaecd63020376626f6f742e696d6700edd8310b824018c6f1b3
+222a08f41b3436b4280dcdd19c11d16ee9109d18d59042d047ec8b04cd0d
+d19d5a4345534bf6ffc173ef29272f38e93b1d0ec67dd79d548462aa1cd2
+d5d20b0000f8438678f90c18d584b8a4bbb3a557991ecb2a0000f80d6b2f
+f4179b656be5c532f2fc066f040000000080e23936af2755f62a3d918df1
+db2a7ab67f9ffdeb7df7cda3465ecb79c4ce7e5c577562bb9364b74449a5
+1e467e20c53c0a57de763193c1779b3b4fcd9d4ee27c6a0e00000000c0ff
+309ffea7010000000040f1dc004129855400400000"""
+
 # Expected response for "abootimg dtb_dump" command
 dtb_dump_resp="""## DTB area contents (concat format):
  - DTB #0:
@@ -56,15 +91,21 @@ dtb_dump_resp="""## DTB area contents (concat format):
      (DTB)compatible = y2,z2"""
 # Address in RAM where to load the boot image ('abootimg' looks in $loadaddr)
 loadaddr = 0x1000
+# Address in RAM where to load the vendor boot image ('abootimg' looks in $vloadaddr)
+vloadaddr= 0x10000
 # Expected DTB #1 offset from the boot image start address
 dtb1_offset = 0x187d
+# Expected DTB offset from the vendor boot image start address
+dtb2_offset = 0x207d
 # DTB #1 start address in RAM
 dtb1_addr = loadaddr + dtb1_offset
+# DTB #2 start address in RAM
+dtb2_addr = vloadaddr + dtb2_offset
 
 class AbootimgTestDiskImage(object):
     """Disk image used by abootimg tests."""
 
-    def __init__(self, u_boot_console):
+    def __init__(self, u_boot_console, image_name, hex_img):
         """Initialize a new AbootimgDiskImage object.
 
         Args:
@@ -74,13 +115,13 @@ class AbootimgTestDiskImage(object):
             Nothing.
         """
 
-        gz_hex = u_boot_console.config.persistent_data_dir + '/boot.img.gz.hex'
-        gz = u_boot_console.config.persistent_data_dir + '/boot.img.gz'
+        gz_hex = u_boot_console.config.persistent_data_dir + '/' + image_name  + '.gz.hex'
+        gz = u_boot_console.config.persistent_data_dir + '/' + image_name + '.gz'
 
-        filename = 'boot.img'
+        filename = image_name
         persistent = u_boot_console.config.persistent_data_dir + '/' + filename
         self.path = u_boot_console.config.result_dir  + '/' + filename
-
+        u_boot_console.log.action('persistent is ' + persistent)
         with u_boot_utils.persistent_file_helper(u_boot_console.log, persistent):
             if os.path.exists(persistent):
                 u_boot_console.log.action('Disk image file ' + persistent +
@@ -89,19 +130,17 @@ class AbootimgTestDiskImage(object):
                 u_boot_console.log.action('Generating ' + persistent)
 
                 f = open(gz_hex, "w")
-                f.write(img_hex)
+                f.write(hex_img)
                 f.close()
-
                 cmd = ('xxd', '-r', '-p', gz_hex, gz)
                 u_boot_utils.run_and_log(u_boot_console, cmd)
-
                 cmd = ('gunzip', '-9', gz)
                 u_boot_utils.run_and_log(u_boot_console, cmd)
 
         cmd = ('cp', persistent, self.path)
         u_boot_utils.run_and_log(u_boot_console, cmd)
 
-gtdi = None
+gtdi1 = None
 @pytest.fixture(scope='function')
 def abootimg_disk_image(u_boot_console):
     """pytest fixture to provide a AbootimgTestDiskImage object to tests.
@@ -109,10 +148,36 @@ def abootimg_disk_image(u_boot_console):
     function-scoped. However, we don't need to actually do any function-scope
     work, so this simply returns the same object over and over each time."""
 
-    global gtdi
-    if not gtdi:
-        gtdi = AbootimgTestDiskImage(u_boot_console)
-    return gtdi
+    global gtdi1
+    if not gtdi1:
+        gtdi1 = AbootimgTestDiskImage(u_boot_console, 'boot.img', img_hex)
+    return gtdi1
+
+gtdi2 = None
+@pytest.fixture(scope='function')
+def abootimgv4_disk_image_vboot(u_boot_console):
+    """pytest fixture to provide a AbootimgTestDiskImage object to tests.
+    This is function-scoped because it uses u_boot_console, which is also
+    function-scoped. However, we don't need to actually do any function-scope
+    work, so this simply returns the same object over and over each time."""
+
+    global gtdi2
+    if not gtdi2:
+        gtdi2 = AbootimgTestDiskImage(u_boot_console, 'vendor_boot.img', vboot_img_hex)
+    return gtdi2
+
+gtdi3 = None
+@pytest.fixture(scope='function')
+def abootimgv4_disk_image_boot(u_boot_console):
+    """pytest fixture to provide a AbootimgTestDiskImage object to tests.
+    This is function-scoped because it uses u_boot_console, which is also
+    function-scoped. However, we don't need to actually do any function-scope
+    work, so this simply returns the same object over and over each time."""
+
+    global gtdi3
+    if not gtdi3:
+        gtdi3 = AbootimgTestDiskImage(u_boot_console, 'bootv4.img', boot_img_hex)
+    return gtdi3
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('android_boot_image')
@@ -157,3 +222,48 @@ def test_abootimg(abootimg_disk_image, u_boot_console):
     u_boot_console.run_command('fdt get value v / model')
     response = u_boot_console.run_command('env print v')
     assert response == 'v=x2'
+
+@pytest.mark.boardspec('sandbox')
+@pytest.mark.buildconfigspec('android_boot_image')
+@pytest.mark.buildconfigspec('cmd_abootimg')
+@pytest.mark.buildconfigspec('cmd_fdt')
+@pytest.mark.requiredtool('xxd')
+@pytest.mark.requiredtool('gunzip')
+def test_abootimgv4(abootimgv4_disk_image_vboot, abootimgv4_disk_image_boot, u_boot_console):
+    """Test the 'abootimg' command with boot image header v4."""
+
+    cons = u_boot_console
+    cons.log.action('Loading disk image to RAM...')
+    cons.run_command('setenv loadaddr 0x%x' % (loadaddr))
+    cons.run_command('setenv vloadaddr 0x%x' % (vloadaddr))
+    cons.run_command('host load hostfs - 0x%x %s' % (vloadaddr,
+       abootimgv4_disk_image_vboot.path))
+    cons.run_command('host load hostfs - 0x%x %s' % (loadaddr,
+        abootimgv4_disk_image_boot.path))
+    cons.run_command('abootimg addr 0x%x 0x%x' % (loadaddr, vloadaddr))
+    cons.log.action('Testing \'abootimg get ver\'...')
+    response = cons.run_command('abootimg get ver')
+    assert response == "4"
+    cons.run_command('abootimg get ver v')
+    response = cons.run_command('env print v')
+    assert response == 'v=4'
+
+    cons.log.action('Testing \'abootimg get recovery_dtbo\'...')
+    response = cons.run_command('abootimg get recovery_dtbo a')
+    assert response == 'Error: header version must be >= 1 and <= 2 to get dtbo'
+
+    cons.log.action('Testing \'abootimg get dtb_load_addr\'...')
+    cons.run_command('abootimg get dtb_load_addr a')
+    response = cons.run_command('env print a')
+    assert response == 'a=11f00000'
+
+    cons.log.action('Testing \'abootimg get dtb --index\'...')
+    cons.run_command('abootimg get dtb --index=1 dtb2_start')
+    response = cons.run_command('env print dtb2_start')
+    correct_str = "dtb2_start=%x" % (dtb2_addr)
+    assert response == correct_str
+
+    cons.run_command('fdt addr $dtb2_start')
+    cons.run_command('fdt get value v / model')
+    response = cons.run_command('env print v')
+    assert response == 'v=x2'

diff --git a/test/py/tests/test_efi_capsule/conftest.py b/test/py/tests/test_efi_capsule/conftest.py
index 4879f2b..0e5137d 100644 (file)
--- a/test/py/tests/test_efi_capsule/conftest.py
+++ b/test/py/tests/test_efi_capsule/conftest.py
@@ -2,30 +2,21 @@
 # Copyright (c) 2020, Linaro Limited
 # Author: AKASHI Takahiro <takahiro.akashi@linaro.org>
 
-import os
-import os.path
-import re
-from subprocess import call, check_call, check_output, CalledProcessError
-import pytest
-from capsule_defs import *
+"""Fixture for UEFI capsule test
+"""
 
-#
-# Fixture for UEFI capsule test
-#
+from subprocess import call, check_call, CalledProcessError
+import pytest
+from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR, EFITOOLS_PATH
 
 @pytest.fixture(scope='session')
 def efi_capsule_data(request, u_boot_config):
-    """Set up a file system to be used in UEFI capsule and
-       authentication test.
-
-    Args:
-        request: Pytest request object.
-        u_boot_config: U-boot configuration.
+    """Set up a file system to be used in UEFI capsule and authentication test
+    and return a ath to disk image to be used for testing
 
-    Return:
-        A path to disk image to be used for testing
+    request -- Pytest request object.
+    u_boot_config -- U-boot configuration.
     """
-    global CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR
 
     mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
     data_dir = mnt_point + CAPSULE_DATA_DIR

diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py
index d28b53a..9ee1528 100644 (file)
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py
@@ -1,16 +1,13 @@
 # SPDX-License-Identifier:      GPL-2.0+
 # Copyright (c) 2020, Linaro Limited
 # Author: AKASHI Takahiro <takahiro.akashi@linaro.org>
-#
-# U-Boot UEFI: Firmware Update Test
 
-"""
+"""U-Boot UEFI: Firmware Update Test
 This test verifies capsule-on-disk firmware update for FIT images
 """
 
-from subprocess import check_call, check_output, CalledProcessError
 import pytest
-from capsule_defs import *
+from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR
 
 
 @pytest.mark.boardspec('sandbox_flattree')
@@ -24,15 +21,18 @@ from capsule_defs import *
 @pytest.mark.buildconfigspec('cmd_nvedit_efi')
 @pytest.mark.buildconfigspec('cmd_sf')
 @pytest.mark.slow
-class TestEfiCapsuleFirmwareFit(object):
+class TestEfiCapsuleFirmwareFit():
+    """Test capsule-on-disk firmware update for FIT images
+    """
+
     def test_efi_capsule_fw1(
             self, u_boot_config, u_boot_console, efi_capsule_data):
-        """
-        Test Case 1 - Update U-Boot and U-Boot environment on SPI Flash
-                      but with an incorrect GUID value in the capsule
-                      No update should happen
-                      0x100000-0x150000: U-Boot binary (but dummy)
-                      0x150000-0x200000: U-Boot environment (but dummy)
+        """Test Case 1
+        Update U-Boot and U-Boot environment on SPI Flash
+        but with an incorrect GUID value in the capsule
+        No update should happen
+        0x100000-0x150000: U-Boot binary (but dummy)
+        0x150000-0x200000: U-Boot environment (but dummy)
         """
         # other tests might have run and the
         # system might not be in a clean state.
@@ -74,8 +74,6 @@ class TestEfiCapsuleFirmwareFit(object):
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
-        capsule_auth = u_boot_config.buildconfig.get(
-            'config_efi_capsule_authenticate')
 
         # reboot
         u_boot_console.restart_uboot(expect_reset = capsule_early)
@@ -107,11 +105,12 @@ class TestEfiCapsuleFirmwareFit(object):
 
     def test_efi_capsule_fw2(
             self, u_boot_config, u_boot_console, efi_capsule_data):
+        """Test Case 2
+        Update U-Boot and U-Boot environment on SPI Flash
+        0x100000-0x150000: U-Boot binary (but dummy)
+        0x150000-0x200000: U-Boot environment (but dummy)
         """
-        Test Case 2 - Update U-Boot and U-Boot environment on SPI Flash
-                      0x100000-0x150000: U-Boot binary (but dummy)
-                      0x150000-0x200000: U-Boot environment (but dummy)
-        """
+
         disk_img = efi_capsule_data
         with u_boot_console.log.section('Test Case 2-a, before reboot'):
             output = u_boot_console.run_command_list([

diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
index 8c2d616..ba8429e 100644 (file)
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
@@ -3,10 +3,8 @@
 # Copyright (c) 2022, Arm Limited
 # Author: AKASHI Takahiro <takahiro.akashi@linaro.org>,
 #         adapted to FIT images by Vincent Stehlé <vincent.stehle@arm.com>
-#
-# U-Boot UEFI: Firmware Update (Signed capsule with FIT images) Test
 
-"""
+"""U-Boot UEFI: Firmware Update (Signed capsule with FIT images) Test
 This test verifies capsule-on-disk firmware update
 with signed capsule files containing FIT images
 """
@@ -25,15 +23,18 @@ from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR
 @pytest.mark.buildconfigspec('cmd_nvedit_efi')
 @pytest.mark.buildconfigspec('cmd_sf')
 @pytest.mark.slow
-class TestEfiCapsuleFirmwareSignedFit(object):
+class TestEfiCapsuleFirmwareSignedFit():
+    """Capsule-on-disk firmware update test
+    """
+
     def test_efi_capsule_auth1(
             self, u_boot_config, u_boot_console, efi_capsule_data):
-        """
-        Test Case 1 - Update U-Boot on SPI Flash, FIT image format
-                      0x100000-0x150000: U-Boot binary (but dummy)
+        """Test Case 1
+        Update U-Boot on SPI Flash, FIT image format
+        x150000: U-Boot binary (but dummy)
 
-                      If the capsule is properly signed, the authentication
-                      should pass and the firmware be updated.
+        If the capsule is properly signed, the authentication
+        should pass and the firmware be updated.
         """
         disk_img = efi_capsule_data
         with u_boot_console.log.section('Test Case 1-a, before reboot'):
@@ -103,13 +104,13 @@ class TestEfiCapsuleFirmwareSignedFit(object):
 
     def test_efi_capsule_auth2(
             self, u_boot_config, u_boot_console, efi_capsule_data):
-        """
-        Test Case 2 - Update U-Boot on SPI Flash, FIT image format
-                      0x100000-0x150000: U-Boot binary (but dummy)
+        """Test Case 2
+        Update U-Boot on SPI Flash, FIT image format
+        0x100000-0x150000: U-Boot binary (but dummy)
 
-                      If the capsule is signed but with an invalid key,
-                      the authentication should fail and the firmware
-                      not be updated.
+        If the capsule is signed but with an invalid key,
+        the authentication should fail and the firmware
+        not be updated.
         """
         disk_img = efi_capsule_data
         with u_boot_console.log.section('Test Case 2-a, before reboot'):
@@ -182,12 +183,12 @@ class TestEfiCapsuleFirmwareSignedFit(object):
 
     def test_efi_capsule_auth3(
             self, u_boot_config, u_boot_console, efi_capsule_data):
-        """
-        Test Case 3 - Update U-Boot on SPI Flash, FIT image format
-                      0x100000-0x150000: U-Boot binary (but dummy)
+        """Test Case 3
+        Update U-Boot on SPI Flash, FIT image format
+        0x100000-0x150000: U-Boot binary (but dummy)
 
-                      If the capsule is not signed, the authentication
-                      should fail and the firmware not be updated.
+        If the capsule is not signed, the authentication
+        should fail and the firmware not be updated.
         """
         disk_img = efi_capsule_data
         with u_boot_console.log.section('Test Case 3-a, before reboot'):

diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
index 2bbaa9c..710d992 100644 (file)
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
@@ -1,10 +1,8 @@
 # SPDX-License-Identifier:      GPL-2.0+
 # Copyright (c) 2021, Linaro Limited
 # Author: AKASHI Takahiro <takahiro.akashi@linaro.org>
-#
-# U-Boot UEFI: Firmware Update (Signed capsule with raw images) Test
 
-"""
+"""U-Boot UEFI: Firmware Update (Signed capsule with raw images) Test
 This test verifies capsule-on-disk firmware update
 with signed capsule files containing raw images
 """
@@ -23,15 +21,17 @@ from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR
 @pytest.mark.buildconfigspec('cmd_nvedit_efi')
 @pytest.mark.buildconfigspec('cmd_sf')
 @pytest.mark.slow
-class TestEfiCapsuleFirmwareSignedRaw(object):
+class TestEfiCapsuleFirmwareSignedRaw():
+    """Firmware Update (Signed capsule with raw images) Test
+    """
+
     def test_efi_capsule_auth1(
             self, u_boot_config, u_boot_console, efi_capsule_data):
-        """
-        Test Case 1 - Update U-Boot on SPI Flash, raw image format
-                      0x100000-0x150000: U-Boot binary (but dummy)
+        """Test Case 1 - Update U-Boot on SPI Flash, raw image format
+        0x100000-0x150000: U-Boot binary (but dummy)
 
-                      If the capsule is properly signed, the authentication
-                      should pass and the firmware be updated.
+        If the capsule is properly signed, the authentication
+        should pass and the firmware be updated.
         """
         disk_img = efi_capsule_data
         with u_boot_console.log.section('Test Case 1-a, before reboot'):
@@ -100,13 +100,12 @@ class TestEfiCapsuleFirmwareSignedRaw(object):
 
     def test_efi_capsule_auth2(
             self, u_boot_config, u_boot_console, efi_capsule_data):
-        """
-        Test Case 2 - Update U-Boot on SPI Flash, raw image format
-                      0x100000-0x150000: U-Boot binary (but dummy)
+        """Test Case 2 - Update U-Boot on SPI Flash, raw image format
+        0x100000-0x150000: U-Boot binary (but dummy)
 
-                      If the capsule is signed but with an invalid key,
-                      the authentication should fail and the firmware
-                      not be updated.
+        If the capsule is signed but with an invalid key,
+        the authentication should fail and the firmware
+        not be updated.
         """
         disk_img = efi_capsule_data
         with u_boot_console.log.section('Test Case 2-a, before reboot'):
@@ -179,12 +178,11 @@ class TestEfiCapsuleFirmwareSignedRaw(object):
 
     def test_efi_capsule_auth3(
             self, u_boot_config, u_boot_console, efi_capsule_data):
-        """
-        Test Case 3 - Update U-Boot on SPI Flash, raw image format
-                      0x100000-0x150000: U-Boot binary (but dummy)
+        """Test Case 3 - Update U-Boot on SPI Flash, raw image format
+        0x100000-0x150000: U-Boot binary (but dummy)
 
-                      If the capsule is not signed, the authentication
-                      should fail and the firmware not be updated.
+        If the capsule is not signed, the authentication
+        should fail and the firmware not be updated.
         """
         disk_img = efi_capsule_data
         with u_boot_console.log.section('Test Case 3-a, before reboot'):

diff --git a/test/py/tests/test_efi_fit.py b/test/py/tests/test_efi_fit.py
index 92d071f..7b7c98f 100644 (file)
--- a/test/py/tests/test_efi_fit.py
+++ b/test/py/tests/test_efi_fit.py
@@ -433,11 +433,13 @@ def test_efi_fit_launch(u_boot_console):
     sys_arch = cons.config.buildconfig.get('config_sys_arch', '"sandbox"')[1:-1]
     is_sandbox = sys_arch == 'sandbox'
 
+    if is_sandbox:
+        old_dtb = cons.config.dtb
+
     try:
         if is_sandbox:
             # Use our own device tree file, will be restored afterwards.
             control_dtb = make_dtb('internal', False)
-            old_dtb = cons.config.dtb
             cons.config.dtb = control_dtb
 
         # Run tests

diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py
index e8c8a6d..0b45863 100644 (file)
--- a/test/py/tests/test_ut.py
+++ b/test/py/tests/test_ut.py
@@ -213,7 +213,7 @@ booti ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}
               str(exc))
     finally:
         if mounted:
-            u_boot_utils.run_and_log(cons, 'sudo umount %s' % mnt)
+            u_boot_utils.run_and_log(cons, 'sudo umount --lazy %s' % mnt)
         if loop:
             u_boot_utils.run_and_log(cons, 'sudo losetup -d %s' % loop)
 
@@ -274,7 +274,7 @@ label Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl)
               str(exc))
     finally:
         if mounted:
-            u_boot_utils.run_and_log(cons, 'sudo umount %s' % mnt)
+            u_boot_utils.run_and_log(cons, 'sudo umount --lazy %s' % mnt)
         if loop:
             u_boot_utils.run_and_log(cons, 'sudo losetup -d %s' % loop)
 

diff --git a/test/py/tests/test_vbe_vpl.py b/test/py/tests/test_vbe_vpl.py
index d1c9d05..ed12d3a 100644 (file)
--- a/test/py/tests/test_vbe_vpl.py
+++ b/test/py/tests/test_vbe_vpl.py
@@ -15,6 +15,7 @@ def test_vbe_vpl(u_boot_console):
     #cmd = [cons.config.build_dir + fname, '-v']
     ram = os.path.join(cons.config.build_dir, 'ram.bin')
     fdt = os.path.join(cons.config.build_dir, 'arch/sandbox/dts/test.dtb')
+    image_fname = os.path.join(cons.config.build_dir, 'image.bin')
 
     # Enable firmware1 and the mmc that it uses. These are needed for the full
     # VBE flow.
@@ -24,12 +25,13 @@ def test_vbe_vpl(u_boot_console):
         cons, f'fdtput -t s {fdt} /bootstd/firmware1 status okay')
     u_boot_utils.run_and_log(
         cons, f'fdtput -t s {fdt} /mmc3 status okay')
+    u_boot_utils.run_and_log(
+        cons, f'fdtput -t s {fdt} /mmc3 filename {image_fname}')
 
     # Remove any existing RAM file, so we don't have old data present
     if os.path.exists(ram):
         os.remove(ram)
-    flags = ['-p', os.path.join(cons.config.build_dir, 'image.bin'), '-w',
-             '-s', 'state.dtb']
+    flags = ['-p', image_fname, '-w', '-s', 'state.dtb']
     cons.restart_uboot_with_flags(flags)
 
     # Make sure that VBE was used in both VPL (to load SPL) and SPL (to load

diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py
index e3e7ca4..04fa59f 100644 (file)
--- a/test/py/tests/test_vboot.py
+++ b/test/py/tests/test_vboot.py
@@ -30,6 +30,12 @@ For pre-load header verification:
 - Check that image verification fails
 
 Tests run with both SHA1 and SHA256 hashing.
+
+This also tests fdt_add_pubkey utility in the simple way:
+- Create DTB and FIT files
+- Add keys with fdt_add_pubkey to DTB
+- Sign FIT image
+- Check with fit_check_sign that keys properly added to DTB file
 """
 
 import os
@@ -40,6 +46,41 @@ import u_boot_utils as util
 import vboot_forge
 import vboot_evil
 
+# Common helper functions
+def dtc(dts, cons, dtc_args, datadir, tmpdir, dtb):
+    """Run the device tree compiler to compile a .dts file
+
+    The output file will be the same as the input file but with a .dtb
+    extension.
+
+    Args:
+        dts: Device tree file to compile.
+        cons: U-Boot console.
+        dtc_args: DTC arguments.
+        datadir: Path to data directory.
+        tmpdir: Path to temp directory.
+        dtb: Resulting DTB file.
+    """
+    dtb = dts.replace('.dts', '.dtb')
+    util.run_and_log(cons, 'dtc %s %s%s -O dtb '
+                     '-o %s%s' % (dtc_args, datadir, dts, tmpdir, dtb))
+
+def make_fit(its, cons, mkimage, dtc_args, datadir, fit):
+    """Make a new FIT from the .its source file.
+
+    This runs 'mkimage -f' to create a new FIT.
+
+    Args:
+        its: Filename containing .its source.
+        cons: U-Boot console.
+        mkimage: Path to mkimage utility.
+        dtc_args: DTC arguments.
+        datadir: Path to data directory.
+        fit: Resulting FIT file.
+    """
+    util.run_and_log(cons, [mkimage, '-D', dtc_args, '-f',
+                            '%s%s' % (datadir, its), fit])
+
 # Only run the full suite on a few combinations, since it doesn't add any more
 # test coverage.
 TESTDATA_IN = [
@@ -82,19 +123,6 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
     The SHA1 and SHA256 tests are combined into a single test since the
     key-generation process is quite slow and we want to avoid doing it twice.
     """
-    def dtc(dts):
-        """Run the device tree compiler to compile a .dts file
-
-        The output file will be the same as the input file but with a .dtb
-        extension.
-
-        Args:
-            dts: Device tree file to compile.
-        """
-        dtb = dts.replace('.dts', '.dtb')
-        util.run_and_log(cons, 'dtc %s %s%s -O dtb '
-                         '-o %s%s' % (dtc_args, datadir, dts, tmpdir, dtb))
-
     def dtc_options(dts, options):
         """Run the device tree compiler to compile a .dts file
 
@@ -152,17 +180,6 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
             assert('sandbox: continuing, as we cannot run'
                    not in ''.join(output))
 
-    def make_fit(its):
-        """Make a new FIT from the .its source file.
-
-        This runs 'mkimage -f' to create a new FIT.
-
-        Args:
-            its: Filename containing .its source.
-        """
-        util.run_and_log(cons, [mkimage, '-D', dtc_args, '-f',
-                                '%s%s' % (datadir, its), fit])
-
     def sign_fit(sha_algo, options):
         """Sign the FIT
 
@@ -286,12 +303,12 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
         # Compile our device tree files for kernel and U-Boot. These are
         # regenerated here since mkimage will modify them (by adding a
         # public key) below.
-        dtc('sandbox-kernel.dts')
-        dtc('sandbox-u-boot.dts')
+        dtc('sandbox-kernel.dts', cons, dtc_args, datadir, tmpdir, dtb)
+        dtc('sandbox-u-boot.dts', cons, dtc_args, datadir, tmpdir, dtb)
 
         # Build the FIT, but don't sign anything yet
         cons.log.action('%s: Test FIT with signed images' % sha_algo)
-        make_fit('sign-images-%s%s.its' % (sha_algo, padding))
+        make_fit('sign-images-%s%s.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
         run_bootm(sha_algo, 'unsigned images', ' - OK' if algo_arg else 'dev-', True)
 
         # Sign images with our dev keys
@@ -299,10 +316,10 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
         run_bootm(sha_algo, 'signed images', 'dev+', True)
 
         # Create a fresh .dtb without the public keys
-        dtc('sandbox-u-boot.dts')
+        dtc('sandbox-u-boot.dts', cons, dtc_args, datadir, tmpdir, dtb)
 
         cons.log.action('%s: Test FIT with signed configuration' % sha_algo)
-        make_fit('sign-configs-%s%s.its' % (sha_algo, padding))
+        make_fit('sign-configs-%s%s.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
         run_bootm(sha_algo, 'unsigned config', '%s+ OK' % ('sha256' if algo_arg else sha_algo), True)
 
         # Sign images with our dev keys
@@ -352,7 +369,7 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
             run_bootm(sha_algo, 'evil kernel@', msg, False, efit)
 
         # Create a new properly signed fit and replace header bytes
-        make_fit('sign-configs-%s%s.its' % (sha_algo, padding))
+        make_fit('sign-configs-%s%s.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
         sign_fit(sha_algo, sign_options)
         bcfg = u_boot_console.config.buildconfig
         max_size = int(bcfg.get('config_fit_signature_max_size', 0x10000000), 0)
@@ -399,19 +416,19 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
         # Compile our device tree files for kernel and U-Boot. These are
         # regenerated here since mkimage will modify them (by adding a
         # public key) below.
-        dtc('sandbox-kernel.dts')
-        dtc('sandbox-u-boot.dts')
+        dtc('sandbox-kernel.dts', cons, dtc_args, datadir, tmpdir, dtb)
+        dtc('sandbox-u-boot.dts', cons, dtc_args, datadir, tmpdir, dtb)
 
         cons.log.action('%s: Test FIT with configs images' % sha_algo)
 
         # Build the FIT with prod key (keys required) and sign it. This puts the
         # signature into sandbox-u-boot.dtb, marked 'required'
-        make_fit('sign-configs-%s%s-prod.its' % (sha_algo, padding))
+        make_fit('sign-configs-%s%s-prod.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
         sign_fit(sha_algo, sign_options)
 
         # Build the FIT with dev key (keys NOT required). This adds the
         # signature into sandbox-u-boot.dtb, NOT marked 'required'.
-        make_fit('sign-configs-%s%s.its' % (sha_algo, padding))
+        make_fit('sign-configs-%s%s.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
         sign_fit_norequire(sha_algo, sign_options)
 
         # So now sandbox-u-boot.dtb two signatures, for the prod and dev keys.
@@ -423,7 +440,7 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
 
         # Build the FIT with dev key (keys required) and sign it. This puts the
         # signature into sandbox-u-boot.dtb, marked 'required'.
-        make_fit('sign-configs-%s%s.its' % (sha_algo, padding))
+        make_fit('sign-configs-%s%s.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
         sign_fit(sha_algo, sign_options)
 
         # Set the required-mode policy to "any".
@@ -461,17 +478,17 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
         # Compile our device tree files for kernel and U-Boot. These are
         # regenerated here since mkimage will modify them (by adding a
         # public key) below.
-        dtc('sandbox-kernel.dts')
+        dtc('sandbox-kernel.dts', cons, dtc_args, datadir, tmpdir, dtb)
         dtc_options('sandbox-u-boot-global%s.dts' % padding, '-p 1024')
 
         # Build the FIT with dev key (keys NOT required). This adds the
         # signature into sandbox-u-boot.dtb, NOT marked 'required'.
-        make_fit('simple-images.its')
+        make_fit('simple-images.its', cons, mkimage, dtc_args, datadir, fit)
         sign_fit_dtb(sha_algo, '', dtb)
 
         # Build the dtb for binman that define the pre-load header
         # with the global sigature.
-        dtc('sandbox-binman%s.dts' % padding)
+        dtc('sandbox-binman%s.dts' % padding, cons, dtc_args, datadir, tmpdir, dtb)
 
         # Run binman to create the final image with the not signed fit
         # and the pre-load header that contains the global signature.
@@ -531,3 +548,96 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
         # Go back to the original U-Boot with the correct dtb.
         cons.config.dtb = old_dtb
         cons.restart_uboot()
+
+
+TESTDATA_IN = [
+    ['sha1-basic', 'sha1', '', None, False],
+    ['sha1-pad', 'sha1', '', '-E -p 0x10000', False],
+    ['sha1-pss', 'sha1', '-pss', None, False],
+    ['sha1-pss-pad', 'sha1', '-pss', '-E -p 0x10000', False],
+    ['sha256-basic', 'sha256', '', None, False],
+    ['sha256-pad', 'sha256', '', '-E -p 0x10000', False],
+    ['sha256-pss', 'sha256', '-pss', None, False],
+    ['sha256-pss-pad', 'sha256', '-pss', '-E -p 0x10000', False],
+    ['sha256-pss-required', 'sha256', '-pss', None, False],
+    ['sha256-pss-pad-required', 'sha256', '-pss', '-E -p 0x10000', False],
+    ['sha384-basic', 'sha384', '', None, False],
+    ['sha384-pad', 'sha384', '', '-E -p 0x10000', False],
+    ['algo-arg', 'algo-arg', '', '-o sha256,rsa2048', True],
+    ['sha256-global-sign', 'sha256', '', '', False],
+    ['sha256-global-sign-pss', 'sha256', '-pss', '', False],
+]
+
+# Mark all but the first test as slow, so they are not run with '-k not slow'
+TESTDATA = [TESTDATA_IN[0]]
+TESTDATA += [pytest.param(*v, marks=pytest.mark.slow) for v in TESTDATA_IN[1:]]
+
+@pytest.mark.boardspec('sandbox')
+@pytest.mark.buildconfigspec('fit_signature')
+@pytest.mark.requiredtool('dtc')
+@pytest.mark.requiredtool('openssl')
+@pytest.mark.parametrize("name,sha_algo,padding,sign_options,algo_arg", TESTDATA)
+def test_fdt_add_pubkey(u_boot_console, name, sha_algo, padding, sign_options, algo_arg):
+    """Test fdt_add_pubkey utility with bunch of different algo options."""
+
+    def sign_fit(sha_algo, options):
+        """Sign the FIT
+
+        Signs the FIT and writes the signature into it.
+
+        Args:
+            sha_algo: Either 'sha1' or 'sha256', to select the algorithm to
+                    use.
+            options: Options to provide to mkimage.
+        """
+        args = [mkimage, '-F', '-k', tmpdir, fit]
+        if options:
+            args += options.split(' ')
+        cons.log.action('%s: Sign images' % sha_algo)
+        util.run_and_log(cons, args)
+
+    def test_add_pubkey(sha_algo, padding, sign_options):
+        """Test fdt_add_pubkey utility with given hash algorithm and padding.
+
+        This function tests if fdt_add_pubkey utility may add public keys into dtb.
+
+        Args:
+            sha_algo: Either 'sha1' or 'sha256', to select the algorithm to use
+            padding: Either '' or '-pss', to select the padding to use for the
+                    rsa signature algorithm.
+            sign_options: Options to mkimage when signing a fit image.
+        """
+
+        # Create a fresh .dtb without the public keys
+        dtc('sandbox-u-boot.dts', cons, dtc_args, datadir, tmpdir, dtb)
+
+        cons.log.action('%s: Test fdt_add_pubkey with signed configuration' % sha_algo)
+        # Then add the dev key via the fdt_add_pubkey tool
+        util.run_and_log(cons, [fdt_add_pubkey, '-a', '%s,%s' % ('sha256' if algo_arg else sha_algo, \
+                                'rsa3072' if sha_algo == 'sha384' else 'rsa2048'),
+                                '-k', tmpdir, '-n', 'dev', '-r', 'conf', dtb])
+
+        make_fit('sign-configs-%s%s.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
+
+        # Sign images with our dev keys
+        sign_fit(sha_algo, sign_options)
+
+        # Check with fit_check_sign that FIT is signed with key
+        util.run_and_log(cons, [fit_check_sign, '-f', fit, '-k', dtb])
+
+    cons = u_boot_console
+    tmpdir = os.path.join(cons.config.result_dir, name) + '/'
+    if not os.path.exists(tmpdir):
+        os.mkdir(tmpdir)
+    datadir = cons.config.source_dir + '/test/py/tests/vboot/'
+    fit = '%stest.fit' % tmpdir
+    mkimage = cons.config.build_dir + '/tools/mkimage'
+    binman = cons.config.source_dir + '/tools/binman/binman'
+    fit_check_sign = cons.config.build_dir + '/tools/fit_check_sign'
+    fdt_add_pubkey = cons.config.build_dir + '/tools/fdt_add_pubkey'
+    dtc_args = '-I dts -O dtb -i %s' % tmpdir
+    dtb = '%ssandbox-u-boot.dtb' % tmpdir
+
+    # keys created in test_vboot test
+
+    test_add_pubkey(sha_algo, padding, sign_options)

diff --git a/test/run b/test/run
index 93b556f..768b225 100755 (executable)
--- a/test/run
+++ b/test/run
@@ -56,6 +56,11 @@ echo "${prompt}"
 run_test "sandbox_noinst" ./test/py/test.py --bd sandbox_noinst --build ${para} \
                -k 'test_ofplatdata or test_handoff or test_spl'
 
+# Run tests which require sandbox_vpl
+echo "${prompt}"
+run_test "sandbox_vpl" ./test/py/test.py --bd sandbox_vpl --build ${para} \
+               -k 'vpl or test_spl'
+
 if [ -z "$tools_only" ]; then
        # Run tests for the flat-device-tree version of sandbox. This is a special
        # build which does not enable CONFIG_OF_LIVE for the live device tree, so we can

diff --git a/tools/aisimage.c b/tools/aisimage.c
index b8b3ee3..c5b33b5 100644 (file)
--- a/tools/aisimage.c
+++ b/tools/aisimage.c
@@ -113,7 +113,7 @@ static int get_ais_table_id(uint32_t *ptr)
        return -1;
 }
 
-static void aisimage_print_header(const void *hdr)
+static void aisimage_print_header(const void *hdr, struct image_tool_params *params)
 {
        struct ais_header *ais_hdr = (struct ais_header *)hdr;
        uint32_t *ptr;

diff --git a/tools/atmelimage.c b/tools/atmelimage.c
index 7b3b243..6a2d9d8 100644 (file)
--- a/tools/atmelimage.c
+++ b/tools/atmelimage.c
@@ -182,7 +182,7 @@ static void atmel_print_pmecc_header(const uint32_t word)
        printf("\t\t====================\n");
 }
 
-static void atmel_print_header(const void *ptr)
+static void atmel_print_header(const void *ptr, struct image_tool_params *params)
 {
        uint32_t *ints = (uint32_t *)ptr;
        size_t pos;

diff --git a/tools/binman/cmdline.py b/tools/binman/cmdline.py
index 4b875a9..9632ec1 100644 (file)
--- a/tools/binman/cmdline.py
+++ b/tools/binman/cmdline.py
@@ -95,7 +95,7 @@ controlled by a description in the board device tree.'''
     parser.add_argument('-H', '--full-help', action='store_true',
         default=False, help='Display the README file')
     parser.add_argument('--tooldir', type=str,
-        default=os.path.join(os.getenv('HOME'), '.binman-tools'),
+        default=os.path.join(os.path.expanduser('~/.binman-tools')),
         help='Set the directory to store tools')
     parser.add_argument('--toolpath', type=str, action='append',
         help='Add a path to the list of directories containing tools')

diff --git a/tools/binman/control.py b/tools/binman/control.py
index 0febcb7..68597c4 100644 (file)
--- a/tools/binman/control.py
+++ b/tools/binman/control.py
@@ -7,7 +7,11 @@
 
 from collections import OrderedDict
 import glob
-import importlib.resources
+try:
+    import importlib.resources
+except ImportError:
+    # for Python 3.6
+    import importlib_resources
 import os
 import pkg_resources
 import re

diff --git a/tools/binman/test/blob_syms.c b/tools/binman/test/blob_syms.c
index d652c79..1df8d64 100644 (file)
--- a/tools/binman/test/blob_syms.c
+++ b/tools/binman/test/blob_syms.c
@@ -5,8 +5,6 @@
  * Simple program to create some binman symbols. This is used by binman tests.
  */
 
-typedef unsigned long ulong;
-
 #include <linux/kconfig.h>
 #include <binman_sym.h>
 

diff --git a/tools/binman/test/u_boot_binman_syms.c b/tools/binman/test/u_boot_binman_syms.c
index ed76124..147c902 100644 (file)
--- a/tools/binman/test/u_boot_binman_syms.c
+++ b/tools/binman/test/u_boot_binman_syms.c
@@ -5,8 +5,6 @@
  * Simple program to create some binman symbols. This is used by binman tests.
  */
 
-typedef unsigned long ulong;
-
 #include <linux/kconfig.h>
 #include <binman_sym.h>
 

diff --git a/tools/binman/test/u_boot_binman_syms_size.c b/tools/binman/test/u_boot_binman_syms_size.c
index fa41b3d..f686892 100644 (file)
--- a/tools/binman/test/u_boot_binman_syms_size.c
+++ b/tools/binman/test/u_boot_binman_syms_size.c
@@ -5,8 +5,6 @@
  * Simple program to create some binman symbols. This is used by binman tests.
  */
 
-typedef unsigned long ulong;
-
 #include <linux/kconfig.h>
 #include <binman_sym.h>
 

diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index 35f44c0..09a11f2 100644 (file)
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -3,7 +3,11 @@
 #
 
 import multiprocessing
-import importlib.resources
+try:
+    import importlib.resources
+except ImportError:
+    # for Python 3.6
+    import importlib_resources
 import os
 import shutil
 import subprocess

diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index 241e8e6..0ecd845 100644 (file)
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -421,7 +421,7 @@ class Toolchains:
         Returns:
             Resolved string
 
-        >>> bsettings.Setup()
+        >>> bsettings.Setup(None)
         >>> tcs = Toolchains()
         >>> tcs.Add('fred', False)
         >>> var_dict = {'oblique' : 'OBLIQUE', 'first' : 'fi${second}rst', \

diff --git a/tools/default_image.c b/tools/default_image.c
index dc429ce..0e49ab3 100644 (file)
--- a/tools/default_image.c
+++ b/tools/default_image.c
@@ -41,6 +41,11 @@ static int image_check_params(struct image_tool_params *params)
                (params->lflag && (params->dflag || params->fflag)));
 }
 
+static void image_print_header(const void *ptr, struct image_tool_params *params)
+{
+       image_print_contents(ptr);
+}
+
 static int image_verify_header(unsigned char *ptr, int image_size,
                        struct image_tool_params *params)
 {
@@ -201,7 +206,7 @@ U_BOOT_IMAGE_TYPE(
        (void *)&header,
        image_check_params,
        image_verify_header,
-       image_print_contents,
+       image_print_header,
        image_set_header,
        image_extract_subimage,
        image_check_image_types,

diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile
index bd02531..9804b55 100644 (file)
--- a/tools/docker/Dockerfile
+++ b/tools/docker/Dockerfile
@@ -12,7 +12,7 @@ ENV DEBIAN_FRONTEND=noninteractive
 # Add LLVM repository
 RUN apt-get update && apt-get install -y gnupg2 wget xz-utils && rm -rf /var/lib/apt/lists/*
 RUN wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add -
-RUN echo deb http://apt.llvm.org/jammy/ llvm-toolchain-jammy-14 main | tee /etc/apt/sources.list.d/llvm.list
+RUN echo deb http://apt.llvm.org/jammy/ llvm-toolchain-jammy-16 main | tee /etc/apt/sources.list.d/llvm.list
 
 # Manually install the kernel.org "Crosstool" based toolchains for gcc-12.2.0
 RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ
@@ -39,7 +39,7 @@ RUN apt-get update && apt-get install -y \
        binutils-dev \
        bison \
        build-essential \
-       clang-14 \
+       clang-16 \
        coreutils \
        cpio \
        cppcheck \
@@ -265,6 +265,17 @@ RUN echo uboot ALL=NOPASSWD: ALL > /etc/sudoers.d/uboot
 RUN useradd -m -U uboot
 USER uboot:uboot
 
+# Populate the cache for pip to use. Get these via wget as the
+# COPY / ADD directives don't work as we need them to.
+RUN wget -O /tmp/pytest-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/test/py/requirements.txt
+RUN wget -O /tmp/sphinx-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/doc/sphinx/requirements.txt
+RUN virtualenv -p /usr/bin/python3 /tmp/venv && \
+       . /tmp/venv/bin/activate && \
+       pip install -r /tmp/pytest-requirements.txt \
+               -r /tmp/sphinx-requirements.txt && \
+       deactivate && \
+       rm -rf /tmp/venv /tmp/pytest-requirements.txt /tmp/sphinx-requirements.txt
+
 # Create the buildman config file
 RUN /bin/echo -e "[toolchain]\nroot = /usr" > ~/.buildman
 RUN /bin/echo -e "kernelorg = /opt/gcc-12.2.0-nolibc/*" >> ~/.buildman
@@ -273,3 +284,7 @@ RUN /bin/echo -e "\n[toolchain-prefix]\nxtensa = /opt/2020.07/xtensa-dc233c-elf/
 RUN /bin/echo -e "\n[toolchain-alias]\nsh = sh2" >> ~/.buildman
 RUN /bin/echo -e "\nsandbox = x86_64" >> ~/.buildman
 RUN /bin/echo -e "\nx86 = i386" >> ~/.buildman;
+
+# Add mkbootimg tool
+RUN git clone https://android.googlesource.com/platform/system/tools/mkbootimg /home/uboot/mkbootimg
+ENV PYTHONPATH "${PYTHONPATH}:/home/uboot/mkbootimg"

diff --git a/tools/env/README b/tools/env/README
index 7092513..480a893 100644 (file)
--- a/tools/env/README
+++ b/tools/env/README
@@ -59,5 +59,5 @@ this environment instance. On NAND this is used to limit the range
 within which bad blocks are skipped, on NOR it is not used.
 
 To prevent losing changes to the environment and to prevent confusing the MTD
-drivers, a lock file at /var/lock/fw_printenv.lock is used to serialize access
+drivers, a lock file at /run/fw_printenv.lock is used to serialize access
 to the environment.

diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c
index 1d193bd..0b201b9 100644 (file)
--- a/tools/env/fw_env_main.c
+++ b/tools/env/fw_env_main.c
@@ -73,7 +73,7 @@ void usage_printenv(void)
                " -c, --config         configuration file, default:" CONFIG_FILE "\n"
 #endif
                " -n, --noheader       do not repeat variable name in output\n"
-               " -l, --lock           lock node, default:/var/lock\n"
+               " -l, --lock           lock node, default:/run\n"
                "\n");
 }
 
@@ -88,7 +88,7 @@ void usage_env_set(void)
 #ifdef CONFIG_FILE
                " -c, --config         configuration file, default:" CONFIG_FILE "\n"
 #endif
-               " -l, --lock           lock node, default:/var/lock\n"
+               " -l, --lock           lock node, default:/run\n"
                " -s, --script         batch mode to minimize writes\n"
                "\n"
                "Examples:\n"
@@ -206,7 +206,7 @@ int parse_setenv_args(int argc, char *argv[])
 
 int main(int argc, char *argv[])
 {
-       char *lockname = "/var/lock/" CMD_PRINTENV ".lock";
+       char *lockname = "/run/" CMD_PRINTENV ".lock";
        int lockfd = -1;
        int retval = EXIT_SUCCESS;
        char *_cmdname;

diff --git a/tools/fdt_add_pubkey.c b/tools/fdt_add_pubkey.c
index 999f5a7..5582d7a 100644 (file)
--- a/tools/fdt_add_pubkey.c
+++ b/tools/fdt_add_pubkey.c
@@ -10,7 +10,7 @@ static const char *keyname = "key"; /* -n <keyname> */
 static const char *require_keys; /* -r <conf|image> */
 static const char *keydest; /* argv[n] */
 
-static void print_usage(const char *msg)
+static void __attribute__((__noreturn__)) print_usage(const char *msg)
 {
        fprintf(stderr, "Error: %s\n", msg);
        fprintf(stderr, "Usage: %s [-a <algo>] [-k <keydir>] [-n <keyname>] [-r <conf|image>]"
@@ -19,7 +19,7 @@ static void print_usage(const char *msg)
        exit(EXIT_FAILURE);
 }
 
-static void print_help(void)
+static void __attribute__((__noreturn__)) print_help(void)
 {
        fprintf(stderr, "Options:\n"
                "\t-a <algo>       Cryptographic algorithm. Optional parameter, default value: sha1,rsa2048\n"

diff --git a/tools/fit_common.c b/tools/fit_common.c
index 0164976..2d417d4 100644 (file)
--- a/tools/fit_common.c
+++ b/tools/fit_common.c
@@ -23,6 +23,11 @@
 #include <image.h>
 #include <u-boot/crc.h>
 
+void fit_print_header(const void *fit, struct image_tool_params *params)
+{
+       fit_print_contents(fit);
+}
+
 int fit_verify_header(unsigned char *ptr, int image_size,
                        struct image_tool_params *params)
 {

diff --git a/tools/fit_common.h b/tools/fit_common.h
index 920a16a..2da4b94 100644 (file)
--- a/tools/fit_common.h
+++ b/tools/fit_common.h
@@ -10,6 +10,8 @@
 #include "mkimage.h"
 #include <image.h>
 
+void fit_print_header(const void *fit, struct image_tool_params *params);
+
 /**
  * Verify the format of FIT header pointed to by ptr
  *

diff --git a/tools/fit_image.c b/tools/fit_image.c
index 8763a36..9fe69ea 100644 (file)
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -944,7 +944,7 @@ U_BOOT_IMAGE_TYPE(
        (void *)&header,
        fit_check_params,
        fit_verify_header,
-       fit_print_contents,
+       fit_print_header,
        NULL,
        fit_extract_contents,
        fit_check_image_types,

diff --git a/tools/gpimage.c b/tools/gpimage.c
index 27de4cf..d2bc79d 100644 (file)
--- a/tools/gpimage.c
+++ b/tools/gpimage.c
@@ -41,7 +41,7 @@ static int gpimage_verify_header(unsigned char *ptr, int image_size,
        return gph_verify_header(gph, 1);
 }
 
-static void gpimage_print_header(const void *ptr)
+static void gpimage_print_header(const void *ptr, struct image_tool_params *params)
 {
        const struct gp_header *gph = (struct gp_header *)ptr;
 

diff --git a/tools/imagetool.c b/tools/imagetool.c
index 87eee4a..b293211 100644 (file)
--- a/tools/imagetool.c
+++ b/tools/imagetool.c
@@ -66,7 +66,7 @@ int imagetool_verify_print_header(
                                 */
                                if ((*curr)->print_header) {
                                        if (!params->quiet)
-                                               (*curr)->print_header(ptr);
+                                               (*curr)->print_header(ptr, params);
                                } else {
                                        fprintf(stderr,
                                                "%s: print_header undefined for %s\n",
@@ -103,7 +103,7 @@ static int imagetool_verify_print_header_by_type(
                         */
                        if (tparams->print_header) {
                                if (!params->quiet)
-                                       tparams->print_header(ptr);
+                                       tparams->print_header(ptr, params);
                        } else {
                                fprintf(stderr,
                                        "%s: print_header undefined for %s\n",

diff --git a/tools/imagetool.h b/tools/imagetool.h
index fdceea4..a766aa2 100644 (file)
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -132,7 +132,7 @@ struct image_type_params {
         */
        int (*verify_header) (unsigned char *, int, struct image_tool_params *);
        /* Prints image information abstracting from image header */
-       void (*print_header) (const void *);
+       void (*print_header) (const void *, struct image_tool_params *);
        /*
         * The header or image contents need to be set as per image type to
         * be generated using this callback function.

diff --git a/tools/imx8image.c b/tools/imx8image.c
index c25ea84..76d0cd6 100644 (file)
--- a/tools/imx8image.c
+++ b/tools/imx8image.c
@@ -30,7 +30,7 @@ static void imx8image_set_header(void *ptr, struct stat *sbuf, int ifd,
 {
 }
 
-static void imx8image_print_header(const void *ptr)
+static void imx8image_print_header(const void *ptr, struct image_tool_params *params)
 {
 }
 

diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c
index 3ca79d8..21075c2 100644 (file)
--- a/tools/imx8mimage.c
+++ b/tools/imx8mimage.c
@@ -60,7 +60,7 @@ static void imx8mimage_set_header(void *ptr, struct stat *sbuf, int ifd,
 {
 }
 
-static void imx8mimage_print_header(const void *ptr)
+static void imx8mimage_print_header(const void *ptr, struct image_tool_params *params)
 {
 }
 

diff --git a/tools/imximage.c b/tools/imximage.c
index 354ee34..b3da1f2 100644 (file)
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -813,7 +813,7 @@ static int imximage_verify_header(unsigned char *ptr, int image_size,
        return 0;
 }
 
-static void imximage_print_header(const void *ptr)
+static void imximage_print_header(const void *ptr, struct image_tool_params *params)
 {
        struct imx_header *imx_hdr = (struct imx_header *) ptr;
        uint32_t version = detect_imximage_version(imx_hdr);

diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 177084a..4dce495 100644 (file)
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -116,6 +116,7 @@ enum image_cfg_type {
        IMAGE_CFG_NAND_BADBLK_LOCATION,
        IMAGE_CFG_NAND_ECC_MODE,
        IMAGE_CFG_NAND_PAGESZ,
+       IMAGE_CFG_SATA_BLKSZ,
        IMAGE_CFG_CPU,
        IMAGE_CFG_BINARY,
        IMAGE_CFG_DATA,
@@ -147,6 +148,7 @@ static const char * const id_strs[] = {
        [IMAGE_CFG_NAND_BADBLK_LOCATION] = "NAND_BADBLK_LOCATION",
        [IMAGE_CFG_NAND_ECC_MODE] = "NAND_ECC_MODE",
        [IMAGE_CFG_NAND_PAGESZ] = "NAND_PAGE_SIZE",
+       [IMAGE_CFG_SATA_BLKSZ] = "SATA_BLKSZ",
        [IMAGE_CFG_CPU] = "CPU",
        [IMAGE_CFG_BINARY] = "BINARY",
        [IMAGE_CFG_DATA] = "DATA",
@@ -185,6 +187,7 @@ struct image_cfg_element {
                unsigned int nandbadblklocation;
                unsigned int nandeccmode;
                unsigned int nandpagesz;
+               unsigned int satablksz;
                struct ext_hdr_v0_reg regdata;
                unsigned int regdata_delay;
                unsigned int baudrate;
@@ -992,13 +995,21 @@ static int image_fill_xip_header(void *image, struct image_tool_params *params)
        return 1;
 }
 
+static unsigned int image_get_satablksz(void)
+{
+       struct image_cfg_element *e;
+       e = image_find_option(IMAGE_CFG_SATA_BLKSZ);
+       return e ? e->satablksz : 512;
+}
+
 static size_t image_headersz_align(size_t headersz, uint8_t blockid)
 {
        /*
         * Header needs to be 4-byte aligned, which is already ensured by code
         * above. Moreover UART images must have header aligned to 128 bytes
         * (xmodem block size), NAND images to 256 bytes (ECC calculation),
-        * and SATA and SDIO images to 512 bytes (storage block size).
+        * SDIO images to 512 bytes (SDHC/SDXC fixed block size) and SATA
+        * images to specified storage block size (default 512 bytes).
         * Note that SPI images do not have to have header size aligned
         * to 256 bytes because it is possible to read from SPI storage from
         * any offset (read offset does not have to be aligned to block size).
@@ -1007,8 +1018,10 @@ static size_t image_headersz_align(size_t headersz, uint8_t blockid)
                return ALIGN(headersz, 128);
        else if (blockid == IBR_HDR_NAND_ID)
                return ALIGN(headersz, 256);
-       else if (blockid == IBR_HDR_SATA_ID || blockid == IBR_HDR_SDIO_ID)
+       else if (blockid == IBR_HDR_SDIO_ID)
                return ALIGN(headersz, 512);
+       else if (blockid == IBR_HDR_SATA_ID)
+               return ALIGN(headersz, image_get_satablksz());
        else
                return headersz;
 }
@@ -1076,12 +1089,11 @@ static void *image_create_v0(size_t *dataoff, struct image_tool_params *params,
        if (e)
                main_hdr->nandbadblklocation = e->nandbadblklocation;
 
-       /*
-        * For SATA srcaddr is specified in number of sectors.
-        * This expects the sector size to be 512 bytes.
-        */
-       if (main_hdr->blockid == IBR_HDR_SATA_ID)
-               main_hdr->srcaddr = cpu_to_le32(le32_to_cpu(main_hdr->srcaddr) / 512);
+       /* For SATA srcaddr is specified in number of sectors. */
+       if (main_hdr->blockid == IBR_HDR_SATA_ID) {
+               params->bl_len = image_get_satablksz();
+               main_hdr->srcaddr = cpu_to_le32(le32_to_cpu(main_hdr->srcaddr) / params->bl_len);
+       }
 
        /* For PCIe srcaddr is not used and must be set to 0xFFFFFFFF. */
        if (main_hdr->blockid == IBR_HDR_PEX_ID)
@@ -1533,12 +1545,11 @@ static void *image_create_v1(size_t *dataoff, struct image_tool_params *params,
        if (e)
                main_hdr->flags = e->debug ? 0x1 : 0;
 
-       /*
-        * For SATA srcaddr is specified in number of sectors.
-        * This expects the sector size to be 512 bytes.
-        */
-       if (main_hdr->blockid == IBR_HDR_SATA_ID)
-               main_hdr->srcaddr = cpu_to_le32(le32_to_cpu(main_hdr->srcaddr) / 512);
+       /* For SATA srcaddr is specified in number of sectors. */
+       if (main_hdr->blockid == IBR_HDR_SATA_ID) {
+               params->bl_len = image_get_satablksz();
+               main_hdr->srcaddr = cpu_to_le32(le32_to_cpu(main_hdr->srcaddr) / params->bl_len);
+       }
 
        /* For PCIe srcaddr is not used and must be set to 0xFFFFFFFF. */
        if (main_hdr->blockid == IBR_HDR_PEX_ID)
@@ -1702,6 +1713,13 @@ static int image_create_config_parse_oneline(char *line,
        case IMAGE_CFG_NAND_PAGESZ:
                el->nandpagesz = strtoul(value1, NULL, 16);
                break;
+       case IMAGE_CFG_SATA_BLKSZ:
+               el->satablksz = strtoul(value1, NULL, 0);
+               if (el->satablksz & (el->satablksz-1)) {
+                       fprintf(stderr, "Invalid SATA block size '%s'\n", value1);
+                       return -1;
+               }
+               break;
        case IMAGE_CFG_BINARY:
                argi = 0;
 
@@ -1893,6 +1911,8 @@ static void kwbimage_set_header(void *ptr, struct stat *sbuf, int ifd,
        struct stat s;
        int ret;
 
+       params->bl_len = 1;
+
        /*
         * Do not use sbuf->st_size as it contains size with padding.
         * We need original image data size, so stat original file.
@@ -1972,7 +1992,7 @@ static void kwbimage_set_header(void *ptr, struct stat *sbuf, int ifd,
        free(image);
 }
 
-static void kwbimage_print_header(const void *ptr)
+static void kwbimage_print_header(const void *ptr, struct image_tool_params *params)
 {
        struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr;
        struct bin_hdr_v0 *bhdr;
@@ -2004,10 +2024,11 @@ static void kwbimage_print_header(const void *ptr)
        genimg_print_size(le32_to_cpu(mhdr->blocksize) - sizeof(uint32_t));
        printf("Data Offset:  ");
        if (mhdr->blockid == IBR_HDR_SATA_ID)
-               printf("%u Sector%s (LBA)\n", le32_to_cpu(mhdr->srcaddr),
+               printf("%u Sector%s (LBA) = ", le32_to_cpu(mhdr->srcaddr),
                       le32_to_cpu(mhdr->srcaddr) != 1 ? "s" : "");
-       else
-               genimg_print_size(le32_to_cpu(mhdr->srcaddr));
+       genimg_print_size(le32_to_cpu(mhdr->srcaddr) * params->bl_len);
+       if (mhdr->blockid == IBR_HDR_SATA_ID)
+               printf("Sector Size:  %u Bytes\n", params->bl_len);
        if (mhdr->blockid == IBR_HDR_SPI_ID && le32_to_cpu(mhdr->destaddr) == 0xFFFFFFFF) {
                printf("Load Address: XIP\n");
                printf("Execute Offs: %08x\n", le32_to_cpu(mhdr->execaddr));
@@ -2033,6 +2054,7 @@ static int kwbimage_verify_header(unsigned char *ptr, int image_size,
        uint32_t offset;
        uint32_t size;
        uint8_t csum;
+       int blksz;
 
        if (header_size > 192*1024)
                return -FDT_ERR_BADSTRUCTURE;
@@ -2091,12 +2113,28 @@ static int kwbimage_verify_header(unsigned char *ptr, int image_size,
                return -FDT_ERR_BADSTRUCTURE;
        }
 
+       if (size < 4 || size % 4 != 0)
+               return -FDT_ERR_BADSTRUCTURE;
+
        /*
         * For SATA srcaddr is specified in number of sectors.
-        * This expects that sector size is 512 bytes.
+        * Try all possible sector sizes which are power of two,
+        * at least 512 bytes and up to the 32 kB.
         */
-       if (blockid == IBR_HDR_SATA_ID)
-               offset *= 512;
+       if (blockid == IBR_HDR_SATA_ID) {
+               for (blksz = 512; blksz < 0x10000; blksz *= 2) {
+                       if (offset * blksz > image_size || offset * blksz + size > image_size)
+                               break;
+
+                       if (image_checksum32(ptr + offset * blksz, size - 4) ==
+                           *(uint32_t *)(ptr + offset * blksz + size - 4)) {
+                               params->bl_len = blksz;
+                               return 0;
+                       }
+               }
+
+               return -FDT_ERR_BADSTRUCTURE;
+       }
 
        /*
         * For PCIe srcaddr is always set to 0xFFFFFFFF.
@@ -2105,21 +2143,17 @@ static int kwbimage_verify_header(unsigned char *ptr, int image_size,
        if (blockid == IBR_HDR_PEX_ID && offset == 0xFFFFFFFF)
                offset = header_size;
 
-       if (offset > image_size || offset % 4 != 0)
-               return -FDT_ERR_BADSTRUCTURE;
-
-       if (size < 4 || offset + size > image_size || size % 4 != 0)
+       if (offset % 4 != 0 || offset > image_size || offset + size > image_size)
                return -FDT_ERR_BADSTRUCTURE;
 
        if (image_checksum32(ptr + offset, size - 4) !=
            *(uint32_t *)(ptr + offset + size - 4))
                return -FDT_ERR_BADSTRUCTURE;
 
+       params->bl_len = 1;
        return 0;
 }
 
-static int kwbimage_align_size(int bootfrom, int alloc_len, struct stat s);
-
 static int kwbimage_generate(struct image_tool_params *params,
                             struct image_type_params *tparams)
 {
@@ -2130,6 +2164,8 @@ static int kwbimage_generate(struct image_tool_params *params,
        int version;
        void *hdr;
        int ret;
+       int align, size;
+       unsigned int satablksz;
 
        fcfg = fopen(params->imagename, "r");
        if (!fcfg) {
@@ -2167,6 +2203,7 @@ static int kwbimage_generate(struct image_tool_params *params,
 
        bootfrom = image_get_bootfrom();
        version = image_get_version();
+       satablksz = image_get_satablksz();
        switch (version) {
                /*
                 * Fallback to version 0 if no version is provided in the
@@ -2212,39 +2249,43 @@ static int kwbimage_generate(struct image_tool_params *params,
        tparams->hdr = hdr;
 
        /*
+        * Final SATA images must be aligned to disk block size.
+        * Final SDIO images must be aligned to 512 bytes.
+        * Final SPI and NAND images must be aligned to 256 bytes.
+        * Final UART image must be aligned to 128 bytes.
+        */
+       if (bootfrom == IBR_HDR_SATA_ID)
+               align = satablksz;
+       else if (bootfrom == IBR_HDR_SDIO_ID)
+               align = 512;
+       else if (bootfrom == IBR_HDR_SPI_ID || bootfrom == IBR_HDR_NAND_ID)
+               align = 256;
+       else if (bootfrom == IBR_HDR_UART_ID)
+               align = 128;
+       else
+               align = 4;
+
+       /*
+        * The resulting image needs to be 4-byte aligned. At least
+        * the Marvell hdrparser tool complains if its unaligned.
+        * After the image data is stored 4-byte checksum.
+        */
+       size = 4 + (align - (alloc_len + s.st_size + 4) % align) % align;
+
+       /*
         * This function should return aligned size of the datafile.
         * When skipcpy is set (datafile is skipped) then return value of this
         * function is ignored, so we have to put required kwbimage aligning
         * into the preallocated header size.
         */
        if (params->skipcpy) {
-               tparams->header_size += kwbimage_align_size(bootfrom, alloc_len, s);
+               tparams->header_size += size;
                return 0;
        } else {
-               return kwbimage_align_size(bootfrom, alloc_len, s);
+               return size;
        }
 }
 
-static int kwbimage_align_size(int bootfrom, int alloc_len, struct stat s)
-{
-       /*
-        * The resulting image needs to be 4-byte aligned. At least
-        * the Marvell hdrparser tool complains if its unaligned.
-        * After the image data is stored 4-byte checksum.
-        * Final UART image must be aligned to 128 bytes.
-        * Final SPI and NAND images must be aligned to 256 bytes.
-        * Final SATA and SDIO images must be aligned to 512 bytes.
-        */
-       if (bootfrom == IBR_HDR_SPI_ID || bootfrom == IBR_HDR_NAND_ID)
-               return 4 + (256 - (alloc_len + s.st_size + 4) % 256) % 256;
-       else if (bootfrom == IBR_HDR_SATA_ID || bootfrom == IBR_HDR_SDIO_ID)
-               return 4 + (512 - (alloc_len + s.st_size + 4) % 512) % 512;
-       else if (bootfrom == IBR_HDR_UART_ID)
-               return 4 + (128 - (alloc_len + s.st_size + 4) % 128) % 128;
-       else
-               return 4 + (4 - s.st_size % 4) % 4;
-}
-
 static int kwbimage_generate_config(void *ptr, struct image_tool_params *params)
 {
        struct main_hdr_v0 *mhdr0 = (struct main_hdr_v0 *)ptr;
@@ -2306,6 +2347,9 @@ static int kwbimage_generate_config(void *ptr, struct image_tool_params *params)
        if (version == 0 && mhdr->blockid == IBR_HDR_SATA_ID)
                fprintf(f, "SATA_PIO_MODE %u\n", (unsigned)mhdr0->satapiomode);
 
+       if (mhdr->blockid == IBR_HDR_SATA_ID)
+               fprintf(f, "SATA_BLKSZ %u\n", params->bl_len);
+
        /*
         * Addresses and sizes which are specified by mkimage command line
         * arguments and not in kwbimage config file
@@ -2486,7 +2530,7 @@ static int kwbimage_extract_subimage(void *ptr, struct image_tool_params *params
                offset = le32_to_cpu(mhdr->srcaddr);
 
                if (mhdr->blockid == IBR_HDR_SATA_ID)
-                       offset *= 512;
+                       offset *= params->bl_len;
 
                if (mhdr->blockid == IBR_HDR_PEX_ID && offset == 0xFFFFFFFF)
                        offset = header_size;

diff --git a/tools/kwboot.c b/tools/kwboot.c
index 348a320..6bef461 100644 (file)
--- a/tools/kwboot.c
+++ b/tools/kwboot.c
@@ -1991,6 +1991,39 @@ _inject_baudrate_change_code(void *img, size_t *size, int for_data,
        }
 }
 
+static int
+kwboot_img_guess_sata_blksz(void *img, uint32_t blkoff, uint32_t data_size, size_t total_size)
+{
+       uint32_t sum, *ptr, *end;
+       int blksz;
+
+       /*
+        * Try all possible sector sizes which are power of two,
+        * at least 512 bytes and up to the 32 kB.
+        */
+       for (blksz = 512; blksz < 0x10000; blksz *= 2) {
+               if (blkoff * blksz > total_size ||
+                   blkoff * blksz + data_size > total_size ||
+                   data_size % 4)
+                       break;
+
+               /*
+                * Calculate data checksum and if it matches
+                * then tried blksz should be correct.
+                */
+               ptr = img + blkoff * blksz;
+               end = (void *)ptr + data_size - 4;
+               for (sum = 0; ptr < end; ptr++)
+                       sum += *ptr;
+
+               if (sum == *end)
+                       return blksz;
+       }
+
+       /* Fallback to 512 bytes */
+       return 512;
+}
+
 static const char *
 kwboot_img_type(uint8_t blockid)
 {
@@ -2049,7 +2082,7 @@ kwboot_img_patch(void *img, size_t *size, int baudrate)
 
        switch (hdr->blockid) {
        case IBR_HDR_SATA_ID:
-               hdr->srcaddr = cpu_to_le32(srcaddr * 512);
+               hdr->srcaddr = cpu_to_le32(srcaddr * kwboot_img_guess_sata_blksz(img, srcaddr, le32_to_cpu(hdr->blocksize), *size));
                break;
 
        case IBR_HDR_PEX_ID:

diff --git a/tools/lpc32xximage.c b/tools/lpc32xximage.c
index 37931f9..715a55a 100644 (file)
--- a/tools/lpc32xximage.c
+++ b/tools/lpc32xximage.c
@@ -125,7 +125,7 @@ static void print_hdr_byte(struct nand_page_0_boot_header *hdr, int ofs)
        printf("header[%d] = %02x\n", ofs, hdr->data[ofs]);
 }
 
-static void lpc32xximage_print_header(const void *ptr)
+static void lpc32xximage_print_header(const void *ptr, struct image_tool_params *params)
 {
        struct nand_page_0_boot_header *hdr =
                (struct nand_page_0_boot_header *)ptr;

diff --git a/tools/mkimage.c b/tools/mkimage.c
index a92d9d5..6dfe3e1 100644 (file)
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -790,7 +790,7 @@ int main(int argc, char **argv)
 
        /* Print the image information by processing image header */
        if (tparams->print_header)
-               tparams->print_header (ptr);
+               tparams->print_header (ptr, &params);
        else {
                fprintf (stderr, "%s: Can't print header for %s\n",
                        params.cmdname, tparams->name);

diff --git a/tools/mtk_image.c b/tools/mtk_image.c
index 5ef9334..30f54c8 100644 (file)
--- a/tools/mtk_image.c
+++ b/tools/mtk_image.c
@@ -510,7 +510,7 @@ static int mtk_image_verify_header(unsigned char *ptr, int image_size,
        return -1;
 }
 
-static void mtk_image_print_header(const void *ptr)
+static void mtk_image_print_header(const void *ptr, struct image_tool_params *params)
 {
        struct legacy_img_hdr *hdr = (struct legacy_img_hdr *)ptr;
        union lk_hdr *lk = (union lk_hdr *)ptr;

diff --git a/tools/mxsimage.c b/tools/mxsimage.c
index fbe46c4..ead61d0 100644 (file)
--- a/tools/mxsimage.c
+++ b/tools/mxsimage.c
@@ -2239,7 +2239,7 @@ static int mxsimage_verify_header(unsigned char *ptr, int image_size,
        return mxsimage_verify_print_header(params->imagefile, 1);
 }
 
-static void mxsimage_print_header(const void *hdr)
+static void mxsimage_print_header(const void *hdr, struct image_tool_params *params)
 {
        if (imagefile)
                mxsimage_verify_print_header(imagefile, 0);

diff --git a/tools/omapimage.c b/tools/omapimage.c
index c59cdcc..b79c1c3 100644 (file)
--- a/tools/omapimage.c
+++ b/tools/omapimage.c
@@ -85,7 +85,7 @@ static void omapimage_print_section(struct ch_settings *chs)
                chs->flags);
 }
 
-static void omapimage_print_header(const void *ptr)
+static void omapimage_print_header(const void *ptr, struct image_tool_params *params)
 {
        const struct ch_toc *toc = (struct ch_toc *)ptr;
        const struct gp_header *gph =

diff --git a/tools/patman/__main__.py b/tools/patman/__main__.py
index 48ffbc8..8eba5d3 100755 (executable)
--- a/tools/patman/__main__.py
+++ b/tools/patman/__main__.py
@@ -7,7 +7,11 @@
 """See README for more information"""
 
 from argparse import ArgumentParser
-import importlib.resources
+try:
+    import importlib.resources
+except ImportError:
+    # for Python 3.6
+    import importlib_resources
 import os
 import re
 import sys

diff --git a/tools/patman/commit.py b/tools/patman/commit.py
index 9537de4..684225c 100644 (file)
--- a/tools/patman/commit.py
+++ b/tools/patman/commit.py
@@ -29,6 +29,8 @@ class Commit:
             value: Set of people who gave that rtag, each a name/email string
         warn: List of warnings for this commit, each a str
         patch (str): Filename of the patch file for this commit
+        future (concurrent.futures.Future): Future object for processing this
+            commit, or None
     """
     def __init__(self, hash):
         self.hash = hash
@@ -42,6 +44,7 @@ class Commit:
         self.rtags = collections.defaultdict(set)
         self.warn = []
         self.patch = ''
+        self.future = None
 
     def __str__(self):
         return self.subject

diff --git a/tools/patman/func_test.py b/tools/patman/func_test.py
index 42ac4ed..e391849 100644 (file)
--- a/tools/patman/func_test.py
+++ b/tools/patman/func_test.py
@@ -489,8 +489,8 @@ complicated as possible''')
         # pylint: disable=E1101
         self.repo.checkout(target, strategy=pygit2.GIT_CHECKOUT_FORCE)
         control.setup()
+        orig_dir = os.getcwd()
         try:
-            orig_dir = os.getcwd()
             os.chdir(self.gitdir)
 
             # Check that it can detect the current branch
@@ -679,8 +679,8 @@ diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
         self.repo.checkout(target, strategy=pygit2.GIT_CHECKOUT_FORCE)
 
         # Check that it can detect the current branch
+        orig_dir = os.getcwd()
         try:
-            orig_dir = os.getcwd()
             os.chdir(self.gitdir)
             with self.assertRaises(ValueError) as exc:
                 gitutil.count_commits_to_branch(None)

diff --git a/tools/pblimage.c b/tools/pblimage.c
index bd639c2..6c4d360 100644 (file)
--- a/tools/pblimage.c
+++ b/tools/pblimage.c
@@ -254,7 +254,7 @@ static int pblimage_verify_header(unsigned char *ptr, int image_size,
        return 0;
 }
 
-static void pblimage_print_header(const void *ptr)
+static void pblimage_print_header(const void *ptr, struct image_tool_params *params)
 {
        printf("Image Type:   Freescale PBL Boot Image\n");
 }

diff --git a/tools/prelink-riscv.c b/tools/prelink-riscv.c
index b046794..43d6412 100644 (file)
--- a/tools/prelink-riscv.c
+++ b/tools/prelink-riscv.c
@@ -118,5 +118,7 @@ int main(int argc, const char *const *argv)
                        prelink_le32(data);
        }
 
+       munmap(data, st.st_size);
+
        return 0;
 }

diff --git a/tools/prelink-riscv.inc b/tools/prelink-riscv.inc
index f2b5467..57c0f65 100644 (file)
--- a/tools/prelink-riscv.inc
+++ b/tools/prelink-riscv.inc
@@ -30,7 +30,7 @@
 #define cpu_to_target32 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 32)
 #define cpu_to_target64 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 64)
 
-static void* get_offset_bonn (void* data, Elf_Phdr* phdrs, size_t phnum, Elf_Addr addr)
+static void *get_offset_bonn(void *data, Elf_Phdr *phdrs, size_t phnum, Elf_Addr addr)
 {
        Elf_Phdr *p;
 
@@ -67,13 +67,13 @@ static void prelink_bonn(void *data)
        Elf_Rela *rela_dyn = NULL;
        size_t rela_count = 0;
        Elf_Sym *dynsym = NULL;
-       for (dyn = dyns;; ++dyn) {
+       for (dyn = dyns; ; ++dyn) {
                if (targetnn_to_cpu(dyn->d_tag) == DT_NULL)
                        break;
                else if (targetnn_to_cpu(dyn->d_tag) == DT_RELA)
                        rela_dyn = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
                else if (targetnn_to_cpu(dyn->d_tag) == DT_RELASZ)
-                 rela_count = targetnn_to_cpu(dyn->d_un.d_val) / sizeof(Elf_Rela);
+                       rela_count = targetnn_to_cpu(dyn->d_un.d_val) / sizeof(Elf_Rela);
                else if (targetnn_to_cpu(dyn->d_tag) == DT_SYMTAB)
                        dynsym = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
 
@@ -92,11 +92,11 @@ static void prelink_bonn(void *data)
                        continue;
 
                if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_RELATIVE)
-                       *((uintnn_t*) buf) = r->r_addend;
+                       *((uintnn_t *)buf) = r->r_addend;
                else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_32)
-                       *((uint32_t*) buf) = cpu_to_target32(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
+                       *((uint32_t *)buf) = cpu_to_target32(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
                else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_64)
-                       *((uint64_t*) buf) = cpu_to_target64(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
+                       *((uint64_t *)buf) = cpu_to_target64(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
        }
 }
 

diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 96efc11..12c27b3 100644 (file)
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -481,7 +481,7 @@ int rkcommon_verify_header(unsigned char *buf, int size,
        return -ENOENT;
 }
 
-void rkcommon_print_header(const void *buf)
+void rkcommon_print_header(const void *buf, struct image_tool_params *params)
 {
        struct header0_info header0;
        struct header0_info_v2 header0_v2;

diff --git a/tools/rkcommon.h b/tools/rkcommon.h
index 49b6df3..5d2770a 100644 (file)
--- a/tools/rkcommon.h
+++ b/tools/rkcommon.h
@@ -68,7 +68,7 @@ int rkcommon_verify_header(unsigned char *buf, int size,
  *
  * @buf:       Pointer to the image (can be a read-only file-mapping)
  */
-void rkcommon_print_header(const void *buf);
+void rkcommon_print_header(const void *buf, struct image_tool_params *params);
 
 /**
  * rkcommon_need_rc4_spl() - check if rc4 encoded spl is required

diff --git a/tools/socfpgaimage.c b/tools/socfpgaimage.c
index eba812f..953dfee 100644 (file)
--- a/tools/socfpgaimage.c
+++ b/tools/socfpgaimage.c
@@ -313,7 +313,7 @@ static void socfpgaimage_print_header_v1(struct socfpga_header_v1 *header)
               le16_to_cpu(header->checksum));
 }
 
-static void socfpgaimage_print_header(const void *ptr)
+static void socfpgaimage_print_header(const void *ptr, struct image_tool_params *params)
 {
        const void *header = ptr + HEADER_OFFSET;
        struct socfpga_header_v0 *header_v0;

diff --git a/tools/stm32image.c b/tools/stm32image.c
index 18357c0..5c6991f 100644 (file)
--- a/tools/stm32image.c
+++ b/tools/stm32image.c
@@ -99,7 +99,7 @@ static int stm32image_verify_header(unsigned char *ptr, int image_size,
        return 0;
 }
 
-static void stm32image_print_header(const void *ptr)
+static void stm32image_print_header(const void *ptr, struct image_tool_params *params)
 {
        struct stm32_header *stm32hdr = (struct stm32_header *)ptr;
 

diff --git a/tools/sunxi_egon.c b/tools/sunxi_egon.c
index d45b6f5..a514427 100644 (file)
--- a/tools/sunxi_egon.c
+++ b/tools/sunxi_egon.c
@@ -82,7 +82,7 @@ static int egon_verify_header(unsigned char *ptr, int image_size,
        return EXIT_SUCCESS;
 }
 
-static void egon_print_header(const void *buf)
+static void egon_print_header(const void *buf, struct image_tool_params *params)
 {
        const struct boot_file_head *header = buf;
 

diff --git a/tools/sunxi_toc0.c b/tools/sunxi_toc0.c
index 7a8d74b..292649f 100644 (file)
--- a/tools/sunxi_toc0.c
+++ b/tools/sunxi_toc0.c
@@ -757,7 +757,7 @@ static const char *toc0_item_name(uint32_t name)
        return "(unknown)";
 }
 
-static void toc0_print_header(const void *buf)
+static void toc0_print_header(const void *buf, struct image_tool_params *params)
 {
        const struct toc0_main_info *main_info = buf;
        const struct toc0_item_info *item_info = (void *)(main_info + 1);

diff --git a/tools/ublimage.c b/tools/ublimage.c
index 1d2e897..8f9b58c 100644 (file)
--- a/tools/ublimage.c
+++ b/tools/ublimage.c
@@ -202,7 +202,7 @@ static int ublimage_verify_header(unsigned char *ptr, int image_size,
        return 0;
 }
 
-static void ublimage_print_header(const void *ptr)
+static void ublimage_print_header(const void *ptr, struct image_tool_params *params)
 {
        struct ubl_header *ubl_hdr = (struct ubl_header *) ptr;
 

diff --git a/tools/vybridimage.c b/tools/vybridimage.c
index 94a6684..c38886f 100644 (file)
--- a/tools/vybridimage.c
+++ b/tools/vybridimage.c
@@ -134,7 +134,7 @@ static void vybridimage_print_hdr_field(struct nand_page_0_boot_header *hdr,
        printf("header.fcb[%d] = %08x\n", idx, hdr->fcb[idx]);
 }
 
-static void vybridimage_print_header(const void *ptr)
+static void vybridimage_print_header(const void *ptr, struct image_tool_params *params)
 {
        struct nand_page_0_boot_header *hdr =
                (struct nand_page_0_boot_header *)ptr;

diff --git a/tools/zynqimage.c b/tools/zynqimage.c
index d3f418b..359c93d 100644 (file)
--- a/tools/zynqimage.c
+++ b/tools/zynqimage.c
@@ -163,7 +163,7 @@ static int zynqimage_verify_header(unsigned char *ptr, int image_size,
        return 0;
 }
 
-static void zynqimage_print_header(const void *ptr)
+static void zynqimage_print_header(const void *ptr, struct image_tool_params *params)
 {
        struct zynq_header *zynqhdr = (struct zynq_header *)ptr;
        int i;

diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c
index 19b2f02..5113ba8 100644 (file)
--- a/tools/zynqmpimage.c
+++ b/tools/zynqmpimage.c
@@ -209,7 +209,7 @@ static void print_partition(const void *ptr, const struct partition_header *ph)
        printf("    Checksum   : 0x%08x\n", le32_to_cpu(ph->checksum));
 }
 
-void zynqmpimage_print_header(const void *ptr)
+void zynqmpimage_print_header(const void *ptr, struct image_tool_params *params)
 {
        struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr;
        int i;

diff --git a/tools/zynqmpimage.h b/tools/zynqmpimage.h
index a1db819..9d526a1 100644 (file)
--- a/tools/zynqmpimage.h
+++ b/tools/zynqmpimage.h
@@ -133,6 +133,6 @@ struct zynqmp_header {
 };
 
 void zynqmpimage_default_header(struct zynqmp_header *ptr);
-void zynqmpimage_print_header(const void *ptr);
+void zynqmpimage_print_header(const void *ptr, struct image_tool_params *params);
 
 #endif /* _ZYNQMPIMAGE_H_ */