BF561-ACVILON BF561
+Brent Kandetzki <brentk@teleco.com>
+
+ IP04 BF532
+
#########################################################################
# End of MAINTAINERS list #
#########################################################################
cm-bf548 \
cm-bf561 \
ibf-dsp561 \
+ ip04 \
tcm-bf518 \
tcm-bf537 \
"
tcm-bf518 tcm-bf537
# Misc third party boards
-BFIN_BOARDS += bf537-minotaur bf537-srv1 bf561-acvilon blackstamp
+BFIN_BOARDS += bf537-minotaur bf537-srv1 bf561-acvilon blackstamp ip04
# I-SYST Micromodule
BFIN_BOARDS += ibf-dsp561
return 0;
}
-#ifdef CONFIG_SMC91111
+#ifdef CONFIG_SMC911X
int board_eth_init(bd_t *bis)
{
- return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+ return smc911x_initialize(0, CONFIG_SMC911X_BASE);
}
#endif
--- /dev/null
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2010 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+CFLAGS_lib_generic += -O2
+CFLAGS_lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
--- /dev/null
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2007 David Rowe,
+ * (c) 2006 Ivan Danov
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/net.h>
+
+int checkboard(void)
+{
+ printf("Board: IP04 IP-PBX\n");
+ printf(" http://www.rowetel.com/ucasterisk/ip04.html\n");
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+
+int misc_init_r(void)
+{
+ uchar enetaddr[6];
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+ puts("Warning: Generating 'random' MAC address\n");
+ bfin_gen_rand_mac(enetaddr);
+ eth_setenv_enetaddr("ethaddr", enetaddr);
+ }
+
+ return 0;
+}
+#endif
# define BFIN_BOOT_SPI_SSEL 1
#endif
+/* There is no Blackfin/NetBSD port */
+#undef CONFIG_BOOTM_NETBSD
+
/* We rarely use interrupts, so favor throughput over latency */
#define CONFIG_BFIN_INS_LOWOVERHEAD
/*
- * U-boot - ptrace.h
+ * Copyright 2004-2008 Analog Devices Inc.
*
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * Licensed under the GPL-2 or later.
*/
-#ifndef _BLACKFIN_PTRACE_H
-#define _BLACKFIN_PTRACE_H
-
-#define NEW_PT_REGS
+#ifndef _BFIN_PTRACE_H
+#define _BFIN_PTRACE_H
/*
* GCC defines register number like this:
* 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
* 32 - 33 A registers A0 & A1
* 34 - status register
+ * -----------------------------
*
* We follows above, except:
* 32-33 --- Low 32-bit of A0&1
* 34-35 --- High 8-bit of A0&1
*/
-#if defined(NEW_PT_REGS)
-
-#define PT_IPEND 0
-#define PT_SYSCFG (PT_IPEND+4)
-#define PT_SEQSTAT (PT_SYSCFG+4)
-#define PT_RETE (PT_SEQSTAT+4)
-#define PT_RETN (PT_RETE+4)
-#define PT_RETX (PT_RETN+4)
-#define PT_RETI (PT_RETX+4)
-#define PT_PC PT_RETI
-#define PT_RETS (PT_RETI+4)
-#define PT_RESERVED (PT_RETS+4)
-#define PT_ASTAT (PT_RESERVED+4)
-#define PT_LB1 (PT_ASTAT+4)
-#define PT_LB0 (PT_LB1+4)
-#define PT_LT1 (PT_LB0+4)
-#define PT_LT0 (PT_LT1+4)
-#define PT_LC1 (PT_LT0+4)
-#define PT_LC0 (PT_LC1+4)
-#define PT_A1W (PT_LC0+4)
-#define PT_A1X (PT_A1W+4)
-#define PT_A0W (PT_A1X+4)
-#define PT_A0X (PT_A0W+4)
-#define PT_B3 (PT_A0X+4)
-#define PT_B2 (PT_B3+4)
-#define PT_B1 (PT_B2+4)
-#define PT_B0 (PT_B1+4)
-#define PT_L3 (PT_B0+4)
-#define PT_L2 (PT_L3+4)
-#define PT_L1 (PT_L2+4)
-#define PT_L0 (PT_L1+4)
-#define PT_M3 (PT_L0+4)
-#define PT_M2 (PT_M3+4)
-#define PT_M1 (PT_M2+4)
-#define PT_M0 (PT_M1+4)
-#define PT_I3 (PT_M0+4)
-#define PT_I2 (PT_I3+4)
-#define PT_I1 (PT_I2+4)
-#define PT_I0 (PT_I1+4)
-#define PT_USP (PT_I0+4)
-#define PT_FP (PT_USP+4)
-#define PT_P5 (PT_FP+4)
-#define PT_P4 (PT_P5+4)
-#define PT_P3 (PT_P4+4)
-#define PT_P2 (PT_P3+4)
-#define PT_P1 (PT_P2+4)
-#define PT_P0 (PT_P1+4)
-#define PT_R7 (PT_P0+4)
-#define PT_R6 (PT_R7+4)
-#define PT_R5 (PT_R6+4)
-#define PT_R4 (PT_R5+4)
-#define PT_R3 (PT_R4+4)
-#define PT_R2 (PT_R3+4)
-#define PT_R1 (PT_R2+4)
-#define PT_R0 (PT_R1+4)
-#define PT_ORIG_R0 (PT_R0+4)
-#define PT_SR PT_SEQSTAT
-
-#else
-/*
- * Here utilize blackfin : dpregs = [pregs + imm16s4]
- * [pregs + imm16s4] = dpregs
- * to access defferent saved reg in stack
- */
-#define PT_R3 0
-#define PT_R4 4
-#define PT_R2 8
-#define PT_R1 12
-#define PT_P5 16
-#define PT_P4 20
-#define PT_P3 24
-#define PT_P2 28
-#define PT_P1 32
-#define PT_P0 36
-#define PT_R7 40
-#define PT_R6 44
-#define PT_R5 48
-#define PT_PC 52
-#define PT_SEQSTAT 56 /* so-called SR reg */
-#define PT_SR PT_SEQSTAT
-#define PT_ASTAT 60
-#define PT_RETS 64
-#define PT_A1w 68
-#define PT_A0w 72
-#define PT_A1x 76
-#define PT_A0x 80
-#define PT_ORIG_R0 84
-#define PT_R0 88
-#define PT_USP 92
-#define PT_FP 96
-#define PT_SP 100
-
-/* Added by HuTao, May26 2003 3:18PM */
-#define PT_IPEND 100
-
-/* Add SYSCFG register for single stepping support */
-#define PT_SYSCFG 104
-
-#endif
-
#ifndef __ASSEMBLY__
-#if defined(NEW_PT_REGS)
+struct task_struct;
+
/* this struct defines the way the registers are stored on the
- * stack during a system call.
- */
+ stack during a system call. */
+
struct pt_regs {
+ long orig_pc;
long ipend;
- long syscfg;
long seqstat;
long rete;
long retn;
long retx;
- long pc;
+ long pc; /* PC == RETI */
long rets;
- long reserved;
+ long reserved; /* Used as scratch during system calls */
long astat;
long lb1;
long lb0;
long r1;
long r0;
long orig_r0;
-};
-
-#else
-/* now we don't know what regs the system call will use */
-struct pt_regs {
- long r3;
- long r4;
- long r2;
- long r1;
- long p5;
- long p4;
- long p3;
- long p2;
- long p1;
- long p0;
- long r7;
- long r6;
- long r5;
- unsigned long pc;
- unsigned long seqstat;
- unsigned long astat;
- unsigned long rets;
- long a1w;
- long a0w;
- long a1x;
- long a0x;
- long orig_r0;
- long r0;
- long usp;
- long fp;
-/*
- * Added for supervisor/user mode switch.
- *
- * HuTao May26 03 3:23PM
- */
- long ipend;
+ long orig_p0;
long syscfg;
};
-#endif
-
/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13 /* ptrace signal */
+#define PTRACE_GETREGS 12
+#define PTRACE_SETREGS 13 /* ptrace signal */
+
+#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */
+#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */
+#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */
+
+#define PS_S (0x0002)
#ifdef __KERNEL__
-#ifndef PS_S
-#define PS_S (0x0c00)
+/* user_mode returns true if only one bit is set in IPEND, other than the
+ master interrupt enable. */
+#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
+#define instruction_pointer(regs) ((regs)->pc)
+#define user_stack_pointer(regs) ((regs)->usp)
+#define profile_pc(regs) instruction_pointer(regs)
+extern void show_regs(struct pt_regs *);
+
+#define arch_has_single_step() (1)
+extern void user_enable_single_step(struct task_struct *);
+/* see arch/blackfin/kernel/ptrace.c about this redirect */
+#define user_disable_single_step(child) ptrace_disable(child)
-/* Bit 11:10 of SEQSTAT defines user/supervisor/debug mode
- * 00: user
- * 01: supervisor
- * 1x: debug
+/*
+ * Get the address of the live pt_regs for the specified task.
+ * These are saved onto the top kernel stack when the process
+ * is not running.
+ *
+ * Note: if a user thread is execve'd from kernel space, the
+ * kernel stack will not be empty on entry to the kernel, so
+ * ptracing these tasks will fail.
*/
+#define task_pt_regs(task) \
+ (struct pt_regs *) \
+ ((unsigned long)task_stack_page(task) + \
+ (THREAD_SIZE - sizeof(struct pt_regs)))
-#define PS_M (0x1000) /* I am not sure why this is required here Akbar */
-#endif
+#endif /* __KERNEL__ */
-#define user_mode(regs) (!((regs)->seqstat & PS_S))
-#define instruction_pointer(regs) ((regs)->pc)
-extern void show_regs(struct pt_regs *);
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ */
-#endif
-#endif
-#endif
+#define PT_R0 204
+#define PT_R1 200
+#define PT_R2 196
+#define PT_R3 192
+#define PT_R4 188
+#define PT_R5 184
+#define PT_R6 180
+#define PT_R7 176
+#define PT_P0 172
+#define PT_P1 168
+#define PT_P2 164
+#define PT_P3 160
+#define PT_P4 156
+#define PT_P5 152
+#define PT_FP 148
+#define PT_USP 144
+#define PT_I0 140
+#define PT_I1 136
+#define PT_I2 132
+#define PT_I3 128
+#define PT_M0 124
+#define PT_M1 120
+#define PT_M2 116
+#define PT_M3 112
+#define PT_L0 108
+#define PT_L1 104
+#define PT_L2 100
+#define PT_L3 96
+#define PT_B0 92
+#define PT_B1 88
+#define PT_B2 84
+#define PT_B3 80
+#define PT_A0X 76
+#define PT_A0W 72
+#define PT_A1X 68
+#define PT_A1W 64
+#define PT_LC0 60
+#define PT_LC1 56
+#define PT_LT0 52
+#define PT_LT1 48
+#define PT_LB0 44
+#define PT_LB1 40
+#define PT_ASTAT 36
+#define PT_RESERVED 32
+#define PT_RETS 28
+#define PT_PC 24
+#define PT_RETX 20
+#define PT_RETN 16
+#define PT_RETE 12
+#define PT_SEQSTAT 8
+#define PT_IPEND 4
+
+#define PT_ORIG_R0 208
+#define PT_ORIG_P0 212
+#define PT_SYSCFG 216
+#define PT_TEXT_ADDR 220
+#define PT_TEXT_END_ADDR 224
+#define PT_DATA_ADDR 228
+#define PT_FDPIC_EXEC 232
+#define PT_FDPIC_INTERP 236
+
+#endif /* _BFIN_PTRACE_H */
/*
- * U-boot - traps.h
+ * Copyright 2004-2009 Analog Devices Inc.
+ * 2001 Lineo, Inc
+ * Tony Kou
+ * 1993 Hamish Macdonald
*
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * linux/include/asm/traps.h
- * Copyright (C) 1993 Hamish Macdonald
- * Lineo, Inc Jul 2001 Tony Kou
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * Licensed under the GPL-2
*/
-/*
- */
-
-#ifndef _BLACKFIN_TRAPS_H
-#define _BLACKFIN_TRAPS_H
-
-#ifndef __ASSEMBLY__
-typedef void (*e_vector) (void);
-extern e_vector vectors[];
-#endif
+#ifndef _BFIN_TRAPS_H
+#define _BFIN_TRAPS_H
#define VEC_SYS (0)
#define VEC_EXCPT01 (1)
#define VEC_CPLB_M (38)
#define VEC_CPLB_MHIT (39)
#define VEC_WATCH (40)
-#define VEC_ISTRU_VL (41)
+#define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */
#define VEC_MISALI_I (42)
#define VEC_CPLB_I_VL (43)
#define VEC_CPLB_I_M (44)
#define VEC_CPLB_I_MHIT (45)
#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
+/* The hardware reserves (63) for future use - we use it to tell our
+ * normal exception handling code we have a hardware error
+ */
+#define VEC_HWERR (63)
-#define VECOFF(vec) ((vec)<<2)
-
-#ifndef __ASSEMBLY__
-
-/* Status register bits */
-#define PS_T (0x8000)
-#define PS_S (0x0c00) /* Supervisor mode = 0b01 */
-#define PS_D (0x0c00) /* Debug mode = 0b1x */
-#define PS_M (0x1000)
-#define PS_C (0x0001)
-
-#endif
-#endif
+#endif /* _BFIN_TRAPS_H */
#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
#endif
+/* These are for board tests */
+#if 0
+#define CONFIG_BOOTCOMMAND "bootldr 0x203f0100"
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT \
+ "autoboot in %d seconds: press space to stop\n", bootdelay
+#define CONFIG_AUTOBOOT_STOP_STR " "
+#endif
+
/*
* Pull in common ADI header for remaining command/environment setup
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
-/* The next 2 lines are for use with DEV-BF5xx */
#define CONFIG_NET_MULTI
-#define CONFIG_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x28000300
-/* The next 3 lines are for use with EXT-BF5xx-USB-ETH2 */
-/* #define CONFIG_DRIVER_SMC911X 1 */
-/* #define CONFIG_DRIVER_SMC911X_BASE 0x24080000 /! AMS1 */
-/* #define CONFIG_DRIVER_SMC911X_32_BIT 1 */
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_BASE 0x24008000 /* AMS1 */
+#define CONFIG_SMC911X_16_BIT
#define CONFIG_HOSTNAME cm-bf561
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:cf */
#define CONFIG_ENV_OFFSET 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
/*
--- /dev/null
+/*
+ * U-boot - Configuration file for IP04 board (having BF532 processor)
+ *
+ * Copyright (c) 2006 Intratrade Ltd., Ivan Danov, idanov@gmail.com
+ *
+ * Copyright (c) 2005-2010 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __CONFIG_IP04_H__
+#define __CONFIG_IP04_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf532-0.5
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_NAND
+
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 10000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 40
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 3
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH 10
+#define CONFIG_MEM_SIZE 64
+
+#define CONFIG_EBIU_SDRRC_VAL 0x408
+#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2
+#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HOSTNAME IP04
+
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DM9000_NO_SROM
+#define CONFIG_DM9000_BASE 0x20100000
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_SYS_NO_FLASH /* we have only NAND */
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ 30000000
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_WINBOND
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_PREBOOT "echo starting from spi flash"
+#define CONFIG_ENV_OFFSET 0x30000
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+
+
+/*
+ * NAND Settings
+ */
+#define CONFIG_NAND_PLAT
+#define CONFIG_SYS_NAND_BASE 0x20000000
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
+#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
+#define BFIN_NAND_READY PF10
+#define BFIN_NAND_WRITE(addr, cmd) \
+ do { \
+ bfin_write8(addr, cmd); \
+ SSYNC(); \
+ } while (0)
+
+#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
+#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
+#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO_FLAG_D() & BFIN_NAND_READY)
+#define NAND_PLAT_INIT() \
+ do { \
+ bfin_write_FIO_DIR(bfin_read_FIO_DIR() & ~BFIN_NAND_READY); \
+ bfin_write_FIO_INEN(bfin_read_FIO_INEN() | BFIN_NAND_READY); \
+ bfin_write_FIO_EDGE(bfin_read_FIO_EDGE() & ~BFIN_NAND_READY); \
+ bfin_write_FIO_POLAR(bfin_read_FIO_POLAR() & ~BFIN_NAND_READY); \
+ } while (0)
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_MISC_INIT_R /* needed for MAC address */
+#define CONFIG_UART_CONSOLE 0
+
+#undef CONFIG_SHOW_BOOT_PROGRESS
+/* Enable this if bootretry required; currently it's disabled */
+#define CONFIG_BOOT_RETRY_TIME -1
+#define CONFIG_BOOTCOMMAND "run nandboot"
+#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
static void display_global_data(void)
{
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
bd_t *bd;
+
+#ifndef CONFIG_DEBUG_EARLY_SERIAL
+ return;
+#endif
+
bd = gd->bd;
printf(" gd: %p\n", gd);
printf(" |-flags: %lx\n", gd->flags);
printf(" |-baudrate: %lu\n", gd->baudrate);
printf(" |-have_console: %lx\n", gd->have_console);
printf(" |-ram_size: %lx\n", gd->ram_size);
- printf(" |-reloc_off: %lx\n", gd->reloc_off);
printf(" |-env_addr: %lx\n", gd->env_addr);
printf(" |-env_valid: %lx\n", gd->env_valid);
printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt));
printf(" |-bi_flashstart: %lx\n", bd->bi_flashstart);
printf(" |-bi_flashsize: %lx\n", bd->bi_flashsize);
printf(" \\-bi_flashoffset: %lx\n", bd->bi_flashoffset);
-#endif
}
#define CPLB_PAGE_SIZE (4 * 1024 * 1024)
* "continue" and != 0 means "fatal error, hang the system".
*/
+extern int watchdog_init(void);
extern int exception_init(void);
extern int irq_init(void);
extern int timer_init(void);
dcache_enable();
#endif
+#ifdef CONFIG_WATCHDOG
+ serial_early_puts("Setting up external watchdog\n");
+ watchdog_init();
+#endif
+
#ifdef DEBUG
if (CONFIG_SYS_GBL_DATA_SIZE < sizeof(*gd))
hang();
CROSS_COMPILE ?= bfin-uclinux-
-STANDALONE_LOAD_ADDR = 0x1000
+STANDALONE_LOAD_ADDR = 0x1000 -m elf32bfin
CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU)))
CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE)))
PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic
PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
-LDFLAGS += --gc-sections
+LDFLAGS += --gc-sections -m elf32bfin
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
ifneq (,$(CONFIG_BFIN_CPU))
/*
* U-boot - u-boot.lds.S
*
- * Copyright (c) 2005-2008 Analog Device Inc.
+ * Copyright (c) 2005-2010 Analog Device Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#include <asm/blackfin.h>
#undef ALIGN
#undef ENTRY
-#undef bfin
#ifndef LDS_BOARD_TEXT
# define LDS_BOARD_TEXT
.data :
{
- . = ALIGN(256);
+ . = ALIGN(4);
*(.data .data.*)
*(.data1)
*(.sdata)
projects / platform / kernel / u-boot.git / commitdiff