RISC-V: dts: jh7110: Change from bootph-pre-ram to u-boot,dm-spl

Mainline is using bootph-pre-ram instead of u-boot,dm-spl.
So it needs to use u-boot,dm-spl in current u-boot version.
Otherwise, spl doesn't work fine.

Thia patch is for only v2022.10. In latest version, this patch doesn't
need.

Change-Id: Ib7258f3d1dd8c892581cd568d72a54a4d59d4521
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
index 3c322c5..f8a738d 100644 (file)
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
@@ -7,63 +7,62 @@
 #include "jh7110-u-boot.dtsi"
 / {
        chosen {
-               bootph-pre-ram;
+               u-boot,dm-spl;
        };
 
        firmware {
                spi0 = &qspi;
-               bootph-pre-ram;
+               u-boot,dm-spl;
        };
 
        config {
-               bootph-pre-ram;
+               u-boot,dm-spl;
                u-boot,spl-payload-offset = <0x100000>;
        };
 
        memory@40000000 {
-               bootph-pre-ram;
+               u-boot,dm-spl;
        };
 };
 
 &uart0 {
-       bootph-pre-ram;
+       u-boot,dm-spl;
 };
 
 &mmc0 {
-       bootph-pre-ram;
+       u-boot,dm-spl;
 };
 
 &mmc1 {
-       bootph-pre-ram;
+       u-boot,dm-spl;
 };
 
 &qspi {
-       bootph-pre-ram;
+       u-boot,dm-spl;
 
        nor-flash@0 {
-               bootph-pre-ram;
+               u-boot,dm-spl;
        };
 };
 
 &sysgpio {
-       bootph-pre-ram;
+       u-boot,dm-spl;
 };
 
 &mmc0_pins {
-       bootph-pre-ram;
+       u-boot,dm-spl;
        mmc0-pins-rest {
-               bootph-pre-ram;
+               u-boot,dm-spl;
        };
 };
 
 &mmc1_pins {
-       bootph-pre-ram;
+       u-boot,dm-spl;
        mmc1-pins0 {
-               bootph-pre-ram;
+               u-boot,dm-spl;
        };
 
        mmc1-pins1 {
-               bootph-pre-ram;
+               u-boot,dm-spl;
        };
 };
-

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
index 3c322c5..f8a738d 100644 (file)
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
@@ -7,63 +7,62 @@
 #include "jh7110-u-boot.dtsi"
 / {
        chosen {
-               bootph-pre-ram;
+               u-boot,dm-spl;
        };
 
        firmware {
                spi0 = &qspi;
-               bootph-pre-ram;
+               u-boot,dm-spl;
        };
 
        config {
-               bootph-pre-ram;
+               u-boot,dm-spl;
                u-boot,spl-payload-offset = <0x100000>;
        };
 
        memory@40000000 {
-               bootph-pre-ram;
+               u-boot,dm-spl;
        };
 };
 
 &uart0 {
-       bootph-pre-ram;
+       u-boot,dm-spl;
 };
 
 &mmc0 {
-       bootph-pre-ram;
+       u-boot,dm-spl;
 };
 
 &mmc1 {
-       bootph-pre-ram;
+       u-boot,dm-spl;
 };
 
 &qspi {
-       bootph-pre-ram;
+       u-boot,dm-spl;
 
        nor-flash@0 {
-               bootph-pre-ram;
+               u-boot,dm-spl;
        };
 };
 
 &sysgpio {
-       bootph-pre-ram;
+       u-boot,dm-spl;
 };
 
 &mmc0_pins {
-       bootph-pre-ram;
+       u-boot,dm-spl;
        mmc0-pins-rest {
-               bootph-pre-ram;
+               u-boot,dm-spl;
        };
 };
 
 &mmc1_pins {
-       bootph-pre-ram;
+       u-boot,dm-spl;
        mmc1-pins0 {
-               bootph-pre-ram;
+               u-boot,dm-spl;
        };
 
        mmc1-pins1 {
-               bootph-pre-ram;
+               u-boot,dm-spl;
        };
 };
-

diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index c221195..31ca054 100644 (file)
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -7,54 +7,54 @@
 
 / {
        cpus: cpus {
-               bootph-pre-ram;
+               u-boot,dm-spl;
 
                S7_0: cpu@0 {
-                       bootph-pre-ram;
+                       u-boot,dm-spl;
                        status = "okay";
                        cpu0_intc: interrupt-controller {
-                               bootph-pre-ram;
+                               u-boot,dm-spl;
                        };
                };
 
                U74_1: cpu@1 {
-                       bootph-pre-ram;
+                       u-boot,dm-spl;
                        cpu1_intc: interrupt-controller {
-                               bootph-pre-ram;
+                               u-boot,dm-spl;
                        };
                };
 
                U74_2: cpu@2 {
-                       bootph-pre-ram;
+                       u-boot,dm-spl;
                        cpu2_intc: interrupt-controller {
-                               bootph-pre-ram;
+                               u-boot,dm-spl;
                        };
                };
 
                U74_3: cpu@3 {
-                       bootph-pre-ram;
+                       u-boot,dm-spl;
                        cpu3_intc: interrupt-controller {
-                               bootph-pre-ram;
+                               u-boot,dm-spl;
                        };
                };
 
                U74_4: cpu@4 {
-                       bootph-pre-ram;
+                       u-boot,dm-spl;
                        cpu4_intc: interrupt-controller {
-                               bootph-pre-ram;
+                               u-boot,dm-spl;
                        };
                };
        };
 
        soc {
-               bootph-pre-ram;
+               u-boot,dm-spl;
 
                clint: timer@2000000 {
-                       bootph-pre-ram;
+                       u-boot,dm-spl;
                };
 
                dmc: dmc@15700000 {
-                       bootph-pre-ram;
+                       u-boot,dm-spl;
                        compatible = "starfive,jh7110-dmc";
                        reg = <0x0 0x15700000 0x0 0x10000>,
                                <0x0 0x13000000 0x0 0x10000>;
@@ -70,28 +70,28 @@
 };
 
 &osc {
-       bootph-pre-ram;
+       u-boot,dm-spl;
 };
 
 &gmac0_rmii_refin {
-       bootph-pre-ram;
+       u-boot,dm-spl;
 };
 
 &aoncrg {
-       bootph-pre-ram;
+       u-boot,dm-spl;
 };
 
 &syscrg {
-       bootph-pre-ram;
+       u-boot,dm-spl;
        starfive,sys-syscon = <&sys_syscon>;
 };
 
 &stgcrg {
-       bootph-pre-ram;
+       u-boot,dm-spl;
 };
 
 &sys_syscon {
-       bootph-pre-ram;
+       u-boot,dm-spl;
 };
 
 &S7_0 {