# Board CPU #
#########################################################################
-Albert ARIBAUD <albert.aribaud@free.fr>
+Albert ARIBAUD <albert.u.boot@aribaud.net>
edminiv2 ARM926EJS (Orion5x SoC)
AT91RM9200DK at91rm9200
+Luca Ceresoli <luca.ceresoli@comelit.it>
+
+ dig297 ARM ARMV7 (OMAP3530 SoC)
+
Po-Yu Chuang <ratbert@faraday-tech.com>
a320evb FA526 (ARM920T-like) (a320 SoC)
impa7 ARM720T (EP7211)
ep7312 ARM720T (EP7312)
+Igor Grinberg <grinberg@compulab.co.il>
+
+ cm-t35 ARM ARMV7 (OMAP3xx Soc)
+
Kshitij Gupta <kshitij@ti.com>
omap1510inn ARM925T
galaxy5200 mpc5200
+Nagendra T S <nagendra@mistralsolutions.com>
+
+ am3517_crane ARM ARMV7 (AM35x SoC)
+
Rolf Offermanns <rof@sysgo.de>
shannon SA1100
at91sam9263ek ARM926EJS (AT91SAM9263 SoC)
at91sam9rlek ARM926EJS (AT91SAM9RL SoC)
-Mike Rapoport <mike@compulab.co.il>
-
- cm_t35 ARM ARMV7 (OMAP3xx SoC)
-
Tom Rix <Tom.Rix@windriver.com>
omap3_zoom2 ARM ARMV7 (OMAP3xx SoC)
## ARMV7 Systems
#########################################################################
LIST_ARMV7=" \
+ am3517_crane \
am3517_evm \
ca9x4_ct_vxp \
devkit8000 \
+ dig297 \
igep0020 \
igep0030 \
mx51evk \
-d $< $@
$(obj)u-boot.imx: $(obj)u-boot.bin
- $(obj)tools/mkimage -n $(IMX_CONFIG) -T imximage \
+ $(obj)tools/mkimage -n $(CONFIG_IMX_CONFIG) -T imximage \
-e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(obj)u-boot.kwb: $(obj)u-boot.bin
#========================================================================
#########################################################################
-## Atmel AT91RM9200 Systems
-#########################################################################
-
-CPUAT91_RAM_config \
-CPUAT91_config : unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a cpuat91 arm arm920t cpuat91 eukrea at91
-
-#########################################################################
## ARM926EJ-S Systems
#########################################################################
cp1026_config: unconfig
@board/armltd/integrator/split_by_variant.sh cp $@
-nhk8815_config \
-nhk8815_onenand_config: unconfig
- @mkdir -p $(obj)include
- @ > $(obj)include/config.h
- @if [ "$(findstring _onenand, $@)" ] ; then \
- echo "#define CONFIG_BOOT_ONENAND" >> $(obj)include/config.h; \
- fi
- @$(MKCONFIG) -n $@ -a nhk8815 arm arm926ejs nhk8815 st nomadik
-
xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$(subst _config,,$1))))
omap1610inn_config \
thus overwriting the architecutre dependent default
settings.
+- Frame Buffer Address:
+ CONFIG_FB_ADDR
+
+ Define CONFIG_FB_ADDR if you want to use specific address for
+ frame buffer.
+ Then system will reserve the frame buffer address to defined address
+ instead of lcd_setmem (this function grab the memory for frame buffer
+ by panel's size).
+
+ Please see board_init_f function.
+
+ If you want this config option then,
+ please define it at your board config file
+
Legacy uImage format:
Arg Where When
that is executed before the actual U-Boot. E.g. when
compiling a NAND SPL.
+- CONFIG_USE_ARCH_MEMCPY
+ CONFIG_USE_ARCH_MEMSET
+ If these options are used a optimized version of memcpy/memset will
+ be used if available. These functions may be faster under some
+ conditions but may increase the binary size.
+
Building the Software:
======================
*/
#include <common.h>
-#include <asm/arch/mx31-regs.h>
-#include <asm/arch/mx31.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
#ifdef CONFIG_SYS_MX31_UART1
void mx31_uart1_hw_init(void)
*/
#include <common.h>
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
#include <asm/io.h>
static u32 mx31_decode_pll(u32 reg, u32 infreq)
}
+struct mx3_cpu_type mx31_cpu_type[] = {
+ { .srev = 0x00, .v = "1.0" },
+ { .srev = 0x10, .v = "1.1" },
+ { .srev = 0x11, .v = "1.1" },
+ { .srev = 0x12, .v = "1.15" },
+ { .srev = 0x13, .v = "1.15" },
+ { .srev = 0x14, .v = "1.2" },
+ { .srev = 0x15, .v = "1.2" },
+ { .srev = 0x28, .v = "2.0" },
+ { .srev = 0x29, .v = "2.0" },
+};
+
+char *get_cpu_rev(void)
+{
+ u32 i, srev;
+
+ /* read SREV register from IIM module */
+ struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR;
+ srev = readl(&iim->iim_srev);
+
+ for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
+ if (srev == mx31_cpu_type[i].srev)
+ return mx31_cpu_type[i].v;
+ return "unknown";
+}
+
+char *get_reset_cause(void)
+{
+ /* read RCSR register from CCM module */
+ struct clock_control_regs *ccm =
+ (struct clock_control_regs *)CCM_BASE;
+
+ u32 cause = readl(&ccm->rcsr) & 0x07;
+
+ switch (cause) {
+ case 0x0000:
+ return "POR";
+ break;
+ case 0x0001:
+ return "RST";
+ break;
+ case 0x0002:
+ return "WDOG";
+ break;
+ case 0x0006:
+ return "JTAG";
+ break;
+ default:
+ return "unknown reset";
+ }
+}
+
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo (void)
{
- printf("CPU: Freescale i.MX31 at %d MHz\n",
- mx31_get_mcu_main_clk() / 1000000);
+ printf("CPU: Freescale i.MX31 rev %s at %d MHz.",
+ get_cpu_rev(), mx31_get_mcu_main_clk() / 1000000);
+ printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
#endif
*/
#include <common.h>
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
#include <div64.h>
+#include <watchdog.h>
+#include <asm/io.h>
#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
void reset_cpu (ulong addr)
{
- __REG16(WDOG_BASE) = 4;
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE;
+ wdog->wcr = WDOG_ENABLE;
+ while (1)
+ ;
}
+
+#ifdef CONFIG_HW_WATCHDOG
+void mxc_hw_watchdog_enable(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE;
+ u16 secs;
+
+ /*
+ * The timer watchdog can be set between
+ * 0.5 and 128 Seconds. If not defined
+ * in configuration file, sets 64 Seconds
+ */
+#ifdef CONFIG_SYS_WD_TIMER_SECS
+ secs = (CONFIG_SYS_WD_TIMER_SECS << 1) & 0xFF;
+ if (!secs) secs = 1;
+#else
+ secs = 64;
+#endif
+ writew(readw(&wdog->wcr) | (secs << WDOG_WT_SHIFT) | WDOG_ENABLE,
+ &wdog->wcr);
+}
+
+
+void mxc_hw_watchdog_reset(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE;
+
+ writew(0x5555, &wdog->wsr);
+ writew(0xAAAA, &wdog->wsr);
+}
+#endif
SOBJS += reset.o
COBJS += timer.o
-COBJS += ftsmc020.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/ftpmu010.h>
-#include <asm/arch/fttmr010.h>
+#include <faraday/ftpmu010.h>
+#include <faraday/fttmr010.h>
static ulong timestamp;
static ulong lastdec;
static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
-static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
#define TIMER_CLOCK 32768
#define TIMER_LOAD_VAL 0xffffffff
int timer_init(void)
{
- unsigned int oscc;
unsigned int cr;
debug("%s()\n", __func__);
/* disable timers */
writel(0, &tmr->cr);
- /*
- * use 32768Hz oscillator for RTC, WDT, TIMER
- */
-
- /* enable the 32768Hz oscillator */
- oscc = readl(&pmu->OSCC);
- oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI);
- writel(oscc, &pmu->OSCC);
-
- /* wait until ready */
- while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE))
- ;
-
- /* select 32768Hz oscillator */
- oscc = readl(&pmu->OSCC);
- oscc |= FTPMU010_OSCC_OSCL_RTCLSEL;
- writel(oscc, &pmu->OSCC);
+ /* use 32768Hz oscillator for RTC, WDT, TIMER */
+ ftpmu010_32768osc_enable();
/* setup timer */
writel(TIMER_LOAD_VAL, &tmr->timer3_load);
/* Enable GPIO clock */
writel(APBC_APBCLK, &apb1clkres->gpio);
+#ifdef CONFIG_I2C_MV
+ /* Enable general I2C clock */
+ writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
+ writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
+
+ /* Enable power I2C clock */
+ writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
+ writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
+#endif
+
/*
* Enable Functional and APB clock at 14.7456MHz
* for configured UART console
return 0;
}
#endif
+
+#ifdef CONFIG_I2C_MV
+void i2c_clk_enable(void)
+{
+}
+#endif
}
#ifdef CONFIG_MXC_UART
-void mx25_uart_init_pins (void)
+void mx25_uart1_init_pins(void)
{
struct iomuxc_mux_ctl *muxctl;
struct iomuxc_pad_ctl *padctl;
#
-# Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
#
# Based on original Kirkwood support which is
# (C) Copyright 2009
/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* Based on original Kirkwood support which is
* (C) Copyright 2009
/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* Based on original Kirkwood support which is
* (C) Copyright 2009
{
struct orion5x_ddr_addr_decode_registers *winregs =
(struct orion5x_ddr_addr_decode_registers *)
- ORION5X_CPU_WIN_BASE;
+ ORION5X_DRAM_BASE;
u32 result = 0;
u32 enable = 0x01 & winregs[bank].size;
/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* Based on original Kirkwood support which is
* Copyright (C) Marvell International Ltd. and its affiliates
/* Enable GPIO clock */
writel(APBC_APBCLK, &apbclkres->gpio);
+#ifdef CONFIG_I2C_MV
+ /* Enable I2C clock */
+ writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
+ writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
+#endif
+
icache_enable();
return 0;
return 0;
}
#endif
+
+#ifdef CONFIG_I2C_MV
+void i2c_clk_enable(void)
+{
+}
+#endif
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
- * Copyright (c) 2010 Albert Aribaud <albert.aribaud@free.fr>
+ * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
*
* See file CREDITS for list of people who contributed to this
* project.
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
- * Copyright (c) 2010 Albert Aribaud <albert.aribaud@free.fr>
+ * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
*
* See file CREDITS for list of people who contributed to this
* project.
return system_rev;
}
+static char *get_reset_cause(void)
+{
+ u32 cause;
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+ cause = readl(&src_regs->srsr);
+ writel(cause, &src_regs->srsr);
+
+ switch (cause) {
+ case 0x00001:
+ return "POR";
+ case 0x00004:
+ return "CSU";
+ case 0x00008:
+ return "IPP USER";
+ case 0x00010:
+ return "WDOG";
+ case 0x00020:
+ return "JTAG HIGH-Z";
+ case 0x00040:
+ return "JTAG SW";
+ case 0x10000:
+ return "WARM BOOT";
+ default:
+ return "unknown reset";
+ }
+}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
(cpurev & 0x000F0) >> 4,
(cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
+ printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
#endif
wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
}
+static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
+{
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ dpll_param *ptr = (dpll_param *) get_per2_dpll_param();
+
+ /* Moving it to the right sysclk base */
+ ptr = ptr + clk_index;
+
+ /* PER2 DPLL (DPLL5) */
+ sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);
+ wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
+ sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */
+ sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */
+ sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/
+ sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel); /* FREQSEL */
+ sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
+}
+
static void mpu_init_34xx(u32 sil_index, u32 clk_index)
{
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
dpll3_init_34xx(sil_index, clk_index);
dpll4_init_34xx(sil_index, clk_index);
+ dpll5_init_34xx(sil_index, clk_index);
iva_init_34xx(sil_index, clk_index);
mpu_init_34xx(sil_index, clk_index);
adr r0, per_dpll_param
mov pc, lr
+/* PER2 DPLL values */
+per2_dpll_param:
+/* 12MHz */
+.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
+
+/* 13MHz */
+.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
+
+/* 19.2MHz */
+.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
+
+/* 26MHz */
+.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
+
+/* 38.4MHz */
+.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
+
+.globl get_per2_dpll_param
+get_per2_dpll_param:
+ adr r0, per2_dpll_param
+ mov pc, lr
+
/*
* Tables for 36XX/37XX devices
*
#include <asm/arch/sys_proto.h>
#include <command.h>
-/*
- * Only One NAND allowed on board at a time.
- * The GPMC CS Base for the same
- */
-unsigned int boot_flash_base;
-unsigned int boot_flash_off;
-unsigned int boot_flash_sec;
-unsigned int boot_flash_type;
-volatile unsigned int boot_flash_env_addr;
-
struct gpmc *gpmc_cfg;
#if defined(CONFIG_CMD_NAND)
const u32 *gpmc_config = NULL;
u32 base = 0;
u32 size = 0;
-#if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_ONENAND)
- u32 f_off = CONFIG_SYS_MONITOR_LEN;
- u32 f_sec = 0;
-#endif
#endif
u32 config = 0;
base = PISMO1_NAND_BASE;
size = PISMO1_NAND_SIZE;
enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
-#if defined(CONFIG_ENV_IS_IN_NAND)
- f_off = SMNAND_ENV_OFFSET;
- f_sec = (128 << 10); /* 128 KiB */
- /* env setup */
- boot_flash_base = base;
- boot_flash_off = f_off;
- boot_flash_sec = f_sec;
- boot_flash_env_addr = f_off;
-#endif
#endif
#if defined(CONFIG_CMD_ONENAND)
base = PISMO1_ONEN_BASE;
size = PISMO1_ONEN_SIZE;
enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
- f_off = ONENAND_ENV_OFFSET;
- f_sec = (128 << 10); /* 128 KiB */
- /* env setup */
- boot_flash_base = base;
- boot_flash_off = f_off;
- boot_flash_sec = f_sec;
- boot_flash_env_addr = f_off;
-#endif
#endif
}
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_TEGRA2
+/*
+ * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s).
+ * U-Boot runs on the AVP first, setting things up for the CPU (PLLs,
+ * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU
+ * to pick up its reset vector, which points here.
+ */
+.globl _armboot_start
+_armboot_start:
+ .word _start
+#endif
+
/*
* These are defined in the board-specific linker script.
*/
orr r0, r0, #0xd3
msr cpsr,r0
-#if (CONFIG_OMAP34XX)
+#if defined(CONFIG_OMAP34XX)
/* Copy vectors to mask ROM indirect addr */
adr r0, _start @ r0 <- current position of code
add r0, r0, #4 @ skip reset vector
LIB = $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
-COBJS := board.o sys_info.o timer.o
+COBJS := ap20.o board.o sys_info.o timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
--- /dev/null
+/*
+* (C) Copyright 2010-2011
+* NVIDIA Corporation <www.nvidia.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include "ap20.h"
+#include <asm/io.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/pmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/scu.h>
+#include <common.h>
+
+u32 s_first_boot = 1;
+
+void init_pllx(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ /* If PLLX is already enabled, just return */
+ reg = readl(&clkrst->crc_pllx_base);
+ if (reg & PLL_ENABLE)
+ return;
+
+ /* Set PLLX_MISC */
+ reg = CPCON; /* CPCON[11:8] = 0001 */
+ writel(reg, &clkrst->crc_pllx_misc);
+
+ /* Use 12MHz clock here */
+ reg = (PLL_BYPASS | PLL_DIVM);
+ reg |= (1000 << 8); /* DIVN = 0x3E8 */
+ writel(reg, &clkrst->crc_pllx_base);
+
+ reg |= PLL_ENABLE;
+ writel(reg, &clkrst->crc_pllx_base);
+
+ reg &= ~PLL_BYPASS;
+ writel(reg, &clkrst->crc_pllx_base);
+}
+
+static void enable_cpu_clock(int enable)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg, clk;
+
+ /*
+ * NOTE:
+ * Regardless of whether the request is to enable or disable the CPU
+ * clock, every processor in the CPU complex except the master (CPU 0)
+ * will have it's clock stopped because the AVP only talks to the
+ * master. The AVP does not know (nor does it need to know) that there
+ * are multiple processors in the CPU complex.
+ */
+
+ if (enable) {
+ /* Initialize PLLX */
+ init_pllx();
+
+ /* Wait until all clocks are stable */
+ udelay(PLL_STABILIZATION_DELAY);
+
+ writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+ writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
+ }
+
+ /* Fetch the register containing the main CPU complex clock enable */
+ reg = readl(&clkrst->crc_clk_out_enb_l);
+ reg |= CLK_ENB_CPU;
+
+ /*
+ * Read the register containing the individual CPU clock enables and
+ * always stop the clock to CPU 1.
+ */
+ clk = readl(&clkrst->crc_clk_cpu_cmplx);
+ clk |= CPU1_CLK_STP;
+
+ if (enable) {
+ /* Unstop the CPU clock */
+ clk &= ~CPU0_CLK_STP;
+ } else {
+ /* Stop the CPU clock */
+ clk |= CPU0_CLK_STP;
+ }
+
+ writel(clk, &clkrst->crc_clk_cpu_cmplx);
+ writel(reg, &clkrst->crc_clk_out_enb_l);
+}
+
+static int is_cpu_powered(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
+}
+
+static void remove_cpu_io_clamps(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+
+ /* Remove the clamps on the CPU I/O signals */
+ reg = readl(&pmc->pmc_remove_clamping);
+ reg |= CPU_CLMP;
+ writel(reg, &pmc->pmc_remove_clamping);
+
+ /* Give I/O signals time to stabilize */
+ udelay(IO_STABILIZATION_DELAY);
+}
+
+static void powerup_cpu(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+ int timeout = IO_STABILIZATION_DELAY;
+
+ if (!is_cpu_powered()) {
+ /* Toggle the CPU power state (OFF -> ON) */
+ reg = readl(&pmc->pmc_pwrgate_toggle);
+ reg &= PARTID_CP;
+ reg |= START_CP;
+ writel(reg, &pmc->pmc_pwrgate_toggle);
+
+ /* Wait for the power to come up */
+ while (!is_cpu_powered()) {
+ if (timeout-- == 0)
+ printf("CPU failed to power up!\n");
+ else
+ udelay(10);
+ }
+
+ /*
+ * Remove the I/O clamps from CPU power partition.
+ * Recommended only on a Warm boot, if the CPU partition gets
+ * power gated. Shouldn't cause any harm when called after a
+ * cold boot according to HW, probably just redundant.
+ */
+ remove_cpu_io_clamps();
+ }
+}
+
+static void enable_cpu_power_rail(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+
+ reg = readl(&pmc->pmc_cntrl);
+ reg |= CPUPWRREQ_OE;
+ writel(reg, &pmc->pmc_cntrl);
+
+ /*
+ * The TI PMU65861C needs a 3.75ms delay between enabling
+ * the power rail and enabling the CPU clock. This delay
+ * between SM1EN and SM1 is for switching time + the ramp
+ * up of the voltage to the CPU (VDD_CPU from PMU).
+ */
+ udelay(3750);
+}
+
+static void reset_A9_cpu(int reset)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg, cpu;
+
+ /*
+ * NOTE: Regardless of whether the request is to hold the CPU in reset
+ * or take it out of reset, every processor in the CPU complex
+ * except the master (CPU 0) will be held in reset because the
+ * AVP only talks to the master. The AVP does not know that there
+ * are multiple processors in the CPU complex.
+ */
+
+ /* Hold CPU 1 in reset */
+ cpu = SET_DBGRESET1 | SET_DERESET1 | SET_CPURESET1;
+ writel(cpu, &clkrst->crc_cpu_cmplx_set);
+
+ reg = readl(&clkrst->crc_rst_dev_l);
+ if (reset) {
+ /* Now place CPU0 into reset */
+ cpu |= SET_DBGRESET0 | SET_DERESET0 | SET_CPURESET0;
+ writel(cpu, &clkrst->crc_cpu_cmplx_set);
+
+ /* Enable master CPU reset */
+ reg |= SWR_CPU_RST;
+ } else {
+ /* Take CPU0 out of reset */
+ cpu = CLR_DBGRESET0 | CLR_DERESET0 | CLR_CPURESET0;
+ writel(cpu, &clkrst->crc_cpu_cmplx_clr);
+
+ /* Disable master CPU reset */
+ reg &= ~SWR_CPU_RST;
+ }
+
+ writel(reg, &clkrst->crc_rst_dev_l);
+}
+
+static void clock_enable_coresight(int enable)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 rst, clk, src;
+
+ rst = readl(&clkrst->crc_rst_dev_u);
+ clk = readl(&clkrst->crc_clk_out_enb_u);
+
+ if (enable) {
+ rst &= ~SWR_CSITE_RST;
+ clk |= CLK_ENB_CSITE;
+ } else {
+ rst |= SWR_CSITE_RST;
+ clk &= ~CLK_ENB_CSITE;
+ }
+
+ writel(clk, &clkrst->crc_clk_out_enb_u);
+ writel(rst, &clkrst->crc_rst_dev_u);
+
+ if (enable) {
+ /*
+ * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by
+ * 1.5, giving an effective frequency of 144MHz.
+ * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
+ * (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
+ */
+ src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
+ writel(src, &clkrst->crc_clk_src_csite);
+
+ /* Unlock the CPU CoreSight interfaces */
+ rst = 0xC5ACCE55;
+ writel(rst, CSITE_CPU_DBG0_LAR);
+ writel(rst, CSITE_CPU_DBG1_LAR);
+ }
+}
+
+void start_cpu(u32 reset_vector)
+{
+ /* Enable VDD_CPU */
+ enable_cpu_power_rail();
+
+ /* Hold the CPUs in reset */
+ reset_A9_cpu(1);
+
+ /* Disable the CPU clock */
+ enable_cpu_clock(0);
+
+ /* Enable CoreSight */
+ clock_enable_coresight(1);
+
+ /*
+ * Set the entry point for CPU execution from reset,
+ * if it's a non-zero value.
+ */
+ if (reset_vector)
+ writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+
+ /* Enable the CPU clock */
+ enable_cpu_clock(1);
+
+ /* If the CPU doesn't already have power, power it up */
+ powerup_cpu();
+
+ /* Take the CPU out of reset */
+ reset_A9_cpu(0);
+}
+
+
+void halt_avp(void)
+{
+ for (;;) {
+ writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
+ | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
+ FLOW_CTLR_HALT_COP_EVENTS);
+ }
+}
+
+void enable_scu(void)
+{
+ struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
+ u32 reg;
+
+ /* If SCU already setup/enabled, return */
+ if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
+ return;
+
+ /* Invalidate all ways for all processors */
+ writel(0xFFFF, &scu->scu_inv_all);
+
+ /* Enable SCU - bit 0 */
+ reg = readl(&scu->scu_ctrl);
+ reg |= SCU_CTRL_ENABLE;
+ writel(reg, &scu->scu_ctrl);
+}
+
+void init_pmc_scratch(void)
+{
+ struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ int i;
+
+ /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
+ for (i = 0; i < 23; i++)
+ writel(0, &pmc->pmc_scratch1+i);
+
+ /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
+ writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20);
+}
+
+void cpu_start(void)
+{
+ struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+
+ /* enable JTAG */
+ writel(0xC0, &pmt->pmt_cfg_ctl);
+
+ if (s_first_boot) {
+ /*
+ * Need to set this before cold-booting,
+ * otherwise we'll end up in an infinite loop.
+ */
+ s_first_boot = 0;
+ cold_boot();
+ }
+}
+
+void tegra2_start()
+{
+ if (s_first_boot) {
+ /* Init Debug UART Port (115200 8n1) */
+ uart_init();
+
+ /* Init PMC scratch memory */
+ init_pmc_scratch();
+ }
+
+#ifdef CONFIG_ENABLE_CORTEXA9
+ /* take the mpcore out of reset */
+ cpu_start();
+
+ /* configure cache */
+ cache_configure();
+#endif
+}
--- /dev/null
+/*
+ * (C) Copyright 2010-2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <asm/types.h>
+
+/* Stabilization delays, in usec */
+#define PLL_STABILIZATION_DELAY (300)
+#define IO_STABILIZATION_DELAY (1000)
+
+#define NVBL_PLLP_KHZ (216000)
+
+#define PLLX_ENABLED (1 << 30)
+#define CCLK_BURST_POLICY 0x20008888
+#define SUPER_CCLK_DIVIDER 0x80000000
+
+/* Calculate clock fractional divider value from ref and target frequencies */
+#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
+
+/* Calculate clock frequency value from reference and clock divider value */
+#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
+
+/* AVP/CPU ID */
+#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
+#define PG_UP_TAG_0 0x0
+
+#define CORESIGHT_UNLOCK 0xC5ACCE55;
+
+/* AP20-Specific Base Addresses */
+
+/* AP20 Base physical address of SDRAM. */
+#define AP20_BASE_PA_SDRAM 0x00000000
+/* AP20 Base physical address of internal SRAM. */
+#define AP20_BASE_PA_SRAM 0x40000000
+/* AP20 Size of internal SRAM (256KB). */
+#define AP20_BASE_PA_SRAM_SIZE 0x00040000
+/* AP20 Base physical address of flash. */
+#define AP20_BASE_PA_NOR_FLASH 0xD0000000
+/* AP20 Base physical address of boot information table. */
+#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM
+
+/*
+ * Super-temporary stacks for EXTREMELY early startup. The values chosen for
+ * these addresses must be valid on ALL SOCs because this value is used before
+ * we are able to differentiate between the SOC types.
+ *
+ * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
+ * stack is placed below the AVP stack. Once the CPU stack has been moved,
+ * the AVP is free to use the IRAM the CPU stack previously occupied if
+ * it should need to do so.
+ *
+ * NOTE: In multi-processor CPU complex configurations, each processor will have
+ * its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
+ * limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
+ * stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
+ * CPU.
+ */
+
+/* Common AVP early boot stack limit */
+#define AVP_EARLY_BOOT_STACK_LIMIT \
+ (AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
+/* Common AVP early boot stack size */
+#define AVP_EARLY_BOOT_STACK_SIZE 0x1000
+/* Common CPU early boot stack limit */
+#define CPU_EARLY_BOOT_STACK_LIMIT \
+ (AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
+/* Common CPU early boot stack size */
+#define CPU_EARLY_BOOT_STACK_SIZE 0x1000
+
+#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
+#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
+#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
+#define FLOW_MODE_STOP 2
+#define HALT_COP_EVENT_JTAG (1 << 28)
+#define HALT_COP_EVENT_IRQ_1 (1 << 11)
+#define HALT_COP_EVENT_FIQ_1 (1 << 9)
+
+/* Prototypes */
+
+void tegra2_start(void);
+void uart_init(void);
+void udelay(unsigned long);
+void cold_boot(void);
+void cache_configure(void);
#include <config.h>
#include <version.h>
+
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE @ sdram load addr from config file
mov pc, lr @ back to arch calling code
+
+.globl startup_cpu
+startup_cpu:
+ @ Initialize the AVP, clocks, and memory controller
+ @ SDRAM is guaranteed to be on at this point
+
+ ldr r0, =cold_boot @ R0 = reset vector for CPU
+ bl start_cpu @ start the CPU
+
+ @ Transfer control to the AVP code
+ bl halt_avp
+
+ @ Should never get here
+_loop_forever2:
+ b _loop_forever2
+
+.globl cache_configure
+cache_configure:
+ stmdb r13!,{r14}
+ @ invalidate instruction cache
+ mov r1, #0
+ mcr p15, 0, r1, c7, c5, 0
+
+ @ invalidate the i&d tlb entries
+ mcr p15, 0, r1, c8, c5, 0
+ mcr p15, 0, r1, c8, c6, 0
+
+ @ enable instruction cache
+ mrc p15, 0, r1, c1, c0, 0
+ orr r1, r1, #(1<<12)
+ mcr p15, 0, r1, c1, c0, 0
+
+ bl enable_scu
+
+ @ enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg
+ mrc p15, 0, r0, c1, c0, 1
+ orr r0, r0, #0x41
+ mcr p15, 0, r0, c1, c0, 1
+
+ @ Now flush the Dcache
+ mov r0, #0
+ @ 256 cache lines
+ mov r1, #256
+
+invalidate_loop:
+ add r1, r1, #-1
+ mov r0, r1, lsl #5
+ @ invalidate d-cache using line (way0)
+ mcr p15, 0, r0, c7, c6, 2
+
+ orr r2, r0, #(1<<30)
+ @ invalidate d-cache using line (way1)
+ mcr p15, 0, r2, c7, c6, 2
+
+ orr r2, r0, #(2<<30)
+ @ invalidate d-cache using line (way2)
+ mcr p15, 0, r2, c7, c6, 2
+
+ orr r2, r0, #(3<<30)
+ @ invalidate d-cache using line (way3)
+ mcr p15, 0, r2, c7, c6, 2
+ cmp r1, #0
+ bne invalidate_loop
+
+ @ FIXME: should have ap20's L2 disabled too?
+invalidate_done:
+ ldmia r13!,{pc}
+
+.globl cold_boot
+cold_boot:
+ msr cpsr_c, #0xD3
+ @ Check current processor: CPU or AVP?
+ @ If CPU, go to CPU boot code, else continue on AVP path
+
+ ldr r0, =NV_PA_PG_UP_BASE
+ ldr r1, [r0]
+ ldr r2, =PG_UP_TAG_AVP
+
+ @ are we the CPU?
+ ldr sp, CPU_STACK
+ cmp r1, r2
+ @ yep, we are the CPU
+ bne _armboot_start
+
+ @ AVP initialization follows this path
+ ldr sp, AVP_STACK
+ @ Init AVP and start CPU
+ b startup_cpu
+
@ the literal pools origin
.ltorg
SRAM_STACK:
.word LOW_LEVEL_SRAM_STACK
+AVP_STACK:
+ .word EARLY_AVP_STACK
+CPU_STACK:
+ .word EARLY_CPU_STACK
START = start.o
COBJS += cpu.o
-COBJS += i2c.o
COBJS += pxafb.o
COBJS += timer.o
COBJS += usb.o
pxa_clock_setup();
return 0;
}
+
+void i2c_clk_enable(void)
+{
+ /* set the global I2C clock on */
+#ifdef CONFIG_CPU_MONAHANS
+ writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
+#else
+ writel(readl(CKEN) | CKEN14_I2C, CKEN);
+#endif
+}
#define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE
#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register
represents UART Unit Enable */
+/*
+ * I2C definition
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MV 1
+#define CONFIG_MV_I2C_NUM 2
+#define CONFIG_I2C_MULTI_BUS 1
+#define CONFIG_MV_I2C_REG {0xd4011000, 0xd4025000}
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 0
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+#endif
#endif /* _ARMD1_CONFIG_H */
* offset, pull,pF, drv,dF, edge,eF ,afn,aF
*/
/* UART1 */
-#define MFP107_UART1_TXD MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST
-#define MFP107_UART1_RXD MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST
-#define MFP108_UART1_RXD MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST
-#define MFP108_UART1_TXD MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST
-#define MFP109_UART1_CTS MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM
-#define MFP109_UART1_RTS MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM
-#define MFP110_UART1_RTS MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM
-#define MFP110_UART1_CTS MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM
-#define MFP111_UART1_RI MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM
-#define MFP111_UART1_DSR MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM
-#define MFP112_UART1_DTR MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM
-#define MFP112_UART1_DCD MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST)
+#define MFP107_UART1_RXD (MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST)
+#define MFP108_UART1_RXD (MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST)
+#define MFP108_UART1_TXD (MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST)
+#define MFP109_UART1_CTS (MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP109_UART1_RTS (MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP110_UART1_RTS (MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP110_UART1_CTS (MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP111_UART1_RI (MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP111_UART1_DSR (MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP112_UART1_DTR (MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP112_UART1_DCD (MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
/* UART2 */
-#define MFP47_UART2_RXD MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM
-#define MFP48_UART2_TXD MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM
-#define MFP88_UART2_RXD MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM
-#define MFP89_UART2_TXD MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP47_UART2_RXD (MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM)
+#define MFP48_UART2_TXD (MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM)
+#define MFP88_UART2_RXD (MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP89_UART2_TXD (MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM)
/* UART3 */
-#define MFPO8_UART3_RXD MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM
-#define MFPO9_UART3_TXD MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFPO8_UART3_RXD (MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFPO9_UART3_TXD (MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+
+/* I2c */
+#define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
/* More macros can be defined here... */
* MA 02111-1307 USA
*/
-#ifndef __ASM_ARCH_MX31_H
-#define __ASM_ARCH_MX31_H
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
extern u32 mx31_get_ipg_clk(void);
#define imx_get_uartclk mx31_get_ipg_clk
void mx31_uart1_hw_init(void);
void mx31_spi2_hw_init(void);
-#endif /* __ASM_ARCH_MX31_H */
+#endif /* __ASM_ARCH_CLOCK_H */
* MA 02111-1307 USA
*/
-#ifndef __ASM_ARCH_MX31_REGS_H
-#define __ASM_ARCH_MX31_REGS_H
+#ifndef __ASM_ARCH_MX31_IMX_REGS_H
+#define __ASM_ARCH_MX31_IMX_REGS_H
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
u32 test;
};
+/* Watchdog Timer (WDOG) registers */
+#define WDOG_ENABLE (1 << 2)
+#define WDOG_WT_SHIFT 8
+struct wdog_regs {
+ u16 wcr; /* Control */
+ u16 wsr; /* Service */
+ u16 wrsr; /* Reset Status */
+};
+
+/* IIM Control Registers */
+struct iim_regs {
+ u32 iim_stat;
+ u32 iim_statm;
+ u32 iim_err;
+ u32 iim_emask;
+ u32 iim_fctl;
+ u32 iim_ua;
+ u32 iim_la;
+ u32 iim_sdat;
+ u32 iim_prev;
+ u32 iim_srev;
+ u32 iim_prog_p;
+ u32 iim_scs0;
+ u32 iim_scs1;
+ u32 iim_scs2;
+ u32 iim_scs3;
+};
+
+struct mx3_cpu_type {
+ u8 srev;
+ char *v;
+};
+
#define IOMUX_PADNUM_MASK 0x1ff
#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
#define CCMR_FPM (1 << 1)
#define CCMR_CKIH (2 << 1)
+#define MX31_IIM_BASE_ADDR 0x5001C000
+
#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
#define MXC_EHCI_IPPUE_DOWN (1 << 8)
#define MXC_EHCI_IPPUE_UP (1 << 9)
-#endif /* __ASM_ARCH_MX31_REGS_H */
+#endif /* __ASM_ARCH_MX31_IMX_REGS_H */
extern dpll_param *get_iva_dpll_param(void);
extern dpll_param *get_core_dpll_param(void);
extern dpll_param *get_per_dpll_param(void);
+extern dpll_param *get_per2_dpll_param(void);
extern dpll_param *get_36x_mpu_dpll_param(void);
extern dpll_param *get_36x_iva_dpll_param(void);
#define PER_FSEL_38P4 0x07
#define PER_M2_38P4 0x09
+/* PER2 DPLL */
+#define PER2_M_12 0x78
+#define PER2_N_12 0x0B
+#define PER2_FSEL_12 0x03
+#define PER2_M2_12 0x01
+
+#define PER2_M_13 0x78
+#define PER2_N_13 0x0C
+#define PER2_FSEL_13 0x03
+#define PER2_M2_13 0x01
+
+#define PER2_M_19P2 0x2EE
+#define PER2_N_19P2 0x0B
+#define PER2_FSEL_19P2 0x06
+#define PER2_M2_19P2 0x0A
+
+#define PER2_M_26 0x78
+#define PER2_N_26 0x0C
+#define PER2_FSEL_26 0x03
+#define PER2_M2_26 0x01
+
+#define PER2_M_38P4 0x2EE
+#define PER2_N_38P4 0x0B
+#define PER2_FSEL_38P4 0x06
+#define PER2_M2_38P4 0x0A
+
/* 36XX PER DPLL */
#define PER_36XX_M_12 0x1B0
u32 clksel2_pll_mpu; /* 0x944 */
u8 res6[0xb8];
u32 fclken1_core; /* 0xa00 */
- u8 res7[0xc];
+ u32 res_fclken2_core;
+ u32 fclken3_core; /* 0xa08 */
+ u8 res7[0x4];
u32 iclken1_core; /* 0xa10 */
u32 iclken2_core; /* 0xa14 */
- u8 res8[0x28];
+ u32 iclken3_core; /* 0xa18 */
+ u8 res8[0x24];
u32 clksel_core; /* 0xa40 */
u8 res9[0xbc];
u32 fclken_gfx; /* 0xb00 */
u32 clksel_wkup; /* 0xc40 */
u8 res16[0xbc];
u32 clken_pll; /* 0xd00 */
- u8 res17[0x1c];
+ u32 clken2_pll; /* 0xd04 */
+ u8 res17[0x18];
u32 idlest_ckgen; /* 0xd20 */
- u8 res18[0x1c];
+ u32 idlest2_ckgen; /* 0xd24 */
+ u8 res18[0x18];
u32 clksel1_pll; /* 0xd40 */
u32 clksel2_pll; /* 0xd44 */
u32 clksel3_pll; /* 0xd48 */
- u8 res19[0xb4];
+ u32 clksel4_pll; /* 0xd4c */
+ u32 clksel5_pll; /* 0xd50 */
+ u8 res19[0xac];
u32 fclken_dss; /* 0xe00 */
u8 res20[0xc];
u32 iclken_dss; /* 0xe10 */
u32 clksel_per; /* 0x1040 */
u8 res28[0xfc];
u32 clksel1_emu; /* 0x1140 */
+ u8 res29[0x2bc];
+ u32 fclken_usbhost; /* 0x1400 */
+ u8 res30[0xc];
+ u32 iclken_usbhost; /* 0x1410 */
};
#else /* __ASSEMBLY__ */
#define CM_CLKSEL_CORE 0x48004a40
--- /dev/null
+/*
+ * (C) Copyright 2011
+ * Alexander Holler <holler@ahsoftware.de>
+ *
+ * Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37
+ *
+ * See there for additional Copyrights.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+#ifndef _EHCI_OMAP3_H_
+#define _EHCI_OMAP3_H_
+
+/* USB/EHCI registers */
+#define OMAP3_USBTLL_BASE 0x48062000UL
+#define OMAP3_UHH_BASE 0x48064000UL
+#define OMAP3_EHCI_BASE 0x48064800UL
+
+/* TLL Register Set */
+#define OMAP_USBTLL_SYSCONFIG (0x10)
+#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
+#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
+#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
+#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
+
+#define OMAP_USBTLL_SYSSTATUS (0x14)
+#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
+
+/* UHH Register Set */
+#define OMAP_UHH_SYSCONFIG (0x10)
+#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
+#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
+#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
+#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
+#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
+
+#define OMAP_UHH_HOSTCONFIG (0x40)
+#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
+#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
+#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
+
+#endif /* _EHCI_OMAP3_H_ */
--- /dev/null
+/*
+ * (c) 2011 Comelit Group SpA, Luca Ceresoli <luca.ceresoli@comelit.it>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAP3_REGS_H
+#define _OMAP3_REGS_H
+
+/*
+ * Register definitions for OMAP3 processors.
+ */
+
+/*
+ * GPMC_CONFIG1 - GPMC_CONFIG7
+ */
+
+/* Values for GPMC_CONFIG1 - signal control parameters */
+#define WRAPBURST (1 << 31)
+#define READMULTIPLE (1 << 30)
+#define READTYPE (1 << 29)
+#define WRITEMULTIPLE (1 << 28)
+#define WRITETYPE (1 << 27)
+#define CLKACTIVATIONTIME(x) (((x) & 3) << 25)
+#define ATTACHEDDEVICEPAGELENGTH(x) (((x) & 3) << 23)
+#define WAITREADMONITORING (1 << 22)
+#define WAITWRITEMONITORING (1 << 21)
+#define WAITMONITORINGTIME(x) (((x) & 3) << 18)
+#define WAITPINSELECT(x) (((x) & 3) << 16)
+#define DEVICESIZE(x) (((x) & 3) << 12)
+#define DEVICESIZE_8BIT DEVICESIZE(0)
+#define DEVICESIZE_16BIT DEVICESIZE(1)
+#define DEVICETYPE(x) (((x) & 3) << 10)
+#define DEVICETYPE_NOR DEVICETYPE(0)
+#define DEVICETYPE_NAND DEVICETYPE(2)
+#define MUXADDDATA (1 << 9)
+#define TIMEPARAGRANULARITY (1 << 4)
+#define GPMCFCLKDIVIDER(x) (((x) & 3) << 0)
+
+/* Values for GPMC_CONFIG2 - CS timing */
+#define CSWROFFTIME(x) (((x) & 0x1f) << 16)
+#define CSRDOFFTIME(x) (((x) & 0x1f) << 8)
+#define CSEXTRADELAY (1 << 7)
+#define CSONTIME(x) (((x) & 0xf) << 0)
+
+/* Values for GPMC_CONFIG3 - nADV timing */
+#define ADVWROFFTIME(x) (((x) & 0x1f) << 16)
+#define ADVRDOFFTIME(x) (((x) & 0x1f) << 8)
+#define ADVEXTRADELAY (1 << 7)
+#define ADVONTIME(x) (((x) & 0xf) << 0)
+
+/* Values for GPMC_CONFIG4 - nWE and nOE timing */
+#define WEOFFTIME(x) (((x) & 0x1f) << 24)
+#define WEEXTRADELAY (1 << 23)
+#define WEONTIME(x) (((x) & 0xf) << 16)
+#define OEOFFTIME(x) (((x) & 0x1f) << 8)
+#define OEEXTRADELAY (1 << 7)
+#define OEONTIME(x) (((x) & 0xf) << 0)
+
+/* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */
+#define PAGEBURSTACCESSTIME(x) (((x) & 0xf) << 24)
+#define RDACCESSTIME(x) (((x) & 0x1f) << 16)
+#define WRCYCLETIME(x) (((x) & 0x1f) << 8)
+#define RDCYCLETIME(x) (((x) & 0x1f) << 0)
+
+/* Values for GPMC_CONFIG6 - misc timings */
+#define WRACCESSTIME(x) (((x) & 0x1f) << 24)
+#define WRDATAONADMUXBUS(x) (((x) & 0xf) << 16)
+#define CYCLE2CYCLEDELAY(x) (((x) & 0xf) << 8)
+#define CYCLE2CYCLESAMECSEN (1 << 7)
+#define CYCLE2CYCLEDIFFCSEN (1 << 6)
+#define BUSTURNAROUND(x) (((x) & 0xf) << 0)
+
+/* Values for GPMC_CONFIG7 - CS address mapping configuration */
+#define MASKADDRESS(x) (((x) & 0xf) << 8)
+#define CSVALID (1 << 6)
+#define BASEADDRESS(x) (((x) & 0x3f) << 0)
+
+#endif /* _OMAP3_REGS_H */
/* CONTROL */
#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000)
+#ifndef __ASSEMBLY__
+/* Signal Integrity Parameter Control Registers */
+struct control_prog_io {
+ unsigned char res[0x408];
+ unsigned int io2; /* 0x408 */
+ unsigned char res2[0x38];
+ unsigned int io0; /* 0x444 */
+ unsigned int io1; /* 0x448 */
+};
+#endif /* __ASSEMBLY__ */
+
+/* Bit definition for CONTROL_PROG_IO1 */
+#define PRG_I2C2_PULLUPRESX 0x00000001
+
/* UART */
#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000)
#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000)
/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* Based on original Kirorion5x_ood support which is
* (C) Copyright 2009
/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* Based on original Kirkwood 88F6182 support which is
* (C) Copyright 2009
/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* Based on original Kirkwood support which is
* (C) Copyright 2009
#define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x)
/* Documented registers */
+#define ORION5X_DRAM_BASE (ORION5X_REGISTER(0x01500))
#define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000))
#define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000))
#define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100))
#define MV_UART_CONSOLE_BASE PANTHEON_UART1_BASE
#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register
represents UART Unit Enable */
+/*
+ * I2C definition
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MV 1
+#define CONFIG_MV_I2C_REG 0xd4011000
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 0
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+#endif
#endif /* _PANTHEON_CONFIG_H */
u32 uart0; /*0x000*/
u32 uart1; /*0x004*/
u32 gpio; /*0x008*/
- u8 pad0[0x034 - 0x08 - 4];
+ u8 pad0[0x02c - 0x08 - 4];
+ u32 twsi; /*0x02c*/
+ u8 pad1[0x034 - 0x2c - 4];
u32 timers; /*0x034*/
};
* offset, pull,pF, drv,dF, edge,eF ,afn,aF
*/
/* UART2 */
-#define MFP47_UART2_RXD MFP_REG(0x198) | MFP_AF6 | MFP_DRIVE_MEDIUM
-#define MFP48_UART2_TXD MFP_REG(0x19c) | MFP_AF6 | MFP_DRIVE_MEDIUM
+#define MFP47_UART2_RXD (MFP_REG(0x198) | MFP_AF6 | MFP_DRIVE_MEDIUM)
+#define MFP48_UART2_TXD (MFP_REG(0x19c) | MFP_AF6 | MFP_DRIVE_MEDIUM)
+#define MFP53_CI2C_SCL (MFP_REG(0x1b0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP54_CI2C_SDA (MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
/* More macros can be defined here... */
IrSR_XMITIR_IR_MODE)
/*
- * I2C registers
- */
-#define IBMR 0x40301680 /* I2C Bus Monitor Register - IBMR */
-#define IDBR 0x40301688 /* I2C Data Buffer Register - IDBR */
-#define ICR 0x40301690 /* I2C Control Register - ICR */
-#define ISR 0x40301698 /* I2C Status Register - ISR */
-#define ISAR 0x403016A0 /* I2C Slave Address Register - ISAR */
-
-#ifdef CONFIG_CPU_MONAHANS
-#define PWRIBMR 0x40f500C0 /* Power I2C Bus Monitor Register-IBMR */
-#define PWRIDBR 0x40f500C4 /* Power I2C Data Buffer Register-IDBR */
-#define PWRICR 0x40f500C8 /* Power I2C Control Register - ICR */
-#define PWRISR 0x40f500CC /* Power I2C Status Register - ISR */
-#define PWRISAR 0x40f500D0 /* Power I2C Slave Address Register-ISAR */
-#else
-#define PWRIBMR 0x40f00180 /* Power I2C Bus Monitor Register-IBMR */
-#define PWRIDBR 0x40f00188 /* Power I2C Data Buffer Register-IDBR */
-#define PWRICR 0x40f00190 /* Power I2C Control Register - ICR */
-#define PWRISR 0x40f00198 /* Power I2C Status Register - ISR */
-#define PWRISAR 0x40f001A0 /* Power I2C Slave Address Register-ISAR */
-#endif
-
-/* ----- Control register bits ---------------------------------------- */
-
-#define ICR_START 0x1 /* start bit */
-#define ICR_STOP 0x2 /* stop bit */
-#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
-#define ICR_TB 0x8 /* transfer byte bit */
-#define ICR_MA 0x10 /* master abort */
-#define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */
-#define ICR_IUE 0x40 /* unit enable */
-#define ICR_GCD 0x80 /* general call disable */
-#define ICR_ITEIE 0x100 /* enable tx interrupts */
-#define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */
-#define ICR_BEIE 0x400 /* enable bus error ints */
-#define ICR_SSDIE 0x800 /* slave STOP detected int enable */
-#define ICR_ALDIE 0x1000 /* enable arbitration interrupt */
-#define ICR_SADIE 0x2000 /* slave address detected int enable */
-#define ICR_UR 0x4000 /* unit reset */
-#define ICR_FM 0x8000 /* Fast Mode */
-
-/* ----- Status register bits ----------------------------------------- */
-
-#define ISR_RWM 0x1 /* read/write mode */
-#define ISR_ACKNAK 0x2 /* ack/nak status */
-#define ISR_UB 0x4 /* unit busy */
-#define ISR_IBB 0x8 /* bus busy */
-#define ISR_SSD 0x10 /* slave stop detected */
-#define ISR_ALD 0x20 /* arbitration loss detected */
-#define ISR_ITE 0x40 /* tx buffer empty */
-#define ISR_IRF 0x80 /* rx buffer full */
-#define ISR_GCAD 0x100 /* general call address detected */
-#define ISR_SAD 0x200 /* slave address detected */
-#define ISR_BED 0x400 /* bus error no ACK/NAK */
-
-/*
* Serial Audio Controller
*/
/* FIXME the audio defines collide w/ the SA1111 defines. I don't like these
uint crc_clk_src_csite; /*_CSITE_0, 0x1D4 */
uint crc_reserved19[9]; /* 0x1D8-1F8 */
uint crc_clk_src_osc; /*_OSC_0, 0x1FC */
+ uint crc_reserved20[80]; /* 0x200-33C */
+ uint crc_cpu_cmplx_set; /* _CPU_CMPLX_SET_0, 0x340 */
+ uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */
};
#define PLL_BYPASS (1 << 31)
#define PLL_DIVP (1 << 20) /* post divider, b22:20 */
#define PLL_DIVM 0x0C /* input divider, b4:0 */
-#define SWR_UARTD_RST (1 << 2)
-#define CLK_ENB_UARTD (1 << 2)
+#define SWR_UARTD_RST (1 << 1)
+#define CLK_ENB_UARTD (1 << 1)
#define SWR_UARTA_RST (1 << 6)
#define CLK_ENB_UARTA (1 << 6)
+#define SWR_CPU_RST (1 << 0)
+#define CLK_ENB_CPU (1 << 0)
+#define SWR_CSITE_RST (1 << 9)
+#define CLK_ENB_CSITE (1 << 9)
+
+#define SET_CPURESET0 (1 << 0)
+#define SET_DERESET0 (1 << 4)
+#define SET_DBGRESET0 (1 << 12)
+
+#define SET_CPURESET1 (1 << 1)
+#define SET_DERESET1 (1 << 5)
+#define SET_DBGRESET1 (1 << 13)
+
+#define CLR_CPURESET0 (1 << 0)
+#define CLR_DERESET0 (1 << 4)
+#define CLR_DBGRESET0 (1 << 12)
+
+#define CLR_CPURESET1 (1 << 1)
+#define CLR_DERESET1 (1 << 5)
+#define CLR_DBGRESET1 (1 << 13)
+
+#define CPU0_CLK_STP (1 << 8)
+#define CPU1_CLK_STP (1 << 9)
+
+#define CPCON (1 << 8)
+
#endif /* CLK_RST_H */
--- /dev/null
+/*
+ * Copyright (c) 2011, Google Inc. All rights reserved.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA2_GPIO_H_
+#define _TEGRA2_GPIO_H_
+
+/*
+ * The Tegra 2x GPIO controller has 222 GPIOs arranged in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS 4 /* The number of ports per bank */
+#define TEGRA_GPIO_BANKS 8 /* The number of banks */
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+ uint gpio_config[TEGRA_GPIO_PORTS];
+ uint gpio_dir_out[TEGRA_GPIO_PORTS];
+ uint gpio_out[TEGRA_GPIO_PORTS];
+ uint gpio_in[TEGRA_GPIO_PORTS];
+ uint gpio_int_status[TEGRA_GPIO_PORTS];
+ uint gpio_int_enable[TEGRA_GPIO_PORTS];
+ uint gpio_int_level[TEGRA_GPIO_PORTS];
+ uint gpio_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+ struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+#define GPIO_BANK(x) ((x) >> 5)
+#define GPIO_PORT(x) (((x) >> 3) & 0x3)
+#define GPIO_BIT(x) ((x) & 0x7)
+
+/*
+ * GPIO_PI3 = Port I = 8, bit = 3.
+ * Seaboard: used for UART/SPI selection
+ * Harmony: not used
+ */
+#define GPIO_PI3 ((8 << 3) | 3)
+
+#endif /* TEGRA2_GPIO_H_ */
uint pmc_gate; /* _GATE_0, offset 15C */
};
+#define CPU_PWRED 1
+#define CPU_CLMP 1
+
+#define PARTID_CP 0xFFFFFFF8
+#define START_CP (1 << 8)
+
+#define CPUPWRREQ_OE (1 << 16)
+
#endif /* PMC_H */
--- /dev/null
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SCU_H_
+#define _SCU_H_
+
+/* ARM Snoop Control Unit (SCU) registers */
+struct scu_ctlr {
+ uint scu_ctrl; /* SCU Control Register, offset 00 */
+ uint scu_cfg; /* SCU Config Register, offset 04 */
+ uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */
+ uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */
+ uint scu_reserved0[12]; /* reserved, offset 10-3C */
+ uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */
+ uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */
+ uint scu_reserved1[2]; /* reserved, offset 48-4C */
+ uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */
+ uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */
+};
+
+#define SCU_CTRL_ENABLE (1 << 0)
+
+#endif /* SCU_H */
#define _TEGRA2_H_
#define NV_PA_SDRAM_BASE 0x00000000
+#define NV_PA_ARM_PERIPHBASE 0x50040000
+#define NV_PA_PG_UP_BASE 0x60000000
#define NV_PA_TMRUS_BASE 0x60005010
#define NV_PA_CLK_RST_BASE 0x60006000
+#define NV_PA_FLOW_BASE 0x60007000
+#define NV_PA_GPIO_BASE 0x6000D000
+#define NV_PA_EVP_BASE 0x6000F000
#define NV_PA_APB_MISC_BASE 0x70000000
#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040)
#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300)
#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
#define NV_PA_PMC_BASE 0x7000E400
+#define NV_PA_CSITE_BASE 0x70040000
#define TEGRA2_SDRC_CS0 NV_PA_SDRAM_BASE
#define LOW_LEVEL_SRAM_STACK 0x4000FFFC
+#define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000)
+#define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096)
+#define PG_UP_TAG_AVP 0xAAAAAAAA
#ifndef __ASSEMBLY__
struct timerus {
--- /dev/null
+/*
+ * arch/arm/include/asm/assembler.h
+ *
+ * Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains arm architecture specific defines
+ * for the different processors.
+ *
+ * Do not include any C declarations in this file - it is included by
+ * assembler source.
+ */
+
+/*
+ * Endian independent macros for shifting bytes within registers.
+ */
+#ifndef __ARMEB__
+#define pull lsr
+#define push lsl
+#define get_byte_0 lsl #0
+#define get_byte_1 lsr #8
+#define get_byte_2 lsr #16
+#define get_byte_3 lsr #24
+#define put_byte_0 lsl #0
+#define put_byte_1 lsl #8
+#define put_byte_2 lsl #16
+#define put_byte_3 lsl #24
+#else
+#define pull lsl
+#define push lsr
+#define get_byte_0 lsr #24
+#define get_byte_1 lsr #16
+#define get_byte_2 lsr #8
+#define get_byte_3 lsl #0
+#define put_byte_0 lsl #24
+#define put_byte_1 lsl #16
+#define put_byte_2 lsl #8
+#define put_byte_3 lsl #0
+#endif
+
+/*
+ * Data preload for architectures that support it
+ */
+#if defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) || \
+ defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \
+ defined(__ARM_ARCH_6T2__) || defined(__ARM_ARCH_6Z__) || \
+ defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_7A__) || \
+ defined(__ARM_ARCH_7R__)
+#define PLD(code...) code
+#else
+#define PLD(code...)
+#endif
+
+/*
+ * Cache alligned
+ */
+#define CALGN(code...) code
#ifndef __ASM_ARM_STRING_H
#define __ASM_ARM_STRING_H
+#include <config.h>
+
/*
* We don't do inline string functions, since the
* optimised inline asm versions are not small.
#undef __HAVE_ARCH_STRCHR
extern char * strchr(const char * s, int c);
-#undef __HAVE_ARCH_MEMCPY
+#ifdef CONFIG_USE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMCPY
+#endif
extern void * memcpy(void *, const void *, __kernel_size_t);
#undef __HAVE_ARCH_MEMMOVE
extern void * memchr(const void *, int, __kernel_size_t);
#undef __HAVE_ARCH_MEMZERO
-#undef __HAVE_ARCH_MEMSET
+#ifdef CONFIG_USE_ARCH_MEMSET
+#define __HAVE_ARCH_MEMSET
+#endif
extern void * memset(void *, int, __kernel_size_t);
#if 0
endif
COBJS-y += interrupts.o
COBJS-y += reset.o
+SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o
+SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \
$(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
#endif /* CONFIG_VFD */
#ifdef CONFIG_LCD
+#ifdef CONFIG_FB_ADDR
+ gd->fb_base = CONFIG_FB_ADDR;
+#else
/* reserve memory for LCD display (always full pages) */
addr = lcd_setmem (addr);
gd->fb_base = addr;
+#endif /* CONFIG_FB_ADDR */
#endif /* CONFIG_LCD */
/*
CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp);
#endif
/* leave 3 words for abort-stack */
- addr_sp -= 3;
+ addr_sp -= 12;
/* 8-byte alignment for ABI compliance */
addr_sp &= ~0x07;
--- /dev/null
+/*
+ * linux/arch/arm/lib/memcpy.S
+ *
+ * Author: Nicolas Pitre
+ * Created: Sep 28, 2005
+ * Copyright: MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/assembler.h>
+
+#define W(instr) instr
+
+#define LDR1W_SHIFT 0
+#define STR1W_SHIFT 0
+
+ .macro ldr1w ptr reg abort
+ W(ldr) \reg, [\ptr], #4
+ .endm
+
+ .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
+ ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
+ .endm
+
+ .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
+ ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
+ .endm
+
+ .macro ldr1b ptr reg cond=al abort
+ ldr\cond\()b \reg, [\ptr], #1
+ .endm
+
+ .macro str1w ptr reg abort
+ W(str) \reg, [\ptr], #4
+ .endm
+
+ .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
+ stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
+ .endm
+
+ .macro str1b ptr reg cond=al abort
+ str\cond\()b \reg, [\ptr], #1
+ .endm
+
+ .macro enter reg1 reg2
+ stmdb sp!, {r0, \reg1, \reg2}
+ .endm
+
+ .macro exit reg1 reg2
+ ldmfd sp!, {r0, \reg1, \reg2}
+ .endm
+
+ .text
+
+/* Prototype: void *memcpy(void *dest, const void *src, size_t n); */
+
+.globl memcpy
+memcpy:
+
+ enter r4, lr
+
+ subs r2, r2, #4
+ blt 8f
+ ands ip, r0, #3
+ PLD( pld [r1, #0] )
+ bne 9f
+ ands ip, r1, #3
+ bne 10f
+
+1: subs r2, r2, #(28)
+ stmfd sp!, {r5 - r8}
+ blt 5f
+
+ CALGN( ands ip, r0, #31 )
+ CALGN( rsb r3, ip, #32 )
+ CALGN( sbcnes r4, r3, r2 ) @ C is always set here
+ CALGN( bcs 2f )
+ CALGN( adr r4, 6f )
+ CALGN( subs r2, r2, r3 ) @ C gets set
+ CALGN( add pc, r4, ip )
+
+ PLD( pld [r1, #0] )
+2: PLD( subs r2, r2, #96 )
+ PLD( pld [r1, #28] )
+ PLD( blt 4f )
+ PLD( pld [r1, #60] )
+ PLD( pld [r1, #92] )
+
+3: PLD( pld [r1, #124] )
+4: ldr8w r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
+ subs r2, r2, #32
+ str8w r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
+ bge 3b
+ PLD( cmn r2, #96 )
+ PLD( bge 4b )
+
+5: ands ip, r2, #28
+ rsb ip, ip, #32
+#if LDR1W_SHIFT > 0
+ lsl ip, ip, #LDR1W_SHIFT
+#endif
+ addne pc, pc, ip @ C is always clear here
+ b 7f
+6:
+ .rept (1 << LDR1W_SHIFT)
+ W(nop)
+ .endr
+ ldr1w r1, r3, abort=20f
+ ldr1w r1, r4, abort=20f
+ ldr1w r1, r5, abort=20f
+ ldr1w r1, r6, abort=20f
+ ldr1w r1, r7, abort=20f
+ ldr1w r1, r8, abort=20f
+ ldr1w r1, lr, abort=20f
+
+#if LDR1W_SHIFT < STR1W_SHIFT
+ lsl ip, ip, #STR1W_SHIFT - LDR1W_SHIFT
+#elif LDR1W_SHIFT > STR1W_SHIFT
+ lsr ip, ip, #LDR1W_SHIFT - STR1W_SHIFT
+#endif
+ add pc, pc, ip
+ nop
+ .rept (1 << STR1W_SHIFT)
+ W(nop)
+ .endr
+ str1w r0, r3, abort=20f
+ str1w r0, r4, abort=20f
+ str1w r0, r5, abort=20f
+ str1w r0, r6, abort=20f
+ str1w r0, r7, abort=20f
+ str1w r0, r8, abort=20f
+ str1w r0, lr, abort=20f
+
+ CALGN( bcs 2b )
+
+7: ldmfd sp!, {r5 - r8}
+
+8: movs r2, r2, lsl #31
+ ldr1b r1, r3, ne, abort=21f
+ ldr1b r1, r4, cs, abort=21f
+ ldr1b r1, ip, cs, abort=21f
+ str1b r0, r3, ne, abort=21f
+ str1b r0, r4, cs, abort=21f
+ str1b r0, ip, cs, abort=21f
+
+ exit r4, pc
+
+9: rsb ip, ip, #4
+ cmp ip, #2
+ ldr1b r1, r3, gt, abort=21f
+ ldr1b r1, r4, ge, abort=21f
+ ldr1b r1, lr, abort=21f
+ str1b r0, r3, gt, abort=21f
+ str1b r0, r4, ge, abort=21f
+ subs r2, r2, ip
+ str1b r0, lr, abort=21f
+ blt 8b
+ ands ip, r1, #3
+ beq 1b
+
+10: bic r1, r1, #3
+ cmp ip, #2
+ ldr1w r1, lr, abort=21f
+ beq 17f
+ bgt 18f
+
+
+ .macro forward_copy_shift pull push
+
+ subs r2, r2, #28
+ blt 14f
+
+ CALGN( ands ip, r0, #31 )
+ CALGN( rsb ip, ip, #32 )
+ CALGN( sbcnes r4, ip, r2 ) @ C is always set here
+ CALGN( subcc r2, r2, ip )
+ CALGN( bcc 15f )
+
+11: stmfd sp!, {r5 - r9}
+
+ PLD( pld [r1, #0] )
+ PLD( subs r2, r2, #96 )
+ PLD( pld [r1, #28] )
+ PLD( blt 13f )
+ PLD( pld [r1, #60] )
+ PLD( pld [r1, #92] )
+
+12: PLD( pld [r1, #124] )
+13: ldr4w r1, r4, r5, r6, r7, abort=19f
+ mov r3, lr, pull #\pull
+ subs r2, r2, #32
+ ldr4w r1, r8, r9, ip, lr, abort=19f
+ orr r3, r3, r4, push #\push
+ mov r4, r4, pull #\pull
+ orr r4, r4, r5, push #\push
+ mov r5, r5, pull #\pull
+ orr r5, r5, r6, push #\push
+ mov r6, r6, pull #\pull
+ orr r6, r6, r7, push #\push
+ mov r7, r7, pull #\pull
+ orr r7, r7, r8, push #\push
+ mov r8, r8, pull #\pull
+ orr r8, r8, r9, push #\push
+ mov r9, r9, pull #\pull
+ orr r9, r9, ip, push #\push
+ mov ip, ip, pull #\pull
+ orr ip, ip, lr, push #\push
+ str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f
+ bge 12b
+ PLD( cmn r2, #96 )
+ PLD( bge 13b )
+
+ ldmfd sp!, {r5 - r9}
+
+14: ands ip, r2, #28
+ beq 16f
+
+15: mov r3, lr, pull #\pull
+ ldr1w r1, lr, abort=21f
+ subs ip, ip, #4
+ orr r3, r3, lr, push #\push
+ str1w r0, r3, abort=21f
+ bgt 15b
+ CALGN( cmp r2, #0 )
+ CALGN( bge 11b )
+
+16: sub r1, r1, #(\push / 8)
+ b 8b
+
+ .endm
+
+
+ forward_copy_shift pull=8 push=24
+
+17: forward_copy_shift pull=16 push=16
+
+18: forward_copy_shift pull=24 push=8
+
--- /dev/null
+/*
+ * linux/arch/arm/lib/memset.S
+ *
+ * Copyright (C) 1995-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * ASM optimised string functions
+ */
+#include <asm/assembler.h>
+
+ .text
+ .align 5
+ .word 0
+
+1: subs r2, r2, #4 @ 1 do we have enough
+ blt 5f @ 1 bytes to align with?
+ cmp r3, #2 @ 1
+ strltb r1, [r0], #1 @ 1
+ strleb r1, [r0], #1 @ 1
+ strb r1, [r0], #1 @ 1
+ add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
+/*
+ * The pointer is now aligned and the length is adjusted. Try doing the
+ * memset again.
+ */
+
+.globl memset
+memset:
+ ands r3, r0, #3 @ 1 unaligned?
+ bne 1b @ 1
+/*
+ * we know that the pointer in r0 is aligned to a word boundary.
+ */
+ orr r1, r1, r1, lsl #8
+ orr r1, r1, r1, lsl #16
+ mov r3, r1
+ cmp r2, #16
+ blt 4f
+
+#if ! CALGN(1)+0
+
+/*
+ * We need an extra register for this loop - save the return address and
+ * use the LR
+ */
+ str lr, [sp, #-4]!
+ mov ip, r1
+ mov lr, r1
+
+2: subs r2, r2, #64
+ stmgeia r0!, {r1, r3, ip, lr} @ 64 bytes at a time.
+ stmgeia r0!, {r1, r3, ip, lr}
+ stmgeia r0!, {r1, r3, ip, lr}
+ stmgeia r0!, {r1, r3, ip, lr}
+ bgt 2b
+ ldmeqfd sp!, {pc} @ Now <64 bytes to go.
+/*
+ * No need to correct the count; we're only testing bits from now on
+ */
+ tst r2, #32
+ stmneia r0!, {r1, r3, ip, lr}
+ stmneia r0!, {r1, r3, ip, lr}
+ tst r2, #16
+ stmneia r0!, {r1, r3, ip, lr}
+ ldr lr, [sp], #4
+
+#else
+
+/*
+ * This version aligns the destination pointer in order to write
+ * whole cache lines at once.
+ */
+
+ stmfd sp!, {r4-r7, lr}
+ mov r4, r1
+ mov r5, r1
+ mov r6, r1
+ mov r7, r1
+ mov ip, r1
+ mov lr, r1
+
+ cmp r2, #96
+ tstgt r0, #31
+ ble 3f
+
+ and ip, r0, #31
+ rsb ip, ip, #32
+ sub r2, r2, ip
+ movs ip, ip, lsl #(32 - 4)
+ stmcsia r0!, {r4, r5, r6, r7}
+ stmmiia r0!, {r4, r5}
+ tst ip, #(1 << 30)
+ mov ip, r1
+ strne r1, [r0], #4
+
+3: subs r2, r2, #64
+ stmgeia r0!, {r1, r3-r7, ip, lr}
+ stmgeia r0!, {r1, r3-r7, ip, lr}
+ bgt 3b
+ ldmeqfd sp!, {r4-r7, pc}
+
+ tst r2, #32
+ stmneia r0!, {r1, r3-r7, ip, lr}
+ tst r2, #16
+ stmneia r0!, {r4-r7}
+ ldmfd sp!, {r4-r7, lr}
+
+#endif
+
+4: tst r2, #8
+ stmneia r0!, {r1, r3}
+ tst r2, #4
+ strne r1, [r0], #4
+/*
+ * When we get here, we've got less than 4 bytes to zero. We
+ * may have an unaligned pointer as well.
+ */
+5: tst r2, #2
+ strneb r1, [r0], #1
+ strneb r1, [r0], #1
+ tst r2, #1
+ strneb r1, [r0], #1
+ mov pc, lr
debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
#ifdef CONFIG_LCD
+#ifdef CONFIG_FB_ADDR
+ gd->fb_base = CONFIG_FB_ADDR;
+#else
/* reserve memory for LCD display (always full pages) */
addr = lcd_setmem (addr);
gd->fb_base = addr;
+#endif /* CONFIG_FB_ADDR */
#endif /* CONFIG_LCD */
/*
debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
#ifdef CONFIG_LCD
+#ifdef CONFIG_FB_ADDR
+ gd->fb_base = CONFIG_FB_ADDR;
+#else
/* reserve memory for LCD display (always full pages) */
addr = lcd_setmem (addr);
gd->fb_base = addr;
+#endif /* CONFIG_FB_ADDR */
#endif /* CONFIG_LCD */
#if defined(CONFIG_VIDEO) && defined(CONFIG_8xx)
#
-# Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
#
# Based on original Kirkwood support which is
# (C) Copyright 2009
#
-# Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
#
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
int board_early_init_f(void)
{
u32 mfp_cfg[] = {
+ /* I2C */
+ MFP105_CI2C_SDA,
+ MFP106_CI2C_SCL,
+
/* Enable Console on UART1 */
MFP107_UART1_RXD,
MFP108_UART1_TXD,
+
MFP_EOC /*End of configureation*/
};
/* configure MFP's */
MFP47_UART2_RXD,
MFP48_UART2_TXD,
+ /* I2C */
+ MFP53_CI2C_SCL,
+ MFP54_CI2C_SDA,
+
MFP_EOC /*End of configureation*/
};
/* configure MFP's */
+++ /dev/null
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-# Linux-Kernel is expected to be at 0x60008000
-#
-CONFIG_SYS_TEXT_BASE = 0x60800000
LIB = $(obj)lib$(BOARD).o
-COBJS := cm_t35.o
+COBJS := cm_t35.o leds.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
/*
- * (C) Copyright 2010
+ * (C) Copyright 2011
* CompuLab, Ltd. <www.compulab.co.il>
*
- * Author: Mike Rapoport <mike@compulab.co.il>
+ * Authors: Mike Rapoport <mike@compulab.co.il>
+ * Igor Grinberg <grinberg@compulab.co.il>
*
* Derived from omap3evm and Beagle Board by
* Manikandan Pillai <mani.pillai@ti.com>
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc.
*/
#include <common.h>
+#include <status_led.h>
#include <netdev.h>
#include <net.h>
#include <i2c.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-types.h>
+DECLARE_GLOBAL_DATA_PTR;
+
const omap3_sysinfo sysinfo = {
DDR_DISCRETE,
- "CM-T35 board",
+ "CM-T3x board",
"NAND",
};
*/
int board_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);
/* board id for Linux */
- gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
+ if (get_cpu_family() == CPU_OMAP34XX)
+ gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
+ else
+ gd->bd->bi_arch_number = MACH_TYPE_CM_T3730;
+
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+
return 0;
}
/*
* Routine: misc_init_r
- * Description: Init I2C and display die ID
+ * Description: display die ID
*/
int misc_init_r(void)
{
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
dieid_num_r();
return 0;
* hardware. Many pins need to be moved from protect to primary
* mode.
*/
-void set_muxconf_regs(void)
+static void cm_t3x_set_common_muxconf(void)
{
/* SDRC */
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
/* SB-T35 Ethernet */
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
- /* CM-T35 Ethernet */
+ /* CM-T3x Ethernet */
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/
/* serial interface */
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/
- MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M4)); /*green LED*/
+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
+
+ /* MMC1 */
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
+}
+
+static void cm_t35_set_muxconf(void)
+{
+ /* DSS */
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/
+
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/
+
+ /* MMC1 */
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/
}
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
+static void cm_t3730_set_muxconf(void)
{
- return omap_mmc_init(0);
+ /* DSS */
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/
+
+ MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/
+ MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/
+ MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/
+ MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/
+ MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/
+}
+
+void set_muxconf_regs(void)
+{
+ cm_t3x_set_common_muxconf();
+
+ if (get_cpu_family() == CPU_OMAP34XX)
+ cm_t35_set_muxconf();
+ else
+ cm_t3730_set_muxconf();
}
-#endif
/*
* Routine: setup_net_chip_gmpc
struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5],
- CM_T35_SMC911X_BASE, GPMC_SIZE_16M);
+ CM_T3X_SMC911X_BASE, GPMC_SIZE_16M);
enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4],
SB_T35_SMC911X_BASE, GPMC_SIZE_16M);
rc1 = handle_mac_address();
if (rc1)
- printf("CM-T35: No MAC address found\n");
+ printf("CM-T3x: No MAC address found\n");
- rc1 = smc911x_initialize(0, CM_T35_SMC911X_BASE);
+ rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE);
if (rc1 > 0)
rc++;
--- /dev/null
+/*
+ * (C) Copyright 2011
+ * CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Author: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#include <common.h>
+#include <status_led.h>
+#include <asm/arch/gpio.h>
+
+static unsigned int leds[] = { GREEN_LED_GPIO };
+
+void __led_init(led_id_t mask, int state)
+{
+ if (omap_request_gpio(leds[mask]) != 0) {
+ printf("%s: failed requesting GPIO%u\n", __func__, leds[mask]);
+ return;
+ }
+
+ omap_set_gpio_direction(leds[mask], 0);
+}
+
+void __led_set(led_id_t mask, int state)
+{
+ omap_set_gpio_dataout(leds[mask], state == STATUS_LED_ON);
+}
+
+void __led_toggle(led_id_t mask)
+{
+ omap_set_gpio_dataout(leds[mask], !omap_get_gpio_datain(leds[mask]));
+}
#
-# Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
# MA 02111-1307 USA
#
-IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
-ALL += $(obj)u-boot.imx
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := dig297.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2011 Comelit Group SpA
+ * Luca Ceresoli <luca.ceresoli@comelit.it>
+ *
+ * Based on board/ti/beagle/beagle.c:
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/omap3-regs.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "dig297.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_NET
+static void setup_net_chip(void);
+
+#define NET_LAN9221_RESET_GPIO 12
+
+/* GPMC CS 5 connected to an SMSC LAN9220 ethernet controller */
+#define NET_LAN9220_GPMC_CONFIG1 (DEVICESIZE_16BIT)
+#define NET_LAN9220_GPMC_CONFIG2 (CSWROFFTIME(8) | \
+ CSRDOFFTIME(7) | \
+ ADVONTIME(1))
+#define NET_LAN9220_GPMC_CONFIG3 (ADVWROFFTIME(2) | \
+ ADVRDOFFTIME(2) | \
+ ADVONTIME(1))
+#define NET_LAN9220_GPMC_CONFIG4 (WEOFFTIME(8) | \
+ WEONTIME(1) | \
+ OEOFFTIME(7)| \
+ OEONTIME(1))
+#define NET_LAN9220_GPMC_CONFIG5 (PAGEBURSTACCESSTIME(0) | \
+ RDACCESSTIME(6) | \
+ WRCYCLETIME(0x1D) | \
+ RDCYCLETIME(0x1D))
+#define NET_LAN9220_GPMC_CONFIG6 ((1 << 31) | \
+ WRACCESSTIME(0x1D) | \
+ WRDATAONADMUXBUS(3))
+
+static const u32 gpmc_lan_config[] = {
+ NET_LAN9220_GPMC_CONFIG1,
+ NET_LAN9220_GPMC_CONFIG2,
+ NET_LAN9220_GPMC_CONFIG3,
+ NET_LAN9220_GPMC_CONFIG4,
+ NET_LAN9220_GPMC_CONFIG5,
+ NET_LAN9220_GPMC_CONFIG6,
+ /* CONFIG7: computed by enable_gpmc_cs_config() */
+};
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CPS;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ struct gpio *gpio1_base = (struct gpio *)OMAP34XX_GPIO1_BASE;
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+
+ twl4030_power_init();
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+
+ /*
+ * GPIO list
+ * - 159 OUT (GPIO5+31): reset for remote camera interface connector.
+ * - 19 OUT (GPIO1+19): integrated speaker amplifier (1=on, 0=shdn).
+ * - 20 OUT (GPIO1+20): handset amplifier (1=on, 0=shdn).
+ */
+
+ /* Configure GPIOs to output */
+ writel(~(GPIO19 | GPIO20), &gpio1_base->oe);
+ writel(~(GPIO31), &gpio5_base->oe);
+
+ /* Set GPIO values */
+ writel((GPIO19 | GPIO20), &gpio1_base->setdataout);
+ writel(0, &gpio5_base->setdataout);
+
+#if defined(CONFIG_CMD_NET)
+ setup_net_chip();
+#endif
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_DIG297();
+}
+
+#ifdef CONFIG_CMD_NET
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ /* Configure GPMC registers */
+ enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
+ CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+
+ /* Make GPIO 12 as output pin and send a magic pulse through it */
+ if (!omap_request_gpio(NET_LAN9221_RESET_GPIO)) {
+ omap_set_gpio_direction(NET_LAN9221_RESET_GPIO, 0);
+ omap_set_gpio_dataout(NET_LAN9221_RESET_GPIO, 1);
+ udelay(1);
+ omap_set_gpio_dataout(NET_LAN9221_RESET_GPIO, 0);
+ udelay(31000); /* Should be >= 30ms according to datasheet */
+ omap_set_gpio_dataout(NET_LAN9221_RESET_GPIO, 1);
+ }
+}
+#endif /* CONFIG_CMD_NET */
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+ return rc;
+}
--- /dev/null
+/*
+ * (C) Copyright 2011 Comelit Group SpA
+ * Luca Ceresoli <luca.ceresoli@comelit.it>
+ *
+ * Based on board/ti/beagle/beagle.h:
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _DIG297_H_
+#define _DIG297_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_STACKED,
+ "OMAP3 DIG297 board",
+ "NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_DIG297() \
+/*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)) /*sdrc_cke1: NC*/\
+/*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*NAND*/\
+ /* GPMC_nCS1/2: not available on CUS package*/\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | DIS | M0)) /*GPMC_nCS4*/\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\
+ MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M0)) /*GPMC_nBE1: NC*/\
+ /* GPMC_WAIT2: not available on CUS package*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | DIS | M0)) /*GPMC_WAIT3: NC*/\
+ /* GPMC_CLK: NC (only asyncronous peripherals are connected) */\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ /* GPMC_WAIT1: not available on CUS package*/\
+/*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ /* DSS_ACBIAS: AC BIAS: connected to TFT, not to be driven */\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTU | EN | M7))\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+/*CAMERA*/\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
+/*Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+/*Expansion card */\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
+/*Wireless LAN */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+/*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
+ MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
+ MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144*/\
+ MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
+ MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
+/*Modem Interface */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+ MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
+ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
+ MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
+ MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
+/*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
+/* USB EHCI (port 2) */\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA0*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA1*/\
+/* MCSPI1: to TOUCH controller TSC2046 (ADS7846 compatible).*/\
+ /*
+ * McSPI1_CLK.
+ * IEN needed fot the McSPI to "receive" the clock and be able to
+ * sample SOMI. See http://e2e.ti.com/support/arm174_microprocessors/
+ * omap_applications_processors/f/42/p/29444/102394.aspx#102394
+ */\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTD | EN | M0)) /*McSPI1_SIMO*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M0)) /*McSPI1_SOMI*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTU | EN | M0)) /*McSPI1_CS0*/\
+/* MCSPI2: to HIMAX TFT controller.*/\
+ MUX_VAL(CP(MCSPI2_CLK), (IDIS | PTD | EN | M0)) /*MCSPI2_CLK*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | EN | M0)) /*MCSPI3_SIMO*/\
+ /* MCSPI3_SOMI: NC because HIMAX in monodirectional (no SOMI line) */\
+ MUX_VAL(CP(MCSPI2_SOMI), (IDIS | PTU | DIS | M7))\
+ MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTU | EN | M0)) /*MCSPI3_CS0*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTU | DIS | M7)) /*Safe mode: NC*/\
+/* GPIO */\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M4)) /*GPIO_12*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M4)) /*GPIO_13*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M4)) /*GPIO_14*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTD | EN | M4)) /*GPIO_15*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTD | EN | M4)) /*GPIO_16*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M4)) /*GPIO_17*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IDIS | PTD | EN | M4)) /*GPIO_18*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IDIS | PTD | EN | M4)) /*GPIO_19*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IDIS | PTD | EN | M4)) /*GPIO_20*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IDIS | PTD | EN | M4)) /*GPIO_21*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M4)) /*GPIO_23*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | EN | M4)) /*GPIO_24*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | EN | M4)) /*GPIO_25*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IDIS | PTD | EN | M4)) /*GPIO_26*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IDIS | PTD | EN | M4)) /*GPIO_27*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M4)) /*GPIO_156*/\
+ MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
+ MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M4)) /*GPIO_161*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | EN | M4)) /*GPIO_164*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | DIS | M4)) /*GPIO_170*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) /*GPIO_177*/\
+/*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */
+
+#endif
*/
#include <common.h>
-#include <asm/arch/mx31.h>
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
#include <mxc_gpio.h>
#include <fpga.h>
#include <lattice.h>
* MA 02111-1307 USA
*/
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
.macro REG reg, val
ldr r2, =\reg
#include <common.h>
#include <netdev.h>
-#include <asm/arch/mx31.h>
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include <nand.h>
#include <fsl_pmic.h>
#include <mxc_gpio.h>
#include "qong_fpga.h"
+#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_HW_WATCHDOG
+void hw_watchdog_reset(void)
+{
+ mxc_hw_watchdog_reset();
+}
+#endif
+
int dram_init (void)
{
/* dram_init must store complete ramsize in gd->ram_size */
pmic_reg_write(REG_POWER_CTL0, val | COINCHEN);
pmic_reg_write(REG_INT_STATUS1, RTCRSTI);
+#ifdef CONFIG_HW_WATCHDOG
+ mxc_hw_watchdog_enable();
+#endif
+
return 0;
}
+++ /dev/null
-CONFIG_SYS_TEXT_BASE = 0x21f00000
#include <common.h>
#include <asm/sizes.h>
#include <asm/arch/at91sam9260.h>
-#include <asm/arch/at91sam9_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
-#include <asm/arch/gpio.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
#include <asm/arch/io.h>
#include <asm/arch/hardware.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
static void cpu9260_nand_hw_init(void)
{
unsigned long csa;
+ at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE;
+ at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
/* Enable CS3 */
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
- at91_sys_write(AT91_MATRIX_EBICSA,
- csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+ csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
+ writel(csa, &matrix->csa);
/* Configure SMC CS3 for NAND/SmartMedia */
#if defined(CONFIG_CPU9G20)
- at91_sys_write(AT91_SMC_SETUP(3),
- AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
- AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
- at91_sys_write(AT91_SMC_PULSE(3),
- AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(4) |
- AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(4));
- at91_sys_write(AT91_SMC_CYCLE(3),
- AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
- at91_sys_write(AT91_SMC_MODE(3),
- AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
- AT91_SMC_EXNWMODE_DISABLE |
- AT91_SMC_DBW_8 |
- AT91_SMC_TDF_(3));
+ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
+ AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(3),
+ &smc->cs[3].mode);
#elif defined(CONFIG_CPU9260)
- at91_sys_write(AT91_SMC_SETUP(3),
- AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
- AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
- at91_sys_write(AT91_SMC_PULSE(3),
- AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
- AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
- at91_sys_write(AT91_SMC_CYCLE(3),
- AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
- at91_sys_write(AT91_SMC_MODE(3),
- AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
- AT91_SMC_EXNWMODE_DISABLE |
- AT91_SMC_DBW_8 |
- AT91_SMC_TDF_(2));
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
#endif
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+ writel(1 << AT91SAM9260_ID_PIOC, &pmc->pcer);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
#ifdef CONFIG_MACB
static void cpu9260_macb_hw_init(void)
{
- unsigned long rstc;
+ unsigned long rstcmr;
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+ at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE;
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
-
- /*
- * Disable pull-up on:
- * RXDV (PA17) => PHY normal mode (not Test mode)
- * ERX0 (PA14) => PHY ADDR0
- * ERX1 (PA15) => PHY ADDR1
- * ERX2 (PA25) => PHY ADDR2
- * ERX3 (PA26) => PHY ADDR3
- * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
- *
- * PHY has internal pull-down
- */
- writel(pin_to_mask(AT91_PIN_PA14) |
- pin_to_mask(AT91_PIN_PA15) |
- pin_to_mask(AT91_PIN_PA17) |
- pin_to_mask(AT91_PIN_PA25) |
- pin_to_mask(AT91_PIN_PA26) |
- pin_to_mask(AT91_PIN_PA28),
- pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
-
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+ writel(1 << AT91SAM9260_ID_EMAC, &pmc->pcer);
+
+ at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
+
+ rstcmr = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
/* Need to reset PHY -> 500ms reset */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0D << 8)) |
- AT91_RSTC_URSTEN);
+ writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0xD) |
+ AT91_RSTC_MR_URSTEN, &rstc->mr);
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+ writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
/* Wait for end hardware reset */
- while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL))
+ while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
;
/* Restore NRST value */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (rstc) |
- AT91_RSTC_URSTEN);
-
- /* Re-enable pull-up */
- writel(pin_to_mask(AT91_PIN_PA14) |
- pin_to_mask(AT91_PIN_PA15) |
- pin_to_mask(AT91_PIN_PA17) |
- pin_to_mask(AT91_PIN_PA25) |
- pin_to_mask(AT91_PIN_PA26) |
- pin_to_mask(AT91_PIN_PA28),
- pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+ writel(AT91_RSTC_KEY | rstcmr | AT91_RSTC_MR_URSTEN, &rstc->mr);
at91_macb_hw_init();
}
#endif
-int board_init(void)
+int board_early_init_f(void)
{
- /* Enable Ctrlc */
- console_init_f();
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ writel((1 << AT91SAM9260_ID_PIOA) |
+ (1 << AT91SAM9260_ID_PIOC) |
+ (1 << AT91SAM9260_ID_PIOB),
+ &pmc->pcer);
+
+ at91_serial_hw_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
/* arch number of the board */
#if defined(CONFIG_CPU9G20)
gd->bd->bi_arch_number = MACH_TYPE_CPUAT9G20;
#endif
/* adress of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- at91_serial_hw_init();
#ifdef CONFIG_CMD_NAND
cpu9260_nand_hw_init();
#endif
int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM;
- if (get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) !=
- PHYS_SDRAM_SIZE)
- return -1;
-
- gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
return 0;
}
-#ifdef CONFIG_RESET_PHY_R
-void reset_phy(void)
-{
-}
-#endif
-
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
+ rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0);
#endif
return rc;
}
void coloured_LED_init(void)
{
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+ writel(1 << AT91SAM9260_ID_PIOC, &pmc->pcer);
- at91_set_gpio_output(CONFIG_RED_LED, 1);
- at91_set_gpio_output(CONFIG_GREEN_LED, 1);
- at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
- at91_set_gpio_output(CONFIG_BLUE_LED, 1);
+ at91_set_pio_output(CONFIG_RED_LED, 1);
+ at91_set_pio_output(CONFIG_GREEN_LED, 1);
+ at91_set_pio_output(CONFIG_YELLOW_LED, 1);
+ at91_set_pio_output(CONFIG_BLUE_LED, 1);
- at91_set_gpio_value(CONFIG_RED_LED, 1);
- at91_set_gpio_value(CONFIG_GREEN_LED, 1);
- at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
- at91_set_gpio_value(CONFIG_BLUE_LED, 1);
+ at91_set_pio_value(CONFIG_RED_LED, 1);
+ at91_set_pio_value(CONFIG_GREEN_LED, 1);
+ at91_set_pio_value(CONFIG_YELLOW_LED, 1);
+ at91_set_pio_value(CONFIG_BLUE_LED, 1);
}
void red_LED_off(void)
{
- at91_set_gpio_value(CONFIG_RED_LED, 1);
+ at91_set_pio_value(CONFIG_RED_LED, 1);
saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
}
void green_LED_off(void)
{
- at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+ at91_set_pio_value(CONFIG_GREEN_LED, 1);
saved_state[STATUS_LED_GREEN] = STATUS_LED_OFF;
}
void yellow_LED_off(void)
{
- at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+ at91_set_pio_value(CONFIG_YELLOW_LED, 1);
saved_state[STATUS_LED_YELLOW] = STATUS_LED_OFF;
}
void blue_LED_off(void)
{
- at91_set_gpio_value(CONFIG_BLUE_LED, 1);
+ at91_set_pio_value(CONFIG_BLUE_LED, 1);
saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF;
}
void red_LED_on(void)
{
- at91_set_gpio_value(CONFIG_RED_LED, 0);
+ at91_set_pio_value(CONFIG_RED_LED, 0);
saved_state[STATUS_LED_RED] = STATUS_LED_ON;
}
void green_LED_on(void)
{
- at91_set_gpio_value(CONFIG_GREEN_LED, 0);
+ at91_set_pio_value(CONFIG_GREEN_LED, 0);
saved_state[STATUS_LED_GREEN] = STATUS_LED_ON;
}
void yellow_LED_on(void)
{
- at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
+ at91_set_pio_value(CONFIG_YELLOW_LED, 0);
saved_state[STATUS_LED_YELLOW] = STATUS_LED_ON;
}
void blue_LED_on(void)
{
- at91_set_gpio_value(CONFIG_BLUE_LED, 0);
+ at91_set_pio_value(CONFIG_BLUE_LED, 0);
saved_state[STATUS_LED_BLUE] = STATUS_LED_ON;
}
LIB = $(obj)lib$(BOARD).o
-COBJS := cpuat91.o
+COBJS := $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
rm -f $(SOBJS) $(OBJS)
distclean: clean
- rm -f $(LIB) core *.bak .depend
+ rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
+++ /dev/null
-CONFIG_SYS_TEXT_BASE = 0x21F00000
/* arch number of CPUAT91-Board */
gd->bd->bi_arch_number = MACH_TYPE_CPUAT91;
/* adress of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
return 0;
}
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
- int rc = 0;
- rc = at91emac_register(bis, 0);
- return rc;
+ return at91emac_register(bis, (u32) AT91_EMAC_BASE);
}
#endif
#include <netdev.h>
#include <asm/io.h>
-#include <asm/arch/ftsmc020.h>
+#include <faraday/ftsmc020.h>
DECLARE_GLOBAL_DATA_PTR;
#include <version.h>
#include <asm/macro.h>
-#include <asm/arch/ftsdmc020.h>
+#include <faraday/ftsdmc020.h>
/*
* parameters for the SDRAM controller
* MA 02111-1307 USA
*/
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
.macro REG reg, val
ldr r2, =\reg
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
-#include <asm/arch/mx31.h>
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
DECLARE_GLOBAL_DATA_PTR;
*/
#include <config.h>
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
#include <asm/macro.h>
.globl lowlevel_init
#include <common.h>
#include <netdev.h>
-#include <asm/arch/mx31.h>
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
- printf("Board: i.MX31 MAX PDK (3DS)\n");
+ printf("Board: MX31PDK\n");
return 0;
}
+++ /dev/null
-#
-# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-CONFIG_SYS_TEXT_BASE = 0x97800000
-IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
-ALL += $(obj)u-boot.imx
#include <common.h>
#include <s6e63d6.h>
#include <netdev.h>
-#include <asm/arch/mx31.h>
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
DECLARE_GLOBAL_DATA_PTR;
* MA 02111-1307 USA
*/
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
.macro REG reg, val
ldr r2, =\reg
*/
int i2c_init_board(void)
{
- int i, icr;
-
- /* disable I2C controller first, otherwhise it thinks we want to */
- /* talk to the slave port... */
- icr = readl(ICR);
- writel(readl(ICR) & ~(ICR_SCLE | ICR_IUE), ICR);
+ int i;
/* set gpio pin low _before_ we change direction to output */
writel(GPIO_bit(70), GPCR(70));
udelay(10);
}
- writel(icr, ICR);
-
return 0;
}
int board_init()
{
#ifdef CONFIG_MXC_UART
- extern void mx25_uart_init_pins(void);
+ extern void mx25_uart1_init_pins(void);
- mx25_uart_init_pins();
+ mx25_uart1_init_pins();
#endif
/* board id for linux */
gd->bd->bi_arch_number = MACH_TYPE_TX25;
#include <common.h>
#include <netdev.h>
-#include <asm/arch/mx31.h>
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
DECLARE_GLOBAL_DATA_PTR;
* MA 02111-1307 USA
*/
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
.macro REG reg, val
ldr r2, =\reg
#include <asm/arch/clk_rst.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/uart.h>
+#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
CONFIG_TEGRA2_BOARD_STRING
};
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ /* Initialize periph clocks */
+ clock_init();
+
+ /* Initialize periph pinmuxes */
+ pinmux_init();
+
+ /* Initialize periph GPIOs */
+ gpio_init();
+
+ /* Init UART, scratch regs, and start CPU */
+ tegra2_start();
+ return 0;
+}
+#endif /* EARLY_INIT */
+
/*
* Routine: timer_init
* Description: init the timestamp and lastinc value
static void clock_init_uart(void)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- static int pllp_init_done;
u32 reg;
- if (!pllp_init_done) {
+ reg = readl(&clkrst->crc_pllp_base);
+ if (!(reg & PLL_BASE_OVRRIDE)) {
/* Override pllp setup for 216MHz operation. */
reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP);
reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM);
reg &= ~PLL_BYPASS;
writel(reg, &clkrst->crc_pllp_base);
-
- pllp_init_done++;
}
/* Now do the UART reset/clock enable */
}
/*
+ * Routine: gpio_init
+ * Description: Do individual peripheral GPIO configs
+ */
+void gpio_init(void)
+{
+ gpio_config_uart();
+}
+
+/*
* Routine: board_init
* Description: Early hardware init.
*/
/* board id for Linux */
gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
- /* Initialize peripheral clocks */
- clock_init();
-
- /* Initialize periph pinmuxes */
- pinmux_init();
-
return 0;
}
--- /dev/null
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void tegra2_start(void);
+void clock_init(void);
+void pinmux_init(void);
+void gpio_init(void);
+void gpio_config_uart(void);
+
+#endif /* BOARD_H */
LIB = $(obj)lib$(BOARD).o
+COBJS := $(BOARD).o
COBJS += ../common/board.o
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra2.h>
+
+/*
+ * Routine: gpio_config_uart
+ * Description: Does nothing on Harmony - no conflict w/SPI.
+ */
+void gpio_config_uart(void)
+{
+}
LIB = $(obj)lib$(BOARD).o
+COBJS := $(BOARD).o
COBJS += ../common/board.o
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/gpio.h>
+
+/*
+ * Routine: gpio_config_uart
+ * Description: Force GPIO_PI3 low on Seaboard so UART4 works.
+ */
+void gpio_config_uart(void)
+{
+ int gp = GPIO_PI3;
+ struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+ struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)];
+ u32 val;
+
+ /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
+ val = readl(&bank->gpio_config[GPIO_PORT(gp)]);
+ val |= 1 << GPIO_BIT(gp);
+ writel(val, &bank->gpio_config[GPIO_PORT(gp)]);
+
+ val = readl(&bank->gpio_out[GPIO_PORT(gp)]);
+ val &= ~(1 << GPIO_BIT(gp));
+ writel(val, &bank->gpio_out[GPIO_PORT(gp)]);
+
+ val = readl(&bank->gpio_dir_out[GPIO_PORT(gp)]);
+ val |= 1 << GPIO_BIT(gp);
+ writel(val, &bank->gpio_dir_out[GPIO_PORT(gp)]);
+}
LIB = $(obj)lib$(BOARD).o
COBJS := nhk8815.o
-SOBJS := platform.o
+SOBJS :=
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
+++ /dev/null
-# (C) Copyright 2007
-# STMicroelectronics, <www.st.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-#
-# image should be loaded at 0x01000000
-#
-
-CONFIG_SYS_TEXT_BASE = 0x03F80000
int dram_init(void)
{
- /* set dram bank start addr and size */
+ gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- return 0;
}
#ifdef CONFIG_CMD_NET
+++ /dev/null
-/*
- * Board specific setup info
- *
- * (C) Copyright 2005
- * STMicrolelctronics, <www.st.com>
- *
- * (C) Copyright 2004, ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-.globl lowlevel_init
-lowlevel_init:
- /* Jump to the flash address */
- ldr r0, =CFG_ONENAND_BASE
-
- /*
- * Make it independent whether we boot from 0x0 or 0x30000000.
- * Non-portable: it relies on the knowledge that ip has to be updated
- */
- orr ip, ip, r0 /* adjust return address of cpu_init_crit */
- orr lr, lr, r0 /* adjust return address */
- orr pc, pc, r0 /* jump to the normal address */
- nop
-
- /* Initialize PLL, Remap clear, FSMC, MPMC here! */
- /* What about GPIO, CLCD and UART */
-
- /* PLL Initialization */
- /* Prog the PLL1 @ 266 MHz ==> SDRAM Clock = 100.8 MHz */
- ldr r0, =NOMADIK_SRC_BASE
-
- ldr r1, =0x2B013502
-
- str r1, [r0, #0x14]
-
- /* Used to set all the timers clock to 2.4MHZ */
- ldr r1, =0x2AAAA004
- str r1, [r0]
-
- ldr r1, =0x10000000
- str r1, [r0, #0x10]
-
- /* FSMC setup ---- */
- ldr r0, =NOMADIK_FSMC_BASE
-
- ldr r1, =0x10DB /* For 16-bit NOR flash */
- str r1, [r0, #0x08]
-
- ldr r1, =0x03333333 /* For 16-bit NOR flash */
- str r1, [r0, #0xc]
-
- /* oneNAND setting */
- ldr r1, =0x0000105B /* BCR0 Prog control register */
- str r1, [r0]
-
- ldr r1, =0x0A200551 /* BTR0 Prog timing register */
- str r1, [r0, #0x04]
-
- /* preload the instructions into icache */
- add r0, pc, #0x1F
- bic r0, r0, #0x1F
- mcr p15, 0, r0, c7, c13, 1
- add r0, r0, #0x20
- mcr p15, 0, r0, c7, c13, 1
-
- /* Now Clear Remap */
- ldr r0, =NOMADIK_SRC_BASE
-
- ldr r1, =0x2004
- str r1, [r0]
-
- ldr r1, =0x10000000
- str r1, [r0, #0x10]
-
- ldr r0, =0x101E9000
- ldr r1, =0x2004
- str r1, [r0]
-
- ldr r0, =NOMADIK_SRC_BASE
- ldr r1, =0x2104
- str r1, [r0]
-
- /* FSMC setup -- */
- mov r0, #(NOMADIK_FSMC_BASE & 0x10000000)
- orr r0, r0, #(NOMADIK_FSMC_BASE & 0x0FFFFFFF)
-
- ldr r1, =0x10DB /* For 16-bit NOR flash */
- str r1, [r0, #0x8]
-
- ldr r1, =0x03333333 /* For 16-bit NOR flash */
- str r1, [r0, #0xc]
-
- /* MPMC Setup */
- ldr r0, =NOMADIK_MPMC_BASE
-
- ldr r1, =0xF00003
- str r1, [r0] /* Enable the MPMC and the DLL */
-
- ldr r1, =0x183
- str r1, [r0, #0x20]
-
- ldr r2, =NOMADIK_PMU_BASE
-
- ldr r1, =0x1111
- str r1, [r2]
-
- ldr r1, =0x1111 /* Prog the, mand delay strategy */
- str r1, [r0, #0x28]
-
- ldr r1, =0x103 /* NOP ,mand */
- str r1, [r0, #0x20]
-
- /* FIXME -- Wait required here */
-
- ldr r1, =0x103 /* PALL ,mand*/
- str r1, [r0, #0x20]
-
- ldr r1, =0x1
- str r1, [r0, #0x24] /* To do at least two auto-refresh */
-
- /* FIXME -- Wait required here */
-
- /* Auto-refresh period = 7.8us @ SDRAM Clock = 100.8 MHz */
- ldr r1, =0x31
- str r1, [r0, #0x24]
-
- /* Prog Little Endian, Not defined in 8800 board */
- ldr r1, =0x0
- str r1, [r0, #0x8]
-
-
- ldr r1, =0x2
- str r1, [r0, #0x30] /* Prog tRP timing */
-
- ldr r1, =0x4 /* Change for 8815 */
- str r1, [r0, #0x34] /* Prog tRAS timing */
-
- ldr r1, =0xB
- str r1, [r0, #0x38] /* Prog tSREX timing */
-
-
- ldr r1, =0x1
- str r1, [r0, #0x44] /* Prog tWR timing */
-
- ldr r1, =0x8
- str r1, [r0, #0x48] /* Prog tRC timing */
-
- ldr r1, =0xA
- str r1, [r0, #0x4C] /* Prog tRFC timing */
-
- ldr r1, =0xB
- str r1, [r0, #0x50] /* Prog tXSR timing */
-
- ldr r1, =0x1
- str r1, [r0, #0x54] /* Prog tRRD timing */
-
- ldr r1, =0x1
- str r1, [r0, #0x58] /* Prog tMRD timing */
-
- ldr r1, =0x1
- str r1, [r0, #0x5C] /* Prog tCDLR timing */
-
- /* DDR-SDRAM MEMORY IS ON BANK0 8815 */
- ldr r1, =0x304 /* Prog RAS and CAS for CS 0 */
- str r1, [r0, #0x104]
-
- /* SDR-SDRAM MEMORY IS ON BANK1 8815 */
- ldr r1, =0x304 /* Prog RAS and CAS for CS 1 */
- str r1, [r0, #0x124]
- /* THE DATA BUS WIDE IS PROGRAM FOR 16-BITS */
- /* DDR-SDRAM MEMORY IS ON BANK0*/
-
- ldr r1, =0x884 /* 8815 : config reg in BRC for CS0 */
- str r1, [r0, #0x100]
-
- /*SDR-SDRAM MEMORY IS ON BANK1*/
-
- ldr r1, =0x884 /* 8815 : config reg in BRC for CS1 */
- str r1, [r0, #0x120]
-
- ldr r1, =0x83 /*MODE Mand*/
- str r1, [r0, #0x20]
-
- /* LOAD MODE REGISTER FOR 2 bursts of 16b, with DDR mem ON BANK0 */
-
- ldr r1, =0x62000 /*Data in*/
- ldr r1, [r1]
-
- /* LOAD MODE REGISTER FOR 2 bursts of 16b, with DDR mem ON BANK1 */
-
- ldr r1, =0x8062000
- ldr r1, [r1]
-
- ldr r1, =0x003
- str r1, [r0, #0x20]
-
- /* ENABLE ALL THE BUFFER FOR EACH AHB PORT*/
-
- ldr r1, =0x01 /* Enable buffer 0 */
- str r1, [r0, #0x400]
-
- ldr r1, =0x01 /* Enable buffer 1 */
- str r1, [r0, #0x420]
-
- ldr r1, =0x01 /* Enable buffer 2 */
- str r1, [r0, #0x440]
-
- ldr r1, =0x01 /* Enable buffer 3 */
- str r1, [r0, #0x460]
-
- ldr r1, =0x01 /* Enable buffer 4 */
- str r1, [r0, #0x480]
-
- ldr r1, =0x01 /* Enable buffer 5 */
- str r1, [r0, #0x4A0]
-
- /* GPIO settings */
-
- ldr r0, =NOMADIK_GPIO1_BASE
-
- ldr r1, =0xC0600000
- str r1, [r0, #0x20]
-
- ldr r1, =0x3F9FFFFF /* ABHI change this for uart1 */
- str r1, [r0, #0x24]
-
- ldr r1, =0x3F9FFFFF /* ABHI change this for uart1 */
- str r1, [r0, #0x28]
-
- ldr r0, =NOMADIK_GPIO0_BASE
-
- ldr r1, =0xFFFFFFFF
- str r1, [r0, #0x20]
-
- ldr r1, =0x00
- str r1, [r0, #0x24]
-
- ldr r1, =0x00
- str r1, [r0, #0x28]
-
- /* Configure CPLD_CTRL register for enabling MUX logic for UART0/UART2 */
-
- ldr r0, =NOMADIK_FSMC_BASE
-
- ldr r1, =0x10DB /* INIT FSMC bank 0 */
- str r1, [r0, #0x00]
-
- ldr r1, =0x0FFFFFFF
- str r1, [r0, #0x04]
-
- ldr r1, =0x010DB /* INIT FSMC bank 1 */
- str r1, [r0, #0x08]
-
- ldr r1, =0x00FFFFFFF
- str r1, [r0, #0x0C]
-
- ldr r0, =NOMADIK_UART0_BASE
-
- ldr r1, =0x00000000
- str r1, [r0, #0x30]
-
- ldr r1, =0x0000004e
- str r1, [r0, #0x24]
-
- ldr r1, =0x00000008
- str r1, [r0, #0x28]
-
- ldr r1, =0x00000060
- str r1, [r0, #0x2C]
-
- ldr r1, =0x00000301
- str r1, [r0, #0x30]
-
- ldr r1, =0x00000066
- str r1, [r0]
-
- ldr r0, =NOMADIK_UART1_BASE
-
- ldr r1, =0x00000000
- str r1, [r0, #0x30]
-
- ldr r1, =0x0000004e
- str r1, [r0, #0x24]
-
- ldr r1, =0x00000008
- str r1, [r0, #0x28]
-
- ldr r1, =0x00000060
- str r1, [r0, #0x2C]
-
- ldr r1, =0x00000301
- str r1, [r0, #0x30]
-
- ldr r1, =0x00000066
- str r1, [r0]
-
- ldr r0, =NOMADIK_UART2_BASE
-
- ldr r1, =0x00000000
- str r1, [r0, #0x30]
-
- ldr r1, =0x0000004e
- str r1, [r0, #0x24]
-
- ldr r1, =0x00000008
- str r1, [r0, #0x28]
-
- ldr r1, =0x00000060
- str r1, [r0, #0x2C]
-
- ldr r1, =0x00000301
- str r1, [r0, #0x30]
-
- ldr r1, =0x00000066
- str r1, [r0]
-
- /* Configure CPLD to enable UART0 */
-
- mov pc, lr
--- /dev/null
+#
+# Author: Srinath R <srinath@mistralsolutions.com>
+#
+# Based on logicpd/am3517evm/Makefile
+#
+# Copyright (C) 2011 Mistral Solutions Pvt Ltd
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := am3517crane.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
--- /dev/null
+/*
+ * am3517crane.c - board file for AM3517 CraneBoard
+ *
+ * Author: Srinath.R <srinath@mistralsolutions.com>
+ *
+ * Based on logicpd/am3517evm/am3517evm.c
+ *
+ * Copyright (C) 2011 Mistral Solutions Pvt Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include <i2c.h>
+#include "am3517crane.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_CRANEBOARD;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Init i2c, ethernet, etc... (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_AM3517CRANE();
+}
--- /dev/null
+/*
+ * am3517crane.h - Header file for the AM3517 CraneBoard.
+ *
+ * Author: Srinath R <srinath@mistralsolutions.com>
+ *
+ * Based on logicpd/am3517evm/am3517evm.h
+ *
+ * Copyright (C) 2011 Mistral Solutions Pvt Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _AM3517CRANE_H_
+#define _AM3517CRANE_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "CraneBoard",
+ "NAND",
+};
+/* AM3517 specific mux configuration */
+#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08
+/* CCDC */
+#define CONTROL_PADCONF_CCDC_PCLK 0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD 0x01E6
+#define CONTROL_PADCONF_CCDC_HD 0x01E8
+#define CONTROL_PADCONF_CCDC_VD 0x01EA
+#define CONTROL_PADCONF_CCDC_WEN 0x01EC
+#define CONTROL_PADCONF_CCDC_DATA0 0x01EE
+#define CONTROL_PADCONF_CCDC_DATA1 0x01F0
+#define CONTROL_PADCONF_CCDC_DATA2 0x01F2
+#define CONTROL_PADCONF_CCDC_DATA3 0x01F4
+#define CONTROL_PADCONF_CCDC_DATA4 0x01F6
+#define CONTROL_PADCONF_CCDC_DATA5 0x01F8
+#define CONTROL_PADCONF_CCDC_DATA6 0x01FA
+#define CONTROL_PADCONF_CCDC_DATA7 0x01FC
+/* RMII */
+#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE
+#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200
+#define CONTROL_PADCONF_RMII_RXD0 0x0202
+#define CONTROL_PADCONF_RMII_RXD1 0x0204
+#define CONTROL_PADCONF_RMII_CRS_DV 0x0206
+#define CONTROL_PADCONF_RMII_RXER 0x0208
+#define CONTROL_PADCONF_RMII_TXD0 0x020A
+#define CONTROL_PADCONF_RMII_TXD1 0x020C
+#define CONTROL_PADCONF_RMII_TXEN 0x020E
+#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210
+#define CONTROL_PADCONF_USB0_DRVBUS 0x0212
+/* CAN */
+#define CONTROL_PADCONF_HECC1_TXD 0x0214
+#define CONTROL_PADCONF_HECC1_RXD 0x0216
+#define CONTROL_PADCONF_SYS_BOOT7 0x0218
+#define CONTROL_PADCONF_SDRC_DQS0N 0x021A
+#define CONTROL_PADCONF_SDRC_DQS1N 0x021C
+#define CONTROL_PADCONF_SDRC_DQS2N 0x021E
+#define CONTROL_PADCONF_SDRC_DQS3N 0x0220
+#define CONTROL_PADCONF_STRBEN_DLY0 0x0222
+#define CONTROL_PADCONF_STRBEN_DLY1 0x0224
+#define CONTROL_PADCONF_SYS_BOOT8 0x0226
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_AM3517CRANE()\
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_CKE0), (M0))\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(SDRC_CKE0), (M0))\
+ MUX_VAL(CP(SDRC_CKE1), (M0))\
+ /*sdrc_strben_dly0*/\
+ MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0))\
+ /*sdrc_strben_dly1*/\
+ MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0))\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (M7))\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | DIS | M4))\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_A6), (M7))\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_A9), (M7))\
+ MUX_VAL(CP(GPMC_A10), (M7))\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_NCS2), (M7))\
+ MUX_VAL(CP(GPMC_NCS3), (M7))\
+ MUX_VAL(CP(GPMC_NCS4), (M7))\
+ MUX_VAL(CP(GPMC_NCS5), (M7))\
+ MUX_VAL(CP(GPMC_NCS6), (M7))\
+ MUX_VAL(CP(GPMC_NCS7), (M7))\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0))/*TP*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_NBE1), (M7))\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_WAIT1), (M7))\
+ MUX_VAL(CP(GPMC_WAIT2), (M7))\
+ MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4))/*GPIO_65*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0))\
+ /*MMC1*/\
+ MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M0))\
+ /*MMC2*/\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | DIS | M0))\
+ /*McBSP*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0))\
+ \
+ MUX_VAL(CP(MCBSP2_FSX), (M7))\
+ MUX_VAL(CP(MCBSP2_CLKX), (M7))\
+ MUX_VAL(CP(MCBSP2_DR), (M7))\
+ MUX_VAL(CP(MCBSP2_DX), (M7))\
+ \
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0))\
+ \
+ MUX_VAL(CP(MCBSP4_CLKX), (M7))\
+ MUX_VAL(CP(MCBSP4_DR), (M7))\
+ MUX_VAL(CP(MCBSP4_DX), (M7))\
+ MUX_VAL(CP(MCBSP4_FSX), (M7))\
+ /*UART*/\
+ MUX_VAL(CP(UART1_TX), (M7))\
+ MUX_VAL(CP(UART1_RTS), (M7))\
+ MUX_VAL(CP(UART1_CTS), (M7))\
+ MUX_VAL(CP(UART1_RX), (M7))\
+ \
+ MUX_VAL(CP(UART2_CTS), (M7))\
+ MUX_VAL(CP(UART2_RTS), (M7))\
+ MUX_VAL(CP(UART2_TX), (M7))\
+ MUX_VAL(CP(UART2_RX), (M7))\
+ \
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0))\
+ /*I2C 1, 2, 3*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\
+ /*McSPI*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4))/*GPIO_171 TP*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4))/*GPIO_172 TP*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4))/*GPIO_173 TP*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTU | EN | M4))/*GPIO_174 TP*/\
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4))/*GPIO_175 TP*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4))/*GPIO_176 TP*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4))/*GPIO_176 TP*/\
+ \
+ MUX_VAL(CP(MCSPI2_CLK), (M7))\
+ MUX_VAL(CP(MCSPI2_SIMO), (M7))\
+ MUX_VAL(CP(MCSPI2_SOMI), (M7))\
+ MUX_VAL(CP(MCSPI2_CS0), (M7))\
+ MUX_VAL(CP(MCSPI2_CS1), (M7))\
+ /*CCDC*/\
+ MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1))/*CCDC_DATA8*/\
+ MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1))/*CCDC_DATA9 */\
+ MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0))\
+ /*RMII*/\
+ MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0))\
+ MUX_VAL(CP(RMII_MDIO_CLK), (M0))\
+ MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0))\
+ MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0))\
+ MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0))\
+ MUX_VAL(CP(RMII_RXER), (PTD | M0))\
+ MUX_VAL(CP(RMII_TXD0), (PTD | M0))\
+ MUX_VAL(CP(RMII_TXD1), (PTD | M0))\
+ MUX_VAL(CP(RMII_TXEN), (PTD | M0))\
+ MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0))\
+ /*HECC*/\
+ MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0))\
+ /*HSUSB*/\
+ MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0))\
+ /*HDQ*/\
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4))\
+ /*Control and debug*/\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M4))/*GPIO_1 TPS_SLEEP*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0))\
+ /*SYS_nRESWARM*/\
+ MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | EN | M0))/*GPIO_30 ToExp*/\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))/*GPIO_10 TP*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0))\
+ /*JTAG*/\
+ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0))\
+ /*ETK (ES2 onwards)*/\
+ MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M3))\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3))\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D10_ES2), (M7))\
+ MUX_VAL(CP(ETK_D11_ES2), (M7))\
+ MUX_VAL(CP(ETK_D12_ES2), (M7))\
+ MUX_VAL(CP(ETK_D13_ES2), (M7))\
+ MUX_VAL(CP(ETK_D14_ES2), (M7))\
+ MUX_VAL(CP(ETK_D15_ES2), (M7))\
+ /*Die to Die*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0))\
+
+#endif /* _AM3517CRANE_H_ */
--- /dev/null
+#
+# Author: Srinath R <srinath@mistralsolutions.com>
+#
+# Based on logicpd/am3517evm/config.mk
+#
+# Copyright (C) 2011 Mistral Solutions Pvt Ltd
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
LIB = $(obj)lib$(BOARD).o
-COBJS := beagle.o
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_STATUS_LED) += led.o
+COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
* MA 02111-1307 USA
*/
#include <common.h>
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+#endif
#include <twl4030.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/gpio.h>
#include <asm/mach-types.h>
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/clocks_omap3.h>
+#include <asm/arch/ehci_omap3.h>
+/* from drivers/usb/host/ehci-core.h */
+extern struct ehci_hccr *hccr;
+extern volatile struct ehci_hcor *hcor;
+#endif
#include "beagle.h"
+#define pr_debug(fmt, args...) debug(fmt, ##args)
+
#define TWL4030_I2C_BUS 0
#define EXPANSION_EEPROM_I2C_BUS 1
#define EXPANSION_EEPROM_I2C_ADDRESS 0x50
#define TINCANTOOLS_TRAINER 0x04000100
#define TINCANTOOLS_SHOWDOG 0x03000100
#define KBADC_BEAGLEFPGA 0x01000600
-
+#define LW_BEAGLETOUCH 0x01000700
+#define BRAINMUX_LCDOG 0x01000800
+#define BRAINMUX_LCDOGTOUCH 0x02000800
+#define BBTOYS_WIFI 0x01000B00
+#define BBTOYS_VGA 0x02000B00
+#define BBTOYS_LCD 0x03000B00
#define BEAGLE_NO_EEPROM 0xffffffff
DECLARE_GLOBAL_DATA_PTR;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+ status_led_set (STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+
return 0;
}
{
struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
+ struct control_prog_io *prog_io_base = (struct gpio *)OMAP34XX_CTRL_BASE;
+
+ /* Enable i2c2 pullup resisters */
+ writel(~(PRG_I2C2_PULLUPRESX), &prog_io_base->io1);
switch (get_board_revision()) {
case REVISION_AXBX:
printf("Beagle Rev Ax/Bx\n");
setenv("beaglerev", "AxBx");
- setenv("mpurate", "600");
break;
case REVISION_CX:
printf("Beagle Rev C1/C2/C3\n");
setenv("beaglerev", "Cx");
- setenv("mpurate", "600");
MUX_BEAGLE_C();
break;
case REVISION_C4:
printf("Beagle Rev C4\n");
setenv("beaglerev", "C4");
- setenv("mpurate", "720");
MUX_BEAGLE_C();
/* Set VAUX2 to 1.8V for EHCI PHY */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
break;
- case REVISION_XM:
+ case REVISION_XM_A:
printf("Beagle xM Rev A\n");
setenv("beaglerev", "xMA");
- setenv("mpurate", "1000");
+ MUX_BEAGLE_XM();
+ /* Set VAUX2 to 1.8V for EHCI PHY */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+ TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
+ TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ break;
+ case REVISION_XM_B:
+ printf("Beagle xM Rev B\n");
+ setenv("beaglerev", "xMB");
MUX_BEAGLE_XM();
/* Set VAUX2 to 1.8V for EHCI PHY */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
break;
default:
printf("Beagle unknown 0x%02x\n", get_board_revision());
+ MUX_BEAGLE_XM();
+ /* Set VAUX2 to 1.8V for EHCI PHY */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+ TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
+ TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
}
switch (get_expansion_id()) {
MUX_KBADC_BEAGLEFPGA();
setenv("buddy", "beaglefpga");
break;
+ case LW_BEAGLETOUCH:
+ printf("Recognized Liquidware BeagleTouch board\n");
+ setenv("buddy", "beagletouch");
+ break;
+ case BRAINMUX_LCDOG:
+ printf("Recognized Brainmux LCDog board\n");
+ setenv("buddy", "lcdog");
+ break;
+ case BRAINMUX_LCDOGTOUCH:
+ printf("Recognized Brainmux LCDog Touch board\n");
+ setenv("buddy", "lcdogtouch");
+ break;
+ case BBTOYS_WIFI:
+ printf("Recognized BeagleBoardToys WiFi board\n");
+ MUX_BBTOYS_WIFI()
+ setenv("buddy", "bbtoys-wifi");
+ break;;
+ case BBTOYS_VGA:
+ printf("Recognized BeagleBoardToys VGA board\n");
+ break;;
+ case BBTOYS_LCD:
+ printf("Recognized BeagleBoardToys LCD board\n");
+ break;;
case BEAGLE_NO_EEPROM:
printf("No EEPROM on expansion board\n");
setenv("buddy", "none");
return 0;
}
#endif
+
+#ifdef CONFIG_USB_EHCI
+
+#define GPIO_PHY_RESET 147
+
+/* Reset is needed otherwise the kernel-driver will throw an error. */
+int ehci_hcd_stop(void)
+{
+ pr_debug("Resetting OMAP3 EHCI\n");
+ omap_set_gpio_dataout(GPIO_PHY_RESET, 0);
+ writel(OMAP_UHH_SYSCONFIG_SOFTRESET, OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);
+ return 0;
+}
+
+/* Call usb_stop() before starting the kernel */
+void show_boot_progress(int val)
+{
+ if(val == 15)
+ usb_stop();
+}
+
+/*
+ * Initialize the OMAP3 EHCI controller and PHY on the BeagleBoard.
+ * Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37.
+ * See there for additional Copyrights.
+ */
+int ehci_hcd_init(void)
+{
+ pr_debug("Initializing OMAP3 ECHI\n");
+
+ /* Put the PHY in RESET */
+ omap_request_gpio(GPIO_PHY_RESET);
+ omap_set_gpio_direction(GPIO_PHY_RESET, 0);
+ omap_set_gpio_dataout(GPIO_PHY_RESET, 0);
+
+ /* Hold the PHY in RESET for enough time till DIR is high */
+ /* Refer: ISSUE1 */
+ udelay(10);
+
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
+ sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
+ /*
+ * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
+ * and USBHOST_120M_FCLK (USBHOST_FCLK2)
+ */
+ sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
+ /* Enable USBTTL_ICLK */
+ sr32(&prcm_base->iclken3_core, 2, 1, 1);
+ /* Enable USBTTL_FCLK */
+ sr32(&prcm_base->fclken3_core, 2, 1, 1);
+ pr_debug("USB clocks enabled\n");
+
+ /* perform TLL soft reset, and wait until reset is complete */
+ writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET,
+ OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
+ /* Wait for TLL reset to complete */
+ while (!(readl(OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS)
+ & OMAP_USBTLL_SYSSTATUS_RESETDONE));
+ pr_debug("TLL reset done\n");
+
+ writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
+ OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
+ OMAP_USBTLL_SYSCONFIG_CACTIVITY,
+ OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
+
+ /* Put UHH in NoIdle/NoStandby mode */
+ writel(OMAP_UHH_SYSCONFIG_ENAWAKEUP
+ | OMAP_UHH_SYSCONFIG_SIDLEMODE
+ | OMAP_UHH_SYSCONFIG_CACTIVITY
+ | OMAP_UHH_SYSCONFIG_MIDLEMODE,
+ OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);
+
+ /* setup burst configurations */
+ writel(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
+ | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
+ | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN,
+ OMAP3_UHH_BASE + OMAP_UHH_HOSTCONFIG);
+
+ /*
+ * Refer ISSUE1:
+ * Hold the PHY in RESET for enough time till
+ * PHY is settled and ready
+ */
+ udelay(10);
+ omap_set_gpio_dataout(GPIO_PHY_RESET, 1);
+
+ hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE);
+ hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE + 0x10);
+
+ pr_debug("OMAP3 EHCI init done\n");
+ return 0;
+}
+
+#endif /* CONFIG_USB_EHCI */
#define REVISION_AXBX 0x7
#define REVISION_CX 0x6
#define REVISION_C4 0x5
-#define REVISION_XM 0x0
+#define REVISION_XM_A 0x0
+#define REVISION_XM_B 0x1
/*
* IEN - Input Enable
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
/* USB EHCI (port 2) */\
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA2*/\
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA7*/\
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA4*/\
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA5*/\
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA6*/\
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA3*/\
- MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/\
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_NXT*/\
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA0*/\
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA1*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)) /*HSUSB2_DATA2*/\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)) /*HSUSB2_DATA7*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)) /*HSUSB2_DATA4*/\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)) /*HSUSB2_DATA5*/\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)) /*HSUSB2_DATA6*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)) /*HSUSB2_DATA3*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DIR*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_NXT*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DATA0*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DATA1*/\
/*Control and debug */\
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
+ MUX_VAL(CP(UART2_RX), (IDIS | PTU | EN | M4)) /*GPIO_147*/
#define MUX_BEAGLE_XM() \
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | EN | M4)) /*GPIO_56*/\
MUX_VAL(CP(MCBSP1_DR), (IEN | PTU | EN | M1)) /*MCSPI4_SOMI*/\
MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTU | DIS | M1)) /*MCSPI4_CS0*/
+#define MUX_BBTOYS_WIFI() \
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) /*GPIO_136 FM_EN/BT_WU*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137 WLAN_IRQ*/\
+ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) /*GPIO_138 BT_EN*/\
+ MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) /*GPIO_139 WLAN_EN*/
+
#endif
--- /dev/null
+/*
+ * Copyright (c) 2010 Texas Instruments, Inc.
+ * Jason Kridner <jkridner@beagleboard.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <status_led.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+
+static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};
+
+/* GPIO pins for the LEDs */
+#define BEAGLE_LED_USR0 149
+#define BEAGLE_LED_USR1 150
+
+#ifdef STATUS_LED_GREEN
+void green_LED_off (void)
+{
+ __led_set (STATUS_LED_GREEN, 0);
+}
+
+void green_LED_on (void)
+{
+ __led_set (STATUS_LED_GREEN, 1);
+}
+#endif
+
+void __led_init (led_id_t mask, int state)
+{
+ __led_set (mask, state);
+}
+
+void __led_toggle (led_id_t mask)
+{
+#ifdef STATUS_LED_BIT
+ if (STATUS_LED_BIT & mask) {
+ if (STATUS_LED_ON == saved_state[0])
+ __led_set(STATUS_LED_BIT, 0);
+ else
+ __led_set(STATUS_LED_BIT, 1);
+ }
+#endif
+#ifdef STATUS_LED_BIT1
+ if (STATUS_LED_BIT1 & mask) {
+ if (STATUS_LED_ON == saved_state[1])
+ __led_set(STATUS_LED_BIT1, 0);
+ else
+ __led_set(STATUS_LED_BIT1, 1);
+ }
+#endif
+}
+
+void __led_set (led_id_t mask, int state)
+{
+#ifdef STATUS_LED_BIT
+ if (STATUS_LED_BIT & mask) {
+ if (!omap_request_gpio(BEAGLE_LED_USR0)) {
+ omap_set_gpio_direction(BEAGLE_LED_USR0, 0);
+ omap_set_gpio_dataout(BEAGLE_LED_USR0, state);
+ }
+ saved_state[0] = state;
+ }
+#endif
+#ifdef STATUS_LED_BIT1
+ if (STATUS_LED_BIT1 & mask) {
+ if (!omap_request_gpio(BEAGLE_LED_USR1)) {
+ omap_set_gpio_direction(BEAGLE_LED_USR1, 0);
+ omap_set_gpio_dataout(BEAGLE_LED_USR1, state);
+ }
+ saved_state[1] = state;
+ }
+#endif
+}
+
at91rm9200ek arm arm920t at91rm9200ek atmel at91 at91rm9200ek
at91rm9200ek_ram arm arm920t at91rm9200ek atmel at91 at91rm9200ek:RAMBOOT
eb_cpux9k2 arm arm920t - BuS at91
+cpuat91 arm arm920t cpuat91 eukrea at91 cpuat91
+cpuat91_ram arm arm920t cpuat91 eukrea at91 cpuat91:RAMBOOT
cmc_pu2 arm arm920t - - at91rm9200
csb637 arm arm920t - - at91rm9200
kb9202 arm arm920t - - at91rm9200
aspenite arm arm926ejs - Marvell armada100
afeb9260 arm arm926ejs - - at91
at91cap9adk arm arm926ejs - atmel at91
+cpu9260 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260
+cpu9260_nand arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,NANDBOOT
+cpu9260_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,CPU9260_128M
+cpu9260_nand_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,CPU9260_128M,NANDBOOT
+cpu9G20 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20
+cpu9G20_nand arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20,NANDBOOT
+cpu9G20_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20,CPU9G20_128M
+cpu9G20_nand_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20,CPU9G20_128M,NANDBOOT
top9000eval_xe arm arm926ejs top9000 emk at91 top9000:EVAL9000
top9000su_xe arm arm926ejs top9000 emk at91 top9000:SU9000
meesc arm arm926ejs - esd at91
jadecpu arm arm926ejs jadecpu syteco mb86r0x
imx27lite arm arm926ejs imx27lite logicpd mx27
magnesium arm arm926ejs imx27lite logicpd mx27
+nhk8815 arm arm926ejs nhk8815 st nomadik
+nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND
omap5912osk arm arm926ejs - ti omap
edminiv2 arm arm926ejs - LaCie orion5x
dkb arm arm926ejs - Marvell pantheon
ca9x4_ct_vxp arm armv7 vexpress armltd
efikamx arm armv7 efikamx - mx5
-mx51evk arm armv7 mx51evk freescale mx5
-mx53evk arm armv7 mx53evk freescale mx5
+mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
+mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg
vision2 arm armv7 vision2 ttcontrol mx5
cm_t35 arm armv7 cm_t35 - omap3
omap3_overo arm armv7 overo - omap3
omap3_pandora arm armv7 pandora - omap3
igep0020 arm armv7 igep0020 isee omap3
igep0030 arm armv7 igep0030 isee omap3
+am3517_crane arm armv7 am3517crane ti omap3
am3517_evm arm armv7 am3517evm logicpd omap3
+dig297 arm armv7 dig297 comelit omap3
omap3_zoom1 arm armv7 zoom1 logicpd omap3
omap3_zoom2 arm armv7 zoom2 logicpd omap3
omap3_beagle arm armv7 beagle ti omap3
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Jason Kridner <jkridner@beagleboard.org>
+ *
+ * Based on cmd_led.c patch from:
+ * http://www.mail-archive.com/u-boot@lists.denx.de/msg06873.html
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf.samuelsson@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <status_led.h>
+
+struct led_tbl_s {
+ char *string; /* String for use in the command */
+ led_id_t mask; /* Mask used for calling __led_set() */
+ void (*on)(void); /* Optional fucntion for turning LED on */
+ void (*off)(void); /* Optional fucntion for turning LED on */
+};
+
+typedef struct led_tbl_s led_tbl_t;
+
+static const led_tbl_t led_commands[] = {
+#ifdef CONFIG_BOARD_SPECIFIC_LED
+#ifdef STATUS_LED_BIT
+ { "0", STATUS_LED_BIT, NULL, NULL },
+#endif
+#ifdef STATUS_LED_BIT1
+ { "1", STATUS_LED_BIT1, NULL, NULL },
+#endif
+#ifdef STATUS_LED_BIT2
+ { "2", STATUS_LED_BIT2, NULL, NULL },
+#endif
+#ifdef STATUS_LED_BIT3
+ { "3", STATUS_LED_BIT3, NULL, NULL },
+#endif
+#endif
+#ifdef STATUS_LED_GREEN
+ { "green", STATUS_LED_GREEN, green_LED_off, green_LED_on },
+#endif
+#ifdef STATUS_LED_YELLOW
+ { "yellow", STATUS_LED_YELLOW, yellow_LED_off, yellow_LED_on },
+#endif
+#ifdef STATUS_LED_RED
+ { "red", STATUS_LED_RED, red_LED_off, red_LED_on },
+#endif
+#ifdef STATUS_LED_BLUE
+ { "blue", STATUS_LED_BLUE, blue_LED_off, blue_LED_on },
+#endif
+ { NULL, 0, NULL, NULL }
+};
+
+int str_onoff (char *var)
+{
+ if (strcmp(var, "off") == 0) {
+ return 0;
+ }
+ if (strcmp(var, "on") == 0) {
+ return 1;
+ }
+ return -1;
+}
+
+int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int state, i;
+
+ /* Validate arguments */
+ if ((argc != 3)) {
+ return cmd_usage(cmdtp);
+ }
+
+ state = str_onoff(argv[2]);
+ if (state < 0) {
+ return cmd_usage(cmdtp);
+ }
+
+ for (i = 0; led_commands[i].string; i++) {
+ if ((strcmp("all", argv[1]) == 0) ||
+ (strcmp(led_commands[i].string, argv[1]) == 0)) {
+ if (led_commands[i].on) {
+ if (state) {
+ led_commands[i].on();
+ } else {
+ led_commands[i].off();
+ }
+ } else {
+ __led_set(led_commands[i].mask, state);
+ }
+ break;
+ }
+ }
+
+ /* If we ran out of matches, print Usage */
+ if (!led_commands[i].string && !(strcmp("all", argv[1]) == 0)) {
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ led, 3, 1, do_led,
+ "led\t- ["
+#ifdef CONFIG_BOARD_SPECIFIC_LED
+#ifdef STATUS_LED_BIT
+ "0|"
+#endif
+#ifdef STATUS_LED_BIT1
+ "1|"
+#endif
+#ifdef STATUS_LED_BIT2
+ "2|"
+#endif
+#ifdef STATUS_LED_BIT3
+ "3|"
+#endif
+#endif
+#ifdef STATUS_LED_GREEN
+ "green|"
+#endif
+#ifdef STATUS_LED_YELLOW
+ "yellow|"
+#endif
+#ifdef STATUS_LED_RED
+ "red|"
+#endif
+#ifdef STATUS_LED_BLUE
+ "blue|"
+#endif
+ "all] [on|off]\n",
+ "led [led_name] [on|off] sets or clears led(s)\n"
+);
/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
- * Written-by: Albert ARIBAUD <albert.aribaud@free.fr>
+ * Written-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
#include <common.h>
-#ifdef CONFIG_MX31
-#include <asm/arch/mx31-regs.h>
-#endif
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h>
-#endif
#include <asm/io.h>
#include <mxc_gpio.h>
COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o
COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
+COBJS-$(CONFIG_I2C_MV) += mv_i2c.o
COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
* (C) Copyright 2003 Pengutronix e.K.
* Robert Schwebel <r.schwebel@pengutronix.de>
*
+ * (C) Copyright 2011 Marvell Inc.
+ * Lei Wen <leiwen@marvell.com>
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
*/
-/* FIXME: this file is PXA255 specific! What about other XScales? */
-
#include <common.h>
#include <asm/io.h>
#ifdef CONFIG_HARD_I2C
-
-/*
- * - CONFIG_SYS_I2C_SPEED
- * - I2C_PXA_SLAVE_ADDR
- */
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
#include <i2c.h>
-
-/*#define DEBUG_I2C 1 /###* activate local debugging output */
-#define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */
-
-#if (CONFIG_SYS_I2C_SPEED == 400000)
-#define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
-#else
-#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
-#endif
-
-#define I2C_ISR_INIT 0x7FF
+#include "mv_i2c.h"
#ifdef DEBUG_I2C
#define PRINTD(x) printf x
#define PRINTD(x)
#endif
-
-/* Shall the current transfer have a start/stop condition? */
-#define I2C_COND_NORMAL 0
-#define I2C_COND_START 1
-#define I2C_COND_STOP 2
-
-/* Shall the current transfer be ack/nacked or being waited for it? */
-#define I2C_ACKNAK_WAITACK 1
-#define I2C_ACKNAK_SENDACK 2
-#define I2C_ACKNAK_SENDNAK 4
-
-/* Specify who shall transfer the data (master or slave) */
-#define I2C_READ 0
-#define I2C_WRITE 1
-
/* All transfers are described by this data structure */
struct i2c_msg {
u8 condition;
u8 data;
};
+struct mv_i2c {
+ u32 ibmr;
+ u32 pad0;
+ u32 idbr;
+ u32 pad1;
+ u32 icr;
+ u32 pad2;
+ u32 isr;
+ u32 pad3;
+ u32 isar;
+};
+
+static struct mv_i2c *base;
+#ifdef CONFIG_I2C_MULTI_BUS
+static u32 i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG;
+static unsigned int bus_initialized[CONFIG_MV_I2C_NUM];
+static unsigned int current_bus;
+
+int i2c_set_bus_num(unsigned int bus)
+{
+ if ((bus < 0) || (bus >= CONFIG_MV_I2C_NUM)) {
+ printf("Bad bus: %d\n", bus);
+ return -1;
+ }
+
+ base = (struct mv_i2c *)i2c_regs[bus];
+ current_bus = bus;
+
+ if (!bus_initialized[current_bus]) {
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ bus_initialized[current_bus] = 1;
+ }
+
+ return 0;
+}
-/**
- * i2c_pxa_reset: - reset the host controller
+unsigned int i2c_get_bus_num(void)
+{
+ return current_bus;
+}
+#endif
+
+/*
+ * i2c_reset: - reset the host controller
*
*/
-
-static void i2c_reset( void )
+static void i2c_reset(void)
{
- writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
- writel(readl(ICR) | ICR_UR, ICR); /* reset the unit */
+ writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
+ writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */
udelay(100);
- writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
-#ifdef CONFIG_CPU_MONAHANS
- /* | CKENB_1_PWM1 | CKENB_0_PWM0); */
- writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
-#else /* CONFIG_CPU_MONAHANS */
- /* set the global I2C clock on */
- writel(readl(CKEN) | CKEN14_I2C, CKEN);
-#endif
- writel(I2C_PXA_SLAVE_ADDR, ISAR); /* set our slave address */
- writel(I2C_ICR_INIT, ICR); /* set control reg values */
- writel(I2C_ISR_INIT, ISR); /* set clear interrupt bits */
- writel(readl(ICR) | ICR_IUE, ICR); /* enable unit */
+ writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
+
+ i2c_clk_enable();
+
+ writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */
+ writel(I2C_ICR_INIT, &base->icr); /* set control reg values */
+ writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */
+ writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */
udelay(100);
}
-
-/**
+/*
* i2c_isr_set_cleared: - wait until certain bits of the I2C status register
* are set and cleared
*
* @return: 1 in case of success, 0 means timeout (no match within 10 ms).
*/
-static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask )
+static int i2c_isr_set_cleared(unsigned long set_mask,
+ unsigned long cleared_mask)
{
- int timeout = 10000;
+ int timeout = 1000, isr;
- while( ((ISR & set_mask)!=set_mask) || ((ISR & cleared_mask)!=0) ){
- udelay( 10 );
- if( timeout-- < 0 ) return 0;
- }
+ do {
+ isr = readl(&base->isr);
+ udelay(10);
+ if (timeout-- < 0)
+ return 0;
+ } while (((isr & set_mask) != set_mask)
+ || ((isr & cleared_mask) != 0));
return 1;
}
-
-/**
+/*
* i2c_transfer: - Transfer one byte over the i2c bus
*
* This function can tranfer a byte over the i2c bus in both directions.
if (!msg)
goto transfer_error_msg_empty;
- switch(msg->direction) {
-
+ switch (msg->direction) {
case I2C_WRITE:
-
/* check if bus is not busy */
- if (!i2c_isr_set_cleared(0,ISR_IBB))
+ if (!i2c_isr_set_cleared(0, ISR_IBB))
goto transfer_error_bus_busy;
/* start transmission */
- writel(readl(ICR) & ~ICR_START, ICR);
- writel(readl(ICR) & ~ICR_STOP, ICR);
- writel(msg->data, IDBR);
+ writel(readl(&base->icr) & ~ICR_START, &base->icr);
+ writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
+ writel(msg->data, &base->idbr);
if (msg->condition == I2C_COND_START)
- writel(readl(ICR) | ICR_START, ICR);
+ writel(readl(&base->icr) | ICR_START, &base->icr);
if (msg->condition == I2C_COND_STOP)
- writel(readl(ICR) | ICR_STOP, ICR);
+ writel(readl(&base->icr) | ICR_STOP, &base->icr);
if (msg->acknack == I2C_ACKNAK_SENDNAK)
- writel(readl(ICR) | ICR_ACKNAK, ICR);
+ writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
if (msg->acknack == I2C_ACKNAK_SENDACK)
- writel(readl(ICR) & ~ICR_ACKNAK, ICR);
- writel(readl(ICR) & ~ICR_ALDIE, ICR);
- writel(readl(ICR) | ICR_TB, ICR);
+ writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
+ writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
+ writel(readl(&base->icr) | ICR_TB, &base->icr);
/* transmit register empty? */
- if (!i2c_isr_set_cleared(ISR_ITE,0))
+ if (!i2c_isr_set_cleared(ISR_ITE, 0))
goto transfer_error_transmit_timeout;
/* clear 'transmit empty' state */
- writel(readl(ISR) | ISR_ITE, ISR);
+ writel(readl(&base->isr) | ISR_ITE, &base->isr);
/* wait for ACK from slave */
if (msg->acknack == I2C_ACKNAK_WAITACK)
- if (!i2c_isr_set_cleared(0,ISR_ACKNAK))
+ if (!i2c_isr_set_cleared(0, ISR_ACKNAK))
goto transfer_error_ack_missing;
break;
case I2C_READ:
/* check if bus is not busy */
- if (!i2c_isr_set_cleared(0,ISR_IBB))
+ if (!i2c_isr_set_cleared(0, ISR_IBB))
goto transfer_error_bus_busy;
/* start receive */
- writel(readl(ICR) & ~ICR_START, ICR);
- writel(readl(ICR) & ~ICR_STOP, ICR);
+ writel(readl(&base->icr) & ~ICR_START, &base->icr);
+ writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
if (msg->condition == I2C_COND_START)
- writel(readl(ICR) | ICR_START, ICR);
+ writel(readl(&base->icr) | ICR_START, &base->icr);
if (msg->condition == I2C_COND_STOP)
- writel(readl(ICR) | ICR_STOP, ICR);
+ writel(readl(&base->icr) | ICR_STOP, &base->icr);
if (msg->acknack == I2C_ACKNAK_SENDNAK)
- writel(readl(ICR) | ICR_ACKNAK, ICR);
+ writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
if (msg->acknack == I2C_ACKNAK_SENDACK)
- writel(readl(ICR) & ~ICR_ACKNAK, ICR);
- writel(readl(ICR) & ~ICR_ALDIE, ICR);
- writel(readl(ICR) | ICR_TB, ICR);
+ writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
+ writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
+ writel(readl(&base->icr) | ICR_TB, &base->icr);
/* receive register full? */
- if (!i2c_isr_set_cleared(ISR_IRF,0))
+ if (!i2c_isr_set_cleared(ISR_IRF, 0))
goto transfer_error_receive_timeout;
- msg->data = readl(IDBR);
+ msg->data = readl(&base->idbr);
/* clear 'receive empty' state */
- writel(readl(ISR) | ISR_IRF, ISR);
-
+ writel(readl(&base->isr) | ISR_IRF, &base->isr);
break;
-
default:
-
goto transfer_error_illegal_param;
-
}
return 0;
ret = -6; goto i2c_transfer_finish;
i2c_transfer_finish:
- PRINTD(("i2c_transfer: ISR: 0x%04x\n",ISR));
+ PRINTD(("i2c_transfer: ISR: 0x%04x\n", ISR));
i2c_reset();
return ret;
-
}
/* ------------------------------------------------------------------------ */
/* API Functions */
/* ------------------------------------------------------------------------ */
-
void i2c_init(int speed, int slaveaddr)
{
+#ifdef CONFIG_I2C_MULTI_BUS
+ base = (struct mv_i2c *)i2c_regs[current_bus];
+#else
+ base = (struct mv_i2c *)CONFIG_MV_I2C_REG;
+#endif
+
#ifdef CONFIG_SYS_I2C_INIT_BOARD
- /* call board specific i2c bus reset routine before accessing the */
- /* environment, which might be in a chip on that bus. For details */
- /* about this problem see doc/I2C_Edge_Conditions. */
+ u32 icr;
+ /*
+ * call board specific i2c bus reset routine before accessing the
+ * environment, which might be in a chip on that bus. For details
+ * about this problem see doc/I2C_Edge_Conditions.
+ *
+ * disable I2C controller first, otherwhise it thinks we want to
+ * talk to the slave port...
+ */
+ icr = readl(&base->icr);
+ writel(readl(&base->icr) & ~(ICR_SCLE | ICR_IUE), &base->icr);
+
i2c_init_board();
+
+ writel(icr, &base->icr);
#endif
}
-
-/**
+/*
* i2c_probe: - Test if a chip answers for a given i2c address
*
* @chip: address of the chip which is searched for
* @return: 0 if a chip was found, -1 otherwhise
*/
-
int i2c_probe(uchar chip)
{
struct i2c_msg msg;
msg.acknack = I2C_ACKNAK_WAITACK;
msg.direction = I2C_WRITE;
msg.data = (chip << 1) + 1;
- if (i2c_transfer(&msg)) return -1;
+ if (i2c_transfer(&msg))
+ return -1;
msg.condition = I2C_COND_STOP;
msg.acknack = I2C_ACKNAK_SENDNAK;
msg.direction = I2C_READ;
msg.data = 0x00;
- if (i2c_transfer(&msg)) return -1;
+ if (i2c_transfer(&msg))
+ return -1;
return 0;
}
-
-/**
+/*
* i2c_read: - Read multiple bytes from an i2c device
*
* The higher level routines take into account that this function is only
* @len: how much byte do we want to read
* @return: 0 in case of success
*/
-
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
struct i2c_msg msg;
u8 addr_bytes[3]; /* lowest...highest byte of data address */
- int ret;
- PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len));
+ PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
+ "len=0x%02x)\n", chip, addr, alen, len));
i2c_reset();
msg.condition = I2C_COND_START;
msg.acknack = I2C_ACKNAK_WAITACK;
msg.direction = I2C_WRITE;
- msg.data = (chip << 1);
- msg.data &= 0xFE;
- if ((ret=i2c_transfer(&msg))) return -1;
+ msg.data = (chip << 1);
+ msg.data &= 0xFE;
+ if (i2c_transfer(&msg))
+ return -1;
/*
* send memory address bytes;
addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF);
while (--alen >= 0) {
-
- PRINTD(("i2c_read: send memory word address byte %1d\n",alen));
+ PRINTD(("i2c_read: send memory word address byte %1d\n", alen));
msg.condition = I2C_COND_NORMAL;
msg.acknack = I2C_ACKNAK_WAITACK;
msg.direction = I2C_WRITE;
msg.data = addr_bytes[alen];
- if ((ret=i2c_transfer(&msg))) return -1;
+ if (i2c_transfer(&msg))
+ return -1;
}
-
/* start read sequence */
PRINTD(("i2c_read: start read sequence\n"));
msg.condition = I2C_COND_START;
msg.direction = I2C_WRITE;
msg.data = (chip << 1);
msg.data |= 0x01;
- if ((ret=i2c_transfer(&msg))) return -1;
+ if (i2c_transfer(&msg))
+ return -1;
/* read bytes; send NACK at last byte */
while (len--) {
-
- if (len==0) {
+ if (len == 0) {
msg.condition = I2C_COND_STOP;
msg.acknack = I2C_ACKNAK_SENDNAK;
} else {
msg.direction = I2C_READ;
msg.data = 0x00;
- if ((ret=i2c_transfer(&msg))) return -1;
+ if (i2c_transfer(&msg))
+ return -1;
*buffer = msg.data;
- PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer));
+ PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",
+ (unsigned int)buffer, *buffer));
buffer++;
-
}
i2c_reset();
return 0;
}
-
-/**
+/*
* i2c_write: - Write multiple bytes to an i2c device
*
* The higher level routines take into account that this function is only
* @len: how much byte do we want to read
* @return: 0 in case of success
*/
-
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
struct i2c_msg msg;
u8 addr_bytes[3]; /* lowest...highest byte of data address */
- PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len));
+ PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
+ "len=0x%02x)\n", chip, addr, alen, len));
i2c_reset();
msg.condition = I2C_COND_START;
msg.acknack = I2C_ACKNAK_WAITACK;
msg.direction = I2C_WRITE;
- msg.data = (chip << 1);
- msg.data &= 0xFE;
- if (i2c_transfer(&msg)) return -1;
+ msg.data = (chip << 1);
+ msg.data &= 0xFE;
+ if (i2c_transfer(&msg))
+ return -1;
/*
* send memory address bytes;
addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF);
while (--alen >= 0) {
-
PRINTD(("i2c_write: send memory word address\n"));
msg.condition = I2C_COND_NORMAL;
msg.acknack = I2C_ACKNAK_WAITACK;
msg.direction = I2C_WRITE;
msg.data = addr_bytes[alen];
- if (i2c_transfer(&msg)) return -1;
+ if (i2c_transfer(&msg))
+ return -1;
}
/* write bytes; send NACK at last byte */
while (len--) {
+ PRINTD(("i2c_write: writing byte (0x%08x)=0x%02x\n",
+ (unsigned int)buffer, *buffer));
- PRINTD(("i2c_write: writing byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer));
-
- if (len==0)
+ if (len == 0)
msg.condition = I2C_COND_STOP;
else
msg.condition = I2C_COND_NORMAL;
msg.direction = I2C_WRITE;
msg.data = *(buffer++);
- if (i2c_transfer(&msg)) return -1;
-
+ if (i2c_transfer(&msg))
+ return -1;
}
i2c_reset();
return 0;
-
}
-
#endif /* CONFIG_HARD_I2C */
--- /dev/null
+/*
+ * (C) Copyright 2011
+ * Marvell Inc, <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _MV_I2C_H_
+#define _MV_I2C_H_
+extern void i2c_clk_enable(void);
+
+/* Shall the current transfer have a start/stop condition? */
+#define I2C_COND_NORMAL 0
+#define I2C_COND_START 1
+#define I2C_COND_STOP 2
+
+/* Shall the current transfer be ack/nacked or being waited for it? */
+#define I2C_ACKNAK_WAITACK 1
+#define I2C_ACKNAK_SENDACK 2
+#define I2C_ACKNAK_SENDNAK 4
+
+/* Specify who shall transfer the data (master or slave) */
+#define I2C_READ 0
+#define I2C_WRITE 1
+
+#if (CONFIG_SYS_I2C_SPEED == 400000)
+#define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD \
+ | ICR_SCLE)
+#else
+#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
+#endif
+
+#define I2C_ISR_INIT 0x7FF
+/* ----- Control register bits ---------------------------------------- */
+
+#define ICR_START 0x1 /* start bit */
+#define ICR_STOP 0x2 /* stop bit */
+#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
+#define ICR_TB 0x8 /* transfer byte bit */
+#define ICR_MA 0x10 /* master abort */
+#define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */
+#define ICR_IUE 0x40 /* unit enable */
+#define ICR_GCD 0x80 /* general call disable */
+#define ICR_ITEIE 0x100 /* enable tx interrupts */
+#define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */
+#define ICR_BEIE 0x400 /* enable bus error ints */
+#define ICR_SSDIE 0x800 /* slave STOP detected int enable */
+#define ICR_ALDIE 0x1000 /* enable arbitration interrupt */
+#define ICR_SADIE 0x2000 /* slave address detected int enable */
+#define ICR_UR 0x4000 /* unit reset */
+#define ICR_FM 0x8000 /* Fast Mode */
+
+/* ----- Status register bits ----------------------------------------- */
+
+#define ISR_RWM 0x1 /* read/write mode */
+#define ISR_ACKNAK 0x2 /* ack/nak status */
+#define ISR_UB 0x4 /* unit busy */
+#define ISR_IBB 0x8 /* bus busy */
+#define ISR_SSD 0x10 /* slave stop detected */
+#define ISR_ALD 0x20 /* arbitration loss detected */
+#define ISR_ITE 0x40 /* tx buffer empty */
+#define ISR_IRF 0x80 /* rx buffer full */
+#define ISR_GCAD 0x100 /* general call address detected */
+#define ISR_SAD 0x200 /* slave address detected */
+#define ISR_BED 0x400 /* bus error no ACK/NAK */
+
+#endif
* Driver for the TWSI (i2c) controller found on the Marvell
* orion5x and kirkwood SoC families.
*
- * Author: Albert Aribaud <albert.aribaud@free.fr>
+ * Author: Albert Aribaud <albert.u.boot@aribaud.net>
* Copyright (c) 2010 Albert Aribaud.
*
* See file CREDITS for list of people who contributed to this
#if defined(CONFIG_HARD_I2C)
-#if defined(CONFIG_MX31)
-#include <asm/arch/mx31.h>
-#include <asm/arch/mx31-regs.h>
-#else
-#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#endif
+#include <asm/arch/imx-regs.h>
#define IADR 0x00
#define IFDR 0x04
COBJS-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o
COBJS-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o
COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o
+COBJS-$(CONFIG_FTSMC020) += ftsmc020.o
COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o
COBJS-$(CONFIG_SPEARSMI) += spr_smi.o
#include <config.h>
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/ftsmc020.h>
+#include <faraday/ftsmc020.h>
struct ftsmc020_config {
unsigned int config;
#include <common.h>
#include <asm/io.h>
-#include "ftpmu010.h"
-
-static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
+#include <faraday/ftpmu010.h>
+/* OSCC: OSC Control Register */
void ftpmu010_32768osc_enable(void)
{
+ static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int oscc;
/* enable the 32768Hz oscillator */
writel(oscc, &pmu->OSCC);
}
+/* MFPSR: Multi-Function Port Setting Register */
+void ftpmu010_mfpsr_select_dev(unsigned int dev)
+{
+ static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
+ unsigned int mfpsr;
+
+ mfpsr = readl(&pmu->MFPSR);
+ mfpsr |= dev;
+ writel(mfpsr, &pmu->MFPSR);
+}
+
+void ftpmu010_mfpsr_diselect_dev(unsigned int dev)
+{
+ static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
+ unsigned int mfpsr;
+
+ mfpsr = readl(&pmu->MFPSR);
+ mfpsr &= ~dev;
+ writel(mfpsr, &pmu->MFPSR);
+}
+
+/* PDLLCR0: PLL/DLL Control Register 0 */
void ftpmu010_dlldis_disable(void)
{
+ static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int pdllcr0;
pdllcr0 = readl(&pmu->PDLLCR0);
void ftpmu010_sdram_clk_disable(unsigned int cr0)
{
+ static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int pdllcr0;
pdllcr0 = readl(&pmu->PDLLCR0);
pdllcr0 |= FTPMU010_PDLLCR0_HCLKOUTDIS(cr0);
writel(pdllcr0, &pmu->PDLLCR0);
}
+
+/* SDRAMHTC: SDRAM Signal Hold Time Control */
+void ftpmu010_sdramhtc_set(unsigned int val)
+{
+ static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
+ unsigned int sdramhtc;
+
+ sdramhtc = readl(&pmu->SDRAMHTC);
+ sdramhtc |= val;
+ writel(sdramhtc, &pmu->SDRAMHTC);
+}
#include <common.h>
#include <watchdog.h>
-#ifdef CONFIG_MX31
-#include <asm/arch/mx31.h>
-#else
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#endif
#define __REG(x) (*((volatile u32 *)(x)))
#include <asm/errno.h>
#include <asm/io.h>
#include <mxc_gpio.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
#elif defined(CONFIG_MX31)
-#include <asm/arch/mx31.h>
-
#define MXC_CSPICTRL_EN (1 << 0)
#define MXC_CSPICTRL_MODE (1 << 1)
#define MXC_CSPICTRL_XCH (1 << 2)
#define mxc_get_clock(x) mx31_get_ipg_clk()
#elif defined(CONFIG_MX51)
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
#define MXC_CSPICTRL_EN (1 << 0)
#define MXC_CSPICTRL_MODE (1 << 1)
#elif defined(CONFIG_MX35)
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-
#define MXC_CSPICTRL_EN (1 << 0)
#define MXC_CSPICTRL_MODE (1 << 1)
#define MXC_CSPICTRL_XCH (1 << 2)
#include <common.h>
#include <usb.h>
#include <asm/io.h>
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
#include <usb/ehci-fsl.h>
#include <errno.h>
*/
#include <common.h>
#include <lcd.h>
-#include <asm/arch/mx31.h>
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
#include <asm/errno.h>
DECLARE_GLOBAL_DATA_PTR;
};
/* IPU Common registers */
-/* IPU_CONF and its bits already defined in mx31-regs.h */
+/* IPU_CONF and its bits already defined in imx-regs.h */
#define IPU_CHA_BUF0_RDY (0x04 + IPU_BASE)
#define IPU_CHA_BUF1_RDY (0x08 + IPU_BASE)
#define IPU_CHA_DB_MODE_SEL (0x0C + IPU_BASE)
#undef CONFIG_SKIP_LOWLEVEL_INIT
/*-----------------------------------------------------------------------
+ * Power Management Unit
+ */
+#define CONFIG_FTPMU010_POWER
+
+/*-----------------------------------------------------------------------
* Timer
*/
#define CONFIG_SYS_HZ 1000 /* timer ticks per second */
* Static memory controller configuration
*/
-#include <asm/arch/ftsmc020.h>
+#define CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
}
+#endif /* CONFIG_FTSMC020 */
/*-----------------------------------------------------------------------
* FLASH and environment organization
--- /dev/null
+/*
+ * am3517_crane.h - Default configuration for AM3517 CraneBoard.
+ *
+ * Author: Srinath.R <srinath@mistralsolutions.com>
+ *
+ * Based on include/configs/am3517evm.h
+ *
+ * Copyright (C) 2011 Mistral Solutions pvt Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
+
+#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+ /* initial data */
+/*
+ * DDR related
+ */
+#define CONFIG_OMAP3_MICRON_DDR 1 /* Micron DDR */
+#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+#define CONFIG_MMC 1
+#define CONFIG_OMAP3_MMC 1
+#define CONFIG_DOS_PARTITION 1
+
+/*
+ * USB configuration
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDC for Device functionalities.
+ */
+#define CONFIG_USB_AM35X 1
+#define CONFIG_MUSB_HCD 1
+
+#ifdef CONFIG_USB_AM35X
+
+#ifdef CONFIG_MUSB_HCD
+#define CONFIG_CMD_USB
+
+#define CONFIG_USB_STORAGE
+#define CONGIG_CMD_STORAGE
+#define CONFIG_CMD_FAT
+
+#ifdef CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_PREBOOT "usb start"
+#endif /* CONFIG_USB_KEYBOARD */
+
+#endif /* CONFIG_MUSB_HCD */
+
+#ifdef CONFIG_MUSB_UDC
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID 0x0451
+#define CONFIG_USBD_PRODUCTID 0x5678
+#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE"
+#endif /* CONFIG_MUSB_UDC */
+
+#endif /* CONFIG_USB_AM35X */
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_NAND /* NAND support */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
+ /* to access nand */
+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
+ /* to access */
+ /* nand at CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
+ /* NAND devices */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV "nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET 0x680000
+#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY 10
+
+#define CONFIG_BOOTFILE uImage
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "console=ttyS2,115200n8\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "root=/dev/mmcblk0p2 rw " \
+ "rootfstype=ext3 rootwait\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "root=/dev/mtdblock4 rw " \
+ "rootfstype=jffs2\0" \
+ "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${loadaddr} 280000 400000; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc init; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run nandboot; " \
+ "fi; " \
+ "fi; " \
+ "else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE 1
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT "AM3517_CRANE # "
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT V_PROMPT
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 32 /* max number of command */
+ /* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
+ 0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
+ /* address */
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
+
+#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
+ /* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
+#define CONFIG_ENV_IS_IN_NAND 1
+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
+ CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS 1
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#endif /* __CONFIG_H */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_SYS_FLASH_BASE boot_flash_base
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_ENV_IS_IN_NAND 1
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
-#define CONFIG_ENV_OFFSET boot_flash_off
-#define CONFIG_ENV_ADDR boot_flash_env_addr
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
/*-----------------------------------------------------------------------
* CFI FLASH driver setup
#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
-
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
+#define CONFIG_CMD_I2C
#define CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
/* Board info register */
#define SYS_ID 0x10000000
#define CONFIG_REVISION_TAG 1
+#define CONFIG_SYS_TEXT_BASE 0x60800000
/* High Level Configuration Options */
#define CONFIG_ARMV7 1
/*
- * (C) Copyright 2010
+ * (C) Copyright 2011
* CompuLab, Ltd.
* Mike Rapoport <mike@compulab.co.il>
+ * Igor Grinberg <grinberg@compulab.co.il>
*
* Based on omap3_beagle.h
* (C) Copyright 2006-2008
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <x0khasim@ti.com>
*
- * Configuration settings for the CompuLab CM-T35 board
+ * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
*
* See file CREDITS for list of people who contributed to this
* project.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc.
*/
#ifndef __CONFIG_H
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
-#define CONFIG_CM_T35 1 /* working with CM-T35 */
+#define CONFIG_CM_T3X 1 /* working with CM-T35 and CM-T3730 */
#define CONFIG_SYS_TEXT_BASE 0x80008000
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
-#define CONFIG_GENERIC_MMC 1
#define CONFIG_MMC 1
-#define CONFIG_OMAP_HSMMC 1
+#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
/* DDR - I use Micron DDR */
"fi; " \
"else run nandboot; fi"
-#define CONFIG_AUTO_COMPLETE 1
/*
* Miscellaneous configurable options
*/
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_TIMESTAMP
+#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_PROMPT "CM-T35 # "
+#define CONFIG_SYS_PROMPT "CM-T3x # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_SYS_FLASH_BASE boot_flash_base
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
-#define CONFIG_ENV_OFFSET boot_flash_off
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
-
#if defined(CONFIG_CMD_NET)
#define CONFIG_NET_MULTI
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
-#define CM_T35_SMC911X_BASE 0x2C000000
-#define SB_T35_SMC911X_BASE (CM_T35_SMC911X_BASE + (16 << 20))
-#define CONFIG_SMC911X_BASE CM_T35_SMC911X_BASE
+#define CM_T3X_SMC911X_BASE 0x2C000000
+#define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20))
+#define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE
#endif /* (CONFIG_CMD_NET) */
/* additions for new relocation code, must be added to all boards */
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
+/* Status LED */
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED 1
+#define STATUS_LED_GREEN 0
+#define STATUS_LED_BIT STATUS_LED_GREEN
+#define STATUS_LED_STATE STATUS_LED_ON
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BOOT STATUS_LED_BIT
+#define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
+
+/* GPIO banks */
+#ifdef CONFIG_STATUS_LED
+#define CONFIG_OMAP3_GPIO_6 1 /* GPIO186 is in GPIO bank 6 */
+#endif
+
#endif /* __CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_AT91_LEGACY
-
-#define CONFIG_DISPLAY_CPUINFO 1
+/* to be removed once maemory-map.h is fixed */
+#define AT91_BASE_SYS 0xffffe800
+#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
#define CONFIG_SYS_HZ 1000
-#define CONFIG_ARM926EJS 1
-
-#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9260)
-#define CONFIG_CPU9260 1
-#elif defined(CONFIG_CPU9G20_128M) || defined(CONFIG_CPU9G20)
-#define CONFIG_CPU9G20 1
-#endif
+#define CONFIG_ARM926EJS
#if defined(CONFIG_CPU9G20)
-#define CONFIG_AT91SAM9G20 1
+#define CONFIG_AT91SAM9G20
#elif defined(CONFIG_CPU9260)
-#define CONFIG_AT91SAM9260 1
+#define CONFIG_AT91SAM9260
#else
#error "Unknown board"
#endif
+#define CONFIG_AT91FAMILY
#define CONFIG_ARCH_CPU_INIT
#undef CONFIG_USE_IRQ
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_CMDLINE_TAG 1
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#if defined(CONFIG_NANDBOOT)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE 0x23f00000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+#endif
/* clocks */
#if defined(CONFIG_CPU9G20)
/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
#define CONFIG_SYS_MATRIX_EBICSA_VAL \
- (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC |\
- AT91_MATRIX_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_VDDIOMSEL)
+ (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \
+ AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V)
/* SDRAM */
/* SDRAMC_MR Mode register */
/* setup SMC0, CS0 (NOR Flash) - 16-bit */
#if defined(CONFIG_CPU9G20)
#define CONFIG_SYS_SMC0_SETUP0_VAL \
- (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \
- AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
+ (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
+ AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
#define CONFIG_SYS_SMC0_PULSE0_VAL \
- (AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(8) | \
- AT91_SMC_NRDPULSE_(14) | AT91_SMC_NCS_RDPULSE_(14))
+ (AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) | \
+ AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14))
#define CONFIG_SYS_SMC0_CYCLE0_VAL \
- (AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(14))
+ (AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14))
#define CONFIG_SYS_SMC0_MODE0_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(3))
+ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
+ AT91_SMC_MODE_DBW_16 | \
+ AT91_SMC_MODE_TDF | \
+ AT91_SMC_MODE_TDF_CYCLE(3))
#elif defined(CONFIG_CPU9260)
#define CONFIG_SYS_SMC0_SETUP0_VAL \
- (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \
- AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
+ (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
+ AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
#define CONFIG_SYS_SMC0_PULSE0_VAL \
- (AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(6) | \
- AT91_SMC_NRDPULSE_(10) | AT91_SMC_NCS_RDPULSE_(10))
+ (AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) | \
+ AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10))
#define CONFIG_SYS_SMC0_CYCLE0_VAL \
- (AT91_SMC_NWECYCLE_(6) | AT91_SMC_NRDCYCLE_(10))
+ (AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10))
#define CONFIG_SYS_SMC0_MODE0_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(2))
+ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
+ AT91_SMC_MODE_DBW_16 | \
+ AT91_SMC_MODE_TDF | \
+ AT91_SMC_MODE_TDF_CYCLE(2))
#endif
/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \
- AT91_RSTC_PROCRST | \
- AT91_RSTC_RSTTYP_WAKEUP | \
- AT91_RSTC_RSTTYP_WATCHDOG)
+ AT91_RSTC_CR_PROCRST | \
+ AT91_RSTC_MR_ERSTL(1) | \
+ AT91_RSTC_MR_ERSTL(2))
/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
- AT91_WDT_WDV | \
- AT91_WDT_WDDIS | \
- AT91_WDT_WDD)
+ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
+ AT91_WDT_MR_WDV(0xfff) | \
+ AT91_WDT_MR_WDDIS | \
+ AT91_WDT_MR_WDD(0xfff))
/*
* Hardware drivers
*/
-#define CONFIG_AT91_GPIO 1
-#define CONFIG_ATMEL_USART 1
+#define CONFIG_AT91SAM9_WATCHDOG
+#define CONFIG_AT91_GPIO
+#define CONFIG_ATMEL_USART
#undef CONFIG_USART0
#undef CONFIG_USART1
#undef CONFIG_USART2
-#define CONFIG_USART3 1 /* USART 3 is DBGU */
+#define CONFIG_USART3
#define CONFIG_BOOTDELAY 3
/*
* BOOTP options
*/
-#define CONFIG_BOOTP_BOOTFILESIZE 1
-#define CONFIG_BOOTP_BOOTPATH 1
-#define CONFIG_BOOTP_GATEWAY 1
-#define CONFIG_BOOTP_HOSTNAME 1
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
-#define CONFIG_CMD_PING 1
-#define CONFIG_CMD_DHCP 1
-#define CONFIG_CMD_NAND 1
-#define CONFIG_CMD_USB 1
-#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MII
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM 0x20000000
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
-#define PHYS_SDRAM_SIZE 0x08000000 /* 128 MB */
+#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB
#else
-#define PHYS_SDRAM_SIZE 0x04000000 /* 64 MB */
+#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB
#endif
/* NAND flash */
-#define CONFIG_NAND_ATMEL 1
+#define CONFIG_NAND_ATMEL
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTC, 13
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
/* NOR flash */
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_FLASH_CFI_DRIVER 1
+#if defined(CONFIG_NANDBOOT)
+#define CONFIG_SYS_NO_FLASH
+#else
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
#define PHYS_FLASH_1 0x10000000
#define PHYS_FLASH_2 0x12000000
#define CONFIG_SYS_FLASH_BANKS_LIST \
#define CONFIG_SYS_MAX_FLASH_SECT (255+4)
#define CONFIG_SYS_MAX_FLASH_BANKS 2
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_EMPTY_INFO 1
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-#define CONFIG_SYS_FLASH_PROTECTION 1
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
+#endif
/* Ethernet */
-#define CONFIG_MACB 1
-#define CONFIG_RMII 1
-#define CONFIG_RESET_PHY_R 1
-#define CONFIG_NET_MULTI 1
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_MULTI
#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_MACB_SEARCH_PHY 1
+#define CONFIG_MACB_SEARCH_PHY
/* LEDS */
/* Status LED */
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-#define CONFIG_BOARD_SPECIFIC_LED 1
+#define CONFIG_STATUS_LED
+#define CONFIG_BOARD_SPECIFIC_LED
#define STATUS_LED_RED 0
#define STATUS_LED_GREEN 1
#define STATUS_LED_YELLOW 2
/* Optional value */
#define STATUS_LED_BOOT STATUS_LED_BIT
-#define CONFIG_RED_LED AT91_PIN_PC11
-#define CONFIG_GREEN_LED AT91_PIN_PC12
-#define CONFIG_YELLOW_LED AT91_PIN_PC7
-#define CONFIG_BLUE_LED AT91_PIN_PC9
+#define CONFIG_RED_LED AT91_PIO_PORTC, 11
+#define CONFIG_GREEN_LED AT91_PIO_PORTC, 12
+#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 7
+#define CONFIG_BLUE_LED AT91_PIO_PORTC, 9
/* USB */
-#define CONFIG_USB_ATMEL 1
-#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g20"
+#elif defined(CONFIG_CPU9260)
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
+#endif
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_USB_STORAGE 1
+#define CONFIG_USB_STORAGE
#define CONFIG_SYS_LOAD_ADDR 0x21000000
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
-#define CONFIG_SYS_MEMTEST_END 0x21e00000
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END \
+ (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
+#if defined(CONFIG_NANDBOOT)
+#define CONFIG_SYS_USE_NANDFLASH
+#undef CONFIG_SYS_USE_FLASH
+#else
+#define CONFIG_SYS_USE_FLASH
#undef CONFIG_SYS_USE_NANDFLASH
-#define CONFIG_SYS_USE_FLASH 1
+#endif
+
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_SYS_BASEDIR "cpu9G20"
+#elif defined(CONFIG_CPU9260)
+#define CONFIG_SYS_BASEDIR "cpu9260"
+#endif
#if defined(CONFIG_SYS_USE_FLASH)
-#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_ENV_OVERWRITE
#define CONFIG_BOOTCOMMAND "run flashboot"
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
#define MTDPARTS_DEFAULT \
"mtdparts=physmap-flash.0:" \
"256k(u-boot)ro," \
#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_BASEDIR "cpu9G20"
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_BASEDIR "cpu9260"
-#endif
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"partition=nand0,0\0" \
"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
- "ramboot=tftpboot 0x22000000 cpu9260/uImage;" \
+ "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
"run ramargs;bootm 22000000\0" \
"flashboot=run ramargs;bootm 0x10060000\0" \
"basedir=" CONFIG_SYS_BASEDIR "\0" \
"0x10220000 0x13ffffff;cp.b 0x24000000 " \
"0x10220000 $(filesize)\0" \
""
+#elif defined(CONFIG_NANDBOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x60000
+#define CONFIG_ENV_OFFSET_REDUND 0x80000
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BOOTCOMMAND "run flashboot"
+
+#define MTDIDS_DEFAULT "nand0=atmel_nand"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=atmel_nand:" \
+ "128k(bootstrap)ro," \
+ "256k(u-boot)ro," \
+ "128k(u-boot-env)ro," \
+ "128k(u-boot-env2)ro," \
+ "2M(kernel)," \
+ "-(rootfs)"
+
+#define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs " \
+ "ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "partition=nand0,5\0" \
+ "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
+ "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
+ "run ramargs;bootm 22000000\0" \
+ "flashboot=run ramargs; nand read 0x22000000 0xA0000 " \
+ "0x200000; bootm 0x22000000\0" \
+ "basedir=" CONFIG_SYS_BASEDIR "\0" \
+ "u-boot=u-boot-eukrea-cpu9260.bin\0" \
+ "kernel=uImage-eukrea-cpu9260.bin\0" \
+ "rootfs=image-eukrea-cpu9260.ubi\0" \
+ "updtub=tftp ${loadaddr} $(basedir)/${u-boot}; " \
+ "nand erase 20000 40000; " \
+ "nand write ${loadaddr} 20000 40000\0" \
+ "updtui=tftp ${loadaddr} $(basedir)/${kernel}; " \
+ "nand erase a0000 200000; " \
+ "nand write ${loadaddr} a0000 200000\0" \
+ "updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; " \
+ "nand erase 2a0000 fd60000; " \
+ "nand write ${loadaddr} 2a0000 ${filesize}\0"
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_SILENT_CONSOLE 1
-#define CONFIG_NETCONSOLE 1
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_NETCONSOLE
/*
* Size of malloc() pool
#define CONFIG_SYS_MALLOC_LEN \
ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
+ GENERATED_GBL_DATA_SIZE)
+
#define CONFIG_STACKSIZE (32 * 1024)
#if defined(CONFIG_USE_IRQ)
#ifndef _CONFIG_CPUAT91_H
#define _CONFIG_CPUAT91_H
-#ifdef CONFIG_CPUAT91_RAM
-#define CONFIG_SKIP_LOWLEVEL_INIT 1
+#include <asm/sizes.h>
+
+#ifdef CONFIG_RAMBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE 0x21F00000
#else
#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_TEXT_BASE 0
#endif
-#define AT91C_MAIN_CLOCK 179712000
-#define AT91C_MASTER_CLOCK 59904000
-
-#define AT91_SLOW_CLOCK 32768
+#define AT91C_XTAL_CLOCK 18432000
+#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
+#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
+#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
+#define CONFIG_SYS_HZ 1000
-#define CONFIG_ARM920T 1
-#define CONFIG_AT91RM9200 1
-#define CONFIG_CPUAT91 1
+#define CONFIG_ARM920T
+#define CONFIG_AT91RM9200
+#define CONFIG_CPUAT91
+#define CONFIG_AT91FAMILY
#undef CONFIG_USE_IRQ
-#define USE_920T_MMU 1
+#define USE_920T_MMU
-#define CONFIG_CMDLINE_TAG 1
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR
/* flash */
#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
#define CONFIG_SYS_MC_PUP_VAL 0x00000000
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
/* define one of these to choose the DBGU, USART0 or USART1 as console */
-#define CONFIG_AT91RM9200_USART 1
-#define CONFIG_DBGU 1
-#undef CONFIG_USART0
-#undef CONFIG_USART1
+#define CONFIG_AT91RM9200_USART
+#define CONFIG_DBGU
#undef CONFIG_HARD_I2C
-#define CONFIG_SOFT_I2C 1
+#undef CONFIG_SOFT_I2C
#define AT91_PIN_SDA (1<<25)
#define AT91_PIN_SCL (1<<26)
-#define CONFIG_SYS_I2C_INIT_BOARD 1
+#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_SYS_I2C_SLAVE 0
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CONFIG_BOOTP_BOOTFILESIZE 1
-#define CONFIG_BOOTP_BOOTPATH 1
-#define CONFIG_BOOTP_GATEWAY 1
-#define CONFIG_BOOTP_HOSTNAME 1
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
#include <config_cmd_default.h>
-#define CONFIG_CMD_DHCP 1
-#define CONFIG_CMD_PING 1
-#define CONFIG_CMD_MII 1
-#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_USB
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM 1
-#define CONFIG_CMD_I2C 1
+#ifdef CONFIG_SOFT_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#endif
#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM 0x20000000
-#define PHYS_SDRAM_SIZE 0x02000000
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END \
- (CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512 * 1024)
+ (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
-#define CONFIG_NET_MULTI 1
-#define CONFIG_DRIVER_AT91EMAC 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8
-#define CONFIG_RMII 1
-#define CONFIG_MII 1
+#define CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC
+#define CONFIG_SYS_RX_ETH_BUFFER 16
+#define CONFIG_RMII
+#define CONFIG_MII
#define CONFIG_DRIVER_AT91EMAC_PHYADDR 1
#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_KS8721_PHY 1
+#define CONFIG_KS8721_PHY
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_SYS_FLASH_EMPTY_INFO 1
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_PROTECTION 1
+#define CONFIG_SYS_FLASH_PROTECTION
#define PHYS_FLASH_1 0x10000000
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_SECT 128
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
+#define PHYS_FLASH_SIZE (16 * 1024 * 1024)
+#define CONFIG_SYS_FLASH_BANKS_LIST \
+ { PHYS_FLASH_1 }
#if defined(CONFIG_CMD_USB)
-#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_USB_STORAGE 1
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_AT91C_PQFP_UHPBU 1
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_AT91C_PQFP_UHPBU
#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
#endif
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000)
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 128 * 1024)
+#define CONFIG_ENV_SIZE (128 * 1024)
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_SYS_LOAD_ADDR 0x21000000
#define CONFIG_SYS_MAXARGS 32
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
+#define CONFIG_SYS_MALLOC_LEN \
+ ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 4 * 1024)
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
+ GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
#define CONFIG_STACKSIZE (32 * 1024)
+#define CONFIG_STACKSIZE_IRQ (4 * 1024)
+#define CONFIG_STACKSIZE_FIQ (4 * 1024)
+
#if defined(CONFIG_USE_IRQ)
#error CONFIG_USE_IRQ not supported
#endif
-#define CONFIG_DEVICE_NULLDEV 1
-#define CONFIG_SILENT_CONSOLE 1
+#define CONFIG_DEVICE_NULLDEV
+#define CONFIG_SILENT_CONSOLE
-#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT \
"Press SPACE to abort autoboot\n"
#define CONFIG_AUTOBOOT_STOP_STR " "
#define CONFIG_AUTOBOOT_DELAY_STR "d"
-#define CONFIG_VERSION_VARIABLE 1
+#define CONFIG_VERSION_VARIABLE
#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
#define MTDPARTS_DEFAULT \
#define CONFIG_ENV_IS_IN_NAND 1
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_ENV_OFFSET boot_flash_off
-
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
--- /dev/null
+/*
+ * (C) Copyright 2011 Comelit Group SpA
+ * Luca Ceresoli <luca.ceresoli@comelit.it>
+ *
+ * Based on omap3_beagle.h:
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the Comelit DIG297 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP /* in a TI OMAP core */
+#define CONFIG_OMAP34XX /* which is a 34XX */
+#define CONFIG_OMAP3430 /* which is in a 3430 */
+
+#define CONFIG_SYS_TEXT_BASE 0x80008000
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+ /* Sector */
+#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* UBI needs >= 512 kB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration: UART3 (ttyO2)
+ */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+#define CONFIG_MMC
+#define CONFIG_OMAP3_MMC
+#define CONFIG_DOS_PARTITION
+
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR
+
+/* library portions to compile in */
+#define CONFIG_RBTREE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_UBI /* UBI Support */
+#define CONFIG_CMD_UBIFS /* UBIFS Support */
+#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:896k(uboot),"\
+ "128k(uboot-env),3m(kernel),252m(ubi)"
+
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_NAND /* NAND support */
+
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#undef CONFIG_CMD_NFS /* NFS support */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER
+#define CONFIG_TWL4030_LED
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
+ /* to access nand */
+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
+ /* to access nand at */
+ /* CS0 */
+#define GPMC_NAND_ECC_LP_x16_LAYOUT
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
+
+#if defined(CONFIG_CMD_NET)
+/*
+ * SMSC9220 Ethernet
+ */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE 0x2C000000
+
+#endif /* (CONFIG_CMD_NET) */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY 1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "console=ttyO2,115200n8\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "partition=nand0,3\0"\
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "nandroot=ubi0:rootfs ro\0" \
+ "nandrootfstype=ubifs\0" \
+ "nfspath=/srv/nfs\0" \
+ "tftpfilename=uImage\0" \
+ "gatewayip=0.0.0.0\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "${mtdparts} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}::off\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "${mtdparts} " \
+ "ubi.mtd=3 " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}::off\0" \
+ "netargs=setenv bootargs console=${console} " \
+ "${mtdparts} " \
+ "root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${nfspath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}::off\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${loadaddr} 100000 300000; " \
+ "bootm ${loadaddr}\0" \
+ "netboot=echo Booting from network ...; " \
+ "run netargs; " \
+ "tftp ${loadaddr} ${serverip}:${tftpfilename}; " \
+ "bootm ${loadaddr}\0" \
+ "resetenv=nand erase e0000 20000\0"\
+
+#define CONFIG_BOOTCOMMAND \
+ "run nandboot"
+
+#define CONFIG_AUTO_COMPLETE
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "DIG297# "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
+ /* works on */
+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
+ 0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
+ /* load address */
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE boot_flash_base
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_ENV_IS_IN_NAND
+#define SMNAND_ENV_OFFSET 0x0E0000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_I2C
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
/*
#include "mv-common.h"
#undef CONFIG_ARCH_MISC_INIT
+
/*
* Environment variables configurations
*/
/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* Based on original Kirkwood support which is
* (C) Copyright 2009
#define CONFIG_MACH_TYPE MACH_TYPE_HARMONY
#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
+#define CONFIG_BOARD_EARLY_INIT_F
#endif /* __CONFIG_H */
*/
#define CONFIG_TWL4030_POWER 1
-/* Environment information */
-#define CONFIG_BOOTCOMMAND \
- "mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0"
-
#define CONFIG_BOOTDELAY 3
#define CONFIG_EXTRA_ENV_SETTINGS \
- "usbtty=cdc_acm\0"
+ "usbtty=cdc_acm\0" \
+ "loadaddr=0x82000000\0" \
+ "usbtty=cdc_acm\0" \
+ "console=ttyS2,115200n8\0" \
+ "mpurate=500\0" \
+ "vram=12M\0" \
+ "dvimode=1024x768MR-16@60\0" \
+ "defaultdisplay=dvi\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "nandroot=/dev/mtdblock4 rw\0" \
+ "nandrootfstype=jffs2\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "nandboot=echo Booting from onenand ...; " \
+ "run nandargs; " \
+ "onenand read ${loadaddr} 280000 400000; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc rescan ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run nandboot; " \
+ "fi; " \
+ "fi; " \
+ "else run nandboot; fi"
#define CONFIG_AUTO_COMPLETE 1
*/
#define CONFIG_TWL4030_POWER 1
-/* Environment information */
-#define CONFIG_BOOTCOMMAND \
- "mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0"
-
#define CONFIG_BOOTDELAY 3
#define CONFIG_EXTRA_ENV_SETTINGS \
- "usbtty=cdc_acm\0"
+ "usbtty=cdc_acm\0" \
+ "loadaddr=0x82000000\0" \
+ "usbtty=cdc_acm\0" \
+ "console=ttyS2,115200n8\0" \
+ "mpurate=500\0" \
+ "vram=12M\0" \
+ "dvimode=1024x768MR-16@60\0" \
+ "defaultdisplay=dvi\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "nandroot=/dev/mtdblock4 rw\0" \
+ "nandrootfstype=jffs2\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "nandboot=echo Booting from onenand ...; " \
+ "run nandargs; " \
+ "onenand read ${loadaddr} 280000 400000; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc rescan ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run nandboot; " \
+ "fi; " \
+ "fi; " \
+ "else run nandboot; fi"
#define CONFIG_AUTO_COMPLETE 1
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
/*
* I2C bus
*/
+#define CONFIG_I2C_MV 1
+#define CONFIG_MV_I2C_REG 0x40301680
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_SYS_I2C_SLAVE 0xfe
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_TEXT_BASE 0x97800000
+
#define CONFIG_L2_OFF
#include <asm/arch/imx-regs.h>
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_OF_LIBFDT
+#define CONFIG_SYS_BOOTMAPSZ 0x800000
+
#endif
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_OF_LIBFDT
+#define CONFIG_SYS_BOOTMAPSZ 0x800000
+
#endif /* __CONFIG_H */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
#define PHYS_SDRAM_2 0x08000000 /* SDR-SDRAM BANK #2*/
#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+/* The IPL loads us at 0, tell so to u-boot. Put stack pointer 1M into RAM */
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + (1<<20))
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_OMAP_HSMMC 1
#define CONFIG_DOS_PARTITION 1
+/* Status LED */
+#define CONFIG_STATUS_LED 1
+#define CONFIG_BOARD_SPECIFIC_LED 1
+#define STATUS_LED_BIT 0x01
+#define STATUS_LED_STATE STATUS_LED_ON
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT1 0x02
+#define STATUS_LED_STATE1 STATUS_LED_ON
+#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BOOT STATUS_LED_BIT
+#define STATUS_LED_GREEN STATUS_LED_BIT1
+
/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR 1
#define CONFIG_USB_TTY 1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+/* USB EHCI */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_USB_STORAGE /* USB storage support */
#define CONFIG_CMD_NAND /* NAND support */
+#define CONFIG_CMD_LED /* LED support */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
"loadaddr=0x82000000\0" \
"usbtty=cdc_acm\0" \
"console=ttyS2,115200n8\0" \
- "mpurate=500\0" \
+ "mpurate=auto\0" \
"vram=12M\0" \
"dvimode=1024x768MR-16@60\0" \
"defaultdisplay=dvi\0" \
"omapdss.def_disp=${defaultdisplay} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source ${loadaddr}\0" \
+ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t $loadaddr $filesize\0" \
"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run nandboot; " \
- "fi; " \
- "fi; " \
- "else run nandboot; fi"
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "run importbootenv;" \
+ "fi;" \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loaduimage; then " \
+ "run mmcboot;" \
+ "fi;" \
+ "fi;" \
+ "run nandboot;" \
#define CONFIG_AUTO_COMPLETE 1
/*
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_SYS_FLASH_BASE boot_flash_base
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
-#define CONFIG_ENV_OFFSET boot_flash_off
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
-
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_SYS_FLASH_BASE boot_flash_base
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#elif defined(CONFIG_CMD_ONENAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
+#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
+#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+
#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_OMAP_GPMC
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#elif defined(CONFIG_CMD_ONENAND)
#define CONFIG_ENV_IS_IN_ONENAND 1
+#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
#endif
-#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
-#define CONFIG_ENV_OFFSET boot_flash_off
-#define CONFIG_ENV_ADDR boot_flash_env_addr
-
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
/*
* Support for relocation
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_SYS_FLASH_BASE boot_flash_base
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
-#define CONFIG_ENV_OFFSET boot_flash_off
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
-
#if defined(CONFIG_CMD_NET)
/*----------------------------------------------------------------------------
* SMSC9211 Ethernet from SMSC9118 family
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_SYS_FLASH_BASE boot_flash_base
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_ENV_IS_IN_NAND 1
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
-#define CONFIG_ENV_OFFSET boot_flash_off
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
-
#endif /* __CONFIG_H */
* - rest for filesystem
*/
-/*--------------------------------------------------------------------------*/
-
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_SYS_FLASH_BASE boot_flash_base
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
-#define CONFIG_ENV_OFFSET boot_flash_off
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_SYS_FLASH_BASE boot_flash_base
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_ENV_IS_IN_NAND 1
#define SMNAND_ENV_OFFSET 0x0c0000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
-#define CONFIG_ENV_OFFSET boot_flash_off
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
-
#endif /* __CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
#define CONFIG_SYS_MX31_UART1 1
#define CONFIG_MXC_GPIO
+#define CONFIG_HW_WATCHDOG
#define CONFIG_MXC_SPI
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
+#define CONFIG_BOARD_EARLY_INIT_F
#endif /* __CONFIG_H */
#define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */
#define CONFIG_L2_OFF /* No L2 cache */
+#define CONFIG_ENABLE_CORTEXA9 /* enable CPU (A9 complex) */
+
#include <asm/arch/tegra2.h> /* get chip and board defs */
/*
/*
* I2C bus
*/
+#define CONFIG_I2C_MV 1
+#define CONFIG_MV_I2C_REG 0x40301680
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_SYS_I2C_SLAVE 0xfe
#ifndef __FTPMU010_H
#define __FTPMU010_H
+#ifndef __ASSEMBLY__
struct ftpmu010 {
unsigned int IDNMBR0; /* 0x00 */
unsigned int reserved0; /* 0x04 */
unsigned int ED0_RACC; /* 0xD4 */
unsigned int ED1_RACC; /* 0xD8 */
};
+#endif /* __ASSEMBLY__ */
/*
* ID Number 0 Register
/*
* Multi-Function Port Setting Register
*/
+#define FTPMU010_MFPSR_DEBUGSEL (1 << 17)
+#define FTPMU010_MFPSR_DMA0PINSEL (1 << 16)
+#define FTPMU010_MFPSR_DMA1PINSEL (1 << 15)
#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14)
#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13)
+#define FTPMU010_MFPSR_PWM1PINSEL (1 << 11)
+#define FTPMU010_MFPSR_PWM0PINSEL (1 << 10)
+#define FTPMU010_MFPSR_IRDACLKSEL (1 << 9)
+#define FTPMU010_MFPSR_UARTCLKSEL (1 << 8)
+#define FTPMU010_MFPSR_SSPCLKSEL (1 << 6)
+#define FTPMU010_MFPSR_I2SCLKSEL (1 << 5)
+#define FTPMU010_MFPSR_AC97CLKSEL (1 << 4)
#define FTPMU010_MFPSR_AC97PINSEL (1 << 3)
+#define FTPMU010_MFPSR_TRIAHBDIS (1 << 1)
+#define FTPMU010_MFPSR_TRIAHBDBG (1 << 0)
/*
* PLL/DLL Control Register 0
+ * Note:
+ * 1. FTPMU010_PDLLCR0_HCLKOUTDIS:
+ * Datasheet indicated it starts at bit #21 which was wrong.
+ * 2. FTPMU010_PDLLCR0_DLLFRAG:
+ * Datasheet indicated it has 2 bit which was wrong.
*/
-#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) >> 20) & 0xf)
-#define FTPMU010_PDLLCR0_DLLFRAG (1 << 19)
+#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20)
+#define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19)
#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18)
#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17)
#define FTPMU010_PDLLCR0_DLLDIS (1 << 16)
-#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) >> 3) & 0x1ff)
+#define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12)
+#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3)
#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2)
#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1)
#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0)
+/*
+ * SDRAM Signal Hold Time Control Register
+ */
+#define FTPMU010_SDRAMHTC_RCLK_DLY(x) (((x) & 0xf) << 28)
+#define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x) (((x) & 0xf) << 24)
+#define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x) (((x) & 0xf) << 20)
+#define FTPMU010_SDRAMHTC_EBICTRL_DCSR (1 << 18)
+#define FTPMU010_SDRAMHTC_EBIDATA_DCSR (1 << 17)
+#define FTPMU010_SDRAMHTC_SDRAMCS_DCSR (1 << 16)
+#define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR (1 << 15)
+#define FTPMU010_SDRAMHTC_CKE_DCSR (1 << 14)
+#define FTPMU010_SDRAMHTC_DQM_DCSR (1 << 13)
+#define FTPMU010_SDRAMHTC_SDCLK_DCSR (1 << 12)
+
+#ifndef __ASSEMBLY__
+void ftpmu010_32768osc_enable(void);
+void ftpmu010_dlldis_disable(void);
+void ftpmu010_sdram_clk_disable(unsigned int cr0);
+#endif
+
+#ifdef __ASSEMBLY__
+#define FTPMU010_IDNMBR0 0x00
+#define FTPMU010_reserved0 0x04
+#define FTPMU010_OSCC 0x08
+#define FTPMU010_PMODE 0x0C
+#define FTPMU010_PMCR 0x10
+#define FTPMU010_PED 0x14
+#define FTPMU010_PEDSR 0x18
+#define FTPMU010_reserved1 0x1C
+#define FTPMU010_PMSR 0x20
+#define FTPMU010_PGSR 0x24
+#define FTPMU010_MFPSR 0x28
+#define FTPMU010_MISC 0x2C
+#define FTPMU010_PDLLCR0 0x30
+#define FTPMU010_PDLLCR1 0x34
+#define FTPMU010_AHBMCLKOFF 0x38
+#define FTPMU010_APBMCLKOFF 0x3C
+#define FTPMU010_DCSRCR0 0x40
+#define FTPMU010_DCSRCR1 0x44
+#define FTPMU010_DCSRCR2 0x48
+#define FTPMU010_SDRAMHTC 0x4C
+#define FTPMU010_PSPR0 0x50
+#define FTPMU010_PSPR1 0x54
+#define FTPMU010_PSPR2 0x58
+#define FTPMU010_PSPR3 0x5C
+#define FTPMU010_PSPR4 0x60
+#define FTPMU010_PSPR5 0x64
+#define FTPMU010_PSPR6 0x68
+#define FTPMU010_PSPR7 0x6C
+#define FTPMU010_PSPR8 0x70
+#define FTPMU010_PSPR9 0x74
+#define FTPMU010_PSPR10 0x78
+#define FTPMU010_PSPR11 0x7C
+#define FTPMU010_PSPR12 0x80
+#define FTPMU010_PSPR13 0x84
+#define FTPMU010_PSPR14 0x88
+#define FTPMU010_PSPR15 0x8C
+#define FTPMU010_AHBDMA_RACCS 0x90
+#define FTPMU010_reserved2 0x94
+#define FTPMU010_reserved3 0x98
+#define FTPMU010_JSS 0x9C
+#define FTPMU010_CFC_RACC 0xA0
+#define FTPMU010_SSP1_RACC 0xA4
+#define FTPMU010_UART1TX_RACC 0xA8
+#define FTPMU010_UART1RX_RACC 0xAC
+#define FTPMU010_UART2TX_RACC 0xB0
+#define FTPMU010_UART2RX_RACC 0xB4
+#define FTPMU010_SDC_RACC 0xB8
+#define FTPMU010_I2SAC97_RACC 0xBC
+#define FTPMU010_IRDATX_RACC 0xC0
+#define FTPMU010_reserved4 0xC4
+#define FTPMU010_USBD_RACC 0xC8
+#define FTPMU010_IRDARX_RACC 0xCC
+#define FTPMU010_IRDA_RACC 0xD0
+#define FTPMU010_ED0_RACC 0xD4
+#define FTPMU010_ED1_RACC 0xD8
+#endif /* __ASSEMBLY__ */
+
#endif /* __FTPMU010_H */
__got_end = .;
+ _end = .;
+
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
*(.dynsym)
}
+ _end = .;
+
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
*(.bss)
*(.dynsym)
}
+ _end = .;
+
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
*(.bss)
#include <common.h>
#include <nand.h>
-#ifdef CONFIG_MX31
-#include <asm/arch/mx31-regs.h>
-#else
#include <asm/arch/imx-regs.h>
-#endif
#include <asm/io.h>
#include <fsl_nfc.h>
projects / platform / kernel / u-boot.git / commitdiff