endif
KBUILD_CFLAGS += $(call cc-option,-Wno-format-nonliteral)
+KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member)
+
ifeq ($(cc-name),clang)
KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier)
KBUILD_CFLAGS += $(call cc-disable-warning, gnu)
-KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member)
KBUILD_CFLAGS += $(call cc-option, -fcatch-undefined-behavior)
endif
endif
endif
+config GIC_V3_ITS
+ bool "ARM GICV3 ITS"
+ help
+ ARM GICV3 Interrupt translation service (ITS).
+ Basic support for programming locality specific peripheral
+ interrupts (LPI) configuration tables and enable LPI tables.
+ LPI configuration table can be used by u-boot or Linux.
+ ARM GICV3 has limitation, once the LPI table is enabled, LPI
+ configuration table can not be re-programmed, unless GICV3 reset.
+
config STATIC_RELA
bool
default y if ARM64 && !POSITION_INDEPENDENT
;
}
+void __noreturn psci_system_reset2(u32 reset_level, u32 cookie)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = ARM_PSCI_0_2_FN64_SYSTEM_RESET2;
+ regs.regs[1] = PSCI_RESET2_TYPE_VENDOR | reset_level;
+ regs.regs[2] = cookie;
+ if (use_smc_for_psci)
+ smc_call(®s);
+ else
+ hvc_call(®s);
+
+ while (1)
+ ;
+}
+
void __noreturn psci_system_off(void)
{
struct pt_regs regs;
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom.
+ */
+
+#ifndef __GIC_V3_H__
+#define __GIC_V3_H__
+
+#define GICR_CTLR_ENABLE_LPIS BIT(0)
+#define GICR_CTLR_RWP BIT(3)
+
+#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
+
+#define GICR_WAKER_PROCESSORSLEEP BIT(1)
+#define GICR_WAKER_CHILDRENASLEEP BIT(2)
+
+#define GIC_BASER_CACHE_NCNB 0ULL
+#define GIC_BASER_CACHE_SAMEASINNER 0ULL
+#define GIC_BASER_CACHE_NC 1ULL
+#define GIC_BASER_CACHE_RAWT 2ULL
+#define GIC_BASER_CACHE_RAWB 3ULL
+#define GIC_BASER_CACHE_WAWT 4ULL
+#define GIC_BASER_CACHE_WAWB 5ULL
+#define GIC_BASER_CACHE_RAWAWT 6ULL
+#define GIC_BASER_CACHE_RAWAWB 7ULL
+#define GIC_BASER_CACHE_MASK 7ULL
+#define GIC_BASER_NONSHAREABLE 0ULL
+#define GIC_BASER_INNERSHAREABLE 1ULL
+#define GIC_BASER_OUTERSHAREABLE 2ULL
+#define GIC_BASER_SHAREABILITY_MASK 3ULL
+
+#define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \
+ (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
+
+#define GIC_BASER_SHAREABILITY(reg, type) \
+ (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
+
+/* encode a size field of width @w containing @n - 1 units */
+#define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) &\
+ GENMASK_ULL(((w) - 1), 0))
+
+#define GICR_PROPBASER_SHAREABILITY_SHIFT (10)
+#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7)
+#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56)
+#define GICR_PROPBASER_SHAREABILITY_MASK \
+ GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK)
+#define GICR_PROPBASER_INNER_CACHEABILITY_MASK \
+ GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
+#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \
+ GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
+#define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK
+
+#define GICR_PROPBASER_INNERSHAREABLE \
+ GIC_BASER_SHAREABILITY(GICR_PROPBASER, INNERSHAREABLE)
+
+#define GICR_PROPBASER_NCNB \
+ GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, NCNB)
+#define GICR_PROPBASER_NC \
+ GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, NC)
+#define GICR_PROPBASER_RAWT \
+ GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWT)
+#define GICR_PROPBASER_RAWB \
+ GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWB)
+#define GICR_PROPBASER_WAWT \
+ GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WAWT)
+#define GICR_PROPBASER_WAWB \
+ GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WAWB)
+#define GICR_PROPBASER_RAWAWT \
+ GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWAWT)
+#define GICR_PROPBASER_RAWAWB \
+ GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWAWB)
+
+#define GICR_PROPBASER_IDBITS_MASK (0x1f)
+#define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12))
+#define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16))
+
+#define GICR_PENDBASER_SHAREABILITY_SHIFT (10)
+#define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7)
+#define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56)
+#define GICR_PENDBASER_SHAREABILITY_MASK \
+ GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK)
+#define GICR_PENDBASER_INNER_CACHEABILITY_MASK \
+ GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK)
+#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \
+ GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK)
+#define GICR_PENDBASER_CACHEABILITY_MASK \
+ GICR_PENDBASER_INNER_CACHEABILITY_MASK
+
+#define GICR_PENDBASER_INNERSHAREABLE \
+ GIC_BASER_SHAREABILITY(GICR_PENDBASER, INNERSHAREABLE)
+
+#define GICR_PENDBASER_NCNB \
+ GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, NCNB)
+#define GICR_PENDBASER_NC \
+ GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, NC)
+#define GICR_PENDBASER_RAWT \
+ GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RAWT)
+#define GICR_PENDBASER_RAWB \
+ GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RAWB)
+#define GICR_PENDBASER_WAWT \
+ GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WAWT)
+#define GICR_PENDBASER_WAWB \
+ GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WAWB)
+#define GICR_PENDBASER_RAWAWT \
+ GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RAWAWT)
+#define GICR_PENDBASER_RAWAWB \
+ GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RAWAWB)
+
+#define GICR_PENDBASER_PTZ BIT_ULL(62)
+
+#define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */
+
+#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
+#define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1)
+#define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32)
+
+/* Message based interrupts support */
+#define GICD_TYPER_MBIS BIT(16)
+/* LPI support */
+#define GICD_TYPER_LPIS BIT(17)
+#define GICD_TYPER_RSS BIT(26)
+
+#define GIC_REDISTRIBUTOR_OFFSET 0x20000
+
+#ifdef CONFIG_GIC_V3_ITS
+int gic_lpi_tables_init(u64 base, u32 max_redist);
+#else
+int gic_lpi_tables_init(u64 base, u32 max_redist)
+{
+ return 0;
+}
+#endif /* CONFIG_GIC_V3_ITS */
+
+#endif /* __GIC_V3_H__ */
#define ARM_PSCI_0_2_FN64_AFFINITY_INFO ARM_PSCI_0_2_FN64(4)
#define ARM_PSCI_0_2_FN64_MIGRATE ARM_PSCI_0_2_FN64(5)
#define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN64(7)
+#define ARM_PSCI_0_2_FN64_SYSTEM_RESET2 ARM_PSCI_0_2_FN64(18)
/* PSCI 1.0 interface */
#define ARM_PSCI_1_0_FN_PSCI_FEATURES ARM_PSCI_0_2_FN(10)
#define PSCI_AFFINITY_LEVEL_OFF 1
#define PSCI_AFFINITY_LEVEL_ON_PENDING 2
+#define PSCI_RESET2_TYPE_VENDOR_SHIFT 31
+#define PSCI_RESET2_TYPE_VENDOR BIT(PSCI_RESET2_TYPE_VENDOR_SHIFT)
+
#ifndef __ASSEMBLY__
#include <asm/types.h>
void smc_call(struct pt_regs *args);
void __noreturn psci_system_reset(void);
+void __noreturn psci_system_reset2(u32 reset_level, u32 cookie);
void __noreturn psci_system_off(void);
#ifdef CONFIG_ARMV8_PSCI
ifneq ($(CONFIG_GICV2)$(CONFIG_GICV3),)
obj-y += gic_64.o
endif
+obj-$(CONFIG_GIC_V3_ITS) += gic-v3-its.o
obj-y += interrupts_64.o
else
obj-y += interrupts.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Broadcom.
+ */
+#include <common.h>
+#include <asm/gic.h>
+#include <asm/gic-v3.h>
+#include <asm/io.h>
+
+static u32 lpi_id_bits;
+
+#define LPI_NRBITS lpi_id_bits
+#define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
+#define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
+
+/*
+ * Program the GIC LPI configuration tables for all
+ * the re-distributors and enable the LPI table
+ * base: Configuration table address
+ * num_redist: number of redistributors
+ */
+int gic_lpi_tables_init(u64 base, u32 num_redist)
+{
+ u32 gicd_typer;
+ u64 val;
+ u64 tmp;
+ int i;
+ u64 redist_lpi_base;
+ u64 pend_base = GICR_BASE + GICR_PENDBASER;
+
+ gicd_typer = readl(GICD_BASE + GICD_TYPER);
+
+ /* GIC support for Locality specific peripheral interrupts (LPI's) */
+ if (!(gicd_typer & GICD_TYPER_LPIS)) {
+ pr_err("GIC implementation does not support LPI's\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Check for LPI is disabled for all the redistributors.
+ * Once the LPI table is enabled, can not program the
+ * LPI configuration tables again, unless the GIC is reset.
+ */
+ for (i = 0; i < num_redist; i++) {
+ u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
+
+ if ((readl((uintptr_t)(GICR_BASE + offset))) &
+ GICR_CTLR_ENABLE_LPIS) {
+ pr_err("Re-Distributor %d LPI is already enabled\n",
+ i);
+ return -EINVAL;
+ }
+ }
+
+ /* lpi_id_bits to get LPI_PENDBASE_SZ and LPi_PROPBASE_SZ */
+ lpi_id_bits = min_t(u32, GICD_TYPER_ID_BITS(gicd_typer),
+ ITS_MAX_LPI_NRBITS);
+
+ /* Set PropBase */
+ val = (base |
+ GICR_PROPBASER_INNERSHAREABLE |
+ GICR_PROPBASER_RAWAWB |
+ ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
+
+ writeq(val, (GICR_BASE + GICR_PROPBASER));
+ tmp = readl(GICR_BASE + GICR_PROPBASER);
+ if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
+ if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
+ val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
+ GICR_PROPBASER_CACHEABILITY_MASK);
+ val |= GICR_PROPBASER_NC;
+ writeq(val, (GICR_BASE + GICR_PROPBASER));
+ }
+ }
+
+ redist_lpi_base = base + LPI_PROPBASE_SZ;
+
+ for (i = 0; i < num_redist; i++) {
+ u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
+
+ val = ((redist_lpi_base + (i * LPI_PENDBASE_SZ)) |
+ GICR_PENDBASER_INNERSHAREABLE |
+ GICR_PENDBASER_RAWAWB);
+
+ writeq(val, (uintptr_t)(pend_base + offset));
+ tmp = readq((uintptr_t)(pend_base + offset));
+ if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
+ val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
+ GICR_PENDBASER_CACHEABILITY_MASK);
+ val |= GICR_PENDBASER_NC;
+ writeq(val, (uintptr_t)(pend_base + offset));
+ }
+
+ /* Enable LPI for the redistributor */
+ writel(GICR_CTLR_ENABLE_LPIS, (uintptr_t)(GICR_BASE + offset));
+ }
+
+ return 0;
+}
+
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
if (setclear) {
/* Enable Ethernet pins */
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
- struct fec_info_s *info = (struct fec_info_s *) dev->priv;
gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+ u32 fec0_base;
+
+ if (fec_get_base_addr(0, &fec0_base))
+ return -1;
if (setclear) {
/* Enable Ethernet pins */
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ if (info->iobase == fec0_base) {
setbits_be16(&gpio->par_feci2c, 0x0f00);
setbits_8(&gpio->par_fec0hl, 0xc0);
} else {
setbits_8(&gpio->par_fec1hl, 0xc0);
}
} else {
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ if (info->iobase == fec0_base) {
clrbits_be16(&gpio->par_feci2c, 0x0f00);
clrbits_8(&gpio->par_fec0hl, 0xc0);
} else {
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
if (setclear) {
MCFGPIO_PASPAR |= 0x0F00;
* create a board-specific function called:
* int board_eth_init(bd_t *bis)
*/
-
int cpu_eth_init(bd_t *bis)
{
return mcffec_initialize(bis);
#include <asm/immap.h>
#include <asm/io.h>
-#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_MCFFEC)
#include <config.h>
#include <net.h>
#include <asm/fec.h>
int cpu_init_r(void)
{
#ifdef CONFIG_MCFFEC
+ u32 fec_mii_base0, fec_mii_base1;
ccm_t *ccm = (ccm_t *) MMAP_CCM;
#endif
#ifdef CONFIG_MCFRTC
#endif
#ifdef CONFIG_MCFFEC
- if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
+ fec_get_mii_base(0, &fec_mii_base0);
+ fec_get_mii_base(1, &fec_mii_base1);
+
+ if (fec_mii_base0 != fec_mii_base1)
setbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
else
clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+ u32 fec0_base;
+
+ if (fec_get_base_addr(0, &fec0_base))
+ return -1;
if (setclear) {
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ if (info->iobase == fec0_base) {
setbits_8(&gpio->par_fec,
GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
setbits_8(&gpio->par_feci2c,
GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1);
}
} else {
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ if (info->iobase == fec0_base) {
clrbits_8(&gpio->par_fec,
GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK);
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-#ifdef CONFIG_MCF5445x
- struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+ u32 fec0_base;
+
+ if (fec_get_base_addr(0, &fec0_base))
+ return -1;
+#ifdef CONFIG_MCF5445x
if (setclear) {
#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+ if (info->iobase == fec0_base)
setbits_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_MDC0_MDC0 |
GPIO_PAR_FECI2C_MDIO0_MDIO0);
GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
#endif
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+ if (info->iobase == fec0_base)
setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
else
setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
clrbits_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ if (info->iobase == fec0_base) {
#ifdef CONFIG_SYS_FEC_FULL_MII
setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
#else
return 0;
}
#endif
-
#if defined(CONFIG_CMD_NET)
#include <config.h>
#include <net.h>
+#include <asm/fec.h>
#include <asm/fsl_mcdmafec.h>
#endif
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
+ u32 fec0_base;
+
+ if (fec_get_base_addr(0, &fec0_base))
+ return -1;
if (setclear) {
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+ if (info->iobase == fec0_base)
setbits_be16(&gpio->par_feci2cirq, 0xf000);
else
setbits_be16(&gpio->par_feci2cirq, 0x0fc0);
} else {
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+ if (info->iobase == fec0_base)
clrbits_be16(&gpio->par_feci2cirq, 0xf000);
else
clrbits_be16(&gpio->par_feci2cirq, 0x0fc0);
status = "okay";
};
+&fec0 {
+ status = "okay";
+};
status = "okay";
};
+&fec0 {
+ status = "okay";
+};
status = "okay";
};
+&fec0 {
+ status = "okay";
+};
status = "okay";
};
+&fec0 {
+ status = "okay";
+};
status = "okay";
};
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
status = "okay";
};
+&fec0 {
+ status = "okay";
+};
status = "okay";
};
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
status = "okay";
};
+&fec0 {
+ status = "okay";
+};
status = "okay";
};
+&fec0 {
+ status = "okay";
+};
status = "okay";
};
+&fec0 {
+ status = "okay";
+};
&dspi0 {
status = "okay";
};
+
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
&dspi0 {
status = "okay";
};
+
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
&dspi0 {
status = "okay";
};
+
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
&dspi0 {
status = "okay";
};
+
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
&dspi0 {
status = "okay";
};
+
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
&dspi0 {
status = "okay";
};
+
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
&dspi0 {
status = "okay";
};
+
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
&dspi0 {
status = "okay";
};
+
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
&dspi0 {
status = "okay";
};
+
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
&dspi0 {
status = "okay";
};
+
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
&dspi0 {
status = "okay";
};
+
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
status = "okay";
};
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
&dspi0 {
status = "okay";
};
+
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
compatible = "fsl,M5475AFE";
};
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
compatible = "fsl,M5475BFE";
};
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
compatible = "fsl,M5475CFE";
};
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
compatible = "fsl,M5475DFE";
};
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
compatible = "fsl,M5475EFE";
};
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
compatible = "fsl,M5475FFE";
};
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
compatible = "fsl,M5475GFE";
};
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
};
};
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
};
};
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
};
};
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
};
};
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
};
};
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
};
};
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
};
};
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
};
};
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
status = "okay";
};
+&fec0 {
+ status = "okay";
+};
status = "okay";
};
+&fec0 {
+ status = "okay";
+};
status = "okay";
};
+&fec0 {
+ status = "okay";
+};
aliases {
serial0 = &uart0;
+ fec0 = &fec0;
};
soc {
reg = <0xfc068000 0x40>;
status = "disabled";
};
+
+ fec0: ethernet@fc030000 {
+ compatible = "fsl,mcf-fec";
+ reg = <0xfc030000 0x400>;
+ mii-base = <0>;
+ max-speed = <100>;
+ timeout-loop = <50000>;
+ status = "disabled";
+ };
};
};
aliases {
serial0 = &uart0;
+ fec0 = &fec0;
};
soc {
reg = <0x280 0x40>;
status = "disabled";
};
+
+ fec0: ethernet@1000 {
+ compatible = "fsl,mcf-fec";
+ #address-cells=<2>;
+ #size-cells=<1>;
+ reg = <0x1000 0x400>;
+ mii-base = <0>;
+ max-speed = <100>;
+ timeout-loop = <50000>;
+ status = "disabled";
+ };
};
};
};
aliases {
serial0 = &uart0;
+ fec0 = &fec0;
};
soc {
reg = <0x280 0x40>;
status = "disabled";
};
+
+ fec0: ethernet@1000 {
+ compatible = "fsl,mcf-fec";
+ reg = <0x1000 0x400>;
+ mii-base = <0>;
+ max-speed = <100>;
+ timeout-loop = <50000>;
+ status = "disabled";
+ };
};
};
};
aliases {
serial0 = &uart0;
+ fec0 = &fec0;
};
soc {
reg = <0x140 0x40>;
status = "disabled";
};
+
+ fec0: ethernet@840 {
+ compatible = "fsl,mcf-fec";
+ reg = <0x840 0x400>;
+ mii-base = <0>;
+ max-speed = <100>;
+ timeout-loop = <50000>;
+ status = "disabled";
+ };
};
};
};
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 201
8 Angelo Dureghello <angelo@sysam.it>
+ * Copyright (C) 201
9 Angelo Dureghello <angelo@sysam.it>
*/
/ {
aliases {
serial0 = &uart0;
+ fec0 = &fec0;
+ fec1 = &fec1;
};
soc {
reg = <0x280 0x40>;
status = "disabled";
};
+
+ fec0: ethernet@1000 {
+ compatible = "fsl,mcf-fec";
+ reg = <0x1000 0x800>;
+ max-speed = <100>;
+ phy-addr = <(-1)>;
+ timeout-loop = <50000>;
+ status = "disabled";
+ };
+
+ fec1: ethernet@1800 {
+ compatible = "fsl,mcf-fec";
+ reg = <0x1800 0x800>;
+ mii-base = <0>;
+ max-speed = <100>;
+ timeout-loop = <50000>;
+ status = "disabled";
+ };
};
};
};
aliases {
serial0 = &uart0;
+ fec0 = &fec0;
};
soc {
reg = <0x280 0x40>;
status = "disabled";
};
+
+ fec0: ethernet@1000 {
+ compatible = "fsl,mcf-fec";
+ reg = <0x1000 0x800>;
+ mii-base = <0>;
+ max-speed = <100>;
+ timeout-loop = <50000>;
+ status = "disabled";
+ };
};
};
};
aliases {
serial0 = &uart0;
spi0 = &dspi0;
+ fec0 = &fec0;
+ fec1 = &fec1;
};
soc {
spi-mode = <0>;
status = "disabled";
};
+
+ fec0: ethernet@fc030000 {
+ compatible = "fsl,mcf-fec";
+ reg = <0xfc030000 0x200>;
+ mii-base = <0>;
+ max-speed = <100>;
+ phy-addr = <(-1)>;
+ timeout-loop = <50000>;
+ status = "disabled";
+ };
+
+ fec1: ethernet@fc034000 {
+ compatible = "fsl,mcf-fec";
+ reg = <0xfc034000 0x800>;
+ mii-base = <1>;
+ max-speed = <100>;
+ timeout-loop = <50000>;
+ status = "disabled";
+ };
};
};
aliases {
serial0 = &uart0;
+ fec0 = &fec0;
};
soc {
reg = <0xfc068000 0x40>;
status = "disabled";
};
+
+ fec0: ethernet@fc030000 {
+ compatible = "fsl,mcf-fec";
+ reg = <0xfc030000 0x800>;
+ mii-base = <0>;
+ max-speed = <100>;
+ timeout-loop = <50000>;
+ status = "disabled";
+ };
};
};
aliases {
serial0 = &uart0;
+ fec0 = &fec0;
};
soc {
reg = <0xfc068000 0x40>;
status = "disabled";
};
+
+ fec0: ethernet@fc030000 {
+ compatible = "fsl,mcf-fec";
+ reg = <0xfc030000 0x400>;
+ mii-base = <0>;
+ max-speed = <100>;
+ timeout-loop = <50000>;
+ status = "disabled";
+ };
};
};
aliases {
serial0 = &uart0;
spi0 = &dspi0;
+ fec0 = &fec0;
+ fec1 = &fec1;
};
soc {
spi-mode = <0>;
status = "disabled";
};
+
+ fec0: ethernet@fc0d4000 {
+ compatible = "fsl,mcf-fec";
+ reg = <0xfc0d4000 0x4000>;
+ mii-base = <0>;
+ max-speed = <100>;
+ timeout-loop = <50000>;
+ status = "disabled";
+ };
+
+ fec1: ethernet@fc0d8000 {
+ compatible = "fsl,mcf-fec";
+ reg = <0xfc0d8000 0x4000>;
+ mii-base = <1>;
+ max-speed = <100>;
+ timeout-loop = <50000>;
+ status = "disabled";
+ };
};
};
aliases {
serial0 = &uart0;
spi0 = &dspi0;
+ fec0 = &fec0;
+ fec1 = &fec1;
};
soc {
spi-mode = <0>;
status = "disabled";
};
+
+ fec0: ethernet@fc030000 {
+ compatible = "fsl,mcf-fec";
+ reg = <0xfc030000 0x4000>;
+ mii-base = <0>;
+ max-speed = <100>;
+ timeout-loop = <50000>;
+ status = "disabled";
+ };
+
+ fec1: ethernet@fc034000 {
+ compatible = "fsl,mcf-fec";
+ reg = <0xfc034000 0x4000>;
+ mii-base = <1>;
+ max-speed = <100>;
+ timeout-loop = <50000>;
+ status = "disabled";
+ };
};
};
* no UARTS.
*/
spi0 = &dspi0;
+ fec0 = &fec0;
+ fec1 = &fec1;
};
soc {
spi-mode = <0>;
status = "disabled";
};
+
+ fec0: ethernet@9000 {
+ compatible = "fsl,mcf-dma-fec";
+ reg = <0x9000 0x800>;
+ mii-base = <0>;
+ max-speed = <100>;
+ timeout-loop = <50000>;
+ rx-task = <0>;
+ tx-task = <1>;
+ rx-piority = <6>;
+ tx-piority = <7>;
+ rx-init = <16>;
+ tx-init = <17>;
+ status = "disabled";
+ };
+
+ fec1: ethernet@9800 {
+ compatible = "fsl,mcf-dma-fec";
+ reg = <0x9800 0x800>;
+ mii-base = <1>;
+ max-speed = <100>;
+ timeout-loop = <50000>;
+ rx-task = <2>;
+ tx-task = <3>;
+ rx-piority = <6>;
+ tx-piority = <7>;
+ rx-init = <30>;
+ tx-init = <31>;
+ status = "disabled";
+ };
};
};
};
reg = <1>;
};
};
+
+&fec0 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+ mii-base = <0>;
+};
int phyname_init;
cbd_t *rxbd; /* Rx BD */
cbd_t *txbd; /* Tx BD */
- uint rxIdx;
- uint txIdx;
+ uint rx_idx;
+ uint tx_idx;
char *txbuf;
int initialized;
- struct fec_info_s *next;
+ int to_loop;
+ struct mii_dev *bus;
};
#ifdef CONFIG_MCFFEC
#define FEC_RESET_DELAY 100
#define FEC_RX_TOUT 100
-int fecpin_setclear(struct eth_device *dev, int setclear);
+#ifdef CONFIG_MCF547x_8x
+typedef struct fec_info_dma fec_info_t;
+#define FEC_T fecdma_t
+#else
+typedef struct fec_info_s fec_info_t;
+#define FEC_T fec_t
+#endif
+
+int fecpin_setclear(fec_info_t *info, int setclear);
+int mii_discover_phy(fec_info_t *info);
+int fec_get_base_addr(int fec_idx, u32 *fec_iobase);
+int fec_get_mii_base(int fec_idx, u32 *mii_base);
#ifdef CONFIG_SYS_DISCOVER_PHY
void __mii_init(void);
uint mii_send(uint mii_cmd);
-int mii_discover_phy(struct eth_device *dev);
int mcffec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg);
int mcffec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
u16 value);
int phyname_init;
cbd_t *rxbd; /* Rx BD */
cbd_t *txbd; /* Tx BD */
- uint rxIdx;
- uint txIdx;
+ uint rx_idx;
+ uint tx_idx;
char *txbuf;
int initialized;
struct fec_info_dma *next;
-
- u16 rxTask; /* DMA receive Task Number */
- u16 txTask; /* DMA Transmit Task Number */
- u16 rxPri; /* DMA Receive Priority */
- u16 txPri; /* DMA Transmit Priority */
- u16 rxInit; /* DMA Receive Initiator */
- u16 txInit; /* DMA Transmit Initiator */
- u16 usedTbdIdx; /* next transmit BD to clean */
- u16 cleanTbdNum; /* the number of available transmit BDs */
+ u16 rx_task; /* DMA receive Task Number */
+ u16 tx_task; /* DMA Transmit Task Number */
+ u16 rx_pri; /* DMA Receive Priority */
+ u16 tx_pri; /* DMA Transmit Priority */
+ u16 rx_init; /* DMA Receive Initiator */
+ u16 tx_init; /* DMA Transmit Initiator */
+ u16 used_tbd_idx; /* next transmit BD to clean */
+ u16 clean_tbd_num; /* the number of available transmit BDs */
+ int to_loop;
+ struct mii_dev *bus;
};
/* Bit definitions and macros for IEVENT */
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
-#ifdef CONFIG_MCFPIT
-#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
-#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
-#define CONFIG_SYS_PIT_PRESCALE (6)
-#endif
-
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M520x */
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
-#ifdef CONFIG_MCFPIT
-#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
-#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
-#define CONFIG_SYS_PIT_PRESCALE (6)
-#endif
-
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M52277 */
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
-#ifdef CONFIG_MCFPIT
-#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
-#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
-#define CONFIG_SYS_PIT_PRESCALE (6)
-#endif
-
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M5235 */
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
-#ifdef CONFIG_MCFPIT
-#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
-#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
-#define CONFIG_SYS_PIT_PRESCALE (6)
-#endif
-
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M5301x */
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
-#ifdef CONFIG_MCFPIT
-#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
-#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
-#define CONFIG_SYS_PIT_PRESCALE (6)
-#endif
-
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M5329 && CONFIG_M5373 */
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
-#ifdef CONFIG_MCFPIT
-#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
-#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
-#define CONFIG_SYS_PIT_PRESCALE (6)
-#endif
-
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (192)
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
-#ifdef CONFIG_MCFPIT
-#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
-#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
-#define CONFIG_SYS_PIT_PRESCALE (6)
-#endif
-
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
obj-y += interrupts.o
obj-y += time.o
obj-y += traps.o
+obj-y += fec.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
+ */
+
+#include <common.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_MCFFEC) || defined(CONFIG_FSLDMAFEC)
+static int fec_get_node(int fec_idx)
+{
+ char fec_alias[5] = {"fec"};
+ const char *path;
+ int node;
+
+ if (fec_idx > 1) {
+ puts("Invalid MII base index");
+ return -ENOENT;
+ }
+
+ fec_alias[3] = fec_idx + '0';
+
+ path = fdt_get_alias(gd->fdt_blob, fec_alias);
+ if (!path) {
+ puts("Invalid MII path");
+ return -ENOENT;
+ }
+
+ node = fdt_path_offset(gd->fdt_blob, path);
+ if (node < 0)
+ return -ENOENT;
+
+ return node;
+}
+
+int fec_get_fdt_prop(int fec_idx, const char *prop, u32 *value)
+{
+ int node;
+ const u32 *val;
+
+ node = fec_get_node(fec_idx);
+ if (node < 0)
+ return node;
+
+ val = fdt_getprop(gd->fdt_blob, node, prop, NULL);
+ if (!val)
+ return -ENOENT;
+
+ *value = fdt32_to_cpu(*val);
+
+ return 0;
+}
+
+int fec_get_base_addr(int fec_idx, u32 *fec_iobase)
+{
+ int node;
+ fdt_size_t size;
+ fdt_addr_t addr;
+
+ node = fec_get_node(fec_idx);
+ if (node < 0)
+ return node;
+
+ addr = fdtdec_get_addr_size(gd->fdt_blob, node, "reg", &size);
+
+ *fec_iobase = (u32)addr;
+
+ return 0;
+}
+
+int fec_get_mii_base(int fec_idx, u32 *mii_base)
+{
+ return fec_get_fdt_prop(fec_idx, "mii-base", mii_base);
+}
+
+#endif //CONFIG_MCFFEC || CONFIG_FSLDMAFEC
#endif /* CONFIG_MCFTMR */
-#if defined(CONFIG_MCFPIT)
-#if !defined(CONFIG_SYS_PIT_BASE)
-# error "CONFIG_SYS_PIT_BASE not defined!"
-#endif
-
-static unsigned short lastinc;
-
-void __udelay(unsigned long usec)
-{
- volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_UDELAY_BASE);
- uint tmp;
-
- while (usec > 0) {
- if (usec > 65000)
- tmp = 65000;
- else
- tmp = usec;
- usec = usec - tmp;
-
- /* Set up TIMER 3 as timebase clock */
- timerp->pcsr = PIT_PCSR_OVW;
- timerp->pmr = 0;
- /* set period to 1 us */
- timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN;
-
- timerp->pmr = tmp;
- while (timerp->pcntr > 0) ;
- }
-}
-
-void timer_init(void)
-{
- volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE);
- timestamp = 0;
-
- /* Set up TIMER 4 as poll clock */
- timerp->pcsr = PIT_PCSR_OVW;
- timerp->pmr = lastinc = 0;
- timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN;
-
- return 0;
-}
-
-ulong get_timer(ulong base)
-{
- unsigned short now, diff;
- volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE);
-
- now = timerp->pcntr;
- diff = -(now - lastinc);
-
- timestamp += diff;
- lastinc = now;
- return timestamp - base;
-}
-
-void wait_ticks(unsigned long ticks)
-{
- u32 start = get_timer(0);
- while (get_timer(start) < ticks) ;
-}
-#endif /* CONFIG_MCFPIT */
-
/*
* This function is derived from PowerPC code (read timebase as long long).
* On M68K it just returns the timer value.
CONFIG_CMD_DATE -- enable to use date feature in U-Boot
CONFIG_MCFTMR -- define to use DMA timer
-CONFIG_MCFPIT -- define to use PIT timer
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
MCFFEC_TOUT_LOOP -- set FEC timeout loop
CONFIG_MCFTMR -- define to use DMA timer
-CONFIG_MCFPIT -- define to use PIT timer
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
MCFFEC_TOUT_LOOP -- set FEC timeout loop
CONFIG_MCFTMR -- define to use DMA timer
-CONFIG_MCFPIT -- define to use PIT timer
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
_IO_BASE -- define for IO base address
CONFIG_MCFTMR -- define to use DMA timer
-CONFIG_MCFPIT -- define to use PIT timer
CONFIG_SYS_FSL_I2C -- define to use FSL common I2C driver
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
Use the Ethernet initialization implemented in common code, which
detects if a Piggy board is present.
-config PIGGY_MAC_ADRESS_OFFSET
+config PIGGY_MAC_ADDRESS_OFFSET
int "Piggy Address Offset"
default 0
help
};
int ethernet_present(void);
-int ivm_read_eeprom(unsigned char *buf, int len);
+int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset);
int ivm_analyze_eeprom(unsigned char *buf, int len);
int trigger_fpga_config(void);
return 0;
}
-static int ivm_populate_env(unsigned char *buf, int len)
+static int ivm_populate_env(unsigned char *buf, int len, int mac_address_offset)
{
unsigned char *page2;
unsigned char valbuf[MAC_STR_SZ];
#ifndef CONFIG_KMTEGR1
/* if an offset is defined, add it */
- process_mac(valbuf, page2, CONFIG_PIGGY_MAC_ADRESS_OFFSET, true);
+ process_mac(valbuf, page2, mac_address_offset, true);
env_set((char *)"ethaddr", (char *)valbuf);
#else
/* KMTEGR1 has a special setup. eth0 has no connection to the outside and
* gets an locally administred MAC address, eth1 is the debug interface and
* gets the official MAC address from the IVM
*/
- process_mac(valbuf, page2, CONFIG_PIGGY_MAC_ADRESS_OFFSET, false);
+ process_mac(valbuf, page2, mac_address_offset, false);
env_set((char *)"ethaddr", (char *)valbuf);
- process_mac(valbuf, page2, CONFIG_PIGGY_MAC_ADRESS_OFFSET, true);
+ process_mac(valbuf, page2, mac_address_offset, true);
env_set((char *)"eth1addr", (char *)valbuf);
#endif
return 0;
}
-int ivm_read_eeprom(unsigned char *buf, int len)
+int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset)
{
int ret;
return -2;
}
- return ivm_populate_env(buf, len);
+ return ivm_populate_env(buf, len, mac_address_offset);
}
int misc_init_r(void)
{
- ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+ ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+ CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
return 0;
}
F: configs/kmnusa_defconfig
F: configs/kmsugp1_defconfig
F: configs/kmsuv31_defconfig
-F: configs/mgcoge3un_defconfig
static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
-#if defined(CONFIG_KM_MGCOGE3UN)
-/*
- * Wait for startup OK from mgcoge3ne
- */
-static int startup_allowed(void)
-{
- unsigned char buf;
-
- /*
- * Read CIRQ16 bit (bit 0)
- */
- if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
- printf("%s: Error reading Boco\n", __func__);
- else
- if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
- return 1;
- return 0;
-}
-#endif
-
#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
/*
* All boards with PIGGY4 connected via a simple switch have ethernet always
int misc_init_r(void)
{
-#if defined(CONFIG_KM_MGCOGE3UN)
- char *wait_for_ne;
- u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
- wait_for_ne = env_get("waitforne");
-
- if ((wait_for_ne != NULL) && (dip_switch == 0)) {
- if (strcmp(wait_for_ne, "true") == 0) {
- int cnt = 0;
- int abort = 0;
- puts("NE go: ");
- while (startup_allowed() == 0) {
- if (tstc()) {
- (void) getc(); /* consume input */
- abort = 1;
- break;
- }
- udelay(200000);
- cnt++;
- if (cnt == 5)
- puts("wait\b\b\b\b");
- if (cnt == 10) {
- cnt = 0;
- puts(" \b\b\b\b");
- }
- }
- if (abort == 1)
- printf("\nAbort waiting for ne\n");
- else
- puts("OK\n");
- }
- }
-#endif
-
- ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+ ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+ CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
initialize_unit_leds();
set_km_env();
int board_late_init(void)
{
-#if (defined(CONFIG_KM_COGE5UN) | defined(CONFIG_KM_MGCOGE3UN))
+#if defined(CONFIG_KM_COGE5UN)
u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
/* if pin 1 do full erase */
}
}
- ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+ ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+ CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
return 0;
}
help
Add an ANSI terminal boot menu command.
-config CMD_DTIMG
- bool "dtimg"
+config CMD_ADTIMG
+ bool "adtimg"
help
Android DTB/DTBO image manipulation commands. Read dtb/dtbo files from
image into RAM, dump image structure information, etc. Those dtb/dtbo
ifdef CONFIG_POST
obj-$(CONFIG_CMD_DIAG) += diag.o
endif
-obj-$(CONFIG_CMD_DTIMG) += dtimg.o
+obj-$(CONFIG_CMD_ADTIMG) += adtimg.o
obj-$(CONFIG_CMD_ECHO) += echo.o
obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o
obj-$(CONFIG_CMD_EEPROM) += eeprom.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ * Eugeniu Rosca <rosca.eugeniu@gmail.com>
+ */
+
+#include <env.h>
+#include <image-android-dt.h>
+#include <common.h>
+
+#define OPT_INDEX "--index"
+
+/*
+ * Current/working DTB/DTBO Android image address.
+ * Similar to 'working_fdt' variable in 'fdt' command.
+ */
+static ulong working_img;
+
+static int do_adtimg_addr(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ char *endp;
+ ulong hdr_addr;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ hdr_addr = simple_strtoul(argv[1], &endp, 16);
+ if (*endp != '\0') {
+ printf("Error: Wrong image address '%s'\n", argv[1]);
+ return CMD_RET_FAILURE;
+ }
+
+ /*
+ * Allow users to set an address prior to copying the DTB/DTBO
+ * image to that same address, i.e. skip header verification.
+ */
+
+ working_img = hdr_addr;
+ return CMD_RET_SUCCESS;
+}
+
+static int adtimg_check_working_img(void)
+{
+ if (!working_img) {
+ printf("Error: Please, call 'adtimg addr <addr>'. Aborting!\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (!android_dt_check_header(working_img)) {
+ printf("Error: Invalid image header at 0x%lx\n", working_img);
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_adtimg_dump(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ if (argc != 1)
+ return CMD_RET_USAGE;
+
+ if (adtimg_check_working_img() != CMD_RET_SUCCESS)
+ return CMD_RET_FAILURE;
+
+ android_dt_print_contents(working_img);
+
+ return CMD_RET_SUCCESS;
+}
+
+static int adtimg_getopt_u32(char * const opt, char * const name, u32 *optval)
+{
+ char *endp, *str;
+ u32 val;
+
+ if (!opt || !name || !optval)
+ return CMD_RET_FAILURE;
+
+ str = strchr(opt, '=');
+ if (!str) {
+ printf("Error: Option '%s' not followed by '='\n", name);
+ return CMD_RET_FAILURE;
+ }
+
+ if (*++str == '\0') {
+ printf("Error: Option '%s=' not followed by value\n", name);
+ return CMD_RET_FAILURE;
+ }
+
+ val = simple_strtoul(str, &endp, 0);
+ if (*endp != '\0') {
+ printf("Error: Wrong integer value '%s=%s'\n", name, str);
+ return CMD_RET_FAILURE;
+ }
+
+ *optval = val;
+ return CMD_RET_SUCCESS;
+}
+
+static int adtimg_getopt_index(int argc, char * const argv[], u32 *index,
+ char **avar, char **svar)
+{
+ int ret;
+
+ if (!argv || !avar || !svar)
+ return CMD_RET_FAILURE;
+
+ if (argc > 3) {
+ printf("Error: Unexpected argument '%s'\n", argv[3]);
+ return CMD_RET_FAILURE;
+ }
+
+ ret = adtimg_getopt_u32(argv[0], OPT_INDEX, index);
+ if (ret != CMD_RET_SUCCESS)
+ return ret;
+
+ if (argc > 1)
+ *avar = argv[1];
+ if (argc > 2)
+ *svar = argv[2];
+
+ return CMD_RET_SUCCESS;
+}
+
+static int adtimg_get_dt_by_index(int argc, char * const argv[])
+{
+ ulong addr;
+ u32 index, size;
+ int ret;
+ char *avar = NULL, *svar = NULL;
+
+ ret = adtimg_getopt_index(argc, argv, &index, &avar, &svar);
+ if (ret != CMD_RET_SUCCESS)
+ return ret;
+
+ if (!android_dt_get_fdt_by_index(working_img, index, &addr, &size))
+ return CMD_RET_FAILURE;
+
+ if (avar && svar) {
+ ret = env_set_hex(avar, addr);
+ if (ret) {
+ printf("Error: Can't set '%s' to 0x%lx\n", avar, addr);
+ return CMD_RET_FAILURE;
+ }
+ ret = env_set_hex(svar, size);
+ if (ret) {
+ printf("Error: Can't set '%s' to 0x%x\n", svar, size);
+ return CMD_RET_FAILURE;
+ }
+ } else if (avar) {
+ ret = env_set_hex(avar, addr);
+ if (ret) {
+ printf("Error: Can't set '%s' to 0x%lx\n", avar, addr);
+ return CMD_RET_FAILURE;
+ }
+ printf("0x%x (%d)\n", size, size);
+ } else {
+ printf("0x%lx, 0x%x (%d)\n", addr, size, size);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int adtimg_get_dt(int argc, char * const argv[])
+{
+ if (argc < 2) {
+ printf("Error: No options passed to '%s'\n", argv[0]);
+ return CMD_RET_FAILURE;
+ }
+
+ /* Strip off leading 'dt' command argument */
+ argc--;
+ argv++;
+
+ if (!strncmp(argv[0], OPT_INDEX, sizeof(OPT_INDEX) - 1))
+ return adtimg_get_dt_by_index(argc, argv);
+
+ printf("Error: Option '%s' not supported\n", argv[0]);
+ return CMD_RET_FAILURE;
+}
+
+static int do_adtimg_get(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ if (argc < 2) {
+ printf("Error: No arguments passed to '%s'\n", argv[0]);
+ return CMD_RET_FAILURE;
+ }
+
+ if (adtimg_check_working_img() != CMD_RET_SUCCESS)
+ return CMD_RET_FAILURE;
+
+ /* Strip off leading 'get' command argument */
+ argc--;
+ argv++;
+
+ if (!strcmp(argv[0], "dt"))
+ return adtimg_get_dt(argc, argv);
+
+ printf("Error: Wrong argument '%s'\n", argv[0]);
+ return CMD_RET_FAILURE;
+}
+
+static cmd_tbl_t cmd_adtimg_sub[] = {
+ U_BOOT_CMD_MKENT(addr, CONFIG_SYS_MAXARGS, 1, do_adtimg_addr, "", ""),
+ U_BOOT_CMD_MKENT(dump, CONFIG_SYS_MAXARGS, 1, do_adtimg_dump, "", ""),
+ U_BOOT_CMD_MKENT(get, CONFIG_SYS_MAXARGS, 1, do_adtimg_get, "", ""),
+};
+
+static int do_adtimg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ cmd_tbl_t *cp;
+
+ cp = find_cmd_tbl(argv[1], cmd_adtimg_sub, ARRAY_SIZE(cmd_adtimg_sub));
+
+ /* Strip off leading 'adtimg' command argument */
+ argc--;
+ argv++;
+
+ if (!cp || argc > cp->maxargs)
+ return CMD_RET_USAGE;
+ if (flag == CMD_FLAG_REPEAT && !cmd_is_repeatable(cp))
+ return CMD_RET_SUCCESS;
+
+ return cp->cmd(cmdtp, flag, argc, argv);
+}
+
+U_BOOT_CMD(
+ adtimg, CONFIG_SYS_MAXARGS, 0, do_adtimg,
+ "manipulate dtb/dtbo Android image",
+ "addr <addr> - Set image location to <addr>\n"
+ "adtimg dump - Print out image contents\n"
+ "adtimg get dt --index=<index> [avar [svar]] - Get DT address/size by index\n"
+ "\n"
+ "Legend:\n"
+ " - <addr>: DTB/DTBO image address (hex) in RAM\n"
+ " - <index>: index (hex/dec) of desired DT in the image\n"
+ " - <avar>: variable name to contain DT address (hex)\n"
+ " - <svar>: variable name to contain DT size (hex)"
+);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2018 Linaro Ltd.
- * Sam Protsenko <semen.protsenko@linaro.org>
- */
-
-#include <env.h>
-#include <image-android-dt.h>
-#include <common.h>
-
-enum cmd_dtimg_info {
- CMD_DTIMG_START = 0,
- CMD_DTIMG_SIZE,
-};
-
-static int do_dtimg_dump(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- char *endp;
- ulong hdr_addr;
-
- if (argc != 2)
- return CMD_RET_USAGE;
-
- hdr_addr = simple_strtoul(argv[1], &endp, 16);
- if (*endp != '\0') {
- printf("Error: Wrong image address\n");
- return CMD_RET_FAILURE;
- }
-
- if (!android_dt_check_header(hdr_addr)) {
- printf("Error: DT image header is incorrect\n");
- return CMD_RET_FAILURE;
- }
-
- android_dt_print_contents(hdr_addr);
-
- return CMD_RET_SUCCESS;
-}
-
-static int dtimg_get_fdt(int argc, char * const argv[], enum cmd_dtimg_info cmd)
-{
- ulong hdr_addr;
- u32 index;
- char *endp;
- ulong fdt_addr;
- u32 fdt_size;
- char buf[65];
-
- if (argc != 4)
- return CMD_RET_USAGE;
-
- hdr_addr = simple_strtoul(argv[1], &endp, 16);
- if (*endp != '\0') {
- printf("Error: Wrong image address\n");
- return CMD_RET_FAILURE;
- }
-
- if (!android_dt_check_header(hdr_addr)) {
- printf("Error: DT image header is incorrect\n");
- return CMD_RET_FAILURE;
- }
-
- index = simple_strtoul(argv[2], &endp, 0);
- if (*endp != '\0') {
- printf("Error: Wrong index\n");
- return CMD_RET_FAILURE;
- }
-
- if (!android_dt_get_fdt_by_index(hdr_addr, index, &fdt_addr, &fdt_size))
- return CMD_RET_FAILURE;
-
- switch (cmd) {
- case CMD_DTIMG_START:
- snprintf(buf, sizeof(buf), "%lx", fdt_addr);
- break;
- case CMD_DTIMG_SIZE:
- snprintf(buf, sizeof(buf), "%x", fdt_size);
- break;
- default:
- printf("Error: Unknown cmd_dtimg_info value: %d\n", cmd);
- return CMD_RET_FAILURE;
- }
-
- env_set(argv[3], buf);
-
- return CMD_RET_SUCCESS;
-}
-
-static int do_dtimg_start(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- return dtimg_get_fdt(argc, argv, CMD_DTIMG_START);
-}
-
-static int do_dtimg_size(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- return dtimg_get_fdt(argc, argv, CMD_DTIMG_SIZE);
-}
-
-static cmd_tbl_t cmd_dtimg_sub[] = {
- U_BOOT_CMD_MKENT(dump, 2, 0, do_dtimg_dump, "", ""),
- U_BOOT_CMD_MKENT(start, 4, 0, do_dtimg_start, "", ""),
- U_BOOT_CMD_MKENT(size, 4, 0, do_dtimg_size, "", ""),
-};
-
-static int do_dtimg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- cmd_tbl_t *cp;
-
- cp = find_cmd_tbl(argv[1], cmd_dtimg_sub, ARRAY_SIZE(cmd_dtimg_sub));
-
- /* Strip off leading 'dtimg' command argument */
- argc--;
- argv++;
-
- if (!cp || argc > cp->maxargs)
- return CMD_RET_USAGE;
- if (flag == CMD_FLAG_REPEAT && !cmd_is_repeatable(cp))
- return CMD_RET_SUCCESS;
-
- return cp->cmd(cmdtp, flag, argc, argv);
-}
-
-U_BOOT_CMD(
- dtimg, CONFIG_SYS_MAXARGS, 0, do_dtimg,
- "manipulate dtb/dtbo Android image",
- "dump <addr>\n"
- " - parse specified image and print its structure info\n"
- " <addr>: image address in RAM, in hex\n"
- "dtimg start <addr> <index> <varname>\n"
- " - get address (hex) of FDT in the image, by index\n"
- " <addr>: image address in RAM, in hex\n"
- " <index>: index of desired FDT in the image\n"
- " <varname>: name of variable where to store address of FDT\n"
- "dtimg size <addr> <index> <varname>\n"
- " - get size (hex, bytes) of FDT in the image, by index\n"
- " <addr>: image address in RAM, in hex\n"
- " <index>: index of desired FDT in the image\n"
- " <varname>: name of variable where to store size of FDT"
-);
{
int rcode = 0;
const char *const fmt =
- "\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... ";
+ "\nEEPROM @0x%lX %s: addr 0x%08lx off 0x%04lx count %ld ... ";
#ifdef CONFIG_CMD_EEPROM_LAYOUT
struct eeprom_layout layout;
#endif
obj-y += memsize.o
obj-y += stdio.o
-obj-$(CONFIG_CMD_DTIMG) += image-android-dt.o
+obj-$(CONFIG_CMD_ADTIMG) += image-android-dt.o
ifdef CONFIG_CMD_EEPROM_LAYOUT
obj-y += eeprom/eeprom_field.o eeprom/eeprom_layout.o
#endif /* !CONFIG_X86 && !CONFIG_ARM */
/**
+ * This function is called from board_init_f_init_reserve to set up
+ * gd->start_addr_sp for stack protection if not already set otherwise
+ */
+__weak void board_init_f_init_stack_protection_addr(ulong base)
+{
+#if CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE)
+ /* set up stack pointer for stack usage if not set yet */
+ if (!gd->start_addr_sp)
+ gd->start_addr_sp = base;
+#endif
+}
+
+/**
* This function is called after the position of the initial stack is
* determined in gd->start_addr_sp. Boards can override it to set up
* stack-checking markers.
#if !defined(CONFIG_ARM)
arch_setup_gd(gd_ptr);
#endif
+
+ if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))
+ board_init_f_init_stack_protection_addr(base);
+
/* next alloc will be higher by one GD plus 16-byte alignment */
base += roundup(sizeof(struct global_data), 16);
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MII=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MII=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MII=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MTD=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MTD=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MTD=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_FSLDMAFEC=y
CONFIG_MII=y
+CONFIG_PHY=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_FSLDMAFEC=y
CONFIG_MII=y
+CONFIG_PHY=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_FSLDMAFEC=y
CONFIG_MII=y
+CONFIG_PHY=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_FSLDMAFEC=y
CONFIG_MII=y
+CONFIG_PHY=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_FSLDMAFEC=y
CONFIG_MII=y
+CONFIG_PHY=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_FSLDMAFEC=y
CONFIG_MII=y
+CONFIG_PHY=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_FSLDMAFEC=y
CONFIG_MII=y
+CONFIG_PHY=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_FSLDMAFEC=y
CONFIG_MII=y
+CONFIG_PHY=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_FSLDMAFEC=y
CONFIG_MII=y
+CONFIG_PHY=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_FSLDMAFEC=y
CONFIG_MII=y
+CONFIG_PHY=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_FSLDMAFEC=y
CONFIG_MII=y
+CONFIG_PHY=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_FSLDMAFEC=y
CONFIG_MII=y
+CONFIG_PHY=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_FSLDMAFEC=y
CONFIG_MII=y
+CONFIG_PHY=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_FSLDMAFEC=y
CONFIG_MII=y
+CONFIG_PHY=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_FSLDMAFEC=y
CONFIG_MII=y
+CONFIG_PHY=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_CMD_DTIMG=y
+CONFIG_CMD_ADTIMG=y
CONFIG_CMD_SPL=y
CONFIG_CMD_BCB=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
-CONFIG_CMD_DTIMG=y
+CONFIG_CMD_ADTIMG=y
CONFIG_CMD_BCB=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_CMD_DTIMG=y
+CONFIG_CMD_ADTIMG=y
CONFIG_CMD_BCB=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_MTD_NOR_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_BAUDRATE=19200
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_VIDEO=y
# CONFIG_CFB_CONSOLE is not set
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_VIDEO=y
# CONFIG_CFB_CONSOLE is not set
CONFIG_MTD_RAW_NAND=y
CONFIG_SF_DEFAULT_SPEED=8100000
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_SYS_NS16550=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SF_DEFAULT_SPEED=8100000
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
-CONFIG_PIGGY_MAC_ADRESS_OFFSET=3
+CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3
CONFIG_KM_ENV_IS_IN_SPI_NOR=y
CONFIG_KM_PIGGY4_88E6352=y
CONFIG_ENV_SIZE=0x2000
CONFIG_MTD_RAW_NAND=y
CONFIG_SF_DEFAULT_SPEED=8100000
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_SYS_NS16550=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SF_DEFAULT_SPEED=8100000
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_MV88E6352_SWITCH=y
CONFIG_MVGBE=y
CONFIG_MII=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_SYS_DCACHE_OFF=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_KIRKWOOD=y
-CONFIG_SYS_TEXT_BASE=0x07d00000
-CONFIG_TARGET_KM_KIRKWOOD=y
-CONFIG_PIGGY_MAC_ADRESS_OFFSET=3
-CONFIG_KM_PIGGY4_88E6061=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_IDENT_STRING="\nKeymile COGE3UN"
-CONFIG_SYS_EXTRA_OPTIONS="KM_MGCOGE3UN"
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
-CONFIG_ENV_IS_IN_EEPROM=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_OFFSET_REDUND=0x2000
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTCOUNT_RAM=y
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SF_DEFAULT_SPEED=8100000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_MVGBE=y
-CONFIG_MII=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_KIRKWOOD_SPI=y
-CONFIG_BCH=y
--- /dev/null
+* Freescale ColdFire DMA-FEC ethernet controller
+
+Required properties:
+- compatible: should be "fsl,mcf-dma-fec"
+- reg: address and length of the register set for the device.
+- rx-task: dma channel
+- tx-task: dma channel
+- rx-priority: dma channel
+- tx-priority: dma channel
+- rx-init: dma channel
+- tx-init: dma channel
+
+Optional properties:
+- mii-base: index of FEC reg area, 0 for FEC0, 1 for FEC1
+- max-speed: max speedm Mbits/sec
+- phy-addr: phy address
+- timeout-loop: integer value for driver loops time out
+
+
+Example:
+
+fec0: ethernet@9000 {
+ compatible = "fsl,mcf-dma-fec";
+ reg = <0x9000 0x800>;
+ mii-base = <0>;
+ phy-addr = <0>;
+ timeout-loop = <5000>;
+ rx-task = <0>;
+ tx-task = <1>;
+ rx-piority = <6>;
+ tx-piority = <7>;
+ rx-init = <16>;
+ tx-init = <17>;
+ status = "disabled";
+};
--- /dev/null
+* Freescale ColdFire FEC ethernet controller
+
+Required properties:
+- compatible: should be "fsl,mcf-fec"
+- reg: address and length of the register set for the device.
+
+Optional properties:
+- mii-base: index of FEC reg area, 0 for FEC0, 1 for FEC1
+- max-speed: max speedm Mbits/sec
+- phy-addr: phy address
+- timeout-loop: integer value for driver loops time out
+
+
+Example:
+
+fec0: ethernet@fc030000 {
+ compatible = "fsl,mcf-fec";
+ reg = <0xfc030000 0x400>;
+ mii-base = <0>;
+ phy-addr = <0>;
+ timeout-loop = <5000>;
+};
--- /dev/null
+DS3232 Real-Time Clock with SRAM
+
+The RTC driver provides time and date functionality. Also read and write
+functions are provided that can be used to access the SRAM memory.
+
+Required properties:
+- compatible : should contain "dallas,ds3232"
+- reg : the I2C RTC address
+
+Example:
+
+rtc@68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+};
Accesses to the backing store are performed using the write16
and read16 ops of DM RTC devices.
+config DM_BOOTCOUNT_I2C_EEPROM
+ bool "Support i2c eeprom devices as a backing store for bootcount"
+ depends on I2C_EEPROM
+ help
+ Enabled reading/writing the bootcount in a DM i2c eeprom device.
+ The wrapper device is to be specified with the compatible string
+ 'u-boot,bootcount-i2c-eeprom' and the 'i2c-eeprom'-property (a phandle
+ pointing to the underlying i2c eeprom device) and an optional 'offset'
+ property are supported.
+
endmenu
endif
obj-$(CONFIG_DM_BOOTCOUNT) += bootcount-uclass.o
obj-$(CONFIG_DM_BOOTCOUNT_RTC) += rtc.o
+obj-$(CONFIG_DM_BOOTCOUNT_I2C_EEPROM) += i2c-eeprom.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Collabora
+ * (C) Copyright 2019 GE
+ */
+
+#include <common.h>
+#include <bootcount.h>
+#include <dm.h>
+#include <i2c_eeprom.h>
+
+static const u8 bootcount_magic = 0xbc;
+
+struct bootcount_i2c_eeprom_priv {
+ struct udevice *i2c_eeprom;
+ u32 offset;
+};
+
+static int bootcount_i2c_eeprom_set(struct udevice *dev, const u32 a)
+{
+ struct bootcount_i2c_eeprom_priv *priv = dev_get_priv(dev);
+ const u16 val = bootcount_magic << 8 | (a & 0xff);
+
+ if (i2c_eeprom_write(priv->i2c_eeprom, priv->offset,
+ (uint8_t *)&val, 2) < 0) {
+ debug("%s: write failed\n", __func__);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int bootcount_i2c_eeprom_get(struct udevice *dev, u32 *a)
+{
+ struct bootcount_i2c_eeprom_priv *priv = dev_get_priv(dev);
+ u16 val;
+
+ if (i2c_eeprom_read(priv->i2c_eeprom, priv->offset,
+ (uint8_t *)&val, 2) < 0) {
+ debug("%s: read failed\n", __func__);
+ return -EIO;
+ }
+
+ if (val >> 8 == bootcount_magic) {
+ *a = val & 0xff;
+ return 0;
+ }
+
+ debug("%s: bootcount magic does not match on %04x\n", __func__, val);
+ return -EIO;
+}
+
+static int bootcount_i2c_eeprom_probe(struct udevice *dev)
+{
+ struct ofnode_phandle_args phandle_args;
+ struct bootcount_i2c_eeprom_priv *priv = dev_get_priv(dev);
+ struct udevice *i2c_eeprom;
+
+ if (dev_read_phandle_with_args(dev, "i2c-eeprom", NULL, 0, 0,
+ &phandle_args)) {
+ debug("%s: i2c-eeprom backing device not specified\n",
+ dev->name);
+ return -ENOENT;
+ }
+
+ if (uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, phandle_args.node,
+ &i2c_eeprom)) {
+ debug("%s: could not get backing device\n", dev->name);
+ return -ENODEV;
+ }
+
+ priv->i2c_eeprom = i2c_eeprom;
+ priv->offset = dev_read_u32_default(dev, "offset", 0);
+
+ return 0;
+}
+
+static const struct bootcount_ops bootcount_i2c_eeprom_ops = {
+ .get = bootcount_i2c_eeprom_get,
+ .set = bootcount_i2c_eeprom_set,
+};
+
+static const struct udevice_id bootcount_i2c_eeprom_ids[] = {
+ { .compatible = "u-boot,bootcount-i2c-eeprom" },
+ { }
+};
+
+U_BOOT_DRIVER(bootcount_spi_flash) = {
+ .name = "bootcount-i2c-eeprom",
+ .id = UCLASS_BOOTCOUNT,
+ .priv_auto_alloc_size = sizeof(struct bootcount_i2c_eeprom_priv),
+ .probe = bootcount_i2c_eeprom_probe,
+ .of_match = bootcount_i2c_eeprom_ids,
+ .ops = &bootcount_i2c_eeprom_ops,
+};
applications.
+config MCFFEC
+ bool "ColdFire Ethernet Support"
+ depends on DM_ETH
+ select PHYLIB
+ help
+ This driver supports the network interface units in the
+ ColdFire family.
+
+config FSLDMAFEC
+ bool "ColdFire DMA Ethernet Support"
+ depends on DM_ETH
+ select PHYLIB
+ help
+ This driver supports the network interface units in the
+ ColdFire family.
+
config MVGBE
bool "Marvell Orion5x/Kirkwood network interface support"
depends on KIRKWOOD || ORION5X
*
* (C) Copyright 2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * Conversion to DM
+ * (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
*/
#include <common.h>
#include <net.h>
#include <miiphy.h>
#include <linux/mii.h>
+#include <asm/immap.h>
+#include <asm/fsl_mcdmafec.h>
+
+#include "MCD_dma.h"
#undef ET_DEBUG
#undef MII_DEBUG
/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH 1520
#define PKT_MAXBUF_SIZE 1518
-#define PKT_MINBUF_SIZE 64
-#define PKT_MAXBLR_SIZE 1536
-#define LAST_PKTBUFSRX PKTBUFSRX - 1
-#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
-#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
#define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
/* RxBD bits definitions */
#define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
BD_ENET_RX_OV | BD_ENET_RX_TR)
-#include <asm/immap.h>
-#include <asm/fsl_mcdmafec.h>
+DECLARE_GLOBAL_DATA_PTR;
-#include "MCD_dma.h"
+static void init_eth_info(struct fec_info_dma *info)
+{
+ /* setup Receive and Transmit buffer descriptor */
+#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
+ static u32 tmp;
-struct fec_info_dma fec_info[] = {
-#ifdef CONFIG_SYS_FEC0_IOBASE
- {
- 0, /* index */
- CONFIG_SYS_FEC0_IOBASE, /* io base */
- CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */
- CONFIG_SYS_FEC0_MIIBASE, /* mii base */
- -1, /* phy_addr */
- 0, /* duplex and speed */
- 0, /* phy name */
- 0, /* phyname init */
- 0, /* RX BD */
- 0, /* TX BD */
- 0, /* rx Index */
- 0, /* tx Index */
- 0, /* tx buffer */
- 0, /* initialized flag */
- (struct fec_info_dma *)-1, /* next */
- FEC0_RX_TASK, /* rxTask */
- FEC0_TX_TASK, /* txTask */
- FEC0_RX_PRIORITY, /* rxPri */
- FEC0_TX_PRIORITY, /* txPri */
- FEC0_RX_INIT, /* rxInit */
- FEC0_TX_INIT, /* txInit */
- 0, /* usedTbdIndex */
- 0, /* cleanTbdNum */
- },
-#endif
-#ifdef CONFIG_SYS_FEC1_IOBASE
- {
- 1, /* index */
- CONFIG_SYS_FEC1_IOBASE, /* io base */
- CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */
- CONFIG_SYS_FEC1_MIIBASE, /* mii base */
- -1, /* phy_addr */
- 0, /* duplex and speed */
- 0, /* phy name */
- 0, /* phy name init */
-#ifdef CONFIG_SYS_DMA_USE_INTSRAM
- (cbd_t *)DBUF_LENGTH, /* RX BD */
+ if (info->index == 0)
+ tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
+ else
+ info->rxbd = (cbd_t *)DBUF_LENGTH;
+
+ info->rxbd = (cbd_t *)((u32)info->rxbd + tmp);
+ tmp = (u32)info->rxbd;
+ info->txbd =
+ (cbd_t *)((u32)info->txbd + tmp +
+ (PKTBUFSRX * sizeof(cbd_t)));
+ tmp = (u32)info->txbd;
+ info->txbuf =
+ (char *)((u32)info->txbuf + tmp +
+ (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
+ tmp = (u32)info->txbuf;
#else
- 0, /* RX BD */
+ info->rxbd =
+ (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
+ (PKTBUFSRX * sizeof(cbd_t)));
+ info->txbd =
+ (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
+ (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
+ info->txbuf =
+ (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
#endif
- 0, /* TX BD */
- 0, /* rx Index */
- 0, /* tx Index */
- 0, /* tx buffer */
- 0, /* initialized flag */
- (struct fec_info_dma *)-1, /* next */
- FEC1_RX_TASK, /* rxTask */
- FEC1_TX_TASK, /* txTask */
- FEC1_RX_PRIORITY, /* rxPri */
- FEC1_TX_PRIORITY, /* txPri */
- FEC1_RX_INIT, /* rxInit */
- FEC1_TX_INIT, /* txInit */
- 0, /* usedTbdIndex */
- 0, /* cleanTbdNum */
- }
+
+#ifdef ET_DEBUG
+ printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd);
#endif
-};
+ info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
+}
+
+static void fec_halt(struct udevice *dev)
+{
+ struct fec_info_dma *info = dev->priv;
+ volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
+ int counter = 0xffff;
+
+ /* issue graceful stop command to the FEC transmitter if necessary */
+ fecp->tcr |= FEC_TCR_GTS;
+
+ /* wait for graceful stop to register */
+ while ((counter--) && (!(fecp->eir & FEC_EIR_GRA)))
+ ;
+
+ /* Disable DMA tasks */
+ MCD_killDma(info->tx_task);
+ MCD_killDma(info->rx_task);
+
+ /* Disable the Ethernet Controller */
+ fecp->ecr &= ~FEC_ECR_ETHER_EN;
+
+ /* Clear FIFO status registers */
+ fecp->rfsr &= FIFO_ERRSTAT;
+ fecp->tfsr &= FIFO_ERRSTAT;
+
+ fecp->frst = 0x01000000;
-static int fec_send(struct eth_device *dev, void *packet, int length);
-static int fec_recv(struct eth_device *dev);
-static int fec_init(struct eth_device *dev, bd_t * bd);
-static void fec_halt(struct eth_device *dev);
+ /* Issue a reset command to the FEC chip */
+ fecp->ecr |= FEC_ECR_RESET;
+
+ /* wait at least 20 clock cycles */
+ mdelay(10);
+
+#ifdef ET_DEBUG
+ printf("Ethernet task stopped\n");
+#endif
+}
#ifdef ET_DEBUG
static void dbg_fec_regs(struct eth_device *dev)
{
struct fec_info_dma *info = dev->priv;
- volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
+ volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
printf("=====\n");
printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
}
#endif
-static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd,
- int dup_spd)
+static void set_fec_duplex_speed(volatile fecdma_t *fecp, int dup_spd)
{
+ bd_t *bd = gd->bd;
+
if ((dup_spd >> 16) == FULL) {
/* Set maximum frame length */
fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
}
}
-static int fec_send(struct eth_device *dev, void *packet, int length)
-{
- struct fec_info_dma *info = dev->priv;
- cbd_t *pTbd, *pUsedTbd;
- u16 phyStatus;
-
- miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
-
- /* process all the consumed TBDs */
- while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) {
- pUsedTbd = &info->txbd[info->usedTbdIdx];
- if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) {
-#ifdef ET_DEBUG
- printf("Cannot clean TBD %d, in use\n",
- info->cleanTbdNum);
-#endif
- return 0;
- }
-
- /* clean this buffer descriptor */
- if (info->usedTbdIdx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
- pUsedTbd->cbd_sc = BD_ENET_TX_WRAP;
- else
- pUsedTbd->cbd_sc = 0;
-
- /* update some indeces for a correct handling of the TBD ring */
- info->cleanTbdNum++;
- info->usedTbdIdx = (info->usedTbdIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
- }
-
- /* Check for valid length of data. */
- if ((length > 1500) || (length <= 0)) {
- return -1;
- }
-
- /* Check the number of vacant TxBDs. */
- if (info->cleanTbdNum < 1) {
- printf("No available TxBDs ...\n");
- return -1;
- }
-
- /* Get the first TxBD to send the mac header */
- pTbd = &info->txbd[info->txIdx];
- pTbd->cbd_datlen = length;
- pTbd->cbd_bufaddr = (u32) packet;
- pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
- info->txIdx = (info->txIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
-
- /* Enable DMA transmit task */
- MCD_continDma(info->txTask);
-
- info->cleanTbdNum -= 1;
-
- /* wait until frame is sent . */
- while (pTbd->cbd_sc & BD_ENET_TX_READY) {
- udelay(10);
- }
-
- return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
-}
-
-static int fec_recv(struct eth_device *dev)
-{
- struct fec_info_dma *info = dev->priv;
- volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
-
- cbd_t *prbd = &info->rxbd[info->rxIdx];
- u32 ievent;
- int frame_length, len = 0;
-
- /* Check if any critical events have happened */
- ievent = fecp->eir;
- if (ievent != 0) {
- fecp->eir = ievent;
-
- if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
- printf("fec_recv: error\n");
- fec_halt(dev);
- fec_init(dev, NULL);
- return 0;
- }
-
- if (ievent & FEC_EIR_HBERR) {
- /* Heartbeat error */
- fecp->tcr |= FEC_TCR_GTS;
- }
-
- if (ievent & FEC_EIR_GRA) {
- /* Graceful stop complete */
- if (fecp->tcr & FEC_TCR_GTS) {
- printf("fec_recv: tcr_gts\n");
- fec_halt(dev);
- fecp->tcr &= ~FEC_TCR_GTS;
- fec_init(dev, NULL);
- }
- }
- }
-
- if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
- if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
- !(prbd->cbd_sc & BD_ENET_RX_ERR) &&
- ((prbd->cbd_datlen - 4) > 14)) {
-
- /* Get buffer address and size */
- frame_length = prbd->cbd_datlen - 4;
-
- /* Fill the buffer and pass it to upper layers */
- net_process_received_packet((uchar *)prbd->cbd_bufaddr,
- frame_length);
- len = frame_length;
- }
-
- /* Reset buffer descriptor as empty */
- if ((info->rxIdx) == (PKTBUFSRX - 1))
- prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
- else
- prbd->cbd_sc = BD_ENET_RX_EMPTY;
-
- prbd->cbd_datlen = PKTSIZE_ALIGN;
-
- /* Now, we have an empty RxBD, restart the DMA receive task */
- MCD_continDma(info->rxTask);
-
- /* Increment BD count */
- info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX;
- }
-
- return len;
-}
-
-static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac)
+static void fec_set_hwaddr(volatile fecdma_t *fecp, u8 *mac)
{
- u8 currByte; /* byte for which to compute the CRC */
+ u8 curr_byte; /* byte for which to compute the CRC */
int byte; /* loop - counter */
int bit; /* loop - counter */
u32 crc = 0xffffffff; /* initial value */
for (byte = 0; byte < 6; byte++) {
- currByte = mac[byte];
+ curr_byte = mac[byte];
for (bit = 0; bit < 8; bit++) {
- if ((currByte & 0x01) ^ (crc & 0x01)) {
+ if ((curr_byte & 0x01) ^ (crc & 0x01)) {
crc >>= 1;
crc = crc ^ 0xedb88320;
} else {
crc >>= 1;
}
- currByte >>= 1;
+ curr_byte >>= 1;
}
}
fecp->galr = 0;
}
-static int fec_init(struct eth_device *dev, bd_t * bd)
+static int fec_init(struct udevice *dev)
{
struct fec_info_dma *info = dev->priv;
- volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
- int i;
+ volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
+ int rval, i;
uchar enetaddr[6];
#ifdef ET_DEBUG
printf("fec_init: iobase 0x%08x ...\n", info->iobase);
#endif
- fecpin_setclear(dev, 1);
-
+ fecpin_setclear(info, 1);
fec_halt(dev);
#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
defined (CONFIG_SYS_DISCOVER_PHY)
mii_init();
-
- set_fec_duplex_speed(fecp, bd, info->dup_spd);
+ set_fec_duplex_speed(fecp, info->dup_spd);
#else
#ifndef CONFIG_SYS_DISCOVER_PHY
- set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
+ set_fec_duplex_speed(fecp, (FECDUPLEX << 16) | FECSPEED);
#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
#endif /* CONFIG_CMD_MII || CONFIG_MII */
fecp->eir = 0xffffffff;
/* Set station address */
- if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE)
- eth_env_get_enetaddr("ethaddr", enetaddr);
+ if (info->index == 0)
+ rval = eth_env_get_enetaddr("ethaddr", enetaddr);
else
- eth_env_get_enetaddr("eth1addr", enetaddr);
+ rval = eth_env_get_enetaddr("eth1addr", enetaddr);
+
+ if (!rval) {
+ puts("Please set a valid MAC address\n");
+ return -EINVAL;
+ }
+
fec_set_hwaddr(fecp, enetaddr);
/* Set Opcode/Pause Duration Register */
fecp->opd = 0x00010020;
/* Setup Buffers and Buffer Descriptors */
- info->rxIdx = 0;
- info->txIdx = 0;
+ info->rx_idx = 0;
+ info->tx_idx = 0;
/* Setup Receiver Buffer Descriptors (13.14.24.18)
* Settings: Empty, Wrap */
}
info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
- info->usedTbdIdx = 0;
- info->cleanTbdNum = CONFIG_SYS_TX_ETH_BUFFER;
+ info->used_tbd_idx = 0;
+ info->clean_tbd_num = CONFIG_SYS_TX_ETH_BUFFER;
/* Set Rx FIFO alarm and granularity value */
fecp->rfcr = 0x0c000000;
fecp->ctcwr = 0x03000000;
/* Enable DMA receive task */
- MCD_startDma(info->rxTask, /* Dma channel */
- (s8 *) info->rxbd, /*Source Address */
- 0, /* Source increment */
- (s8 *) (&fecp->rfdr), /* dest */
- 4, /* dest increment */
- 0, /* DMA size */
- 4, /* xfer size */
- info->rxInit, /* initiator */
- info->rxPri, /* priority */
- (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF), /* Flags */
- (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */
+ MCD_startDma(info->rx_task,
+ (s8 *)info->rxbd,
+ 0,
+ (s8 *)&fecp->rfdr,
+ 4,
+ 0,
+ 4,
+ info->rx_init,
+ info->rx_pri,
+ (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF),
+ (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
);
/* Enable DMA tx task with no ready buffer descriptors */
- MCD_startDma(info->txTask, /* Dma channel */
- (s8 *) info->txbd, /*Source Address */
- 0, /* Source increment */
- (s8 *) (&fecp->tfdr), /* dest */
- 4, /* dest incr */
- 0, /* DMA size */
- 4, /* xfer size */
- info->txInit, /* initiator */
- info->txPri, /* priority */
- (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF), /* Flags */
- (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */
+ MCD_startDma(info->tx_task,
+ (s8 *)info->txbd,
+ 0,
+ (s8 *)&fecp->tfdr,
+ 4,
+ 0,
+ 4,
+ info->tx_init,
+ info->tx_pri,
+ (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF),
+ (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
);
/* Now enable the transmit and receive processing */
fecp->ecr |= FEC_ECR_ETHER_EN;
- return 1;
+ return 0;
+}
+
+static int mcdmafec_init(struct udevice *dev)
+{
+ return fec_init(dev);
}
-static void fec_halt(struct eth_device *dev)
+static int mcdmafec_send(struct udevice *dev, void *packet, int length)
{
struct fec_info_dma *info = dev->priv;
- volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
- int counter = 0xffff;
+ cbd_t *p_tbd, *p_used_tbd;
+ u16 phy_status;
- /* issue graceful stop command to the FEC transmitter if necessary */
- fecp->tcr |= FEC_TCR_GTS;
+ miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
- /* wait for graceful stop to register */
- while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ;
+ /* process all the consumed TBDs */
+ while (info->clean_tbd_num < CONFIG_SYS_TX_ETH_BUFFER) {
+ p_used_tbd = &info->txbd[info->used_tbd_idx];
+ if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) {
+#ifdef ET_DEBUG
+ printf("Cannot clean TBD %d, in use\n",
+ info->clean_tbd_num);
+#endif
+ return 0;
+ }
- /* Disable DMA tasks */
- MCD_killDma(info->txTask);
- MCD_killDma(info->rxTask);
+ /* clean this buffer descriptor */
+ if (info->used_tbd_idx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
+ p_used_tbd->cbd_sc = BD_ENET_TX_WRAP;
+ else
+ p_used_tbd->cbd_sc = 0;
- /* Disable the Ethernet Controller */
- fecp->ecr &= ~FEC_ECR_ETHER_EN;
+ /* update some indeces for a correct handling of TBD ring */
+ info->clean_tbd_num++;
+ info->used_tbd_idx = (info->used_tbd_idx + 1)
+ % CONFIG_SYS_TX_ETH_BUFFER;
+ }
- /* Clear FIFO status registers */
- fecp->rfsr &= FIFO_ERRSTAT;
- fecp->tfsr &= FIFO_ERRSTAT;
+ /* Check for valid length of data. */
+ if (length > 1500 || length <= 0)
+ return -1;
- fecp->frst = 0x01000000;
+ /* Check the number of vacant TxBDs. */
+ if (info->clean_tbd_num < 1) {
+ printf("No available TxBDs ...\n");
+ return -1;
+ }
- /* Issue a reset command to the FEC chip */
- fecp->ecr |= FEC_ECR_RESET;
+ /* Get the first TxBD to send the mac header */
+ p_tbd = &info->txbd[info->tx_idx];
+ p_tbd->cbd_datlen = length;
+ p_tbd->cbd_bufaddr = (u32)packet;
+ p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
+ info->tx_idx = (info->tx_idx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
- /* wait at least 20 clock cycles */
- udelay(10000);
+ /* Enable DMA transmit task */
+ MCD_continDma(info->tx_task);
-#ifdef ET_DEBUG
- printf("Ethernet task stopped\n");
-#endif
+ info->clean_tbd_num -= 1;
+
+ /* wait until frame is sent . */
+ while (p_tbd->cbd_sc & BD_ENET_TX_READY)
+ udelay(10);
+
+ return (int)(info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS);
}
-int mcdmafec_initialize(bd_t * bis)
+static int mcdmafec_recv(struct udevice *dev, int flags, uchar **packetp)
{
- struct eth_device *dev;
- int i;
-#ifdef CONFIG_SYS_DMA_USE_INTSRAM
- u32 tmp = CONFIG_SYS_INTSRAM + 0x2000;
-#endif
+ struct fec_info_dma *info = dev->priv;
+ volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
- for (i = 0; i < ARRAY_SIZE(fec_info); i++) {
-
- dev =
- (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
- sizeof *dev);
- if (dev == NULL)
- hang();
-
- memset(dev, 0, sizeof(*dev));
-
- sprintf(dev->name, "FEC%d", fec_info[i].index);
-
- dev->priv = &fec_info[i];
- dev->init = fec_init;
- dev->halt = fec_halt;
- dev->send = fec_send;
- dev->recv = fec_recv;
-
- /* setup Receive and Transmit buffer descriptor */
-#ifdef CONFIG_SYS_DMA_USE_INTSRAM
- fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
- tmp = (u32)fec_info[i].rxbd;
- fec_info[i].txbd =
- (cbd_t *)((u32)fec_info[i].txbd + tmp +
- (PKTBUFSRX * sizeof(cbd_t)));
- tmp = (u32)fec_info[i].txbd;
- fec_info[i].txbuf =
- (char *)((u32)fec_info[i].txbuf + tmp +
- (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
- tmp = (u32)fec_info[i].txbuf;
-#else
- fec_info[i].rxbd =
- (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
- (PKTBUFSRX * sizeof(cbd_t)));
- fec_info[i].txbd =
- (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
- (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
- fec_info[i].txbuf =
- (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
-#endif
+ cbd_t *prbd = &info->rxbd[info->rx_idx];
+ u32 ievent;
+ int frame_length, len = 0;
-#ifdef ET_DEBUG
- printf("rxbd %x txbd %x\n",
- (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
-#endif
+ /* Check if any critical events have happened */
+ ievent = fecp->eir;
+ if (ievent != 0) {
+ fecp->eir = ievent;
- fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
+ if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
+ printf("fec_recv: error\n");
+ fec_halt(dev);
+ fec_init(dev);
+ return 0;
+ }
- eth_register(dev);
+ if (ievent & FEC_EIR_HBERR) {
+ /* Heartbeat error */
+ fecp->tcr |= FEC_TCR_GTS;
+ }
+
+ if (ievent & FEC_EIR_GRA) {
+ /* Graceful stop complete */
+ if (fecp->tcr & FEC_TCR_GTS) {
+ printf("fec_recv: tcr_gts\n");
+ fec_halt(dev);
+ fecp->tcr &= ~FEC_TCR_GTS;
+ fec_init(dev);
+ }
+ }
+ }
+
+ if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
+ if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
+ !(prbd->cbd_sc & BD_ENET_RX_ERR) &&
+ ((prbd->cbd_datlen - 4) > 14)) {
+ /* Get buffer address and size */
+ frame_length = prbd->cbd_datlen - 4;
+
+ /* Fill the buffer and pass it to upper layers */
+ net_process_received_packet((uchar *)prbd->cbd_bufaddr,
+ frame_length);
+ len = frame_length;
+ }
+
+ /* Reset buffer descriptor as empty */
+ if (info->rx_idx == (PKTBUFSRX - 1))
+ prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
+ else
+ prbd->cbd_sc = BD_ENET_RX_EMPTY;
+
+ prbd->cbd_datlen = PKTSIZE_ALIGN;
+
+ /* Now, we have an empty RxBD, restart the DMA receive task */
+ MCD_continDma(info->rx_task);
+
+ /* Increment BD count */
+ info->rx_idx = (info->rx_idx + 1) % PKTBUFSRX;
+ }
+
+ return len;
+}
+
+static void mcdmafec_halt(struct udevice *dev)
+{
+ fec_halt(dev);
+}
+
+static const struct eth_ops mcdmafec_ops = {
+ .start = mcdmafec_init,
+ .send = mcdmafec_send,
+ .recv = mcdmafec_recv,
+ .stop = mcdmafec_halt,
+};
+
+/*
+ * Boot sequence, called just after mcffec_ofdata_to_platdata,
+ * as DM way, it replaces old mcffec_initialize.
+ */
+static int mcdmafec_probe(struct udevice *dev)
+{
+ struct fec_info_dma *info = dev->priv;
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ int node = dev_of_offset(dev);
+ int retval;
+ const u32 *val;
+
+ info->index = dev->seq;
+ info->iobase = pdata->iobase;
+ info->miibase = pdata->iobase;
+ info->phy_addr = -1;
+
+ val = fdt_getprop(gd->fdt_blob, node, "rx-task", NULL);
+ if (val)
+ info->rx_task = fdt32_to_cpu(*val);
+
+ val = fdt_getprop(gd->fdt_blob, node, "tx-task", NULL);
+ if (val)
+ info->tx_task = fdt32_to_cpu(*val);
+
+ val = fdt_getprop(gd->fdt_blob, node, "rx-prioprity", NULL);
+ if (val)
+ info->rx_pri = fdt32_to_cpu(*val);
+
+ val = fdt_getprop(gd->fdt_blob, node, "tx-prioprity", NULL);
+ if (val)
+ info->tx_pri = fdt32_to_cpu(*val);
+
+ val = fdt_getprop(gd->fdt_blob, node, "rx-init", NULL);
+ if (val)
+ info->rx_init = fdt32_to_cpu(*val);
+
+ val = fdt_getprop(gd->fdt_blob, node, "tx-init", NULL);
+ if (val)
+ info->tx_init = fdt32_to_cpu(*val);
+
+#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
+ u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
+#endif
+ init_eth_info(info);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = mcffec_miiphy_read;
- mdiodev->write = mcffec_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
+ info->bus = mdio_alloc();
+ if (!info->bus)
+ return -ENOMEM;
+ strncpy(info->bus->name, dev->name, MDIO_NAME_LEN);
+ info->bus->read = mcffec_miiphy_read;
+ info->bus->write = mcffec_miiphy_write;
+
+ retval = mdio_register(info->bus);
+ if (retval < 0)
+ return retval;
#endif
- if (i > 0)
- fec_info[i - 1].next = &fec_info[i];
- }
- fec_info[i - 1].next = &fec_info[0];
+ return 0;
+}
- /* default speed */
- bis->bi_ethspeed = 10;
+static int mcdmafec_remove(struct udevice *dev)
+{
+ struct fec_info_dma *priv = dev_get_priv(dev);
+
+ mdio_unregister(priv->bus);
+ mdio_free(priv->bus);
return 0;
}
+
+/*
+ * Boot sequence, called 1st
+ */
+static int mcdmafec_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ const u32 *val;
+
+ pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
+ /* Default to 10Mbit/s */
+ pdata->max_speed = 10;
+
+ val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
+ if (val)
+ pdata->max_speed = fdt32_to_cpu(*val);
+
+ return 0;
+}
+
+static const struct udevice_id mcdmafec_ids[] = {
+ { .compatible = "fsl,mcf-dma-fec" },
+ { }
+};
+
+U_BOOT_DRIVER(mcffec) = {
+ .name = "mcdmafec",
+ .id = UCLASS_ETH,
+ .of_match = mcdmafec_ids,
+ .ofdata_to_platdata = mcdmafec_ofdata_to_platdata,
+ .probe = mcdmafec_probe,
+ .remove = mcdmafec_remove,
+ .ops = &mcdmafec_ops,
+ .priv_auto_alloc_size = sizeof(struct fec_info_dma),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
*
* (C) Copyright 2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * Conversion to DM
+ * (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
*/
#include <common.h>
#include <env.h>
#include <malloc.h>
-
#include <command.h>
#include <net.h>
-#include <netdev.h>
#include <miiphy.h>
-
#include <asm/fec.h>
#include <asm/immap.h>
#include <linux/mii.h>
#define DBUF_LENGTH 1520
#define TX_BUF_CNT 2
#define PKT_MAXBUF_SIZE 1518
-#define PKT_MINBUF_SIZE 64
#define PKT_MAXBLR_SIZE 1520
#define LAST_PKTBUFSRX PKTBUFSRX - 1
#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
-struct fec_info_s fec_info[] = {
-#ifdef CONFIG_SYS_FEC0_IOBASE
- {
- 0, /* index */
- CONFIG_SYS_FEC0_IOBASE, /* io base */
- CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */
- CONFIG_SYS_FEC0_MIIBASE, /* mii base */
- -1, /* phy_addr */
- 0, /* duplex and speed */
- 0, /* phy name */
- 0, /* phyname init */
- 0, /* RX BD */
- 0, /* TX BD */
- 0, /* rx Index */
- 0, /* tx Index */
- 0, /* tx buffer */
- 0, /* initialized flag */
- (struct fec_info_s *)-1,
- },
-#endif
-#ifdef CONFIG_SYS_FEC1_IOBASE
- {
- 1, /* index */
- CONFIG_SYS_FEC1_IOBASE, /* io base */
- CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */
- CONFIG_SYS_FEC1_MIIBASE, /* mii base */
- -1, /* phy_addr */
- 0, /* duplex and speed */
- 0, /* phy name */
- 0, /* phy name init */
+DECLARE_GLOBAL_DATA_PTR;
+
+static void init_eth_info(struct fec_info_s *info)
+{
#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
- (cbd_t *)DBUF_LENGTH, /* RX BD */
+ static u32 tmp;
+
+ if (info->index == 0)
+ tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
+ else
+ info->rxbd = (cbd_t *)DBUF_LENGTH;
+
+ /* setup Receive and Transmit buffer descriptor */
+ info->rxbd = (cbd_t *)((u32)info->rxbd + tmp);
+ tmp = (u32)info->rxbd;
+ info->txbd =
+ (cbd_t *)((u32)info->txbd + tmp +
+ (PKTBUFSRX * sizeof(cbd_t)));
+ tmp = (u32)info->txbd;
+ info->txbuf =
+ (char *)((u32)info->txbuf + tmp +
+ (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
+ tmp = (u32)info->txbuf;
#else
- 0, /* RX BD */
+ info->rxbd =
+ (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
+ (PKTBUFSRX * sizeof(cbd_t)));
+ info->txbd =
+ (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
+ (TX_BUF_CNT * sizeof(cbd_t)));
+ info->txbuf =
+ (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
#endif
- 0, /* TX BD */
- 0, /* rx Index */
- 0, /* tx Index */
- 0, /* tx buffer */
- 0, /* initialized flag */
- (struct fec_info_s *)-1,
- }
+
+#ifdef ET_DEBUG
+ printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd);
#endif
-};
+ info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
+}
+
+static void fec_reset(struct fec_info_s *info)
+{
+ volatile fec_t *fecp = (fec_t *)(info->iobase);
+ int i;
+
+ fecp->ecr = FEC_ECR_RESET;
+ for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i)
+ udelay(1);
-int fec_recv(struct eth_device *dev);
-int fec_init(struct eth_device *dev, bd_t * bd);
-void fec_halt(struct eth_device *dev);
-void fec_reset(struct eth_device *dev);
+ if (i == FEC_RESET_DELAY)
+ printf("FEC_RESET_DELAY timeout\n");
+}
-void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
+static void set_fec_duplex_speed(volatile fec_t *fecp, int dup_spd)
{
+ bd_t *bd = gd->bd;
+
if ((dup_spd >> 16) == FULL) {
/* Set maximum frame length */
fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
}
}
-static int fec_send(struct eth_device *dev, void *packet, int length)
-{
- struct fec_info_s *info = dev->priv;
- volatile fec_t *fecp = (fec_t *) (info->iobase);
- int j, rc;
- u16 phyStatus;
-
- miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
-
- /* section 16.9.23.3
- * Wait for ready
- */
- j = 0;
- while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
- (j < MCFFEC_TOUT_LOOP)) {
- udelay(1);
- j++;
- }
- if (j >= MCFFEC_TOUT_LOOP) {
- printf("TX not ready\n");
- }
-
- info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
- info->txbd[info->txIdx].cbd_datlen = length;
- info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST;
-
- /* Activate transmit Buffer Descriptor polling */
- fecp->tdar = 0x01000000; /* Descriptor polling active */
-
-#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
- /*
- * FEC unable to initial transmit data packet.
- * A nop will ensure the descriptor polling active completed.
- * CF Internal RAM has shorter cycle access than DRAM. If use
- * DRAM as Buffer descriptor and data, a nop is a must.
- * Affect only V2 and V3.
- */
- __asm__ ("nop");
-
-#endif
-
-#ifdef CONFIG_SYS_UNIFY_CACHE
- icache_invalid();
-#endif
-
- j = 0;
- while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
- (j < MCFFEC_TOUT_LOOP)) {
- udelay(1);
- j++;
- }
- if (j >= MCFFEC_TOUT_LOOP) {
- printf("TX timeout\n");
- }
-
-#ifdef ET_DEBUG
- printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
- __FILE__, __LINE__, __FUNCTION__, j,
- info->txbd[info->txIdx].cbd_sc,
- (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2);
-#endif
-
- /* return only status bits */
- rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
- info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;
-
- return rc;
-}
-
-int fec_recv(struct eth_device *dev)
-{
- struct fec_info_s *info = dev->priv;
- volatile fec_t *fecp = (fec_t *) (info->iobase);
- int length;
-
- for (;;) {
-#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
-#endif
-#ifdef CONFIG_SYS_UNIFY_CACHE
- icache_invalid();
-#endif
- /* section 16.9.23.2 */
- if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
- length = -1;
- break; /* nothing received - leave for() loop */
- }
-
- length = info->rxbd[info->rxIdx].cbd_datlen;
-
- if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) {
- printf("%s[%d] err: %x\n",
- __FUNCTION__, __LINE__,
- info->rxbd[info->rxIdx].cbd_sc);
-#ifdef ET_DEBUG
- printf("%s[%d] err: %x\n",
- __FUNCTION__, __LINE__,
- info->rxbd[info->rxIdx].cbd_sc);
-#endif
- } else {
-
- length -= 4;
- /* Pass the packet up to the protocol layers. */
- net_process_received_packet(net_rx_packets[info->rxIdx],
- length);
-
- fecp->eir |= FEC_EIR_RXF;
- }
-
- /* Give the buffer back to the FEC. */
- info->rxbd[info->rxIdx].cbd_datlen = 0;
-
- /* wrap around buffer index when necessary */
- if (info->rxIdx == LAST_PKTBUFSRX) {
- info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E;
- info->rxIdx = 0;
- } else {
- info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
- info->rxIdx++;
- }
-
- /* Try to fill Buffer Descriptors */
- fecp->rdar = 0x01000000; /* Descriptor polling active */
- }
-
- return length;
-}
-
#ifdef ET_DEBUG
-void dbgFecRegs(struct eth_device *dev)
+static void dbg_fec_regs(struct udevice *dev)
{
struct fec_info_s *info = dev->priv;
- volatile fec_t *fecp = (fec_t *) (info->iobase);
+ volatile fec_t *fecp = (fec_t *)(info->iobase);
printf("=====\n");
printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
}
#endif
-int fec_init(struct eth_device *dev, bd_t * bd)
+int mcffec_init(struct udevice *dev)
{
struct fec_info_s *info = dev->priv;
volatile fec_t *fecp = (fec_t *) (info->iobase);
- int i;
+ int rval, i;
uchar ea[6];
- fecpin_setclear(dev, 1);
-
- fec_reset(dev);
+ fecpin_setclear(info, 1);
+ fec_reset(info);
#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
defined (CONFIG_SYS_DISCOVER_PHY)
mii_init();
- setFecDuplexSpeed(fecp, bd, info->dup_spd);
+ set_fec_duplex_speed(fecp, info->dup_spd);
#else
#ifndef CONFIG_SYS_DISCOVER_PHY
- setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
-#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
-#endif /* CONFIG_CMD_MII || CONFIG_MII */
+ set_fec_duplex_speed(fecp, (FECDUPLEX << 16) | FECSPEED);
+#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
+#endif /* CONFIG_CMD_MII || CONFIG_MII */
/* We use strictly polling mode only */
fecp->eimr = 0;
fecp->eir = 0xffffffff;
/* Set station address */
- if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) {
-#ifdef CONFIG_SYS_FEC1_IOBASE
- volatile fec_t *fecp1 = (fec_t *) (CONFIG_SYS_FEC1_IOBASE);
- eth_env_get_enetaddr("eth1addr", ea);
- fecp1->palr =
- (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
- fecp1->paur = (ea[4] << 24) | (ea[5] << 16);
-#endif
- eth_env_get_enetaddr("ethaddr", ea);
- fecp->palr =
- (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
- fecp->paur = (ea[4] << 24) | (ea[5] << 16);
- } else {
-#ifdef CONFIG_SYS_FEC0_IOBASE
- volatile fec_t *fecp0 = (fec_t *) (CONFIG_SYS_FEC0_IOBASE);
- eth_env_get_enetaddr("ethaddr", ea);
- fecp0->palr =
- (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
- fecp0->paur = (ea[4] << 24) | (ea[5] << 16);
-#endif
-#ifdef CONFIG_SYS_FEC1_IOBASE
- eth_env_get_enetaddr("eth1addr", ea);
- fecp->palr =
- (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
- fecp->paur = (ea[4] << 24) | (ea[5] << 16);
-#endif
+ if (info->index == 0)
+ rval = eth_env_get_enetaddr("ethaddr", ea);
+ else
+ rval = eth_env_get_enetaddr("eth1addr", ea);
+
+ if (!rval) {
+ puts("Please set a valid MAC address\n");
+ return -EINVAL;
}
+ fecp->palr =
+ (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
+ fecp->paur = (ea[4] << 24) | (ea[5] << 16);
+
/* Clear unicast address hash table */
fecp->iaur = 0;
fecp->ialr = 0;
/*
* Setup Buffers and Buffer Descriptors
*/
- info->rxIdx = 0;
- info->txIdx = 0;
+ info->rx_idx = 0;
+ info->tx_idx = 0;
/*
* Setup Receiver Buffer Descriptors (13.14.24.18)
/* Now enable the transmit and receive processing */
fecp->ecr |= FEC_ECR_ETHER_EN;
- /* And last, try to fill Rx Buffer Descriptors */
- fecp->rdar = 0x01000000; /* Descriptor polling active */
+ /* And last, try to fill Rx Buffer Descriptors
+ * Descriptor polling active
+ */
+ fecp->rdar = 0x01000000;
- return 1;
+ return 0;
}
-void fec_reset(struct eth_device *dev)
+static int mcffec_send(struct udevice *dev, void *packet, int length)
{
struct fec_info_s *info = dev->priv;
- volatile fec_t *fecp = (fec_t *) (info->iobase);
- int i;
+ volatile fec_t *fecp = (fec_t *)info->iobase;
+ int j, rc;
+ u16 phy_status;
- fecp->ecr = FEC_ECR_RESET;
- for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
+ miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
+
+ /* section 16.9.23.3
+ * Wait for ready
+ */
+ j = 0;
+ while ((info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_READY) &&
+ (j < info->to_loop)) {
udelay(1);
+ j++;
}
- if (i == FEC_RESET_DELAY) {
- printf("FEC_RESET_DELAY timeout\n");
+ if (j >= info->to_loop)
+ printf("TX not ready\n");
+
+ info->txbd[info->tx_idx].cbd_bufaddr = (uint)packet;
+ info->txbd[info->tx_idx].cbd_datlen = length;
+ info->txbd[info->tx_idx].cbd_sc |= BD_ENET_TX_RDY_LST;
+
+ /* Activate transmit Buffer Descriptor polling */
+ fecp->tdar = 0x01000000; /* Descriptor polling active */
+
+#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
+ /*
+ * FEC unable to initial transmit data packet.
+ * A nop will ensure the descriptor polling active completed.
+ * CF Internal RAM has shorter cycle access than DRAM. If use
+ * DRAM as Buffer descriptor and data, a nop is a must.
+ * Affect only V2 and V3.
+ */
+ __asm__ ("nop");
+#endif
+
+#ifdef CONFIG_SYS_UNIFY_CACHE
+ icache_invalid();
+#endif
+
+ j = 0;
+ while ((info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_READY) &&
+ (j < info->to_loop)) {
+ udelay(1);
+ j++;
+ }
+ if (j >= info->to_loop)
+ printf("TX timeout\n");
+
+#ifdef ET_DEBUG
+ printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
+ __FILE__, __LINE__, __func__, j,
+ info->txbd[info->tx_idx].cbd_sc,
+ (info->txbd[info->tx_idx].cbd_sc & 0x003C) >> 2);
+#endif
+
+ /* return only status bits */
+ rc = (info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS);
+ info->tx_idx = (info->tx_idx + 1) % TX_BUF_CNT;
+
+ return rc;
+}
+
+static int mcffec_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct fec_info_s *info = dev->priv;
+ volatile fec_t *fecp = (fec_t *)info->iobase;
+ int length = -1;
+
+ for (;;) {
+#ifdef CONFIG_SYS_UNIFY_CACHE
+ icache_invalid();
+#endif
+ /* If nothing received - leave for() loop */
+ if (info->rxbd[info->rx_idx].cbd_sc & BD_ENET_RX_EMPTY)
+ break;
+
+ length = info->rxbd[info->rx_idx].cbd_datlen;
+
+ if (info->rxbd[info->rx_idx].cbd_sc & 0x003f) {
+ printf("%s[%d] err: %x\n",
+ __func__, __LINE__,
+ info->rxbd[info->rx_idx].cbd_sc);
+ } else {
+ length -= 4;
+
+ /*
+ * Pass the buffer ptr up to the protocol layers.
+ */
+ *packetp = net_rx_packets[info->rx_idx];
+
+ fecp->eir |= FEC_EIR_RXF;
+ }
+
+ /* Give the buffer back to the FEC. */
+ info->rxbd[info->rx_idx].cbd_datlen = 0;
+
+ /* wrap around buffer index when necessary */
+ if (info->rx_idx == LAST_PKTBUFSRX) {
+ info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E;
+ info->rx_idx = 0;
+ } else {
+ info->rxbd[info->rx_idx].cbd_sc = BD_ENET_RX_EMPTY;
+ info->rx_idx++;
+ }
+
+ /* Try to fill Buffer Descriptors
+ * Descriptor polling active
+ */
+ fecp->rdar = 0x01000000;
}
+
+ return length;
}
-void fec_halt(struct eth_device *dev)
+static void mcffec_halt(struct udevice *dev)
{
struct fec_info_s *info = dev->priv;
- fec_reset(dev);
+ fec_reset(info);
+ fecpin_setclear(info, 0);
- fecpin_setclear(dev, 0);
+ info->rx_idx = 0;
+ info->tx_idx = 0;
- info->rxIdx = info->txIdx = 0;
memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t));
memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
memset(info->txbuf, 0, DBUF_LENGTH);
}
-int mcffec_initialize(bd_t * bis)
+static const struct eth_ops mcffec_ops = {
+ .start = mcffec_init,
+ .send = mcffec_send,
+ .recv = mcffec_recv,
+ .stop = mcffec_halt,
+};
+
+/*
+ * Boot sequence, called just after mcffec_ofdata_to_platdata,
+ * as DM way, it replaces old mcffec_initialize.
+ */
+static int mcffec_probe(struct udevice *dev)
{
- struct eth_device *dev;
- int i;
-#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
- u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
-#endif
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct fec_info_s *info = dev->priv;
+ int node = dev_of_offset(dev);
+ int retval, fec_idx;
+ const u32 *val;
- for (i = 0; i < ARRAY_SIZE(fec_info); i++) {
+ info->index = dev->seq;
+ info->iobase = pdata->iobase;
+ info->phy_addr = -1;
- dev =
- (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
- sizeof *dev);
- if (dev == NULL)
- hang();
+ val = fdt_getprop(gd->fdt_blob, node, "mii-base", NULL);
+ if (val) {
+ u32 fec_iobase;
- memset(dev, 0, sizeof(*dev));
+ fec_idx = fdt32_to_cpu(*val);
+ if (fec_idx == info->index) {
+ fec_iobase = info->iobase;
+ } else {
+ printf("mii base != base address, fec_idx %d\n",
+ fec_idx);
+ retval = fec_get_base_addr(fec_idx, &fec_iobase);
+ if (retval)
+ return retval;
+ }
+ info->miibase = fec_iobase;
+ }
- sprintf(dev->name, "FEC%d", fec_info[i].index);
+ val = fdt_getprop(gd->fdt_blob, node, "phy-addr", NULL);
+ if (val)
+ info->phy_addr = fdt32_to_cpu(*val);
- dev->priv = &fec_info[i];
- dev->init = fec_init;
- dev->halt = fec_halt;
- dev->send = fec_send;
- dev->recv = fec_recv;
+ val = fdt_getprop(gd->fdt_blob, node, "timeout-loop", NULL);
+ if (val)
+ info->to_loop = fdt32_to_cpu(*val);
- /* setup Receive and Transmit buffer descriptor */
-#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
- fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
- tmp = (u32)fec_info[i].rxbd;
- fec_info[i].txbd =
- (cbd_t *)((u32)fec_info[i].txbd + tmp +
- (PKTBUFSRX * sizeof(cbd_t)));
- tmp = (u32)fec_info[i].txbd;
- fec_info[i].txbuf =
- (char *)((u32)fec_info[i].txbuf + tmp +
- (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
- tmp = (u32)fec_info[i].txbuf;
-#else
- fec_info[i].rxbd =
- (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
- (PKTBUFSRX * sizeof(cbd_t)));
- fec_info[i].txbd =
- (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
- (TX_BUF_CNT * sizeof(cbd_t)));
- fec_info[i].txbuf =
- (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
-#endif
+ init_eth_info(info);
-#ifdef ET_DEBUG
- printf("rxbd %x txbd %x\n",
- (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+ info->bus = mdio_alloc();
+ if (!info->bus)
+ return -ENOMEM;
+ strcpy(info->bus->name, dev->name);
+ info->bus->read = mcffec_miiphy_read;
+ info->bus->write = mcffec_miiphy_write;
+
+ retval = mdio_register(info->bus);
+ if (retval < 0)
+ return retval;
#endif
- fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
+ return 0;
+}
- eth_register(dev);
+static int mcffec_remove(struct udevice *dev)
+{
+ struct fec_info_s *priv = dev_get_priv(dev);
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = mcffec_miiphy_read;
- mdiodev->write = mcffec_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-#endif
- if (i > 0)
- fec_info[i - 1].next = &fec_info[i];
- }
- fec_info[i - 1].next = &fec_info[0];
+ mdio_unregister(priv->bus);
+ mdio_free(priv->bus);
+
+ return 0;
+}
+
+/*
+ * Boot sequence, called 1st
+ */
+static int mcffec_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ const u32 *val;
- /* default speed */
- bis->bi_ethspeed = 10;
+ pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
+ /* Default to 10Mbit/s */
+ pdata->max_speed = 10;
+
+ val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
+ "max-speed", NULL);
+ if (val)
+ pdata->max_speed = fdt32_to_cpu(*val);
return 0;
}
+
+static const struct udevice_id mcffec_ids[] = {
+ { .compatible = "fsl,mcf-fec" },
+ { }
+};
+
+U_BOOT_DRIVER(mcffec) = {
+ .name = "mcffec",
+ .id = UCLASS_ETH,
+ .of_match = mcffec_ids,
+ .ofdata_to_platdata = mcffec_ofdata_to_platdata,
+ .probe = mcffec_probe,
+ .remove = mcffec_remove,
+ .ops = &mcffec_ops,
+ .priv_auto_alloc_size = sizeof(struct fec_info_s),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
# define CONFIG_SYS_UNSPEC_STRID 0
#endif
-#ifdef CONFIG_MCF547x_8x
-typedef struct fec_info_dma FEC_INFO_T;
-#define FEC_T fecdma_t
-#else
-typedef struct fec_info_s FEC_INFO_T;
-#define FEC_T fec_t
-#endif
-
typedef struct phy_info_struct {
u32 phyid;
char *strid;
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
*/
-void mii_reset(FEC_INFO_T *info)
+void mii_reset(fec_info_t *info)
{
volatile FEC_T *fecp = (FEC_T *) (info->miibase);
int i;
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
- FEC_INFO_T *info;
- volatile FEC_T *ep;
+#ifdef CONFIG_DM_ETH
+ struct udevice *dev;
+#else
struct eth_device *dev;
+#endif
+ fec_info_t *info;
+ volatile FEC_T *ep;
uint mii_reply;
int j = 0;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
- while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
+ while (!(ep->eir & FEC_EIR_MII) && (j < info->to_loop)) {
udelay(1);
j++;
}
- if (j >= MCFFEC_TOUT_LOOP) {
+ if (j >= info->to_loop) {
printf("MII not complete\n");
return -1;
}
#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
#if defined(CONFIG_SYS_DISCOVER_PHY)
-int mii_discover_phy(struct eth_device *dev)
+int mii_discover_phy(fec_info_t *info)
{
#define MAX_PHY_PASSES 11
- FEC_INFO_T *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
int i, found = 0;
phytype = mii_send(mk_mii_read(phyno, MII_PHYSID1));
#ifdef ET_DEBUG
- printf("PHY type 0x%x pass %d type\n", phytype, pass);
+ printf("PHY type 0x%x pass %d\n", phytype, pass);
#endif
if (phytype == 0xffff)
continue;
void __mii_init(void)
{
- FEC_INFO_T *info;
- volatile FEC_T *fecp;
+#ifdef CONFIG_DM_ETH
+ struct udevice *dev;
+#else
struct eth_device *dev;
+#endif
+ fec_info_t *info;
+ volatile FEC_T *fecp;
int miispd = 0, i = 0;
u16 status = 0;
u16 linkgood = 0;
fecp = (FEC_T *) info->miibase;
- fecpin_setclear(dev, 1);
+ fecpin_setclear(info, 1);
mii_reset(info);
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
- info->phy_addr = mii_discover_phy(dev);
+#ifdef CONFIG_SYS_DISCOVER_PHY
+ info->phy_addr = mii_discover_phy(info);
+#endif
+ if (info->phy_addr == -1)
+ return;
- while (i < MCFFEC_TOUT_LOOP) {
+ while (i < info->to_loop) {
status = 0;
i++;
/* Read PHY control register */
udelay(1);
}
- if (i >= MCFFEC_TOUT_LOOP) {
+ if (i >= info->to_loop)
printf("Link UP timeout\n");
- }
/* adapt to the duplex and speed settings of the phy */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
The TWL4030 in a combination audio CODEC/power management with
GPIO and it is commonly used with the OMAP3 family of processors
+config POWER_MT6323
+ bool "Poweroff driver for mediatek mt6323"
+ select CMD_POWEROFF
+ help
+ This adds poweroff driver for mt6323
+ this pmic is used on mt7623 / Bananapi R2
+
endmenu
obj-$(CONFIG_POWER_FSL) += power_fsl.o
obj-$(CONFIG_POWER_I2C) += power_i2c.o
obj-$(CONFIG_POWER_SPI) += power_spi.o
+obj-$(CONFIG_POWER_MT6323) += mt6323.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Frank Wunderlich <frank-w@public-files.de>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#define PWRAP_BASE 0x1000d000
+#define PWRAP_WACS2_CMD 0x9c
+
+#define PWRAP_CALC(adr, wdata) ((1 << 31) | (((adr) >> 1) << 16) | (wdata))
+
+#define MT6323_PWRC_BASE 0x8000
+#define RTC_BBPU 0x0000
+#define RTC_BBPU_KEY (0x43 << 8)
+#define RTC_WRTGR 0x003c
+
+int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u32 addr, val;
+
+ addr = PWRAP_BASE + PWRAP_WACS2_CMD;
+ val = PWRAP_CALC(MT6323_PWRC_BASE + RTC_BBPU, RTC_BBPU_KEY);
+ writel(val, addr);
+
+ mdelay(10);
+
+ val = PWRAP_CALC(MT6323_PWRC_BASE + RTC_WRTGR, 1);
+ writel(val, addr);
+
+ // wait some time and then print error
+ mdelay(10000);
+ printf("Failed to power off!!!\n");
+ return 1;
+}
Support for Dallas Semiconductor (now Maxim) DS1307 and DS1338/9 and
compatible Real Time Clock devices.
+config RTC_DS3232
+ bool "Enable DS3232 driver"
+ depends on DM_RTC
+ depends on DM_I2C
+ help
+ Support for Dallas Semiconductor (now Maxim) DS3232 compatible
+ Real Time Clock devices.
+
config RTC_ISL1208
bool "Enable ISL1208 driver"
depends on DM_RTC
obj-$(CONFIG_RTC_DS164x) += ds164x.o
obj-$(CONFIG_RTC_DS174x) += ds174x.o
obj-$(CONFIG_RTC_DS3231) += ds3231.o
+obj-$(CONFIG_RTC_DS3232) += ds3232.o
obj-$(CONFIG_RTC_FTRTC010) += ftrtc010.o
obj-$(CONFIG_SANDBOX) += i2c_rtc_emul.o
obj-$(CONFIG_RTC_IMXDI) += imxdi.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019, Vaisala Oyj
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <i2c.h>
+#include <rtc.h>
+
+/*
+ * RTC register addresses
+ */
+#define RTC_SEC_REG_ADDR 0x00
+#define RTC_MIN_REG_ADDR 0x01
+#define RTC_HR_REG_ADDR 0x02
+#define RTC_DAY_REG_ADDR 0x03
+#define RTC_DATE_REG_ADDR 0x04
+#define RTC_MON_REG_ADDR 0x05
+#define RTC_YR_REG_ADDR 0x06
+#define RTC_CTL_REG_ADDR 0x0e
+#define RTC_STAT_REG_ADDR 0x0f
+#define RTC_TEST_REG_ADDR 0x13
+
+/*
+ * RTC control register bits
+ */
+#define RTC_CTL_BIT_A1IE BIT(0) /* Alarm 1 interrupt enable */
+#define RTC_CTL_BIT_A2IE BIT(1) /* Alarm 2 interrupt enable */
+#define RTC_CTL_BIT_INTCN BIT(2) /* Interrupt control */
+#define RTC_CTL_BIT_DOSC BIT(7) /* Disable Oscillator */
+
+/*
+ * RTC status register bits
+ */
+#define RTC_STAT_BIT_A1F BIT(0) /* Alarm 1 flag */
+#define RTC_STAT_BIT_A2F BIT(1) /* Alarm 2 flag */
+#define RTC_STAT_BIT_EN32KHZ BIT(3) /* Enable 32KHz Output */
+#define RTC_STAT_BIT_BB32KHZ BIT(6) /* Battery backed 32KHz Output */
+#define RTC_STAT_BIT_OSF BIT(7) /* Oscillator stop flag */
+
+/*
+ * RTC test register bits
+ */
+#define RTC_TEST_BIT_SWRST BIT(7) /* Software reset */
+
+#define RTC_DATE_TIME_REG_SIZE 7
+#define RTC_SRAM_START 0x14
+#define RTC_SRAM_END 0xFF
+#define RTC_SRAM_SIZE 236
+
+struct ds3232_priv_data {
+ u8 max_register;
+ u8 sram_start;
+ int sram_size;
+};
+
+static int ds3232_rtc_read8(struct udevice *dev, unsigned int reg)
+{
+ int ret;
+ u8 buf;
+ struct ds3232_priv_data *priv_data;
+
+ priv_data = dev_get_priv(dev);
+ if (!priv_data)
+ return -EINVAL;
+
+ if (reg > priv_data->max_register)
+ return -EINVAL;
+
+ ret = dm_i2c_read(dev, reg, &buf, sizeof(buf));
+ if (ret < 0)
+ return ret;
+
+ return buf;
+}
+
+static int ds3232_rtc_write8(struct udevice *dev, unsigned int reg, int val)
+{
+ u8 buf = (u8)val;
+ struct ds3232_priv_data *priv_data;
+
+ priv_data = dev_get_priv(dev);
+ if (!priv_data)
+ return -EINVAL;
+
+ if (reg > priv_data->max_register)
+ return -EINVAL;
+
+ return dm_i2c_write(dev, reg, &buf, sizeof(buf));
+}
+
+static int reset_sram(struct udevice *dev)
+{
+ int ret, sram_end, reg;
+ struct ds3232_priv_data *priv_data;
+
+ priv_data = dev_get_priv(dev);
+ if (!priv_data)
+ return -EINVAL;
+
+ sram_end = priv_data->sram_start + priv_data->sram_size;
+
+ for (reg = priv_data->sram_start; reg < sram_end; reg++) {
+ ret = ds3232_rtc_write8(dev, reg, 0x00);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int verify_osc(struct udevice *dev)
+{
+ int ret, rtc_status;
+
+ ret = ds3232_rtc_read8(dev, RTC_STAT_REG_ADDR);
+ if (ret < 0)
+ return ret;
+
+ rtc_status = ret;
+
+ if (rtc_status & RTC_STAT_BIT_OSF) {
+ dev_warn(dev,
+ "oscillator discontinuity flagged, time unreliable\n");
+ /*
+ * In case OSC was off we cannot trust the SRAM data anymore.
+ * Reset it to 0x00.
+ */
+ ret = reset_sram(dev);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ds3232_rtc_set(struct udevice *dev, const struct rtc_time *tm)
+{
+ u8 buf[RTC_DATE_TIME_REG_SIZE];
+ u8 is_century;
+
+ if (tm->tm_year < 1900 || tm->tm_year > 2099)
+ dev_warn(dev, "WARNING: year should be between 1900 and 2099!\n");
+
+ is_century = (tm->tm_year >= 2000) ? 0x80 : 0;
+
+ buf[RTC_SEC_REG_ADDR] = bin2bcd(tm->tm_sec);
+ buf[RTC_MIN_REG_ADDR] = bin2bcd(tm->tm_min);
+ buf[RTC_HR_REG_ADDR] = bin2bcd(tm->tm_hour);
+ buf[RTC_DAY_REG_ADDR] = bin2bcd(tm->tm_wday + 1);
+ buf[RTC_DATE_REG_ADDR] = bin2bcd(tm->tm_mday);
+ buf[RTC_MON_REG_ADDR] = bin2bcd(tm->tm_mon) | is_century;
+ buf[RTC_YR_REG_ADDR] = bin2bcd(tm->tm_year % 100);
+
+ return dm_i2c_write(dev, 0, buf, sizeof(buf));
+}
+
+static int ds3232_rtc_get(struct udevice *dev, struct rtc_time *tm)
+{
+ int ret;
+ u8 buf[RTC_DATE_TIME_REG_SIZE];
+ u8 is_twelve_hr;
+ u8 is_pm;
+ u8 is_century;
+
+ ret = verify_osc(dev);
+ if (ret < 0)
+ return ret;
+
+ ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
+ if (ret < 0)
+ return ret;
+
+ /* Extract additional information for AM/PM and century */
+ is_twelve_hr = buf[RTC_HR_REG_ADDR] & 0x40;
+ is_pm = buf[RTC_HR_REG_ADDR] & 0x20;
+ is_century = buf[RTC_MON_REG_ADDR] & 0x80;
+
+ tm->tm_sec = bcd2bin(buf[RTC_SEC_REG_ADDR] & 0x7F);
+ tm->tm_min = bcd2bin(buf[RTC_MIN_REG_ADDR] & 0x7F);
+
+ if (is_twelve_hr)
+ tm->tm_hour = bcd2bin(buf[RTC_HR_REG_ADDR] & 0x1F)
+ + (is_pm ? 12 : 0);
+ else
+ tm->tm_hour = bcd2bin(buf[RTC_HR_REG_ADDR]);
+
+ tm->tm_wday = bcd2bin((buf[RTC_DAY_REG_ADDR] & 0x07) - 1);
+ tm->tm_mday = bcd2bin(buf[RTC_DATE_REG_ADDR] & 0x3F);
+ tm->tm_mon = bcd2bin((buf[RTC_MON_REG_ADDR] & 0x7F));
+ tm->tm_year = bcd2bin(buf[RTC_YR_REG_ADDR])
+ + (is_century ? 2000 : 1900);
+ tm->tm_yday = 0;
+ tm->tm_isdst = 0;
+
+ return 0;
+}
+
+static int ds3232_rtc_reset(struct udevice *dev)
+{
+ int ret;
+
+ ret = reset_sram(dev);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * From datasheet
+ * (https://datasheets.maximintegrated.com/en/ds/DS3232M.pdf):
+ *
+ * The device reset occurs during the normal acknowledge time slot
+ * following the receipt of the data byte carrying that
+ * SWRST instruction a NACK occurs due to the resetting action.
+ *
+ * Therefore we don't verify the result of I2C write operation since it
+ * will fail due the NACK.
+ */
+ ds3232_rtc_write8(dev, RTC_TEST_REG_ADDR, RTC_TEST_BIT_SWRST);
+
+ return 0;
+}
+
+static int ds3232_probe(struct udevice *dev)
+{
+ int rtc_status;
+ int ret;
+ struct ds3232_priv_data *priv_data;
+
+ priv_data = dev_get_priv(dev);
+ if (!priv_data)
+ return -EINVAL;
+
+ priv_data->sram_start = RTC_SRAM_START;
+ priv_data->max_register = RTC_SRAM_END;
+ priv_data->sram_size = RTC_SRAM_SIZE;
+
+ ret = ds3232_rtc_read8(dev, RTC_STAT_REG_ADDR);
+ if (ret < 0)
+ return ret;
+
+ rtc_status = ret;
+
+ ret = verify_osc(dev);
+ if (ret < 0)
+ return ret;
+
+ rtc_status &= ~(RTC_STAT_BIT_OSF | RTC_STAT_BIT_A1F | RTC_STAT_BIT_A2F);
+
+ return ds3232_rtc_write8(dev, RTC_STAT_REG_ADDR, rtc_status);
+}
+
+static const struct rtc_ops ds3232_rtc_ops = {
+ .get = ds3232_rtc_get,
+ .set = ds3232_rtc_set,
+ .reset = ds3232_rtc_reset,
+ .read8 = ds3232_rtc_read8,
+ .write8 = ds3232_rtc_write8
+};
+
+static const struct udevice_id ds3232_rtc_ids[] = {
+ { .compatible = "dallas,ds3232" },
+ { }
+};
+
+U_BOOT_DRIVER(rtc_ds3232) = {
+ .name = "rtc-ds3232",
+ .id = UCLASS_RTC,
+ .probe = ds3232_probe,
+ .of_match = ds3232_rtc_ids,
+ .ops = &ds3232_rtc_ops,
+ .priv_auto_alloc_size = sizeof(struct ds3232_priv_data),
+};
return 0;
}
- /* Check devicd ID */
+ /* Check device ID */
uc_priv->device = readl(priv->base + VIRTIO_MMIO_DEVICE_ID);
if (uc_priv->device == 0) {
/*
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000
-#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_HAS_ETH1
-
-# define CONFIG_SYS_FEC0_PINMUX 0
-# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
/* Timer */
#define CONFIG_MCFTMR
-#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_SYS_I2C
/* Timer */
#define CONFIG_MCFTMR
-#undef CONFIG_MCFPIT
/* I2c */
#define CONFIG_SYS_I2C
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-# define CONFIG_SYS_FEC0_PINMUX 0
-# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
/* Timer */
#define CONFIG_MCFTMR
-#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_SYS_I2C
/*
* Command line configuration.
*/
-
-#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-# define CONFIG_SYS_FEC0_PINMUX 0
-# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
/* Available command configuration */
-#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#define CONFIG_MII_INIT 1
#define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_SYS_RX_ETH_BUFFER 8
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#define CONFIG_SYS_FEC0_PINMUX 0
-#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-#define CONFIG_SYS_FEC1_PINMUX 0
-#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
-#define MCFFEC_TOUT_LOOP 50000
#define CONFIG_HAS_ETH1
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#ifndef CONFIG_SYS_DISCOVER_PHY
/*
* Command line configuration.
*/
-
-#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-# define CONFIG_SYS_FEC0_PINMUX 0
-# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
#define CONFIG_SYS_UNIFY_CACHE
-#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_HAS_ETH1
-# define CONFIG_SYS_FEC0_PINMUX 0
-# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define CONFIG_SYS_FEC1_PINMUX 0
-# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
-
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
/* Timer */
#define CONFIG_MCFTMR
-#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_UNIFY_CACHE
-#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-# define CONFIG_SYS_FEC0_PINMUX 0
-# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
/* Timer */
#define CONFIG_MCFTMR
-#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_UNIFY_CACHE
-#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-# define CONFIG_SYS_FEC0_PINMUX 0
-# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
/* Timer */
#define CONFIG_MCFTMR
-#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_SYS_I2C
#endif
/* Network configuration */
-#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#define CONFIG_MII_INIT 1
#define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_SYS_TX_ETH_BUFFER 2
#define CONFIG_HAS_ETH1
-#define CONFIG_SYS_FEC0_PINMUX 0
-#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-#define CONFIG_SYS_FEC1_PINMUX 0
-#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
-#define MCFFEC_TOUT_LOOP 50000
-#define CONFIG_SYS_FEC0_PHYADDR 0
-#define CONFIG_SYS_FEC1_PHYADDR 1
-
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_IPADDR 192.168.1.2
#define CONFIG_NETMASK 255.255.255.0
/* Timer */
#define CONFIG_MCFTMR
-#undef CONFIG_MCFPIT
/* I2c */
#undef CONFIG_SYS_FSL_I2C
#define CONFIG_BOOTP_BOOTFILESIZE
/* Network configuration */
-#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-# define CONFIG_SYS_FEC0_PINMUX 0
-# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
-
# define CONFIG_ETHPRIME "FEC0"
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
/* Timer */
#define CONFIG_MCFTMR
-#undef CONFIG_MCFPIT
/* I2c */
#define CONFIG_SYS_I2C
#define CONFIG_BOOTP_BOOTFILESIZE
/* Network configuration */
-#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-# define CONFIG_SYS_FEC0_PINMUX 0
-# define CONFIG_SYS_FEC1_PINMUX 0
-# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
# define CONFIG_HAS_ETH1
-
# define CONFIG_ETHPRIME "FEC0"
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
/* Timer */
#define CONFIG_MCFTMR
-#undef CONFIG_MCFPIT
/* I2c */
#define CONFIG_SYS_I2C
#define CONFIG_SLTTMR
-#define CONFIG_FSLDMAFEC
#ifdef CONFIG_FSLDMAFEC
# define CONFIG_MII_INIT 1
# define CONFIG_HAS_ETH1
-
# define CONFIG_SYS_DMA_USE_INTSRAM 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 32
# define CONFIG_SYS_TX_ETH_BUFFER 48
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-# define CONFIG_SYS_FEC0_PINMUX 0
-# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define CONFIG_SYS_FEC1_PINMUX 0
-# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
-
-# define MCFFEC_TOUT_LOOP 50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
-
#endif
#ifdef CONFIG_CMD_USB
#define CONFIG_SLTTMR
-#define CONFIG_FSLDMAFEC
#ifdef CONFIG_FSLDMAFEC
# define CONFIG_MII_INIT 1
# define CONFIG_HAS_ETH1
-
# define CONFIG_SYS_DMA_USE_INTSRAM 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 32
# define CONFIG_SYS_TX_ETH_BUFFER 48
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-# define CONFIG_SYS_FEC0_PINMUX 0
-# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define CONFIG_SYS_FEC1_PINMUX 0
-# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
-
-# define MCFFEC_TOUT_LOOP 50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
-
#endif
#ifdef CONFIG_CMD_USB
/* Timer */
#define CONFIG_MCFTMR
-#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_CLK 66000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
-/* ---
- * Enable use of Ethernet
- * ---
- */
-#define CONFIG_MCFFEC
-
/* Enable Dma Timer */
#define CONFIG_MCFTMR
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-# define CONFIG_SYS_FEC0_PINMUX 0
-# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
* Network *
*----------------------------------------------------------------------*/
-#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
#define CONFIG_MII_INIT 1
#define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_SYS_RX_ETH_BUFFER 8
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-#define CONFIG_SYS_FEC0_PINMUX 0
-#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-#define MCFFEC_TOUT_LOOP 50000
-
#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif
/*-------------------------------------------------------------------------
* Low Level Configuration Settings
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
-/* KM_MGCOGE3UN */
-#elif defined(CONFIG_KM_MGCOGE3UN)
-#define CONFIG_HOSTNAME "mgcoge3un"
-#undef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
-#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0"
-#define CONFIG_KM_DISABLE_PCIE
-
/* KMCOGE5UN */
#elif defined(CONFIG_KM_COGE5UN)
#undef CONFIG_SYS_KWD_CONFIG
#ifdef CONFIG_KM_PIGGY4_88E6061
/*
- * Some keymile boards like mgcoge3un have their PIGGY4 connected via
+ * Some keymile boards like mgcoge5un have their PIGGY4 connected via
* an Marvell 88E6061 simple switch.
* In this case we have to change the default settings for the
* ethernet phy connected to the kirkwood.
/* Timer */
#define CONFIG_MCFTMR
-#undef CONFIG_MCFPIT
/* DSPI and Serial Flash */
#define CONFIG_CF_DSPI
#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 12)
+#ifdef CONFIG_MCFFEC
+#define CONFIG_MII_INIT 1
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_SYS_RX_ETH_BUFFER 8
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#ifndef CONFIG_SYS_DISCOVER_PHY
+#define FECDUPLEX FULL
+#define FECSPEED _100BASET
+#else
+#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#endif
+#endif /* CONFIG_SYS_DISCOVER_PHY */
+#endif
#endif /* __STMARK2_CONFIG_H */
CONFIG_KM_KIRKWOOD
CONFIG_KM_KIRKWOOD_128M16
CONFIG_KM_KIRKWOOD_PCI
-CONFIG_KM_MGCOGE3UN
CONFIG_KM_NEW_ENV
CONFIG_KM_NUSA
CONFIG_KM_ROOTFSSIZE
CONFIG_MCF5249
CONFIG_MCF5253
CONFIG_MCFFEC
-CONFIG_MCFPIT
CONFIG_MCFRTC
CONFIG_MCFTMR
CONFIG_MCLK_DIS
const char *test_name = test->name;
/* Remove the prefix */
- if (!strncmp(test_name, prefix, prefix_len))
+ if (prefix && !strncmp(test_name, prefix, prefix_len))
test_name += prefix_len;
if (argc > 1 && strcmp(argv[1], test_name))
{
if (params->auto_its)
return 0;
- return ((params->dflag && (params->fflag || params->lflag)) ||
- (params->fflag && (params->dflag || params->lflag)) ||
- (params->lflag && (params->dflag || params->fflag)));
+ return ((params->dflag && params->fflag) ||
+ (params->fflag && params->lflag) ||
+ (params->lflag && params->dflag));
}
U_BOOT_IMAGE_TYPE(
projects / platform / kernel / u-boot.git / commitdiff