LCDIF clock gate was wrong so set it according to RM.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
clk_dm(IMXRT1050_CLK_SEMC,
imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
clk_dm(IMXRT1050_CLK_LCDIF,
clk_dm(IMXRT1050_CLK_SEMC,
imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
clk_dm(IMXRT1050_CLK_LCDIF,
- imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
+ imx_clk_gate2("lcdif", "lcdif_podf", base + 0x74, 10));