Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx

diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index 77f9989..9b24a7e 100644 (file)
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -96,6 +96,23 @@ int board_early_init_f(void)
 
        gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
 
+       /*
+        * Reset PHY's:
+        * The PHY's need a 2nd reset pulse, since the MDIO address is latched
+        * upon reset, and with the first reset upon powerup, the addresses are
+        * not latched reliable, since the IRQ line is multiplexed with an
+        * MDIO address. A 2nd reset at this time will make sure, that the
+        * correct address is latched.
+        */
+       gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
+       gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
+       udelay(1000);
+       gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
+       gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
+       udelay(1000);
+       gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
+       gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
+
        return 0;
 }
 
@@ -231,15 +248,6 @@ int misc_init_r(void)
        out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
 
        /*
-        * Reset PHY's
-        */
-       gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
-       gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
-       udelay(100);
-       gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
-       gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
-
-       /*
         * Init display controller
         */
        /* Setup dot clock (internal PLL, division rate 1/16) */

diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 00c34d5..52deab4 100644 (file)
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -432,7 +432,7 @@
 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12                               */      \
 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13                               */      \
 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14                               */      \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15                               */      \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15                               */      \
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4)                     */      \
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5)                     */      \
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6)                     */      \
@@ -473,7 +473,7 @@
 {GPIO1_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit */      \
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit */      \
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit */      \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53  Unselect via TraceSelect Bit */      \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit */      \
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit */      \
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55  Unselect via TraceSelect Bit */      \
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit */      \