MPC8610HPCD_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8610hpcd freescale
+MPC8641HPCN_36BIT_config \
MPC8641HPCN_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale
+ @mkdir -p $(obj)include
+ @if [ "$(findstring _36BIT_,$@)" ] ; then \
+ echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \
+ $(XECHO) "... enabling 36-bit physical addressing." ; \
+ fi
+ @$(MKCONFIG) -a MPC8641HPCN ppc mpc86xx mpc8641hpcn freescale
sbc8641d_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc86xx sbc8641d
#include "../common/pixis.h"
void sdram_init(void);
-long int fixed_sdram(void);
+phys_size_t fixed_sdram(void);
void mpc8610hpcd_diu_init(void);
phys_size_t
initdram(int board_type)
{
- long dram_size = 0;
+ phys_size_t dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();
* Fixed sdram init -- doesn't use serial presence detect.
*/
-long int fixed_sdram(void)
+phys_size_t fixed_sdram(void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
# default CCSRBAR is at 0xff700000
# assume U-Boot is less than 0.5MB
#
-TEXT_BASE = 0xfff00000
+TEXT_BASE = 0xeff00000
PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
+ * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
- * 0xc000_0000 0xdfff_ffff RapidIO 512M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
- * 0xf800_0000 0xf80f_ffff CCSRBAR 1M
- * 0xf810_0000 0xf81f_ffff PIXIS 1M
- * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
+ * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
+ * 0x8000_0000 0x9fff_ffff RapidIO 512M
+ * endif
+ * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT)
+ * 0xffc0_0000 0xffc0_ffff PCI1 IO 64K
+ * 0xffc1_0000 0xffc1_ffff PCI2 IO 64K
+ * 0xffe0_0000 0xffef_ffff CCSRBAR 1M
+ * 0xffdf_0000 0xffe0_0000 PIXIS, CF 64K
+ * 0xef80_0000 0xefff_ffff FLASH (boot bank) 8M
*
* Notes:
- * CCSRBAR don't need a configured Local Access Window.
+ * CCSRBAR doesn't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
#if !defined(CONFIG_SPD_EEPROM)
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
#endif
- SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
- SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
- SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
- SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
- SET_LAW((CONFIG_SYS_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
+#ifdef CONFIG_PCI
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
+#elif defined(CONFIG_RIO)
+ SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+#endif
+ SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);
#include "../common/pixis.h"
-long int fixed_sdram(void);
+phys_size_t fixed_sdram(void);
int board_early_init_f(void)
{
phys_size_t
initdram(int board_type)
{
- long dram_size = 0;
+ phys_size_t dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
-long int
+phys_size_t
fixed_sdram(void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_fsl86xxads_config_table[] = {
- {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
- {}
-};
-#endif
-
-
-static struct pci_controller pci1_hose = {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc86xxcts_config_table
-#endif
-};
+static struct pci_controller pci1_hose;
#endif /* CONFIG_PCI */
#ifdef CONFIG_PCI2
void pci_init_board(void)
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- uint devdisr = gur->devdisr;
- uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
- >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
-
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
struct pci_controller *hose = &pci1_hose;
struct pci_region *r = hose->regions;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ uint devdisr = gur->devdisr;
+ uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
+ >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
#ifdef DEBUG
uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
void
ft_board_setup(void *blob, bd_t *bd)
{
+ int off;
+ u64 *tmp;
+ u32 *addrcells;
+
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI1
#ifdef CONFIG_PCI2
ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
#endif
+
+ /*
+ * Warn if it looks like the device tree doesn't match u-boot.
+ * This is just an estimation, based on the location of CCSR,
+ * which is defined by the "reg" property in the soc node.
+ */
+ off = fdt_path_offset(blob, "/soc8641");
+ addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
+ tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
+
+ if (tmp) {
+ u64 addr;
+ if (addrcells && (*addrcells == 1))
+ addr = *(u32 *)tmp;
+ else
+ addr = *tmp;
+
+ if (addr != CONFIG_SYS_CCSRBAR_PHYS)
+ printf("WARNING: The CCSRBAR address in your .dts "
+ "does not match the address of the CCSR "
+ "in u-boot. This means your .dts might "
+ "be old.\n");
+ }
}
#endif
START = start.o
SOBJS = cache.o
+ifneq ($(CONFIG_NUM_CPUS),1)
+COBJS-y += mp.o
+SOBJS += release.o
+endif
COBJS-y += traps.o
COBJS-y += cpu.o
COBJS-y += cpu_init.o
#include <mpc86xx.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
+#include "mp.h"
+
+void setup_bats(void);
DECLARE_GLOBAL_DATA_PTR;
init_laws();
#endif
+ setup_bats();
+
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
* addresses - these have to be modified later when FLASH size
* has been determined
*/
int cpu_init_r(void)
{
+#if (CONFIG_NUM_CPUS > 1)
+ setup_mp();
+#endif
return 0;
}
#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include "mp.h"
+
+DECLARE_GLOBAL_DATA_PTR;
void ft_cpu_setup(void *blob, bd_t *bd)
{
+#if (CONFIG_NUM_CPUS > 1)
+ int off;
+ u32 bootpg;
+#endif
+
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", bd->bi_busfreq / 4, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
do_fixup_by_compat_u32(blob, "ns16550",
"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
#endif
+
+#if (CONFIG_NUM_CPUS > 1)
+ /* if we have 4G or more of memory, put the boot page at 4Gb-1M */
+ if (gd->ram_size > 0xfffff000)
+ bootpg = 0xfff00000;
+ else
+ bootpg = gd->ram_size - (1024 * 1024);
+
+ /* Reserve the boot page so OSes dont use it */
+ off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
+ if (off < 0)
+ printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
+#endif
}
--- /dev/null
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <ioports.h>
+#include <lmb.h>
+#include <asm/io.h>
+#include "mp.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_NUM_CPUS > 1)
+void cpu_mp_lmb_reserve(struct lmb *lmb)
+{
+ u32 bootpg;
+
+ /* if we have 4G or more of memory, put the boot page at 4Gb-1M */
+ if ((u64)gd->ram_size > 0xfffff000)
+ bootpg = 0xfff00000;
+ else
+ bootpg = gd->ram_size - (1024 * 1024);
+
+ /* tell u-boot we stole a page */
+ lmb_reserve(lmb, bootpg, 4096);
+}
+
+/*
+ * Copy the code for other cpus to execute into an
+ * aligned location accessible via BPTR
+ */
+void setup_mp(void)
+{
+ extern ulong __secondary_start_page;
+ ulong fixup = (ulong)&__secondary_start_page;
+ u32 bootpg;
+ u32 bootpg_va;
+
+ /*
+ * If we have 4G or more of memory, put the boot page at 4Gb-1M.
+ * Otherwise, put it at the very end of RAM.
+ */
+ if (gd->ram_size > 0xfffff000)
+ bootpg = 0xfff00000;
+ else
+ bootpg = gd->ram_size - (1024 * 1024);
+
+ if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
+ /* We're not covered by the DDR mapping, set up BAT */
+ write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K |
+ BATU_VS | BATU_VP,
+ bootpg | BATL_PP_RW | BATL_MEMCOHERENCE);
+ bootpg_va = CONFIG_SYS_SCRATCH_VA;
+ } else {
+ bootpg_va = bootpg;
+ }
+
+ memcpy((void *)bootpg_va, (void *)fixup, 4096);
+ flush_cache(bootpg_va, 4096);
+
+ /* remove the temporary BAT mapping */
+ if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE)
+ write_bat(DBAT7, 0, 0);
+
+ /* If the physical location of bootpg is not at fff00000, set BPTR */
+ if (bootpg != 0xfff00000)
+ out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 |
+ (bootpg >> 12));
+}
+#endif
--- /dev/null
+#ifndef __MPC86XX_MP_H_
+#define __MPC86XX_MP_H_
+
+void setup_mp(void);
+void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+#endif
--- /dev/null
+/*
+ * Copyright 2004, 2007, 2008 Freescale Semiconductor.
+ * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <mpc86xx.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+/* If this is a multi-cpu system then we need to handle the
+ * 2nd cpu. The assumption is that the 2nd cpu is being
+ * held in boot holdoff mode until the 1st cpu unlocks it
+ * from Linux. We'll do some basic cpu init and then pass
+ * it to the Linux Reset Vector.
+ * Sri: Much of this initialization is not required. Linux
+ * rewrites the bats, and the sprs and also enables the L1 cache.
+ *
+ * Core 0 must copy this to a 1M aligned region and set BPTR
+ * to point to it.
+ */
+#if (CONFIG_NUM_CPUS > 1)
+ .align 12
+.globl __secondary_start_page
+__secondary_start_page:
+ .space 0x100 /* space over to reset vector loc */
+ mfspr r0, MSSCR0
+ andi. r0, r0, 0x0020
+ rlwinm r0,r0,27,31,31
+ mtspr PIR, r0
+
+ /* Invalidate BATs */
+ li r0, 0
+ mtspr IBAT0U, r0
+ mtspr IBAT1U, r0
+ mtspr IBAT2U, r0
+ mtspr IBAT3U, r0
+ mtspr IBAT4U, r0
+ mtspr IBAT5U, r0
+ mtspr IBAT6U, r0
+ mtspr IBAT7U, r0
+ isync
+ mtspr DBAT0U, r0
+ mtspr DBAT1U, r0
+ mtspr DBAT2U, r0
+ mtspr DBAT3U, r0
+ mtspr DBAT4U, r0
+ mtspr DBAT5U, r0
+ mtspr DBAT6U, r0
+ mtspr DBAT7U, r0
+ isync
+ sync
+
+ /* enable extended addressing */
+ mfspr r0, HID0
+ lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
+ ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
+ mtspr HID0, r0
+ sync
+ isync
+
+#ifdef CONFIG_SYS_L2
+ /* init the L2 cache */
+ addis r3, r0, L2_INIT@h
+ ori r3, r3, L2_INIT@l
+ sync
+ mtspr l2cr, r3
+#ifdef CONFIG_ALTIVEC
+ dssall
+#endif
+ /* invalidate the L2 cache */
+ mfspr r3, l2cr
+ rlwinm. r3, r3, 0, 0, 0
+ beq 1f
+
+ mfspr r3, l2cr
+ rlwinm r3, r3, 0, 1, 31
+
+#ifdef CONFIG_ALTIVEC
+ dssall
+#endif
+ sync
+ mtspr l2cr, r3
+ sync
+1: mfspr r3, l2cr
+ oris r3, r3, L2CR_L2I@h
+ mtspr l2cr, r3
+
+invl2:
+ mfspr r3, l2cr
+ andis. r3, r3, L2CR_L2I@h
+ bne invl2
+ sync
+#endif
+
+ /* enable and invalidate the data cache */
+ mfspr r3, HID0
+ li r5, HID0_DCFI|HID0_DLOCK
+ andc r3, r3, r5
+ mtspr HID0, r3 /* no invalidate, unlock */
+ ori r3, r3, HID0_DCE
+ ori r5, r3, HID0_DCFI
+ mtspr HID0, r5 /* enable + invalidate */
+ mtspr HID0, r3 /* enable */
+ sync
+#ifdef CFG_L2
+ sync
+ lis r3, L2_ENABLE@h
+ ori r3, r3, L2_ENABLE@l
+ mtspr l2cr, r3
+ isync
+ sync
+#endif
+
+ /* enable and invalidate the instruction cache*/
+ mfspr r3, HID0
+ li r5, HID0_ICFI|HID0_ILOCK
+ andc r3, r3, r5
+ ori r3, r3, HID0_ICE
+ ori r5, r3, HID0_ICFI
+ mtspr HID0, r5
+ mtspr HID0, r3
+ isync
+ sync
+
+ /* TBEN in HID0 */
+ mfspr r4, HID0
+ oris r4, r4, 0x0400
+ mtspr HID0, r4
+ sync
+ isync
+
+ /* MCP|SYNCBE|ABE in HID1 */
+ mfspr r4, HID1
+ oris r4, r4, 0x8000
+ ori r4, r4, 0x0C00
+ mtspr HID1, r4
+ sync
+ isync
+
+ lis r3, CONFIG_LINUX_RESET_VEC@h
+ ori r3, r3, CONFIG_LINUX_RESET_VEC@l
+ mtlr r3
+ blr
+
+ /* Never Returns, Running in Linux Now */
+#endif
boot_cold:
boot_warm:
-
- /* if this is a multi-core system we need to check which cpu
- * this is, if it is not cpu 0 send the cpu to the linux reset
- * vector */
-#if (CONFIG_NUM_CPUS > 1)
- mfspr r0, MSSCR0
- andi. r0, r0, 0x0020
- rlwinm r0,r0,27,31,31
- mtspr PIR, r0
- beq 1f
-
- bl secondary_cpu_setup
-#endif
-
+ /*
+ * NOTE: Only Cpu 0 will ever come here. Other cores go to an
+ * address specified by the BPTR
+ */
1:
#ifdef CONFIG_SYS_RAMBOOT
/* disable everything */
/*
* Calculate absolute address in FLASH and jump there
*------------------------------------------------------*/
- lis r3, CONFIG_SYS_MONITOR_BASE@h
- ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
+ lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h
+ ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l
addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r3
blr
*/
/* enable address translation */
- bl enable_addr_trans
- sync
+ mfmsr r5
+ ori r5, r5, (MSR_IR | MSR_DR)
+ lis r3,addr_trans_enabled@h
+ ori r3, r3, addr_trans_enabled@l
+ mtspr SPRN_SRR0,r3
+ mtspr SPRN_SRR1,r5
+ rfi
+addr_trans_enabled:
/* enable and invalidate the data cache */
/* bl l1dcache_enable */
bl dcache_enable
sync
#endif
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+ bl setup_ccsrbar
+#endif
+
/* set up the stack pointer in our newly created
* cache-ram (r1) */
lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
GET_GOT /* initialize GOT access */
- /* setup the rest of the bats */
- bl setup_bats
- sync
-
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
- /* setup ccsrbar */
- bl setup_ccsrbar
-#endif
-
/* run low-level CPU init code (from Flash) */
bl cpu_init_f
sync
#ifdef RUN_DIAG
/* Load PX_AUX register address in r4 */
- lis r4, 0xf810
+ lis r4, PIXIS_BASE@h
ori r4, r4, 0x6
/* Load contents of PX_AUX in r3 bits 24 to 31*/
lbz r3, 0(r4)
* early_bats:
*
* Set up bats needed early on - this is usually the BAT for the
- * stack-in-cache and the Flash
+ * stack-in-cache, the Flash, and CCSR space
*/
.globl early_bats
early_bats:
+ /* IBAT 3 */
+ lis r4, CONFIG_SYS_IBAT3L@h
+ ori r4, r4, CONFIG_SYS_IBAT3L@l
+ lis r3, CONFIG_SYS_IBAT3U@h
+ ori r3, r3, CONFIG_SYS_IBAT3U@l
+ mtspr IBAT3L, r4
+ mtspr IBAT3U, r3
+ isync
+
+ /* DBAT 3 */
+ lis r4, CONFIG_SYS_DBAT3L@h
+ ori r4, r4, CONFIG_SYS_DBAT3L@l
+ lis r3, CONFIG_SYS_DBAT3U@h
+ ori r3, r3, CONFIG_SYS_DBAT3U@l
+ mtspr DBAT3L, r4
+ mtspr DBAT3U, r3
+ isync
+
/* IBAT 5 */
lis r4, CONFIG_SYS_IBAT5L@h
ori r4, r4, CONFIG_SYS_IBAT5L@l
isync
/* IBAT 6 */
- lis r4, CONFIG_SYS_IBAT6L@h
- ori r4, r4, CONFIG_SYS_IBAT6L@l
- lis r3, CONFIG_SYS_IBAT6U@h
- ori r3, r3, CONFIG_SYS_IBAT6U@l
+ lis r4, CONFIG_SYS_IBAT6L_EARLY@h
+ ori r4, r4, CONFIG_SYS_IBAT6L_EARLY@l
+ lis r3, CONFIG_SYS_IBAT6U_EARLY@h
+ ori r3, r3, CONFIG_SYS_IBAT6U_EARLY@l
mtspr IBAT6L, r4
mtspr IBAT6U, r3
isync
/* DBAT 6 */
- lis r4, CONFIG_SYS_DBAT6L@h
- ori r4, r4, CONFIG_SYS_DBAT6L@l
- lis r3, CONFIG_SYS_DBAT6U@h
- ori r3, r3, CONFIG_SYS_DBAT6U@l
+ lis r4, CONFIG_SYS_DBAT6L_EARLY@h
+ ori r4, r4, CONFIG_SYS_DBAT6L_EARLY@l
+ lis r3, CONFIG_SYS_DBAT6U_EARLY@h
+ ori r3, r3, CONFIG_SYS_DBAT6U_EARLY@l
mtspr DBAT6L, r4
mtspr DBAT6U, r3
isync
+
+#if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+ /* IBAT 7 */
+ lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h
+ ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l
+ lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h
+ ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l
+ mtspr IBAT7L, r4
+ mtspr IBAT7U, r3
+ isync
+
+ /* DBAT 7 */
+ lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h
+ ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l
+ lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h
+ ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l
+ mtspr DBAT7L, r4
+ mtspr DBAT7U, r3
+ isync
+#endif
blr
.globl clear_tlbs
blt tlblp
blr
- .globl enable_addr_trans
-enable_addr_trans:
- /* enable address translation */
- mfmsr r5
- ori r5, r5, (MSR_IR | MSR_DR)
- mtmsr r5
- isync
- blr
-
.globl disable_addr_trans
disable_addr_trans:
/* disable address translation */
lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h
ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l
- lis r5, CONFIG_SYS_CCSRBAR@h
- ori r5, r5, CONFIG_SYS_CCSRBAR@l
- srwi r6,r5,12
- stw r6, 0(r4)
+ lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
+ ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
+ srwi r5,r5,12
+ li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
+ rlwimi r5,r6,20,8,11
+ stw r5, 0(r4) /* Store physical value of CCSR */
isync
- lis r5, 0xffff
- ori r5,r5,0xf000
+ lis r5, TEXT_BASE@h
+ ori r5,r5,TEXT_BASE@l
lwz r5, 0(r5)
isync
+ /* Use VA of CCSR to do read */
lis r3, CONFIG_SYS_CCSRBAR@h
lwz r5, CONFIG_SYS_CCSRBAR@l(r3)
isync
#endif
#endif
-/* If this is a multi-cpu system then we need to handle the
- * 2nd cpu. The assumption is that the 2nd cpu is being
- * held in boot holdoff mode until the 1st cpu unlocks it
- * from Linux. We'll do some basic cpu init and then pass
- * it to the Linux Reset Vector.
- * Sri: Much of this initialization is not required. Linux
- * rewrites the bats, and the sprs and also enables the L1 cache.
- */
-#if (CONFIG_NUM_CPUS > 1)
-.globl secondary_cpu_setup
-secondary_cpu_setup:
- /* Do only core setup on all cores except cpu0 */
- bl invalidate_bats
- sync
- bl enable_ext_addr
-
-#ifdef CONFIG_SYS_L2
- /* init the L2 cache */
- addis r3, r0, L2_INIT@h
- ori r3, r3, L2_INIT@l
- sync
- mtspr l2cr, r3
-#ifdef CONFIG_ALTIVEC
- dssall
-#endif
- /* invalidate the L2 cache */
- bl l2cache_invalidate
- sync
-#endif
- /* enable and invalidate the data cache */
- bl dcache_enable
- sync
-
- /* enable and invalidate the instruction cache*/
- bl icache_enable
- sync
-
- /* TBEN in HID0 */
- mfspr r4, HID0
- oris r4, r4, 0x0400
- mtspr HID0, r4
- sync
- isync
-
- /* MCP|SYNCBE|ABE in HID1 */
- mfspr r4, HID1
- oris r4, r4, 0x8000
- ori r4, r4, 0x0C00
- mtspr HID1, r4
- sync
- isync
-
- lis r3, CONFIG_LINUX_RESET_VEC@h
- ori r3, r3, CONFIG_LINUX_RESET_VEC@l
- mtlr r3
- blr
-
- /* Never Returns, Running in Linux Now */
-#endif
3. Flash U-Boot
---------------
-The flash range 0xFF800000 to 0xFFFFFFFF can be divided into 2 halves.
+The flash range 0xEF800000 to 0xEFFFFFFF can be divided into 2 halves.
It is possible to use either half to boot using u-boot. Switch 5 bit 2
is used for this purpose.
-0xFF800000 to 0xFFBFFFFF - 4MB
-0xFFC00000 to 0xFFFFFFFF - 4MB
-When this bit is 0, U-Boot is at 0xFFF00000.
-When this bit is 1, U-Boot is at 0xFFB00000.
+0xEF800000 to 0xEFBFFFFF - 4MB
+0xEFC00000 to 0xEFFFFFFF - 4MB
+When this bit is 0, U-Boot is at 0xEFF00000.
+When this bit is 1, U-Boot is at 0xEFB00000.
Use the above mentioned flash commands to program the other half, and
use switch 5, bit 2 to alternate between the halves. Note: The booting
-version of U-Boot will always be at 0xFFF00000.
+version of U-Boot will always be at 0xEFF00000.
-To Flash U-Boot into the booting bank (0xFFC00000 - 0xFFFFFFFF):
+To Flash U-Boot into the booting bank (0xEFC00000 - 0xEFFFFFFF):
tftp 1000000 u-boot.bin
protect off all
- erase fff00000 +$filesize
- cp.b 1000000 fff00000 $filesize
+ erase eff00000 +$filesize
+ cp.b 1000000 eff00000 $filesize
or use tftpflash command:
run tftpflash
-To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF):
+To Flash U-boot into the alternative bank (0xEF800000 - 0xEFBFFFFF):
tftp 1000000 u-boot.bin
- erase ffb00000 +$filesize
- cp.b 1000000 ffb00000 $filesize
+ erase efb00000 +$filesize
+ cp.b 1000000 efb00000 $filesize
4. Memory Map
-------------
+NOTE: RIO and PCI are mutually exclusive, so they share an address
+
+For 32-bit u-boot, devices are mapped so that the virtual address ==
+the physical address, and the map looks liks this:
Memory Range Device Size
------------ ------ ----
0x0000_0000 0x7fff_ffff DDR 2G
+ 0x8000_0000 0x9fff_ffff RIO MEM 512M
0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M
- 0xa000_0000 0xafff_ffff PCI2/PEX2 MEM 512M
- 0xf800_0000 0xf80f_ffff CCSR 1M
- 0xf810_0000 0xf81f_ffff PIXIS 1M
+ 0xa000_0000 0xbfff_ffff PCI2/PEX2 MEM 512M
+ 0xffe0_0000 0xffef_ffff CCSR 1M
+ 0xffdf_0000 0xffdf_7fff PIXIS 8K
+ 0xffdf_8000 0xffdf_ffff CF 8K
0xf840_0000 0xf840_3fff Stack space 32K
- 0xe200_0000 0xe2ff_ffff PCI1/PEX1 IO 16M
- 0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 16M
- 0xfe00_0000 0xfeff_ffff Flash(alternate)16M
- 0xff00_0000 0xffff_ffff Flash(boot bank)16M
+ 0xffc0_0000 0xffc0_ffff PCI1/PEX1 IO 64K
+ 0xffc1_0000 0xffc1_ffff PCI2/PEX2 IO 64K
+ 0xef80_0000 0xefff_ffff Flash 8M
+
+For 36-bit-enabled u-boot, the virtual map is the same as for 32-bit.
+However, the physical map is altered to reside in 36-bit space, as follows.
+Addresses are no longer mapped with VA == PA. All accesses from
+software use the VA; the PA is only used for setting up windows
+and mappings. Note that the low 32 bits are the same as the VA above;
+only the top 4 bits vary:
+
+ Memory Range Device Size
+ ------------ ------ ----
+ 0x0_0000_0000 0x0_7fff_ffff DDR 2G
+ 0xc_8000_0000 0xc_9fff_ffff RIO MEM 512M
+ 0xc_8000_0000 0xc_9fff_ffff PCI1/PEX1 MEM 512M
+ 0xc_a000_0000 0xc_bfff_ffff PCI2/PEX2 MEM 512M
+ 0xf_ffe0_0000 0xf_ffef_ffff CCSR 1M
+ 0xf_ffdf_0000 0xf_ffdf_7fff PIXIS 8K
+ 0xf_ffdf_8000 0xf_ffdf_ffff CF 8K
+ 0x0_f840_0000 0xf_f840_3fff Stack space 32K
+ 0xf_ffc0_0000 0xf_ffc0_ffff PCI1/PEX1 IO 64K
+ 0xf_ffc1_0000 0xf_ffc1_ffff PCI2/PEX2 IO 64K
+ 0xf_ef80_0000 0xf_efff_ffff Flash 8M
5. pixis_reset command
--------------------
#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
+/*
+ * virtual address to be used for temporary mappings. There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA 0xc0000000
+
#define CONFIG_PCI 1 /* Enable PCI/PCIE*/
#define CONFIG_PCI1 1 /* PCI controler 1 */
#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM
#define MPC86xx_DDR_SDRAM_CLK_CNTL
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
/*
- * BAT3 32M Cache-inhibited, guarded
- * 0xe200_0000 1M PCI-Express 2 I/O
- * 0xe300_0000 1M PCI-Express 1 I/O
+ * BAT3 4M Cache-inhibited, guarded
+ * 0xe000_0000 4M CCSR
*/
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
/*
- * BAT4 4M Cache-inhibited, guarded
- * 0xe000_0000 4M CCSR
+ * BAT4 32M Cache-inhibited, guarded
+ * 0xe200_0000 1M PCI-Express 2 I/O
+ * 0xe300_0000 1M PCI-Express 1 I/O
*/
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
+
+#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
+
/*
* BAT5 128K Cacheable, non-guarded
* 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
+
/*
* BAT7 4M Cache-inhibited, guarded
* 0xe800_0000 4M PIXIS
#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
+/*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */
#ifdef RUN_DIAG
-#define CONFIG_SYS_DIAG_ADDR 0xff800000
+#define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
#endif
#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
+/*
+ * virtual address to be used for temporary mappings. There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA 0xe0000000
+
+/*
+ * set this to enable Rapid IO. PCI and RIO are mutually exclusive
+ */
+/*#define CONFIG_RIO 1*/
+
+#ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */
#define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
+#endif
#define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_SYS_MEMTEST_END 0x00400000
/*
+ * With the exception of PCI Memory and Rapid IO, most devices will simply
+ * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
+ * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
+ */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL
+#else
+#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0
+#endif
+
+/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
-#define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
+/* Physical addresses */
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
+#define CONFIG_SYS_CCSRBAR_PHYS (CONFIG_SYS_CCSRBAR_PHYS_LOW \
+ | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32))
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
+#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
+#endif
+
#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM
#define MPC86xx_DDR_SDRAM_CLK_CNTL
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-/*
- * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000.
- * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff
- * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff.
- * However, when u-boot comes up, the flash_init needs hard start addresses
- * to build its info table. For user convenience, the flash addresses is
- * fe800000 and ff800000. That way, u-boot knows where the flash is
- * and the user can download u-boot code from promjet to fef00000, a
- * more intuitive location than fe700000.
- *
- * Note that, on switching the boot location, fef00000 becomes fff00000.
- */
-#define CONFIG_SYS_FLASH_BASE 0xfe800000 /* start of FLASH 32M */
-#define CONFIG_SYS_FLASH_BASE2 0xff800000
+#define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
+#define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \
+ | CONFIG_SYS_PHYS_ADDR_HIGH)
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
-#define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */
-#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_BR1_PRELIM 0xfe001001 /* port size 16bit */
-#define CONFIG_SYS_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/
+/* Convert an address into the right format for the BR registers */
+#ifdef CONFIG_PHYS_64BIT
+#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
+ ((x & 0x300000000ULL) >> 19)))
+#else
+#define BR_PHYS_ADDR(x) (x & 0xffff8000)
+#endif
+
+#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+ | 0x00001001) /* port size 16bit */
+#define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
-#define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
-#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
+#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
+ | 0x00001001) /* port size 16bit */
+#define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
-#define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
+#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
+ | 0x00000801) /* port size 8bit */
+#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
+/*
+ * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
+ * The PIXIS and CF by themselves aren't large enough to take up the 128k
+ * required for the smallest BAT mapping, so there's a 64k hole.
+ */
+#define CONFIG_SYS_LBC_BASE 0xffde0000
+#define CONFIG_SYS_LBC_BASE_PHYS (CONFIG_SYS_LBC_BASE \
+ | CONFIG_SYS_PHYS_ADDR_HIGH)
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
-#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
+#define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
+#define PIXIS_BASE_PHYS (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000)
+#define PIXIS_SIZE 0x00008000 /* 32k */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
+#define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
+#define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
/*
* RapidIO MMU
*/
-#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
+#define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_RIO_MEM_PHYS 0x0000000c00000000ULL
+#else
#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
+#endif
#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
/*
* Addresses are mapped 1-1.
*/
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL
+#else
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#endif
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
+#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
+#define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \
+ | CONFIG_SYS_PHYS_ADDR_HIGH)
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */
/* For RTL8139 */
#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
#define _IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MEM_BASE \
+ + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \
+ + CONFIG_SYS_PCI1_MEM_SIZE)
#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000
-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
+#define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \
+ + CONFIG_SYS_PCI1_IO_SIZE)
+#define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \
+ + CONFIG_SYS_PCI1_IO_SIZE)
+#define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE
#if defined(CONFIG_PCI)
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xe0000000
- #define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
-#endif
-
/*PCIE video card used*/
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_PHYS
+#define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_VIRT
/*PCI video card used*/
-/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/
+/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
/* video */
#define CONFIG_VIDEO
#define CONFIG_ATI_RADEON_FB
#define CONFIG_VIDEO_LOGO
/*#define CONFIG_CONSOLE_CURSOR*/
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_PHYS
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_TSEC_ENET */
+/* Contort an addr into the format needed for BATs */
+#ifdef CONFIG_PHYS_64BIT
+#define BAT_PHYS_ADDR(x) ((unsigned long) \
+ ((x & 0x00000000ffffffffULL) | \
+ ((x & 0x0000000e00000000ULL) >> 24) | \
+ ((x & 0x0000000100000000ULL) >> 30)))
+#else
+#define BAT_PHYS_ADDR(x) (x)
+#endif
+
+
+/* Put high physical address bits into the BAT format */
+#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
+#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
+
/*
- * BAT0 2G Cacheable, non-guarded
- * 0x0000_0000 2G DDR
+ * BAT0 DDR
*/
#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
/*
- * BAT1 1G Cache-inhibited, guarded
- * 0x8000_0000 512M PCI-Express 1 Memory
- * 0xa000_0000 512M PCI-Express 2 Memory
- * Changed it for operating from 0xd0000000
+ * BAT1 LBC (PIXIS/CF)
*/
-#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT | \
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
+ | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
+ | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
-/*
- * BAT2 512M Cache-inhibited, guarded
- * 0xc000_0000 512M RapidIO Memory
+/* if CONFIG_PCI:
+ * BAT2 PCI1 and PCI1 MEM
+ * if CONFIG_RIO
+ * BAT2 Rapidio Memory
*/
+#ifdef CONFIG_PCI
+#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_1G \
+ | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+#else /* CONFIG_RIO */
+#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT | \
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \
+ | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT)
+
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+#endif
/*
- * BAT3 4M Cache-inhibited, guarded
- * 0xf800_0000 4M CCSR
+ * BAT3 CCSR Space
+ * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs
+ * instead. The assembler chokes on ULL.
*/
-#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \
+ | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+ | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \
+ | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+ | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
/*
- * BAT4 32M Cache-inhibited, guarded
- * 0xe200_0000 16M PCI-Express 1 I/O
- * 0xe300_0000 16M PCI-Express 2 I/0
- * Note that this is at 0xe0000000
+ * BAT4 PCI1_IO and PCI2_IO
*/
-#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \
+ | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
/*
- * BAT5 128K Cacheable, non-guarded
- * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
+ * BAT5 Init RAM for stack in the CPU DCache (no backing memory)
*/
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
/*
- * BAT6 32M Cache-inhibited, guarded
- * 0xfe00_0000 32M FLASH
+ * BAT6 FLASH
*/
-#define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+ | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
+
+/*
+ * BAT7 FREE - used later for tmp mappings
+ */
#define CONFIG_SYS_DBAT7L 0x00000000
#define CONFIG_SYS_DBAT7U 0x00000000
#define CONFIG_SYS_IBAT7L 0x00000000
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
- #define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
#endif
+#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
"ramdiskfile=your.ramdisk.u-boot\0" \
"fdtaddr=c00000\0" \
"fdtfile=mpc8641_hpcn.dtb\0" \
- "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
- "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+ "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
+ "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
"maxcpus=2"
#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
+/*
+ * virtual address to be used for temporary mappings. There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA 0xe8000000
+
#define CONFIG_PCI 1 /* Enable PCIE */
#define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */
#define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */
#define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM
#define MPC86xx_DDR_SDRAM_CLK_CNTL
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
+
#define CONFIG_SYS_DBAT7L 0x00000000
#define CONFIG_SYS_DBAT7U 0x00000000
#define CONFIG_SYS_IBAT7L 0x00000000
WATCHDOG_RESET ();
+ /*
+ * Setup trap handlers
+ */
+ trap_init (dest_addr);
+
#if defined(CONFIG_BOARD_EARLY_INIT_R)
board_early_init_r ();
#endif
asm ("sync ; isync");
- /*
- * Setup trap handlers
- */
- trap_init (dest_addr);
-
#if !defined(CONFIG_SYS_NO_FLASH)
puts ("FLASH: ");
projects / platform / kernel / u-boot.git / commitdiff