ARM: tegra: move CONFIG_TEGRAnn
authorStephen Warren <swarren@nvidia.com>
Mon, 3 Feb 2014 21:03:24 +0000 (14:03 -0700)
committerTom Warren <twarren@nvidia.com>
Wed, 5 Mar 2014 23:59:07 +0000 (16:59 -0700)
<asm/arch-tegra/tegra.h> needs to use CONFIG_TEGRA* to conditionalize
some definitions, since some modules moved between generations. Move
the definition of CONFIG_TEGRAnn to a header that's included earlier,
so that it's set by the time tegra.h needs to use it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
arch/arm/include/asm/arch-tegra114/tegra.h
arch/arm/include/asm/arch-tegra124/tegra.h
arch/arm/include/asm/arch-tegra20/tegra.h
arch/arm/include/asm/arch-tegra30/tegra.h
include/configs/tegra114-common.h
include/configs/tegra124-common.h
include/configs/tegra20-common.h
include/configs/tegra30-common.h

index 5d426b5..705ca57 100644 (file)
@@ -17,6 +17,8 @@
 #ifndef _TEGRA114_H_
 #define _TEGRA114_H_
 
+#define CONFIG_TEGRA114
+
 #define NV_PA_SDRAM_BASE       0x80000000      /* 0x80000000 for real T114 */
 #define NV_PA_TSC_BASE         0x700F0000      /* System Counter TSC regs */
 
index db3d837..86ebd19 100644 (file)
@@ -8,6 +8,8 @@
 #ifndef _TEGRA124_H_
 #define _TEGRA124_H_
 
+#define CONFIG_TEGRA124
+
 #define NV_PA_SDRAM_BASE       0x80000000
 #define NV_PA_TSC_BASE         0x700F0000      /* System Counter TSC regs */
 #define NV_PA_MC_BASE          0x70019000      /* Mem Ctlr regs (MCB, etc.) */
index 18856ac..6a4b40e 100644 (file)
@@ -8,6 +8,8 @@
 #ifndef _TEGRA20_H_
 #define _TEGRA20_H_
 
+#define CONFIG_TEGRA20
+
 #define NV_PA_SDRAM_BASE       0x00000000
 
 #include <asm/arch-tegra/tegra.h>
index c02c5d8..4ad8b1c 100644 (file)
@@ -17,6 +17,8 @@
 #ifndef _TEGRA30_H_
 #define _TEGRA30_H_
 
+#define CONFIG_TEGRA30
+
 #define NV_PA_SDRAM_BASE       0x80000000      /* 0x80000000 for real T30 */
 
 #include <asm/arch-tegra/tegra.h>
index a4e8a5f..1bf5af5 100644 (file)
  */
 #define V_NS16550_CLK          408000000       /* 408MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA114                        /* in a NVidia Tegra114 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR                0x80408000      /* def. location for kernel */
 
index 0a4541b..4568bc7 100644 (file)
  */
 #define V_NS16550_CLK          408000000       /* 408MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA124                        /* is an NVIDIA Tegra124 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR                0x80408000      /* def. location for kernel */
 
index b009a31..d2c4532 100644 (file)
  */
 #define V_NS16550_CLK          216000000       /* 216MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA20                         /* in a NVidia Tegra20 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR                0x00408000      /* def. location for kernel */
 
index b5550d7..edb930e 100644 (file)
  */
 #define V_NS16550_CLK          408000000       /* 408MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA30                 /* in a NVidia Tegra30 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR                0x80408000      /* def. location for kernel */