LIB = $(obj)lib$(BOARD).a
-COBJS-y := $(BOARD).o iopin.o
+COBJS-y := $(BOARD).o
COBJS-${CONFIG_FSL_DIU_FB} += ads5121_diu.o
COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_diu_fb.o
COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_logo_bmp.o
#include <common.h>
#include <mpc512x.h>
-#include "iopin.h"
#include <asm/bitops.h>
#include <command.h>
#include <fdt_support.h>
#ifdef CONFIG_MISC_INIT_R
#include <i2c.h>
#endif
-#include "iopin.h" /* for iopin_initialize() prototype */
/* Clocks in use */
#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
u32 i;
/* Initialize IO Control */
- im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR;
+ im->io_ctrl.regs[IOCTL_MEM/4] = IOCTRL_MUX_DDR;
/* Initialize DDR Local Window */
im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
return 0;
}
+static iopin_t ioregs_init[] = {
+ /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
+ {
+ IOCTL_SPDIF_TXCLK, 3, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* Set highest Slew on 9 PATA pins */
+ {
+ IOCTL_PATA_CE1, 9, 1,
+ IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
+ {
+ IOCTL_PSC0_0, 15, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=SPDIF_TXCLK */
+ {
+ IOCTL_LPC_CS1, 1, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+ },
+ /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
+ {
+ IOCTL_I2C1_SCL, 2, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+ },
+ /* FUNC2=DIU CLK */
+ {
+ IOCTL_PSC6_0, 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+ },
+ /* FUNC2=DIU_HSYNC */
+ {
+ IOCTL_PSC6_1, 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
+ {
+ IOCTL_PSC6_4, 26, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ }
+};
int checkboard (void)
{
printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
brd_rev, cpld_rev);
/* initialize function mux & slew rate IO inter alia on IO Pins */
- iopin_initialize();
+
+
+ iopin_initialize(ioregs_init, sizeof(ioregs_init) / sizeof(ioregs_init[0]));
return 0;
}
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com
- * mpc512x I/O pin/pad initialization for the ADS5121 board
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <linux/types.h>
-#include "iopin.h"
-
-/* IO pin fields */
-#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */
-#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */
-#define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */
-#define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */
-#define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */
-#define IO_PIN_DS(v) ((v)) /* slew rate */
-
-static struct iopin_t {
- int p_offset; /* offset from IOCTL_MEM_OFFSET */
- int nr_pins; /* number of pins to set this way */
- int bit_or; /* or in the value instead of overwrite */
- u_long val; /* value to write or or */
-} ioregs_init[] = {
- /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
- {
- IOCTL_SPDIF_TXCLK, 3, 0,
- IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
- IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
- },
- /* Set highest Slew on 9 PATA pins */
- {
- IOCTL_PATA_CE1, 9, 1,
- IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
- IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
- },
- /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
- {
- IOCTL_PSC0_0, 15, 0,
- IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
- IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
- },
- /* FUNC1=SPDIF_TXCLK */
- {
- IOCTL_LPC_CS1, 1, 0,
- IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
- IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
- },
- /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
- {
- IOCTL_I2C1_SCL, 2, 0,
- IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
- IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
- },
- /* FUNC2=DIU CLK */
- {
- IOCTL_PSC6_0, 1, 0,
- IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
- IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
- },
- /* FUNC2=DIU_HSYNC */
- {
- IOCTL_PSC6_1, 1, 0,
- IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
- IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
- },
- /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
- {
- IOCTL_PSC6_4, 26, 0,
- IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
- IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
- }
-};
-
-void iopin_initialize(void)
-{
- short i, j, n, p;
- u_long *reg;
- immap_t *im = (immap_t *)CFG_IMMR;
-
- reg = (u_long *)&(im->io_ctrl.regs[0]);
-
- if (sizeof(ioregs_init) == 0)
- return;
-
- n = sizeof(ioregs_init) / sizeof(ioregs_init[0]);
-
- for (i = 0; i < n; i++) {
- for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
- p < ioregs_init[i].nr_pins; p++, j++) {
- if (ioregs_init[i].bit_or)
- reg[j] |= ioregs_init[i].val;
- else
- reg[j] = ioregs_init[i].val;
- }
- }
- return;
-}
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com
- * mpc512x I/O pin/pad initialization for the ADS5121 board
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#define IOCTL_MEM 0x000
-#define IOCTL_GP 0x004
-#define IOCTL_LPC_CLK 0x008
-#define IOCTL_LPC_OE 0x00C
-#define IOCTL_LPC_RWB 0x010
-#define IOCTL_LPC_ACK 0x014
-#define IOCTL_LPC_CS0 0x018
-#define IOCTL_NFC_CE0 0x01C
-#define IOCTL_LPC_CS1 0x020
-#define IOCTL_LPC_CS2 0x024
-#define IOCTL_LPC_AX03 0x028
-#define IOCTL_EMB_AX02 0x02C
-#define IOCTL_EMB_AX01 0x030
-#define IOCTL_EMB_AX00 0x034
-#define IOCTL_EMB_AD31 0x038
-#define IOCTL_EMB_AD30 0x03C
-#define IOCTL_EMB_AD29 0x040
-#define IOCTL_EMB_AD28 0x044
-#define IOCTL_EMB_AD27 0x048
-#define IOCTL_EMB_AD26 0x04C
-#define IOCTL_EMB_AD25 0x050
-#define IOCTL_EMB_AD24 0x054
-#define IOCTL_EMB_AD23 0x058
-#define IOCTL_EMB_AD22 0x05C
-#define IOCTL_EMB_AD21 0x060
-#define IOCTL_EMB_AD20 0x064
-#define IOCTL_EMB_AD19 0x068
-#define IOCTL_EMB_AD18 0x06C
-#define IOCTL_EMB_AD17 0x070
-#define IOCTL_EMB_AD16 0x074
-#define IOCTL_EMB_AD15 0x078
-#define IOCTL_EMB_AD14 0x07C
-#define IOCTL_EMB_AD13 0x080
-#define IOCTL_EMB_AD12 0x084
-#define IOCTL_EMB_AD11 0x088
-#define IOCTL_EMB_AD10 0x08C
-#define IOCTL_EMB_AD09 0x090
-#define IOCTL_EMB_AD08 0x094
-#define IOCTL_EMB_AD07 0x098
-#define IOCTL_EMB_AD06 0x09C
-#define IOCTL_EMB_AD05 0x0A0
-#define IOCTL_EMB_AD04 0x0A4
-#define IOCTL_EMB_AD03 0x0A8
-#define IOCTL_EMB_AD02 0x0AC
-#define IOCTL_EMB_AD01 0x0B0
-#define IOCTL_EMB_AD00 0x0B4
-#define IOCTL_PATA_CE1 0x0B8
-#define IOCTL_PATA_CE2 0x0BC
-#define IOCTL_PATA_ISOLATE 0x0C0
-#define IOCTL_PATA_IOR 0x0C4
-#define IOCTL_PATA_IOW 0x0C8
-#define IOCTL_PATA_IOCHRDY 0x0CC
-#define IOCTL_PATA_INTRQ 0x0D0
-#define IOCTL_PATA_DRQ 0x0D4
-#define IOCTL_PATA_DACK 0x0D8
-#define IOCTL_NFC_WP 0x0DC
-#define IOCTL_NFC_RB 0x0E0
-#define IOCTL_NFC_ALE 0x0E4
-#define IOCTL_NFC_CLE 0x0E8
-#define IOCTL_NFC_WE 0x0EC
-#define IOCTL_NFC_RE 0x0F0
-#define IOCTL_PCI_AD31 0x0F4
-#define IOCTL_PCI_AD30 0x0F8
-#define IOCTL_PCI_AD29 0x0FC
-#define IOCTL_PCI_AD28 0x100
-#define IOCTL_PCI_AD27 0x104
-#define IOCTL_PCI_AD26 0x108
-#define IOCTL_PCI_AD25 0x10C
-#define IOCTL_PCI_AD24 0x110
-#define IOCTL_PCI_AD23 0x114
-#define IOCTL_PCI_AD22 0x118
-#define IOCTL_PCI_AD21 0x11C
-#define IOCTL_PCI_AD20 0x120
-#define IOCTL_PCI_AD19 0x124
-#define IOCTL_PCI_AD18 0x128
-#define IOCTL_PCI_AD17 0x12C
-#define IOCTL_PCI_AD16 0x130
-#define IOCTL_PCI_AD15 0x134
-#define IOCTL_PCI_AD14 0x138
-#define IOCTL_PCI_AD13 0x13C
-#define IOCTL_PCI_AD12 0x140
-#define IOCTL_PCI_AD11 0x144
-#define IOCTL_PCI_AD10 0x148
-#define IOCTL_PCI_AD09 0x14C
-#define IOCTL_PCI_AD08 0x150
-#define IOCTL_PCI_AD07 0x154
-#define IOCTL_PCI_AD06 0x158
-#define IOCTL_PCI_AD05 0x15C
-#define IOCTL_PCI_AD04 0x160
-#define IOCTL_PCI_AD03 0x164
-#define IOCTL_PCI_AD02 0x168
-#define IOCTL_PCI_AD01 0x16C
-#define IOCTL_PCI_AD00 0x170
-#define IOCTL_PCI_CBE0 0x174
-#define IOCTL_PCI_CBE1 0x178
-#define IOCTL_PCI_CBE2 0x17C
-#define IOCTL_PCI_CBE3 0x180
-#define IOCTL_PCI_GNT2 0x184
-#define IOCTL_PCI_REQ2 0x188
-#define IOCTL_PCI_GNT1 0x18C
-#define IOCTL_PCI_REQ1 0x190
-#define IOCTL_PCI_GNT0 0x194
-#define IOCTL_PCI_REQ0 0x198
-#define IOCTL_PCI_INTA 0x19C
-#define IOCTL_PCI_CLK 0x1A0
-#define IOCTL_PCI_RST_OUT 0x1A4
-#define IOCTL_PCI_FRAME 0x1A8
-#define IOCTL_PCI_IDSEL 0x1AC
-#define IOCTL_PCI_DEVSEL 0x1B0
-#define IOCTL_PCI_IRDY 0x1B4
-#define IOCTL_PCI_TRDY 0x1B8
-#define IOCTL_PCI_STOP 0x1BC
-#define IOCTL_PCI_PAR 0x1C0
-#define IOCTL_PCI_PERR 0x1C4
-#define IOCTL_PCI_SERR 0x1C8
-#define IOCTL_SPDIF_TXCLK 0x1CC
-#define IOCTL_SPDIF_TX 0x1D0
-#define IOCTL_SPDIF_RX 0x1D4
-#define IOCTL_I2C0_SCL 0x1D8
-#define IOCTL_I2C0_SDA 0x1DC
-#define IOCTL_I2C1_SCL 0x1E0
-#define IOCTL_I2C1_SDA 0x1E4
-#define IOCTL_I2C2_SCL 0x1E8
-#define IOCTL_I2C2_SDA 0x1EC
-#define IOCTL_IRQ0 0x1F0
-#define IOCTL_IRQ1 0x1F4
-#define IOCTL_CAN1_TX 0x1F8
-#define IOCTL_CAN2_TX 0x1FC
-#define IOCTL_J1850_TX 0x200
-#define IOCTL_J1850_RX 0x204
-#define IOCTL_PSC_MCLK_IN 0x208
-#define IOCTL_PSC0_0 0x20C
-#define IOCTL_PSC0_1 0x210
-#define IOCTL_PSC0_2 0x214
-#define IOCTL_PSC0_3 0x218
-#define IOCTL_PSC0_4 0x21C
-#define IOCTL_PSC1_0 0x220
-#define IOCTL_PSC1_1 0x224
-#define IOCTL_PSC1_2 0x228
-#define IOCTL_PSC1_3 0x22C
-#define IOCTL_PSC1_4 0x230
-#define IOCTL_PSC2_0 0x234
-#define IOCTL_PSC2_1 0x238
-#define IOCTL_PSC2_2 0x23C
-#define IOCTL_PSC2_3 0x240
-#define IOCTL_PSC2_4 0x244
-#define IOCTL_PSC3_0 0x248
-#define IOCTL_PSC3_1 0x24C
-#define IOCTL_PSC3_2 0x250
-#define IOCTL_PSC3_3 0x254
-#define IOCTL_PSC3_4 0x258
-#define IOCTL_PSC4_0 0x25C
-#define IOCTL_PSC4_1 0x260
-#define IOCTL_PSC4_2 0x264
-#define IOCTL_PSC4_3 0x268
-#define IOCTL_PSC4_4 0x26C
-#define IOCTL_PSC5_0 0x270
-#define IOCTL_PSC5_1 0x274
-#define IOCTL_PSC5_2 0x278
-#define IOCTL_PSC5_3 0x27C
-#define IOCTL_PSC5_4 0x280
-#define IOCTL_PSC6_0 0x284
-#define IOCTL_PSC6_1 0x288
-#define IOCTL_PSC6_2 0x28C
-#define IOCTL_PSC6_3 0x290
-#define IOCTL_PSC6_4 0x294
-#define IOCTL_PSC7_0 0x298
-#define IOCTL_PSC7_1 0x29C
-#define IOCTL_PSC7_2 0x2A0
-#define IOCTL_PSC7_3 0x2A4
-#define IOCTL_PSC7_4 0x2A8
-#define IOCTL_PSC8_0 0x2AC
-#define IOCTL_PSC8_1 0x2B0
-#define IOCTL_PSC8_2 0x2B4
-#define IOCTL_PSC8_3 0x2B8
-#define IOCTL_PSC8_4 0x2BC
-#define IOCTL_PSC9_0 0x2C0
-#define IOCTL_PSC9_1 0x2C4
-#define IOCTL_PSC9_2 0x2C8
-#define IOCTL_PSC9_3 0x2CC
-#define IOCTL_PSC9_4 0x2D0
-#define IOCTL_PSC10_0 0x2D4
-#define IOCTL_PSC10_1 0x2D8
-#define IOCTL_PSC10_2 0x2DC
-#define IOCTL_PSC10_3 0x2E0
-#define IOCTL_PSC10_4 0x2E4
-#define IOCTL_PSC11_0 0x2E8
-#define IOCTL_PSC11_1 0x2EC
-#define IOCTL_PSC11_2 0x2F0
-#define IOCTL_PSC11_3 0x2F4
-#define IOCTL_PSC11_4 0x2F8
-#define IOCTL_HRESET 0x2FC
-#define IOCTL_SRESET 0x300
-#define IOCTL_CKSTP_OUT 0x304
-#define IOCTL_USB2_VBUS_PWR_FAULT 0x308
-#define IOCTL_USB2_VBUS_PWR_SELECT 0x30C
-#define IOCTL_USB2_PHY_DRVV_BUS 0x310
-
-extern void iopin_initialize(void);
rd_noffset = fit_conf_get_ramdisk_node (fit_hdr, cfg_noffset);
if (rd_noffset < 0) {
debug ("* ramdisk: no ramdisk in config\n");
- return 1;
+ return 0;
}
}
#endif
sprintf (info, "%s (%s - %s) ", U_BOOT_VERSION, __DATE__, __TIME__);
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y, (uchar *)info, strlen(info));
- sprintf (info, "(C) 2004 DENX Software Engineering");
+ sprintf (info, "(C) 2008 DENX Software Engineering GmbH");
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT,
(uchar *)info, strlen(info));
LIB = $(obj)lib$(CPU).a
START = start.o
-COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o
+COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o iopin.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
#endif
#ifdef CONFIG_OF_LIBFDT
-void ft_cpu_setup(void *blob, bd_t *bd)
+
+#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
+/*
+ * fdt setup for old device trees
+ * fix up
+ * cpu clocks
+ * soc clocks
+ * ethernet addresses
+ */
+static void old_ft_cpu_setup(void *blob, bd_t *bd)
+{
+ /*
+ * avoid fixing up by path because that
+ * produces scary error messages
+ */
+
+ /*
+ * old device trees have ethernet nodes with
+ * device_type = "network"
+ */
+ do_fixup_by_prop(blob, "device_type", "network", 8,
+ "local-mac-address", bd->bi_enetaddr, 6, 0);
+ do_fixup_by_prop(blob, "device_type", "network", 8,
+ "address", bd->bi_enetaddr, 6, 0);
+ /*
+ * old device trees have soc nodes with
+ * device_type = "soc"
+ */
+ do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
+ "bus-frequency", bd->bi_ipsfreq, 0);
+}
+#endif
+
+static void ft_clock_setup(void *blob, bd_t *bd)
{
+ int node;
char *cpu_path = "/cpus/" OF_CPU;
- char *eth_path = "/" OF_SOC "/ethernet@2800";
- char *eth_path_old = "/" OF_SOC_OLD "/ethernet@2800";
-
- do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
- do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
- do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
- do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipsfreq, 1);
- do_fixup_by_path(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0);
-
- /* this is so old kernels with old device trees will boot */
- do_fixup_by_path_u32(blob, "/" OF_SOC_OLD, "bus-frequency", bd->bi_ipsfreq, 0);
- do_fixup_by_path(blob, eth_path_old, "local-mac-address",
- bd->bi_enetaddr, 6, 0);
- do_fixup_by_path(blob, eth_path_old, "address", bd->bi_enetaddr, 6, 0);
+ const char *path = NULL;
+
+ /*
+ * fixup cpu clocks using path
+ */
+ do_fixup_by_path_u32(blob, cpu_path,
+ "timebase-frequency", OF_TBCLK, 1);
+ do_fixup_by_path_u32(blob, cpu_path,
+ "bus-frequency", bd->bi_busfreq, 1);
+ do_fixup_by_path_u32(blob, cpu_path,
+ "clock-frequency", bd->bi_intfreq, 1);
+ /*
+ * fixup soc clocks using compatible
+ */
+ do_fixup_by_compat_u32(blob, OF_SOC_COMPAT,
+ "bus-frequency", bd->bi_ipsfreq, 1);
+}
+
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
+ old_ft_cpu_setup(blob, bd);
+#endif
+ ft_clock_setup(blob, bd);
+#ifdef CONFIG_HAS_ETH0
+ fdt_fixup_ethernet(blob, bd);
+#endif
}
#endif
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com
+ * mpc512x I/O pin/pad initialization for the ADS5121 board
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <mpc512x.h>
+
+void iopin_initialize(iopin_t *ioregs_init, int len)
+{
+ short i, j, n, p;
+ u_long *reg;
+ immap_t *im = (immap_t *)CFG_IMMR;
+
+ reg = (u_long *)&(im->io_ctrl.regs[0]);
+
+ if (sizeof(ioregs_init) == 0)
+ return;
+
+ for (i = 0; i < len; i++) {
+ for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
+ p < ioregs_init[i].nr_pins; p++, j++) {
+ if (ioregs_init[i].bit_or)
+ reg[j] |= ioregs_init[i].val;
+ else
+ reg[j] = ioregs_init[i].val;
+ }
+ }
+ return;
+}
/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
#ifdef CFG_MAX_FLASH_BANKS_DETECT
-static ulong bank_base[CFG_MAX_FLASH_BANKS_DETECT] = CFG_FLASH_BANKS_LIST;
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */
+# define CFI_MAX_FLASH_BANKS CFG_MAX_FLASH_BANKS_DETECT
#else
-static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */
+# define CFI_MAX_FLASH_BANKS CFG_MAX_FLASH_BANKS
#endif
+flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */
+
/*
* Check if chip width is defined. If not, start detecting with 8bit.
*/
char *s = getenv("unlock");
#endif
+#define BANK_BASE(i) (((unsigned long [CFI_MAX_FLASH_BANKS])CFG_FLASH_BANKS_LIST)[i])
+
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
- if (!flash_detect_legacy (bank_base[i], i))
- flash_get_size (bank_base[i], i);
+ if (!flash_detect_legacy (BANK_BASE(i), i))
+ flash_get_size (BANK_BASE(i), i);
size += flash_info[i].size;
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
#ifndef CFG_FLASH_QUIET_TEST
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/fps850L/uImage\0" \
+ "hostname=FPS850L\0" \
+ "bootfile=FPS850L/uImage\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
+ "u-boot=FPS850L/u-image.bin\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=prot off 40000000 +${filesize};" \
+ "era 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
+#define CONFIG_NETCONSOLE
+
+
/*
* Miscellaneous configurable options
*/
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
+
+#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
+ "128k(dtb)," \
+ "1664k(kernel)," \
+ "2m(rootfs)," \
+ "4m(data)"
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
/*
- * (C) Copyright 2000-2005
+ * (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/fps850L/uImage\0" \
+ "hostname=FPS860L\0" \
+ "bootfile=FPS860L/uImage\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
+ "u-boot=FPS860L/u-image.bin\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=prot off 40000000 +${filesize};" \
+ "era 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
+#define CONFIG_NETCONSOLE
+
+
/*
* Miscellaneous configurable options
*/
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
+
+#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
+ "128k(dtb)," \
+ "1664k(kernel)," \
+ "2m(rootfs)," \
+ "4m(data)"
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
- OR_SCY_5_CLK | OR_EHTR)
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
+ OR_SCY_3_CLK | OR_EHTR | OR_BI)
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
/*
* Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ * gclk CPU clock (not bus clock!)
+ * Trefresh Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096 Rows from SDRAM example configuration
+ * 1000 factor s -> ms
+ * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4 Number of refresh cycles per period
+ * 64 Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider = 98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
*/
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
+#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA 98
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
+ * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
+ */
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_SCC1_ENET
+
#endif /* __CONFIG_H */
/*
- * (C) Copyright 2000-2005
+ * (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/NSCU/uImage\0" \
+ "hostname=NSCU\0" \
+ "bootfile=${hostname}/uImage\0" \
"kernel_addr=40080000\0" \
"ramdisk_addr=40180000\0" \
+ "u-boot=${hostname}/u-image.bin\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=prot off 40000000 +${filesize};" \
+ "era 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
+#define CONFIG_NETCONSOLE
+
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if 0
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history
+*/
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
-#endif
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
+#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
-#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
/*
- * (C) Copyright 2000-2005
+ * (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
#ifdef CONFIG_LCD /* with LCD controller ? */
+#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */
+#define CONFIG_LCD_INFO 1 /* ... and some board info */
#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
#endif
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/TQM823L/uImage\0" \
+ "hostname=TQM823L\0" \
+ "bootfile=TQM823L/uImage\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
+ "u-boot=TQM823L/u-image.bin\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=prot off 40000000 +${filesize};" \
+ "era 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#endif
+#define CONFIG_NETCONSOLE
+
/*
* Miscellaneous configurable options
*/
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
+
+#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
+ "128k(dtb)," \
+ "1664k(kernel)," \
+ "2m(rootfs)," \
+ "4m(data)"
+
+/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
/*
- * (C) Copyright 2000-2005
+ * (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/TQM823M/uImage\0" \
+ "hostname=TQM823M\0" \
+ "bootfile=TQM823M/uImage\0" \
"fdt_addr=40080000\0" \
"kernel_addr=400A0000\0" \
"ramdisk_addr=40280000\0" \
+ "u-boot=TQM823M/u-image.bin\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=prot off 40000000 +${filesize};" \
+ "era 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
+#define CONFIG_NETCONSOLE
+
+
/*
* Miscellaneous configurable options
*/
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
+
+#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
+ "128k(dtb)," \
+ "1920k(kernel)," \
+ "5632(rootfs)," \
+ "4m(data)"
+
+/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
/*
- * (C) Copyright 2000-2005
+ * (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/TQM850L/uImage\0" \
+ "hostname=TQM850L\0" \
+ "bootfile=TQM850L/uImage\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
+ "u-boot=TQM850L/u-image.bin\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=prot off 40000000 +${filesize};" \
+ "era 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
+#define CONFIG_NETCONSOLE
+
/*
* Miscellaneous configurable options
*/
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
+
+#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
+ "128k(dtb)," \
+ "1664k(kernel)," \
+ "2m(rootfs)," \
+ "4m(data)"
+
+/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
/*
- * (C) Copyright 2000-2005
+ * (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/TQM850M/uImage\0" \
+ "hostname=TQM850M\0" \
+ "bootfile=TQM850M/uImage\0" \
"fdt_addr=40080000\0" \
"kernel_addr=400A0000\0" \
"ramdisk_addr=40280000\0" \
+ "u-boot=TQM850M/u-image.bin\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=prot off 40000000 +${filesize};" \
+ "era 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
+#define CONFIG_NETCONSOLE
+
+
/*
* Miscellaneous configurable options
*/
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
+
+#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
+ "128k(dtb)," \
+ "1920k(kernel)," \
+ "5632(rootfs)," \
+ "4m(data)"
+
+/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
/*
- * (C) Copyright 2000-2005
+ * (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/TQM855L/uImage\0" \
+ "hostname=TQM855L\0" \
+ "bootfile=TQM855L/uImage\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
+ "u-boot=TQM855L/u-image.bin\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=prot off 40000000 +${filesize};" \
+ "era 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
+#define CONFIG_NETCONSOLE
+
+
/*
* Miscellaneous configurable options
*/
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
+
+#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
+ "128k(dtb)," \
+ "1664k(kernel)," \
+ "2m(rootfs)," \
+ "4m(data)"
+
+/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
/*
- * (C) Copyright 2000-2005
+ * (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/TQM855M/uImage\0" \
+ "hostname=TQM855M\0" \
+ "bootfile=TQM855M/uImage\0" \
"fdt_addr=40080000\0" \
"kernel_addr=400A0000\0" \
"ramdisk_addr=40280000\0" \
+ "u-boot=TQM855M/u-image.bin\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=prot off 40000000 +${filesize};" \
+ "era 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
+#define CONFIG_NETCONSOLE
+
+
/*
* Miscellaneous configurable options
*/
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
+
+#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
+ "128k(dtb)," \
+ "1920k(kernel)," \
+ "5632(rootfs)," \
+ "4m(data)"
+
+/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
/*
- * (C) Copyright 2000-2005
+ * (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/TQM860L/uImage\0" \
+ "hostname=TQM860L\0" \
+ "bootfile=TQM860L/uImage\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
+ "u-boot=TQM860L/u-image.bin\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=prot off 40000000 +${filesize};" \
+ "era 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
+
+#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
+ "128k(dtb)," \
+ "1664k(kernel)," \
+ "2m(rootfs)," \
+ "4m(data)"
+
+/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/TQM860M/uImage\0" \
+ "hostname=TQM860M\0" \
+ "bootfile=TQM860M/uImage\0" \
"fdt_addr=400C0000\0" \
"kernel_addr=40100000\0" \
"ramdisk_addr=40280000\0" \
+ "u-boot=TQM860M/u-image.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
- "update=protect off 40000000 +${filesize};" \
- "erase 40000000 +${filesize};" \
+ "update=prot off 40000000 +${filesize};" \
+ "era 40000000 +${filesize};" \
"cp.b 200000 40000000 ${filesize};" \
- "protect on 40000000 +${filesize}\0" \
+ "sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
+#define CONFIG_NETCONSOLE
+
+
/*
* Miscellaneous configurable options
*/
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
+
+#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
+ "128k(dtb)," \
+ "1920k(kernel)," \
+ "5632(rootfs)," \
+ "4m(data)"
+
+/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
/*
- * (C) Copyright 2000-2005
+ * (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/TQM862L/uImage\0" \
+ "hostname=TQM862L\0" \
+ "bootfile=TQM862L/uImage\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
+ "u-boot=TQM862L/u-image.bin\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=prot off 40000000 +${filesize};" \
+ "era 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
+#define CONFIG_NETCONSOLE
+
+
/*
* Miscellaneous configurable options
*/
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
+
+#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
+ "128k(dtb)," \
+ "1664k(kernel)," \
+ "2m(rootfs)," \
+ "4m(data)"
+
+/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/TQM862M/uImage\0" \
+ "hostname=TQM862M\0" \
+ "bootfile=TQM862M/uImage\0" \
"fdt_addr=40080000\0" \
"kernel_addr=400A0000\0" \
"ramdisk_addr=40280000\0" \
+ "u-boot=TQM862M/u-image.bin\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=prot off 40000000 +${filesize};" \
+ "era 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
+#define CONFIG_NETCONSOLE
+
+
/*
* Miscellaneous configurable options
*/
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
+
+#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
+ "128k(dtb)," \
+ "1920k(kernel)," \
+ "5632(rootfs)," \
+ "4m(data)"
+
+/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/TQM866M/uImage\0" \
+ "hostname=TQM866M\0" \
+ "bootfile=TQM866M/uImage\0" \
"fdt_addr=400C0000\0" \
"kernel_addr=40100000\0" \
"ramdisk_addr=40280000\0" \
+ "u-boot=TQM866M/u-image.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
- "update=protect off 40000000 +${filesize};" \
- "erase 40000000 +${filesize};" \
+ "update=prot off 40000000 +${filesize};" \
+ "era 40000000 +${filesize};" \
"cp.b 200000 40000000 ${filesize};" \
- "protect on 40000000 +${filesize}\0" \
+ "sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
+#define CONFIG_CMD_ELF
#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+#define CONFIG_NETCONSOLE
/*
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
+
+#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
+ "128k(dtb)," \
+ "1920k(kernel)," \
+ "5632(rootfs)," \
+ "4m(data)"
+
+/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
#define CONFIG_PHY_ADDR 0x1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_FEC_AN_TIMEOUT 1
+#define CONFIG_HAS_ETH0
/*
* Configure on-board RTC
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
#define OF_CPU "PowerPC,5121@0"
-#define OF_SOC "soc@80000000"
-#define OF_SOC_OLD "soc5121@80000000"
+#define OF_SOC_COMPAT "fsl,mpc5121-immr"
#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
/*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#define CONFIG_VIRTLAB2 1 /* ...on a virtlab2 module */
#define CONFIG_TQM8xxL 1
-#ifdef CONFIG_LCD /* with LCD controller ? */
-#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
-#endif
-
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/TQM823L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "hostname=virtlab2\0" \
+ "bootfile=virtlab2/uImage\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
+ "u-boot=virtlab2/u-image.bin\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=prot off 40000000 +${filesize};" \
+ "era 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#endif
+#define CONFIG_NETCONSOLE
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if 0
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
-#endif
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
+
+#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
+ "128k(dtb)," \
+ "1664k(kernel)," \
+ "2m(rootfs)," \
+ "4m(data)"
+
+/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
/* IO Control Register
*/
+#define IOCTL_MEM 0x000
+#define IOCTL_GP 0x004
+#define IOCTL_LPC_CLK 0x008
+#define IOCTL_LPC_OE 0x00C
+#define IOCTL_LPC_RWB 0x010
+#define IOCTL_LPC_ACK 0x014
+#define IOCTL_LPC_CS0 0x018
+#define IOCTL_NFC_CE0 0x01C
+#define IOCTL_LPC_CS1 0x020
+#define IOCTL_LPC_CS2 0x024
+#define IOCTL_LPC_AX03 0x028
+#define IOCTL_EMB_AX02 0x02C
+#define IOCTL_EMB_AX01 0x030
+#define IOCTL_EMB_AX00 0x034
+#define IOCTL_EMB_AD31 0x038
+#define IOCTL_EMB_AD30 0x03C
+#define IOCTL_EMB_AD29 0x040
+#define IOCTL_EMB_AD28 0x044
+#define IOCTL_EMB_AD27 0x048
+#define IOCTL_EMB_AD26 0x04C
+#define IOCTL_EMB_AD25 0x050
+#define IOCTL_EMB_AD24 0x054
+#define IOCTL_EMB_AD23 0x058
+#define IOCTL_EMB_AD22 0x05C
+#define IOCTL_EMB_AD21 0x060
+#define IOCTL_EMB_AD20 0x064
+#define IOCTL_EMB_AD19 0x068
+#define IOCTL_EMB_AD18 0x06C
+#define IOCTL_EMB_AD17 0x070
+#define IOCTL_EMB_AD16 0x074
+#define IOCTL_EMB_AD15 0x078
+#define IOCTL_EMB_AD14 0x07C
+#define IOCTL_EMB_AD13 0x080
+#define IOCTL_EMB_AD12 0x084
+#define IOCTL_EMB_AD11 0x088
+#define IOCTL_EMB_AD10 0x08C
+#define IOCTL_EMB_AD09 0x090
+#define IOCTL_EMB_AD08 0x094
+#define IOCTL_EMB_AD07 0x098
+#define IOCTL_EMB_AD06 0x09C
+#define IOCTL_EMB_AD05 0x0A0
+#define IOCTL_EMB_AD04 0x0A4
+#define IOCTL_EMB_AD03 0x0A8
+#define IOCTL_EMB_AD02 0x0AC
+#define IOCTL_EMB_AD01 0x0B0
+#define IOCTL_EMB_AD00 0x0B4
+#define IOCTL_PATA_CE1 0x0B8
+#define IOCTL_PATA_CE2 0x0BC
+#define IOCTL_PATA_ISOLATE 0x0C0
+#define IOCTL_PATA_IOR 0x0C4
+#define IOCTL_PATA_IOW 0x0C8
+#define IOCTL_PATA_IOCHRDY 0x0CC
+#define IOCTL_PATA_INTRQ 0x0D0
+#define IOCTL_PATA_DRQ 0x0D4
+#define IOCTL_PATA_DACK 0x0D8
+#define IOCTL_NFC_WP 0x0DC
+#define IOCTL_NFC_RB 0x0E0
+#define IOCTL_NFC_ALE 0x0E4
+#define IOCTL_NFC_CLE 0x0E8
+#define IOCTL_NFC_WE 0x0EC
+#define IOCTL_NFC_RE 0x0F0
+#define IOCTL_PCI_AD31 0x0F4
+#define IOCTL_PCI_AD30 0x0F8
+#define IOCTL_PCI_AD29 0x0FC
+#define IOCTL_PCI_AD28 0x100
+#define IOCTL_PCI_AD27 0x104
+#define IOCTL_PCI_AD26 0x108
+#define IOCTL_PCI_AD25 0x10C
+#define IOCTL_PCI_AD24 0x110
+#define IOCTL_PCI_AD23 0x114
+#define IOCTL_PCI_AD22 0x118
+#define IOCTL_PCI_AD21 0x11C
+#define IOCTL_PCI_AD20 0x120
+#define IOCTL_PCI_AD19 0x124
+#define IOCTL_PCI_AD18 0x128
+#define IOCTL_PCI_AD17 0x12C
+#define IOCTL_PCI_AD16 0x130
+#define IOCTL_PCI_AD15 0x134
+#define IOCTL_PCI_AD14 0x138
+#define IOCTL_PCI_AD13 0x13C
+#define IOCTL_PCI_AD12 0x140
+#define IOCTL_PCI_AD11 0x144
+#define IOCTL_PCI_AD10 0x148
+#define IOCTL_PCI_AD09 0x14C
+#define IOCTL_PCI_AD08 0x150
+#define IOCTL_PCI_AD07 0x154
+#define IOCTL_PCI_AD06 0x158
+#define IOCTL_PCI_AD05 0x15C
+#define IOCTL_PCI_AD04 0x160
+#define IOCTL_PCI_AD03 0x164
+#define IOCTL_PCI_AD02 0x168
+#define IOCTL_PCI_AD01 0x16C
+#define IOCTL_PCI_AD00 0x170
+#define IOCTL_PCI_CBE0 0x174
+#define IOCTL_PCI_CBE1 0x178
+#define IOCTL_PCI_CBE2 0x17C
+#define IOCTL_PCI_CBE3 0x180
+#define IOCTL_PCI_GNT2 0x184
+#define IOCTL_PCI_REQ2 0x188
+#define IOCTL_PCI_GNT1 0x18C
+#define IOCTL_PCI_REQ1 0x190
+#define IOCTL_PCI_GNT0 0x194
+#define IOCTL_PCI_REQ0 0x198
+#define IOCTL_PCI_INTA 0x19C
+#define IOCTL_PCI_CLK 0x1A0
+#define IOCTL_PCI_RST_OUT 0x1A4
+#define IOCTL_PCI_FRAME 0x1A8
+#define IOCTL_PCI_IDSEL 0x1AC
+#define IOCTL_PCI_DEVSEL 0x1B0
+#define IOCTL_PCI_IRDY 0x1B4
+#define IOCTL_PCI_TRDY 0x1B8
+#define IOCTL_PCI_STOP 0x1BC
+#define IOCTL_PCI_PAR 0x1C0
+#define IOCTL_PCI_PERR 0x1C4
+#define IOCTL_PCI_SERR 0x1C8
+#define IOCTL_SPDIF_TXCLK 0x1CC
+#define IOCTL_SPDIF_TX 0x1D0
+#define IOCTL_SPDIF_RX 0x1D4
+#define IOCTL_I2C0_SCL 0x1D8
+#define IOCTL_I2C0_SDA 0x1DC
+#define IOCTL_I2C1_SCL 0x1E0
+#define IOCTL_I2C1_SDA 0x1E4
+#define IOCTL_I2C2_SCL 0x1E8
+#define IOCTL_I2C2_SDA 0x1EC
+#define IOCTL_IRQ0 0x1F0
+#define IOCTL_IRQ1 0x1F4
+#define IOCTL_CAN1_TX 0x1F8
+#define IOCTL_CAN2_TX 0x1FC
+#define IOCTL_J1850_TX 0x200
+#define IOCTL_J1850_RX 0x204
+#define IOCTL_PSC_MCLK_IN 0x208
+#define IOCTL_PSC0_0 0x20C
+#define IOCTL_PSC0_1 0x210
+#define IOCTL_PSC0_2 0x214
+#define IOCTL_PSC0_3 0x218
+#define IOCTL_PSC0_4 0x21C
+#define IOCTL_PSC1_0 0x220
+#define IOCTL_PSC1_1 0x224
+#define IOCTL_PSC1_2 0x228
+#define IOCTL_PSC1_3 0x22C
+#define IOCTL_PSC1_4 0x230
+#define IOCTL_PSC2_0 0x234
+#define IOCTL_PSC2_1 0x238
+#define IOCTL_PSC2_2 0x23C
+#define IOCTL_PSC2_3 0x240
+#define IOCTL_PSC2_4 0x244
+#define IOCTL_PSC3_0 0x248
+#define IOCTL_PSC3_1 0x24C
+#define IOCTL_PSC3_2 0x250
+#define IOCTL_PSC3_3 0x254
+#define IOCTL_PSC3_4 0x258
+#define IOCTL_PSC4_0 0x25C
+#define IOCTL_PSC4_1 0x260
+#define IOCTL_PSC4_2 0x264
+#define IOCTL_PSC4_3 0x268
+#define IOCTL_PSC4_4 0x26C
+#define IOCTL_PSC5_0 0x270
+#define IOCTL_PSC5_1 0x274
+#define IOCTL_PSC5_2 0x278
+#define IOCTL_PSC5_3 0x27C
+#define IOCTL_PSC5_4 0x280
+#define IOCTL_PSC6_0 0x284
+#define IOCTL_PSC6_1 0x288
+#define IOCTL_PSC6_2 0x28C
+#define IOCTL_PSC6_3 0x290
+#define IOCTL_PSC6_4 0x294
+#define IOCTL_PSC7_0 0x298
+#define IOCTL_PSC7_1 0x29C
+#define IOCTL_PSC7_2 0x2A0
+#define IOCTL_PSC7_3 0x2A4
+#define IOCTL_PSC7_4 0x2A8
+#define IOCTL_PSC8_0 0x2AC
+#define IOCTL_PSC8_1 0x2B0
+#define IOCTL_PSC8_2 0x2B4
+#define IOCTL_PSC8_3 0x2B8
+#define IOCTL_PSC8_4 0x2BC
+#define IOCTL_PSC9_0 0x2C0
+#define IOCTL_PSC9_1 0x2C4
+#define IOCTL_PSC9_2 0x2C8
+#define IOCTL_PSC9_3 0x2CC
+#define IOCTL_PSC9_4 0x2D0
+#define IOCTL_PSC10_0 0x2D4
+#define IOCTL_PSC10_1 0x2D8
+#define IOCTL_PSC10_2 0x2DC
+#define IOCTL_PSC10_3 0x2E0
+#define IOCTL_PSC10_4 0x2E4
+#define IOCTL_PSC11_0 0x2E8
+#define IOCTL_PSC11_1 0x2EC
+#define IOCTL_PSC11_2 0x2F0
+#define IOCTL_PSC11_3 0x2F4
+#define IOCTL_PSC11_4 0x2F8
+#define IOCTL_HRESET 0x2FC
+#define IOCTL_SRESET 0x300
+#define IOCTL_CKSTP_OUT 0x304
+#define IOCTL_USB2_VBUS_PWR_FAULT 0x308
+#define IOCTL_USB2_VBUS_PWR_SELECT 0x30C
+#define IOCTL_USB2_PHY_DRVV_BUS 0x310
+
+#ifndef __ASSEMBLY__
+
+
+/* IO pin fields */
+#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */
+#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */
+#define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */
+#define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */
+#define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */
+#define IO_PIN_DS(v) ((v)) /* slew rate */
+
+typedef struct iopin_t {
+ int p_offset; /* offset from IOCTL_MEM_OFFSET */
+ int nr_pins; /* number of pins to set this way */
+ int bit_or; /* or in the value instead of overwrite */
+ u_long val; /* value to write or or */
+}iopin_t;
+
+void iopin_initialize(iopin_t *,int);
+#endif
/* Indexes in regs array */
-#define MEM_IDX 0x00
-#define PATA_CE1_IDX 0x2e
-#define PATA_CE2_IDX 0x2f
-#define PATA_ISOLATE_IDX 0x30
-#define PATA_IOR_IDX 0x31
-#define PATA_IOW_IDX 0x32
-#define PATA_IOCHRDY_IDX 0x33
-#define PATA_INTRQ_IDX 0x34
-#define PATA_DRQ_IDX 0x35
-#define PATA_DACK_IDX 0x36
-#define SPDIF_TXCLOCK_IDX 0x73
-#define SPDIF_TX_IDX 0x74
-#define SPDIF_RX_IDX 0x75
-#define PSC0_0_IDX 0x83
-#define PSC0_1_IDX 0x84
-#define PSC0_2_IDX 0x85
-#define PSC0_3_IDX 0x86
-#define PSC0_4_IDX 0x87
-#define PSC1_0_IDX 0x88
-#define PSC1_1_IDX 0x89
-#define PSC1_2_IDX 0x8a
-#define PSC1_3_IDX 0x8b
-#define PSC1_4_IDX 0x8c
-#define PSC2_0_IDX 0x8d
-#define PSC2_1_IDX 0x8e
-#define PSC2_2_IDX 0x8f
-#define PSC2_3_IDX 0x90
-#define PSC2_4_IDX 0x91
-
-#define IOCTRL_FUNCMUX_SHIFT 7
-#define IOCTRL_FUNCMUX_FEC 1
-#define IOCTRL_MUX_FEC (IOCTRL_FUNCMUX_FEC << IOCTRL_FUNCMUX_SHIFT)
-
/* Set for DDR */
#define IOCTRL_MUX_DDR 0x00000036
projects / platform / kernel / u-boot.git / commitdiff