config TARGET_LS2080A_EMU
bool "Support ls2080a_emu"
+ select ARCH_LS2080A
select ARM64
select ARMV8_MULTIENTRY
help
config TARGET_LS2080A_SIMU
bool "Support ls2080a_simu"
+ select ARCH_LS2080A
select ARM64
select ARMV8_MULTIENTRY
help
config TARGET_LS2080AQDS
bool "Support ls2080aqds"
+ select ARCH_LS2080A
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
config TARGET_LS2080ARDB
bool "Support ls2080ardb"
+ select ARCH_LS2080A
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select CPU_V7
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
select SUPPORT_SPL
select ARCH_LS1021A
select ARCH_SUPPORT_PSCI
config TARGET_LS1021ATWR
bool "Support ls1021atwr"
select CPU_V7
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
select SUPPORT_SPL
select ARCH_LS1021A
select ARCH_SUPPORT_PSCI
select DM_GPIO
select DM_I2C
select DM_MMC
+ select DM_RESET
select DM_SERIAL
select DM_USB
select OF_CONTROL
obj-y += cpu.o cp15.o
obj-y += syslib.o
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_LS102XA),)
ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
obj-y += lowlevel_init.o
endif
config ARCH_LS1021A
- bool "Freescale Layerscape LS1021A SoC"
+ bool
select SYS_FSL_ERRATUM_A010315
+ select SYS_FSL_SRDS_1
+ select SYS_HAS_SERDES
+ select SYS_FSL_DDR_BE
+ select SYS_FSL_DDR_VER_50
+
+menu "LS102xA architecture"
+ depends on ARCH_LS1021A
config LS1_DEEP_SLEEP
- bool "Freescale Layerscape 1 deep sleep"
+ bool "Deep sleep"
+ depends on ARCH_LS1021A
+
+config MAX_CPUS
+ int "Maximum number of CPUs permitted for LS102xA"
+ depends on ARCH_LS1021A
+ default 2
+ help
+ Set this number to the maximum number of possible CPUs in the SoC.
+ SoCs may have multiple clusters with each cluster may have multiple
+ ports. If some ports are reserved but higher ports are used for
+ cores, count the reserved ports. This will allocate enough memory
+ in spin table to properly handle all cores.
+
+config NUM_DDR_CONTROLLERS
+ int "Maximum DDR controllers"
+ default 1
+
+config SYS_FSL_ERRATUM_A010315
+ bool "Workaround for PCIe erratum A010315"
+
+config SYS_FSL_SRDS_1
+ bool
+
+config SYS_FSL_SRDS_2
+ bool
+
+config SYS_HAS_SERDES
+ bool
+
+config SYS_FSL_DDR
+ bool "Freescale DDR driver"
+ help
+ Select Freescale General DDR driver, shared between most Freescale
+ PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
+ based Layerscape SoCs (such as ls2080a).
+
+config SYS_FSL_DDR_BE
+ bool
+ default y
+ help
+ Access DDR registers in big-endian.
+
+config SYS_FSL_DDR_VER
+ int
+ default 50 if SYS_FSL_DDR_VER_50
+
+config SYS_FSL_DDR_VER_50
+ bool
+
+config SYS_FSL_DDRC_ARM_GEN3
+ bool
+
+config SYS_FSL_DDRC_GEN4
+ bool
+
+config SYS_FSL_DDR3
+ bool "Freescale DDR3 controller"
+ depends on !SYS_FSL_DDR4
+ select SYS_FSL_DDR
+ select SYS_FSL_DDRC_ARM_GEN3
+ help
+ Enable Freescale DDR3 controller on ARM-based SoCs.
+
+config SYS_FSL_DDR4
+ bool "Freescale DDR4 controller"
+ select SYS_FSL_DDR
+ select SYS_FSL_DDRC_GEN4
+ help
+ Enable Freescale DDR4 controller.
+
+config SYS_FSL_IFC_BANK_COUNT
+ int "Maximum banks of Integrated flash controller"
+ depends on ARCH_LS1021A
+ default 8
+
+endmenu
return major;
}
+void s_init(void)
+{
+}
+
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
void erratum_a010315(void)
{
config ARCH_LS1012A
- bool "Freescale Layerscape LS1012A SoC"
+ bool
+ select FSL_LSCH2
+ select SYS_FSL_DDR_BE
select SYS_FSL_MMDC
select SYS_FSL_ERRATUM_A010315
config ARCH_LS1043A
- bool "Freescale Layerscape LS1043A SoC"
+ bool
+ select FSL_LSCH2
+ select SYS_FSL_DDR_BE
+ select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A010315
+ select SYS_FSL_ERRATUM_A010539
config ARCH_LS1046A
- bool "Freescale Layerscape LS1046A SoC"
+ bool
+ select FSL_LSCH2
+ select SYS_FSL_DDR_BE
+ select SYS_FSL_DDR4
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A010539
+ select SYS_FSL_SRDS_2
+
+config ARCH_LS2080A
+ bool
+ select FSL_LSCH3
+ select SYS_FSL_DDR4
+ select SYS_FSL_DDR_LE
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_HAS_DP_DDR
+ select SYS_FSL_SRDS_2
+
+config FSL_LSCH2
+ bool
+ select SYS_FSL_SRDS_1
+ select SYS_HAS_SERDES
+
+config FSL_LSCH3
+ bool
+ select SYS_FSL_SRDS_1
+ select SYS_HAS_SERDES
+
+menu "Layerscape architecture"
+ depends on FSL_LSCH2 || FSL_LSCH3
config SYS_FSL_MMDC
- bool "Freescale Multi Mode DDR Controller"
+ bool
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
+
+config SYS_FSL_ERRATUM_A010539
+ bool "Workaround for PIN MUX erratum A010539"
+
+config MAX_CPUS
+ int "Maximum number of CPUs permitted for Layerscape"
+ default 4 if ARCH_LS1043A
+ default 4 if ARCH_LS1046A
+ default 16 if ARCH_LS2080A
+ default 1
+ help
+ Set this number to the maximum number of possible CPUs in the SoC.
+ SoCs may have multiple clusters with each cluster may have multiple
+ ports. If some ports are reserved but higher ports are used for
+ cores, count the reserved ports. This will allocate enough memory
+ in spin table to properly handle all cores.
+
+config NUM_DDR_CONTROLLERS
+ int "Maximum DDR controllers"
+ default 3 if ARCH_LS2080A
+ default 1
+
+config SYS_FSL_IFC_BANK_COUNT
+ int "Maximum banks of Integrated flash controller"
+ depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
+ default 4 if ARCH_LS1043A
+ default 4 if ARCH_LS1046A
+ default 8 if ARCH_LS2080A
+
+config SYS_FSL_HAS_DP_DDR
+ bool
+
+config SYS_FSL_SRDS_1
+ bool
+
+config SYS_FSL_SRDS_2
+ bool
+
+config SYS_HAS_SERDES
+ bool
+
+config SYS_FSL_DDR
+ bool "Freescale DDR driver"
+ help
+ Select Freescale General DDR driver, shared between most Freescale
+ PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
+ based Layerscape SoCs (such as ls2080a).
+
+config SYS_FSL_DDR_BE
+ bool
+ help
+ Access DDR registers in big-endian.
+
+config SYS_FSL_DDR_LE
+ bool
+ help
+ Access DDR registers in little-endian.
+
+config SYS_FSL_DDR_VER
+ int
+ default 50 if SYS_FSL_DDR_VER_50
+
+config SYS_FSL_DDR_VER_50
+ bool
+
+config SYS_FSL_DDRC_ARM_GEN3
+ bool
+
+config SYS_FSL_DDRC_GEN4
+ bool
+
+config SYS_FSL_DDR3
+ bool "Freescale DDR3 controller"
+ depends on !SYS_FSL_DDR4
+ select SYS_FSL_DDR
+ select SYS_FSL_DDRC_ARM_GEN3
+ help
+ Enable Freescale DDR3 controller on ARM-based SoCs.
+
+config SYS_FSL_DDR4
+ bool "Freescale DDR4 controller"
+ select SYS_FSL_DDR
+ select SYS_FSL_DDRC_GEN4
+ help
+ Enable Freescale DDR4 controller.
+
+endmenu
if (IS_E_PROCESSOR(svr))
strcat(name, "E");
+
+ sprintf(name + strlen(name), " Rev%d.%d",
+ SVR_MAJ(svr), SVR_MIN(svr));
break;
}
return 0;
}
+u32 cpu_pos_mask(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ int i = 0;
+ u32 cluster, type, mask = 0;
+
+ do {
+ int j;
+
+ cluster = gur_in32(&gur->tp_cluster[i].lower);
+ for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+ type = initiator_type(cluster, j);
+ if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
+ mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
+ }
+ i++;
+ } while ((cluster & TP_CLUSTER_EOC) == 0x0);
+
+ return mask;
+}
+
u32 cpu_mask(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
}
#endif
+void fsl_fdt_disable_usb(void *blob)
+{
+ int off;
+ /*
+ * SYSCLK is used as a reference clock for USB. When the USB
+ * controller is used, SYSCLK must meet the additional requirement
+ * of 100 MHz.
+ */
+ if (CONFIG_SYS_CLK_FREQ != 100000000) {
+ off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
+ while (off != -FDT_ERR_NOTFOUND) {
+ fdt_status_disabled(blob, off);
+ off = fdt_node_offset_by_compatible(blob, off,
+ "snps,dwc3");
+ }
+ }
+}
+
void ft_cpu_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_FSL_LSCH2
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_firmware(blob);
#endif
+ fsl_fdt_disable_usb(blob);
+
}
return !!((1 << core) & cpu_mask());
}
+static int is_pos_valid(unsigned int pos)
+{
+ return !!((1 << pos) & cpu_pos_mask());
+}
+
int is_core_online(u64 cpu_id)
{
u64 *table;
return 0;
}
-int core_to_pos(int nr)
+static int core_to_pos(int nr)
{
- u32 cores = cpu_mask();
+ u32 cores = cpu_pos_mask();
int i, count = 0;
if (nr == 0) {
}
for (i = 1; i < 32; i++) {
- if (is_core_valid(i)) {
+ if (is_pos_valid(i)) {
count++;
if (count == nr)
break;
}
}
- return count;
+ if (count != nr)
+ return -1;
+
+ return i;
}
int cpu_status(int nr)
out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
#endif
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
- out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
- out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+ out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
ahci_init((void __iomem *)CONFIG_SYS_SATA);
scsi_scan(0);
}
#endif
+static void erratum_a010539(void)
+{
+#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 porsr1;
+
+ porsr1 = in_be32(&gur->porsr1);
+ porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
+ out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+ porsr1);
+#endif
+}
+
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
#endif
/* Make SEC reads and writes snoopable */
setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
- SCFG_SNPCNFGCR_SECWRSNP);
+ SCFG_SNPCNFGCR_SECWRSNP |
+ SCFG_SNPCNFGCR_SATARDSNP |
+ SCFG_SNPCNFGCR_SATAWRSNP);
/*
* Enable snoop requests and DVM message requests for
erratum_a008850_early(); /* part 1 of 2 */
erratum_a009929();
erratum_a009660();
+ erratum_a010539();
}
#endif
big-endian;
status = "disabled";
};
+
+ usb0: usb3@2f00000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x2f00000 0x0 0x10000>;
+ interrupts = <0 60 0x4>;
+ dr_mode = "host";
+ };
+
+ usb1: usb3@3000000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3000000 0x0 0x10000>;
+ interrupts = <0 61 0x4>;
+ dr_mode = "host";
+ };
+
+ usb2: usb3@3100000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <0 63 0x4>;
+ dr_mode = "host";
+ };
};
};
reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <4>;
};
+
+ usb0: usb3@3100000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <0 80 0x4>; /* Level high type */
+ dr_mode = "host";
+ };
+
+ usb1: usb3@3110000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3110000 0x0 0x10000>;
+ interrupts = <0 81 0x4>; /* Level high type */
+ dr_mode = "host";
+ };
};
i2c0 = "/i2c@7000d000";
i2c1 = "/i2c@7000c000";
i2c2 = "/i2c@7000c400";
- usb0 = "/usb@c5008000";
- usb1 = "/usb@c5000000";
- usb2 = "/usb@c5004000";
mmc0 = "/sdhci@c8000600";
+ usb0 = "/usb@c5000000";
+ usb1 = "/usb@c5004000"; /* on-module only, for ASIX */
+ usb2 = "/usb@c5008000";
};
host1x@50000000 {
- status = "okay";
dc@54200000 {
- status = "okay";
rgb {
status = "okay";
nvidia,panel = <&lcd_panel>;
+ display-timings {
+ timing@0 {
+ /* VESA VGA */
+ clock-frequency = <25175000>;
+ hactive = <640>;
+ vactive = <480>;
+ hback-porch = <48>;
+ hfront-porch = <16>;
+ hsync-len = <96>;
+ vback-porch = <31>;
+ vfront-porch = <11>;
+ vsync-len = <2>;
+ };
+ };
};
};
};
- usb@c5000000 {
- statuc = "okay";
- dr_mode = "otg";
- };
-
- usb@c5004000 {
- statuc = "okay";
- /* VBUS_LAN */
- nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
- GPIO_ACTIVE_LOW>;
- nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
- };
-
- usb@c5008000 {
- statuc = "okay";
- /* USBH_PEN */
- nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
- };
-
nand-controller@70008000 {
nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
nvidia,width = <8>;
};
};
+ pwm@7000a000 {
+ status = "okay";
+ };
+
/*
* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
* board)
clock-frequency = <100000>;
};
+ /* EHCI instance 0: USB1_DP/N -> USBC_P/N */
+ usb@c5000000 {
+ status = "okay";
+ dr_mode = "otg";
+ };
+
+ /* EHCI instance 1: ULPI -> USB3340 -> AX88772B */
+ usb@c5004000 {
+ status = "okay";
+ /* VBUS_LAN */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
+ };
+
+ /* EHCI instance 2: USB3_DP/N -> USBH_P/N */
+ usb@c5008000 {
+ status = "okay";
+ /* USBH_PEN */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+ };
+
sdhci@c8000600 {
status = "okay";
bus-width = <4>;
cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ brightness-levels = <255 128 64 32 16 8 4 0>;
+ default-brightness-level = <6>;
+ /* BL_ON */
+ enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>;
+ power-supply = <®_3v3>;
+ /* PWM<A> */
+ pwms = <&pwm 0 5000000>;
+ };
+
clocks {
compatible = "simple-bus";
#address-cells = <1>;
};
};
- pwm: pwm@7000a000 {
- status = "okay";
+ lcd_panel: panel {
+ /*
+ * edt,et057090dhu: EDT 5.7" LCD TFT
+ * edt,et070080dh6: EDT 7.0" LCD TFT
+ */
+ compatible = "edt,et057090dhu", "simple-panel";
+
+ backlight = <&backlight>;
};
- lcd_panel: panel {
- clock = <25175000>;
- xres = <640>;
- yres = <480>;
- left-margin = <48>; /* horizontal back porch */
- right-margin = <16>; /* horizontal front porch */
- hsync-len = <96>;
- lower-margin = <11>; /* vertical front porch */
- upper-margin = <31>; /* vertical back porch */
- vsync-len = <2>;
- hsync-active-high;
- vsync-active-high;
- nvidia,bits-per-pixel = <16>;
- nvidia,pwm = <&pwm 0 0>;
- nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>;
- nvidia,panel-timings = <0 0 0 0>;
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_3v3: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "+V3.3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
};
};
#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
-#ifdef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDRC_GEN4
-#else
-#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
-#endif
-
-#ifndef CONFIG_ARCH_LS1012A
-#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
-#endif
-
/*
* Reserve secure memory
* To be aligned with MMU block size
#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
#ifdef CONFIG_LS2080A
-#define CONFIG_MAX_CPUS 16
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_NUM_DDR_CONTROLLERS 3
-#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_PAGE_SIZE 0x10000
#ifndef L1_CACHE_BYTES
#define L1_CACHE_SHIFT 6
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
/* DDR */
-#define CONFIG_SYS_FSL_DDR_LE
#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
#define CONFIG_SYS_FSL_PEX_LUT_BE
#define CONFIG_SYS_FSL_SEC_BE
-#define CONFIG_SYS_FSL_SRDS_1
-
/* SoC related */
#ifdef CONFIG_LS1043A
-#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 7
#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
-#define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CONFIG_SYS_FSL_ERRATUM_A009660
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_ARCH_LS1012A)
-#define CONFIG_MAX_CPUS 1
#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
#elif defined(CONFIG_ARCH_LS1046A)
-#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 2
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
-#define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
-#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_FSL_IFC_BE
#define CONFIG_SYS_FSL_SFP_VER_3_2
#define CONFIG_SYS_FSL_SNVS_LE
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
/* Device Configuration and Pin Control */
+#define DCFG_DCSR_PORCR1 0x0
+
struct ccsr_gur {
u32 porsr1; /* POR status 1 */
#define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
+#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
+#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000
/* Supplemental Configuration Unit */
struct ccsr_scfg {
phys_addr_t determine_mp_bootpg(void);
void secondary_boot_func(void);
int is_core_online(u64 cpu_id);
+u32 cpu_pos_mask(void);
#endif
#endif /* _FSL_LAYERSCAPE_MP_H */
/* ahci port register default value */
#define AHCI_PORT_PHY_1_CFG 0xa003fffe
-#define AHCI_PORT_PHY_2_CFG 0x28184d1f
-#define AHCI_PORT_PHY_3_CFG 0x0e081509
#define AHCI_PORT_TRANS_CFG 0x08000029
+#define AHCI_PORT_AXICC_CFG 0x3fffffff
/* AHCI (sata) register map */
struct ccsr_ahci {
#define CONFIG_SYS_FSL_ERRATUM_A008407
#ifdef CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_VERY_BIG_RAM
-#ifdef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDRC_GEN4
-#else
-#define CONFIG_SYS_FSL_DDRC_ARM_GEN3
-#endif
-#define CONFIG_SYS_FSL_DDR
#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
#endif
#define DCU_LAYER_MAX_NUM 16
-#define CONFIG_SYS_FSL_SRDS_1
-
#ifdef CONFIG_LS102XA
-#define CONFIG_MAX_CPUS 2
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_ERRATUM_A008378
config TARGET_DREAMPLUG
bool "DreamPlug Board"
+config TARGET_DS109
+ bool "Synology DS109"
+
config TARGET_GURUPLUG
bool "GuruPlug Board"
source "board/Marvell/openrd/Kconfig"
source "board/Marvell/dreamplug/Kconfig"
+source "board/Synology/ds109/Kconfig"
source "board/Marvell/guruplug/Kconfig"
source "board/Marvell/sheevaplug/Kconfig"
source "board/buffalo/lsxl/Kconfig"
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
- int i;
- u16 zq_val[6];
- u8 val;
+ if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 &&
+ (readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0) {
+ u32 reg_val;
- writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
-
- for (i = 0; i < 6; i++) {
- u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
-
- writel((zq << 20) | (zq << 16) | (zq << 12) |
- (zq << 8) | (zq << 4) | (zq << 0),
- &mctl_ctl->zqcr);
+ clrsetbits_le32(&mctl_ctl->zqcr, 0xffff,
+ CONFIG_DRAM_ZQ & 0xffff);
writel(PIR_CLRSR, &mctl_ctl->pir);
mctl_phy_init(PIR_ZCAL);
- zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
- writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
+ reg_val = readl(&mctl_ctl->zqdr[0]);
+ reg_val &= (0x1f << 16) | (0x1f << 0);
+ reg_val |= reg_val << 8;
+ writel(reg_val, &mctl_ctl->zqdr[0]);
- writel(PIR_CLRSR, &mctl_ctl->pir);
- mctl_phy_init(PIR_ZCAL);
+ reg_val = readl(&mctl_ctl->zqdr[1]);
+ reg_val &= (0x1f << 16) | (0x1f << 0);
+ reg_val |= reg_val << 8;
+ writel(reg_val, &mctl_ctl->zqdr[1]);
+ writel(reg_val, &mctl_ctl->zqdr[2]);
+ } else {
+ int i;
+ u16 zq_val[6];
+ u8 val;
- val = readl(&mctl_ctl->zqdr[0]) >> 24;
- zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
- }
+ writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
+
+ for (i = 0; i < 6; i++) {
+ u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
+
+ writel((zq << 20) | (zq << 16) | (zq << 12) |
+ (zq << 8) | (zq << 4) | (zq << 0),
+ &mctl_ctl->zqcr);
- writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
- writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
- writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
+ writel(PIR_CLRSR, &mctl_ctl->pir);
+ mctl_phy_init(PIR_ZCAL);
+
+ zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
+ writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
+
+ writel(PIR_CLRSR, &mctl_ctl->pir);
+ mctl_phy_init(PIR_ZCAL);
+
+ val = readl(&mctl_ctl->zqdr[0]) >> 24;
+ zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
+ }
+
+ writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
+ writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
+ writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
+ }
}
static void mctl_set_cr(struct dram_para *para)
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
- .size = 0xff80000000UL,
+ .size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
case SOC_UNIPHIER_LD20:
+ /* ES1 errata: increase VDD09 supply to suppress VBO noise */
+ if (uniphier_get_soc_revision() == 1) {
+ writel(0x00000003, 0x6184e004);
+ writel(0x00000100, 0x6184e040);
+ writel(0x0000b500, 0x6184e024);
+ writel(0x00000001, 0x6184e000);
+ }
uniphier_nand_pin_init(false);
sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
sg_set_iectrl(149);
uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL);
uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_DPLLCTRL);
uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
#ifndef _DDRPHY_LD20_REGS_H
#define _DDRPHY_LD20_REGS_H
+#include <linux/bitops.h>
+
#define PHY_REG_SHIFT 2
+#define PHY_SLV_DLY_WIDTH 6
+#define PHY_BITLVL_DLY_WIDTH 6
+#define PHY_MAS_DLY_WIDTH 8
#define PHY_SCL_START (0x40 << (PHY_REG_SHIFT))
#define PHY_SCL_DATA_0 (0x41 << (PHY_REG_SHIFT))
#define PHY_SCL_CONFIG_2 (0x47 << (PHY_REG_SHIFT))
#define PHY_PAD_CTRL (0x48 << (PHY_REG_SHIFT))
#define PHY_DLL_RECALIB (0x49 << (PHY_REG_SHIFT))
+#define PHY_DLL_RECALIB_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0)
+#define PHY_DLL_RECALIB_INCR BIT(27)
#define PHY_DLL_ADRCTRL (0x4A << (PHY_REG_SHIFT))
+#define PHY_DLL_ADRCTRL_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0)
+#define PHY_DLL_ADRCTRL_INCR BIT(9)
+#define PHY_DLL_ADRCTRL_MDL_SHIFT 24
+#define PHY_DLL_ADRCTRL_MDL_MASK (GENMASK(PHY_MAS_DLY_WIDTH - 1, 0) << \
+ PHY_DLL_ADRCTRL_MDL_SHIFT)
#define PHY_LANE_SEL (0x4B << (PHY_REG_SHIFT))
+#define PHY_LANE_SEL_LANE_SHIFT 0
+#define PHY_LANE_SEL_LANE_WIDTH 8
+#define PHY_LANE_SEL_BIT_SHIFT 8
+#define PHY_LANE_SEL_BIT_WIDTH 4
#define PHY_DLL_TRIM_1 (0x4C << (PHY_REG_SHIFT))
#define PHY_DLL_TRIM_2 (0x4D << (PHY_REG_SHIFT))
#define PHY_DLL_TRIM_3 (0x4E << (PHY_REG_SHIFT))
#define PHY_UNIQUIFY_TSMC_IO_1 (0x5C << (PHY_REG_SHIFT))
#define PHY_SCL_START_ADDR (0x62 << (PHY_REG_SHIFT))
#define PHY_IP_DQ_DQS_BITWISE_TRIM (0x65 << (PHY_REG_SHIFT))
+#define PHY_IP_DQ_DQS_BITWISE_TRIM_MASK \
+ GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0)
+#define PHY_IP_DQ_DQS_BITWISE_TRIM_INC \
+ BIT(PHY_BITLVL_DLY_WIDTH)
+#define PHY_IP_DQ_DQS_BITWISE_TRIM_OVERRIDE \
+ BIT(PHY_BITLVL_DLY_WIDTH + 1)
#define PHY_DSCL_CNT (0x67 << (PHY_REG_SHIFT))
#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM (0x68 << (PHY_REG_SHIFT))
+#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_MASK \
+ GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0)
+#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_INC \
+ BIT(PHY_BITLVL_DLY_WIDTH)
+#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_OVERRIDE \
+ BIT(PHY_BITLVL_DLY_WIDTH + 1)
#define PHY_DLL_TRIM_CLK (0x69 << (PHY_REG_SHIFT))
+#define PHY_DLL_TRIM_CLK_MASK GENMASK(PHY_SLV_DLY_WIDTH, 0)
+#define PHY_DLL_TRIM_CLK_INCR BIT(PHY_SLV_DLY_WIDTH + 1)
#define PHY_DYNAMIC_BIT_LVL (0x6B << (PHY_REG_SHIFT))
#define PHY_SCL_WINDOW_TRIM (0x6D << (PHY_REG_SHIFT))
#define PHY_DISABLE_GATING_FOR_SCL (0x6E << (PHY_REG_SHIFT))
#define PHY_VREF_TRAINING (0x72 << (PHY_REG_SHIFT))
#define PHY_SCL_GATE_TIMING (0x78 << (PHY_REG_SHIFT))
-/* MASK */
-#define MSK_OP_DQ_DM_DQS_BITWISE_TRIM 0x0000007F
-#define MSK_IP_DQ_DQS_BITWISE_TRIM 0x0000007F
-#define MSK_OVERRIDE 0x00000080
-
-#define PHY_BITLVL_DLY_WIDTH 6
-
#endif /* _DDRPHY_LD20_REGS_H */
/*
* Copyright (C) 2016 Socionext Inc.
*
- * based on commit a3c28918e86ad57127cf07bf8b32950cab20c03c of Diag
+ * based on commit 9073035a9860f892f8d1345dfb0ea862b5021145 of Diag
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "umc64-regs.h"
#define DRAM_CH_NR 3
-#define CONFIG_DDR_FREQ 1866
enum dram_freq {
DRAM_FREQ_1866M,
DRAM_BOARD_NR,
};
-#define MSK_PHY_LANE_SEL 0x000000FF
-#define MSK_BIT_SEL 0x00000F00
-#define MSK_DLL_MAS_DLY 0xFF000000
-#define MSK_MAS_DLY 0x7F000000
-#define MSK_DLLS_TRIM_CLK 0x000000FF
-
-#define PHY_DLL_MAS_DLY_WIDTH 8
-#define PHY_SLV_DLY_WIDTH 6
-
-static void ddrphy_maskwritel(u32 data, u32 mask, void *addr)
-{
- u32 value;
-
- value = (readl(addr) & ~mask) | (data & mask);
- writel(value, addr);
-}
-
-static u32 ddrphy_maskreadl(u32 mask, void *addr)
-{
- return readl(addr) & mask;
-}
-
-/* set phy_lane_sel.phy_lane_sel */
-static void ddrphy_set_phy_lane_sel(int val, void __iomem *phy_base)
-{
- ddrphy_maskwritel(val, MSK_PHY_LANE_SEL, phy_base + PHY_LANE_SEL);
-}
-
-/* set phy_lane_sel.bit_sel */
-static void ddrphy_set_bit_sel(int bit, void __iomem *phy_base)
-{
- ddrphy_maskwritel(bit << 8, MSK_BIT_SEL, phy_base + PHY_LANE_SEL);
-}
-
-/* Calculating step for PUB-byte */
-static int ddrphy_hpstep(int delay, void __iomem *phy_base)
-{
- int mdl, freq;
-
- freq = CONFIG_DDR_FREQ; /* FIXME */
- mdl = ddrphy_maskreadl(MSK_DLL_MAS_DLY, phy_base + PHY_DLL_ADRCTRL) >> 24;
-
- return DIV_ROUND_CLOSEST(freq * delay * mdl, 2 * 1000000);
-}
-
-static void ddrphy_set_dll_trim_clk(int delay_ckoffset, void __iomem *phy_base)
-{
- u8 ck_step; /* ckoffset_step for clock */
- u32 ck_step_all;
-
- /* CK-Offset */
- if (delay_ckoffset >= 0) {
- /* shift + direction */
- ck_step = min(ddrphy_hpstep(delay_ckoffset, phy_base), 127);
- ck_step_all = ((0x1<<(PHY_SLV_DLY_WIDTH + 1))|ck_step);
- } else{
- /* shift - direction */
- ck_step = min(ddrphy_hpstep(-1*delay_ckoffset, phy_base), 127);
- ck_step_all = ck_step;
- }
-
- ddrphy_set_phy_lane_sel(0, phy_base);
- ddrphy_maskwritel(ck_step_all, MSK_DLLS_TRIM_CLK, phy_base + PHY_DLL_TRIM_CLK);
-}
-
-static void ddrphy_set_dll_recalib(int delay_qoffset, u32 recalib_cnt,
- u8 disable_recalib, u8 ctr_start_val,
- void __iomem *phy_base)
-{
- u8 dlls_trim_adrctrl_ma, incr_dly_adrctrl_ma; /* qoffset_step and flag for inc/dec */
- u32 recalib_all; /* all fields of register dll_recalib */
-
- /* Q-Offset */
- if (delay_qoffset >= 0) {
- dlls_trim_adrctrl_ma = min(ddrphy_hpstep(delay_qoffset, phy_base), 63);
- incr_dly_adrctrl_ma = 0x1;
- } else {
- dlls_trim_adrctrl_ma = min(ddrphy_hpstep(-1*delay_qoffset, phy_base), 63);
- incr_dly_adrctrl_ma = 0x0;
- }
-
- recalib_all = ((ctr_start_val & 0xf) << 28) |
- (incr_dly_adrctrl_ma << 27) |
- ((disable_recalib & 0x1) << 26) |
- ((recalib_cnt & 0x3ffff) << 8) |
- (dlls_trim_adrctrl_ma & 0x3f);
-
- /* write value for all bits other than bit[7:6] */
- ddrphy_maskwritel(recalib_all, ~0xc0, phy_base + PHY_DLL_RECALIB);
-}
-
-static void ddrphy_set_dll_adrctrl(int delay_qoffset, u8 override_adrctrl,
- void __iomem *phy_base)
-{
- u8 dlls_trim_adrctrl, incr_dly_adrctrl; /* qoffset_step for clock */
- u32 adrctrl_all;
-
- if (delay_qoffset >= 0) {
- dlls_trim_adrctrl = min(ddrphy_hpstep(delay_qoffset, phy_base), 63);
- incr_dly_adrctrl = 0x1;
- } else {
- dlls_trim_adrctrl = min(ddrphy_hpstep(-delay_qoffset, phy_base), 63);
- incr_dly_adrctrl = 0x0;
- }
-
- adrctrl_all = (incr_dly_adrctrl << 9) |
- ((override_adrctrl & 0x1) << 8) |
- dlls_trim_adrctrl;
-
- ddrphy_maskwritel(adrctrl_all, 0x33f, phy_base + PHY_DLL_ADRCTRL);
-}
-
-/* dio */
-static int dio_adrctrl_0[DRAM_BOARD_NR][DRAM_CH_NR] = {
- {268-262, 268-263, 268-378}, /* LD20 reference */
- {268-262, 268-263, 268-378}, /* LD20 TV */
- {268-212, 268-268, 0}, /* LD21 reference */
- {268-212, 268-268, 0}, /* LD21 TV */
+/* PHY */
+static const int ddrphy_adrctrl[DRAM_BOARD_NR][DRAM_CH_NR] = {
+ {268 - 262, 268 - 263, 268 - 378}, /* LD20 reference */
+ {268 - 262, 268 - 263, 268 - 378}, /* LD20 TV */
+ {268 - 212, 268 - 268, /* No CH2 */}, /* LD21 reference */
+ {268 - 212, 268 - 268, /* No CH2 */}, /* LD21 TV */
};
-static int dio_dlltrimclk_0[DRAM_BOARD_NR][DRAM_CH_NR] = {
+
+static const int ddrphy_dlltrimclk[DRAM_BOARD_NR][DRAM_CH_NR] = {
{268, 268, 268}, /* LD20 reference */
{268, 268, 268}, /* LD20 TV */
- {268, 268+252, 0}, /* LD21 reference */
- {268, 268+202, 0}, /* LD21 TV */
+ {268, 268 + 252, /* No CH2 */}, /* LD21 reference */
+ {268, 268 + 202, /* No CH2 */}, /* LD21 TV */
};
-static int dio_dllrecalib_0[DRAM_BOARD_NR][DRAM_CH_NR] = {
- {268-378, 268-263, 268-378}, /* LD20 reference */
- {268-378, 268-263, 268-378}, /* LD20 TV */
- {268-212, 268-536, 0}, /* LD21 reference */
- {268-212, 268-536, 0}, /* LD21 TV */
+
+static const int ddrphy_dllrecalib[DRAM_BOARD_NR][DRAM_CH_NR] = {
+ {268 - 378, 268 - 263, 268 - 378}, /* LD20 reference */
+ {268 - 378, 268 - 263, 268 - 378}, /* LD20 TV */
+ {268 - 212, 268 - 536, /* No CH2 */}, /* LD21 reference */
+ {268 - 212, 268 - 536, /* No CH2 */}, /* LD21 TV */
};
-static u32 dio_phy_pad_ctrl[DRAM_BOARD_NR][DRAM_CH_NR] = {
+static const u32 ddrphy_phy_pad_ctrl[DRAM_BOARD_NR][DRAM_CH_NR] = {
{0x50B840B1, 0x50B840B1, 0x50B840B1}, /* LD20 reference */
{0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV */
- {0x50BB40B4, 0x50B840B1, 0x50BB40B1}, /* LD21 reference */
- {0x50BB40B4, 0x50B840B1, 0x50BB40B1}, /* LD21 TV */
+ {0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 reference */
+ {0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 TV */
};
-static u32 dio_scl_gate_timing[DRAM_CH_NR] = {0x00000140, 0x00000180, 0x00000140};
+static const u32 ddrphy_scl_gate_timing[DRAM_CH_NR] = {
+ 0x00000140, 0x00000180, 0x00000140
+};
-static int dio_op_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
+static const int ddrphy_op_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
{ /* LD20 reference */
{
- 2, 1, 0, 1, 2, 1, 1, 1, 2, 1, 1, 2, 1, 1, 1, 1,
- 1, 2, 1, 1, 1, 2, 1, 1, 2, 2, 0, 1, 1, 2, 2, 1,
+ 2, 1, 0, 1, 2, 1, 1, 1,
+ 2, 1, 1, 2, 1, 1, 1, 1,
+ 1, 2, 1, 1, 1, 2, 1, 1,
+ 2, 2, 0, 1, 1, 2, 2, 1,
},
{
- 1, 1, 0, 1, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 2, 1, 2, 1,
+ 1, 1, 0, 1, 2, 2, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 0, 0, 1, 1, 0, 0,
+ 0, 1, 1, 1, 2, 1, 2, 1,
},
{
- 2, 2, 0, 2, 1, 1, 2, 1, 1, 1, 0, 1, 1, -1, 1, 1,
- 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 1, 2,
+ 2, 2, 0, 2, 1, 1, 2, 1,
+ 1, 1, 0, 1, 1, -1, 1, 1,
+ 2, 2, 2, 2, 1, 1, 1, 1,
+ 1, 1, 1, 0, 2, 2, 1, 2,
},
},
{ /* LD20 TV */
{
- 2, 1, 0, 1, 2, 1, 1, 1, 2, 1, 1, 2, 1, 1, 1, 1,
- 1, 2, 1, 1, 1, 2, 1, 1, 2, 2, 0, 1, 1, 2, 2, 1,
+ 2, 1, 0, 1, 2, 1, 1, 1,
+ 2, 1, 1, 2, 1, 1, 1, 1,
+ 1, 2, 1, 1, 1, 2, 1, 1,
+ 2, 2, 0, 1, 1, 2, 2, 1,
},
{
- 1, 1, 0, 1, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 2, 1, 2, 1,
+ 1, 1, 0, 1, 2, 2, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 0, 0, 1, 1, 0, 0,
+ 0, 1, 1, 1, 2, 1, 2, 1,
},
{
- 2, 2, 0, 2, 1, 1, 2, 1, 1, 1, 0, 1, 1, -1, 1, 1,
- 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 1, 2,
+ 2, 2, 0, 2, 1, 1, 2, 1,
+ 1, 1, 0, 1, 1, -1, 1, 1,
+ 2, 2, 2, 2, 1, 1, 1, 1,
+ 1, 1, 1, 0, 2, 2, 1, 2,
},
},
{ /* LD21 reference */
{
- 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 2,
- 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1,
- },
- { 1, 0, 2, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0,
- 1, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0,
+ 1, 1, 0, 1, 1, 1, 1, 1,
+ 1, 0, 0, 0, 1, 1, 0, 2,
+ 1, 1, 0, 0, 1, 1, 1, 1,
+ 1, 0, 0, 0, 1, 0, 0, 1,
},
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { 1, 0, 2, 1, 1, 1, 1, 0,
+ 1, 0, 0, 1, 0, 1, 0, 0,
+ 1, 0, 1, 0, 1, 1, 1, 0,
+ 1, 1, 1, 1, 0, 1, 0, 0,
},
+ /* No CH2 */
},
{ /* LD21 TV */
{
- 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 2,
- 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1,
- },
- { 1, 0, 2, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0,
- 1, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0,
+ 1, 1, 0, 1, 1, 1, 1, 1,
+ 1, 0, 0, 0, 1, 1, 0, 2,
+ 1, 1, 0, 0, 1, 1, 1, 1,
+ 1, 0, 0, 0, 1, 0, 0, 1,
},
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { 1, 0, 2, 1, 1, 1, 1, 0,
+ 1, 0, 0, 1, 0, 1, 0, 0,
+ 1, 0, 1, 0, 1, 1, 1, 0,
+ 1, 1, 1, 1, 0, 1, 0, 0,
},
+ /* No CH2 */
},
};
-static int dio_ip_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
+
+static int ddrphy_ip_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
{ /* LD20 reference */
{
- 3, 3, 3, 2, 3, 2, 0, 2, 2, 3, 3, 1, 2, 2, 2, 2,
- 2, 2, 2, 2, 0, 1, 1, 1, 2, 2, 2, 2, 3, 0, 2, 2,
+ 3, 3, 3, 2, 3, 2, 0, 2,
+ 2, 3, 3, 1, 2, 2, 2, 2,
+ 2, 2, 2, 2, 0, 1, 1, 1,
+ 2, 2, 2, 2, 3, 0, 2, 2,
},
{
- 2, 2, 1, 1, -1, 1, 1, 1, 2, 0, 2, 2, 2, 1, 0, 2,
- 2, 1, 2, 1, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 1, 1, -1, 1, 1, 1,
+ 2, 0, 2, 2, 2, 1, 0, 2,
+ 2, 1, 2, 1, 0, 1, 1, 1,
+ 2, 2, 2, 2, 2, 2, 2, 2,
},
{
- 2, 2, 3, 2, 1, 2, 2, 2, 2, 3, 4, 2, 3, 4, 3, 3,
- 2, 2, 1, 2, 1, 1, 1, 1, 2, 2, 2, 2, 1, 2, 2, 1,
+ 2, 2, 3, 2, 1, 2, 2, 2,
+ 2, 3, 4, 2, 3, 4, 3, 3,
+ 2, 2, 1, 2, 1, 1, 1, 1,
+ 2, 2, 2, 2, 1, 2, 2, 1,
},
},
{ /* LD20 TV */
{
- 3, 3, 3, 2, 3, 2, 0, 2, 2, 3, 3, 1, 2, 2, 2, 2,
- 2, 2, 2, 2, 0, 1, 1, 1, 2, 2, 2, 2, 3, 0, 2, 2,
+ 3, 3, 3, 2, 3, 2, 0, 2,
+ 2, 3, 3, 1, 2, 2, 2, 2,
+ 2, 2, 2, 2, 0, 1, 1, 1,
+ 2, 2, 2, 2, 3, 0, 2, 2,
},
{
- 2, 2, 1, 1, -1, 1, 1, 1, 2, 0, 2, 2, 2, 1, 0, 2,
- 2, 1, 2, 1, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 1, 1, -1, 1, 1, 1,
+ 2, 0, 2, 2, 2, 1, 0, 2,
+ 2, 1, 2, 1, 0, 1, 1, 1,
+ 2, 2, 2, 2, 2, 2, 2, 2,
},
{
- 2, 2, 3, 2, 1, 2, 2, 2, 2, 3, 4, 2, 3, 4, 3, 3,
- 2, 2, 1, 2, 1, 1, 1, 1, 2, 2, 2, 2, 1, 2, 2, 1,
+ 2, 2, 3, 2, 1, 2, 2, 2,
+ 2, 3, 4, 2, 3, 4, 3, 3,
+ 2, 2, 1, 2, 1, 1, 1, 1,
+ 2, 2, 2, 2, 1, 2, 2, 1,
},
},
{ /* LD21 reference */
{
- 2, 2, 2, 2, 1, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 2,
- 2, 1, 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 1, 2, 2, 2,
- },
- {
- 3, 4, 4, 1, 0, 1, 1, 1, 1, 2, 1, 2, 2, 3, 3, 2,
- 1, 0, 2, 1, 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 0, 1,
+ 2, 2, 2, 2, 1, 2, 2, 2,
+ 2, 3, 3, 2, 2, 2, 2, 2,
+ 2, 1, 2, 2, 1, 1, 1, 1,
+ 2, 2, 2, 3, 1, 2, 2, 2,
},
{
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 3, 4, 4, 1, 0, 1, 1, 1,
+ 1, 2, 1, 2, 2, 3, 3, 2,
+ 1, 0, 2, 1, 1, 0, 1, 0,
+ 0, 1, 0, 0, 1, 1, 0, 1,
},
+ /* No CH2 */
},
{ /* LD21 TV */
{
- 2, 2, 2, 2, 1, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 2,
- 2, 1, 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 1, 2, 2, 2,
- },
- {
- 3, 4, 4, 1, 0, 1, 1, 1, 1, 2, 1, 2, 2, 3, 3, 2,
- 1, 0, 2, 1, 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 0, 1,
+ 2, 2, 2, 2, 1, 2, 2, 2,
+ 2, 3, 3, 2, 2, 2, 2, 2,
+ 2, 1, 2, 2, 1, 1, 1, 1,
+ 2, 2, 2, 3, 1, 2, 2, 2,
},
{
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 3, 4, 4, 1, 0, 1, 1, 1,
+ 1, 2, 1, 2, 2, 3, 3, 2,
+ 1, 0, 2, 1, 1, 0, 1, 0,
+ 0, 1, 0, 0, 1, 1, 0, 1,
},
+ /* No CH2 */
},
};
-/* umc */
-static u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11};
-static u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC};
-static u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF};
-static u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114};
-static u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0};
-
-static u32 umc_memconf0a[DRAM_FREQ_NR][DRAM_SZ_NR] = {
- /* 256MB 512MB */
- {0x00000601, 0x00000801}, /* 1866 MHz */
-};
-static u32 umc_memconf0b[DRAM_FREQ_NR][DRAM_SZ_NR] = {
- /* 256MB 512MB */
- {0x00000120, 0x00000130}, /* 1866 MHz */
-};
-static u32 umc_memconfch[DRAM_FREQ_NR][DRAM_SZ_NR] = {
- /* 256MB 512MB */
- {0x00033603, 0x00033803}, /* 1866 MHz */
-};
-static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
-static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
-static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
-static u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = {
- /* 256MB 512MB */
- {0x0049071D, 0x0078071D}, /* 1866 MHz */
-};
-
-static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000610};
-static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000610};
-static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000204};
-static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000204};
-static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
-static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
-static u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000};
-
-static u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E};
-static u32 umc_directbusctrla[DRAM_CH_NR] = {
- 0x00000000, 0x00000001, 0x00000001
-};
-
-/* polling function for PHY Init Complete */
-static void ddrphy_init_complete(void __iomem *dc_base)
+/* DDR PHY */
+static void ddrphy_select_lane(void __iomem *phy_base, unsigned int lane,
+ unsigned int bit)
{
- /* Wait for PHY Init Complete */
- while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0)))
- cpu_relax();
+ WARN_ON(lane >= (1 << PHY_LANE_SEL_LANE_WIDTH));
+ WARN_ON(bit >= (1 << PHY_LANE_SEL_BIT_WIDTH));
+
+ writel((bit << PHY_LANE_SEL_BIT_SHIFT) |
+ (lane << PHY_LANE_SEL_LANE_SHIFT),
+ phy_base + PHY_LANE_SEL);
}
-/* DDR PHY */
-static void ddrphy_init(void __iomem *phy_base, void __iomem *dc_base,
- enum dram_freq freq, enum dram_board board, int ch)
+static void ddrphy_init(void __iomem *phy_base, enum dram_board board, int ch)
{
writel(0x0C001001, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
while (!(readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1)))
writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3);
writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1);
- writel(0x00000000, phy_base + PHY_LANE_SEL);
+ ddrphy_select_lane(phy_base, 0, 0);
writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
- writel(0x00000006, phy_base + PHY_LANE_SEL);
+ ddrphy_select_lane(phy_base, 6, 0);
writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
- writel(0x0000000c, phy_base + PHY_LANE_SEL);
+ ddrphy_select_lane(phy_base, 12, 0);
writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
- writel(0x00000012, phy_base + PHY_LANE_SEL);
+ ddrphy_select_lane(phy_base, 18, 0);
writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
writel(0x00000001, phy_base + PHY_SCL_WINDOW_TRIM);
writel(0x00000000, phy_base + PHY_UNQ_ANALOG_DLL_1);
- writel(dio_phy_pad_ctrl[board][ch], phy_base + PHY_PAD_CTRL);
+ writel(ddrphy_phy_pad_ctrl[board][ch], phy_base + PHY_PAD_CTRL);
writel(0x00000070, phy_base + PHY_VREF_TRAINING);
writel(0x01000075, phy_base + PHY_SCL_CONFIG_1);
writel(0x00000501, phy_base + PHY_SCL_CONFIG_2);
writel(0x00000000, phy_base + PHY_SCL_CONFIG_3);
writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL);
writel(0x00000000, phy_base + PHY_SCL_CONFIG_4);
- writel(dio_scl_gate_timing[ch], phy_base + PHY_SCL_GATE_TIMING);
+ writel(ddrphy_scl_gate_timing[ch], phy_base + PHY_SCL_GATE_TIMING);
writel(0x02a000a0, phy_base + PHY_WRLVL_DYN_ODT);
writel(0x00840004, phy_base + PHY_WRLVL_ON_OFF);
writel(0x0000020d, phy_base + PHY_DLL_ADRCTRL);
- writel(0x00000000, phy_base + PHY_LANE_SEL);
+ ddrphy_select_lane(phy_base, 0, 0);
writel(0x0000008d, phy_base + PHY_DLL_TRIM_CLK);
writel(0xa800100d, phy_base + PHY_DLL_RECALIB);
writel(0x00005076, phy_base + PHY_SCL_LATENCY);
+}
- ddrphy_init_complete(dc_base);
+static int ddrphy_to_dly_step(void __iomem *phy_base, unsigned int freq,
+ int delay)
+{
+ int mdl;
+
+ mdl = (readl(phy_base + PHY_DLL_ADRCTRL) & PHY_DLL_ADRCTRL_MDL_MASK) >>
+ PHY_DLL_ADRCTRL_MDL_SHIFT;
- ddrphy_set_dll_adrctrl(dio_adrctrl_0[board][ch], 0, phy_base);
- ddrphy_set_dll_trim_clk(dio_dlltrimclk_0[board][ch], phy_base);
- ddrphy_set_dll_recalib(dio_dllrecalib_0[board][ch], 0x10, 0, 0xa,
- phy_base);
+ return DIV_ROUND_CLOSEST((long)freq * delay * mdl, 2 * 1000000L);
}
-static void ddrphy_shift_dq(u32 reg_mask, u32 reg_addr, int shift_val,
- void __iomem *phy_base)
+static void ddrphy_set_delay(void __iomem *phy_base, unsigned int reg,
+ u32 mask, u32 incr, int dly_step)
{
- u32 reg_val;
- int dq_val;
+ u32 tmp;
- reg_val = ddrphy_maskreadl(reg_mask, phy_base + reg_addr) & 0x7f;
- dq_val = reg_val & 0x3f;
+ tmp = readl(phy_base + reg);
+ tmp &= ~mask;
+ tmp |= min_t(u32, abs(dly_step), mask);
- if ((reg_val & 0x40) == 0x00)
- dq_val = -1 * dq_val;
+ if (dly_step >= 0)
+ tmp |= incr;
+ else
+ tmp &= ~incr;
- /* value shift*/
- dq_val = dq_val + shift_val;
+ writel(tmp, phy_base + reg);
+}
- if (dq_val >= 0)
- reg_val = 0x40 + (dq_val & 0x3f);
- else
- reg_val = ((-1 * dq_val) & 0x3f);
+static void ddrphy_set_dll_recalib(void __iomem *phy_base, int dly_step)
+{
+ ddrphy_set_delay(phy_base, PHY_DLL_RECALIB,
+ PHY_DLL_RECALIB_TRIM_MASK, PHY_DLL_RECALIB_INCR,
+ dly_step);
+}
- ddrphy_maskwritel(reg_val, reg_mask, phy_base + reg_addr);
+static void ddrphy_set_dll_adrctrl(void __iomem *phy_base, int dly_step)
+{
+ ddrphy_set_delay(phy_base, PHY_DLL_ADRCTRL,
+ PHY_DLL_ADRCTRL_TRIM_MASK, PHY_DLL_ADRCTRL_INCR,
+ dly_step);
}
-static void ddrphy_shift(void __iomem *phy_base, enum dram_board board, int ch)
+static void ddrphy_set_dll_trim_clk(void __iomem *phy_base, int dly_step)
{
- u32 dx, bit;
+ ddrphy_select_lane(phy_base, 0, 0);
+
+ ddrphy_set_delay(phy_base, PHY_DLL_TRIM_CLK,
+ PHY_DLL_TRIM_CLK_MASK, PHY_DLL_TRIM_CLK_INCR,
+ dly_step);
+}
- /* set override = 1 */
- ddrphy_maskwritel(MSK_OVERRIDE, MSK_OVERRIDE,
- phy_base + PHY_OP_DQ_DM_DQS_BITWISE_TRIM);
- ddrphy_maskwritel(MSK_OVERRIDE, MSK_OVERRIDE,
- phy_base + PHY_IP_DQ_DQS_BITWISE_TRIM);
+static void ddrphy_init_tail(void __iomem *phy_base, enum dram_board board,
+ unsigned int freq, int ch)
+{
+ int step;
- for (dx = 0; dx < 4; dx++) {
- /* set byte to PHY_LANE_SEL.phy_lane_sel= dx * (PHY_BITLVL_DLY_WIDTH+1) */
- ddrphy_set_phy_lane_sel(dx * (PHY_BITLVL_DLY_WIDTH + 1),
- phy_base);
+ step = ddrphy_to_dly_step(phy_base, freq, ddrphy_adrctrl[board][ch]);
+ ddrphy_set_dll_adrctrl(phy_base, step);
+ step = ddrphy_to_dly_step(phy_base, freq, ddrphy_dlltrimclk[board][ch]);
+ ddrphy_set_dll_trim_clk(phy_base, step);
+
+ step = ddrphy_to_dly_step(phy_base, freq, ddrphy_dllrecalib[board][ch]);
+ ddrphy_set_dll_recalib(phy_base, step);
+}
+
+static void ddrphy_shift_one_dq(void __iomem *phy_base, unsigned int reg,
+ u32 mask, u32 incr, int shift_val)
+{
+ u32 tmp;
+ int val;
+
+ tmp = readl(phy_base + reg);
+
+ val = tmp & mask;
+ if (!(tmp & incr))
+ val = -val;
+
+ val += shift_val;
+
+ tmp &= ~(incr | mask);
+ tmp |= min_t(u32, abs(val), mask);
+ if (val >= 0)
+ tmp |= incr;
+
+ writel(tmp, phy_base + reg);
+}
+
+static void ddrphy_shift_dq(void __iomem *phy_base, unsigned int reg,
+ u32 mask, u32 incr, u32 override,
+ const int *shift_val_array)
+{
+ u32 tmp;
+ int dx, bit;
+
+ tmp = readl(phy_base + reg);
+ tmp |= override;
+ writel(tmp, phy_base + reg);
+
+ for (dx = 0; dx < 4; dx++) {
for (bit = 0; bit < 8; bit++) {
- ddrphy_set_bit_sel(bit, phy_base);
-
- /* shift write reg value*/
- ddrphy_shift_dq(MSK_OP_DQ_DM_DQS_BITWISE_TRIM,
- PHY_OP_DQ_DM_DQS_BITWISE_TRIM,
- dio_op_dq_shift_val[board][ch][dx * 8 + bit],
- phy_base);
- /* shift read reg value */
- ddrphy_shift_dq(MSK_IP_DQ_DQS_BITWISE_TRIM,
- PHY_IP_DQ_DQS_BITWISE_TRIM,
- dio_ip_dq_shift_val[board][ch][dx * 8 + bit],
- phy_base);
- }
+ ddrphy_select_lane(phy_base,
+ (PHY_BITLVL_DLY_WIDTH + 1) * dx,
+ bit);
+ ddrphy_shift_one_dq(phy_base, reg, mask, incr,
+ shift_val_array[dx * 8 + bit]);
+ }
}
- ddrphy_set_phy_lane_sel(0, phy_base);
- ddrphy_set_bit_sel(0, phy_base);
+
+ ddrphy_select_lane(phy_base, 0, 0);
}
static int ddrphy_training(void __iomem *phy_base, enum dram_board board,
writel(0x00003270, phy_base + PHY_DYNAMIC_BIT_LVL);
writel(0x011BD0C4, phy_base + PHY_DSCL_CNT);
- /* shift ip_dq, op_dq trim */
- ddrphy_shift(phy_base, board, ch);
+ /* shift ip_dq trim */
+ ddrphy_shift_dq(phy_base,
+ PHY_IP_DQ_DQS_BITWISE_TRIM,
+ PHY_IP_DQ_DQS_BITWISE_TRIM_MASK,
+ PHY_IP_DQ_DQS_BITWISE_TRIM_INC,
+ PHY_IP_DQ_DQS_BITWISE_TRIM_OVERRIDE,
+ ddrphy_ip_dq_shift_val[board][ch]);
+
+ /* shift op_dq trim */
+ ddrphy_shift_dq(phy_base,
+ PHY_OP_DQ_DM_DQS_BITWISE_TRIM,
+ PHY_OP_DQ_DM_DQS_BITWISE_TRIM_MASK,
+ PHY_OP_DQ_DM_DQS_BITWISE_TRIM_INC,
+ PHY_OP_DQ_DM_DQS_BITWISE_TRIM_OVERRIDE,
+ ddrphy_op_dq_shift_val[board][ch]);
+
return 0;
}
-static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
+/* UMC */
+static u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11};
+static u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC};
+static u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF};
+static u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114};
+static u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0};
+
+static u32 umc_memconf0a[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+ /* 256MB 512MB */
+ {0x00000601, 0x00000801}, /* 1866 MHz */
+};
+
+static u32 umc_memconf0b[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+ /* 256MB 512MB */
+ {0x00000120, 0x00000130}, /* 1866 MHz */
+};
+
+static u32 umc_memconfch[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+ /* 256MB 512MB */
+ {0x00033603, 0x00033803}, /* 1866 MHz */
+};
+
+static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
+static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
+static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
+static u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+ /* 256MB 512MB */
+ {0x0049071D, 0x0078071D}, /* 1866 MHz */
+};
+
+static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000610};
+static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000610};
+static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000204};
+static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000204};
+static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
+static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
+static u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000};
+
+static u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E};
+static u32 umc_directbusctrla[DRAM_CH_NR] = {
+ 0x00000000, 0x00000001, 0x00000001
+};
+
+static void umc_poll_phy_init_complete(void __iomem *dc_base)
+{
+ /* Wait for PHY Init Complete */
+ while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0)))
+ cpu_relax();
+}
+
+static int umc_dc_init(void __iomem *dc_base, unsigned int freq,
unsigned long size, int ch)
{
+ enum dram_freq freq_e;
enum dram_size size_e;
+ switch (freq) {
+ case 1866:
+ freq_e = DRAM_FREQ_1866M;
+ break;
+ default:
+ pr_err("unsupported DRAM frequency %ud MHz\n", freq);
+ return -EINVAL;
+ }
+
switch (size) {
case 0:
return 0;
writel(0x00000001, dc_base + UMC_DFICSOVRRD);
writel(0x00000000, dc_base + UMC_DFITURNOFF);
- writel(umc_initctla[freq], dc_base + UMC_INITCTLA);
- writel(umc_initctlb[freq], dc_base + UMC_INITCTLB);
- writel(umc_initctlc[freq], dc_base + UMC_INITCTLC);
+ writel(umc_initctla[freq_e], dc_base + UMC_INITCTLA);
+ writel(umc_initctlb[freq_e], dc_base + UMC_INITCTLB);
+ writel(umc_initctlc[freq_e], dc_base + UMC_INITCTLC);
- writel(umc_drmmr0[freq], dc_base + UMC_DRMMR0);
+ writel(umc_drmmr0[freq_e], dc_base + UMC_DRMMR0);
writel(0x00000004, dc_base + UMC_DRMMR1);
- writel(umc_drmmr2[freq], dc_base + UMC_DRMMR2);
+ writel(umc_drmmr2[freq_e], dc_base + UMC_DRMMR2);
writel(0x00000000, dc_base + UMC_DRMMR3);
- writel(umc_memconf0a[freq][size_e], dc_base + UMC_MEMCONF0A);
- writel(umc_memconf0b[freq][size_e], dc_base + UMC_MEMCONF0B);
- writel(umc_memconfch[freq][size_e], dc_base + UMC_MEMCONFCH);
+ writel(umc_memconf0a[freq_e][size_e], dc_base + UMC_MEMCONF0A);
+ writel(umc_memconf0b[freq_e][size_e], dc_base + UMC_MEMCONF0B);
+ writel(umc_memconfch[freq_e][size_e], dc_base + UMC_MEMCONFCH);
writel(0x00000008, dc_base + UMC_MEMMAPSET);
- writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
- writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
- writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
- writel(umc_cmdctle[freq][size_e], dc_base + UMC_CMDCTLE);
+ writel(umc_cmdctla[freq_e], dc_base + UMC_CMDCTLA);
+ writel(umc_cmdctlb[freq_e], dc_base + UMC_CMDCTLB);
+ writel(umc_cmdctlc[freq_e], dc_base + UMC_CMDCTLC);
+ writel(umc_cmdctle[freq_e][size_e], dc_base + UMC_CMDCTLE);
- writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0);
- writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1);
+ writel(umc_rdatactl_d0[freq_e], dc_base + UMC_RDATACTL_D0);
+ writel(umc_rdatactl_d1[freq_e], dc_base + UMC_RDATACTL_D1);
- writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0);
- writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1);
- writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0);
- writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1);
- writel(umc_dataset[freq], dc_base + UMC_DATASET);
+ writel(umc_wdatactl_d0[freq_e], dc_base + UMC_WDATACTL_D0);
+ writel(umc_wdatactl_d1[freq_e], dc_base + UMC_WDATACTL_D1);
+ writel(umc_odtctl_d0[freq_e], dc_base + UMC_ODTCTL_D0);
+ writel(umc_odtctl_d1[freq_e], dc_base + UMC_ODTCTL_D1);
+ writel(umc_dataset[freq_e], dc_base + UMC_DATASET);
writel(0x00400020, dc_base + UMC_DCCGCTL);
writel(0x00000003, dc_base + UMC_ACSSETA);
writel(0x00000103, dc_base + UMC_FLOWCTLG);
writel(0x00010200, dc_base + UMC_ACSSETB);
- writel(umc_flowctla[freq], dc_base + UMC_FLOWCTLA);
+ writel(umc_flowctla[freq_e], dc_base + UMC_FLOWCTLA);
writel(0x00004444, dc_base + UMC_FLOWCTLC);
writel(0x00000000, dc_base + UMC_DFICUPDCTLA);
}
static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base,
- enum dram_freq freq, enum dram_board board,
+ enum dram_board board, unsigned int freq,
unsigned long size, int ch)
{
void __iomem *dc_base = umc_ch_base + 0x00011000;
writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
dc_base + UMC_DIOCTLA);
- ddrphy_init(phy_base, dc_base, freq, board, ch);
+ ddrphy_init(phy_base, board, ch);
+
+ umc_poll_phy_init_complete(dc_base);
+
+ ddrphy_init_tail(phy_base, board, freq, ch);
ret = umc_dc_init(dc_base, freq, size, ch);
if (ret)
void __iomem *um_base = (void __iomem *)0x5b600000;
void __iomem *umc_ch_base = (void __iomem *)0x5b800000;
void __iomem *phy_ch_base = (void __iomem *)0x6e200000;
- enum dram_freq freq;
enum dram_board board;
int ch, ret;
- switch (bd->dram_freq) {
- case 1866:
- freq = DRAM_FREQ_1866M;
- break;
- default:
- pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
- return -EINVAL;
- }
-
switch (UNIPHIER_BD_BOARD_GET_TYPE(bd->flags)) {
case UNIPHIER_BD_BOARD_LD20_REF:
board = DRAM_BOARD_LD20_REF;
unsigned long size = bd->dram_ch[ch].size;
unsigned int width = bd->dram_ch[ch].width;
- ret = umc_ch_init(umc_ch_base, phy_ch_base, freq, board,
- size / (width / 16), ch);
+ ret = umc_ch_init(umc_ch_base, phy_ch_base, board,
+ bd->dram_freq, size / (width / 16), ch);
if (ret) {
pr_err("failed to initialize UMC ch%d\n", ch);
return ret;
{
uniphier_sbc_init_savepin(bd);
uniphier_pxs2_sbc_init(bd);
- uniphier_pin_init("system_bus_grp");
+ /* pins for NAND and System Bus are multiplexed */
+ if (spl_boot_device() != BOOT_DEVICE_NAND)
+ uniphier_pin_init("system_bus_grp");
support_card_reset();
{
uniphier_sbc_init_savepin(bd);
uniphier_pxs2_sbc_init(bd);
- uniphier_pin_init("system_bus_grp");
+ /* pins for NAND and System Bus are multiplexed */
+ if (spl_boot_device() != BOOT_DEVICE_NAND)
+ uniphier_pin_init("system_bus_grp");
support_card_reset();
/*
* After power on, we need to keep the LAN controller in reset state
* for a while. (200 usec)
- * Fortunately, enough wait time is already inserted in pll_init()
- * function. So we do not have to wait here.
*/
+ udelay(200);
support_card_reset_deassert();
}
}
#endif
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_CPU CONFIG_BFIN_CPU
int os_dirent_ls(const char *dirname, struct os_dirent_node **headp)
{
- struct dirent entry, *result;
+ struct dirent *entry;
struct os_dirent_node *head, *node, *next;
struct stat buf;
DIR *dir;
int ret;
char *fname;
int len;
+ int dirlen;
*headp = NULL;
dir = opendir(dirname);
if (!dir)
return -1;
- /* Create a buffer for the maximum filename length */
- len = sizeof(entry.d_name) + strlen(dirname) + 2;
+ /* Create a buffer upfront, with typically sufficient size */
+ dirlen = strlen(dirname) + 2;
+ len = dirlen + 256;
fname = malloc(len);
if (!fname) {
ret = -ENOMEM;
}
for (node = head = NULL;; node = next) {
- ret = readdir_r(dir, &entry, &result);
- if (ret || !result)
+ errno = 0;
+ entry = readdir(dir);
+ if (!entry) {
+ ret = errno;
break;
- next = malloc(sizeof(*node) + strlen(entry.d_name) + 1);
- if (!next) {
+ }
+ next = malloc(sizeof(*node) + strlen(entry->d_name) + 1);
+ if (dirlen + strlen(entry->d_name) > len) {
+ len = dirlen + strlen(entry->d_name);
+ fname = realloc(fname, len);
+ }
+ if (!next || !fname) {
+ free(next);
os_dirent_free(head);
ret = -ENOMEM;
goto done;
}
next->next = NULL;
- strcpy(next->name, entry.d_name);
- switch (entry.d_type) {
+ strcpy(next->name, entry->d_name);
+ switch (entry->d_type) {
case DT_REG:
next->type = OS_FILET_REG;
break;
case DT_LNK:
next->type = OS_FILET_LNK;
break;
+ default:
+ next->type = OS_FILET_UNKNOWN;
}
next->size = 0;
snprintf(fname, len, "%s/%s", dirname, next->name);
next->size = buf.st_size;
if (node)
node->next = next;
- if (!head)
- head = node;
+ else
+ head = next;
}
*headp = head;
phys_addr_t map_to_sysmem(const void *ptr);
/* Define nops for sandbox I/O access */
-#define readb(addr) 0
-#define readw(addr) 0
-#define readl(addr) 0
-#define writeb(v, addr)
-#define writew(v, addr)
-#define writel(v, addr)
+#define readb(addr) ((void)addr, 0)
+#define readw(addr) ((void)addr, 0)
+#define readl(addr) ((void)addr, 0)
+#define writeb(v, addr) ((void)addr)
+#define writew(v, addr) ((void)addr)
+#define writel(v, addr) ((void)addr)
/* I/O access functions */
int inl(unsigned int addr);
#include <asm/post.h>
static struct pci_device_id mmc_supported[] = {
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SDIO },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SD },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_EMMC2 },
{},
};
static const struct udevice_id broadwell_syscon_ids[] = {
{ .compatible = "intel,me", .data = X86_SYSCON_ME },
- { .compatible = "intel,gma", .data = X86_SYSCON_GMA },
{ }
};
bool
default y
-config VIDEO_COREBOOT
- bool
- default y
-
endif
struct gdt_ptr gdt;
gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
- gdt.ptr = (u32)boot_gdt;
+ gdt.ptr = (ulong)boot_gdt;
asm volatile("lgdtl %0\n" : : "m" (gdt));
}
memset(pgtable, '\0', PAGETABLE_SIZE);
/* Level 4 needs a single entry */
- pgtable[0] = (uint32_t)&pgtable[1024] + 7;
+ pgtable[0] = (ulong)&pgtable[1024] + 7;
/* Level 3 has one 64-bit entry for each GiB of memory */
- for (i = 0; i < 4; i++) {
- pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
- 0x1000 * i + 7;
- }
+ for (i = 0; i < 4; i++)
+ pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7;
/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
for (i = 0; i < 2048; i++)
void set_vector(u8 intnum, void *routine)
{
- idt[intnum].base_high = (u16)((u32)(routine) >> 16);
- idt[intnum].base_low = (u16)((u32)(routine) & 0xffff);
+ idt[intnum].base_high = (u16)((ulong)(routine) >> 16);
+ idt[intnum].base_low = (u16)((ulong)(routine) & 0xffff);
}
/*
{
long flags;
+#ifdef CONFIG_X86_64
+ asm volatile ("pushfq ; popq %0 ; cli\n" : "=g" (flags) : );
+#else
asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
-
+#endif
return flags & X86_EFLAGS_IF;
}
else
obj-y += cpu.o
obj-y += early_me.o
-obj-y += gma.o
obj-y += lpc.o
obj-y += model_206ax.o
obj-y += northbridge.o
#include <fdtdec.h>
#include <malloc.h>
#include <pch.h>
-#include <syscon.h>
#include <asm/cpu.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/lapic.h>
#include <asm/lpc_common.h>
#include <asm/pci.h>
-#include <asm/arch/bd82x6x.h>
#include <asm/arch/model_206ax.h>
#include <asm/arch/pch.h>
#include <asm/arch/sandybridge.h>
static int bd82x6x_probe(struct udevice *dev)
{
- struct udevice *gma_dev;
- int ret;
-
if (!(gd->flags & GD_FLG_RELOC))
return 0;
/* Cause the SATA device to do its init */
uclass_first_device(UCLASS_AHCI, &dev);
- ret = syscon_get_by_driver_data(X86_SYSCON_GMA, &gma_dev);
- if (ret)
- return ret;
- ret = gma_func0_init(gma_dev);
- if (ret)
- return ret;
-
return 0;
}
#endif /* CONFIG_HAVE_FSP */
static const struct udevice_id ivybridge_syscon_ids[] = {
{ .compatible = "intel,me", .data = X86_SYSCON_ME },
- { .compatible = "intel,gma", .data = X86_SYSCON_GMA },
{ }
};
+++ /dev/null
-/*
- * From Coreboot file of the same name
- *
- * Copyright (C) 2012 Chromium OS Authors
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-/* mailbox 0: header */
-__packed struct opregion_header {
- u8 signature[16];
- u32 size;
- u32 version;
- u8 sbios_version[32];
- u8 vbios_version[16];
- u8 driver_version[16];
- u32 mailboxes;
- u8 reserved[164];
-};
-
-#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
-#define IGD_OPREGION_VERSION 2
-
-#define IGD_MBOX1 (1 << 0)
-#define IGD_MBOX2 (1 << 1)
-#define IGD_MBOX3 (1 << 2)
-#define IGD_MBOX4 (1 << 3)
-#define IGD_MBOX5 (1 << 4)
-
-#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
- IGD_MBOX4 | IGD_MBOX5)
-#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
-
-#define SBIOS_VERSION_SIZE 32
-
-/* mailbox 1: public acpi methods */
-__packed struct opregion_mailbox1 {
- u32 drdy;
- u32 csts;
- u32 cevt;
- u8 reserved1[20];
- u32 didl[8];
- u32 cpdl[8];
- u32 cadl[8];
- u32 nadl[8];
- u32 aslp;
- u32 tidx;
- u32 chpd;
- u32 clid;
- u32 cdck;
- u32 sxsw;
- u32 evts;
- u32 cnot;
- u32 nrdy;
- u8 reserved2[60];
-};
-
-/* mailbox 2: software sci interface */
-__packed struct opregion_mailbox2 {
- u32 scic;
- u32 parm;
- u32 dslp;
- u8 reserved[244];
-};
-
-/* mailbox 3: power conservation */
-__packed struct opregion_mailbox3 {
- u32 ardy;
- u32 aslc;
- u32 tche;
- u32 alsi;
- u32 bclp;
- u32 pfit;
- u32 cblv;
- u16 bclm[20];
- u32 cpfm;
- u32 epfm;
- u8 plut[74];
- u32 pfmb;
- u32 ccdv;
- u32 pcft;
- u8 reserved[94];
-};
-
-#define IGD_BACKLIGHT_BRIGHTNESS 0xff
-#define IGD_INITIAL_BRIGHTNESS 0x64
-
-#define IGD_FIELD_VALID (1 << 31)
-#define IGD_WORD_FIELD_VALID (1 << 15)
-#define IGD_PFIT_STRETCH 6
-
-/* mailbox 4: vbt */
-__packed struct {
- u8 gvd1[7168];
-} opregion_vbt_t;
-
-/* IGD OpRegion */
-__packed struct igd_opregion {
- opregion_header_t header;
- opregion_mailbox1_t mailbox1;
- opregion_mailbox2_t mailbox2;
- opregion_mailbox3_t mailbox3;
- opregion_vbt_t vbt;
-};
-
-/* Intel Video BIOS (Option ROM) */
-__packed struct optionrom_header {
- u16 signature;
- u8 size;
- u8 reserved[21];
- u16 pcir_offset;
- u16 vbt_offset;
-};
-
-#define OPROM_SIGNATURE 0xaa55
-
-__packed struct optionrom_pcir {
- u32 signature;
- u16 vendor;
- u16 device;
- u16 reserved1;
- u16 length;
- u8 revision;
- u8 classcode[3];
- u16 imagelength;
- u16 coderevision;
- u8 codetype;
- u8 indicator;
- u16 reserved2;
-};
-
-__packed struct optionrom_vbt {
- u8 hdr_signature[20];
- u16 hdr_version;
- u16 hdr_size;
- u16 hdr_vbt_size;
- u8 hdr_vbt_checksum;
- u8 hdr_reserved;
- u32 hdr_vbt_datablock;
- u32 hdr_aim[4];
- u8 datahdr_signature[16];
- u16 datahdr_version;
- u16 datahdr_size;
- u16 datahdr_datablocksize;
- u8 coreblock_id;
- u16 coreblock_size;
- u16 coreblock_biossize;
- u8 coreblock_biostype;
- u8 coreblock_releasestatus;
- u8 coreblock_hwsupported;
- u8 coreblock_integratedhw;
- u8 coreblock_biosbuild[4];
- u8 coreblock_biossignon[155];
-};
-
-#define VBT_SIGNATURE 0x54425624
dm_pci_read_config16(pch, 0x40, &pmbase);
pmbase &= 0xfffe;
- writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
- "intel,gpe0-enable", 0));
- writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node,
- "intel,alt-gp-smi-enable", 0));
+ writel(fdtdec_get_int(blob, node, "intel,gpe0-enable", 0),
+ (ulong)pmbase + GPE0_EN);
+ writew(fdtdec_get_int(blob, node, "intel,alt-gp-smi-enable", 0),
+ (ulong)pmbase + ALT_GP_SMI_EN);
/* Set up power management block and determine sleep mode */
reg32 = inl(pmbase + 0x04); /* PM1_CNT */
reg16 |= (1 << 2) | (1 << 11);
dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
- pch_iobp_update(pch, 0xEB007F07, ~0UL, (1 << 31));
- pch_iobp_update(pch, 0xEB004000, ~0UL, (1 << 7));
- pch_iobp_update(pch, 0xEC007F07, ~0UL, (1 << 31));
- pch_iobp_update(pch, 0xEC004000, ~0UL, (1 << 7));
+ pch_iobp_update(pch, 0xeb007f07, ~0U, 1 << 31);
+ pch_iobp_update(pch, 0xeb004000, ~0U, 1 << 7);
+ pch_iobp_update(pch, 0xec007f07, ~0U, 1 << 31);
+ pch_iobp_update(pch, 0xec004000, ~0U, 1 << 7);
reg32 = readl(RCB_REG(CG));
reg32 |= (1 << 31);
#include <asm/processor.h>
#include <asm/speedstep.h>
#include <asm/turbo.h>
-#include <asm/arch/bd82x6x.h>
#include <asm/arch/model_206ax.h>
static void enable_vmx(void)
#include <asm/pch_common.h>
#include <asm/pci.h>
#include <asm/arch/pch.h>
-#include <asm/arch/bd82x6x.h>
DECLARE_GLOBAL_DATA_PTR;
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+/include/ "coreboot_fb.dtsi"
/ {
model = "Intel Bayley Bay";
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+/include/ "coreboot_fb.dtsi"
/ {
model = "Advantech SOM-6896";
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+/include/ "coreboot_fb.dtsi"
/ {
model = "Google Link";
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+/include/ "coreboot_fb.dtsi"
/ {
model = "Google Samus";
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+/include/ "coreboot_fb.dtsi"
/ {
model = "Google Panther";
--- /dev/null
+/ {
+ coreboot-fb {
+ compatible = "coreboot-fb";
+ };
+};
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+/include/ "coreboot_fb.dtsi"
/ {
model = "Intel Minnowboard Max";
+++ /dev/null
-/*
- * Copyright (C) 2014 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_BD82X6X_H
-#define _ASM_ARCH_BD82X6X_H
-
-int gma_func0_init(struct udevice *dev);
-
-#endif
__u32 payload_offset;
__u32 payload_length;
__u64 setup_data;
+ __u64 pref_address;
+ __u32 init_size;
+ __u32 handover_offset;
} __attribute__((packed));
struct sys_desc_table {
enum {
X86_NONE,
X86_SYSCON_ME, /* Intel Management Engine */
- X86_SYSCON_GMA, /* Intel Graphics Media Accelerator */
X86_SYSCON_PINCONF, /* Intel x86 pin configuration */
};
#define _INIT_HELPERS_H_
int init_cache_f_r(void);
-int init_bd_struct_r(void);
-int init_func_spi(void);
#endif /* !_INIT_HELPERS_H_ */
#define __HAVE_ARCH_MEMCPY
extern void * memcpy(void *, const void *, __kernel_size_t);
-#undef __HAVE_ARCH_MEMMOVE
+#define __HAVE_ARCH_MEMMOVE
extern void * memmove(void *, const void *, __kernel_size_t);
#undef __HAVE_ARCH_MEMCHR
/* Initialise the CPU cache(s) */
return init_cache();
}
-
-bd_t bd_data;
-
-int init_bd_struct_r(void)
-{
- gd->bd = &bd_data;
- memset(gd->bd, 0, sizeof(bd_t));
-
- return 0;
-}
/* Find the flash chip within the SPI controller node */
node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
- if (node < 0)
+ if (node < 0) {
+ debug("%s: Cannot find SPI flash\n", __func__);
return -ENOENT;
+ }
if (fdtdec_get_int_array(blob, node, "memory-map", reg, 2))
- return -FDT_ERR_NOTFOUND;
+ return -EINVAL;
entry->base = reg[0];
/* Find the place where we put the MRC cache */
return -EPERM;
if (fdtdec_get_int_array(blob, mrc_node, "reg", reg, 2))
- return -FDT_ERR_NOTFOUND;
+ return -EINVAL;
entry->offset = reg[0];
entry->length = reg[1];
return dstpp;
}
+
+void *memmove(void *dest, const void *src, size_t n)
+{
+ int d0, d1, d2, d3, d4, d5;
+ char *ret = dest;
+
+ __asm__ __volatile__(
+ /* Handle more 16 bytes in loop */
+ "cmp $0x10, %0\n\t"
+ "jb 1f\n\t"
+
+ /* Decide forward/backward copy mode */
+ "cmp %2, %1\n\t"
+ "jb 2f\n\t"
+
+ /*
+ * movs instruction have many startup latency
+ * so we handle small size by general register.
+ */
+ "cmp $680, %0\n\t"
+ "jb 3f\n\t"
+ /* movs instruction is only good for aligned case */
+ "mov %1, %3\n\t"
+ "xor %2, %3\n\t"
+ "and $0xff, %3\n\t"
+ "jz 4f\n\t"
+ "3:\n\t"
+ "sub $0x10, %0\n\t"
+
+ /* We gobble 16 bytes forward in each loop */
+ "3:\n\t"
+ "sub $0x10, %0\n\t"
+ "mov 0*4(%1), %3\n\t"
+ "mov 1*4(%1), %4\n\t"
+ "mov %3, 0*4(%2)\n\t"
+ "mov %4, 1*4(%2)\n\t"
+ "mov 2*4(%1), %3\n\t"
+ "mov 3*4(%1), %4\n\t"
+ "mov %3, 2*4(%2)\n\t"
+ "mov %4, 3*4(%2)\n\t"
+ "lea 0x10(%1), %1\n\t"
+ "lea 0x10(%2), %2\n\t"
+ "jae 3b\n\t"
+ "add $0x10, %0\n\t"
+ "jmp 1f\n\t"
+
+ /* Handle data forward by movs */
+ ".p2align 4\n\t"
+ "4:\n\t"
+ "mov -4(%1, %0), %3\n\t"
+ "lea -4(%2, %0), %4\n\t"
+ "shr $2, %0\n\t"
+ "rep movsl\n\t"
+ "mov %3, (%4)\n\t"
+ "jmp 11f\n\t"
+ /* Handle data backward by movs */
+ ".p2align 4\n\t"
+ "6:\n\t"
+ "mov (%1), %3\n\t"
+ "mov %2, %4\n\t"
+ "lea -4(%1, %0), %1\n\t"
+ "lea -4(%2, %0), %2\n\t"
+ "shr $2, %0\n\t"
+ "std\n\t"
+ "rep movsl\n\t"
+ "mov %3,(%4)\n\t"
+ "cld\n\t"
+ "jmp 11f\n\t"
+
+ /* Start to prepare for backward copy */
+ ".p2align 4\n\t"
+ "2:\n\t"
+ "cmp $680, %0\n\t"
+ "jb 5f\n\t"
+ "mov %1, %3\n\t"
+ "xor %2, %3\n\t"
+ "and $0xff, %3\n\t"
+ "jz 6b\n\t"
+
+ /* Calculate copy position to tail */
+ "5:\n\t"
+ "add %0, %1\n\t"
+ "add %0, %2\n\t"
+ "sub $0x10, %0\n\t"
+
+ /* We gobble 16 bytes backward in each loop */
+ "7:\n\t"
+ "sub $0x10, %0\n\t"
+
+ "mov -1*4(%1), %3\n\t"
+ "mov -2*4(%1), %4\n\t"
+ "mov %3, -1*4(%2)\n\t"
+ "mov %4, -2*4(%2)\n\t"
+ "mov -3*4(%1), %3\n\t"
+ "mov -4*4(%1), %4\n\t"
+ "mov %3, -3*4(%2)\n\t"
+ "mov %4, -4*4(%2)\n\t"
+ "lea -0x10(%1), %1\n\t"
+ "lea -0x10(%2), %2\n\t"
+ "jae 7b\n\t"
+ /* Calculate copy position to head */
+ "add $0x10, %0\n\t"
+ "sub %0, %1\n\t"
+ "sub %0, %2\n\t"
+
+ /* Move data from 8 bytes to 15 bytes */
+ ".p2align 4\n\t"
+ "1:\n\t"
+ "cmp $8, %0\n\t"
+ "jb 8f\n\t"
+ "mov 0*4(%1), %3\n\t"
+ "mov 1*4(%1), %4\n\t"
+ "mov -2*4(%1, %0), %5\n\t"
+ "mov -1*4(%1, %0), %1\n\t"
+
+ "mov %3, 0*4(%2)\n\t"
+ "mov %4, 1*4(%2)\n\t"
+ "mov %5, -2*4(%2, %0)\n\t"
+ "mov %1, -1*4(%2, %0)\n\t"
+ "jmp 11f\n\t"
+
+ /* Move data from 4 bytes to 7 bytes */
+ ".p2align 4\n\t"
+ "8:\n\t"
+ "cmp $4, %0\n\t"
+ "jb 9f\n\t"
+ "mov 0*4(%1), %3\n\t"
+ "mov -1*4(%1, %0), %4\n\t"
+ "mov %3, 0*4(%2)\n\t"
+ "mov %4, -1*4(%2, %0)\n\t"
+ "jmp 11f\n\t"
+
+ /* Move data from 2 bytes to 3 bytes */
+ ".p2align 4\n\t"
+ "9:\n\t"
+ "cmp $2, %0\n\t"
+ "jb 10f\n\t"
+ "movw 0*2(%1), %%dx\n\t"
+ "movw -1*2(%1, %0), %%bx\n\t"
+ "movw %%dx, 0*2(%2)\n\t"
+ "movw %%bx, -1*2(%2, %0)\n\t"
+ "jmp 11f\n\t"
+
+ /* Move data for 1 byte */
+ ".p2align 4\n\t"
+ "10:\n\t"
+ "cmp $1, %0\n\t"
+ "jb 11f\n\t"
+ "movb (%1), %%cl\n\t"
+ "movb %%cl, (%2)\n\t"
+ ".p2align 4\n\t"
+ "11:"
+ : "=&c" (d0), "=&S" (d1), "=&D" (d2),
+ "=r" (d3), "=r" (d4), "=r"(d5)
+ : "0" (n),
+ "1" (src),
+ "2" (dest)
+ : "memory");
+
+ return ret;
+}
--- /dev/null
+if TARGET_DS109
+
+config SYS_BOARD
+ default "ds109"
+
+config SYS_VENDOR
+ default "Synology"
+
+config SYS_CONFIG_NAME
+ default "ds109"
+
+endif
--- /dev/null
+DS109 BOARD
+M: Walter Schweizer <swwa@users.sourceforge.net>
+S: Maintained
+F: board/Synology/ds109
+F: configs/ds109_defconfig
+F: include/configs/ds109.h
--- /dev/null
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ds109.o
--- /dev/null
+/*
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include "ds109.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(DS109_OE_VAL_LOW,
+ DS109_OE_VAL_HIGH,
+ DS109_OE_LOW, DS109_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_SPI_SCn, /* SPI Flash */
+ MPP1_SPI_MOSI,
+ MPP2_SPI_SCK,
+ MPP3_SPI_MISO,
+ MPP4_GPIO,
+ MPP5_GPO,
+ MPP6_SYSRST_OUTn, /* Reset signal */
+ MPP7_GPO,
+ MPP8_TW_SDA, /* I2C */
+ MPP9_TW_SCK, /* I2C */
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO,
+ MPP13_UART1_TXD,
+ MPP14_UART1_RXD,
+ MPP15_GPIO,
+ MPP16_GPIO,
+ MPP17_GPIO,
+ MPP18_GPO,
+ MPP19_GPO,
+ MPP20_SATA1_ACTn,
+ MPP21_SATA0_ACTn,
+ MPP22_GPIO, /* HDD2 FAIL LED */
+ MPP23_GPIO, /* HDD1 FAIL LED */
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GPIO,
+ MPP31_GPIO, /* HDD2 */
+ MPP32_GPIO, /* FAN A */
+ MPP33_GPIO, /* FAN B */
+ MPP34_GPIO, /* FAN C */
+ MPP35_GPIO, /* FAN SENSE */
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_GPIO,
+ MPP41_GPIO,
+ MPP42_GPIO,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO,
+ MPP48_GPIO,
+ MPP49_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+/* Synology reset uses UART */
+#include <ns16550.h>
+#define SOFTWARE_SHUTDOWN 0x31
+#define SOFTWARE_REBOOT 0x43
+#define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE
+void reset_misc(void)
+{
+ int b_d;
+ printf("Synology reset...");
+ udelay(50000);
+
+ b_d = ns16550_calc_divisor((NS16550_t)CONFIG_SYS_NS16550_COM2,
+ CONFIG_SYS_NS16550_CLK, 9600);
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM2, b_d);
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM2, SOFTWARE_REBOOT);
+}
+
+/* Support old kernels */
+void setup_board_tags(struct tag **in_params)
+{
+ unsigned int boardId;
+ struct tag *params;
+ struct tag_mv_uboot *t;
+ int i;
+
+ printf("Synology board tags...");
+ params = *in_params;
+ t = (struct tag_mv_uboot *)¶ms->u;
+
+ t->uboot_version = VER_NUM;
+
+ boardId = SYNO_DS109_ID;
+ t->uboot_version |= boardId;
+
+ t->tclk = CONFIG_SYS_TCLK;
+ t->sysclk = CONFIG_SYS_TCLK*2;
+
+ t->isusbhost = 1;
+ for (i = 0; i < 4; i++) {
+ memset(t->macaddr[i], 0, sizeof(t->macaddr[i]));
+ t->mtu[i] = 0;
+ }
+
+ params->hdr.tag = ATAG_MV_UBOOT;
+ params->hdr.size = tag_size(tag_mv_uboot);
+ params = tag_next(params);
+ *in_params = params;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
+ printf("Error: 88E1116 could not read PHY dev address\n");
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
--- /dev/null
+/*
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DS109_H
+#define __DS109_H
+
+#define DS109_OE_LOW (0)
+#define DS109_OE_HIGH (0)
+#define DS109_OE_VAL_LOW ((1 << 22)|(1 << 23))
+#define DS109_OE_VAL_HIGH ((1 << 1)|1)
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_MAC_CTRL2_REG 21
+
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+/* Marvell uboot parameters */
+#define ATAG_MV_UBOOT 0x41000403
+#define VER_NUM 0x03040400 /* 3.4.4 */
+#define BOARD_ID_BASE 0x0
+#define SYNO_DS109_ID (BOARD_ID_BASE+0x15)
+
+struct tag_mv_uboot {
+ u32 uboot_version;
+ u32 tclk;
+ u32 sysclk;
+ u32 isusbhost;
+ char macaddr[4][6];
+ u16 mtu[4];
+ u32 fw_image_base;
+ u32 fw_image_size;
+};
+
+#endif /* __DS109_H */
--- /dev/null
+#
+# (C) Copyright 2011
+# Jason Cooper <u-boot@lakedaemon.net>
+#
+# Based on work by:
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+DATA 0xFFD20134 0xbbbbbbbb
+DATA 0xFFD20138 0x00bbbbbb
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000d # DDR Address Control
+# bit1-0: 01, Cs0width=x8
+# bit3-2: 10, Cs0size=1Gb
+# bit5-4: 01, Cs1width=x8
+# bit7-6: 10, Cs1size=1Gb
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000042 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+
+DATA 0xFFD01510 0x20000000 # CS[2]n Base address to 256Mb
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD01518 0x30000000 # CS[3]n Base address to 256Mb
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x003C0000 # DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000F80F # CPU ODT Control
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
--- /dev/null
+# Synology DS109
+
+interface ftdi
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x000b
+ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040
+
+adapter_khz 2000
+
+# length of reset signal: [ms]
+adapter_nsrst_assert_width 1000
+
+# don't talk to JTAG after reset for: [ms]
+adapter_nsrst_delay 200
+
+source [find target/feroceon.cfg]
+
+reset_config trst_and_srst srst_nogate
+
+proc ds109_init { } {
+
+ # We need to assert DBGRQ while holding nSRST down.
+ # However DBGACK will be set only when nSRST is released.
+ # Furthermore, the JTAG interface doesn't respond at all when
+ # the CPU is in the WFI (wait for interrupts) state, so it is
+ # possible that initial tap examination failed. So let's
+ # re-examine the target again here when nSRST is asserted which
+ # should then succeed.
+ jtag_reset 0 1
+ feroceon.cpu arp_examine
+ halt 0
+ jtag_reset 0 0
+ wait_halt
+ #reset run
+ #soft_reset_halt
+
+ arm mcr 15 0 0 1 0 0x00052078
+
+ mww 0xD00100e0 0x1b1b1b9b ;#
+ mww 0xD0020134 0xbbbbbbbb ;#
+ mww 0xD0020138 0x00bbbbbb ;#
+ mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register
+ mww 0xD0001404 0x39743000 ;# Dunit Control Low Register
+ mww 0xD0001408 0x22125551 ;# DDR SDRAM Timing (Low) Register
+ mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register
+ mww 0xD0001410 0x0000000d ;# DDR SDRAM Address Control Register
+ mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register
+ mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register
+ mww 0xD000141C 0x00000C62 ;# DDR SDRAM Mode Register
+ mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register
+ mww 0xD0001424 0x0000F1FF ;# Dunit Control High Register
+ mww 0xD0001428 0x00085520 ;# Dunit Control High Register
+ mww 0xD000147c 0x00008552 ;# Dunit Control High Register
+ mww 0xD0001500 0x00000000 ;#
+ mww 0xD0001504 0x07FFFFF1 ;# CS0n Size Register
+ mww 0xD0001508 0x10000000 ;# CS1n Base Register
+ mww 0xD000150C 0x00000000 ;# CS1n Size Register
+ mww 0xD0001510 0x20000000 ;#
+ mww 0xD0001514 0x00000000 ;# CS2n Size Register
+ mww 0xD000151C 0x00000000 ;# CS3n Size Register
+ mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register
+ mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
+ mww 0xD000149C 0x0000F80F ;# DDR2 Dunit ODT Control Register
+ mww 0xD0001480 0x00000001 ;# DDR SDRAM Initialization Control Register
+ mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+
+ mww 0xD0010000 0x01111111 ;# MPP 0 to 7
+ mww 0xD0010004 0x11113322 ;# MPP 8 to 15
+ mww 0xD0010008 0x00001111 ;# MPP 16 to 23
+}
+
+proc ds109_load { } {
+ # load u-Boot into RAM and execute it
+ ds109_init
+ load_image u-boot.bin 0x00600000 bin
+ resume 0x00600000
+}
config SYS_CONFIG_NAME
default "acadia"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
config SYS_CONFIG_NAME
default "bamboo"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
config SYS_CONFIG_NAME
default "bubinga"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
endchoice
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
config SYS_CONFIG_NAME
default "katmai"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
config SYS_CONFIG_NAME
default "kilauea"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
config SYS_CONFIG_NAME
default "luan"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
config SYS_CONFIG_NAME
default "makalu"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
config SYS_CONFIG_NAME
default "redwood"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
config SYS_CONFIG_NAME
default "sequoia"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
config SYS_CONFIG_NAME
default "walnut"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
config SYS_CONFIG_NAME
default "yosemite"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
config SYS_CONFIG_NAME
default "yucca"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
--- /dev/null
+------------------------------
+U-Boot console UART selection:
+------------------------------
+
+The U-Boot port for this congatec board currently supports two different
+configurations (defconfig files). The only difference is the UART that
+is used as the U-Boot console UART. The default defconfig file:
+
+conga-qeval20-qa3-e3845_defconfig
+
+provides this console on the UART0 which is provided via a Winbond
+Super-IO chip connected on the congatec Qseven 2.0 evaluation carrier
+board (conga-QEVAL). This UART is the one provided with a SubD9
+connector on the mainboard (the low one). The 2nd defconfig file:
+
+conga-qeval20-qa3-e3845-internal-uart_defconfig
+
+provides the U-Boot console on the BayTrail internal legacy UART,
+which is routed from the QSeven SoM to the X300 connector on the
+baseboard. Here is called COM2. The baseboard already provides the
+RS232 level shifters. So a TTL-USB UART adapter does not work in
+this case. The signals need to get connected directly to the
+RS232 level signals of the PC UART via some adapter cable.
*/
static void fsl_secboot_header_verification_failure(void)
{
- struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
- (CONFIG_SYS_SEC_MON_ADDR);
struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
- u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat);
/* 29th bit of OSPR is ITS */
u32 its = sfp_in32(&sfp_regs->ospr) >> 2;
- /*
- * Read the SEC_MON status register
- * Read SSM_ST field
- */
- sts = sec_mon_in32(&sec_mon_regs->hp_stat);
- if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) {
- if (its == 1)
- change_sec_mon_state(HPSR_SSM_ST_TRUST,
- HPSR_SSM_ST_SOFT_FAIL);
- else
- change_sec_mon_state(HPSR_SSM_ST_TRUST,
- HPSR_SSM_ST_NON_SECURE);
- }
+ if (its == 1)
+ set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL);
+ else
+ set_sec_mon_state(HPSR_SSM_ST_NON_SECURE);
printf("Generating reset request\n");
do_reset(NULL, 0, 0, NULL);
*/
static void fsl_secboot_image_verification_failure(void)
{
- struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
- (CONFIG_SYS_SEC_MON_ADDR);
struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
- u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat);
u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT;
- /*
- * Read the SEC_MON status register
- * Read SSM_ST field
- */
- sts = sec_mon_in32(&sec_mon_regs->hp_stat);
- if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) {
- if (its == 1) {
- change_sec_mon_state(HPSR_SSM_ST_TRUST,
- HPSR_SSM_ST_SOFT_FAIL);
-
- printf("Generating reset request\n");
- do_reset(NULL, 0, 0, NULL);
- /* If reset doesn't coocur, halt execution */
- do_esbc_halt(NULL, 0, 0, NULL);
-
- } else {
- change_sec_mon_state(HPSR_SSM_ST_TRUST,
- HPSR_SSM_ST_NON_SECURE);
- }
+ if (its == 1) {
+ set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL);
+
+ printf("Generating reset request\n");
+ do_reset(NULL, 0, 0, NULL);
+ /* If reset doesn't coocur, halt execution */
+ do_esbc_halt(NULL, 0, 0, NULL);
+
+ } else {
+ set_sec_mon_state(HPSR_SSM_ST_NON_SECURE);
}
}
0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB
0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB
0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
+
+LS1021a rev1.0 Soc specific Options/Settings
+--------------------------------------------
+If the LS1021a Soc is rev1.0, you need modify the configure file.
+Add the following define in include/configs/ls1021aqds.h:
+#define CONFIG_SKIP_LOWLEVEL_INIT
0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB
0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
+
+LS1021a rev1.0 Soc specific Options/Settings
+--------------------------------------------
+If the LS1021a Soc is rev1.0, you need modify the configure file.
+Add the following define in include/configs/ls1021atwr.h:
+#define CONFIG_SKIP_LOWLEVEL_INIT
config SYS_CONFIG_NAME
default "lwmon5"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
endmenu
+menu "Firmware commands"
+config CMD_CROS_EC
+ bool "Enable crosec command"
+ depends on CROS_EC
+ default y
+ help
+ Enable command-line access to the Chrome OS EC (Embedded
+ Controller). This provides the 'crosec' command which has
+ a number of sub-commands for performing EC tasks such as
+ updating its flash, accessing a small saved context area
+ and talking to the I2C bus behind the EC (if there is one).
+endmenu
+
menu "Filesystem commands"
config CMD_EXT2
bool "ext2 command support"
obj-$(CONFIG_HUSH_PARSER) += test.o
obj-$(CONFIG_CMD_TPM) += tpm.o
obj-$(CONFIG_CMD_TPM_TEST) += tpm_test.o
+obj-$(CONFIG_CMD_CROS_EC) += cros_ec.o
obj-$(CONFIG_CMD_TSI148) += tsi148.o
obj-$(CONFIG_CMD_UBI) += ubi.o
obj-$(CONFIG_CMD_UBIFS) += ubifs.o
--- /dev/null
+/*
+ * Chromium OS cros_ec driver
+ *
+ * Copyright (c) 2016 The Chromium OS Authors.
+ * Copyright (c) 2016 National Instruments Corp
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cros_ec.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+
+/* Note: depends on enum ec_current_image */
+static const char * const ec_current_image_name[] = {"unknown", "RO", "RW"};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * Perform a flash read or write command
+ *
+ * @param dev CROS-EC device to read/write
+ * @param is_write 1 do to a write, 0 to do a read
+ * @param argc Number of arguments
+ * @param argv Arguments (2 is region, 3 is address)
+ * @return 0 for ok, 1 for a usage error or -ve for ec command error
+ * (negative EC_RES_...)
+ */
+static int do_read_write(struct cros_ec_dev *dev, int is_write, int argc,
+ char * const argv[])
+{
+ uint32_t offset, size = -1U, region_size;
+ unsigned long addr;
+ char *endp;
+ int region;
+ int ret;
+
+ region = cros_ec_decode_region(argc - 2, argv + 2);
+ if (region == -1)
+ return 1;
+ if (argc < 4)
+ return 1;
+ addr = simple_strtoul(argv[3], &endp, 16);
+ if (*argv[3] == 0 || *endp != 0)
+ return 1;
+ if (argc > 4) {
+ size = simple_strtoul(argv[4], &endp, 16);
+ if (*argv[4] == 0 || *endp != 0)
+ return 1;
+ }
+
+ ret = cros_ec_flash_offset(dev, region, &offset, ®ion_size);
+ if (ret) {
+ debug("%s: Could not read region info\n", __func__);
+ return ret;
+ }
+ if (size == -1U)
+ size = region_size;
+
+ ret = is_write ?
+ cros_ec_flash_write(dev, (uint8_t *)addr, offset, size) :
+ cros_ec_flash_read(dev, (uint8_t *)addr, offset, size);
+ if (ret) {
+ debug("%s: Could not %s region\n", __func__,
+ is_write ? "write" : "read");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct cros_ec_dev *dev;
+ struct udevice *udev;
+ const char *cmd;
+ int ret = 0;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ cmd = argv[1];
+ if (0 == strcmp("init", cmd)) {
+ /* Remove any existing device */
+ ret = uclass_find_device(UCLASS_CROS_EC, 0, &udev);
+ if (!ret)
+ device_remove(udev);
+ ret = uclass_get_device(UCLASS_CROS_EC, 0, &udev);
+ if (ret) {
+ printf("Could not init cros_ec device (err %d)\n", ret);
+ return 1;
+ }
+ return 0;
+ }
+
+ ret = uclass_get_device(UCLASS_CROS_EC, 0, &udev);
+ if (ret) {
+ printf("Cannot get cros-ec device (err=%d)\n", ret);
+ return 1;
+ }
+ dev = dev_get_uclass_priv(udev);
+ if (0 == strcmp("id", cmd)) {
+ char id[MSG_BYTES];
+
+ if (cros_ec_read_id(dev, id, sizeof(id))) {
+ debug("%s: Could not read KBC ID\n", __func__);
+ return 1;
+ }
+ printf("%s\n", id);
+ } else if (0 == strcmp("info", cmd)) {
+ struct ec_response_mkbp_info info;
+
+ if (cros_ec_info(dev, &info)) {
+ debug("%s: Could not read KBC info\n", __func__);
+ return 1;
+ }
+ printf("rows = %u\n", info.rows);
+ printf("cols = %u\n", info.cols);
+ printf("switches = %#x\n", info.switches);
+ } else if (0 == strcmp("curimage", cmd)) {
+ enum ec_current_image image;
+
+ if (cros_ec_read_current_image(dev, &image)) {
+ debug("%s: Could not read KBC image\n", __func__);
+ return 1;
+ }
+ printf("%d\n", image);
+ } else if (0 == strcmp("hash", cmd)) {
+ struct ec_response_vboot_hash hash;
+ int i;
+
+ if (cros_ec_read_hash(dev, &hash)) {
+ debug("%s: Could not read KBC hash\n", __func__);
+ return 1;
+ }
+
+ if (hash.hash_type == EC_VBOOT_HASH_TYPE_SHA256)
+ printf("type: SHA-256\n");
+ else
+ printf("type: %d\n", hash.hash_type);
+
+ printf("offset: 0x%08x\n", hash.offset);
+ printf("size: 0x%08x\n", hash.size);
+
+ printf("digest: ");
+ for (i = 0; i < hash.digest_size; i++)
+ printf("%02x", hash.hash_digest[i]);
+ printf("\n");
+ } else if (0 == strcmp("reboot", cmd)) {
+ int region;
+ enum ec_reboot_cmd cmd;
+
+ if (argc >= 3 && !strcmp(argv[2], "cold")) {
+ cmd = EC_REBOOT_COLD;
+ } else {
+ region = cros_ec_decode_region(argc - 2, argv + 2);
+ if (region == EC_FLASH_REGION_RO)
+ cmd = EC_REBOOT_JUMP_RO;
+ else if (region == EC_FLASH_REGION_RW)
+ cmd = EC_REBOOT_JUMP_RW;
+ else
+ return CMD_RET_USAGE;
+ }
+
+ if (cros_ec_reboot(dev, cmd, 0)) {
+ debug("%s: Could not reboot KBC\n", __func__);
+ return 1;
+ }
+ } else if (0 == strcmp("events", cmd)) {
+ uint32_t events;
+
+ if (cros_ec_get_host_events(dev, &events)) {
+ debug("%s: Could not read host events\n", __func__);
+ return 1;
+ }
+ printf("0x%08x\n", events);
+ } else if (0 == strcmp("clrevents", cmd)) {
+ uint32_t events = 0x7fffffff;
+
+ if (argc >= 3)
+ events = simple_strtol(argv[2], NULL, 0);
+
+ if (cros_ec_clear_host_events(dev, events)) {
+ debug("%s: Could not clear host events\n", __func__);
+ return 1;
+ }
+ } else if (0 == strcmp("read", cmd)) {
+ ret = do_read_write(dev, 0, argc, argv);
+ if (ret > 0)
+ return CMD_RET_USAGE;
+ } else if (0 == strcmp("write", cmd)) {
+ ret = do_read_write(dev, 1, argc, argv);
+ if (ret > 0)
+ return CMD_RET_USAGE;
+ } else if (0 == strcmp("erase", cmd)) {
+ int region = cros_ec_decode_region(argc - 2, argv + 2);
+ uint32_t offset, size;
+
+ if (region == -1)
+ return CMD_RET_USAGE;
+ if (cros_ec_flash_offset(dev, region, &offset, &size)) {
+ debug("%s: Could not read region info\n", __func__);
+ ret = -1;
+ } else {
+ ret = cros_ec_flash_erase(dev, offset, size);
+ if (ret) {
+ debug("%s: Could not erase region\n",
+ __func__);
+ }
+ }
+ } else if (0 == strcmp("regioninfo", cmd)) {
+ int region = cros_ec_decode_region(argc - 2, argv + 2);
+ uint32_t offset, size;
+
+ if (region == -1)
+ return CMD_RET_USAGE;
+ ret = cros_ec_flash_offset(dev, region, &offset, &size);
+ if (ret) {
+ debug("%s: Could not read region info\n", __func__);
+ } else {
+ printf("Region: %s\n", region == EC_FLASH_REGION_RO ?
+ "RO" : "RW");
+ printf("Offset: %x\n", offset);
+ printf("Size: %x\n", size);
+ }
+ } else if (0 == strcmp("flashinfo", cmd)) {
+ struct ec_response_flash_info p;
+
+ ret = cros_ec_read_flashinfo(dev, &p);
+ if (!ret) {
+ printf("Flash size: %u\n", p.flash_size);
+ printf("Write block size: %u\n", p.write_block_size);
+ printf("Erase block size: %u\n", p.erase_block_size);
+ }
+ } else if (0 == strcmp("vbnvcontext", cmd)) {
+ uint8_t block[EC_VBNV_BLOCK_SIZE];
+ char buf[3];
+ int i, len;
+ unsigned long result;
+
+ if (argc <= 2) {
+ ret = cros_ec_read_vbnvcontext(dev, block);
+ if (!ret) {
+ printf("vbnv_block: ");
+ for (i = 0; i < EC_VBNV_BLOCK_SIZE; i++)
+ printf("%02x", block[i]);
+ putc('\n');
+ }
+ } else {
+ /*
+ * TODO(clchiou): Move this to a utility function as
+ * cmd_spi might want to call it.
+ */
+ memset(block, 0, EC_VBNV_BLOCK_SIZE);
+ len = strlen(argv[2]);
+ buf[2] = '\0';
+ for (i = 0; i < EC_VBNV_BLOCK_SIZE; i++) {
+ if (i * 2 >= len)
+ break;
+ buf[0] = argv[2][i * 2];
+ if (i * 2 + 1 >= len)
+ buf[1] = '0';
+ else
+ buf[1] = argv[2][i * 2 + 1];
+ strict_strtoul(buf, 16, &result);
+ block[i] = result;
+ }
+ ret = cros_ec_write_vbnvcontext(dev, block);
+ }
+ if (ret) {
+ debug("%s: Could not %s VbNvContext\n", __func__,
+ argc <= 2 ? "read" : "write");
+ }
+ } else if (0 == strcmp("test", cmd)) {
+ int result = cros_ec_test(dev);
+
+ if (result)
+ printf("Test failed with error %d\n", result);
+ else
+ puts("Test passed\n");
+ } else if (0 == strcmp("version", cmd)) {
+ struct ec_response_get_version *p;
+ char *build_string;
+
+ ret = cros_ec_read_version(dev, &p);
+ if (!ret) {
+ /* Print versions */
+ printf("RO version: %1.*s\n",
+ (int)sizeof(p->version_string_ro),
+ p->version_string_ro);
+ printf("RW version: %1.*s\n",
+ (int)sizeof(p->version_string_rw),
+ p->version_string_rw);
+ printf("Firmware copy: %s\n",
+ (p->current_image <
+ ARRAY_SIZE(ec_current_image_name) ?
+ ec_current_image_name[p->current_image] :
+ "?"));
+ ret = cros_ec_read_build_info(dev, &build_string);
+ if (!ret)
+ printf("Build info: %s\n", build_string);
+ }
+ } else if (0 == strcmp("ldo", cmd)) {
+ uint8_t index, state;
+ char *endp;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+ index = simple_strtoul(argv[2], &endp, 10);
+ if (*argv[2] == 0 || *endp != 0)
+ return CMD_RET_USAGE;
+ if (argc > 3) {
+ state = simple_strtoul(argv[3], &endp, 10);
+ if (*argv[3] == 0 || *endp != 0)
+ return CMD_RET_USAGE;
+ ret = cros_ec_set_ldo(udev, index, state);
+ } else {
+ ret = cros_ec_get_ldo(udev, index, &state);
+ if (!ret) {
+ printf("LDO%d: %s\n", index,
+ state == EC_LDO_STATE_ON ?
+ "on" : "off");
+ }
+ }
+
+ if (ret) {
+ debug("%s: Could not access LDO%d\n", __func__, index);
+ return ret;
+ }
+ } else {
+ return CMD_RET_USAGE;
+ }
+
+ if (ret < 0) {
+ printf("Error: CROS-EC command failed (error %d)\n", ret);
+ ret = 1;
+ }
+
+ return ret;
+}
+
+U_BOOT_CMD(
+ crosec, 6, 1, do_cros_ec,
+ "CROS-EC utility command",
+ "init Re-init CROS-EC (done on startup automatically)\n"
+ "crosec id Read CROS-EC ID\n"
+ "crosec info Read CROS-EC info\n"
+ "crosec curimage Read CROS-EC current image\n"
+ "crosec hash Read CROS-EC hash\n"
+ "crosec reboot [rw | ro | cold] Reboot CROS-EC\n"
+ "crosec events Read CROS-EC host events\n"
+ "crosec clrevents [mask] Clear CROS-EC host events\n"
+ "crosec regioninfo <ro|rw> Read image info\n"
+ "crosec flashinfo Read flash info\n"
+ "crosec erase <ro|rw> Erase EC image\n"
+ "crosec read <ro|rw> <addr> [<size>] Read EC image\n"
+ "crosec write <ro|rw> <addr> [<size>] Write EC image\n"
+ "crosec vbnvcontext [hexstring] Read [write] VbNvContext from EC\n"
+ "crosec ldo <idx> [<state>] Switch/Read LDO state\n"
+ "crosec test run tests on cros_ec\n"
+ "crosec version Read CROS-EC version"
+);
Any change to this variable will be reverted at the
next reset.
+config DISPLAY_CPUINFO
+ bool "Display information about the CPU during start up"
+ default y if ARM || BLACKFIN || NIOS2 || X86 || XTENSA
+ help
+ Display information about the CPU that U-Boot is running on
+ when U-Boot starts up. The function print_cpuinfo() is called
+ to do this.
+
+config DISPLAY_BOARDINFO
+ bool "Display information about the board during start up"
+ default y if ARM || M68K || MIPS || PPC || SPARC || XTENSA
+ help
+ Display information about the board that U-Boot is running on
+ when U-Boot starts up. The board function checkboard() is called
+ to do this.
+
source "common/spl/Kconfig"
#ifdef CONFIG_SANDBOX
sandbox_early_getopt_check,
#endif
-#ifdef CONFIG_OF_CONTROL
- fdtdec_prepare_fdt,
-#endif
display_options, /* say that we are here */
display_text_info, /* show debugging info if required */
#if defined(CONFIG_MPC8260)
return &(devs.list);
}
+#ifdef CONFIG_DM_VIDEO
+/**
+ * stdio_probe_device() - Find a device which provides the given stdio device
+ *
+ * This looks for a device of the given uclass which provides a particular
+ * stdio device. It is currently really only useful for UCLASS_VIDEO.
+ *
+ * Ultimately we want to be able to probe a device by its stdio name. At
+ * present devices register in their probe function (for video devices this
+ * is done in vidconsole_post_probe()) and we don't know what name they will
+ * use until they do so.
+ * TODO(sjg@chromium.org): We should be able to determine the name before
+ * probing, and probe the required device.
+ *
+ * @name: stdio device name (e.g. "vidconsole")
+ * id: Uclass ID of device to look for (e.g. UCLASS_VIDEO)
+ * @sdevp: Returns stdout device, if found, else NULL
+ * @return 0 if found, -ENOENT if no device found with that name, other -ve
+ * on other error
+ */
+static int stdio_probe_device(const char *name, enum uclass_id id,
+ struct stdio_dev **sdevp)
+{
+ struct stdio_dev *sdev;
+ struct udevice *dev;
+ int seq, ret;
+
+ *sdevp = NULL;
+ seq = trailing_strtoln(name, NULL);
+ if (seq == -1)
+ ret = uclass_first_device_err(id, &dev);
+ else
+ ret = uclass_get_device_by_seq(id, seq, &dev);
+ if (ret) {
+ debug("No %s device for seq %d (%s)\n", uclass_get_name(id),
+ seq, name);
+ return ret;
+ }
+ /* The device should be be the last one registered */
+ sdev = list_empty(&devs.list) ? NULL :
+ list_last_entry(&devs.list, struct stdio_dev, list);
+ if (!sdev || strcmp(sdev->name, name)) {
+ debug("Device '%s' did not register with stdio as '%s'\n",
+ dev->name, name);
+ return -ENOENT;
+ }
+ *sdevp = sdev;
+
+ return 0;
+}
+#endif
+
struct stdio_dev* stdio_get_by_name(const char *name)
{
struct list_head *pos;
- struct stdio_dev *dev;
+ struct stdio_dev *sdev;
if(!name)
return NULL;
list_for_each(pos, &(devs.list)) {
- dev = list_entry(pos, struct stdio_dev, list);
- if(strcmp(dev->name, name) == 0)
- return dev;
+ sdev = list_entry(pos, struct stdio_dev, list);
+ if (strcmp(sdev->name, name) == 0)
+ return sdev;
}
+#ifdef CONFIG_DM_VIDEO
+ /*
+ * We did not find a suitable stdio device. If there is a video
+ * driver with a name starting with 'vidconsole', we can try probing
+ * that in the hope that it will produce the required stdio device.
+ *
+ * This function is sometimes called with the entire value of
+ * 'stdout', which may include a list of devices separate by commas.
+ * Obviously this is not going to work, so we ignore that case. The
+ * call path in that case is console_init_r() -> search_device() ->
+ * stdio_get_by_name().
+ */
+ if (!strncmp(name, "vidconsole", 10) && !strchr(name, ',') &&
+ !stdio_probe_device(name, UCLASS_VIDEO, &sdev))
+ return sdev;
+#endif
return NULL;
}
#endif
#endif
#ifdef CONFIG_DM_VIDEO
+ /*
+ * If the console setting is not in environment variables then
+ * console_init_r() will not be calling iomux_doenv() (which calls
+ * search_device()). So we will not dynamically add devices by
+ * calling stdio_probe_device().
+ *
+ * So just probe all video devices now so that whichever one is
+ * required will be available.
+ */
+#ifndef CONFIG_SYS_CONSOLE_IS_IN_ENV
struct udevice *vdev;
# ifndef CONFIG_DM_KEYBOARD
int ret;
;
if (ret)
printf("%s: Video device failed (ret=%d)\n", __func__, ret);
+#endif /* !CONFIG_SYS_CONSOLE_IS_IN_ENV */
#else
# if defined(CONFIG_LCD)
drv_lcd_init ();
CONFIG_ARCH_SUNXI=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_ARCH_SUNXI=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_TARGET_M5208EVBE=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_SYS_TEXT_BASE=0xFFC00000
CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_I2C=y
CONFIG_TARGET_M5235EVB=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_M68K=y
CONFIG_TARGET_M5249EVB=y
CONFIG_SYS_TEXT_BASE=0xffe00000
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_AUTOBOOT is not set
CONFIG_LOOPW=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_M5253DEMO=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_TARGET_M5253EVBE=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
CONFIG_CMD_CACHE=y
CONFIG_TARGET_M5272C3=y
CONFIG_SYS_TEXT_BASE=0xffe00000
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_TARGET_M5275EVB=y
CONFIG_SYS_TEXT_BASE=0xffe00000
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_TARGET_M5282EVB=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_TARGET_M53017EVB=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=25000000"
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=50000000"
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_INPUT_CLKSRC=50000000"
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=25000000"
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
CONFIG_4xx=y
CONFIG_TARGET_MIP405T=y
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_4xx=y
CONFIG_TARGET_MIP405=y
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_5xx=y
CONFIG_TARGET_PATI=y
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="pati=> "
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_IMLS is not set
CONFIG_4xx=y
CONFIG_TARGET_PIP405=y
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_NAND=y
CONFIG_DFU_RAM=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
CONFIG_DM=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
CONFIG_DM=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DM_SERIAL=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DM_ETH=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am57xx-beagle-x15 am572x-idk"
CONFIG_DM=y
+# CONFIG_BLK is not set
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PALMAS=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+# CONFIG_BLK is not set
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_TARGET_AMCORE=y
CONFIG_SYS_TEXT_BASE=0xffc00000
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="amcore $ "
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_ARCH_ATH79=y
CONFIG_DEFAULT_DEVICE_TREE="ap121"
CONFIG_BOOTDELAY=3
+CONFIG_DISPLAY_CPUINFO=y
CONFIG_SYS_PROMPT="ap121 # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
CONFIG_TARGET_AP143=y
CONFIG_DEFAULT_DEVICE_TREE="ap143"
CONFIG_BOOTDELAY=3
+CONFIG_DISPLAY_CPUINFO=y
CONFIG_SYS_PROMPT="ap143 # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_E1000=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_TARGET_ASPENITE=y
CONFIG_IDENT_STRING="\nMarvell-Aspenite DB"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_M68K=y
CONFIG_TARGET_ASTRO_MCF5373L=y
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="URMEL > "
CONFIG_CMD_I2C=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91RM9200EK=y
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_AT91RM9200EK=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_TARGET_BCM28155_AP=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_MMC_ENV_DEV=0"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_BCM28155_AP=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
CONFIG_TARGET_BCM23550_W1D=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_FASTBOOT=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
CONFIG_TARGET_BCM28155_AP=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_FASTBOOT=y
CONFIG_TARGET_BCM28155_AP=y
CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_BCMCYGNUS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000,ARMV7_NONSEC"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_BCMCYGNUS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_BCMCYGNUS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_BCMCYGNUS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000,ARMV7_NONSEC"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_BCMCYGNUS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_BCMCYGNUS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_BCMNSP=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x01000000"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
CONFIG_BOOTDELAY=-2
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
CONFIG_BOOTDELAY=-2
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=-2
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
CONFIG_BOOTDELAY=-2
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_TARGET_CALIMAIN=y
CONFIG_BOOTDELAY=0
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Calimain > "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DM_KEYBOARD=y
CONFIG_DEFAULT_DEVICE_TREE="rk3288-jerry"
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_HUSH_PARSER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_VIDEO_IVYBRIDGE_IGD=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TPM=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_COBRA5272=y
CONFIG_SYS_TEXT_BASE=0xffe00000
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="COBRA > "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Colibri iMX7 # "
# CONFIG_CMD_BOOTD is not set
CONFIG_ARM=y
CONFIG_TARGET_COLIBRI_PXA270=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD,DEVELOP"
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_TARGET_CONTROLCENTERD=y
CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH,DEVELOP"
CONFIG_BOOTDELAY=-2
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_TARGET_CONTROLCENTERD=y
CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH"
CONFIG_BOOTDELAY=-2
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_COREBOOT=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TPM=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-corvus"
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_IDENT_STRING=" D2 v2"
CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="d2v2> "
# CONFIG_CMD_IMLS is not set
CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50"
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT"
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_DEFAULT_DEVICE_TREE="armada-375-db"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-385-amc"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SYS_EXTRA_OPTIONS="DEVCONCENTER"
CONFIG_BOOTDELAY=5
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set
CONFIG_CMD_ASKENV=y
CONFIG_TARGET_DNS325=y
CONFIG_IDENT_STRING="\nD-Link DNS-325"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_TARGET_DOCKSTAR=y
CONFIG_IDENT_STRING="\nSeagate FreeAgent DockStar"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="DockStar> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc"
CONFIG_DM=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_PCF8575_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_ETH=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PALMAS=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="dra7-evm dra72-evm"
CONFIG_DM=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_PCF8575_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_ARCH_SNAPDRAGON=y
CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C"
CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="dragonboard410c => "
# CONFIG_CMD_IMI is not set
CONFIG_TARGET_DREAMPLUG=y
CONFIG_IDENT_STRING="\nMarvell-DreamPlug"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
+CONFIG_TARGET_DS109=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_TARGET_EA20=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ea20 > "
# CONFIG_CMD_IMLS is not set
CONFIG_SYS_TEXT_BASE=0xFF000000
CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xFF000400"
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="\nEB+CPU5282> "
# CONFIG_CMD_LOADB is not set
CONFIG_CMD_I2C=y
CONFIG_SYS_TEXT_BASE=0xF0000000
CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xF0000418"
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_LOADB is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_EDB93XX=y
CONFIG_SYS_EXTRA_OPTIONS="MK_edb9315a"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="EDB9315A> "
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_EDMINIV2=y
CONFIG_IDENT_STRING=" EDMiniV2"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_IDENT_STRING=" for ESPRESSO7420"
CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420"
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="ESPRESSO7420 # "
# CONFIG_AUTOBOOT is not set
# CONFIG_CMD_IMLS is not set
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_TARGET_ETHERNUT5=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_TARGET_EVB_RK3036=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_EVB_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb"
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_HUSH_PARSER=y
CONFIG_ROCKCHIP_RK3288_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_ACT8846=y
-CONFIG_DM_REGULATOR=y
CONFIG_REGULATOR_ACT8846=y
CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb"
CONFIG_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_TARGET_FENNEC_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-fennec"
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_FIREFLY_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly"
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_FLEA3=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="flea3 U-Boot > "
CONFIG_CMD_SPI=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_TARGET_GOFLEXHOME=y
CONFIG_IDENT_STRING="\nSeagate GoFlex Home"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="GoFlexHome> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_TARGET_GPLUGD=y
CONFIG_IDENT_STRING="\nMarvell-gplugD"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_TARGET_GURUPLUG=y
CONFIG_IDENT_STRING="\nMarvell-GuruPlug"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_ARM=y
CONFIG_TARGET_H2200=y
CONFIG_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_ARCH_HIGHBANK=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds...\nPress <s> to stop or <d> to delay\n"
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_IDENT_STRING="hikey"
CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH"
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_TARGET_IB62X0=y
CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ib62x0 => "
CONFIG_CMD_BOOTZ=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_TARGET_ICONNECT=y
CONFIG_IDENT_STRING=" Iomega iConnect"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="iconnect => "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000"
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n"
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DEFAULT_DEVICE_TREE="nexys4ddr"
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="MIPSfpga # "
# CONFIG_CMD_IMLS is not set
CONFIG_IDENT_STRING=" IS v2"
CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
# CONFIG_CMD_IMLS is not set
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM720T=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-AP # "
CONFIG_CMD_ARMFLASH=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM920T=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-AP # "
CONFIG_CMD_ARMFLASH=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM926EJ_S=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-AP # "
CONFIG_CMD_ARMFLASH=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM946ES=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-AP # "
CONFIG_CMD_ARMFLASH=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM1136=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-CP # "
CONFIG_CMD_ARMFLASH=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM920T=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-CP # "
CONFIG_CMD_ARMFLASH=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM926EJ_S=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-CP # "
CONFIG_CMD_ARMFLASH=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM946ES=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-CP # "
CONFIG_CMD_ARMFLASH=y
CONFIG_SYS_EXTRA_OPTIONS="INTIB"
CONFIG_BOOTDELAY=5
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+# CONFIG_BLK is not set
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_IDENT_STRING="\nKeymile Kirkwood 128M16"
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_IDENT_STRING="\nKeymile Kirkwood"
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_IDENT_STRING="\nKeymile Kirkwood PCI"
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_IDENT_STRING="\nKeymile COGE5UN"
CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_IDENT_STRING="\nKeymile NUSA"
CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_IDENT_STRING="\nKeymile SUGP1"
CONFIG_SYS_EXTRA_OPTIONS="KM_SUGP1"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_IDENT_STRING="\nKeymile SUV31"
CONFIG_SYS_EXTRA_OPTIONS="KM_SUV31"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_TARGET_KYLIN_RK3036=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_LEGOEV3=y
CONFIG_BOOTDELAY=0
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds - press 'l' to stop...\n"
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_SF=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_SYS_FSL_DDR4=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
+CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_SYS_FSL_DDR4=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
+CONFIG_SYS_FSL_DDR3=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SYS_FSL_DDR3=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_DM_SERIAL=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_SYS_FSL_DDR3=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_SYS_FSL_DDR3=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_SYS_FSL_DDR4=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
+CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_SYS_FSL_DDR4=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
+CONFIG_SYS_FSL_DDR4=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_SYS_FSL_DDR4=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_SYS_FSL_DDR4=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_SYS_FSL_DDR4=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SYS_FSL_DDR4=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_SYS_FSL_DDR4=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
+CONFIG_SYS_FSL_DDR4=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_SYS_FSL_DDR4=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2080A"
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2080A"
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_TARGET_LS2080ARDB=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_DM=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_IDENT_STRING=" LS-CHLv2"
CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_IDENT_STRING=" LS-XHL"
CONFIG_SYS_EXTRA_OPTIONS="LSXHL"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4"
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_IDENT_STRING="\nKeymile COGE3UN"
CONFIG_SYS_EXTRA_OPTIONS="KM_MGCOGE3UN"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_TARGET_MINIARM_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-miniarm"
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_HUSH_PARSER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-db"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_DEFAULT_DEVICE_TREE="armada-7040-db"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_NAND"
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_SPI_FLASH"
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_ARM=y
CONFIG_TARGET_MX35PDK=y
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MMC=y
CONFIG_TARGET_MX53LOCO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6ULL_14X14_EVK=y
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
+# CONFIG_BLK is not set
+CONFIG_DM_GPIO=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
CONFIG_TARGET_NAS220=y
CONFIG_IDENT_STRING="\nNAS 220"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="nas220> "
# CONFIG_CMD_IMLS is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set
CONFIG_CMD_ASKENV=y
CONFIG_IDENT_STRING=" 2Big v2"
CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="2big2> "
# CONFIG_CMD_IMLS is not set
CONFIG_IDENT_STRING=" NS v2 Lite"
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
# CONFIG_CMD_IMLS is not set
CONFIG_IDENT_STRING=" NS Max v2"
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
# CONFIG_CMD_IMLS is not set
CONFIG_IDENT_STRING=" NS v2 Mini"
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
# CONFIG_CMD_IMLS is not set
CONFIG_IDENT_STRING=" NS v2"
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
# CONFIG_CMD_IMLS is not set
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NSA310S=y
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="nsa310s => "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PMIC=y
CONFIG_TARGET_ODROID_C2=y
CONFIG_IDENT_STRING=" odroid-c2"
CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_IDENT_STRING="\nOpenRD-Base"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_IDENT_STRING="\nOpenRD-Client"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_IDENT_STRING="\nOpenRD-Ultimate"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
CONFIG_TEGRA186_BPMP_I2C=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_E1000=y
CONFIG_RTL8169=y
CONFIG_PCI_TEGRA=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
CONFIG_TEGRA186_BPMP_I2C=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_E1000=y
CONFIG_RTL8169=y
CONFIG_PCI_TEGRA=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_USB_STORAGE=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
+# CONFIG_BLK is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_TARGET_PM9261=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="pm9261> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_TARGET_PM9G45=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_IMLS is not set
CONFIG_TARGET_POGO_E02=y
CONFIG_IDENT_STRING="\nPogo E02"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="PogoE02> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_TARGET_POPMETAL_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-popmetal"
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_HUSH_PARSER=y
CONFIG_IDENT_STRING="\nKeymile Port-L2"
CONFIG_SYS_EXTRA_OPTIONS="KM_PORTL2"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_DEFAULT_DEVICE_TREE="am335x-pxm50"
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_111=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_111=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_111=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_TARGET_ROCK2=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock2-square"
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_ARCH_BCM283X=y
CONFIG_TARGET_RPI_2=y
CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_RPI_3_32B=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_RPI_3=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_IMLS is not set
CONFIG_ARCH_BCM283X=y
CONFIG_TARGET_RPI=y
CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-rut"
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_DEBUG_DEVRES=y
CONFIG_ADC=y
CONFIG_ADC_SANDBOX=y
+# CONFIG_BLK is not set
CONFIG_CLK=y
CONFIG_CPU=y
CONFIG_DM_DEMO=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,33,PCIE"
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,33"
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,66,PCIE"
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,66"
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_TARGET_SHEEVAPLUG=y
CONFIG_IDENT_STRING="\nMarvell-Sheevaplug"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_ARM=y
CONFIG_TARGET_SMDK2410=y
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SMDK2410 # "
CONFIG_CMD_USB=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Snapper> "
# CONFIG_CMD_BDI is not set
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
CONFIG_FIT=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
CONFIG_FIT=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
CONFIG_FIT=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
CONFIG_FIT=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
CONFIG_FIT=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
CONFIG_FIT=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_FIT=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
CONFIG_FIT=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=5
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR300"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR300,NAND"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR300,USBTTY"
CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR300,USBTTY,NAND"
CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR310"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,NAND"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,FLASH_PNOR"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,USBTTY"
CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,USBTTY,NAND"
CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,USBTTY,FLASH_PNOR"
CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR320"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,NAND"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,FLASH_PNOR"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,USBTTY"
CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,USBTTY,NAND"
CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,USBTTY,FLASH_PNOR"
CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR600"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR600,NAND"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR600,USBTTY"
CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR600,USBTTY,NAND"
CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F429_DISCOVERY=y
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
# CONFIG_CMD_SETEXPR is not set
CONFIG_STM32F7=y
CONFIG_TARGET_STM32F746_DISCO=y
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON"
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON_DP"
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU"
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU,STRIDER_CPU_DP"
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_DEFAULT_DEVICE_TREE="stv0991"
CONFIG_SYS_EXTRA_OPTIONS="STV0991"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="STV0991> "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_IDENT_STRING=" for Cavium Thunder CN88XX ARM v8 Multi-Core"
CONFIG_DEFAULT_DEVICE_TREE="thunderx-88xx"
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ThunderX_88XX> "
# CONFIG_CMD_IMLS is not set
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot/ti816x# "
CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300"
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_TARGET_USB_A9263=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_IDENT_STRING=" vexpress_aemv8a"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="VExpress64# "
# CONFIG_CMD_CONSOLE is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_IDENT_STRING=" vexpress_aemv8a"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="VExpress64# "
# CONFIG_CMD_CONSOLE is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_IDENT_STRING=" vexpress_aemv8a"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="VExpress64# "
# CONFIG_CMD_CONSOLE is not set
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS_CA15_TC2=y
CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS_CA5X2=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS_CA9X4=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
CONFIG_TARGET_VINCO=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="vinco => "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_ARM=y
CONFIG_TARGET_WOODBURN=y
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="woodburn U-Boot > "
CONFIG_CMD_MMC=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="woodburn U-Boot > "
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000"
CONFIG_BOOTDELAY=5
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="xlx-ppc405:/# "
# CONFIG_CMD_IMLS is not set
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1"
CONFIG_BOOTDELAY=5
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="board:/# "
CONFIG_CMD_ASKENV=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_HUSH_PARSER=y
CONFIG_ARM=y
CONFIG_TARGET_ZIPITZ2=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
CONFIG_TARGET_ZMX25=y
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="zmx25> "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_ARCH_ZYNQ=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
- Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
- Keep VESA framebuffer
+And include coreboot_fb.dtsi in your board's device tree source file, like:
+
+ /include/ "coreboot_fb.dtsi"
+
At present it seems that for Minnowboard Max, coreboot does not pass through
the video information correctly (it always says the resolution is 0x0). This
works correctly for link though.
+Note: coreboot framebuffer driver does not work on QEMU. The reason is unknown
+at this point. Patches are welcome if you figure out anything wrong.
+
Test with QEMU for bare mode
----------------------------
QEMU is a fancy emulator that can enable us to test U-Boot without access to
Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then,
'zboot' can be used to boot the kernel:
-=> zboot 02000000 - 04000000 1b1ab50
+=> zboot 01000000 - 04000000 1b1ab50
CPU Microcode
-------------
if (clean_up) {
BE_exit();
if (vga_info->BIOSImage &&
- (u32)(vga_info->BIOSImage) != 0xc0000)
+ (ulong)(vga_info->BIOSImage) != 0xc0000)
free(vga_info->BIOSImage);
free(vga_info);
vga_info = NULL;
config BLK
bool "Support block devices"
depends on DM
+ default y if DM_MMC
help
Enable support for block devices, such as SCSI, MMC and USB
flash sticks. These provide a block-level interface which permits
return 0;
}
+const char *uclass_get_name(enum uclass_id id)
+{
+ struct uclass *uc;
+
+ if (uclass_get(id, &uc))
+ return NULL;
+ return uc->uc_drv->name;
+}
+
int uclass_find_device(enum uclass_id id, int index, struct udevice **devp)
{
struct uclass *uc;
#include <fdtdec.h>
#include <pch.h>
#include <pci.h>
+#include <syscon.h>
#include <asm/cpu.h>
#include <asm/gpio.h>
#include <asm/io.h>
struct broadwell_bank_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct broadwell_bank_priv *priv = dev_get_priv(dev);
+ struct udevice *pinctrl;
+ int ret;
+
+ /* Set up pin control if available */
+ ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
+ debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
uc_priv->gpio_count = GPIO_PER_BANK;
uc_priv->bank_name = plat->bank_name;
static int intel_i2c_probe(struct udevice *dev)
{
struct intel_i2c *priv = dev_get_priv(dev);
- u32 base;
+ ulong base;
/* Save base address from PCI BAR */
- priv->base = (u32)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4,
- PCI_REGION_IO);
+ priv->base = (ulong)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4,
+ PCI_REGION_IO);
base = priv->base;
/* Set SMBus enable. */
DECLARE_GLOBAL_DATA_PTR;
-/* Note: depends on enum ec_current_image */
-static const char * const ec_current_image_name[] = {"unknown", "RO", "RW"};
-
void cros_ec_dump_data(const char *name, int cmd, const uint8_t *data, int len)
{
#ifdef DEBUG
static int cros_ec_flash_write_block(struct cros_ec_dev *dev,
const uint8_t *data, uint32_t offset, uint32_t size)
{
- struct ec_params_flash_write p;
+ struct ec_params_flash_write *p;
+ int ret;
- p.offset = offset;
- p.size = size;
- assert(data && p.size <= EC_FLASH_WRITE_VER0_SIZE);
- memcpy(&p + 1, data, p.size);
+ p = malloc(sizeof(*p) + size);
+ if (!p)
+ return -ENOMEM;
+
+ p->offset = offset;
+ p->size = size;
+ assert(data && p->size <= EC_FLASH_WRITE_VER0_SIZE);
+ memcpy(p + 1, data, p->size);
+
+ ret = ec_command_inptr(dev, EC_CMD_FLASH_WRITE, 0,
+ p, sizeof(*p) + size, NULL, 0) >= 0 ? 0 : -1;
- return ec_command_inptr(dev, EC_CMD_FLASH_WRITE, 0,
- &p, sizeof(p), NULL, 0) >= 0 ? 0 : -1;
+ free(p);
+
+ return ret;
}
/**
return 1;
}
+/**
+ * Read back flash parameters
+ *
+ * This function reads back parameters of the flash as reported by the EC
+ *
+ * @param dev Pointer to device
+ * @param info Pointer to output flash info struct
+ */
+int cros_ec_read_flashinfo(struct cros_ec_dev *dev,
+ struct ec_response_flash_info *info)
+{
+ int ret;
+
+ ret = ec_command(dev, EC_CMD_FLASH_INFO, 0,
+ NULL, 0, info, sizeof(*info));
+ if (ret < 0)
+ return ret;
+
+ return ret < sizeof(*info) ? -1 : 0;
+}
+
int cros_ec_flash_write(struct cros_ec_dev *dev, const uint8_t *data,
uint32_t offset, uint32_t size)
{
return 0;
}
-#ifdef CONFIG_CMD_CROS_EC
-
-/**
- * Perform a flash read or write command
- *
- * @param dev CROS-EC device to read/write
- * @param is_write 1 do to a write, 0 to do a read
- * @param argc Number of arguments
- * @param argv Arguments (2 is region, 3 is address)
- * @return 0 for ok, 1 for a usage error or -ve for ec command error
- * (negative EC_RES_...)
- */
-static int do_read_write(struct cros_ec_dev *dev, int is_write, int argc,
- char * const argv[])
-{
- uint32_t offset, size = -1U, region_size;
- unsigned long addr;
- char *endp;
- int region;
- int ret;
-
- region = cros_ec_decode_region(argc - 2, argv + 2);
- if (region == -1)
- return 1;
- if (argc < 4)
- return 1;
- addr = simple_strtoul(argv[3], &endp, 16);
- if (*argv[3] == 0 || *endp != 0)
- return 1;
- if (argc > 4) {
- size = simple_strtoul(argv[4], &endp, 16);
- if (*argv[4] == 0 || *endp != 0)
- return 1;
- }
-
- ret = cros_ec_flash_offset(dev, region, &offset, ®ion_size);
- if (ret) {
- debug("%s: Could not read region info\n", __func__);
- return ret;
- }
- if (size == -1U)
- size = region_size;
-
- ret = is_write ?
- cros_ec_flash_write(dev, (uint8_t *)addr, offset, size) :
- cros_ec_flash_read(dev, (uint8_t *)addr, offset, size);
- if (ret) {
- debug("%s: Could not %s region\n", __func__,
- is_write ? "write" : "read");
- return ret;
- }
-
- return 0;
-}
-
-static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- struct cros_ec_dev *dev;
- struct udevice *udev;
- const char *cmd;
- int ret = 0;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- cmd = argv[1];
- if (0 == strcmp("init", cmd)) {
- /* Remove any existing device */
- ret = uclass_find_device(UCLASS_CROS_EC, 0, &udev);
- if (!ret)
- device_remove(udev);
- ret = uclass_get_device(UCLASS_CROS_EC, 0, &udev);
- if (ret) {
- printf("Could not init cros_ec device (err %d)\n", ret);
- return 1;
- }
- return 0;
- }
-
- ret = uclass_get_device(UCLASS_CROS_EC, 0, &udev);
- if (ret) {
- printf("Cannot get cros-ec device (err=%d)\n", ret);
- return 1;
- }
- dev = dev_get_uclass_priv(udev);
- if (0 == strcmp("id", cmd)) {
- char id[MSG_BYTES];
-
- if (cros_ec_read_id(dev, id, sizeof(id))) {
- debug("%s: Could not read KBC ID\n", __func__);
- return 1;
- }
- printf("%s\n", id);
- } else if (0 == strcmp("info", cmd)) {
- struct ec_response_mkbp_info info;
-
- if (cros_ec_info(dev, &info)) {
- debug("%s: Could not read KBC info\n", __func__);
- return 1;
- }
- printf("rows = %u\n", info.rows);
- printf("cols = %u\n", info.cols);
- printf("switches = %#x\n", info.switches);
- } else if (0 == strcmp("curimage", cmd)) {
- enum ec_current_image image;
-
- if (cros_ec_read_current_image(dev, &image)) {
- debug("%s: Could not read KBC image\n", __func__);
- return 1;
- }
- printf("%d\n", image);
- } else if (0 == strcmp("hash", cmd)) {
- struct ec_response_vboot_hash hash;
- int i;
-
- if (cros_ec_read_hash(dev, &hash)) {
- debug("%s: Could not read KBC hash\n", __func__);
- return 1;
- }
-
- if (hash.hash_type == EC_VBOOT_HASH_TYPE_SHA256)
- printf("type: SHA-256\n");
- else
- printf("type: %d\n", hash.hash_type);
-
- printf("offset: 0x%08x\n", hash.offset);
- printf("size: 0x%08x\n", hash.size);
-
- printf("digest: ");
- for (i = 0; i < hash.digest_size; i++)
- printf("%02x", hash.hash_digest[i]);
- printf("\n");
- } else if (0 == strcmp("reboot", cmd)) {
- int region;
- enum ec_reboot_cmd cmd;
-
- if (argc >= 3 && !strcmp(argv[2], "cold"))
- cmd = EC_REBOOT_COLD;
- else {
- region = cros_ec_decode_region(argc - 2, argv + 2);
- if (region == EC_FLASH_REGION_RO)
- cmd = EC_REBOOT_JUMP_RO;
- else if (region == EC_FLASH_REGION_RW)
- cmd = EC_REBOOT_JUMP_RW;
- else
- return CMD_RET_USAGE;
- }
-
- if (cros_ec_reboot(dev, cmd, 0)) {
- debug("%s: Could not reboot KBC\n", __func__);
- return 1;
- }
- } else if (0 == strcmp("events", cmd)) {
- uint32_t events;
-
- if (cros_ec_get_host_events(dev, &events)) {
- debug("%s: Could not read host events\n", __func__);
- return 1;
- }
- printf("0x%08x\n", events);
- } else if (0 == strcmp("clrevents", cmd)) {
- uint32_t events = 0x7fffffff;
-
- if (argc >= 3)
- events = simple_strtol(argv[2], NULL, 0);
-
- if (cros_ec_clear_host_events(dev, events)) {
- debug("%s: Could not clear host events\n", __func__);
- return 1;
- }
- } else if (0 == strcmp("read", cmd)) {
- ret = do_read_write(dev, 0, argc, argv);
- if (ret > 0)
- return CMD_RET_USAGE;
- } else if (0 == strcmp("write", cmd)) {
- ret = do_read_write(dev, 1, argc, argv);
- if (ret > 0)
- return CMD_RET_USAGE;
- } else if (0 == strcmp("erase", cmd)) {
- int region = cros_ec_decode_region(argc - 2, argv + 2);
- uint32_t offset, size;
-
- if (region == -1)
- return CMD_RET_USAGE;
- if (cros_ec_flash_offset(dev, region, &offset, &size)) {
- debug("%s: Could not read region info\n", __func__);
- ret = -1;
- } else {
- ret = cros_ec_flash_erase(dev, offset, size);
- if (ret) {
- debug("%s: Could not erase region\n",
- __func__);
- }
- }
- } else if (0 == strcmp("regioninfo", cmd)) {
- int region = cros_ec_decode_region(argc - 2, argv + 2);
- uint32_t offset, size;
-
- if (region == -1)
- return CMD_RET_USAGE;
- ret = cros_ec_flash_offset(dev, region, &offset, &size);
- if (ret) {
- debug("%s: Could not read region info\n", __func__);
- } else {
- printf("Region: %s\n", region == EC_FLASH_REGION_RO ?
- "RO" : "RW");
- printf("Offset: %x\n", offset);
- printf("Size: %x\n", size);
- }
- } else if (0 == strcmp("vbnvcontext", cmd)) {
- uint8_t block[EC_VBNV_BLOCK_SIZE];
- char buf[3];
- int i, len;
- unsigned long result;
-
- if (argc <= 2) {
- ret = cros_ec_read_vbnvcontext(dev, block);
- if (!ret) {
- printf("vbnv_block: ");
- for (i = 0; i < EC_VBNV_BLOCK_SIZE; i++)
- printf("%02x", block[i]);
- putc('\n');
- }
- } else {
- /*
- * TODO(clchiou): Move this to a utility function as
- * cmd_spi might want to call it.
- */
- memset(block, 0, EC_VBNV_BLOCK_SIZE);
- len = strlen(argv[2]);
- buf[2] = '\0';
- for (i = 0; i < EC_VBNV_BLOCK_SIZE; i++) {
- if (i * 2 >= len)
- break;
- buf[0] = argv[2][i * 2];
- if (i * 2 + 1 >= len)
- buf[1] = '0';
- else
- buf[1] = argv[2][i * 2 + 1];
- strict_strtoul(buf, 16, &result);
- block[i] = result;
- }
- ret = cros_ec_write_vbnvcontext(dev, block);
- }
- if (ret) {
- debug("%s: Could not %s VbNvContext\n", __func__,
- argc <= 2 ? "read" : "write");
- }
- } else if (0 == strcmp("test", cmd)) {
- int result = cros_ec_test(dev);
-
- if (result)
- printf("Test failed with error %d\n", result);
- else
- puts("Test passed\n");
- } else if (0 == strcmp("version", cmd)) {
- struct ec_response_get_version *p;
- char *build_string;
-
- ret = cros_ec_read_version(dev, &p);
- if (!ret) {
- /* Print versions */
- printf("RO version: %1.*s\n",
- (int)sizeof(p->version_string_ro),
- p->version_string_ro);
- printf("RW version: %1.*s\n",
- (int)sizeof(p->version_string_rw),
- p->version_string_rw);
- printf("Firmware copy: %s\n",
- (p->current_image <
- ARRAY_SIZE(ec_current_image_name) ?
- ec_current_image_name[p->current_image] :
- "?"));
- ret = cros_ec_read_build_info(dev, &build_string);
- if (!ret)
- printf("Build info: %s\n", build_string);
- }
- } else if (0 == strcmp("ldo", cmd)) {
- uint8_t index, state;
- char *endp;
-
- if (argc < 3)
- return CMD_RET_USAGE;
- index = simple_strtoul(argv[2], &endp, 10);
- if (*argv[2] == 0 || *endp != 0)
- return CMD_RET_USAGE;
- if (argc > 3) {
- state = simple_strtoul(argv[3], &endp, 10);
- if (*argv[3] == 0 || *endp != 0)
- return CMD_RET_USAGE;
- ret = cros_ec_set_ldo(udev, index, state);
- } else {
- ret = cros_ec_get_ldo(udev, index, &state);
- if (!ret) {
- printf("LDO%d: %s\n", index,
- state == EC_LDO_STATE_ON ?
- "on" : "off");
- }
- }
-
- if (ret) {
- debug("%s: Could not access LDO%d\n", __func__, index);
- return ret;
- }
- } else {
- return CMD_RET_USAGE;
- }
-
- if (ret < 0) {
- printf("Error: CROS-EC command failed (error %d)\n", ret);
- ret = 1;
- }
-
- return ret;
-}
-
-U_BOOT_CMD(
- crosec, 6, 1, do_cros_ec,
- "CROS-EC utility command",
- "init Re-init CROS-EC (done on startup automatically)\n"
- "crosec id Read CROS-EC ID\n"
- "crosec info Read CROS-EC info\n"
- "crosec curimage Read CROS-EC current image\n"
- "crosec hash Read CROS-EC hash\n"
- "crosec reboot [rw | ro | cold] Reboot CROS-EC\n"
- "crosec events Read CROS-EC host events\n"
- "crosec clrevents [mask] Clear CROS-EC host events\n"
- "crosec regioninfo <ro|rw> Read image info\n"
- "crosec erase <ro|rw> Erase EC image\n"
- "crosec read <ro|rw> <addr> [<size>] Read EC image\n"
- "crosec write <ro|rw> <addr> [<size>] Write EC image\n"
- "crosec vbnvcontext [hexstring] Read [write] VbNvContext from EC\n"
- "crosec ldo <idx> [<state>] Switch/Read LDO state\n"
- "crosec test run tests on cros_ec\n"
- "crosec version Read CROS-EC version"
-);
-#endif
-
UCLASS_DRIVER(cros_ec) = {
.id = UCLASS_CROS_EC,
.name = "cros_ec",
#include <common.h>
#include <fsl_sec_mon.h>
-int change_sec_mon_state(u32 initial_state, u32 final_state)
+static u32 get_sec_mon_state(void)
{
struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
(CONFIG_SYS_SEC_MON_ADDR);
- u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat);
+ return sec_mon_in32(&sec_mon_regs->hp_stat) & HPSR_SSM_ST_MASK;
+}
+
+static int set_sec_mon_state_non_sec(void)
+{
+ u32 sts;
int timeout = 10;
+ struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
+ (CONFIG_SYS_SEC_MON_ADDR);
- if ((sts & HPSR_SSM_ST_MASK) != initial_state)
- return -1;
+ sts = get_sec_mon_state();
- if (initial_state == HPSR_SSM_ST_TRUST) {
- switch (final_state) {
- case HPSR_SSM_ST_NON_SECURE:
- printf("SEC_MON state transitioning to Soft Fail.\n");
- sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV);
-
- /*
- * poll till SEC_MON is in
- * Soft Fail state
- */
- while (((sts & HPSR_SSM_ST_MASK) !=
- HPSR_SSM_ST_SOFT_FAIL)) {
- while (timeout) {
- sts = sec_mon_in32
- (&sec_mon_regs->hp_stat);
-
- if ((sts & HPSR_SSM_ST_MASK) ==
- HPSR_SSM_ST_SOFT_FAIL)
- break;
-
- udelay(10);
- timeout--;
- }
- }
+ switch (sts) {
+ /*
+ * If initial state is check or Non-Secure, then set the Software
+ * Security Violation Bit and transition to Non-Secure State.
+ */
+ case HPSR_SSM_ST_CHECK:
+ printf("SEC_MON state transitioning to Non Secure.\n");
+ sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV);
- if (timeout == 0) {
- printf("SEC_MON state transition timeout.\n");
- return -1;
- }
+ /* polling loop till SEC_MON is in Non Secure state */
+ while (timeout) {
+ sts = get_sec_mon_state();
+
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_NON_SECURE)
+ break;
+
+ udelay(10);
+ timeout--;
+ }
- timeout = 10;
+ if (timeout == 0) {
+ printf("SEC_MON state transition timeout.\n");
+ return -1;
+ }
+ break;
+
+ /*
+ * If initial state is Trusted, Secure or Soft-Fail, then first set
+ * the Software Security Violation Bit and transition to Soft-Fail
+ * State.
+ */
+ case HPSR_SSM_ST_TRUST:
+ case HPSR_SSM_ST_SECURE:
+ case HPSR_SSM_ST_SOFT_FAIL:
+ printf("SEC_MON state transitioning to Soft Fail.\n");
+ sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV);
+
+ /* polling loop till SEC_MON is in Soft-Fail state */
+ while (timeout) {
+ sts = get_sec_mon_state();
+
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_SOFT_FAIL)
+ break;
+
+ udelay(10);
+ timeout--;
+ }
+
+ if (timeout == 0) {
+ printf("SEC_MON state transition timeout.\n");
+ return -1;
+ }
+
+ timeout = 10;
+ /*
+ * If SSM Soft Fail to Non-Secure State Transition
+ * disable is not set, then set SSM_ST bit and
+ * transition to Non-Secure State.
+ */
+ if ((sec_mon_in32(&sec_mon_regs->hp_com) &
+ HPCOMR_SSM_SFNS_DIS) == 0) {
printf("SEC_MON state transitioning to Non Secure.\n");
sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SSM_ST);
- /*
- * poll till SEC_MON is in
- * Non Secure state
- */
- while (((sts & HPSR_SSM_ST_MASK) !=
- HPSR_SSM_ST_NON_SECURE)) {
- while (timeout) {
- sts = sec_mon_in32
- (&sec_mon_regs->hp_stat);
-
- if ((sts & HPSR_SSM_ST_MASK) ==
- HPSR_SSM_ST_NON_SECURE)
- break;
-
- udelay(10);
- timeout--;
- }
- }
+ /* polling loop till SEC_MON is in Non Secure*/
+ while (timeout) {
+ sts = get_sec_mon_state();
- if (timeout == 0) {
- printf("SEC_MON state transition timeout.\n");
- return -1;
- }
- break;
- case HPSR_SSM_ST_SOFT_FAIL:
- printf("SEC_MON state transitioning to Soft Fail.\n");
- sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV);
-
- /*
- * polling loop till SEC_MON is in
- * Soft Fail state
- */
- while (((sts & HPSR_SSM_ST_MASK) !=
- HPSR_SSM_ST_SOFT_FAIL)) {
- while (timeout) {
- sts = sec_mon_in32
- (&sec_mon_regs->hp_stat);
-
- if ((sts & HPSR_SSM_ST_MASK) ==
- HPSR_SSM_ST_SOFT_FAIL)
- break;
-
- udelay(10);
- timeout--;
- }
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_NON_SECURE)
+ break;
+
+ udelay(10);
+ timeout--;
}
if (timeout == 0) {
printf("SEC_MON state transition timeout.\n");
return -1;
}
- break;
- default:
- return -1;
}
- } else if (initial_state == HPSR_SSM_ST_NON_SECURE) {
- switch (final_state) {
- case HPSR_SSM_ST_SOFT_FAIL:
- printf("SEC_MON state transitioning to Soft Fail.\n");
- sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV);
-
- /*
- * polling loop till SEC_MON is in
- * Soft Fail state
- */
- while (((sts & HPSR_SSM_ST_MASK) !=
- HPSR_SSM_ST_SOFT_FAIL)) {
- while (timeout) {
- sts = sec_mon_in32
- (&sec_mon_regs->hp_stat);
-
- if ((sts & HPSR_SSM_ST_MASK) ==
- HPSR_SSM_ST_SOFT_FAIL)
- break;
-
- udelay(10);
- timeout--;
- }
- }
+ break;
+ default:
+ printf("SEC_MON already in Non Secure state.\n");
+ return 0;
+ }
+ return 0;
+}
- if (timeout == 0) {
- printf("SEC_MON state transition timeout.\n");
- return -1;
- }
+static int set_sec_mon_state_soft_fail(void)
+{
+ u32 sts;
+ int timeout = 10;
+ struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
+ (CONFIG_SYS_SEC_MON_ADDR);
+
+ printf("SEC_MON state transitioning to Soft Fail.\n");
+ sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV);
+
+ /* polling loop till SEC_MON is in Soft-Fail state */
+ while (timeout) {
+ sts = get_sec_mon_state();
+
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_SOFT_FAIL)
break;
- default:
- return -1;
- }
+
+ udelay(10);
+ timeout--;
}
+ if (timeout == 0) {
+ printf("SEC_MON state transition timeout.\n");
+ return -1;
+ }
return 0;
}
+
+int set_sec_mon_state(u32 state)
+{
+ int ret = -1;
+
+ switch (state) {
+ case HPSR_SSM_ST_NON_SECURE:
+ ret = set_sec_mon_state_non_sec();
+ break;
+ case HPSR_SSM_ST_SOFT_FAIL:
+ ret = set_sec_mon_state_soft_fail();
+ break;
+ default:
+ printf("SEC_MON state transition not supported.\n");
+ return 0;
+ }
+
+ return ret;
+}
config DM_MMC_OPS
bool "Support MMC controller operations using Driver Model"
depends on DM_MMC
+ default y if DM_MMC
help
Driver model provides a means of supporting device operations. This
option moves MMC operations under the control of driver model. The
.read = mmc_bread,
#ifndef CONFIG_SPL_BUILD
.write = mmc_bwrite,
+ .erase = mmc_berase,
#endif
.select_hwpart = mmc_select_hwpart,
};
#endif
#if !(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_SAVEENV))
-unsigned long mmc_berase(struct blk_desc *block_dev, lbaint_t start,
- lbaint_t blkcnt);
#ifdef CONFIG_BLK
ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
const void *src);
+ulong mmc_berase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt);
#else
ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
const void *src);
+ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt);
#endif
#else /* CONFIG_SPL_BUILD and CONFIG_SPL_SAVEENV is not defined */
return err;
}
-unsigned long mmc_berase(struct blk_desc *block_dev, lbaint_t start,
- lbaint_t blkcnt)
+#ifdef CONFIG_BLK
+ulong mmc_berase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt)
+#else
+ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt)
+#endif
{
+#ifdef CONFIG_BLK
+ struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
int dev_num = block_dev->devnum;
int err = 0;
u32 start_rem, blkcnt_rem;
#include <pci.h>
#include <pci_rom.h>
#include <vbe.h>
+#include <video.h>
#include <video_fb.h>
#include <linux/screen_info.h>
free(ram);
return ret;
}
+
+#ifdef CONFIG_DM_VIDEO
+int vbe_setup_video_priv(struct vesa_mode_info *vesa,
+ struct video_priv *uc_priv,
+ struct video_uc_platdata *plat)
+{
+ if (!vesa->x_resolution)
+ return -ENXIO;
+ uc_priv->xsize = vesa->x_resolution;
+ uc_priv->ysize = vesa->y_resolution;
+ switch (vesa->bits_per_pixel) {
+ case 32:
+ case 24:
+ uc_priv->bpix = VIDEO_BPP32;
+ break;
+ case 16:
+ uc_priv->bpix = VIDEO_BPP16;
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+ plat->base = vesa->phys_base_ptr;
+ plat->size = vesa->bytes_per_scanline * vesa->y_resolution;
+
+ return 0;
+}
+
+int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void))
+{
+ struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+ int ret;
+
+ printf("Video: ");
+
+ /* If we are running from EFI or coreboot, this can't work */
+ if (!ll_boot_init()) {
+ printf("Not available (previous bootloader prevents it)\n");
+ return -EPERM;
+ }
+ bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
+ ret = dm_pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
+ PCI_ROM_ALLOW_FALLBACK);
+ bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
+ if (ret) {
+ debug("failed to run video BIOS: %d\n", ret);
+ return ret;
+ }
+
+ ret = vbe_setup_video_priv(&mode_info.vesa, uc_priv, plat);
+ if (ret) {
+ debug("No video mode configured\n");
+ return ret;
+ }
+
+ printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
+ mode_info.vesa.bits_per_pixel);
+
+ return 0;
+}
+#endif
FETs and a battery charger. This driver provides register access
only, and you can enable the regulator/charger drivers separately if
required.
+
+config PMIC_PALMAS
+ bool "Enable driver for Texas Instruments PALMAS PMIC"
+ depends on DM_PMIC
+ ---help---
+ The PALMAS is a PMIC containing several LDOs, SMPS.
+ This driver binds the pmic children.
+
+config PMIC_LP873X
+ bool "Enable driver for Texas Instruments LP873X PMIC"
+ depends on DM_PMIC
+ ---help---
+ The LP873X is a PMIC containing couple of LDOs and couple of SMPS.
+ This driver binds the pmic children.
obj-$(CONFIG_PMIC_RN5T567) += rn5t567.o
obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
+obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o
+obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o
obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o
--- /dev/null
+/*
+ * (C) Copyright 2016 Texas Instruments Incorporated, <www.ti.com>
+ * Keerthy <j-keerthy@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/lp873x.h>
+#include <dm/device.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pmic_child_info pmic_children_info[] = {
+ { .prefix = "ldo", .driver = LP873X_LDO_DRIVER },
+ { .prefix = "buck", .driver = LP873X_BUCK_DRIVER },
+ { },
+};
+
+static int lp873x_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+ if (dm_i2c_write(dev, reg, buff, len)) {
+ error("write error to device: %p register: %#x!", dev, reg);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int lp873x_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ if (dm_i2c_read(dev, reg, buff, len)) {
+ error("read error from device: %p register: %#x!", dev, reg);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int lp873x_bind(struct udevice *dev)
+{
+ int regulators_node;
+ const void *blob = gd->fdt_blob;
+ int children;
+ int node = dev->of_offset;
+
+ regulators_node = fdt_subnode_offset(blob, node, "regulators");
+
+ if (regulators_node <= 0) {
+ printf("%s: %s reg subnode not found!", __func__, dev->name);
+ return -ENXIO;
+ }
+
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ printf("%s: %s - no child found\n", __func__, dev->name);
+
+ /* Always return success for this device */
+ return 0;
+}
+
+static struct dm_pmic_ops lp873x_ops = {
+ .read = lp873x_read,
+ .write = lp873x_write,
+};
+
+static const struct udevice_id lp873x_ids[] = {
+ { .compatible = "ti,lp8732", .data = LP8732 },
+ { .compatible = "ti,lp8733" , .data = LP8733 },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_lp873x) = {
+ .name = "lp873x_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = lp873x_ids,
+ .bind = lp873x_bind,
+ .ops = &lp873x_ops,
+};
--- /dev/null
+/*
+ * (C) Copyright 2016 Texas Instruments Incorporated, <www.ti.com>
+ * Keerthy <j-keerthy@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/palmas.h>
+#include <dm/device.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pmic_child_info pmic_children_info[] = {
+ { .prefix = "ldo", .driver = PALMAS_LDO_DRIVER },
+ { .prefix = "smps", .driver = PALMAS_SMPS_DRIVER },
+ { },
+};
+
+static int palmas_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+ if (dm_i2c_write(dev, reg, buff, len)) {
+ error("write error to device: %p register: %#x!", dev, reg);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int palmas_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ if (dm_i2c_read(dev, reg, buff, len)) {
+ error("read error from device: %p register: %#x!", dev, reg);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int palmas_bind(struct udevice *dev)
+{
+ int pmic_node = -1, regulators_node;
+ const void *blob = gd->fdt_blob;
+ int children;
+ int node = dev->of_offset;
+ int subnode, len;
+
+ fdt_for_each_subnode(blob, subnode, node) {
+ const char *name;
+ char *temp;
+
+ name = fdt_get_name(blob, subnode, &len);
+ temp = strstr(name, "pmic");
+ if (temp) {
+ pmic_node = subnode;
+ break;
+ }
+ }
+
+ if (pmic_node <= 0) {
+ debug("%s: %s pmic subnode not found!", __func__, dev->name);
+ return -ENXIO;
+ }
+
+ regulators_node = fdt_subnode_offset(blob, pmic_node, "regulators");
+
+ if (regulators_node <= 0) {
+ debug("%s: %s reg subnode not found!", __func__, dev->name);
+ return -ENXIO;
+ }
+
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ debug("%s: %s - no child found\n", __func__, dev->name);
+
+ /* Always return success for this device */
+ return 0;
+}
+
+static struct dm_pmic_ops palmas_ops = {
+ .read = palmas_read,
+ .write = palmas_write,
+};
+
+static const struct udevice_id palmas_ids[] = {
+ { .compatible = "ti,tps659038", .data = TPS659038 },
+ { .compatible = "ti,tps65917" , .data = TPS65917 },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_palmas) = {
+ .name = "palmas_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = palmas_ids,
+ .bind = palmas_bind,
+ .ops = &palmas_ops,
+};
features for fixed value regulators. The driver implements get/set api
for enable and get only for voltage value.
+config DM_REGULATOR_GPIO
+ bool "Enable Driver Model for GPIO REGULATOR"
+ depends on DM_REGULATOR
+ ---help---
+ This config enables implementation of driver-model regulator uclass
+ features for gpio regulators. The driver implements get/set for
+ voltage value.
+
config REGULATOR_RK808
bool "Enable driver for RK808 regulators"
depends on DM_REGULATOR && PMIC_RK808
regulators, one for each FET. The standard regulator interface is
supported, but it is only possible to turn the regulators on or off.
There is no voltage/current control.
+
+config DM_REGULATOR_PALMAS
+ bool "Enable driver for PALMAS PMIC regulators"
+ depends on PMIC_PALMAS
+ ---help---
+ This enables implementation of driver-model regulator uclass
+ features for REGULATOR PALMAS and the family of PALMAS PMICs.
+ The driver implements get/set api for: value and enable.
+
+config DM_REGULATOR_LP873X
+ bool "Enable driver for LP873X PMIC regulators"
+ depends on PMIC_LP873X
+ ---help---
+ This enables implementation of driver-model regulator uclass
+ features for REGULATOR LP873X and the family of LP873X PMICs.
+ The driver implements get/set api for: value and enable.
obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o
obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o
obj-$(CONFIG_REGULATOR_RK808) += rk808.o
obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o
obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_PALMAS) += palmas_regulator.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o
/* Set type to fixed */
uc_pdata->type = REGULATOR_TYPE_FIXED;
- /* Get fixed regulator gpio desc */
+ /* Get fixed regulator optional enable GPIO desc */
gpio = &dev_pdata->gpio;
ret = gpio_request_by_name(dev, "gpio", 0, gpio, GPIOD_IS_OUT);
- if (ret)
- debug("Fixed regulator gpio - not found! Error: %d", ret);
+ if (ret) {
+ debug("Fixed regulator optional enable GPIO - not found! Error: %d\n",
+ ret);
+ if (ret != -ENOENT)
+ return ret;
+ }
/* Get optional ramp up delay */
dev_pdata->startup_delay_us = fdtdec_get_uint(gd->fdt_blob,
{
struct fixed_regulator_platdata *dev_pdata = dev_get_platdata(dev);
+ /* Enable GPIO is optional */
if (!dev_pdata->gpio.dev)
- return false;
+ return true;
return dm_gpio_get_value(&dev_pdata->gpio);
}
struct fixed_regulator_platdata *dev_pdata = dev_get_platdata(dev);
int ret;
- if (!dev_pdata->gpio.dev)
- return -ENOSYS;
+ /* Enable GPIO is optional */
+ if (!dev_pdata->gpio.dev) {
+ if (!enable)
+ return -ENOSYS;
+ return 0;
+ }
ret = dm_gpio_set_value(&dev_pdata->gpio, enable);
if (ret) {
--- /dev/null
+/*
+ * (C) Copyright 2016 Texas Instruments Incorporated, <www.ti.com>
+ * Keerthy <j-keerthy@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+
+#define GPIO_REGULATOR_MAX_STATES 2
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct gpio_regulator_platdata {
+ struct gpio_desc gpio; /* GPIO for regulator voltage control */
+ int states[GPIO_REGULATOR_MAX_STATES];
+ int voltages[GPIO_REGULATOR_MAX_STATES];
+};
+
+static int gpio_regulator_ofdata_to_platdata(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+ struct gpio_regulator_platdata *dev_pdata;
+ struct gpio_desc *gpio;
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
+ int ret, count, i, j;
+ u32 states_array[8];
+
+ dev_pdata = dev_get_platdata(dev);
+ uc_pdata = dev_get_uclass_platdata(dev);
+ if (!uc_pdata)
+ return -ENXIO;
+
+ /* Set type to gpio */
+ uc_pdata->type = REGULATOR_TYPE_GPIO;
+
+ /*
+ * Get gpio regulator gpio desc
+ * Assuming one GPIO per regulator.
+ * Can be extended later to multiple GPIOs
+ * per gpio-regulator. As of now no instance with multiple
+ * gpios is presnt
+ */
+ gpio = &dev_pdata->gpio;
+ ret = gpio_request_by_name(dev, "gpios", 0, gpio, GPIOD_IS_OUT);
+ if (ret)
+ debug("regulator gpio - not found! Error: %d", ret);
+
+ count = fdtdec_get_int_array_count(blob, node, "states",
+ states_array, 8);
+
+ if (!count)
+ return -EINVAL;
+
+ for (i = 0, j = 0; i < count; i += 2) {
+ dev_pdata->voltages[j] = states_array[i];
+ dev_pdata->states[j] = states_array[i + 1];
+ j++;
+ }
+
+ return 0;
+}
+
+static int gpio_regulator_get_value(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+ struct gpio_regulator_platdata *dev_pdata = dev_get_platdata(dev);
+ int enable;
+
+ if (!dev_pdata->gpio.dev)
+ return -ENOSYS;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ if (uc_pdata->min_uV > uc_pdata->max_uV) {
+ debug("Invalid constraints for: %s\n", uc_pdata->name);
+ return -EINVAL;
+ }
+
+ enable = dm_gpio_get_value(&dev_pdata->gpio);
+ if (enable == dev_pdata->states[0])
+ return dev_pdata->voltages[0];
+ else
+ return dev_pdata->voltages[1];
+}
+
+static int gpio_regulator_set_value(struct udevice *dev, int uV)
+{
+ struct gpio_regulator_platdata *dev_pdata = dev_get_platdata(dev);
+ int ret;
+ bool enable;
+
+ if (!dev_pdata->gpio.dev)
+ return -ENOSYS;
+
+ if (uV == dev_pdata->voltages[0])
+ enable = dev_pdata->states[0];
+ else if (uV == dev_pdata->voltages[1])
+ enable = dev_pdata->states[1];
+ else
+ return -EINVAL;
+
+ ret = dm_gpio_set_value(&dev_pdata->gpio, enable);
+ if (ret) {
+ error("Can't set regulator : %s gpio to: %d\n", dev->name,
+ enable);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct dm_regulator_ops gpio_regulator_ops = {
+ .get_value = gpio_regulator_get_value,
+ .set_value = gpio_regulator_set_value,
+};
+
+static const struct udevice_id gpio_regulator_ids[] = {
+ { .compatible = "regulator-gpio" },
+ { },
+};
+
+U_BOOT_DRIVER(gpio_regulator) = {
+ .name = "gpio regulator",
+ .id = UCLASS_REGULATOR,
+ .ops = &gpio_regulator_ops,
+ .of_match = gpio_regulator_ids,
+ .ofdata_to_platdata = gpio_regulator_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct gpio_regulator_platdata),
+};
--- /dev/null
+/*
+ * (C) Copyright 2016
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Keerthy <j-keerthy@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/lp873x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char lp873x_buck_ctrl[LP873X_BUCK_NUM] = {0x2, 0x4};
+static const char lp873x_buck_volt[LP873X_BUCK_NUM] = {0x6, 0x7};
+static const char lp873x_ldo_ctrl[LP873X_LDO_NUM] = {0x8, 0x9};
+static const char lp873x_ldo_volt[LP873X_LDO_NUM] = {0xA, 0xB};
+
+static int lp873x_buck_enable(struct udevice *dev, int op, bool *enable)
+{
+ int ret;
+ unsigned int adr;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ adr = uc_pdata->ctrl_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ ret &= LP873X_BUCK_MODE_MASK;
+
+ if (ret)
+ *enable = true;
+ else
+ *enable = false;
+
+ return 0;
+ } else if (op == PMIC_OP_SET) {
+ if (*enable)
+ ret |= LP873X_BUCK_MODE_MASK;
+ else
+ ret &= ~(LP873X_BUCK_MODE_MASK);
+ ret = pmic_reg_write(dev->parent, adr, ret);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int lp873x_buck_volt2hex(int uV)
+{
+ if (uV > LP873X_BUCK_VOLT_MAX)
+ return -EINVAL;
+ else if (uV > 1400000)
+ return (uV - 1420000) / 20000 + 0x9E;
+ else if (uV > 730000)
+ return (uV - 735000) / 5000 + 0x18;
+ else if (uV >= 700000)
+ return (uV - 700000) / 10000 + 0x1;
+ else
+ return -EINVAL;
+}
+
+static int lp873x_buck_hex2volt(int hex)
+{
+ if (hex > LP873X_BUCK_VOLT_MAX_HEX)
+ return -EINVAL;
+ else if (hex > 0x9D)
+ return 1400000 + (hex - 0x9D) * 20000;
+ else if (hex > 0x17)
+ return 730000 + (hex - 0x17) * 5000;
+ else if (hex >= 0x14)
+ return 700000 + (hex - 0x14) * 10000;
+ else
+ return -EINVAL;
+}
+
+static int lp873x_buck_val(struct udevice *dev, int op, int *uV)
+{
+ unsigned int hex, adr;
+ int ret;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ if (op == PMIC_OP_GET)
+ *uV = 0;
+
+ adr = uc_pdata->volt_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ ret &= LP873X_BUCK_VOLT_MASK;
+ ret = lp873x_buck_hex2volt(ret);
+ if (ret < 0)
+ return ret;
+ *uV = ret;
+
+ return 0;
+ }
+
+ hex = lp873x_buck_volt2hex(*uV);
+ if (hex < 0)
+ return hex;
+
+ ret &= 0x0;
+ ret |= hex;
+
+ ret = pmic_reg_write(dev->parent, adr, ret);
+
+ return ret;
+}
+
+static int lp873x_ldo_enable(struct udevice *dev, int op, bool *enable)
+{
+ int ret;
+ unsigned int adr;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ adr = uc_pdata->ctrl_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ ret &= LP873X_LDO_MODE_MASK;
+
+ if (ret)
+ *enable = true;
+ else
+ *enable = false;
+
+ return 0;
+ } else if (op == PMIC_OP_SET) {
+ if (*enable)
+ ret |= LP873X_LDO_MODE_MASK;
+ else
+ ret &= ~(LP873X_LDO_MODE_MASK);
+
+ ret = pmic_reg_write(dev->parent, adr, ret);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int lp873x_ldo_volt2hex(int uV)
+{
+ if (uV > LP873X_LDO_VOLT_MAX)
+ return -EINVAL;
+
+ return (uV - 800000) / 100000;
+}
+
+static int lp873x_ldo_hex2volt(int hex)
+{
+ if (hex > LP873X_LDO_VOLT_MAX_HEX)
+ return -EINVAL;
+
+ if (!hex)
+ return 0;
+
+ return (hex * 100000) + 800000;
+}
+
+static int lp873x_ldo_val(struct udevice *dev, int op, int *uV)
+{
+ unsigned int hex, adr;
+ int ret;
+
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ if (op == PMIC_OP_GET)
+ *uV = 0;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ adr = uc_pdata->volt_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ ret &= LP873X_LDO_VOLT_MASK;
+ ret = lp873x_ldo_hex2volt(ret);
+ if (ret < 0)
+ return ret;
+ *uV = ret;
+ return 0;
+ }
+
+ hex = lp873x_ldo_volt2hex(*uV);
+ if (hex < 0)
+ return hex;
+
+ ret &= ~LP873X_LDO_VOLT_MASK;
+ ret |= hex;
+ if (*uV > 1650000)
+ ret |= 0x80;
+ ret = pmic_reg_write(dev->parent, adr, ret);
+
+ return ret;
+}
+
+static int lp873x_ldo_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata->type = REGULATOR_TYPE_LDO;
+
+ int idx = dev->driver_data;
+ if (idx >= LP873X_LDO_NUM) {
+ printf("Wrong ID for regulator\n");
+ return -1;
+ }
+
+ uc_pdata->ctrl_reg = lp873x_ldo_ctrl[idx];
+ uc_pdata->volt_reg = lp873x_ldo_volt[idx];
+
+ return 0;
+}
+
+static int ldo_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = lp873x_ldo_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int ldo_set_value(struct udevice *dev, int uV)
+{
+ return lp873x_ldo_val(dev, PMIC_OP_SET, &uV);
+}
+
+static bool ldo_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+ ret = lp873x_ldo_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+
+ return enable;
+}
+
+static int ldo_set_enable(struct udevice *dev, bool enable)
+{
+ return lp873x_ldo_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static int lp873x_buck_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+ int idx;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata->type = REGULATOR_TYPE_BUCK;
+
+ idx = dev->driver_data;
+ if (idx >= LP873X_BUCK_NUM) {
+ printf("Wrong ID for regulator\n");
+ return -1;
+ }
+
+ uc_pdata->ctrl_reg = lp873x_buck_ctrl[idx];
+ uc_pdata->volt_reg = lp873x_buck_volt[idx];
+
+ return 0;
+}
+
+static int buck_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = lp873x_buck_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int buck_set_value(struct udevice *dev, int uV)
+{
+ return lp873x_buck_val(dev, PMIC_OP_SET, &uV);
+}
+
+static bool buck_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+
+ ret = lp873x_buck_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+
+ return enable;
+}
+
+static int buck_set_enable(struct udevice *dev, bool enable)
+{
+ return lp873x_buck_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static const struct dm_regulator_ops lp873x_ldo_ops = {
+ .get_value = ldo_get_value,
+ .set_value = ldo_set_value,
+ .get_enable = ldo_get_enable,
+ .set_enable = ldo_set_enable,
+};
+
+U_BOOT_DRIVER(lp873x_ldo) = {
+ .name = LP873X_LDO_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &lp873x_ldo_ops,
+ .probe = lp873x_ldo_probe,
+};
+
+static const struct dm_regulator_ops lp873x_buck_ops = {
+ .get_value = buck_get_value,
+ .set_value = buck_set_value,
+ .get_enable = buck_get_enable,
+ .set_enable = buck_set_enable,
+};
+
+U_BOOT_DRIVER(lp873x_buck) = {
+ .name = LP873X_BUCK_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &lp873x_buck_ops,
+ .probe = lp873x_buck_probe,
+};
--- /dev/null
+/*
+ * (C) Copyright 2016
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Keerthy <j-keerthy@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/palmas.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define REGULATOR_ON 0x1
+#define REGULATOR_OFF 0x0
+
+#define SMPS_MODE_MASK 0x3
+#define SMPS_MODE_SHIFT 0x0
+#define LDO_MODE_MASK 0x1
+#define LDO_MODE_SHIFT 0x0
+
+static const char palmas_smps_ctrl[][PALMAS_SMPS_NUM] = {
+ {0x20, 0x24, 0x28, 0x2c, 0x30, 0x34, 0x38, 0x3c},
+ {0x20, 0x24, 0x28, 0x2c, 0x30, 0x34, 0x38},
+ {0x20, 0x24, 0x2c, 0x30, 0x38},
+};
+
+static const char palmas_smps_volt[][PALMAS_SMPS_NUM] = {
+ {0x23, 0x27, 0x2b, 0x2f, 0x33, 0x37, 0x3b, 0x3c},
+ {0x23, 0x27, 0x2b, 0x2f, 0x33, 0x37, 0x3b},
+ {0x23, 0x27, 0x2f, 0x33, 0x3B}
+};
+
+static const char palmas_ldo_ctrl[][PALMAS_LDO_NUM] = {
+ {0x50, 0x52, 0x54, 0x56, 0x58, 0x5a, 0x5c, 0x5e, 0x60, 0x62, 0x64},
+ {0x50, 0x52, 0x54, 0x56, 0x58, 0x5a, 0x5c, 0x5e, 0x60, 0x62, 0x64},
+ {0x50, 0x52, 0x54, 0x5e, 0x62}
+};
+
+static const char palmas_ldo_volt[][PALMAS_LDO_NUM] = {
+ {0x51, 0x53, 0x55, 0x57, 0x59, 0x5b, 0x5d, 0x5f, 0x61, 0x63, 0x65},
+ {0x51, 0x53, 0x55, 0x57, 0x59, 0x5b, 0x5d, 0x5f, 0x61, 0x63, 0x65},
+ {0x51, 0x53, 0x55, 0x5f, 0x63}
+};
+
+static int palmas_smps_enable(struct udevice *dev, int op, bool *enable)
+{
+ int ret;
+ unsigned int adr;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ adr = uc_pdata->ctrl_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ ret &= PALMAS_SMPS_STATUS_MASK;
+
+ if (ret)
+ *enable = true;
+ else
+ *enable = false;
+
+ return 0;
+ } else if (op == PMIC_OP_SET) {
+ if (*enable)
+ ret |= PALMAS_SMPS_MODE_MASK;
+ else
+ ret &= ~(PALMAS_SMPS_MODE_MASK);
+
+ ret = pmic_reg_write(dev->parent, adr, ret);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int palmas_smps_volt2hex(int uV)
+{
+ if (uV > PALMAS_LDO_VOLT_MAX)
+ return -EINVAL;
+
+ if (uV > 1650000)
+ return (uV - 1000000) / 20000 + 0x6;
+
+ if (uV == 500000)
+ return 0x6;
+ else
+ return 0x6 + ((uV - 500000) / 10000);
+}
+
+static int palmas_smps_hex2volt(int hex, bool range)
+{
+ unsigned int uV = 0;
+
+ if (hex > PALMAS_SMPS_VOLT_MAX_HEX)
+ return -EINVAL;
+
+ if (hex < 0x7)
+ uV = 500000;
+ else
+ uV = 500000 + (hex - 0x6) * 10000;
+
+ if (range)
+ uV *= 2;
+
+ return uV;
+}
+
+static int palmas_smps_val(struct udevice *dev, int op, int *uV)
+{
+ unsigned int hex, adr;
+ int ret;
+ bool range;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ if (op == PMIC_OP_GET)
+ *uV = 0;
+
+ adr = uc_pdata->volt_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ if (ret & PALMAS_SMPS_RANGE_MASK)
+ range = true;
+ else
+ range = false;
+
+ ret &= PALMAS_SMPS_VOLT_MASK;
+ ret = palmas_smps_hex2volt(ret, range);
+ if (ret < 0)
+ return ret;
+ *uV = ret;
+
+ return 0;
+ }
+
+ hex = palmas_smps_volt2hex(*uV);
+ if (hex < 0)
+ return hex;
+
+ ret &= ~PALMAS_SMPS_VOLT_MASK;
+ ret |= hex;
+ if (*uV > 1650000)
+ ret |= PALMAS_SMPS_RANGE_MASK;
+
+ return pmic_reg_write(dev->parent, adr, ret);
+}
+
+static int palmas_ldo_enable(struct udevice *dev, int op, bool *enable)
+{
+ int ret;
+ unsigned int adr;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ adr = uc_pdata->ctrl_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ ret &= PALMAS_LDO_STATUS_MASK;
+
+ if (ret)
+ *enable = true;
+ else
+ *enable = false;
+
+ return 0;
+ } else if (op == PMIC_OP_SET) {
+ if (*enable)
+ ret |= PALMAS_LDO_MODE_MASK;
+ else
+ ret &= ~(PALMAS_LDO_MODE_MASK);
+
+ ret = pmic_reg_write(dev->parent, adr, ret);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int palmas_ldo_volt2hex(int uV)
+{
+ if (uV > PALMAS_LDO_VOLT_MAX)
+ return -EINVAL;
+
+ return (uV - 850000) / 50000;
+}
+
+static int palmas_ldo_hex2volt(int hex)
+{
+ if (hex > PALMAS_LDO_VOLT_MAX_HEX)
+ return -EINVAL;
+
+ if (!hex)
+ return 0;
+
+ return (hex * 50000) + 850000;
+}
+
+static int palmas_ldo_val(struct udevice *dev, int op, int *uV)
+{
+ unsigned int hex, adr;
+ int ret;
+
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ if (op == PMIC_OP_GET)
+ *uV = 0;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ adr = uc_pdata->volt_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ ret &= PALMAS_LDO_VOLT_MASK;
+ ret = palmas_ldo_hex2volt(ret);
+ if (ret < 0)
+ return ret;
+ *uV = ret;
+ return 0;
+ }
+
+ hex = palmas_ldo_volt2hex(*uV);
+ if (hex < 0)
+ return hex;
+
+ ret &= ~PALMAS_LDO_VOLT_MASK;
+ ret |= hex;
+ if (*uV > 1650000)
+ ret |= 0x80;
+
+ return pmic_reg_write(dev->parent, adr, ret);
+}
+
+static int palmas_ldo_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+ struct udevice *parent;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ parent = dev_get_parent(dev);
+ int type = dev_get_driver_data(parent);
+
+ uc_pdata->type = REGULATOR_TYPE_LDO;
+
+ if (dev->driver_data) {
+ u8 idx = dev->driver_data - 1;
+ uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][idx];
+ uc_pdata->volt_reg = palmas_ldo_volt[type][idx];
+ } else {
+ /* check for ldoln and ldousb cases */
+ if (!strcmp("ldoln", dev->name)) {
+ uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][9];
+ uc_pdata->volt_reg = palmas_ldo_volt[type][9];
+ } else if (!strcmp("ldousb", dev->name)) {
+ uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][10];
+ uc_pdata->volt_reg = palmas_ldo_volt[type][10];
+ }
+ }
+
+ return 0;
+}
+
+static int ldo_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = palmas_ldo_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int ldo_set_value(struct udevice *dev, int uV)
+{
+ return palmas_ldo_val(dev, PMIC_OP_SET, &uV);
+}
+
+static bool ldo_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+ ret = palmas_ldo_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+
+ return enable;
+}
+
+static int ldo_set_enable(struct udevice *dev, bool enable)
+{
+ return palmas_ldo_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static int palmas_smps_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+ struct udevice *parent;
+ int idx;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ parent = dev_get_parent(dev);
+ int type = dev_get_driver_data(parent);
+
+ uc_pdata->type = REGULATOR_TYPE_BUCK;
+
+ switch (type) {
+ case PALMAS:
+ case TPS659038:
+ switch (dev->driver_data) {
+ case 123:
+ case 12:
+ uc_pdata->ctrl_reg = palmas_smps_ctrl[type][0];
+ uc_pdata->volt_reg = palmas_smps_volt[type][0];
+ break;
+ case 3:
+ uc_pdata->ctrl_reg = palmas_smps_ctrl[type][1];
+ uc_pdata->volt_reg = palmas_smps_volt[type][1];
+ break;
+ case 45:
+ uc_pdata->ctrl_reg = palmas_smps_ctrl[type][2];
+ uc_pdata->volt_reg = palmas_smps_volt[type][2];
+ break;
+ case 6:
+ case 7:
+ case 8:
+ case 9:
+ case 10:
+ idx = dev->driver_data - 4;
+ uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
+ uc_pdata->volt_reg = palmas_smps_volt[type][idx];
+ break;
+
+ default:
+ printf("Wrong ID for regulator\n");
+ }
+ break;
+
+ case TPS65917:
+ switch (dev->driver_data) {
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ idx = dev->driver_data - 1;
+ uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
+ uc_pdata->volt_reg = palmas_smps_volt[type][idx];
+ break;
+
+ default:
+ printf("Wrong ID for regulator\n");
+ }
+ break;
+
+ default:
+ printf("Invalid PMIC ID\n");
+ }
+
+ return 0;
+}
+
+static int smps_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = palmas_smps_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int smps_set_value(struct udevice *dev, int uV)
+{
+ return palmas_smps_val(dev, PMIC_OP_SET, &uV);
+}
+
+static bool smps_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+ ret = palmas_smps_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+
+ return enable;
+}
+
+static int smps_set_enable(struct udevice *dev, bool enable)
+{
+ return palmas_smps_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static const struct dm_regulator_ops palmas_ldo_ops = {
+ .get_value = ldo_get_value,
+ .set_value = ldo_set_value,
+ .get_enable = ldo_get_enable,
+ .set_enable = ldo_set_enable,
+};
+
+U_BOOT_DRIVER(palmas_ldo) = {
+ .name = PALMAS_LDO_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &palmas_ldo_ops,
+ .probe = palmas_ldo_probe,
+};
+
+static const struct dm_regulator_ops palmas_smps_ops = {
+ .get_value = smps_get_value,
+ .set_value = smps_set_value,
+ .get_enable = smps_get_enable,
+ .set_enable = smps_set_enable,
+};
+
+U_BOOT_DRIVER(palmas_smps) = {
+ .name = PALMAS_SMPS_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &palmas_smps_ops,
+ .probe = palmas_smps_probe,
+};
Enable support for manipulating Tegra's on-SoC reset signals via IPC
requests to the BPMP (Boot and Power Management Processor).
+config RESET_UNIPHIER
+ bool "Reset controller driver for UniPhier SoCs"
+ depends on ARCH_UNIPHIER
+ default y
+ help
+ Support for reset controllers on UniPhier SoCs.
+ Say Y if you want to control reset signals provided by System Control
+ block, Media I/O block, Peripheral Block.
+
endmenu
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
+obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
--- /dev/null
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <reset-uclass.h>
+#include <dm/device.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+struct uniphier_reset_data {
+ unsigned int id;
+ unsigned int reg;
+ unsigned int bit;
+ unsigned int flags;
+#define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
+};
+
+#define UNIPHIER_RESET_ID_END (unsigned int)(-1)
+
+#define UNIPHIER_RESET_END \
+ { .id = UNIPHIER_RESET_ID_END }
+
+#define UNIPHIER_RESET(_id, _reg, _bit) \
+ { \
+ .id = (_id), \
+ .reg = (_reg), \
+ .bit = (_bit), \
+ }
+
+#define UNIPHIER_RESETX(_id, _reg, _bit) \
+ { \
+ .id = (_id), \
+ .reg = (_reg), \
+ .bit = (_bit), \
+ .flags = UNIPHIER_RESET_ACTIVE_LOW, \
+ }
+
+/* System reset data */
+#define UNIPHIER_SLD3_SYS_RESET_STDMAC(id) \
+ UNIPHIER_RESETX((id), 0x2000, 10)
+
+#define UNIPHIER_LD11_SYS_RESET_STDMAC(id) \
+ UNIPHIER_RESETX((id), 0x200c, 8)
+
+#define UNIPHIER_PRO4_SYS_RESET_GIO(id) \
+ UNIPHIER_RESETX((id), 0x2000, 6)
+
+#define UNIPHIER_LD20_SYS_RESET_GIO(id) \
+ UNIPHIER_RESETX((id), 0x200c, 5)
+
+#define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch) \
+ UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17)
+
+const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = {
+ UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */
+ UNIPHIER_RESET_END,
+};
+
+const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
+ UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, MIO, RLE */
+ UNIPHIER_PRO4_SYS_RESET_GIO(12), /* Ether, SATA, USB3 */
+ UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
+ UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
+ UNIPHIER_RESET_END,
+};
+
+const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
+ UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC */
+ UNIPHIER_PRO4_SYS_RESET_GIO(12), /* PCIe, USB3 */
+ UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
+ UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
+ UNIPHIER_RESET_END,
+};
+
+const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
+ UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, RLE */
+ UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
+ UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
+ UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */
+ UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */
+ UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */
+ UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */
+ UNIPHIER_RESETX(21, 0x2014, 1), /* USB31-PHY1 */
+ UNIPHIER_RESETX(28, 0x2014, 12), /* SATA */
+ UNIPHIER_RESET(29, 0x2014, 8), /* SATA-PHY (active high) */
+ UNIPHIER_RESET_END,
+};
+
+const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
+ UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC, MIO */
+ UNIPHIER_RESET_END,
+};
+
+const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
+ UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC */
+ UNIPHIER_LD20_SYS_RESET_GIO(12), /* PCIe, USB3 */
+ UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
+ UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */
+ UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */
+ UNIPHIER_RESETX(19, 0x200c, 15), /* USB30-PHY3 */
+ UNIPHIER_RESET_END,
+};
+
+/* Media I/O reset data */
+#define UNIPHIER_MIO_RESET_SD(id, ch) \
+ UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0)
+
+#define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch) \
+ UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 26)
+
+#define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch) \
+ UNIPHIER_RESETX((id), 0x80 + 0x200 * (ch), 0)
+
+#define UNIPHIER_MIO_RESET_USB2(id, ch) \
+ UNIPHIER_RESETX((id), 0x114 + 0x200 * (ch), 0)
+
+#define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch) \
+ UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 24)
+
+#define UNIPHIER_MIO_RESET_DMAC(id) \
+ UNIPHIER_RESETX((id), 0x110, 17)
+
+const struct uniphier_reset_data uniphier_mio_reset_data[] = {
+ UNIPHIER_MIO_RESET_SD(0, 0),
+ UNIPHIER_MIO_RESET_SD(1, 1),
+ UNIPHIER_MIO_RESET_SD(2, 2),
+ UNIPHIER_MIO_RESET_SD_BRIDGE(3, 0),
+ UNIPHIER_MIO_RESET_SD_BRIDGE(4, 1),
+ UNIPHIER_MIO_RESET_SD_BRIDGE(5, 2),
+ UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
+ UNIPHIER_MIO_RESET_DMAC(7),
+ UNIPHIER_MIO_RESET_USB2(8, 0),
+ UNIPHIER_MIO_RESET_USB2(9, 1),
+ UNIPHIER_MIO_RESET_USB2(10, 2),
+ UNIPHIER_MIO_RESET_USB2(11, 3),
+ UNIPHIER_MIO_RESET_USB2_BRIDGE(12, 0),
+ UNIPHIER_MIO_RESET_USB2_BRIDGE(13, 1),
+ UNIPHIER_MIO_RESET_USB2_BRIDGE(14, 2),
+ UNIPHIER_MIO_RESET_USB2_BRIDGE(15, 3),
+ UNIPHIER_RESET_END,
+};
+
+/* Peripheral reset data */
+#define UNIPHIER_PERI_RESET_UART(id, ch) \
+ UNIPHIER_RESETX((id), 0x114, 19 + (ch))
+
+#define UNIPHIER_PERI_RESET_I2C(id, ch) \
+ UNIPHIER_RESETX((id), 0x114, 5 + (ch))
+
+#define UNIPHIER_PERI_RESET_FI2C(id, ch) \
+ UNIPHIER_RESETX((id), 0x114, 24 + (ch))
+
+const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
+ UNIPHIER_PERI_RESET_UART(0, 0),
+ UNIPHIER_PERI_RESET_UART(1, 1),
+ UNIPHIER_PERI_RESET_UART(2, 2),
+ UNIPHIER_PERI_RESET_UART(3, 3),
+ UNIPHIER_PERI_RESET_I2C(4, 0),
+ UNIPHIER_PERI_RESET_I2C(5, 1),
+ UNIPHIER_PERI_RESET_I2C(6, 2),
+ UNIPHIER_PERI_RESET_I2C(7, 3),
+ UNIPHIER_PERI_RESET_I2C(8, 4),
+ UNIPHIER_RESET_END,
+};
+
+const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = {
+ UNIPHIER_PERI_RESET_UART(0, 0),
+ UNIPHIER_PERI_RESET_UART(1, 1),
+ UNIPHIER_PERI_RESET_UART(2, 2),
+ UNIPHIER_PERI_RESET_UART(3, 3),
+ UNIPHIER_PERI_RESET_FI2C(4, 0),
+ UNIPHIER_PERI_RESET_FI2C(5, 1),
+ UNIPHIER_PERI_RESET_FI2C(6, 2),
+ UNIPHIER_PERI_RESET_FI2C(7, 3),
+ UNIPHIER_PERI_RESET_FI2C(8, 4),
+ UNIPHIER_PERI_RESET_FI2C(9, 5),
+ UNIPHIER_PERI_RESET_FI2C(10, 6),
+ UNIPHIER_RESET_END,
+};
+
+/* core implementaton */
+struct uniphier_reset_priv {
+ void __iomem *base;
+ const struct uniphier_reset_data *data;
+};
+
+static int uniphier_reset_request(struct reset_ctl *reset_ctl)
+{
+ return 0;
+}
+
+static int uniphier_reset_free(struct reset_ctl *reset_ctl)
+{
+ return 0;
+}
+
+static int uniphier_reset_update(struct reset_ctl *reset_ctl, int assert)
+{
+ struct uniphier_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ unsigned long id = reset_ctl->id;
+ const struct uniphier_reset_data *p;
+
+ for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) {
+ u32 mask, val;
+
+ if (p->id != id)
+ continue;
+
+ val = readl(priv->base + p->reg);
+
+ if (p->flags & UNIPHIER_RESET_ACTIVE_LOW)
+ assert = !assert;
+
+ mask = BIT(p->bit);
+
+ if (assert)
+ val |= mask;
+ else
+ val &= ~mask;
+
+ writel(val, priv->base + p->reg);
+
+ return 0;
+ }
+
+ dev_err(priv->dev, "reset_id=%lu was not handled\n", id);
+ return -EINVAL;
+}
+
+static int uniphier_reset_assert(struct reset_ctl *reset_ctl)
+{
+ return uniphier_reset_update(reset_ctl, 1);
+}
+
+static int uniphier_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ return uniphier_reset_update(reset_ctl, 0);
+}
+
+static const struct reset_ops uniphier_reset_ops = {
+ .request = uniphier_reset_request,
+ .free = uniphier_reset_free,
+ .rst_assert = uniphier_reset_assert,
+ .rst_deassert = uniphier_reset_deassert,
+};
+
+static int uniphier_reset_probe(struct udevice *dev)
+{
+ struct uniphier_reset_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+
+ addr = dev_get_addr(dev->parent);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->base = devm_ioremap(dev, addr, SZ_4K);
+ if (!priv->base)
+ return -ENOMEM;
+
+ priv->data = (void *)dev_get_driver_data(dev);
+
+ return 0;
+}
+
+static const struct udevice_id uniphier_reset_match[] = {
+ /* System reset */
+ {
+ .compatible = "socionext,uniphier-sld3-reset",
+ .data = (ulong)uniphier_sld3_sys_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld4-reset",
+ .data = (ulong)uniphier_sld3_sys_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro4-reset",
+ .data = (ulong)uniphier_pro4_sys_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-sld8-reset",
+ .data = (ulong)uniphier_sld3_sys_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro5-reset",
+ .data = (ulong)uniphier_pro5_sys_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pxs2-reset",
+ .data = (ulong)uniphier_pxs2_sys_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld11-reset",
+ .data = (ulong)uniphier_ld11_sys_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld20-reset",
+ .data = (ulong)uniphier_ld20_sys_reset_data,
+ },
+ /* Media I/O reset */
+ {
+ .compatible = "socionext,uniphier-sld3-mio-clock",
+ .data = (ulong)uniphier_mio_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld4-mio-reset",
+ .data = (ulong)uniphier_mio_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro4-mio-reset",
+ .data = (ulong)uniphier_mio_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-sld8-mio-reset",
+ .data = (ulong)uniphier_mio_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro5-mio-reset",
+ .data = (ulong)uniphier_mio_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pxs2-mio-reset",
+ .data = (ulong)uniphier_mio_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld11-mio-reset",
+ .data = (ulong)uniphier_mio_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld20-mio-reset",
+ .data = (ulong)uniphier_mio_reset_data,
+ },
+ /* Peripheral reset */
+ {
+ .compatible = "socionext,uniphier-ld4-peri-reset",
+ .data = (ulong)uniphier_ld4_peri_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro4-peri-reset",
+ .data = (ulong)uniphier_pro4_peri_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-sld8-peri-reset",
+ .data = (ulong)uniphier_ld4_peri_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro5-peri-reset",
+ .data = (ulong)uniphier_pro4_peri_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pxs2-peri-reset",
+ .data = (ulong)uniphier_pro4_peri_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld11-peri-reset",
+ .data = (ulong)uniphier_pro4_peri_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld20-peri-reset",
+ .data = (ulong)uniphier_pro4_peri_reset_data,
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_reset) = {
+ .name = "uniphier-reset",
+ .id = UCLASS_RESET,
+ .of_match = uniphier_reset_match,
+ .probe = uniphier_reset_probe,
+ .priv_auto_alloc_size = sizeof(struct uniphier_reset_priv),
+ .ops = &uniphier_reset_ops,
+};
#include <dm.h>
#include <rtc.h>
-#if defined(__I386__) || defined(CONFIG_MALTA)
+#if defined(CONFIG_X86) || defined(CONFIG_MALTA)
#include <asm/io.h>
#define in8(p) inb(p)
#define out8(p, v) outb(v, p)
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
+ u32 mcr_val;
struct fsl_qspi *qspi;
struct fsl_qspi_regs *regs;
u32 total_size;
qspi->slave.max_write_size = TX_BUFFER_SIZE;
+ mcr_val = qspi_read32(qspi->priv.flags, ®s->mcr);
qspi_write32(qspi->priv.flags, ®s->mcr,
- QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK);
+ QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
+ (mcr_val & QSPI_MCR_END_CFD_MASK));
qspi_cfg_smpr(&qspi->priv,
~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
static int fsl_qspi_probe(struct udevice *bus)
{
+ u32 mcr_val;
u32 amba_size_per_chip;
struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
struct fsl_qspi_priv *priv = dev_get_priv(bus);
priv->flash_num = plat->flash_num;
priv->num_chipselect = plat->num_chipselect;
+ mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
qspi_write32(priv->flags, &priv->regs->mcr,
- QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK);
+ QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
+ (mcr_val & QSPI_MCR_END_CFD_MASK));
qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
/* Wait till the device is ready to accept more data. */
while (!burst) {
if (max_cycles++ == MAX_DELAY_US) {
- printf("%s:%d failed to feed %d bytes of %d\n",
+ printf("%s:%d failed to feed %zd bytes of %zd\n",
__FILE__, __LINE__, len - offset, len);
return -ETIMEDOUT;
}
* changes to zero exactly after the last byte is fed into the
* FIFO.
*/
- count = min((u32)burst, len - offset - 1);
+ count = min((size_t)burst, len - offset - 1);
while (count--)
tpm_write_byte(priv, data[offset++],
®s[locality].data);
hcor = (struct ehci_hcor *)((uintptr_t) hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
- debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
- (u32)hccr, (u32)hcor,
+ debug("EHCI-PCI init hccr %#lx and hcor %#lx hc_length %d\n",
+ (ulong)hccr, (ulong)hcor,
(u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
*ret_hccr = hccr;
to update the environment, the breakage may be confusing for users.
This option will be removed around the end of 2016.
+config VIDEO_COREBOOT
+ bool "Enable coreboot framebuffer driver support"
+ depends on X86 && SYS_COREBOOT
+ help
+ Turn on this option to enable a framebuffer driver when U-Boot is
+ loaded by coreboot where the graphics device is configured by
+ coreboot already. This can in principle be used with any platform
+ that coreboot supports.
+
config VIDEO_VESA
bool "Enable VESA video driver support"
default n
bool "Enable Intel Broadwell integrated graphics device"
depends on X86
help
- This enabled support for integrated graphics on Intel broadwell
+ This enables support for integrated graphics on Intel broadwell
+ devices. Initialisation is mostly performed by a VGA boot ROM, with
+ some setup handled by U-Boot itself. The graphics adaptor works as
+ a VESA device and supports LCD panels, eDP and LVDS outputs.
+ Configuration of most aspects of device operation is performed using
+ a special tool which configures the VGA ROM, but the graphics
+ resolution can be selected in U-Boot.
+
+config VIDEO_IVYBRIDGE_IGD
+ bool "Enable Intel Ivybridge integration graphics support"
+ depends on X86
+ help
+ This enables support for integrated graphics on Intel ivybridge
devices. Initialisation is mostly performed by a VGA boot ROM, with
some setup handled by U-Boot itself. The graphics adaptor works as
a VESA device and supports LCD panels, eDP and LVDS outputs.
endif
obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o
+obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o
obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
obj-$(CONFIG_LD9040) += ld9040.o
obj-$(CONFIG_SED156X) += sed156x.o
obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o
-obj-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o
+obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
obj-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o
obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o videomodes.o
obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o
obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
-obj-$(CONFIG_VIDEO_VESA) += vesa_fb.o
+obj-$(CONFIG_VIDEO_VESA) += vesa.o
obj-$(CONFIG_FORMIKE) += formike.o
obj-$(CONFIG_LG4573) += lg4573.o
obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
#include <common.h>
#include <bios_emul.h>
#include <dm.h>
-#include <pci_rom.h>
#include <vbe.h>
#include <video.h>
-#include <video_fb.h>
#include <asm/cpu.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/iomap.h>
#include <asm/arch/pch.h>
-#include <linux/log2.h>
#include "i915_reg.h"
struct broadwell_igd_priv {
- GraphicDevice ctfb;
u8 *regs;
};
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
- struct broadwell_igd_priv *priv = dev_get_priv(dev);
bool is_broadwell;
- GraphicDevice *gdev = &priv->ctfb;
- int bits_per_pixel;
int ret;
if (!ll_boot_init()) {
debug("%s: is_broadwell=%d\n", __func__, is_broadwell);
ret = igd_pre_init(dev, is_broadwell);
if (!ret) {
- ret = dm_pci_run_vga_bios(dev, broadwell_igd_int15_handler,
- PCI_ROM_USE_NATIVE |
- PCI_ROM_ALLOW_FALLBACK);
- if (ret) {
- printf("failed to run video BIOS: %d\n", ret);
- ret = -EIO;
- }
+ ret = vbe_setup_video(dev, broadwell_igd_int15_handler);
+ if (ret)
+ debug("failed to run video BIOS: %d\n", ret);
}
if (!ret)
ret = igd_post_init(dev, is_broadwell);
if (ret)
return ret;
- if (vbe_get_video_info(gdev)) {
- printf("No video mode configured\n");
- return -ENXIO;
- }
-
- /* Use write-through for the graphics memory, 256MB */
- ret = mtrr_add_request(MTRR_TYPE_WRTHROUGH, gdev->pciBase, 256 << 20);
+ /* Use write-combining for the graphics memory, 256MB */
+ ret = mtrr_add_request(MTRR_TYPE_WRCOMB, plat->base, 256 << 20);
if (!ret)
ret = mtrr_commit(true);
if (ret && ret != -ENOSYS) {
ret);
}
- bits_per_pixel = gdev->gdfBytesPP * 8;
- sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
- bits_per_pixel);
- printf("%s\n", gdev->modeIdent);
- uc_priv->xsize = gdev->winSizeX;
- uc_priv->ysize = gdev->winSizeY;
- uc_priv->bpix = ilog2(bits_per_pixel);
- plat->base = gdev->pciBase;
- plat->size = gdev->memSize;
- debug("fb=%x, size %x, display size=%d %d %d\n", gdev->pciBase,
- gdev->memSize, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix);
+ debug("fb=%lx, size %x, display size=%d %d %d\n", plat->base,
+ plat->size, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix);
return 0;
}
--- /dev/null
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <vbe.h>
+#include <video.h>
+#include <asm/arch/sysinfo.h>
+
+static int save_vesa_mode(struct cb_framebuffer *fb,
+ struct vesa_mode_info *vesa)
+{
+ /*
+ * If there is no framebuffer structure, bail out and keep
+ * running on the serial console.
+ */
+ if (!fb)
+ return -ENXIO;
+
+ vesa->x_resolution = fb->x_resolution;
+ vesa->y_resolution = fb->y_resolution;
+ vesa->bits_per_pixel = fb->bits_per_pixel;
+ vesa->bytes_per_scanline = fb->bytes_per_line;
+ vesa->phys_base_ptr = fb->physical_address;
+ vesa->red_mask_size = fb->red_mask_size;
+ vesa->red_mask_pos = fb->red_mask_pos;
+ vesa->green_mask_size = fb->green_mask_size;
+ vesa->green_mask_pos = fb->green_mask_pos;
+ vesa->blue_mask_size = fb->blue_mask_size;
+ vesa->blue_mask_pos = fb->blue_mask_pos;
+ vesa->reserved_mask_size = fb->reserved_mask_size;
+ vesa->reserved_mask_pos = fb->reserved_mask_pos;
+
+ return 0;
+}
+
+static int coreboot_video_probe(struct udevice *dev)
+{
+ struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct cb_framebuffer *fb = lib_sysinfo.framebuffer;
+ struct vesa_mode_info *vesa = &mode_info.vesa;
+ int ret;
+
+ printf("Video: ");
+
+ /* Initialize vesa_mode_info structure */
+ ret = save_vesa_mode(fb, vesa);
+ if (ret)
+ goto err;
+
+ ret = vbe_setup_video_priv(vesa, uc_priv, plat);
+ if (ret)
+ goto err;
+
+ printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
+ vesa->bits_per_pixel);
+
+ return 0;
+
+err:
+ printf("No video mode configured in coreboot!\n");
+ return ret;
+}
+
+static const struct udevice_id coreboot_video_ids[] = {
+ { .compatible = "coreboot-fb" },
+ { }
+};
+
+U_BOOT_DRIVER(coreboot_video) = {
+ .name = "coreboot_video",
+ .id = UCLASS_VIDEO,
+ .of_match = coreboot_video_ids,
+ .probe = coreboot_video_probe,
+};
+++ /dev/null
-/*
- * coreboot Framebuffer driver.
- *
- * Copyright (C) 2011 The Chromium OS authors
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/sysinfo.h>
-#include <vbe.h>
-#include <video_fb.h>
-#include "videomodes.h"
-
-/*
- * The Graphic Device
- */
-GraphicDevice ctfb;
-
-static void save_vesa_mode(void)
-{
- struct vesa_mode_info *vesa = &mode_info.vesa;
- struct cb_framebuffer *fb = lib_sysinfo.framebuffer;
-
- vesa->x_resolution = fb->x_resolution;
- vesa->y_resolution = fb->y_resolution;
- vesa->bits_per_pixel = fb->bits_per_pixel;
- vesa->bytes_per_scanline = fb->bytes_per_line;
- vesa->phys_base_ptr = fb->physical_address;
- vesa->red_mask_size = fb->red_mask_size;
- vesa->red_mask_pos = fb->red_mask_pos;
- vesa->green_mask_size = fb->green_mask_size;
- vesa->green_mask_pos = fb->green_mask_pos;
- vesa->blue_mask_size = fb->blue_mask_size;
- vesa->blue_mask_pos = fb->blue_mask_pos;
- vesa->reserved_mask_size = fb->reserved_mask_size;
- vesa->reserved_mask_pos = fb->reserved_mask_pos;
-}
-
-static int parse_coreboot_table_fb(GraphicDevice *gdev)
-{
- struct cb_framebuffer *fb = lib_sysinfo.framebuffer;
-
- /* If there is no framebuffer structure, bail out and keep
- * running on the serial console.
- */
- if (!fb)
- return 0;
-
- gdev->winSizeX = fb->x_resolution;
- gdev->winSizeY = fb->y_resolution;
-
- gdev->plnSizeX = fb->x_resolution;
- gdev->plnSizeY = fb->y_resolution;
-
- gdev->gdfBytesPP = fb->bits_per_pixel / 8;
-
- switch (fb->bits_per_pixel) {
- case 24:
- gdev->gdfIndex = GDF_32BIT_X888RGB;
- break;
- case 16:
- gdev->gdfIndex = GDF_16BIT_565RGB;
- break;
- default:
- gdev->gdfIndex = GDF__8BIT_INDEX;
- break;
- }
-
- gdev->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
- gdev->pciBase = (unsigned int)fb->physical_address;
-
- gdev->frameAdrs = (unsigned int)fb->physical_address;
- gdev->memSize = fb->bytes_per_line * fb->y_resolution;
-
- gdev->vprBase = (unsigned int)fb->physical_address;
- gdev->cprBase = (unsigned int)fb->physical_address;
-
- return 1;
-}
-
-void *video_hw_init(void)
-{
- GraphicDevice *gdev = &ctfb;
- int bits_per_pixel;
-
- printf("Video: ");
-
- if (!parse_coreboot_table_fb(gdev)) {
- printf("No video mode configured in coreboot!\n");
- return NULL;
- }
-
- bits_per_pixel = gdev->gdfBytesPP * 8;
-
- /* fill in Graphic device struct */
- sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
- bits_per_pixel);
- printf("%s\n", gdev->modeIdent);
-
- memset((void *)gdev->pciBase, 0,
- gdev->winSizeX * gdev->winSizeY * gdev->gdfBytesPP);
-
- /* Initialize vesa_mode_info structure */
- save_vesa_mode();
-
- return (void *)gdev;
-}
/*
- * From Coreboot file of the same name
- *
- * Copyright (C) 2011 Chromium OS Authors
+ * Copyright (C) 2016 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <errno.h>
#include <fdtdec.h>
#include <pci_rom.h>
+#include <vbe.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/mtrr.h>
u32 value;
};
+/* These are magic values - unfortunately the meaning is unknown */
static const struct gt_powermeter snb_pm_gt1[] = {
{ 0xa200, 0xcc000000 },
{ 0xa204, 0x07000040 },
{ 0 }
};
-/*
- * Some vga option roms are used for several chipsets but they only have one
- * PCI ID in their header. If we encounter such an option rom, we need to do
- * the mapping ourselves.
- */
-
-u32 map_oprom_vendev(u32 vendev)
-{
- u32 new_vendev = vendev;
-
- switch (vendev) {
- case 0x80860102: /* GT1 Desktop */
- case 0x8086010a: /* GT1 Server */
- case 0x80860112: /* GT2 Desktop */
- case 0x80860116: /* GT2 Mobile */
- case 0x80860122: /* GT2 Desktop >=1.3GHz */
- case 0x80860126: /* GT2 Mobile >=1.3GHz */
- case 0x80860156: /* IVB */
- case 0x80860166: /* IVB */
- /* Set to GT1 Mobile */
- new_vendev = 0x80860106;
- break;
- }
-
- return new_vendev;
-}
-
static inline u32 gtt_read(void *bar, u32 reg)
{
return readl(bar + reg);
return 0;
}
-int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar)
+static int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar)
{
const void *blob = gd->fdt_blob;
int node = dev->of_offset;
return res;
}
-void sandybridge_setup_graphics(struct udevice *dev, struct udevice *video_dev)
+static void sandybridge_setup_graphics(struct udevice *dev,
+ struct udevice *video_dev)
{
u32 reg32;
u16 reg16;
writel(reg32, MCHBAR_REG(0x5418));
}
-int gma_func0_init(struct udevice *dev)
+static int gma_func0_init(struct udevice *dev)
{
-#ifdef CONFIG_VIDEO
- ulong start;
-#endif
struct udevice *nbridge;
void *gtt_bar;
ulong base;
if (ret)
return ret;
-#ifdef CONFIG_VIDEO
- start = get_timer(0);
- ret = dm_pci_run_vga_bios(dev, int15_handler,
- PCI_ROM_USE_NATIVE | PCI_ROM_ALLOW_FALLBACK);
- debug("BIOS ran in %lums\n", get_timer(start));
-#endif
+ return rev;
+}
+
+static int bd82x6x_video_probe(struct udevice *dev)
+{
+ void *gtt_bar;
+ int ret, rev;
+
+ rev = gma_func0_init(dev);
+ if (rev < 0)
+ return rev;
+ ret = vbe_setup_video(dev, int15_handler);
+ if (ret)
+ return ret;
+
/* Post VBIOS init */
+ gtt_bar = (void *)dm_pci_read_bar32(dev, 0);
ret = gma_pm_init_post_vbios(dev, rev, gtt_bar);
if (ret)
return ret;
return 0;
}
+
+static const struct udevice_id bd82x6x_video_ids[] = {
+ { .compatible = "intel,gma" },
+ { }
+};
+
+U_BOOT_DRIVER(bd82x6x_video) = {
+ .name = "bd82x6x_video",
+ .id = UCLASS_VIDEO,
+ .of_match = bd82x6x_video_ids,
+ .probe = bd82x6x_video_probe,
+};
ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
"power-supply", &priv->reg);
if (ret) {
- debug("%s: Warning: cnnot get power supply: ret=%d\n",
+ debug("%s: Warning: cannot get power supply: ret=%d\n",
__func__, ret);
if (ret != -ENOENT)
return ret;
--- /dev/null
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pci.h>
+#include <vbe.h>
+
+static int vesa_video_probe(struct udevice *dev)
+{
+ return vbe_setup_video(dev, NULL);
+}
+
+static const struct udevice_id vesa_video_ids[] = {
+ { .compatible = "vesa-fb" },
+ { }
+};
+
+U_BOOT_DRIVER(vesa_video) = {
+ .name = "vesa_video",
+ .id = UCLASS_VIDEO,
+ .of_match = vesa_video_ids,
+ .probe = vesa_video_probe,
+};
+
+static struct pci_device_id vesa_video_supported[] = {
+ { PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, ~0) },
+ { },
+};
+
+U_BOOT_PCI_DEVICE(vesa_video, vesa_video_supported);
+++ /dev/null
-/*
- * VESA frame buffer driver
- *
- * Copyright (C) 2014 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <pci_rom.h>
-#include <video_fb.h>
-#include <vbe.h>
-
-/*
- * The Graphic Device
- */
-GraphicDevice ctfb;
-
-void *video_hw_init(void)
-{
- GraphicDevice *gdev = &ctfb;
- struct udevice *dev;
- int bits_per_pixel;
- int ret;
-
- printf("Video: ");
- if (!ll_boot_init()) {
- /*
- * If we are running from EFI or coreboot, this driver can't
- * work.
- */
- printf("Not available (previous bootloader prevents it)\n");
- return NULL;
- }
- if (vbe_get_video_info(gdev)) {
- ret = dm_pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0, &dev);
- if (ret) {
- printf("no card detected\n");
- return NULL;
- }
- bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
- ret = dm_pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE |
- PCI_ROM_ALLOW_FALLBACK);
- bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
- if (ret) {
- printf("failed to run video BIOS: %d\n", ret);
- return NULL;
- }
- }
-
- if (vbe_get_video_info(gdev)) {
- printf("No video mode configured\n");
- return NULL;
- }
-
- bits_per_pixel = gdev->gdfBytesPP * 8;
- sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
- bits_per_pixel);
- printf("%s\n", gdev->modeIdent);
- debug("Frame buffer at %x\n", gdev->pciBase);
-
- return (void *)gdev;
-}
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
ulong base, align, size;
+ if (!plat->size)
+ return 0;
+
align = plat->align ? plat->align : 1 << 20;
base = *addrp - plat->size;
base &= ~(align - 1);
printf("%s %10lu %s\n", os_dirent_get_typename(node->type),
node->size, node->name);
}
+ os_dirent_free(head);
return 0;
}
EXPORT_FUNC(putc, void, putc, const char)
EXPORT_FUNC(puts, void, puts, const char *)
EXPORT_FUNC(printf, int, printf, const char*, ...)
-#if defined(CONFIG_X86) || defined(CONFIG_PPC)
+#if (defined(CONFIG_X86) && !defined(CONFIG_X86_64)) || defined(CONFIG_PPC)
EXPORT_FUNC(irq_install_handler, void, install_hdlr,
int, interrupt_handler_t, void*)
extern ulong __rel_dyn_start;
extern ulong __rel_dyn_end;
extern ulong __bss_end;
+extern ulong _image_binary_end;
extern ulong _TEXT_BASE; /* code start */
/*
* BOARD/CPU
*/
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
/*
* BOARD/CPU
*/
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* B4860 QDS board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#ifdef CONFIG_BSC9131RDB
#define CONFIG_BSC9131
#define CONFIG_NAND_FSL_IFC
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#ifdef CONFIG_BSC9132QDS
#define CONFIG_BSC9132
#endif
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#ifdef CONFIG_C29XPCIE
#define CONFIG_PPC_C29X
#endif
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
*/
#define CONFIG_M54451EVB /* M54451EVB board */
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
*/
#define CONFIG_M54455EVB /* M54455EVB board */
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
* (easy to change)
*/
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
* (easy to change)
*/
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
#define CONFIG_SYS_LOWBOOT
#endif
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
#define CONFIG_MPC837XERDB 1
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0xFE000000
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_SDCARD
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#include "../board/freescale/common/ics307_clk.h"
#ifndef CONFIG_SYS_TEXT_BASE
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/* High Level Configuration Options */
#define CONFIG_MPC8610 1 /* MPC8610 specific */
#define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/* High Level Configuration Options */
#define CONFIG_MPC8641 1 /* MPC8641 specific */
#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_P1010
#define CONFIG_E500 /* BOOKE e500 family */
#include <asm/config_mpc85xx.h>
#include "../board/freescale/common/ics307_clk.h"
-#define CONFIG_DISPLAY_BOARDINFO
-
#ifdef CONFIG_SDCARD
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#define __CONFIG_H
#define CONFIG_P2041RDB
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_PPC_P2041
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_PLU405 1 /* ...on a PLU405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_SYS_TEXT_BASE 0xFFF90000
#endif
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_SYS_CLK_FREQ 33333400
#if 0 /* temporary disabled because OS/9 does not like dcache on startup */
#define __T1024QDS_H
/* High Level Configuration Options */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOOKE
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_E500MC /* BOOKE e500mc family */
#define __T1024RDB_H
/* High Level Configuration Options */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOOKE
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_E500MC /* BOOKE e500mc family */
* T1040 QDS board configuration file
*/
#define CONFIG_T1040QDS
-#define CONFIG_DISPLAY_BOARDINFO
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
* T104x RDB board configuration file
*/
#define CONFIG_T104xRDB
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_E500 /* BOOKE e500 family */
#include <asm/config_mpc85xx.h>
#ifndef __T208xQDS_H
#define __T208xQDS_H
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#define CONFIG_MMC
#define CONFIG_USB_EHCI
#ifndef __T2080RDB_H
#define __T2080RDB_H
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_T2080RDB
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#define CONFIG_MMC
#define __CONFIG_H
#define CONFIG_T4240RDB
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE4
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
-#define CONFIG_DISPLAY_BOARDINFO
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
#define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
#define CONFIG_MPC860 1
#define CONFIG_MPC860T 1
#define CONFIG_MPC862 1
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */
#define CONFIG_MPC860 1
#define CONFIG_MPC860T 1
#define CONFIG_MPC862 1
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */
#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_FSL_ELBC
#define CONFIG_PCI
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
-#define CONFIG_DISPLAY_BOARDINFO /* Display board info */
-
#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */
#define CONFIG_VOM405 1 /* ...on a VOM405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC8000
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_MPC5200
#define CONFIG_A3M071 /* A3M071 board */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
#define CONFIG_A4M072 1 /* ... on A4M072 board */
#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0xFE000000
#define __CONFIG_H
#define CONFIG_AC14XX 1
-#define CONFIG_DISPLAY_BOARDINFO
/*
* Memory map for the ifm AC14xx board:
#include "mx6_common.h"
#include <linux/sizes.h>
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
-/* Display CPU and Board information */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_HZ 1000
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_NO_FLASH
/*
- * Board display option
- */
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_DISPLAY_CPUINFO
-
-/*
* SPL
*/
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_DATE
#define __CONFIG_H
#define CONFIG_ARIA 1
-#define CONFIG_DISPLAY_BOARDINFO
/*
* Memory map for the ARIA board:
#undef CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_USE_ARCH_MEMSET
#define CONFIG_USE_ARCH_MEMCPY
#endif
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_DISPLAY_CPUINFO
-
#define CONFIG_ATMEL_LEGACY
#define CONFIG_SYS_TEXT_BASE 0x21f00000
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
-
/*
* Hardware drivers
*/
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
/* general purpose I/O */
#define CONFIG_AT91_GPIO
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
-#define CONFIG_DISPLAY_CPUINFO
-
#define CONFIG_ATMEL_LEGACY
#define CONFIG_AT91_GPIO 1
#define CONFIG_AT91_GPIO_PULLUP 1
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#define CONFIG_PCI_PNP
-#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \
- "stdout=serial,vga\0" \
- "stderr=serial,vga\0"
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_NAND
#define __CONFIGS_BOSTON_H__
/*
- * General board configuration
- */
-#define CONFIG_DISPLAY_BOARDINFO
-
-/*
* CPU
*/
#define CONFIG_SYS_MIPS_TIMER_FREQ 30000000
#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */
-#define CONFIG_DISPLAY_BOARDINFO
/*
* allowed and functional CONFIG_SYS_TEXT_BASE values:
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#define CONFIG_SYS_FSL_CLK
#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SKIP_LOWLEVEL_INIT
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x5ff000
-/* Video is not supported for now */
-#undef CONFIG_VIDEO
-#undef CONFIG_CFB_CONSOLE
-
#endif /* __CONFIG_H */
#define CONFIG_PCI_PNP
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
- "stdout=serial,vga\0" \
- "stderr=serial,vga\0"
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_CYRUS
#if !defined(CONFIG_PPC_P5020) && !defined(CONFIG_PPC_P5040)
#define CONFIG_DBAU1X00 1
#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
-#define CONFIG_DISPLAY_BOARDINFO
-
#ifdef CONFIG_DBAU1000
/* Also known as Merlot */
#define CONFIG_SOC_AU1000 1
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
/*
#include <configs/ti_omap3_common.h>
-/* Display CPU and Board information */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
#define CONFIG_MISC_INIT_R
#define CONFIG_REVISION_TAG 1
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
-#define CONFIG_DISPLAY_BOARDINFO
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/*
- * Display cpu info at boot
- */
-#define CONFIG_DISPLAY_CPUINFO
-
-/*
* Environment variables configurations
*/
#ifdef CONFIG_CMD_NAND
#include "siemens-am33x-common.h"
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_MPUCLK 300
#define DDR_PLL_FREQ 303
#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
--- /dev/null
+/*
+ * (C) Copyright 2011
+ * Jason Cooper <u-boot@lakedaemon.net>
+ *
+ * Based on work by:
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_DS109_H
+#define _CONFIG_DS109_H
+
+/*
+ * FIXME: This belongs in mach-types.h. However, we only pull mach-types
+ * from Linus' kernel.org tree. This hasn't been updated primarily due to
+ * the recent arch/arm reshuffling. So, in the meantime, we'll place it
+ * here.
+ */
+#include <asm/mach-types.h>
+#ifdef MACH_TYPE_SYNOLOGY
+#error "MACH_TYPE_SYNOLOGY has been defined properly, please remove this."
+#else
+#define MACH_TYPE_SYNOLOGY 527
+#endif
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
+#define CONFIG_MACH_TYPE MACH_TYPE_SYNOLOGY
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+/*
+ * mv-plug-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-plug-common.h"
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64k */
+#else
+#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
+#endif
+
+#ifdef CONFIG_CMD_SF
+#define CONFIG_HARD_SPI 1
+#define CONFIG_KIRKWOOD_SPI 1
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */
+#endif
+
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_ADDR 0x3d0000
+#define CONFIG_ENV_OFFSET 0x3d0000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \
+ "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
+ "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
+ "bootm 0x6400000;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "x_bootcmd_ethernet=ping 192.168.1.2\0" \
+ "x_bootcmd_usb=usb start\0" \
+ "x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \
+ "x_bootargs=console=ttyS0,115200\0" \
+ "x_bootargs_root=root=/dev/sda2 rootdelay=10\0" \
+ "ipaddr=192.168.1.5\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable one port */
+#define CONFIG_PHY_BASE_ADR 8
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
+
+#endif /* _CONFIG_DS109_H */
#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
-#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_LOAD_ADDR 0x00800000
#undef CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_IS_NOWHERE
-#undef CONFIG_VIDEO
-#undef CONFIG_CFB_CONSOLE
#undef CONFIG_SCSI_AHCI
#undef CONFIG_SCSI
#undef CONFIG_INTEL_ICH6_GPIO
CONFIG_SYS_NAND_BASE2}
#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_MPUCLK 300
#define DDR_PLL_FREQ 303
#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
/* CPU information */
-#define CONFIG_DISPLAY_CPUINFO /* Display at console. */
#define CONFIG_ARCH_CPU_INIT
/* ARM asynchronous clock */
#include <linux/sizes.h>
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#include <linux/sizes.h>
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
/* Size of malloc() pool before and after relocation */
#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_DISPLAY_CPUINFO
-
/* Only in case the value is not present in mach-types.h */
#ifndef MACH_TYPE_FLEA3
#define MACH_TYPE_FLEA3 3668
#undef CONFIG_SCSI_AHCI
#undef CONFIG_SCSI
-/* Video is not supported in Quark SoC */
-#undef CONFIG_VIDEO
-#undef CONFIG_CFB_CONSOLE
-
/* SD/MMC support */
#define CONFIG_MMC
#define CONFIG_SDHCI
#include "mx6_common.h"
#include <linux/sizes.h>
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
* (easy to change)
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
* (easy to change)
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
* (easy to change)
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
* (easy to change)
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
* (easy to change)
#include "imx6_spl.h" /* common IMX6 SPL configuration */
#include "mx6_common.h"
-#undef CONFIG_DISPLAY_BOARDINFO
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */
#define CONFIG_MX27
#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_DISPLAY_CPUINFO
-
#define CONFIG_SYS_TEXT_BASE 0xc0000000
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_MX31 /* This is a mx31 */
#define CONFIG_MX31_CLK32 32000
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_INKA4X0 1 /* INKA4x0 board */
-#define CONFIG_DISPLAY_BOARDINFO
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
#define CONFIG_MPX5200 1 /* MPX5200 board */
#define CONFIG_MPC5200_DDR 1 /* use DDR RAM */
#define CONFIG_IPEK01 /* Motherboard is ipek01 */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0xfc000000
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_JUPITER 1 /* ... on Jupiter board */
-#define CONFIG_DISPLAY_BOARDINFO
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_LONGHELP
#ifndef __CONFIG_KM8309_COMMON_H
#define __CONFIG_KM8309_COMMON_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_KM8321_COMMON_H
#define __CONFIG_KM8321_COMMON_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_KM83XX_H
#define __CONFIG_KM83XX_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
#include "km-powerpc.h"
#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
-#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
#define CONFIG_NR_DRAM_BANKS 4
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
#define CONFIG_NAND_ECC_BCH
-#define CONFIG_DISPLAY_BOARDINFO
-
/* common KM defines */
#include "keymile-common.h"
#error ("Board unsupported")
#endif
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_SYS_TEXT_BASE 0xFE000000
#define CONFIG_MISC_INIT_R
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/* KMBEC FPGA (PRIO) */
#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
#define CONFIG_SYS_KMBEC_FPGA_SIZE 64
#include <asm/arch/rmobile.h>
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_CMDLINE_TAG
#define __LS1012A_COMMON_H
#define CONFIG_FSL_LAYERSCAPE
-#define CONFIG_FSL_LSCH2
#define CONFIG_GICV2
-#define CONFIG_SYS_HAS_SERDES
-
#include <asm/arch/config.h>
#define CONFIG_SYS_NO_FLASH
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
-#define CONFIG_DISPLAY_CPUINFO
-
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "initrd_high=0xffffffff\0" \
"verify=no\0" \
- "hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x80100000\0" \
"kernel_addr=0x100000\0" \
- "ramdisk_addr=0x800000\0" \
- "ramdisk_size=0x2000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"kernel_start=0xa00000\0" \
"kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \
- "console=ttyAMA0,38400n8\0"
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
"earlycon=uart8250,mmio,0x21c0500"
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=no\0" \
+ "loadaddr=0x80100000\0" \
+ "kernel_addr=0x100000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0xa00000\0" \
+ "kernel_load=0x96000000\0" \
+ "kernel_size=0x2800000\0"
+
/*
* USB
*/
#define CONFIG_SYS_FSL_CLK
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
#define CONFIG_SYS_DDR_RAW_TIMING
#endif
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
-#define CONFIG_SYS_HAS_SERDES
-
#define CONFIG_FSL_CAAM /* Enable CAAM */
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
#define CONFIG_CMDLINE_TAG
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_ARMV7_NONSEC
-#define CONFIG_ARMV7_VIRT
#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
#define CONFIG_SYS_FSL_CLK
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DEEP_SLEEP
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_HAS_SERDES
-
#define CONFIG_FSL_CAAM /* Enable CAAM */
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
#define CONFIG_CMDLINE_TAG
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_ARMV7_NONSEC
-#define CONFIG_ARMV7_VIRT
#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
-#define CONFIG_FSL_LSCH2
#define CONFIG_LS1043A
#define CONFIG_MP
#define CONFIG_SYS_FSL_CLK
#define CONFIG_GICV2
#include <asm/arch/config.h>
-#ifdef CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_HAS_SERDES
-#endif
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F 1
-#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
-#endif
-
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#include "ls1043a_common.h"
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_TEXT_BASE 0x82000000
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
-#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
-#endif
#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
-#define CONFIG_SYS_HAS_SERDES
-
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB
#endif
#endif
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_TEXT_BASE 0x82000000
#else
#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
-#define CONFIG_FSL_LSCH2
#define CONFIG_MP
#define CONFIG_SYS_FSL_CLK
#define CONFIG_GICV2
#include <asm/arch/config.h>
-#ifdef CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_HAS_SERDES
-#endif
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
#include "ls1046a_common.h"
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_TEXT_BASE 0x82000000
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
-#define CONFIG_SYS_HAS_SERDES
-
/* DSPI */
#ifdef CONFIG_FSL_DSPI
#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
#endif
#endif
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_TEXT_BASE 0x82000000
#else
#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
-#define CONFIG_FSL_LSCH3
#define CONFIG_MP
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
#include <asm/arch/ls2080a_stream_id.h>
#include <asm/arch/config.h>
-#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
-#define CONFIG_SYS_HAS_SERDES
-#endif
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#endif
#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
#define CONFIG_SYS_DDR_RAW_TIMING
#endif
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
-#define CONFIG_DISPLAY_CPUINFO
-
/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#include "ls2080a_common.h"
-#define CONFIG_DISPLAY_BOARDINFO
-
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#undef CONFIG_CONS_INDEX
#define CONFIG_CONS_INDEX 2
-#define CONFIG_DISPLAY_BOARDINFO
-
#define I2C_MUX_CH_VOL_MONITOR 0xa
#define I2C_VOL_MONITOR_ADDR 0x38
#define CONFIG_VOL_MONITOR_IR36021_READ
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#include <asm/arch/imx-regs.h>
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_REVISION_TAG
#define CONFIG_SYS_NO_FLASH
/*
* U-Boot Commands
*/
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
*/
#define CONFIG_MALTA
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MEMSIZE_IN_BYTES
*/
#define CONFIG_SYS_TEXT_BASE 0x80008000
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#define __CONFIG_H
#define CONFIG_MECP5123 1
-#define CONFIG_DISPLAY_BOARDINFO
/*
* Memory map for the MECP5123 board:
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_MISC_INIT_R /* Call misc_init_r */
-#define CONFIG_DISPLAY_BOARDINFO /* call checkboard() */
-#define CONFIG_DISPLAY_CPUINFO /* display cpu info and speed */
#define CONFIG_PREBOOT /* enable preboot variable */
/*
#define CONFIG_SMSC_LPC47M
#define CONFIG_PCI_PNP
-#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
- "stdout=vga,serial\0" \
- "stderr=vga,serial\0"
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \
+ "stdout=vidconsole,serial\0" \
+ "stderr=vidconsole,serial\0"
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
/* CPU and board */
#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
#define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
#define __CONFIG_H
#define CONFIG_MPC5121ADS 1
-#define CONFIG_DISPLAY_BOARDINFO
/*
* Memory map for the MPC5121ADS board:
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
-#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_CMDLINE_EDITING 1
/*
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
#define CONFIG_BOARD_EARLY_INIT_F /* call board_init_f for early inits */
-#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */
#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_LED
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_VIDEO
#define CONFIG_SYS_TIMER_COUNTER \
(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_DATE
/* High Level Configuration Options */
#define CONFIG_MX31 1 /* This is a mx31 */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_SYS_TEXT_BASE 0xA0000000
#define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS
/* High Level Configuration Options */
#define CONFIG_MX31 /* This is a mx31 */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/* High Level Configuration Options */
#define CONFIG_MX35
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_FSL_CLK
/* Set TEXT at the beginning of the NOR flash */
#define CONFIG_MX51 /* in a mx51 */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_TEXT_BASE 0x97800000
#define CONFIG_MX53
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_MACH_TYPE MACH_TYPE_MX53_ARD
#include <asm/arch/imx-regs.h>
#define CONFIG_MX53
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_MACH_TYPE MACH_TYPE_MX53_EVK
#include <asm/arch/imx-regs.h>
#define CONFIG_MX53
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO
#include <asm/arch/imx-regs.h>
#define CONFIG_MX53
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_MACH_TYPE MACH_TYPE_MX53_SMD
#include <asm/arch/imx-regs.h>
#define CONFIG_MX6
#endif
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_FSL_CLK
/* ATAGs */
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_DISPLAY_CPUINFO
-
#define CONFIG_LOADADDR 0x80800000
#define CONFIG_SYS_TEXT_BASE 0x87800000
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Uncomment to enable secure boot support */
/* #define CONFIG_SECURE_BOOT */
#define CONFIG_CSF_SIZE 0x4000
#include <asm/arch/mem.h>
#include <linux/stringify.h>
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
* High Level Configuration Options
*/
#define CONFIG_MPC5200
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */
#include <configs/ti_omap3_common.h>
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
#define CONFIG_MISC_INIT_R
#define CONFIG_REVISION_TAG 1
#include <configs/ti_omap3_common.h>
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
#define CONFIG_MISC_INIT_R
#define CONFIG_REVISION_TAG 1
*/
#define CONFIG_SYS_LONGHELP
-/* Display CPU and Board information */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE 0x40200000
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
#define CONFIG_MISC_INIT_R
#define CONFIG_REVISION_TAG 1
#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE 0x40200000
-/* Display CPU and Board information */
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_BCH
-/* Display CPU and Board information */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* call misc_init_r */
#define CONFIG_MISC_INIT_R
#include <configs/ti_omap3_common.h>
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
#define CONFIG_MISC_INIT_R
#define CONFIG_REVISION_TAG 1
/* Generic NAND definition conflicts with debug_base */
#undef CONFIG_SYS_NAND_BASE
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
#define CONFIG_MISC_INIT_R
#define CONFIG_REVISION_TAG 1
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#if defined(CONFIG_P1020MBG)
#define CONFIG_BOARDNAME "P1020MBG-PC"
#define CONFIG_P1020
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
#if defined(CONFIG_TWR_P1025)
#define CONFIG_BOARDNAME "TWR-P1025"
#define CONFIG_P1025
#define CONFIG_PB1X00 1
#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
-#define CONFIG_DISPLAY_BOARDINFO
-
#ifdef CONFIG_PB1000
#define CONFIG_SOC_AU1000 1
#else
#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-#define CONFIG_DISPLAY_BOARDINFO 1
-
/*-----------------------------------------------------------------------------
Various low-level settings
-----------------------------------------------------------------------------*/
#define CONFIG_VF610
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#define __CONFIG_H
#define CONFIG_PDM360NG 1
-#define CONFIG_DISPLAY_BOARDINFO
/*
* Memory map for the PDM360NG board:
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_ENV_IS_NOWHERE
-/* Display cpuinfo */
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
#define __PIC32MZDASK_CONFIG_H
/* System Configuration */
-#define CONFIG_DISPLAY_BOARDINFO
/*--------------------------------------------
* CPU configuration
#include "mx6_common.h"
#include <asm/imx-common/gpio.h>
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Network support */
#define CONFIG_FEC_MXC
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#include <asm/hardware.h>
/* ARM asynchronous clock */
-#define CONFIG_DISPLAY_BOARDINFO
-
#define MASTER_PLL_DIV 15
#define MASTER_PLL_MUL 162
#define MAIN_PLL_DIV 2
#include <asm/hardware.h>
/* ARM asynchronous clock */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define MASTER_PLL_DIV 6
#define MASTER_PLL_MUL 65
#ifndef __CONFIG_PXA_COMMON_H__
#define __CONFIG_PXA_COMMON_H__
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
/*
#define CONFIG_QEMU_MIPS
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_R
#define CONFIG_QEMU_MIPS
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_R
#define CONFIG_PCI_PNP
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \
- "stdout=serial,vga\0" \
- "stderr=serial,vga\0"
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
/*
* ATA/SATA support for QEMU x86 targets
#include "siemens-am33x-common.h"
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_MPUCLK 300
#define DDR_PLL_FREQ 303
#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
#undef CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_TMU_TIMER
#undef CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SH_GPIO_PFC
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_THUMB_BUILD
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_THUMB_BUILD
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
#define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_S32V234
#define CONFIG_DM
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Config GIC */
#define CONFIG_GICV2
#define GICD_BASE 0x7D001000
#include <asm/arch/cpu.h> /* get chip and board defs */
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
/* input clock of PLL: has 24MHz input clock at S5PC110 */
#define CONFIG_SYS_CLK_FREQ_C110 24000000
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_VIDEO
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
/* Memory configuration */
#define CONFIG_INITRD_TAG /* pass initrd param to kernel */
#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* U-Boot is loaded by a bootloader */
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
-#define CONFIG_DISPLAY_CPUINFO /* display CPU Info at startup */
/* We set the max number of command args high to avoid HUSH bugs. */
#define CONFIG_SYS_MAXARGS 32
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
-
#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* input clock of PLL: SMDKC100 has 12MHz input clock */
#define CONFIG_SYS_CLK_FREQ 12000000
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_DISPLAY_CPUINFO
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_LONGHELP
/*
* High level configuration
*/
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC8544 1
#define CONFIG_SOCRATES 1
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#define CONFIG_ARCH_EARLY_INIT_R
-#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \
- "stdout=serial,vga\0" \
- "stderr=serial,vga\0"
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x00ff0000
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_PCI_PNP
-#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd,vga\0" \
- "stdout=serial,vga\0" \
- "stderr=serial,vga\0"
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
/* Miscellaneous configurable options */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#endif
/* CPU */
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_TIMER_CLK_FREQ 24000000
/*
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#ifndef __T4QDS_H
#define __T4QDS_H
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_CMD_REGINFO
/* High Level Configuration Options */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#ifndef CONFIG_SPL_BUILD
/* USB gadget mode support*/
+#ifndef CONFIG_TEGRA20
#define CONFIG_CI_UDC_HAS_HOSTPC
+#endif
/* USB mass storage protocol */
#define CONFIG_USB_FUNCTION_MASS_STORAGE
/* DFU protocol */
#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
#endif
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
/* Environment */
#include "siemens-am33x-common.h"
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_MPUCLK 300
#define DDR_PLL_FREQ 303
#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG /* required for ramdisk support */
-#define CONFIG_DISPLAY_CPUINFO
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x81000000\0" \
/* U-Boot Build Configuration */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
/* SoC Configuration */
#define CONFIG_ARCH_CPU_INIT
*/
#define CONFIG_OMAP4430 1 /* which is in a 4430 */
#define CONFIG_MISC_INIT_R
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_SYS_THUMB_BUILD
#ifndef __CONFIG_TI_OMAP5_COMMON_H
#define __CONFIG_TI_OMAP5_COMMON_H
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_798870
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_HZ 1000
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
-/* Display CPU and Board information */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_SILENT_CONSOLE
/* Clock Defines */
/* High Level Configuration Options */
#define CONFIG_MX51
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_SYS_NO_FLASH /* No NOR Flash */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage bootloader */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CONFIG_SMC911X
-
-/* dummy: referenced by examples/standalone/smc911x_eeprom.c */
-#define CONFIG_SMC911X_BASE 0
-#define CONFIG_SMC911X_32_BIT
-
/*-----------------------------------------------------------------------
* MMU and Cache Setting
*----------------------------------------------------------------------*/
/* #define CONFIG_SYS_ICACHE_OFF */
/* #define CONFIG_SYS_DCACHE_OFF */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/* FLASH related */
#define CONFIG_MTD_DEVICE
-/*
- * uncomment the following to disable FLASH related code.
- */
-/* #define CONFIG_SYS_NO_FLASH */
+#define CONFIG_SMC911X_32_BIT
+/* dummy: referenced by examples/standalone/smc911x_eeprom.c */
+#define CONFIG_SMC911X_BASE 0
+
+#ifdef CONFIG_MICRO_SUPPORT_CARD
+#define CONFIG_SMC911X
+#else
+#define CONFIG_SYS_NO_FLASH
+#endif
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_BASE 0
/*
- * flash_toggle does not work for out supoort card.
+ * flash_toggle does not work for our support card.
* We need to use flash_status_poll.
*/
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_DISPLAY_CPUINFO
-
#define CONFIG_SYS_TEXT_BASE 0x23f00000
/*
#define __CONFIG_H
#define CONFIG_MX53
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_FSL_CLK
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MXC_GPIO
*/
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_V38B 1 /* ...on V38B board */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0xFF000000
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */
#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
#define CONFIG_VF610
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_FSL_CLK
#define CONFIG_MACH_TYPE 4146
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* Top level Makefile configuration choices
*/
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_DISPLAY_BOARDINFO
-
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_DISPLAY_CPUINFO
-
/* Only in case the value is not present in mach-types.h */
#ifndef MACH_TYPE_FLEA3
#define MACH_TYPE_FLEA3 3668
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
/*
/* Miscellaneous configurable options */
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \
- "stdout=vga,serial\0" \
- "stderr=vga,serial\0"
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \
+ "stdout=vidconsole,serial\0" \
+ "stderr=vidconsole,serial\0"
#endif
#define CONFIG_ZBOOT_32
#define CONFIG_PHYSMEM
#define CONFIG_DISPLAY_BOARDINFO_LATE
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_NR_DRAM_BANKS 8
/*-----------------------------------------------------------------------
* Video Configuration
*/
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_SW_CURSOR
-#define VIDEO_FB_16BPP_WORD_SWAP
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_CFB_CONSOLE
#define CONFIG_CONSOLE_SCROLL_LINES 5
/*-----------------------------------------------------------------------
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_VIDEO
#define CONFIG_440GX 1 /* 440 GX */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
#define CONFIG_ALTIVEC 1
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0xfff00000
#define CONFIG_SYS_BOARD_NAME "XPedite5200"
#define CONFIG_SYS_FORM_PMC_XMC 1
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
-#define CONFIG_DISPLAY_BOARDINFO
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#define CONFIG_SYS_BOARD_NAME "XPedite5370"
#define CONFIG_SYS_FORM_3U_VPX 1
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
-#define CONFIG_DISPLAY_BOARDINFO
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#define CONFIG_SYS_FORM_PMC_XMC 1
#define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
-#define CONFIG_DISPLAY_BOARDINFO
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfff80000
/* SPL options */
#include "imx6_spl.h"
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (16 << 20)
#undef CONFIG_USE_IRQ /* Keep it simple, poll only */
#define CONFIG_BOARD_POSTCLK_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_R
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_LONGHELP
#define CONFIG_CLOCKS
#define CONFIG_CMD_CLK
uint32_t size);
/**
+ * Read back flash parameters
+ *
+ * This function reads back parameters of the flash as reported by the EC
+ *
+ * @param dev Pointer to device
+ * @param info Pointer to output flash info struct
+ */
+int cros_ec_read_flashinfo(struct cros_ec_dev *dev,
+ struct ec_response_flash_info *info);
+
+/**
* Write data to the flash
*
* Write an arbitrary amount of data to the EC flash, by repeatedly writing
int uclass_get(enum uclass_id key, struct uclass **ucp);
/**
+ * uclass_get_name() - Get the name of a uclass driver
+ *
+ * @id: ID to look up
+ * @returns the name of the uclass driver for that ID, or NULL if none
+ */
+const char *uclass_get_name(enum uclass_id id);
+
+/**
* uclass_get_device() - Get a uclass device based on an ID and index
*
* The device is probed to activate it ready for use.
Elf64_Xword r_info; /* index and type of relocation */
} Elf64_Rel;
+typedef struct {
+ Elf64_Addr r_offset; /* Location at which to apply the action */
+ Elf64_Xword r_info; /* index and type of relocation */
+ Elf64_Sxword r_addend; /* Constant addend used to compute value */
+} Elf64_Rela;
+
/* Extract relocation info - r_info */
#define ELF32_R_SYM(i) ((i) >> 8)
#define ELF32_R_TYPE(i) ((unsigned char) (i))
u32 hp_stat; /* 0x08 SEC_MON_HP Status Register */
};
-#define HPCOMR_SW_SV 0x100 /* Security Violation bit */
-#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */
-#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */
+#define HPCOMR_SW_SV 0x100 /* Security Violation bit */
+#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */
+#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */
+#define HPCOMR_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */
+#define HPCOMR_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */
#define HPSR_SSM_ST_CHECK 0x900 /* SEC_MON is in check state */
#define HPSR_SSM_ST_NON_SECURE 0xb00 /* SEC_MON is in non secure state */
#define HPSR_SSM_ST_TRUST 0xd00 /* SEC_MON is in trusted state */
#define HPSR_SSM_ST_SOFT_FAIL 0x300 /* SEC_MON is in soft fail state */
+#define HPSR_SSM_ST_SECURE 0xf00 /* SEC_MON is in secure state */
#define HPSR_SSM_ST_MASK 0xf00 /* Mask for SSM_ST field */
/*
SEC_MON_SW_SV,
};
-int change_sec_mon_state(uint32_t initial_state, uint32_t final_state);
+/* Transition SEC_MON state */
+int set_sec_mon_state(u32 state);
#endif /* __FSL_SEC_MON_H */
u32 fsl_uid; /* 0xB0 FSL Unique ID */
};
#endif
+
#define ITS_MASK 0x00000004
#define ITS_BIT 2
-#define OSPR_KEY_REVOC_SHIFT 13
-#define OSPR_KEY_REVOC_MASK 0x0000e000
+
+#if defined(CONFIG_SYS_FSL_SFP_VER_3_4)
+#define OSPR_KEY_REVOC_SHIFT 9
+#define OSPR_KEY_REVOC_MASK 0x0000fe00
+#else
+#define OSPR_KEY_REVOC_SHIFT 13
+#define OSPR_KEY_REVOC_MASK 0x0000e000
+#endif /* CONFIG_SYS_FSL_SFP_VER_3_4 */
#endif
list_entry((ptr)->next, type, member)
/**
+ * list_last_entry - get the last element from a list
+ * @ptr: the list head to take the element from.
+ * @type: the type of the struct this is embedded in.
+ * @member: the name of the list_struct within the struct.
+ *
+ * Note, that list is expected to be not empty.
+ */
+#define list_last_entry(ptr, type, member) \
+ list_entry((ptr)->prev, type, member)
+
+/**
* list_for_each - iterate over a list
* @pos: the &struct list_head to use as a loop cursor.
* @head: the head for your list.
int os_dirent_ls(const char *dirname, struct os_dirent_node **headp);
/**
+ * Free directory list
+ *
+ * This frees a linked list containing a directory listing.
+ *
+ * @param node Pointer to head of linked list
+ */
+void os_dirent_free(struct os_dirent_node *node);
+
+/**
* Get the name of a directory entry type
*
- * @param type Type to cehck
+ * @param type Type to check
* @return string containing the name of that type, or "???" if none/invalid
*/
const char *os_dirent_get_typename(enum os_dirent_t type);
#define PCI_DEVICE_ID_INTEL_I960 0x0960
#define PCI_DEVICE_ID_INTEL_I960RM 0x0962
#define PCI_DEVICE_ID_INTEL_CENTERTON_ILB 0x0c60
-#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO 0x0f15
-#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD 0x0f16
+#define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15
+#define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC 0x0f1c
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IDE 0x0f20
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IDE_ALT 0x0f21
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA 0x0f22
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT 0x0f23
+#define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50
#define PCI_DEVICE_ID_INTEL_82541ER 0x1078
#define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c
#define PCI_DEVICE_ID_INTEL_82542 0x1000
--- /dev/null
+#define LP8732 0x0
+#define LP8733 0x1
+
+#define LP873X_LDO_NUM 2
+#define LP873X_BUCK_NUM 2
+
+/* Drivers name */
+#define LP873X_LDO_DRIVER "lp873x_ldo"
+#define LP873X_BUCK_DRIVER "lp873x_buck"
+
+#define LP873X_BUCK_VOLT_MASK 0xFF
+#define LP873X_BUCK_VOLT_MAX_HEX 0xFF
+#define LP873X_BUCK_VOLT_MAX 3360000
+#define LP873X_BUCK_MODE_MASK 0x1
+
+#define LP873X_LDO_VOLT_MASK 0x1F
+#define LP873X_LDO_VOLT_MAX_HEX 0x19
+#define LP873X_LDO_VOLT_MAX 3300000
+#define LP873X_LDO_MODE_MASK 0x1
--- /dev/null
+#define PALMAS 0x0
+#define TPS659038 0x1
+#define TPS65917 0x2
+
+/* I2C device address for pmic palmas */
+#define PALMAS_I2C_ADDR (0x12 >> 1)
+#define PALMAS_LDO_NUM 11
+#define PALMAS_SMPS_NUM 8
+
+/* Drivers name */
+#define PALMAS_LDO_DRIVER "palmas_ldo"
+#define PALMAS_SMPS_DRIVER "palmas_smps"
+
+#define PALMAS_SMPS_VOLT_MASK 0x7F
+#define PALMAS_SMPS_RANGE_MASK 0x80
+#define PALMAS_SMPS_VOLT_MAX_HEX 0x7F
+#define PALMAS_SMPS_VOLT_MAX 3300000
+#define PALMAS_SMPS_MODE_MASK 0x3
+#define PALMAS_SMPS_STATUS_MASK 0x30
+
+#define PALMAS_LDO_VOLT_MASK 0x3F
+#define PALMAS_LDO_VOLT_MAX_HEX 0x3F
+#define PALMAS_LDO_VOLT_MAX 3300000
+#define PALMAS_LDO_MODE_MASK 0x1
+#define PALMAS_LDO_STATUS_MASK 0x10
REGULATOR_TYPE_BUCK,
REGULATOR_TYPE_DVS,
REGULATOR_TYPE_FIXED,
+ REGULATOR_TYPE_GPIO,
REGULATOR_TYPE_OTHER,
};
* TODO(sjg@chromium.org): Consider putting the above two into @flags
* @flags: - flags value (see REGULATOR_FLAG_...)
* @name** - fdt regulator name - should be taken from the device tree
+ * ctrl_reg: - Control register offset used to enable/disable regulator
+ * volt_reg: - register offset for writing voltage vsel values
*
* Note:
* * - set automatically on device probe by the uclass's '.pre_probe' method.
bool boot_on;
const char *name;
int flags;
+ u8 ctrl_reg;
+ u8 volt_reg;
};
/* Regulator device operations */
#include <reset.h>
+struct fdtdec_phandle_args;
struct udevice;
/**
struct graphic_device;
int vbe_get_video_info(struct graphic_device *gdev);
+struct video_priv;
+struct video_uc_platdata;
+int vbe_setup_video_priv(struct vesa_mode_info *vesa,
+ struct video_priv *uc_priv,
+ struct video_uc_platdata *plat);
+int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void));
#endif
if (!end)
end = str + strlen(str);
- for (p = end - 1; p > str; p--) {
- if (!isdigit(*p))
- return simple_strtoul(p + 1, NULL, 10);
+ if (isdigit(end[-1])) {
+ for (p = end - 1; p > str; p--) {
+ if (!isdigit(*p))
+ return simple_strtoul(p + 1, NULL, 10);
+ }
}
return -1;
CONFIG_FSL_LAYERSCAPE
CONFIG_FSL_LBC
CONFIG_FSL_LINFLEXUART
-CONFIG_FSL_LSCH2
-CONFIG_FSL_LSCH3
CONFIG_FSL_LS_PPA
CONFIG_FSL_MC9SDZ60
CONFIG_FSL_MC_ENET
and buildman will find arm-none-eabi-gcc in /usr/bin if you have it installed.
+[toolchain-wrapper]
+wrapper: ccache
+
+This tells buildman to use a compiler wrapper in front of CROSS_COMPILE. In
+this example, ccache. It doesn't affect the toolchain scan. The wrapper is
+added when CROSS_COMPILE environtal variable is set. The name in this
+section is ignored. If more than one line is provided, only the last one
+is taken.
+
3. Make sure you have the require Python pre-requisites
Buildman uses multiprocessing, Queue, shutil, StringIO, ConfigParser and
import re
import Queue
import shutil
+import signal
import string
import sys
+import threading
import time
import builderthread
"""Class for building U-Boot for a particular commit.
Public members: (many should ->private)
- active: True if the builder is active and has not been stopped
already_done: Number of builds already completed
base_dir: Base directory to use for builder
checkout: True to check out source, False to skip that step.
self.base_dir = base_dir
self._working_dir = os.path.join(base_dir, '.bm-work')
self.threads = []
- self.active = True
self.do_make = self.Make
self.gnu_make = gnu_make
self.checkout = checkout
ignore_lines = ['(make.*Waiting for unfinished)', '(Segmentation fault)']
self.re_make_err = re.compile('|'.join(ignore_lines))
+ # Handle existing graceful with SIGINT / Ctrl-C
+ signal.signal(signal.SIGINT, self.signal_handler)
+
def __del__(self):
"""Get rid of all threads created by the builder"""
for t in self.threads:
del t
+ def signal_handler(self, signal, frame):
+ sys.exit(1)
+
def SetDisplayOptions(self, show_errors=False, show_sizes=False,
show_detail=False, show_bloat=False,
list_error_boards=False, show_config=False):
if result:
target = result.brd.target
- if result.return_code < 0:
- self.active = False
- command.StopAll()
- return
-
self.upto += 1
if result.return_code != 0:
self.fail += 1
if os.path.exists(git_dir):
gitutil.Fetch(git_dir, thread_dir)
else:
- Print('Cloning repo for thread %d' % thread_num)
+ Print('\rCloning repo for thread %d' % thread_num,
+ newline=False)
gitutil.Clone(src_dir, thread_dir)
+ Print('\r%s\r' % (' ' * 30), newline=False)
def _PrepareWorkingSpace(self, max_threads, setup_git):
"""Prepare the working directory for use.
for commit_upto in range(self.commit_count):
dir_list.append(self._GetOutputDir(commit_upto))
+ to_remove = []
for dirname in glob.glob(os.path.join(self.base_dir, '*')):
if dirname not in dir_list:
+ to_remove.append(dirname)
+ if to_remove:
+ Print('Removing %d old build directories' % len(to_remove),
+ newline=False)
+ for dirname in to_remove:
shutil.rmtree(dirname)
def BuildBoards(self, commits, board_selected, keep_outputs, verbose):
self._PrepareWorkingSpace(min(self.num_threads, len(board_selected)),
commits is not None)
self._PrepareOutputSpace()
+ Print('\rStarting build...', newline=False)
self.SetupBuild(board_selected, commits)
self.ProcessResult(None)
job.step = self._step
self.queue.put(job)
- # Wait until all jobs are started
- self.queue.join()
+ term = threading.Thread(target=self.queue.join)
+ term.setDaemon(True)
+ term.start()
+ while term.isAlive():
+ term.join(100)
# Wait until we have processed all output
self.out_queue.join()
print >>fd, 'arch', result.toolchain.arch
fd.write('%s' % result.return_code)
- with open(os.path.join(build_dir, 'toolchain'), 'w') as fd:
- print >>fd, 'gcc', result.toolchain.gcc
- print >>fd, 'path', result.toolchain.path
-
# Write out the image and function size information and an objdump
env = result.toolchain.MakeEnvironment(self.builder.full_path)
lines = []
This thread picks a job from the queue, runs it, and then goes to the
next job.
"""
- alive = True
while True:
job = self.builder.queue.get()
- if self.builder.active and alive:
- self.RunJob(job)
- '''
- try:
- if self.builder.active and alive:
- self.RunJob(job)
- except Exception as err:
- alive = False
- print err
- '''
+ self.RunJob(job)
self.builder.queue.task_done()
# Bring in the patman libraries
our_path = os.path.dirname(os.path.realpath(__file__))
-sys.path.append(os.path.join(our_path, '../patman'))
+sys.path.insert(1, os.path.join(our_path, '../patman'))
# Our modules
import board
if line.text.strip():
count += 1
- # We should get one starting message, then an update for every commit
+ # We should get two starting messages, then an update for every commit
# built.
- self.assertEqual(count, len(commits) * len(boards) + 1)
+ self.assertEqual(count, len(commits) * len(boards) + 2)
build.SetDisplayOptions(show_errors=True);
build.ShowSummary(self.commits, board_selected)
#terminal.EchoPrintTestLines()
return PRIORITY_CALC + prio
return PRIORITY_CALC + prio
+ def GetWrapper(self, show_warning=True):
+ """Get toolchain wrapper from the setting file.
+ """
+ value = ''
+ for name, value in bsettings.GetItems('toolchain-wrapper'):
+ if not value:
+ print "Warning: Wrapper not found"
+ if value:
+ value = value + ' '
+
+ return value
+
def MakeEnvironment(self, full_path):
"""Returns an environment for using the toolchain.
PATH
"""
env = dict(os.environ)
+ wrapper = self.GetWrapper()
+
if full_path:
- env['CROSS_COMPILE'] = os.path.join(self.path, self.cross)
+ env['CROSS_COMPILE'] = wrapper + os.path.join(self.path, self.cross)
else:
- env['CROSS_COMPILE'] = self.cross
+ env['CROSS_COMPILE'] = wrapper + self.cross
env['PATH'] = self.path + ':' + env['PATH']
return env
def TabTo(num_tabs, str):
if len(str) >= num_tabs * 8:
return str + ' '
- return str + '\t' * (num_tabs - len(str) / 8)
+ return str + '\t' * (num_tabs - len(str) // 8)
class DtbPlatdata:
"""Provide a means to convert device tree binary data to platform data
fields = {}
# Get a list of all the valid properties in this node.
- for name, prop in node.props.iteritems():
+ for name, prop in node.props.items():
if name not in PROP_IGNORE_LIST and name[0] != '#':
fields[name] = copy.deepcopy(prop)
# If we've seen this node_name before, update the existing struct.
if node_name in structs:
struct = structs[node_name]
- for name, prop in fields.iteritems():
+ for name, prop in fields.items():
oldprop = struct.get(name)
if oldprop:
oldprop.Widen(prop)
for node in self._valid_nodes:
node_name = self.GetCompatName(node)
struct = structs[node_name]
- for name, prop in node.props.iteritems():
+ for name, prop in node.props.items():
if name not in PROP_IGNORE_LIST and name[0] != '#':
prop.Widen(struct[name])
upto += 1
var_name = Conv_name_to_c(node.name)
self.Buf('static struct %s%s %s%s = {\n' %
(STRUCT_PREFIX, struct_name, VAL_PREFIX, var_name))
- for pname, prop in node.props.iteritems():
+ for pname, prop in node.props.items():
if pname in PROP_IGNORE_LIST or pname[0] == '#':
continue
ptype = TYPE_NAMES[prop.type]
This fills in the props and subnodes properties, recursively
searching into subnodes so that the entire tree is built.
"""
- for name, byte_list_str in self._fdt.GetProps(self.path).iteritems():
+ for name, byte_list_str in self._fdt.GetProps(self.path).items():
prop = Prop(self, name, byte_list_str)
self.props[name] = prop
if default is not None:
args += ['-d', str(default)]
if typespec is not None:
- args += ['-t%s' % typespec]
+ args += ['-t', typespec]
out = command.Output('fdtget', *args)
return out.strip()
This fills in the props and subnodes properties, recursively
searching into subnodes so that the entire tree is built.
"""
- self.props = self._fdt.GetProps(self, self.path)
+ self.props = self._fdt.GetProps(self)
offset = libfdt.fdt_first_subnode(self._fdt.GetFdt(), self.Offset())
while offset >= 0:
fdt_len = libfdt.fdt_totalsize(self._fdt)
del self._fdt[fdt_len:]
- def GetProps(self, node, path):
+ def GetProps(self, node):
"""Get all properties from a node.
Args:
Raises:
ValueError: if the node does not exist.
"""
- offset = libfdt.fdt_path_offset(self._fdt, path)
- if offset < 0:
- libfdt.Raise(offset)
props_dict = {}
- poffset = libfdt.fdt_first_property_offset(self._fdt, offset)
+ poffset = libfdt.fdt_first_property_offset(self._fdt, node._offset)
while poffset >= 0:
dprop, plen = libfdt.fdt_get_property_by_offset(self._fdt, poffset)
prop = Prop(node, poffset, libfdt.String(self._fdt, dprop.nameoff),
# SPDX-License-Identifier: GPL-2.0+
#
+import fdt_fallback
+
# Bring in either the normal fdt library (which relies on libfdt) or the
# fallback one (which uses fdtget and is slower). Both provide the same
# interface for this file to use.
have_libfdt = True
except ImportError:
have_libfdt = False
- import fdt_fallback
-def FdtScan(fname):
+force_fallback = False
+
+def FdtScan(fname, _force_fallback=False):
"""Returns a new Fdt object from the implementation we are using"""
- if have_libfdt:
+ if have_libfdt and not force_fallback and not _force_fallback:
dtb = fdt_normal.FdtNormal(fname)
else:
dtb = fdt_fallback.FdtFallback(fname)
dtb.Scan()
return dtb
+
+def UseFallback(fallback):
+ global force_fallback
+
+ old_val = force_fallback
+ force_fallback = fallback
+ return old_val
import os
import struct
+import sys
import tempfile
import command
Return:
A native-endian integer value
"""
+ if sys.version_info > (3, 0):
+ val = val.encode('raw_unicode_escape')
return struct.unpack('>I', val)[0]
def EnsureCompiled(fname):
for line in result.stdout.splitlines():
if verbose:
- print line
+ print(line)
# A blank line indicates the end of a message
if not line and item:
error_count += result.errors
warning_count += result.warnings
check_count += result.checks
- print '%d errors, %d warnings, %d checks for %s:' % (result.errors,
- result.warnings, result.checks, col.Color(col.BLUE, fname))
+ print('%d errors, %d warnings, %d checks for %s:' % (result.errors,
+ result.warnings, result.checks, col.Color(col.BLUE, fname)))
if (len(result.problems) != result.errors + result.warnings +
result.checks):
- print "Internal error: some problems lost"
+ print("Internal error: some problems lost")
for item in result.problems:
- print GetWarningMsg(col, item.get('type', '<unknown>'),
+ print(GetWarningMsg(col, item.get('type', '<unknown>'),
item.get('file', '<unknown>'),
- item.get('line', 0), item.get('msg', 'message'))
+ item.get('line', 0), item.get('msg', 'message')))
print
- #print stdout
+ #print(stdout)
if error_count or warning_count or check_count:
str = 'checkpatch.pl found %d error(s), %d warning(s), %d checks(s)'
color = col.GREEN
color = col.YELLOW
if error_count:
color = col.RED
- print col.Color(color, str % (error_count, warning_count, check_count))
+ print(col.Color(color, str % (error_count, warning_count, check_count)))
return False
return True
try:
last_pipe = cros_subprocess.Popen(cmd, cwd=cwd, **kwargs)
- except Exception, err:
+ except Exception as err:
result.exception = err
if raise_on_error:
raise Exception("Error running '%s': %s" % (user_pipestr, str))
while read_set or write_set:
try:
rlist, wlist, _ = select.select(read_set, write_set, [], 0.2)
- except select.error, e:
+ except select.error as e:
if e.args[0] == errno.EINTR:
continue
raise
get_maintainer = FindGetMaintainer()
if not get_maintainer:
if verbose:
- print "WARNING: Couldn't find get_maintainer.pl"
+ print("WARNING: Couldn't find get_maintainer.pl")
return []
stdout = command.Output(get_maintainer, '--norolestats', fname)
leaf = merge.split('/')[-1]
return '%s/%s' % (remote, leaf), None
else:
- raise ValueError, ("Cannot determine upstream branch for branch "
+ raise ValueError("Cannot determine upstream branch for branch "
"'%s' remote='%s', merge='%s'" % (branch, remote, merge))
result = command.RunPipe([pipe], capture=True, raise_on_error=False,
capture_stderr=True)
if result.return_code != 0:
- raise OSError, 'git checkout (%s): %s' % (pipe, result.stderr)
+ raise OSError('git checkout (%s): %s' % (pipe, result.stderr))
def Clone(git_dir, output_dir):
"""Checkout the selected commit for this build
result = command.RunPipe([pipe], capture=True, cwd=output_dir,
capture_stderr=True)
if result.return_code != 0:
- raise OSError, 'git clone: %s' % result.stderr
+ raise OSError('git clone: %s' % result.stderr)
def Fetch(git_dir=None, work_tree=None):
"""Fetch from the origin repo
pipe.append('fetch')
result = command.RunPipe([pipe], capture=True, capture_stderr=True)
if result.return_code != 0:
- raise OSError, 'git fetch: %s' % result.stderr
+ raise OSError('git fetch: %s' % result.stderr)
def CreatePatches(start, count, series):
"""Create a series of patches from the top of the current branch.
if level > 10:
msg = "Recursive email alias at '%s'" % lookup_name
if raise_on_error:
- raise OSError, msg
+ raise OSError(msg)
else:
- print col.Color(col.RED, msg)
+ print(col.Color(col.RED, msg))
return out_list
if lookup_name:
if not lookup_name in alias:
msg = "Alias '%s' not found" % lookup_name
if raise_on_error:
- raise ValueError, msg
+ raise ValueError(msg)
else:
- print col.Color(col.RED, msg)
+ print(col.Color(col.RED, msg))
return out_list
for item in alias[lookup_name]:
todo = LookupEmail(item, alias, raise_on_error, level + 1)
if not new_item in out_list:
out_list.append(new_item)
- #print "No match for alias '%s'" % lookup_name
+ #print("No match for alias '%s'" % lookup_name)
return out_list
def GetTopLevel():
commit.patch = fname
result = FixPatch(backup_dir, fname, series, commit)
if result:
- print '%d warnings for %s:' % (len(result), fname)
+ print('%d warnings for %s:' % (len(result), fname))
for warn in result:
- print '\t', warn
+ print('\t', warn)
print
count += 1
- print 'Cleaned %d patches' % count
+ print('Cleaned %d patches' % count)
return series
def InsertCoverLetter(fname, series, count):
suite.run(result)
# TODO: Surely we can just 'print' result?
- print result
+ print(result)
for test, err in result.errors:
- print err
+ print(err)
for test, err in result.failures:
- print err
+ print(err)
# Called from git with a patch filename as argument
# Printout a list of additional CC recipients for this patch
for cc in match.group(2).split(', '):
cc = cc.strip()
if cc:
- print cc
+ print(cc)
fd.close()
elif options.full_help:
options.dry_run, not options.ignore_bad_tags, cc_file,
in_reply_to=options.in_reply_to, thread=options.thread)
else:
- print col.Color(col.RED, "Not sending emails due to errors/warnings")
+ print(col.Color(col.RED, "Not sending emails due to errors/warnings"))
# For a dry run, just show our actions as a sanity check
if options.dry_run:
series.ShowActions(args, cmd, options.process_tags)
if not its_a_go:
- print col.Color(col.RED, "Email would not be sent")
+ print(col.Color(col.RED, "Email would not be sent"))
os.remove(cc_file)
# SPDX-License-Identifier: GPL-2.0+
#
+from __future__ import print_function
+
import itertools
import os
cc_set = set(gitutil.BuildEmailList(self.cc));
col = terminal.Color()
- print 'Dry run, so not doing much. But I would do this:'
- print
- print 'Send a total of %d patch%s with %scover letter.' % (
+ print('Dry run, so not doing much. But I would do this:')
+ print()
+ print('Send a total of %d patch%s with %scover letter.' % (
len(args), '' if len(args) == 1 else 'es',
- self.get('cover') and 'a ' or 'no ')
+ self.get('cover') and 'a ' or 'no '))
# TODO: Colour the patches according to whether they passed checks
for upto in range(len(args)):
commit = self.commits[upto]
- print col.Color(col.GREEN, ' %s' % args[upto])
+ print(col.Color(col.GREEN, ' %s' % args[upto]))
cc_list = list(self._generated_cc[commit.patch])
for email in set(cc_list) - to_set - cc_set:
if email == None:
email = col.Color(col.YELLOW, "<alias '%s' not found>"
% tag)
if email:
- print ' Cc: ',email
+ print(' Cc: ', email)
print
for item in to_set:
- print 'To:\t ', item
+ print('To:\t ', item)
for item in cc_set - to_set:
- print 'Cc:\t ', item
- print 'Version: ', self.get('version')
- print 'Prefix:\t ', self.get('prefix')
+ print('Cc:\t ', item)
+ print('Version: ', self.get('version'))
+ print('Prefix:\t ', self.get('prefix'))
if self.cover:
- print 'Cover: %d lines' % len(self.cover)
+ print('Cover: %d lines' % len(self.cover))
cover_cc = gitutil.BuildEmailList(self.get('cover_cc', ''))
all_ccs = itertools.chain(cover_cc, *self._generated_cc.values())
for email in set(all_ccs) - to_set - cc_set:
- print ' Cc: ',email
+ print(' Cc: ', email)
if cmd:
- print 'Git command: %s' % cmd
+ print('Git command: %s' % cmd)
def MakeChangeLog(self, commit):
"""Create a list of changes for each version.
else:
if version > 1:
str = 'Change log missing for v%d' % version
- print col.Color(col.RED, str)
+ print(col.Color(col.RED, str))
for version in changes_copy:
str = 'Change log for unknown version v%d' % version
- print col.Color(col.RED, str)
+ print(col.Color(col.RED, str))
elif self.changes:
str = 'Change log exists, but no version is set'
- print col.Color(col.RED, str)
+ print(col.Color(col.RED, str))
def MakeCcFile(self, process_tags, cover_fname, raise_on_error,
add_maintainers):
raise_on_error=raise_on_error)
list += gitutil.BuildEmailList(commit.cc_list,
raise_on_error=raise_on_error)
- if add_maintainers:
+ if add_maintainers:
list += get_maintainer.GetMaintainer(commit.patch)
all_ccs += list
- print >>fd, commit.patch, ', '.join(set(list))
+ print(commit.patch, ', '.join(set(list)), file=fd)
self._generated_cc[commit.patch] = list
if cover_fname:
cover_cc = gitutil.BuildEmailList(self.get('cover_cc', ''))
- print >>fd, cover_fname, ', '.join(set(cover_cc + all_ccs))
+ print(cover_fname, ', '.join(set(cover_cc + all_ccs)), file=fd)
fd.close()
return fname
"""
git_prefix = gitutil.GetDefaultSubjectPrefix()
if git_prefix:
- git_prefix = '%s][' % git_prefix
+ git_prefix = '%s][' % git_prefix
else:
git_prefix = ''
# SPDX-License-Identifier: GPL-2.0+
#
-import ConfigParser
+from __future__ import print_function
+
+try:
+ import configparser as ConfigParser
+except:
+ import ConfigParser
+
import os
import re
- Merge general default settings/aliases with project-specific ones.
# Sample config used for tests below...
- >>> import StringIO
+ >>> try:
+ ... from StringIO import StringIO
+ ... except ImportError:
+ ... from io import StringIO
>>> sample_config = '''
... [alias]
... me: Peter P. <likesspiders@example.com>
# Check to make sure that bogus project gets general alias.
>>> config = _ProjectConfigParser("zzz")
- >>> config.readfp(StringIO.StringIO(sample_config))
+ >>> config.readfp(StringIO(sample_config))
>>> config.get("alias", "enemies")
'Evil <evil@example.com>'
# Check to make sure that alias gets overridden by project.
>>> config = _ProjectConfigParser("sm")
- >>> config.readfp(StringIO.StringIO(sample_config))
+ >>> config.readfp(StringIO(sample_config))
>>> config.get("alias", "enemies")
'Green G. <ugly@example.com>'
# Check to make sure that settings get merged with project.
>>> config = _ProjectConfigParser("linux")
- >>> config.readfp(StringIO.StringIO(sample_config))
+ >>> config.readfp(StringIO(sample_config))
>>> sorted(config.items("settings"))
[('am_hero', 'True'), ('process_tags', 'False')]
# Check to make sure that settings works with unknown project.
>>> config = _ProjectConfigParser("unknown")
- >>> config.readfp(StringIO.StringIO(sample_config))
+ >>> config.readfp(StringIO(sample_config))
>>> sorted(config.items("settings"))
[('am_hero', 'True')]
"""
if not self.has_section(project_settings):
self.add_section(project_settings)
project_defaults = _default_settings.get(project_name, {})
- for setting_name, setting_value in project_defaults.iteritems():
+ for setting_name, setting_value in project_defaults.items():
self.set(project_settings, setting_name, setting_value)
def get(self, section, option, *args, **kwargs):
try:
fd = open(fname, 'r')
except IOError:
- print "Warning: Cannot find alias file '%s'" % fname
+ print("Warning: Cannot find alias file '%s'" % fname)
return
re_line = re.compile('alias\s+(\S+)\s+(.*)')
m = re_line.match(line)
if not m:
- print "Warning: Alias file line '%s' not understood" % line
+ print("Warning: Alias file line '%s' not understood" % line)
continue
list = alias.get(m.group(1), [])
try:
f = open(config_fname, 'w')
except IOError:
- print "Couldn't create patman config file\n"
+ print("Couldn't create patman config file\n")
raise
- print >>f, "[alias]\nme: %s <%s>" % (name, email)
+ print("[alias]\nme: %s <%s>" % (name, email), file=f)
f.close();
def _UpdateDefaults(parser, config):
val = config.getint('settings', name)
parser.set_default(name, val)
else:
- print "WARNING: Unknown setting %s" % name
+ print("WARNING: Unknown setting %s" % name)
def _ReadAliasFile(fname):
"""Read in the U-Boot git alias file if it exists.
continue
alias[words[1]] = [s.strip() for s in words[2].split(',')]
if bad_line:
- print bad_line
+ print(bad_line)
def Setup(parser, project_name, config_fname=''):
"""Set up the settings module by reading config files.
config_fname = '%s/.patman' % os.getenv('HOME')
if not os.path.exists(config_fname):
- print "No config file found ~/.patman\nCreating one...\n"
+ print("No config file found ~/.patman\nCreating one...\n")
CreatePatmanConfigFile(config_fname)
config.read(config_fname)
This module handles terminal interaction including ANSI color codes.
"""
+from __future__ import print_function
+
import os
import sys
if colour:
col = Color()
text = col.Color(colour, text)
- print text,
+ print(text, end='')
if newline:
- print
+ print()
+ else:
+ sys.stdout.flush()
def SetPrintTestMode():
"""Go into test mode, where all printing is recorded"""
for line in print_test_list:
if line.colour:
col = Color()
- print col.Color(line.colour, line.text),
+ print(col.Color(line.colour, line.text), end='')
else:
- print line.text,
+ print(line.text, end='')
if line.newline:
- print
+ print()
class Color(object):
elif data_type == 'indent':
indent = tab
else:
- print 'not implemented'
+ print('not implemented')
return data % (signoff, tab, indent, tab)
def SetupData(self, data_type):
projects / platform / kernel / u-boot.git / commitdiff