/SPL
/System.map
/u-boot
+/u-boot.elf
/u-boot.hex
/u-boot.imx
/u-boot-with-spl.imx
/errlog
/reloc_off
-/spl/
!/spl/Makefile
+/spl/*
/tpl/
/include/generated/
VERSION = 2014
PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION =
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(obj)u-boot.pbl: $(obj)u-boot.bin
- $(obj)tools/mkimage -n $(CONFIG_PBLRCW_CONFIG) \
- -R $(CONFIG_PBLPBI_CONFIG) -T pblimage \
+ $(obj)tools/mkimage -n $(CONFIG_SYS_FSL_PBL_RCW) \
+ -R $(CONFIG_SYS_FSL_PBL_PBI) -T pblimage \
-d $< $@
$(obj)u-boot.sha1: $(obj)u-boot.bin
Board config to use DDR3. It can be enabled for SoCs with
Freescale DDR3 controllers.
+ CONFIG_SYS_FSL_PBL_PBI
+ It enables addition of RCW (Power on reset configuration) in built image.
+ Please refer doc/README.pblimage for more details
+
+ CONFIG_SYS_FSL_PBL_RCW
+ It adds PBI(pre-boot instructions) commands in u-boot build image.
+ PBI commands can be used to configure SoC before it starts the execution.
+ Please refer doc/README.pblimage for more details
+
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
Define this option to use the Bank addr/Extended addr
support on SPI flashes which has size > 16Mbytes.
+ CONFIG_SF_DUAL_FLASH Dual flash memories
+
+ Define this option to use dual flash support where two flash
+ memories can be connected with a given cs line.
+ currently Xilinx Zynq qspi support these type of connections.
+
- SystemACE Support:
CONFIG_SYSTEMACE
LDFLAGS_FINAL += --gc-sections
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
-fno-common -ffixed-r9
-PLATFORM_RELFLAGS += $(call cc-option, -msoft-float)
+PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
+ $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
# Support generic board on ARM
__HAVE_ARCH_GENERIC_BOARD := y
ifdef CONFIG_ARM64
OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
else
-OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rel.dyn
+OBJCFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
endif
# Make ARMv5 to allow more compilers to work, even though its v6.
PLATFORM_CPPFLAGS += -march=armv5
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
ifneq ($(CONFIG_IMX_CONFIG),)
ifdef CONFIG_SPL
#include <asm/io.h>
#include <asm/arch/mbox.h>
-#define TIMEOUT (100 * 1000) /* 100mS in uS */
+#define TIMEOUT 1000 /* ms */
int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv)
{
#include <asm/io.h>
#include <asm/arch/timer.h>
-int timer_init(void)
-{
- return 0;
-}
-
ulong get_timer_us(ulong base)
{
struct bcm2835_timer_regs *regs =
# Make ARMv5 to allow more compilers to work, even though its v6.
PLATFORM_CPPFLAGS += -march=armv5t
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
- $(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
#
PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
- $(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
#
PLATFORM_CPPFLAGS += -march=armv4
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
#
PLATFORM_CPPFLAGS += -march=armv5te
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
ifneq ($(CONFIG_IMX_CONFIG),)
ifdef CONFIG_SPL
#
PLATFORM_CPPFLAGS += -march=armv4
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
#
PLATFORM_CPPFLAGS += -march=armv4
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5)
PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7)
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
-
# SEE README.arm-unaligned-accesses
PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
--- /dev/null
+#
+# Copyright (C) Albert ARIBAUD <albert.u.boot@aribaud.net>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+SPL_OBJCFLAGS += -j .machine_param
#ifdef CONFIG_SPL_BUILD
ldr r9, =gdata
#else
- sub sp, #GD_SIZE
+ sub sp, sp, #GD_SIZE
bic sp, sp, #7
mov r9, sp
#endif
*/
#include <common.h>
+#include <div64.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/imx-regs.h>
return 0;
}
- return (freq * 18) / ((div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
+ return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
ANATOP_PFD_FRAC_SHIFT(pfd_num));
}
#endif
#ifdef CONFIG_FEC_MXC
-int enable_fec_anatop_clock(void)
+int enable_fec_anatop_clock(enum enet_freq freq)
{
u32 reg = 0;
s32 timeout = 100000;
struct anatop_regs __iomem *anatop =
(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+ if (freq < ENET_25MHz || freq > ENET_125MHz)
+ return -EINVAL;
+
reg = readl(&anatop->pll_enet);
+ reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
+ reg |= freq;
+
if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
(!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
-#define VDDPU_MASK (0x1f << 9)
-
enum ldo_reg {
LDO_ARM,
LDO_SOC,
writew(enable, &wdog2->wmcr);
}
-static void imx_set_vddpu_power_down(void)
-{
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- struct gpc_regs *gpc = (struct gpc_regs *)GPC_BASE_ADDR;
-
- u32 reg;
-
- /*
- * Disable the brown out detection since we are going to be
- * disabling the LDO.
- */
- reg = readl(&anatop->ana_misc2);
- reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN;
- writel(reg, &anatop->ana_misc2);
-
- /* need to power down xPU in GPC before turning off PU LDO */
- reg = readl(&gpc->gpu_ctrl);
- writel(reg | 0x1, &gpc->gpu_ctrl);
-
- reg = readl(&gpc->ctrl);
- writel(reg | 0x1, &gpc->ctrl);
- while (readl(&gpc->ctrl) & 0x1)
- ;
-
- /* Mask the ANATOP brown out interrupt in the GPC. */
- reg = readl(&gpc->imr4);
- reg |= 0x80000000;
- writel(reg, &gpc->imr4);
-
- /* disable VDDPU */
- writel(VDDPU_MASK, &anatop->reg_core_clr);
-
- /* Clear the BO interrupt in the ANATOP. */
- reg = readl(&anatop->ana_misc1);
- reg |= 0x80000000;
- writel(reg, &anatop->ana_misc1);
-}
-
int arch_cpu_init(void)
{
init_aips();
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
- imx_set_vddpu_power_down();
#ifdef CONFIG_APBH_DMA
/* Start APBH DMA */
PLATFORM_LDFLAGS += -EB
USE_PRIVATE_LIBGCC = yes
-
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
#
PLATFORM_CPPFLAGS += -mcpu=xscale
-# =========================================================================
+
#
-# Supply options according to compiler version
+# !WARNING!
+# The PXA's OneNAND SPL uses .text.0 and .text.1 segments to allow booting from
+# really small OneNAND memories where the mmap'd window is only 1KiB big. The
+# .text.0 contains only the bare minimum needed to load the real SPL into SRAM.
+# Add .text.0 and .text.1 into OBJFLAGS, so when the SPL is being objcopy'd,
+# they are not discarded.
#
-# ========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
+
+#ifdef CONFIG_SPL_BUILD
+OBJCFLAGS += -j .text.0 -j .text.1
+#endif
#
PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# ========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
#include <common.h>
#include <SA-1100.h>
-int timer_init (void)
-{
- return 0;
-}
-
ulong get_timer (ulong base)
{
return get_timer_masked ();
}
.dynsym _end : { *(.dynsym) }
- .hash : { *(.hash) }
- .got.plt : { *(.got.plt) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
.interp : { *(.interp*) }
.gnu : { *(.gnu*) }
.ARM.exidx : { *(.ARM.exidx*) }
+ .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
}
#define BOOT_DEVICE_MMC1 7
#define BOOT_DEVICE_MMC2 8
#define BOOT_DEVICE_SPI 10
+#define BOOT_DEVICE_USB 13
#define BOOT_DEVICE_UART 65
#define BOOT_DEVICE_CPGMAC 71
#else
#endif
#define BOOT_DEVICE_MMC2_2 0xFF
-#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
-#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
-#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2
+#if defined(CONFIG_AM33XX)
+#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
+#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2
+#elif defined(CONFIG_AM43XX)
+#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
+#ifdef CONFIG_SPL_USB_SUPPORT
+#define MMC_BOOT_DEVICES_END BOOT_DEVICE_USB
+#else
+#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2
+#endif
#elif defined(CONFIG_TI81XX)
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1
} body;
};
+#define BCM2835_MBOX_POWER_DEVID_SDHCI 0
+#define BCM2835_MBOX_POWER_DEVID_UART0 1
+#define BCM2835_MBOX_POWER_DEVID_UART1 2
+#define BCM2835_MBOX_POWER_DEVID_USB_HCD 3
+#define BCM2835_MBOX_POWER_DEVID_I2C0 4
+#define BCM2835_MBOX_POWER_DEVID_I2C1 5
+#define BCM2835_MBOX_POWER_DEVID_I2C2 6
+#define BCM2835_MBOX_POWER_DEVID_SPI 7
+#define BCM2835_MBOX_POWER_DEVID_CCP2TX 8
+
+#define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 1)
+/* Device doesn't exist */
+#define BCM2835_MBOX_POWER_STATE_RESP_NODEV (1 << 1)
+
+#define BCM2835_MBOX_TAG_GET_POWER_STATE 0x00020001
+
+struct bcm2835_mbox_tag_get_power_state {
+ struct bcm2835_mbox_tag_hdr tag_hdr;
+ union {
+ struct {
+ u32 device_id;
+ } req;
+ struct {
+ u32 device_id;
+ u32 state;
+ } resp;
+ } body;
+};
+
+#define BCM2835_MBOX_TAG_SET_POWER_STATE 0x00028001
+
+#define BCM2835_MBOX_SET_POWER_STATE_REQ_ON (1 << 0)
+#define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT (1 << 1)
+
+struct bcm2835_mbox_tag_set_power_state {
+ struct bcm2835_mbox_tag_hdr tag_hdr;
+ union {
+ struct {
+ u32 device_id;
+ u32 state;
+ } req;
+ struct {
+ u32 device_id;
+ u32 state;
+ } resp;
+ } body;
+};
+
#define BCM2835_MBOX_TAG_GET_CLOCK_RATE 0x00030002
#define BCM2835_MBOX_CLOCK_ID_EMMC 1
#define EHCICTRL_ENAINCR8 (1 << 27)
#define EHCICTRL_ENAINCR16 (1 << 26)
+#define HSIC_CTRL_REFCLKSEL (0x2)
+#define HSIC_CTRL_REFCLKSEL_MASK (0x3)
+#define HSIC_CTRL_REFCLKSEL_SHIFT (23)
+
+#define HSIC_CTRL_REFCLKDIV_12 (0x24)
+#define HSIC_CTRL_REFCLKDIV_MASK (0x7f)
+#define HSIC_CTRL_REFCLKDIV_SHIFT (16)
+
+#define HSIC_CTRL_SIDDQ (0x1 << 6)
+#define HSIC_CTRL_FORCESLEEP (0x1 << 5)
+#define HSIC_CTRL_FORCESUSPEND (0x1 << 4)
+#define HSIC_CTRL_UTMISWRST (0x1 << 2)
+#define HSIC_CTRL_PHYSWRST (0x1 << 0)
+
/* Register map for PHY control */
struct exynos_usb_phy {
unsigned int usbphyctrl0;
MXC_I2C_CLK,
};
+enum enet_freq {
+ ENET_25MHz,
+ ENET_50MHz,
+ ENET_100MHz,
+ ENET_125MHz,
+};
+
u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
int enable_sata_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
void enable_ipu_clock(void);
-int enable_fec_anatop_clock(void);
+int enable_fec_anatop_clock(enum enet_freq freq);
#endif /* __ASM_ARCH_CLOCK_H */
#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
-#define ANADIG_ANA_MISC2_REG1_BO_EN (1 << 13)
#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
u32 gpr10;
};
+/* GPR1 bitfields */
+#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
+#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
+
/* GPR3 bitfields */
#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
u16 wmcr; /* Miscellaneous Control */
};
-struct gpc_regs {
- u32 ctrl; /* 0x000 */
- u32 pgr; /* 0x004 */
- u32 imr1; /* 0x008 */
- u32 imr2; /* 0x00c */
- u32 imr3; /* 0x010 */
- u32 imr4; /* 0x014 */
- u32 isr1; /* 0x018 */
- u32 isr2; /* 0x01c */
- u32 isr3; /* 0x020 */
- u32 isr4; /* 0x024 */
- u32 reserved1[0x86];
- u32 gpu_ctrl; /* 0x260 */
- u32 gpu_pupscr; /* 0x264 */
- u32 gpu_pdnscr; /* 0x268 */
- u32 gpu_sr; /* 0x26c */
- u32 reserved2[0xc];
- u32 cpu_ctrl; /* 0x2a0 */
- u32 cpu_pupscr; /* 0x2a4 */
- u32 cpu_pdnscr; /* 0x2a8 */
- u32 cpu_sr; /* 0x2ac */
-};
-
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
#define DBSC3_1_BASE 0xE67A0000
#define TMU_BASE 0xE61E0000
#define GPIO5_BASE 0xE6055000
+#define SH_QSPI_BASE 0xE6B10000
#define S3C_BASE 0xE6784000
#define S3C_INT_BASE 0xE6784A00
#define DBSC3_1_BASE 0xE67A0000
#define TMU_BASE 0xE61E0000
#define GPIO5_BASE 0xE6055000
+#define SH_QSPI_BASE 0xE6B10000
#define S3C_BASE 0xE6784000
#define S3C_INT_BASE 0xE6784A00
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
#endif
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- sub sp, #GD_SIZE /* allocate one GD above SP */
+ sub sp, sp, #GD_SIZE /* allocate one GD above SP */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
mov r9, sp /* GD is above SP */
mov r0, #0
#
CROSS_COMPILE ?= avr32-linux-
-
+PLATFORM_CPPFLAGS += -DCONFIG_AVR32
CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000
PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax
+++ /dev/null
-/*
- * Register definitions for Parallel Input/Output Controller
- */
-#ifndef __CPU_AT32AP_PIO2_H__
-#define __CPU_AT32AP_PIO2_H__
-
-/* PIO2 register offsets */
-#define PIO2_PER 0x0000
-#define PIO2_PDR 0x0004
-#define PIO2_PSR 0x0008
-#define PIO2_OER 0x0010
-#define PIO2_ODR 0x0014
-#define PIO2_OSR 0x0018
-#define PIO2_IFER 0x0020
-#define PIO2_IFDR 0x0024
-#define PIO2_ISFR 0x0028
-#define PIO2_SODR 0x0030
-#define PIO2_CODR 0x0034
-#define PIO2_ODSR 0x0038
-#define PIO2_PDSR 0x003c
-#define PIO2_IER 0x0040
-#define PIO2_IDR 0x0044
-#define PIO2_IMR 0x0048
-#define PIO2_ISR 0x004c
-#define PIO2_MDER 0x0050
-#define PIO2_MDDR 0x0054
-#define PIO2_MDSR 0x0058
-#define PIO2_PUDR 0x0060
-#define PIO2_PUER 0x0064
-#define PIO2_PUSR 0x0068
-#define PIO2_ASR 0x0070
-#define PIO2_BSR 0x0074
-#define PIO2_ABSR 0x0078
-#define PIO2_OWER 0x00a0
-#define PIO2_OWDR 0x00a4
-#define PIO2_OWSR 0x00a8
-
-/* Register access macros */
-#define pio2_readl(base,reg) \
- readl((void *)base + PIO2_##reg)
-#define pio2_writel(base,reg,value) \
- writel((value), (void *)base + PIO2_##reg)
-
-#endif /* __CPU_AT32AP_PIO2_H__ */
+++ /dev/null
-#ifndef __ASM_AVR32_ARCH_GPIO_IMPL_H__
-#define __ASM_AVR32_ARCH_GPIO_IMPL_H__
-
-/* Register offsets */
-struct gpio_regs {
- u32 GPER;
- u32 GPERS;
- u32 GPERC;
- u32 GPERT;
- u32 PMR0;
- u32 PMR0S;
- u32 PMR0C;
- u32 PMR0T;
- u32 PMR1;
- u32 PMR1S;
- u32 PMR1C;
- u32 PMR1T;
- u32 __reserved0[4];
- u32 ODER;
- u32 ODERS;
- u32 ODERC;
- u32 ODERT;
- u32 OVR;
- u32 OVRS;
- u32 OVRC;
- u32 OVRT;
- u32 PVR;
- u32 __reserved_PVRS;
- u32 __reserved_PVRC;
- u32 __reserved_PVRT;
- u32 PUER;
- u32 PUERS;
- u32 PUERC;
- u32 PUERT;
- u32 PDER;
- u32 PDERS;
- u32 PDERC;
- u32 PDERT;
- u32 IER;
- u32 IERS;
- u32 IERC;
- u32 IERT;
- u32 IMR0;
- u32 IMR0S;
- u32 IMR0C;
- u32 IMR0T;
- u32 IMR1;
- u32 IMR1S;
- u32 IMR1C;
- u32 IMR1T;
- u32 GFER;
- u32 GFERS;
- u32 GFERC;
- u32 GFERT;
- u32 IFR;
- u32 __reserved_IFRS;
- u32 IFRC;
- u32 __reserved_IFRT;
- u32 ODMER;
- u32 ODMERS;
- u32 ODMERC;
- u32 ODMERT;
- u32 __reserved1[4];
- u32 ODCR0;
- u32 ODCR0S;
- u32 ODCR0C;
- u32 ODCR0T;
- u32 ODCR1;
- u32 ODCR1S;
- u32 ODCR1C;
- u32 ODCR1T;
- u32 __reserved2[4];
- u32 OSRR0;
- u32 OSRR0S;
- u32 OSRR0C;
- u32 OSRR0T;
- u32 __reserved3[8];
- u32 STER;
- u32 STERS;
- u32 STERC;
- u32 STERT;
- u32 __reserved4[35];
- u32 VERSION;
-};
-
-#endif /* __ASM_AVR32_ARCH_GPIO_IMPL_H__ */
+++ /dev/null
-/*
- * Copyright (C) 2008 Atmel Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __AVR32_PORTMUX_GPIO_H__
-#define __AVR32_PORTMUX_GPIO_H__
-
-#include <asm/io.h>
-
-/* Register layout for this specific device */
-#include <asm/arch/gpio-impl.h>
-
-/* Register access macros */
-#define gpio_readl(port, reg) \
- __raw_readl(&((struct gpio_regs *)port)->reg)
-#define gpio_writel(gpio, reg, value) \
- __raw_writel(value, &((struct gpio_regs *)port)->reg)
-
-/* Portmux API starts here. See doc/README.AVR32-port-muxing */
-
-enum portmux_function {
- PORTMUX_FUNC_A,
- PORTMUX_FUNC_B,
- PORTMUX_FUNC_C,
- PORTMUX_FUNC_D,
-};
-
-#define PORTMUX_DIR_INPUT (0 << 0)
-#define PORTMUX_DIR_OUTPUT (1 << 0)
-#define PORTMUX_INIT_LOW (0 << 1)
-#define PORTMUX_INIT_HIGH (1 << 1)
-#define PORTMUX_PULL_UP (1 << 2)
-#define PORTMUX_PULL_DOWN (2 << 2)
-#define PORTMUX_BUSKEEPER (3 << 2)
-#define PORTMUX_DRIVE_MIN (0 << 4)
-#define PORTMUX_DRIVE_LOW (1 << 4)
-#define PORTMUX_DRIVE_HIGH (2 << 4)
-#define PORTMUX_DRIVE_MAX (3 << 4)
-#define PORTMUX_OPEN_DRAIN (1 << 6)
-
-void portmux_select_peripheral(void *port, unsigned long pin_mask,
- enum portmux_function func, unsigned long flags);
-void portmux_select_gpio(void *port, unsigned long pin_mask,
- unsigned long flags);
-
-/* Internal helper functions */
-
-static inline void *gpio_pin_to_port(unsigned int pin)
-{
- return (void *)GPIO_BASE + (pin >> 5) * 0x200;
-}
-
-static inline void __gpio_set_output_value(void *port, unsigned int pin,
- int value)
-{
- if (value)
- gpio_writel(port, OVRS, 1 << pin);
- else
- gpio_writel(port, OVRC, 1 << pin);
-}
-
-static inline int __gpio_get_input_value(void *port, unsigned int pin)
-{
- return (gpio_readl(port, PVR) >> pin) & 1;
-}
-
-void gpio_set_output_value(unsigned int pin, int value);
-int gpio_get_input_value(unsigned int pin);
-
-/* GPIO API starts here */
-
-/*
- * GCC doesn't realize that the constant case is extremely trivial,
- * so we need to help it make the right decision by using
- * always_inline.
- */
-__attribute__((always_inline))
-static inline void gpio_set_value(unsigned int pin, int value)
-{
- if (__builtin_constant_p(pin))
- __gpio_set_output_value(gpio_pin_to_port(pin),
- pin & 0x1f, value);
- else
- gpio_set_output_value(pin, value);
-}
-
-__attribute__((always_inline))
-static inline int gpio_get_value(unsigned int pin)
-{
- if (__builtin_constant_p(pin))
- return __gpio_get_input_value(gpio_pin_to_port(pin),
- pin & 0x1f);
- else
- return gpio_get_input_value(pin);
-}
-
-#endif /* __AVR32_PORTMUX_GPIO_H__ */
+++ /dev/null
-/*
- * Lockbox/Security Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_LOCKBOX__
-#define __BFIN_PERIPHERAL_LOCKBOX__
-
-#ifndef __ASSEMBLY__
-
-#include "bootrom.h"
-
-/* SESR argument structure. Expected to reside at 0xFF900018. */
-typedef struct SESR_args {
- unsigned short usFlags; /* security firmware flags */
- unsigned short usIRQMask; /* interrupt mask */
- unsigned long ulMessageSize; /* message length in bytes */
- unsigned long ulSFEntryPoint; /* entry point of secure function */
- unsigned long ulMessagePtr; /* pointer to the buffer containing
- the digital signature and message */
- unsigned long ulReserved1; /* reserved */
- unsigned long ulReserved2; /* reserved */
-} tSESR_args;
-
-/* Secure Entry Service Routine */
-static void (* const sesr)(void) = (void *)_BOOTROM_SESR;
-
-#endif
-
-/* SESR flags argument bitfields */
-#define SESR_FLAGS_STAY_AT_NMI 0x0000
-#define SESR_FLAGS_DROP_BELOW_NMI 0x0001
-#define SESR_FLAGS_NO_SF_DMA 0x0000
-#define SESR_FLAGS_DMA_SF_TO_RUN_DEST 0x0002
-#define SESR_FLAGS_USE_ADI_PUB_KEY 0x0000
-#define SESR_FLAGS_USE_CUST_PUB_KEY 0x0100
-
-/* Bit masks for SECURE_SYSSWT */
-#define EMUDABL 0x00000001 /* Emulation Disable */
-#define RSTDABL 0x00000002 /* Reset Disable */
-#define L1IDABL 0x0000001c /* L1 Instruction Memory Disable */
-#define L1DADABL 0x000000e0 /* L1 Data Bank A Memory Disable */
-#define L1DBDABL 0x00000700 /* L1 Data Bank B Memory Disable */
-#define DMA0OVR 0x00000800 /* DMA0 Memory Access Override */
-#define DMA1OVR 0x00001000 /* DMA1 Memory Access Override */
-#define EMUOVR 0x00004000 /* Emulation Override */
-#define OTPSEN 0x00008000 /* OTP Secrets Enable */
-#define L2DABL 0x00070000 /* L2 Memory Disable */
-
-/* Bit masks for SECURE_CONTROL */
-#define SECURE0 0x0001 /* SECURE 0 */
-#define SECURE1 0x0002 /* SECURE 1 */
-#define SECURE2 0x0004 /* SECURE 2 */
-#define SECURE3 0x0008 /* SECURE 3 */
-
-/* Bit masks for SECURE_STATUS */
-#define SECMODE 0x0003 /* Secured Mode Control State */
-#define NMI 0x0004 /* Non Maskable Interrupt */
-#define AFVALID 0x0008 /* Authentication Firmware Valid */
-#define AFEXIT 0x0010 /* Authentication Firmware Exit */
-#define SECSTAT 0x00e0 /* Secure Status */
-
-#endif
+++ /dev/null
-/*
- * SPORT Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_SPORT__
-#define __BFIN_PERIPHERAL_SPORT__
-
-/* SPORTx_TCR1 Masks */
-#define TSPEN 0x0001 /* TX enable */
-#define ITCLK 0x0002 /* Internal TX Clock Select */
-#define TDTYPE 0x000C /* TX Data Formatting Select */
-#define DTYPE_NORM 0x0004 /* Data Format Normal */
-#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
-#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
-#define TLSBIT 0x0010 /* TX Bit Order */
-#define ITFS 0x0200 /* Internal TX Frame Sync Select */
-#define TFSR 0x0400 /* TX Frame Sync Required Select */
-#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
-#define LTFS 0x1000 /* Low TX Frame Sync Select */
-#define LATFS 0x2000 /* Late TX Frame Sync Select */
-#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
-
-/* SPORTx_TCR2 Masks */
-#define SLEN 0x001F /* TX Word Length */
-#define TXSE 0x0100 /* TX Secondary Enable */
-#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */
-#define TRFST 0x0400 /* TX Right-First Data Order */
-
-/* SPORTx_RCR1 Masks */
-#define RSPEN 0x0001 /* RX enable */
-#define IRCLK 0x0002 /* Internal RX Clock Select */
-#define RDTYPE 0x000C /* RX Data Formatting Select */
-#define DTYPE_NORM 0x0004 /* Data Format Normal */
-#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
-#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
-#define RLSBIT 0x0010 /* RX Bit Order */
-#define IRFS 0x0200 /* Internal RX Frame Sync Select */
-#define RFSR 0x0400 /* RX Frame Sync Required Select */
-#define LRFS 0x1000 /* Low RX Frame Sync Select */
-#define LARFS 0x2000 /* Late RX Frame Sync Select */
-#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
-
-/* SPORTx_RCR2 Masks */
-#define SLEN 0x001F /* RX Word Length */
-#define RXSE 0x0100 /* RX Secondary Enable */
-#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
-#define RRFST 0x0400 /* Right-First Data Order */
-
-/* SPORTx_STAT Masks */
-#define RXNE 0x0001 /* RX FIFO Not Empty Status */
-#define RUVF 0x0002 /* RX Underflow Status */
-#define ROVF 0x0004 /* RX Overflow Status */
-#define TXF 0x0008 /* TX FIFO Full Status */
-#define TUVF 0x0010 /* TX Underflow Status */
-#define TOVF 0x0020 /* TX Overflow Status */
-#define TXHRE 0x0040 /* TX Hold Register Empty */
-
-/* SPORTx_MCMC1 Masks */
-#define WSIZE 0xF000 /* Multichannel Window Size Field */
-#define WOFF 0x03FF /* Multichannel Window Offset Field */
-
-/* SPORTx_MCMC2 Masks */
-#define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */
-#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
-#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
-#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
-#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
-#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
-#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
-#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
-#define MFD 0xF000 /* Multichannel Frame Delay */
-#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
-#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
-#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
-#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
-#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
-#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
-#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
-#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
-#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
-#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
-#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
-#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
-#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
-#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
-#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
-#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
-
-#endif
#include <mpc5xx.h>
#include <version.h>
-#define CONFIG_5xx 1 /* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <mpc5xxx.h>
#include <version.h>
-#define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
+++ /dev/null
-#ifndef I2C_EXPORT_H
-#define I2C_EXPORT_H
-
-/****************************************************
- *
- * Copyright Motrola 1999
- *
- ****************************************************/
-
-/* These are the defined return values for the I2C_do_transaction function.
- * Any non-zero value indicates failure. Failure modes can be added for
- * more detailed error reporting.
- */
-typedef enum _i2c_status
-{
- I2C_SUCCESS = 0,
- I2C_ERROR,
-} I2C_Status;
-
-/* These are the defined tasks for I2C_do_transaction.
- * Modes for SLAVE_RCV and SLAVE_XMIT will be added.
- */
-typedef enum _i2c_transaction_mode
-{
- I2C_MASTER_RCV = 0,
- I2C_MASTER_XMIT = 1,
-} I2C_TRANSACTION_MODE;
-
-typedef enum _i2c_interrupt_mode
-{
- I2C_INT_DISABLE = 0,
- I2C_INT_ENABLE = 1,
-} I2C_INTERRUPT_MODE;
-
-typedef enum _i2c_stop
-{
- I2C_NO_STOP = 0,
- I2C_STOP = 1,
-} I2C_STOP_MODE;
-
-typedef enum _i2c_restart
-{
- I2C_NO_RESTART = 0,
- I2C_RESTART = 1,
-} I2C_RESTART_MODE;
-
-/******************** App. API ********************
- * The application API is for user level application
- * to use the functionality provided by I2C driver.
- * This is a "generic" I2C interface, it should contain
- * nothing specific to the Kahlua implementation.
- * Only the generic functions are exported by the library.
- *
- * Note: Its App.s responsibility to swap the data
- * byte. In our API, we just transfer whatever
- * we are given
- **************************************************/
-
-
-/* Initialize I2C unit with the following:
- * driver's slave address
- * interrupt enabled
- * optional pointer to application layer print function
- *
- * These parameters may be added:
- * desired clock rate
- * digital filter frequency sampling rate
- *
- * This function must be called before I2C unit can be used.
- */
-extern I2C_Status I2C_Initialize(
- unsigned char addr, /* driver's I2C slave address */
- I2C_INTERRUPT_MODE en_int, /* 1 - enable I2C interrupt
- * 0 - disable I2C interrupt
- */
- int (*app_print_function)(char *,...)); /* pointer to optional "printf"
- * provided by application
- */
-
-/* Perform the given I2C transaction, only MASTER_XMIT and MASTER_RCV
- * are implemented. Both are only in polling mode.
- *
- * en_int controls interrupt/polling mode
- * act is the type of transaction
- * addr is the I2C address of the slave device
- * len is the length of data to send or receive
- * buffer is the address of the data buffer
- * stop = I2C_NO_STOP, don't signal STOP at end of transaction
- * I2C_STOP, signal STOP at end of transaction
- * retry is the timeout retry value, currently ignored
- * rsta = I2C_NO_RESTART, this is not continuation of existing transaction
- * I2C_RESTART, this is a continuation of existing transaction
- */
-extern I2C_Status I2C_do_transaction( I2C_INTERRUPT_MODE en_int,
- I2C_TRANSACTION_MODE act,
- unsigned char i2c_addr,
- unsigned char data_addr,
- int len,
- char *buffer,
- I2C_STOP_MODE stop,
- int retry,
- I2C_RESTART_MODE rsta);
-#endif
#include <mpc824x.h>
#include <version.h>
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <version.h>
#define CONFIG_8260 1 /* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*-----------------------------------------------------------------------
- * Timer value for timer 2, ICLK = 10
- *
- * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1))
- * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
- *
- * SPEED_FCOUNT2 timer 2 counting frequency
- * GCLK CPU clock
- * SPEED_TMR2_PS prescaler
- */
-#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */
-
-/*-----------------------------------------------------------------------
- * Timer value for PIT
- *
- * PIT_TIME = SPEED_PITC / PITRTCLK
- * PITRTCLK = 8192
- */
-#define SPEED_PITC (82 << 16) /* start counting from 82 */
-
-/*
- * The new value for PTA is calculated from
- *
- * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock !)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- * DFBRG For normal mode (no clock reduction) always 0
- * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
- * NCS Number of SDRAM banks (chip selects) on this UPM.
- */
#include <version.h>
#define CONFIG_8260 1 /* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <version.h>
#define CONFIG_83XX 1 /* needed for Linux kernel header files*/
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
mtspr SRR1, r3
rfi
+ .globl get_svr
+get_svr:
+ mfspr r3, SVR
+ blr
+
.globl get_pvr
get_pvr:
mfspr r3, PVR
puts("Work-around for Erratum CPU-A003999 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
- puts("Work-around for Erratum DDR-A003473 enabled\n");
+ puts("Work-around for Erratum DDR-A003474 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
# SPDX-License-Identifier: GPL-2.0+
#
-PLATFORM_CPPFLAGS += -Wa,-me500 -msoft-float -mno-string
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -Wa,-me500 -msoft-float -mno-string
# -mspe=yes is needed to have -mno-spe accepted by a buggy GCC;
# see "[PATCH,rs6000] make -mno-spe work as expected" on
#include <mpc85xx.h>
#include <version.h>
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <mpc85xx.h>
#include <version.h>
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
. = ALIGN(8);
__init_begin = .;
__init_end = .;
-/* FIXME for non-NAND SPL */
+
+/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+ .bootpg ADDR(.text) - 0x1000 :
+ {
+ KEEP(*(.bootpg))
+ } :text = 0xffff
+#else
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
.bootpg ADDR(.text) + 0x1000 :
{
#else
#error unknown NAND controller
#endif
-#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
- .bootpg ADDR(.text) - 0x1000 :
- {
- KEEP(*(.bootpg))
- } :text = 0xffff
-#else
.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
KEEP(*(.resetvec))
} = 0xffff
# SPDX-License-Identifier: GPL-2.0+
#
-PLATFORM_CPPFLAGS += -mstring -maltivec -mabi=altivec -msoft-float
+PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -mstring -maltivec -mabi=altivec -msoft-float
#include <mpc8xx.h>
#include <version.h>
-#define CONFIG_8xx 1 /* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <mpc8xx.h>
#include <version.h>
-#define CONFIG_8xx 1 /* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/ppc4xx.h>
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <version.h>
#define CONFIG_405GP 1 /* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/ppc4xx.h>
#include <version.h>
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
+#define CONFIG_ESDHC_HC_BLK_ADDR
/* P1011 is single core version of P1020 */
#elif defined(CONFIG_P1011)
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_BSC9132)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
+#define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
#define CONFIG_E6500
{
u32 svr = get_svr();
if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) ||
- ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2))
+ ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) ||
+ ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) ||
+ ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) ||
+ ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) ||
+ ((SVR_SOC_VER(svr) == SVR_T2081) && SVR_MAJ(svr) <= 1))
return true;
return false;
+++ /dev/null
-/*
- * MPC85xx I/O port pin manipulation functions
- */
-
-#ifndef _ASM_IOPIN_85xx_H_
-#define _ASM_IOPIN_85xx_H_
-
-#include <linux/types.h>
-#include <asm/immap_85xx.h>
-
-#ifdef __KERNEL__
-
-typedef struct {
- u_char port:2; /* port number (A=0, B=1, C=2, D=3) */
- u_char pin:5; /* port pin (0-31) */
- u_char flag:1; /* for whatever */
-} iopin_t;
-
-#define IOPIN_PORTA 0
-#define IOPIN_PORTB 1
-#define IOPIN_PORTC 2
-#define IOPIN_PORTD 3
-
-extern __inline__ void iopin_set_high (iopin_t * iopin)
-{
- volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
- datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-extern __inline__ void iopin_set_low (iopin_t * iopin)
-{
- volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
- datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-extern __inline__ uint iopin_is_high (iopin_t * iopin)
-{
- volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
- return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-extern __inline__ uint iopin_is_low (iopin_t * iopin)
-{
- volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
- return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-extern __inline__ void iopin_set_out (iopin_t * iopin)
-{
- volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
- dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-extern __inline__ void iopin_set_in (iopin_t * iopin)
-{
- volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
- dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-extern __inline__ uint iopin_is_out (iopin_t * iopin)
-{
- volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
- return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-extern __inline__ uint iopin_is_in (iopin_t * iopin)
-{
- volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
- return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-extern __inline__ void iopin_set_odr (iopin_t * iopin)
-{
- volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
- odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-extern __inline__ void iopin_set_act (iopin_t * iopin)
-{
- volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
- odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-extern __inline__ uint iopin_is_odr (iopin_t * iopin)
-{
- volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
- return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-extern __inline__ uint iopin_is_act (iopin_t * iopin)
-{
- volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
- return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-extern __inline__ void iopin_set_ded (iopin_t * iopin)
-{
- volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
- parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-extern __inline__ void iopin_set_gen (iopin_t * iopin)
-{
- volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
- parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-extern __inline__ uint iopin_is_ded (iopin_t * iopin)
-{
- volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
- return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-extern __inline__ uint iopin_is_gen (iopin_t * iopin)
-{
- volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
- return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-extern __inline__ void iopin_set_opt2 (iopin_t * iopin)
-{
- volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
- sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-extern __inline__ void iopin_set_opt1 (iopin_t * iopin)
-{
- volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
- sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-extern __inline__ uint iopin_is_opt2 (iopin_t * iopin)
-{
- volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
- return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-extern __inline__ uint iopin_is_opt1 (iopin_t * iopin)
-{
- volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
- return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_IOPIN_85xx_H_ */
+++ /dev/null
-/* 11/02/95 */
-/*----------------------------------------------------------------------------*/
-/* Plug and Play header definitions */
-/*----------------------------------------------------------------------------*/
-
-/* Structure map for PnP on PowerPC Reference Platform */
-/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993. It */
-/* (or later versions) is available on Compuserve in the PLUGPLAY area. */
-/* This code has extensions to that specification, namely new short and */
-/* long tag types for platform dependent information */
-
-/* Warning: LE notation used throughout this file */
-
-/* For enum's: if given in hex then they are bit significant, i.e. */
-/* only one bit is on for each enum */
-
-#ifndef _PNP_
-#define _PNP_
-
-#ifndef __ASSEMBLY__
-#define MAX_MEM_REGISTERS 9
-#define MAX_IO_PORTS 20
-#define MAX_IRQS 7
-/*#define MAX_DMA_CHANNELS 7*/
-
-/* Interrupt controllers */
-
-#define PNPinterrupt0 "PNP0000" /* AT Interrupt Controller */
-#define PNPinterrupt1 "PNP0001" /* EISA Interrupt Controller */
-#define PNPinterrupt2 "PNP0002" /* MCA Interrupt Controller */
-#define PNPinterrupt3 "PNP0003" /* APIC */
-#define PNPExtInt "IBM000D" /* PowerPC Extended Interrupt Controller */
-
-/* Timers */
-
-#define PNPtimer0 "PNP0100" /* AT Timer */
-#define PNPtimer1 "PNP0101" /* EISA Timer */
-#define PNPtimer2 "PNP0102" /* MCA Timer */
-
-/* DMA controllers */
-
-#define PNPdma0 "PNP0200" /* AT DMA Controller */
-#define PNPdma1 "PNP0201" /* EISA DMA Controller */
-#define PNPdma2 "PNP0202" /* MCA DMA Controller */
-
-/* start of August 15, 1994 additions */
-/* CMOS */
-#define PNPCMOS "IBM0009" /* CMOS */
-
-/* L2 Cache */
-#define PNPL2 "IBM0007" /* L2 Cache */
-
-/* NVRAM */
-#define PNPNVRAM "IBM0008" /* NVRAM */
-
-/* Power Management */
-#define PNPPM "IBM0005" /* Power Management */
-/* end of August 15, 1994 additions */
-
-/* Keyboards */
-
-#define PNPkeyboard0 "PNP0300" /* IBM PC/XT KB Cntlr (83 key, no mouse) */
-#define PNPkeyboard1 "PNP0301" /* Olivetti ICO (102 key) */
-#define PNPkeyboard2 "PNP0302" /* IBM PC/AT KB Cntlr (84 key) */
-#define PNPkeyboard3 "PNP0303" /* IBM Enhanced (101/2 key, PS/2 mouse) */
-#define PNPkeyboard4 "PNP0304" /* Nokia 1050 KB Cntlr */
-#define PNPkeyboard5 "PNP0305" /* Nokia 9140 KB Cntlr */
-#define PNPkeyboard6 "PNP0306" /* Standard Japanese KB Cntlr */
-#define PNPkeyboard7 "PNP0307" /* Microsoft Windows (R) KB Cntlr */
-
-/* Parallel port controllers */
-
-#define PNPparallel0 "PNP0400" /* Standard LPT Parallel Port */
-#define PNPparallel1 "PNP0401" /* ECP Parallel Port */
-#define PNPepp "IBM001C" /* EPP Parallel Port */
-
-/* Serial port controllers */
-
-#define PNPserial0 "PNP0500" /* Standard PC Serial port */
-#define PNPSerial1 "PNP0501" /* 16550A Compatible Serial port */
-
-/* Disk controllers */
-
-#define PNPdisk0 "PNP0600" /* Generic ESDI/IDE/ATA Compat HD Cntlr */
-#define PNPdisk1 "PNP0601" /* Plus Hardcard II */
-#define PNPdisk2 "PNP0602" /* Plus Hardcard IIXL/EZ */
-
-/* Diskette controllers */
-
-#define PNPdiskette0 "PNP0700" /* PC Standard Floppy Disk Controller */
-
-/* Display controllers */
-
-#define PNPdisplay0 "PNP0900" /* VGA Compatible */
-#define PNPdisplay1 "PNP0901" /* Video Seven VGA */
-#define PNPdisplay2 "PNP0902" /* 8514/A Compatible */
-#define PNPdisplay3 "PNP0903" /* Trident VGA */
-#define PNPdisplay4 "PNP0904" /* Cirrus Logic Laptop VGA */
-#define PNPdisplay5 "PNP0905" /* Cirrus Logic VGA */
-#define PNPdisplay6 "PNP0906" /* Tseng ET4000 or ET4000/W32 */
-#define PNPdisplay7 "PNP0907" /* Western Digital VGA */
-#define PNPdisplay8 "PNP0908" /* Western Digital Laptop VGA */
-#define PNPdisplay9 "PNP0909" /* S3 */
-#define PNPdisplayA "PNP090A" /* ATI Ultra Pro/Plus (Mach 32) */
-#define PNPdisplayB "PNP090B" /* ATI Ultra (Mach 8) */
-#define PNPdisplayC "PNP090C" /* XGA Compatible */
-#define PNPdisplayD "PNP090D" /* ATI VGA Wonder */
-#define PNPdisplayE "PNP090E" /* Weitek P9000 Graphics Adapter */
-#define PNPdisplayF "PNP090F" /* Oak Technology VGA */
-
-/* Peripheral busses */
-
-#define PNPbuses0 "PNP0A00" /* ISA Bus */
-#define PNPbuses1 "PNP0A01" /* EISA Bus */
-#define PNPbuses2 "PNP0A02" /* MCA Bus */
-#define PNPbuses3 "PNP0A03" /* PCI Bus */
-#define PNPbuses4 "PNP0A04" /* VESA/VL Bus */
-
-/* RTC, BIOS, planar devices */
-
-#define PNPspeaker0 "PNP0800" /* AT Style Speaker Sound */
-#define PNPrtc0 "PNP0B00" /* AT RTC */
-#define PNPpnpbios0 "PNP0C00" /* PNP BIOS (only created by root enum) */
-#define PNPpnpbios1 "PNP0C01" /* System Board Memory Device */
-#define PNPpnpbios2 "PNP0C02" /* Math Coprocessor */
-#define PNPpnpbios3 "PNP0C03" /* PNP BIOS Event Notification Interrupt */
-
-/* PCMCIA controller */
-
-#define PNPpcmcia0 "PNP0E00" /* Intel 82365 Compatible PCMCIA Cntlr */
-
-/* Mice */
-
-#define PNPmouse0 "PNP0F00" /* Microsoft Bus Mouse */
-#define PNPmouse1 "PNP0F01" /* Microsoft Serial Mouse */
-#define PNPmouse2 "PNP0F02" /* Microsoft Inport Mouse */
-#define PNPmouse3 "PNP0F03" /* Microsoft PS/2 Mouse */
-#define PNPmouse4 "PNP0F04" /* Mousesystems Mouse */
-#define PNPmouse5 "PNP0F05" /* Mousesystems 3 Button Mouse - COM2 */
-#define PNPmouse6 "PNP0F06" /* Genius Mouse - COM1 */
-#define PNPmouse7 "PNP0F07" /* Genius Mouse - COM2 */
-#define PNPmouse8 "PNP0F08" /* Logitech Serial Mouse */
-#define PNPmouse9 "PNP0F09" /* Microsoft Ballpoint Serial Mouse */
-#define PNPmouseA "PNP0F0A" /* Microsoft PNP Mouse */
-#define PNPmouseB "PNP0F0B" /* Microsoft PNP Ballpoint Mouse */
-
-/* Modems */
-
-#define PNPmodem0 "PNP9000" /* Specific IDs TBD */
-
-/* Network controllers */
-
-#define PNPnetworkC9 "PNP80C9" /* IBM Token Ring */
-#define PNPnetworkCA "PNP80CA" /* IBM Token Ring II */
-#define PNPnetworkCB "PNP80CB" /* IBM Token Ring II/Short */
-#define PNPnetworkCC "PNP80CC" /* IBM Token Ring 4/16Mbs */
-#define PNPnetwork27 "PNP8327" /* IBM Token Ring (All types) */
-#define PNPnetworket "IBM0010" /* IBM Ethernet used by Power PC */
-#define PNPneteisaet "IBM2001" /* IBM Ethernet EISA adapter */
-#define PNPAMD79C970 "IBM0016" /* AMD 79C970 (PCI Ethernet) */
-
-/* SCSI controllers */
-
-#define PNPscsi0 "PNPA000" /* Adaptec 154x Compatible SCSI Cntlr */
-#define PNPscsi1 "PNPA001" /* Adaptec 174x Compatible SCSI Cntlr */
-#define PNPscsi2 "PNPA002" /* Future Domain 16-700 Compat SCSI Cntlr*/
-#define PNPscsi3 "PNPA003" /* Panasonic CDROM Adapter (SBPro/SB16) */
-#define PNPscsiF "IBM000F" /* NCR 810 SCSI Controller */
-#define PNPscsi825 "IBM001B" /* NCR 825 SCSI Controller */
-#define PNPscsi875 "IBM0018" /* NCR 875 SCSI Controller */
-
-/* Sound/Video, Multimedia */
-
-#define PNPmm0 "PNPB000" /* Sound Blaster Compatible Sound Device */
-#define PNPmm1 "PNPB001" /* MS Windows Sound System Compat Device */
-#define PNPmmF "IBM000E" /* Crystal CS4231 Audio Device */
-#define PNPv7310 "IBM0015" /* ASCII V7310 Video Capture Device */
-#define PNPmm4232 "IBM0017" /* Crystal CS4232 Audio Device */
-#define PNPpmsyn "IBM001D" /* YMF 289B chip (Yamaha) */
-#define PNPgp4232 "IBM0012" /* Crystal CS4232 Game Port */
-#define PNPmidi4232 "IBM0013" /* Crystal CS4232 MIDI */
-
-/* Operator Panel */
-#define PNPopctl "IBM000B" /* Operator's panel */
-
-/* Service Processor */
-#define PNPsp "IBM0011" /* IBM Service Processor */
-#define PNPLTsp "IBM001E" /* Lightning/Terlingua Support Processor */
-#define PNPLTmsp "IBM001F" /* Lightning/Terlingua Mini-SP */
-
-/* Memory Controller */
-#define PNPmemctl "IBM000A" /* Memory controller */
-
-/* Graphics Assist */
-#define PNPg_assist "IBM0014" /* Graphics Assist */
-
-/* Miscellaneous Device Controllers */
-#define PNPtablet "IBM0019" /* IBM Tablet Controller */
-
-/* PNP Packet Handles */
-
-#define S1_Packet 0x0A /* Version resource */
-#define S2_Packet 0x15 /* Logical DEVID (without flags) */
-#define S2_Packet_flags 0x16 /* Logical DEVID (with flags) */
-#define S3_Packet 0x1C /* Compatible device ID */
-#define S4_Packet 0x22 /* IRQ resource (without flags) */
-#define S4_Packet_flags 0x23 /* IRQ resource (with flags) */
-#define S5_Packet 0x2A /* DMA resource */
-#define S6_Packet 0x30 /* Depend funct start (w/o priority) */
-#define S6_Packet_priority 0x31 /* Depend funct start (w/ priority) */
-#define S7_Packet 0x38 /* Depend funct end */
-#define S8_Packet 0x47 /* I/O port resource (w/o fixed loc) */
-#define S9_Packet_fixed 0x4B /* I/O port resource (w/ fixed loc) */
-#define S14_Packet 0x71 /* Vendor defined */
-#define S15_Packet 0x78 /* End of resource (w/o checksum) */
-#define S15_Packet_checksum 0x79 /* End of resource (w/ checksum) */
-#define L1_Packet 0x81 /* Memory range */
-#define L1_Shadow 0x20 /* Memory is shadowable */
-#define L1_32bit_mem 0x18 /* 32-bit memory only */
-#define L1_8_16bit_mem 0x10 /* 8- and 16-bit supported */
-#define L1_Decode_Hi 0x04 /* decode supports high address */
-#define L1_Cache 0x02 /* read cacheable, write-through */
-#define L1_Writeable 0x01 /* Memory is writeable */
-#define L2_Packet 0x82 /* ANSI ID string */
-#define L3_Packet 0x83 /* Unicode ID string */
-#define L4_Packet 0x84 /* Vendor defined */
-#define L5_Packet 0x85 /* Large I/O */
-#define L6_Packet 0x86 /* 32-bit Fixed Loc Mem Range Desc */
-#define END_TAG 0x78 /* End of resource */
-#define DF_START_TAG 0x30 /* Dependent function start */
-#define DF_START_TAG_priority 0x31 /* Dependent function start */
-#define DF_END_TAG 0x38 /* Dependent function end */
-#define SUBOPTIMAL_CONFIGURATION 0x2 /* Priority byte sub optimal config */
-
-/* Device Base Type Codes */
-
-typedef enum _PnP_BASE_TYPE {
- Reserved = 0,
- MassStorageDevice = 1,
- NetworkInterfaceController = 2,
- DisplayController = 3,
- MultimediaController = 4,
- MemoryController = 5,
- BridgeController = 6,
- CommunicationsDevice = 7,
- SystemPeripheral = 8,
- InputDevice = 9,
- ServiceProcessor = 0x0A, /* 11/2/95 */
- } PnP_BASE_TYPE;
-
-/* Device Sub Type Codes */
-
-typedef enum _PnP_SUB_TYPE {
- SCSIController = 0,
- IDEController = 1,
- FloppyController = 2,
- IPIController = 3,
- OtherMassStorageController = 0x80,
-
- EthernetController = 0,
- TokenRingController = 1,
- FDDIController = 2,
- OtherNetworkController = 0x80,
-
- VGAController= 0,
- SVGAController= 1,
- XGAController= 2,
- OtherDisplayController = 0x80,
-
- VideoController = 0,
- AudioController = 1,
- OtherMultimediaController = 0x80,
-
- RAM = 0,
- FLASH = 1,
- OtherMemoryDevice = 0x80,
-
- HostProcessorBridge = 0,
- ISABridge = 1,
- EISABridge = 2,
- MicroChannelBridge = 3,
- PCIBridge = 4,
- PCMCIABridge = 5,
- VMEBridge = 6,
- OtherBridgeDevice = 0x80,
-
- RS232Device = 0,
- ATCompatibleParallelPort = 1,
- OtherCommunicationsDevice = 0x80,
-
- ProgrammableInterruptController = 0,
- DMAController = 1,
- SystemTimer = 2,
- RealTimeClock = 3,
- L2Cache = 4,
- NVRAM = 5,
- PowerManagement = 6,
- CMOS = 7,
- OperatorPanel = 8,
- ServiceProcessorClass1 = 9,
- ServiceProcessorClass2 = 0xA,
- ServiceProcessorClass3 = 0xB,
- GraphicAssist = 0xC,
- SystemPlanar = 0xF, /* 10/5/95 */
- OtherSystemPeripheral = 0x80,
-
- KeyboardController = 0,
- Digitizer = 1,
- MouseController = 2,
- TabletController = 3, /* 10/27/95 */
- OtherInputController = 0x80,
-
- GeneralMemoryController = 0,
- } PnP_SUB_TYPE;
-
-/* Device Interface Type Codes */
-
-typedef enum _PnP_INTERFACE {
- General = 0,
- GeneralSCSI = 0,
- GeneralIDE = 0,
- ATACompatible = 1,
-
- GeneralFloppy = 0,
- Compatible765 = 1,
- NS398_Floppy = 2, /* NS Super I/O wired to use index
- register at port 398 and data
- register at port 399 */
- NS26E_Floppy = 3, /* Ports 26E and 26F */
- NS15C_Floppy = 4, /* Ports 15C and 15D */
- NS2E_Floppy = 5, /* Ports 2E and 2F */
- CHRP_Floppy = 6, /* CHRP Floppy in PR*P system */
-
- GeneralIPI = 0,
-
- GeneralEther = 0,
- GeneralToken = 0,
- GeneralFDDI = 0,
-
- GeneralVGA = 0,
- GeneralSVGA = 0,
- GeneralXGA = 0,
-
- GeneralVideo = 0,
- GeneralAudio = 0,
- CS4232Audio = 1, /* CS 4232 Plug 'n Play Configured */
-
- GeneralRAM = 0,
- GeneralFLASH = 0,
- PCIMemoryController = 0, /* PCI Config Method */
- RS6KMemoryController = 1, /* RS6K Config Method */
-
- GeneralHostBridge = 0,
- GeneralISABridge = 0,
- GeneralEISABridge = 0,
- GeneralMCABridge = 0,
- GeneralPCIBridge = 0,
- PCIBridgeDirect = 0,
- PCIBridgeIndirect = 1,
- PCIBridgeRS6K = 2,
- GeneralPCMCIABridge = 0,
- GeneralVMEBridge = 0,
-
- GeneralRS232 = 0,
- COMx = 1,
- Compatible16450 = 2,
- Compatible16550 = 3,
- NS398SerPort = 4, /* NS Super I/O wired to use index
- register at port 398 and data
- register at port 399 */
- NS26ESerPort = 5, /* Ports 26E and 26F */
- NS15CSerPort = 6, /* Ports 15C and 15D */
- NS2ESerPort = 7, /* Ports 2E and 2F */
-
- GeneralParPort = 0,
- LPTx = 1,
- NS398ParPort = 2, /* NS Super I/O wired to use index
- register at port 398 and data
- register at port 399 */
- NS26EParPort = 3, /* Ports 26E and 26F */
- NS15CParPort = 4, /* Ports 15C and 15D */
- NS2EParPort = 5, /* Ports 2E and 2F */
-
- GeneralPIC = 0,
- ISA_PIC = 1,
- EISA_PIC = 2,
- MPIC = 3,
- RS6K_PIC = 4,
-
- GeneralDMA = 0,
- ISA_DMA = 1,
- EISA_DMA = 2,
-
- GeneralTimer = 0,
- ISA_Timer = 1,
- EISA_Timer = 2,
- GeneralRTC = 0,
- ISA_RTC = 1,
-
- StoreThruOnly = 1,
- StoreInEnabled = 2,
- RS6KL2Cache = 3,
-
- IndirectNVRAM = 0, /* Indirectly addressed */
- DirectNVRAM = 1, /* Memory Mapped */
- IndirectNVRAM24 = 2, /* Indirectly addressed - 24 bit */
-
- GeneralPowerManagement = 0,
- EPOWPowerManagement = 1,
- PowerControl = 2, /* d1378 */
-
- GeneralCMOS = 0,
-
- GeneralOPPanel = 0,
- HarddiskLight = 1,
- CDROMLight = 2,
- PowerLight = 3,
- KeyLock = 4,
- ANDisplay = 5, /* AlphaNumeric Display */
- SystemStatusLED = 6, /* 3 digit 7 segment LED */
- CHRP_SystemStatusLED = 7, /* CHRP LEDs in PR*P system */
-
- GeneralServiceProcessor = 0,
-
- TransferData = 1,
- IGMC32 = 2,
- IGMC64 = 3,
-
- GeneralSystemPlanar = 0, /* 10/5/95 */
-
- } PnP_INTERFACE;
-
-/* PnP resources */
-
-/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */
-
-typedef struct _SERIAL_ID {
- unsigned char VendorID0; /* Bit(7)=0 */
- /* Bits(6:2)=1st character in */
- /* compressed ASCII */
- /* Bits(1:0)=2nd character in */
- /* compressed ASCII bits(4:3) */
- unsigned char VendorID1; /* Bits(7:5)=2nd character in */
- /* compressed ASCII bits(2:0) */
- /* Bits(4:0)=3rd character in */
- /* compressed ASCII */
- unsigned char VendorID2; /* Product number - vendor assigned */
- unsigned char VendorID3; /* Product number - vendor assigned */
-
-/* Serial number is to provide uniqueness if more than one board of same */
-/* type is in system. Must be "FFFFFFFF" if feature not supported. */
-
- unsigned char Serial0; /* Unique serial number bits (7:0) */
- unsigned char Serial1; /* Unique serial number bits (15:8) */
- unsigned char Serial2; /* Unique serial number bits (23:16) */
- unsigned char Serial3; /* Unique serial number bits (31:24) */
- unsigned char Checksum;
- } SERIAL_ID;
-
-typedef enum _PnPItemName {
- Unused = 0,
- PnPVersion = 1,
- LogicalDevice = 2,
- CompatibleDevice = 3,
- IRQFormat = 4,
- DMAFormat = 5,
- StartDepFunc = 6,
- EndDepFunc = 7,
- IOPort = 8,
- FixedIOPort = 9,
- Res1 = 10,
- Res2 = 11,
- Res3 = 12,
- SmallVendorItem = 14,
- EndTag = 15,
- MemoryRange = 1,
- ANSIIdentifier = 2,
- UnicodeIdentifier = 3,
- LargeVendorItem = 4,
- MemoryRange32 = 5,
- MemoryRangeFixed32 = 6,
- } PnPItemName;
-
-/* Define a bunch of access functions for the bits in the tag field */
-
-/* Tag type - 0 = small; 1 = large */
-#define tag_type(t) (((t) & 0x80)>>7)
-#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7))
-
-/* Small item name is 4 bits - one of PnPItemName enum above */
-#define tag_small_item_name(t) (((t) & 0x78)>>3)
-#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3))
-
-/* Small item count is 3 bits - count of further bytes in packet */
-#define tag_small_count(t) ((t) & 0x07)
-#define set_tag_count(t,v) (t = (t & 0x78) | (v))
-
-/* Large item name is 7 bits - one of PnPItemName enum above */
-#define tag_large_item_name(t) ((t) & 0x7f)
-#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v))
-
-/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */
-
-typedef union _PnP_TAG_PACKET {
- struct _S1_Pack{ /* VERSION PACKET */
- unsigned char Tag; /* small tag = 0x0a */
- unsigned char Version[2]; /* PnP version, Vendor version */
- } S1_Pack;
-
- struct _S2_Pack{ /* LOGICAL DEVICE ID PACKET */
- unsigned char Tag; /* small tag = 0x15 or 0x16 */
- unsigned char DevId[4]; /* Logical device id */
- unsigned char Flags[2]; /* bit(0) boot device; */
- /* bit(7:1) cmd in range x31-x37 */
- /* bit(7:0) cmd in range x28-x3f (opt)*/
- } S2_Pack;
-
- struct _S3_Pack{ /* COMPATIBLE DEVICE ID PACKET */
- unsigned char Tag; /* small tag = 0x1c */
- unsigned char CompatId[4]; /* Compatible device id */
- } S3_Pack;
-
- struct _S4_Pack{ /* IRQ PACKET */
- unsigned char Tag; /* small tag = 0x22 or 0x23 */
- unsigned char IRQMask[2]; /* bit(0) is IRQ0, ...; */
- /* bit(0) is IRQ8 ... */
- unsigned char IRQInfo; /* optional; assume bit(0)=1; else */
- /* bit(0) - high true edge sensitive */
- /* bit(1) - low true edge sensitive */
- /* bit(2) - high true level sensitive*/
- /* bit(3) - low true level sensitive */
- /* bit(7:4) - must be 0 */
- } S4_Pack;
-
- struct _S5_Pack{ /* DMA PACKET */
- unsigned char Tag; /* small tag = 0x2a */
- unsigned char DMAMask; /* bit(0) is channel 0 ... */
- unsigned char DMAInfo;
- } S5_Pack;
-
- struct _S6_Pack{ /* START DEPENDENT FUNCTION PACKET */
- unsigned char Tag; /* small tag = 0x30 or 0x31 */
- unsigned char Priority; /* Optional; if missing then x01; else*/
- /* x00 = best possible */
- /* x01 = acceptible */
- /* x02 = sub-optimal but functional */
- } S6_Pack;
-
- struct _S7_Pack{ /* END DEPENDENT FUNCTION PACKET */
- unsigned char Tag; /* small tag = 0x38 */
- } S7_Pack;
-
- struct _S8_Pack{ /* VARIABLE I/O PORT PACKET */
- unsigned char Tag; /* small tag x47 */
- unsigned char IOInfo; /* x0 = decode only bits(9:0); */
-#define ISAAddr16bit 0x01 /* x01 = decode bits(15:0) */
- unsigned char RangeMin[2]; /* Min base address */
- unsigned char RangeMax[2]; /* Max base address */
- unsigned char IOAlign; /* base alignmt, incr in 1B blocks */
- unsigned char IONum; /* number of contiguous I/O ports */
- } S8_Pack;
-
- struct _S9_Pack{ /* FIXED I/O PORT PACKET */
- unsigned char Tag; /* small tag = 0x4b */
- unsigned char Range[2]; /* base address 10 bits */
- unsigned char IONum; /* number of contiguous I/O ports */
- } S9_Pack;
-
- struct _S14_Pack{ /* VENDOR DEFINED PACKET */
- unsigned char Tag; /* small tag = 0x7m m = 1-7 */
- union _S14_Data{
- unsigned char Data[7]; /* Vendor defined */
- struct _S14_PPCPack{ /* Pr*p s14 pack */
- unsigned char Type; /* 00=non-IBM */
- unsigned char PPCData[6]; /* Vendor defined */
- } S14_PPCPack;
- } S14_Data;
- } S14_Pack;
-
- struct _S15_Pack{ /* END PACKET */
- unsigned char Tag; /* small tag = 0x78 or 0x79 */
- unsigned char Check; /* optional - checksum */
- } S15_Pack;
-
- struct _L1_Pack{ /* MEMORY RANGE PACKET */
- unsigned char Tag; /* large tag = 0x81 */
- unsigned char Count0; /* x09 */
- unsigned char Count1; /* x00 */
- unsigned char Data[9]; /* a variable array of bytes, */
- /* count in tag */
- } L1_Pack;
-
- struct _L2_Pack{ /* ANSI ID STRING PACKET */
- unsigned char Tag; /* large tag = 0x82 */
- unsigned char Count0; /* Length of string */
- unsigned char Count1;
- unsigned char Identifier[1]; /* a variable array of bytes, */
- /* count in tag */
- } L2_Pack;
-
- struct _L3_Pack{ /* UNICODE ID STRING PACKET */
- unsigned char Tag; /* large tag = 0x83 */
- unsigned char Count0; /* Length + 2 of string */
- unsigned char Count1;
- unsigned char Country0; /* TBD */
- unsigned char Country1; /* TBD */
- unsigned char Identifier[1]; /* a variable array of bytes, */
- /* count in tag */
- } L3_Pack;
-
- struct _L4_Pack{ /* VENDOR DEFINED PACKET */
- unsigned char Tag; /* large tag = 0x84 */
- unsigned char Count0;
- unsigned char Count1;
- union _L4_Data{
- unsigned char Data[1]; /* a variable array of bytes, */
- /* count in tag */
- struct _L4_PPCPack{ /* Pr*p L4 packet */
- unsigned char Type; /* 00=non-IBM */
- unsigned char PPCData[1]; /* a variable array of bytes, */
- /* count in tag */
- } L4_PPCPack;
- } L4_Data;
- } L4_Pack;
-
- struct _L5_Pack{
- unsigned char Tag; /* large tag = 0x85 */
- unsigned char Count0; /* Count = 17 */
- unsigned char Count1;
- unsigned char Data[17];
- } L5_Pack;
-
- struct _L6_Pack{
- unsigned char Tag; /* large tag = 0x86 */
- unsigned char Count0; /* Count = 9 */
- unsigned char Count1;
- unsigned char Data[9];
- } L6_Pack;
-
- } PnP_TAG_PACKET;
-
-#endif /* __ASSEMBLY__ */
-#endif /* ndef _PNP_ */
+++ /dev/null
-/* 7/18/95 */
-/*----------------------------------------------------------------------------*/
-/* Residual Data header definitions and prototypes */
-/*----------------------------------------------------------------------------*/
-
-/* Structure map for RESIDUAL on PowerPC Reference Platform */
-/* residual.h - Residual data structure passed in r3. */
-/* Load point passed in r4 to boot image. */
-/* For enum's: if given in hex then they are bit significant, */
-/* i.e. only one bit is on for each enum */
-/* Reserved fields must be filled with zeros. */
-
-#ifndef _RESIDUAL_
-#define _RESIDUAL_
-
-#ifndef __ASSEMBLY__
-
-#define MAX_CPUS 32 /* These should be set to the maximum */
-#define MAX_MEMS 64 /* number possible for this system. */
-#define MAX_DEVICES 256 /* Changing these will change the */
-#define AVE_PNP_SIZE 32 /* structure, hence the version of */
-#define MAX_MEM_SEGS 64 /* this header file. */
-
-/*----------------------------------------------------------------------------*/
-/* Public structures... */
-/*----------------------------------------------------------------------------*/
-
-#include "pnp.h"
-
-typedef enum _L1CACHE_TYPE {
- NoneCAC = 0,
- SplitCAC = 1,
- CombinedCAC = 2
- } L1CACHE_TYPE;
-
-typedef enum _TLB_TYPE {
- NoneTLB = 0,
- SplitTLB = 1,
- CombinedTLB = 2
- } TLB_TYPE;
-
-typedef enum _FIRMWARE_SUPPORT {
- Conventional = 0x01,
- OpenFirmware = 0x02,
- Diagnostics = 0x04,
- LowDebug = 0x08,
- Multiboot = 0x10,
- LowClient = 0x20,
- Hex41 = 0x40,
- FAT = 0x80,
- ISO9660 = 0x0100,
- SCSI_InitiatorID_Override = 0x0200,
- Tape_Boot = 0x0400,
- FW_Boot_Path = 0x0800
- } FIRMWARE_SUPPORT;
-
-typedef enum _FIRMWARE_SUPPLIERS {
- IBMFirmware = 0x00,
- MotoFirmware = 0x01, /* 7/18/95 */
- FirmWorks = 0x02, /* 10/5/95 */
- Bull = 0x03, /* 04/03/96 */
- } FIRMWARE_SUPPLIERS;
-
-typedef enum _ENDIAN_SWITCH_METHODS {
- UsePort92 = 0x01,
- UsePCIConfigA8 = 0x02,
- UseFF001030 = 0x03,
- } ENDIAN_SWITCH_METHODS;
-
-typedef enum _SPREAD_IO_METHODS {
- UsePort850 = 0x00,
-/*UsePCIConfigA8 = 0x02,*/
- } SPREAD_IO_METHODS;
-
-typedef struct _VPD {
-
- /* Box dependent stuff */
- unsigned char PrintableModel[32]; /* Null terminated string.
- Must be of the form:
- vvv,<20h>,<model designation>,<0x0>
- where vvv is the vendor ID
- e.g. IBM PPS MODEL 6015<0x0> */
- unsigned char Serial[16]; /* 12/94:
- Serial Number; must be of the form:
- vvv<serial number> where vvv is the
- vendor ID.
- e.g. IBM60151234567<20h><20h> */
- unsigned char Reserved[48];
- unsigned long FirmwareSupplier; /* See FirmwareSuppliers enum */
- unsigned long FirmwareSupports; /* See FirmwareSupport enum */
- unsigned long NvramSize; /* Size of nvram in bytes */
- unsigned long NumSIMMSlots;
- unsigned short EndianSwitchMethod; /* See EndianSwitchMethods enum */
- unsigned short SpreadIOMethod; /* See SpreadIOMethods enum */
- unsigned long SmpIar;
- unsigned long RAMErrLogOffset; /* Heap offset to error log */
- unsigned long Reserved5;
- unsigned long Reserved6;
- unsigned long ProcessorHz; /* Processor clock frequency in Hertz */
- unsigned long ProcessorBusHz; /* Processor bus clock frequency */
- unsigned long Reserved7;
- unsigned long TimeBaseDivisor; /* (Bus clocks per timebase tic)*1000 */
- unsigned long WordWidth; /* Word width in bits */
- unsigned long PageSize; /* Page size in bytes */
- unsigned long CoherenceBlockSize; /* Unit of transfer in/out of cache
- for which coherency is maintained;
- normally <= CacheLineSize. */
- unsigned long GranuleSize; /* Unit of lock allocation to avoid */
- /* false sharing of locks. */
-
- /* L1 Cache variables */
- unsigned long CacheSize; /* L1 Cache size in KB. This is the */
- /* total size of the L1, whether */
- /* combined or split */
- unsigned long CacheAttrib; /* L1CACHE_TYPE */
- unsigned long CacheAssoc; /* L1 Cache associativity. Use this
- for combined cache. If split, put
- zeros here. */
- unsigned long CacheLineSize; /* L1 Cache line size in bytes. Use
- for combined cache. If split, put
- zeros here. */
- /* For split L1 Cache: (= combined if combined cache) */
- unsigned long I_CacheSize;
- unsigned long I_CacheAssoc;
- unsigned long I_CacheLineSize;
- unsigned long D_CacheSize;
- unsigned long D_CacheAssoc;
- unsigned long D_CacheLineSize;
-
- /* Translation Lookaside Buffer variables */
- unsigned long TLBSize; /* Total number of TLBs on the system */
- unsigned long TLBAttrib; /* Combined I+D or split TLB */
- unsigned long TLBAssoc; /* TLB Associativity. Use this for
- combined TLB. If split, put zeros
- here. */
- /* For split TLB: (= combined if combined TLB) */
- unsigned long I_TLBSize;
- unsigned long I_TLBAssoc;
- unsigned long D_TLBSize;
- unsigned long D_TLBAssoc;
-
- unsigned long ExtendedVPD; /* Offset to extended VPD area;
- null if unused */
- } VPD;
-
-typedef enum _DEVICE_FLAGS {
- Enabled = 0x4000, /* 1 - PCI device is enabled */
- Integrated = 0x2000,
- Failed = 0x1000, /* 1 - device failed POST code tests */
- Static = 0x0800, /* 0 - dynamically configurable
- 1 - static */
- Dock = 0x0400, /* 0 - not a docking station device
- 1 - is a docking station device */
- Boot = 0x0200, /* 0 - device cannot be used for BOOT
- 1 - can be a BOOT device */
- Configurable = 0x0100, /* 1 - device is configurable */
- Disableable = 0x80, /* 1 - device can be disabled */
- PowerManaged = 0x40, /* 0 - not managed; 1 - managed */
- ReadOnly = 0x20, /* 1 - device is read only */
- Removable = 0x10, /* 1 - device is removable */
- ConsoleIn = 0x08,
- ConsoleOut = 0x04,
- Input = 0x02,
- Output = 0x01
- } DEVICE_FLAGS;
-
-typedef enum _BUS_ID {
- ISADEVICE = 0x01,
- EISADEVICE = 0x02,
- PCIDEVICE = 0x04,
- PCMCIADEVICE = 0x08,
- PNPISADEVICE = 0x10,
- MCADEVICE = 0x20,
- MXDEVICE = 0x40, /* Devices on mezzanine bus */
- PROCESSORDEVICE = 0x80, /* Devices on processor bus */
- VMEDEVICE = 0x100,
- } BUS_ID;
-
-typedef struct _DEVICE_ID {
- unsigned long BusId; /* See BUS_ID enum above */
- unsigned long DevId; /* Big Endian format */
- unsigned long SerialNum; /* For multiple usage of a single
- DevId */
- unsigned long Flags; /* See DEVICE_FLAGS enum above */
- unsigned char BaseType; /* See pnp.h for bit definitions */
- unsigned char SubType; /* See pnp.h for bit definitions */
- unsigned char Interface; /* See pnp.h for bit definitions */
- unsigned char Spare;
- } DEVICE_ID;
-
-typedef union _BUS_ACCESS {
- struct _PnPAccess{
- unsigned char CSN;
- unsigned char LogicalDevNumber;
- unsigned short ReadDataPort;
- } PnPAccess;
- struct _ISAAccess{
- unsigned char SlotNumber; /* ISA Slot Number generally not
- available; 0 if unknown */
- unsigned char LogicalDevNumber;
- unsigned short ISAReserved;
- } ISAAccess;
- struct _MCAAccess{
- unsigned char SlotNumber;
- unsigned char LogicalDevNumber;
- unsigned short MCAReserved;
- } MCAAccess;
- struct _PCMCIAAccess{
- unsigned char SlotNumber;
- unsigned char LogicalDevNumber;
- unsigned short PCMCIAReserved;
- } PCMCIAAccess;
- struct _EISAAccess{
- unsigned char SlotNumber;
- unsigned char FunctionNumber;
- unsigned short EISAReserved;
- } EISAAccess;
- struct _PCIAccess{
- unsigned char BusNumber;
- unsigned char DevFuncNumber;
- unsigned short PCIReserved;
- } PCIAccess;
- struct _ProcBusAccess{
- unsigned char BusNumber;
- unsigned char BUID;
- unsigned short ProcBusReserved;
- } ProcBusAccess;
- } BUS_ACCESS;
-
-/* Per logical device information */
-typedef struct _PPC_DEVICE {
- DEVICE_ID DeviceId;
- BUS_ACCESS BusAccess;
-
- /* The following three are offsets into the DevicePnPHeap */
- /* All are in PnP compressed format */
- unsigned long AllocatedOffset; /* Allocated resource description */
- unsigned long PossibleOffset; /* Possible resource description */
- unsigned long CompatibleOffset; /* Compatible device identifiers */
- } PPC_DEVICE;
-
-typedef enum _CPU_STATE {
- CPU_GOOD = 0, /* CPU is present, and active */
- CPU_GOOD_FW = 1, /* CPU is present, and in firmware */
- CPU_OFF = 2, /* CPU is present, but inactive */
- CPU_FAILED = 3, /* CPU is present, but failed POST */
- CPU_NOT_PRESENT = 255 /* CPU not present */
- } CPU_STATE;
-
-typedef struct _PPC_CPU {
- unsigned long CpuType; /* Result of mfspr from Processor
- Version Register (PVR).
- PVR(0-15) = Version (e.g. 601)
- PVR(16-31 = EC Level */
- unsigned char CpuNumber; /* CPU Number for this processor */
- unsigned char CpuState; /* CPU State, see CPU_STATE enum */
- unsigned short Reserved;
- } PPC_CPU;
-
-typedef struct _PPC_MEM {
- unsigned long SIMMSize; /* 0 - absent or bad
- 8M, 32M (in MB) */
- } PPC_MEM;
-
-typedef enum _MEM_USAGE {
- Other = 0x8000,
- ResumeBlock = 0x4000, /* for use by power management */
- SystemROM = 0x2000, /* Flash memory (populated) */
- UnPopSystemROM = 0x1000, /* Unpopulated part of SystemROM area */
- IOMemory = 0x0800,
- SystemIO = 0x0400,
- SystemRegs = 0x0200,
- PCIAddr = 0x0100,
- PCIConfig = 0x80,
- ISAAddr = 0x40,
- Unpopulated = 0x20, /* Unpopulated part of System Memory */
- Free = 0x10, /* Free part of System Memory */
- BootImage = 0x08, /* BootImage part of System Memory */
- FirmwareCode = 0x04, /* FirmwareCode part of System Memory */
- FirmwareHeap = 0x02, /* FirmwareHeap part of System Memory */
- FirmwareStack = 0x01 /* FirmwareStack part of System Memory*/
- } MEM_USAGE;
-
-typedef struct _MEM_MAP {
- unsigned long Usage; /* See MEM_USAGE above */
- unsigned long BasePage; /* Page number measured in 4KB pages */
- unsigned long PageCount; /* Page count measured in 4KB pages */
- } MEM_MAP;
-
-typedef struct _RESIDUAL {
- unsigned long ResidualLength; /* Length of Residual */
- unsigned char Version; /* of this data structure */
- unsigned char Revision; /* of this data structure */
- unsigned short EC; /* of this data structure */
- /* VPD */
- VPD VitalProductData;
- /* CPU */
- unsigned short MaxNumCpus; /* Max CPUs in this system */
- unsigned short ActualNumCpus; /* ActualNumCpus < MaxNumCpus means */
- /* that there are unpopulated or */
- /* otherwise unusable cpu locations */
- PPC_CPU Cpus[MAX_CPUS];
- /* Memory */
- unsigned long TotalMemory; /* Total amount of memory installed */
- unsigned long GoodMemory; /* Total amount of good memory */
- unsigned long ActualNumMemSegs;
- MEM_MAP Segs[MAX_MEM_SEGS];
- unsigned long ActualNumMemories;
- PPC_MEM Memories[MAX_MEMS];
- /* Devices */
- unsigned long ActualNumDevices;
- PPC_DEVICE Devices[MAX_DEVICES];
- unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE];
- } RESIDUAL;
-
-
-extern RESIDUAL *res;
-extern void print_residual_device_info(void);
-extern PPC_DEVICE *residual_find_device(unsigned long BusMask,
- unsigned char * DevID, int BaseType,
- int SubType, int Interface, int n);
-extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag,
- int n);
-extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p,
- unsigned packet_type,
- int n);
-extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p,
- unsigned packet_type,
- int n);
-#endif /* __ASSEMBLY__ */
-#endif /* ndef _RESIDUAL_ */
return hdr + 1;
}
-void *os_free(void *ptr)
+void os_free(void *ptr)
{
struct os_mem_hdr *hdr = ptr;
+++ /dev/null
-/*
- * Generic MTRR (Memory Type Range Register) ioctls.
- * Taken from the Linux kernel
- *
- * (C) Copyright 2012
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * Copyright (C) 1997-1999 Richard Gooch <rgooch@atnf.csiro.au>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_X86_MTRR_H
-#define _ASM_X86_MTRR_H
-
-#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
-#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-#include <linux/ioctl.h>
-#include <errno.h>
-
-#define MTRR_IOCTL_BASE 'M'
-
-struct mtrr_sentry {
- unsigned long base; /* Base address */
- unsigned int size; /* Size of region */
- unsigned int type; /* Type of region */
-};
-
-/*
- * Warning: this structure has a different order from i386
- * on x86-64. The 32bit emulation code takes care of that.
- * But you need to use this for 64bit, otherwise your X server
- * will break.
- */
-
-#ifdef __i386__
-struct mtrr_gentry {
- unsigned int regnum; /* Register number */
- unsigned long base; /* Base address */
- unsigned int size; /* Size of region */
- unsigned int type; /* Type of region */
-};
-
-#else /* __i386__ */
-
-struct mtrr_gentry {
- unsigned long base; /* Base address */
- unsigned int size; /* Size of region */
- unsigned int regnum; /* Register number */
- unsigned int type; /* Type of region */
-};
-#endif /* !__i386__ */
-
-struct mtrr_var_range {
- __u32 base_lo;
- __u32 base_hi;
- __u32 mask_lo;
- __u32 mask_hi;
-};
-
-/*
- * In the Intel processor's MTRR interface, the MTRR type is always held in
- * an 8 bit field:
- */
-typedef __u8 mtrr_type;
-
-#define MTRR_NUM_FIXED_RANGES 88
-#define MTRR_MAX_VAR_RANGES 256
-
-struct mtrr_state_type {
- struct mtrr_var_range var_ranges[MTRR_MAX_VAR_RANGES];
- mtrr_type fixed_ranges[MTRR_NUM_FIXED_RANGES];
- unsigned char enabled;
- unsigned char have_fixed;
- mtrr_type def_type;
-};
-
-/* These are the various ioctls */
-#define MTRRIOC_ADD_ENTRY _IOW(MTRR_IOCTL_BASE, 0, struct mtrr_sentry)
-#define MTRRIOC_SET_ENTRY _IOW(MTRR_IOCTL_BASE, 1, struct mtrr_sentry)
-#define MTRRIOC_DEL_ENTRY _IOW(MTRR_IOCTL_BASE, 2, struct mtrr_sentry)
-#define MTRRIOC_GET_ENTRY _IOWR(MTRR_IOCTL_BASE, 3, struct mtrr_gentry)
-#define MTRRIOC_KILL_ENTRY _IOW(MTRR_IOCTL_BASE, 4, struct mtrr_sentry)
-#define MTRRIOC_ADD_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 5, struct mtrr_sentry)
-#define MTRRIOC_SET_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 6, struct mtrr_sentry)
-#define MTRRIOC_DEL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 7, struct mtrr_sentry)
-#define MTRRIOC_GET_PAGE_ENTRY _IOWR(MTRR_IOCTL_BASE, 8, struct mtrr_gentry)
-#define MTRRIOC_KILL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 9, struct mtrr_sentry)
-
-/* These are the region types */
-#define MTRR_TYPE_UNCACHABLE 0
-#define MTRR_TYPE_WRCOMB 1
-/*#define MTRR_TYPE_ 2*/
-/*#define MTRR_TYPE_ 3*/
-#define MTRR_TYPE_WRTHROUGH 4
-#define MTRR_TYPE_WRPROT 5
-#define MTRR_TYPE_WRBACK 6
-#define MTRR_NUM_TYPES 7
-
-#ifdef __KERNEL__
-
-/* The following functions are for use by other drivers */
-# ifdef CONFIG_MTRR
-extern u8 mtrr_type_lookup(u64 addr, u64 end);
-extern void mtrr_save_fixed_ranges(void *);
-extern void mtrr_save_state(void);
-extern int mtrr_add(unsigned long base, unsigned long size,
- unsigned int type, bool increment);
-extern int mtrr_add_page(unsigned long base, unsigned long size,
- unsigned int type, bool increment);
-extern int mtrr_del(int reg, unsigned long base, unsigned long size);
-extern int mtrr_del_page(int reg, unsigned long base, unsigned long size);
-extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi);
-extern void mtrr_ap_init(void);
-extern void mtrr_bp_init(void);
-extern void set_mtrr_aps_delayed_init(void);
-extern void mtrr_aps_init(void);
-extern void mtrr_bp_restore(void);
-extern int mtrr_trim_uncached_memory(unsigned long end_pfn);
-extern int amd_special_default_mtrr(void);
-# else
-static inline u8 mtrr_type_lookup(u64 addr, u64 end)
-{
- /*
- * Return no-MTRRs:
- */
- return 0xff;
-}
-#define mtrr_save_fixed_ranges(arg) do {} while (0)
-#define mtrr_save_state() do {} while (0)
-static inline int mtrr_del(int reg, unsigned long base, unsigned long size)
-{
- return -ENODEV;
-}
-static inline int mtrr_del_page(int reg, unsigned long base, unsigned long size)
-{
- return -ENODEV;
-}
-static inline int mtrr_trim_uncached_memory(unsigned long end_pfn)
-{
- return 0;
-}
-static inline void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi)
-{
-}
-
-#define mtrr_ap_init() do {} while (0)
-#define mtrr_bp_init() do {} while (0)
-#define set_mtrr_aps_delayed_init() do {} while (0)
-#define mtrr_aps_init() do {} while (0)
-#define mtrr_bp_restore() do {} while (0)
-# endif
-
-#ifdef CONFIG_COMPAT
-#include <linux/compat.h>
-
-struct mtrr_sentry32 {
- compat_ulong_t base; /* Base address */
- compat_uint_t size; /* Size of region */
- compat_uint_t type; /* Type of region */
-};
-
-struct mtrr_gentry32 {
- compat_ulong_t regnum; /* Register number */
- compat_uint_t base; /* Base address */
- compat_uint_t size; /* Size of region */
- compat_uint_t type; /* Type of region */
-};
-
-#define MTRR_IOCTL_BASE 'M'
-
-#define MTRRIOC32_ADD_ENTRY _IOW(MTRR_IOCTL_BASE, 0, struct mtrr_sentry32)
-#define MTRRIOC32_SET_ENTRY _IOW(MTRR_IOCTL_BASE, 1, struct mtrr_sentry32)
-#define MTRRIOC32_DEL_ENTRY _IOW(MTRR_IOCTL_BASE, 2, struct mtrr_sentry32)
-#define MTRRIOC32_GET_ENTRY _IOWR(MTRR_IOCTL_BASE, 3, struct mtrr_gentry32)
-#define MTRRIOC32_KILL_ENTRY _IOW(MTRR_IOCTL_BASE, 4, struct mtrr_sentry32)
-#define MTRRIOC32_ADD_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 5, struct mtrr_sentry32)
-#define MTRRIOC32_SET_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 6, struct mtrr_sentry32)
-#define MTRRIOC32_DEL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 7, struct mtrr_sentry32)
-#define MTRRIOC32_GET_PAGE_ENTRY _IOWR(MTRR_IOCTL_BASE, 8, struct mtrr_gentry32)
-#define MTRRIOC32_KILL_PAGE_ENTRY \
- _IOW(MTRR_IOCTL_BASE, 9, struct mtrr_sentry32)
-#endif /* CONFIG_COMPAT */
-
-#endif /* __KERNEL__ */
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_X86_MTRR_H */
#include <linux/compiler.h>
#include "../include/memory.h"
-#include "serial.h"
#ifdef CONFIG_DB64360
#include "../db64360/mpsc.h"
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * modified for marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* serial.h - mostly useful for DUART serial_init in serial.c */
-
-#ifndef __SERIAL_H__
-#define __SERIAL_H__
-
-#if 0
-
-#define B230400 1
-#define B115200 2
-#define B57600 4
-#define B38400 82
-#define B19200 163
-#define B9600 24
-#define B4800 651
-#define B2400 1302
-#define B1200 2604
-#define B600 5208
-#define B300 10417
-#define B150 20833
-#define B110 28409
-#define BDEFAULT B115200
-
- /* this stuff is important to initialize
- the DUART channels */
-
-#define Scale 0x01L /* distance between port addresses */
-#define COM1 0x000003f8 /* Keyboard */
-#define COM2 0x000002f8 /* Host */
-
-
-/* Port Definitions relative to base COM port addresses */
-#define DataIn (0x00*Scale) /* data input port */
-#define DataOut (0x00*Scale) /* data output port */
-#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */
-#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */
-#define Ier (0x01*Scale) /* interrupt enable register */
-#define Iir (0x02*Scale) /* interrupt identification register */
-#define Lcr (0x03*Scale) /* line control register */
-#define Mcr (0x04*Scale) /* modem control register */
-#define Lsr (0x05*Scale) /* line status register */
-#define Msr (0x06*Scale) /* modem status register */
-
-/* Bit Definitions for above ports */
-#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */
-#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */
-
-#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */
-#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */
-#define McrDflt (McrRts|McrDtr)
-
-#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/
- /* b6: transmitter empty */
-#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */
-
-#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */
-#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */
-#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */
-
-#define IerRda 0xf /* b0: Enable received data available interrupt */
-
-#endif
-
-#endif /* __SERIAL_H__ */
#include <common.h>
#include <netdev.h>
+#if defined(CONFIG_CFI_FLASH_MTD)
#include <mtd/cfi_flash.h>
+#endif
#include <asm/io.h>
#include <asm/gpio.h>
get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
}
-int timer_init(void)
-{
- return 0;
-}
-
/*
* Start timer:
* Setup a 32 bit timer, running at 1KHz
# SPDX-License-Identifier: GPL-2.0+
#
-$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
-
obj-y := ../common/tamonten-ng.o
include ../../nvidia/common/common.mk
int board_eth_init(bd_t *bis)
{
- int ret;
-
setup_iomux_enet();
- ret = cpu_eth_init(bis);
- if (ret)
- printf("FEC MXC: %s:failed\n", __func__);
-
- return ret;
+ return cpu_eth_init(bis);
}
int board_early_init_f(void)
+++ /dev/null
-/* keyboard/mouse not implemented yet */
-
-extern int cma_kbm_not_implemented;
-
-/**************** DEFINES for H8542B Keyboard/Mouse Controller ***************/
-
-/*
- * note the auxillary port is used to control the mouse
- */
-
-/* 8542B Commands (Sent to the Command Port) */
-#define HT8542_CMD_SET_BYTE 0x60 /* Set the command byte */
-#define HT8542_CMD_GET_BYTE 0x20 /* Get the command byte */
-#define HT8542_CMD_KBD_OBUFF 0xD2 /* Write to HT8542 Kbd Output Buffer */
-#define HT8542_CMD_AUX_OBUFF 0xD3 /* Write to HT8542 Mse Output Buffer */
-#define HT8542_CMD_AUX_WRITE 0xD4 /* Write to Mouse Port */
-#define HT8542_CMD_AUX_OFF 0xA7 /* Disable Mouse Port */
-#define HT8542_CMD_AUX_ON 0xA8 /* Re-Enable Mouse Port */
-#define HT8542_CMD_AUX_TEST 0xA9 /* Test for the presence of a Mouse */
-#define HT8542_CMD_DIAG 0xAA /* Start Diagnostics */
-#define HT8542_CMD_KBD_TEST 0xAB /* Test for presence of a keyboard */
-#define HT8542_CMD_KBD_OFF 0xAD /* Disable Kbd Port (use KBD_DAT_ON) */
-#define HT8542_CMD_KBD_ON 0xAE /* Enable Kbd Port (use KBD_DAT_OFF) */
-
-/* HT8542B cmd byte set by KBD_CMD_SET_BYTE and retrieved by KBD_CMD_GET_BYTE */
-#define HT8542_CMD_BYTE_TRANS 0x40
-#define HT8542_CMD_BYTE_AUX_OFF 0x20 /* 1 = mse port disabled, 0 = enabled */
-#define HT8542_CMD_BYTE_KBD_OFF 0x10 /* 1 = kbd port disabled, 0 = enabled */
-#define HT8542_CMD_BYTE_OVER 0x08 /* 1 = override keyboard lock */
-#define HT8542_CMD_BYTE_RES 0x04 /* reserved */
-#define HT8542_CMD_BYTE_AUX_INT 0x02 /* 1 = enable mouse interrupt */
-#define HT8542_CMD_BYTE_KBD_INT 0x01 /* 1 = enable keyboard interrupt */
-
-/* Keyboard Commands (Sent to the Data Port) */
-#define KBD_CMD_LED 0xED /* Set Keyboard LEDS with next byte */
-#define KBD_CMD_ECHO 0xEE /* Echo - we get 0xFA, 0xEE back */
-#define KBD_CMD_MODE 0xF0 /* set scan code mode with next byte */
-#define KBD_CMD_ID 0xF2 /* get keyboard/mouse ID */
-#define KBD_CMD_RPT 0xF3 /* Set Repeat Rate and Delay 2nd Byte */
-#define KBD_CMD_ON 0xF4 /* Enable keyboard */
-#define KBD_CMD_OFF 0xF5 /* Disables Scanning, Resets to Def */
-#define KBD_CMD_DEF 0xF6 /* Reverts kbd to default settings */
-#define KBD_CMD_RST 0xFF /* Reset - should get 0xFA, 0xAA back */
-
-/* Set LED second bit defines */
-#define KBD_CMD_LED_SCROLL 0x01 /* Set SCROLL LOCK LED on */
-#define KBD_CMD_LED_NUM 0x02 /* Set NUM LOCK LED on */
-#define KBD_CMD_LED_CAPS 0x04 /* Set CAPS LOCK LED on */
-
-/* Set Mode second byte defines */
-#define KBD_CMD_MODE_STAT 0x00 /* get current scan code mode */
-#define KBD_CMD_MODE_SCAN1 0x01 /* set mode to scan code 1 */
-#define KBD_CMD_MODE_SCAN2 0x02 /* set mode to scan code 2 */
-#define KBD_CMD_MODE_SCAN3 0x03 /* set mode to scan code 3 */
-
-/* Keyboard/Mouse ID Codes */
-#define KBD_CMD_ID_1ST 0xAB /* 1st byte is 0xAB, 2nd is actual ID */
-#define KBD_CMD_ID_KBD 0x83 /* Keyboard */
-#define KBD_CMD_ID_MOUSE 0x00 /* Mouse */
-
-/* Keyboard Data Return Defines */
-#define KBD_STAT_OVER 0x00 /* Buffer Overrun */
-#define KBD_STAT_DIAG_OK 0x55 /* Internal Self Test OK */
-#define KBD_STAT_RST_OK 0xAA /* Reset Complete */
-#define KBD_STAT_ECHO 0xEE /* Echo Command Return */
-#define KBD_STAT_BRK 0xF0 /* Prefix for Break Key Code */
-#define KBD_STAT_ACK 0xFA /* Received after all commands */
-#define KBD_STAT_DIAG_FAIL 0xFD /* Internal Self Test Failed */
-#define KBD_STAT_RESEND 0xFE /* Resend Last Command */
-
-/* HT8542B Status Register Bit Defines */
-#define HT8542_STAT_OBF 0x01 /* 1 = output buffer is full */
-#define HT8542_STAT_IBF 0x02 /* 1 = input buffer is full */
-#define HT8542_STAT_SYS 0x04 /* system flag - unused */
-#define HT8542_STAT_CMD 0x08 /* 1 = cmd in input buffer, 0 = data */
-#define HT8542_STAT_INH 0x10 /* 1 = Inhibit - unused */
-#define HT8542_STAT_TX 0x20 /* 1 = Transmit Timeout has occured */
-#define HT8542_STAT_RX 0x40 /* 1 = Receive Timeout has occured */
-#define HT8542_STAT_PERR 0x80 /* 1 = Parity Error from Keyboard */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/****************************************************************************
- * FLASH Memory Map as used by CRAY L1, 4MB AMD29F032B flash chip
- *
- * Start Address Length
- * +++++++++++++++++++++++++ 0xFFC0_0000 Start of Flash -----------------
- * | Failsafe Linux Image | (1M)
- * +=======================+ 0xFFD0_0000
- * | (Reserved FlashFiles) | (1M)
- * +=======================+ 0xFFE0_0000
- * | Failsafe RootFS | (1M)
- * +=======================+ 0xFFF0_0000
- * | |
- * | U N U S E D |
- * | |
- * +-----------------------+ 0xFFFD_0000 U-Boot image header (64 bytes)
- * | environment settings | (64k)
- * +-----------------------+ 0xFFFE_0000 U-Boot image header (64 bytes)
- * | U-Boot | 0xFFFE_0040 _start of U-Boot
- * | | 0xFFFE_FFFC reset vector - branch to _start
- * +++++++++++++++++++++++++ 0xFFFF_FFFF End of Flash -----------------
- *****************************************************************************/
/*-----------------------------------------------------------------------------#include <config.h> */
#include <asm/ppc4xx.h>
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <config.h>
#include <asm/ppc4xx.h>
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <config.h>
#include <asm/ppc4xx.h>
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
+++ /dev/null
-/*
- * Copyright (c) 2000,2001 Epson Research and Development, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * File generated by S1D13806CFG.EXE
- * Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz)
- * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz)
- */
-
-static S1D_REGS regs_13806_640_320_16bpp[] =
-{
- {0x0001,0x00}, /* Miscellaneous Register */
- {0x01FC,0x00}, /* Display Mode Register */
- {0x0004,0x18}, /* General IO Pins Configuration Register 0 */
- {0x0005,0x00}, /* General IO Pins Configuration Register 1 */
- {0x0008,0x18}, /* General IO Pins Control Register 0 */
- {0x0009,0x00}, /* General IO Pins Control Register 1 */
- {0x0010,0x00}, /* Memory Clock Configuration Register */
- {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */
- {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */
- {0x001C,0x02}, /* MediaPlug Clock Configuration Register */
- {0x001E,0x01}, /* CPU To Memory Wait State Select Register */
- {0x0021,0x03}, /* DRAM Refresh Rate Register */
- {0x002A,0x00}, /* DRAM Timings Control Register 0 */
- {0x002B,0x01}, /* DRAM Timings Control Register 1 */
- {0x0020,0x80}, /* Memory Configuration Register */
- {0x0030,0x25}, /* Panel Type Register */
- {0x0031,0x00}, /* MOD Rate Register */
- {0x0032,0x4F}, /* LCD Horizontal Display Width Register */
- {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */
- {0x0035,0x00}, /* TFT FPLINE Start Position Register */
- {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
- {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */
- {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */
- {0x003A,0x24}, /* LCD Vertical Non-Display Period Register */
- {0x003B,0x00}, /* TFT FPFRAME Start Position Register */
- {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
- {0x0040,0x03}, /* LCD Display Mode Register (8bpp) */
- {0x0041,0x00}, /* LCD Miscellaneous Register */
- {0x0042,0x00}, /* LCD Display Start Address Register 0 */
- {0x0043,0x00}, /* LCD Display Start Address Register 1 */
- {0x0044,0x00}, /* LCD Display Start Address Register 2 */
- {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */
- {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */
- {0x0048,0x00}, /* LCD Pixel Panning Register */
- {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
- {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
- {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
- {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
- {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
- {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
- {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
- {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
- {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
- {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
- {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
- {0x005B,0x10}, /* TV Output Control Register */
- {0x0060,0x05}, /* CRT/TV Display Mode Register */
- {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
- {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
- {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
- {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */
- {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */
- {0x0068,0x00}, /* CRT/TV Pixel Panning Register */
- {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
- {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
- {0x0070,0x00}, /* LCD Ink/Cursor Control Register */
- {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */
- {0x0072,0x00}, /* LCD Cursor X Position Register 0 */
- {0x0073,0x00}, /* LCD Cursor X Position Register 1 */
- {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
- {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
- {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
- {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
- {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
- {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
- {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
- {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
- {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
- {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
- {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */
- {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
- {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
- {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
- {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
- {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
- {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
- {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
- {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
- {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
- {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
- {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
- {0x0100,0x00}, /* BitBlt Control Register 0 */
- {0x0101,0x00}, /* BitBlt Control Register 1 */
- {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
- {0x0103,0x00}, /* BitBlt Operation Register */
- {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
- {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
- {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
- {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
- {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
- {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
- {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
- {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
- {0x0110,0x00}, /* BitBlt Width Register 0 */
- {0x0111,0x00}, /* BitBlt Width Register 1 */
- {0x0112,0x00}, /* BitBlt Height Register 0 */
- {0x0113,0x00}, /* BitBlt Height Register 1 */
- {0x0114,0x00}, /* BitBlt Background Color Register 0 */
- {0x0115,0x00}, /* BitBlt Background Color Register 1 */
- {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
- {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
- {0x01E0,0x00}, /* Look-Up Table Mode Register */
- {0x01E2,0x00}, /* Look-Up Table Address Register */
- {0x01F0,0x10}, /* Power Save Configuration Register */
- {0x01F1,0x00}, /* Power Save Status Register */
- {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
- {0x01FC,0x01}, /* Display Mode Register */
-};
#include <linux/compiler.h>
#include "../../Marvell/include/memory.h"
-#include "serial.h"
#include "mpsc.h"
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * modified for marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* serial.h - mostly useful for DUART serial_init in serial.c */
-
-#ifndef __SERIAL_H__
-#define __SERIAL_H__
-
-#if 0
-
-#define B230400 1
-#define B115200 2
-#define B57600 4
-#define B38400 82
-#define B19200 163
-#define B9600 24
-#define B4800 651
-#define B2400 1302
-#define B1200 2604
-#define B600 5208
-#define B300 10417
-#define B150 20833
-#define B110 28409
-#define BDEFAULT B115200
-
- /* this stuff is important to initialize
- the DUART channels */
-
-#define Scale 0x01L /* distance between port addresses */
-#define COM1 0x000003f8 /* Keyboard */
-#define COM2 0x000002f8 /* Host */
-
-
-/* Port Definitions relative to base COM port addresses */
-#define DataIn (0x00*Scale) /* data input port */
-#define DataOut (0x00*Scale) /* data output port */
-#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */
-#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */
-#define Ier (0x01*Scale) /* interrupt enable register */
-#define Iir (0x02*Scale) /* interrupt identification register */
-#define Lcr (0x03*Scale) /* line control register */
-#define Mcr (0x04*Scale) /* modem control register */
-#define Lsr (0x05*Scale) /* line status register */
-#define Msr (0x06*Scale) /* modem status register */
-
-/* Bit Definitions for above ports */
-#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */
-#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */
-
-#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */
-#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */
-#define McrDflt (McrRts|McrDtr)
-
-#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/
- /* b6: transmitter empty */
-#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */
-
-#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */
-#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */
-#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */
-
-#define IerRda 0xf /* b0: Enable received data available interrupt */
-
-#endif
-
-#endif /* __SERIAL_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*-----------------------------------------------------------------------
- * Timer value for timer 2, ICLK = 10
- *
- * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1))
- * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
- *
- * SPEED_FCOUNT2 timer 2 counting frequency
- * GCLK CPU clock
- * SPEED_TMR2_PS prescaler
- */
-#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */
-
-/*-----------------------------------------------------------------------
- * Timer value for PIT
- *
- * PIT_TIME = SPEED_PITC / PITRTCLK
- * PITRTCLK = 8192
- */
-#define SPEED_PITC (82 << 16) /* start counting from 82 */
-
-/*
- * The new value for PTA is calculated from
- *
- * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock !)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- * DFBRG For normal mode (no clock reduction) always 0
- * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
- * NCS Number of SDRAM banks (chip selects) on this UPM.
- */
#include <ns16550.h>
#endif
-#include "serial.h"
-
#include "mpsc.h"
DECLARE_GLOBAL_DATA_PTR;
+++ /dev/null
-/* serial.h - mostly useful for DUART serial_init in serial.c */
-
-#ifndef __SERIAL_H__
-#define __SERIAL_H__
-
-#if 0
-
-#define B230400 1
-#define B115200 2
-#define B57600 4
-#define B38400 82
-#define B19200 163
-#define B9600 24
-#define B4800 651
-#define B2400 1302
-#define B1200 2604
-#define B600 5208
-#define B300 10417
-#define B150 20833
-#define B110 28409
-#define BDEFAULT B115200
-
- /* this stuff is important to initialize
- the DUART channels */
-
-#define Scale 0x01L /* distance between port addresses */
-#define COM1 0x000003f8 /* Keyboard */
-#define COM2 0x000002f8 /* Host */
-
-
-/* Port Definitions relative to base COM port addresses */
-#define DataIn (0x00*Scale) /* data input port */
-#define DataOut (0x00*Scale) /* data output port */
-#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */
-#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */
-#define Ier (0x01*Scale) /* interrupt enable register */
-#define Iir (0x02*Scale) /* interrupt identification register */
-#define Lcr (0x03*Scale) /* line control register */
-#define Mcr (0x04*Scale) /* modem control register */
-#define Lsr (0x05*Scale) /* line status register */
-#define Msr (0x06*Scale) /* modem status register */
-
-/* Bit Definitions for above ports */
-#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */
-#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */
-
-#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */
-#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */
-#define McrDflt (McrRts|McrDtr)
-
-#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/
- /* b6: transmitter empty */
-#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */
-
-#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */
-#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */
-#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */
-
-#define IerRda 0xf /* b0: Enable received data available interrupt */
-
-#endif
-
-#endif /* __SERIAL_H__ */
#
# SPDX-License-Identifier: GPL-2.0+
+MINIMAL=
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+obj-y += spl_minimal.o tlb.o law.o
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
+
obj-y += c29xpcie.o
obj-y += cpld.o
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
+endif
2. Program u-boot.bin into NOR flash
=> tftp $loadaddr $uboot
- => protect off eff80000 +$filesize
- => erase eff80000 +$filesize
- => cp.b $loadaddr eff80000 $filesize
+ => protect off eff40000 +$filesize
+ => erase eff40000 +$filesize
+ => cp.b $loadaddr eff40000 $filesize
3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on.
There are four banks in C29XPCIE board, example to change bank booting:
1. Program u-boot.bin into alternate NOR bank
=> tftp $loadaddr $uboot
- => protect off e9f80000 +$filesize
- => erase e9f80000 +$filesize
- => cp.b $loadaddr e9f80000 $filesize
+ => protect off e9f40000 +$filesize
+ => erase e9f40000 +$filesize
+ => cp.b $loadaddr e9f40000 $filesize
2. Switch to alternate NOR bank
=> cpld_cmd reset altbank [bank]
}
#endif
+#ifndef CONFIG_SPL_BUILD
int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rc = 0;
"cpld_cmd dump - display the CPLD registers\n"
#endif
);
+#endif
--- /dev/null
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+ /* relocate environment function pointers etc. */
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ puts("TPL\n");
+#else
+ puts("SPL\n");
+#endif
+
+ nand_boot();
+}
--- /dev/null
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot...\n");
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ puts("SPL\n");
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#ifndef CONFIG_SPL_BUILD
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 1, BOOKE_PAGESZ_64M, 1),
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256K, 1),
#endif
+#endif
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_64K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_256K, 1),
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_256M, 1),
#endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
#define ESDHC_BOOT_IMAGE_SIZE 0x48
#define ESDHC_BOOT_IMAGE_ADDR 0x50
+#define ESDHC_DEFAULT_ENVADDR 0x400
+
int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
{
u8 *tmp_buf;
/* Get the code size from offset 0x48 */
code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE);
+#ifdef CONFIG_ESDHC_HC_BLK_ADDR
+ /*
+ * On soc BSC9131, BSC9132:
+ * In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and
+ * code length of these soc specify the memory address in block address
+ * format. Block length is fixed to 512 bytes as per the SD High
+ * Capacity specification.
+ */
+ u64 tmp;
+
+ if (mmc->high_capacity) {
+ tmp = (u64)code_offset * blklen;
+ tmp += code_len * blklen;
+ } else
+ tmp = code_offset + code_len;
+
+ if ((tmp + CONFIG_ENV_SIZE > mmc->capacity) ||
+ (tmp > 0xFFFFFFFFU))
+ *env_addr = ESDHC_DEFAULT_ENVADDR;
+ else
+ *env_addr = tmp;
+
+ free(tmp_buf);
+
+ return 0;
+#endif
+
*env_addr = code_offset + code_len;
free(tmp_buf);
int board_eth_init(bd_t *bis)
{
struct eth_device *dev;
- int ret;
+ int ret = cpu_eth_init(bis);
- ret = cpu_eth_init(bis);
- if (ret) {
- printf("FEC MXC: %s:failed\n", __func__);
+ if (ret)
return ret;
- }
dev = eth_get_dev_by_name("FEC");
if (!dev) {
int board_eth_init(bd_t *bis)
{
- int ret;
-
setup_iomux_enet();
- ret = cpu_eth_init(bis);
- if (ret)
- printf("FEC MXC: %s:failed\n", __func__);
-
- return ret;
+ return cpu_eth_init(bis);
}
#define BOARD_REV_B 0x200
int board_eth_init(bd_t *bis)
{
- int ret;
-
setup_iomux_enet();
- ret = cpu_eth_init(bis);
- if (ret)
- printf("FEC MXC: %s:failed\n", __func__);
-
- return ret;
+ return cpu_eth_init(bis);
}
int board_early_init_f(void)
#ifdef CONFIG_FEC_MXC
int board_eth_init(bd_t *bis)
{
- int ret;
-
setup_iomux_fec();
- ret = cpu_eth_init(bis);
- if (ret) {
- printf("FEC MXC: %s:failed\n", __func__);
- return ret;
- }
-
- return 0;
+ return cpu_eth_init(bis);
}
static int setup_fec(void)
/* clear gpr1[14], gpr1[18:17] to select anatop clock */
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
- ret = enable_fec_anatop_clock();
+ ret = enable_fec_anatop_clock(ENET_50MHz);
if (ret)
return ret;
2. Burn u-boot.bin into NOR flash
=> tftp $loadaddr $uboot
- => protect off eff80000 +$filesize
- => erase eff80000 +$filesize
- => cp.b $loadaddr eff80000 $filesize
+ => protect off eff40000 +$filesize
+ => erase eff40000 +$filesize
+ => cp.b $loadaddr eff40000 $filesize
3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
==================
1. Burn u-boot.bin into alternate NOR bank
=> tftp $loadaddr $uboot
- => protect off eef80000 +$filesize
- => erase eef80000 +$filesize
- => cp.b $loadaddr eef80000 $filesize
+ => protect off eef40000 +$filesize
+ => erase eef40000 +$filesize
+ => cp.b $loadaddr eef40000 $filesize
2. Switch to alternate NOR bank
=> mw.b ffb00009 1
1. NOR boot
=> tftp 1000000 u-boot.bin
For bank0
- => pro off all;era eff80000 efffffff;cp.b 1000000 eff80000 $filesize
+ => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
For bank1
- => pro off all;era eef80000 eeffffff;cp.b 1000000 eef80000 $filesize
+ => pro off all;era eef40000 eeffffff;cp.b 1000000 eef40000 $filesize
set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
2. NAND boot
NOR flash boot:
=> tftp 1000000 u-boot.bin
=> protect off all
- => erase eff80000 efffffff
- => cp.b 1000000 eff80000 80000
+ => erase eff40000 efffffff
+ => cp.b 1000000 eff40000 c0000
NAND flash boot:
=> tftp 1000000 u-boot-nand.bin
0xef00_0000 - 0xef7f_ffff Alternate bank 8MB
0xe800_0000 - 0xefff_ffff Boot bank 8MB
-0xef78_0000 - 0xef7f_ffff Alternate u-boot address 512KB
-0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB
+0xef74_0000 - 0xef7f_ffff Alternate u-boot address 768KB
+0xeff4_0000 - 0xefff_ffff Boot u-boot address 768KB
Switch settings to boot from the NOR flash banks
------------------------------------------------
To place a new u-boot image in the alternate flash bank and then boot
with that new image temporarily, use this:
tftp 1000000 u-boot.bin
- erase ef780000 ef7fffff
- cp.b 1000000 ef780000 80000
+ erase ef740000 ef7fffff
+ cp.b 1000000 ef740000 c0000
Now to boot from the alternate bank change the SW4[8] from 0 to 1.
To program the image in the boot flash bank:
tftp 1000000 u-boot.bin
protect off all
- erase eff80000 ffffffff
- cp.b 1000000 eff80000 80000
+ erase eff40000 ffffffff
+ cp.b 1000000 eff40000 c0000
Using the Device Tree Source File
---------------------------------
2. Program image
=> tftp 1000000 u-boot.bin
=> protect off all
- => erase eff80000 efffffff
- => cp.b 1000000 eff80000 80000
+ => erase eff40000 efffffff
+ => cp.b 1000000 eff40000 c0000
3. Program RCW
=> tftp 1000000 rcw.bin
4. Program FMAN Firmware ucode
=> tftp 1000000 ucode.bin
=> protect off all
- => erase ef000000 ef0fffff
- => cp.b 1000000 ef000000 2000
+ => erase eff00000 eff3ffff
+ => cp.b 1000000 eff00000 2000
5. Change DIP-switch
SW1[1-5] = 10110
3. Program the PBL image to SDCard
=> tftp 1000000 pbl_sd.bin
=> mmcinfo
- => mmc write 1000000 8 441
+ => mmc write 1000000 8 672
4. Program FMAN Firmware ucode
=> tftp 1000000 ucode.bin
- => mmc write 1000000 46a 10
+ => mmc write 1000000 690 10
5. Change DIP-switch
SW1[1-5] = 01100
NOR Flash memory Map on T1040QDS
--------------------------------
Start End Definition Size
-0xEFF80000 0xEFFFFFFF u-boot (current bank) 512KB
-0xEFF60000 0xEFF7FFFF u-boot env (current bank) 128KB
-0xEFF40000 0xEFF5FFFF FMAN Ucode (current bank) 128KB
+0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
+0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
+0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
0xED300000 0xEFF3FFFF rootfs (alt bank) 44MB + 256KB
0xEC800000 0xEC8FFFF Hardware device tree (alt bank) 1MB
0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
-0xEBF80000 0xEBFFFFFF u-boot (alt bank) 512KB
-0xEBF60000 0xEBF7FFFF u-boot env (alt bank) 128KB
-0xEBF40000 0xEBF5FFFF FMAN ucode (alt bank) 128KB
+0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
+0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
+0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
0xE9300000 0xEBF3FFFF rootfs (current bank) 44MB + 256KB
0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
- {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
- {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
- {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
- {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
- {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
- {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
- {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
- {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
+ {2, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0},
+ {2, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0},
+ {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0},
+ {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0},
+ {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0},
+ {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0},
+ {1, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0},
+ {1, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0},
+ {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0},
+ {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0},
+ {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0},
+ {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0},
{}
};
NOR Flash memory Map
---------------------
Start End Definition Size
-0xEFF80000 0xEFFFFFFF u-boot (current bank) 512KB
-0xEFF60000 0xEFF7FFFF u-boot env (current bank) 128KB
-0xEFF40000 0xEFF5FFFF FMAN Ucode (current bank) 128KB
+0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
+0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
+0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
0xED300000 0xEFF3FFFF rootfs (alt bank) 44MB + 256KB
0xEC800000 0xEC8FFFF Hardware device tree (alt bank) 1MB
0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
-0xEBF80000 0xEBFFFFFF u-boot (alt bank) 512KB
-0xEBF60000 0xEBF7FFFF u-boot env (alt bank) 128KB
-0xEBF40000 0xEBF5FFFF FMAN ucode (alt bank) 128KB
+0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
+0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
+0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
0xE9300000 0xEBF3FFFF rootfs (current bank) 44MB + 256KB
0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
- if (ctrl_num > 2) {
+ if (ctrl_num > 1) {
printf("Not supported controller number %d\n", ctrl_num);
return;
}
else
pbsp = udimms[0];
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
if (pbsp->n_ranks == pdimm->n_ranks &&
(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- popts->twot_en = pbsp->force_2t;
goto found;
}
pbsp_highest = pbsp;
printf("for data rate %lu MT/s\n", ddr_freq);
printf("Trying to use the highest speed (%u) parameters\n",
pbsp_highest->datarate_mhz_high);
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- popts->twot_en = pbsp_highest->force_2t;
} else {
panic("DIMM is not supported by this board");
}
u32 wrlvl_start;
u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
};
/*
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
- {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
- {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
- {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
- {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
- {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
- {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
- {1, 1800, 2, 5, 6, 0x06070709, 0x110a0b08, 0xff, 2, 0},
- {1, 1866, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0},
- {1, 1900, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0},
- {1, 2000, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0},
- {1, 2133, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0},
+ {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
+ {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
+ {2, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
+ {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
+ {2, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b},
+ {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
+ {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
+ {1, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
+ {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
+ {1, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b},
{}
};
static const struct board_specific_parameters rdimm0[] = {
/*
* memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
- {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
- {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
- {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
- {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
- {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
- {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ /* TODO: need tuning these parameters if RDIMM is used */
+ {4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
+ {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
+ {2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
+ {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
+ {1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
+ {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
{}
};
-/*
- * The three slots have slightly different timing. The center values are good
- * for all slots. We use identical speed tables for them. In future use, if
- * DIMMs require separated tables, make more entries as needed.
- */
static const struct board_specific_parameters *udimms[] = {
udimm0,
};
-/*
- * The three slots have slightly different timing. See comments above.
- */
static const struct board_specific_parameters *rdimms[] = {
rdimm0,
};
-
-
#endif
break;
case 0x6c:
case 0x6d:
+ fm_info_set_phy_address(FM1_10GEC1, 4);
+ fm_info_set_phy_address(FM1_10GEC2, 5);
/* SGMII in Slot3 */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
break;
case 0x71:
/* SGMII in Slot3 */
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
break;
default:
- puts("Invalid SerDes1 protocol for T2080QDS\n");
break;
}
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
- };
+ case 3:
+ mdio_mux[i] = EMI1_SLOT3;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ }
break;
case PHY_INTERFACE_MODE_RGMII:
if (i == FM1_DTSEC3)
printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+#ifdef CONFIG_SDCARD
+ puts("SD/MMC\n");
+#elif CONFIG_SPIFLASH
+ puts("SPI\n");
+#else
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
puts("NAND\n");
else
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+#endif
printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
qixis_read_tag(buf), (int)qixis_read_minor());
/* SerDes1 is not enabled */
break;
case 0x1c:
- case 0x95:
case 0xa2:
- case 0x94:
/* SD1(A:D) => SLOT3 SGMII
* SD1(G:H) => SLOT1 SGMII
*/
- QIXIS_WRITE(brdcfg[12], 0x58);
+ QIXIS_WRITE(brdcfg[12], 0x1a);
+ break;
+ case 0x94:
+ case 0x95:
+ /* SD1(A:B) => SLOT3 SGMII@1.25bps
+ * SD1(C:D) => SFP Module, SGMII@3.125bps
+ * SD1(E:H) => SLOT1 SGMII@1.25bps
+ */
+ case 0x96:
+ /* SD1(A:B) => SLOT3 SGMII@1.25bps
+ * SD1(C) => SFP Module, SGMII@3.125bps
+ * SD1(D) => SFP Module, SGMII@1.25bps
+ * SD1(E:H) => SLOT1 PCIe4 x4
+ */
+ QIXIS_WRITE(brdcfg[12], 0x3a);
break;
case 0x51:
/* SD1(A:D) => SLOT3 XAUI
*/
QIXIS_WRITE(brdcfg[12], 0xda);
break;
+ case 0x6e:
+ /* SD1(A:B) => SFP Module, XFI
+ * SD1(C:D) => SLOT3 SGMII
+ * SD1(E:F) => SLOT1 PCIe4 x2
+ * SD1(G:H) => SLOT2 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0xd9);
+ break;
+ case 0xda:
+ /* SD1(A:H) => SLOT3 PCIe3 x8
+ */
+ QIXIS_WRITE(brdcfg[12], 0x0);
+ break;
+ case 0xc8:
+ /* SD1(A) => SLOT3 PCIe3 x1
+ * SD1(B) => SFP Module, SGMII@1.25bps
+ * SD1(C:D) => SFP Module, SGMII@3.125bps
+ * SD1(E:F) => SLOT1 PCIe4 x2
+ * SD1(G:H) => SLOT2 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x79);
+ break;
+ case 0xab:
+ /* SD1(A:D) => SLOT3 PCIe3 x4
+ * SD1(E:H) => SLOT1 PCIe4 x4
+ */
+ QIXIS_WRITE(brdcfg[12], 0x1a);
+ break;
default:
printf("WARNING: unsupported for SerDes1 Protocol %d\n",
srds_prtcl_s1);
case 0x01:
case 0x02:
/* SD2(A:H) => SLOT4 PCIe1 */
- QIXIS_WRITE(brdcfg[13], 0x20);
+ QIXIS_WRITE(brdcfg[13], 0x10);
break;
case 0x15:
case 0x16:
* SD2(E:F) => SLOT5 Aurora
* SD2(G:H) => SATA1,SATA2
*/
- QIXIS_WRITE(brdcfg[13], 0x70);
+ QIXIS_WRITE(brdcfg[13], 0x78);
break;
case 0x1f:
/*
* SD2(A:D) => SLOT4 SRIO2
* SD2(E:H) => SLOT5 SRIO1
*/
- QIXIS_WRITE(brdcfg[13], 0x50);
+ QIXIS_WRITE(brdcfg[13], 0xa0);
+ break;
+ case 0x36:
+ /*
+ * SD2(A:D) => SLOT4 SRIO2
+ * SD2(E:F) => Aurora
+ * SD2(G:H) => SATA1,SATA2
+ */
+ QIXIS_WRITE(brdcfg[13], 0x78);
break;
default:
printf("WARNING: unsupported for SerDes2 Protocol %d\n",
+++ /dev/null
-#
-# (C) Copyright 2012
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mini2440.o
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2009
- * Michel Pollet <buserror@gmail.com>
- *
- * (C) Copyright 2012
- * Gabriel Huau <contact@huau-gabriel.fr>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/s3c2440.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/gpio.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <netdev.h>
-#include "mini2440.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static inline void pll_delay(unsigned long loops)
-{
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b" : "=r" (loops) : "0" (loops));
-}
-
-int board_early_init_f(void)
-{
- struct s3c24x0_clock_power * const clk_power =
- s3c24x0_get_base_clock_power();
-
- /* to reduce PLL lock time, adjust the LOCKTIME register */
- clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
- clk_power->clkdivn = CLKDIVN_VAL;
-
- /* configure UPLL */
- clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
- /* some delay between MPLL and UPLL */
- pll_delay(100);
-
- /* configure MPLL */
- clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
-
- /* some delay between MPLL and UPLL */
- pll_delay(10000);
-
- return 0;
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
- /* IOMUX Port H : UART Configuration */
- gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
- IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
-
- gpio_direction_output(GPH8, 0);
- gpio_direction_output(GPH9, 0);
- gpio_direction_output(GPH10, 0);
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
-
- return 0;
-}
-
-int dram_init(void)
-{
- struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
-
- /*
- * Configuring bus width and timing
- * Initialize clocks for each bank 0..5
- * Bank 3 and 4 are used for DM9000
- */
- writel(BANK_CONF, &memctl->bwscon);
- writel(B0_CONF, &memctl->bankcon[0]);
- writel(B1_CONF, &memctl->bankcon[1]);
- writel(B2_CONF, &memctl->bankcon[2]);
- writel(B3_CONF, &memctl->bankcon[3]);
- writel(B4_CONF, &memctl->bankcon[4]);
- writel(B5_CONF, &memctl->bankcon[5]);
-
- /* Bank 6 and 7 are used for DRAM */
- writel(SDRAM_64MB, &memctl->bankcon[6]);
- writel(SDRAM_64MB, &memctl->bankcon[7]);
-
- writel(MEM_TIMING, &memctl->refresh);
- writel(BANKSIZE_CONF, &memctl->banksize);
- writel(B6_MRSR, &memctl->mrsrb6);
- writel(B7_MRSR, &memctl->mrsrb7);
-
- gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_SIZE);
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_DRIVER_DM9000
- return dm9000_initialize(bis);
-#else
- return 0;
-#endif
-}
+++ /dev/null
-#ifndef __MINI2440_BOARD_CONF_H__
-#define __MINI2440_BOARD_CONF_H__
-
-/* PLL Parameters */
-#define CLKDIVN_VAL 7
-#define M_MDIV 0x7f
-#define M_PDIV 0x2
-#define M_SDIV 0x1
-
-#define U_M_MDIV 0x38
-#define U_M_PDIV 0x2
-#define U_M_SDIV 0x2
-
-/* BWSCON */
-#define DW8 0x0
-#define DW16 0x1
-#define DW32 0x2
-#define WAIT (0x1<<2)
-#define UBLB (0x1<<3)
-
-#define B1_BWSCON (DW32)
-#define B2_BWSCON (DW16)
-#define B3_BWSCON (DW16 + WAIT + UBLB)
-#define B4_BWSCON (DW16 + WAIT + UBLB)
-#define B5_BWSCON (DW16)
-#define B6_BWSCON (DW32)
-#define B7_BWSCON (DW32)
-
-/*
- * Bank Configuration
- */
-#define B0_Tacs 0x0 /* 0clk */
-#define B0_Tcos 0x0 /* 0clk */
-#define B0_Tacc 0x7 /* 14clk */
-#define B0_Tcoh 0x0 /* 0clk */
-#define B0_Tah 0x0 /* 0clk */
-#define B0_Tacp 0x0 /* 0clk */
-#define B0_PMC 0x0 /* normal */
-
-#define B1_Tacs 0x0
-#define B1_Tcos 0x0
-#define B1_Tacc 0x7
-#define B1_Tcoh 0x0
-#define B1_Tah 0x0
-#define B1_Tacp 0x0
-#define B1_PMC 0x0
-
-#define B2_Tacs 0x0
-#define B2_Tcos 0x0
-#define B2_Tacc 0x7
-#define B2_Tcoh 0x0
-#define B2_Tah 0x0
-#define B2_Tacp 0x0
-#define B2_PMC 0x0
-
-#define B3_Tacs 0x0
-#define B3_Tcos 0x3 /* 4clk */
-#define B3_Tacc 0x7
-#define B3_Tcoh 0x1 /* 1clk */
-#define B3_Tah 0x3 /* 4clk */
-#define B3_Tacp 0x0
-#define B3_PMC 0x0
-
-#define B4_Tacs 0x0
-#define B4_Tcos 0x3
-#define B4_Tacc 0x7
-#define B4_Tcoh 0x1
-#define B4_Tah 0x3
-#define B4_Tacp 0x0
-#define B4_PMC 0x0
-
-#define B5_Tacs 0x0
-#define B5_Tcos 0x0
-#define B5_Tacc 0x7
-#define B5_Tcoh 0x0
-#define B5_Tah 0x0
-#define B5_Tacp 0x0
-#define B5_PMC 0x0
-
-/*
- * SDRAM Configuration
- */
-#define SDRAM_MT 0x3 /* SDRAM */
-#define SDRAM_Trcd 0x0 /* 2clk */
-#define SDRAM_SCAN_9 0x1 /* 9bit */
-#define SDRAM_SCAN_10 0x2 /* 10bit */
-
-#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
-
-/*
- * Refresh Parameter
- */
-#define REFEN 0x1 /* Refresh enable */
-#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
-#define Trp 0x1 /* 3clk */
-#define Trc 0x3 /* 7clk */
-#define Tchr 0x0 /* unused */
-#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */
-
-/*
- * MRSR Parameter
- */
-#define BL 0x0
-#define BT 0x0
-#define CL 0x3 /* 3 clocks */
-#define TM 0x0
-#define WBL 0x0
-
-/*
- * BankSize Parameter
- */
-#define BK76MAP 0x2 /* 128MB/128MB */
-#define SCLK_EN 0x1 /* SCLK active */
-#define SCKE_EN 0x1 /* SDRAM power down mode enable */
-#define BURST_EN 0x1 /* Burst enable */
-
-/*
- * Register values
- */
-#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \
- (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
- (B7_BWSCON<<28)))
-
-#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \
- (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))
-#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \
- (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))
-#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \
- (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))
-#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \
- (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))
-#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \
- (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))
-#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \
- (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))
-
-#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \
- (Trc<<18) + (Tchr<<16) + REFCNT
-
-#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7)
-#define B6_MRSR (CL<<4)
-#define B7_MRSR (CL<<4)
-
-#endif
+++ /dev/null
-/*
- * The GENIETV is using the following physical memorymap (copied from
- * the FADS configuration):
- *
- * ff020000 -> ff02ffff : pcmcia
- * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM
- * ff000000 -> ff00ffff : IMAP internal in the cpu
- * 02800000 -> 0287ffff : flash connected to CS0
- * 00000000 -> nnnnnnnn : sdram setup by U-Boot
- *
- * CS pins are connected as follows:
- *
- * CS0 -512Kb boot flash
- * CS1 - SDRAM #1
- * CS2 - SDRAM #2
- * CS3 - Flash #1
- * CS4 - Flash #2
- * CS5 - LON (if present)
- * CS6 - PCMCIA #1
- * CS7 - PCMCIA #2
- *
- * Ports are configured as follows:
- *
- * PA7 - SDRAM banks enable
- */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*-----------------------------------------------------------------------
- * Timer value for timer 2, ICLK = 10
- *
- * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1))
- * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
- *
- * SPEED_FCOUNT2 timer 2 counting frequency
- * GCLK CPU clock
- * SPEED_TMR2_PS prescaler
- */
-#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */
-
-/*-----------------------------------------------------------------------
- * Timer value for PIT
- *
- * PIT_TIME = SPEED_PITC / PITRTCLK
- * PITRTCLK = 8192
- */
-#define SPEED_PITC (82 << 16) /* start counting from 82 */
-
-/*
- * The new value for PTA is calculated from
- *
- * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock !)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- * DFBRG For normal mode (no clock reduction) always 0
- * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
- * NCS Number of SDRAM banks (chip selects) on this UPM.
- */
+++ /dev/null
-/*
- * Copyright (C) 2007 Semihalf
- * Written by Marian Balakowicz <m8@semihalf.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 1 /* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x018D0000
-#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x714F0F00
-#define SDRAM_CONFIG1 0x73711930
-#define SDRAM_CONFIG2 0x46770000
-#define SDRAM_TAPDELAY 0x10000000
* Bank 6 - not used
* Bank 7 - PLD Register
*-----------------------------------------------------------------------------*/
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <configs/MIP405.h>
#include <ppc_asm.tmpl>
* Bank 6 - used to switch on the 12V for the Multipurpose socket
* Bank 7 - Config Register
*-----------------------------------------------------------------------------*/
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <configs/PIP405.h>
#include <ppc_asm.tmpl>
+++ /dev/null
-#
-# board/mx1ads/Makefile
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (c) Copyright 2004
-# Techware Information Technology, Inc.
-# http://www.techware.com.tw/
-#
-# Ming-Len Wu <minglen_wu@techware.com.tw>
-#
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y := mx1ads.o syncflash.o
-obj-y += lowlevel_init.o
+++ /dev/null
-/*
- * board/mx1ads/lowlevel_init.S
- *
- * (c) Copyright 2004
- * Techware Information Technology, Inc.
- * http://www.techware.com.tw/
- *
- * Ming-Len Wu <minglen_wu@techware.com.tw>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-
-#define SDCTL0 0x221000
-#define SDCTL1 0x221004
-
-
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE
-
-.globl lowlevel_init
-lowlevel_init:
-/* memory controller init */
-
- ldr r1, =SDCTL0
-
-/* Set Precharge Command */
-
- ldr r3, =0x92120200
-/* ldr r3, =0x92120251
-*/
- str r3, [r1]
-
-/* Issue Precharge All Commad */
- ldr r3, =0x8200000
- ldr r2, [r3]
-
-/* Set AutoRefresh Command */
- ldr r3, =0xA2120200
- str r3, [r1]
-
-/* Issue AutoRefresh Command */
- ldr r3, =0x8000000
- ldr r2, [r3]
- ldr r2, [r3]
- ldr r2, [r3]
- ldr r2, [r3]
- ldr r2, [r3]
- ldr r2, [r3]
- ldr r2, [r3]
- ldr r2, [r3]
-
-/* Set Mode Register */
- ldr r3, =0xB2120200
- str r3, [r1]
-
-/* Issue Mode Register Command */
- ldr r3, =0x08111800 /* Mode Register Value */
- ldr r2, [r3]
-
-/* Set Normal Mode */
- ldr r3, =0x82124200
- str r3, [r1]
-
-/* everything is fine now */
- mov pc, lr
+++ /dev/null
-/*
- * board/mx1ads/mx1ads.c
- *
- * (c) Copyright 2004
- * Techware Information Technology, Inc.
- * http://www.techware.com.tw/
- *
- * Ming-Len Wu <minglen_wu@techware.com.tw>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-/*#include <mc9328.h>*/
-#include <asm/arch/imx-regs.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define FCLK_SPEED 1
-
-#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
-#define M_MDIV 0xC3
-#define M_PDIV 0x4
-#define M_SDIV 0x1
-#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
-#define M_MDIV 0xA1
-#define M_PDIV 0x3
-#define M_SDIV 0x1
-#endif
-
-#define USB_CLOCK 1
-
-#if USB_CLOCK==0
-#define U_M_MDIV 0xA1
-#define U_M_PDIV 0x3
-#define U_M_SDIV 0x1
-#elif USB_CLOCK==1
-#define U_M_MDIV 0x48
-#define U_M_PDIV 0x3
-#define U_M_SDIV 0x2
-#endif
-
-#if 0
-
-static inline void delay (unsigned long loops)
-{
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0" (loops));
-}
-
-#endif
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-void SetAsynchMode (void)
-{
- __asm__ ("mrc p15,0,r0,c1,c0,0 \n"
- "mov r2, #0xC0000000 \n"
- "orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n");
-}
-
-static u32 mc9328sid;
-
-int board_early_init_f(void)
-{
- mc9328sid = SIDR;
-
- GPCR = 0x000003AB; /* I/O pad driving strength */
-
- /* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
-/* MX1_CS1L = 0x11110601; */
-
- MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
-
-/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
- * BCLK divider to 2 (i.e. BCLK to 48 MHz)
- */
- CSCR = 0xAF000403;
-
- CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */
- CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
-
-/* setup cs4 for cs8900 ethernet */
-
- CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
- CS4L = 0x00001501;
-
- GIUS (0) &= 0xFF3FFFFF;
- GPR (0) &= 0xFF3FFFFF;
-
- readl(0x1500000C);
- readl(0x1500000C);
-
- SetAsynchMode ();
-
- icache_enable ();
- dcache_enable ();
-
-/* set PERCLKs */
- PCDR = 0x00000055; /* set PERCLKS */
-
-/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
- * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
- * all sources selected as normal interrupt
- */
-
-/* MX1_INTTYPEH = 0;
- MX1_INTTYPEL = 0;
-*/
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_MX1ADS;
-
- gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */
-
- return 0;
-}
-
-int board_late_init (void)
-{
-
- setenv ("stdout", "serial");
- setenv ("stderr", "serial");
-
- switch (mc9328sid) {
- case 0x0005901d:
- printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",
- mc9328sid);
- break;
- case 0x04d4c01d:
- printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",
- mc9328sid);
- break;
- case 0x00d4c01d:
- printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",
- mc9328sid);
- break;
-
- default:
- printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",
- mc9328sid);
- break;
- }
- return 0;
-}
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_CS8900
- rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
-#endif
- return rc;
-}
-#endif
+++ /dev/null
-/*
- * board/mx1ads/syncflash.c
- *
- * (c) Copyright 2004
- * Techware Information Technology, Inc.
- * http://www.techware.com.tw/
- *
- * Ming-Len Wu <minglen_wu@techware.com.tw>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-/*#include <mc9328.h>*/
-#include <asm/arch/imx-regs.h>
-
-typedef unsigned long * p_u32;
-
-/* 4Mx16x2 IAM=0 CSD1 */
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* Following Setting is for CSD1 */
-#define SFCTL 0x00221004
-#define reg_SFCTL __REG(SFCTL)
-
-#define SYNCFLASH_A10 (0x00100000)
-
-#define CMD_NORMAL (0x81020300) /* Normal Mode */
-#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */
-#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */
-#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */
-#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */
-#define CMD_PROGRAM (CMD_NORMAL + 0x70000000)
-
-#define MODE_REG_VAL (CONFIG_SYS_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */
-
-/* LCR Command */
-#define LCR_READSTATUS (0x0001C000) /* 0x70 */
-#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */
-#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */
-#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */
-#define LCR_SR_CLEAR (0x00014000) /* 0x50 */
-
-/* Get Status register */
-u32 SF_SR(void) {
- u32 tmp;
-
- reg_SFCTL = CMD_PROGRAM;
- tmp = __REG(CONFIG_SYS_FLASH_BASE);
-
- reg_SFCTL = CMD_NORMAL;
-
- reg_SFCTL = CMD_LCR; /* Activate LCR Mode */
- __REG(CONFIG_SYS_FLASH_BASE + LCR_SR_CLEAR);
-
- return tmp;
-}
-
-/* check if SyncFlash is ready */
-u8 SF_Ready(void) {
- u32 tmp;
-
- tmp = SF_SR();
-
- if ((tmp & 0x00800000) && (tmp & 0x001C0000)) {
- printf ("SyncFlash Error code %08x\n",tmp);
- };
-
- if ((tmp & 0x00000080) && (tmp & 0x0000001C)) {
- printf ("SyncFlash Error code %08x\n",tmp);
- };
-
- if (tmp == 0x00800080) /* Test Bit 7 of SR */
- return 1;
- else
- return 0;
-}
-
-/* Issue the precharge all command */
-void SF_PrechargeAll(void) {
-
- /* Set Precharge Command */
- reg_SFCTL = CMD_PREC;
- /* Issue Precharge All Command */
- __REG(CONFIG_SYS_FLASH_BASE + SYNCFLASH_A10);
-}
-
-/* set SyncFlash to normal mode */
-void SF_Normal(void) {
-
- SF_PrechargeAll();
-
- reg_SFCTL = CMD_NORMAL;
-}
-
-/* Erase SyncFlash */
-void SF_Erase(u32 RowAddress) {
-
- reg_SFCTL = CMD_NORMAL;
- __REG(RowAddress);
-
- reg_SFCTL = CMD_PREC;
- __REG(RowAddress);
-
- reg_SFCTL = CMD_LCR; /* Set LCR mode */
- __REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */
-
- reg_SFCTL = CMD_NORMAL; /* return to Normal mode */
- __REG(RowAddress) = 0xD0D0D0D0; /* Confirm */
-
- while(!SF_Ready());
-}
-
-void SF_NvmodeErase(void) {
- SF_PrechargeAll();
-
- reg_SFCTL = CMD_LCR; /* Set to LCR mode */
- __REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */
-
- reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
- __REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */
-
- while(!SF_Ready());
-}
-
-void SF_NvmodeWrite(void) {
- SF_PrechargeAll();
-
- reg_SFCTL = CMD_LCR; /* Set to LCR mode */
- __REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */
-
- reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
- __REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */
-}
-
-/****************************************************************************************/
-
-ulong flash_init(void) {
- int i, j;
-
-/* Turn on CSD1 for negating RESETSF of SyncFLash */
-
- reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */
- udelay(200);
-
- reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */
- __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */
-
- SF_Normal();
-
- i = 0;
-
- flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC;
-
- flash_info[i].size = FLASH_BANK_SIZE;
- flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-
- memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
-
- for (j = 0; j < flash_info[i].sector_count; j++) {
- flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + j * 0x00100000;
- }
-
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
-
- return FLASH_BANK_SIZE;
-}
-
-void flash_print_info (flash_info_t *info) {
-
- int i;
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case (FLASH_MAN_MT & FLASH_VENDMASK):
- printf("Micron: ");
- break;
- default:
- printf("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
- printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- return;
- break;
- }
-
- printf(" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf(" Sector Start Addresses: ");
-
- for (i = 0; i < info->sector_count; i++) {
- if ((i % 5) == 0)
- printf ("\n ");
-
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
-
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------*/
-
-int flash_erase (flash_info_t *info, int s_first, int s_last) {
- int iflag, cflag, prot, sect;
- int rc = ERR_OK;
-
-/* first look for protection bits */
-
- if (info->flash_id == FLASH_UNKNOWN)
- return ERR_UNKNOWN_FLASH_TYPE;
-
- if ((s_first < 0) || (s_first > s_last))
- return ERR_INVAL;
-
- if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
- return ERR_UNKNOWN_FLASH_VENDOR;
-
- prot = 0;
-
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect])
- prot++;
- }
-
- if (prot) {
- printf("protected!\n");
- return ERR_PROTECTED;
- }
-/*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
-
- cflag = icache_status();
- icache_disable();
- iflag = disable_interrupts();
-
-/* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last && !ctrlc(); sect++) {
-
- printf("Erasing sector %2d ... ", sect);
-
-/* arm simple, non interrupt dependent timer */
-
- get_timer(0);
-
- SF_NvmodeErase();
- SF_NvmodeWrite();
-
- SF_Erase(CONFIG_SYS_FLASH_BASE + (0x0100000 * sect));
- SF_Normal();
-
- printf("ok.\n");
- }
-
- if (ctrlc())
- printf("User Interrupt!\n");
-
- if (iflag)
- enable_interrupts();
-
- if (cflag)
- icache_enable();
-
- return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash.
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
- int i;
-
- for(i = 0; i < cnt; i += 4) {
-
- SF_PrechargeAll();
-
- reg_SFCTL = CMD_PROGRAM; /* Enter SyncFlash Program mode */
- __REG(addr + i) = __REG((u32)src + i);
-
- while(!SF_Ready());
- }
-
- SF_Normal();
-
- return ERR_OK;
-}
CONFIG_TEGRA_BOARD_STRING
};
-#ifndef CONFIG_SPL_BUILD
-/*
- * Routine: timer_init
- * Description: init the timestamp and lastinc value
- */
-int timer_init(void)
-{
- return 0;
-}
-#endif
-
void __pin_mux_usb(void)
{
}
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * BK Id: SCCS/s.errno.h 1.9 06/05/01 21:45:21 paulus
- */
-#ifndef _MV_PPC_ERRNO_H
-#define _MV_PPC_ERRNO_H
-
-#define EPERM 1 /* Operation not permitted */
-#define ENOENT 2 /* No such file or directory */
-#define ESRCH 3 /* No such process */
-#define EINTR 4 /* Interrupted system call */
-#define EIO 5 /* I/O error */
-#define ENXIO 6 /* No such device or address */
-#define E2BIG 7 /* Arg list too long */
-#define ENOEXEC 8 /* Exec format error */
-#define EBADF 9 /* Bad file number */
-#define ECHILD 10 /* No child processes */
-#define EAGAIN 11 /* Try again */
-#define ENOMEM 12 /* Out of memory */
-#define EACCES 13 /* Permission denied */
-#define EFAULT 14 /* Bad address */
-#define ENOTBLK 15 /* Block device required */
-#define EBUSY 16 /* Device or resource busy */
-#define EEXIST 17 /* File exists */
-#define EXDEV 18 /* Cross-device link */
-#define ENODEV 19 /* No such device */
-#define ENOTDIR 20 /* Not a directory */
-#define EISDIR 21 /* Is a directory */
-#define EINVAL 22 /* Invalid argument */
-#define ENFILE 23 /* File table overflow */
-#define EMFILE 24 /* Too many open files */
-#define ENOTTY 25 /* Not a typewriter */
-#define ETXTBSY 26 /* Text file busy */
-#define EFBIG 27 /* File too large */
-#define ENOSPC 28 /* No space left on device */
-#define ESPIPE 29 /* Illegal seek */
-#define EROFS 30 /* Read-only file system */
-#define EMLINK 31 /* Too many links */
-#define EPIPE 32 /* Broken pipe */
-#define EDOM 33 /* Math argument out of domain of func */
-#define ERANGE 34 /* Math result not representable */
-#define EDEADLK 35 /* Resource deadlock would occur */
-#define ENAMETOOLONG 36 /* File name too long */
-#define ENOLCK 37 /* No record locks available */
-#define ENOSYS 38 /* Function not implemented */
-#define ENOTEMPTY 39 /* Directory not empty */
-#define ELOOP 40 /* Too many symbolic links encountered */
-#define EWOULDBLOCK EAGAIN /* Operation would block */
-#define ENOMSG 42 /* No message of desired type */
-#define EIDRM 43 /* Identifier removed */
-#define ECHRNG 44 /* Channel number out of range */
-#define EL2NSYNC 45 /* Level 2 not synchronized */
-#define EL3HLT 46 /* Level 3 halted */
-#define EL3RST 47 /* Level 3 reset */
-#define ELNRNG 48 /* Link number out of range */
-#define EUNATCH 49 /* Protocol driver not attached */
-#define ENOCSI 50 /* No CSI structure available */
-#define EL2HLT 51 /* Level 2 halted */
-#define EBADE 52 /* Invalid exchange */
-#define EBADR 53 /* Invalid request descriptor */
-#define EXFULL 54 /* Exchange full */
-#define ENOANO 55 /* No anode */
-#define EBADRQC 56 /* Invalid request code */
-#define EBADSLT 57 /* Invalid slot */
-#define EDEADLOCK 58 /* File locking deadlock error */
-#define EBFONT 59 /* Bad font file format */
-#define ENOSTR 60 /* Device not a stream */
-#define ENODATA 61 /* No data available */
-#define ETIME 62 /* Timer expired */
-#define ENOSR 63 /* Out of streams resources */
-#define ENONET 64 /* Machine is not on the network */
-#define ENOPKG 65 /* Package not installed */
-#define EREMOTE 66 /* Object is remote */
-#define ENOLINK 67 /* Link has been severed */
-#define EADV 68 /* Advertise error */
-#define ESRMNT 69 /* Srmount error */
-#define ECOMM 70 /* Communication error on send */
-#define EPROTO 71 /* Protocol error */
-#define EMULTIHOP 72 /* Multihop attempted */
-#define EDOTDOT 73 /* RFS specific error */
-#define EBADMSG 74 /* Not a data message */
-#define EOVERFLOW 75 /* Value too large for defined data type */
-#define ENOTUNIQ 76 /* Name not unique on network */
-#define EBADFD 77 /* File descriptor in bad state */
-#define EREMCHG 78 /* Remote address changed */
-#define ELIBACC 79 /* Can not access a needed shared library */
-#define ELIBBAD 80 /* Accessing a corrupted shared library */
-#define ELIBSCN 81 /* .lib section in a.out corrupted */
-#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
-#define ELIBEXEC 83 /* Cannot exec a shared library directly */
-#define EILSEQ 84 /* Illegal byte sequence */
-#define ERESTART 85 /* Interrupted system call should be restarted */
-#define ESTRPIPE 86 /* Streams pipe error */
-#define EUSERS 87 /* Too many users */
-#define ENOTSOCK 88 /* Socket operation on non-socket */
-#define EDESTADDRREQ 89 /* Destination address required */
-#define EMSGSIZE 90 /* Message too long */
-#define EPROTOTYPE 91 /* Protocol wrong type for socket */
-#define ENOPROTOOPT 92 /* Protocol not available */
-#define EPROTONOSUPPORT 93 /* Protocol not supported */
-#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
-#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
-#define EPFNOSUPPORT 96 /* Protocol family not supported */
-#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
-#define EADDRINUSE 98 /* Address already in use */
-#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
-#define ENETDOWN 100 /* Network is down */
-#define ENETUNREACH 101 /* Network is unreachable */
-#define ENETRESET 102 /* Network dropped connection because of reset */
-#define ECONNABORTED 103 /* Software caused connection abort */
-#define ECONNRESET 104 /* Connection reset by peer */
-#define ENOBUFS 105 /* No buffer space available */
-#define EISCONN 106 /* Transport endpoint is already connected */
-#define ENOTCONN 107 /* Transport endpoint is not connected */
-#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
-#define ETOOMANYREFS 109 /* Too many references: cannot splice */
-#define ETIMEDOUT 110 /* Connection timed out */
-#define ECONNREFUSED 111 /* Connection refused */
-#define EHOSTDOWN 112 /* Host is down */
-#define EHOSTUNREACH 113 /* No route to host */
-#define EALREADY 114 /* Operation already in progress */
-#define EINPROGRESS 115 /* Operation now in progress */
-#define ESTALE 116 /* Stale NFS file handle */
-#define EUCLEAN 117 /* Structure needs cleaning */
-#define ENOTNAM 118 /* Not a XENIX named type file */
-#define ENAVAIL 119 /* No XENIX semaphores available */
-#define EISNAM 120 /* Is a named type file */
-#define EREMOTEIO 121 /* Remote I/O error */
-#define EDQUOT 122 /* Quota exceeded */
-
-#define ENOMEDIUM 123 /* No medium found */
-#define EMEDIUMTYPE 124 /* Wrong medium type */
-
-/* Should never be seen by user programs */
-#define ERESTARTSYS 512
-#define ERESTARTNOINTR 513
-#define ERESTARTNOHAND 514 /* restart if no handler.. */
-#define ENOIOCTLCMD 515 /* No ioctl command */
-
-#define _LAST_ERRNO 515
-
-#endif
#include <linux/compiler.h>
#include "../../Marvell/include/memory.h"
-#include "serial.h"
#include "mpsc.h"
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * modified for marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* serial.h - mostly useful for DUART serial_init in serial.c */
-
-#ifndef __SERIAL_H__
-#define __SERIAL_H__
-
-#if 0
-
-#define B230400 1
-#define B115200 2
-#define B57600 4
-#define B38400 82
-#define B19200 163
-#define B9600 24
-#define B4800 651
-#define B2400 1302
-#define B1200 2604
-#define B600 5208
-#define B300 10417
-#define B150 20833
-#define B110 28409
-#define BDEFAULT B115200
-
- /* this stuff is important to initialize
- the DUART channels */
-
-#define Scale 0x01L /* distance between port addresses */
-#define COM1 0x000003f8 /* Keyboard */
-#define COM2 0x000002f8 /* Host */
-
-
-/* Port Definitions relative to base COM port addresses */
-#define DataIn (0x00*Scale) /* data input port */
-#define DataOut (0x00*Scale) /* data output port */
-#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */
-#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */
-#define Ier (0x01*Scale) /* interrupt enable register */
-#define Iir (0x02*Scale) /* interrupt identification register */
-#define Lcr (0x03*Scale) /* line control register */
-#define Mcr (0x04*Scale) /* modem control register */
-#define Lsr (0x05*Scale) /* line status register */
-#define Msr (0x06*Scale) /* modem status register */
-
-/* Bit Definitions for above ports */
-#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */
-#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */
-
-#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */
-#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */
-#define McrDflt (McrRts|McrDtr)
-
-#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/
- /* b6: transmitter empty */
-#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */
-
-#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */
-#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */
-#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */
-
-#define IerRda 0xf /* b0: Enable received data available interrupt */
-
-#endif
-
-#endif /* __SERIAL_H__ */
u32 end_tag;
};
+struct msg_set_power_state {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_set_power_state set_power_state;
+ u32 end_tag;
+};
+
struct msg_get_clock_rate {
struct bcm2835_mbox_hdr hdr;
struct bcm2835_mbox_tag_get_clock_rate get_clock_rate;
return 0;
}
+static int power_on_module(u32 module)
+{
+ ALLOC_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1, 16);
+ int ret;
+
+ BCM2835_MBOX_INIT_HDR(msg_pwr);
+ BCM2835_MBOX_INIT_TAG(&msg_pwr->set_power_state,
+ SET_POWER_STATE);
+ msg_pwr->set_power_state.body.req.device_id = module;
+ msg_pwr->set_power_state.body.req.state =
+ BCM2835_MBOX_SET_POWER_STATE_REQ_ON |
+ BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT;
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN,
+ &msg_pwr->hdr);
+ if (ret) {
+ printf("bcm2835: Could not set module %u power state\n",
+ module);
+ return -1;
+ }
+
+ return 0;
+}
+
int board_init(void)
{
gd->bd->bi_boot_params = 0x100;
- return 0;
+ return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD);
}
int board_mmc_init(void)
ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 16);
int ret;
+ power_on_module(BCM2835_MBOX_POWER_DEVID_SDHCI);
+
BCM2835_MBOX_INIT_HDR(msg_clk);
BCM2835_MBOX_INIT_TAG(&msg_clk->get_clock_rate, GET_CLOCK_RATE);
msg_clk->get_clock_rate.body.req.clock_id = BCM2835_MBOX_CLOCK_ID_EMMC;
return 0;
}
+void arch_preboot_os(void)
+{
+ /* Disable TMU0 */
+ mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+}
+
/* LSI pin pull-up control */
#define PUPR5 0xe6060114
#define PUPR5_ETH 0x3FFC0000
return 0;
}
+void arch_preboot_os(void)
+{
+ /* Disable TMU0 */
+ mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+}
+
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
*/
#include <common.h>
+#include <usb.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/dwmmc.h>
+#include <asm/arch/gpio.h>
#include <asm/arch/power.h>
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_USB_EHCI_EXYNOS
+int board_usb_init(int index, enum usb_init_type init)
+{
+ struct exynos5_gpio_part1 *gpio = (struct exynos5_gpio_part1 *)
+ samsung_get_base_gpio_part1();
+
+ /* Configure gpios for usb 3503 hub:
+ * disconnect, toggle reset and connect
+ */
+ s5p_gpio_direction_output(&gpio->d1, 7, 0);
+ s5p_gpio_direction_output(&gpio->x3, 5, 0);
+
+ s5p_gpio_direction_output(&gpio->x3, 5, 1);
+ s5p_gpio_direction_output(&gpio->d1, 7, 1);
+
+ return 0;
+}
+#endif
+
int board_init(void)
{
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
* For PMIC the I2C bus is named as I2C5, but it is connected
* to logical I2C adapter 0
*/
- ret = pmic_init(I2C_5);
+ ret = pmic_init(I2C_0);
if (ret)
return ret;
return os_get_nsec() / 1000;
}
-int timer_init(void)
-{
- return 0;
-}
-
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*-----------------------------------------------------------------------
- * Timer value for timer 2, ICLK = 10
- *
- * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1))
- * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
- *
- * SPEED_FCOUNT2 timer 2 counting frequency
- * GCLK CPU clock
- * SPEED_TMR2_PS prescaler
- */
-#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */
-
-/*-----------------------------------------------------------------------
- * Timer value for PIT
- *
- * PIT_TIME = SPEED_PITC / PITRTCLK
- * PITRTCLK = 8192
- */
-#define SPEED_PITC (82 << 16) /* start counting from 82 */
-
-/*
- * The new value for PTA is calculated from
- *
- * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock !)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- * DFBRG For normal mode (no clock reduction) always 0
- * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
- * NCS Number of SDRAM banks (chip selects) on this UPM.
- */
#include <config.h>
#include <asm/ppc4xx.h>
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
--- /dev/null
+#
+# (C) Copyright 2013 Freescale Semiconductor, Inc.
+# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+# Copyright (C) 2013, Jon Nettleton <jon.nettleton@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := hummingboard.o
--- /dev/null
+U-Boot for SolidRun Hummingboard
+--------------------------------
+
+This file contains information for the port of U-Boot to the Hummingboard.
+
+For more details about Hummingboard, please refer to:
+http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware
+
+(Carrier-One was the previous name of Hummingboard).
+
+Building U-boot for Hummingboard
+--------------------------------
+
+To build U-Boot for the Hummingboard Solo version:
+
+$ make hummingboard_solo_config
+$ make
+
+Flashing U-boot into the SD card
+--------------------------------
+
+- After the 'make' command completes, the generated 'u-boot.imx' binary must be
+flashed into the SD card:
+
+$ sudo dd if=u-boot.imx of=/dev/mmcblk0 bs=1k seek=1; sync
+
+(Note - the SD card node may vary, so adjust this as needed).
+
+Also, a more detailed explanation on how to format the SD card is available
+at doc/README.imximage.
+
+- Insert the micro SD card into the slot located in the bottom of the board
+
+- Connect a 3.3V USB to serial converter cable to the host PC. The MX6 UART
+signals are available in the 26 pin connector as shown at:
+http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware
+(Check for "26 pin header layout").
+
+- Power up the board via USB cable (CON201) and U-boot messages will appear in
+the serial console.
--- /dev/null
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
+ *
+ * Authors: Fabio Estevam <fabio.estevam@freescale.com>
+ Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
+ PAD_CTL_HYS)
+
+#define USDHC_PAD_GPIO_CTRL (PAD_CTL_PUS_22K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define ETH_PHY_RESET IMX_GPIO_NR(4, 15)
+
+int dram_init(void)
+{
+ gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024);
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_GPIO_4__SD2_CD_B | MUX_PAD_CTRL(USDHC_PAD_GPIO_CTRL),
+};
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ { USDHC2_BASE_ADDR },
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1; /* SD card is the boot medium, so always present */
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+static iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* AR8035 reset */
+ MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ /* AR8035 interrupt */
+ MX6_PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* GPIO16 -> AR8035 25MHz */
+ MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+};
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+ gpio_direction_output(ETH_PHY_RESET, 0);
+ mdelay(2);
+ gpio_set_value(ETH_PHY_RESET, 1);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct iomuxc_base_regs *const iomuxc_regs =
+ (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+
+ int ret = enable_fec_anatop_clock(ENET_25MHz);
+ if (ret)
+ return ret;
+
+ /* set gpr1[ENET_CLK_SEL] */
+ setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
+ setup_iomux_enet();
+
+ ret = cpu_eth_init(bis);
+ if (ret)
+ printf("FEC MXC: %s:failed\n", __func__);
+
+ return ret;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Hummingboard\n");
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "../mx6-microsom/ddr-800mhz-32bit-setup.cfg"
+#include "../mx6-microsom/800mhz_2x128mx16.cfg"
+#include "../mx6-microsom/clocks.cfg"
--- /dev/null
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* ZQ Calibrations */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
+/* write leveling */
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x005a0057
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x004a0052
+/*
+ * DQS gating, read delay, write delay calibration values
+ * based on calibration compare of 0x00ffff00
+ */
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x02480240
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02340230
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40404440
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x38343034
+/* read data bit delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+/* Complete calibration by forced measurement */
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+
+/*
+ * MMDC init:
+ * in DDR3, 32-bit mode, only MMDC0 is initiated:
+ */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333040
+
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x3f435313
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8b63
+
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
+/* CS0_END - 0x2fffffff, 512M */
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
+
+/* MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled */
+DATA 4, 0x021b0400, 0x11420000
+
+/* MMDC0_MDCTL- row-14bits; col-10bits; burst length 8;32-bit data bus */
+DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
+
+/*
+ * Initialize 2GB DDR3 - Hynix H5TQ2G63BFR-H9C
+ * MR2
+ */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032
+/* MR3 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+/* MR1 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031
+/* MR0 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
+/* ZQ calibration */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+/* final DDR setup */
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
--- /dev/null
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en = 1 --> CKO1 enabled
+ * cko1_div = 111 --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
--- /dev/null
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * DDR3 settings
+ * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
+ * memory bus width: 64 bits x16/x32/x64
+ * MX6DL ddr is limited to 800 MHz(400 MHz clock)
+ * memory bus width: 64 bits x16/x32/x64
+ * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
+ * memory bus width: 32 bits x16/x32
+ */
+/* DDR IO TYPE */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+/* Clock */
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028
+/* Address */
+DATA 4, MX6_IOM_DRAM_CAS, 0x00000010
+DATA 4, MX6_IOM_DRAM_RAS, 0x00000010
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000010
+/* Control */
+DATA 4, MX6_IOM_DRAM_RESET, 0x00000010
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000010
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000010
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000010
+
+/*
+ * Data Strobe: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DDR_INPUT=0, CMOS,
+ * CMOS mode saves power, but have less timing margin in case of DDR
+ * timing issue on your board you can try DDR_MODE: [= 0x00020000]
+ */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000
+
+/*
+ * DATA:IOMUXC_SW_PAD_CTL_GRP_DDRMODE - DDR_INPUT=0, CMOS,
+ * CMOS mode saves power, but have less timing margin in case of DDR
+ * timing issue on your board you can try DDR_MODE: [= 0x00020000]
+ */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000000
+
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000
.text.0 :
{
arch/arm/cpu/pxa/start.o (.text*)
+ arch/arm/lib/built-in.o (.text*)
board/vpac270/built-in.o (.text*)
drivers/mtd/onenand/built-in.o (.text*)
}
#include <config.h>
#include <asm/ppc4xx.h>
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <config.h>
#include <asm/ppc4xx.h>
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
int board_eth_init(bd_t *bis)
{
- int ret;
-
setup_iomux_enet();
- ret = cpu_eth_init(bis);
- if (ret)
- printf("FEC MXC: %s:failed\n", __func__);
-
- return ret;
+ return cpu_eth_init(bis);
}
int board_early_init_f(void)
# Status, Arch, CPU:SPLCPU, SoC, Vendor, Board name, Target, Options, Maintainers
###########################################################################################################
+Active aarch64 armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng <fenghua@phytium.com.cn>
Active arm arm1136 - armltd integrator integratorcp_cm1136 integratorcp:CM1136 Linus Walleij <linus.walleij@linaro.org>
Active arm arm1136 mx31 - - imx31_phycore - -
Active arm arm1136 mx31 davedenx - qong - Wolfgang Denk <wd@denx.de>
Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2_ram eb_cpux9k2:RAMBOOT Jens Scharsig <esw@bus-elektronik.de>
Active arm arm920t at91 eukrea cpuat91 cpuat91 cpuat91 Eric Benard <eric@eukrea.com>
Active arm arm920t at91 eukrea cpuat91 cpuat91_ram cpuat91:RAMBOOT Eric Benard <eric@eukrea.com>
-Active arm arm920t imx - - mx1ads - -
Active arm arm920t imx - - scb9328 - Torsten Koschorrek <koschorrek@synertronixx.de>
Active arm arm920t ks8695 - - cm4008 - Greg Ungerer <greg.ungerer@opengear.com>
Active arm arm920t ks8695 - - cm41xx - -
-Active arm arm920t s3c24x0 friendlyarm mini2440 mini2440 - Gabriel Huau <contact@huau-gabriel.fr>
Active arm arm920t s3c24x0 mpl vcma9 VCMA9 - David Müller <d.mueller@elsoft.ch>
Active arm arm920t s3c24x0 samsung - smdk2410 - David Müller <d.mueller@elsoft.ch>
Active arm arm926ejs - armltd integrator integratorap_cm926ejs integratorap:CM926EJ_S Linus Walleij <linus.walleij@linaro.org>
Active arm arm926ejs at91 ronetix pm9261 pm9261 pm9261:AT91SAM9261 Ilko Iliev <iliev@ronetix.at>
Active arm arm926ejs at91 ronetix pm9263 pm9263 pm9263:AT91SAM9263 Ilko Iliev <iliev@ronetix.at>
Active arm arm926ejs at91 ronetix pm9g45 pm9g45 pm9g45:AT91SAM9G45 Ilko Iliev <iliev@ronetix.at>
-Active arm arm926ejs at91 taskit stamp9g20 portuxg20 stamp9g20:AT91SAM9G20,PORTUXG20 Markus Hubig <mhubig@imko.de>
-Active arm arm926ejs at91 taskit stamp9g20 stamp9g20 stamp9g20:AT91SAM9G20 Markus Hubig <mhubig@imko.de>
-Active arm arm926ejs at91 siemens taurus axm taurus:AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM Heiko Schocher <hs@denx.de>
Active arm arm926ejs at91 siemens corvus corvus corvus:AT91SAM9M10G45,SYS_USE_NANDFLASH Heiko Schocher <hs@denx.de>
+Active arm arm926ejs at91 siemens taurus axm taurus:AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM Heiko Schocher <hs@denx.de>
Active arm arm926ejs at91 siemens taurus taurus taurus:AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS Heiko Schocher <hs@denx.de>
+Active arm arm926ejs at91 taskit stamp9g20 portuxg20 stamp9g20:AT91SAM9G20,PORTUXG20 Markus Hubig <mhubig@imko.de>
+Active arm arm926ejs at91 taskit stamp9g20 stamp9g20 stamp9g20:AT91SAM9G20 Markus Hubig <mhubig@imko.de>
Active arm arm926ejs davinci ait cam_enc_4xx cam_enc_4xx cam_enc_4xx Heiko Schocher <hs@denx.de>
Active arm arm926ejs davinci Barix ipam390 ipam390 - Heiko Schocher <hs@denx.de>
Active arm arm926ejs davinci davinci da8xxevm da830evm - Nick Thompson <nick.thompson@gefanuc.com>
Active arm arm926ejs kirkwood iomega - iconnect - Luka Perkov <luka@openwrt.org>
Active arm arm926ejs kirkwood karo tk71 tk71 - -
Active arm arm926ejs kirkwood keymile km_arm km_kirkwood km_kirkwood:KM_KIRKWOOD Valentin Longchamp <valentin.longchamp@keymile.com>
-Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_pci km_kirkwood:KM_KIRKWOOD_PCI Valentin Longchamp <valentin.longchamp@keymile.com>
Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_128m16 km_kirkwood:KM_KIRKWOOD_128M16 Valentin Longchamp <valentin.longchamp@keymile.com>
+Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_pci km_kirkwood:KM_KIRKWOOD_PCI Valentin Longchamp <valentin.longchamp@keymile.com>
Active arm arm926ejs kirkwood keymile km_arm kmcoge5un km_kirkwood:KM_COGE5UN Valentin Longchamp <valentin.longchamp@keymile.com>
Active arm arm926ejs kirkwood keymile km_arm kmnusa km_kirkwood:KM_NUSA Valentin Longchamp <valentin.longchamp@keymile.com>
Active arm arm926ejs kirkwood keymile km_arm kmsuv31 km_kirkwood:KM_SUV31 Valentin Longchamp <valentin.longchamp@keymile.com>
Active arm armv7 exynos samsung origen origen - Chander Kashyap <k.chander@samsung.com>
Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap <k.chander@samsung.com>
Active arm armv7 exynos samsung smdk5250 snow - Rajeshwari Shinde <rajeshwari.s@samsung.com>
-Active arm armv7 exynos samsung smdk5420 smdk5420 - Rajeshwari Shinde <rajeshwari.s@samsung.com>
+Active arm armv7 exynos samsung smdk5420 smdk5420 - Rajeshwari Shinde <rajeshwari.s@samsung.com>
Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap <k.chander@samsung.com>
Active arm armv7 exynos samsung trats trats - Lukasz Majewski <l.majewski@samsung.com>
Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek <p.wilczek@samsung.com>
Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg -
Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg -
Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic <sbabic@denx.de>
-Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese <sr@denx.de>
Active arm armv7 mx6 boundary nitrogen6x mx6qsabrelite nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE Eric Nelson <eric.nelson@boundarydevices.com>
Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 Eric Nelson <eric.nelson@boundarydevices.com>
Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam@freescale.com>
-Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese <sr@denx.de>
+Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <jon.nettleton@gmail.com>
Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com>
Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com>
Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat <raph@8d.com>
Active arm armv7 omap5 ti omap5_uevm omap5_uevm - -
Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
-Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
-Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 s5pc1xx samsung goni s5p_goni - Mateusz Zalega <m.zalega@samsung.com>
Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org>
Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com>
-Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
-Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
-Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
-Active arm armv7 zynq xilinx zynq zynq_zc770_xm010 zynq_zc770:ZC770_XM010 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
-Active arm armv7 zynq xilinx zynq zynq_zc770_xm012 zynq_zc770:ZC770_XM012 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
-Active arm armv7 zynq xilinx zynq zynq_zc770_xm013 zynq_zc770:ZC770_XM013 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active arm armv7 zynq xilinx zynq zynq_zc770_xm010 zynq_zc770:ZC770_XM010 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active arm armv7 zynq xilinx zynq zynq_zc770_xm012 zynq_zc770:ZC770_XM012 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active arm armv7 zynq xilinx zynq zynq_zc770_xm013 zynq_zc770:ZC770_XM013 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com>
Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel <alban.bedel@avionic-design.de>
Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel <alban.bedel@avionic-design.de>
Active arm armv7:arm720t tegra20 avionic-design tec tec - Alban Bedel <alban.bedel@avionic-design.de>
-Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel <alban.bedel@avionic-design.de>
Active arm armv7:arm720t tegra20 compal paz00 paz00 - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
Active arm armv7:arm720t tegra20 compulab trimslice trimslice - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
Active arm armv7:arm720t tegra20 nvidia harmony harmony - Tom Warren <twarren@nvidia.com>
Active arm armv7:arm720t tegra20 nvidia ventana ventana - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
Active arm armv7:arm720t tegra20 nvidia whistler whistler - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
Active arm armv7:arm720t tegra20 toradex colibri_t20_iris colibri_t20_iris - Lucas Stach <dev@lynxeye.de>
+Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel <alban.bedel@avionic-design.de>
Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren <twarren@nvidia.com>
Active arm ixp - - - actux2 - Michael Schwingen <michael@schwingen.org>
Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich <ynvich@gmail.com>
Active arm pxa - toradex - colibri_pxa270 - Marek Vasut <marek.vasut@gmail.com>
Active arm sa1100 - - - jornada - Kristoffer Ericson <kristoffer.ericson@gmail.com>
-Active aarch64 armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng <fenghua@phytium.com.cn>
Active avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas Bießmann <andreas.devel@googlemail.com>
Active avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Active powerpc mpc85xx - - socrates socrates - -
Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett@boeing.com>
Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 -
-Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
-Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 -
-Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
-Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
-Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND BSC9131RDB:BSC9131RDB,NAND Poonam Aggrwal <poonam.aggrwal@freescale.com>
Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND_SYSCLK100 BSC9131RDB:BSC9131RDB,NAND,SYS_CLK_100 Poonam Aggrwal <poonam.aggrwal@freescale.com>
Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH BSC9131RDB:BSC9131RDB,SPIFLASH Poonam Aggrwal <poonam.aggrwal@freescale.com>
Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu <po.liu@freescale.com>
+Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale corenet_ds P3041DS - -
-Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
-Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale corenet_ds P3041DS_SECURE_BOOT P3041DS:SECURE_BOOT -
-Active powerpc mpc85xx - freescale corenet_ds P3041DS_SPIFLASH P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
-Active powerpc mpc85xx - freescale corenet_ds P3041DS_SRIO_PCIE_BOOT P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P3041DS_SPIFLASH P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P3041DS_SRIO_PCIE_BOOT P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale corenet_ds P4080DS - -
-Active powerpc mpc85xx - freescale corenet_ds P4080DS_SDCARD P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P4080DS_SDCARD P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale corenet_ds P4080DS_SECURE_BOOT P4080DS:SECURE_BOOT -
-Active powerpc mpc85xx - freescale corenet_ds P4080DS_SPIFLASH P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
-Active powerpc mpc85xx - freescale corenet_ds P4080DS_SRIO_PCIE_BOOT P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P4080DS_SPIFLASH P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P4080DS_SRIO_PCIE_BOOT P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale corenet_ds P5020DS - -
-Active powerpc mpc85xx - freescale corenet_ds P5020DS_NAND P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
-Active powerpc mpc85xx - freescale corenet_ds P5020DS_SDCARD P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P5020DS_NAND P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P5020DS_SDCARD P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale corenet_ds P5020DS_SECURE_BOOT P5020DS:SECURE_BOOT -
-Active powerpc mpc85xx - freescale corenet_ds P5020DS_SPIFLASH P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
-Active powerpc mpc85xx - freescale corenet_ds P5020DS_SRIO_PCIE_BOOT P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P5020DS_SPIFLASH P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P5020DS_SRIO_PCIE_BOOT P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale corenet_ds P5040DS - -
-Active powerpc mpc85xx - freescale corenet_ds P5040DS_NAND P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
-Active powerpc mpc85xx - freescale corenet_ds P5040DS_SDCARD P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
-Active powerpc mpc85xx - freescale corenet_ds P5040DS_SPIFLASH P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P5040DS_NAND P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P5040DS_SDCARD P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale corenet_ds P5040DS_SPIFLASH P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS MPC8536DS -
Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_36BIT MPC8536DS:36BIT -
Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_NAND MPC8536DS:NAND -
Active powerpc mpc85xx - freescale p2020ds P2020DS_SDCARD P2020DS:SDCARD -
Active powerpc mpc85xx - freescale p2020ds P2020DS_SPIFLASH P2020DS:SPIFLASH -
Active powerpc mpc85xx - freescale p2041rdb P2041RDB - -
-Active powerpc mpc85xx - freescale p2041rdb P2041RDB_NAND P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
-Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SDCARD P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale p2041rdb P2041RDB_NAND P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SDCARD P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SECURE_BOOT P2041RDB:SECURE_BOOT -
-Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
-Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale t2080qds T2080QDS T2080QDS:PPC_T2080 -
+Active powerpc mpc85xx - freescale t2080qds T2080QDS_NAND T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t2080qds T2080QDS_SDCARD T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t2080qds T2080QDS_SPIFLASH T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t2080qds T2080QDS_SRIO_PCIE_BOOT T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 -
-Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
-Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun <yorksun@freescale.com>
Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 -
-Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
-Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
-Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
-Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
-Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
-Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
-Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal@freescale.com>
-Active powerpc mpc85xx - freescale t2080qds T2080QDS T2080QDS:PPC_T2080
-Active powerpc mpc85xx - freescale t2080qds T2080QDS_SDCARD T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
-Active powerpc mpc85xx - freescale t2080qds T2080QDS_SPIFLASH T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
-Active powerpc mpc85xx - freescale t2080qds T2080QDS_NAND T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
-Active powerpc mpc85xx - freescale t2080qds T2080QDS_SRIO_PCIE_BOOT T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
+Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de>
obj-$(CONFIG_SPL_ENV_SUPPORT) += env_attr.o
obj-$(CONFIG_SPL_ENV_SUPPORT) += env_flags.o
obj-$(CONFIG_SPL_ENV_SUPPORT) += env_callback.o
+ifdef CONFIG_SPL_USB_HOST_SUPPORT
+obj-$(CONFIG_SPL_USB_SUPPORT) += usb.o usb_hub.o
+obj-$(CONFIG_USB_STORAGE) += usb_storage.o
+endif
ifneq ($(CONFIG_SPL_NET_SUPPORT),y)
obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
void board_init_r(gd_t *new_gd, ulong dest_addr)
{
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+ int i;
+#endif
+
#ifndef CONFIG_X86
gd = new_gd;
#endif
+
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+ for (i = 0; i < ARRAY_SIZE(init_sequence_r); i++)
+ init_sequence_r[i] += gd->reloc_off;
+#endif
+
if (initcall_run_list(init_sequence_r))
hang();
static void fixup_silent_linux(void);
#endif
+static int do_bootm_standalone(int flag, int argc, char * const argv[],
+ bootm_headers_t *images);
+
static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[], bootm_headers_t *images,
ulong *os_data, ulong *os_len);
#endif
static boot_os_fn *boot_os[] = {
+ [IH_OS_U_BOOT] = do_bootm_standalone,
#ifdef CONFIG_BOOTM_LINUX
[IH_OS_LINUX] = do_bootm_linux,
#endif
return 0;
}
-static int bootm_start_standalone(int argc, char * const argv[])
+static int do_bootm_standalone(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
{
char *s;
int (*appl)(int, char * const []);
/* Don't start if "autostart" is set to "no" */
if (((s = getenv("autostart")) != NULL) && (strcmp(s, "no") == 0)) {
- setenv_hex("filesize", images.os.image_len);
+ setenv_hex("filesize", images->os.image_len);
return 0;
}
- appl = (int (*)(int, char * const []))(ulong)ntohl(images.ep);
+ appl = (int (*)(int, char * const []))(ulong)ntohl(images->ep);
(*appl)(argc, argv);
return 0;
}
static int boot_selected_os(int argc, char * const argv[], int state,
bootm_headers_t *images, boot_os_fn *boot_fn)
{
- if (images->os.type == IH_TYPE_STANDALONE) {
- /* This may return when 'autostart' is 'no' */
- bootm_start_standalone(argc, argv);
- return 0;
- }
arch_preboot_os();
boot_fn(state, argc, argv, images);
- if (state == BOOTM_STATE_OS_FAKE_GO) /* We expect to return */
+
+ /* Stand-alone may return when 'autostart' is 'no' */
+ if (images->os.type == IH_TYPE_STANDALONE ||
+ state == BOOTM_STATE_OS_FAKE_GO) /* We expect to return */
return 0;
bootstage_error(BOOTSTAGE_ID_BOOT_OS_RETURNED);
#ifdef DEBUG
int bps; /* Bits per second */
speed = (long long)test->bytes * 1000;
- do_div(speed, test->time_ms[stage] * 1024);
+ if (test->time_ms[stage])
+ do_div(speed, test->time_ms[stage] * 1024);
bps = speed * 8;
printf("%d %s: %d ticks, %d KiB/s %d.%03d Mbps\n", stage,
{
unsigned long offset;
unsigned long len;
- uint8_t *buf = (uint8_t *)CONFIG_SYS_TEXT_BASE;
+ uint8_t *buf, *from;
char *endp;
uint8_t *vbuf;
int ret;
+ if (argc < 3)
+ return -1;
offset = simple_strtoul(argv[1], &endp, 16);
if (*argv[1] == 0 || *endp != 0)
return -1;
vbuf = malloc(len);
if (!vbuf) {
- printf("Cannot allocate memory\n");
+ printf("Cannot allocate memory (%lu bytes)\n", len);
return 1;
}
buf = malloc(len);
if (!buf) {
free(vbuf);
- printf("Cannot allocate memory\n");
+ printf("Cannot allocate memory (%lu bytes)\n", len);
return 1;
}
- memcpy(buf, (char *)CONFIG_SYS_TEXT_BASE, len);
+ from = map_sysmem(CONFIG_SYS_TEXT_BASE, 0);
+ memcpy(buf, from, len);
ret = spi_flash_test(flash, buf, len, offset, vbuf);
free(vbuf);
free(buf);
g_dnl_register("ums");
+ /* Timeout unit: seconds */
+ int cable_ready_timeout = UMS_CABLE_READY_TIMEOUT;
+
+ if (!usb_cable_connected()) {
+ puts("Please connect USB cable.\n");
+
+ while (!usb_cable_connected()) {
+ if (ctrlc()) {
+ puts("\rCTRL+C - Operation aborted.\n");
+ goto exit;
+ }
+ if (!cable_ready_timeout) {
+ puts("\rUSB cable not detected.\n" \
+ "Command exit.\n");
+ goto exit;
+ }
+
+ printf("\rAuto exit in: %.2d s.", cable_ready_timeout);
+ mdelay(1000);
+ cable_ready_timeout--;
+ }
+ puts("\r\n");
+ }
+
while (1) {
usb_gadget_handle_interrupts();
/* output full list of commands */
for (; cmdtp != cmdend; cmdtp++) {
if (n_found >= maxv - 2) {
- cmdv[n_found] = "...";
+ cmdv[n_found++] = "...";
break;
}
- cmdv[n_found] = cmdtp->name;
+ cmdv[n_found++] = cmdtp->name;
}
cmdv[n_found] = NULL;
return n_found;
return NULL;
}
+static int first_call = 1;
+static const char *callback_list;
+
/*
* Look for a possible callback for a newly added variable
* This is called specifically when the variable did not exist in the hash
void env_callback_init(ENTRY *var_entry)
{
const char *var_name = var_entry->key;
- const char *callback_list = getenv(ENV_CALLBACK_VAR);
char callback_name[256] = "";
struct env_clbk_tbl *clbkp;
int ret = 1;
+ if (first_call) {
+ callback_list = getenv(ENV_CALLBACK_VAR);
+ first_call = 0;
+ }
+
/* look in the ".callbacks" var for a reference to this variable */
if (callback_list != NULL)
ret = env_attr_lookup(callback_list, var_name, callback_name);
env_t *env_ptr;
char *env_name_spec = "EEPROM";
-int env_eeprom_bus = -1;
static int eeprom_bus_read(unsigned dev_addr, unsigned offset,
uchar *buffer, unsigned cnt)
rcode = eeprom_read(dev_addr, offset, buffer, cnt);
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
- if (old_bus != env_eeprom_bus)
- i2c_set_bus_num(old_bus);
+ i2c_set_bus_num(old_bus);
#endif
return rcode;
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
i2c_set_bus_num(old_bus);
#endif
+
return rcode;
}
return binflags;
}
+static int first_call = 1;
+static const char *flags_list;
+
/*
* Look for possible flags for a newly added variable
* This is called specifically when the variable did not exist in the hash
void env_flags_init(ENTRY *var_entry)
{
const char *var_name = var_entry->key;
- const char *flags_list = getenv(ENV_FLAGS_VAR);
char flags[ENV_FLAGS_ATTR_MAX_LEN + 1] = "";
int ret = 1;
+ if (first_call) {
+ flags_list = getenv(ENV_FLAGS_VAR);
+ first_call = 0;
+ }
/* look in the ".flags" and static for a reference to this variable */
ret = env_flags_lookup(flags_list, var_name, flags);
if ((path == NULL) || force) {
write_cell((u8 *)&tmp, initrd_start, addr_cell_len);
err = fdt_setprop(fdt, nodeoffset,
- "linux,initrd-start", &tmp, sizeof(tmp));
+ "linux,initrd-start", &tmp, addr_cell_len);
if (err < 0) {
printf("WARNING: "
"could not set linux,initrd-start %s.\n",
}
write_cell((u8 *)&tmp, initrd_end, addr_cell_len);
err = fdt_setprop(fdt, nodeoffset,
- "linux,initrd-end", &tmp, sizeof(tmp));
+ "linux,initrd-end", &tmp, addr_cell_len);
if (err < 0) {
printf("WARNING: could not set linux,initrd-end %s.\n",
fdt_strerror(err));
{ IH_OS_PLAN9, "plan9", "Plan 9", },
{ IH_OS_RTEMS, "rtems", "RTEMS", },
{ IH_OS_U_BOOT, "u-boot", "U-Boot", },
+ { IH_OS_VXWORKS, "vxworks", "VxWorks", },
#if defined(CONFIG_CMD_ELF) || defined(USE_HOSTCC)
{ IH_OS_QNX, "qnx", "QNX", },
- { IH_OS_VXWORKS, "vxworks", "VxWorks", },
#endif
#if defined(CONFIG_INTEGRITY) || defined(USE_HOSTCC)
{ IH_OS_INTEGRITY,"integrity", "INTEGRITY", },
obj-$(CONFIG_SPL_ONENAND_SUPPORT) += spl_onenand.o
obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o
obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o
+obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
+obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o
endif
spl_net_load_image("usb_ether");
break;
#endif
+#ifdef CONFIG_SPL_USB_SUPPORT
+ case BOOT_DEVICE_USB:
+ spl_usb_load_image();
+ break;
+#endif
default:
debug("SPL: Un-supported Boot Device\n");
hang();
--- /dev/null
+/*
+ * (C) Copyright 2014
+ * Texas Instruments, <www.ti.com>
+ *
+ * Dan Murphy <dmurphy@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * FAT Image Functions copied from spl_mmc.c
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/u-boot.h>
+#include <fat.h>
+#include <image.h>
+
+static int fat_registered;
+
+#ifdef CONFIG_SPL_FAT_SUPPORT
+static int spl_register_fat_device(block_dev_desc_t *block_dev, int partition)
+{
+ int err = 0;
+
+ if (fat_registered)
+ return err;
+
+ err = fat_register_device(block_dev, partition);
+ if (err) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ printf("%s: fat register err - %d\n", __func__, err);
+#endif
+ hang();
+ }
+
+ fat_registered = 1;
+
+ return err;
+}
+
+int spl_load_image_fat(block_dev_desc_t *block_dev,
+ int partition,
+ const char *filename)
+{
+ int err;
+ struct image_header *header;
+
+ err = spl_register_fat_device(block_dev, partition);
+ if (err)
+ goto end;
+
+ header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
+ sizeof(struct image_header));
+
+ err = file_fat_read(filename, header, sizeof(struct image_header));
+ if (err <= 0)
+ goto end;
+
+ spl_parse_image_header(header);
+
+ err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
+
+end:
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ if (err <= 0)
+ printf("%s: error reading image %s, err - %d\n",
+ __func__, filename, err);
+#endif
+
+ return (err <= 0);
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition)
+{
+ int err;
+
+ err = spl_register_fat_device(block_dev, partition);
+ if (err)
+ return err;
+
+ err = file_fat_read(CONFIG_SPL_FAT_LOAD_ARGS_NAME,
+ (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0);
+ if (err <= 0) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ printf("%s: error reading image %s, err - %d\n",
+ __func__, CONFIG_SPL_FAT_LOAD_ARGS_NAME, err);
+#endif
+ return -1;
+ }
+
+ return spl_load_image_fat(block_dev, partition,
+ CONFIG_SPL_FAT_LOAD_KERNEL_NAME);
+}
+#endif
+#endif
#include <spl.h>
#include <asm/u-boot.h>
#include <mmc.h>
-#include <fat.h>
#include <version.h>
#include <image.h>
}
#endif
-#ifdef CONFIG_SPL_FAT_SUPPORT
-static int mmc_load_image_fat(struct mmc *mmc, const char *filename)
-{
- int err;
- struct image_header *header;
-
- header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
- sizeof(struct image_header));
-
- err = file_fat_read(filename, header, sizeof(struct image_header));
- if (err <= 0)
- goto end;
-
- spl_parse_image_header(header);
-
- err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
-
-end:
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- if (err <= 0)
- printf("spl: error reading image %s, err - %d\n",
- filename, err);
-#endif
-
- return (err <= 0);
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-static int mmc_load_image_fat_os(struct mmc *mmc)
-{
- int err;
-
- err = file_fat_read(CONFIG_SPL_FAT_LOAD_ARGS_NAME,
- (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0);
- if (err <= 0) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- printf("spl: error reading image %s, err - %d\n",
- CONFIG_SPL_FAT_LOAD_ARGS_NAME, err);
-#endif
- return -1;
- }
-
- return mmc_load_image_fat(mmc, CONFIG_SPL_FAT_LOAD_KERNEL_NAME);
-}
-#endif
-
-#endif
-
void spl_mmc_load_image(void)
{
struct mmc *mmc;
if (spl_start_uboot() || mmc_load_image_raw_os(mmc))
#endif
err = mmc_load_image_raw(mmc,
- CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
+ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
#ifdef CONFIG_SPL_FAT_SUPPORT
} else if (boot_mode == MMCSD_MODE_FAT) {
debug("boot mode - FAT\n");
-
- err = fat_register_device(&mmc->block_dev,
- CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION);
- if (err) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- printf("spl: fat register err - %d\n", err);
-#endif
- hang();
- }
-
#ifdef CONFIG_SPL_OS_BOOT
- if (spl_start_uboot() || mmc_load_image_fat_os(mmc))
+ if (spl_start_uboot() || spl_load_image_fat_os(&mmc->block_dev,
+ CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION))
#endif
- err = mmc_load_image_fat(mmc, CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);
+ err = spl_load_image_fat(&mmc->block_dev,
+ CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION,
+ CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);
#endif
} else {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
--- /dev/null
+/*
+ * (C) Copyright 2014
+ * Texas Instruments, <www.ti.com>
+ *
+ * Dan Murphy <dmurphy@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Derived work from spl_mmc.c
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/u-boot.h>
+#include <usb.h>
+#include <fat.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USB_STORAGE
+static int usb_stor_curr_dev = -1; /* current device */
+#endif
+
+void spl_usb_load_image(void)
+{
+ int err;
+ block_dev_desc_t *stor_dev;
+
+ usb_stop();
+ err = usb_init();
+ if (err) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ printf("%s: usb init failed: err - %d\n", __func__, err);
+#endif
+ hang();
+ }
+
+#ifdef CONFIG_USB_STORAGE
+ /* try to recognize storage devices immediately */
+ usb_stor_curr_dev = usb_stor_scan(1);
+ stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
+#endif
+
+ debug("boot mode - FAT\n");
+
+#ifdef CONFIG_SPL_OS_BOOT
+ if (spl_start_uboot() || spl_load_image_fat_os(stor_dev,
+ CONFIG_SYS_USB_FAT_BOOT_PARTITION))
+#endif
+ err = spl_load_image_fat(stor_dev,
+ CONFIG_SYS_USB_FAT_BOOT_PARTITION,
+ CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);
+
+ if (err) {
+ puts("Error loading USB device\n");
+ hang();
+ }
+}
CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
+CONFIG_SPL_DRIVERS_MISC_SUPPORT (drivers/misc)
CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o)
CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o)
CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o)
NOR Flash memory Map on B4860 and B4420QDS
------------------------------------------
Start End Definition Size
-0xEFF80000 0xEFFFFFFF u-boot (current bank) 512KB
-0xEFF60000 0xEFF7FFFF u-boot env (current bank) 128KB
-0xEFF40000 0xEFF5FFFF FMAN Ucode (current bank) 128KB
+0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
+0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
+0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
0xEF300000 0xEFF3FFFF rootfs (alternate bank) 12MB + 256KB
0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB
0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB
0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB
-0xEDF80000 0xEDFFFFFF u-boot (alternate bank) 512KB
-0xEDF60000 0xEDF7FFFF u-boot env (alternate bank) 128KB
-0xEDF40000 0xEDF5FFFF FMAN ucode (alternate bank) 128KB
+0xEDF40000 0xEDFFFFFF u-boot (alternate bank) 768KB
+0xEDF20000 0xEDF3FFFF u-boot env (alternate bank) 128KB
+0xEDF00000 0xEDF1FFFF FMAN ucode (alternate bank) 128KB
0xED300000 0xEDF3FFFF rootfs (current bank) 12MB+256MB
0xEC800000 0xEC8FFFFF device tree (current bank) 1MB
0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB
+++ /dev/null
-U-Boot for FriendlyARM Mini2440 (s3c2440)
-
-This file contains information for the port of U-Boot to FriendlyARM
-mini2440
-
-All information about the board can be found on :
-http://www.friendlyarm.net/products/mini2440
-
-To build u-boot : ./MAKEALL mini2440
-
-Overview :
---------
-FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440
-ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9
-systems. It's a low cost board.
-
-Boot Methods :
-------------
-Mini2440 can boot from NOR or NAND.
-
-Build :
------
-./MAKEALL mini2440
-
-or
-
-make mini2440_config
-make
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-omap730p2 arm arm926ejs - 2013-11-11
-pn62 powerpc mpc824x - 2013-11-11 Wolfgang Grandegger <wg@grandegger.com>
+mx1ads arm arm920t - 2014-01-13
+mini2440 arm arm920t - 2014-01-13 Gabriel Huau <contact@huau-gabriel.fr>
+omap730p2 arm arm926ejs 79c5c08d 2013-11-11
+pn62 powerpc mpc824x 649acfe1 2013-11-11 Wolfgang Grandegger <wg@grandegger.com>
pdnb3 arm ixp 304db0b 2013-09-24 Stefan Roese <sr@denx.de>
scpu arm ixp 304db0b 2013-09-24 Stefan Roese <sr@denx.de>
omap1510inn arm arm925t 0610a16 2013-09-23 Kshitij Gupta <kshitij@ti.com>
--- /dev/null
+SPI/QSPI Dual flash connection modes:
+=====================================
+
+This describes how SPI/QSPI flash memories are connected to a given
+controller in a single chip select line.
+
+Current spi_flash framework supports, single flash memory connected
+to a given controller with single chip select line, but there are some
+hw logics(ex: xilinx zynq qspi) that describes two/dual memories are
+connected with a single chip select line from a controller.
+
+"dual_flash" from include/spi.h describes these types of connection mode
+
+Possible connections:
+--------------------
+SF_SINGLE_FLASH:
+ - single spi flash memory connected with single chip select line.
+
+ +------------+ CS +---------------+
+ | |----------------------->| |
+ | Controller | I0[3:0] | Flash memory |
+ | SPI/QSPI |<======================>| (SPI/QSPI) |
+ | | CLK | |
+ | |----------------------->| |
+ +------------+ +---------------+
+
+SF_DUAL_STACKED_FLASH:
+ - dual spi/qspi flash memories are connected with a single chipselect
+ line and these two memories are operating stacked fasion with shared buses.
+ - xilinx zynq qspi controller has implemented this feature [1]
+
+ +------------+ CS +---------------+
+ | |---------------------->| |
+ | | I0[3:0] | Upper Flash |
+ | | +=========>| memory |
+ | | | CLK | (SPI/QSPI) |
+ | | | +---->| |
+ | Controller | CS | | +---------------+
+ | SPI/QSPI |------------|----|---->| |
+ | | I0[3:0] | | | Lower Flash |
+ | |<===========+====|====>| memory |
+ | | CLK | | (SPI/QSPI) |
+ | |-----------------+---->| |
+ +------------+ +---------------+
+
+ - two memory flash devices should has same hw part attributes (like size,
+ vendor..etc)
+ - Configurations:
+ on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG
+ Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
+ Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
+ - Operation:
+ accessing memories serially like one after another.
+ by default, if U_PAGE is unset lower memory should accessible,
+ once user wants to access upper memory need to set U_PAGE.
+
+SPI_FLASH_CONN_DUALPARALLEL:
+ - dual spi/qspi flash memories are connected with a single chipselect
+ line and these two memories are operating parallel with separate buses.
+ - xilinx zynq qspi controller has implemented this feature [1]
+
+ +-------------+ CS +---------------+
+ | |---------------------->| |
+ | | I0[3:0] | Upper Flash |
+ | |<=====================>| memory |
+ | | CLK | (SPI/QSPI) |
+ | |---------------------->| |
+ | Controller | CS +---------------+
+ | SPI/QSPI |---------------------->| |
+ | | I0[3:0] | Lower Flash |
+ | |<=====================>| memory |
+ | | CLK | (SPI/QSPI) |
+ | |---------------------->| |
+ +-------------+ +---------------+
+
+ - two memory flash devices should has same hw part attributes (like size,
+ vendor..etc)
+ - Configurations:
+ Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG register.
+ - Operation:
+ Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory
+ and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory.
+
+Note: Technically there is only one CS line from the controller, but
+zynq qspi controller has an internal hw logic to enable additional CS
+when controller is configured for dual memories.
+
+[1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
+
+--
+Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+05-01-2014.
--- /dev/null
+SPI Flash test on Faraday A369 EVB:
+==================================
+
+U-Boot 2014.01-rc2-g3444b6f (Dec 20 2013 - 10:58:40)
+
+CPU: FA626TE 528 MHz
+AHB: 132 MHz
+APB: 66 MHz
+I2C: ready
+DRAM: 256 MiB
+MMU: on
+NAND: 512 MiB
+MMC: ftsdc010: 0
+*** Warning - bad CRC, using default environment
+
+In: serial
+Out: serial
+Err: serial
+Net: FTGMAC100#0
+Hit any key to stop autoboot: 0
+=> sf probe 0:0
+SF: Detected MX25L1605D with page size 256 Bytes, erase size 64 KiB, total 2 MiB
+=> sf read 0x10800000 0 0x400
+SF: 1024 bytes @ 0x0 Read: OK
+=> md 0x10800000
+10800000: ea000013 e59ff014 e59ff014 e59ff014 ................
+10800010: e59ff014 e59ff014 e59ff014 e59ff014 ................
+10800020: 1ff7b0c0 1ff7b120 1ff7b180 1ff7b1e0 .... ...........
+10800030: 1ff7b240 1ff7b2a0 1ff7b300 deadbeef @...............
+10800040: 10800000 0002c1f0 0007409c 00032048 .........@..H ..
+10800050: 1fd6af40 e10f0000 e3c0001f e38000d3 @...............
+10800060: e129f000 eb000001 eb000223 e12fff1e ..).....#...../.
+10800070: e3a00000 ee070f1e ee080f17 ee070f15 ................
+10800080: ee070f9a ee110f10 e3c00c03 e3c00087 ................
+10800090: e3c00a02 e3800002 e3800a01 ee010f10 ................
+108000a0: e1a0c00e eb007a68 e1a0e00c e1a0f00e ....hz..........
+108000b0: e1a00000 e1a00000 e1a00000 e1a00000 ................
+108000c0: e51fd078 e58de000 e14fe000 e58de004 x.........O.....
+108000d0: e3a0d013 e169f00d e1a0e00f e1b0f00e ......i.........
+108000e0: e24dd048 e88d1fff e51f20a0 e892000c H.M...... ......
+108000f0: e28d0048 e28d5034 e1a0100e e885000f H...4P..........
- Bank Address Register (Accessing flashes > 16Mbytes in 3-byte addressing)
- Added memory_mapped support for read operations.
- Common probe support for all supported flash vendors except, ramtron.
+- Extended read commands support(dual read, dual IO read)
+- Quad Page Program support.
+- Quad Read support(quad fast read, quad IO read)
+- Dual flash connection topology support(accessing two spi flash memories with single cs)
+- Banking support on dual flash connection topology.
SPI DRIVERS (drivers/spi):
-
TODO:
- Runtime detection of spi_flash params, SFDP(if possible)
- Add support for multibus build/accessing.
-- Extended read commands support(dual read, dual IO read)
-- Quad Page Program support.
-- Quad Read support(quad fast read, quad IO read)
-- Dual flash connection topology support(accessing two spi flash memories with single cs)
-- Banking support on dual flash connection topology.
- Need proper cleanups on spi_flash and drivers.
--
Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
18-09-2013.
07-10-2013.
+08-01-2014.
an image source file, which describes the contents of the image and defines
its various properties used during booting. By convention, image source file
has the ".its" extension, also, the details of its format are given in
-doc/source_file_format.txt. The actual data that is to be included in the
-uImage (kernel, ramdisk, etc.) is specified in the image source file in the
+doc/uImage.FIT/source_file_format.txt. The actual data that is to be included in
+the uImage (kernel, ramdisk, etc.) is specified in the image source file in the
form of paths to appropriate data files. The outcome of the image creation
process is a binary file (by convention with the ".itb" extension) that
contains all the referenced data (kernel, ramdisk, etc.) and other information
image source file mkimage + dtc transfer to target
+ ---------------> image file --------------------> bootm
-image data files(s)
+image data file(s)
Example 1 -- old-style (non-FDT) kernel booting
- description : Textual description of the component sub-image
- type : Name of component sub-image type, supported types are:
"standalone", "kernel", "ramdisk", "firmware", "script", "filesystem",
- "fdt".
+ "flat_dt".
- data : Path to the external file which contains this node's binary data.
- compression : Compression used by included data. Supported compressions
are "gzip" and "bzip2". If no compression is used compression property
+++ /dev/null
-/****************************************************************************
-*
-* Realmode X86 Emulator Library
-*
-* Copyright (C) 1991-2004 SciTech Software, Inc.
-* Copyright (C) David Mosberger-Tang
-* Copyright (C) 1999 Egbert Eich
-*
-* ========================================================================
-*
-* Permission to use, copy, modify, distribute, and sell this software and
-* its documentation for any purpose is hereby granted without fee,
-* provided that the above copyright notice appear in all copies and that
-* both that copyright notice and this permission notice appear in
-* supporting documentation, and that the name of the authors not be used
-* in advertising or publicity pertaining to distribution of the software
-* without specific, written prior permission. The authors makes no
-* representations about the suitability of this software for any purpose.
-* It is provided "as is" without express or implied warranty.
-*
-* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
-* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
-* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
-* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
-* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
-* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
-* PERFORMANCE OF THIS SOFTWARE.
-*
-* ========================================================================
-*
-* Language: Watcom C++ 10.6 or later
-* Environment: Any
-* Developer: Kendall Bennett
-*
-* Description: Inline assembler versions of the primitive operand
-* functions for faster performance. At the moment this is
-* x86 inline assembler, but these functions could be replaced
-* with native inline assembler for each supported processor
-* platform.
-*
-****************************************************************************/
-
-#ifndef __X86EMU_PRIM_ASM_H
-#define __X86EMU_PRIM_ASM_H
-
-#ifdef __WATCOMC__
-
-#ifndef VALIDATE
-#define __HAVE_INLINE_ASSEMBLER__
-#endif
-
-u32 get_flags_asm(void);
-#pragma aux get_flags_asm = \
- "pushf" \
- "pop eax" \
- value [eax] \
- modify exact [eax];
-
-u16 aaa_word_asm(u32 * flags, u16 d);
-#pragma aux aaa_word_asm = \
- "push [edi]" \
- "popf" \
- "aaa" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] \
- value [ax] \
- modify exact [ax];
-
-u16 aas_word_asm(u32 * flags, u16 d);
-#pragma aux aas_word_asm = \
- "push [edi]" \
- "popf" \
- "aas" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] \
- value [ax] \
- modify exact [ax];
-
-u16 aad_word_asm(u32 * flags, u16 d);
-#pragma aux aad_word_asm = \
- "push [edi]" \
- "popf" \
- "aad" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] \
- value [ax] \
- modify exact [ax];
-
-u16 aam_word_asm(u32 * flags, u8 d);
-#pragma aux aam_word_asm = \
- "push [edi]" \
- "popf" \
- "aam" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] \
- value [ax] \
- modify exact [ax];
-
-u8 adc_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux adc_byte_asm = \
- "push [edi]" \
- "popf" \
- "adc al,bl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] [bl] \
- value [al] \
- modify exact [al bl];
-
-u16 adc_word_asm(u32 * flags, u16 d, u16 s);
-#pragma aux adc_word_asm = \
- "push [edi]" \
- "popf" \
- "adc ax,bx" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] [bx] \
- value [ax] \
- modify exact [ax bx];
-
-u32 adc_long_asm(u32 * flags, u32 d, u32 s);
-#pragma aux adc_long_asm = \
- "push [edi]" \
- "popf" \
- "adc eax,ebx" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] [ebx] \
- value [eax] \
- modify exact [eax ebx];
-
-u8 add_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux add_byte_asm = \
- "push [edi]" \
- "popf" \
- "add al,bl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] [bl] \
- value [al] \
- modify exact [al bl];
-
-u16 add_word_asm(u32 * flags, u16 d, u16 s);
-#pragma aux add_word_asm = \
- "push [edi]" \
- "popf" \
- "add ax,bx" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] [bx] \
- value [ax] \
- modify exact [ax bx];
-
-u32 add_long_asm(u32 * flags, u32 d, u32 s);
-#pragma aux add_long_asm = \
- "push [edi]" \
- "popf" \
- "add eax,ebx" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] [ebx] \
- value [eax] \
- modify exact [eax ebx];
-
-u8 and_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux and_byte_asm = \
- "push [edi]" \
- "popf" \
- "and al,bl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] [bl] \
- value [al] \
- modify exact [al bl];
-
-u16 and_word_asm(u32 * flags, u16 d, u16 s);
-#pragma aux and_word_asm = \
- "push [edi]" \
- "popf" \
- "and ax,bx" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] [bx] \
- value [ax] \
- modify exact [ax bx];
-
-u32 and_long_asm(u32 * flags, u32 d, u32 s);
-#pragma aux and_long_asm = \
- "push [edi]" \
- "popf" \
- "and eax,ebx" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] [ebx] \
- value [eax] \
- modify exact [eax ebx];
-
-u8 cmp_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux cmp_byte_asm = \
- "push [edi]" \
- "popf" \
- "cmp al,bl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] [bl] \
- value [al] \
- modify exact [al bl];
-
-u16 cmp_word_asm(u32 * flags, u16 d, u16 s);
-#pragma aux cmp_word_asm = \
- "push [edi]" \
- "popf" \
- "cmp ax,bx" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] [bx] \
- value [ax] \
- modify exact [ax bx];
-
-u32 cmp_long_asm(u32 * flags, u32 d, u32 s);
-#pragma aux cmp_long_asm = \
- "push [edi]" \
- "popf" \
- "cmp eax,ebx" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] [ebx] \
- value [eax] \
- modify exact [eax ebx];
-
-u8 daa_byte_asm(u32 * flags, u8 d);
-#pragma aux daa_byte_asm = \
- "push [edi]" \
- "popf" \
- "daa" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] \
- value [al] \
- modify exact [al];
-
-u8 das_byte_asm(u32 * flags, u8 d);
-#pragma aux das_byte_asm = \
- "push [edi]" \
- "popf" \
- "das" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] \
- value [al] \
- modify exact [al];
-
-u8 dec_byte_asm(u32 * flags, u8 d);
-#pragma aux dec_byte_asm = \
- "push [edi]" \
- "popf" \
- "dec al" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] \
- value [al] \
- modify exact [al];
-
-u16 dec_word_asm(u32 * flags, u16 d);
-#pragma aux dec_word_asm = \
- "push [edi]" \
- "popf" \
- "dec ax" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] \
- value [ax] \
- modify exact [ax];
-
-u32 dec_long_asm(u32 * flags, u32 d);
-#pragma aux dec_long_asm = \
- "push [edi]" \
- "popf" \
- "dec eax" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] \
- value [eax] \
- modify exact [eax];
-
-u8 inc_byte_asm(u32 * flags, u8 d);
-#pragma aux inc_byte_asm = \
- "push [edi]" \
- "popf" \
- "inc al" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] \
- value [al] \
- modify exact [al];
-
-u16 inc_word_asm(u32 * flags, u16 d);
-#pragma aux inc_word_asm = \
- "push [edi]" \
- "popf" \
- "inc ax" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] \
- value [ax] \
- modify exact [ax];
-
-u32 inc_long_asm(u32 * flags, u32 d);
-#pragma aux inc_long_asm = \
- "push [edi]" \
- "popf" \
- "inc eax" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] \
- value [eax] \
- modify exact [eax];
-
-u8 or_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux or_byte_asm = \
- "push [edi]" \
- "popf" \
- "or al,bl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] [bl] \
- value [al] \
- modify exact [al bl];
-
-u16 or_word_asm(u32 * flags, u16 d, u16 s);
-#pragma aux or_word_asm = \
- "push [edi]" \
- "popf" \
- "or ax,bx" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] [bx] \
- value [ax] \
- modify exact [ax bx];
-
-u32 or_long_asm(u32 * flags, u32 d, u32 s);
-#pragma aux or_long_asm = \
- "push [edi]" \
- "popf" \
- "or eax,ebx" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] [ebx] \
- value [eax] \
- modify exact [eax ebx];
-
-u8 neg_byte_asm(u32 * flags, u8 d);
-#pragma aux neg_byte_asm = \
- "push [edi]" \
- "popf" \
- "neg al" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] \
- value [al] \
- modify exact [al];
-
-u16 neg_word_asm(u32 * flags, u16 d);
-#pragma aux neg_word_asm = \
- "push [edi]" \
- "popf" \
- "neg ax" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] \
- value [ax] \
- modify exact [ax];
-
-u32 neg_long_asm(u32 * flags, u32 d);
-#pragma aux neg_long_asm = \
- "push [edi]" \
- "popf" \
- "neg eax" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] \
- value [eax] \
- modify exact [eax];
-
-u8 not_byte_asm(u32 * flags, u8 d);
-#pragma aux not_byte_asm = \
- "push [edi]" \
- "popf" \
- "not al" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] \
- value [al] \
- modify exact [al];
-
-u16 not_word_asm(u32 * flags, u16 d);
-#pragma aux not_word_asm = \
- "push [edi]" \
- "popf" \
- "not ax" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] \
- value [ax] \
- modify exact [ax];
-
-u32 not_long_asm(u32 * flags, u32 d);
-#pragma aux not_long_asm = \
- "push [edi]" \
- "popf" \
- "not eax" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] \
- value [eax] \
- modify exact [eax];
-
-u8 rcl_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux rcl_byte_asm = \
- "push [edi]" \
- "popf" \
- "rcl al,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] [cl] \
- value [al] \
- modify exact [al cl];
-
-u16 rcl_word_asm(u32 * flags, u16 d, u8 s);
-#pragma aux rcl_word_asm = \
- "push [edi]" \
- "popf" \
- "rcl ax,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] [cl] \
- value [ax] \
- modify exact [ax cl];
-
-u32 rcl_long_asm(u32 * flags, u32 d, u8 s);
-#pragma aux rcl_long_asm = \
- "push [edi]" \
- "popf" \
- "rcl eax,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] [cl] \
- value [eax] \
- modify exact [eax cl];
-
-u8 rcr_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux rcr_byte_asm = \
- "push [edi]" \
- "popf" \
- "rcr al,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] [cl] \
- value [al] \
- modify exact [al cl];
-
-u16 rcr_word_asm(u32 * flags, u16 d, u8 s);
-#pragma aux rcr_word_asm = \
- "push [edi]" \
- "popf" \
- "rcr ax,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] [cl] \
- value [ax] \
- modify exact [ax cl];
-
-u32 rcr_long_asm(u32 * flags, u32 d, u8 s);
-#pragma aux rcr_long_asm = \
- "push [edi]" \
- "popf" \
- "rcr eax,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] [cl] \
- value [eax] \
- modify exact [eax cl];
-
-u8 rol_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux rol_byte_asm = \
- "push [edi]" \
- "popf" \
- "rol al,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] [cl] \
- value [al] \
- modify exact [al cl];
-
-u16 rol_word_asm(u32 * flags, u16 d, u8 s);
-#pragma aux rol_word_asm = \
- "push [edi]" \
- "popf" \
- "rol ax,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] [cl] \
- value [ax] \
- modify exact [ax cl];
-
-u32 rol_long_asm(u32 * flags, u32 d, u8 s);
-#pragma aux rol_long_asm = \
- "push [edi]" \
- "popf" \
- "rol eax,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] [cl] \
- value [eax] \
- modify exact [eax cl];
-
-u8 ror_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux ror_byte_asm = \
- "push [edi]" \
- "popf" \
- "ror al,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] [cl] \
- value [al] \
- modify exact [al cl];
-
-u16 ror_word_asm(u32 * flags, u16 d, u8 s);
-#pragma aux ror_word_asm = \
- "push [edi]" \
- "popf" \
- "ror ax,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] [cl] \
- value [ax] \
- modify exact [ax cl];
-
-u32 ror_long_asm(u32 * flags, u32 d, u8 s);
-#pragma aux ror_long_asm = \
- "push [edi]" \
- "popf" \
- "ror eax,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] [cl] \
- value [eax] \
- modify exact [eax cl];
-
-u8 shl_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux shl_byte_asm = \
- "push [edi]" \
- "popf" \
- "shl al,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] [cl] \
- value [al] \
- modify exact [al cl];
-
-u16 shl_word_asm(u32 * flags, u16 d, u8 s);
-#pragma aux shl_word_asm = \
- "push [edi]" \
- "popf" \
- "shl ax,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] [cl] \
- value [ax] \
- modify exact [ax cl];
-
-u32 shl_long_asm(u32 * flags, u32 d, u8 s);
-#pragma aux shl_long_asm = \
- "push [edi]" \
- "popf" \
- "shl eax,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] [cl] \
- value [eax] \
- modify exact [eax cl];
-
-u8 shr_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux shr_byte_asm = \
- "push [edi]" \
- "popf" \
- "shr al,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] [cl] \
- value [al] \
- modify exact [al cl];
-
-u16 shr_word_asm(u32 * flags, u16 d, u8 s);
-#pragma aux shr_word_asm = \
- "push [edi]" \
- "popf" \
- "shr ax,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] [cl] \
- value [ax] \
- modify exact [ax cl];
-
-u32 shr_long_asm(u32 * flags, u32 d, u8 s);
-#pragma aux shr_long_asm = \
- "push [edi]" \
- "popf" \
- "shr eax,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] [cl] \
- value [eax] \
- modify exact [eax cl];
-
-u8 sar_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux sar_byte_asm = \
- "push [edi]" \
- "popf" \
- "sar al,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] [cl] \
- value [al] \
- modify exact [al cl];
-
-u16 sar_word_asm(u32 * flags, u16 d, u8 s);
-#pragma aux sar_word_asm = \
- "push [edi]" \
- "popf" \
- "sar ax,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] [cl] \
- value [ax] \
- modify exact [ax cl];
-
-u32 sar_long_asm(u32 * flags, u32 d, u8 s);
-#pragma aux sar_long_asm = \
- "push [edi]" \
- "popf" \
- "sar eax,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] [cl] \
- value [eax] \
- modify exact [eax cl];
-
-u16 shld_word_asm(u32 * flags, u16 d, u16 fill, u8 s);
-#pragma aux shld_word_asm = \
- "push [edi]" \
- "popf" \
- "shld ax,dx,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] [dx] [cl] \
- value [ax] \
- modify exact [ax dx cl];
-
-u32 shld_long_asm(u32 * flags, u32 d, u32 fill, u8 s);
-#pragma aux shld_long_asm = \
- "push [edi]" \
- "popf" \
- "shld eax,edx,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] [edx] [cl] \
- value [eax] \
- modify exact [eax edx cl];
-
-u16 shrd_word_asm(u32 * flags, u16 d, u16 fill, u8 s);
-#pragma aux shrd_word_asm = \
- "push [edi]" \
- "popf" \
- "shrd ax,dx,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] [dx] [cl] \
- value [ax] \
- modify exact [ax dx cl];
-
-u32 shrd_long_asm(u32 * flags, u32 d, u32 fill, u8 s);
-#pragma aux shrd_long_asm = \
- "push [edi]" \
- "popf" \
- "shrd eax,edx,cl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] [edx] [cl] \
- value [eax] \
- modify exact [eax edx cl];
-
-u8 sbb_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux sbb_byte_asm = \
- "push [edi]" \
- "popf" \
- "sbb al,bl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] [bl] \
- value [al] \
- modify exact [al bl];
-
-u16 sbb_word_asm(u32 * flags, u16 d, u16 s);
-#pragma aux sbb_word_asm = \
- "push [edi]" \
- "popf" \
- "sbb ax,bx" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] [bx] \
- value [ax] \
- modify exact [ax bx];
-
-u32 sbb_long_asm(u32 * flags, u32 d, u32 s);
-#pragma aux sbb_long_asm = \
- "push [edi]" \
- "popf" \
- "sbb eax,ebx" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] [ebx] \
- value [eax] \
- modify exact [eax ebx];
-
-u8 sub_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux sub_byte_asm = \
- "push [edi]" \
- "popf" \
- "sub al,bl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] [bl] \
- value [al] \
- modify exact [al bl];
-
-u16 sub_word_asm(u32 * flags, u16 d, u16 s);
-#pragma aux sub_word_asm = \
- "push [edi]" \
- "popf" \
- "sub ax,bx" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] [bx] \
- value [ax] \
- modify exact [ax bx];
-
-u32 sub_long_asm(u32 * flags, u32 d, u32 s);
-#pragma aux sub_long_asm = \
- "push [edi]" \
- "popf" \
- "sub eax,ebx" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] [ebx] \
- value [eax] \
- modify exact [eax ebx];
-
-void test_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux test_byte_asm = \
- "push [edi]" \
- "popf" \
- "test al,bl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] [bl] \
- modify exact [al bl];
-
-void test_word_asm(u32 * flags, u16 d, u16 s);
-#pragma aux test_word_asm = \
- "push [edi]" \
- "popf" \
- "test ax,bx" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] [bx] \
- modify exact [ax bx];
-
-void test_long_asm(u32 * flags, u32 d, u32 s);
-#pragma aux test_long_asm = \
- "push [edi]" \
- "popf" \
- "test eax,ebx" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] [ebx] \
- modify exact [eax ebx];
-
-u8 xor_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux xor_byte_asm = \
- "push [edi]" \
- "popf" \
- "xor al,bl" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [al] [bl] \
- value [al] \
- modify exact [al bl];
-
-u16 xor_word_asm(u32 * flags, u16 d, u16 s);
-#pragma aux xor_word_asm = \
- "push [edi]" \
- "popf" \
- "xor ax,bx" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [ax] [bx] \
- value [ax] \
- modify exact [ax bx];
-
-u32 xor_long_asm(u32 * flags, u32 d, u32 s);
-#pragma aux xor_long_asm = \
- "push [edi]" \
- "popf" \
- "xor eax,ebx" \
- "pushf" \
- "pop [edi]" \
- parm [edi] [eax] [ebx] \
- value [eax] \
- modify exact [eax ebx];
-
-void imul_byte_asm(u32 * flags, u16 * ax, u8 d, u8 s);
-#pragma aux imul_byte_asm = \
- "push [edi]" \
- "popf" \
- "imul bl" \
- "pushf" \
- "pop [edi]" \
- "mov [esi],ax" \
- parm [edi] [esi] [al] [bl] \
- modify exact [esi ax bl];
-
-void imul_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 d, u16 s);
-#pragma aux imul_word_asm = \
- "push [edi]" \
- "popf" \
- "imul bx" \
- "pushf" \
- "pop [edi]" \
- "mov [esi],ax" \
- "mov [ecx],dx" \
- parm [edi] [esi] [ecx] [ax] [bx]\
- modify exact [esi edi ax bx dx];
-
-void imul_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 d, u32 s);
-#pragma aux imul_long_asm = \
- "push [edi]" \
- "popf" \
- "imul ebx" \
- "pushf" \
- "pop [edi]" \
- "mov [esi],eax" \
- "mov [ecx],edx" \
- parm [edi] [esi] [ecx] [eax] [ebx] \
- modify exact [esi edi eax ebx edx];
-
-void mul_byte_asm(u32 * flags, u16 * ax, u8 d, u8 s);
-#pragma aux mul_byte_asm = \
- "push [edi]" \
- "popf" \
- "mul bl" \
- "pushf" \
- "pop [edi]" \
- "mov [esi],ax" \
- parm [edi] [esi] [al] [bl] \
- modify exact [esi ax bl];
-
-void mul_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 d, u16 s);
-#pragma aux mul_word_asm = \
- "push [edi]" \
- "popf" \
- "mul bx" \
- "pushf" \
- "pop [edi]" \
- "mov [esi],ax" \
- "mov [ecx],dx" \
- parm [edi] [esi] [ecx] [ax] [bx]\
- modify exact [esi edi ax bx dx];
-
-void mul_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 d, u32 s);
-#pragma aux mul_long_asm = \
- "push [edi]" \
- "popf" \
- "mul ebx" \
- "pushf" \
- "pop [edi]" \
- "mov [esi],eax" \
- "mov [ecx],edx" \
- parm [edi] [esi] [ecx] [eax] [ebx] \
- modify exact [esi edi eax ebx edx];
-
-void idiv_byte_asm(u32 * flags, u8 * al, u8 * ah, u16 d, u8 s);
-#pragma aux idiv_byte_asm = \
- "push [edi]" \
- "popf" \
- "idiv bl" \
- "pushf" \
- "pop [edi]" \
- "mov [esi],al" \
- "mov [ecx],ah" \
- parm [edi] [esi] [ecx] [ax] [bl]\
- modify exact [esi edi ax bl];
-
-void idiv_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 dlo, u16 dhi, u16 s);
-#pragma aux idiv_word_asm = \
- "push [edi]" \
- "popf" \
- "idiv bx" \
- "pushf" \
- "pop [edi]" \
- "mov [esi],ax" \
- "mov [ecx],dx" \
- parm [edi] [esi] [ecx] [ax] [dx] [bx]\
- modify exact [esi edi ax dx bx];
-
-void idiv_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 dlo, u32 dhi, u32 s);
-#pragma aux idiv_long_asm = \
- "push [edi]" \
- "popf" \
- "idiv ebx" \
- "pushf" \
- "pop [edi]" \
- "mov [esi],eax" \
- "mov [ecx],edx" \
- parm [edi] [esi] [ecx] [eax] [edx] [ebx]\
- modify exact [esi edi eax edx ebx];
-
-void div_byte_asm(u32 * flags, u8 * al, u8 * ah, u16 d, u8 s);
-#pragma aux div_byte_asm = \
- "push [edi]" \
- "popf" \
- "div bl" \
- "pushf" \
- "pop [edi]" \
- "mov [esi],al" \
- "mov [ecx],ah" \
- parm [edi] [esi] [ecx] [ax] [bl]\
- modify exact [esi edi ax bl];
-
-void div_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 dlo, u16 dhi, u16 s);
-#pragma aux div_word_asm = \
- "push [edi]" \
- "popf" \
- "div bx" \
- "pushf" \
- "pop [edi]" \
- "mov [esi],ax" \
- "mov [ecx],dx" \
- parm [edi] [esi] [ecx] [ax] [dx] [bx]\
- modify exact [esi edi ax dx bx];
-
-void div_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 dlo, u32 dhi, u32 s);
-#pragma aux div_long_asm = \
- "push [edi]" \
- "popf" \
- "div ebx" \
- "pushf" \
- "pop [edi]" \
- "mov [esi],eax" \
- "mov [ecx],edx" \
- parm [edi] [esi] [ecx] [eax] [edx] [ebx]\
- modify exact [esi edi eax edx ebx];
-
-#endif
-
-#endif /* __X86EMU_PRIM_ASM_H */
unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
int csn = -1;
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
+ u32 save1, save2;
+#endif
switch (ctrl_num) {
case 0:
out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
out_be32(&ddr->mtcr, 0);
+ save1 = in_be32(&ddr->debug[12]);
+ save2 = in_be32(&ddr->debug[21]);
out_be32(&ddr->debug[12], 0x00000015);
out_be32(&ddr->debug[21], 0x24000000);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
0x04000000 |
MD_CNTL_WRCW |
MD_CNTL_MD_VALUE(0x02));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+ if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+ break;
+ while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
+ ;
+ out_be32(&ddr->sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL_CS2_CS3 |
+ 0x04000000 |
+ MD_CNTL_WRCW |
+ MD_CNTL_MD_VALUE(0x02));
+#endif
break;
case 0x00100000:
out_be32(&ddr->sdram_md_cntl,
0x04000000 |
MD_CNTL_WRCW |
MD_CNTL_MD_VALUE(0x0a));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+ if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+ break;
+ while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
+ ;
+ out_be32(&ddr->sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL_CS2_CS3 |
+ 0x04000000 |
+ MD_CNTL_WRCW |
+ MD_CNTL_MD_VALUE(0x0a));
+#endif
break;
case 0x00200000:
out_be32(&ddr->sdram_md_cntl,
0x04000000 |
MD_CNTL_WRCW |
MD_CNTL_MD_VALUE(0x12));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+ if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+ break;
+ while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
+ ;
+ out_be32(&ddr->sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL_CS2_CS3 |
+ 0x04000000 |
+ MD_CNTL_WRCW |
+ MD_CNTL_MD_VALUE(0x12));
+#endif
break;
case 0x00300000:
out_be32(&ddr->sdram_md_cntl,
0x04000000 |
MD_CNTL_WRCW |
MD_CNTL_MD_VALUE(0x1a));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+ if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+ break;
+ while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
+ ;
+ out_be32(&ddr->sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL_CS2_CS3 |
+ 0x04000000 |
+ MD_CNTL_WRCW |
+ MD_CNTL_MD_VALUE(0x1a));
+#endif
break;
default:
out_be32(&ddr->sdram_md_cntl,
0x04000000 |
MD_CNTL_WRCW |
MD_CNTL_MD_VALUE(0x02));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+ if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+ break;
+ while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
+ ;
+ out_be32(&ddr->sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL_CS2_CS3 |
+ 0x04000000 |
+ MD_CNTL_WRCW |
+ MD_CNTL_MD_VALUE(0x02));
+#endif
printf("Unsupported RC10\n");
break;
}
out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
- out_be32(&ddr->debug[12], 0x0);
- out_be32(&ddr->debug[21], 0x0);
+ out_be32(&ddr->debug[12], save1);
+ out_be32(&ddr->debug[21], save2);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
}
{
unsigned long start_time_rx;
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
+ /*
+ * EEPROM chips that implement "address overflow" are ones
+ * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+ * address and the extra bits end up in the "chip address"
+ * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+ * four 256 byte chips.
+ *
+ * Note that we consider the length of the address field to
+ * still be one byte because the extra address bits are
+ * hidden in the chip address.
+ */
+ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+ addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
+
+ debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip,
+ addr);
+#endif
+
if (check_params(addr, alen, buffer, len))
return 1;
int nb = len;
unsigned long start_time_tx;
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
+ /*
+ * EEPROM chips that implement "address overflow" are ones
+ * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+ * address and the extra bits end up in the "chip address"
+ * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+ * four 256 byte chips.
+ *
+ * Note that we consider the length of the address field to
+ * still be one byte because the extra address bits are
+ * hidden in the chip address.
+ */
+ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+ addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
+
+ debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip,
+ addr);
+#endif
+
if (check_params(addr, alen, buffer, len))
return 1;
struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
struct fti2c010_regs *regs = chip->regs;
int ret, pos;
- uchar paddr[4];
+ uchar paddr[4] = { 0 };
to_i2c_addr(paddr, addr, alen);
struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
struct fti2c010_regs *regs = chip->regs;
int ret, pos;
- uchar paddr[4];
+ uchar paddr[4] = { 0 };
to_i2c_addr(paddr, addr, alen);
return 0;
ret = I2C_ADAP->set_bus_speed(I2C_ADAP, speed);
if (gd->flags & GD_FLG_RELOC)
- I2C_ADAP->speed = ret;
+ I2C_ADAP->speed = (ret == 0) ? speed : 0;
return ret;
}
/* set slave address, receive */
writel((chip << 1) | 1, &dev->icmar);
+ /* clear status */
+ writel(0, &dev->icmsr);
/* start master receive */
writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
- while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDE))
- != (MSR_MAT | MSR_MDE))
+ while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDR))
+ != (MSR_MAT | MSR_MDR))
udelay(10);
/* clear ESG */
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
int timeout = 1000;
+#ifdef CONFIG_ESDHC_DETECT_QUIRK
+ if (CONFIG_ESDHC_DETECT_QUIRK)
+ return 1;
+#endif
while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
udelay(1000);
if (caps & ESDHC_HOSTCAPBLT_HSS)
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
+ if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
+ mmc->host_caps &= ~MMC_MODE_8BIT;
+#endif
+
mmc->f_min = 400000;
mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000);
+++ /dev/null
-/*
- * linux/drivers/mmc/mmc_pxa.h
- *
- * Author: Vladimir Shebordaev, Igor Oblakov
- * Copyright: MontaVista Software Inc.
- *
- * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __MMC_PXA_P_H__
-#define __MMC_PXA_P_H__
-
-/* PXA-250 MMC controller registers */
-
-/* MMC_STRPCL */
-#define MMC_STRPCL_STOP_CLK (0x0001UL)
-#define MMC_STRPCL_START_CLK (0x0002UL)
-
-/* MMC_STAT */
-#define MMC_STAT_END_CMD_RES (0x0001UL << 13)
-#define MMC_STAT_PRG_DONE (0x0001UL << 12)
-#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11)
-#define MMC_STAT_CLK_EN (0x0001UL << 8)
-#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7)
-#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6)
-#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5)
-#define MMC_STAT_SPI_READ_ERROR_TOKEN (0x0001UL << 4)
-#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3)
-#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2)
-#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1)
-#define MMC_STAT_READ_TIME_OUT (0x0001UL)
-
-#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\
- |MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\
- |MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR)
-
-/* MMC_CLKRT */
-#define MMC_CLKRT_20MHZ (0x0000UL)
-#define MMC_CLKRT_10MHZ (0x0001UL)
-#define MMC_CLKRT_5MHZ (0x0002UL)
-#define MMC_CLKRT_2_5MHZ (0x0003UL)
-#define MMC_CLKRT_1_25MHZ (0x0004UL)
-#define MMC_CLKRT_0_625MHZ (0x0005UL)
-#define MMC_CLKRT_0_3125MHZ (0x0006UL)
-
-/* MMC_SPI */
-#define MMC_SPI_DISABLE (0x00UL)
-#define MMC_SPI_EN (0x01UL)
-#define MMC_SPI_CS_EN (0x01UL << 2)
-#define MMC_SPI_CS_ADDRESS (0x01UL << 3)
-#define MMC_SPI_CRC_ON (0x01UL << 1)
-
-/* MMC_CMDAT */
-#define MMC_CMDAT_SD_4DAT (0x0001UL << 8)
-#define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7)
-#define MMC_CMDAT_INIT (0x0001UL << 6)
-#define MMC_CMDAT_BUSY (0x0001UL << 5)
-#define MMC_CMDAT_BCR (0x0003UL << 5)
-#define MMC_CMDAT_STREAM (0x0001UL << 4)
-#define MMC_CMDAT_BLOCK (0x0000UL << 4)
-#define MMC_CMDAT_WRITE (0x0001UL << 3)
-#define MMC_CMDAT_READ (0x0000UL << 3)
-#define MMC_CMDAT_DATA_EN (0x0001UL << 2)
-#define MMC_CMDAT_R0 (0)
-#define MMC_CMDAT_R1 (0x0001UL)
-#define MMC_CMDAT_R2 (0x0002UL)
-#define MMC_CMDAT_R3 (0x0003UL)
-
-/* MMC_RESTO */
-#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */
-
-/* MMC_RDTO */
-#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */
-
-/* MMC_BLKLEN */
-#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */
-
-/* MMC_PRTBUF */
-#define MMC_PRTBUF_BUF_PART_FULL (0x01UL)
-#define MMC_PRTBUF_BUF_FULL (0x00UL )
-
-/* MMC_I_MASK */
-#define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6)
-#define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5)
-#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4)
-#define MMC_I_MASK_STOP_CMD (0x01UL << 3)
-#define MMC_I_MASK_END_CMD_RES (0x01UL << 2)
-#define MMC_I_MASK_PRG_DONE (0x01UL << 1)
-#define MMC_I_MASK_DATA_TRAN_DONE (0x01UL)
-#define MMC_I_MASK_ALL (0x07fUL)
-
-
-/* MMC_I_REG */
-#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6)
-#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5)
-#define MMC_I_REG_CLK_IS_OFF (0x01UL << 4)
-#define MMC_I_REG_STOP_CMD (0x01UL << 3)
-#define MMC_I_REG_END_CMD_RES (0x01UL << 2)
-#define MMC_I_REG_PRG_DONE (0x01UL << 1)
-#define MMC_I_REG_DATA_TRAN_DONE (0x01UL)
-#define MMC_I_REG_ALL (0x007fUL)
-
-/* MMC_CMD */
-#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */
-#define CMD(x) (x)
-
-#define MMC_DEFAULT_RCA 1
-
-#define MMC_BLOCK_SIZE 512
-#define MMC_MAX_BLOCK_SIZE 512
-
-#define MMC_R1_IDLE_STATE 0x01
-#define MMC_R1_ERASE_STATE 0x02
-#define MMC_R1_ILLEGAL_CMD 0x04
-#define MMC_R1_COM_CRC_ERR 0x08
-#define MMC_R1_ERASE_SEQ_ERR 0x01
-#define MMC_R1_ADDR_ERR 0x02
-#define MMC_R1_PARAM_ERR 0x04
-
-#define MMC_R1B_WP_ERASE_SKIP 0x0002
-#define MMC_R1B_ERR 0x0004
-#define MMC_R1B_CC_ERR 0x0008
-#define MMC_R1B_CARD_ECC_ERR 0x0010
-#define MMC_R1B_WP_VIOLATION 0x0020
-#define MMC_R1B_ERASE_PARAM 0x0040
-#define MMC_R1B_OOR 0x0080
-#define MMC_R1B_IDLE_STATE 0x0100
-#define MMC_R1B_ERASE_RESET 0x0200
-#define MMC_R1B_ILLEGAL_CMD 0x0400
-#define MMC_R1B_COM_CRC_ERR 0x0800
-#define MMC_R1B_ERASE_SEQ_ERR 0x1000
-#define MMC_R1B_ADDR_ERR 0x2000
-#define MMC_R1B_PARAM_ERR 0x4000
-
-#endif /* __MMC_PXA_P_H__ */
return __raw_readw((u16 *)marker) != 0xffff;
}
-static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
+#ifdef CONFIG_TPL_BUILD
+int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
+#else
+static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst)
+#endif
{
struct fsl_ifc *ifc = IFC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
int sram_addr;
int pg_no;
+ uchar *dst = vdst;
/* Get NAND Flash configuration */
csor = CONFIG_SYS_NAND_CSOR;
offs += page_size;
} while ((offs & (blk_size - 1)) && (pos < uboot_size));
}
+
+ return 0;
}
/*
+ * Defines a static function nand_load_image() here, because non-static makes
+ * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
+ */
+#ifndef CONFIG_TPL_BUILD
+#define nand_spl_load_image(offs, uboot_size, vdst) \
+ nand_load(offs, uboot_size, vdst)
+#endif
+
+/*
* Main entrypoint for NAND Boot. It's necessary that SDRAM is already
* configured and available since this code loads the main U-boot image
* from NAND into SDRAM and starts from there.
/*
* Load U-Boot image from NAND into RAM
*/
- nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
+ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
- nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST);
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_NAND_ENV_DST);
#ifdef CONFIG_ENV_OFFSET_REDUND
- nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+ nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
#endif
#endif
/*
mtd = &nand_info[nand_curr_device];
nand = mtd->priv;
nand->options |= NAND_OWN_BUFFERS;
+ nand->options &= ~NAND_SUBPAGE_READ;
/* Setup the ecc configurations again */
if (hardware) {
if (eccstrength == 1) {
obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
endif
-obj-$(CONFIG_CMD_SF) += sf.o
-obj-$(CONFIG_SPI_FLASH) += sf_probe.o sf_ops.o
+obj-$(CONFIG_CMD_SF) += sf.o
+obj-$(CONFIG_SPI_FLASH) += sf_params.o sf_probe.o sf_ops.o
obj-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
obj-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
unsigned long flags = SPI_XFER_BEGIN;
int ret;
+#ifdef CONFIG_SF_DUAL_FLASH
+ if (spi->flags & SPI_XFER_U_PAGE)
+ flags |= SPI_XFER_U_PAGE;
+#endif
if (data_len == 0)
flags |= SPI_XFER_END;
#ifndef _SF_INTERNAL_H_
#define _SF_INTERNAL_H_
+#define SPI_FLASH_3B_ADDR_LEN 3
+#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
#define SPI_FLASH_16MB_BOUN 0x1000000
-/* SECT flags */
-#define SECT_4K (1 << 1)
-#define SECT_32K (1 << 2)
-#define E_FSR (1 << 3)
+/* CFI Manufacture ID's */
+#define SPI_FLASH_CFI_MFR_SPANSION 0x01
+#define SPI_FLASH_CFI_MFR_STMICRO 0x20
+#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2
+#define SPI_FLASH_CFI_MFR_WINBOND 0xef
/* Erase commands */
#define CMD_ERASE_4K 0x20
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
#define CMD_READ_STATUS 0x05
+#define CMD_QUAD_PAGE_PROGRAM 0x32
#define CMD_READ_STATUS1 0x35
#define CMD_WRITE_ENABLE 0x06
#define CMD_READ_CONFIG 0x35
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
#define CMD_READ_ARRAY_FAST 0x0b
+#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
+#define CMD_READ_DUAL_IO_FAST 0xbb
+#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
+#define CMD_READ_QUAD_IO_FAST 0xeb
#define CMD_READ_ID 0x9f
/* Bank addr access commands */
#endif
/* Common status */
-#define STATUS_WIP 0x01
-#define STATUS_PEC 0x80
+#define STATUS_WIP (1 << 0)
+#define STATUS_QEB_WINSPAN (1 << 1)
+#define STATUS_QEB_MXIC (1 << 6)
+#define STATUS_PEC (1 << 7)
/* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
/* Flash erase(sectors) operation, support all possible erase commands */
int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
+/* Read the status register */
+int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
+
/* Program the status register */
-int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
+int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws);
+
+/* Read the config register */
+int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
-/* Set quad enbale bit */
-int spi_flash_set_qeb(struct spi_flash *flash);
+/* Program the config register */
+int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc);
/* Enable writing on the SPI flash */
static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
*/
#include <common.h>
+#include <malloc.h>
#include <spi.h>
#include <spi_flash.h>
#include <watchdog.h>
cmd[3] = addr >> 0;
}
-int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
+int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs)
+{
+ int ret;
+ u8 cmd;
+
+ cmd = CMD_READ_STATUS;
+ ret = spi_flash_read_common(flash, &cmd, 1, rs, 1);
+ if (ret < 0) {
+ debug("SF: fail to read status register\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws)
{
u8 cmd;
int ret;
cmd = CMD_WRITE_STATUS;
- ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
+ ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1);
if (ret < 0) {
debug("SF: fail to write status register\n");
return ret;
return 0;
}
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc)
+{
+ int ret;
+ u8 cmd;
+
+ cmd = CMD_READ_CONFIG;
+ ret = spi_flash_read_common(flash, &cmd, 1, rc, 1);
+ if (ret < 0) {
+ debug("SF: fail to read config register\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc)
+{
+ u8 data[2];
+ u8 cmd;
+ int ret;
+
+ ret = spi_flash_cmd_read_status(flash, &data[0]);
+ if (ret < 0)
+ return ret;
+
+ cmd = CMD_WRITE_STATUS;
+ data[1] = wc;
+ ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
+ if (ret) {
+ debug("SF: fail to write config register\n");
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
{
u8 bank_sel;
int ret;
- bank_sel = offset / SPI_FLASH_16MB_BOUN;
+ bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
if (ret) {
return ret;
}
- return 0;
+ return bank_sel;
+}
+#endif
+
+#ifdef CONFIG_SF_DUAL_FLASH
+static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr)
+{
+ switch (flash->dual_flash) {
+ case SF_DUAL_STACKED_FLASH:
+ if (*addr >= (flash->size >> 1)) {
+ *addr -= flash->size >> 1;
+ flash->spi->flags |= SPI_XFER_U_PAGE;
+ } else {
+ flash->spi->flags &= ~SPI_XFER_U_PAGE;
+ }
+ break;
+ case SF_DUAL_PARALLEL_FLASH:
+ *addr >>= flash->shift;
+ break;
+ default:
+ debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash);
+ break;
+ }
}
#endif
{
struct spi_slave *spi = flash->spi;
unsigned long timebase;
+ unsigned long flags = SPI_XFER_BEGIN;
int ret;
u8 status;
u8 check_status = 0x0;
check_status = poll_bit;
}
- ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
+#ifdef CONFIG_SF_DUAL_FLASH
+ if (spi->flags & SPI_XFER_U_PAGE)
+ flags |= SPI_XFER_U_PAGE;
+#endif
+ ret = spi_xfer(spi, 8, &cmd, NULL, flags);
if (ret) {
debug("SF: fail to read %s status register\n",
cmd == CMD_READ_STATUS ? "read" : "flag");
int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
{
- u32 erase_size;
- u8 cmd[4];
+ u32 erase_size, erase_addr;
+ u8 cmd[SPI_FLASH_CMD_LEN];
int ret = -1;
erase_size = flash->erase_size;
cmd[0] = flash->erase_cmd;
while (len) {
+ erase_addr = offset;
+
+#ifdef CONFIG_SF_DUAL_FLASH
+ if (flash->dual_flash > SF_SINGLE_FLASH)
+ spi_flash_dual_flash(flash, &erase_addr);
+#endif
#ifdef CONFIG_SPI_FLASH_BAR
- ret = spi_flash_bank(flash, offset);
+ ret = spi_flash_bank(flash, erase_addr);
if (ret < 0)
return ret;
#endif
- spi_flash_addr(offset, cmd);
+ spi_flash_addr(erase_addr, cmd);
debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
- cmd[2], cmd[3], offset);
+ cmd[2], cmd[3], erase_addr);
ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
if (ret < 0) {
size_t len, const void *buf)
{
unsigned long byte_addr, page_size;
+ u32 write_addr;
size_t chunk_len, actual;
- u8 cmd[4];
+ u8 cmd[SPI_FLASH_CMD_LEN];
int ret = -1;
page_size = flash->page_size;
- cmd[0] = CMD_PAGE_PROGRAM;
+ cmd[0] = flash->write_cmd;
for (actual = 0; actual < len; actual += chunk_len) {
+ write_addr = offset;
+
+#ifdef CONFIG_SF_DUAL_FLASH
+ if (flash->dual_flash > SF_SINGLE_FLASH)
+ spi_flash_dual_flash(flash, &write_addr);
+#endif
#ifdef CONFIG_SPI_FLASH_BAR
- ret = spi_flash_bank(flash, offset);
+ ret = spi_flash_bank(flash, write_addr);
if (ret < 0)
return ret;
#endif
if (flash->spi->max_write_size)
chunk_len = min(chunk_len, flash->spi->max_write_size);
- spi_flash_addr(offset, cmd);
+ spi_flash_addr(write_addr, cmd);
- debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
+ debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- u8 cmd[5], bank_sel = 0;
- u32 remain_len, read_len;
+ u8 *cmd, cmdsz;
+ u32 remain_len, read_len, read_addr;
+ int bank_sel = 0;
int ret = -1;
/* Handle memory-mapped SPI */
return 0;
}
- cmd[0] = CMD_READ_ARRAY_FAST;
- cmd[4] = 0x00;
+ cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
+ cmd = malloc(cmdsz);
+ memset(cmd, 0, cmdsz);
+ cmd[0] = flash->read_cmd;
while (len) {
-#ifdef CONFIG_SPI_FLASH_BAR
- bank_sel = offset / SPI_FLASH_16MB_BOUN;
+ read_addr = offset;
- ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
- if (ret) {
- debug("SF: fail to set bank%d\n", bank_sel);
+#ifdef CONFIG_SF_DUAL_FLASH
+ if (flash->dual_flash > SF_SINGLE_FLASH)
+ spi_flash_dual_flash(flash, &read_addr);
+#endif
+#ifdef CONFIG_SPI_FLASH_BAR
+ bank_sel = spi_flash_bank(flash, read_addr);
+ if (bank_sel < 0)
return ret;
- }
#endif
- remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset;
+ remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
+ (bank_sel + 1)) - offset;
if (len < remain_len)
read_len = len;
else
read_len = remain_len;
- spi_flash_addr(offset, cmd);
+ spi_flash_addr(read_addr, cmd);
- ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
- data, read_len);
+ ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
if (ret < 0) {
debug("SF: read failed\n");
break;
--- /dev/null
+/*
+ * SPI flash Params table
+ *
+ * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi_flash.h>
+
+#include "sf_internal.h"
+
+/* SPI/QSPI flash device params structure */
+const struct spi_flash_params spi_flash_params_table[] = {
+#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
+ {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, 0, SECT_4K},
+ {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, 0, SECT_4K},
+ {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, 0, SECT_4K},
+ {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, 0, SECT_4K},
+ {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, 0, SECT_4K},
+ {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, 0, SECT_4K},
+#endif
+#ifdef CONFIG_SPI_FLASH_EON /* EON */
+ {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0, 0},
+ {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0, 0},
+ {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0, 0},
+#endif
+#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
+ {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, 0, SECT_4K},
+#endif
+#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
+ {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0, 0},
+ {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0, 0},
+ {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0, 0},
+ {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0, 0},
+ {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0, 0},
+ {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0, 0},
+ {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
+ {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP},
+ {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP},
+ {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
+#endif
+#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
+ {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0, 0},
+ {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0, 0},
+ {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0, 0},
+ {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0, 0},
+ {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP},
+ {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP},
+ {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP},
+ {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, WR_QPP},
+ {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP},
+ {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, RD_FULL, WR_QPP},
+ {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
+ {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, RD_FULL, WR_QPP},
+ {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP},
+#endif
+#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
+ {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0},
+ {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0, 0},
+ {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0, 0},
+ {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0, 0},
+ {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0, 0},
+ {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0},
+ {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0},
+ {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0},
+ {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
+ {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
+ {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+ {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+ {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+ {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+#endif
+#ifdef CONFIG_SPI_FLASH_SST /* SST */
+ {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
+ {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
+ {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, 0, SECT_4K | SST_WP},
+ {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, 0, SECT_4K | SST_WP},
+ {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, 0, SECT_4K | SST_WP},
+ {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, 0, SECT_4K | SST_WP},
+ {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, 0, SECT_4K | SST_WP},
+ {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
+ {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
+#endif
+#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
+ {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0, 0},
+ {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0, 0},
+ {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0, 0},
+ {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, 0, SECT_4K},
+ {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, 0, SECT_4K},
+ {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
+ {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
+#endif
+ /*
+ * Note:
+ * Below paired flash devices has similar spi_flash params.
+ * (S25FL129P_64K, S25FL128S_64K)
+ * (W25Q80BL, W25Q80BV)
+ * (W25Q16CL, W25Q16DV)
+ * (W25Q32BV, W25Q32FV_SPI)
+ * (W25Q64CV, W25Q64FV_SPI)
+ * (W25Q128BV, W25Q128FV_SPI)
+ * (W25Q32DW, W25Q32FV_QPI)
+ * (W25Q64DW, W25Q64FV_QPI)
+ * (W25Q128FW, W25Q128FV_QPI)
+ */
+};
DECLARE_GLOBAL_DATA_PTR;
-/**
- * struct spi_flash_params - SPI/QSPI flash device params structure
- *
- * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
- * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
- * @ext_jedec: Device ext_jedec ID
- * @sector_size: Sector size of this device
- * @nr_sectors: No.of sectors on this device
- * @flags: Importent param, for flash specific behaviour
- */
-struct spi_flash_params {
- const char *name;
- u32 jedec;
- u16 ext_jedec;
- u32 sector_size;
- u32 nr_sectors;
- u16 flags;
+/* Read commands array */
+static u8 spi_read_cmds_array[] = {
+ CMD_READ_ARRAY_SLOW,
+ CMD_READ_DUAL_OUTPUT_FAST,
+ CMD_READ_DUAL_IO_FAST,
+ CMD_READ_QUAD_OUTPUT_FAST,
+ CMD_READ_QUAD_IO_FAST,
};
-static const struct spi_flash_params spi_flash_params_table[] = {
-#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
- {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, SECT_4K},
- {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, SECT_4K},
- {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, SECT_4K},
- {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, SECT_4K},
- {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, SECT_4K},
- {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, SECT_4K},
- {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, SECT_4K},
- {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, SECT_4K},
-#endif
-#ifdef CONFIG_SPI_FLASH_EON /* EON */
- {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0},
- {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, SECT_4K},
- {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0},
- {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0},
-#endif
-#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
- {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, SECT_4K},
- {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, SECT_4K},
-#endif
-#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
- {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0},
- {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0},
- {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0},
- {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0},
- {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0},
- {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0},
- {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, 0},
- {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, 0},
- {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, 0},
- {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, 0},
+#ifdef CONFIG_SPI_FLASH_MACRONIX
+static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
+{
+ u8 qeb_status;
+ int ret;
+
+ ret = spi_flash_cmd_read_status(flash, &qeb_status);
+ if (ret < 0)
+ return ret;
+
+ if (qeb_status & STATUS_QEB_MXIC) {
+ debug("SF: mxic: QEB is already set\n");
+ } else {
+ ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
+ if (ret < 0)
+ return ret;
+ }
+
+ return ret;
+}
#endif
-#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
- {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0},
- {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0},
- {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0},
- {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0},
- {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, 0},
- {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, 0},
- {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, 0},
- {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, 0},
- {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, 0},
- {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, 0},
- {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, 0},
- {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, 0},
- {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, 0},
+
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+static int spi_flash_set_qeb_winspan(struct spi_flash *flash)
+{
+ u8 qeb_status;
+ int ret;
+
+ ret = spi_flash_cmd_read_config(flash, &qeb_status);
+ if (ret < 0)
+ return ret;
+
+ if (qeb_status & STATUS_QEB_WINSPAN) {
+ debug("SF: winspan: QEB is already set\n");
+ } else {
+ ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN);
+ if (ret < 0)
+ return ret;
+ }
+
+ return ret;
+}
#endif
-#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
- {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0},
- {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0},
- {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0},
- {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0},
- {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0},
- {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0},
- {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0},
- {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0},
- {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, SECT_4K},
- {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, SECT_4K},
- {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, SECT_4K},
- {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, SECT_4K},
- {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, SECT_4K},
- {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, SECT_4K},
- {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, SECT_4K},
- {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, SECT_4K},
- {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, E_FSR | SECT_4K},
- {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, E_FSR | SECT_4K},
- {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, E_FSR | SECT_4K},
- {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, E_FSR | SECT_4K},
+
+static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
+{
+ switch (idcode0) {
+#ifdef CONFIG_SPI_FLASH_MACRONIX
+ case SPI_FLASH_CFI_MFR_MACRONIX:
+ return spi_flash_set_qeb_mxic(flash);
#endif
-#ifdef CONFIG_SPI_FLASH_SST /* SST */
- {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WP},
- {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WP},
- {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WP},
- {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WP},
- {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, SECT_4K},
- {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WP},
- {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WP},
- {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WP},
- {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WP},
- {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WP},
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+ case SPI_FLASH_CFI_MFR_SPANSION:
+ case SPI_FLASH_CFI_MFR_WINBOND:
+ return spi_flash_set_qeb_winspan(flash);
#endif
-#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
- {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0},
- {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0},
- {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0},
- {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, SECT_4K},
- {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, SECT_4K},
- {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, SECT_4K},
- {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, SECT_4K},
- {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, SECT_4K},
- {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, SECT_4K},
- {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, SECT_4K},
- {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, SECT_4K},
- {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, SECT_4K},
- {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, SECT_4K},
- {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, SECT_4K},
- {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, SECT_4K},
- {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, SECT_4K},
- {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, SECT_4K},
- {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, SECT_4K},
+#ifdef CONFIG_SPI_FLASH_STMICRO
+ case SPI_FLASH_CFI_MFR_STMICRO:
+ debug("SF: QEB is volatile for %02x flash\n", idcode0);
+ return 0;
#endif
- /*
- * Note:
- * Below paired flash devices has similar spi_flash params.
- * (S25FL129P_64K, S25FL128S_64K)
- * (W25Q80BL, W25Q80BV)
- * (W25Q16CL, W25Q16DV)
- * (W25Q32BV, W25Q32FV_SPI)
- * (W25Q64CV, W25Q64FV_SPI)
- * (W25Q128BV, W25Q128FV_SPI)
- * (W25Q32DW, W25Q32FV_QPI)
- * (W25Q64DW, W25Q64FV_QPI)
- * (W25Q128FW, W25Q128FV_QPI)
- */
-};
+ default:
+ printf("SF: Need set QEB func for %02x flash\n", idcode0);
+ return -1;
+ }
+}
static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
u8 *idcode)
{
const struct spi_flash_params *params;
struct spi_flash *flash;
- int i;
+ u8 cmd;
u16 jedec = idcode[1] << 8 | idcode[2];
u16 ext_jedec = idcode[3] << 8 | idcode[4];
- /* Get the flash id (jedec = manuf_id + dev_id, ext_jedec) */
- for (i = 0; i < ARRAY_SIZE(spi_flash_params_table); i++) {
- params = &spi_flash_params_table[i];
+ params = spi_flash_params_table;
+ for (; params->name != NULL; params++) {
if ((params->jedec >> 16) == idcode[0]) {
if ((params->jedec & 0xFFFF) == jedec) {
if (params->ext_jedec == 0)
}
}
- if (i == ARRAY_SIZE(spi_flash_params_table)) {
+ if (!params->name) {
printf("SF: Unsupported flash IDs: ");
printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
idcode[0], jedec, ext_jedec);
flash->spi = spi;
flash->name = params->name;
flash->memory_map = spi->memory_map;
+ flash->dual_flash = flash->spi->option;
/* Assign spi_flash ops */
flash->write = spi_flash_cmd_write_ops;
flash->read = spi_flash_cmd_read_ops;
/* Compute the flash size */
- flash->page_size = (ext_jedec == 0x4d00) ? 512 : 256;
- flash->sector_size = params->sector_size;
- flash->size = flash->sector_size * params->nr_sectors;
+ flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
+ flash->page_size = ((ext_jedec == 0x4d00) ? 512 : 256) << flash->shift;
+ flash->sector_size = params->sector_size << flash->shift;
+ flash->size = flash->sector_size * params->nr_sectors << flash->shift;
+#ifdef CONFIG_SF_DUAL_FLASH
+ if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
+ flash->size <<= 1;
+#endif
/* Compute erase sector and command */
if (params->flags & SECT_4K) {
flash->erase_cmd = CMD_ERASE_4K;
- flash->erase_size = 4096;
+ flash->erase_size = 4096 << flash->shift;
} else if (params->flags & SECT_32K) {
flash->erase_cmd = CMD_ERASE_32K;
- flash->erase_size = 32768;
+ flash->erase_size = 32768 << flash->shift;
} else {
flash->erase_cmd = CMD_ERASE_64K;
flash->erase_size = flash->sector_size;
}
- /* Poll cmd seclection */
+ /* Look for the fastest read cmd */
+ cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx);
+ if (cmd) {
+ cmd = spi_read_cmds_array[cmd - 1];
+ flash->read_cmd = cmd;
+ } else {
+ /* Go for default supported read cmd */
+ flash->read_cmd = CMD_READ_ARRAY_FAST;
+ }
+
+ /* Not require to look for fastest only two write cmds yet */
+ if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP)
+ flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
+ else
+ /* Go for default supported write cmd */
+ flash->write_cmd = CMD_PAGE_PROGRAM;
+
+ /* Set the quad enable bit - only for quad commands */
+ if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
+ (flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
+ (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
+ if (spi_flash_set_qeb(flash, idcode[0])) {
+ debug("SF: Fail to set QEB for %02x\n", idcode[0]);
+ return NULL;
+ }
+ }
+
+ /* Read dummy_byte: dummy byte is determined based on the
+ * dummy cycles of a particular command.
+ * Fast commands - dummy_byte = dummy_cycles/8
+ * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8
+ * For I/O commands except cmd[0] everything goes on no.of lines
+ * based on particular command but incase of fast commands except
+ * data all go on single line irrespective of command.
+ */
+ switch (flash->read_cmd) {
+ case CMD_READ_QUAD_IO_FAST:
+ flash->dummy_byte = 2;
+ break;
+ case CMD_READ_ARRAY_SLOW:
+ flash->dummy_byte = 0;
+ break;
+ default:
+ flash->dummy_byte = 1;
+ }
+
+ /* Poll cmd selection */
flash->poll_cmd = CMD_READ_STATUS;
#ifdef CONFIG_SPI_FLASH_STMICRO
if (params->flags & E_FSR)
puts("\n");
#endif
#ifndef CONFIG_SPI_FLASH_BAR
- if (flash->size > SPI_FLASH_16MB_BOUN) {
+ if (((flash->dual_flash == SF_SINGLE_FLASH) &&
+ (flash->size > SPI_FLASH_16MB_BOUN)) ||
+ ((flash->dual_flash > SF_SINGLE_FLASH) &&
+ (flash->size > SPI_FLASH_16MB_BOUN << 1))) {
puts("SF: Warning - Only lower 16MiB accessible,");
puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
}
"status", "disabled", strlen("disabled") + 1, 1);
}
-#ifdef CONFIG_SYS_FMAN_V3
-static int ft_fixup_xgec(void *blob, struct fm_eth_info *info)
-{
- int off, i, ci;
-#define FM1_10GEC3_RX_PORT_ADDR (CONFIG_SYS_CCSRBAR_PHYS + 0x488000)
-#define FM1_10GEC3_TX_PORT_ADDR (CONFIG_SYS_CCSRBAR_PHYS + 0x4a8000)
-#define FM1_10GEC3_MAC_ADDR (CONFIG_SYS_CCSRBAR_PHYS + 0x4e0000)
-
- if ((info->port == FM1_10GEC3) || (info->port == FM1_10GEC4)) {
- ci = (info->port == FM1_10GEC3) ? 2 : 3;
- i = (info->port == FM1_10GEC3) ? 0 : 1;
-
- off = fdt_node_offset_by_compat_reg(blob, "fsl,fman-port-1g-rx",
- FM1_10GEC3_RX_PORT_ADDR +
- i * 0x1000);
- if (off > 0) {
- fdt_setprop(blob, off, "cell-index", &ci, sizeof(int));
- fdt_setprop(blob, off, "compatible",
- "fsl,fman-port-10g-rx", 20);
- } else {
- goto err;
- }
-
- off = fdt_node_offset_by_compat_reg(blob, "fsl,fman-port-1g-tx",
- FM1_10GEC3_TX_PORT_ADDR +
- i * 0x1000);
- if (off > 0) {
- fdt_setprop(blob, off, "cell-index", &ci, sizeof(int));
- fdt_setprop(blob, off, "compatible",
- "fsl,fman-port-10g-tx", 20);
- } else {
- goto err;
- }
-
- off = fdt_node_offset_by_compat_reg(blob, "fsl,fman-memac",
- FM1_10GEC3_MAC_ADDR +
- i * 0x2000);
- if (off > 0)
- fdt_setprop(blob, off, "cell-index", &ci, sizeof(int));
- else
- goto err;
- }
- return 0;
-err:
- printf("WARNING: Fail to find the node\n");
- return -1;
-}
-#endif
-
void fdt_fixup_fman_ethernet(void *blob)
{
int i;
#ifdef CONFIG_SYS_FMAN_V3
- for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
+ for (i = 0; i < ARRAY_SIZE(fm_info); i++)
ft_fixup_port(blob, &fm_info[i], "fsl,fman-memac");
- ft_fixup_xgec(blob, &fm_info[i]);
- }
#else
for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
if (fm_info[i].type == FM_ETH_1G_E)
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
- if ((port == FM1_10GEC1 || port == FM1_10GEC2 ||
- port == FM1_10GEC3 || port == FM1_10GEC4) &&
+ if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
((is_serdes_configured(XAUI_FM1_MAC9)) ||
- (is_serdes_configured(XFI_FM1_MAC1)) ||
- (is_serdes_configured(XFI_FM1_MAC2)) ||
(is_serdes_configured(XFI_FM1_MAC9)) ||
(is_serdes_configured(XFI_FM1_MAC10))))
return PHY_INTERFACE_MODE_XGMII;
+ if ((port == FM1_10GEC3 || port == FM1_10GEC4) &&
+ ((is_serdes_configured(XFI_FM1_MAC1)) ||
+ (is_serdes_configured(XFI_FM1_MAC2))))
+ return PHY_INTERFACE_MODE_XGMII;
+
if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII))
return PHY_INTERFACE_MODE_RGMII;
+++ /dev/null
-/****************************************************************************
- * Copyright(c) 2000-2001 Broadcom Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation.
- *
- * Name: nicext.h
- *
- * Description: Broadcom Network Interface Card Extension (NICE) is an
- * extension to Linux NET device kernel mode drivers.
- * NICE is designed to provide additional functionalities,
- * such as receive packet intercept. To support Broadcom NICE,
- * the network device driver can be modified by adding an
- * device ioctl handler and by indicating receiving packets
- * to the NICE receive handler. Broadcom NICE will only be
- * enabled by a NICE-aware intermediate driver, such as
- * Broadcom Advanced Server Program Driver (BASP). When NICE
- * is not enabled, the modified network device drivers
- * functions exactly as other non-NICE aware drivers.
- *
- * Author: Frankie Fan
- *
- * Created: September 17, 2000
- *
- ****************************************************************************/
-#ifndef _nicext_h_
-#define _nicext_h_
-
-/*
- * ioctl for NICE
- */
-#define SIOCNICE SIOCDEVPRIVATE+7
-
-/*
- * SIOCNICE:
- *
- * The following structure needs to be less than IFNAMSIZ (16 bytes) because
- * we're overloading ifreq.ifr_ifru.
- *
- * If 16 bytes is not enough, we should consider relaxing this because
- * this is no field after ifr_ifru in the ifreq structure. But we may
- * run into future compatiability problem in case of changing struct ifreq.
- */
-struct nice_req
-{
- __u32 cmd;
-
- union
- {
-#ifdef __KERNEL__
- /* cmd = NICE_CMD_SET_RX or NICE_CMD_GET_RX */
- struct
- {
- void (*nrqus1_rx)( struct sk_buff*, void* );
- void* nrqus1_ctx;
- } nrqu_nrqus1;
-
- /* cmd = NICE_CMD_QUERY_SUPPORT */
- struct
- {
- __u32 nrqus2_magic;
- __u32 nrqus2_support_rx:1;
- __u32 nrqus2_support_vlan:1;
- __u32 nrqus2_support_get_speed:1;
- } nrqu_nrqus2;
-#endif
-
- /* cmd = NICE_CMD_GET_SPEED */
- struct
- {
- unsigned int nrqus3_speed; /* 0 if link is down, */
- /* otherwise speed in Mbps */
- } nrqu_nrqus3;
-
- /* cmd = NICE_CMD_BLINK_LED */
- struct
- {
- unsigned int nrqus4_blink_time; /* blink duration in seconds */
- } nrqu_nrqus4;
-
- } nrq_nrqu;
-};
-
-#define nrq_rx nrq_nrqu.nrqu_nrqus1.nrqus1_rx
-#define nrq_ctx nrq_nrqu.nrqu_nrqus1.nrqus1_ctx
-#define nrq_support_rx nrq_nrqu.nrqu_nrqus2.nrqus2_support_rx
-#define nrq_magic nrq_nrqu.nrqu_nrqus2.nrqus2_magic
-#define nrq_support_vlan nrq_nrqu.nrqu_nrqus2.nrqus2_support_vlan
-#define nrq_support_get_speed nrq_nrqu.nrqu_nrqus2.nrqus2_support_get_speed
-#define nrq_speed nrq_nrqu.nrqu_nrqus3.nrqus3_speed
-#define nrq_blink_time nrq_nrqu.nrqu_nrqus4.nrqus4_blink_time
-
-/*
- * magic constants
- */
-#define NICE_REQUESTOR_MAGIC 0x4543494E /* NICE in ascii */
-#define NICE_DEVICE_MAGIC 0x4E494345 /* ECIN in ascii */
-
-/*
- * command field
- */
-#define NICE_CMD_QUERY_SUPPORT 0x00000001
-#define NICE_CMD_SET_RX 0x00000002
-#define NICE_CMD_GET_RX 0x00000003
-#define NICE_CMD_GET_SPEED 0x00000004
-#define NICE_CMD_BLINK_LED 0x00000005
-
-#endif /* _nicext_h_ */
static struct phy_driver AR8031_driver = {
.name = "AR8031/AR8033",
.uid = 0x4dd074,
- .mask = 0x4fffff,
+ .mask = 0xffffffef,
.features = PHY_GBIT_FEATURES,
.config = ar8021_config,
.startup = genphy_startup,
static struct phy_driver AR8035_driver = {
.name = "AR8035",
.uid = 0x4dd072,
- .mask = 0x4fffff,
+ .mask = 0xffffffef,
.features = PHY_GBIT_FEATURES,
.config = ar8035_config,
.startup = genphy_startup,
int ret = 0;
int i;
- for (i = 0; i < num; i++, addr++)
- ret |= pmic_reg_write(p, addr, *(data + i));
+ for (i = 0; i < num; i++, addr++) {
+ ret = pmic_reg_write(p, addr, *(data + i));
+ if (ret)
+ return ret;
+ }
- return ret;
+ return 0;
}
static int fg_read_regs(struct pmic *p, u8 addr, u16 *data, int num)
{
+ unsigned int dat;
int ret = 0;
int i;
- for (i = 0; i < num; i++, addr++)
- ret |= pmic_reg_read(p, addr, (u32 *) (data + i));
+ for (i = 0; i < num; i++, addr++) {
+ ret = pmic_reg_read(p, addr, &dat);
+ if (ret)
+ return ret;
- return ret;
+ *(data + i) = (u16)dat;
+ }
+
+ return 0;
}
static int fg_write_and_verify(struct pmic *p, u8 addr, u16 data)
static void por_fuelgauge_init(struct pmic *p)
{
u16 r_data0[16], r_data1[16], r_data2[16];
- u32 rewrite_count = 5, i = 0;
- unsigned int val;
- int ret = 0;
+ u32 rewrite_count = 5;
+ u32 check_count;
+ u32 lock_count;
+ u32 i = 0;
+ u32 val;
+ s32 ret = 0;
+ char *status_msg;
/* Delay 500 ms */
mdelay(500);
pmic_reg_write(p, MAX17042_CONFIG, 0x2310);
rewrite_model:
+ check_count = 5;
+ lock_count = 5;
+
+ if (!rewrite_count--) {
+ status_msg = "init failed!";
+ goto error;
+ }
+
/* Unlock Model Access */
pmic_reg_write(p, MAX17042_MLOCKReg1, MODEL_UNLOCK1);
pmic_reg_write(p, MAX17042_MLOCKReg2, MODEL_UNLOCK2);
/* Write/Read/Verify the Custom Model */
- ret |= fg_write_regs(p, MAX17042_MODEL1, cell_character0,
+ ret = fg_write_regs(p, MAX17042_MODEL1, cell_character0,
ARRAY_SIZE(cell_character0));
- ret |= fg_write_regs(p, MAX17042_MODEL2, cell_character1,
+ if (ret)
+ goto rewrite_model;
+
+ ret = fg_write_regs(p, MAX17042_MODEL2, cell_character1,
ARRAY_SIZE(cell_character1));
- ret |= fg_write_regs(p, MAX17042_MODEL3, cell_character2,
+ if (ret)
+ goto rewrite_model;
+
+ ret = fg_write_regs(p, MAX17042_MODEL3, cell_character2,
ARRAY_SIZE(cell_character2));
+ if (ret)
+ goto rewrite_model;
- if (ret) {
- printf("%s: Cell parameters write failed!\n", __func__);
- return;
+check_model:
+ if (!check_count--) {
+ if (rewrite_count)
+ goto rewrite_model;
+ else
+ status_msg = "check failed!";
+
+ goto error;
}
- ret |= fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0));
- ret |= fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1));
- ret |= fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2));
+ ret = fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0));
+ if (ret)
+ goto check_model;
+
+ ret = fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1));
+ if (ret)
+ goto check_model;
+ ret = fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2));
if (ret)
- printf("%s: Cell parameters read failed!\n", __func__);
+ goto check_model;
for (i = 0; i < 16; i++) {
if ((cell_character0[i] != r_data0[i])
goto rewrite_model;
}
+lock_model:
+ if (!lock_count--) {
+ if (rewrite_count)
+ goto rewrite_model;
+ else
+ status_msg = "lock failed!";
+
+ goto error;
+ }
+
/* Lock model access */
pmic_reg_write(p, MAX17042_MLOCKReg1, MODEL_LOCK1);
pmic_reg_write(p, MAX17042_MLOCKReg2, MODEL_LOCK2);
/* Verify the model access is locked */
- ret |= fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0));
- ret |= fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1));
- ret |= fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2));
+ ret = fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0));
+ if (ret)
+ goto lock_model;
- if (ret) {
- printf("%s: Cell parameters read failed!\n", __func__);
- return;
- }
+ ret = fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1));
+ if (ret)
+ goto lock_model;
+
+ ret = fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2));
+ if (ret)
+ goto lock_model;
for (i = 0; i < ARRAY_SIZE(r_data0); i++) {
/* Check if model locked */
- if (r_data0[i] || r_data1[i] || r_data2[i]) {
- /* Rewrite model data - prevent from endless loop */
- if (rewrite_count--) {
- puts("FG - Lock model access failed!\n");
- goto rewrite_model;
- }
- }
+ if (r_data0[i] || r_data1[i] || r_data2[i])
+ goto lock_model;
}
/* Write Custom Parameters */
/* Delay at least 350 ms */
mdelay(350);
+
+ status_msg = "OK!";
+error:
+ debug("%s: model init status: %s\n", p->name, status_msg);
+ return;
}
static int power_update_battery(struct pmic *p, struct pmic *bat)
ret |= pmic_reg_read(p, MAX17042_STATUS, &val);
debug("fg status: 0x%x\n", val);
- if (val == MAX17042_POR)
+ if (val & MAX17042_POR)
por_fuelgauge_init(p);
ret |= pmic_reg_read(p, MAX17042_VERSION, &val);
obj-$(CONFIG_CF_QSPI) += cf_qspi.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
+obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/compat.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <spi.h>
+
+#ifndef CONFIG_FTSSP010_BASE_LIST
+#define CONFIG_FTSSP010_BASE_LIST { CONFIG_FTSSP010_BASE }
+#endif
+
+#ifndef CONFIG_FTSSP010_GPIO_BASE
+#define CONFIG_FTSSP010_GPIO_BASE 0
+#endif
+
+#ifndef CONFIG_FTSSP010_GPIO_LIST
+#define CONFIG_FTSSP010_GPIO_LIST { CONFIG_FTSSP010_GPIO_BASE }
+#endif
+
+#ifndef CONFIG_FTSSP010_CLOCK
+#define CONFIG_FTSSP010_CLOCK clk_get_rate("SSP");
+#endif
+
+#ifndef CONFIG_FTSSP010_TIMEOUT
+#define CONFIG_FTSSP010_TIMEOUT 100
+#endif
+
+/* FTSSP010 chip registers */
+struct ftssp010_regs {
+ uint32_t cr[3];/* control register */
+ uint32_t sr; /* status register */
+ uint32_t icr; /* interrupt control register */
+ uint32_t isr; /* interrupt status register */
+ uint32_t dr; /* data register */
+ uint32_t rsvd[17];
+ uint32_t revr; /* revision register */
+ uint32_t fear; /* feature register */
+};
+
+/* Control Register 0 */
+#define CR0_FFMT_MASK (7 << 12)
+#define CR0_FFMT_SSP (0 << 12)
+#define CR0_FFMT_SPI (1 << 12)
+#define CR0_FFMT_MICROWIRE (2 << 12)
+#define CR0_FFMT_I2S (3 << 12)
+#define CR0_FFMT_AC97 (4 << 12)
+#define CR0_FLASH (1 << 11)
+#define CR0_FSDIST(x) (((x) & 0x03) << 8)
+#define CR0_LOOP (1 << 7) /* loopback mode */
+#define CR0_LSB (1 << 6) /* LSB */
+#define CR0_FSPO (1 << 5) /* fs atcive low (I2S only) */
+#define CR0_FSJUSTIFY (1 << 4)
+#define CR0_OPM_SLAVE (0 << 2)
+#define CR0_OPM_MASTER (3 << 2)
+#define CR0_OPM_I2S_MSST (3 << 2) /* master stereo mode */
+#define CR0_OPM_I2S_MSMO (2 << 2) /* master mono mode */
+#define CR0_OPM_I2S_SLST (1 << 2) /* slave stereo mode */
+#define CR0_OPM_I2S_SLMO (0 << 2) /* slave mono mode */
+#define CR0_SCLKPO (1 << 1) /* clock polarity */
+#define CR0_SCLKPH (1 << 0) /* clock phase */
+
+/* Control Register 1 */
+#define CR1_PDL(x) (((x) & 0xff) << 24) /* padding length */
+#define CR1_SDL(x) ((((x) - 1) & 0x1f) << 16) /* data length */
+#define CR1_DIV(x) (((x) - 1) & 0xffff) /* clock divider */
+
+/* Control Register 2 */
+#define CR2_CS(x) (((x) & 3) << 10) /* CS/FS select */
+#define CR2_FS (1 << 9) /* CS/FS signal level */
+#define CR2_TXEN (1 << 8) /* tx enable */
+#define CR2_RXEN (1 << 7) /* rx enable */
+#define CR2_RESET (1 << 6) /* chip reset */
+#define CR2_TXFC (1 << 3) /* tx fifo Clear */
+#define CR2_RXFC (1 << 2) /* rx fifo Clear */
+#define CR2_TXDOE (1 << 1) /* tx data output enable */
+#define CR2_EN (1 << 0) /* chip enable */
+
+/* Status Register */
+#define SR_RFF (1 << 0) /* rx fifo full */
+#define SR_TFNF (1 << 1) /* tx fifo not full */
+#define SR_BUSY (1 << 2) /* chip busy */
+#define SR_RFVE(reg) (((reg) >> 4) & 0x1f) /* rx fifo valid entries */
+#define SR_TFVE(reg) (((reg) >> 12) & 0x1f) /* tx fifo valid entries */
+
+/* Feature Register */
+#define FEAR_BITS(reg) ((((reg) >> 0) & 0xff) + 1) /* data width */
+#define FEAR_RFSZ(reg) ((((reg) >> 8) & 0xff) + 1) /* rx fifo size */
+#define FEAR_TFSZ(reg) ((((reg) >> 16) & 0xff) + 1) /* tx fifo size */
+#define FEAR_AC97 (1 << 24)
+#define FEAR_I2S (1 << 25)
+#define FEAR_SPI_MWR (1 << 26)
+#define FEAR_SSP (1 << 27)
+#define FEAR_SPDIF (1 << 28)
+
+/* FTGPIO010 chip registers */
+struct ftgpio010_regs {
+ uint32_t out; /* 0x00: Data Output */
+ uint32_t in; /* 0x04: Data Input */
+ uint32_t dir; /* 0x08: Direction */
+ uint32_t bypass; /* 0x0c: Bypass */
+ uint32_t set; /* 0x10: Data Set */
+ uint32_t clr; /* 0x14: Data Clear */
+ uint32_t pull_up; /* 0x18: Pull-Up Enabled */
+ uint32_t pull_st; /* 0x1c: Pull State (0=pull-down, 1=pull-up) */
+};
+
+struct ftssp010_gpio {
+ struct ftgpio010_regs *regs;
+ uint32_t pin;
+};
+
+struct ftssp010_spi {
+ struct spi_slave slave;
+ struct ftssp010_gpio gpio;
+ struct ftssp010_regs *regs;
+ uint32_t fifo;
+ uint32_t mode;
+ uint32_t div;
+ uint32_t clk;
+ uint32_t speed;
+ uint32_t revision;
+};
+
+static inline struct ftssp010_spi *to_ftssp010_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct ftssp010_spi, slave);
+}
+
+static int get_spi_chip(int bus, struct ftssp010_spi *chip)
+{
+ uint32_t fear, base[] = CONFIG_FTSSP010_BASE_LIST;
+
+ if (bus >= ARRAY_SIZE(base) || !base[bus])
+ return -1;
+
+ chip->regs = (struct ftssp010_regs *)base[bus];
+
+ chip->revision = readl(&chip->regs->revr);
+
+ fear = readl(&chip->regs->fear);
+ chip->fifo = min_t(uint32_t, FEAR_TFSZ(fear), FEAR_RFSZ(fear));
+
+ return 0;
+}
+
+static int get_spi_gpio(int bus, struct ftssp010_gpio *chip)
+{
+ uint32_t base[] = CONFIG_FTSSP010_GPIO_LIST;
+
+ if (bus >= ARRAY_SIZE(base) || !base[bus])
+ return -1;
+
+ chip->regs = (struct ftgpio010_regs *)(base[bus] & 0xfff00000);
+ chip->pin = base[bus] & 0x1f;
+
+ /* make it an output pin */
+ setbits_le32(&chip->regs->dir, 1 << chip->pin);
+
+ return 0;
+}
+
+static int ftssp010_wait(struct ftssp010_spi *chip)
+{
+ struct ftssp010_regs *regs = chip->regs;
+ int ret = -1;
+ ulong t;
+
+ /* wait until device idle */
+ for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
+ if (readl(®s->sr) & SR_BUSY)
+ continue;
+ ret = 0;
+ break;
+ }
+
+ if (ret)
+ puts("ftspi010: busy timeout\n");
+
+ return ret;
+}
+
+static int ftssp010_wait_tx(struct ftssp010_spi *chip)
+{
+ struct ftssp010_regs *regs = chip->regs;
+ int ret = -1;
+ ulong t;
+
+ /* wait until tx fifo not full */
+ for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
+ if (!(readl(®s->sr) & SR_TFNF))
+ continue;
+ ret = 0;
+ break;
+ }
+
+ if (ret)
+ puts("ftssp010: tx timeout\n");
+
+ return ret;
+}
+
+static int ftssp010_wait_rx(struct ftssp010_spi *chip)
+{
+ struct ftssp010_regs *regs = chip->regs;
+ int ret = -1;
+ ulong t;
+
+ /* wait until rx fifo not empty */
+ for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
+ if (!SR_RFVE(readl(®s->sr)))
+ continue;
+ ret = 0;
+ break;
+ }
+
+ if (ret)
+ puts("ftssp010: rx timeout\n");
+
+ return ret;
+}
+
+static int ftssp010_spi_work_transfer_v2(struct ftssp010_spi *chip,
+ const void *tx_buf, void *rx_buf, int len, uint flags)
+{
+ struct ftssp010_regs *regs = chip->regs;
+ const uint8_t *txb = tx_buf;
+ uint8_t *rxb = rx_buf;
+
+ while (len > 0) {
+ int i, depth = min(chip->fifo >> 2, len);
+ uint32_t xmsk = 0;
+
+ if (tx_buf) {
+ for (i = 0; i < depth; ++i) {
+ ftssp010_wait_tx(chip);
+ writel(*txb++, ®s->dr);
+ }
+ xmsk |= CR2_TXEN | CR2_TXDOE;
+ if ((readl(®s->cr[2]) & xmsk) != xmsk)
+ setbits_le32(®s->cr[2], xmsk);
+ }
+ if (rx_buf) {
+ xmsk |= CR2_RXEN;
+ if ((readl(®s->cr[2]) & xmsk) != xmsk)
+ setbits_le32(®s->cr[2], xmsk);
+ for (i = 0; i < depth; ++i) {
+ ftssp010_wait_rx(chip);
+ *rxb++ = (uint8_t)readl(®s->dr);
+ }
+ }
+
+ len -= depth;
+ }
+
+ return 0;
+}
+
+static int ftssp010_spi_work_transfer_v1(struct ftssp010_spi *chip,
+ const void *tx_buf, void *rx_buf, int len, uint flags)
+{
+ struct ftssp010_regs *regs = chip->regs;
+ const uint8_t *txb = tx_buf;
+ uint8_t *rxb = rx_buf;
+
+ while (len > 0) {
+ int i, depth = min(chip->fifo >> 2, len);
+ uint32_t tmp;
+
+ for (i = 0; i < depth; ++i) {
+ ftssp010_wait_tx(chip);
+ writel(txb ? (*txb++) : 0, ®s->dr);
+ }
+ for (i = 0; i < depth; ++i) {
+ ftssp010_wait_rx(chip);
+ tmp = readl(®s->dr);
+ if (rxb)
+ *rxb++ = (uint8_t)tmp;
+ }
+
+ len -= depth;
+ }
+
+ return 0;
+}
+
+static void ftssp010_cs_set(struct ftssp010_spi *chip, int high)
+{
+ struct ftssp010_regs *regs = chip->regs;
+ struct ftssp010_gpio *gpio = &chip->gpio;
+ uint32_t mask;
+
+ /* cs pull high/low */
+ if (chip->revision >= 0x11900) {
+ mask = CR2_CS(chip->slave.cs) | (high ? CR2_FS : 0);
+ writel(mask, ®s->cr[2]);
+ } else if (gpio->regs) {
+ mask = 1 << gpio->pin;
+ if (high)
+ writel(mask, &gpio->regs->set);
+ else
+ writel(mask, &gpio->regs->clr);
+ }
+
+ /* extra delay for signal propagation */
+ udelay_masked(1);
+}
+
+/*
+ * Determine if a SPI chipselect is valid.
+ * This function is provided by the board if the low-level SPI driver
+ * needs it to determine if a given chipselect is actually valid.
+ *
+ * Returns: 1 if bus:cs identifies a valid chip on this board, 0
+ * otherwise.
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ struct ftssp010_spi chip;
+
+ if (get_spi_chip(bus, &chip))
+ return 0;
+
+ if (!cs)
+ return 1;
+ else if ((cs < 4) && (chip.revision >= 0x11900))
+ return 1;
+
+ return 0;
+}
+
+/*
+ * Activate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should activate the chip select
+ * to the device identified by "slave".
+ */
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct ftssp010_spi *chip = to_ftssp010_spi(slave);
+ struct ftssp010_regs *regs = chip->regs;
+
+ /* cs pull */
+ if (chip->mode & SPI_CS_HIGH)
+ ftssp010_cs_set(chip, 1);
+ else
+ ftssp010_cs_set(chip, 0);
+
+ /* chip enable + fifo clear */
+ setbits_le32(®s->cr[2], CR2_EN | CR2_TXFC | CR2_RXFC);
+}
+
+/*
+ * Deactivate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should deactivate the chip
+ * select to the device identified by "slave".
+ */
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct ftssp010_spi *chip = to_ftssp010_spi(slave);
+
+ /* wait until chip idle */
+ ftssp010_wait(chip);
+
+ /* cs pull */
+ if (chip->mode & SPI_CS_HIGH)
+ ftssp010_cs_set(chip, 0);
+ else
+ ftssp010_cs_set(chip, 1);
+}
+
+void spi_init(void)
+{
+ /* nothing to do */
+}
+
+struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
+{
+ struct ftssp010_spi *chip;
+
+ if (mode & SPI_3WIRE) {
+ puts("ftssp010: can't do 3-wire\n");
+ return NULL;
+ }
+
+ if (mode & SPI_SLAVE) {
+ puts("ftssp010: can't do slave mode\n");
+ return NULL;
+ }
+
+ if (mode & SPI_PREAMBLE) {
+ puts("ftssp010: can't skip preamble bytes\n");
+ return NULL;
+ }
+
+ if (!spi_cs_is_valid(bus, cs)) {
+ puts("ftssp010: invalid (bus, cs)\n");
+ return NULL;
+ }
+
+ chip = spi_alloc_slave(struct ftssp010_spi, bus, cs);
+ if (!chip)
+ return NULL;
+
+ if (get_spi_chip(bus, chip))
+ goto free_out;
+
+ if (chip->revision < 0x11900 && get_spi_gpio(bus, &chip->gpio)) {
+ puts("ftssp010: Before revision 1.19.0, its clock & cs are\n"
+ "controlled by tx engine which is not synced with rx engine,\n"
+ "so the clock & cs might be shutdown before rx engine\n"
+ "finishs its jobs.\n"
+ "If possible, please add a dedicated gpio for it.\n");
+ }
+
+ chip->mode = mode;
+ chip->clk = CONFIG_FTSSP010_CLOCK;
+ chip->div = 2;
+ if (max_hz) {
+ while (chip->div < 0xffff) {
+ if ((chip->clk / (2 * chip->div)) <= max_hz)
+ break;
+ chip->div += 1;
+ }
+ }
+ chip->speed = chip->clk / (2 * chip->div);
+
+ return &chip->slave;
+
+free_out:
+ free(chip);
+ return NULL;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ free(slave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct ftssp010_spi *chip = to_ftssp010_spi(slave);
+ struct ftssp010_regs *regs = chip->regs;
+
+ writel(CR1_SDL(8) | CR1_DIV(chip->div), ®s->cr[1]);
+
+ if (chip->revision >= 0x11900) {
+ writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO | CR0_FLASH,
+ ®s->cr[0]);
+ writel(CR2_TXFC | CR2_RXFC,
+ ®s->cr[2]);
+ } else {
+ writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO,
+ ®s->cr[0]);
+ writel(CR2_TXFC | CR2_RXFC | CR2_EN | CR2_TXDOE,
+ ®s->cr[2]);
+ }
+
+ if (chip->mode & SPI_LOOP)
+ setbits_le32(®s->cr[0], CR0_LOOP);
+
+ if (chip->mode & SPI_CPOL)
+ setbits_le32(®s->cr[0], CR0_SCLKPO);
+
+ if (chip->mode & SPI_CPHA)
+ setbits_le32(®s->cr[0], CR0_SCLKPH);
+
+ spi_cs_deactivate(slave);
+
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct ftssp010_spi *chip = to_ftssp010_spi(slave);
+ struct ftssp010_regs *regs = chip->regs;
+
+ writel(0, ®s->cr[2]);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct ftssp010_spi *chip = to_ftssp010_spi(slave);
+ uint32_t len = bitlen >> 3;
+
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(slave);
+
+ if (chip->revision >= 0x11900)
+ ftssp010_spi_work_transfer_v2(chip, dout, din, len, flags);
+ else
+ ftssp010_spi_work_transfer_v1(chip, dout, din, len, flags);
+
+ if (flags & SPI_XFER_END)
+ spi_cs_deactivate(slave);
+
+ return 0;
+}
#include <common.h>
#include <malloc.h>
#include <spi.h>
+#include <asm/arch/rmobile.h>
#include <asm/io.h>
/* SH QSPI register bit masks <REG>_<BIT> */
return NULL;
}
- ss->regs = (struct sh_qspi_regs *)CONFIG_SH_QSPI_BASE;
+ ss->regs = (struct sh_qspi_regs *)SH_QSPI_BASE;
/* Init SH QSPI */
sh_qspi_init(ss);
{
int i, cur_len, ret = 0;
int remain = (int)len;
- unsigned long tmp;
if (len >= SH_SPI_FIFO_SIZE)
sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
}
if (flags & SPI_XFER_END) {
- tmp = sh_spi_read(&ss->regs->cr1);
- tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB);
- sh_spi_write(tmp, &ss->regs->cr1);
+ sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
udelay(100);
write_fifo_empty_wait(ss);
unsigned int len, unsigned long flags)
{
int i;
- unsigned long tmp;
if (len > SH_SPI_MAX_BYTE)
sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3);
else
sh_spi_write(len, &ss->regs->cr3);
- tmp = sh_spi_read(&ss->regs->cr1);
- tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB);
- sh_spi_write(tmp, &ss->regs->cr1);
+ sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
for (i = 0; i < len; i++) {
if (ep->id == 0) {
/* Wait until cx/ep0 fifo empty */
fotg210_cxwait(chip, CXFIFO_CXFIFOE);
+ udelay(1);
writel(DMAFIFO_CX, ®s->dma_fifo);
} else {
/* Wait until epx fifo empty */
/* CX interrupts */
if (gisr & GISR_GRP0) {
st = readl(®s->gisr0);
+ /*
+ * Write 1 and then 0 works for both W1C & RW.
+ *
+ * HW v1.11.0+: It's a W1C register (write 1 clear)
+ * HW v1.10.0-: It's a R/W register (write 0 clear)
+ */
+ writel(st & GISR0_CXABORT, ®s->gisr0);
writel(0, ®s->gisr0);
if (st & GISR0_CXERR)
/* Device Status Interrupts */
if (gisr & GISR_GRP2) {
st = readl(®s->gisr2);
+ /*
+ * Write 1 and then 0 works for both W1C & RW.
+ *
+ * HW v1.11.0+: It's a W1C register (write 1 clear)
+ * HW v1.10.0-: It's a R/W register (write 0 clear)
+ */
+ writel(st, ®s->gisr2);
writel(0, ®s->gisr2);
if (st & GISR2_RESET)
/* Setup the EHCI host controller. */
static void setup_usb_phy(struct exynos_usb_phy *usb)
{
+ u32 hsic_ctrl;
+
set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
clrbits_le32(&usb->usbphyctrl0,
HOST_CTRL0_LINKSWRST |
HOST_CTRL0_UTMISWRST);
+
+ /* HSIC Phy Setting */
+ hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
+ HSIC_CTRL_FORCESLEEP |
+ HSIC_CTRL_SIDDQ);
+
+ clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
+ clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
+
+ hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK)
+ << HSIC_CTRL_REFCLKDIV_SHIFT)
+ | ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK)
+ << HSIC_CTRL_REFCLKSEL_SHIFT)
+ | HSIC_CTRL_UTMISWRST);
+
+ setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
+ setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
+
+ udelay(10);
+
+ clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST |
+ HSIC_CTRL_UTMISWRST);
+
+ clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST |
+ HSIC_CTRL_UTMISWRST);
+
udelay(20);
/* EHCI Ctrl setting */
/* Reset the EHCI host controller. */
static void reset_usb_phy(struct exynos_usb_phy *usb)
{
+ u32 hsic_ctrl;
+
/* HOST_PHY reset */
setbits_le32(&usb->usbphyctrl0,
HOST_CTRL0_PHYSWRST |
HOST_CTRL0_FORCESUSPEND |
HOST_CTRL0_FORCESLEEP);
+ /* HSIC Phy reset */
+ hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
+ HSIC_CTRL_FORCESLEEP |
+ HSIC_CTRL_SIDDQ |
+ HSIC_CTRL_PHYSWRST);
+
+ setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
+ setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
+
set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
}
setup_usb_phy(ctx->usb);
+ board_usb_init(index, init);
+
*hccr = ctx->hcd;
*hcor = (struct ehci_hcor *)((uint32_t) *hccr
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
u32 gpr;
u32 reserved0[26];
u32 ch_db_mode_sel[2];
- u32 reserved1[16];
+ u32 reserved1[4];
u32 alt_ch_db_mode_sel[2];
u32 reserved2[2];
u32 ch_trb_mode_sel[2];
u32 sub_addr[5];
u32 bndm_en[2];
u32 sc_cord[2];
- u32 reserved[45];
+ u32 reserved[44];
u32 ch_busy[2];
};
get_fs()->dev_desc = rbdd;
part_info = info;
part_offset = info->start;
- get_fs()->total_sect = (info->size * info->blksz) >>
+ get_fs()->total_sect = ((uint64_t)info->size * info->blksz) >>
get_fs()->dev_desc->log2blksz;
}
goto fail;
}
put_ext4(((uint64_t)
- (g_parent_inode->b.
+ ((uint64_t)g_parent_inode->b.
blocks.dir_blocks[direct_blk_idx] *
- fs->blksz)), zero_buffer, fs->blksz);
+ (uint64_t)fs->blksz)), zero_buffer, fs->blksz);
g_parent_inode->size =
g_parent_inode->size + fs->blksz;
g_parent_inode->blockcnt =
for (i = 0; i < fs->no_blkgrp; i++) {
if (bgd[i].free_blocks) {
if (bgd[i].bg_flags & EXT4_BG_BLOCK_UNINIT) {
- put_ext4(((uint64_t) (bgd[i].block_id *
- fs->blksz)),
+ put_ext4(((uint64_t) ((uint64_t)bgd[i].block_id *
+ (uint64_t)fs->blksz)),
zero_buffer, fs->blksz);
bgd[i].bg_flags =
bgd[i].
if (bgd[bg_idx].bg_flags & EXT4_BG_BLOCK_UNINIT) {
memset(zero_buffer, '\0', fs->blksz);
- put_ext4(((uint64_t) (bgd[bg_idx].block_id *
- fs->blksz)), zero_buffer, fs->blksz);
+ put_ext4(((uint64_t) ((uint64_t)bgd[bg_idx].block_id *
+ (uint64_t)fs->blksz)), zero_buffer, fs->blksz);
memcpy(fs->blk_bmaps[bg_idx], zero_buffer, fs->blksz);
bgd[bg_idx].bg_flags = bgd[bg_idx].bg_flags &
~EXT4_BG_BLOCK_UNINIT;
bgd[i].free_inodes;
if (bgd[i].bg_flags & EXT4_BG_INODE_UNINIT) {
put_ext4(((uint64_t)
- (bgd[i].inode_id *
- fs->blksz)),
+ ((uint64_t)bgd[i].inode_id *
+ (uint64_t)fs->blksz)),
zero_buffer, fs->blksz);
bgd[i].bg_flags = bgd[i].bg_flags &
~EXT4_BG_INODE_UNINIT;
ibmap_idx = fs->curr_inode_no / inodes_per_grp;
if (bgd[ibmap_idx].bg_flags & EXT4_BG_INODE_UNINIT) {
memset(zero_buffer, '\0', fs->blksz);
- put_ext4(((uint64_t) (bgd[ibmap_idx].inode_id *
- fs->blksz)), zero_buffer,
+ put_ext4(((uint64_t) ((uint64_t)bgd[ibmap_idx].inode_id *
+ (uint64_t)fs->blksz)), zero_buffer,
fs->blksz);
bgd[ibmap_idx].bg_flags =
bgd[ibmap_idx].bg_flags & ~EXT4_BG_INODE_UNINIT;
}
/* write the block to disk */
- put_ext4(((uint64_t) (si_blockno * fs->blksz)),
+ put_ext4(((uint64_t) ((uint64_t)si_blockno * (uint64_t)fs->blksz)),
si_start_addr, fs->blksz);
file_inode->b.blocks.indir_block = si_blockno;
}
break;
}
/* write the block table */
- put_ext4(((uint64_t) (di_blockno_child * fs->blksz)),
+ put_ext4(((uint64_t) ((uint64_t)di_blockno_child * (uint64_t)fs->blksz)),
di_child_buff_start, fs->blksz);
free(di_child_buff_start);
di_child_buff_start = NULL;
if (*total_remaining_blocks == 0)
break;
}
- put_ext4(((uint64_t) (di_blockno_parent * fs->blksz)),
+ put_ext4(((uint64_t) ((uint64_t)di_blockno_parent * (uint64_t)fs->blksz)),
di_block_start_addr, fs->blksz);
file_inode->b.blocks.double_indir_block = di_blockno_parent;
}
break;
}
/* write the child block */
- put_ext4(((uint64_t) (ti_child_blockno *
- fs->blksz)),
+ put_ext4(((uint64_t) ((uint64_t)ti_child_blockno *
+ (uint64_t)fs->blksz)),
ti_cbuff_start_addr, fs->blksz);
free(ti_cbuff_start_addr);
break;
}
/* write the parent block */
- put_ext4(((uint64_t) (ti_parent_blockno * fs->blksz)),
+ put_ext4(((uint64_t) ((uint64_t)ti_parent_blockno * (uint64_t)fs->blksz)),
ti_pbuff_start_addr, fs->blksz);
free(ti_pbuff_start_addr);
break;
}
/* write the grand parent block */
- put_ext4(((uint64_t) (ti_gp_blockno * fs->blksz)),
+ put_ext4(((uint64_t) ((uint64_t)ti_gp_blockno * (uint64_t)fs->blksz)),
ti_gp_buff_start_addr, fs->blksz);
file_inode->b.blocks.triple_indir_block = ti_gp_blockno;
}
{
struct ext4_extent_idx *index;
unsigned long long block;
- struct ext_filesystem *fs = get_fs();
+ int blksz = EXT2_BLOCK_SIZE(data);
int i;
while (1) {
i++;
if (i >= le16_to_cpu(ext_block->eh_entries))
break;
- } while (fileblock > le32_to_cpu(index[i].ei_block));
+ } while (fileblock >= le32_to_cpu(index[i].ei_block));
if (--i < 0)
return 0;
block = le16_to_cpu(index[i].ei_leaf_hi);
block = (block << 32) + le32_to_cpu(index[i].ei_leaf_lo);
- if (ext4fs_devread((lbaint_t)block << log2_blksz, 0, fs->blksz,
+ if (ext4fs_devread((lbaint_t)block << log2_blksz, 0, blksz,
buf))
ext_block = (struct ext4_extent_header *)buf;
else
blknr = read_allocated_block(&inode_journal, i);
ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0,
fs->blksz, metadata_buff);
- put_ext4((uint64_t)(be32_to_cpu(tag->block) * fs->blksz),
+ put_ext4((uint64_t)((uint64_t)be32_to_cpu(tag->block) * (uint64_t)fs->blksz),
metadata_buff, (uint32_t) fs->blksz);
} while (!(flags & EXT3_JOURNAL_FLAG_LAST_TAG));
fail:
blknr = read_allocated_block(&inode_journal,
EXT2_JOURNAL_SUPERBLOCK);
- put_ext4((uint64_t) (blknr * fs->blksz),
+ put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz),
(struct journal_superblock_t *)temp_buff,
(uint32_t) fs->blksz);
ext4fs_free_revoke_blks();
tag.flags = cpu_to_be32(EXT3_JOURNAL_FLAG_LAST_TAG);
memcpy(temp - sizeof(struct ext3_journal_block_tag), &tag,
sizeof(struct ext3_journal_block_tag));
- put_ext4((uint64_t) (blknr * fs->blksz), buf, (uint32_t) fs->blksz);
+ put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz), buf, (uint32_t) fs->blksz);
free(temp_buff);
free(buf);
return;
}
memcpy(buf, &jdb, sizeof(struct journal_header_t));
- put_ext4((uint64_t) (blknr * fs->blksz), buf, (uint32_t) fs->blksz);
+ put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz), buf, (uint32_t) fs->blksz);
free(temp_buff);
free(buf);
/* update block groups */
for (i = 0; i < fs->no_blkgrp; i++) {
fs->bgd[i].bg_checksum = ext4fs_checksum_update(i);
- put_ext4((uint64_t)(fs->bgd[i].block_id * fs->blksz),
+ put_ext4((uint64_t)((uint64_t)fs->bgd[i].block_id * (uint64_t)fs->blksz),
fs->blk_bmaps[i], fs->blksz);
}
/* update inode table groups */
for (i = 0; i < fs->no_blkgrp; i++) {
- put_ext4((uint64_t) (fs->bgd[i].inode_id * fs->blksz),
+ put_ext4((uint64_t) ((uint64_t)fs->bgd[i].inode_id * (uint64_t)fs->blksz),
fs->inode_bmaps[i], fs->blksz);
}
/* update the block group descriptor table */
- put_ext4((uint64_t)(fs->gdtable_blkno * fs->blksz),
+ put_ext4((uint64_t)((uint64_t)fs->gdtable_blkno * (uint64_t)fs->blksz),
(struct ext2_block_group *)fs->gdtable,
(fs->blksz * fs->no_blk_pergdt));
temp_buff);
jsb = (struct journal_superblock_t *)temp_buff;
jsb->s_start = cpu_to_be32(0);
- put_ext4((uint64_t) (blknr * fs->blksz),
+ put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz),
(struct journal_superblock_t *)temp_buff, fs->blksz);
free(temp_buff);
}
delayed_next += blockend >> log2blksz;
} else { /* spill */
put_ext4((uint64_t)
- (delayed_start << log2blksz),
+ ((uint64_t)delayed_start << log2blksz),
delayed_buf,
(uint32_t) delayed_extent);
previous_block_number = blknr;
} else {
if (previous_block_number != -1) {
/* spill */
- put_ext4((uint64_t) (delayed_start <<
+ put_ext4((uint64_t) ((uint64_t)delayed_start <<
log2blksz),
delayed_buf,
(uint32_t) delayed_extent);
}
if (previous_block_number != -1) {
/* spill */
- put_ext4((uint64_t) (delayed_start << log2blksz),
+ put_ext4((uint64_t) ((uint64_t)delayed_start << log2blksz),
delayed_buf, (uint32_t) delayed_extent);
previous_block_number = -1;
}
if (result == YAFFS_OK) {
/* Verify header */
if (hdr.version != YAFFS_SUMMARY_VERSION ||
- hdr.block != blk ||
hdr.seq != bi->seq_number ||
hdr.sum != yaffs_summary_sum(dev))
result = YAFFS_FAIL;
+++ /dev/null
-/*
- * Register definitions for the AMBA CLCD logic cell.
- *
- * derived from David A Rusling, although rearranged as a C structure
- * linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
- *
- * Copyright (C) 2001 ARM Limited
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive
- * for more details.
- */
-
-/*
- * CLCD Controller Internal Register addresses
- */
-struct clcd_registers {
- u32 tim0; /* 0x00 */
- u32 tim1;
- u32 tim2;
- u32 tim3;
- u32 ubas; /* 0x10 */
- u32 lbas;
-#if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW)
- u32 ienb;
- u32 cntl;
-#else /* Someone rearranged these two registers on the Versatile */
- u32 cntl;
- u32 ienb;
-#endif
- u32 stat; /* 0x20 */
- u32 intr;
- u32 ucur;
- u32 lcur;
- u32 unused[0x74]; /* 0x030..0x1ff */
- u32 palette[0x80]; /* 0x200..0x3ff */
-};
-
-/* Bit definition for TIM2 */
-#define TIM2_CLKSEL (1 << 5)
-#define TIM2_IVS (1 << 11)
-#define TIM2_IHS (1 << 12)
-#define TIM2_IPC (1 << 13)
-#define TIM2_IOE (1 << 14)
-#define TIM2_BCD (1 << 26)
-
-/* Bit definitions for control register */
-#define CNTL_LCDEN (1 << 0)
-#define CNTL_LCDBPP1 (0 << 1)
-#define CNTL_LCDBPP2 (1 << 1)
-#define CNTL_LCDBPP4 (2 << 1)
-#define CNTL_LCDBPP8 (3 << 1)
-#define CNTL_LCDBPP16 (4 << 1)
-#define CNTL_LCDBPP16_565 (6 << 1)
-#define CNTL_LCDBPP24 (5 << 1)
-#define CNTL_LCDBW (1 << 4)
-#define CNTL_LCDTFT (1 << 5)
-#define CNTL_LCDMONO8 (1 << 6)
-#define CNTL_LCDDUAL (1 << 7)
-#define CNTL_BGR (1 << 8)
-#define CNTL_BEBO (1 << 9)
-#define CNTL_BEPO (1 << 10)
-#define CNTL_LCDPWR (1 << 11)
-#define CNTL_LCDVCOMP(x) ((x) << 12)
-#define CNTL_LDMAFIFOTIME (1 << 15)
-#define CNTL_WATERMARK (1 << 16)
-
-/* u-boot specific: information passed by the board file */
-struct clcd_config {
- struct clcd_registers *address;
- u32 tim0;
- u32 tim1;
- u32 tim2;
- u32 tim3;
- u32 cntl;
- unsigned long pixclock;
-};
+++ /dev/null
-/*
- * transitional header until we merge global_data.h
- *
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_GENERIC_GLOBAL_DATA_FLAGS_H
-#define __ASM_GENERIC_GLOBAL_DATA_FLAGS_H
-
-/*
- * Global Data Flags
- *
- * Note: The low 16 bits are expected for common code. If your arch
- * really needs to add your own, use the high 16bits.
- */
-#define GD_FLG_RELOC 0x0001 /* Code was relocated to RAM */
-#define GD_FLG_DEVINIT 0x0002 /* Devices have been initialized */
-#define GD_FLG_SILENT 0x0004 /* Silent mode */
-#define GD_FLG_POSTFAIL 0x0008 /* Critical POST test failed */
-#define GD_FLG_POSTSTOP 0x0010 /* POST seqeunce aborted */
-#define GD_FLG_LOGINIT 0x0020 /* Log Buffer has been initialized */
-#define GD_FLG_DISABLE_CONSOLE 0x0040 /* Disable console (in & out) */
-#define GD_FLG_ENV_READY 0x0080 /* Environment imported into hash table */
-
-#endif
+++ /dev/null
-#ifndef _AT45_H_
-#define _AT45_H_
-#ifdef CONFIG_DATAFLASH_MMC_SELECT
-extern void AT91F_SelectMMC(void);
-extern void AT91F_SelectSPI(void);
-extern int AT91F_GetMuxStatus(void);
-#endif
-extern void AT91F_SpiInit(void);
-extern void AT91F_SpiEnable(int cs);
-extern unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc );
-extern AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
- AT91PS_DataFlash pDataFlash,
- unsigned char OpCode,
- unsigned int CmdSize,
- unsigned int DataflashAddress);
-extern AT91S_DataFlashStatus AT91F_DataFlashGetStatus (
- AT91PS_DataflashDesc pDesc);
-extern AT91S_DataFlashStatus AT91F_DataFlashWaitReady (
- AT91PS_DataflashDesc pDataFlashDesc,
- unsigned int timeout);
-extern AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
- AT91PS_DataFlash pDataFlash,
- int src,
- unsigned char *dataBuffer,
- int sizeToRead );
-extern AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
- AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- unsigned int dest,
- unsigned int SizeToWrite);
-extern AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
- AT91PS_DataFlash pDataFlash,
- unsigned char BufferCommand,
- unsigned int page);
-extern AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
- AT91PS_DataFlash pDataFlash,
- unsigned char BufferCommand,
- unsigned char *dataBuffer,
- unsigned int bufferAddress,
- int SizeToWrite );
-extern AT91S_DataFlashStatus AT91F_PageErase(
- AT91PS_DataFlash pDataFlash,
- unsigned int page);
-extern AT91S_DataFlashStatus AT91F_BlockErase(
- AT91PS_DataFlash pDataFlash,
- unsigned int block);
-extern AT91S_DataFlashStatus AT91F_WriteBufferToMain (
- AT91PS_DataFlash pDataFlash,
- unsigned char BufferCommand,
- unsigned int dest );
-extern AT91S_DataFlashStatus AT91F_PartialPageWrite (
- AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- unsigned int dest,
- unsigned int size);
-extern AT91S_DataFlashStatus AT91F_DataFlashWrite(
- AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- int dest,
- int size );
-extern int AT91F_DataFlashRead(
- AT91PS_DataFlash pDataFlash,
- unsigned long addr,
- unsigned long size,
- char *buffer);
-extern int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc);
-
-#endif
+++ /dev/null
-/* ---------------------------------------------------------------------------- */
-/* ATMEL Microcontroller Software Support - ROUSSET - */
-/* ---------------------------------------------------------------------------- */
-/* The software is delivered "AS IS" without warranty or condition of any */
-/* kind, either express, implied or statutory. This includes without */
-/* limitation any warranty or condition with respect to merchantability or */
-/* fitness for any particular purpose, or against the infringements of */
-/* intellectual property rights of others. */
-/* ---------------------------------------------------------------------------- */
-/* File Name : at91rm9200_i2c.h */
-/* Object : AT91RM9200 / TWI definitions */
-/* Generated : AT91 SW Application Group 12/03/2002 (10:48:02) */
-/* */
-/* ---------------------------------------------------------------------------- */
-
-#ifndef AT91RM9200_TWI_H
-#define AT91RM9200_TWI_H
-
-/* ******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Two-wire Interface */
-/* ******************************************************************************/
-#ifndef __ASSEMBLY__
-
-typedef struct _AT91S_TWI {
- AT91_REG TWI_CR; /* Control Register */
- AT91_REG TWI_MMR; /* Master Mode Register */
- AT91_REG TWI_SMR; /* Slave Mode Register */
- AT91_REG TWI_IADR; /* Internal Address Register */
- AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */
- AT91_REG Reserved0[3];
- AT91_REG TWI_SR; /* Status Register */
- AT91_REG TWI_IER; /* Interrupt Enable Register */
- AT91_REG TWI_IDR; /* Interrupt Disable Register */
- AT91_REG TWI_IMR; /* Interrupt Mask Register */
- AT91_REG TWI_RHR; /* Receive Holding Register */
- AT91_REG TWI_THR; /* Transmit Holding Register */
- AT91_REG Reserved1[50];
- AT91_REG TWI_RPR; /* Receive Pointer Register */
- AT91_REG TWI_RCR; /* Receive Counter Register */
- AT91_REG TWI_TPR; /* Transmit Pointer Register */
- AT91_REG TWI_TCR; /* Transmit Counter Register */
- AT91_REG TWI_RNPR; /* Receive Next Pointer Register */
- AT91_REG TWI_RNCR; /* Receive Next Counter Register */
- AT91_REG TWI_TNPR; /* Transmit Next Pointer Register */
- AT91_REG TWI_TNCR; /* Transmit Next Counter Register */
- AT91_REG TWI_PTCR; /* PDC Transfer Control Register */
- AT91_REG TWI_PTSR; /* PDC Transfer Status Register */
-} AT91S_TWI, *AT91PS_TWI;
-
-#endif
-
-/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
-#define AT91C_TWI_START (0x1 << 0) /* (TWI) Send a START Condition */
-#define AT91C_TWI_STOP (0x1 << 1) /* (TWI) Send a STOP Condition */
-#define AT91C_TWI_MSEN (0x1 << 2) /* (TWI) TWI Master Transfer Enabled */
-#define AT91C_TWI_MSDIS (0x1 << 3) /* (TWI) TWI Master Transfer Disabled */
-#define AT91C_TWI_SVEN (0x1 << 4) /* (TWI) TWI Slave Transfer Enabled */
-#define AT91C_TWI_SVDIS (0x1 << 5) /* (TWI) TWI Slave Transfer Disabled */
-#define AT91C_TWI_SWRST (0x1 << 7) /* (TWI) Software Reset */
-/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
-#define AT91C_TWI_IADRSZ (0x3 << 8) /* (TWI) Internal Device Address Size */
-#define AT91C_TWI_IADRSZ_NO (0x0 << 8) /* (TWI) No internal device address */
-#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) /* (TWI) One-byte internal device address */
-#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) /* (TWI) Two-byte internal device address */
-#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) /* (TWI) Three-byte internal device address */
-#define AT91C_TWI_MREAD (0x1 << 12) /* (TWI) Master Read Direction */
-#define AT91C_TWI_DADR (0x7F << 6) /* (TWI) Device Address */
-/* -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- */
-#define AT91C_TWI_SADR (0x7F << 16) /* (TWI) Slave Device Address */
-/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
-#define AT91C_TWI_CLDIV (0xFF << 0) /* (TWI) Clock Low Divider */
-#define AT91C_TWI_CHDIV (0xFF << 8) /* (TWI) Clock High Divider */
-#define AT91C_TWI_CKDIV (0x7 << 16) /* (TWI) Clock Divider */
-/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
-#define AT91C_TWI_TXCOMP (0x1 << 0) /* (TWI) Transmission Completed */
-#define AT91C_TWI_RXRDY (0x1 << 1) /* (TWI) Receive holding register ReaDY */
-#define AT91C_TWI_TXRDY (0x1 << 2) /* (TWI) Transmit holding register ReaDY*/
-#define AT91C_TWI_SVREAD (0x1 << 3) /* (TWI) Slave Read */
-#define AT91C_TWI_SVACC (0x1 << 4) /* (TWI) Slave Access */
-#define AT91C_TWI_GCACC (0x1 << 5) /* (TWI) General Call Access */
-#define AT91C_TWI_OVRE (0x1 << 6) /* (TWI) Overrun Error */
-#define AT91C_TWI_UNRE (0x1 << 7) /* (TWI) Underrun Error */
-#define AT91C_TWI_NACK (0x1 << 8) /* (TWI) Not Acknowledged */
-#define AT91C_TWI_ARBLST (0x1 << 9) /* (TWI) Arbitration Lost */
-/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
-/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register ------- */
-/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
-
-/*
- i2c Support for Atmel's AT91RM9200 Two-Wire Interface
-
- (c) Rick Bronson
-
- * SPDX-License-Identifier: GPL-2.0+
-*/
-
-#ifndef AT91_I2C_H
-#define AT91_I2C_H
-
-#define AT91C_TWI_CLOCK 100000
-#define AT91C_TWI_SCLOCK (10 * AT91C_MASTER_CLOCK / AT91C_TWI_CLOCK)
-#define AT91C_TWI_CKDIV1 (2 << 16) /* TWI clock divider. NOTE: see Errata #22 */
-
-#if (AT91C_TWI_SCLOCK % 10) >= 5
-#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 5)
-#else
-#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 6)
-#endif
-#define AT91C_TWI_CLDIV3 ((AT91C_TWI_CLDIV2 + (4 - AT91C_TWI_CLDIV2 % 4)) >> 2)
-
-#define AT91C_EEPROM_I2C_ADDRESS (0x50 << 16)
-
-#endif /* __ASSEMBLY__ */
-#endif /* AT91RM9200_TWI_H */
+++ /dev/null
-/*
- * Ethernet: An implementation of the Ethernet Device Driver suite for the
- * uClinux 2.0.38 operating system. This Driver has been developed
- * for AT75C220 board.
- *
- * NOTE: The driver is implemented for one MAC
- *
- * Version: @(#)at91rm9200_net.h 1.0.0 01/10/2001
- *
- * Authors: Lineo Inc <www.lineo.com>
- *
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91RM9200_ETHERNET
-#define AT91RM9200_ETHERNET
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-#define ETHERNET_ADDRESS_SIZE 6
-
-typedef unsigned char UCHAR;
-
-/* Interface to drive the physical layer */
-typedef struct _AT91S_PhyOps
-{
- unsigned char (*Init)(AT91S_EMAC *pmac);
- unsigned int (*IsPhyConnected)(AT91S_EMAC *pmac);
- unsigned char (*GetLinkSpeed)(AT91S_EMAC *pmac);
- unsigned char (*AutoNegotiate)(AT91S_EMAC *pmac, int *);
-
-} AT91S_PhyOps,*AT91PS_PhyOps;
-
-
-#define EMAC_DESC_DONE 0x00000001 /* ownership bit */
-#define EMAC_DESC_WRAP 0x00000002 /* bit for wrap */
-
-/****************** function prototypes **********************/
-
-/* MII functions */
-void at91rm9200_EmacEnableMDIO(AT91PS_EMAC p_mac);
-void at91rm9200_EmacDisableMDIO(AT91PS_EMAC p_mac);
-UCHAR at91rm9200_EmacReadPhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pInput);
-UCHAR at91rm9200_EmacWritePhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pOutput);
-void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops);
-
-#endif /* AT91RM9200_ETHERNET */
+++ /dev/null
-/*
- * Broadcom BCM5221 Ethernet PHY
- *
- * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
- * Anders Larsen <alarsen@rea.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define BCM5221_BMCR 0 /* Basic Mode Control Register */
-#define BCM5221_BMSR 1 /* Basic Mode Status Register */
-#define BCM5221_PHYID1 2 /* PHY Identifier Register 1 */
-#define BCM5221_PHYID2 3 /* PHY Identifier Register 2 */
-#define BCM5221_ANAR 4 /* Auto-negotiation Advertisement Register */
-#define BCM5221_ANLPAR 5 /* Auto-negotiation Link Partner Ability Register */
-#define BCM5221_ANER 6 /* Auto-negotiation Expansion Register */
-#define BCM5221_ACSR 24 /* Auxiliary Control/Status Register */
-#define BCM5221_INTR 26 /* Interrupt Register */
-
-/* --Bit definitions: BCM5221_BMCR */
-#define BCM5221_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */
-#define BCM5221_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */
-#define BCM5221_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */
-#define BCM5221_AUTONEG (1 << 12)
-#define BCM5221_POWER_DOWN (1 << 11)
-#define BCM5221_ISOLATE (1 << 10)
-#define BCM5221_RESTART_AUTONEG (1 << 9)
-#define BCM5221_DUPLEX_MODE (1 << 8)
-#define BCM5221_COLLISION_TEST (1 << 7)
-
-/*--Bit definitions: BCM5221_BMSR */
-#define BCM5221_100BASE_T4 (1 << 15)
-#define BCM5221_100BASE_TX_FD (1 << 14)
-#define BCM5221_100BASE_TX_HD (1 << 13)
-#define BCM5221_10BASE_T_FD (1 << 12)
-#define BCM5221_10BASE_T_HD (1 << 11)
-#define BCM5221_MF_PREAMB_SUPPR (1 << 6)
-#define BCM5221_AUTONEG_COMP (1 << 5)
-#define BCM5221_REMOTE_FAULT (1 << 4)
-#define BCM5221_AUTONEG_ABILITY (1 << 3)
-#define BCM5221_LINK_STATUS (1 << 2)
-#define BCM5221_JABBER_DETECT (1 << 1)
-#define BCM5221_EXTEND_CAPAB (1 << 0)
-
-/*--definitions: BCM5221_PHYID1 */
-#define BCM5221_PHYID1_OUI 0x1018
-#define BCM5221_LSB_MASK 0x3F
-
-/*--Bit definitions: BCM5221_ANAR, BCM5221_ANLPAR */
-#define BCM5221_NP (1 << 15)
-#define BCM5221_ACK (1 << 14)
-#define BCM5221_RF (1 << 13)
-#define BCM5221_FCS (1 << 10)
-#define BCM5221_T4 (1 << 9)
-#define BCM5221_TX_FDX (1 << 8)
-#define BCM5221_TX_HDX (1 << 7)
-#define BCM5221_10_FDX (1 << 6)
-#define BCM5221_10_HDX (1 << 5)
-#define BCM5221_AN_IEEE_802_3 0x0001
-
-/*--Bit definitions: BCM5221_ANER */
-#define BCM5221_PDF (1 << 4)
-#define BCM5221_LP_NP_ABLE (1 << 3)
-#define BCM5221_NP_ABLE (1 << 2)
-#define BCM5221_PAGE_RX (1 << 1)
-#define BCM5221_LP_AN_ABLE (1 << 0)
-
-/*--Bit definitions: BCM5221_ACSR */
-#define BCM5221_100 (1 << 1)
-#define BCM5221_FDX (1 << 0)
-
-/*--Bit definitions: BCM5221_INTR */
-#define BCM5221_FDX_LED (1 << 15)
-#define BCM5221_INTR_ENABLE (1 << 14)
-#define BCM5221_FDX_MASK (1 << 11)
-#define BCM5221_SPD_MASK (1 << 10)
-#define BCM5221_LINK_MASK (1 << 9)
-#define BCM5221_INTR_MASK (1 << 8)
-#define BCM5221_FDX_CHG (1 << 3)
-#define BCM5221_SPD_CHG (1 << 2)
-#define BCM5221_LINK_CHG (1 << 1)
-#define BCM5221_INTR_STATUS (1 << 0)
-
-/****************** function prototypes **********************/
-unsigned int bcm5221_IsPhyConnected(AT91PS_EMAC p_mac);
-unsigned char bcm5221_GetLinkSpeed(AT91PS_EMAC p_mac);
-unsigned char bcm5221_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
-unsigned char bcm5221_InitPhy(AT91PS_EMAC p_mac);
#ifndef __COMMON_H_
#define __COMMON_H_ 1
-#undef _LINUX_CONFIG_H
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
#ifndef __ASSEMBLY__ /* put C only stuff in this section */
typedef unsigned char uchar;
* (easy to change)
*/
-#define CONFIG_MPC824X 1
#define CONFIG_MPC8245 1
#define CONFIG_A3000 1
* (easy to change)
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_APCG405 1 /* ...on a APC405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
*/
#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_AR405 1 /* ...on a AR405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
*/
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_ASH405 1 /* ...on a ASH405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+++ /dev/null
-/*
- * Copyright (C) 2006 CodeHermit.
- * Bryan O'Donoghue <bodonoghue@codehermit.ie>
- *
- * Provides support for USB console on the Analogue & Micro Adder87x
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ADDERUSB__
-#define __ADDERUSB__
-
-/* Include the board port */
-#include "Adder.h"
-
-#define CONFIG_USB_DEVICE /* Include UDC driver */
-#define CONFIG_USB_TTY /* Bind the TTY driver to UDC */
-#define CONFIG_SYS_USB_EXTC_CLK 0x02 /* Oscillator on EXTC_CLK 2 */
-#define CONFIG_SYS_USB_BRG_CLK 0x04 /* or use Baud rate generator 0x04 */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Console is in env */
-
-/* If you have a USB-IF assigned VendorID then you may wish to define
- * your own vendor specific values either in BoardName.h or directly in
- * usbd_vendor_info.h
- */
-
-/*
-#define CONFIG_USBD_MANUFACTURER "CodeHermit.ie"
-#define CONFIG_USBD_PRODUCT_NAME "Das U-Boot"
-#define CONFIG_USBD_VENDORID 0xFFFF
-#define CONFIG_USBD_PRODUCTID_GSERIAL 0xFFFF
-#define CONFIG_USBD_PRODUCTID_CDCACM 0xFFFE
-*/
-
-#endif /* __ADDERUSB_H__ */
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
#define CONFIG_MP /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
/*
* High Level Configuration Options
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
+#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
#define CONFIG_TQM5200 1 /* ... on a TQM5200 module */
#define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#endif
#ifdef CONFIG_NAND
#define CONFIG_SPL_MAX_SIZE 8192
#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
#define CONFIG_SPL_RELOC_STACK 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_MPC85xx /* MPC8540/60/55/41/48/P1020/P2020/P1010,etc*/
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
#elif defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#endif
#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1
#ifdef CONFIG_SPIFLASH
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#endif
#ifdef CONFIG_NAND
#define CONFIG_SPL_MAX_SIZE 8192
#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
#define CONFIG_SPL_RELOC_STACK 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
#endif
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0x8ff80000
+#define CONFIG_SYS_TEXT_BASE 0x8ff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_MPC85xx
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
*/
#if defined(CONFIG_RAMBOOT_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_RAMBOOT_SPIFLASH)
#elif defined(CONFIG_NAND)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
#elif defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR 0xfff80000
-#else
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#define CONFIG_ENV_SECT_SIZE 0x20000
#endif
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE (128 << 10)
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TEXT_BASE 0xff800000
+#define CONFIG_SPL_MAX_SIZE 8192
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_TPL_PAD_TO 0x20000
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_MPC85xx
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
(0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
+
/*
* IFC Definitions
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
/* 8Bit NAND Flash - K9F1G08U0B */
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CONFIG_SYS_NAND_DDR_LAW 11
/* Set up IFC registers for boot location NOR/NAND */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
/* CPLD on IFC, selected by CS2 */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
+#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
#endif
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
#else
-#define CONFIG_ENV_IS_IN_FLASH
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR 0xfff80000
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
+#endif
+#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
#else
+#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000
#endif
*/
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */
*/
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_VOM405 1 /* ...on a VOM405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC8000
* (easy to change)
*/
-#define CONFIG_MPC824X 1
#define CONFIG_MPC8245 1
#define CONFIG_CPC45 1
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
#define CONFIG_CPCI405AB 1 /* ...and special AB version */
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CPCIISER4 1 /* ...on a CPCIISER4 board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC405 family */
/*
* Note: I make an "image" from U-Boot itself, which prefixes 0x40
* (easy to change)
*/
-#define CONFIG_MPC824X 1
#define CONFIG_MPC8240 1
#define CONFIG_CU824 1
*/
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_DP405 1 /* ...on a DP405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
* (easy to change)
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_DU405 1 /* ...on a DU405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
*/
#define CONFIG_DU440 1 /* Board is esd DU440 */
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */
#ifndef CONFIG_SYS_TEXT_BASE
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-#define CONFIG_EXBITGEN 1 /* on a Exbit Generic board */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-
-#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
-
-/* I2C configuration */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed */
-#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
-
-/* environment is in EEPROM */
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NVRAM
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 /* 1010110 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit internal addressing */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 /* ... and 1 bit in I2C address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 4 bytes per page */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* write takes up to 40 msec */
-#define CONFIG_ENV_OFFSET 4 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 350 /* that is 350 bytes only! */
-#endif
-
-#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
-/* Explanation:
- autbooting is altogether disabled and cannot be
- enabled if CONFIG_BOOTDELAY is negative.
- If you want shorter bootdelay, then
- - "setenv bootdelay <delay>" to the proper value
-*/
-
-#define CONFIG_BOOTCOMMAND "bootm 20400000 20800000"
-
-#define CONFIG_BOOTARGS "root=/dev/ram " \
- "ramdisk_size=32768 " \
- "console=ttyS0,115200 " \
- "ram=128M debug"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-/* UART configuration */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* Default baud rate */
-#define CONFIG_BAUDRATE 115200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#undef CONFIG_PCI /* no pci support */
-
-/*-----------------------------------------------------------------------
- * External peripheral base address
- *-----------------------------------------------------------------------
- */
-#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#undef CONFIG_IDE_RESET /* no reset for ide supported */
-
-#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000
-#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000
-#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH0_BASE 0xFFF80000
-#define CONFIG_SYS_FLASH0_SIZE 0x00080000
-#define CONFIG_SYS_FLASH1_BASE 0x20000000
-#define CONFIG_SYS_FLASH1_SIZE 0x02000000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_RAMSTART
-#endif
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 5 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET 0x00060000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x00010000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE 0x00010000 /* see README - env sector total size */
-#endif
-
-/* On Chip Memory location/size */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-
-/* Global info and initial stack */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-#endif /* __CONFIG_H */
*/
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_G2000 1 /* ...on a PLU405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
*/
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_HH405 1 /* ...on a HH405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
* (easy to change)
*/
-#define CONFIG_MPC824X 1
#define CONFIG_MPC8245 1
#define CONFIG_HIDDEN_DRAGON 1
*/
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_HUB405 1 /* ...on a HUB405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
/* High-level system configuration options */
#define CONFIG_BOOKE /* Power/PowerPC Book-E */
#define CONFIG_E500 /* e500 (Power ISA v2.03 with SPE) */
-#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 family */
#define CONFIG_FSL_ELBC /* FreeScale Enhanced LocalBus Cntlr */
#define CONFIG_FSL_LAW /* FreeScale Local Access Window */
#define CONFIG_P2020 /* FreeScale P2020 */
* (easy to change)
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
+#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
#define CONFIG_ICECUBE 1 /* ... on IceCube board */
/*
#define CONFIG_JSE 1
/* JSE has a PPC405GPr */
#define CONFIG_405GP 1
- /* ... which is a 4xxx series */
-#define CONFIG_4x 1
/* ... with a 33MHz OSC. connected to the SysCLK input */
#define CONFIG_SYS_CLK_FREQ 33333333
/* ... with on-chip memory here (4KBytes) */
#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */
#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
* High Level Configuration Options
*/
#define CONFIG_E300 1
-#define CONFIG_MPC83xx 1
#define CONFIG_MPC837x 1
#define CONFIG_MPC8377 1
#define CONFIG_METROBOX 1 /* Board is Metrobox */
#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
* (easy to change)
***********************************************************/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_MIP405 1 /* ...on a MIP405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
* (easy to change)
*/
-#define CONFIG_MPC824X 1
#define CONFIG_MPC8240 1
#define CONFIG_MOUSSE 1
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC830x 1 /* MPC830x family */
#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
#define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */
* High Level Configuration Options
*/
#define CONFIG_E300 1
-#define CONFIG_MPC83xx 1
#define CONFIG_MPC831x 1
#define CONFIG_MPC8313 1
#define CONFIG_MPC8313ERDB 1
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC831x 1 /* MPC831x CPU family */
#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */
#define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
#define CONFIG_SYS_TEXT_BASE 0xFE000000
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC834x 1 /* MPC834x family */
#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
/*
* High Level Configuration Options
*/
-#define CONFIG_MPC83xx 1
#define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */
#define CONFIG_MPC8349 /* MPC8349 specific */
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
#define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
#define CONFIG_MPC837XERDB 1
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
#define CONFIG_MPC8536 1
#define CONFIG_MPC8536DS 1
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
#define CONFIG_MPC8540 1 /* MPC8540 specific */
#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_MPC8541 1 /* MPC8541 specific */
#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
#define CONFIG_MPC8544 1
#define CONFIG_MPC8544DS 1
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_MPC8555 1 /* MPC8555 specific */
#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
#define CONFIG_MPC8560 1
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
#define CONFIG_MPC8568 1 /* MPC8568 specific */
#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
#define CONFIG_MPC8569 1 /* MPC8569 specific */
#define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
#define CONFIG_MPC8572 1
#define CONFIG_MPC8572DS 1
#define CONFIG_MP 1 /* support multiple processors */
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_MPC86xx 1 /* MPC86xx */
#define CONFIG_MPC8610 1 /* MPC8610 specific */
#define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_MPC86xx 1 /* MPC86xx */
#define CONFIG_MPC8641 1 /* MPC8641 specific */
#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
#define CONFIG_MP 1 /* support multiple processors */
* (easy to change)
*/
-#define CONFIG_MPC824X 1
#define CONFIG_MPC8245 1
#define CONFIG_MUSENKI 1
#include <version.h>
-#define CONFIG_MPC5xxx 1
#define CONFIG_MPC5200 1
#ifndef CONFIG_SYS_TEXT_BASE
* High Level Configuration Options
*/
#define CONFIG_E300 1
-#define CONFIG_MPC83xx 1
#define CONFIG_MPC834x 1
#define CONFIG_MPC8343 1
#define ERR_LED(code)
#endif
-#define CONFIG_MPC824X 1
#define CONFIG_MPC8245 1
#define CONFIG_MVBLUE 1
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
-#define CONFIG_MVS 1 /* ...on a MVsensor module */
-#define CONFIG_MVS_16BIT_FLASH /* ...with 16-bit flash access */
-#define CONFIG_8xx_GCLK_FREQ 50000000/* ... and a 50 MHz CPU */
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#undef CONFIG_8xx_CONS_SMC1 /* Console is *NOT* on SMC1 */
-#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 115200 /* console baudrate */
-#define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo To mount root over NFS use \"run bootnet\";" \
- "echo To mount root from FLASH use \"run bootflash\";" \
- "echo"
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw"
-#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#define CONFIG_WATCHDOG /* watchdog disabled/enabled */
-
-#undef CONFIG_STATUS_LED /* Status LED disabled/enabled */
-
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_VENDOREX
-
-#undef CONFIG_MAC_PARTITION
-#undef CONFIG_DOS_PARTITION
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_RUN
-
-
-/*
- * Miscellaneous configurable options
- */
-#undef CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot ?? */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-
-#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 192 kB for Monitor */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip (for AMD320DB chip) */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-
-/* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */
-#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector (bottom boot sector) */
-#define CONFIG_ENV_SIZE 0x2000 /* Used Size of Environment Sector 8k */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- */
-#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_TBS | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PCCARD 0 /* **DON'T** Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 0 /* max. no. of IDE buses */
-#define CONFIG_SYS_IDE_MAXDEVICE 0 /* max. no. of drives per IDE bus */
-
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define CONFIG_SYS_DER 0x2002000F*/
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#undef FLASH_BASE1_PRELIM
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-
-/*
- * FLASH timing:
- */
-/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
- OR_SCY_2_CLK | OR_EHTR | OR_BI)
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
-/*
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
- OR_SCY_5_CLK | OR_EHTR)
-*/
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#ifdef CONFIG_MVS_16BIT_FLASH
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-#else
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
-#endif
-
-#undef CONFIG_SYS_OR1_REMAP
-#undef CONFIG_SYS_OR1_PRELIM
-#undef CONFIG_SYS_BR1_PRELIM
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
-#undef SDRAM_BASE3_PRELIM
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#undef CONFIG_SYS_OR3_PRELIM
-#undef CONFIG_SYS_BR3_PRELIM
-
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock!)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- *
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider = 98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-#define CONFIG_SYS_MAMR_PTA 98
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-#endif /* __CONFIG_H */
#include <version.h>
-#define CONFIG_MPC5xxx 1
#define CONFIG_MPC5200 1
#ifndef CONFIG_SYS_TEXT_BASE
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_OCRTC 1 /* ...on a OCRTC board */
#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-#define CONFIG_ORSG 1 /* ...on a ORSG board */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-
-#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND "go fff00100"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_EEPROM
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter */
-#undef CONFIG_PCI_PNP /* no pci plug-and-play */
- /* resource configuration */
-
-#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0411 /* PCI Device ID: ORSG */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#if 0 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
-#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
-#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */
-
-#else /* Use EEPROM for environment variables */
-
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */
- /* total size of a CAT24WC08 is 1024 bytes */
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC08) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (PLD - FPGA-boot) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
- /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 3 (PLD - OSL) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
- /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 4 (Spartan2 1) initialization */
-#define CONFIG_SYS_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
- /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
-
-/* Memory Bank 5 (Spartan2 2) initialization */
-#define CONFIG_SYS_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
- /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
-
-/* Memory Bank 6 (Virtex 1) initialization */
-#define CONFIG_SYS_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
- /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 7 (Virtex 2) initialization */
-#define CONFIG_SYS_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
- /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
-
-
-#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#endif /* __CONFIG_H */
#ifdef CONFIG_SDCARD
#define CONFIG_RAMBOOT_SDCARD
#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#endif
#ifdef CONFIG_NAND
#define CONFIG_SPL_MAX_SIZE 8192
#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
#define CONFIG_SPL_RELOC_STACK 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
#ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
#define CONFIG_RAMBOOT_NAND
#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#endif
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_MPC85xx
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
#define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
#endif
-#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR 0xfff80000
-#else
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x18000
#define CONFIG_SPL_MAX_SIZE (96 * 1024)
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x18000
#define CONFIG_SPL_MAX_SIZE (96 * 1024)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
#define CONFIG_SPL_MAX_SIZE (128 << 10)
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
#define CONFIG_P1022
#define CONFIG_P1022DS
#define CONFIG_MP /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR 0xfff80000
-#else
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
#define __CONFIG_H
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_SYS_MONITOR_BASE
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_MPC85xx
#define CONFIG_P1023
#define CONFIG_MP /* support multiple processors */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_IS_IN_FLASH
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR 0xfff80000
-#else
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
/* Default address of microcode for the Linux Fman driver */
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xeff40000
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_SYS_MONITOR_BASE
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_MPC85xx
#define CONFIG_P1023
#define CONFIG_P1023RDS
#define CONFIG_MP /* support multiple processors */
/* NAND boot: 4K NAND loader config */
#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
#if defined(CONFIG_RAMBOOT_NAND)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x4000)
#endif
#else
#define CONFIG_ENV_IS_IN_FLASH
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR 0xfff80000
-#else
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
/* Default address of microcode for the Linux Fman driver */
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x1f00000
#ifdef CONFIG_SDCARD
#define CONFIG_RAMBOOT_SDCARD 1
#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH 1
#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#endif
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
/* NAND boot: 4K NAND loader config */
#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
#if defined(CONFIG_RAMBOOT_NAND)
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
- #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+ #define CONFIG_ENV_OFFSET ((768*1024)+CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_RAMBOOT_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#endif
#else
#define CONFIG_ENV_IS_IN_FLASH 1
- #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
- #define CONFIG_ENV_ADDR 0xfff80000
- #else
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
- #endif
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
#define CONFIG_P2020 1
#define CONFIG_P2020COME 1
#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
#ifdef CONFIG_SDCARD
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE 0xf8f80000
+#define CONFIG_SYS_TEXT_BASE 0xf8f40000
#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE 0xf8f80000
+#define CONFIG_SYS_TEXT_BASE 0xf8f40000
#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
#define CONFIG_P2020 1
#define CONFIG_P2020DS 1
#define CONFIG_MP 1 /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_ENV_SECT_SIZE 0x10000
#else
#define CONFIG_ENV_IS_IN_FLASH 1
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR 0xfff80000
-#else
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW \
+ $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
#define CONFIG_MP /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
- #define CONFIG_ENV_OFFSET (512 * 1097)
+ #define CONFIG_ENV_OFFSET (512 * 1658)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 545KB (1089 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
* (easy to change)
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_PCI405 1 /* ...on a PCI405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
* (easy to change)
***********************************************************/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_PIP405 1 /* ...on a PIP405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
*/
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_PLU405 1 /* ...on a PLU405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
*/
#define CONFIG_MPC5200
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_PM520 1 /* ... on PM520 board */
+#define CONFIG_PM520 1 /* PM520 board */
#define CONFIG_SYS_TEXT_BASE 0xfff00000
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_PMC405 1 /* ...on a PMC405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
#define __CONFIG_H
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
*----------------------------------------------------------------------*/
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFFF90000
*/
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */
#define CONFIG_NAND_U_BOOT
#define CONFIG_E300 1
-#define CONFIG_MPC83xx 1
#define CONFIG_MPC831x 1
#define CONFIG_MPC8313 1
* (easy to change)
*/
-#define CONFIG_MPC824X 1
#define CONFIG_MPC8240 1
#define CONFIG_SANDPOINT 1
* (easy to change)
*/
-#define CONFIG_MPC824X 1
#define CONFIG_MPC8245 1
#define CONFIG_SANDPOINT 1
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg
#endif
/* High Level Configuration Options */
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
#define CONFIG_MP /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET (512 * 1105)
+#define CONFIG_ENV_OFFSET (512 * 1658)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR3
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
-#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 545KB (1089 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
#define CONFIG_MP /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET (512 * 1105)
+#define CONFIG_ENV_OFFSET (512 * 1658)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 545KB (1089 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
#define CONFIG_MP /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET (512 * 1105)
+#define CONFIG_ENV_OFFSET (512 * 1658)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 545KB (1089 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
#define CONFIG_MP /* support multiple processors */
#define CONFIG_ENABLE_36BIT_PHYS
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg
#endif
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#endif
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET (512 * 1105)
+#define CONFIG_ENV_OFFSET (512 * 1658)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 545KB (1089 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#define CONFIG_SYS_INTERLAKEN
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
"bank_intlv=auto;" \
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=t4240emu/ramdisk.uboot\0" \
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET (512 * 1097)
+#define CONFIG_ENV_OFFSET (512 * 1658)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_BRDCFG5 0x55
+#define QIXIS_MUX_SDHC 2
+#define QIXIS_MUX_SDHC_WIDTH8 1
#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
#define CONFIG_SYS_CSPR3_EXT (0xf)
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 545KB (1089 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_ESDHC_DETECT_QUIRK \
+ (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
+ IS_SVR_REV(get_svr(), 1, 0))
+#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
+ (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
#endif
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
* (easy to change)
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
#define CONFIG_TB5200 1 /* ... on a TB5200 base board */
* (easy to change)
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
+#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */
/*
* (easy to change)
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC834x 1 /* MPC834x specific */
#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_TQM834X 1 /* TQM834X board specific */
* (easy to change)
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
+#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
#define CONFIG_TOTAL5200 1 /* ... on Total5200 board */
/*
*/
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_VOH405 1 /* ...on a VOH405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
* (easy to change)
*/
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_VOM405 1 /* ...on a VOM405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC8000
*/
#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
-#define CONFIG_4xx 1 /* ...member of PPC405 family */
#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */
#define CONFIG_W7OLMC 1 /* ...specifically an LMC */
*/
#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
-#define CONFIG_4xx 1 /* ...member of PPC405 family */
#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */
#define CONFIG_W7OLMG 1 /* ...specifically an LMG */
#define CONFIG_IDENT_STRING " $Name: $"
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_WUH405 1 /* ...on a WUH405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
*/
#define CONFIG_MPC5200
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_A3M071 /* ... on A3M071 board */
+#define CONFIG_A3M071 /* A3M071 board */
#define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
* (easy to change)
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
+#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
#define CONFIG_A4M072 1 /* ... on A4M072 board */
#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC512X 1 /* MPC512X family */
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_ACADIA 1 /* Board is Acadia */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
#ifndef CONFIG_SYS_TEXT_BASE
* (easy to change)
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
#define CONFIG_ALPR 1 /* Board is ebony */
#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+/* SPL USB Support */
+#define CONFIG_SPL_USB_SUPPORT
+#define CONFIG_SPL_USB_HOST_SUPPORT
+#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
+
#define CONFIG_CMD_USB
#define CONFIG_USB_HOST
#define CONFIG_USB_XHCI
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext4 rootwait\0" \
+ "usbroot=/dev/sda2 rw\0" \
+ "usbrootfstype=ext4 rootwait\0" \
+ "usbdev=0\0" \
"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
"ramrootfstype=ext2\0" \
"mmcargs=setenv bootargs console=${console} " \
"${optargs} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
+ "usbargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${usbroot} " \
+ "rootfstype=${usbrootfstype}\0" \
"bootenv=uEnv.txt\0" \
- "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+ "loadbootenv=load ${devtype} ${devnum} ${loadaddr} ${bootenv}\0" \
"importbootenv=echo Importing environment from mmc ...; " \
"env import -t $loadaddr $filesize\0" \
"ramargs=setenv bootargs console=${console} " \
"${optargs} " \
"root=${ramroot} " \
"rootfstype=${ramrootfstype}\0" \
- "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
- "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
- "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+ "loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \
+ "loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+ "loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
"mmcboot=mmc dev ${mmcdev}; " \
+ "setenv devnum ${mmcdev}; " \
"if mmc rescan; then " \
- "echo SD/MMC found on device ${mmcdev};" \
+ "echo SD/MMC found on device ${devnum};" \
"if run loadbootenv; then " \
"echo Loaded environment from ${bootenv};" \
"run importbootenv;" \
"bootz ${loadaddr} - ${fdtaddr}; " \
"fi;" \
"fi;\0" \
+ "usbboot=" \
+ "setenv devnum ${usbdev}; " \
+ "setenv devtype usb; " \
+ "usb start ${usbdev}; " \
+ "if usb dev ${usbdev}; then " \
+ "if run loadbootenv; then " \
+ "echo Loaded environment from ${bootenv};" \
+ "run importbootenv;" \
+ "fi;" \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loadimage; then " \
+ "run loadfdt; " \
+ "echo Booting from usb ${usbdev}...; " \
+ "run usbargs;" \
+ "bootz ${loadaddr} - ${fdtaddr}; " \
+ "fi;" \
+ "fi\0" \
"findfdt="\
"if test $board_name = AM43EPOS; then " \
"setenv fdtfile am43x-epos-evm.dtb; fi; " \
#define CONFIG_BOOTCOMMAND \
"run findfdt; " \
- "run mmcboot;"
+ "run mmcboot;" \
+ "run usbboot;"
#endif
#endif /* __CONFIG_AM43XX_EVM_H */
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC512X 1 /* MPC512X family */
#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
#define CONFIG_USB_EHCI_EXYNOS
#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
/* MMC SPL */
#define CONFIG_EXYNOS_SPL
#define CONFIG_SPL
#include <asm/arch/hardware.h>
-#define CONFIG_AVR32
#define CONFIG_AT32AP
#define CONFIG_AT32AP7000
#define CONFIG_ATNGW100
#include <asm/arch/hardware.h>
-#define CONFIG_AVR32
#define CONFIG_AT32AP
#define CONFIG_AT32AP7000
#define CONFIG_ATNGW100MKII
#include <asm/arch/hardware.h>
-#define CONFIG_AVR32
#define CONFIG_AT32AP
#define CONFIG_AT32AP7000
#define CONFIG_ATSTK1002
#include <asm/arch/hardware.h>
-#define CONFIG_AVR32
#define CONFIG_AT32AP
#define CONFIG_AT32AP7001
#define CONFIG_ATSTK1003
#include <asm/arch/hardware.h>
-#define CONFIG_AVR32
#define CONFIG_AT32AP
#define CONFIG_AT32AP7002
#define CONFIG_ATSTK1004
#include <asm/arch/hardware.h>
-#define CONFIG_AVR32
#define CONFIG_AT32AP
#define CONFIG_AT32AP7000
#define CONFIG_ATSTK1006
#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
#define CONFIG_440EP 1 /* Specific PPC440EP support */
#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_APM821XX 1 /* APM821XX series */
#define CONFIG_HOSTNAME bluestone
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1
#ifndef CONFIG_SYS_TEXT_BASE
*/
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
* (easy to change)
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
+#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */
/*
#endif
#define CONFIG_440 1
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
/*
* High Level Configuration Options
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_CM5200 1 /* ... on CM5200 platform */
#define CONFIG_SYS_TEXT_BASE 0xfc000000
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
#define CONFIG_P1022
#define CONFIG_CONTROLCENTERD
#define CONFIG_MP /* support multiple processors */
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
#if defined(CONFIG_P3041DS)
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg
+#define CONFIG_SYS_FSL_PBL_RCW \
+ $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg
#elif defined(CONFIG_P4080DS)
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
+#define CONFIG_SYS_FSL_PBL_RCW \
+ $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
#elif defined(CONFIG_P5020DS)
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
+#define CONFIG_SYS_FSL_PBL_RCW \
+ $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
#elif defined(CONFIG_P5040DS)
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg
+#define CONFIG_SYS_FSL_PBL_RCW \
+ $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg
#endif
#endif
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
#define CONFIG_MP /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET (512 * 1097)
+#define CONFIG_ENV_OFFSET (512 * 1658)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 545KB (1089 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
* (easy to change)
*/
-#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_ICECUBE 1 /* ... on IceCube board */
#define CONFIG_CPCI5200 1 /* ... on CPCI5200 board */
#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
*/
#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CSB272 1 /* on a Cogent CSB272 board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */
*/
#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CSB472 1 /* on a Cogent CSB472 board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */
* (easy to change)
*/
-#define CONFIG_MPC824X 1
#define CONFIG_MPC8245 1
#define CONFIG_DEBRIS 1
* High Level Configuration Options
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
/*
#define __CONFIG_H
#define CONFIG_405EP 1 /* this is a PPC405 CPU */
-#define CONFIG_4xx 1 /* member of PPC4xx family */
#define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
#define __CONFIG_H
#define CONFIG_405EP 1 /* this is a PPC405 CPU */
-#define CONFIG_4xx 1 /* member of PPC4xx family */
#define CONFIG_DLVISION 1 /* on a Neo board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
* (easy to change)
*/
-#define CONFIG_MPC824X 1
/* #define CONFIG_MPC8240 1 */
#define CONFIG_MPC8245 1
#define CONFIG_EXALION 1
#define CONFIG_EBONY 1 /* Board is ebony */
#define CONFIG_440GP 1 /* Specifc GP support */
#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#include <asm/arch/hardware.h>
-#define CONFIG_AVR32
#define CONFIG_AT32AP
#define CONFIG_AT32AP7000
#define CONFIG_FAVR32_EZKIT
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
/*
#define CONFIG_440GR 1 /* Specific PPC440GR support */
#define CONFIG_HOSTNAME gdppc440etx
#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
#include <asm/arch/hardware.h>
-#define CONFIG_AVR32
#define CONFIG_AT32AP
#define CONFIG_AT32AP7000
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_AVR32
#define CONFIG_AT32AP
#define CONFIG_AT32AP7000
#define CONFIG_HAMMERHEAD
* (easy to change)
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
-#define CONFIG_HMI1001 1 /* HMI1001 board */
+#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
+#define CONFIG_HMI1001 1 /* HMI1001 board */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
--- /dev/null
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * Configuration settings for the SolidRun Hummingboard.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+#include <asm/sizes.h>
+
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_MACH_TYPE 4773
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_I2C
+
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
+#define CONFIG_LOADADDR 0x12000000
+#define CONFIG_SYS_TEXT_BASE 0x17800000
+
+/* MMC Configuration */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* Ethernet Configuration */
+#define CONFIG_FEC_MXC
+#ifdef CONFIG_FEC_MXC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+#endif
+
+#if defined(CONFIG_MX6S)
+#define CONFIG_DEFAULT_FDT_FILE "imx6dl-hummingboard.dtb"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "uimage=uImage\0" \
+ "console=ttymxc0\0" \
+ "splashpos=m,m\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdt_addr=0x18000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+ "update_sd_firmware_filename=u-boot.imx\0" \
+ "update_sd_firmware=" \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "if mmc dev ${mmcdev}; then " \
+ "if ${get_cmd} ${update_sd_firmware_filename}; then " \
+ "setexpr fw_sz ${filesize} / 0x200; " \
+ "setexpr fw_sz ${fw_sz} + 1; " \
+ "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+ "fi; " \
+ "fi\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${uimage}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 1024
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif /* __CONFIG_H * */
* High Level Configuration Options
*/
#define CONFIG_ICON 1 /* Board is icon */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_440SPE 1 /* Specifc SPe support */
* (easy to change)
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
-#define CONFIG_INKA4X0 1 /* INKA4x0 board */
+#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
+#define CONFIG_INKA4X0 1 /* INKA4x0 board */
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
#define CONFIG_IDENT_STRING " intip 0.06"
#endif
#define CONFIG_440 1
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
#define __CONFIG_H
#define CONFIG_405EP 1 /* this is a PPC405 CPU */
-#define CONFIG_4xx 1 /* member of PPC4xx family */
#define CONFIG_IO 1 /* on a Io board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_IO64 1 /* Board is Io64 */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EX 1 /* Specifc 405EX support*/
#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
#define __CONFIG_H
#define CONFIG_405EP 1 /* this is a PPC405 CPU */
-#define CONFIG_4xx 1 /* member of PPC4xx family */
#define CONFIG_IOCON 1 /* on a IoCon board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
*/
#define CONFIG_MPC5200
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPX5200 1 /* ... on MPX5200 board */
-#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
+#define CONFIG_MPX5200 1 /* MPX5200 board */
+#define CONFIG_MPC5200_DDR 1 /* use DDR RAM */
#define CONFIG_IPEK01 /* Motherboard is ipek01 */
#define CONFIG_SYS_TEXT_BASE 0xfc000000
* (easy to change)
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* especially an MPC5200 */
+#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_JUPITER 1 /* ... on Jupiter board */
/*
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_KATMAI 1 /* Board is Katmai */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_440SPE 1 /* Specifc SPe support */
#define CONFIG_440SPE_REVA 1 /* Support old Rev A. */
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_KILAUEA 1 /* Board is Kilauea */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EX 1 /* Specifc 405EX support*/
#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC830x 1 /* MPC830x family */
#define CONFIG_MPC8309 1 /* MPC8309 CPU specific */
#define CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/keymile/kmp204x/pbi.cfg
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/keymile/kmp204x/rcw_kmp204x.cfg
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/keymile/kmp204x/pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/keymile/kmp204x/rcw_kmp204x.cfg
/* High Level Configuration Options */
#define CONFIG_BOOKE
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_MP /* support multiple processors */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NFS
#define CONFIG_CMD_BOOTZ
+
+#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
#define CONFIG_CMD_FLASH
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+#else
+/* SPI flash boot is default. */
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SYS_TEXT_BASE 0xE6304000
+#endif
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
-#define CONFIG_SYS_TEXT_BASE 0x00000000
+#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
-
/* ENV setting */
#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_ENV_SECT_SIZE (256 * 1024)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
CONFIG_SYS_MONITOR_LEN)
+
+#else /* CONFIG_SYS_USE_BOOT_NORFLASH */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SPI
+#define CONFIG_SH_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_FLASH_SPANSION
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_ADDR 0xC0000
+
+#endif /* CONFIG_SYS_USE_BOOT_NORFLASH */
+
+/* Common ENV setting */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SECT_SIZE (256 * 1024)
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
* High Level Configuration Options
*/
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333
#ifdef CONFIG_KORAT_PERMANENT
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MPC824X 1
#define CONFIG_MPC8245 1
#define CONFIG_KVME080 1
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NFS
#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_FLASH
+
+#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
+#define CONFIG_CMD_FLASH
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+#else
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SYS_TEXT_BASE 0xE8080000
+#endif
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
+#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
/* USE NOR FLASH */
-#define CONFIG_SYS_TEXT_BASE 0x00000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_FLASH_CFI_DRIVER
/* ENV setting */
#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_ENV_SECT_SIZE (256 * 1024)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
CONFIG_SYS_MONITOR_LEN)
+
+#else /* CONFIG_SYS_USE_BOOT_NORFLASH */
+
+/* USE SPI */
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SH_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SYS_NO_FLASH
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_ADDR 0xC0000
+#endif
+
+/* Common ENV setting */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SECT_SIZE (256 * 1024)
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
*----------------------------------------------------------------------*/
#define CONFIG_LUAN 1 /* Board is Luan */
#define CONFIG_440SP 1 /* Specific PPC440SP support */
-#define CONFIG_4xx 1 /* PPC4xx family */
#define CONFIG_440 1
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CONFIG_LWMON5 1 /* Board is lwmon5 */
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#ifdef CONFIG_LCD4_LWMON5
#define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_MAKALU 1 /* Board is Makalu */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EX 1 /* Specifc 405EX support*/
#define CONFIG_SYS_CLK_FREQ 33330000 /* ext frequency to pll */
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_MPC5200 1 /* MPC5200 CPU */
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
*/
#define CONFIG_MPC5200
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MCC200 1 /* ... on MCC200 board */
+#define CONFIG_MCC200 1 /* MCC200 board */
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC512X 1 /* MPC512X family */
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
* (easy to change)
*/
-#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_ICECUBE 1 /* ... on IceCube board */
#define CONFIG_MECP5200 1 /* ... on MECP5200 board */
#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
#include <asm/arch/hardware.h>
-#define CONFIG_AVR32
#define CONFIG_AT32AP
#define CONFIG_AT32AP7000
#define CONFIG_MIMC200
*/
/* CPU and board */
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
+#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
#define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC512X 1 /* MPC512X family */
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC830x 1 /* MPC830x family */
#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
#define CONFIG_MPC8308_P1M 1 /* mpc8308_p1m board specific */
+++ /dev/null
-/*
- * Copyright 2011 Alex Dubov <oakad@yahoo.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Merury Computers MPQ101 board configuration file
- *
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifdef CONFIG_36BIT
-# define CONFIG_PHYS_64BIT
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE /* BOOKE */
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
-#define CONFIG_MPC8548 /* MPC8548 specific */
-#define CONFIG_MPQ101 /* MPQ101 board specific */
-
-#define CONFIG_SYS_SRIO /* enable serial RapidIO */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_PANIC_HANG
-
-/*
- * Only possible on E500 Version 2 or newer cores.
- */
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#ifdef CONFIG_PHYS_64BIT
-# define CONFIG_ADDR_MAP
-# define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
-
-#define CONFIG_SYS_CLK_FREQ 33000000 /* sysclk for MPC85xx */
-
-#define CONFIG_SYS_CCSRBAR 0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR2
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/* Fixed 512MB DDR2 parameters */
-#define CONFIG_SYS_SDRAM_SIZE_LOG 29 /* DDR is 512MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014102
-#define CONFIG_SYS_DDR_TIMING_3 0x00010000
-#define CONFIG_SYS_DDR_TIMING_0 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1 0x5c47a432
-#define CONFIG_SYS_DDR_TIMING_1_PERF 0x49352322
-#define CONFIG_SYS_DDR_TIMING_2 0x03984cce
-#define CONFIG_SYS_DDR_TIMING_2_PERF 0x14904cca
-#define CONFIG_SYS_DDR_MODE_1 0x00400442
-#define CONFIG_SYS_DDR_MODE_1_PERF 0x00480432
-#define CONFIG_SYS_DDR_MODE_2 0x00000000
-#define CONFIG_SYS_DDR_MODE_2_PERF 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x08200100
-#define CONFIG_SYS_DDR_INTERVAL_PERF 0x06180100
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
-#define CONFIG_SYS_DDR_CONTROL 0xc3008000 /* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2 0x04400000
-
-#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_SYS_MEMTEST_START 0x0ff00000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0ffffffc
-
-/*
- * RAM definitions
- */
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
-
-
-/*
- * FLASH on the Local Bus
- * One bank, 128M, using the CFI driver.
- */
-#define CONFIG_SYS_BOOT_BLOCK 0xf8000000 /* boot TLB block */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
-
-#ifdef CONFIG_PHYS_64BIT
-# define CONFIG_SYS_FLASH_BASE_PHYS 0xff8000000ull
-#else
-# define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-/* 0xf8001801 */
-#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
- | BR_PS_32 | BR_V)
-
-/* 0xf8006ff7 */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 | OR_GPCM_TRLX \
- | OR_GPCM_EHTR | OR_GPCM_EAD)
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
-/*
- * Environment parameters
- */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_USE_PPCENV
-#define ENV_IS_EMBEDDED
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */
-#define CONFIG_ENV_SIZE 0x800
-
-/* Environment at the start of flash sector, before text. */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SIZE)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#define CONFIG_SYS_TEXT_BASE 0xfffc0800
-#define CONFIG_SYS_LDSCRIPT "board/mercury/mpq101/u-boot.lds"
-
-/*
- * Cypress CY7C67200 USB controller on the Local Bus.
- * Not supported by u-boot at present.
- */
-#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000
-
-#ifdef CONFIG_PHYS_64BIT
-# define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull
-#else
-# define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE
-#endif
-
-/* 0xf0001001 */
-#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \
- | BR_PS_16 | BR_V)
-
-/* fffff002 */
-#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \
- | OR_GPCM_BCTLD | OR_GPCM_EHTR)
-
-/*
- * Serial Ports
- */
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, 9600, \
- 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/*
- * I2C buses and peripherals
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/* I2C RTC - M41T81 */
-#define CONFIG_RTC_M41T62
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 2000
-
-/* I2C EEPROM - 24C256 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_BUS_NUM 1
-
-/*
- * RapidIO MMU
- */
-#ifdef CONFIG_SYS_SRIO
-# define CONFIG_SRIO1
-# define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
-# define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
-
-# ifdef CONFIG_PHYS_64BIT
-# define CONFIG_SYS_SRIO1_MEM_PHYS 0xfc0000000ull
-# else
-# define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_VIRT
-# endif
-#endif
-
-/*
- * Ethernet
- */
-#ifdef CONFIG_TSEC_ENET
-
-# define CONFIG_MII /* MII PHY management */
-# define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-
-# define CONFIG_TSEC1
-# define CONFIG_TSEC1_NAME "eTSEC0"
-# define TSEC1_PHY_ADDR 0x10
-# define TSEC1_PHYIDX 0
-# define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-# define CONFIG_TSEC2
-# define CONFIG_TSEC2_NAME "eTSEC1"
-# define TSEC2_PHY_ADDR 0x11
-# define TSEC2_PHYIDX 0
-# define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-# define CONFIG_TSEC3
-# define CONFIG_TSEC3_NAME "eTSEC2"
-# define TSEC3_PHY_ADDR 0x12
-# define TSEC3_PHYIDX 0
-# define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-# define CONFIG_TSEC4
-# define CONFIG_TSEC4_NAME "eTSEC3"
-# define TSEC4_PHY_ADDR 0x13
-# define TSEC4_PHYIDX 0
-# define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-/* Options are: eTSEC[0-3] */
-# define CONFIG_ETHPRIME "eTSEC0"
-# define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
-#endif
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_SETEXPR
-#define CONFIG_CMD_JFFS2
-
-/*
- * Miscellaneous configurable options
- */
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-#define CONFIG_FIT /* new uImage format support */
-#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "MPQ-101=> " /* Monitor Command Prompt */
-
-/* Console I/O Buffer Size */
-#ifdef CONFIG_CMD_KGDB
-# define CONFIG_SYS_CBSIZE 1024
-#else
-# define CONFIG_SYS_CBSIZE 256
-#endif
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
-
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 16 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-# define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Basic Environment Configuration
- */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
-
-/*default location for tftp and bootm*/
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
-
-#endif /* __CONFIG_H */
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
#define CONFIG_MUNICES 1 /* ... on MUNICes board */
+++ /dev/null
-/*
- * include/configs/mx1ads.h
- *
- * (c) Copyright 2004
- * Techware Information Technology, Inc.
- * http://www.techware.com.tw/
- *
- * Ming-Len Wu <minglen_wu@techware.com.tw>
- *
- * This is the Configuration setting for Motorola MX1ADS board
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
-#define CONFIG_IMX 1 /* It's a Motorola MC9328 SoC */
-#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */
-
-/*
- * Select serial console configuration
- */
-#define CONFIG_IMX_SERIAL
-#define CONFIG_IMX_SERIAL1 /* internal uart 1 */
-/* #define _CONFIG_UART2 */ /* internal uart 2 */
-/* #define CONFIG_SILENT_CONSOLE */ /* use this to disable output */
-
-#define CONFIG_BOARD_LATE_INIT
-#define USE_920T_MMU 1
-
-#if 0
-#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
-#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
-#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
-#endif
-
-/*
- * Size of malloc() pool
- */
-
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * CS8900 Ethernet drivers
- */
-#define CONFIG_CS8900 /* we have a CS8900 on-board */
-#define CONFIG_CS8900_BASE 0x15000300
-#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */
-
-/*
- * select serial console configuration
- */
-
-/* #define CONFIG_UART1 */
-/* #define CONFIG_UART2 1 */
-
-#define CONFIG_BAUDRATE 115200
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_ELF
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTARGS "root=/dev/msdk mem=48M"
-#define CONFIG_BOOTFILE "mx1ads"
-#define CONFIG_BOOTCOMMAND "tftp; bootm"
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "MX1ADS$ " /* Monitor Command Prompt */
-#else
-#define CONFIG_SYS_PROMPT "MX1ADS=> " /* Monitor Command Prompt */
-#endif
-
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
- /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x09000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x08800000 /* default load address */
-#define CONFIG_SYS_HZ 3686400
-#define CONFIG_SYS_CPUSPEED 0x141
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
-#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-
-#define CONFIG_SYS_TEXT_BASE 0x10000000
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00300000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x000FFFFF
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_GBL_DATA_OFFSET)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */
-#define CONFIG_SYS_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */
-#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYNCFLASH 1
-#define PHYS_FLASH_SIZE 0x01000000
-#define CONFIG_SYS_MAX_FLASH_SECT (16)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x00ff8000)
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE 0x100000
-
-/*-----------------------------------------------------------------------
- * Enable passing ATAGS
- */
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-
-#define CONFIG_SYS_CLK_FREQ 16780000
-#define CONFIG_SYSPLL_CLK_FREQ 16000000
-
-#endif /* __CONFIG_H */
#define CONFIG_LOADADDR 0x12000000
#define CONFIG_SYS_TEXT_BASE 0x17800000
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+#define EMMC_ENV \
+ "emmcdev=2\0" \
+ "update_emmc_firmware=" \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "if ${get_cmd} ${update_sd_firmware_filename}; then " \
+ "if mmc dev ${emmcdev} && " \
+ "mmc open ${emmcdev} 1; then " \
+ "setexpr fw_sz ${filesize} / 0x200; " \
+ "setexpr fw_sz ${fw_sz} + 1; " \
+ "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+ "mmc close ${emmcdev} 1; " \
+ "fi; " \
+ "fi\0"
+#else
+#define EMMC_ENV ""
+#endif
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"uimage=uImage\0" \
"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
"fi; " \
"fi\0" \
+ EMMC_ENV \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadbootscript=" \
#endif
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+
#include "mx6sabre_common.h"
#define CONFIG_SYS_FSL_USDHC_NUM 3
#include <asm/arch/imx-regs.h>
#include <asm/sizes.h>
+#include "mx6_common.h"
#define CONFIG_MX6
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_405EP 1 /* this is a PPC405 CPU */
-#define CONFIG_4xx 1 /* member of PPC4xx family */
#define CONFIG_NEO 1 /* on a Neo board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
/*
* High Level Configuration Options
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */
#define CONFIG_OCOTEA 1 /* Board is ebony */
#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
"setenv fdtfile omap3-beagle.dtb; fi; " \
"if test $beaglerev = Cx; then " \
"setenv fdtfile omap3-beagle.dtb; fi; " \
+ "if test $beaglerev = C4; then " \
+ "setenv fdtfile omap3-beagle.dtb; fi; " \
"if test $beaglerev = xMAB; then " \
"setenv fdtfile omap3-beagle-xm.dtb; fi; " \
"if test $beaglerev = xMC; then " \
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x18000
#define CONFIG_SPL_MAX_SIZE (96 * 1024)
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x18000
#define CONFIG_SPL_MAX_SIZE (96 * 1024)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
#define CONFIG_SPL_MAX_SIZE (128 << 10)
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
#endif
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
/* High Level Configuration Options */
#define CONFIG_BOOKE
#define CONFIG_E500
-#define CONFIG_MPC85xx
#define CONFIG_MP
#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR 0xfff80000
-#else
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#endif
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
/* High Level Configuration Options */
#define CONFIG_BOOKE
#define CONFIG_E500
-#define CONFIG_MPC85xx
#define CONFIG_MP
#endif
#else
#define CONFIG_ENV_IS_IN_FLASH
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR 0xfff80000
-#else
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
#define CONFIG_P3P440 1 /* Board is P3P440 */
#define CONFIG_440GP 1 /* Specifc GP support */
#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
High Level Configuration Options
(easy to change)
-----------------------------------------------------------------------------*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */
/* FEC configuration and IDE */
#define CONFIG_PCS440EP 1 /* Board is PCS440EP */
#define CONFIG_440EP 1 /* Specific PPC440EP support */
#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC512X 1 /* MPC512X family */
#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
#define CONFIG_SYS_TEXT_BASE 0xF0000000
* (easy to change)
*/
-#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_ICECUBE 1 /* ... on IceCube board */
#define CONFIG_PF5200 1 /* ... on PF5200 board */
#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_QUAD100HD 1 /* Board is Quad100hd */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EP 1 /* Specifc 405EP support*/
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1 /* ... PPC460 family */
#define CONFIG_460SX 1 /* ... PPC460 family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_SBC405 1 /* ...on a WR SBC405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC834x 1 /* MPC834x family */
#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */
*/
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_SBC8548 1 /* SBC8548 board specific */
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_MPC86xx 1 /* MPC86xx */
#define CONFIG_MPC8641 1 /* MPC8641 specific */
#define CONFIG_SBC8641D 1 /* SBC8641D board specific */
#define CONFIG_MP 1 /* support multiple processors */
*/
#define CONFIG_SC3 1
-#define CONFIG_4xx 1
#define CONFIG_405GP 1
#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
#define CONFIG_HOSTNAME rainier
#endif
#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
#define CONFIG_MPC8544 1
#define CONFIG_SOCRATES 1
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/
#define CONFIG_MPC8560 1
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
#define CONFIG_MPC8560 1
*/
#define CONFIG_460GT 1 /* Specific PPC460GT */
#define CONFIG_440 1
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
#define CONFIG_MP /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_405EP 1 /* this is a PPC405 CPU */
-#define CONFIG_4xx 1 /* member of PPC4xx family */
#define CONFIG_TAIHU 1 /* on a taihu board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
#define CONFIG_TAISHAN 1 /* Board is taishan */
#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Masami Komiya <mkomiya@sonare.it>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Config header file for TANBAC TB0229 board using an VR4131 CPU module
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
-#define CONFIG_TB0229 1 /* on a TB0229 Board */
-
-#ifndef CPU_CLOCK_RATE
-#define CPU_CLOCK_RATE 200000000 /* 200 MHz clock for the MIPS core */
-#endif
-#define CPU_TCLOCK_RATE 16588800 /* 16.5888 MHz for TClock */
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"boot\\\" for the network boot using DHCP, TFTP and NFS;" \
- "echo Type \\\"run netboot_initrd\\\" for the network boot with initrd;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo Type \\\"run flash_local\\\" to mount local root filesystem;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netboot=dhcp;tftp;run netargs; bootm\0" \
- "nfsargs=setenv bootargs root=/dev/nfs ip=dhcp\0" \
- "localargs=setenv bootargs root=1F02 ip=dhcp\0" \
- "addmisc=setenv bootargs ${bootargs} " \
- "console=ttyS0,${baudrate} " \
- "read-only=readonly\0" \
- "netargs=run nfsargs addmisc\0" \
- "flash_nfs=run nfsargs addmisc;" \
- "bootm ${kernel_addr}\0" \
- "flash_local=run localargs addmisc;" \
- "bootm ${kernel_addr}\0" \
- "netboot_initrd=dhcp;tftp;tftp 80600000 initrd;" \
- "setenv bootargs root=/dev/ram ramdisk_size=8192 ip=dhcp;"\
- "run addmisc;" \
- "bootm 80400000 80600000\0" \
- "rootpath=/export/miniroot-mipsel\0" \
- "autoload=no\0" \
- "kernel_addr=BFC60000\0" \
- "ramdisk_addr=B0100000\0" \
- "u-boot=u-boot.bin\0" \
- "bootfile=uImage\0" \
- "load=dhcp;tftp 80400000 ${u-boot}\0" \
- "load_kernel=dhcp;tftp 80400000 ${bootfile}\0" \
- "update_uboot=run load;" \
- "protect off BFC00000 BFC3FFFF;" \
- "erase BFC00000 BFC3FFFF;" \
- "cp.b 80400000 BFC00000 ${filesize}\0" \
- "update_kernel=run load_kernel;" \
- "erase BFC60000 BFD5FFFF;" \
- "cp.b 80400000 BFC60000 ${filesize}\0" \
- "initenv=erase bfc40000 bfc5ffff\0" \
- ""
-/*#define CONFIG_BOOTCOMMAND "run flash_local" */
-#define CONFIG_BOOTCOMMAND "run netboot"
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_ELF
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "# " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
-
-#define CONFIG_SYS_MALLOC_LEN 128*1024
-
-#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
-
-#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_TCLOCK_RATE/4)
-
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-
-#define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */
-
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END 0x80800000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
-
-#define PHYS_FLASH_1 0xbfc00000 /* Flash Bank #1 */
-
-/* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 << 10)
-
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (20 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-
-/* Address and size of Primary Environment Sector */
-#define CONFIG_ENV_ADDR 0xBFC40000
-#define CONFIG_ENV_SIZE 0x20000
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP
-
-#define CONFIG_NR_DRAM_BANKS 1
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE 16384
-#define CONFIG_SYS_ICACHE_SIZE 16384
-#define CONFIG_SYS_CACHELINE_SIZE 16
-
-/*-----------------------------------------------------------------------
- * Serial Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK 18432000
-#define CONFIG_SYS_NS16550_COM1 0xaf000800
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- */
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-
-#define CONFIG_RTL8139
-
-#endif /* __CONFIG_H */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x10502000
"u-boot mmc 80 400;" \
"uImage ext4 0 2;" \
"exynos4210-trats.dtb ext4 0 2;" \
- ""PARTS_ROOT" part 0 5\0"
+ ""PARTS_BOOT" part 0 2;" \
+ ""PARTS_ROOT" part 0 5;" \
+ ""PARTS_DATA" part 0 6;" \
+ ""PARTS_UMS" part 0 7\0"
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SYS_CACHELINE_SIZE 32
+#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x10502000
/* USB Composite download gadget - g_dnl */
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
+#define DFU_DEFAULT_POLL_TIMEOUT 300
#define CONFIG_DFU_FUNCTION
#define CONFIG_DFU_MMC
"u-boot mmc 80 800;" \
"uImage ext4 0 2;" \
"exynos4412-trats2.dtb ext4 0 2;" \
- ""PARTS_ROOT" part 0 5\0"
+ ""PARTS_BOOT" part 0 2;" \
+ ""PARTS_ROOT" part 0 5;" \
+ ""PARTS_DATA" part 0 6;" \
+ ""PARTS_UMS" part 0 7\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootk=" \
* (easy to change)
*/
-#define CONFIG_MPC824X 1
#define CONFIG_MPC8245 1
#define CONFIG_UTX8245 1
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_V38B 1 /* ...on V38B board */
* High Level Configuration Options
*/
#define CONFIG_E300 1
-#define CONFIG_MPC83xx 1
#define CONFIG_MPC831x 1
#define CONFIG_MPC8313 1
#define CONFIG_VE8313 1
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
-/* SMSC9115 Ethernet from SMSC9118 family */
-#define CONFIG_SMC9111 1
-#define CONFIG_SMC9111_BASE (0x1a000000)
+/* SMSC91C111 Ethernet Configuration */
+#define CONFIG_SMC91111 1
+#define CONFIG_SMC91111_BASE (0x01A000000)
/* PL011 Serial Configuration */
#define CONFIG_PL011_SERIAL
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC834x 1 /* MPC834x family */
#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_VME8349 1 /* ESD VME8349 board specific */
/*
* Memory settings
*/
-#define CONFIG_SYS_MSC0_VAL 0x3ffc95fa
+#define CONFIG_SYS_MSC0_VAL 0x3ffc95f9
#define CONFIG_SYS_MSC1_VAL 0x02ccf974
#define CONFIG_SYS_MSC2_VAL 0x00000000
#ifdef CONFIG_RAM_256M
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_WALNUT 1 /* ...on a WALNUT board */
/* ...or on a SYCAMORE board */
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
- "uimage=uImage\0" \
+ "image=zImage\0" \
"console=ttymxc0\0" \
"splashpos=m,m\0" \
"fdt_high=0xffffffff\0" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
- "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
- "bootm ${loadaddr} - ${fdt_addr}; " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
- "bootm; " \
+ "bootz; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
- "bootm; " \
+ "bootz; " \
"fi;\0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
- "${get_cmd} ${uimage}; " \
+ "${get_cmd} ${image}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
- "bootm ${loadaddr} - ${fdt_addr}; " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
- "bootm; " \
+ "bootz; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
- "bootm; " \
+ "bootz; " \
"fi;\0"
#define CONFIG_BOOTCOMMAND \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
- "if run loaduimage; then " \
+ "if run loadimage; then " \
"run mmcboot; " \
"else run netboot; " \
"fi; " \
/* cpu parameter */
#define CONFIG_405 1
-#define CONFIG_4xx 1
#define CONFIG_XILINX_405 1
#include <configs/xilinx-ppc.h>
#define __CONFIG_GEN_H
/*CPU*/
-#define CONFIG_4xx 1
#define CONFIG_440 1
#define CONFIG_XILINX_440 1
#define CONFIG_XPEDITE1000 1
#define CONFIG_SYS_BOARD_NAME "XPedite1000"
#define CONFIG_SYS_FORM_PMC 1
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1
#define CONFIG_440GX 1 /* 440 GX */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
/*
* High Level Configuration Options
*/
-#define CONFIG_MPC86xx 1 /* MPC86xx */
#define CONFIG_MPC8641 1 /* MPC8641 specific */
#define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
#define CONFIG_SYS_BOARD_NAME "XPedite5170"
*/
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
#define CONFIG_MPC8548 1
#define CONFIG_XPEDITE5200 1
#define CONFIG_SYS_BOARD_NAME "XPedite5200"
*/
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
#define CONFIG_MPC8572 1
#define CONFIG_XPEDITE5370 1
#define CONFIG_SYS_BOARD_NAME "XPedite5370"
*/
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
#define CONFIG_P2020 1
#define CONFIG_XPEDITE550X 1
#define CONFIG_SYS_BOARD_NAME "XPedite5500"
#define CONFIG_HOSTNAME yellowstone
#endif
#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_440SPE 1 /* Specifc SPe support */
#define CONFIG_440SPE_REVA 1 /* Support old Rev A. */
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_ZEUS 1 /* Board is Zeus */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EP 1 /* Specifc 405EP support*/
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+++ /dev/null
-#ifndef _CRAMFS_FS_SB
-#define _CRAMFS_FS_SB
-
-/*
- * cramfs super-block data in memory
- */
-struct cramfs_sb_info {
- unsigned long magic;
- unsigned long size;
- unsigned long blocks;
- unsigned long files;
- unsigned long flags;
-#ifdef CONFIG_CRAMFS_LINEAR
- unsigned long linear_phys_addr;
- char * linear_virt_addr;
-#endif
-};
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2006 DENX Software Engineering
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* DA9030 register definitions */
-#define CID 0x00
-#define EVENT_A 0x01
-#define EVENT_B 0x02
-#define EVENT_C 0x03
-#define STATUS 0x04
-#define IRQ_MASK_A 0x05
-#define IRQ_MASK_B 0x06
-#define IRQ_MASK_C 0x07
-#define SYS_CONTROL_A 0x08
-#define SYS_CONTROL_B 0x09
-#define FAULT_LOG 0x0A
-#define LDO_10_11 0x10
-#define LDO_15 0x11
-#define LDO_14_16 0x12
-#define LDO_18_19 0x13
-#define LDO_17_SIMCP0 0x14
-#define BUCK2_DVC1 0x15
-#define BUCK2_DVC2 0x16
-#define REG_CONTROL_1_17 0x17
-#define REG_CONTROL_2_18 0x18
-#define USBPUMP 0x19
-#define SLEEP_CONTROL 0x1A
-#define STARTUP_CONTROL 0x1B
-#define LED1_CONTROL 0x20
-#define LED2_CONTROL 0x21
-#define LED3_CONTROL 0x22
-#define LED4_CONTROL 0x23
-#define LEDPC_CONTROL 0x24
-#define WLED_CONTROL 0x25
-#define MISC_CONTROLA 0x26
-#define MISC_CONTROLB 0x27
-#define CHARGE_CONTROL 0x28
-#define CCTR_CONTROL 0x29
-#define TCTR_CONTROL 0x2A
-#define CHARGE_PULSE 0x2B
-
-/* ... some missing ...*/
-
-#define LDO1 0x90
-#define LDO2_3 0x91
-#define LDO4_5 0x92
-#define LDO6_SIMCP 0x93
-#define LDO7_8 0x94
-#define LDO9_12 0x95
-#define BUCK 0x96
-#define REG_CONTROL_1_97 0x97
-#define REG_CONTROL_2_98 0x98
-#define REG_SLEEP_CONTROL1 0x99
-#define REG_SLEEP_CONTROL2 0x9A
-#define REG_SLEEP_CONTROL3 0x9B
-#define ADC_MAN_CONTROL 0xA0
-#define ADC_AUTO_CONTROL 0xA1
-#define VBATMON 0xA2
-#define VBATMONTXMON 0xA3
-#define TBATHIGHP 0xA4
-#define TBATHIGHN 0xA5
-#define TBATLOW 0xA6
-#define MAN_RES 0xB0
-#define VBAT_RES 0xB1
-#define VBATMIN_RES 0xB2
-#define VBATMINTXON_RES 0xB3
-#define ICHMAX_RES 0xB4
-#define ICHMIN_RES 0xB5
-#define ICHAVERAGE_RES 0xB6
-#define VCHMAX_RES 0xB7
-#define VCHMIN_RES 0xB8
-#define TBAT_RES 0xB9
-#define ADC_IN4_RES 0xBA
-
-#define STATUS_ONKEY_N 0x1 /* current ONKEY_N value */
-#define STATUS_PWREN1 (1<<1) /* PWREN1 value */
-#define STATUS_EXTON (1<<2) /* EXTON value */
-#define STATUS_CHDET (1<<3) /* Charger detection status */
-#define STATUS_TBAT (1<<4) /* Battery over/under temperature status */
-#define STATUS_VBATMON (1<<5) /* VBATMON comparison status */
-#define STATUS_VBATMONTXON (1<<6) /* VBATMONTXON comparison status */
-#define STATUS_CHIOVER (1<<7) /* Charge overcurrent */
-
-#define SYS_CONTROL_A_SLEEP_N_PIN_ENABLE 0x1
-#define SYS_CONTROL_A_SHUT_DOWN (1<<1)
-#define SYS_CONTROL_A_HWRES_ENABLE (1<<2)
-#define SYS_CONTROL_A_WDOG_ACTION (1<<3)
-#define SYS_CONTROL_A_WATCHDOG (1<<7)
-
-#define MISC_CONTROLB_USB_INT_RISING (1<<2)
-#define MISC_CONTROLB_SESSION_VALID_EN (1<<3)
-
-#define USB_PUMP_USBVE (1<<0)
-#define USB_PUMP_USBVEP (1<<1)
-#define USB_PUMP_SRP_DETECT (1<<2)
-#define USB_PUMP_SESSION_VALID (1<<3)
-#define USB_PUMP_VBUS_VALID_4_0 (1<<4)
-#define USB_PUMP_VBUS_VALID_4_4 (1<<5)
-#define USB_PUMP_EN_USBVE (1<<6)
-#define USB_PUMP_EN_USBVEP (1<<7)
+++ /dev/null
-/*
- * NOTE: DAVICOM ethernet Physical layer
- *
- * Version: @(#)DM9161.h 1.0.0 01/10/2001
- *
- * Authors: ATMEL Rousset
- *
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-/* DAVICOM PHYSICAL LAYER TRANSCEIVER DM9161 */
-
-#define DM9161_BMCR 0 /* Basic Mode Control Register */
-#define DM9161_BMSR 1 /* Basic Mode Status Register */
-#define DM9161_PHYID1 2 /* PHY Idendifier Register 1 */
-#define DM9161_PHYID2 3 /* PHY Idendifier Register 2 */
-#define DM9161_ANAR 4 /* Auto_Negotiation Advertisement Register */
-#define DM9161_ANLPAR 5 /* Auto_negotiation Link Partner Ability Register */
-#define DM9161_ANER 6 /* Auto-negotiation Expansion Register */
-#define DM9161_DSCR 16 /* Specified Configuration Register */
-#define DM9161_DSCSR 17 /* Specified Configuration and Status Register */
-#define DM9161_10BTCSR 18 /* 10BASE-T Configuration and Satus Register */
-#define DM9161_MDINTR 21 /* Specified Interrupt Register */
-#define DM9161_RECR 22 /* Specified Receive Error Counter Register */
-#define DM9161_DISCR 23 /* Specified Disconnect Counter Register */
-#define DM9161_RLSR 24 /* Hardware Reset Latch State Register */
-
-
-/* --Bit definitions: DM9161_BMCR */
-#define DM9161_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */
-#define DM9161_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */
-#define DM9161_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */
-#define DM9161_AUTONEG (1 << 12)
-#define DM9161_POWER_DOWN (1 << 11)
-#define DM9161_ISOLATE (1 << 10)
-#define DM9161_RESTART_AUTONEG (1 << 9)
-#define DM9161_DUPLEX_MODE (1 << 8)
-#define DM9161_COLLISION_TEST (1 << 7)
-
-/*--Bit definitions: DM9161_BMSR */
-#define DM9161_100BASE_TX (1 << 15)
-#define DM9161_100BASE_TX_FD (1 << 14)
-#define DM9161_100BASE_TX_HD (1 << 13)
-#define DM9161_10BASE_T_FD (1 << 12)
-#define DM9161_10BASE_T_HD (1 << 11)
-#define DM9161_MF_PREAMB_SUPPR (1 << 6)
-#define DM9161_AUTONEG_COMP (1 << 5)
-#define DM9161_REMOTE_FAULT (1 << 4)
-#define DM9161_AUTONEG_ABILITY (1 << 3)
-#define DM9161_LINK_STATUS (1 << 2)
-#define DM9161_JABBER_DETECT (1 << 1)
-#define DM9161_EXTEND_CAPAB (1 << 0)
-
-/*--definitions: DM9161_PHYID1 */
-#define DM9161_PHYID1_OUI 0x606E
-#define DM9161_LSB_MASK 0x3F
-
-/*--Bit definitions: DM9161_ANAR, DM9161_ANLPAR */
-#define DM9161_NP (1 << 15)
-#define DM9161_ACK (1 << 14)
-#define DM9161_RF (1 << 13)
-#define DM9161_FCS (1 << 10)
-#define DM9161_T4 (1 << 9)
-#define DM9161_TX_FDX (1 << 8)
-#define DM9161_TX_HDX (1 << 7)
-#define DM9161_10_FDX (1 << 6)
-#define DM9161_10_HDX (1 << 5)
-#define DM9161_AN_IEEE_802_3 0x0001
-
-/*--Bit definitions: DM9161_ANER */
-#define DM9161_PDF (1 << 4)
-#define DM9161_LP_NP_ABLE (1 << 3)
-#define DM9161_NP_ABLE (1 << 2)
-#define DM9161_PAGE_RX (1 << 1)
-#define DM9161_LP_AN_ABLE (1 << 0)
-
-/*--Bit definitions: DM9161_DSCR */
-#define DM9161_BP4B5B (1 << 15)
-#define DM9161_BP_SCR (1 << 14)
-#define DM9161_BP_ALIGN (1 << 13)
-#define DM9161_BP_ADPOK (1 << 12)
-#define DM9161_REPEATER (1 << 11)
-#define DM9161_TX (1 << 10)
-#define DM9161_RMII_ENABLE (1 << 8)
-#define DM9161_F_LINK_100 (1 << 7)
-#define DM9161_SPLED_CTL (1 << 6)
-#define DM9161_COLLED_CTL (1 << 5)
-#define DM9161_RPDCTR_EN (1 << 4)
-#define DM9161_SM_RST (1 << 3)
-#define DM9161_MFP SC (1 << 2)
-#define DM9161_SLEEP (1 << 1)
-#define DM9161_RLOUT (1 << 0)
-
-/*--Bit definitions: DM9161_DSCSR */
-#define DM9161_100FDX (1 << 15)
-#define DM9161_100HDX (1 << 14)
-#define DM9161_10FDX (1 << 13)
-#define DM9161_10HDX (1 << 12)
-
-/*--Bit definitions: DM9161_10BTCSR */
-#define DM9161_LP_EN (1 << 14)
-#define DM9161_HBE (1 << 13)
-#define DM9161_SQUELCH (1 << 12)
-#define DM9161_JABEN (1 << 11)
-#define DM9161_10BT_SER (1 << 10)
-#define DM9161_POLR (1 << 0)
-
-
-/*--Bit definitions: DM9161_MDINTR */
-#define DM9161_INTR_PEND (1 << 15)
-#define DM9161_FDX_MASK (1 << 11)
-#define DM9161_SPD_MASK (1 << 10)
-#define DM9161_LINK_MASK (1 << 9)
-#define DM9161_INTR_MASK (1 << 8)
-#define DM9161_FDX_CHANGE (1 << 4)
-#define DM9161_SPD_CHANGE (1 << 3)
-#define DM9161_LINK_CHANGE (1 << 2)
-#define DM9161_INTR_STATUS (1 << 0)
-
-
-/****************** function prototypes **********************/
-unsigned int dm9161_IsPhyConnected(AT91PS_EMAC p_mac);
-unsigned char dm9161_GetLinkSpeed(AT91PS_EMAC p_mac);
-unsigned char dm9161_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
-unsigned char dm9161_InitPhy(AT91PS_EMAC p_mac);
+++ /dev/null
-/*
- * (C) Copyright 2013 Faraday Technology
- * Dante Su <dantesu@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __FTSDC021_H
-#define __FTSDC021_H
-
-int ftsdc021_sdhci_init(u32 regbase);
-
-#endif /* __FTSDC021_H */
+++ /dev/null
-/*
- * NOTE: MICREL ethernet Physical layer
- *
- * Version: KS8721.h
- *
- * Authors: Eric Benard (based on dm9161.h)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* MICREL PHYSICAL LAYER TRANSCEIVER KS8721 */
-
-#define KS8721_BMCR 0
-#define KS8721_BMSR 1
-#define KS8721_PHYID1 2
-#define KS8721_PHYID2 3
-#define KS8721_ANAR 4
-#define KS8721_ANLPAR 5
-#define KS8721_ANER 6
-#define KS8721_RECR 15
-#define KS8721_MDINTR 27
-#define KS8721_100BT 31
-
-/* --Bit definitions: KS8721_BMCR */
-#define KS8721_RESET (1 << 15)
-#define KS8721_LOOPBACK (1 << 14)
-#define KS8721_SPEED_SELECT (1 << 13)
-#define KS8721_AUTONEG (1 << 12)
-#define KS8721_POWER_DOWN (1 << 11)
-#define KS8721_ISOLATE (1 << 10)
-#define KS8721_RESTART_AUTONEG (1 << 9)
-#define KS8721_DUPLEX_MODE (1 << 8)
-#define KS8721_COLLISION_TEST (1 << 7)
-#define KS8721_DISABLE (1 << 0)
-
-/*--Bit definitions: KS8721_BMSR */
-#define KS8721_100BASE_T4 (1 << 15)
-#define KS8721_100BASE_TX_FD (1 << 14)
-#define KS8721_100BASE_T4_HD (1 << 13)
-#define KS8721_10BASE_T_FD (1 << 12)
-#define KS8721_10BASE_T_HD (1 << 11)
-#define KS8721_MF_PREAMB_SUPPR (1 << 6)
-#define KS8721_AUTONEG_COMP (1 << 5)
-#define KS8721_REMOTE_FAULT (1 << 4)
-#define KS8721_AUTONEG_ABILITY (1 << 3)
-#define KS8721_LINK_STATUS (1 << 2)
-#define KS8721_JABBER_DETECT (1 << 1)
-#define KS8721_EXTEND_CAPAB (1 << 0)
-
-/*--Bit definitions: KS8721_PHYID */
-#define KS8721_PHYID_OUI 0x0885
-#define KS8721_LSB_MASK 0x3F
-
-#define KS8721BL_MODEL 0x21
-#define KS8721_MODELMASK 0x3F0
-#define KS8721BL_REV 0x9
-#define KS8721_REVMASK 0xF
-
-/*--Bit definitions: KS8721_ANAR, KS8721_ANLPAR */
-#define KS8721_NP (1 << 15)
-#define KS8721_ACK (1 << 14)
-#define KS8721_RF (1 << 13)
-#define KS8721_PAUSE (1 << 10)
-#define KS8721_T4 (1 << 9)
-#define KS8721_TX_FDX (1 << 8)
-#define KS8721_TX_HDX (1 << 7)
-#define KS8721_10_FDX (1 << 6)
-#define KS8721_10_HDX (1 << 5)
-#define KS8721_AN_IEEE_802_3 0x0001
-
-/****************** function prototypes **********************/
-unsigned int ks8721_isphyconnected(AT91PS_EMAC p_mac);
-unsigned char ks8721_getlinkspeed(AT91PS_EMAC p_mac);
-unsigned char ks8721_autonegotiate(AT91PS_EMAC p_mac, int *status);
-unsigned char ks8721_initphy(AT91PS_EMAC p_mac);
+++ /dev/null
-/*
- * $Id: inftl-user.h,v 1.2 2005/11/07 11:14:56 gleixner Exp $
- *
- * Parts of INFTL headers shared with userspace
- *
- */
-
-#ifndef __MTD_INFTL_USER_H__
-#define __MTD_INFTL_USER_H__
-
-#define OSAK_VERSION 0x5120
-#define PERCENTUSED 98
-
-#define SECTORSIZE 512
-
-/* Block Control Information */
-
-struct inftl_bci {
- uint8_t ECCsig[6];
- uint8_t Status;
- uint8_t Status1;
-} __attribute__((packed));
-
-struct inftl_unithead1 {
- uint16_t virtualUnitNo;
- uint16_t prevUnitNo;
- uint8_t ANAC;
- uint8_t NACs;
- uint8_t parityPerField;
- uint8_t discarded;
-} __attribute__((packed));
-
-struct inftl_unithead2 {
- uint8_t parityPerField;
- uint8_t ANAC;
- uint16_t prevUnitNo;
- uint16_t virtualUnitNo;
- uint8_t NACs;
- uint8_t discarded;
-} __attribute__((packed));
-
-struct inftl_unittail {
- uint8_t Reserved[4];
- uint16_t EraseMark;
- uint16_t EraseMark1;
-} __attribute__((packed));
-
-union inftl_uci {
- struct inftl_unithead1 a;
- struct inftl_unithead2 b;
- struct inftl_unittail c;
-};
-
-struct inftl_oob {
- struct inftl_bci b;
- union inftl_uci u;
-};
-
-
-/* INFTL Media Header */
-
-struct INFTLPartition {
- __u32 virtualUnits;
- __u32 firstUnit;
- __u32 lastUnit;
- __u32 flags;
- __u32 spareUnits;
- __u32 Reserved0;
- __u32 Reserved1;
-} __attribute__((packed));
-
-struct INFTLMediaHeader {
- char bootRecordID[8];
- __u32 NoOfBootImageBlocks;
- __u32 NoOfBinaryPartitions;
- __u32 NoOfBDTLPartitions;
- __u32 BlockMultiplierBits;
- __u32 FormatFlags;
- __u32 OsakVersion;
- __u32 PercentUsed;
- struct INFTLPartition Partitions[4];
-} __attribute__((packed));
-
-/* Partition flag types */
-#define INFTL_BINARY 0x20000000
-#define INFTL_BDTL 0x40000000
-#define INFTL_LAST 0x80000000
-
-#endif /* __MTD_INFTL_USER_H__ */
+++ /dev/null
-/*
- * $Id: jffs2-user.h,v 1.1 2004/05/05 11:57:54 dwmw2 Exp $
- *
- * JFFS2 definitions for use in user space only
- */
-
-#ifndef __JFFS2_USER_H__
-#define __JFFS2_USER_H__
-
-/* This file is blessed for inclusion by userspace */
-#include <linux/jffs2.h>
-#include <endian.h>
-#include <byteswap.h>
-
-#undef cpu_to_je16
-#undef cpu_to_je32
-#undef cpu_to_jemode
-#undef je16_to_cpu
-#undef je32_to_cpu
-#undef jemode_to_cpu
-
-extern int target_endian;
-
-#define t16(x) ({ uint16_t __b = (x); (target_endian==__BYTE_ORDER)?__b:bswap_16(__b); })
-#define t32(x) ({ uint32_t __b = (x); (target_endian==__BYTE_ORDER)?__b:bswap_32(__b); })
-
-#define cpu_to_je16(x) ((jint16_t){t16(x)})
-#define cpu_to_je32(x) ((jint32_t){t32(x)})
-#define cpu_to_jemode(x) ((jmode_t){t32(x)})
-
-#define je16_to_cpu(x) (t16((x).v16))
-#define je32_to_cpu(x) (t32((x).v32))
-#define jemode_to_cpu(x) (t32((x).m))
-
-#endif /* __JFFS2_USER_H__ */
*
* \param ptr Pointer to memory block to free
*/
-void *os_free(void *ptr);
+void os_free(void *ptr);
/**
* Reallocate previously-allocated memory to increase/decrease space
+++ /dev/null
-/*
- * (C) Copyright 1997-2002 ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * smiLynxEM.h
- * Silicon Motion graphic interface for sm810/sm710/sm712 accelerator
- *
- *
- * modification history
- * --------------------
- * 04-18-2002 Rewritten for U-Boot <fgottschling@eltec.de>.
- */
-
-#ifndef _SMI_LYNX_EM_H_
-#define _SMI_LYNX_EM_H_
-
-/*
- * SMI 710/712 have 4MB internal RAM; SMI 810 2MB internal + 2MB external
- */
-#define VIDEO_MEM_SIZE 0x400000
-
-/*
- * Supported video modes for SMI Lynx E/EM/EM+
- */
-#define VIDEO_MODES 7
-#define DUAL_800_600 0 /* SMI710:VGA1:75Hz (pitch=1600) */
- /* VGA2:60/120Hz (pitch=1600) */
- /* SMI810:VGA1:75Hz (pitch=1600) */
- /* VGA2:75Hz (pitch=1600) */
-#define DUAL_1024_768 1 /* VGA1:75Hz VGA2:73Hz (pitch=2048) */
-#define SINGLE_800_600 2 /* VGA1:75Hz (pitch=800) */
-#define SINGLE_1024_768 3 /* VGA1:75Hz (pitch=1024) */
-#define SINGLE_1280_1024 4 /* VGA1:75Hz (pitch=1280) */
-#define TV_MODE_CCIR 5 /* VGA1:50Hz (h=720;v=576;pitch=720) */
-#define TV_MODE_EIA 6 /* VGA1:60Hz (h=720;v=484;pitch=720) */
-
-
-/*
- * ISA mapped regs
- */
-#define SMI_INDX_C4 (pGD->isaBase + 0x03c4) /* index reg */
-#define SMI_DATA_C5 (pGD->isaBase + 0x03c5) /* data reg */
-#define SMI_INDX_D4 (pGD->isaBase + 0x03d4) /* index reg */
-#define SMI_DATA_D5 (pGD->isaBase + 0x03d5) /* data reg */
-#define SMI_INDX_CE (pGD->isaBase + 0x03ce) /* index reg */
-#define SMI_DATA_CF (pGD->isaBase + 0x03cf) /* data reg */
-#define SMI_LOCK_REG (pGD->isaBase + 0x03c3) /* unlock/lock ext crt reg */
-#define SMI_MISC_REG (pGD->isaBase + 0x03c2) /* misc reg */
-#define SMI_LUT_MASK (pGD->isaBase + 0x03c6) /* lut mask reg */
-#define SMI_LUT_START (pGD->isaBase + 0x03c8) /* lut start index */
-#define SMI_LUT_RGB (pGD->isaBase + 0x03c9) /* lut colors auto incr.*/
-
-
-/*
- * Video processor control
- */
-typedef struct {
- unsigned int control;
- unsigned int colorKey;
- unsigned int colorKeyMask;
- unsigned int start;
- unsigned short offset;
- unsigned short width;
- unsigned int fifoPrio;
- unsigned int fifoERL;
- unsigned int YUVtoRGB;
-} SmiVideoProc;
-
-/*
- * Video window control
- */
-typedef struct {
- unsigned short top;
- unsigned short left;
- unsigned short bottom;
- unsigned short right;
- unsigned int srcStart;
- unsigned short width;
- unsigned short offset;
- unsigned char hStretch;
- unsigned char vStretch;
-} SmiVideoWin;
-
-/*
- * Capture port control
- */
-typedef struct {
- unsigned int control;
- unsigned short topClip;
- unsigned short leftClip;
- unsigned short srcHeight;
- unsigned short srcWidth;
- unsigned int srcBufStart1;
- unsigned int srcBufStart2;
- unsigned short srcOffset;
- unsigned short fifoControl;
-} SmiCapturePort;
-
-
-/******************************************************************************/
-/* Export Graphic Driver Control */
-/******************************************************************************/
-
-typedef struct {
- unsigned int isaBase;
- unsigned int pciBase;
- unsigned int dprBase;
- unsigned int vprBase;
- unsigned int cprBase;
- unsigned int frameAdrs;
- unsigned int memSize;
- unsigned int mode;
- unsigned int gdfIndex;
- unsigned int gdfBytesPP;
- unsigned int fg;
- unsigned int bg;
- unsigned int plnSizeX;
- unsigned int plnSizeY;
- unsigned int winSizeX;
- unsigned int winSizeY;
- char modeIdent[80];
-} GraphicDevice;
-
-extern GraphicDevice smi;
-
-
-/******************************************************************************/
-/* Export Graphic Functions */
-/******************************************************************************/
-
-void *video_hw_init (void); /* returns GraphicDevice struct or NULL */
-
-void video_hw_bitblt (
- unsigned int bpp, /* bytes per pixel */
- unsigned int src_x, /* source pos x */
- unsigned int src_y, /* source pos y */
- unsigned int dst_x, /* dest pos x */
- unsigned int dst_y, /* dest pos y */
- unsigned int dim_x, /* frame width */
- unsigned int dim_y /* frame height */
- );
-
-void video_hw_rectfill (
- unsigned int bpp, /* bytes per pixel */
- unsigned int dst_x, /* dest pos x */
- unsigned int dst_y, /* dest pos y */
- unsigned int dim_x, /* frame width */
- unsigned int dim_y, /* frame height */
- unsigned int color /* fill color */
- );
-
-void video_set_lut (
- unsigned int index, /* color number */
- unsigned char r, /* red */
- unsigned char g, /* green */
- unsigned char b /* blue */
- );
-
-#endif /*_SMI_LYNX_EM_H_ */
#define SPI_XFER_MMAP 0x08 /* Memory Mapped start */
#define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */
#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
+#define SPI_XFER_U_PAGE (1 << 5)
+
+/* SPI TX operation modes */
+#define SPI_OPM_TX_QPP 1 << 0
+
+/* SPI RX operation modes */
+#define SPI_OPM_RX_AS 1 << 0
+#define SPI_OPM_RX_DOUT 1 << 1
+#define SPI_OPM_RX_DIO 1 << 2
+#define SPI_OPM_RX_QOF 1 << 3
+#define SPI_OPM_RX_QIOF 1 << 4
+#define SPI_OPM_RX_EXTN SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \
+ SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \
+ SPI_OPM_RX_QIOF
+
+/* SPI bus connection options */
+#define SPI_CONN_DUAL_SHARED 1 << 0
+#define SPI_CONN_DUAL_SEPARATED 1 << 1
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
*
* @bus: ID of the bus that the slave is attached to.
* @cs: ID of the chip select connected to the slave.
+ * @op_mode_rx: SPI RX operation mode.
+ * @op_mode_tx: SPI TX operation mode.
* @wordlen: Size of SPI word in number of bits
* @max_write_size: If non-zero, the maximum number of bytes which can
* be written at once, excluding command bytes.
* @memory_map: Address of read-only SPI flash access.
+ * @option: Varies SPI bus options - separate, shared bus.
+ * @flags: Indication of SPI flags.
*/
struct spi_slave {
unsigned int bus;
unsigned int cs;
+ u8 op_mode_rx;
+ u8 op_mode_tx;
unsigned int wordlen;
unsigned int max_write_size;
void *memory_map;
+ u8 option;
+ u8 flags;
};
/**
#include <linux/types.h>
#include <linux/compiler.h>
+/* sf param flags */
+#define SECT_4K 1 << 1
+#define SECT_32K 1 << 2
+#define E_FSR 1 << 3
+#define WR_QPP 1 << 4
+
+/* Enum list - Full read commands */
+enum spi_read_cmds {
+ ARRAY_SLOW = 1 << 0,
+ DUAL_OUTPUT_FAST = 1 << 1,
+ DUAL_IO_FAST = 1 << 2,
+ QUAD_OUTPUT_FAST = 1 << 3,
+ QUAD_IO_FAST = 1 << 4,
+};
+#define RD_EXTN ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST
+#define RD_FULL RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST
+
+/* Dual SPI flash memories */
+enum spi_dual_flash {
+ SF_SINGLE_FLASH = 0,
+ SF_DUAL_STACKED_FLASH = 1 << 0,
+ SF_DUAL_PARALLEL_FLASH = 1 << 1,
+};
+
+/**
+ * struct spi_flash_params - SPI/QSPI flash device params structure
+ *
+ * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
+ * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
+ * @ext_jedec: Device ext_jedec ID
+ * @sector_size: Sector size of this device
+ * @nr_sectors: No.of sectors on this device
+ * @e_rd_cmd: Enum list for read commands
+ * @flags: Importent param, for flash specific behaviour
+ */
+struct spi_flash_params {
+ const char *name;
+ u32 jedec;
+ u16 ext_jedec;
+ u32 sector_size;
+ u32 nr_sectors;
+ u8 e_rd_cmd;
+ u16 flags;
+};
+
+extern const struct spi_flash_params spi_flash_params_table[];
+
/**
* struct spi_flash - SPI flash structure
*
* @spi: SPI slave
* @name: Name of SPI flash
+ * @dual_flash: Indicates dual flash memories - dual stacked, parallel
+ * @shift: Flash shift useful in dual parallel
* @size: Total flash size
* @page_size: Write (page) size
* @sector_size: Sector size
* @bank_curr: Current flash bank
* @poll_cmd: Poll cmd - for flash erase/program
* @erase_cmd: Erase cmd 4K, 32K, 64K
+ * @read_cmd: Read cmd - Array Fast, Extn read and quad read.
+ * @write_cmd: Write cmd - page and quad program.
+ * @dummy_byte: Dummy cycles for read operation.
* @memory_map: Address of read-only SPI flash access
* @read: Flash read ops: Read len bytes at offset into buf
* Supported cmds: Fast Array Read
struct spi_flash {
struct spi_slave *spi;
const char *name;
+ u8 dual_flash;
+ u8 shift;
u32 size;
u32 page_size;
#endif
u8 poll_cmd;
u8 erase_cmd;
+ u8 read_cmd;
+ u8 write_cmd;
+ u8 dummy_byte;
void *memory_map;
int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf);
#include <linux/compiler.h>
#include <asm/spl.h>
+
/* Boot type */
#define MMCSD_MODE_UNDEFINED 0
#define MMCSD_MODE_RAW 1
/* Ethernet SPL functions */
void spl_net_load_image(const char *device);
+/* USB SPL functions */
+void spl_usb_load_image(void);
+
+/* SPL FAT image functions */
+int spl_load_image_fat(block_dev_desc_t *block_dev, int partition, const char *filename);
+int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition);
+
#ifdef CONFIG_SPL_BOARD_INIT
void spl_board_init(void);
#endif
#define UMS_NUM_SECTORS 0
#endif
+/* Wait at maximum 60 seconds for cable connection */
+#define UMS_CABLE_READY_TIMEOUT 60
+
struct ums {
int (*read_sector)(struct ums *ums_dev,
ulong start, lbaint_t blkcnt, void *buf);
return SZ_ERROR_OUTPUT_EOF;
/* Decompress */
- outProcessed = *uncompressedSize;
+ outProcessed = outSizeFull;
WATCHDOG_RESET();
inStream + LZMA_DATA_OFFSET, &compressedSize,
inStream, LZMA_PROPS_SIZE, LZMA_FINISH_END, &state, &g_Alloc);
*uncompressedSize = outProcessed;
+
+ debug("LZMA: Uncompresed ................ 0x%zx\n", outProcessed);
+
if (res != SZ_OK) {
return res;
}
return tick;
}
+int __weak timer_init(void)
+{
+ return 0;
+}
+
ulong __weak get_timer(ulong base)
{
return tick_to_time(get_ticks()) - base;
ADDCH(str, '\0');
if (str > end)
end[-1] = '\0';
+ --str;
}
#else
*str = '\0';
LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ \
drivers/power/pmic/
LIBS-$(if $(CONFIG_CMD_NAND),$(CONFIG_SPL_NAND_SUPPORT)) += drivers/mtd/nand/
+LIBS-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/
LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/
LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/
LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/
LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/
LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/
LIBS-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/
+LIBS-$(CONFIG_SPL_USB_HOST_SUPPORT) += drivers/usb/host/
+LIBS-$(CONFIG_OMAP_USB_PHY) += drivers/usb/phy/
ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
LIBS-y += arch/$(ARCH)/imx-common/
endif
$(obj)$(SPL_BIN).bin: $(obj)$(SPL_BIN)
- $(OBJCOPY) $(OBJCFLAGS) -O binary $< $@
+ $(OBJCOPY) $(OBJCFLAGS) $(SPL_OBJCFLAGS) -O binary $< $@
GEN_UBOOT = \
cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $(__START) \
/mxsboot
/ncb
/proftool
+/relocate-rela
/ubsha1
/xway-swap-bytes
/*.exe
This directory contains scripts that help to perform certain actions
that need to be done frequently when working with U-Boot.
-They are meant as EXAMPLE code, so it is very likely that you will
+They are meant as EXAMPLE code, so it is very likely that you will
have to modify them before use.
projects / platform / kernel / u-boot.git / commitdiff