tuge1 MPC8321
tuxx1 MPC8321
-Cyril Chemparathy <cyril@ti.com>
-
- tnetv107x_evm tnetv107x
-
Conn Clark <clark@esteem.com>
ESTEEM192E MPC8xx
Matthias Fuchs <matthias.fuchs@esd-electronics.com>
- ADCIOP IOP480 (PPC401)
APC405 PPC405GP
AR405 PPC405GP
ASH405 PPC405EP
CPCI405AB PPC405GP
CPCI405DT PPC405GP
CPCIISER4 PPC405GP
- DASA_SIM IOP480 (PPC401)
DP405 PPC405EP
DU405 PPC405GP
DU440 PPC440EPx
KUP4K MPC855
KUP4X MPC859
+Gabriel Huau <contact@huau-gabriel.fr>
+
+ mini2440 s3c2440
+
Gary Jennejohn <garyj@denx.de>
quad100hd PPC405EP
ep8260 MPC8260
+Chan-Taek Park <c-park@ti.com>
+
+ tnetv107x_evm tnetv107x
+
Denis Peter <d.peter@mpl.ch>
MIP405 PPC4xx
uc100 MPC857
- TQM85xx MPC8540/8541/8555/8560
-
acadia PPC405EZ
alpr PPC440GX
bamboo PPC440EP
uc101 MPC5200
ve8313 MPC8313
-Peter De Schrijver <p2@mind.be>
-
- ML2 PPC4xx
-
Andre Schwarz <andre.schwarz@matrix-vision.de>
mergerbox MPC8377
mx31pdk i.MX31
mx53ard i.MX53
mx53smd i.MX53
+ mx6qsabresd i.MX6Q
+ mx6qsabreauto i.MX6Q
Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
SMDKV310 ARM ARMV7 (EXYNOS4210 SoC)
SMDK5250 ARM ARMV7 (EXYNOS5250 SoC)
-Heungjun Kim <riverful.kim@samsung.com>
+Lukasz Majewski <l.majewski@samsung.com>
trats ARM ARMV7 (EXYNOS4210 SoC)
am3517_crane ARM ARMV7 (AM35x SoC)
+Dinh Nguyen <dinguyen@altera.com>
+Chin Liang See <clsee@altera.com>
+
+ socfpga socfpga_cyclone5
+
Sandeep Paulraj <s-paulraj@ti.com>
davinci_dm355evm ARM926EJS
Luka Perkov <uboot@lukaperkov.net>
ib62x0 ARM926EJS
+ iconnect ARM926EJS
Dave Peverley <dpeverley@mpc-data.co.uk>
Thierry Reding <thierry.reding@avionic-design.de>
plutux Tegra20 (ARM7 & A9 Dual Core)
- medcom Tegra20 (ARM7 & A9 Dual Core)
+ medcom-wide Tegra20 (ARM7 & A9 Dual Core)
tec Tegra20 (ARM7 & A9 Dual Core)
Christian Riesch <christian.riesch@omicron.at>
Stefan Roese <sr@denx.de>
+ x600 ARM926EJS (spear600 Soc)
+
pdnb3 xscale/ixp
scpu xscale/ixp
Bo Shen <voice.shen@atmel.com>
at91sam9x5ek ARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC)
+Michal Simek <monstr@monstr.eu>
+
+ zynq ARM ARMV7 (Zynq SoC)
+
Nick Thompson <nick.thompson@gefanuc.com>
da830evm ARM926EJS (DA830/OMAP-L137)
SMDK6400 ARM1176 (S3C6400 SoC)
+Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Tetsuyuki Kobayashi <koba@kmckk.co.jp>
+
+ kzm9g SH73A0 (RMOBILE SoC)
+
+Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+
+ armadillo-800eva R8A7740 (RMOBILE SoC)
+
-------------------------------------------------------------------------
Unknown / orphaned boards:
- Board CPU Last known maintainer / Comment
+ Board CPU Last known maintainer / Comment
.........................................................................
omap1510inn ARM925T Kshitij Gupta <kshitij@ti.com>
incaip MIPS32 4Kc
-Thomas Lange <thomas@corelatus.se>
- dbau1x00 MIPS32 Au1000
- gth2 MIPS32 Au1000
-
Vlad Lungu <vlad.lungu@windriver.com>
qemu_mips MIPS32
qi_lb60 MIPS32 (XBurst Jz4740 SoC)
+-------------------------------------------------------------------------
+
+Unknown / orphaned boards:
+ Board CPU Last known maintainer / Comment
+.........................................................................
+
+ dbau1x00 MIPS32 Au1000 Thomas Lange <thomas@corelatus.se>
+
#########################################################################
# Nios-II Systems: #
# #
-l, --list List all targets to be built
-m, --maintainers List all targets and maintainer email
-M, --mails List all targets and all affilated emails
+ -C, --check Enable build checking
-h, --help This help output
Selections by these options are logically ANDed; if the same option
exit ${ret}
}
-SHORT_OPTS="ha:c:v:s:lmM"
-LONG_OPTS="help,arch:,cpu:,vendor:,soc:,list,maintainers,mails"
+SHORT_OPTS="ha:c:v:s:lmMC"
+LONG_OPTS="help,arch:,cpu:,vendor:,soc:,list,maintainers,mails,check"
# Option processing based on util-linux-2.13/getopt-parse.bash
fi
SELECTED='y'
shift 2 ;;
+ -C|--check)
+ CHECK='C=1'
+ shift ;;
-l|--list)
ONLY_LIST='y'
shift ;;
dbau1100 \
dbau1500 \
dbau1550 \
- gth2 \
"
LIST_mips=" \
${MAKE} distclean >/dev/null
${MAKE} -s ${target}_config
- ${MAKE} ${JOBS} all \
+ ${MAKE} ${JOBS} ${CHECK} all \
>${LOG_DIR}/$target.MAKELOG 2> ${LOG_DIR}/$target.ERR
# Check for 'make' errors
VERSION = 2012
PATCHLEVEL = 10
SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION =
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
endif
endif
+# Call a source code checker (by default, "sparse") as part of the
+# C compilation.
+#
+# Use 'make C=1' to enable checking of re-compiled files.
+#
+# See the linux kernel file "Documentation/sparse.txt" for more details,
+# including where to get the "sparse" utility.
+
+ifdef C
+ifeq ("$(origin C)", "command line")
+CHECKSRC := $(C)
+endif
+endif
+ifndef CHECKSRC
+ CHECKSRC = 0
+endif
+export CHECKSRC
+
ifneq ($(BUILD_DIR),)
saved-output := $(BUILD_DIR)
endif
ifeq ($(SOC),tegra20)
LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
+LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
+LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o
endif
LIBS := $(addprefix $(obj),$(sort $(LIBS-y)))
$(MAKE) -C tools/$@ all MTD_VERSION=${MTD_VERSION}
gdbtools: gdb
+xmldocs pdfdocs psdocs htmldocs mandocs: tools/kernel-doc/docproc
+ $(MAKE) U_BOOT_VERSION=$(U_BOOT_VERSION) -C doc/DocBook/ $@
+
tools-all: easylogo env gdb $(VERSION_FILE) $(TIMESTAMP_FILE)
$(MAKE) -C tools HOST_TOOLS_ALL=y
$(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \
$(obj)tools/mk{smdk5250,}spl \
$(obj)tools/mxsboot \
- $(obj)tools/ncb $(obj)tools/ubsha1
+ $(obj)tools/ncb $(obj)tools/ubsha1 \
+ $(obj)tools/kernel-doc/docproc
@rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image} \
$(obj)board/matrix_vision/*/bootscript.img \
$(obj)board/voiceblue/eeprom \
@rm -f $(obj)include/generated/asm-offsets.h
@rm -f $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
+ @$(MAKE) -C doc/DocBook/ cleandocs
@find $(OBJTREE) -type f \
\( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \
-o -name '*.o' -o -name '*.a' -o -name '*.exe' \) -print \
- Boot Delay: CONFIG_BOOTDELAY - in seconds
Delay before automatically booting the default image;
set to -1 to disable autoboot.
+ set to -2 to autoboot with no delay and not check for abort
+ (even when CONFIG_ZERO_BOOTDELAY_CHECK is defined).
See doc/README.autoboot for these options that
work with CONFIG_BOOTDELAY. None are required.
CONFIG_CMD_IMLS List all found images
CONFIG_CMD_IMMAP * IMMR dump support
CONFIG_CMD_IMPORTENV * import an environment
+ CONFIG_CMD_INI * import data from an ini file into the env
CONFIG_CMD_IRQ * irqinfo
CONFIG_CMD_ITEST Integer/string test of 2 values
CONFIG_CMD_JFFS2 * JFFS2 Support
CONFIG_CMD_SPI * SPI serial bus support
CONFIG_CMD_TFTPSRV * TFTP transfer in server mode
CONFIG_CMD_TFTPPUT * TFTP put command (upload)
- CONFIG_CMD_TIME * run command and report execution time
+ CONFIG_CMD_TIME * run command and report execution time (ARM specific)
+ CONFIG_CMD_TIMER * access to the system tick timer
CONFIG_CMD_USB * USB support
CONFIG_CMD_CDP * Cisco Discover Protocol support
CONFIG_CMD_MFSL * Microblaze FSL support
viewport is supported.
To enable the ULPI layer support, define CONFIG_USB_ULPI and
CONFIG_USB_ULPI_VIEWPORT in your board configuration file.
+ If your ULPI phy needs a different reference clock than the
+ standard 24 MHz then you have to define CONFIG_ULPI_REF_CLK to
+ the appropriate value in Hz.
- MMC Support:
The MMC controller on the Intel PXA is supported. To
consider minicom to be broken, and recommend not to use it. Under
Unix, I recommend to use C-Kermit for general purpose use (and
especially for kermit binary protocol download ("loadb" command), and
-use "cu" for S-Record download ("loads" command).
+use "cu" for S-Record download ("loads" command). See
+http://www.denx.de/wiki/view/DULG/SystemSetup#Section_4.3.
+for help with kermit.
+
Nevertheless, if you absolutely want to use it try adding this
configuration to your "File transfer protocols" section:
ifndef CONFIG_NAND_SPL
LDFLAGS_u-boot += -pie
endif
+
+#
+# FIXME: binutils versions < 2.22 have a bug in the assembler where
+# branches to weak symbols can be incorrectly optimized in thumb mode
+# to a short branch (b.n instruction) that won't reach when the symbol
+# gets preempted
+#
+# http://sourceware.org/bugzilla/show_bug.cgi?id=12532
+#
+ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
+ifeq ($(GAS_BUG_12532),)
+export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \
+ then echo y; else echo n; fi)
+endif
+ifeq ($(GAS_BUG_12532),y)
+PLATFORM_RELFLAGS += -fno-optimize-sibling-calls
+endif
+endif
case MXC_CSPI_CLK:
case MXC_UART_CLK:
case MXC_ESDHC_CLK:
+ case MXC_I2C_CLK:
return mx31_get_ipg_clk();
case MXC_IPU_CLK:
return mx31_get_hsp_clk();
int main(void)
{
-
/* Round up to make sure size gives nice stack alignment */
DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
+ DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
+
+ /* Multi-Layer AHB Crossbar Switch */
+ DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
+ DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
+ DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
+ DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
+ DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
+ DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
+ DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
+ DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
+ DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
+ DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
+ DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
+ DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
+ DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
+ DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
+ DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
+ DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
+
+ /* AHB <-> IP-Bus Interface */
+ DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
+ DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
+ DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
+ DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
+ DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
+ DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
+ DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
+ DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
+ DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
+ DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
+ DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
return 0;
}
case MXC_IPG_CLK:
return get_ipg_clk();
case MXC_IPG_PERCLK:
+ case MXC_I2C_CLK:
return get_ipg_per_clk();
case MXC_UART_CLK:
return imx_get_uartclk();
adr r0, _start
cmp r0, r6
+ moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
adr r0, _start
cmp r0, r6
+ moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
--- /dev/null
+#
+# (C) Copyright 2010,2011 Nvidia Corporation.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)libtegra-common.o
+
+COBJS-$(CONFIG_SPL_BUILD) += spl.o
+
+SRCS := $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
#include <common.h>
#include <asm/u-boot.h>
#include <asm/utils.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/clock.h>
#include <nand.h>
#include <mmc.h>
#include <fat.h>
#include <image.h>
#include <malloc.h>
#include <linux/compiler.h>
-#include "board.h"
#include "cpu.h"
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
-#include <asm/arch/pmc.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/scu.h>
-#include <common.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/scu.h>
+#include <asm/arch-tegra/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
board_init_uart_f();
/* Initialize periph GPIOs */
-#ifdef CONFIG_SPI_UART_SWITCH
gpio_early_init_uart();
-#else
- gpio_config_uart();
-#endif
/*
* We call relocate_code() with relocation target same as the
LIB = $(obj)lib$(SOC).o
COBJS-y += cpu.o
-COBJS-$(CONFIG_SPL_BUILD) += spl.o
SRCS := $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
* MA 02111-1307 USA
*/
+#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
-#include <asm/arch/pmc.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/scu.h>
-#include <common.h>
-#include "cpu.h"
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/scu.h>
+#include "../tegra-common/cpu.h"
/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
int ap20_cpu_is_cortexa9(void)
*/
static char ohci_inited = 0;
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
return 0;
}
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
adr r0, _start
cmp r0, r6
+ moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
adr r0, _start
cmp r0, r6
+ moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
DECLARE_GLOBAL_DATA_PTR;
-#define KW_REG_CPUCS_WIN_BAR(x) (KW_REGISTER(0x1500) + (x * 0x08))
-#define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + (x * 0x08))
+struct kw_sdram_bank {
+ u32 win_bar;
+ u32 win_sz;
+};
+
+struct kw_sdram_addr_dec {
+ struct kw_sdram_bank sdram_bank[4];
+};
+
+#define KW_REG_CPUCS_WIN_ENABLE (1 << 0)
+#define KW_REG_CPUCS_WIN_WR_PROTECT (1 << 1)
+#define KW_REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
+#define KW_REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
+
/*
* kw_sdram_bar - reads SDRAM Base Address Register
*/
u32 kw_sdram_bar(enum memory_bank bank)
{
+ struct kw_sdram_addr_dec *base =
+ (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
u32 result = 0;
- u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
+ u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
if ((!enable) || (bank > BANK3))
return 0;
- result = readl(KW_REG_CPUCS_WIN_BAR(bank));
+ result = readl(&base->sdram_bank[bank].win_bar);
return result;
}
/*
+ * kw_sdram_bs_set - writes SDRAM Bank size
+ */
+static void kw_sdram_bs_set(enum memory_bank bank, u32 size)
+{
+ struct kw_sdram_addr_dec *base =
+ (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
+ /* Read current register value */
+ u32 reg = readl(&base->sdram_bank[bank].win_sz);
+
+ /* Clear window size */
+ reg &= ~KW_REG_CPUCS_WIN_SIZE(0xFF);
+
+ /* Set new window size */
+ reg |= KW_REG_CPUCS_WIN_SIZE((size - 1) >> 24);
+
+ writel(reg, &base->sdram_bank[bank].win_sz);
+}
+
+/*
* kw_sdram_bs - reads SDRAM Bank size
*/
u32 kw_sdram_bs(enum memory_bank bank)
{
+ struct kw_sdram_addr_dec *base =
+ (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
u32 result = 0;
- u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
+ u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
if ((!enable) || (bank > BANK3))
return 0;
- result = 0xff000000 & readl(KW_REG_CPUCS_WIN_SZ(bank));
+ result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
result += 0x01000000;
return result;
}
+void kw_sdram_size_adjust(enum memory_bank bank)
+{
+ u32 size;
+
+ /* probe currently equipped RAM size */
+ size = get_ram_size((void *)kw_sdram_bar(bank), kw_sdram_bs(bank));
+
+ /* adjust SDRAM window size accordingly */
+ kw_sdram_bs_set(bank, size);
+}
+
#ifndef CONFIG_SYS_BOARD_DRAM_INIT
int dram_init(void)
{
#include <asm/arch/imx-regs.h>
#include <asm/arch/imx25-pinmux.h>
#include <asm/arch/clock.h>
-#ifdef CONFIG_MXC_MMC
-#include <asm/arch/mxcmmc.h>
-#endif
#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+
DECLARE_GLOBAL_DATA_PTR;
#endif
{
unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
& CCM_PLL_MFI_MASK;
- unsigned int mfn = (pll >> CCM_PLL_MFN_SHIFT)
+ int mfn = (pll >> CCM_PLL_MFN_SHIFT)
& CCM_PLL_MFN_MASK;
unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
& CCM_PLL_MFD_MASK;
& CCM_PLL_PD_MASK;
mfi = mfi <= 5 ? 5 : mfi;
+ mfn = mfn >= 512 ? mfn - 1024 : mfn;
+ mfd += 1;
+ pd += 1;
- return lldiv(2 * (u64) f_ref * (mfi * (mfd + 1) + mfn),
- (mfd + 1) * (pd + 1));
+ return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
+ mfd * pd);
}
static ulong imx_get_mpllclk(void)
return imx_decode_pll(readl(&ccm->mpctl), fref);
}
-ulong imx_get_armclk(void)
+static ulong imx_get_armclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong cctl = readl(&ccm->cctl);
ulong div;
if (cctl & CCM_CCTL_ARM_SRC)
- fref = lldiv((fref * 3), 4);
+ fref = lldiv((u64) fref * 3, 4);
div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
& CCM_CCTL_ARM_DIV_MASK) + 1;
- return lldiv(fref, div);
+ return fref / div;
}
-ulong imx_get_ahbclk(void)
+static ulong imx_get_ahbclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong cctl = readl(&ccm->cctl);
div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
& CCM_CCTL_AHB_DIV_MASK) + 1;
- return lldiv(fref, div);
+ return fref / div;
+}
+
+static ulong imx_get_ipgclk(void)
+{
+ return imx_get_ahbclk() / 2;
}
-ulong imx_get_perclk(int clk)
+static ulong imx_get_perclk(int clk)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong fref = imx_get_ahbclk();
div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
- return lldiv(fref, div);
+ return fref / div;
}
unsigned int mxc_get_clock(enum mxc_clock clk)
switch (clk) {
case MXC_ARM_CLK:
return imx_get_armclk();
- case MXC_FEC_CLK:
+ case MXC_AHB_CLK:
return imx_get_ahbclk();
+ case MXC_IPG_CLK:
+ case MXC_CSPI_CLK:
+ case MXC_FEC_CLK:
+ return imx_get_ipgclk();
default:
return imx_get_perclk(clk);
}
case 0x01:
system_rev |= CHIP_REV_1_1;
break;
+ case 0x02:
+ system_rev |= CHIP_REV_1_2;
+ break;
default:
system_rev |= 0x8000;
break;
#endif
}
+#if defined(CONFIG_FEC_MXC)
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
int cpu_eth_init(bd_t *bis)
{
-#if defined(CONFIG_FEC_MXC)
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong val;
val |= (1 << 23);
writel(val, &ccm->cgr0);
return fecmxc_initialize(bis);
-#else
- return 0;
-#endif
}
+#endif
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#else
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+#endif
#endif
return 0;
}
+#ifdef CONFIG_FSL_ESDHC
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(bd_t *bis)
{
-#ifdef CONFIG_MXC_MMC
- return mxc_mmc_init(bis);
-#else
- return 0;
-#endif
+ return fsl_esdhc_mmc_init(bis);
}
+#endif
#ifdef CONFIG_MXC_UART
void mx25_uart1_init_pins(void)
;
}
-#ifndef CONFIG_SPL_SERIAL_SUPPORT
-void serial_putc(const char c) {}
-void serial_puts(const char *s) {}
-#endif
void hang(void) __attribute__ ((noreturn));
void hang(void)
{
*/
int print_cpuinfo(void)
{
- char dev_str[] = "0x0000";
- char rev_str[] = "0x00";
+ char dev_str[7]; /* room enough for 0x0000 plus null byte */
+ char rev_str[5]; /* room enough for 0x00 plus null byte */
char *dev_name = NULL;
char *rev_name = NULL;
adr r0, _start
sub r9, r6, r0 /* r9 <- relocation offset */
cmp r0, r6
+ moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy loop */
ldr r3, _bss_start_ofs
adr r0, _start
cmp r0, r6
+ moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
adr r0, _start
cmp r0, r6
+ moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
# =========================================================================
PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
+
+# SEE README.arm-unaligned-accesses
+PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
+PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
+
ifneq ($(CONFIG_IMX_CONFIG),)
ALL-y += $(obj)u-boot.imx
endif
+++ /dev/null
-PLATFORM_CPPFLAGS += -march=armv7-a
PLL1_CLOCK = 0,
PLL2_CLOCK,
PLL3_CLOCK,
+#ifdef CONFIG_MX53
PLL4_CLOCK,
+#endif
PLL_CLOCKS,
};
};
const struct fixed_pll_mfd fixed_mfd[] = {
- {CONFIG_SYS_MX5_HCLK, 24 * 16},
+ {MXC_HCLK, 24 * 16},
};
struct pll_param {
void set_usboh3_clk(void)
{
- unsigned int reg;
-
- reg = readl(&mxc_ccm->cscmr1) &
- ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
- reg |= 1 << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
- writel(reg, &mxc_ccm->cscmr1);
-
- reg = readl(&mxc_ccm->cscdr1);
- reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
- reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
- reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
- reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
-
- writel(reg, &mxc_ccm->cscdr1);
+ clrsetbits_le32(&mxc_ccm->cscmr1,
+ MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
+ MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
+ clrsetbits_le32(&mxc_ccm->cscdr1,
+ MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
+ MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
+ MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
+ MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
}
void enable_usboh3_clk(unsigned char enable)
{
- unsigned int reg;
+ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
- reg = readl(&mxc_ccm->CCGR2);
- if (enable)
- reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET;
- else
- reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET);
- writel(reg, &mxc_ccm->CCGR2);
+ clrsetbits_le32(&mxc_ccm->CCGR2,
+ MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
+ MXC_CCM_CCGR2_USBOH3_60M(cg));
}
#ifdef CONFIG_I2C_MXC
-/* i2c_num can be from 0 - 2 */
+/* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
{
- u32 reg;
u32 mask;
+#if defined(CONFIG_MX51)
+ if (i2c_num > 1)
+#elif defined(CONFIG_MX53)
if (i2c_num > 2)
+#endif
return -EINVAL;
- mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 9) << 1);
- reg = __raw_readl(&mxc_ccm->CCGR1);
+ mask = MXC_CCM_CCGR_CG_MASK <<
+ (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
if (enable)
- reg |= mask;
+ setbits_le32(&mxc_ccm->CCGR1, mask);
else
- reg &= ~mask;
- __raw_writel(reg, &mxc_ccm->CCGR1);
+ clrbits_le32(&mxc_ccm->CCGR1, mask);
return 0;
}
#endif
-void set_usb_phy1_clk(void)
+void set_usb_phy_clk(void)
{
- unsigned int reg;
-
- reg = readl(&mxc_ccm->cscmr1);
- reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
- writel(reg, &mxc_ccm->cscmr1);
+ clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
}
+#if defined(CONFIG_MX51)
void enable_usb_phy1_clk(unsigned char enable)
{
- unsigned int reg;
+ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
- reg = readl(&mxc_ccm->CCGR4);
- if (enable)
- reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET;
- else
- reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET);
- writel(reg, &mxc_ccm->CCGR4);
+ clrsetbits_le32(&mxc_ccm->CCGR2,
+ MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
+ MXC_CCM_CCGR2_USB_PHY(cg));
}
-void set_usb_phy2_clk(void)
+void enable_usb_phy2_clk(unsigned char enable)
{
- unsigned int reg;
+ /* i.MX51 has a single USB PHY clock, so do nothing here. */
+}
+#elif defined(CONFIG_MX53)
+void enable_usb_phy1_clk(unsigned char enable)
+{
+ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
- reg = readl(&mxc_ccm->cscmr1);
- reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
- writel(reg, &mxc_ccm->cscmr1);
+ clrsetbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
+ MXC_CCM_CCGR4_USB_PHY1(cg));
}
void enable_usb_phy2_clk(unsigned char enable)
{
- unsigned int reg;
+ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
- reg = readl(&mxc_ccm->CCGR4);
- if (enable)
- reg |= 1 << MXC_CCM_CCGR4_CG6_OFFSET;
- else
- reg &= ~(1 << MXC_CCM_CCGR4_CG6_OFFSET);
- writel(reg, &mxc_ccm->CCGR4);
+ clrsetbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
+ MXC_CCM_CCGR4_USB_PHY2(cg));
}
+#endif
/*
* Calculate the frequency of PLLn.
ctrl = readl(&pll->ctrl);
if (ctrl & MXC_DPLLC_CTL_HFSM) {
- mfn = __raw_readl(&pll->hfs_mfn);
- mfd = __raw_readl(&pll->hfs_mfd);
- op = __raw_readl(&pll->hfs_op);
+ mfn = readl(&pll->hfs_mfn);
+ mfd = readl(&pll->hfs_mfd);
+ op = readl(&pll->hfs_op);
} else {
- mfn = __raw_readl(&pll->mfn);
- mfd = __raw_readl(&pll->mfd);
- op = __raw_readl(&pll->op);
+ mfn = readl(&pll->mfn);
+ mfd = readl(&pll->mfd);
+ op = readl(&pll->op);
}
mfd &= MXC_DPLLC_MFD_MFD_MASK;
mfn &= MXC_DPLLC_MFN_MFN_MASK;
pdf = op & MXC_DPLLC_OP_PDF_MASK;
- mfi = (op & MXC_DPLLC_OP_MFI_MASK) >> MXC_DPLLC_OP_MFI_OFFSET;
+ mfi = MXC_DPLLC_OP_MFI_RD(op);
/* 21.2.3 */
if (mfi < 5)
return ret;
}
+#ifdef CONFIG_MX51
+/*
+ * This function returns the Frequency Pre-Multiplier clock.
+ */
+static u32 get_fpm(void)
+{
+ u32 mult;
+ u32 ccr = readl(&mxc_ccm->ccr);
+
+ if (ccr & MXC_CCM_CCR_FPM_MULT)
+ mult = 1024;
+ else
+ mult = 512;
+
+ return MXC_CLK32 * mult;
+}
+#endif
+
+/*
+ * This function returns the low power audio clock.
+ */
+static u32 get_lp_apm(void)
+{
+ u32 ret_val = 0;
+ u32 ccsr = readl(&mxc_ccm->ccsr);
+
+ if (ccsr & MXC_CCM_CCSR_LP_APM)
+#if defined(CONFIG_MX51)
+ ret_val = get_fpm();
+#elif defined(CONFIG_MX53)
+ ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
+#endif
+ else
+ ret_val = MXC_HCLK;
+
+ return ret_val;
+}
+
/*
* Get mcu main rate
*/
{
u32 reg, freq;
- reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
- MXC_CCM_CACRR_ARM_PODF_OFFSET;
- freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+ reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
+ freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
return freq / (reg + 1);
}
{
u32 reg;
- reg = __raw_readl(&mxc_ccm->cbcdr);
+ reg = readl(&mxc_ccm->cbcdr);
if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
- return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
- reg = __raw_readl(&mxc_ccm->cbcmr);
- switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
- MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
+ return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
+ reg = readl(&mxc_ccm->cbcmr);
+ switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
case 0:
- return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+ return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
case 1:
- return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
+ return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
+ case 2:
+ return get_lp_apm();
default:
return 0;
}
freq = get_ahb_clk();
- reg = __raw_readl(&mxc_ccm->cbcdr);
- div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
- MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
+ reg = readl(&mxc_ccm->cbcdr);
+ div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
return freq / div;
}
*/
static u32 get_ipg_per_clk(void)
{
- u32 pred1, pred2, podf;
+ u32 freq, pred1, pred2, podf;
- if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
+ if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
return get_ipg_clk();
- /* Fixme: not handle what about lpm*/
- podf = __raw_readl(&mxc_ccm->cbcdr);
- pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
- MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
- pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
- MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
- podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
- MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
- return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
+ if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL)
+ freq = get_lp_apm();
+ else
+ freq = get_periph_clk();
+ podf = readl(&mxc_ccm->cbcdr);
+ pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
+ pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
+ podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
+ return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
}
-/*
- * Get the rate of uart clk.
- */
-static u32 get_uart_clk(void)
+/* Get the output clock rate of a standard PLL MUX for peripherals. */
+static u32 get_standard_pll_sel_clk(u32 clk_sel)
{
- unsigned int freq, reg, pred, podf;
+ u32 freq;
- reg = __raw_readl(&mxc_ccm->cscmr1);
- switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
- MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
- case 0x0:
- freq = decode_pll(mxc_plls[PLL1_CLOCK],
- CONFIG_SYS_MX5_HCLK);
+ switch (clk_sel & 0x3) {
+ case 0:
+ freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
+ break;
+ case 1:
+ freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
break;
- case 0x1:
- freq = decode_pll(mxc_plls[PLL2_CLOCK],
- CONFIG_SYS_MX5_HCLK);
+ case 2:
+ freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
break;
- case 0x2:
- freq = decode_pll(mxc_plls[PLL3_CLOCK],
- CONFIG_SYS_MX5_HCLK);
+ case 3:
+ freq = get_lp_apm();
break;
- default:
- return 66500000;
}
- reg = __raw_readl(&mxc_ccm->cscdr1);
+ return freq;
+}
+
+/*
+ * Get the rate of uart clk.
+ */
+static u32 get_uart_clk(void)
+{
+ unsigned int clk_sel, freq, reg, pred, podf;
- pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
- MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
+ reg = readl(&mxc_ccm->cscmr1);
+ clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);
+ freq = get_standard_pll_sel_clk(clk_sel);
- podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
- MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
+ reg = readl(&mxc_ccm->cscdr1);
+ pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
+ podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
freq /= (pred + 1) * (podf + 1);
return freq;
}
/*
- * This function returns the low power audio clock.
+ * get cspi clock rate.
*/
-static u32 get_lp_apm(void)
+static u32 imx_get_cspiclk(void)
{
- u32 ret_val = 0;
- u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
-
- if (((ccsr >> 9) & 1) == 0)
- ret_val = CONFIG_SYS_MX5_HCLK;
- else
- ret_val = ((32768 * 1024));
+ u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
+ u32 cscmr1 = readl(&mxc_ccm->cscmr1);
+ u32 cscdr2 = readl(&mxc_ccm->cscdr2);
+ pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
+ pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
+ clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
+ freq = get_standard_pll_sel_clk(clk_sel);
+ ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
return ret_val;
}
/*
- * get cspi clock rate.
+ * get esdhc clock rate.
*/
-static u32 imx_get_cspiclk(void)
+static u32 get_esdhc_clk(u32 port)
{
- u32 ret_val = 0, pdf, pre_pdf, clk_sel;
- u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
- u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
+ u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
+ u32 cscmr1 = readl(&mxc_ccm->cscmr1);
+ u32 cscdr1 = readl(&mxc_ccm->cscdr1);
- pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
- >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
- pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
- >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
- clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
- >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
-
- switch (clk_sel) {
+ switch (port) {
case 0:
- ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
- CONFIG_SYS_MX5_HCLK) /
- ((pre_pdf + 1) * (pdf + 1));
+ clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
+ pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1);
+ podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1);
break;
case 1:
- ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
- CONFIG_SYS_MX5_HCLK) /
- ((pre_pdf + 1) * (pdf + 1));
+ clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
+ pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1);
+ podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1);
break;
case 2:
- ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
- CONFIG_SYS_MX5_HCLK) /
- ((pre_pdf + 1) * (pdf + 1));
- break;
+ if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
+ return get_esdhc_clk(1);
+ else
+ return get_esdhc_clk(0);
+ case 3:
+ if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
+ return get_esdhc_clk(1);
+ else
+ return get_esdhc_clk(0);
default:
- ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
break;
}
- return ret_val;
+ freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
+ return freq;
}
static u32 get_axi_a_clk(void)
{
- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \
- >> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
+ u32 cbcdr = readl(&mxc_ccm->cbcdr);
+ u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
return get_periph_clk() / (pdf + 1);
}
static u32 get_axi_b_clk(void)
{
- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \
- >> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
+ u32 cbcdr = readl(&mxc_ccm->cbcdr);
+ u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
return get_periph_clk() / (pdf + 1);
}
static u32 get_emi_slow_clk(void)
{
- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+ u32 cbcdr = readl(&mxc_ccm->cbcdr);
u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \
- >> MXC_CCM_CBCDR_EMI_PODF_OFFSET;
+ u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
if (emi_clk_sel)
return get_ahb_clk() / (pdf + 1);
static u32 get_ddr_clk(void)
{
u32 ret_val = 0;
- u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
- u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \
- >> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
+ u32 cbcmr = readl(&mxc_ccm->cbcmr);
+ u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
#ifdef CONFIG_MX51
- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+ u32 cbcdr = readl(&mxc_ccm->cbcdr);
if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
- u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \
- MXC_CCM_CBCDR_DDR_PODF_OFFSET;
+ u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
- ret_val = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+ ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
ret_val /= ddr_clk_podf + 1;
return ret_val;
case MXC_IPG_CLK:
return get_ipg_clk();
case MXC_IPG_PERCLK:
+ case MXC_I2C_CLK:
return get_ipg_per_clk();
case MXC_UART_CLK:
return get_uart_clk();
case MXC_CSPI_CLK:
return imx_get_cspiclk();
+ case MXC_ESDHC_CLK:
+ return get_esdhc_clk(0);
+ case MXC_ESDHC2_CLK:
+ return get_esdhc_clk(1);
+ case MXC_ESDHC3_CLK:
+ return get_esdhc_clk(2);
+ case MXC_ESDHC4_CLK:
+ return get_esdhc_clk(3);
case MXC_FEC_CLK:
- return decode_pll(mxc_plls[PLL1_CLOCK],
- CONFIG_SYS_MX5_HCLK);
+ return get_ipg_clk();
case MXC_SATA_CLK:
return get_ahb_clk();
case MXC_DDR_CLK:
return get_uart_clk();
}
-
u32 imx_get_fecclk(void)
{
- return mxc_get_clock(MXC_IPG_CLK);
+ return get_ipg_clk();
}
static int gcd(int m, int n)
#define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
{ \
- __raw_writel(0x1232, &pll->ctrl); \
- __raw_writel(0x2, &pll->config); \
- __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
- &pll->op); \
- __raw_writel(fn, &(pll->mfn)); \
- __raw_writel((fd) - 1, &pll->mfd); \
- __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
- &pll->hfs_op); \
- __raw_writel(fn, &pll->hfs_mfn); \
- __raw_writel((fd) - 1, &pll->hfs_mfd); \
- __raw_writel(0x1232, &pll->ctrl); \
- while (!__raw_readl(&pll->ctrl) & 0x1) \
+ writel(0x1232, &pll->ctrl); \
+ writel(0x2, &pll->config); \
+ writel((((pd) - 1) << 0) | ((fi) << 4), \
+ &pll->op); \
+ writel(fn, &(pll->mfn)); \
+ writel((fd) - 1, &pll->mfd); \
+ writel((((pd) - 1) << 0) | ((fi) << 4), \
+ &pll->hfs_op); \
+ writel(fn, &pll->hfs_mfn); \
+ writel((fd) - 1, &pll->hfs_mfd); \
+ writel(0x1232, &pll->ctrl); \
+ while (!readl(&pll->ctrl) & 0x1) \
;\
}
static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
{
- u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
+ u32 ccsr = readl(&mxc_ccm->ccsr);
struct mxc_pll_reg *pll = mxc_plls[index];
switch (index) {
case PLL1_CLOCK:
/* Switch ARM to PLL2 clock */
- __raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
+ writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
- __raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
+ writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
break;
case PLL2_CLOCK:
/* Switch to pll2 bypass clock */
- __raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
+ writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
- __raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
+ writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
break;
case PLL3_CLOCK:
/* Switch to pll3 bypass clock */
- __raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
+ writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
- __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
+ writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
break;
+#ifdef CONFIG_MX53
case PLL4_CLOCK:
/* Switch to pll4 bypass clock */
- __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
+ writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
- __raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
+ writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
break;
+#endif
default:
return -EINVAL;
}
static int config_nfc_clk(u32 nfc_clk)
{
- u32 reg;
u32 parent_rate = get_emi_slow_clk();
u32 div = parent_rate / nfc_clk;
div++;
if (parent_rate / div > NFC_CLK_MAX)
div++;
- reg = __raw_readl(&mxc_ccm->cbcdr);
- reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
- reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
- __raw_writel(reg, &mxc_ccm->cbcdr);
- while (__raw_readl(&mxc_ccm->cdhipr) != 0)
+ clrsetbits_le32(&mxc_ccm->cbcdr,
+ MXC_CCM_CBCDR_NFC_PODF_MASK,
+ MXC_CCM_CBCDR_NFC_PODF(div - 1));
+ while (readl(&mxc_ccm->cdhipr) != 0)
;
return 0;
}
memset(&pll_param, 0, sizeof(struct pll_param));
- if (__raw_readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+ if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
ret = calc_pll_params(ref, freq, &pll_param);
if (ret != 0) {
printf("Error:Can't find pll parameters: %d\n",
ret);
return ret;
}
- switch ((__raw_readl(&mxc_ccm->cbcmr) & \
- MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> \
- MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
+ switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
+ readl(&mxc_ccm->cbcmr))) {
case 0:
return config_pll_clk(PLL1_CLOCK, &pll_param);
break;
{
u32 clk_src;
s32 shift = 0, clk_sel, div = 1;
- u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+ u32 cbcmr = readl(&mxc_ccm->cbcmr);
if (emi_clk > MAX_DDR_CLK) {
printf("Warning:DDR clock should not exceed %d MHz\n",
clk_src = get_periph_clk();
/* Find DDR clock input */
- clk_sel = (cbcmr >> 10) & 0x3;
+ clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
switch (clk_sel) {
case 0:
shift = 16;
if (div > 8)
div = 8;
- cbcdr = cbcdr & ~(0x7 << shift);
- cbcdr |= ((div - 1) << shift);
- __raw_writel(cbcdr, &mxc_ccm->cbcdr);
- while (__raw_readl(&mxc_ccm->cdhipr) != 0)
+ clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
+ while (readl(&mxc_ccm->cdhipr) != 0)
;
- __raw_writel(0x0, &mxc_ccm->ccdr);
+ writel(0x0, &mxc_ccm->ccdr);
return 0;
}
u32 *tmp_base =
(u32 *)(IIM_BASE_ADDR + 0x180c);
- set_usb_phy1_clk();
+ set_usb_phy_clk();
- writel((readl(tmp_base) & (~0x6)) | 0x4, tmp_base);
+ clrsetbits_le32(tmp_base, 0x6, 0x4);
}
#endif
{
u32 freq;
- freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+ freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
printf("PLL1 %8d MHz\n", freq / 1000000);
- freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
+ freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
printf("PLL2 %8d MHz\n", freq / 1000000);
- freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
+ freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
printf("PLL3 %8d MHz\n", freq / 1000000);
#ifdef CONFIG_MX53
- freq = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
+ freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
printf("PLL4 %8d MHz\n", freq / 1000000);
#endif
#include <generated/asm-offsets.h>
#include <linux/linkage.h>
+.section ".text.init", "x"
+
/*
* L2CC Cache setup/invalidation/disable
*/
mcr 15, 0, r0, c1, c0, 1
/* reconfigure L2 cache aux control reg */
- mov r0, #0xC0 /* tag RAM */
- add r0, r0, #0x4 /* data RAM */
- orr r0, r0, #1 << 24 /* disable write allocate delay */
- orr r0, r0, #1 << 23 /* disable write allocate combine */
- orr r0, r0, #1 << 22 /* disable write allocate */
+ ldr r0, =0xC0 | /* tag RAM */ \
+ 0x4 | /* data RAM */ \
+ 1 << 24 | /* disable write allocate delay */ \
+ 1 << 23 | /* disable write allocate combine */ \
+ 1 << 22 /* disable write allocate */
#if defined(CONFIG_MX51)
- ldr r1, =0x0
- ldr r3, [r1, #ROM_SI_REV]
+ ldr r3, [r4, #ROM_SI_REV]
cmp r3, #0x10
/* disable write combine for TO 2 and lower revs */
ldr r1, =0x00000203
str r1, [r0, #0x40]
- ldr r1, =0x0
- str r1, [r0, #0x44]
+ str r4, [r0, #0x44]
ldr r1, =0x00120125
str r1, [r0, #0x9C]
.macro setup_pll pll, freq
ldr r0, =\pll
+ adr r2, W_DP_\freq
+ bl setup_pll_func
+.endm
+
+#define W_DP_OP 0
+#define W_DP_MFD 4
+#define W_DP_MFN 8
+
+setup_pll_func:
ldr r1, =0x00001232
str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
mov r1, #0x2
str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
- ldr r1, W_DP_OP_\freq
+ ldr r1, [r2, #W_DP_OP]
str r1, [r0, #PLL_DP_OP]
str r1, [r0, #PLL_DP_HFS_OP]
- ldr r1, W_DP_MFD_\freq
+ ldr r1, [r2, #W_DP_MFD]
str r1, [r0, #PLL_DP_MFD]
str r1, [r0, #PLL_DP_HFS_MFD]
- ldr r1, W_DP_MFN_\freq
+ ldr r1, [r2, #W_DP_MFN]
str r1, [r0, #PLL_DP_MFN]
str r1, [r0, #PLL_DP_HFS_MFN]
1: ldr r1, [r0, #PLL_DP_CTL]
ands r1, r1, #0x1
beq 1b
-.endm
+
+ /* r10 saved upper lr */
+ mov pc, lr
.macro setup_pll_errata pll, freq
ldr r2, =\pll
- mov r1, #0x0
- str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
+ str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
ldr r1, =0x00001236
str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
/* Gate of clocks to the peripherals first */
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
- ldr r1, =0x0
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
+ str r4, [r0, #CLKCTL_CCGR1]
+ str r4, [r0, #CLKCTL_CCGR2]
+ str r4, [r0, #CLKCTL_CCGR3]
ldr r1, =0x00030000
str r1, [r0, #CLKCTL_CCGR4]
#else
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
- ldr r1, =0x0
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
- str r1, [r0, #CLKCTL_CCGR7]
+ str r4, [r0, #CLKCTL_CCGR1]
+ str r4, [r0, #CLKCTL_CCGR2]
+ str r4, [r0, #CLKCTL_CCGR3]
+ str r4, [r0, #CLKCTL_CCGR7]
ldr r1, =0x00030000
str r1, [r0, #CLKCTL_CCGR4]
/* Switch peripheral to PLL 3 */
ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x000010C0
- orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+ ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x13239145
str r1, [r0, #CLKCTL_CBCDR]
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x19239145
str r1, [r0, #CLKCTL_CBCDR]
- ldr r1, =0x000020C0
- orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+ ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
#endif
setup_pll PLL3_BASE_ADDR, 216
#if defined(CONFIG_MX51)
/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
- ldr r1, =0x0
- ldr r3, [r1, #ROM_SI_REV]
+ ldr r3, [r4, #ROM_SI_REV]
cmp r3, #0x10
movls r1, #0x1
movhi r1, #0
str r1, [r0, #CLKCTL_CACRR]
/* Switch ARM back to PLL 1 */
- mov r1, #0
- str r1, [r0, #CLKCTL_CCSR]
+ str r4, [r0, #CLKCTL_CCSR]
#if defined(CONFIG_MX51)
/* setup the rest */
/* Use lp_apm (24MHz) source for perclk */
- ldr r1, =0x000020C2
- orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+ ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
ldr r1, =CONFIG_SYS_CLKTL_CBCDR
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00808145
orr r1, r1, #2 << 10
- orr r1, r1, #0 << 16
orr r1, r1, #1 << 19
str r1, [r0, #CLKCTL_CBCDR]
cmp r1, #0x0
bne 1b
- mov r1, #0x0
- str r1, [r0, #CLKCTL_CCDR]
+ str r4, [r0, #CLKCTL_CCDR]
/* for cko - for ARM div by 8 */
mov r1, #0x000A0000
strh r1, [r0]
.endm
-.section ".text.init", "x"
-
ENTRY(lowlevel_init)
+ mov r10, lr
+ mov r4, #0 /* Fix R4 to 0 */
+
#if defined(CONFIG_MX51)
ldr r0, =GPIO1_BASE_ADDR
ldr r1, [r0, #0x0]
init_clock
- /* r12 saved upper lr*/
- mov pc,lr
+ mov pc, r10
ENDPROC(lowlevel_init)
/* Board level setting value */
-W_DP_OP_864: .word DP_OP_864
-W_DP_MFD_864: .word DP_MFD_864
-W_DP_MFN_864: .word DP_MFN_864
+#if defined(CONFIG_MX51_PLL_ERRATA)
+W_DP_864: .word DP_OP_864
+ .word DP_MFD_864
+ .word DP_MFN_864
W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
-W_DP_OP_800: .word DP_OP_800
-W_DP_MFD_800: .word DP_MFD_800
-W_DP_MFN_800: .word DP_MFN_800
-W_DP_OP_665: .word DP_OP_665
-W_DP_MFD_665: .word DP_MFD_665
-W_DP_MFN_665: .word DP_MFN_665
-W_DP_OP_216: .word DP_OP_216
-W_DP_MFD_216: .word DP_MFD_216
-W_DP_MFN_216: .word DP_MFN_216
+#else
+W_DP_800: .word DP_OP_800
+ .word DP_MFD_800
+ .word DP_MFN_800
+#endif
+#if defined(CONFIG_MX51)
+W_DP_665: .word DP_OP_665
+ .word DP_MFD_665
+ .word DP_MFN_665
+#endif
+W_DP_216: .word DP_OP_216
+ .word DP_MFD_216
+ .word DP_MFN_216
reg = __raw_readl(&imx_ccm->CCGR6);
if (enable)
- reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET;
+ reg |= MXC_CCM_CCGR6_USBOH3_MASK;
else
- reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET);
+ reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
__raw_writel(reg, &imx_ccm->CCGR6);
}
if (i2c_num > 2)
return -EINVAL;
- mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 3) << 1);
+
+ mask = MXC_CCM_CCGR_CG_MASK
+ << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
reg = __raw_readl(&imx_ccm->CCGR2);
if (enable)
reg |= mask;
reg = __raw_readl(&imx_ccm->cacrr);
reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
- freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
+ freq = decode_pll(PLL_SYS, MXC_HCLK);
return freq / (reg + 1);
}
switch (reg) {
case 0:
- freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
+ freq = decode_pll(PLL_USBOTG, MXC_HCLK);
break;
case 1:
case 2:
- freq = CONFIG_SYS_MX6_HCLK;
+ freq = MXC_HCLK;
break;
default:
break;
switch (reg) {
case 0:
- freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
+ freq = decode_pll(PLL_BUS, MXC_HCLK);
break;
case 1:
freq = PLL2_PFD2_FREQ;
root_freq = get_axi_clk();
break;
case 1:
- root_freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
+ root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
break;
case 2:
root_freq = PLL2_PFD2_FREQ;
u32 imx_get_fecclk(void)
{
- return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
+ return decode_pll(PLL_ENET, MXC_HCLK);
}
int enable_sata_clock(void)
/* Enable sata clock */
reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
- reg |= MXC_CCM_CCGR5_CG2_MASK;
+ reg |= MXC_CCM_CCGR5_SATA_MASK;
writel(reg, &imx_ccm->CCGR5);
/* Enable PLLs */
case MXC_IPG_CLK:
return get_ipg_clk();
case MXC_IPG_PERCLK:
+ case MXC_I2C_CLK:
return get_ipg_per_clk();
case MXC_UART_CLK:
return get_uart_clk();
int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 freq;
- freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
+ freq = decode_pll(PLL_SYS, MXC_HCLK);
printf("PLL_SYS %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
+ freq = decode_pll(PLL_BUS, MXC_HCLK);
printf("PLL_BUS %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
+ freq = decode_pll(PLL_USBOTG, MXC_HCLK);
printf("PLL_OTG %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
+ freq = decode_pll(PLL_ENET, MXC_HCLK);
printf("PLL_NET %8d MHz\n", freq / 1000000);
printf("\n");
void boot_mode_apply(unsigned cfg_val)
{
unsigned reg;
- struct src_regs *psrc = (struct src_regs *)SRC_BASE_ADDR;
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
writel(cfg_val, &psrc->gpr9);
reg = readl(&psrc->gpr10);
if (cfg_val)
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
# Make ARMv5 to allow more compilers to work, even though its v7a.
PLATFORM_CPPFLAGS += -march=armv5
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
- $(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
*/
#include <asm/arch/omap.h>
+#include <asm/arch/spl.h>
#include <linux/linkage.h>
ENTRY(save_boot_params)
strb r2, [r3, #BOOT_DEVICE_OFFSET] @ spl_boot_device <- r1
/* boot mode is passed only for devices that can raw/fat mode */
- cmp r2, #2
+ cmp r2, #BOOT_DEVICE_XIP
blt 2f
- cmp r2, #7
+ cmp r2, #BOOT_DEVICE_MMC2
bgt 2f
/* Store the boot mode (raw/FAT) in omap_bootmode */
ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr
ENTRY(lowlevel_init)
ldr sp, SRAM_STACK
- str ip, [sp] /* stash old link register */
+ str ip, [sp] /* stash ip register */
mov ip, lr /* save link reg across call */
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
/*
ldr r1, =SRAM_CLK_CODE
bl cpy_clk_code
#endif /* NAND Boot */
- bl s_init /* go setup pll, mux, memory */
- ldr ip, [sp] /* restore save ip */
mov lr, ip /* restore link reg */
+ ldr ip, [sp] /* restore save ip */
+ /* tail-call s_init to setup pll, mux, memory */
+ b s_init
- /* back to arch calling code */
- mov pc, lr
ENDPROC(lowlevel_init)
/* the literal pools origin */
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+SOBJS = lowlevel_init.o
+COBJS-y += cpu_info.o
+COBJS-y += emac.o
+
+COBJS-$(CONFIG_DISPLAY_BOARDINFO) += board.o
+COBJS-$(CONFIG_GLOBAL_TIMER) += timer.o
+COBJS-$(CONFIG_R8A7740) += cpu_info-r8a7740.o
+COBJS-$(CONFIG_R8A7740) += pfc-r8a7740.o
+COBJS-$(CONFIG_SH73A0) += cpu_info-sh73a0.o
+COBJS-$(CONFIG_SH73A0) += pfc-sh73a0.o
+COBJS_LN-$(CONFIG_TMU_TIMER) += sh_timer.o
+
+COBJS := $(COBJS-y)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix $(obj),$(COBJS_LN-y:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS_LN-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+# from arch/sh/lib/ directory
+$(obj)sh_timer.c:
+ @rm -f $(obj)sh_timer.c
+ ln -s $(SRCTREE)/arch/sh/lib/time.c $(obj)sh_timer.c
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+
/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
-#ifndef _TEGRA_BOARD_H_
-#define _TEGRA_BOARD_H_
-
-/* Setup UARTs for the board according to the selected config */
-void board_init_uart_f(void);
-
-#endif
+int checkboard(void)
+{
+ printf("Board: %s\n", sysinfo.board_string);
+ return 0;
+}
#
-# (C) Copyright 2004-2005
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
#
# See file CREDITS for list of people who contributed to this
# project.
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-#
-# AMD Alchemy AU1000, MIPS32 core
-#
-
-ifeq ($(TBASE),0)
-CONFIG_SYS_TEXT_BASE = 0
-else
-ifeq ($(TBASE),1)
-CONFIG_SYS_TEXT_BASE = 0xbfc10070
-else
-ifeq ($(TBASE),2)
-CONFIG_SYS_TEXT_BASE = 0xbfc30070
-else
-## Only to make ordinary make work
-CONFIG_SYS_TEXT_BASE = 0x90000000
-endif
-endif
-endif
+# Make ARMv5 to allow more compilers to work, even though its v7a.
+PLATFORM_CPPFLAGS += -march=armv5
/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-
#include <common.h>
+#include <asm/io.h>
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
+u32 rmobile_get_cpu_type(void)
{
- printf ("Skipping flash_init\n");
- return (0);
+ u32 id;
+ u32 type;
+ struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE;
+
+ id = readl(hpb->cccr);
+ type = (id >> 8) & 0xFF;
+
+ return type;
}
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+u32 rmobile_get_cpu_rev(void)
{
- printf ("write_buff not implemented\n");
- return (-1);
+ u32 id;
+ u32 rev;
+ struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE;
+
+ id = readl(hpb->cccr);
+ rev = (id >> 4) & 0xF;
+
+ return rev;
}
--- /dev/null
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+
+u32 rmobile_get_cpu_type(void)
+{
+ u32 id;
+ u32 type;
+ struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+
+ id = readl(&hpb->cccr);
+ type = (id >> 8) & 0xFF;
+
+ return type;
+}
+
+u32 rmobile_get_cpu_rev_integer(void)
+{
+ u32 id;
+ u32 rev;
+ struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+
+ id = readl(&hpb->cccr);
+ rev = ((id >> 4) & 0xF) + 1;
+
+ return rev;
+}
+
+u32 rmobile_get_cpu_rev_fraction(void)
+{
+ u32 id;
+ u32 rev;
+ struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+
+ id = readl(&hpb->cccr);
+ rev = id & 0xF;
+
+ return rev;
+}
--- /dev/null
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+ icache_enable();
+ return 0;
+}
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ dcache_enable();
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+static u32 __rmobile_get_cpu_type(void)
+{
+ return 0x0;
+}
+u32 rmobile_get_cpu_type(void)
+ __attribute__((weak, alias("__rmobile_get_cpu_type")));
+
+static u32 __rmobile_get_cpu_rev_integer(void)
+{
+ return 0;
+}
+u32 rmobile_get_cpu_rev_integer(void)
+ __attribute__((weak, alias("__rmobile_get_cpu_rev_integer")));
+
+static u32 __rmobile_get_cpu_rev_fraction(void)
+{
+ return 0;
+}
+u32 rmobile_get_cpu_rev_fraction(void)
+ __attribute__((weak, alias("__rmobile_get_cpu_rev_fraction")));
+
+int print_cpuinfo(void)
+{
+ switch (rmobile_get_cpu_type()) {
+ case 0x37:
+ printf("CPU: Renesas Electronics SH73A0 rev %d.%d\n",
+ rmobile_get_cpu_rev_integer(),
+ rmobile_get_cpu_rev_fraction());
+ break;
+ case 0x40:
+ printf("CPU: Renesas Electronics R8A7740 rev %d.%d\n",
+ rmobile_get_cpu_rev_integer(),
+ rmobile_get_cpu_rev_fraction());
+ break;
+
+ default:
+ printf("CPU: Renesas Electronics CPU rev %d.%d\n",
+ rmobile_get_cpu_rev_integer(),
+ rmobile_get_cpu_rev_fraction());
+ break;
+ }
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
--- /dev/null
+/*
+ * RMOBILE EtherMAC initialization.
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <netdev.h>
+
+int cpu_eth_init(bd_t *bis)
+{
+ int ret = -ENODEV;
+#ifdef CONFIG_SH_ETHER
+ ret = sh_eth_initialize(bis);
+#endif
+ return ret;
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com>
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+ ldr r0, =MERAM_BASE
+ mov r1, #0x0
+ str r1, [r0]
+
+ mrc p15, 0, r0, c0, c0, 5
+ ands r0, r0, #0xF
+ beq lowlevel_init__
+ b wait_interrupt
+
+ .pool
+ .align 4
+
+wait_interrupt:
+#ifdef ICCICR
+ ldr r1, =ICCICR
+ mov r2, #0x0
+ str r2, [r1]
+ mov r2, #0xF0
+ adds r1, r1, #4 /* ICCPMR */
+ str r2, [r1]
+ ldr r1, =ICCICR
+ mov r2, #0x1
+ str r2, [r1]
+#endif
+
+wait_loop:
+ .long 0xE320F003 /* wfi */
+
+ ldr r2, [r1, #0xC]
+ str r2, [r1, #0x10]
+
+ ldr r0, =MERAM_BASE
+ ldr r2, [r0]
+ cmp r2, #0
+ movne pc, r2
+
+ b wait_loop
+
+wait_loop_end:
+ .pool
+ .align 4
+
+lowlevel_init__:
+
+ mov r0, #0x200000
+
+loop0:
+ subs r0, r0, #1
+ bne loop0
+
+ ldr sp, MERAM_STACK
+ b s_init
+
+ .pool
+ .align 4
+
+ENDPROC(lowlevel_init)
+ .ltorg
+
+MERAM_STACK:
+ .word LOW_LEVEL_MERAM_STACK
--- /dev/null
+/*
+ * R8A7740 processor support
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <common.h>
+#include <sh_pfc.h>
+#include <asm/gpio.h>
+#include <asm/arch/irqs.h>
+
+#define CPU_ALL_PORT(fn, pfx, sfx) \
+ PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
+ PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
+ PORT_10(fn, pfx##20, sfx), \
+ PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx)
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ /* PORT0_DATA -> PORT211_DATA */
+ PINMUX_DATA_BEGIN,
+ PORT_ALL(DATA),
+ PINMUX_DATA_END,
+
+ /* PORT0_IN -> PORT211_IN */
+ PINMUX_INPUT_BEGIN,
+ PORT_ALL(IN),
+ PINMUX_INPUT_END,
+
+ /* PORT0_IN_PU -> PORT211_IN_PU */
+ PINMUX_INPUT_PULLUP_BEGIN,
+ PORT_ALL(IN_PU),
+ PINMUX_INPUT_PULLUP_END,
+
+ /* PORT0_IN_PD -> PORT211_IN_PD */
+ PINMUX_INPUT_PULLDOWN_BEGIN,
+ PORT_ALL(IN_PD),
+ PINMUX_INPUT_PULLDOWN_END,
+
+ /* PORT0_OUT -> PORT211_OUT */
+ PINMUX_OUTPUT_BEGIN,
+ PORT_ALL(OUT),
+ PINMUX_OUTPUT_END,
+
+ PINMUX_FUNCTION_BEGIN,
+ PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
+ PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
+ PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
+ PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
+ PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
+ PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
+ PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
+ PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
+ PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
+ PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
+
+ MSEL1CR_31_0, MSEL1CR_31_1,
+ MSEL1CR_30_0, MSEL1CR_30_1,
+ MSEL1CR_29_0, MSEL1CR_29_1,
+ MSEL1CR_28_0, MSEL1CR_28_1,
+ MSEL1CR_27_0, MSEL1CR_27_1,
+ MSEL1CR_26_0, MSEL1CR_26_1,
+ MSEL1CR_16_0, MSEL1CR_16_1,
+ MSEL1CR_15_0, MSEL1CR_15_1,
+ MSEL1CR_14_0, MSEL1CR_14_1,
+ MSEL1CR_13_0, MSEL1CR_13_1,
+ MSEL1CR_12_0, MSEL1CR_12_1,
+ MSEL1CR_9_0, MSEL1CR_9_1,
+ MSEL1CR_7_0, MSEL1CR_7_1,
+ MSEL1CR_6_0, MSEL1CR_6_1,
+ MSEL1CR_5_0, MSEL1CR_5_1,
+ MSEL1CR_4_0, MSEL1CR_4_1,
+ MSEL1CR_3_0, MSEL1CR_3_1,
+ MSEL1CR_2_0, MSEL1CR_2_1,
+ MSEL1CR_0_0, MSEL1CR_0_1,
+
+ MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
+ MSEL3CR_6_0, MSEL3CR_6_1,
+
+ MSEL4CR_19_0, MSEL4CR_19_1,
+ MSEL4CR_18_0, MSEL4CR_18_1,
+ MSEL4CR_15_0, MSEL4CR_15_1,
+ MSEL4CR_10_0, MSEL4CR_10_1,
+ MSEL4CR_6_0, MSEL4CR_6_1,
+ MSEL4CR_4_0, MSEL4CR_4_1,
+ MSEL4CR_1_0, MSEL4CR_1_1,
+
+ MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
+ MSEL5CR_30_0, MSEL5CR_30_1,
+ MSEL5CR_29_0, MSEL5CR_29_1,
+ MSEL5CR_27_0, MSEL5CR_27_1,
+ MSEL5CR_25_0, MSEL5CR_25_1,
+ MSEL5CR_23_0, MSEL5CR_23_1,
+ MSEL5CR_21_0, MSEL5CR_21_1,
+ MSEL5CR_19_0, MSEL5CR_19_1,
+ MSEL5CR_17_0, MSEL5CR_17_1,
+ MSEL5CR_15_0, MSEL5CR_15_1,
+ MSEL5CR_14_0, MSEL5CR_14_1,
+ MSEL5CR_13_0, MSEL5CR_13_1,
+ MSEL5CR_12_0, MSEL5CR_12_1,
+ MSEL5CR_11_0, MSEL5CR_11_1,
+ MSEL5CR_10_0, MSEL5CR_10_1,
+ MSEL5CR_8_0, MSEL5CR_8_1,
+ MSEL5CR_7_0, MSEL5CR_7_1,
+ MSEL5CR_6_0, MSEL5CR_6_1,
+ MSEL5CR_5_0, MSEL5CR_5_1,
+ MSEL5CR_4_0, MSEL5CR_4_1,
+ MSEL5CR_3_0, MSEL5CR_3_1,
+ MSEL5CR_2_0, MSEL5CR_2_1,
+ MSEL5CR_0_0, MSEL5CR_0_1,
+ PINMUX_FUNCTION_END,
+
+ PINMUX_MARK_BEGIN,
+
+ /* IRQ */
+ IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
+ IRQ1_MARK,
+ IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
+ IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
+ IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
+ IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
+ IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
+ IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
+ IRQ8_MARK,
+ IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
+ IRQ10_MARK,
+ IRQ11_MARK,
+ IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
+ IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
+ IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
+ IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
+ IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
+ IRQ17_MARK,
+ IRQ18_MARK,
+ IRQ19_MARK,
+ IRQ20_MARK,
+ IRQ21_MARK,
+ IRQ22_MARK,
+ IRQ23_MARK,
+ IRQ24_MARK,
+ IRQ25_MARK,
+ IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
+ IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
+ IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
+ IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
+ IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
+ IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
+
+ /* Function */
+
+ /* DBGT */
+ DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
+ DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
+ DBGMD21_MARK,
+
+ /* FSI */
+ FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
+ FSIAISLD_PORT5_MARK,
+ FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
+ FSIASPDIF_PORT18_MARK,
+ FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
+ FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
+ FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
+
+ /* FMSI */
+ FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
+ FMSISLD_PORT6_MARK,
+ FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
+ FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
+ FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
+
+ /* SCIFA0 */
+ SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
+ SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+
+ /* SCIFA1 */
+ SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
+ SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
+
+ /* SCIFA2 */
+ SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
+ SCIFA2_SCK_PORT199_MARK,
+ SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
+ SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
+
+ /* SCIFA3 */
+ SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
+ SCIFA3_SCK_PORT116_MARK,
+ SCIFA3_CTS_PORT117_MARK,
+ SCIFA3_RXD_PORT174_MARK,
+ SCIFA3_TXD_PORT175_MARK,
+
+ SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
+ SCIFA3_SCK_PORT158_MARK,
+ SCIFA3_CTS_PORT162_MARK,
+ SCIFA3_RXD_PORT159_MARK,
+ SCIFA3_TXD_PORT160_MARK,
+
+ /* SCIFA4 */
+ SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
+ SCIFA4_TXD_PORT13_MARK,
+
+ SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
+ SCIFA4_TXD_PORT203_MARK,
+
+ SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
+ SCIFA4_TXD_PORT93_MARK,
+
+ SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
+ SCIFA4_SCK_PORT205_MARK,
+
+ /* SCIFA5 */
+ SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
+ SCIFA5_RXD_PORT10_MARK,
+
+ SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
+ SCIFA5_TXD_PORT208_MARK,
+
+ SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
+ SCIFA5_RXD_PORT92_MARK,
+
+ SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
+ SCIFA5_SCK_PORT206_MARK,
+
+ /* SCIFA6 */
+ SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
+
+ /* SCIFA7 */
+ SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
+
+ /* SCIFAB */
+ SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
+ SCIFB_RXD_PORT191_MARK,
+ SCIFB_TXD_PORT192_MARK,
+ SCIFB_RTS_PORT186_MARK,
+ SCIFB_CTS_PORT187_MARK,
+
+ SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
+ SCIFB_RXD_PORT3_MARK,
+ SCIFB_TXD_PORT4_MARK,
+ SCIFB_RTS_PORT172_MARK,
+ SCIFB_CTS_PORT173_MARK,
+
+ /* LCD0 */
+ LCDC0_SELECT_MARK,
+
+ LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+ LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+ LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
+ LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
+ LCD0_D16_MARK, LCD0_D17_MARK,
+ LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
+ LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
+ LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
+ LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
+ LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
+
+ LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
+ LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
+ LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
+ LCD0_LCLK_PORT165_MARK,
+
+ LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
+ LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
+ LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
+ LCD0_LCLK_PORT102_MARK,
+
+ /* LCD1 */
+ LCDC1_SELECT_MARK,
+
+ LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+ LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+ LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
+ LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
+ LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
+ LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
+ LCD1_DON_MARK, LCD1_VCPWC_MARK,
+ LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
+
+ LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
+ LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
+ LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
+ LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
+
+ /* RSPI */
+ RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
+ RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
+ RSPI_MISO_A_MARK,
+
+ /* VIO CKO */
+ VIO_CKO1_MARK, /* needs fixup */
+ VIO_CKO2_MARK,
+ VIO_CKO_1_MARK,
+ VIO_CKO_MARK,
+
+ /* VIO0 */
+ VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
+ VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
+ VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
+ VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
+ VIO0_FIELD_MARK,
+
+ VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
+ VIO0_D14_PORT25_MARK,
+ VIO0_D15_PORT24_MARK,
+
+ VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
+ VIO0_D14_PORT95_MARK,
+ VIO0_D15_PORT96_MARK,
+
+ /* VIO1 */
+ VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
+ VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
+ VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
+
+ /* TPU0 */
+ TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
+ TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
+ TPU0TO2_PORT202_MARK,
+
+ /* SSP1 0 */
+ STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
+ STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
+ STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
+
+ /* SSP1 1 */
+ STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
+ STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
+ STP1_IPSYNC_MARK,
+
+ STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
+ STP1_IPEN_PORT187_MARK,
+
+ STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
+ STP1_IPEN_PORT193_MARK,
+
+ /* SIM */
+ SIM_RST_MARK, SIM_CLK_MARK,
+ SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
+ SIM_D_PORT199_MARK,
+
+ /* SDHI0 */
+ SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
+ SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
+
+ /* SDHI1 */
+ SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
+ SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
+
+ /* SDHI2 */
+ SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
+ SDHI2_CLK_MARK, SDHI2_CMD_MARK,
+
+ SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
+ SDHI2_WP_PORT25_MARK,
+
+ SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
+ SDHI2_CD_PORT202_MARK,
+
+ /* MSIOF2 */
+ MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
+ MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
+ MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
+ MSIOF2_RSCK_MARK,
+
+ /* KEYSC */
+ KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
+ KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+ KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
+
+ KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
+ KEYIN1_PORT44_MARK,
+ KEYIN2_PORT45_MARK,
+ KEYIN3_PORT46_MARK,
+
+ KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
+ KEYIN1_PORT57_MARK,
+ KEYIN2_PORT56_MARK,
+ KEYIN3_PORT55_MARK,
+
+ /* VOU */
+ DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
+ DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
+ DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
+ DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
+ DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
+
+ /* MEMC */
+ MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
+ MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
+ MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
+ MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
+ MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
+
+ MEMC_CS1_MARK, /* MSEL4CR_6_0 */
+ MEMC_ADV_MARK,
+ MEMC_WAIT_MARK,
+ MEMC_BUSCLK_MARK,
+
+ MEMC_A1_MARK, /* MSEL4CR_6_1 */
+ MEMC_DREQ0_MARK,
+ MEMC_DREQ1_MARK,
+ MEMC_A0_MARK,
+
+ /* MMC */
+ MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
+ MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
+ MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
+ MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
+
+ MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
+ MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
+ MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
+ MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
+
+ /* MSIOF0 */
+ MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
+ MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
+ MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
+ MSIOF0_TSYNC_MARK,
+
+ /* MSIOF1 */
+ MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
+ MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
+
+ MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
+ MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
+ MSIOF1_TSYNC_PORT120_MARK,
+ MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
+
+ MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
+ MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
+ MSIOF1_RXD_PORT75_MARK,
+ MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
+
+ /* GPIO */
+ GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
+
+ /* USB0 */
+ USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
+
+ /* USB1 */
+ USB1_OCI_MARK, USB1_PPON_MARK,
+
+ /* BBIF1 */
+ BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
+ BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
+ BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
+
+ /* BBIF2 */
+ BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
+ BBIF2_RXD2_PORT60_MARK,
+ BBIF2_TSYNC2_PORT6_MARK,
+ BBIF2_TSCK2_PORT59_MARK,
+
+ BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
+ BBIF2_TXD2_PORT183_MARK,
+ BBIF2_TSCK2_PORT89_MARK,
+ BBIF2_TSYNC2_PORT184_MARK,
+
+ /* BSC / FLCTL / PCMCIA */
+ CS0_MARK, CS2_MARK, CS4_MARK,
+ CS5B_MARK, CS6A_MARK,
+ CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
+ CS5A_PORT19_MARK,
+ IOIS16_MARK, /* ? */
+
+ A0_MARK, A1_MARK, A2_MARK, A3_MARK,
+ A4_FOE_MARK, /* share with FLCTL */
+ A5_FCDE_MARK, /* share with FLCTL */
+ A6_MARK, A7_MARK, A8_MARK, A9_MARK,
+ A10_MARK, A11_MARK, A12_MARK, A13_MARK,
+ A14_MARK, A15_MARK, A16_MARK, A17_MARK,
+ A18_MARK, A19_MARK, A20_MARK, A21_MARK,
+ A22_MARK, A23_MARK, A24_MARK, A25_MARK,
+ A26_MARK,
+
+ D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
+ D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
+ D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
+ D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
+ D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
+ D15_NAF15_MARK, /* share with FLCTL */
+ D16_MARK, D17_MARK, D18_MARK, D19_MARK,
+ D20_MARK, D21_MARK, D22_MARK, D23_MARK,
+ D24_MARK, D25_MARK, D26_MARK, D27_MARK,
+ D28_MARK, D29_MARK, D30_MARK, D31_MARK,
+
+ WE0_FWE_MARK, /* share with FLCTL */
+ WE1_MARK,
+ WE2_ICIORD_MARK, /* share with PCMCIA */
+ WE3_ICIOWR_MARK, /* share with PCMCIA */
+ CKO_MARK, BS_MARK, RDWR_MARK,
+ RD_FSC_MARK, /* share with FLCTL */
+ WAIT_PORT177_MARK, /* WAIT Port 90/177 */
+ WAIT_PORT90_MARK,
+
+ FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
+
+ /* IRDA */
+ IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
+
+ /* ATAPI */
+ IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
+ IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
+ IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
+ IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
+ IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
+ IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
+ IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
+ IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
+
+ /* RMII */
+ RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
+ RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
+ RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
+ RMII_REF50CK_MARK, /* for RMII */
+ RMII_REF125CK_MARK, /* for GMII */
+
+ /* GEther */
+ ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
+ ET_ETXD2_MARK, ET_ETXD3_MARK,
+ ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
+ ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
+ ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
+ ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
+ ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
+ ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
+ ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
+ ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
+
+ /* DMA0 */
+ DREQ0_MARK, DACK0_MARK,
+
+ /* DMA1 */
+ DREQ1_MARK, DACK1_MARK,
+
+ /* SYSC */
+ RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
+
+ /* IRREM */
+ IROUT_MARK,
+
+ /* SDENC */
+ SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
+
+ /* DEBUG */
+ EDEBGREQ_PULLUP_MARK, /* for JTAG */
+ EDEBGREQ_PULLDOWN_MARK,
+
+ TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
+ TRACEAUD_FROM_LCDC0_MARK,
+ TRACEAUD_FROM_MEMC_MARK,
+
+ PINMUX_MARK_END,
+};
+
+static unsigned short pinmux_data[] = {
+ /* specify valid pin states for each pin in GPIO mode */
+
+ /* I/O and Pull U/D */
+ PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
+ PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3),
+ PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5),
+ PORT_DATA_IO_PD(6), PORT_DATA_IO(7),
+ PORT_DATA_IO(8), PORT_DATA_IO(9),
+
+ PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11),
+ PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13),
+ PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15),
+ PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17),
+ PORT_DATA_IO(18), PORT_DATA_IO_PU(19),
+
+ PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21),
+ PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23),
+ PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25),
+ PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27),
+ PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29),
+
+ PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31),
+ PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33),
+ PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35),
+ PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37),
+ PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39),
+
+ PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41),
+ PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43),
+ PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45),
+ PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47),
+ PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49),
+
+ PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51),
+ PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53),
+ PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55),
+ PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57),
+ PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59),
+
+ PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61),
+ PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
+ PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
+ PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
+ PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
+
+ PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
+ PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
+ PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75),
+ PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
+ PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
+
+ PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
+ PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83),
+ PORT_DATA_IO(84), PORT_DATA_IO_PD(85),
+ PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87),
+ PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89),
+
+ PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91),
+ PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93),
+ PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95),
+ PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
+ PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),
+
+ PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101),
+ PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103),
+ PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105),
+ PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107),
+ PORT_DATA_IO(108), PORT_DATA_IO(109),
+
+ PORT_DATA_IO(110), PORT_DATA_IO(111),
+ PORT_DATA_IO(112), PORT_DATA_IO(113),
+ PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115),
+ PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117),
+ PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119),
+
+ PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121),
+ PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123),
+ PORT_DATA_IO_PD(124), PORT_DATA_IO(125),
+ PORT_DATA_IO(126), PORT_DATA_IO(127),
+ PORT_DATA_IO(128), PORT_DATA_IO(129),
+
+ PORT_DATA_IO(130), PORT_DATA_IO(131),
+ PORT_DATA_IO(132), PORT_DATA_IO(133),
+ PORT_DATA_IO(134), PORT_DATA_IO(135),
+ PORT_DATA_IO(136), PORT_DATA_IO(137),
+ PORT_DATA_IO(138), PORT_DATA_IO(139),
+
+ PORT_DATA_IO(140), PORT_DATA_IO(141),
+ PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143),
+ PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145),
+ PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147),
+ PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149),
+
+ PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151),
+ PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153),
+ PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155),
+ PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157),
+ PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159),
+
+ PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161),
+ PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163),
+ PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165),
+ PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167),
+ PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169),
+
+ PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171),
+ PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
+ PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175),
+ PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177),
+ PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179),
+
+ PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181),
+ PORT_DATA_IO_PU(182), PORT_DATA_IO(183),
+ PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185),
+ PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187),
+ PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
+
+ PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191),
+ PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193),
+ PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195),
+ PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197),
+ PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),
+
+ PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201),
+ PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203),
+ PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
+ PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
+ PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209),
+
+ PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
+
+ /* Port0 */
+ PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
+ PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
+ PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
+ PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
+ PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
+ PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
+ PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
+
+ /* Port1 */
+ PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
+ PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
+ PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
+ PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
+ PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
+ PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
+ PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
+
+ /* Port2 */
+ PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
+ PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
+ PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
+ PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
+ PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
+
+ /* Port3 */
+ PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
+ PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
+ PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
+ PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
+
+ /* Port4 */
+ PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
+ PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
+ PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
+ PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
+
+ /* Port5 */
+ PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
+ PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
+ PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
+ PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
+ PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
+
+ /* Port6 */
+ PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
+ PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
+ PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
+ PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
+ PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
+
+ /* Port7 */
+ PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
+
+ /* Port8 */
+ PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
+
+ /* Port9 */
+ PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
+ PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
+
+ /* Port10 */
+ PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
+ PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0,
+ MSEL5CR_15_0),
+ PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
+
+ /* Port11 */
+ PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
+ PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
+
+ /* Port12 */
+ PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
+ PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0,
+ MSEL5CR_11_0),
+ PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
+ PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
+ PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
+
+ /* Port13 */
+ PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
+ PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0,
+ MSEL5CR_11_0),
+ PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
+ PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
+
+ /* Port14 */
+ PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
+ PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
+ PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
+ PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
+ PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
+
+ /* Port15 */
+ PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
+ PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
+ PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
+ PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
+ PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
+
+ /* Port16 */
+ PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
+ PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
+
+ /* Port17 */
+ PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
+ PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
+
+ /* Port18 */
+ PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
+ PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
+
+ /* Port19 */
+ PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
+ PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
+ PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
+
+ /* Port20 */
+ PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
+ PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0,
+ MSEL5CR_14_0),
+ PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
+
+ /* Port21 */
+ PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
+ PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
+ PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
+ PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
+ PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
+ PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
+
+ /* Port22 */
+ PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
+ PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
+ PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
+
+ /* Port23 */
+ PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
+ PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
+ PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
+ PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
+ PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
+ PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
+
+ /* Port24 */
+ PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
+ PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
+ PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
+ PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
+
+ /* Port25 */
+ PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
+ PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
+ PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
+ PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
+
+ /* Port26 */
+ PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
+ PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
+ PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
+
+ /* Port27 - Port39 Function */
+ PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
+ PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
+ PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
+ PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
+ PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
+ PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
+ PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
+ PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
+ PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
+ PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
+ PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
+ PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
+ PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
+
+ /* Port38 IRQ */
+ PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
+
+ /* Port40 */
+ PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
+ PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
+ PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
+
+ /* Port41 */
+ PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
+ PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
+ PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
+
+ /* Port42 */
+ PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
+ PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
+ PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
+
+ /* Port43 */
+ PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
+ PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
+ PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
+ PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
+
+ /* Port44 */
+ PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
+ PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
+ PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
+ PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
+
+ /* Port45 */
+ PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
+ PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
+ PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
+ PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
+
+ /* Port46 */
+ PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
+ PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
+ PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
+
+ /* Port47 */
+ PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
+ PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
+ PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
+
+ /* Port48 */
+ PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
+ PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
+ PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
+
+ /* Port49 */
+ PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
+ PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
+ PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
+ PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
+
+ /* Port50 */
+ PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
+ PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
+ PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
+ PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
+
+ /* Port51 */
+ PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
+ PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
+ PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
+
+ /* Port52 */
+ PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
+ PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
+ PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
+
+ /* Port53 */
+ PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
+ PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
+ PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
+
+ /* Port54 */
+ PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
+ PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
+ PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
+
+ /* Port55 */
+ PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
+ PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
+ PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
+ PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
+
+ /* Port56 */
+ PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
+ PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
+ PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
+ PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
+ PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
+
+ /* Port57 */
+ PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
+ PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
+ PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
+ PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
+ PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
+
+ /* Port58 */
+ PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1),
+ PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
+ PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
+ PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
+ PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
+
+ /* Port59 */
+ PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
+ PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
+ PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
+
+ /* Port60 */
+ PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
+ PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
+ PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
+
+ /* Port61 */
+ PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
+ PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
+
+ /* Port62 */
+ PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
+ PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
+ PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
+ PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
+
+ /* Port63 */
+ PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
+ PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
+ PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
+
+ /* Port64 */
+ PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
+ PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
+ PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
+ PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
+
+ /* Port65 */
+ PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
+ PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
+ PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
+
+ /* Port66 */
+ PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
+ PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
+ PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
+ PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
+
+ /* Port67 - Port73 Function1 */
+ PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
+ PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
+ PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
+ PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
+ PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
+ PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
+ PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
+
+ /* Port67 - Port73 Function2 */
+ PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
+ PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
+ PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
+ PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
+ PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
+ PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
+ PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
+
+ /* Port67 - Port73 Function4 */
+ PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
+ PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
+ PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
+ PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
+ PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
+ PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
+ PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
+
+ /* Port67 - Port73 Function6 */
+ PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
+ PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
+ PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
+ PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
+ PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
+ PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
+ PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
+
+ /* Port67 - Port71 IRQ */
+ PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
+ PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
+ PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
+ PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
+ PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
+
+ /* Port74 */
+ PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
+ PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
+ PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
+ PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
+ PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
+
+ /* Port75 */
+ PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
+ PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
+ PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
+ PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
+ PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
+
+ /* Port76 - Port80 Function */
+ PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
+ PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
+ PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
+ PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
+ PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
+
+ /* Port81 */
+ PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
+ PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
+
+ /* Port82 - Port88 Function */
+ PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
+ PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
+ PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
+ PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
+ PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
+ PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
+ PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
+
+ /* Port89 */
+ PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
+ PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
+ PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
+
+ /* Port90 */
+ PINMUX_DATA(DACK0_MARK, PORT90_FN1),
+ PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
+ PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
+ PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
+
+ /* Port91 */
+ PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
+ PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
+ PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1,
+ MSEL5CR_14_0),
+ PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
+
+ /* Port92 */
+ PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
+ PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
+ PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1,
+ MSEL5CR_14_0),
+ PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
+ PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
+
+ /* Port93 */
+ PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
+ PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
+ PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1,
+ MSEL5CR_11_0),
+ PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
+ PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
+
+ /* Port94 */
+ PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
+ PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
+ PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1,
+ MSEL5CR_11_0),
+ PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
+ PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
+
+ /* Port95 */
+ PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
+ PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
+
+ PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
+ PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
+ PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
+ PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
+
+ /* Port96 */
+ PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
+ PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
+
+ PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
+ PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
+ PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
+ PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
+
+ /* Port97 */
+ PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
+ PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
+ PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
+ PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
+ PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
+
+ /* Port98 */
+ PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
+ PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
+ PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
+ PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
+
+ /* Port99 */
+ PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
+ PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
+ PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
+ PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
+ PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
+
+ /* Port100 */
+ PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
+ PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
+ PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
+ PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
+
+ /* Port101 */
+ PINMUX_DATA(FCE0_MARK, PORT101_FN1),
+
+ /* Port102 */
+ PINMUX_DATA(FRB_MARK, PORT102_FN1),
+ PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
+
+ /* Port103 */
+ PINMUX_DATA(CS5B_MARK, PORT103_FN1),
+ PINMUX_DATA(FCE1_MARK, PORT103_FN2),
+ PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
+
+ /* Port104 */
+ PINMUX_DATA(CS6A_MARK, PORT104_FN1),
+ PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
+ PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
+
+ /* Port105 */
+ PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
+ PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
+
+ /* Port106 */
+ PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
+ PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
+
+ /* Port107 - Port115 Function */
+ PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
+ PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
+ PINMUX_DATA(CS0_MARK, PORT109_FN1),
+ PINMUX_DATA(CS2_MARK, PORT110_FN1),
+ PINMUX_DATA(CS4_MARK, PORT111_FN1),
+ PINMUX_DATA(WE1_MARK, PORT112_FN1),
+ PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
+ PINMUX_DATA(RDWR_MARK, PORT114_FN1),
+ PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
+
+ /* Port116 */
+ PINMUX_DATA(A25_MARK, PORT116_FN1),
+ PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
+ PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
+ PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
+ PINMUX_DATA(GPO1_MARK, PORT116_FN5),
+
+ /* Port117 */
+ PINMUX_DATA(A24_MARK, PORT117_FN1),
+ PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
+ PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
+ PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
+ PINMUX_DATA(GPO0_MARK, PORT117_FN5),
+
+ /* Port118 */
+ PINMUX_DATA(A23_MARK, PORT118_FN1),
+ PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
+ PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
+ PINMUX_DATA(GPI1_MARK, PORT118_FN5),
+ PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
+
+ /* Port119 */
+ PINMUX_DATA(A22_MARK, PORT119_FN1),
+ PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
+ PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
+ PINMUX_DATA(GPI0_MARK, PORT119_FN5),
+ PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
+
+ /* Port120 */
+ PINMUX_DATA(A21_MARK, PORT120_FN1),
+ PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
+ PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
+ PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_0),
+
+ /* Port121 */
+ PINMUX_DATA(A20_MARK, PORT121_FN1),
+ PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
+ PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
+ PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
+
+ /* Port122 */
+ PINMUX_DATA(A19_MARK, PORT122_FN1),
+ PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
+
+ /* Port123 */
+ PINMUX_DATA(A18_MARK, PORT123_FN1),
+ PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
+
+ /* Port124 */
+ PINMUX_DATA(A17_MARK, PORT124_FN1),
+ PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
+
+ /* Port125 - Port141 Function */
+ PINMUX_DATA(A16_MARK, PORT125_FN1),
+ PINMUX_DATA(A15_MARK, PORT126_FN1),
+ PINMUX_DATA(A14_MARK, PORT127_FN1),
+ PINMUX_DATA(A13_MARK, PORT128_FN1),
+ PINMUX_DATA(A12_MARK, PORT129_FN1),
+ PINMUX_DATA(A11_MARK, PORT130_FN1),
+ PINMUX_DATA(A10_MARK, PORT131_FN1),
+ PINMUX_DATA(A9_MARK, PORT132_FN1),
+ PINMUX_DATA(A8_MARK, PORT133_FN1),
+ PINMUX_DATA(A7_MARK, PORT134_FN1),
+ PINMUX_DATA(A6_MARK, PORT135_FN1),
+ PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
+ PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
+ PINMUX_DATA(A3_MARK, PORT138_FN1),
+ PINMUX_DATA(A2_MARK, PORT139_FN1),
+ PINMUX_DATA(A1_MARK, PORT140_FN1),
+ PINMUX_DATA(CKO_MARK, PORT141_FN1),
+
+ /* Port142 - Port157 Function1 */
+ PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
+ PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
+ PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
+ PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
+ PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
+ PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
+ PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
+ PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
+ PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
+ PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
+ PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
+ PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
+ PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
+ PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
+ PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
+ PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
+
+ /* Port142 - Port149 Function3 */
+ PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
+ PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
+ PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
+ PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
+ PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
+ PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
+ PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
+ PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
+
+ /* Port158 */
+ PINMUX_DATA(D31_MARK, PORT158_FN1),
+ PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
+ PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
+ PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
+ PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
+ PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
+
+ /* Port159 */
+ PINMUX_DATA(D30_MARK, PORT159_FN1),
+ PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
+ PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
+ PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
+ PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
+
+ /* Port160 */
+ PINMUX_DATA(D29_MARK, PORT160_FN1),
+ PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
+ PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
+ PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
+ PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
+
+ /* Port161 */
+ PINMUX_DATA(D28_MARK, PORT161_FN1),
+ PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
+ PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
+ PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
+ PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
+ PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
+
+ /* Port162 */
+ PINMUX_DATA(D27_MARK, PORT162_FN1),
+ PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
+ PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
+ PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
+ PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
+
+ /* Port163 */
+ PINMUX_DATA(D26_MARK, PORT163_FN1),
+ PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
+ PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
+ PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
+ PINMUX_DATA(IROUT_MARK, PORT163_FN5),
+ PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
+
+ /* Port164 */
+ PINMUX_DATA(D25_MARK, PORT164_FN1),
+ PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
+ PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
+ PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
+ PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
+
+ /* Port165 */
+ PINMUX_DATA(D24_MARK, PORT165_FN1),
+ PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
+ PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
+ PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
+
+ /* Port166 - Port171 Function1 */
+ PINMUX_DATA(D21_MARK, PORT166_FN1),
+ PINMUX_DATA(D20_MARK, PORT167_FN1),
+ PINMUX_DATA(D19_MARK, PORT168_FN1),
+ PINMUX_DATA(D18_MARK, PORT169_FN1),
+ PINMUX_DATA(D17_MARK, PORT170_FN1),
+ PINMUX_DATA(D16_MARK, PORT171_FN1),
+
+ /* Port166 - Port171 Function3 */
+ PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
+ PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
+ PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
+ PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
+ PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
+ PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
+
+ /* Port166 - Port171 Function6 */
+ PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
+ PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
+ PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
+ PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
+ PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
+ PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
+
+ /* Port167 - Port171 IRQ */
+ PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
+ PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
+ PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
+ PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
+ PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
+
+ /* Port172 */
+ PINMUX_DATA(D23_MARK, PORT172_FN1),
+ PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
+ PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
+ PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
+ PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
+
+ /* Port173 */
+ PINMUX_DATA(D22_MARK, PORT173_FN1),
+ PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
+ PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
+ PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
+ PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
+
+ /* Port174 */
+ PINMUX_DATA(A26_MARK, PORT174_FN1),
+ PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
+ PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
+ PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
+
+ /* Port175 */
+ PINMUX_DATA(A0_MARK, PORT175_FN1),
+ PINMUX_DATA(BS_MARK, PORT175_FN2),
+ PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
+ PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
+
+ /* Port176 */
+ PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
+
+ /* Port177 */
+ PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
+ PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
+ PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
+ PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
+
+ /* Port178 */
+ PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
+ PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
+ PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
+
+ /* Port179 */
+ PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
+ PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
+ PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
+
+ /* Port180 */
+ PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
+ PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
+ PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
+ PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
+ PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
+
+ /* Port181 */
+ PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
+ PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
+ PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
+
+ /* Port182 */
+ PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
+ PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
+ PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
+
+ /* Port183 */
+ PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
+ PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
+ PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
+
+ /* Port184 */
+ PINMUX_DATA(DACK1_MARK, PORT184_FN1),
+ PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
+ PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
+
+ /* Port185 - Port192 Function1 */
+ PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
+ PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
+ PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
+ PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
+ PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
+ PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
+ PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
+
+ /* Port185 - Port192 Function3 */
+ PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
+ PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
+ PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
+ PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
+ PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
+ PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
+ PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
+ PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
+
+ /* Port185 - Port192 Function6 */
+ PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
+ PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
+ PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
+ PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
+ PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
+ PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
+ PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
+ PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
+
+ /* Port193 */
+ PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
+ PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
+ PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1),
+ PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
+
+ /* Port194 */
+ PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
+ PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
+ PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1),
+ PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
+
+ /* Port195 */
+ PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
+ PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
+ PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
+ PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
+
+ /* Port196 */
+ PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
+ PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
+ PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
+ PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
+
+ /* Port197 */
+ PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
+ PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
+ PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
+ PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
+
+ /* Port198 */
+ PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
+ PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
+ PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
+ PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
+
+ /* Port199 */
+ PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
+ PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
+ PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
+ PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
+ PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
+ PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
+
+ /* Port200 */
+ PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
+ PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
+ PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
+ PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
+ PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
+
+ /* Port201 */
+ PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
+ PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
+
+ PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
+ PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
+ PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
+ PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
+
+ /* Port202 */
+ PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
+ PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
+
+ PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
+ PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
+ PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
+ PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
+ PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
+ PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
+
+ /* Port203 - Port208 Function1 */
+ PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
+ PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
+ PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
+ PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
+ PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
+ PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
+
+ /* Port203 - Port208 Function3 */
+ PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
+ PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
+ PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
+ PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
+ PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
+ PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
+
+ /* Port203 - Port208 Function6 */
+ PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
+ PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
+ PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
+ PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
+ PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
+ PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
+
+ /* Port203 - Port208 Function7 */
+ PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0,
+ MSEL5CR_11_1),
+ PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0,
+ MSEL5CR_11_1),
+ PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
+ PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
+ PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0,
+ MSEL5CR_14_1),
+ PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0,
+ MSEL5CR_14_1),
+
+ /* Port209 */
+ PINMUX_DATA(VBUS_MARK, PORT209_FN1),
+ PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_1),
+
+ /* Port210 */
+ PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
+
+ /* Port211 */
+ PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
+
+ /* LCDC select */
+ PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0),
+ PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1),
+
+ /* SDENC */
+ PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
+ PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
+
+ /* SYSC */
+ PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
+ PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
+
+ /* DEBUG */
+ PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
+ PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
+
+ PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
+ PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
+ PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+
+ /* PORT */
+ GPIO_PORT_ALL(),
+
+ /* IRQ */
+ GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13),
+ GPIO_FN(IRQ1),
+ GPIO_FN(IRQ2_PORT11), GPIO_FN(IRQ2_PORT12),
+ GPIO_FN(IRQ3_PORT10), GPIO_FN(IRQ3_PORT14),
+ GPIO_FN(IRQ4_PORT15), GPIO_FN(IRQ4_PORT172),
+ GPIO_FN(IRQ5_PORT0), GPIO_FN(IRQ5_PORT1),
+ GPIO_FN(IRQ6_PORT121), GPIO_FN(IRQ6_PORT173),
+ GPIO_FN(IRQ7_PORT120), GPIO_FN(IRQ7_PORT209),
+ GPIO_FN(IRQ8),
+ GPIO_FN(IRQ9_PORT118), GPIO_FN(IRQ9_PORT210),
+ GPIO_FN(IRQ10),
+ GPIO_FN(IRQ11),
+ GPIO_FN(IRQ12_PORT42), GPIO_FN(IRQ12_PORT97),
+ GPIO_FN(IRQ13_PORT64), GPIO_FN(IRQ13_PORT98),
+ GPIO_FN(IRQ14_PORT63), GPIO_FN(IRQ14_PORT99),
+ GPIO_FN(IRQ15_PORT62), GPIO_FN(IRQ15_PORT100),
+ GPIO_FN(IRQ16_PORT68), GPIO_FN(IRQ16_PORT211),
+ GPIO_FN(IRQ17),
+ GPIO_FN(IRQ18),
+ GPIO_FN(IRQ19),
+ GPIO_FN(IRQ20),
+ GPIO_FN(IRQ21),
+ GPIO_FN(IRQ22),
+ GPIO_FN(IRQ23),
+ GPIO_FN(IRQ24),
+ GPIO_FN(IRQ25),
+ GPIO_FN(IRQ26_PORT58), GPIO_FN(IRQ26_PORT81),
+ GPIO_FN(IRQ27_PORT57), GPIO_FN(IRQ27_PORT168),
+ GPIO_FN(IRQ28_PORT56), GPIO_FN(IRQ28_PORT169),
+ GPIO_FN(IRQ29_PORT50), GPIO_FN(IRQ29_PORT170),
+ GPIO_FN(IRQ30_PORT49), GPIO_FN(IRQ30_PORT171),
+ GPIO_FN(IRQ31_PORT41), GPIO_FN(IRQ31_PORT167),
+
+ /* Function */
+
+ /* DBGT */
+ GPIO_FN(DBGMDT2), GPIO_FN(DBGMDT1), GPIO_FN(DBGMDT0),
+ GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20),
+ GPIO_FN(DBGMD21),
+
+ /* FSI */
+ GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */
+ GPIO_FN(FSIAISLD_PORT5),
+ GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */
+ GPIO_FN(FSIASPDIF_PORT18),
+ GPIO_FN(FSIAOSLD1), GPIO_FN(FSIAOSLD2), GPIO_FN(FSIAOLR),
+ GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC),
+ GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT),
+
+ /* FMSI */
+ GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
+ GPIO_FN(FMSISLD_PORT6),
+ GPIO_FN(FMSIILR), GPIO_FN(FMSIIBT), GPIO_FN(FMSIOLR),
+ GPIO_FN(FMSIOBT), GPIO_FN(FMSICK), GPIO_FN(FMSOILR),
+ GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT),
+ GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK),
+
+ /* SCIFA0 */
+ GPIO_FN(SCIFA0_SCK), GPIO_FN(SCIFA0_CTS), GPIO_FN(SCIFA0_RTS),
+ GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_TXD),
+
+ /* SCIFA1 */
+ GPIO_FN(SCIFA1_CTS), GPIO_FN(SCIFA1_SCK),
+ GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RTS),
+
+ /* SCIFA2 */
+ GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */
+ GPIO_FN(SCIFA2_SCK_PORT199),
+ GPIO_FN(SCIFA2_RXD), GPIO_FN(SCIFA2_TXD),
+ GPIO_FN(SCIFA2_CTS), GPIO_FN(SCIFA2_RTS),
+
+ /* SCIFA3 */
+ GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */
+ GPIO_FN(SCIFA3_SCK_PORT116),
+ GPIO_FN(SCIFA3_CTS_PORT117),
+ GPIO_FN(SCIFA3_RXD_PORT174),
+ GPIO_FN(SCIFA3_TXD_PORT175),
+
+ GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */
+ GPIO_FN(SCIFA3_SCK_PORT158),
+ GPIO_FN(SCIFA3_CTS_PORT162),
+ GPIO_FN(SCIFA3_RXD_PORT159),
+ GPIO_FN(SCIFA3_TXD_PORT160),
+
+ /* SCIFA4 */
+ GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */
+ GPIO_FN(SCIFA4_TXD_PORT13),
+
+ GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */
+ GPIO_FN(SCIFA4_TXD_PORT203),
+
+ GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */
+ GPIO_FN(SCIFA4_TXD_PORT93),
+
+ GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */
+ GPIO_FN(SCIFA4_SCK_PORT205),
+
+ /* SCIFA5 */
+ GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */
+ GPIO_FN(SCIFA5_RXD_PORT10),
+
+ GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */
+ GPIO_FN(SCIFA5_TXD_PORT208),
+
+ GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */
+ GPIO_FN(SCIFA5_RXD_PORT92),
+
+ GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */
+ GPIO_FN(SCIFA5_SCK_PORT206),
+
+ /* SCIFA6 */
+ GPIO_FN(SCIFA6_SCK), GPIO_FN(SCIFA6_RXD), GPIO_FN(SCIFA6_TXD),
+
+ /* SCIFA7 */
+ GPIO_FN(SCIFA7_TXD), GPIO_FN(SCIFA7_RXD),
+
+ /* SCIFAB */
+ GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */
+ GPIO_FN(SCIFB_RXD_PORT191),
+ GPIO_FN(SCIFB_TXD_PORT192),
+ GPIO_FN(SCIFB_RTS_PORT186),
+ GPIO_FN(SCIFB_CTS_PORT187),
+
+ GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */
+ GPIO_FN(SCIFB_RXD_PORT3),
+ GPIO_FN(SCIFB_TXD_PORT4),
+ GPIO_FN(SCIFB_RTS_PORT172),
+ GPIO_FN(SCIFB_CTS_PORT173),
+
+ /* LCD0 */
+ GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2),
+ GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5),
+ GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8),
+ GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11),
+ GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14),
+ GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17),
+ GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC),
+ GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN),
+ GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP),
+ GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD),
+ GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS),
+
+ GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162),
+ GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158),
+ GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159),
+ GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */
+
+ GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4),
+ GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2),
+ GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1),
+ GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */
+
+ /* LCD1 */
+ GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2),
+ GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5),
+ GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8),
+ GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11),
+ GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14),
+ GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17),
+ GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20),
+ GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23),
+ GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS),
+ GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON),
+ GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN),
+ GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP),
+
+ /* RSPI */
+ GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A),
+ GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A),
+ GPIO_FN(RSPI_MISO_A),
+
+ /* VIO CKO */
+ GPIO_FN(VIO_CKO1),
+ GPIO_FN(VIO_CKO2),
+ GPIO_FN(VIO_CKO_1),
+ GPIO_FN(VIO_CKO),
+
+ /* VIO0 */
+ GPIO_FN(VIO0_D0), GPIO_FN(VIO0_D1), GPIO_FN(VIO0_D2),
+ GPIO_FN(VIO0_D3), GPIO_FN(VIO0_D4), GPIO_FN(VIO0_D5),
+ GPIO_FN(VIO0_D6), GPIO_FN(VIO0_D7), GPIO_FN(VIO0_D8),
+ GPIO_FN(VIO0_D9), GPIO_FN(VIO0_D10), GPIO_FN(VIO0_D11),
+ GPIO_FN(VIO0_D12), GPIO_FN(VIO0_VD), GPIO_FN(VIO0_HD),
+ GPIO_FN(VIO0_CLK), GPIO_FN(VIO0_FIELD),
+
+ GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
+ GPIO_FN(VIO0_D14_PORT25),
+ GPIO_FN(VIO0_D15_PORT24),
+
+ GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
+ GPIO_FN(VIO0_D14_PORT95),
+ GPIO_FN(VIO0_D15_PORT96),
+
+ /* VIO1 */
+ GPIO_FN(VIO1_D0), GPIO_FN(VIO1_D1), GPIO_FN(VIO1_D2),
+ GPIO_FN(VIO1_D3), GPIO_FN(VIO1_D4), GPIO_FN(VIO1_D5),
+ GPIO_FN(VIO1_D6), GPIO_FN(VIO1_D7), GPIO_FN(VIO1_VD),
+ GPIO_FN(VIO1_HD), GPIO_FN(VIO1_CLK), GPIO_FN(VIO1_FIELD),
+
+ /* TPU0 */
+ GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3),
+ GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
+ GPIO_FN(TPU0TO2_PORT202),
+
+ /* SSP1 0 */
+ GPIO_FN(STP0_IPD0), GPIO_FN(STP0_IPD1), GPIO_FN(STP0_IPD2),
+ GPIO_FN(STP0_IPD3), GPIO_FN(STP0_IPD4), GPIO_FN(STP0_IPD5),
+ GPIO_FN(STP0_IPD6), GPIO_FN(STP0_IPD7), GPIO_FN(STP0_IPEN),
+ GPIO_FN(STP0_IPCLK), GPIO_FN(STP0_IPSYNC),
+
+ /* SSP1 1 */
+ GPIO_FN(STP1_IPD1), GPIO_FN(STP1_IPD2), GPIO_FN(STP1_IPD3),
+ GPIO_FN(STP1_IPD4), GPIO_FN(STP1_IPD5), GPIO_FN(STP1_IPD6),
+ GPIO_FN(STP1_IPD7), GPIO_FN(STP1_IPCLK), GPIO_FN(STP1_IPSYNC),
+
+ GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
+ GPIO_FN(STP1_IPEN_PORT187),
+
+ GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
+ GPIO_FN(STP1_IPEN_PORT193),
+
+ /* SIM */
+ GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK),
+ GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */
+ GPIO_FN(SIM_D_PORT199),
+
+ /* SDHI0 */
+ GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2),
+ GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP),
+ GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK),
+
+ /* SDHI1 */
+ GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2),
+ GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP),
+ GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK),
+
+ /* SDHI2 */
+ GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2),
+ GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD),
+
+ GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */
+ GPIO_FN(SDHI2_WP_PORT25),
+
+ GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */
+ GPIO_FN(SDHI2_CD_PORT202),
+
+ /* MSIOF2 */
+ GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK),
+ GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1),
+ GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_MCK0), GPIO_FN(MSIOF2_RSYNC),
+ GPIO_FN(MSIOF2_RSCK),
+
+ /* KEYSC */
+ GPIO_FN(KEYIN4), GPIO_FN(KEYIN5),
+ GPIO_FN(KEYIN6), GPIO_FN(KEYIN7),
+ GPIO_FN(KEYOUT0), GPIO_FN(KEYOUT1), GPIO_FN(KEYOUT2),
+ GPIO_FN(KEYOUT3), GPIO_FN(KEYOUT4), GPIO_FN(KEYOUT5),
+ GPIO_FN(KEYOUT6), GPIO_FN(KEYOUT7),
+
+ GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
+ GPIO_FN(KEYIN1_PORT44),
+ GPIO_FN(KEYIN2_PORT45),
+ GPIO_FN(KEYIN3_PORT46),
+
+ GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
+ GPIO_FN(KEYIN1_PORT57),
+ GPIO_FN(KEYIN2_PORT56),
+ GPIO_FN(KEYIN3_PORT55),
+
+ /* VOU */
+ GPIO_FN(DV_D0), GPIO_FN(DV_D1), GPIO_FN(DV_D2),
+ GPIO_FN(DV_D3), GPIO_FN(DV_D4), GPIO_FN(DV_D5),
+ GPIO_FN(DV_D6), GPIO_FN(DV_D7), GPIO_FN(DV_D8),
+ GPIO_FN(DV_D9), GPIO_FN(DV_D10), GPIO_FN(DV_D11),
+ GPIO_FN(DV_D12), GPIO_FN(DV_D13), GPIO_FN(DV_D14),
+ GPIO_FN(DV_D15), GPIO_FN(DV_CLK),
+ GPIO_FN(DV_VSYNC), GPIO_FN(DV_HSYNC),
+
+ /* MEMC */
+ GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2),
+ GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5),
+ GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8),
+ GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11),
+ GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14),
+ GPIO_FN(MEMC_AD15), GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_INT),
+ GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_NOE), GPIO_FN(MEMC_CS1),
+ GPIO_FN(MEMC_A1), GPIO_FN(MEMC_ADV), GPIO_FN(MEMC_DREQ0),
+ GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK),
+ GPIO_FN(MEMC_A0),
+
+ /* MMC */
+ GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69),
+ GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71),
+ GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73),
+ GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75),
+ GPIO_FN(MMC0_CLK_PORT66),
+ GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */
+
+ GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148),
+ GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146),
+ GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144),
+ GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142),
+ GPIO_FN(MMC1_CLK_PORT103),
+ GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */
+
+ /* MSIOF0 */
+ GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD),
+ GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1),
+ GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_TSCK),
+ GPIO_FN(MSIOF0_TSYNC),
+
+ /* MSIOF1 */
+ GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC),
+ GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
+
+ GPIO_FN(MSIOF1_SS2_PORT116), GPIO_FN(MSIOF1_SS1_PORT117),
+ GPIO_FN(MSIOF1_RXD_PORT118), GPIO_FN(MSIOF1_TXD_PORT119),
+ GPIO_FN(MSIOF1_TSYNC_PORT120),
+ GPIO_FN(MSIOF1_TSCK_PORT121), /* MSEL4CR_10_0 */
+
+ GPIO_FN(MSIOF1_SS1_PORT67), GPIO_FN(MSIOF1_TSCK_PORT72),
+ GPIO_FN(MSIOF1_TSYNC_PORT73), GPIO_FN(MSIOF1_TXD_PORT74),
+ GPIO_FN(MSIOF1_RXD_PORT75),
+ GPIO_FN(MSIOF1_SS2_PORT202), /* MSEL4CR_10_1 */
+
+ /* GPIO */
+ GPIO_FN(GPO0), GPIO_FN(GPI0),
+ GPIO_FN(GPO1), GPIO_FN(GPI1),
+
+ /* USB0 */
+ GPIO_FN(USB0_OCI), GPIO_FN(USB0_PPON), GPIO_FN(VBUS),
+
+ /* USB1 */
+ GPIO_FN(USB1_OCI), GPIO_FN(USB1_PPON),
+
+ /* BBIF1 */
+ GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_TSYNC),
+ GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC),
+ GPIO_FN(BBIF1_FLOW), GPIO_FN(BBIF1_RX_FLOW_N),
+
+ /* BBIF2 */
+ GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
+ GPIO_FN(BBIF2_RXD2_PORT60),
+ GPIO_FN(BBIF2_TSYNC2_PORT6),
+ GPIO_FN(BBIF2_TSCK2_PORT59),
+
+ GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
+ GPIO_FN(BBIF2_TXD2_PORT183),
+ GPIO_FN(BBIF2_TSCK2_PORT89),
+ GPIO_FN(BBIF2_TSYNC2_PORT184),
+
+ /* BSC / FLCTL / PCMCIA */
+ GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4),
+ GPIO_FN(CS5B), GPIO_FN(CS6A),
+ GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */
+ GPIO_FN(CS5A_PORT19),
+ GPIO_FN(IOIS16), /* ? */
+
+ GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3),
+ GPIO_FN(A4_FOE), GPIO_FN(A5_FCDE), /* share with FLCTL */
+ GPIO_FN(A6), GPIO_FN(A7), GPIO_FN(A8), GPIO_FN(A9),
+ GPIO_FN(A10), GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13),
+ GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), GPIO_FN(A17),
+ GPIO_FN(A18), GPIO_FN(A19), GPIO_FN(A20), GPIO_FN(A21),
+ GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25),
+ GPIO_FN(A26),
+
+ GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), /* share with FLCTL */
+ GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), /* share with FLCTL */
+ GPIO_FN(D4_NAF4), GPIO_FN(D5_NAF5), /* share with FLCTL */
+ GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), /* share with FLCTL */
+ GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), /* share with FLCTL */
+ GPIO_FN(D10_NAF10), GPIO_FN(D11_NAF11), /* share with FLCTL */
+ GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), /* share with FLCTL */
+ GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), /* share with FLCTL */
+ GPIO_FN(D16), GPIO_FN(D17), GPIO_FN(D18), GPIO_FN(D19),
+ GPIO_FN(D20), GPIO_FN(D21), GPIO_FN(D22), GPIO_FN(D23),
+ GPIO_FN(D24), GPIO_FN(D25), GPIO_FN(D26), GPIO_FN(D27),
+ GPIO_FN(D28), GPIO_FN(D29), GPIO_FN(D30), GPIO_FN(D31),
+
+ GPIO_FN(WE0_FWE), /* share with FLCTL */
+ GPIO_FN(WE1),
+ GPIO_FN(WE2_ICIORD), /* share with PCMCIA */
+ GPIO_FN(WE3_ICIOWR), /* share with PCMCIA */
+ GPIO_FN(CKO), GPIO_FN(BS), GPIO_FN(RDWR),
+ GPIO_FN(RD_FSC), /* share with FLCTL */
+ GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
+ GPIO_FN(WAIT_PORT90),
+
+ GPIO_FN(FCE0), GPIO_FN(FCE1), GPIO_FN(FRB), /* FLCTL */
+
+ /* IRDA */
+ GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_OUT),
+
+ /* ATAPI */
+ GPIO_FN(IDE_D0), GPIO_FN(IDE_D1), GPIO_FN(IDE_D2),
+ GPIO_FN(IDE_D3), GPIO_FN(IDE_D4), GPIO_FN(IDE_D5),
+ GPIO_FN(IDE_D6), GPIO_FN(IDE_D7), GPIO_FN(IDE_D8),
+ GPIO_FN(IDE_D9), GPIO_FN(IDE_D10), GPIO_FN(IDE_D11),
+ GPIO_FN(IDE_D12), GPIO_FN(IDE_D13), GPIO_FN(IDE_D14),
+ GPIO_FN(IDE_D15), GPIO_FN(IDE_A0), GPIO_FN(IDE_A1),
+ GPIO_FN(IDE_A2), GPIO_FN(IDE_CS0), GPIO_FN(IDE_CS1),
+ GPIO_FN(IDE_IOWR), GPIO_FN(IDE_IORD), GPIO_FN(IDE_IORDY),
+ GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION),
+ GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ),
+
+ /* RMII */
+ GPIO_FN(RMII_CRS_DV), GPIO_FN(RMII_RX_ER), GPIO_FN(RMII_RXD0),
+ GPIO_FN(RMII_RXD1), GPIO_FN(RMII_TX_EN), GPIO_FN(RMII_TXD0),
+ GPIO_FN(RMII_MDC), GPIO_FN(RMII_TXD1), GPIO_FN(RMII_MDIO),
+ GPIO_FN(RMII_REF50CK), GPIO_FN(RMII_REF125CK), /* for GMII */
+
+ /* GEther */
+ GPIO_FN(ET_TX_CLK), GPIO_FN(ET_TX_EN), GPIO_FN(ET_ETXD0),
+ GPIO_FN(ET_ETXD1), GPIO_FN(ET_ETXD2), GPIO_FN(ET_ETXD3),
+ GPIO_FN(ET_ETXD4), GPIO_FN(ET_ETXD5), /* for GEther */
+ GPIO_FN(ET_ETXD6), GPIO_FN(ET_ETXD7), /* for GEther */
+ GPIO_FN(ET_COL), GPIO_FN(ET_TX_ER), GPIO_FN(ET_RX_CLK),
+ GPIO_FN(ET_RX_DV), GPIO_FN(ET_ERXD0), GPIO_FN(ET_ERXD1),
+ GPIO_FN(ET_ERXD2), GPIO_FN(ET_ERXD3),
+ GPIO_FN(ET_ERXD4), GPIO_FN(ET_ERXD5), /* for GEther */
+ GPIO_FN(ET_ERXD6), GPIO_FN(ET_ERXD7), /* for GEther */
+ GPIO_FN(ET_RX_ER), GPIO_FN(ET_CRS), GPIO_FN(ET_MDC),
+ GPIO_FN(ET_MDIO), GPIO_FN(ET_LINK), GPIO_FN(ET_PHY_INT),
+ GPIO_FN(ET_WOL), GPIO_FN(ET_GTX_CLK),
+
+ /* DMA0 */
+ GPIO_FN(DREQ0), GPIO_FN(DACK0),
+
+ /* DMA1 */
+ GPIO_FN(DREQ1), GPIO_FN(DACK1),
+
+ /* SYSC */
+ GPIO_FN(RESETOUTS),
+
+ /* IRREM */
+ GPIO_FN(IROUT),
+
+ /* LCDC */
+ GPIO_FN(LCDC0_SELECT),
+ GPIO_FN(LCDC1_SELECT),
+
+ /* SDENC */
+ GPIO_FN(SDENC_CPG),
+ GPIO_FN(SDENC_DV_CLKI),
+
+ /* SYSC */
+ GPIO_FN(RESETP_PULLUP),
+ GPIO_FN(RESETP_PLAIN),
+
+ /* DEBUG */
+ GPIO_FN(EDEBGREQ_PULLDOWN),
+ GPIO_FN(EDEBGREQ_PULLUP),
+
+ GPIO_FN(TRACEAUD_FROM_VIO),
+ GPIO_FN(TRACEAUD_FROM_LCDC0),
+ GPIO_FN(TRACEAUD_FROM_MEMC),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+ PORTCR(0, 0xe6050000), /* PORT0CR */
+ PORTCR(1, 0xe6050001), /* PORT1CR */
+ PORTCR(2, 0xe6050002), /* PORT2CR */
+ PORTCR(3, 0xe6050003), /* PORT3CR */
+ PORTCR(4, 0xe6050004), /* PORT4CR */
+ PORTCR(5, 0xe6050005), /* PORT5CR */
+ PORTCR(6, 0xe6050006), /* PORT6CR */
+ PORTCR(7, 0xe6050007), /* PORT7CR */
+ PORTCR(8, 0xe6050008), /* PORT8CR */
+ PORTCR(9, 0xe6050009), /* PORT9CR */
+ PORTCR(10, 0xe605000a), /* PORT10CR */
+ PORTCR(11, 0xe605000b), /* PORT11CR */
+ PORTCR(12, 0xe605000c), /* PORT12CR */
+ PORTCR(13, 0xe605000d), /* PORT13CR */
+ PORTCR(14, 0xe605000e), /* PORT14CR */
+ PORTCR(15, 0xe605000f), /* PORT15CR */
+ PORTCR(16, 0xe6050010), /* PORT16CR */
+ PORTCR(17, 0xe6050011), /* PORT17CR */
+ PORTCR(18, 0xe6050012), /* PORT18CR */
+ PORTCR(19, 0xe6050013), /* PORT19CR */
+ PORTCR(20, 0xe6050014), /* PORT20CR */
+ PORTCR(21, 0xe6050015), /* PORT21CR */
+ PORTCR(22, 0xe6050016), /* PORT22CR */
+ PORTCR(23, 0xe6050017), /* PORT23CR */
+ PORTCR(24, 0xe6050018), /* PORT24CR */
+ PORTCR(25, 0xe6050019), /* PORT25CR */
+ PORTCR(26, 0xe605001a), /* PORT26CR */
+ PORTCR(27, 0xe605001b), /* PORT27CR */
+ PORTCR(28, 0xe605001c), /* PORT28CR */
+ PORTCR(29, 0xe605001d), /* PORT29CR */
+ PORTCR(30, 0xe605001e), /* PORT30CR */
+ PORTCR(31, 0xe605001f), /* PORT31CR */
+ PORTCR(32, 0xe6050020), /* PORT32CR */
+ PORTCR(33, 0xe6050021), /* PORT33CR */
+ PORTCR(34, 0xe6050022), /* PORT34CR */
+ PORTCR(35, 0xe6050023), /* PORT35CR */
+ PORTCR(36, 0xe6050024), /* PORT36CR */
+ PORTCR(37, 0xe6050025), /* PORT37CR */
+ PORTCR(38, 0xe6050026), /* PORT38CR */
+ PORTCR(39, 0xe6050027), /* PORT39CR */
+ PORTCR(40, 0xe6050028), /* PORT40CR */
+ PORTCR(41, 0xe6050029), /* PORT41CR */
+ PORTCR(42, 0xe605002a), /* PORT42CR */
+ PORTCR(43, 0xe605002b), /* PORT43CR */
+ PORTCR(44, 0xe605002c), /* PORT44CR */
+ PORTCR(45, 0xe605002d), /* PORT45CR */
+ PORTCR(46, 0xe605002e), /* PORT46CR */
+ PORTCR(47, 0xe605002f), /* PORT47CR */
+ PORTCR(48, 0xe6050030), /* PORT48CR */
+ PORTCR(49, 0xe6050031), /* PORT49CR */
+ PORTCR(50, 0xe6050032), /* PORT50CR */
+ PORTCR(51, 0xe6050033), /* PORT51CR */
+ PORTCR(52, 0xe6050034), /* PORT52CR */
+ PORTCR(53, 0xe6050035), /* PORT53CR */
+ PORTCR(54, 0xe6050036), /* PORT54CR */
+ PORTCR(55, 0xe6050037), /* PORT55CR */
+ PORTCR(56, 0xe6050038), /* PORT56CR */
+ PORTCR(57, 0xe6050039), /* PORT57CR */
+ PORTCR(58, 0xe605003a), /* PORT58CR */
+ PORTCR(59, 0xe605003b), /* PORT59CR */
+ PORTCR(60, 0xe605003c), /* PORT60CR */
+ PORTCR(61, 0xe605003d), /* PORT61CR */
+ PORTCR(62, 0xe605003e), /* PORT62CR */
+ PORTCR(63, 0xe605003f), /* PORT63CR */
+ PORTCR(64, 0xe6050040), /* PORT64CR */
+ PORTCR(65, 0xe6050041), /* PORT65CR */
+ PORTCR(66, 0xe6050042), /* PORT66CR */
+ PORTCR(67, 0xe6050043), /* PORT67CR */
+ PORTCR(68, 0xe6050044), /* PORT68CR */
+ PORTCR(69, 0xe6050045), /* PORT69CR */
+ PORTCR(70, 0xe6050046), /* PORT70CR */
+ PORTCR(71, 0xe6050047), /* PORT71CR */
+ PORTCR(72, 0xe6050048), /* PORT72CR */
+ PORTCR(73, 0xe6050049), /* PORT73CR */
+ PORTCR(74, 0xe605004a), /* PORT74CR */
+ PORTCR(75, 0xe605004b), /* PORT75CR */
+ PORTCR(76, 0xe605004c), /* PORT76CR */
+ PORTCR(77, 0xe605004d), /* PORT77CR */
+ PORTCR(78, 0xe605004e), /* PORT78CR */
+ PORTCR(79, 0xe605004f), /* PORT79CR */
+ PORTCR(80, 0xe6050050), /* PORT80CR */
+ PORTCR(81, 0xe6050051), /* PORT81CR */
+ PORTCR(82, 0xe6050052), /* PORT82CR */
+ PORTCR(83, 0xe6050053), /* PORT83CR */
+
+ PORTCR(84, 0xe6051054), /* PORT84CR */
+ PORTCR(85, 0xe6051055), /* PORT85CR */
+ PORTCR(86, 0xe6051056), /* PORT86CR */
+ PORTCR(87, 0xe6051057), /* PORT87CR */
+ PORTCR(88, 0xe6051058), /* PORT88CR */
+ PORTCR(89, 0xe6051059), /* PORT89CR */
+ PORTCR(90, 0xe605105a), /* PORT90CR */
+ PORTCR(91, 0xe605105b), /* PORT91CR */
+ PORTCR(92, 0xe605105c), /* PORT92CR */
+ PORTCR(93, 0xe605105d), /* PORT93CR */
+ PORTCR(94, 0xe605105e), /* PORT94CR */
+ PORTCR(95, 0xe605105f), /* PORT95CR */
+ PORTCR(96, 0xe6051060), /* PORT96CR */
+ PORTCR(97, 0xe6051061), /* PORT97CR */
+ PORTCR(98, 0xe6051062), /* PORT98CR */
+ PORTCR(99, 0xe6051063), /* PORT99CR */
+ PORTCR(100, 0xe6051064), /* PORT100CR */
+ PORTCR(101, 0xe6051065), /* PORT101CR */
+ PORTCR(102, 0xe6051066), /* PORT102CR */
+ PORTCR(103, 0xe6051067), /* PORT103CR */
+ PORTCR(104, 0xe6051068), /* PORT104CR */
+ PORTCR(105, 0xe6051069), /* PORT105CR */
+ PORTCR(106, 0xe605106a), /* PORT106CR */
+ PORTCR(107, 0xe605106b), /* PORT107CR */
+ PORTCR(108, 0xe605106c), /* PORT108CR */
+ PORTCR(109, 0xe605106d), /* PORT109CR */
+ PORTCR(110, 0xe605106e), /* PORT110CR */
+ PORTCR(111, 0xe605106f), /* PORT111CR */
+ PORTCR(112, 0xe6051070), /* PORT112CR */
+ PORTCR(113, 0xe6051071), /* PORT113CR */
+ PORTCR(114, 0xe6051072), /* PORT114CR */
+
+ PORTCR(115, 0xe6052073), /* PORT115CR */
+ PORTCR(116, 0xe6052074), /* PORT116CR */
+ PORTCR(117, 0xe6052075), /* PORT117CR */
+ PORTCR(118, 0xe6052076), /* PORT118CR */
+ PORTCR(119, 0xe6052077), /* PORT119CR */
+ PORTCR(120, 0xe6052078), /* PORT120CR */
+ PORTCR(121, 0xe6052079), /* PORT121CR */
+ PORTCR(122, 0xe605207a), /* PORT122CR */
+ PORTCR(123, 0xe605207b), /* PORT123CR */
+ PORTCR(124, 0xe605207c), /* PORT124CR */
+ PORTCR(125, 0xe605207d), /* PORT125CR */
+ PORTCR(126, 0xe605207e), /* PORT126CR */
+ PORTCR(127, 0xe605207f), /* PORT127CR */
+ PORTCR(128, 0xe6052080), /* PORT128CR */
+ PORTCR(129, 0xe6052081), /* PORT129CR */
+ PORTCR(130, 0xe6052082), /* PORT130CR */
+ PORTCR(131, 0xe6052083), /* PORT131CR */
+ PORTCR(132, 0xe6052084), /* PORT132CR */
+ PORTCR(133, 0xe6052085), /* PORT133CR */
+ PORTCR(134, 0xe6052086), /* PORT134CR */
+ PORTCR(135, 0xe6052087), /* PORT135CR */
+ PORTCR(136, 0xe6052088), /* PORT136CR */
+ PORTCR(137, 0xe6052089), /* PORT137CR */
+ PORTCR(138, 0xe605208a), /* PORT138CR */
+ PORTCR(139, 0xe605208b), /* PORT139CR */
+ PORTCR(140, 0xe605208c), /* PORT140CR */
+ PORTCR(141, 0xe605208d), /* PORT141CR */
+ PORTCR(142, 0xe605208e), /* PORT142CR */
+ PORTCR(143, 0xe605208f), /* PORT143CR */
+ PORTCR(144, 0xe6052090), /* PORT144CR */
+ PORTCR(145, 0xe6052091), /* PORT145CR */
+ PORTCR(146, 0xe6052092), /* PORT146CR */
+ PORTCR(147, 0xe6052093), /* PORT147CR */
+ PORTCR(148, 0xe6052094), /* PORT148CR */
+ PORTCR(149, 0xe6052095), /* PORT149CR */
+ PORTCR(150, 0xe6052096), /* PORT150CR */
+ PORTCR(151, 0xe6052097), /* PORT151CR */
+ PORTCR(152, 0xe6052098), /* PORT152CR */
+ PORTCR(153, 0xe6052099), /* PORT153CR */
+ PORTCR(154, 0xe605209a), /* PORT154CR */
+ PORTCR(155, 0xe605209b), /* PORT155CR */
+ PORTCR(156, 0xe605209c), /* PORT156CR */
+ PORTCR(157, 0xe605209d), /* PORT157CR */
+ PORTCR(158, 0xe605209e), /* PORT158CR */
+ PORTCR(159, 0xe605209f), /* PORT159CR */
+ PORTCR(160, 0xe60520a0), /* PORT160CR */
+ PORTCR(161, 0xe60520a1), /* PORT161CR */
+ PORTCR(162, 0xe60520a2), /* PORT162CR */
+ PORTCR(163, 0xe60520a3), /* PORT163CR */
+ PORTCR(164, 0xe60520a4), /* PORT164CR */
+ PORTCR(165, 0xe60520a5), /* PORT165CR */
+ PORTCR(166, 0xe60520a6), /* PORT166CR */
+ PORTCR(167, 0xe60520a7), /* PORT167CR */
+ PORTCR(168, 0xe60520a8), /* PORT168CR */
+ PORTCR(169, 0xe60520a9), /* PORT169CR */
+ PORTCR(170, 0xe60520aa), /* PORT170CR */
+ PORTCR(171, 0xe60520ab), /* PORT171CR */
+ PORTCR(172, 0xe60520ac), /* PORT172CR */
+ PORTCR(173, 0xe60520ad), /* PORT173CR */
+ PORTCR(174, 0xe60520ae), /* PORT174CR */
+ PORTCR(175, 0xe60520af), /* PORT175CR */
+ PORTCR(176, 0xe60520b0), /* PORT176CR */
+ PORTCR(177, 0xe60520b1), /* PORT177CR */
+ PORTCR(178, 0xe60520b2), /* PORT178CR */
+ PORTCR(179, 0xe60520b3), /* PORT179CR */
+ PORTCR(180, 0xe60520b4), /* PORT180CR */
+ PORTCR(181, 0xe60520b5), /* PORT181CR */
+ PORTCR(182, 0xe60520b6), /* PORT182CR */
+ PORTCR(183, 0xe60520b7), /* PORT183CR */
+ PORTCR(184, 0xe60520b8), /* PORT184CR */
+ PORTCR(185, 0xe60520b9), /* PORT185CR */
+ PORTCR(186, 0xe60520ba), /* PORT186CR */
+ PORTCR(187, 0xe60520bb), /* PORT187CR */
+ PORTCR(188, 0xe60520bc), /* PORT188CR */
+ PORTCR(189, 0xe60520bd), /* PORT189CR */
+ PORTCR(190, 0xe60520be), /* PORT190CR */
+ PORTCR(191, 0xe60520bf), /* PORT191CR */
+ PORTCR(192, 0xe60520c0), /* PORT192CR */
+ PORTCR(193, 0xe60520c1), /* PORT193CR */
+ PORTCR(194, 0xe60520c2), /* PORT194CR */
+ PORTCR(195, 0xe60520c3), /* PORT195CR */
+ PORTCR(196, 0xe60520c4), /* PORT196CR */
+ PORTCR(197, 0xe60520c5), /* PORT197CR */
+ PORTCR(198, 0xe60520c6), /* PORT198CR */
+ PORTCR(199, 0xe60520c7), /* PORT199CR */
+ PORTCR(200, 0xe60520c8), /* PORT200CR */
+ PORTCR(201, 0xe60520c9), /* PORT201CR */
+ PORTCR(202, 0xe60520ca), /* PORT202CR */
+ PORTCR(203, 0xe60520cb), /* PORT203CR */
+ PORTCR(204, 0xe60520cc), /* PORT204CR */
+ PORTCR(205, 0xe60520cd), /* PORT205CR */
+ PORTCR(206, 0xe60520ce), /* PORT206CR */
+ PORTCR(207, 0xe60520cf), /* PORT207CR */
+ PORTCR(208, 0xe60520d0), /* PORT208CR */
+ PORTCR(209, 0xe60520d1), /* PORT209CR */
+
+ PORTCR(210, 0xe60530d2), /* PORT210CR */
+ PORTCR(211, 0xe60530d3), /* PORT211CR */
+
+ { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
+ MSEL1CR_31_0, MSEL1CR_31_1,
+ MSEL1CR_30_0, MSEL1CR_30_1,
+ MSEL1CR_29_0, MSEL1CR_29_1,
+ MSEL1CR_28_0, MSEL1CR_28_1,
+ MSEL1CR_27_0, MSEL1CR_27_1,
+ MSEL1CR_26_0, MSEL1CR_26_1,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ MSEL1CR_16_0, MSEL1CR_16_1,
+ MSEL1CR_15_0, MSEL1CR_15_1,
+ MSEL1CR_14_0, MSEL1CR_14_1,
+ MSEL1CR_13_0, MSEL1CR_13_1,
+ MSEL1CR_12_0, MSEL1CR_12_1,
+ 0, 0, 0, 0,
+ MSEL1CR_9_0, MSEL1CR_9_1,
+ 0, 0,
+ MSEL1CR_7_0, MSEL1CR_7_1,
+ MSEL1CR_6_0, MSEL1CR_6_1,
+ MSEL1CR_5_0, MSEL1CR_5_1,
+ MSEL1CR_4_0, MSEL1CR_4_1,
+ MSEL1CR_3_0, MSEL1CR_3_1,
+ MSEL1CR_2_0, MSEL1CR_2_1,
+ 0, 0,
+ MSEL1CR_0_0, MSEL1CR_0_1,
+ }
+ },
+ { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ MSEL3CR_15_0, MSEL3CR_15_1,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ MSEL3CR_6_0, MSEL3CR_6_1,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ }
+ },
+ { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ MSEL4CR_19_0, MSEL4CR_19_1,
+ MSEL4CR_18_0, MSEL4CR_18_1,
+ 0, 0, 0, 0,
+ MSEL4CR_15_0, MSEL4CR_15_1,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ MSEL4CR_10_0, MSEL4CR_10_1,
+ 0, 0, 0, 0, 0, 0,
+ MSEL4CR_6_0, MSEL4CR_6_1,
+ 0, 0,
+ MSEL4CR_4_0, MSEL4CR_4_1,
+ 0, 0, 0, 0,
+ MSEL4CR_1_0, MSEL4CR_1_1,
+ 0, 0,
+ }
+ },
+ { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
+ MSEL5CR_31_0, MSEL5CR_31_1,
+ MSEL5CR_30_0, MSEL5CR_30_1,
+ MSEL5CR_29_0, MSEL5CR_29_1,
+ 0, 0,
+ MSEL5CR_27_0, MSEL5CR_27_1,
+ 0, 0,
+ MSEL5CR_25_0, MSEL5CR_25_1,
+ 0, 0,
+ MSEL5CR_23_0, MSEL5CR_23_1,
+ 0, 0,
+ MSEL5CR_21_0, MSEL5CR_21_1,
+ 0, 0,
+ MSEL5CR_19_0, MSEL5CR_19_1,
+ 0, 0,
+ MSEL5CR_17_0, MSEL5CR_17_1,
+ 0, 0,
+ MSEL5CR_15_0, MSEL5CR_15_1,
+ MSEL5CR_14_0, MSEL5CR_14_1,
+ MSEL5CR_13_0, MSEL5CR_13_1,
+ MSEL5CR_12_0, MSEL5CR_12_1,
+ MSEL5CR_11_0, MSEL5CR_11_1,
+ MSEL5CR_10_0, MSEL5CR_10_1,
+ 0, 0,
+ MSEL5CR_8_0, MSEL5CR_8_1,
+ MSEL5CR_7_0, MSEL5CR_7_1,
+ MSEL5CR_6_0, MSEL5CR_6_1,
+ MSEL5CR_5_0, MSEL5CR_5_1,
+ MSEL5CR_4_0, MSEL5CR_4_1,
+ MSEL5CR_3_0, MSEL5CR_3_1,
+ MSEL5CR_2_0, MSEL5CR_2_1,
+ 0, 0,
+ MSEL5CR_0_0, MSEL5CR_0_1,
+ }
+ },
+ { },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+ { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
+ PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
+ PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
+ PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
+ PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
+ PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
+ PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
+ PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
+ PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
+ },
+ { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
+ PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
+ PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
+ PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
+ PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
+ PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
+ PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
+ PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
+ PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
+ },
+ { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
+ PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
+ PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
+ PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
+ PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
+ },
+ { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
+ PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
+ PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
+ PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0 }
+ },
+ { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
+ PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
+ PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
+ PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
+ PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
+ },
+ { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
+ PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
+ PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
+ PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
+ PORT115_DATA, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0 }
+ },
+ { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
+ PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
+ PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
+ PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
+ PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
+ PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
+ PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
+ PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
+ PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
+ },
+ { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
+ PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
+ PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
+ PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
+ PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
+ PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
+ PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
+ PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
+ PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
+ },
+ { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, PORT209_DATA, PORT208_DATA,
+ PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
+ PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
+ PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
+ PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
+ },
+ { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ PORT211_DATA, PORT210_DATA, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0 }
+ },
+ { },
+};
+
+static struct pinmux_irq pinmux_irqs[] = {
+ PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0, PORT13_FN0), /* IRQ0A */
+ PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0), /* IRQ1A */
+ PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0, PORT12_FN0), /* IRQ2A */
+ PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0, PORT14_FN0), /* IRQ3A */
+ PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0, PORT172_FN0), /* IRQ4A */
+ PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0, PORT1_FN0), /* IRQ5A */
+ PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0), /* IRQ6A */
+ PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0), /* IRQ7A */
+ PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0), /* IRQ8A */
+ PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0), /* IRQ9A */
+ PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0), /* IRQ10A */
+ PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0), /* IRQ11A */
+ PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0, PORT97_FN0), /* IRQ12A */
+ PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0, PORT98_FN0), /* IRQ13A */
+ PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0, PORT99_FN0), /* IRQ14A */
+ PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0, PORT100_FN0), /* IRQ15A */
+ PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0, PORT211_FN0), /* IRQ16A */
+ PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0), /* IRQ17A */
+ PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0), /* IRQ18A */
+ PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0), /* IRQ19A */
+ PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0), /* IRQ20A */
+ PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0), /* IRQ21A */
+ PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0), /* IRQ22A */
+ PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0), /* IRQ23A */
+ PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0), /* IRQ24A */
+ PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0), /* IRQ25A */
+ PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0, PORT81_FN0), /* IRQ26A */
+ PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0, PORT168_FN0), /* IRQ27A */
+ PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0, PORT169_FN0), /* IRQ28A */
+ PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0, PORT170_FN0), /* IRQ29A */
+ PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0, PORT171_FN0), /* IRQ30A */
+ PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0, PORT167_FN0), /* IRQ31A */
+};
+
+static struct pinmux_info r8a7740_pinmux_info = {
+ .name = "r8a7740_pfc",
+ .reserved_id = PINMUX_RESERVED,
+ .data = { PINMUX_DATA_BEGIN,
+ PINMUX_DATA_END },
+ .input = { PINMUX_INPUT_BEGIN,
+ PINMUX_INPUT_END },
+ .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
+ PINMUX_INPUT_PULLUP_END },
+ .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN,
+ PINMUX_INPUT_PULLDOWN_END },
+ .output = { PINMUX_OUTPUT_BEGIN,
+ PINMUX_OUTPUT_END },
+ .mark = { PINMUX_MARK_BEGIN,
+ PINMUX_MARK_END },
+ .function = { PINMUX_FUNCTION_BEGIN,
+ PINMUX_FUNCTION_END },
+
+ .first_gpio = GPIO_PORT0,
+ .last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC,
+
+ .gpios = pinmux_gpios,
+ .cfg_regs = pinmux_config_regs,
+ .data_regs = pinmux_data_regs,
+
+ .gpio_data = pinmux_data,
+ .gpio_data_size = ARRAY_SIZE(pinmux_data),
+
+ .gpio_irq = pinmux_irqs,
+ .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
+};
+
+void r8a7740_pinmux_init(void)
+{
+ register_pinmux(&r8a7740_pinmux_info);
+}
--- /dev/null
+/*
+ * sh73a0 processor support - PFC hardware block
+ *
+ * Copyright (C) 2010 Renesas Solutions Corp.
+ * Copyright (C) 2010 NISHIMOTO Hiroki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <sh_pfc.h>
+#include <asm/arch/sh73a0-gpio.h>
+
+#define CPU_ALL_PORT(fn, pfx, sfx) \
+ PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
+ PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx), \
+ PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx), \
+ PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx), \
+ PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx), \
+ PORT_10(fn, pfx##10, sfx), \
+ PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
+ PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
+ PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \
+ PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \
+ PORT_1(fn, pfx##118, sfx), \
+ PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
+ PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \
+ PORT_10(fn, pfx##15, sfx), \
+ PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \
+ PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \
+ PORT_1(fn, pfx##164, sfx), \
+ PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
+ PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
+ PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
+ PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
+ PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
+ PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
+ PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
+ PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx), \
+ PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
+ PORT_1(fn, pfx##282, sfx), \
+ PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
+ PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx)
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ PINMUX_DATA_BEGIN,
+ PORT_ALL(DATA), /* PORT0_DATA -> PORT309_DATA */
+ PINMUX_DATA_END,
+
+ PINMUX_INPUT_BEGIN,
+ PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */
+ PINMUX_INPUT_END,
+
+ PINMUX_INPUT_PULLUP_BEGIN,
+ PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */
+ PINMUX_INPUT_PULLUP_END,
+
+ PINMUX_INPUT_PULLDOWN_BEGIN,
+ PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */
+ PINMUX_INPUT_PULLDOWN_END,
+
+ PINMUX_OUTPUT_BEGIN,
+ PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */
+ PINMUX_OUTPUT_END,
+
+ PINMUX_FUNCTION_BEGIN,
+ PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */
+ PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */
+ PORT_ALL(FN0), /* PORT0_FN0 -> PORT309_FN0 */
+ PORT_ALL(FN1), /* PORT0_FN1 -> PORT309_FN1 */
+ PORT_ALL(FN2), /* PORT0_FN2 -> PORT309_FN2 */
+ PORT_ALL(FN3), /* PORT0_FN3 -> PORT309_FN3 */
+ PORT_ALL(FN4), /* PORT0_FN4 -> PORT309_FN4 */
+ PORT_ALL(FN5), /* PORT0_FN5 -> PORT309_FN5 */
+ PORT_ALL(FN6), /* PORT0_FN6 -> PORT309_FN6 */
+ PORT_ALL(FN7), /* PORT0_FN7 -> PORT309_FN7 */
+
+ MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
+ MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
+ MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
+ MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
+ MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
+ MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
+ MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
+ MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
+ MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
+ MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
+ MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
+ MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
+ MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
+ MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
+ MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
+ MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
+ MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
+ MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
+ MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
+ MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
+ MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
+ MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
+ MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
+ MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
+ MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
+ MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
+ MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
+ MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
+ MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
+ MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
+ MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
+ MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
+ MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
+ MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
+ MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
+ MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
+ MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
+ MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
+ MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
+ MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
+ MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
+ MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
+ PINMUX_FUNCTION_END,
+
+ PINMUX_MARK_BEGIN,
+ /* Hardware manual Table 25-1 (Function 0-7) */
+ VBUS_0_MARK,
+ GPI0_MARK,
+ GPI1_MARK,
+ GPI2_MARK,
+ GPI3_MARK,
+ GPI4_MARK,
+ GPI5_MARK,
+ GPI6_MARK,
+ GPI7_MARK,
+ SCIFA7_RXD_MARK,
+ SCIFA7_CTS__MARK,
+ GPO7_MARK, MFG0_OUT2_MARK,
+ GPO6_MARK, MFG1_OUT2_MARK,
+ GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
+ SCIFA0_TXD_MARK,
+ SCIFA7_TXD_MARK,
+ SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
+ GPO0_MARK,
+ GPO1_MARK,
+ GPO2_MARK, STATUS0_MARK,
+ GPO3_MARK, STATUS1_MARK,
+ GPO4_MARK, STATUS2_MARK,
+ VINT_MARK,
+ TCKON_MARK,
+ XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
+ MFG0_OUT1_MARK, PORT27_IROUT_MARK,
+ XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
+ PORT28_TPU1TO1_MARK,
+ SIM_RST_MARK, PORT29_TPU1TO1_MARK,
+ SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
+ SIM_D_MARK, PORT31_IROUT_MARK,
+ SCIFA4_TXD_MARK,
+ SCIFA4_RXD_MARK, XWUP_MARK,
+ SCIFA4_RTS__MARK,
+ SCIFA4_CTS__MARK,
+ FSIBOBT_MARK, FSIBIBT_MARK,
+ FSIBOLR_MARK, FSIBILR_MARK,
+ FSIBOSLD_MARK,
+ FSIBISLD_MARK,
+ VACK_MARK,
+ XTAL1L_MARK,
+ SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
+ SCIFA0_RXD_MARK,
+ SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
+ FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
+ FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
+ FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
+ FSICISLD_MARK, FSIDISLD_MARK,
+ FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
+ FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
+
+ FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
+ FSIAOSLD_MARK, BBIF2_TXD2_MARK,
+ FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
+ PORT53_FSICSPDIF_MARK,
+ FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
+ FSICCK_MARK, FSICOMC_MARK,
+ FSIAISLD_MARK, TPU0TO0_MARK,
+ A0_MARK, BS__MARK,
+ A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
+ A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
+ A14_MARK, KEYOUT5_MARK,
+ A15_MARK, KEYOUT4_MARK,
+ A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
+ A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
+ A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
+ A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
+ A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
+ A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
+ A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
+ A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
+ A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
+ A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
+ A26_MARK, KEYIN6_MARK,
+ KEYIN7_MARK,
+ D0_NAF0_MARK,
+ D1_NAF1_MARK,
+ D2_NAF2_MARK,
+ D3_NAF3_MARK,
+ D4_NAF4_MARK,
+ D5_NAF5_MARK,
+ D6_NAF6_MARK,
+ D7_NAF7_MARK,
+ D8_NAF8_MARK,
+ D9_NAF9_MARK,
+ D10_NAF10_MARK,
+ D11_NAF11_MARK,
+ D12_NAF12_MARK,
+ D13_NAF13_MARK,
+ D14_NAF14_MARK,
+ D15_NAF15_MARK,
+ CS4__MARK,
+ CS5A__MARK, PORT91_RDWR_MARK,
+ CS5B__MARK, FCE1__MARK,
+ CS6B__MARK, DACK0_MARK,
+ FCE0__MARK, CS6A__MARK,
+ WAIT__MARK, DREQ0_MARK,
+ RD__FSC_MARK,
+ WE0__FWE_MARK, RDWR_FWE_MARK,
+ WE1__MARK,
+ FRB_MARK,
+ CKO_MARK,
+ NBRSTOUT__MARK,
+ NBRST__MARK,
+ BBIF2_TXD_MARK,
+ BBIF2_RXD_MARK,
+ BBIF2_SYNC_MARK,
+ BBIF2_SCK_MARK,
+ SCIFA3_CTS__MARK, MFG3_IN2_MARK,
+ SCIFA3_RXD_MARK, MFG3_IN1_MARK,
+ BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
+ SCIFA3_TXD_MARK,
+ HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
+ HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
+ HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
+ HSI_TX_READY_MARK, BBIF1_TXD_MARK,
+ HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
+ PORT115_I2C_SCL3_MARK,
+ HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
+ PORT116_I2C_SDA3_MARK,
+ HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
+ HSI_TX_FLAG_MARK,
+ VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
+
+ VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
+ VIO2_HD_MARK, LCD2D1_MARK,
+ VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
+ VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
+ PORT131_KEYOUT11_MARK, LCD2D11_MARK,
+ VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
+ PORT132_KEYOUT10_MARK, LCD2D12_MARK,
+ VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
+ VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
+ VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
+ VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
+ VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
+ VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
+ VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
+ VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
+ VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
+ VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
+ VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
+ VIO2_D5_MARK, LCD2D3_MARK,
+ VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
+ VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
+ PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
+ VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
+ LCD2D18_MARK,
+ VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
+ VIO_CKO_MARK,
+ A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
+ MFG0_IN2_MARK,
+ TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
+ TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
+ TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
+ SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
+ SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
+ SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
+ SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
+ DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
+ PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
+ PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
+ PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
+ PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
+ PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
+ LCDD0_MARK,
+ LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
+ LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
+ LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
+ LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
+ LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
+ LCDD6_MARK,
+ LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
+ LCDD8_MARK, D16_MARK,
+ LCDD9_MARK, D17_MARK,
+ LCDD10_MARK, D18_MARK,
+ LCDD11_MARK, D19_MARK,
+ LCDD12_MARK, D20_MARK,
+ LCDD13_MARK, D21_MARK,
+ LCDD14_MARK, D22_MARK,
+ LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
+ LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
+ LCDD17_MARK, D25_MARK,
+ LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
+ LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
+ LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
+ LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
+ LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
+ LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
+ LCDDCK_MARK, LCDWR__MARK,
+ LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
+ VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
+ LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
+ PORT218_VIO_CKOR_MARK,
+ LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
+ MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
+ LCDVSYN_MARK, LCDVSYN2_MARK,
+ LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
+ MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
+ LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
+ VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
+
+ SCIFA1_TXD_MARK, OVCN2_MARK,
+ EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
+ SCIFA1_RTS__MARK, IDIN_MARK,
+ SCIFA1_RXD_MARK,
+ SCIFA1_CTS__MARK, MFG1_IN1_MARK,
+ MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
+ MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
+ MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
+ MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
+ MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
+ MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
+ MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
+ MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
+ MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
+ MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
+ SCIFA6_TXD_MARK,
+ PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
+ PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
+ PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
+ PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
+ MSIOF2R_RXD_MARK,
+ PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
+ MSIOF2R_TXD_MARK,
+ PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
+ TPU1TO0_MARK,
+ PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
+ TPU3TO1_MARK,
+ PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
+ TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
+ PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
+ MSIOF2R_TSYNC_MARK,
+ SDHICLK0_MARK,
+ SDHICD0_MARK,
+ SDHID0_0_MARK,
+ SDHID0_1_MARK,
+ SDHID0_2_MARK,
+ SDHID0_3_MARK,
+ SDHICMD0_MARK,
+ SDHIWP0_MARK,
+ SDHICLK1_MARK,
+ SDHID1_0_MARK, TS_SPSYNC2_MARK,
+ SDHID1_1_MARK, TS_SDAT2_MARK,
+ SDHID1_2_MARK, TS_SDEN2_MARK,
+ SDHID1_3_MARK, TS_SCK2_MARK,
+ SDHICMD1_MARK,
+ SDHICLK2_MARK,
+ SDHID2_0_MARK, TS_SPSYNC4_MARK,
+ SDHID2_1_MARK, TS_SDAT4_MARK,
+ SDHID2_2_MARK, TS_SDEN4_MARK,
+ SDHID2_3_MARK, TS_SCK4_MARK,
+ SDHICMD2_MARK,
+ MMCCLK0_MARK,
+ MMCD0_0_MARK,
+ MMCD0_1_MARK,
+ MMCD0_2_MARK,
+ MMCD0_3_MARK,
+ MMCD0_4_MARK, TS_SPSYNC5_MARK,
+ MMCD0_5_MARK, TS_SDAT5_MARK,
+ MMCD0_6_MARK, TS_SDEN5_MARK,
+ MMCD0_7_MARK, TS_SCK5_MARK,
+ MMCCMD0_MARK,
+ RESETOUTS__MARK, EXTAL2OUT_MARK,
+ MCP_WAIT__MCP_FRB_MARK,
+ MCP_CKO_MARK, MMCCLK1_MARK,
+ MCP_D15_MCP_NAF15_MARK,
+ MCP_D14_MCP_NAF14_MARK,
+ MCP_D13_MCP_NAF13_MARK,
+ MCP_D12_MCP_NAF12_MARK,
+ MCP_D11_MCP_NAF11_MARK,
+ MCP_D10_MCP_NAF10_MARK,
+ MCP_D9_MCP_NAF9_MARK,
+ MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
+ MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
+
+ MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
+ MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
+ MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
+ MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
+ MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
+ MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
+ MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
+ MCP_NBRSTOUT__MARK,
+ MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
+
+ /* MSEL2 special cases */
+ TSIF2_TS_XX1_MARK,
+ TSIF2_TS_XX2_MARK,
+ TSIF2_TS_XX3_MARK,
+ TSIF2_TS_XX4_MARK,
+ TSIF2_TS_XX5_MARK,
+ TSIF1_TS_XX1_MARK,
+ TSIF1_TS_XX2_MARK,
+ TSIF1_TS_XX3_MARK,
+ TSIF1_TS_XX4_MARK,
+ TSIF1_TS_XX5_MARK,
+ TSIF0_TS_XX1_MARK,
+ TSIF0_TS_XX2_MARK,
+ TSIF0_TS_XX3_MARK,
+ TSIF0_TS_XX4_MARK,
+ TSIF0_TS_XX5_MARK,
+ MST1_TS_XX1_MARK,
+ MST1_TS_XX2_MARK,
+ MST1_TS_XX3_MARK,
+ MST1_TS_XX4_MARK,
+ MST1_TS_XX5_MARK,
+ MST0_TS_XX1_MARK,
+ MST0_TS_XX2_MARK,
+ MST0_TS_XX3_MARK,
+ MST0_TS_XX4_MARK,
+ MST0_TS_XX5_MARK,
+
+ /* MSEL3 special cases */
+ SDHI0_VCCQ_MC0_ON_MARK,
+ SDHI0_VCCQ_MC0_OFF_MARK,
+ DEBUG_MON_VIO_MARK,
+ DEBUG_MON_LCDD_MARK,
+ LCDC_LCDC0_MARK,
+ LCDC_LCDC1_MARK,
+
+ /* MSEL4 special cases */
+ IRQ9_MEM_INT_MARK,
+ IRQ9_MCP_INT_MARK,
+ A11_MARK,
+ KEYOUT8_MARK,
+ TPU4TO3_MARK,
+ RESETA_N_PU_ON_MARK,
+ RESETA_N_PU_OFF_MARK,
+ EDBGREQ_PD_MARK,
+ EDBGREQ_PU_MARK,
+
+ /* Functions with pull-ups */
+ KEYIN0_PU_MARK,
+ KEYIN1_PU_MARK,
+ KEYIN2_PU_MARK,
+ KEYIN3_PU_MARK,
+ KEYIN4_PU_MARK,
+ KEYIN5_PU_MARK,
+ KEYIN6_PU_MARK,
+ KEYIN7_PU_MARK,
+ SDHICD0_PU_MARK,
+ SDHID0_0_PU_MARK,
+ SDHID0_1_PU_MARK,
+ SDHID0_2_PU_MARK,
+ SDHID0_3_PU_MARK,
+ SDHICMD0_PU_MARK,
+ SDHIWP0_PU_MARK,
+ SDHID1_0_PU_MARK,
+ SDHID1_1_PU_MARK,
+ SDHID1_2_PU_MARK,
+ SDHID1_3_PU_MARK,
+ SDHICMD1_PU_MARK,
+ SDHID2_0_PU_MARK,
+ SDHID2_1_PU_MARK,
+ SDHID2_2_PU_MARK,
+ SDHID2_3_PU_MARK,
+ SDHICMD2_PU_MARK,
+ MMCCMD0_PU_MARK,
+ MMCCMD1_PU_MARK,
+ MMCD0_0_PU_MARK,
+ MMCD0_1_PU_MARK,
+ MMCD0_2_PU_MARK,
+ MMCD0_3_PU_MARK,
+ MMCD0_4_PU_MARK,
+ MMCD0_5_PU_MARK,
+ MMCD0_6_PU_MARK,
+ MMCD0_7_PU_MARK,
+ FSIBISLD_PU_MARK,
+ FSIACK_PU_MARK,
+ FSIAILR_PU_MARK,
+ FSIAIBT_PU_MARK,
+ FSIAISLD_PU_MARK,
+
+ PINMUX_MARK_END,
+};
+
+static unsigned short pinmux_data[] = {
+ /* specify valid pin states for each pin in GPIO mode */
+
+ /* Table 25-1 (I/O and Pull U/D) */
+ PORT_DATA_I_PD(0),
+ PORT_DATA_I_PU(1),
+ PORT_DATA_I_PU(2),
+ PORT_DATA_I_PU(3),
+ PORT_DATA_I_PU(4),
+ PORT_DATA_I_PU(5),
+ PORT_DATA_I_PU(6),
+ PORT_DATA_I_PU(7),
+ PORT_DATA_I_PU(8),
+ PORT_DATA_I_PD(9),
+ PORT_DATA_I_PD(10),
+ PORT_DATA_I_PU_PD(11),
+ PORT_DATA_IO_PU_PD(12),
+ PORT_DATA_IO_PU_PD(13),
+ PORT_DATA_IO_PU_PD(14),
+ PORT_DATA_IO_PU_PD(15),
+ PORT_DATA_IO_PD(16),
+ PORT_DATA_IO_PD(17),
+ PORT_DATA_IO_PU(18),
+ PORT_DATA_IO_PU(19),
+ PORT_DATA_O(20),
+ PORT_DATA_O(21),
+ PORT_DATA_O(22),
+ PORT_DATA_O(23),
+ PORT_DATA_O(24),
+ PORT_DATA_I_PD(25),
+ PORT_DATA_I_PD(26),
+ PORT_DATA_IO_PU(27),
+ PORT_DATA_IO_PU(28),
+ PORT_DATA_IO_PD(29),
+ PORT_DATA_IO_PD(30),
+ PORT_DATA_IO_PU(31),
+ PORT_DATA_IO_PD(32),
+ PORT_DATA_I_PU_PD(33),
+ PORT_DATA_IO_PD(34),
+ PORT_DATA_I_PU_PD(35),
+ PORT_DATA_IO_PD(36),
+ PORT_DATA_IO(37),
+ PORT_DATA_O(38),
+ PORT_DATA_I_PU(39),
+ PORT_DATA_I_PU_PD(40),
+ PORT_DATA_O(41),
+ PORT_DATA_IO_PD(42),
+ PORT_DATA_IO_PU_PD(43),
+ PORT_DATA_IO_PU_PD(44),
+ PORT_DATA_IO_PD(45),
+ PORT_DATA_IO_PD(46),
+ PORT_DATA_IO_PD(47),
+ PORT_DATA_I_PD(48),
+ PORT_DATA_IO_PU_PD(49),
+ PORT_DATA_IO_PD(50),
+
+ PORT_DATA_IO_PD(51),
+ PORT_DATA_O(52),
+ PORT_DATA_IO_PU_PD(53),
+ PORT_DATA_IO_PU_PD(54),
+ PORT_DATA_IO_PD(55),
+ PORT_DATA_I_PU_PD(56),
+ PORT_DATA_IO(57),
+ PORT_DATA_IO(58),
+ PORT_DATA_IO(59),
+ PORT_DATA_IO(60),
+ PORT_DATA_IO(61),
+ PORT_DATA_IO_PD(62),
+ PORT_DATA_IO_PD(63),
+ PORT_DATA_IO_PU_PD(64),
+ PORT_DATA_IO_PD(65),
+ PORT_DATA_IO_PU_PD(66),
+ PORT_DATA_IO_PU_PD(67),
+ PORT_DATA_IO_PU_PD(68),
+ PORT_DATA_IO_PU_PD(69),
+ PORT_DATA_IO_PU_PD(70),
+ PORT_DATA_IO_PU_PD(71),
+ PORT_DATA_IO_PU_PD(72),
+ PORT_DATA_I_PU_PD(73),
+ PORT_DATA_IO_PU(74),
+ PORT_DATA_IO_PU(75),
+ PORT_DATA_IO_PU(76),
+ PORT_DATA_IO_PU(77),
+ PORT_DATA_IO_PU(78),
+ PORT_DATA_IO_PU(79),
+ PORT_DATA_IO_PU(80),
+ PORT_DATA_IO_PU(81),
+ PORT_DATA_IO_PU(82),
+ PORT_DATA_IO_PU(83),
+ PORT_DATA_IO_PU(84),
+ PORT_DATA_IO_PU(85),
+ PORT_DATA_IO_PU(86),
+ PORT_DATA_IO_PU(87),
+ PORT_DATA_IO_PU(88),
+ PORT_DATA_IO_PU(89),
+ PORT_DATA_O(90),
+ PORT_DATA_IO_PU(91),
+ PORT_DATA_O(92),
+ PORT_DATA_IO_PU(93),
+ PORT_DATA_O(94),
+ PORT_DATA_I_PU_PD(95),
+ PORT_DATA_IO(96),
+ PORT_DATA_IO(97),
+ PORT_DATA_IO(98),
+ PORT_DATA_I_PU(99),
+ PORT_DATA_O(100),
+ PORT_DATA_O(101),
+ PORT_DATA_I_PU(102),
+ PORT_DATA_IO_PD(103),
+ PORT_DATA_I_PU_PD(104),
+ PORT_DATA_I_PD(105),
+ PORT_DATA_I_PD(106),
+ PORT_DATA_I_PU_PD(107),
+ PORT_DATA_I_PU_PD(108),
+ PORT_DATA_IO_PD(109),
+ PORT_DATA_IO_PD(110),
+ PORT_DATA_IO_PU_PD(111),
+ PORT_DATA_IO_PU_PD(112),
+ PORT_DATA_IO_PU_PD(113),
+ PORT_DATA_IO_PD(114),
+ PORT_DATA_IO_PU(115),
+ PORT_DATA_IO_PU(116),
+ PORT_DATA_IO_PU_PD(117),
+ PORT_DATA_IO_PU_PD(118),
+ PORT_DATA_IO_PD(128),
+
+ PORT_DATA_IO_PD(129),
+ PORT_DATA_IO_PU_PD(130),
+ PORT_DATA_IO_PD(131),
+ PORT_DATA_IO_PD(132),
+ PORT_DATA_IO_PD(133),
+ PORT_DATA_IO_PU_PD(134),
+ PORT_DATA_IO_PU_PD(135),
+ PORT_DATA_IO_PU_PD(136),
+ PORT_DATA_IO_PU_PD(137),
+ PORT_DATA_IO_PD(138),
+ PORT_DATA_IO_PD(139),
+ PORT_DATA_IO_PD(140),
+ PORT_DATA_IO_PD(141),
+ PORT_DATA_IO_PD(142),
+ PORT_DATA_IO_PD(143),
+ PORT_DATA_IO_PU_PD(144),
+ PORT_DATA_IO_PD(145),
+ PORT_DATA_IO_PU_PD(146),
+ PORT_DATA_IO_PU_PD(147),
+ PORT_DATA_IO_PU_PD(148),
+ PORT_DATA_IO_PU_PD(149),
+ PORT_DATA_I_PU_PD(150),
+ PORT_DATA_IO_PU_PD(151),
+ PORT_DATA_IO_PU_PD(152),
+ PORT_DATA_IO_PD(153),
+ PORT_DATA_IO_PD(154),
+ PORT_DATA_I_PU_PD(155),
+ PORT_DATA_IO_PU_PD(156),
+ PORT_DATA_I_PD(157),
+ PORT_DATA_IO_PD(158),
+ PORT_DATA_IO_PU_PD(159),
+ PORT_DATA_IO_PU_PD(160),
+ PORT_DATA_I_PU_PD(161),
+ PORT_DATA_I_PU_PD(162),
+ PORT_DATA_IO_PU_PD(163),
+ PORT_DATA_I_PU_PD(164),
+ PORT_DATA_IO_PD(192),
+ PORT_DATA_IO_PU_PD(193),
+ PORT_DATA_IO_PD(194),
+ PORT_DATA_IO_PU_PD(195),
+ PORT_DATA_IO_PD(196),
+ PORT_DATA_IO_PD(197),
+ PORT_DATA_IO_PD(198),
+ PORT_DATA_IO_PD(199),
+ PORT_DATA_IO_PU_PD(200),
+ PORT_DATA_IO_PU_PD(201),
+ PORT_DATA_IO_PU_PD(202),
+ PORT_DATA_IO_PU_PD(203),
+ PORT_DATA_IO_PU_PD(204),
+ PORT_DATA_IO_PU_PD(205),
+ PORT_DATA_IO_PU_PD(206),
+ PORT_DATA_IO_PD(207),
+ PORT_DATA_IO_PD(208),
+ PORT_DATA_IO_PD(209),
+ PORT_DATA_IO_PD(210),
+ PORT_DATA_IO_PD(211),
+ PORT_DATA_IO_PD(212),
+ PORT_DATA_IO_PD(213),
+ PORT_DATA_IO_PU_PD(214),
+ PORT_DATA_IO_PU_PD(215),
+ PORT_DATA_IO_PD(216),
+ PORT_DATA_IO_PD(217),
+ PORT_DATA_O(218),
+ PORT_DATA_IO_PD(219),
+ PORT_DATA_IO_PD(220),
+ PORT_DATA_IO_PU_PD(221),
+ PORT_DATA_IO_PU_PD(222),
+ PORT_DATA_I_PU_PD(223),
+ PORT_DATA_I_PU_PD(224),
+
+ PORT_DATA_IO_PU_PD(225),
+ PORT_DATA_O(226),
+ PORT_DATA_IO_PU_PD(227),
+ PORT_DATA_I_PU_PD(228),
+ PORT_DATA_I_PD(229),
+ PORT_DATA_IO(230),
+ PORT_DATA_IO_PU_PD(231),
+ PORT_DATA_IO_PU_PD(232),
+ PORT_DATA_I_PU_PD(233),
+ PORT_DATA_IO_PU_PD(234),
+ PORT_DATA_IO_PU_PD(235),
+ PORT_DATA_IO_PU_PD(236),
+ PORT_DATA_IO_PD(237),
+ PORT_DATA_IO_PU_PD(238),
+ PORT_DATA_IO_PU_PD(239),
+ PORT_DATA_IO_PU_PD(240),
+ PORT_DATA_O(241),
+ PORT_DATA_I_PD(242),
+ PORT_DATA_IO_PU_PD(243),
+ PORT_DATA_IO_PU_PD(244),
+ PORT_DATA_IO_PU_PD(245),
+ PORT_DATA_IO_PU_PD(246),
+ PORT_DATA_IO_PU_PD(247),
+ PORT_DATA_IO_PU_PD(248),
+ PORT_DATA_IO_PU_PD(249),
+ PORT_DATA_IO_PU_PD(250),
+ PORT_DATA_IO_PU_PD(251),
+ PORT_DATA_IO_PU_PD(252),
+ PORT_DATA_IO_PU_PD(253),
+ PORT_DATA_IO_PU_PD(254),
+ PORT_DATA_IO_PU_PD(255),
+ PORT_DATA_IO_PU_PD(256),
+ PORT_DATA_IO_PU_PD(257),
+ PORT_DATA_IO_PU_PD(258),
+ PORT_DATA_IO_PU_PD(259),
+ PORT_DATA_IO_PU_PD(260),
+ PORT_DATA_IO_PU_PD(261),
+ PORT_DATA_IO_PU_PD(262),
+ PORT_DATA_IO_PU_PD(263),
+ PORT_DATA_IO_PU_PD(264),
+ PORT_DATA_IO_PU_PD(265),
+ PORT_DATA_IO_PU_PD(266),
+ PORT_DATA_IO_PU_PD(267),
+ PORT_DATA_IO_PU_PD(268),
+ PORT_DATA_IO_PU_PD(269),
+ PORT_DATA_IO_PU_PD(270),
+ PORT_DATA_IO_PU_PD(271),
+ PORT_DATA_IO_PU_PD(272),
+ PORT_DATA_IO_PU_PD(273),
+ PORT_DATA_IO_PU_PD(274),
+ PORT_DATA_IO_PU_PD(275),
+ PORT_DATA_IO_PU_PD(276),
+ PORT_DATA_IO_PU_PD(277),
+ PORT_DATA_IO_PU_PD(278),
+ PORT_DATA_IO_PU_PD(279),
+ PORT_DATA_IO_PU_PD(280),
+ PORT_DATA_O(281),
+ PORT_DATA_O(282),
+ PORT_DATA_I_PU(288),
+ PORT_DATA_IO_PU_PD(289),
+ PORT_DATA_IO_PU_PD(290),
+ PORT_DATA_IO_PU_PD(291),
+ PORT_DATA_IO_PU_PD(292),
+ PORT_DATA_IO_PU_PD(293),
+ PORT_DATA_IO_PU_PD(294),
+ PORT_DATA_IO_PU_PD(295),
+ PORT_DATA_IO_PU_PD(296),
+ PORT_DATA_IO_PU_PD(297),
+ PORT_DATA_IO_PU_PD(298),
+
+ PORT_DATA_IO_PU_PD(299),
+ PORT_DATA_IO_PU_PD(300),
+ PORT_DATA_IO_PU_PD(301),
+ PORT_DATA_IO_PU_PD(302),
+ PORT_DATA_IO_PU_PD(303),
+ PORT_DATA_IO_PU_PD(304),
+ PORT_DATA_IO_PU_PD(305),
+ PORT_DATA_O(306),
+ PORT_DATA_O(307),
+ PORT_DATA_I_PU(308),
+ PORT_DATA_O(309),
+
+ /* Table 25-1 (Function 0-7) */
+ PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
+ PINMUX_DATA(GPI0_MARK, PORT1_FN1),
+ PINMUX_DATA(GPI1_MARK, PORT2_FN1),
+ PINMUX_DATA(GPI2_MARK, PORT3_FN1),
+ PINMUX_DATA(GPI3_MARK, PORT4_FN1),
+ PINMUX_DATA(GPI4_MARK, PORT5_FN1),
+ PINMUX_DATA(GPI5_MARK, PORT6_FN1),
+ PINMUX_DATA(GPI6_MARK, PORT7_FN1),
+ PINMUX_DATA(GPI7_MARK, PORT8_FN1),
+ PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
+ PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
+ PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
+ PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
+ PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
+ PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
+ PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
+ PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
+ PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
+ PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
+ PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
+ PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
+ PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
+ PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
+ PINMUX_DATA(GPO0_MARK, PORT20_FN1),
+ PINMUX_DATA(GPO1_MARK, PORT21_FN1),
+ PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
+ PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
+ PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
+ PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
+ PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
+ PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
+ PINMUX_DATA(VINT_MARK, PORT25_FN1),
+ PINMUX_DATA(TCKON_MARK, PORT26_FN1),
+ PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
+ PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
+ MSEL2CR_MSEL16_1), \
+ PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
+ MSEL2CR_MSEL18_1), \
+ PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
+ PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
+ PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
+ PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
+ MSEL2CR_MSEL16_1), \
+ PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
+ MSEL2CR_MSEL18_1), \
+ PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
+ PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
+ PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
+ PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
+ PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
+ PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
+ PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
+ PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
+ PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
+ PINMUX_DATA(XWUP_MARK, PORT33_FN3),
+ PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
+ PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
+ PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
+ PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
+ PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
+ PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
+ PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
+ PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
+ PINMUX_DATA(VACK_MARK, PORT40_FN1),
+ PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
+ PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
+ PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
+ PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
+ PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
+ PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
+ PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
+ PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
+ PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
+ PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
+ PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
+ PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
+ PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
+ PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
+ PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
+ PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
+ PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
+ PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
+ PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
+ PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
+ PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
+ PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
+ PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
+ PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
+ PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
+ PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
+
+ PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
+ PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
+ PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
+ PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
+ PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
+ PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
+ PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
+ PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
+ PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
+ PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
+ PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
+ PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
+ PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
+ PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
+ PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
+ PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
+ PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
+ PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
+ PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
+ PINMUX_DATA(A0_MARK, PORT57_FN1), \
+ PINMUX_DATA(BS__MARK, PORT57_FN2),
+ PINMUX_DATA(A12_MARK, PORT58_FN1), \
+ PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
+ PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
+ PINMUX_DATA(A13_MARK, PORT59_FN1), \
+ PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
+ PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
+ PINMUX_DATA(A14_MARK, PORT60_FN1), \
+ PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
+ PINMUX_DATA(A15_MARK, PORT61_FN1), \
+ PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
+ PINMUX_DATA(A16_MARK, PORT62_FN1), \
+ PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
+ PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
+ PINMUX_DATA(A17_MARK, PORT63_FN1), \
+ PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
+ PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
+ PINMUX_DATA(A18_MARK, PORT64_FN1), \
+ PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
+ PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
+ PINMUX_DATA(A19_MARK, PORT65_FN1), \
+ PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
+ PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
+ PINMUX_DATA(A20_MARK, PORT66_FN1), \
+ PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
+ PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
+ PINMUX_DATA(A21_MARK, PORT67_FN1), \
+ PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
+ PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
+ PINMUX_DATA(A22_MARK, PORT68_FN1), \
+ PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
+ PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
+ PINMUX_DATA(A23_MARK, PORT69_FN1), \
+ PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
+ PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
+ PINMUX_DATA(A24_MARK, PORT70_FN1), \
+ PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
+ PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
+ PINMUX_DATA(A25_MARK, PORT71_FN1), \
+ PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
+ PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
+ PINMUX_DATA(A26_MARK, PORT72_FN1), \
+ PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
+ PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
+ PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
+ PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
+ PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
+ PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
+ PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
+ PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
+ PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
+ PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
+ PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
+ PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
+ PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
+ PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
+ PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
+ PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
+ PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
+ PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
+ PINMUX_DATA(CS4__MARK, PORT90_FN1),
+ PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
+ PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
+ PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
+ PINMUX_DATA(FCE1__MARK, PORT92_FN2),
+ PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
+ PINMUX_DATA(DACK0_MARK, PORT93_FN4),
+ PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
+ PINMUX_DATA(CS6A__MARK, PORT94_FN2),
+ PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
+ PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
+ PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
+ PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
+ PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
+ PINMUX_DATA(WE1__MARK, PORT98_FN1),
+ PINMUX_DATA(FRB_MARK, PORT99_FN1),
+ PINMUX_DATA(CKO_MARK, PORT100_FN1),
+ PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
+ PINMUX_DATA(NBRST__MARK, PORT102_FN1),
+ PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
+ PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
+ PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
+ PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
+ PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
+ PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
+ PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
+ PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
+ PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
+ PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
+ PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
+ PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
+ PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
+ PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
+ PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
+ PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
+ PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
+ PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
+ PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
+ PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
+ PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
+ PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
+ PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
+ PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
+ PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
+ PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
+ PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
+ PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
+ PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
+ PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
+ PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
+ PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
+ PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
+ PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
+ PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
+ PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
+
+ PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
+ PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
+ PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
+ PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
+ PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
+ PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
+ PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
+ MSEL4CR_MSEL10_1), \
+ PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
+ PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
+ PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
+ PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
+ PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
+ PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
+ PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
+ PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
+ PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
+ PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
+ PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
+ PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
+ PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
+ PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
+ PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
+ PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
+ PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
+ PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
+ PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
+ PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
+ PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
+ PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
+ PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
+ PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
+ PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
+ PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
+ PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
+ PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
+ PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
+ PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
+ PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
+ PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
+ PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
+ PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
+ PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
+ PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
+ PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
+ PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
+ PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
+ PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
+ PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
+ PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
+ PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
+ PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
+ PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
+ PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
+ PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
+ PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
+ PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
+ PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
+ PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
+ PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
+ PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
+ PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
+ PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
+ PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
+ PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
+ PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
+ PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
+ PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
+ PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
+ PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
+ PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
+ PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
+ PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
+ PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
+ PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
+ PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
+ PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
+ PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
+ PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
+ PINMUX_DATA(A27_MARK, PORT149_FN1), \
+ PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
+ PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
+ PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
+ PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
+ PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
+ PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
+ PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
+ PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
+ PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
+ PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
+ PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
+ PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
+ PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
+ PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
+ PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
+ PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
+ PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
+ PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
+ PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
+ MSEL4CR_MSEL10_0),
+ PINMUX_DATA(DINT__MARK, PORT158_FN1), \
+ PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
+ PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
+ PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
+ PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
+ PINMUX_DATA(NMI_MARK, PORT159_FN3),
+ PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
+ PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
+ PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
+ PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
+ PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
+ PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
+ PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
+ PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
+ PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
+ PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
+ PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
+ PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
+ MSEL4CR_MSEL20_1), \
+ PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
+ PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
+ PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
+ MSEL4CR_MSEL20_1), \
+ PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
+ PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
+ PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
+ MSEL4CR_MSEL20_1), \
+ PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
+ PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
+ PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
+ MSEL4CR_MSEL20_1),
+ PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
+ PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
+ MSEL4CR_MSEL20_1), \
+ PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
+ PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
+ PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
+ PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
+ PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
+ PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
+ PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
+ PINMUX_DATA(D16_MARK, PORT200_FN6),
+ PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
+ PINMUX_DATA(D17_MARK, PORT201_FN6),
+ PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
+ PINMUX_DATA(D18_MARK, PORT202_FN6),
+ PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
+ PINMUX_DATA(D19_MARK, PORT203_FN6),
+ PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
+ PINMUX_DATA(D20_MARK, PORT204_FN6),
+ PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
+ PINMUX_DATA(D21_MARK, PORT205_FN6),
+ PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
+ PINMUX_DATA(D22_MARK, PORT206_FN6),
+ PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
+ PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
+ PINMUX_DATA(D23_MARK, PORT207_FN6),
+ PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
+ PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
+ PINMUX_DATA(D24_MARK, PORT208_FN6),
+ PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
+ PINMUX_DATA(D25_MARK, PORT209_FN6),
+ PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
+ PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
+ PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
+ PINMUX_DATA(D26_MARK, PORT210_FN6),
+ PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
+ PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
+ PINMUX_DATA(D27_MARK, PORT211_FN6),
+ PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
+ PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
+ PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
+ PINMUX_DATA(D28_MARK, PORT212_FN6),
+ PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
+ PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
+ PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
+ PINMUX_DATA(D29_MARK, PORT213_FN6),
+ PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
+ PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
+ PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
+ PINMUX_DATA(D30_MARK, PORT214_FN6),
+ PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
+ PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
+ PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
+ PINMUX_DATA(D31_MARK, PORT215_FN6),
+ PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
+ PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
+ PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
+ PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
+ PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
+ PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
+ PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
+ MSEL4CR_MSEL26_1), \
+ PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
+ PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
+ PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
+ PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
+ PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
+ PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
+ PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
+ PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
+ PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
+ PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
+ PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
+ PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
+ MSEL4CR_MSEL26_1), \
+ PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
+ PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
+ PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
+ PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
+ PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
+ PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
+ PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
+ PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
+ PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
+ MSEL4CR_MSEL26_1), \
+ PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
+ PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
+ PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
+ PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
+ PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
+ PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
+ PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
+ MSEL4CR_MSEL26_1), \
+ PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
+
+ PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
+ PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
+ PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
+ PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
+ PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
+ PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
+ PINMUX_DATA(IDIN_MARK, PORT227_FN4),
+ PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
+ PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
+ PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
+ PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
+ PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
+ PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
+ PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
+ PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
+ PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
+ PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
+ PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
+ PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
+ PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
+ PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
+ MSEL4CR_MSEL26_0), \
+ PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
+ PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
+ PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
+ PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
+ MSEL4CR_MSEL26_0), \
+ PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
+ PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
+ PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
+ MSEL2CR_MSEL16_0),
+ PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
+ PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
+ MSEL2CR_MSEL16_0),
+ PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
+ PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
+ MSEL4CR_MSEL26_0), \
+ PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
+ PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
+ PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
+ MSEL4CR_MSEL26_0), \
+ PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
+ PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
+ PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
+ PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
+ PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
+ PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
+ PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
+ PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
+ PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
+ PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
+ PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
+ MSEL4CR_MSEL20_0), \
+ PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
+ PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
+ PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
+ PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
+ MSEL4CR_MSEL20_0), \
+ PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
+ PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
+ PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
+ PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
+ MSEL4CR_MSEL20_0), \
+ PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
+ PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
+ PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
+ PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
+ MSEL4CR_MSEL20_0), \
+ PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
+ PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
+ PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
+ PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
+ MSEL4CR_MSEL20_0), \
+ PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
+ PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
+ PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
+ PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
+ MSEL2CR_MSEL18_0), \
+ PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
+ PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
+ PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
+ PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
+ MSEL2CR_MSEL18_0), \
+ PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
+ PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
+ PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
+ PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
+ PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
+ PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
+ PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
+ PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
+ PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
+ PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
+ PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
+ PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
+ PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
+ PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
+ PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
+ PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
+ PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
+ PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
+ PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
+ PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
+ PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
+ PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
+ PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
+ PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
+ PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
+ PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
+ PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
+ PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
+ PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
+ PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU,
+ MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU,
+ MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU,
+ MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU,
+ MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU,
+ MSEL4CR_MSEL15_0), \
+ PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
+ PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU,
+ MSEL4CR_MSEL15_0), \
+ PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
+ PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU,
+ MSEL4CR_MSEL15_0), \
+ PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
+ PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU,
+ MSEL4CR_MSEL15_0), \
+ PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
+ PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU,
+ MSEL4CR_MSEL15_0),
+ PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
+ PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
+ PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
+ PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
+ PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
+ PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
+ PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
+ PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
+ PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
+ PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
+ PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
+ PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
+ PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
+ PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
+ PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
+ PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
+
+ PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
+ PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
+ PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
+ PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
+ PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
+ PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
+ PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
+ PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
+ PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
+ PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
+ PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
+ PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
+ PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
+ PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
+ PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
+ PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
+ PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
+
+ /* MSEL2 special cases */
+ PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
+ MSEL2CR_MSEL12_0),
+ PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
+ MSEL2CR_MSEL12_1),
+ PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
+ MSEL2CR_MSEL12_0),
+ PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
+ MSEL2CR_MSEL12_1),
+ PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
+ MSEL2CR_MSEL12_0),
+ PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
+ MSEL2CR_MSEL9_0),
+ PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
+ MSEL2CR_MSEL9_1),
+ PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
+ MSEL2CR_MSEL9_0),
+ PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
+ MSEL2CR_MSEL9_1),
+ PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
+ MSEL2CR_MSEL9_0),
+ PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
+ MSEL2CR_MSEL6_0),
+ PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
+ MSEL2CR_MSEL6_1),
+ PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
+ MSEL2CR_MSEL6_0),
+ PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
+ MSEL2CR_MSEL6_1),
+ PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
+ MSEL2CR_MSEL6_0),
+ PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
+ MSEL2CR_MSEL3_0),
+ PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
+ MSEL2CR_MSEL3_1),
+ PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
+ MSEL2CR_MSEL3_0),
+ PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
+ MSEL2CR_MSEL3_1),
+ PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
+ MSEL2CR_MSEL3_0),
+ PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
+ MSEL2CR_MSEL0_0),
+ PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
+ MSEL2CR_MSEL0_1),
+ PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
+ MSEL2CR_MSEL0_0),
+ PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
+ MSEL2CR_MSEL0_1),
+ PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
+ MSEL2CR_MSEL0_0),
+
+ /* MSEL3 special cases */
+ PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
+ PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
+ PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
+ PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
+ PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
+ PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
+
+ /* MSEL4 special cases */
+ PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
+ PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
+ PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
+ PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
+ PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
+ PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
+ PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
+ PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
+ PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
+
+ /* Functions with pull-ups */
+ PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU),
+ PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU),
+ PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU),
+ PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU),
+ PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU),
+ PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU),
+ PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU),
+ PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU),
+
+ PINMUX_DATA(SDHICD0_PU_MARK, PORT251_FN1, PORT251_IN_PU),
+ PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU),
+ PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU),
+ PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU),
+ PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU),
+ PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU),
+ PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT256_IN_PU),
+ PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU),
+ PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU),
+ PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU),
+ PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU),
+ PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU),
+ PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU),
+ PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU),
+ PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU),
+ PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU),
+ PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU),
+
+ PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU,
+ MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU,
+ MSEL4CR_MSEL15_1),
+
+ PINMUX_DATA(MMCD0_0_PU_MARK,
+ PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_1_PU_MARK,
+ PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_2_PU_MARK,
+ PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_3_PU_MARK,
+ PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_4_PU_MARK,
+ PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_5_PU_MARK,
+ PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_6_PU_MARK,
+ PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_7_PU_MARK,
+ PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0),
+
+ PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU),
+ PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU),
+ PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU),
+ PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU),
+ PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+ GPIO_PORT_ALL(),
+
+ /* Table 25-1 (Functions 0-7) */
+ GPIO_FN(VBUS_0),
+ GPIO_FN(GPI0),
+ GPIO_FN(GPI1),
+ GPIO_FN(GPI2),
+ GPIO_FN(GPI3),
+ GPIO_FN(GPI4),
+ GPIO_FN(GPI5),
+ GPIO_FN(GPI6),
+ GPIO_FN(GPI7),
+ GPIO_FN(SCIFA7_RXD),
+ GPIO_FN(SCIFA7_CTS_),
+ GPIO_FN(GPO7), \
+ GPIO_FN(MFG0_OUT2),
+ GPIO_FN(GPO6), \
+ GPIO_FN(MFG1_OUT2),
+ GPIO_FN(GPO5), \
+ GPIO_FN(SCIFA0_SCK), \
+ GPIO_FN(FSICOSLDT3), \
+ GPIO_FN(PORT16_VIO_CKOR),
+ GPIO_FN(SCIFA0_TXD),
+ GPIO_FN(SCIFA7_TXD),
+ GPIO_FN(SCIFA7_RTS_), \
+ GPIO_FN(PORT19_VIO_CKO2),
+ GPIO_FN(GPO0),
+ GPIO_FN(GPO1),
+ GPIO_FN(GPO2), \
+ GPIO_FN(STATUS0),
+ GPIO_FN(GPO3), \
+ GPIO_FN(STATUS1),
+ GPIO_FN(GPO4), \
+ GPIO_FN(STATUS2),
+ GPIO_FN(VINT),
+ GPIO_FN(TCKON),
+ GPIO_FN(XDVFS1), \
+ GPIO_FN(PORT27_I2C_SCL2), \
+ GPIO_FN(PORT27_I2C_SCL3), \
+ GPIO_FN(MFG0_OUT1), \
+ GPIO_FN(PORT27_IROUT),
+ GPIO_FN(XDVFS2), \
+ GPIO_FN(PORT28_I2C_SDA2), \
+ GPIO_FN(PORT28_I2C_SDA3), \
+ GPIO_FN(PORT28_TPU1TO1),
+ GPIO_FN(SIM_RST), \
+ GPIO_FN(PORT29_TPU1TO1),
+ GPIO_FN(SIM_CLK), \
+ GPIO_FN(PORT30_VIO_CKOR),
+ GPIO_FN(SIM_D), \
+ GPIO_FN(PORT31_IROUT),
+ GPIO_FN(SCIFA4_TXD),
+ GPIO_FN(SCIFA4_RXD), \
+ GPIO_FN(XWUP),
+ GPIO_FN(SCIFA4_RTS_),
+ GPIO_FN(SCIFA4_CTS_),
+ GPIO_FN(FSIBOBT), \
+ GPIO_FN(FSIBIBT),
+ GPIO_FN(FSIBOLR), \
+ GPIO_FN(FSIBILR),
+ GPIO_FN(FSIBOSLD),
+ GPIO_FN(FSIBISLD),
+ GPIO_FN(VACK),
+ GPIO_FN(XTAL1L),
+ GPIO_FN(SCIFA0_RTS_), \
+ GPIO_FN(FSICOSLDT2),
+ GPIO_FN(SCIFA0_RXD),
+ GPIO_FN(SCIFA0_CTS_), \
+ GPIO_FN(FSICOSLDT1),
+ GPIO_FN(FSICOBT), \
+ GPIO_FN(FSICIBT), \
+ GPIO_FN(FSIDOBT), \
+ GPIO_FN(FSIDIBT),
+ GPIO_FN(FSICOLR), \
+ GPIO_FN(FSICILR), \
+ GPIO_FN(FSIDOLR), \
+ GPIO_FN(FSIDILR),
+ GPIO_FN(FSICOSLD), \
+ GPIO_FN(PORT47_FSICSPDIF),
+ GPIO_FN(FSICISLD), \
+ GPIO_FN(FSIDISLD),
+ GPIO_FN(FSIACK), \
+ GPIO_FN(PORT49_IRDA_OUT), \
+ GPIO_FN(PORT49_IROUT), \
+ GPIO_FN(FSIAOMC),
+ GPIO_FN(FSIAOLR), \
+ GPIO_FN(BBIF2_TSYNC2), \
+ GPIO_FN(TPU2TO2), \
+ GPIO_FN(FSIAILR),
+
+ GPIO_FN(FSIAOBT), \
+ GPIO_FN(BBIF2_TSCK2), \
+ GPIO_FN(TPU2TO3), \
+ GPIO_FN(FSIAIBT),
+ GPIO_FN(FSIAOSLD), \
+ GPIO_FN(BBIF2_TXD2),
+ GPIO_FN(FSIASPDIF), \
+ GPIO_FN(PORT53_IRDA_IN), \
+ GPIO_FN(TPU3TO3), \
+ GPIO_FN(FSIBSPDIF), \
+ GPIO_FN(PORT53_FSICSPDIF),
+ GPIO_FN(FSIBCK), \
+ GPIO_FN(PORT54_IRDA_FIRSEL), \
+ GPIO_FN(TPU3TO2), \
+ GPIO_FN(FSIBOMC), \
+ GPIO_FN(FSICCK), \
+ GPIO_FN(FSICOMC),
+ GPIO_FN(FSIAISLD), \
+ GPIO_FN(TPU0TO0),
+ GPIO_FN(A0), \
+ GPIO_FN(BS_),
+ GPIO_FN(A12), \
+ GPIO_FN(PORT58_KEYOUT7), \
+ GPIO_FN(TPU4TO2),
+ GPIO_FN(A13), \
+ GPIO_FN(PORT59_KEYOUT6), \
+ GPIO_FN(TPU0TO1),
+ GPIO_FN(A14), \
+ GPIO_FN(KEYOUT5),
+ GPIO_FN(A15), \
+ GPIO_FN(KEYOUT4),
+ GPIO_FN(A16), \
+ GPIO_FN(KEYOUT3), \
+ GPIO_FN(MSIOF0_SS1),
+ GPIO_FN(A17), \
+ GPIO_FN(KEYOUT2), \
+ GPIO_FN(MSIOF0_TSYNC),
+ GPIO_FN(A18), \
+ GPIO_FN(KEYOUT1), \
+ GPIO_FN(MSIOF0_TSCK),
+ GPIO_FN(A19), \
+ GPIO_FN(KEYOUT0), \
+ GPIO_FN(MSIOF0_TXD),
+ GPIO_FN(A20), \
+ GPIO_FN(KEYIN0), \
+ GPIO_FN(MSIOF0_RSCK),
+ GPIO_FN(A21), \
+ GPIO_FN(KEYIN1), \
+ GPIO_FN(MSIOF0_RSYNC),
+ GPIO_FN(A22), \
+ GPIO_FN(KEYIN2), \
+ GPIO_FN(MSIOF0_MCK0),
+ GPIO_FN(A23), \
+ GPIO_FN(KEYIN3), \
+ GPIO_FN(MSIOF0_MCK1),
+ GPIO_FN(A24), \
+ GPIO_FN(KEYIN4), \
+ GPIO_FN(MSIOF0_RXD),
+ GPIO_FN(A25), \
+ GPIO_FN(KEYIN5), \
+ GPIO_FN(MSIOF0_SS2),
+ GPIO_FN(A26), \
+ GPIO_FN(KEYIN6),
+ GPIO_FN(KEYIN7),
+ GPIO_FN(D0_NAF0),
+ GPIO_FN(D1_NAF1),
+ GPIO_FN(D2_NAF2),
+ GPIO_FN(D3_NAF3),
+ GPIO_FN(D4_NAF4),
+ GPIO_FN(D5_NAF5),
+ GPIO_FN(D6_NAF6),
+ GPIO_FN(D7_NAF7),
+ GPIO_FN(D8_NAF8),
+ GPIO_FN(D9_NAF9),
+ GPIO_FN(D10_NAF10),
+ GPIO_FN(D11_NAF11),
+ GPIO_FN(D12_NAF12),
+ GPIO_FN(D13_NAF13),
+ GPIO_FN(D14_NAF14),
+ GPIO_FN(D15_NAF15),
+ GPIO_FN(CS4_),
+ GPIO_FN(CS5A_), \
+ GPIO_FN(PORT91_RDWR),
+ GPIO_FN(CS5B_), \
+ GPIO_FN(FCE1_),
+ GPIO_FN(CS6B_), \
+ GPIO_FN(DACK0),
+ GPIO_FN(FCE0_), \
+ GPIO_FN(CS6A_),
+ GPIO_FN(WAIT_), \
+ GPIO_FN(DREQ0),
+ GPIO_FN(RD__FSC),
+ GPIO_FN(WE0__FWE), \
+ GPIO_FN(RDWR_FWE),
+ GPIO_FN(WE1_),
+ GPIO_FN(FRB),
+ GPIO_FN(CKO),
+ GPIO_FN(NBRSTOUT_),
+ GPIO_FN(NBRST_),
+ GPIO_FN(BBIF2_TXD),
+ GPIO_FN(BBIF2_RXD),
+ GPIO_FN(BBIF2_SYNC),
+ GPIO_FN(BBIF2_SCK),
+ GPIO_FN(SCIFA3_CTS_), \
+ GPIO_FN(MFG3_IN2),
+ GPIO_FN(SCIFA3_RXD), \
+ GPIO_FN(MFG3_IN1),
+ GPIO_FN(BBIF1_SS2), \
+ GPIO_FN(SCIFA3_RTS_), \
+ GPIO_FN(MFG3_OUT1),
+ GPIO_FN(SCIFA3_TXD),
+ GPIO_FN(HSI_RX_DATA), \
+ GPIO_FN(BBIF1_RXD),
+ GPIO_FN(HSI_TX_WAKE), \
+ GPIO_FN(BBIF1_TSCK),
+ GPIO_FN(HSI_TX_DATA), \
+ GPIO_FN(BBIF1_TSYNC),
+ GPIO_FN(HSI_TX_READY), \
+ GPIO_FN(BBIF1_TXD),
+ GPIO_FN(HSI_RX_READY), \
+ GPIO_FN(BBIF1_RSCK), \
+ GPIO_FN(PORT115_I2C_SCL2), \
+ GPIO_FN(PORT115_I2C_SCL3),
+ GPIO_FN(HSI_RX_WAKE), \
+ GPIO_FN(BBIF1_RSYNC), \
+ GPIO_FN(PORT116_I2C_SDA2), \
+ GPIO_FN(PORT116_I2C_SDA3),
+ GPIO_FN(HSI_RX_FLAG), \
+ GPIO_FN(BBIF1_SS1), \
+ GPIO_FN(BBIF1_FLOW),
+ GPIO_FN(HSI_TX_FLAG),
+ GPIO_FN(VIO_VD), \
+ GPIO_FN(PORT128_LCD2VSYN), \
+ GPIO_FN(VIO2_VD), \
+ GPIO_FN(LCD2D0),
+
+ GPIO_FN(VIO_HD), \
+ GPIO_FN(PORT129_LCD2HSYN), \
+ GPIO_FN(PORT129_LCD2CS_), \
+ GPIO_FN(VIO2_HD), \
+ GPIO_FN(LCD2D1),
+ GPIO_FN(VIO_D0), \
+ GPIO_FN(PORT130_MSIOF2_RXD), \
+ GPIO_FN(LCD2D10),
+ GPIO_FN(VIO_D1), \
+ GPIO_FN(PORT131_KEYOUT6), \
+ GPIO_FN(PORT131_MSIOF2_SS1), \
+ GPIO_FN(PORT131_KEYOUT11), \
+ GPIO_FN(LCD2D11),
+ GPIO_FN(VIO_D2), \
+ GPIO_FN(PORT132_KEYOUT7), \
+ GPIO_FN(PORT132_MSIOF2_SS2), \
+ GPIO_FN(PORT132_KEYOUT10), \
+ GPIO_FN(LCD2D12),
+ GPIO_FN(VIO_D3), \
+ GPIO_FN(MSIOF2_TSYNC), \
+ GPIO_FN(LCD2D13),
+ GPIO_FN(VIO_D4), \
+ GPIO_FN(MSIOF2_TXD), \
+ GPIO_FN(LCD2D14),
+ GPIO_FN(VIO_D5), \
+ GPIO_FN(MSIOF2_TSCK), \
+ GPIO_FN(LCD2D15),
+ GPIO_FN(VIO_D6), \
+ GPIO_FN(PORT136_KEYOUT8), \
+ GPIO_FN(LCD2D16),
+ GPIO_FN(VIO_D7), \
+ GPIO_FN(PORT137_KEYOUT9), \
+ GPIO_FN(LCD2D17),
+ GPIO_FN(VIO_D8), \
+ GPIO_FN(PORT138_KEYOUT8), \
+ GPIO_FN(VIO2_D0), \
+ GPIO_FN(LCD2D6),
+ GPIO_FN(VIO_D9), \
+ GPIO_FN(PORT139_KEYOUT9), \
+ GPIO_FN(VIO2_D1), \
+ GPIO_FN(LCD2D7),
+ GPIO_FN(VIO_D10), \
+ GPIO_FN(TPU0TO2), \
+ GPIO_FN(VIO2_D2), \
+ GPIO_FN(LCD2D8),
+ GPIO_FN(VIO_D11), \
+ GPIO_FN(TPU0TO3), \
+ GPIO_FN(VIO2_D3), \
+ GPIO_FN(LCD2D9),
+ GPIO_FN(VIO_D12), \
+ GPIO_FN(PORT142_KEYOUT10), \
+ GPIO_FN(VIO2_D4), \
+ GPIO_FN(LCD2D2),
+ GPIO_FN(VIO_D13), \
+ GPIO_FN(PORT143_KEYOUT11), \
+ GPIO_FN(PORT143_KEYOUT6), \
+ GPIO_FN(VIO2_D5), \
+ GPIO_FN(LCD2D3),
+ GPIO_FN(VIO_D14), \
+ GPIO_FN(PORT144_KEYOUT7), \
+ GPIO_FN(VIO2_D6), \
+ GPIO_FN(LCD2D4),
+ GPIO_FN(VIO_D15), \
+ GPIO_FN(TPU1TO3), \
+ GPIO_FN(PORT145_LCD2DISP), \
+ GPIO_FN(PORT145_LCD2RS), \
+ GPIO_FN(VIO2_D7), \
+ GPIO_FN(LCD2D5),
+ GPIO_FN(VIO_CLK), \
+ GPIO_FN(LCD2DCK), \
+ GPIO_FN(PORT146_LCD2WR_), \
+ GPIO_FN(VIO2_CLK), \
+ GPIO_FN(LCD2D18),
+ GPIO_FN(VIO_FIELD), \
+ GPIO_FN(LCD2RD_), \
+ GPIO_FN(VIO2_FIELD), \
+ GPIO_FN(LCD2D19),
+ GPIO_FN(VIO_CKO),
+ GPIO_FN(A27), \
+ GPIO_FN(PORT149_RDWR), \
+ GPIO_FN(MFG0_IN1), \
+ GPIO_FN(PORT149_KEYOUT9),
+ GPIO_FN(MFG0_IN2),
+ GPIO_FN(TS_SPSYNC3), \
+ GPIO_FN(MSIOF2_RSCK),
+ GPIO_FN(TS_SDAT3), \
+ GPIO_FN(MSIOF2_RSYNC),
+ GPIO_FN(TPU1TO2), \
+ GPIO_FN(TS_SDEN3), \
+ GPIO_FN(PORT153_MSIOF2_SS1),
+ GPIO_FN(SCIFA2_TXD1), \
+ GPIO_FN(MSIOF2_MCK0),
+ GPIO_FN(SCIFA2_RXD1), \
+ GPIO_FN(MSIOF2_MCK1),
+ GPIO_FN(SCIFA2_RTS1_), \
+ GPIO_FN(PORT156_MSIOF2_SS2),
+ GPIO_FN(SCIFA2_CTS1_), \
+ GPIO_FN(PORT157_MSIOF2_RXD),
+ GPIO_FN(DINT_), \
+ GPIO_FN(SCIFA2_SCK1), \
+ GPIO_FN(TS_SCK3),
+ GPIO_FN(PORT159_SCIFB_SCK), \
+ GPIO_FN(PORT159_SCIFA5_SCK), \
+ GPIO_FN(NMI),
+ GPIO_FN(PORT160_SCIFB_TXD), \
+ GPIO_FN(PORT160_SCIFA5_TXD),
+ GPIO_FN(PORT161_SCIFB_CTS_), \
+ GPIO_FN(PORT161_SCIFA5_CTS_),
+ GPIO_FN(PORT162_SCIFB_RXD), \
+ GPIO_FN(PORT162_SCIFA5_RXD),
+ GPIO_FN(PORT163_SCIFB_RTS_), \
+ GPIO_FN(PORT163_SCIFA5_RTS_), \
+ GPIO_FN(TPU3TO0),
+ GPIO_FN(LCDD0),
+ GPIO_FN(LCDD1), \
+ GPIO_FN(PORT193_SCIFA5_CTS_), \
+ GPIO_FN(BBIF2_TSYNC1),
+ GPIO_FN(LCDD2), \
+ GPIO_FN(PORT194_SCIFA5_RTS_), \
+ GPIO_FN(BBIF2_TSCK1),
+ GPIO_FN(LCDD3), \
+ GPIO_FN(PORT195_SCIFA5_RXD), \
+ GPIO_FN(BBIF2_TXD1),
+ GPIO_FN(LCDD4), \
+ GPIO_FN(PORT196_SCIFA5_TXD),
+ GPIO_FN(LCDD5), \
+ GPIO_FN(PORT197_SCIFA5_SCK), \
+ GPIO_FN(MFG2_OUT2), \
+ GPIO_FN(TPU2TO1),
+ GPIO_FN(LCDD6),
+ GPIO_FN(LCDD7), \
+ GPIO_FN(TPU4TO1), \
+ GPIO_FN(MFG4_OUT2),
+ GPIO_FN(LCDD8), \
+ GPIO_FN(D16),
+ GPIO_FN(LCDD9), \
+ GPIO_FN(D17),
+ GPIO_FN(LCDD10), \
+ GPIO_FN(D18),
+ GPIO_FN(LCDD11), \
+ GPIO_FN(D19),
+ GPIO_FN(LCDD12), \
+ GPIO_FN(D20),
+ GPIO_FN(LCDD13), \
+ GPIO_FN(D21),
+ GPIO_FN(LCDD14), \
+ GPIO_FN(D22),
+ GPIO_FN(LCDD15), \
+ GPIO_FN(PORT207_MSIOF0L_SS1), \
+ GPIO_FN(D23),
+ GPIO_FN(LCDD16), \
+ GPIO_FN(PORT208_MSIOF0L_SS2), \
+ GPIO_FN(D24),
+ GPIO_FN(LCDD17), \
+ GPIO_FN(D25),
+ GPIO_FN(LCDD18), \
+ GPIO_FN(DREQ2), \
+ GPIO_FN(PORT210_MSIOF0L_SS1), \
+ GPIO_FN(D26),
+ GPIO_FN(LCDD19), \
+ GPIO_FN(PORT211_MSIOF0L_SS2), \
+ GPIO_FN(D27),
+ GPIO_FN(LCDD20), \
+ GPIO_FN(TS_SPSYNC1), \
+ GPIO_FN(MSIOF0L_MCK0), \
+ GPIO_FN(D28),
+ GPIO_FN(LCDD21), \
+ GPIO_FN(TS_SDAT1), \
+ GPIO_FN(MSIOF0L_MCK1), \
+ GPIO_FN(D29),
+ GPIO_FN(LCDD22), \
+ GPIO_FN(TS_SDEN1), \
+ GPIO_FN(MSIOF0L_RSCK), \
+ GPIO_FN(D30),
+ GPIO_FN(LCDD23), \
+ GPIO_FN(TS_SCK1), \
+ GPIO_FN(MSIOF0L_RSYNC), \
+ GPIO_FN(D31),
+ GPIO_FN(LCDDCK), \
+ GPIO_FN(LCDWR_),
+ GPIO_FN(LCDRD_), \
+ GPIO_FN(DACK2), \
+ GPIO_FN(PORT217_LCD2RS), \
+ GPIO_FN(MSIOF0L_TSYNC), \
+ GPIO_FN(VIO2_FIELD3), \
+ GPIO_FN(PORT217_LCD2DISP),
+ GPIO_FN(LCDHSYN), \
+ GPIO_FN(LCDCS_), \
+ GPIO_FN(LCDCS2_), \
+ GPIO_FN(DACK3), \
+ GPIO_FN(PORT218_VIO_CKOR),
+ GPIO_FN(LCDDISP), \
+ GPIO_FN(LCDRS), \
+ GPIO_FN(PORT219_LCD2WR_), \
+ GPIO_FN(DREQ3), \
+ GPIO_FN(MSIOF0L_TSCK), \
+ GPIO_FN(VIO2_CLK3), \
+ GPIO_FN(LCD2DCK_2),
+ GPIO_FN(LCDVSYN), \
+ GPIO_FN(LCDVSYN2),
+ GPIO_FN(LCDLCLK), \
+ GPIO_FN(DREQ1), \
+ GPIO_FN(PORT221_LCD2CS_), \
+ GPIO_FN(PWEN), \
+ GPIO_FN(MSIOF0L_RXD), \
+ GPIO_FN(VIO2_HD3), \
+ GPIO_FN(PORT221_LCD2HSYN),
+ GPIO_FN(LCDDON), \
+ GPIO_FN(LCDDON2), \
+ GPIO_FN(DACK1), \
+ GPIO_FN(OVCN), \
+ GPIO_FN(MSIOF0L_TXD), \
+ GPIO_FN(VIO2_VD3), \
+ GPIO_FN(PORT222_LCD2VSYN),
+
+ GPIO_FN(SCIFA1_TXD), \
+ GPIO_FN(OVCN2),
+ GPIO_FN(EXTLP), \
+ GPIO_FN(SCIFA1_SCK), \
+ GPIO_FN(PORT226_VIO_CKO2),
+ GPIO_FN(SCIFA1_RTS_), \
+ GPIO_FN(IDIN),
+ GPIO_FN(SCIFA1_RXD),
+ GPIO_FN(SCIFA1_CTS_), \
+ GPIO_FN(MFG1_IN1),
+ GPIO_FN(MSIOF1_TXD), \
+ GPIO_FN(SCIFA2_TXD2),
+ GPIO_FN(MSIOF1_TSYNC), \
+ GPIO_FN(SCIFA2_CTS2_),
+ GPIO_FN(MSIOF1_TSCK), \
+ GPIO_FN(SCIFA2_SCK2),
+ GPIO_FN(MSIOF1_RXD), \
+ GPIO_FN(SCIFA2_RXD2),
+ GPIO_FN(MSIOF1_RSCK), \
+ GPIO_FN(SCIFA2_RTS2_), \
+ GPIO_FN(VIO2_CLK2), \
+ GPIO_FN(LCD2D20),
+ GPIO_FN(MSIOF1_RSYNC), \
+ GPIO_FN(MFG1_IN2), \
+ GPIO_FN(VIO2_VD2), \
+ GPIO_FN(LCD2D21),
+ GPIO_FN(MSIOF1_MCK0), \
+ GPIO_FN(PORT236_I2C_SDA2),
+ GPIO_FN(MSIOF1_MCK1), \
+ GPIO_FN(PORT237_I2C_SCL2),
+ GPIO_FN(MSIOF1_SS1), \
+ GPIO_FN(VIO2_FIELD2), \
+ GPIO_FN(LCD2D22),
+ GPIO_FN(MSIOF1_SS2), \
+ GPIO_FN(VIO2_HD2), \
+ GPIO_FN(LCD2D23),
+ GPIO_FN(SCIFA6_TXD),
+ GPIO_FN(PORT241_IRDA_OUT), \
+ GPIO_FN(PORT241_IROUT), \
+ GPIO_FN(MFG4_OUT1), \
+ GPIO_FN(TPU4TO0),
+ GPIO_FN(PORT242_IRDA_IN), \
+ GPIO_FN(MFG4_IN2),
+ GPIO_FN(PORT243_IRDA_FIRSEL), \
+ GPIO_FN(PORT243_VIO_CKO2),
+ GPIO_FN(PORT244_SCIFA5_CTS_), \
+ GPIO_FN(MFG2_IN1), \
+ GPIO_FN(PORT244_SCIFB_CTS_), \
+ GPIO_FN(MSIOF2R_RXD),
+ GPIO_FN(PORT245_SCIFA5_RTS_), \
+ GPIO_FN(MFG2_IN2), \
+ GPIO_FN(PORT245_SCIFB_RTS_), \
+ GPIO_FN(MSIOF2R_TXD),
+ GPIO_FN(PORT246_SCIFA5_RXD), \
+ GPIO_FN(MFG1_OUT1), \
+ GPIO_FN(PORT246_SCIFB_RXD), \
+ GPIO_FN(TPU1TO0),
+ GPIO_FN(PORT247_SCIFA5_TXD), \
+ GPIO_FN(MFG3_OUT2), \
+ GPIO_FN(PORT247_SCIFB_TXD), \
+ GPIO_FN(TPU3TO1),
+ GPIO_FN(PORT248_SCIFA5_SCK), \
+ GPIO_FN(MFG2_OUT1), \
+ GPIO_FN(PORT248_SCIFB_SCK), \
+ GPIO_FN(TPU2TO0), \
+ GPIO_FN(PORT248_I2C_SCL3), \
+ GPIO_FN(MSIOF2R_TSCK),
+ GPIO_FN(PORT249_IROUT), \
+ GPIO_FN(MFG4_IN1), \
+ GPIO_FN(PORT249_I2C_SDA3), \
+ GPIO_FN(MSIOF2R_TSYNC),
+ GPIO_FN(SDHICLK0),
+ GPIO_FN(SDHICD0),
+ GPIO_FN(SDHID0_0),
+ GPIO_FN(SDHID0_1),
+ GPIO_FN(SDHID0_2),
+ GPIO_FN(SDHID0_3),
+ GPIO_FN(SDHICMD0),
+ GPIO_FN(SDHIWP0),
+ GPIO_FN(SDHICLK1),
+ GPIO_FN(SDHID1_0), \
+ GPIO_FN(TS_SPSYNC2),
+ GPIO_FN(SDHID1_1), \
+ GPIO_FN(TS_SDAT2),
+ GPIO_FN(SDHID1_2), \
+ GPIO_FN(TS_SDEN2),
+ GPIO_FN(SDHID1_3), \
+ GPIO_FN(TS_SCK2),
+ GPIO_FN(SDHICMD1),
+ GPIO_FN(SDHICLK2),
+ GPIO_FN(SDHID2_0), \
+ GPIO_FN(TS_SPSYNC4),
+ GPIO_FN(SDHID2_1), \
+ GPIO_FN(TS_SDAT4),
+ GPIO_FN(SDHID2_2), \
+ GPIO_FN(TS_SDEN4),
+ GPIO_FN(SDHID2_3), \
+ GPIO_FN(TS_SCK4),
+ GPIO_FN(SDHICMD2),
+ GPIO_FN(MMCCLK0),
+ GPIO_FN(MMCD0_0),
+ GPIO_FN(MMCD0_1),
+ GPIO_FN(MMCD0_2),
+ GPIO_FN(MMCD0_3),
+ GPIO_FN(MMCD0_4), \
+ GPIO_FN(TS_SPSYNC5),
+ GPIO_FN(MMCD0_5), \
+ GPIO_FN(TS_SDAT5),
+ GPIO_FN(MMCD0_6), \
+ GPIO_FN(TS_SDEN5),
+ GPIO_FN(MMCD0_7), \
+ GPIO_FN(TS_SCK5),
+ GPIO_FN(MMCCMD0),
+ GPIO_FN(RESETOUTS_), \
+ GPIO_FN(EXTAL2OUT),
+ GPIO_FN(MCP_WAIT__MCP_FRB),
+ GPIO_FN(MCP_CKO), \
+ GPIO_FN(MMCCLK1),
+ GPIO_FN(MCP_D15_MCP_NAF15),
+ GPIO_FN(MCP_D14_MCP_NAF14),
+ GPIO_FN(MCP_D13_MCP_NAF13),
+ GPIO_FN(MCP_D12_MCP_NAF12),
+ GPIO_FN(MCP_D11_MCP_NAF11),
+ GPIO_FN(MCP_D10_MCP_NAF10),
+ GPIO_FN(MCP_D9_MCP_NAF9),
+ GPIO_FN(MCP_D8_MCP_NAF8), \
+ GPIO_FN(MMCCMD1),
+ GPIO_FN(MCP_D7_MCP_NAF7), \
+ GPIO_FN(MMCD1_7),
+
+ GPIO_FN(MCP_D6_MCP_NAF6), \
+ GPIO_FN(MMCD1_6),
+ GPIO_FN(MCP_D5_MCP_NAF5), \
+ GPIO_FN(MMCD1_5),
+ GPIO_FN(MCP_D4_MCP_NAF4), \
+ GPIO_FN(MMCD1_4),
+ GPIO_FN(MCP_D3_MCP_NAF3), \
+ GPIO_FN(MMCD1_3),
+ GPIO_FN(MCP_D2_MCP_NAF2), \
+ GPIO_FN(MMCD1_2),
+ GPIO_FN(MCP_D1_MCP_NAF1), \
+ GPIO_FN(MMCD1_1),
+ GPIO_FN(MCP_D0_MCP_NAF0), \
+ GPIO_FN(MMCD1_0),
+ GPIO_FN(MCP_NBRSTOUT_),
+ GPIO_FN(MCP_WE0__MCP_FWE), \
+ GPIO_FN(MCP_RDWR_MCP_FWE),
+
+ /* MSEL2 special cases */
+ GPIO_FN(TSIF2_TS_XX1),
+ GPIO_FN(TSIF2_TS_XX2),
+ GPIO_FN(TSIF2_TS_XX3),
+ GPIO_FN(TSIF2_TS_XX4),
+ GPIO_FN(TSIF2_TS_XX5),
+ GPIO_FN(TSIF1_TS_XX1),
+ GPIO_FN(TSIF1_TS_XX2),
+ GPIO_FN(TSIF1_TS_XX3),
+ GPIO_FN(TSIF1_TS_XX4),
+ GPIO_FN(TSIF1_TS_XX5),
+ GPIO_FN(TSIF0_TS_XX1),
+ GPIO_FN(TSIF0_TS_XX2),
+ GPIO_FN(TSIF0_TS_XX3),
+ GPIO_FN(TSIF0_TS_XX4),
+ GPIO_FN(TSIF0_TS_XX5),
+ GPIO_FN(MST1_TS_XX1),
+ GPIO_FN(MST1_TS_XX2),
+ GPIO_FN(MST1_TS_XX3),
+ GPIO_FN(MST1_TS_XX4),
+ GPIO_FN(MST1_TS_XX5),
+ GPIO_FN(MST0_TS_XX1),
+ GPIO_FN(MST0_TS_XX2),
+ GPIO_FN(MST0_TS_XX3),
+ GPIO_FN(MST0_TS_XX4),
+ GPIO_FN(MST0_TS_XX5),
+
+ /* MSEL3 special cases */
+ GPIO_FN(SDHI0_VCCQ_MC0_ON),
+ GPIO_FN(SDHI0_VCCQ_MC0_OFF),
+ GPIO_FN(DEBUG_MON_VIO),
+ GPIO_FN(DEBUG_MON_LCDD),
+ GPIO_FN(LCDC_LCDC0),
+ GPIO_FN(LCDC_LCDC1),
+
+ /* MSEL4 special cases */
+ GPIO_FN(IRQ9_MEM_INT),
+ GPIO_FN(IRQ9_MCP_INT),
+ GPIO_FN(A11),
+ GPIO_FN(KEYOUT8),
+ GPIO_FN(TPU4TO3),
+ GPIO_FN(RESETA_N_PU_ON),
+ GPIO_FN(RESETA_N_PU_OFF),
+ GPIO_FN(EDBGREQ_PD),
+ GPIO_FN(EDBGREQ_PU),
+
+ /* Functions with pull-ups */
+ GPIO_FN(KEYIN0_PU),
+ GPIO_FN(KEYIN1_PU),
+ GPIO_FN(KEYIN2_PU),
+ GPIO_FN(KEYIN3_PU),
+ GPIO_FN(KEYIN4_PU),
+ GPIO_FN(KEYIN5_PU),
+ GPIO_FN(KEYIN6_PU),
+ GPIO_FN(KEYIN7_PU),
+ GPIO_FN(SDHICD0_PU),
+ GPIO_FN(SDHID0_0_PU),
+ GPIO_FN(SDHID0_1_PU),
+ GPIO_FN(SDHID0_2_PU),
+ GPIO_FN(SDHID0_3_PU),
+ GPIO_FN(SDHICMD0_PU),
+ GPIO_FN(SDHIWP0_PU),
+ GPIO_FN(SDHID1_0_PU),
+ GPIO_FN(SDHID1_1_PU),
+ GPIO_FN(SDHID1_2_PU),
+ GPIO_FN(SDHID1_3_PU),
+ GPIO_FN(SDHICMD1_PU),
+ GPIO_FN(SDHID2_0_PU),
+ GPIO_FN(SDHID2_1_PU),
+ GPIO_FN(SDHID2_2_PU),
+ GPIO_FN(SDHID2_3_PU),
+ GPIO_FN(SDHICMD2_PU),
+ GPIO_FN(MMCCMD0_PU),
+ GPIO_FN(MMCCMD1_PU),
+ GPIO_FN(MMCD0_0_PU),
+ GPIO_FN(MMCD0_1_PU),
+ GPIO_FN(MMCD0_2_PU),
+ GPIO_FN(MMCD0_3_PU),
+ GPIO_FN(MMCD0_4_PU),
+ GPIO_FN(MMCD0_5_PU),
+ GPIO_FN(MMCD0_6_PU),
+ GPIO_FN(MMCD0_7_PU),
+ GPIO_FN(FSIACK_PU),
+ GPIO_FN(FSIAILR_PU),
+ GPIO_FN(FSIAIBT_PU),
+ GPIO_FN(FSIAISLD_PU),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+ PORTCR(0, 0xe6050000), /* PORT0CR */
+ PORTCR(1, 0xe6050001), /* PORT1CR */
+ PORTCR(2, 0xe6050002), /* PORT2CR */
+ PORTCR(3, 0xe6050003), /* PORT3CR */
+ PORTCR(4, 0xe6050004), /* PORT4CR */
+ PORTCR(5, 0xe6050005), /* PORT5CR */
+ PORTCR(6, 0xe6050006), /* PORT6CR */
+ PORTCR(7, 0xe6050007), /* PORT7CR */
+ PORTCR(8, 0xe6050008), /* PORT8CR */
+ PORTCR(9, 0xe6050009), /* PORT9CR */
+
+ PORTCR(10, 0xe605000a), /* PORT10CR */
+ PORTCR(11, 0xe605000b), /* PORT11CR */
+ PORTCR(12, 0xe605000c), /* PORT12CR */
+ PORTCR(13, 0xe605000d), /* PORT13CR */
+ PORTCR(14, 0xe605000e), /* PORT14CR */
+ PORTCR(15, 0xe605000f), /* PORT15CR */
+ PORTCR(16, 0xe6050010), /* PORT16CR */
+ PORTCR(17, 0xe6050011), /* PORT17CR */
+ PORTCR(18, 0xe6050012), /* PORT18CR */
+ PORTCR(19, 0xe6050013), /* PORT19CR */
+
+ PORTCR(20, 0xe6050014), /* PORT20CR */
+ PORTCR(21, 0xe6050015), /* PORT21CR */
+ PORTCR(22, 0xe6050016), /* PORT22CR */
+ PORTCR(23, 0xe6050017), /* PORT23CR */
+ PORTCR(24, 0xe6050018), /* PORT24CR */
+ PORTCR(25, 0xe6050019), /* PORT25CR */
+ PORTCR(26, 0xe605001a), /* PORT26CR */
+ PORTCR(27, 0xe605001b), /* PORT27CR */
+ PORTCR(28, 0xe605001c), /* PORT28CR */
+ PORTCR(29, 0xe605001d), /* PORT29CR */
+
+ PORTCR(30, 0xe605001e), /* PORT30CR */
+ PORTCR(31, 0xe605001f), /* PORT31CR */
+ PORTCR(32, 0xe6051020), /* PORT32CR */
+ PORTCR(33, 0xe6051021), /* PORT33CR */
+ PORTCR(34, 0xe6051022), /* PORT34CR */
+ PORTCR(35, 0xe6051023), /* PORT35CR */
+ PORTCR(36, 0xe6051024), /* PORT36CR */
+ PORTCR(37, 0xe6051025), /* PORT37CR */
+ PORTCR(38, 0xe6051026), /* PORT38CR */
+ PORTCR(39, 0xe6051027), /* PORT39CR */
+
+ PORTCR(40, 0xe6051028), /* PORT40CR */
+ PORTCR(41, 0xe6051029), /* PORT41CR */
+ PORTCR(42, 0xe605102a), /* PORT42CR */
+ PORTCR(43, 0xe605102b), /* PORT43CR */
+ PORTCR(44, 0xe605102c), /* PORT44CR */
+ PORTCR(45, 0xe605102d), /* PORT45CR */
+ PORTCR(46, 0xe605102e), /* PORT46CR */
+ PORTCR(47, 0xe605102f), /* PORT47CR */
+ PORTCR(48, 0xe6051030), /* PORT48CR */
+ PORTCR(49, 0xe6051031), /* PORT49CR */
+
+ PORTCR(50, 0xe6051032), /* PORT50CR */
+ PORTCR(51, 0xe6051033), /* PORT51CR */
+ PORTCR(52, 0xe6051034), /* PORT52CR */
+ PORTCR(53, 0xe6051035), /* PORT53CR */
+ PORTCR(54, 0xe6051036), /* PORT54CR */
+ PORTCR(55, 0xe6051037), /* PORT55CR */
+ PORTCR(56, 0xe6051038), /* PORT56CR */
+ PORTCR(57, 0xe6051039), /* PORT57CR */
+ PORTCR(58, 0xe605103a), /* PORT58CR */
+ PORTCR(59, 0xe605103b), /* PORT59CR */
+
+ PORTCR(60, 0xe605103c), /* PORT60CR */
+ PORTCR(61, 0xe605103d), /* PORT61CR */
+ PORTCR(62, 0xe605103e), /* PORT62CR */
+ PORTCR(63, 0xe605103f), /* PORT63CR */
+ PORTCR(64, 0xe6051040), /* PORT64CR */
+ PORTCR(65, 0xe6051041), /* PORT65CR */
+ PORTCR(66, 0xe6051042), /* PORT66CR */
+ PORTCR(67, 0xe6051043), /* PORT67CR */
+ PORTCR(68, 0xe6051044), /* PORT68CR */
+ PORTCR(69, 0xe6051045), /* PORT69CR */
+
+ PORTCR(70, 0xe6051046), /* PORT70CR */
+ PORTCR(71, 0xe6051047), /* PORT71CR */
+ PORTCR(72, 0xe6051048), /* PORT72CR */
+ PORTCR(73, 0xe6051049), /* PORT73CR */
+ PORTCR(74, 0xe605104a), /* PORT74CR */
+ PORTCR(75, 0xe605104b), /* PORT75CR */
+ PORTCR(76, 0xe605104c), /* PORT76CR */
+ PORTCR(77, 0xe605104d), /* PORT77CR */
+ PORTCR(78, 0xe605104e), /* PORT78CR */
+ PORTCR(79, 0xe605104f), /* PORT79CR */
+
+ PORTCR(80, 0xe6051050), /* PORT80CR */
+ PORTCR(81, 0xe6051051), /* PORT81CR */
+ PORTCR(82, 0xe6051052), /* PORT82CR */
+ PORTCR(83, 0xe6051053), /* PORT83CR */
+ PORTCR(84, 0xe6051054), /* PORT84CR */
+ PORTCR(85, 0xe6051055), /* PORT85CR */
+ PORTCR(86, 0xe6051056), /* PORT86CR */
+ PORTCR(87, 0xe6051057), /* PORT87CR */
+ PORTCR(88, 0xe6051058), /* PORT88CR */
+ PORTCR(89, 0xe6051059), /* PORT89CR */
+
+ PORTCR(90, 0xe605105a), /* PORT90CR */
+ PORTCR(91, 0xe605105b), /* PORT91CR */
+ PORTCR(92, 0xe605105c), /* PORT92CR */
+ PORTCR(93, 0xe605105d), /* PORT93CR */
+ PORTCR(94, 0xe605105e), /* PORT94CR */
+ PORTCR(95, 0xe605105f), /* PORT95CR */
+ PORTCR(96, 0xe6052060), /* PORT96CR */
+ PORTCR(97, 0xe6052061), /* PORT97CR */
+ PORTCR(98, 0xe6052062), /* PORT98CR */
+ PORTCR(99, 0xe6052063), /* PORT99CR */
+
+ PORTCR(100, 0xe6052064), /* PORT100CR */
+ PORTCR(101, 0xe6052065), /* PORT101CR */
+ PORTCR(102, 0xe6052066), /* PORT102CR */
+ PORTCR(103, 0xe6052067), /* PORT103CR */
+ PORTCR(104, 0xe6052068), /* PORT104CR */
+ PORTCR(105, 0xe6052069), /* PORT105CR */
+ PORTCR(106, 0xe605206a), /* PORT106CR */
+ PORTCR(107, 0xe605206b), /* PORT107CR */
+ PORTCR(108, 0xe605206c), /* PORT108CR */
+ PORTCR(109, 0xe605206d), /* PORT109CR */
+
+ PORTCR(110, 0xe605206e), /* PORT110CR */
+ PORTCR(111, 0xe605206f), /* PORT111CR */
+ PORTCR(112, 0xe6052070), /* PORT112CR */
+ PORTCR(113, 0xe6052071), /* PORT113CR */
+ PORTCR(114, 0xe6052072), /* PORT114CR */
+ PORTCR(115, 0xe6052073), /* PORT115CR */
+ PORTCR(116, 0xe6052074), /* PORT116CR */
+ PORTCR(117, 0xe6052075), /* PORT117CR */
+ PORTCR(118, 0xe6052076), /* PORT118CR */
+
+ PORTCR(128, 0xe6052080), /* PORT128CR */
+ PORTCR(129, 0xe6052081), /* PORT129CR */
+
+ PORTCR(130, 0xe6052082), /* PORT130CR */
+ PORTCR(131, 0xe6052083), /* PORT131CR */
+ PORTCR(132, 0xe6052084), /* PORT132CR */
+ PORTCR(133, 0xe6052085), /* PORT133CR */
+ PORTCR(134, 0xe6052086), /* PORT134CR */
+ PORTCR(135, 0xe6052087), /* PORT135CR */
+ PORTCR(136, 0xe6052088), /* PORT136CR */
+ PORTCR(137, 0xe6052089), /* PORT137CR */
+ PORTCR(138, 0xe605208a), /* PORT138CR */
+ PORTCR(139, 0xe605208b), /* PORT139CR */
+
+ PORTCR(140, 0xe605208c), /* PORT140CR */
+ PORTCR(141, 0xe605208d), /* PORT141CR */
+ PORTCR(142, 0xe605208e), /* PORT142CR */
+ PORTCR(143, 0xe605208f), /* PORT143CR */
+ PORTCR(144, 0xe6052090), /* PORT144CR */
+ PORTCR(145, 0xe6052091), /* PORT145CR */
+ PORTCR(146, 0xe6052092), /* PORT146CR */
+ PORTCR(147, 0xe6052093), /* PORT147CR */
+ PORTCR(148, 0xe6052094), /* PORT148CR */
+ PORTCR(149, 0xe6052095), /* PORT149CR */
+
+ PORTCR(150, 0xe6052096), /* PORT150CR */
+ PORTCR(151, 0xe6052097), /* PORT151CR */
+ PORTCR(152, 0xe6052098), /* PORT152CR */
+ PORTCR(153, 0xe6052099), /* PORT153CR */
+ PORTCR(154, 0xe605209a), /* PORT154CR */
+ PORTCR(155, 0xe605209b), /* PORT155CR */
+ PORTCR(156, 0xe605209c), /* PORT156CR */
+ PORTCR(157, 0xe605209d), /* PORT157CR */
+ PORTCR(158, 0xe605209e), /* PORT158CR */
+ PORTCR(159, 0xe605209f), /* PORT159CR */
+
+ PORTCR(160, 0xe60520a0), /* PORT160CR */
+ PORTCR(161, 0xe60520a1), /* PORT161CR */
+ PORTCR(162, 0xe60520a2), /* PORT162CR */
+ PORTCR(163, 0xe60520a3), /* PORT163CR */
+ PORTCR(164, 0xe60520a4), /* PORT164CR */
+
+ PORTCR(192, 0xe60520c0), /* PORT192CR */
+ PORTCR(193, 0xe60520c1), /* PORT193CR */
+ PORTCR(194, 0xe60520c2), /* PORT194CR */
+ PORTCR(195, 0xe60520c3), /* PORT195CR */
+ PORTCR(196, 0xe60520c4), /* PORT196CR */
+ PORTCR(197, 0xe60520c5), /* PORT197CR */
+ PORTCR(198, 0xe60520c6), /* PORT198CR */
+ PORTCR(199, 0xe60520c7), /* PORT199CR */
+
+ PORTCR(200, 0xe60520c8), /* PORT200CR */
+ PORTCR(201, 0xe60520c9), /* PORT201CR */
+ PORTCR(202, 0xe60520ca), /* PORT202CR */
+ PORTCR(203, 0xe60520cb), /* PORT203CR */
+ PORTCR(204, 0xe60520cc), /* PORT204CR */
+ PORTCR(205, 0xe60520cd), /* PORT205CR */
+ PORTCR(206, 0xe60520ce), /* PORT206CR */
+ PORTCR(207, 0xe60520cf), /* PORT207CR */
+ PORTCR(208, 0xe60520d0), /* PORT208CR */
+ PORTCR(209, 0xe60520d1), /* PORT209CR */
+
+ PORTCR(210, 0xe60520d2), /* PORT210CR */
+ PORTCR(211, 0xe60520d3), /* PORT211CR */
+ PORTCR(212, 0xe60520d4), /* PORT212CR */
+ PORTCR(213, 0xe60520d5), /* PORT213CR */
+ PORTCR(214, 0xe60520d6), /* PORT214CR */
+ PORTCR(215, 0xe60520d7), /* PORT215CR */
+ PORTCR(216, 0xe60520d8), /* PORT216CR */
+ PORTCR(217, 0xe60520d9), /* PORT217CR */
+ PORTCR(218, 0xe60520da), /* PORT218CR */
+ PORTCR(219, 0xe60520db), /* PORT219CR */
+
+ PORTCR(220, 0xe60520dc), /* PORT220CR */
+ PORTCR(221, 0xe60520dd), /* PORT221CR */
+ PORTCR(222, 0xe60520de), /* PORT222CR */
+ PORTCR(223, 0xe60520df), /* PORT223CR */
+ PORTCR(224, 0xe60530e0), /* PORT224CR */
+ PORTCR(225, 0xe60530e1), /* PORT225CR */
+ PORTCR(226, 0xe60530e2), /* PORT226CR */
+ PORTCR(227, 0xe60530e3), /* PORT227CR */
+ PORTCR(228, 0xe60530e4), /* PORT228CR */
+ PORTCR(229, 0xe60530e5), /* PORT229CR */
+
+ PORTCR(230, 0xe60530e6), /* PORT230CR */
+ PORTCR(231, 0xe60530e7), /* PORT231CR */
+ PORTCR(232, 0xe60530e8), /* PORT232CR */
+ PORTCR(233, 0xe60530e9), /* PORT233CR */
+ PORTCR(234, 0xe60530ea), /* PORT234CR */
+ PORTCR(235, 0xe60530eb), /* PORT235CR */
+ PORTCR(236, 0xe60530ec), /* PORT236CR */
+ PORTCR(237, 0xe60530ed), /* PORT237CR */
+ PORTCR(238, 0xe60530ee), /* PORT238CR */
+ PORTCR(239, 0xe60530ef), /* PORT239CR */
+
+ PORTCR(240, 0xe60530f0), /* PORT240CR */
+ PORTCR(241, 0xe60530f1), /* PORT241CR */
+ PORTCR(242, 0xe60530f2), /* PORT242CR */
+ PORTCR(243, 0xe60530f3), /* PORT243CR */
+ PORTCR(244, 0xe60530f4), /* PORT244CR */
+ PORTCR(245, 0xe60530f5), /* PORT245CR */
+ PORTCR(246, 0xe60530f6), /* PORT246CR */
+ PORTCR(247, 0xe60530f7), /* PORT247CR */
+ PORTCR(248, 0xe60530f8), /* PORT248CR */
+ PORTCR(249, 0xe60530f9), /* PORT249CR */
+
+ PORTCR(250, 0xe60530fa), /* PORT250CR */
+ PORTCR(251, 0xe60530fb), /* PORT251CR */
+ PORTCR(252, 0xe60530fc), /* PORT252CR */
+ PORTCR(253, 0xe60530fd), /* PORT253CR */
+ PORTCR(254, 0xe60530fe), /* PORT254CR */
+ PORTCR(255, 0xe60530ff), /* PORT255CR */
+ PORTCR(256, 0xe6053100), /* PORT256CR */
+ PORTCR(257, 0xe6053101), /* PORT257CR */
+ PORTCR(258, 0xe6053102), /* PORT258CR */
+ PORTCR(259, 0xe6053103), /* PORT259CR */
+
+ PORTCR(260, 0xe6053104), /* PORT260CR */
+ PORTCR(261, 0xe6053105), /* PORT261CR */
+ PORTCR(262, 0xe6053106), /* PORT262CR */
+ PORTCR(263, 0xe6053107), /* PORT263CR */
+ PORTCR(264, 0xe6053108), /* PORT264CR */
+ PORTCR(265, 0xe6053109), /* PORT265CR */
+ PORTCR(266, 0xe605310a), /* PORT266CR */
+ PORTCR(267, 0xe605310b), /* PORT267CR */
+ PORTCR(268, 0xe605310c), /* PORT268CR */
+ PORTCR(269, 0xe605310d), /* PORT269CR */
+
+ PORTCR(270, 0xe605310e), /* PORT270CR */
+ PORTCR(271, 0xe605310f), /* PORT271CR */
+ PORTCR(272, 0xe6053110), /* PORT272CR */
+ PORTCR(273, 0xe6053111), /* PORT273CR */
+ PORTCR(274, 0xe6053112), /* PORT274CR */
+ PORTCR(275, 0xe6053113), /* PORT275CR */
+ PORTCR(276, 0xe6053114), /* PORT276CR */
+ PORTCR(277, 0xe6053115), /* PORT277CR */
+ PORTCR(278, 0xe6053116), /* PORT278CR */
+ PORTCR(279, 0xe6053117), /* PORT279CR */
+
+ PORTCR(280, 0xe6053118), /* PORT280CR */
+ PORTCR(281, 0xe6053119), /* PORT281CR */
+ PORTCR(282, 0xe605311a), /* PORT282CR */
+
+ PORTCR(288, 0xe6052120), /* PORT288CR */
+ PORTCR(289, 0xe6052121), /* PORT289CR */
+
+ PORTCR(290, 0xe6052122), /* PORT290CR */
+ PORTCR(291, 0xe6052123), /* PORT291CR */
+ PORTCR(292, 0xe6052124), /* PORT292CR */
+ PORTCR(293, 0xe6052125), /* PORT293CR */
+ PORTCR(294, 0xe6052126), /* PORT294CR */
+ PORTCR(295, 0xe6052127), /* PORT295CR */
+ PORTCR(296, 0xe6052128), /* PORT296CR */
+ PORTCR(297, 0xe6052129), /* PORT297CR */
+ PORTCR(298, 0xe605212a), /* PORT298CR */
+ PORTCR(299, 0xe605212b), /* PORT299CR */
+
+ PORTCR(300, 0xe605212c), /* PORT300CR */
+ PORTCR(301, 0xe605212d), /* PORT301CR */
+ PORTCR(302, 0xe605212e), /* PORT302CR */
+ PORTCR(303, 0xe605212f), /* PORT303CR */
+ PORTCR(304, 0xe6052130), /* PORT304CR */
+ PORTCR(305, 0xe6052131), /* PORT305CR */
+ PORTCR(306, 0xe6052132), /* PORT306CR */
+ PORTCR(307, 0xe6052133), /* PORT307CR */
+ PORTCR(308, 0xe6052134), /* PORT308CR */
+ PORTCR(309, 0xe6052135), /* PORT309CR */
+
+ { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
+ MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
+ MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
+ MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
+ 0, 0,
+ MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
+ MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
+ MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
+ MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
+ MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
+ MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
+ MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
+ MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
+ MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
+ MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
+ MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
+ MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
+ MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
+ MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
+ MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
+ }
+ },
+ { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
+ 0, 0,
+ MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
+ 0, 0,
+ 0, 0,
+ MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
+ 0, 0,
+ 0, 0,
+ }
+ },
+ { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
+ 0, 0,
+ 0, 0,
+ MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
+ 0, 0,
+ MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
+ MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
+ MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
+ MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
+ MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
+ 0, 0,
+ MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
+ MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
+ MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
+ MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
+ MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
+ MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
+ MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
+ 0, 0,
+ 0, 0,
+ MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
+ 0, 0,
+ 0, 0,
+ MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
+ 0, 0,
+ }
+ },
+ { },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+ { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
+ PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
+ PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
+ PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
+ PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
+ PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
+ PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
+ PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
+ PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
+ },
+ { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
+ PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
+ PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
+ PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
+ PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
+ PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
+ PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
+ PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
+ PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
+ },
+ { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) {
+ PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
+ PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
+ PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
+ PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
+ PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
+ PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
+ PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
+ PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
+ },
+ { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
+ PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
+ PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
+ PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
+ PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
+ PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
+ },
+ { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) {
+ PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
+ PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
+ PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
+ PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
+ PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
+ PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
+ PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
+ PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
+ },
+ { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, PORT164_DATA,
+ PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
+ },
+ { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) {
+ PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
+ PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
+ PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
+ PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
+ PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
+ PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
+ PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
+ PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
+ },
+ { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
+ PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
+ PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
+ PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
+ PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
+ PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
+ PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
+ PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
+ PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
+ },
+ { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
+ 0, 0, 0, 0,
+ 0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
+ PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
+ PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
+ PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
+ PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
+ PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
+ PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
+ },
+ { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, PORT309_DATA, PORT308_DATA,
+ PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
+ PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
+ PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
+ PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
+ PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA }
+ },
+ { },
+};
+
+#if 0
+/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */
+#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5))
+#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5))
+#else
+#define EXT_IRQ16L(n) (n)
+#define EXT_IRQ16H(n) (n)
+#endif
+
+static struct pinmux_irq pinmux_irqs[] = {
+ PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0),
+};
+
+static struct pinmux_info sh73a0_pinmux_info = {
+ .name = "sh73a0_pfc",
+ .reserved_id = PINMUX_RESERVED,
+ .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+ .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+ .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
+ .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
+ .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+ .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .first_gpio = GPIO_PORT0,
+ .last_gpio = GPIO_FN_FSIAISLD_PU,
+
+ .gpios = pinmux_gpios,
+ .cfg_regs = pinmux_config_regs,
+ .data_regs = pinmux_data_regs,
+
+ .gpio_data = pinmux_data,
+ .gpio_data_size = ARRAY_SIZE(pinmux_data),
+
+ .gpio_irq = pinmux_irqs,
+ .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
+};
+
+void sh73a0_pinmux_init(void)
+{
+ register_pinmux(&sh73a0_pinmux_info);
+}
--- /dev/null
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-armv7/globaltimer.h>
+#include <asm/arch/rmobile.h>
+
+static struct globaltimer *global_timer = \
+ (struct globaltimer *)GLOBAL_TIMER_BASE_ADDR;
+
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
+static u64 get_cpu_global_timer(void)
+{
+ u32 low, high;
+ u64 timer;
+
+ u32 old = readl(&global_timer->cnt_h);
+ while (1) {
+ low = readl(&global_timer->cnt_l);
+ high = readl(&global_timer->cnt_h);
+ if (old == high)
+ break;
+ else
+ old = high;
+ }
+
+ timer = high;
+ return (u64)((timer << 32) | low);
+}
+
+static u64 get_time_us(void)
+{
+ u64 timer = get_cpu_global_timer();
+
+ timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1));
+ timer /= (u64)CLK2MHZ(CONFIG_SYS_CPU_CLK);
+ return timer;
+}
+
+static ulong get_time_ms(void)
+{
+ return (ulong)(get_time_us() / 1000);
+}
+
+int timer_init(void)
+{
+ writel(0x01, &global_timer->ctl);
+ return 0;
+}
+
+void __udelay(unsigned long usec)
+{
+ u64 start, current;
+ u64 wait;
+
+ start = get_cpu_global_timer();
+ wait = (u64)((usec * CLK2MHZ(CONFIG_SYS_CPU_CLK)) >> 2);
+ do {
+ current = get_cpu_global_timer();
+ } while ((current - start) < wait);
+}
+
+ulong get_timer(ulong base)
+{
+ return get_time_ms() - base;
+}
+
+unsigned long long get_ticks(void)
+{
+ return get_cpu_global_timer();
+}
+
+ulong get_tbclk(void)
+{
+ return (ulong)(CONFIG_SYS_CPU_CLK >> 2);
+}
--- /dev/null
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2012 Altera Corporation <www.altera.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+SOBJS := lowlevel_init.o
+COBJS-y := misc.o timer.o
+COBJS-$(CONFIG_SPL_BUILD) += spl.o
+
+COBJS := $(COBJS-y)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+ifndef CONFIG_SPL_BUILD
+ALL-y += $(obj)u-boot.img
+endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Save the parameter pass in by previous boot loader */
+.global save_boot_params
+save_boot_params:
+ /* save the parameter here */
+
+ /*
+ * Setup stack for exception, which is located
+ * at the end of on-chip RAM. We don't expect exception prior to
+ * relocation and if that happens, we won't worry -- it will overide
+ * global data region as the code will goto reset. After relocation,
+ * this region won't be used by other part of program.
+ * Hence it is safe.
+ */
+ ldr r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
+ ldr r1, =IRQ_STACK_START_IN
+ str r0, [r1]
+
+ bx lr
+
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+
+ /* Remap */
+#ifdef CONFIG_SPL_BUILD
+ /*
+ * SPL : configure the remap (L3 NIC-301 GPV)
+ * so the on-chip RAM at lower memory instead ROM.
+ */
+ ldr r0, =SOCFPGA_L3REGS_ADDRESS
+ mov r1, #0x19
+ str r1, [r0]
+#else
+ /*
+ * U-Boot : configure the remap (L3 NIC-301 GPV)
+ * so the SDRAM at lower memory instead on-chip RAM.
+ */
+ ldr r0, =SOCFPGA_L3REGS_ADDRESS
+ mov r1, #0x2
+ str r1, [r0]
+
+ /* Private components security */
+
+ /*
+ * U-Boot : configure private timer, global timer and cpu
+ * component access as non secure for kernel stage (as required
+ * by kernel)
+ */
+ mrc p15,4,r0,c15,c0,0
+ add r1, r0, #0x54
+ ldr r2, [r1]
+ orr r2, r2, #0xff
+ orr r2, r2, #0xf00
+ str r2, [r1]
+#endif /* #ifdef CONFIG_SPL_BUILD */
+ mov pc, lr
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+ (void *)SOCFPGA_RSTMGR_ADDRESS;
+
+/*
+ * Write the reset manager register to cause reset
+ */
+void reset_cpu(ulong addr)
+{
+ /* request a warm reset */
+ writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
+ /*
+ * infinite loop here as watchdog will trigger and reset
+ * the processor
+ */
+ while (1)
+ ;
+}
+
+/*
+ * Release peripherals from reset based on handoff
+ */
+void reset_deassert_peripherals_handoff(void)
+{
+ writel(0, &reset_manager_base->per_mod_reset);
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <version.h>
+#include <image.h>
+#include <malloc.h>
+#include <asm/arch/reset_manager.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_RAM;
+}
+
+/*
+ * Board initialization after bss clearance
+ */
+void spl_board_init(void)
+{
+ /* init timer for enabling delay function */
+ timer_init();
+
+ /* de-assert reset for peripherals and bridges based on handoff */
+ reset_deassert_peripherals_handoff();
+
+ /* enable console uart printing */
+ preloader_console_init();
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
+
+/*
+ * Timer initialization
+ */
+int timer_init(void)
+{
+ writel(TIMER_LOAD_VAL, &timer_base->load_val);
+ writel(TIMER_LOAD_VAL, &timer_base->curr_val);
+ writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl);
+ return 0;
+}
+
+static u32 read_timer(void)
+{
+ return readl(&timer_base->curr_val);
+}
+
+/*
+ * Delay x useconds
+ */
+void __udelay(unsigned long usec)
+{
+ unsigned long now, last;
+ /*
+ * get the tmo value based on timer clock speed
+ * tmo = delay required / period of timer clock
+ */
+ long tmo = usec * CONFIG_TIMER_CLOCK_KHZ / 1000;
+
+ last = read_timer();
+ while (tmo > 0) {
+ now = read_timer();
+ if (last >= now)
+ /* normal mode (non roll) */
+ tmo -= last - now;
+ else
+ /* we have overflow of the count down timer */
+ tmo -= TIMER_LOAD_VAL - last + now;
+ last = now;
+ }
+}
+
+/*
+ * Get the timer value
+ */
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+/*
+ * Timer : get the time difference
+ * Unit of tick is based on the CONFIG_SYS_HZ
+ */
+ulong get_timer_masked(void)
+{
+ /* current tick value */
+ ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
+ if (gd->lastinc >= now) {
+ /* normal mode (non roll) */
+ /* move stamp forward with absolute diff ticks */
+ gd->tbl += gd->lastinc - now;
+ } else {
+ /* we have overflow of the count down timer */
+ gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now;
+ }
+ gd->lastinc = now;
+ return gd->tbl;
+}
+
+/*
+ * Reset the timer
+ */
+void reset_timer(void)
+{
+ /* capture current decrementer value time */
+ gd->lastinc = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
+ /* start "advancing" time stamp from 0 */
+ gd->tbl = 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+MEMORY { .sdram : ORIGIN = (0), LENGTH = (0xffffffff) }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ arch/arm/cpu/armv7/start.o (.text)
+ *(.text*)
+ } >.sdram
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } >.sdram
+
+ . = ALIGN(4);
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sdram
+
+ . = ALIGN(4);
+ __image_copy_end = .;
+ _end = .;
+
+ .bss : {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } >.sdram
+
+ . = ALIGN(8);
+ __malloc_start = .;
+ . = . + CONFIG_SPL_MALLOC_SIZE;
+ __malloc_end = .;
+
+ . = . + CONFIG_SPL_STACK_SIZE;
+ . = ALIGN(8);
+ __stack_start = .;
+}
* basic memory. Go here to bump up clock rate and handle
* wake up conditions.
*/
- mov ip, lr @ persevere link reg across call
- bl lowlevel_init @ go setup pll,mux,memory
- mov lr, ip @ restore link
- mov pc, lr @ back to my caller
+ b lowlevel_init @ go setup pll,mux,memory
ENDPROC(cpu_init_crit)
#endif
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2010,2011 Nvidia Corporation.
+#
+# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).o
+LIB = $(obj)libtegra-common.o
-COBJS = $(BOARD).o flash.o serial.o pci.o powerspan.o
-SOBJS = init.o
+COBJS-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+COBJS := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-all: $(LIB) $(SOBJS)
+all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(call cmd_link_o_target, $^)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
*/
#include <common.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/pmc.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/pmc.h>
static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
LIB = $(obj)lib$(SOC).o
COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
-COBJS-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
#include <common.h>
#include <asm/io.h>
#include <asm-generic/gpio.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/uart.h>
+#include <asm/arch/tegra.h>
#include <asm/arch/usb.h>
+#include <usb/ulpi.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/sys_proto.h>
+#include <asm/arch-tegra/uart.h>
#include <libfdt.h>
#include <fdtdec.h>
+#ifdef CONFIG_USB_ULPI
+ #ifndef CONFIG_USB_ULPI_VIEWPORT
+ #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \
+ define CONFIG_USB_ULPI_VIEWPORT"
+ #endif
+#endif
+
enum {
USB_PORTS_MAX = 4, /* Maximum ports we allow */
};
struct fdt_usb {
struct usb_ctlr *reg; /* address of registers in physical memory */
unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */
+ unsigned ulpi:1; /* 1 if port has external ULPI transceiver */
unsigned enabled:1; /* 1 to enable, 0 to disable */
unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
enum dr_mode dr_mode; /* dual role mode */
enum periph_id periph_id;/* peripheral id */
struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */
+ struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */
};
static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */
static unsigned port_count; /* Number of available ports */
-static int port_current; /* Current port (-1 = none) */
/*
* This table has USB timing parameters for each Oscillator frequency we
*/
}
-/* set up the USB controller with the parameters provided */
-static int init_usb_controller(struct fdt_usb *config,
+/* set up the UTMI USB controller with the parameters provided */
+static int init_utmi_usb_controller(struct fdt_usb *config,
struct usb_ctlr *usbctlr, const u32 timing[])
{
u32 val;
if (!loop_count)
return -1;
- return 0;
-}
+ /* Disable ICUSB FS/LS transceiver */
+ clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
+
+ /* Select UTMI parallel interface */
+ clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+ PTS_UTMI << PTS_SHIFT);
+ clrbits_le32(&usbctlr->port_sc1, STS);
-static void power_up_port(struct usb_ctlr *usbctlr)
-{
/* Deassert power down state */
clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_ULPI
+/* if board file does not set a ULPI reference frequency we default to 24MHz */
+#ifndef CONFIG_ULPI_REF_CLK
+#define CONFIG_ULPI_REF_CLK 24000000
+#endif
+
+/* set up the ULPI USB controller with the parameters provided */
+static int init_ulpi_usb_controller(struct fdt_usb *config,
+ struct usb_ctlr *usbctlr)
+{
+ u32 val;
+ int loop_count;
+ struct ulpi_viewport ulpi_vp;
+
+ /* set up ULPI reference clock on pllp_out4 */
+ clock_enable(PERIPH_ID_DEV2_OUT);
+ clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK);
+
+ /* reset ULPI phy */
+ if (fdt_gpio_isvalid(&config->phy_reset_gpio)) {
+ fdtdec_setup_gpio(&config->phy_reset_gpio);
+ gpio_direction_output(config->phy_reset_gpio.gpio, 0);
+ mdelay(5);
+ gpio_set_value(config->phy_reset_gpio.gpio, 1);
+ }
+
+ /* Reset the usb controller */
+ clock_enable(config->periph_id);
+ usbf_reset_controller(config, usbctlr);
+
+ /* enable pinmux bypass */
+ setbits_le32(&usbctlr->ulpi_timing_ctrl_0,
+ ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
+
+ /* Select ULPI parallel interface */
+ clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
+
+ /* enable ULPI transceiver */
+ setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
+
+ /* configure ULPI transceiver timings */
+ val = 0;
+ writel(val, &usbctlr->ulpi_timing_ctrl_1);
+
+ val |= ULPI_DATA_TRIMMER_SEL(4);
+ val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
+ val |= ULPI_DIR_TRIMMER_SEL(4);
+ writel(val, &usbctlr->ulpi_timing_ctrl_1);
+ udelay(10);
+
+ val |= ULPI_DATA_TRIMMER_LOAD;
+ val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
+ val |= ULPI_DIR_TRIMMER_LOAD;
+ writel(val, &usbctlr->ulpi_timing_ctrl_1);
+
+ /* set up phy for host operation with external vbus supply */
+ ulpi_vp.port_num = 0;
+ ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport;
+
+ if (ulpi_init(&ulpi_vp)) {
+ printf("Tegra ULPI viewport init failed\n");
+ return -1;
+ }
+
+ ulpi_set_vbus(&ulpi_vp, 1, 1);
+ ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0);
+
+ /* enable wakeup events */
+ setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC);
+
+ /* Enable and wait for the phy clock to become valid in 100 ms */
+ setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
+ for (loop_count = 100000; loop_count != 0; loop_count--) {
+ if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
+ break;
+ udelay(1);
+ }
+ if (!loop_count)
+ return -1;
+ clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
+
+ return 0;
+}
+#else
+static int init_ulpi_usb_controller(struct fdt_usb *config,
+ struct usb_ctlr *usbctlr)
+{
+ printf("No code to set up ULPI controller, please enable"
+ "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT");
+ return -1;
}
+#endif
static void config_clock(const u32 timing[])
{
struct usb_ctlr *usbctlr = config->reg;
if (port_count == USB_PORTS_MAX) {
- debug("tegrausb: Cannot register more than %d ports\n",
+ printf("tegrausb: Cannot register more than %d ports\n",
USB_PORTS_MAX);
return -1;
}
- if (init_usb_controller(config, usbctlr, timing)) {
- debug("tegrausb: Cannot init port\n");
+
+ if (config->utmi && init_utmi_usb_controller(config, usbctlr, timing)) {
+ printf("tegrausb: Cannot init port\n");
return -1;
}
- if (config->utmi) {
- /* Disable ICUSB FS/LS transceiver */
- clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
-
- /* Select UTMI parallel interface */
- clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
- PTS_UTMI << PTS_SHIFT);
- clrbits_le32(&usbctlr->port_sc1, STS);
- power_up_port(usbctlr);
+
+ if (config->ulpi && init_ulpi_usb_controller(config, usbctlr)) {
+ printf("tegrausb: Cannot init port\n");
+ return -1;
}
+
port[port_count++] = *config;
return 0;
}
-int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor)
+int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor)
{
struct usb_ctlr *usbctlr;
if (portnum >= port_count)
return -1;
- tegrausb_stop_port();
set_host_mode(&port[portnum]);
usbctlr = port[portnum].reg;
*hccr = (u32)&usbctlr->cap_length;
*hcor = (u32)&usbctlr->usb_cmd;
- port_current = portnum;
return 0;
}
-int tegrausb_stop_port(void)
+int tegrausb_stop_port(int portnum)
{
struct usb_ctlr *usbctlr;
- if (port_current == -1)
- return -1;
-
- usbctlr = port[port_current].reg;
+ usbctlr = port[portnum].reg;
/* Stop controller */
writel(0, &usbctlr->usb_cmd);
/* Initiate controller reset */
writel(2, &usbctlr->usb_cmd);
udelay(1000);
- port_current = -1;
+
return 0;
}
phy = fdt_getprop(blob, node, "phy_type", NULL);
config->utmi = phy && 0 == strcmp("utmi", phy);
+ config->ulpi = phy && 0 == strcmp("ulpi", phy);
config->enabled = fdtdec_get_is_enabled(blob, node);
config->has_legacy_mode = fdtdec_get_bool(blob, node,
"nvidia,has-legacy-mode");
return -FDT_ERR_NOTFOUND;
}
fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio);
- debug("enabled=%d, legacy_mode=%d, utmi=%d, periph_id=%d, vbus=%d, "
- "dr_mode=%d\n", config->enabled, config->has_legacy_mode,
- config->utmi, config->periph_id, config->vbus_gpio.gpio,
- config->dr_mode);
+ fdtdec_decode_gpio(blob, node, "nvidia,phy-reset-gpio",
+ &config->phy_reset_gpio);
+ debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, "
+ "vbus=%d, phy_reset=%d, dr_mode=%d\n",
+ config->enabled, config->has_legacy_mode, config->utmi,
+ config->ulpi, config->periph_id, config->vbus_gpio.gpio,
+ config->phy_reset_gpio.gpio, config->dr_mode);
return 0;
}
return -1;
set_host_mode(&config);
}
- port_current = -1;
return 0;
}
--- /dev/null
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS-y := timer.o
+COBJS-y += cpu.o
+
+COBJS := $(COBJS-y)
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+inline void lowlevel_init(void) {}
+
+void reset_cpu(ulong addr)
+{
+ while (1)
+ ;
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct scu_timer {
+ u32 load; /* Timer Load Register */
+ u32 counter; /* Timer Counter Register */
+ u32 control; /* Timer Control Register */
+};
+
+static struct scu_timer *timer_base =
+ (struct scu_timer *) CONFIG_SCUTIMER_BASEADDR;
+
+#define SCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /* Prescaler */
+#define SCUTIMER_CONTROL_PRESCALER_SHIFT 8
+#define SCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /* Auto-reload */
+#define SCUTIMER_CONTROL_ENABLE_MASK 0x00000001 /* Timer enable */
+
+#define TIMER_LOAD_VAL 0xFFFFFFFF
+#define TIMER_PRESCALE 255
+#define TIMER_TICK_HZ (CONFIG_CPU_FREQ_HZ / 2 / TIMER_PRESCALE)
+
+int timer_init(void)
+{
+ const u32 emask = SCUTIMER_CONTROL_AUTO_RELOAD_MASK |
+ (TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) |
+ SCUTIMER_CONTROL_ENABLE_MASK;
+
+ /* Load the timer counter register */
+ writel(0xFFFFFFFF, &timer_base->counter);
+
+ /*
+ * Start the A9Timer device
+ * Enable Auto reload mode, Clear prescaler control bits
+ * Set prescaler value, Enable the decrementer
+ */
+ clrsetbits_le32(&timer_base->control, SCUTIMER_CONTROL_PRESCALER_MASK,
+ emask);
+
+ /* Reset time */
+ gd->lastinc = readl(&timer_base->counter) /
+ (TIMER_TICK_HZ / CONFIG_SYS_HZ);
+ gd->tbl = 0;
+
+ return 0;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+ulong get_timer_masked(void)
+{
+ ulong now;
+
+ now = readl(&timer_base->counter) / (TIMER_TICK_HZ / CONFIG_SYS_HZ);
+
+ if (gd->lastinc >= now) {
+ /* Normal mode */
+ gd->tbl += gd->lastinc - now;
+ } else {
+ /* We have an overflow ... */
+ gd->tbl += gd->lastinc + TIMER_LOAD_VAL - now;
+ }
+ gd->lastinc = now;
+
+ return gd->tbl;
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned long long tmp;
+ ulong tmo;
+
+ tmo = usec / (1000000 / CONFIG_SYS_HZ);
+ tmp = get_ticks() + tmo; /* Get current timestamp */
+
+ while (get_ticks() < tmp) { /* Loop till event */
+ /* NOP */;
+ }
+}
+
+/* Timer without interrupts */
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
adr r0, _start
cmp r0, r6
+ moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
adr r0, _start
cmp r0, r6
+ moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
#include <errno.h>
#include <linux/compiler.h>
-#define CPU_MASK_PXA_REVID 0x00f
+#define CPU_MASK_PXA_PRODID 0x000003f0
+#define CPU_MASK_PXA_REVID 0x0000000f
+
+#define CPU_MASK_PRODREV (CPU_MASK_PXA_PRODID | CPU_MASK_PXA_REVID)
-#define CPU_MASK_PXA_PRODID 0x3f0
#define CPU_VALUE_PXA25X 0x100
#define CPU_VALUE_PXA27X 0x110
return id == CPU_VALUE_PXA27X;
}
+uint32_t pxa_get_cpu_revision(void)
+{
+ return pxa_get_cpuid() & CPU_MASK_PRODREV;
+}
+
#ifdef CONFIG_DISPLAY_CPUINFO
static const char *pxa25x_get_revision(void)
{
adr r0, _start
cmp r0, r6
+ moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
adr r0, _start
cmp r0, r6
+ moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
adr r0, _start
cmp r0, r6
+ moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
--- /dev/null
+#
+# (C) Copyright 2010,2011 Nvidia Corporation.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)libcputegra-common.o
+
+SOBJS += lowlevel_init.o
+COBJS-y += ap.o board.o sys_info.o timer.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+#include <common.h>
#include <asm/io.h>
-#include <asm/arch/ap20.h>
-#include <asm/arch/fuse.h>
#include <asm/arch/gp_padctrl.h>
-#include <asm/arch/pmc.h>
-#include <asm/arch/scu.h>
-#include <asm/arch/warmboot.h>
-#include <common.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/fuse.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/scu.h>
+#include <asm/arch-tegra/warmboot.h>
int tegra_get_chip_type(void)
{
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
-#include <asm/arch/pmc.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/warmboot.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/sys_proto.h>
+#include <asm/arch-tegra/warmboot.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/timer.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/timer.h>
DECLARE_GLOBAL_DATA_PTR;
LIB = $(obj)lib$(SOC)-common.o
-SOBJS += lowlevel_init.o
-COBJS-y += ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
+COBJS-y += clock.o funcmux.o pinmux.o
COBJS-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o
COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
/* Tegra20 Clock control functions */
+#include <common.h>
#include <asm/io.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
-#include <asm/arch/timer.h>
-#include <asm/arch/tegra20.h>
-#include <common.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
#include <div64.h>
#include <fdtdec.h>
NONE(CRAM2),
};
+/* number of clock outputs of a PLL */
+static const u8 pll_num_clkouts[] = {
+ 1, /* PLLC */
+ 1, /* PLLM */
+ 4, /* PLLP */
+ 1, /* PLLA */
+ 0, /* PLLU */
+ 0, /* PLLD */
+};
+
/*
* Get the oscillator frequency, from the corresponding hardware configuration
* field.
case PERIPH_ID_RESERVED81:
case PERIPH_ID_RESERVED82:
case PERIPH_ID_RESERVED83:
+ case PERIPH_ID_RESERVED91:
printf("Peripheral id %d is reserved\n", id);
break;
default:
(readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
}
+int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
+{
+ struct clk_pll *pll = get_pll(clkid);
+ int data = 0, div = 0, offset = 0;
+
+ if (!clock_id_is_pll(clkid))
+ return -1;
+
+ if (pllout + 1 > pll_num_clkouts[clkid])
+ return -1;
+
+ div = clk_get_divider(8, pll_rate[clkid], rate);
+
+ if (div < 0)
+ return -1;
+
+ /* out2 and out4 are in the high part of the register */
+ if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
+ offset = 16;
+
+ data = (div << PLL_OUT_RATIO_SHIFT) |
+ PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
+ clrsetbits_le32(&pll->pll_out[pllout >> 1],
+ PLL_OUT_RATIO_MASK << offset, data << offset);
+
+ return 0;
+}
+
/**
* Find the best available 7.1 format divisor given a parent clock rate and
* required child clock rate. This function assumes that a second-stage
#include <common.h>
#include <fdtdec.h>
#include <asm/io.h>
-#include <asm/arch/ap20.h>
+#include <asm/arch-tegra/ap.h>
#include <asm/arch/apb_misc.h>
#include <asm/arch/clock.h>
#include <asm/arch/emc.h>
-#include <asm/arch/tegra20.h>
+#include <asm/arch/tegra.h>
/*
* The EMC registers have shadow registers. When the EMC clock is updated
break;
case PERIPH_ID_NDFLASH:
- if (config == FUNCMUX_NDFLASH_ATC) {
+ switch (config) {
+ case FUNCMUX_NDFLASH_ATC:
pinmux_set_func(PINGRP_ATC, PMUX_FUNC_NAND);
pinmux_tristate_disable(PINGRP_ATC);
+ break;
+ case FUNCMUX_NDFLASH_KBC_8_BIT:
+ pinmux_set_func(PINGRP_KBCA, PMUX_FUNC_NAND);
+ pinmux_set_func(PINGRP_KBCC, PMUX_FUNC_NAND);
+ pinmux_set_func(PINGRP_KBCD, PMUX_FUNC_NAND);
+ pinmux_set_func(PINGRP_KBCE, PMUX_FUNC_NAND);
+ pinmux_set_func(PINGRP_KBCF, PMUX_FUNC_NAND);
+
+ pinmux_tristate_disable(PINGRP_KBCA);
+ pinmux_tristate_disable(PINGRP_KBCC);
+ pinmux_tristate_disable(PINGRP_KBCD);
+ pinmux_tristate_disable(PINGRP_KBCE);
+ pinmux_tristate_disable(PINGRP_KBCF);
+
+ bad_config = 0;
+ break;
}
break;
/* Tegra20 pin multiplexing functions */
+#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
+#include <asm/arch/tegra.h>
#include <asm/arch/pinmux.h>
-#include <common.h>
/*
#include <common.h>
#include <tps6586x.h>
#include <asm/io.h>
-#include <asm/arch/ap20.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/tegra_i2c.h>
-#include <asm/arch/sys_proto.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <asm/arch-tegra/sys_proto.h>
#define VDD_CORE_NOMINAL_T25 0x17 /* 1.3v */
#define VDD_CPU_NOMINAL_T25 0x10 /* 1.125v */
#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
-#include <asm/arch/ap20.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
-#include <asm/arch/pmc.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/fuse.h>
#include <asm/arch/emc.h>
#include <asm/arch/gp_padctrl.h>
-#include <asm/arch/warmboot.h>
+#include <asm/arch/pinmux.h>
#include <asm/arch/sdram_param.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/fuse.h>
+#include <asm/arch-tegra/warmboot.h>
DECLARE_GLOBAL_DATA_PTR;
/* Populate the header. */
dst_header->length_insecure = length + sizeof(struct wb_header);
dst_header->length_secure = length + sizeof(struct wb_header);
- dst_header->destination = AP20_WB_RUN_ADDRESS;
- dst_header->entry_point = AP20_WB_RUN_ADDRESS;
+ dst_header->destination = NV_WB_RUN_ADDRESS;
+ dst_header->entry_point = NV_WB_RUN_ADDRESS;
dst_header->code_length = length;
if (is_encrypted) {
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/ap20.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/flow.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/pmc.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/warmboot.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/warmboot.h>
#include "warmboot_avp.h"
#define DEBUG_RESET_CORESIGHT
/* no input, no clobber list */
);
- if (reg != AP20_WB_RUN_ADDRESS)
+ if (reg != NV_WB_RUN_ADDRESS)
goto do_reset;
/* Are we running with AVP? */
reg = PLLM_OUT1_RSTN_RESET_DISABLE | PLLM_OUT1_CLKEN_ENABLE |
PLLM_OUT1_RATIO_VAL_8;
- writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out);
+ writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out[0]);
reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 |
SCLK_SWAKE_RUN_SRC_PLLM_OUT1 | SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 |
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
+#include <ipu_pixfmt.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
return get_periph_clk() / (ahb_podf + 1);
}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+void arch_preboot_os(void)
+{
+ /* disable video before launching O/S */
+ ipuv3_fb_shutdown();
+}
+#endif
{
#ifdef CONFIG_FSL_ESDHC
#ifdef CONFIG_FSL_USDHC
+#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+#else
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+#else
+#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
#else
- gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
#endif
#endif
return 0;
#include <asm/io.h>
#include <div64.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
/* General purpose timers registers */
struct mxc_gpt {
#define GPTCR_FRR (1 << 9) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
-#define CLK_32KHZ 32768 /* 32Khz input */
DECLARE_GLOBAL_DATA_PTR;
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
- do_div(tick, CLK_32KHZ);
+ do_div(tick, MXC_CLK32);
return tick;
}
static inline unsigned long long us_to_tick(unsigned long long usec)
{
- usec = usec * CLK_32KHZ + 999999;
+ usec = usec * MXC_CLK32 + 999999;
do_div(usec, 1000000);
return usec;
__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
val = __raw_readl(&cur_gpt->counter);
- lastinc = val / (CLK_32KHZ / CONFIG_SYS_HZ);
+ lastinc = val / (MXC_CLK32 / CONFIG_SYS_HZ);
timestamp = 0;
return 0;
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
- * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+ * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
*/
ulong get_tbclk(void)
{
- return CLK_32KHZ;
+ return MXC_CLK32;
}
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_SPL_H_
+#define BOOT_DEVICE_XIP 2
#define BOOT_DEVICE_NAND 5
#define BOOT_DEVICE_MMC1 8
#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
#define BOOT_DEVICE_UART 65
+#define BOOT_DEVICE_CPGMAC 70
#define BOOT_DEVICE_MMC2_2 0xFF
#endif
--- /dev/null
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _GLOBALTIMER_H_
+#define _GLOBALTIMER_H_
+
+struct globaltimer {
+ u32 cnt_l; /* 0x00 */
+ u32 cnt_h;
+ u32 ctl;
+ u32 stat;
+ u32 cmp_l; /* 0x10 */
+ u32 cmp_h;
+ u32 inc;
+};
+
+#endif /* _GLOBALTIMER_H_ */
/*
* functions
*/
-void reset_cpu(unsigned long ignored);
unsigned char get_random_hex(void);
unsigned int kw_sdram_bar(enum memory_bank bank);
unsigned int kw_sdram_bs(enum memory_bank bank);
+void kw_sdram_size_adjust(enum memory_bank bank);
int kw_config_adr_windows(void);
void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
unsigned int gpp0_oe, unsigned int gpp1_oe);
#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 )
#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 )
-#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 )
+#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 )
#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 )
#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 )
#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 )
#endif
enum mxc_clock {
+ /* PER clocks (do not change order) */
MXC_CSI_CLK,
MXC_EPIT_CLK,
MXC_ESAI_CLK,
MXC_SSI1_CLK,
MXC_SSI2_CLK,
MXC_UART_CLK,
+ /* Other clocks */
MXC_ARM_CLK,
+ MXC_AHB_CLK,
+ MXC_IPG_CLK,
+ MXC_CSPI_CLK,
MXC_FEC_CLK,
MXC_CLK_NUM
};
-ulong imx_get_perclk(int clk);
-ulong imx_get_ahbclk(void);
-
-#define imx_get_uartclk() imx_get_perclk(15)
-#define imx_get_fecclk() (imx_get_ahbclk()/2)
-
unsigned int mxc_get_clock(enum mxc_clock clk);
+#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK)
+#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
+
#endif /* __ASM_ARCH_CLOCK_H */
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_1 0x11
+#define CHIP_REV_1_2 0x12
#endif /* _IMX_REGS_H */
#include <asm/arch/imx-regs.h>
#include <generated/asm-offsets.h>
+#include <asm/macro.h>
-.macro init_aips
- write32 IMX_AIPS1_BASE + AIPS_MPR_0_7, 0x77777777
- write32 IMX_AIPS1_BASE + AIPS_MPR_8_15, 0x77777777
- write32 IMX_AIPS2_BASE + AIPS_MPR_0_7, 0x77777777
- write32 IMX_AIPS2_BASE + AIPS_MPR_8_15, 0x77777777
+/*
+ * AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.
+ *
+ * Default argument values:
+ * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
+ * user-mode.
+ */
+.macro init_aips mpr=0x77777777
+ ldr r0, =IMX_AIPS1_BASE
+ ldr r1, =\mpr
+ str r1, [r0, #AIPS_MPR_0_7]
+ str r1, [r0, #AIPS_MPR_8_15]
+ ldr r2, =IMX_AIPS2_BASE
+ str r1, [r2, #AIPS_MPR_0_7]
+ str r1, [r2, #AIPS_MPR_8_15]
.endm
-.macro init_max
- write32 IMX_MAX_BASE + MAX_MPR0, 0x43210
- write32 IMX_MAX_BASE + MAX_MPR1, 0x43210
- write32 IMX_MAX_BASE + MAX_MPR2, 0x43210
- write32 IMX_MAX_BASE + MAX_MPR3, 0x43210
- write32 IMX_MAX_BASE + MAX_MPR4, 0x43210
-
- write32 IMX_MAX_BASE + MAX_SGPCR0, 0x10
- write32 IMX_MAX_BASE + MAX_SGPCR1, 0x10
- write32 IMX_MAX_BASE + MAX_SGPCR2, 0x10
- write32 IMX_MAX_BASE + MAX_SGPCR3, 0x10
- write32 IMX_MAX_BASE + MAX_SGPCR4, 0x10
+/*
+ * MAX (Multi-Layer AHB Crossbar Switch) setup
+ *
+ * Default argument values:
+ * - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA
+ * - SGPCR: always park on last master
+ * - MGPCR: restore default values
+ */
+.macro init_max mpr=0x00043210, sgpcr=0x00000010, mgpcr=0x00000000
+ ldr r0, =IMX_MAX_BASE
+ ldr r1, =\mpr
+ str r1, [r0, #MAX_MPR0] /* for S0 */
+ str r1, [r0, #MAX_MPR1] /* for S1 */
+ str r1, [r0, #MAX_MPR2] /* for S2 */
+ str r1, [r0, #MAX_MPR3] /* for S3 */
+ str r1, [r0, #MAX_MPR4] /* for S4 */
+ ldr r1, =\sgpcr
+ str r1, [r0, #MAX_SGPCR0] /* for S0 */
+ str r1, [r0, #MAX_SGPCR1] /* for S1 */
+ str r1, [r0, #MAX_SGPCR2] /* for S2 */
+ str r1, [r0, #MAX_SGPCR3] /* for S3 */
+ str r1, [r0, #MAX_SGPCR4] /* for S4 */
+ ldr r1, =\mgpcr
+ str r1, [r0, #MAX_MGPCR0] /* for M0 */
+ str r1, [r0, #MAX_MGPCR1] /* for M1 */
+ str r1, [r0, #MAX_MGPCR2] /* for M2 */
+ str r1, [r0, #MAX_MGPCR3] /* for M3 */
+ str r1, [r0, #MAX_MGPCR4] /* for M4 */
+.endm
- write32 IMX_MAX_BASE + MAX_MGPCR0, 0x0
- write32 IMX_MAX_BASE + MAX_MGPCR1, 0x0
- write32 IMX_MAX_BASE + MAX_MGPCR2, 0x0
- write32 IMX_MAX_BASE + MAX_MGPCR3, 0x0
- write32 IMX_MAX_BASE + MAX_MGPCR4, 0x0
+/*
+ * M3IF setup
+ *
+ * Default argument values:
+ * - CTL:
+ * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
+ * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
+ * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
+ * MRRP[3] = USBH not on priority list (0 << 3) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
+ * MRRP[5] = eSDHC1/ATA/FEC not on priority list (0 << 5) = 0x00000000
+ * MRRP[6] = LCDC/SLCDC/MAX2 not on priority list (0 << 6) = 0x00000000
+ * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
+ * ------------
+ * 0x00000001
+ */
+.macro init_m3if ctl=0x00000001
+ /* M3IF Control Register (M3IFCTL) */
+ write32 IMX_M3IF_CTRL_BASE, \ctl
.endm
#endif /* __ASSEMBLY__ */
MXC_UART_CLK,
MXC_IPU_CLK,
MXC_ESDHC_CLK,
+ MXC_I2C_CLK,
};
unsigned int mxc_get_clock(enum mxc_clock clk);
#define MX31_IIM_BASE_ADDR 0x5001C000
-#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
+#define PDR0_CSI_PODF(x) (((x) & 0x3f) << 26)
+#define PDR0_CSI_PRDF(x) (((x) & 0x7) << 23)
#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
#define PDR0_MCU_PODF(x) ((x) & 0x7)
+#define PDR1_USB_PRDF(x) (((x) & 0x3) << 30)
+#define PDR1_USB_PODF(x) (((x) & 0x7) << 27)
+#define PDR1_FIRI_PRDF(x) (((x) & 0x7) << 24)
+#define PDR1_FIRI_PODF(x) (((x) & 0x3f) << 18)
+#define PDR1_SSI2_PRDF(x) (((x) & 0x7) << 15)
+#define PDR1_SSI2_PODF(x) (((x) & 0x3f) << 9)
+#define PDR1_SSI1_PRDF(x) (((x) & 0x7) << 6)
+#define PDR1_SSI1_PODF(x) ((x) & 0x3f)
+
+#define PLL_BRMO(x) (((x) & 0x1) << 31)
#define PLL_PD(x) (((x) & 0xf) << 26)
#define PLL_MFD(x) (((x) & 0x3ff) << 16)
#define PLL_MFI(x) (((x) & 0xf) << 10)
#define PLL_MFN(x) (((x) & 0x3ff) << 0)
-#define GET_PDR0_CSI_PODF(x) (((x) >> 23) & 0x1ff)
+#define GET_PDR0_CSI_PODF(x) (((x) >> 26) & 0x3f)
+#define GET_PDR0_CSI_PRDF(x) (((x) >> 23) & 0x7)
#define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f)
#define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7)
#define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7)
MXC_USB_CLK,
MXC_CSPI_CLK,
MXC_FEC_CLK,
+ MXC_I2C_CLK,
};
enum mxc_main_clock {
#define ESDC_MISC_DDR_EN (1 << 8)
#define ESDC_MISC_DDR2_EN (1 << 9)
+/* Multi-Layer AHB Crossbar Switch (MAX) registers */
+struct max_regs {
+ u32 mpr0;
+ u32 pad00[3];
+ u32 sgpcr0;
+ u32 pad01[59];
+ u32 mpr1;
+ u32 pad02[3];
+ u32 sgpcr1;
+ u32 pad03[59];
+ u32 mpr2;
+ u32 pad04[3];
+ u32 sgpcr2;
+ u32 pad05[59];
+ u32 mpr3;
+ u32 pad06[3];
+ u32 sgpcr3;
+ u32 pad07[59];
+ u32 mpr4;
+ u32 pad08[3];
+ u32 sgpcr4;
+ u32 pad09[251];
+ u32 mgpcr0;
+ u32 pad10[63];
+ u32 mgpcr1;
+ u32 pad11[63];
+ u32 mgpcr2;
+ u32 pad12[63];
+ u32 mgpcr3;
+ u32 pad13[63];
+ u32 mgpcr4;
+ u32 pad14[63];
+ u32 mgpcr5;
+};
+
+/* AHB <-> IP-Bus Interface (AIPS) */
+struct aips_regs {
+ u32 mpr_0_7;
+ u32 mpr_8_15;
+ u32 pad0[6];
+ u32 pacr_0_7;
+ u32 pacr_8_15;
+ u32 pacr_16_23;
+ u32 pacr_24_31;
+ u32 pad1[4];
+ u32 opacr_0_7;
+ u32 opacr_8_15;
+ u32 opacr_16_23;
+ u32 opacr_24_31;
+ u32 opacr_32_39;
+};
+
/*
* NFMS bit in RCSR register for pagesize of nandflash
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
+#include <common.h>
+
+#ifdef CONFIG_SYS_MX5_HCLK
+#define MXC_HCLK CONFIG_SYS_MX5_HCLK
+#else
+#define MXC_HCLK 24000000
+#endif
+
+#ifdef CONFIG_SYS_MX5_CLK32
+#define MXC_CLK32 CONFIG_SYS_MX5_CLK32
+#else
+#define MXC_CLK32 32768
+#endif
+
enum mxc_clock {
MXC_ARM_CLK = 0,
MXC_AHB_CLK,
MXC_IPG_PERCLK,
MXC_UART_CLK,
MXC_CSPI_CLK,
+ MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
+ MXC_ESDHC4_CLK,
MXC_FEC_CLK,
MXC_SATA_CLK,
MXC_DDR_CLK,
MXC_NFC_CLK,
MXC_PERIPH_CLK,
+ MXC_I2C_CLK,
};
u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
-void set_usb_phy2_clk(void);
+void set_usb_phy_clk(void);
+void enable_usb_phy1_clk(unsigned char enable);
void enable_usb_phy2_clk(unsigned char enable);
void set_usboh3_clk(void);
void enable_usboh3_clk(unsigned char enable);
u32 cmeor;
};
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_COSC_EN (0x1 << 12)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCR_FPM_MULT (0x1 << 11)
+#endif
+#define MXC_CCM_CCR_CAMP2_EN (0x1 << 10)
+#define MXC_CCM_CCR_CAMP1_EN (0x1 << 9)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCR_FPM_EN (0x1 << 8)
+#endif
+#define MXC_CCM_CCR_OSCNT_OFFSET 0
+#define MXC_CCM_CCR_OSCNT_MASK 0xFF
+#define MXC_CCM_CCR_OSCNT(v) ((v) & 0xFF)
+#define MXC_CCM_CCR_OSCNT_RD(r) ((r) & 0xFF)
+
+/* Define the bits in register CCSR */
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCSR_LP_APM (0x1 << 9)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCSR_LP_APM (0x1 << 10)
+#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (0x1 << 9)
+#endif
+#define MXC_CCM_CCSR_STEP_SEL_OFFSET 7
+#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
+#define MXC_CCM_CCSR_STEP_SEL(v) (((v) & 0x3) << 7)
+#define MXC_CCM_CCSR_STEP_SEL_RD(r) (((r) >> 7) & 0x3)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET 5
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK (0x3 << 5)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF(v) (((v) & 0x3) << 5)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r) (((r) >> 5) & 0x3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET 3
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK (0x3 << 3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF(v) (((v) & 0x3) << 3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r) (((r) >> 3) & 0x3)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (0x1 << 2)
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (0x1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL 0x1
+
/* Define the bits in register CACRR */
#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
+#define MXC_CCM_CACRR_ARM_PODF(v) ((v) & 0x7)
+#define MXC_CCM_CACRR_ARM_PODF_RD(r) ((r) & 0x7)
/* Define the bits in register CBCDR */
#define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30)
-#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
#define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27
+#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
+#define MXC_CCM_CBCDR_DDR_PODF(v) (((v) & 0x7) << 27)
+#define MXC_CCM_CBCDR_DDR_PODF_RD(r) (((r) >> 27) & 0x7)
#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
#define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22
#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
+#define MXC_CCM_CBCDR_EMI_PODF(v) (((v) & 0x7) << 22)
+#define MXC_CCM_CBCDR_EMI_PODF_RD(r) (((r) >> 22) & 0x7)
#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19
#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CBCDR_AXI_B_PODF(v) (((v) & 0x7) << 19)
+#define MXC_CCM_CBCDR_AXI_B_PODF_RD(r) (((r) >> 19) & 0x7)
#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16
#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CBCDR_AXI_A_PODF(v) (((v) & 0x7) << 16)
+#define MXC_CCM_CBCDR_AXI_A_PODF_RD(r) (((r) >> 16) & 0x7)
#define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13
#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
+#define MXC_CCM_CBCDR_NFC_PODF(v) (((v) & 0x7) << 13)
+#define MXC_CCM_CBCDR_NFC_PODF_RD(r) (((r) >> 13) & 0x7)
#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
+#define MXC_CCM_CBCDR_AHB_PODF(v) (((v) & 0x7) << 10)
+#define MXC_CCM_CBCDR_AHB_PODF_RD(r) (((r) >> 10) & 0x7)
#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
+#define MXC_CCM_CBCDR_IPG_PODF(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CBCDR_IPG_PODF_RD(r) (((r) >> 8) & 0x3)
#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6
#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED1(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r) (((r) >> 6) & 0x3)
#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3
#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2(v) (((v) & 0x7) << 3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r) (((r) >> 3) & 0x7)
#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0
#define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7
+#define MXC_CCM_CBCDR_PERCLK_PODF(v) ((v) & 0x7)
+#define MXC_CCM_CBCDR_PERCLK_PODF_RD(r) ((r) & 0x7)
/* Define the bits in register CSCMR1 */
#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30
#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v) (((v) & 0x3) << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r) (((r) >> 30) & 0x3)
#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28
#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET 26
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v) (((v) & 0x3) << 28)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r) (((r) >> 28) & 0x3)
#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24
#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL(v) (((v) & 0x3) << 24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r) (((r) >> 24) & 0x3)
#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22
#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v) (((v) & 0x3) << 22)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r) (((r) >> 22) & 0x3)
#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20
#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v) (((v) & 0x3) << 20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r) (((r) >> 20) & 0x3)
#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16
#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v) (((v) & 0x3) << 16)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r) (((r) >> 16) & 0x3)
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v) (((v) & 0x3) << 14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r) (((r) >> 14) & 0x3)
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v) (((v) & 0x3) << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r) (((r) >> 12) & 0x3)
#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8
#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r) (((r) >> 8) & 0x3)
#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4
#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v) (((v) & 0x3) << 4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r) (((r) >> 4) & 0x3)
#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2
#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v) (((v) & 0x3) << 2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r) (((r) >> 2) & 0x3)
#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1
/* Define the bits in register CSCDR2 */
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v) (((v) & 0x7) << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r) (((r) >> 25) & 0x7)
#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19
#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v) (((v) & 0x3F) << 19)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r) (((r) >> 19) & 0x3F)
#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16
#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED(v) (((v) & 0x7) << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r) (((r) >> 16) & 0x7)
#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9
#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF(v) (((v) & 0x3F) << 9)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r) (((r) >> 9) & 0x3F)
#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6
-#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET 0
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK 0x3F
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v) (((v) & 0x7) << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r) (((r) >> 6) & 0x7)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET 0
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK 0x3F
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v) ((v) & 0x3F)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r) ((r) & 0x3F)
/* Define the bits in register CBCMR */
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v) (((v) & 0x3) << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r) (((r) >> 14) & 0x3)
#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12
#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v) (((v) & 0x3) << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r) (((r) >> 12) & 0x3)
#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10
#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL(v) (((v) & 0x3) << 10)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r) (((r) >> 10) & 0x3)
#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8
#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r) (((r) >> 8) & 0x3)
#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6
#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r) (((r) >> 6) & 0x3)
#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4
#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL(v) (((v) & 0x3) << 4)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r) (((r) >> 4) & 0x3)
#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
/* Define the bits in register CSCDR1 */
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v) (((v) & 0x7) << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r) (((r) >> 22) & 0x7)
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v) (((v) & 0x7) << 19)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r) (((r) >> 19) & 0x7)
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v) (((v) & 0x7) << 16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r) (((r) >> 16) & 0x7)
#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14
#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF(v) (((v) & 0x3) << 14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r) (((r) >> 14) & 0x3)
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v) (((v) & 0x7) << 11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r) (((r) >> 11) & 0x7)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v) (((v) & 0x7) << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r) (((r) >> 8) & 0x7)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r) (((r) >> 6) & 0x3)
#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3
#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED(v) (((v) & 0x7) << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r) (((r) >> 3) & 0x7)
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7
+#define MXC_CCM_CSCDR1_UART_CLK_PODF(v) ((v) & 0x7)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r) ((r) & 0x7)
/* Define the bits in register CCDR */
#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
/* Define the bits in register CCGRx */
#define MXC_CCM_CCGR_CG_MASK 0x3
+#define MXC_CCM_CCGR_CG_OFF 0x0
+#define MXC_CCM_CCGR_CG_RUN_ON 0x1
+#define MXC_CCM_CCGR_CG_ON 0x3
+
+#define MXC_CCM_CCGR0_ARM_BUS_OFFSET 0
+#define MXC_CCM_CCGR0_ARM_BUS(v) (((v) & 0x3) << 0)
+#define MXC_CCM_CCGR0_ARM_AXI_OFFSET 2
+#define MXC_CCM_CCGR0_ARM_AXI(v) (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET 4
+#define MXC_CCM_CCGR0_ARM_DEBUG(v) (((v) & 0x3) << 4)
+#define MXC_CCM_CCGR0_TZIC_OFFSET 6
+#define MXC_CCM_CCGR0_TZIC(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR0_DAP_OFFSET 8
+#define MXC_CCM_CCGR0_DAP(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR0_TPIU_OFFSET 10
+#define MXC_CCM_CCGR0_TPIU(v) (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR0_CTI2_OFFSET 12
+#define MXC_CCM_CCGR0_CTI2(v) (((v) & 0x3) << 12)
+#define MXC_CCM_CCGR0_CTI3_OFFSET 14
+#define MXC_CCM_CCGR0_CTI3(v) (((v) & 0x3) << 14)
+#define MXC_CCM_CCGR0_AHBMUX1_OFFSET 16
+#define MXC_CCM_CCGR0_AHBMUX1(v) (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR0_AHBMUX2_OFFSET 18
+#define MXC_CCM_CCGR0_AHBMUX2(v) (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR0_ROMCP_OFFSET 20
+#define MXC_CCM_CCGR0_ROMCP(v) (((v) & 0x3) << 20)
+#define MXC_CCM_CCGR0_ROM_OFFSET 22
+#define MXC_CCM_CCGR0_ROM(v) (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 24
+#define MXC_CCM_CCGR0_AIPS_TZ1(v) (((v) & 0x3) << 24)
+#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 26
+#define MXC_CCM_CCGR0_AIPS_TZ2(v) (((v) & 0x3) << 26)
+#define MXC_CCM_CCGR0_AHB_MAX_OFFSET 28
+#define MXC_CCM_CCGR0_AHB_MAX(v) (((v) & 0x3) << 28)
+#define MXC_CCM_CCGR0_IIM_OFFSET 30
+#define MXC_CCM_CCGR0_IIM(v) (((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR1_TMAX1_OFFSET 0
+#define MXC_CCM_CCGR1_TMAX1(v) (((v) & 0x3) << 0)
+#define MXC_CCM_CCGR1_TMAX2_OFFSET 2
+#define MXC_CCM_CCGR1_TMAX2(v) (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR1_TMAX3_OFFSET 4
+#define MXC_CCM_CCGR1_TMAX3(v) (((v) & 0x3) << 4)
+#define MXC_CCM_CCGR1_UART1_IPG_OFFSET 6
+#define MXC_CCM_CCGR1_UART1_IPG(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR1_UART1_PER_OFFSET 8
+#define MXC_CCM_CCGR1_UART1_PER(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR1_UART2_IPG_OFFSET 10
+#define MXC_CCM_CCGR1_UART2_IPG(v) (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR1_UART2_PER_OFFSET 12
+#define MXC_CCM_CCGR1_UART2_PER(v) (((v) & 0x3) << 12)
+#define MXC_CCM_CCGR1_UART3_IPG_OFFSET 14
+#define MXC_CCM_CCGR1_UART3_IPG(v) (((v) & 0x3) << 14)
+#define MXC_CCM_CCGR1_UART3_PER_OFFSET 16
+#define MXC_CCM_CCGR1_UART3_PER(v) (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR1_I2C1_OFFSET 18
+#define MXC_CCM_CCGR1_I2C1(v) (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR1_I2C2_OFFSET 20
+#define MXC_CCM_CCGR1_I2C2(v) (((v) & 0x3) << 20)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET 22
+#define MXC_CCM_CCGR1_HSI2C_IPG(v) (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET 24
+#define MXC_CCM_CCGR1_HSI2C_SERIAL(v) (((v) & 0x3) << 24)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR1_I2C3_OFFSET 22
+#define MXC_CCM_CCGR1_I2C3(v) (((v) & 0x3) << 22)
+#endif
+#define MXC_CCM_CCGR1_FIRI_IPG_OFFSET 26
+#define MXC_CCM_CCGR1_FIRI_IPG(v) (((v) & 0x3) << 26)
+#define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET 28
+#define MXC_CCM_CCGR1_FIRI_SERIAL(v) (((v) & 0x3) << 28)
+#define MXC_CCM_CCGR1_SCC_OFFSET 30
+#define MXC_CCM_CCGR1_SCC(v) (((v) & 0x3) << 30)
+
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR2_USB_PHY_OFFSET 0
+#define MXC_CCM_CCGR2_USB_PHY(v) (((v) & 0x3) << 0)
+#endif
+#define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET 2
+#define MXC_CCM_CCGR2_EPIT1_IPG(v) (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR2_EPIT1_HF_OFFSET 4
+#define MXC_CCM_CCGR2_EPIT1_HF(v) (((v) & 0x3) << 4)
+#define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET 6
+#define MXC_CCM_CCGR2_EPIT2_IPG(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR2_EPIT2_HF_OFFSET 8
+#define MXC_CCM_CCGR2_EPIT2_HF(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR2_PWM1_IPG_OFFSET 10
+#define MXC_CCM_CCGR2_PWM1_IPG(v) (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR2_PWM1_HF_OFFSET 12
+#define MXC_CCM_CCGR2_PWM1_HF(v) (((v) & 0x3) << 12)
+#define MXC_CCM_CCGR2_PWM2_IPG_OFFSET 14
+#define MXC_CCM_CCGR2_PWM2_IPG(v) (((v) & 0x3) << 14)
+#define MXC_CCM_CCGR2_PWM2_HF_OFFSET 16
+#define MXC_CCM_CCGR2_PWM2_HF(v) (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR2_GPT_IPG_OFFSET 18
+#define MXC_CCM_CCGR2_GPT_IPG(v) (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR2_GPT_HF_OFFSET 20
+#define MXC_CCM_CCGR2_GPT_HF(v) (((v) & 0x3) << 20)
+#define MXC_CCM_CCGR2_OWIRE_OFFSET 22
+#define MXC_CCM_CCGR2_OWIRE(v) (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR2_FEC_OFFSET 24
+#define MXC_CCM_CCGR2_FEC(v) (((v) & 0x3) << 24)
+#define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET 26
+#define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v) (((v) & 0x3) << 26)
+#define MXC_CCM_CCGR2_USBOH3_60M_OFFSET 28
+#define MXC_CCM_CCGR2_USBOH3_60M(v) (((v) & 0x3) << 28)
+#define MXC_CCM_CCGR2_TVE_OFFSET 30
+#define MXC_CCM_CCGR2_TVE(v) (((v) & 0x3) << 30)
-#define MXC_CCM_CCGR4_CG5_OFFSET 10
-#define MXC_CCM_CCGR4_CG6_OFFSET 12
-#define MXC_CCM_CCGR5_CG5_OFFSET 10
-#define MXC_CCM_CCGR2_CG14_OFFSET 28
+#define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET 0
+#define MXC_CCM_CCGR3_ESDHC1_IPG(v) (((v) & 0x3) << 0)
+#define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET 2
+#define MXC_CCM_CCGR3_ESDHC1_PER(v) (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET 4
+#define MXC_CCM_CCGR3_ESDHC2_IPG(v) (((v) & 0x3) << 4)
+#define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET 6
+#define MXC_CCM_CCGR3_ESDHC2_PER(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET 8
+#define MXC_CCM_CCGR3_ESDHC3_IPG(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET 10
+#define MXC_CCM_CCGR3_ESDHC3_PER(v) (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET 12
+#define MXC_CCM_CCGR3_ESDHC4_IPG(v) (((v) & 0x3) << 12)
+#define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET 14
+#define MXC_CCM_CCGR3_ESDHC4_PER(v) (((v) & 0x3) << 14)
+#define MXC_CCM_CCGR3_SSI1_IPG_OFFSET 16
+#define MXC_CCM_CCGR3_SSI1_IPG(v) (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR3_SSI1_SSI_OFFSET 18
+#define MXC_CCM_CCGR3_SSI1_SSI(v) (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR3_SSI2_IPG_OFFSET 20
+#define MXC_CCM_CCGR3_SSI2_IPG(v) (((v) & 0x3) << 20)
+#define MXC_CCM_CCGR3_SSI2_SSI_OFFSET 22
+#define MXC_CCM_CCGR3_SSI2_SSI(v) (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR3_SSI3_IPG_OFFSET 24
+#define MXC_CCM_CCGR3_SSI3_IPG(v) (((v) & 0x3) << 24)
+#define MXC_CCM_CCGR3_SSI3_SSI_OFFSET 26
+#define MXC_CCM_CCGR3_SSI3_SSI(v) (((v) & 0x3) << 26)
+#define MXC_CCM_CCGR3_SSI_EXT1_OFFSET 28
+#define MXC_CCM_CCGR3_SSI_EXT1(v) (((v) & 0x3) << 28)
+#define MXC_CCM_CCGR3_SSI_EXT2_OFFSET 30
+#define MXC_CCM_CCGR3_SSI_EXT2(v) (((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR4_PATA_OFFSET 0
+#define MXC_CCM_CCGR4_PATA(v) (((v) & 0x3) << 0)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR4_SIM_IPG_OFFSET 2
+#define MXC_CCM_CCGR4_SIM_IPG(v) (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET 4
+#define MXC_CCM_CCGR4_SIM_SERIAL(v) (((v) & 0x3) << 4)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR4_SATA_OFFSET 2
+#define MXC_CCM_CCGR4_SATA(v) (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR4_CAN2_IPG_OFFSET 6
+#define MXC_CCM_CCGR4_CAN2_IPG(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET 8
+#define MXC_CCM_CCGR4_CAN2_SERIAL(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR4_USB_PHY1_OFFSET 10
+#define MXC_CCM_CCGR4_USB_PHY1(v) (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR4_USB_PHY2_OFFSET 12
+#define MXC_CCM_CCGR4_USB_PHY2(v) (((v) & 0x3) << 12)
+#endif
+#define MXC_CCM_CCGR4_SAHARA_OFFSET 14
+#define MXC_CCM_CCGR4_SAHARA(v) (((v) & 0x3) << 14)
+#define MXC_CCM_CCGR4_RTIC_OFFSET 16
+#define MXC_CCM_CCGR4_RTIC(v) (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET 18
+#define MXC_CCM_CCGR4_ECSPI1_IPG(v) (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET 20
+#define MXC_CCM_CCGR4_ECSPI1_PER(v) (((v) & 0x3) << 20)
+#define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET 22
+#define MXC_CCM_CCGR4_ECSPI2_IPG(v) (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET 24
+#define MXC_CCM_CCGR4_ECSPI2_PER(v) (((v) & 0x3) << 24)
+#define MXC_CCM_CCGR4_CSPI_IPG_OFFSET 26
+#define MXC_CCM_CCGR4_CSPI_IPG(v) (((v) & 0x3) << 26)
+#define MXC_CCM_CCGR4_SRTC_OFFSET 28
+#define MXC_CCM_CCGR4_SRTC(v) (((v) & 0x3) << 28)
+#define MXC_CCM_CCGR4_SDMA_OFFSET 30
+#define MXC_CCM_CCGR4_SDMA(v) (((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR5_SPBA_OFFSET 0
+#define MXC_CCM_CCGR5_SPBA(v) (((v) & 0x3) << 0)
+#define MXC_CCM_CCGR5_GPU_OFFSET 2
+#define MXC_CCM_CCGR5_GPU(v) (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR5_GARB_OFFSET 4
+#define MXC_CCM_CCGR5_GARB(v) (((v) & 0x3) << 4)
+#define MXC_CCM_CCGR5_VPU_OFFSET 6
+#define MXC_CCM_CCGR5_VPU(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR5_VPU_REF_OFFSET 8
+#define MXC_CCM_CCGR5_VPU_REF(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR5_IPU_OFFSET 10
+#define MXC_CCM_CCGR5_IPU(v) (((v) & 0x3) << 10)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR5_IPUMUX12_OFFSET 12
+#define MXC_CCM_CCGR5_IPUMUX12(v) (((v) & 0x3) << 12)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR5_IPUMUX1_OFFSET 12
+#define MXC_CCM_CCGR5_IPUMUX1(v) (((v) & 0x3) << 12)
+#endif
+#define MXC_CCM_CCGR5_EMI_FAST_OFFSET 14
+#define MXC_CCM_CCGR5_EMI_FAST(v) (((v) & 0x3) << 14)
+#define MXC_CCM_CCGR5_EMI_SLOW_OFFSET 16
+#define MXC_CCM_CCGR5_EMI_SLOW(v) (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR5_EMI_INT1_OFFSET 18
+#define MXC_CCM_CCGR5_EMI_INT1(v) (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR5_EMI_ENFC_OFFSET 20
+#define MXC_CCM_CCGR5_EMI_ENFC(v) (((v) & 0x3) << 20)
+#define MXC_CCM_CCGR5_EMI_WRCK_OFFSET 22
+#define MXC_CCM_CCGR5_EMI_WRCK(v) (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR5_GPC_IPG_OFFSET 24
+#define MXC_CCM_CCGR5_GPC_IPG(v) (((v) & 0x3) << 24)
+#define MXC_CCM_CCGR5_SPDIF0_OFFSET 26
+#define MXC_CCM_CCGR5_SPDIF0(v) (((v) & 0x3) << 26)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR5_SPDIF1_OFFSET 28
+#define MXC_CCM_CCGR5_SPDIF1(v) (((v) & 0x3) << 28)
+#endif
+#define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET 30
+#define MXC_CCM_CCGR5_SPDIF_IPG(v) (((v) & 0x3) << 30)
+
+#if defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_IPUMUX2_OFFSET 0
+#define MXC_CCM_CCGR6_IPUMUX2(v) (((v) & 0x3) << 0)
+#define MXC_CCM_CCGR6_OCRAM_OFFSET 2
+#define MXC_CCM_CCGR6_OCRAM(v) (((v) & 0x3) << 2)
+#endif
+#define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET 4
+#define MXC_CCM_CCGR6_CSI_MCLK1(v) (((v) & 0x3) << 4)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET 6
+#define MXC_CCM_CCGR6_CSI_MCLK2(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR6_EMI_GARB_OFFSET 8
+#define MXC_CCM_CCGR6_EMI_GARB(v) (((v) & 0x3) << 8)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_EMI_INT2_OFFSET 8
+#define MXC_CCM_CCGR6_EMI_INT2(v) (((v) & 0x3) << 8)
+#endif
+#define MXC_CCM_CCGR6_IPU_DI0_OFFSET 10
+#define MXC_CCM_CCGR6_IPU_DI0(v) (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR6_IPU_DI1_OFFSET 12
+#define MXC_CCM_CCGR6_IPU_DI1(v) (((v) & 0x3) << 12)
+#define MXC_CCM_CCGR6_GPU2D_OFFSET 14
+#define MXC_CCM_CCGR6_GPU2D(v) (((v) & 0x3) << 14)
+#if defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_ESAI_IPG_OFFSET 16
+#define MXC_CCM_CCGR6_ESAI_IPG(v) (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET 18
+#define MXC_CCM_CCGR6_ESAI_ROOT(v) (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR6_CAN1_IPG_OFFSET 20
+#define MXC_CCM_CCGR6_CAN1_IPG(v) (((v) & 0x3) << 20)
+#define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET 22
+#define MXC_CCM_CCGR6_CAN1_SERIAL(v) (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR6_PL301_4X1_OFFSET 24
+#define MXC_CCM_CCGR6_PL301_4X1(v) (((v) & 0x3) << 24)
+#define MXC_CCM_CCGR6_PL301_2X2_OFFSET 26
+#define MXC_CCM_CCGR6_PL301_2X2(v) (((v) & 0x3) << 26)
+#define MXC_CCM_CCGR6_LDB_DI0_OFFSET 28
+#define MXC_CCM_CCGR6_LDB_DI0(v) (((v) & 0x3) << 28)
+#define MXC_CCM_CCGR6_LDB_DI1_OFFSET 30
+#define MXC_CCM_CCGR6_LDB_DI1(v) (((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR7_ASRC_IPG_OFFSET 0
+#define MXC_CCM_CCGR7_ASRC_IPG(v) (((v) & 0x3) << 0)
+#define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET 2
+#define MXC_CCM_CCGR7_ASRC_ASRCK(v) (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR7_MLB_OFFSET 4
+#define MXC_CCM_CCGR7_MLB(v) (((v) & 0x3) << 4)
+#define MXC_CCM_CCGR7_IEEE1588_OFFSET 6
+#define MXC_CCM_CCGR7_IEEE1588(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR7_UART4_IPG_OFFSET 8
+#define MXC_CCM_CCGR7_UART4_IPG(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR7_UART4_PER_OFFSET 10
+#define MXC_CCM_CCGR7_UART4_PER(v) (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR7_UART5_IPG_OFFSET 12
+#define MXC_CCM_CCGR7_UART5_IPG(v) (((v) & 0x3) << 12)
+#define MXC_CCM_CCGR7_UART5_PER_OFFSET 14
+#define MXC_CCM_CCGR7_UART5_PER(v) (((v) & 0x3) << 14)
+#endif
/* Define the bits in register CLPCR */
#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
#define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12)
#define MXC_DPLLC_OP_PDF_MASK 0xf
-#define MXC_DPLLC_OP_MFI_MASK (0xf << 4)
#define MXC_DPLLC_OP_MFI_OFFSET 4
+#define MXC_DPLLC_OP_MFI_MASK (0xf << 4)
+#define MXC_DPLLC_OP_MFI(v) (((v) & 0xf) << 4)
+#define MXC_DPLLC_OP_MFI_RD(r) (((r) >> 4) & 0xf)
#define MXC_DPLLC_MFD_MFD_MASK 0x7ffffff
#define BOARD_REV_1_0 0x0
#define BOARD_REV_2_0 0x1
+#define BOARD_VER_OFFSET 0x8
+
#define IMX_IIM_BASE (IIM_BASE_ADDR)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
+#include <common.h>
+
+#ifdef CONFIG_SYS_MX6_HCLK
+#define MXC_HCLK CONFIG_SYS_MX6_HCLK
+#else
+#define MXC_HCLK 24000000
+#endif
+
+#ifdef CONFIG_SYS_MX6_CLK32
+#define MXC_CLK32 CONFIG_SYS_MX6_CLK32
+#else
+#define MXC_CLK32 32768
+#endif
+
enum mxc_clock {
MXC_ARM_CLK = 0,
MXC_PER_CLK,
MXC_ESDHC4_CLK,
MXC_SATA_CLK,
MXC_NFC_CLK,
+ MXC_I2C_CLK,
};
u32 imx_get_uartclk(void);
u32 cs1cdr;
u32 cs2cdr;
u32 cdcdr; /* 0x0030 */
- u32 chscdr;
+ u32 chsccdr;
u32 cscdr2;
u32 cscdr3;
u32 cscdr4; /* 0x0040 */
#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
+#define CHSCCDR_CLK_SEL_LDB_DI0 3
+#define CHSCCDR_PODF_DIVIDE_BY_3 2
+#define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
+
/* Define the bits in register CSCDR2 */
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
/* Define the bits in registers CCGRx */
#define MXC_CCM_CCGR_CG_MASK 3
-#define MXC_CCM_CCGR0_CG15_OFFSET 30
-#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
-#define MXC_CCM_CCGR0_CG14_OFFSET 28
-#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
-#define MXC_CCM_CCGR0_CG13_OFFSET 26
-#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
-#define MXC_CCM_CCGR0_CG12_OFFSET 24
-#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
-#define MXC_CCM_CCGR0_CG11_OFFSET 22
-#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
-#define MXC_CCM_CCGR0_CG10_OFFSET 20
-#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
-#define MXC_CCM_CCGR0_CG9_OFFSET 18
-#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
-#define MXC_CCM_CCGR0_CG8_OFFSET 16
-#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
-#define MXC_CCM_CCGR0_CG7_OFFSET 14
-#define MXC_CCM_CCGR0_CG6_OFFSET 12
-#define MXC_CCM_CCGR0_CG5_OFFSET 10
-#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
-#define MXC_CCM_CCGR0_CG4_OFFSET 8
-#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
-#define MXC_CCM_CCGR0_CG3_OFFSET 6
-#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
-#define MXC_CCM_CCGR0_CG2_OFFSET 4
-#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
-#define MXC_CCM_CCGR0_CG1_OFFSET 2
-#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
-#define MXC_CCM_CCGR0_CG0_OFFSET 0
-#define MXC_CCM_CCGR0_CG0_MASK 3
-
-#define MXC_CCM_CCGR1_CG15_OFFSET 30
-#define MXC_CCM_CCGR1_CG14_OFFSET 28
-#define MXC_CCM_CCGR1_CG13_OFFSET 26
-#define MXC_CCM_CCGR1_CG12_OFFSET 24
-#define MXC_CCM_CCGR1_CG11_OFFSET 22
-#define MXC_CCM_CCGR1_CG10_OFFSET 20
-#define MXC_CCM_CCGR1_CG9_OFFSET 18
-#define MXC_CCM_CCGR1_CG8_OFFSET 16
-#define MXC_CCM_CCGR1_CG7_OFFSET 14
-#define MXC_CCM_CCGR1_CG6_OFFSET 12
-#define MXC_CCM_CCGR1_CG5_OFFSET 10
-#define MXC_CCM_CCGR1_CG4_OFFSET 8
-#define MXC_CCM_CCGR1_CG3_OFFSET 6
-#define MXC_CCM_CCGR1_CG2_OFFSET 4
-#define MXC_CCM_CCGR1_CG1_OFFSET 2
-#define MXC_CCM_CCGR1_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR2_CG15_OFFSET 30
-#define MXC_CCM_CCGR2_CG14_OFFSET 28
-#define MXC_CCM_CCGR2_CG13_OFFSET 26
-#define MXC_CCM_CCGR2_CG12_OFFSET 24
-#define MXC_CCM_CCGR2_CG11_OFFSET 22
-#define MXC_CCM_CCGR2_CG10_OFFSET 20
-#define MXC_CCM_CCGR2_CG9_OFFSET 18
-#define MXC_CCM_CCGR2_CG8_OFFSET 16
-#define MXC_CCM_CCGR2_CG7_OFFSET 14
-#define MXC_CCM_CCGR2_CG6_OFFSET 12
-#define MXC_CCM_CCGR2_CG5_OFFSET 10
-#define MXC_CCM_CCGR2_CG4_OFFSET 8
-#define MXC_CCM_CCGR2_CG3_OFFSET 6
-#define MXC_CCM_CCGR2_CG2_OFFSET 4
-#define MXC_CCM_CCGR2_CG1_OFFSET 2
-#define MXC_CCM_CCGR2_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR3_CG15_OFFSET 30
-#define MXC_CCM_CCGR3_CG14_OFFSET 28
-#define MXC_CCM_CCGR3_CG13_OFFSET 26
-#define MXC_CCM_CCGR3_CG12_OFFSET 24
-#define MXC_CCM_CCGR3_CG11_OFFSET 22
-#define MXC_CCM_CCGR3_CG10_OFFSET 20
-#define MXC_CCM_CCGR3_CG9_OFFSET 18
-#define MXC_CCM_CCGR3_CG8_OFFSET 16
-#define MXC_CCM_CCGR3_CG7_OFFSET 14
-#define MXC_CCM_CCGR3_CG6_OFFSET 12
-#define MXC_CCM_CCGR3_CG5_OFFSET 10
-#define MXC_CCM_CCGR3_CG4_OFFSET 8
-#define MXC_CCM_CCGR3_CG3_OFFSET 6
-#define MXC_CCM_CCGR3_CG2_OFFSET 4
-#define MXC_CCM_CCGR3_CG1_OFFSET 2
-#define MXC_CCM_CCGR3_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR4_CG15_OFFSET 30
-#define MXC_CCM_CCGR4_CG14_OFFSET 28
-#define MXC_CCM_CCGR4_CG13_OFFSET 26
-#define MXC_CCM_CCGR4_CG12_OFFSET 24
-#define MXC_CCM_CCGR4_CG11_OFFSET 22
-#define MXC_CCM_CCGR4_CG10_OFFSET 20
-#define MXC_CCM_CCGR4_CG9_OFFSET 18
-#define MXC_CCM_CCGR4_CG8_OFFSET 16
-#define MXC_CCM_CCGR4_CG7_OFFSET 14
-#define MXC_CCM_CCGR4_CG6_OFFSET 12
-#define MXC_CCM_CCGR4_CG5_OFFSET 10
-#define MXC_CCM_CCGR4_CG4_OFFSET 8
-#define MXC_CCM_CCGR4_CG3_OFFSET 6
-#define MXC_CCM_CCGR4_CG2_OFFSET 4
-#define MXC_CCM_CCGR4_CG1_OFFSET 2
-#define MXC_CCM_CCGR4_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR5_CG15_OFFSET 30
-#define MXC_CCM_CCGR5_CG14_OFFSET 28
-#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
-#define MXC_CCM_CCGR5_CG13_OFFSET 26
-#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
-#define MXC_CCM_CCGR5_CG12_OFFSET 24
-#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
-#define MXC_CCM_CCGR5_CG11_OFFSET 22
-#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
-#define MXC_CCM_CCGR5_CG10_OFFSET 20
-#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
-#define MXC_CCM_CCGR5_CG9_OFFSET 18
-#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
-#define MXC_CCM_CCGR5_CG8_OFFSET 16
-#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
-#define MXC_CCM_CCGR5_CG7_OFFSET 14
-#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
-#define MXC_CCM_CCGR5_CG6_OFFSET 12
-#define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12)
-#define MXC_CCM_CCGR5_CG5_OFFSET 10
-#define MXC_CCM_CCGR5_CG4_OFFSET 8
-#define MXC_CCM_CCGR5_CG3_OFFSET 6
-#define MXC_CCM_CCGR5_CG2_OFFSET 4
-#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
-#define MXC_CCM_CCGR5_CG1_OFFSET 2
-#define MXC_CCM_CCGR5_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR6_CG15_OFFSET 30
-#define MXC_CCM_CCGR6_CG14_OFFSET 28
-#define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28)
-#define MXC_CCM_CCGR6_CG13_OFFSET 26
-#define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26)
-#define MXC_CCM_CCGR6_CG12_OFFSET 24
-#define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24)
-#define MXC_CCM_CCGR6_CG11_OFFSET 22
-#define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22)
-#define MXC_CCM_CCGR6_CG10_OFFSET 20
-#define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20)
-#define MXC_CCM_CCGR6_CG9_OFFSET 18
-#define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18)
-#define MXC_CCM_CCGR6_CG8_OFFSET 16
-#define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16)
-#define MXC_CCM_CCGR6_CG7_OFFSET 14
-#define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14)
-#define MXC_CCM_CCGR6_CG6_OFFSET 12
-#define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12)
-#define MXC_CCM_CCGR6_CG5_OFFSET 10
-#define MXC_CCM_CCGR6_CG4_OFFSET 8
-#define MXC_CCM_CCGR6_CG3_OFFSET 6
-#define MXC_CCM_CCGR6_CG2_OFFSET 4
-#define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4)
-#define MXC_CCM_CCGR6_CG1_OFFSET 2
-#define MXC_CCM_CCGR6_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR7_CG15_OFFSET 30
-#define MXC_CCM_CCGR7_CG14_OFFSET 28
-#define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28)
-#define MXC_CCM_CCGR7_CG13_OFFSET 26
-#define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26)
-#define MXC_CCM_CCGR7_CG12_OFFSET 24
-#define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24)
-#define MXC_CCM_CCGR7_CG11_OFFSET 22
-#define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22)
-#define MXC_CCM_CCGR7_CG10_OFFSET 20
-#define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20)
-#define MXC_CCM_CCGR7_CG9_OFFSET 18
-#define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18)
-#define MXC_CCM_CCGR7_CG8_OFFSET 16
-#define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16)
-#define MXC_CCM_CCGR7_CG7_OFFSET 14
-#define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14)
-#define MXC_CCM_CCGR7_CG6_OFFSET 12
-#define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12)
-#define MXC_CCM_CCGR7_CG5_OFFSET 10
-#define MXC_CCM_CCGR7_CG4_OFFSET 8
-#define MXC_CCM_CCGR7_CG3_OFFSET 6
-#define MXC_CCM_CCGR7_CG2_OFFSET 4
-#define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4)
-#define MXC_CCM_CCGR7_CG1_OFFSET 2
-#define MXC_CCM_CCGR7_CG0_OFFSET 0
+#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
+#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
+#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
+#define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
+#define MXC_CCM_CCGR0_APBHDMA HCLK_OFFSET 4
+#define MXC_CCM_CCGR0_AMASK (3<<MXC_CCM_CCGR0_APBHDMA)
+#define MXC_CCM_CCGR0_ASRC_OFFSET 6
+#define MXC_CCM_CCGR0_ASRC_MASK (3<<MXC_CCM_CCGR0_ASRC_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3<<MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_OFFSET 14
+#define MXC_CCM_CCGR0_CAN1_MASK (3<<MXC_CCM_CCGR0_CAN1_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
+#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_OFFSET 18
+#define MXC_CCM_CCGR0_CAN2_MASK (3<<MXC_CCM_CCGR0_CAN2_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
+#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3<<MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
+#define MXC_CCM_CCGR0_DCIC1_OFFSET 24
+#define MXC_CCM_CCGR0_DCIC1_MASK (3<<MXC_CCM_CCGR0_DCIC1_OFFSET)
+#define MXC_CCM_CCGR0_DCIC2_OFFSET 26
+#define MXC_CCM_CCGR0_DCIC2_MASK (3<<MXC_CCM_CCGR0_DCIC2_OFFSET)
+#define MXC_CCM_CCGR0_DTCP_OFFSET 28
+#define MXC_CCM_CCGR0_DTCP_MASK (3<<MXC_CCM_CCGR0_DTCP_OFFSET)
+
+#define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
+#define MXC_CCM_CCGR1_ECSPI1S_MASK (3<<MXC_CCM_CCGR1_ECSPI1S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
+#define MXC_CCM_CCGR1_ECSPI2S_MASK (3<<MXC_CCM_CCGR1_ECSPI2S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
+#define MXC_CCM_CCGR1_ECSPI3S_MASK (3<<MXC_CCM_CCGR1_ECSPI3S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
+#define MXC_CCM_CCGR1_ECSPI4S_MASK (3<<MXC_CCM_CCGR1_ECSPI4S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
+#define MXC_CCM_CCGR1_ECSPI5S_MASK (3<<MXC_CCM_CCGR1_ECSPI5S_OFFSET)
+#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
+#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3<<MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
+#define MXC_CCM_CCGR1_EPIT1S_MASK (3<<MXC_CCM_CCGR1_EPIT1S_OFFSET)
+#define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
+#define MXC_CCM_CCGR1_EPIT2S_MASK (3<<MXC_CCM_CCGR1_EPIT2S_OFFSET)
+#define MXC_CCM_CCGR1_ESAIS_OFFSET 16
+#define MXC_CCM_CCGR1_ESAIS_MASK (3<<MXC_CCM_CCGR1_ESAIS_OFFSET)
+#define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
+#define MXC_CCM_CCGR1_GPT_BUS_MASK (3<<MXC_CCM_CCGR1_GPT_BUS_OFFSET)
+#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
+#define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3<<MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
+#define MXC_CCM_CCGR1_GPU2D_OFFSET 24
+#define MXC_CCM_CCGR1_GPU2D_MASK (3<<MXC_CCM_CCGR1_GPU2D_OFFSET)
+#define MXC_CCM_CCGR1_GPU3D_OFFSET 26
+#define MXC_CCM_CCGR1_GPU3D_MASK (3<<MXC_CCM_CCGR1_GPU3D_OFFSET)
+
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
+#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
+#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
+#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
+#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
+#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3<<MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3<<MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
+#define MXC_CCM_CCGR2_IPMUX1_MASK (3<<MXC_CCM_CCGR2_IPMUX1_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
+#define MXC_CCM_CCGR2_IPMUX2_MASK (3<<MXC_CCM_CCGR2_IPMUX2_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
+#define MXC_CCM_CCGR2_IPMUX3_MASK (3<<MXC_CCM_CCGR2_IPMUX3_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3<<MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
+
+#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
+#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
+#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
+#define MXC_CCM_CCGR3_LDB_DI0_MASK (3<<MXC_CCM_CCGR3_LDB_DI0_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
+#define MXC_CCM_CCGR3_LDB_DI1_MASK (3<<MXC_CCM_CCGR3_LDB_DI1_OFFSET)
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3<<MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
+#define MXC_CCM_CCGR3_MLB_OFFSET 18
+#define MXC_CCM_CCGR3_MLB_MASK (3<<MXC_CCM_CCGR3_MLB_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
+#define MXC_CCM_CCGR3_OCRAM_OFFSET 28
+#define MXC_CCM_CCGR3_OCRAM_MASK (3<<MXC_CCM_CCGR3_OCRAM_OFFSET)
+#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
+#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3<<MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
+
+#define MXC_CCM_CCGR4_PCIE_OFFSET 0
+#define MXC_CCM_CCGR4_PCIE_MASK (3<<MXC_CCM_CCGR4_PCIE_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR4_PWM1_OFFSET 16
+#define MXC_CCM_CCGR4_PWM1_MASK (3<<MXC_CCM_CCGR4_PWM1_OFFSET)
+#define MXC_CCM_CCGR4_PWM2_OFFSET 18
+#define MXC_CCM_CCGR4_PWM2_MASK (3<<MXC_CCM_CCGR4_PWM2_OFFSET)
+#define MXC_CCM_CCGR4_PWM3_OFFSET 20
+#define MXC_CCM_CCGR4_PWM3_MASK (3<<MXC_CCM_CCGR4_PWM3_OFFSET)
+#define MXC_CCM_CCGR4_PWM4_OFFSET 22
+#define MXC_CCM_CCGR4_PWM4_MASK (3<<MXC_CCM_CCGR4_PWM4_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
+
+#define MXC_CCM_CCGR5_ROM_OFFSET 0
+#define MXC_CCM_CCGR5_ROM_MASK (3<<MXC_CCM_CCGR5_ROM_OFFSET)
+#define MXC_CCM_CCGR5_SATA_OFFSET 4
+#define MXC_CCM_CCGR5_SATA_MASK (3<<MXC_CCM_CCGR5_SATA_OFFSET)
+#define MXC_CCM_CCGR5_SDMA_OFFSET 6
+#define MXC_CCM_CCGR5_SDMA_MASK (3<<MXC_CCM_CCGR5_SDMA_OFFSET)
+#define MXC_CCM_CCGR5_SPBA_OFFSET 12
+#define MXC_CCM_CCGR5_SPBA_MASK (3<<MXC_CCM_CCGR5_SPBA_OFFSET)
+#define MXC_CCM_CCGR5_SPDIF_OFFSET 14
+#define MXC_CCM_CCGR5_SPDIF_MASK (3<<MXC_CCM_CCGR5_SPDIF_OFFSET)
+#define MXC_CCM_CCGR5_SSI1_OFFSET 18
+#define MXC_CCM_CCGR5_SSI1_MASK (3<<MXC_CCM_CCGR5_SSI1_OFFSET)
+#define MXC_CCM_CCGR5_SSI2_OFFSET 20
+#define MXC_CCM_CCGR5_SSI2_MASK (3<<MXC_CCM_CCGR5_SSI2_OFFSET)
+#define MXC_CCM_CCGR5_SSI3_OFFSET 22
+#define MXC_CCM_CCGR5_SSI3_MASK (3<<MXC_CCM_CCGR5_SSI3_OFFSET)
+#define MXC_CCM_CCGR5_UART_OFFSET 24
+#define MXC_CCM_CCGR5_UART_MASK (3<<MXC_CCM_CCGR5_UART_OFFSET)
+#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
+#define MXC_CCM_CCGR5_UART_SERIAL_MASK (3<<MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
+
+#define MXC_CCM_CCGR6_USBOH3_OFFSET 0
+#define MXC_CCM_CCGR6_USBOH3_MASK (3<<MXC_CCM_CCGR6_USBOH3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC1_OFFSET 2
+#define MXC_CCM_CCGR6_USDHC1_MASK (3<<MXC_CCM_CCGR6_USDHC1_OFFSET)
+#define MXC_CCM_CCGR6_USDHC2_OFFSET 4
+#define MXC_CCM_CCGR6_USDHC2_MASK (3<<MXC_CCM_CCGR6_USDHC2_OFFSET)
+#define MXC_CCM_CCGR6_USDHC3_OFFSET 6
+#define MXC_CCM_CCGR6_USDHC3_MASK (3<<MXC_CCM_CCGR6_USDHC3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC4_OFFSET 8
+#define MXC_CCM_CCGR6_USDHC4_MASK (3<<MXC_CCM_CCGR6_USDHC4_OFFSET)
+#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
+#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3<<MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
+#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3<<MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+
#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
#define BP_ANADIG_PLL_SYS_RSVD0 20
#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
u32 gpr10;
};
+/* GPR3 bitfields */
+#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
+#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
+#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28
+#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27
+#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
+#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
+#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21
+#define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
+#define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17
+#define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
+#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16
+#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15
+#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14
+#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13
+#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12
+#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
+#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11
+#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
+#define IOMUXC_GPR3_IPU_DIAG_OFFSET 10
+#define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
+
+#define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0
+#define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1
+#define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2
+#define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3
+
+#define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8
+#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6
+#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4
+#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
+#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
+
+
+struct iomuxc {
+ u32 gpr[14];
+ u32 omux[5];
+ /* mux and pad registers */
+};
+
+#define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
+#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
+#define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16
+#define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
+
+#define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15
+#define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0
+#define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1
+
+#define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10
+#define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+
+#define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9
+#define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+
+#define IOMUXC_GPR2_BITMAP_SPWG 0
+#define IOMUXC_GPR2_BITMAP_JEIDA 1
+
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+
+#define IOMUXC_GPR2_DATA_WIDTH_18 0
+#define IOMUXC_GPR2_DATA_WIDTH_24 1
+
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+
+#define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4
+#define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
+
+#define IOMUXC_GPR2_MODE_DISABLED 0
+#define IOMUXC_GPR2_MODE_ENABLED_DI0 1
+#define IOMUXC_GPR2_MODE_ENABLED_DI1 2
+
+#define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2
+#define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+
+#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
+#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+
/* ECSPI registers */
struct cspi_regs {
u32 rxdata;
u32 digprog; /* 0x260 */
};
+#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
+#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
+#define ANATOP_PFD_480_PFD0_STABLE_MASK (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
+#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
+#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
+#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
+#define ANATOP_PFD_480_PFD1_STABLE_MASK (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
+#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
+#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
+#define ANATOP_PFD_480_PFD2_FRAC_MASK (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
+#define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
+#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
+#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
+#define ANATOP_PFD_480_PFD3_FRAC_MASK (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
+#define ANATOP_PFD_480_PFD3_STABLE_MASK (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
+
struct iomuxc_base_regs {
u32 gpr[14]; /* 0x000 */
u32 obsrv[5]; /* 0x038 */
u32 daisy[104]; /* 0x7b0..94c */
};
-struct src_regs {
- u32 scr; /* 0x00 */
- u32 sbmr1; /* 0x04 */
- u32 srsr; /* 0x08 */
- u32 reserved1; /* 0x0c */
- u32 reserved2; /* 0x10 */
- u32 sisr; /* 0x14 */
- u32 simr; /* 0x18 */
- u32 sbmr2; /* 0x1c */
- u32 gpr1; /* 0x20 */
- u32 gpr2; /* 0x24 */
- u32 gpr3; /* 0x28 */
- u32 gpr4; /* 0x2c */
- u32 gpr5; /* 0x30 */
- u32 gpr6; /* 0x34 */
- u32 gpr7; /* 0x38 */
- u32 gpr8; /* 0x3c */
- u32 gpr9; /* 0x40 */
- u32 gpr10; /* 0x44 */
-};
-
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
/*
* functions
*/
-void reset_cpu(unsigned long ignored);
u32 orion5x_device_id(void);
u32 orion5x_device_rev(void);
unsigned int orion5x_winctrl_calcsize(unsigned int sizeval);
#ifndef __PXA_H__
#define __PXA_H__
+#define PXA255_A0 0x00000106
+#define PXA250_C0 0x00000105
+#define PXA250_B2 0x00000104
+#define PXA250_B1 0x00000103
+#define PXA250_B0 0x00000102
+#define PXA250_A1 0x00000101
+#define PXA250_A0 0x00000100
+#define PXA210_C0 0x00000125
+#define PXA210_B2 0x00000124
+#define PXA210_B1 0x00000123
+#define PXA210_B0 0x00000122
+
int cpu_is_pxa25x(void);
int cpu_is_pxa27x(void);
+uint32_t pxa_get_cpu_revision(void);
void pxa2xx_dram_init(void);
#endif /* __PXA_H__ */
--- /dev/null
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#if defined(CONFIG_SH73A0)
+#include "sh73a0-gpio.h"
+void sh73a0_pinmux_init(void);
+#elif defined(CONFIG_R8A7740)
+#include "r8a7740-gpio.h"
+void r8a7740_pinmux_init(void);
+#endif
+
+#endif /* __ASM_ARCH_GPIO_H */
--- /dev/null
+#ifndef __ASM_MACH_IRQS_H
+#define __ASM_MACH_IRQS_H
+
+#define NR_IRQS 1024
+
+/* GIC */
+#define gic_spi(nr) ((nr) + 32)
+
+/* INTCA */
+#define evt2irq(evt) (((evt) >> 5) - 16)
+#define irq2evt(irq) (((irq) + 16) << 5)
+
+/* INTCS */
+#define INTCS_VECT_BASE 0x2200
+#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect))
+#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt))
+
+#endif /* __ASM_MACH_IRQS_H */
--- /dev/null
+/*
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __ASM_R8A7740_H__
+#define __ASM_R8A7740_H__
+
+/*
+ * MD_CKx pin
+ */
+#define MD_CK2 (1 << 2)
+#define MD_CK1 (1 << 1)
+#define MD_CK0 (1 << 0)
+
+/*
+ * Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+ /* PORT */
+ GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
+ GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
+
+ GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
+ GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
+
+ GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
+ GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
+
+ GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
+ GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
+
+ GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
+ GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
+
+ GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
+ GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
+
+ GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
+ GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
+
+ GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
+ GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
+
+ GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
+ GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
+
+ GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
+ GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
+
+ GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
+ GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
+
+ GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
+ GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
+
+ GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
+ GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
+
+ GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
+ GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
+
+ GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
+ GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
+
+ GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
+ GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
+
+ GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
+ GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
+
+ GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
+ GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
+
+ GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
+ GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
+
+ GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
+ GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
+
+ GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
+ GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
+
+ GPIO_PORT210, GPIO_PORT211,
+
+ /* IRQ */
+ GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13,
+ GPIO_FN_IRQ1,
+ GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12,
+ GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14,
+ GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172,
+ GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1,
+ GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173,
+ GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209,
+ GPIO_FN_IRQ8,
+ GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210,
+ GPIO_FN_IRQ10,
+ GPIO_FN_IRQ11,
+ GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97,
+ GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98,
+ GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99,
+ GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100,
+ GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211,
+ GPIO_FN_IRQ17,
+ GPIO_FN_IRQ18,
+ GPIO_FN_IRQ19,
+ GPIO_FN_IRQ20,
+ GPIO_FN_IRQ21,
+ GPIO_FN_IRQ22,
+ GPIO_FN_IRQ23,
+ GPIO_FN_IRQ24,
+ GPIO_FN_IRQ25,
+ GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81,
+ GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168,
+ GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169,
+ GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170,
+ GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171,
+ GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167,
+
+ /* Function */
+
+ /* DBGT */
+ GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0,
+ GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20,
+ GPIO_FN_DBGMD21,
+
+ /* FSI */
+ GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */
+ GPIO_FN_FSIAISLD_PORT5,
+ GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */
+ GPIO_FN_FSIASPDIF_PORT18,
+ GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2,
+ GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT,
+ GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC,
+ GPIO_FN_FSIACK, GPIO_FN_FSIAILR,
+ GPIO_FN_FSIAIBT,
+
+ /* FMSI */
+ GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
+ GPIO_FN_FMSISLD_PORT6,
+ GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT,
+ GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT,
+ GPIO_FN_FMSICK, GPIO_FN_FMSOILR,
+ GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR,
+ GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD,
+ GPIO_FN_FMSOCK,
+
+ /* SCIFA0 */
+ GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS,
+ GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD,
+ GPIO_FN_SCIFA0_TXD,
+
+ /* SCIFA1 */
+ GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK,
+ GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD,
+ GPIO_FN_SCIFA1_RTS,
+
+ /* SCIFA2 */
+ GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
+ GPIO_FN_SCIFA2_SCK_PORT199,
+ GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD,
+ GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS,
+
+ /* SCIFA3 */
+ GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
+ GPIO_FN_SCIFA3_SCK_PORT116,
+ GPIO_FN_SCIFA3_CTS_PORT117,
+ GPIO_FN_SCIFA3_RXD_PORT174,
+ GPIO_FN_SCIFA3_TXD_PORT175,
+
+ GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
+ GPIO_FN_SCIFA3_SCK_PORT158,
+ GPIO_FN_SCIFA3_CTS_PORT162,
+ GPIO_FN_SCIFA3_RXD_PORT159,
+ GPIO_FN_SCIFA3_TXD_PORT160,
+
+ /* SCIFA4 */
+ GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
+ GPIO_FN_SCIFA4_TXD_PORT13,
+
+ GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
+ GPIO_FN_SCIFA4_TXD_PORT203,
+
+ GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
+ GPIO_FN_SCIFA4_TXD_PORT93,
+
+ GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
+ GPIO_FN_SCIFA4_SCK_PORT205,
+
+ /* SCIFA5 */
+ GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
+ GPIO_FN_SCIFA5_RXD_PORT10,
+
+ GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
+ GPIO_FN_SCIFA5_TXD_PORT208,
+
+ GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
+ GPIO_FN_SCIFA5_RXD_PORT92,
+
+ GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
+ GPIO_FN_SCIFA5_SCK_PORT206,
+
+ /* SCIFA6 */
+ GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD,
+
+ /* SCIFA7 */
+ GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD,
+
+ /* SCIFAB */
+ GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
+ GPIO_FN_SCIFB_RXD_PORT191,
+ GPIO_FN_SCIFB_TXD_PORT192,
+ GPIO_FN_SCIFB_RTS_PORT186,
+ GPIO_FN_SCIFB_CTS_PORT187,
+
+ GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
+ GPIO_FN_SCIFB_RXD_PORT3,
+ GPIO_FN_SCIFB_TXD_PORT4,
+ GPIO_FN_SCIFB_RTS_PORT172,
+ GPIO_FN_SCIFB_CTS_PORT173,
+
+ /* LCD0 */
+ GPIO_FN_LCDC0_SELECT,
+ GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2,
+ GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5,
+ GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8,
+ GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11,
+ GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14,
+ GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17,
+ GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC,
+
+ GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */
+ GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */
+
+ GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */
+ GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */
+
+ GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162,
+ GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158,
+ GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159,
+ GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */
+
+ GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4,
+ GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2,
+ GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1,
+ GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */
+
+ /* LCD1 */
+ GPIO_FN_LCDC1_SELECT,
+ GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2,
+ GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5,
+ GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8,
+ GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11,
+ GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14,
+ GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17,
+ GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20,
+ GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23,
+ GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC,
+ GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC,
+
+ GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */
+ GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */
+
+ GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */
+ GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */
+
+ /* RSPI */
+ GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A,
+ GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A,
+ GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A,
+ GPIO_FN_RSPI_CK_A,
+
+ /* VIO CKO */
+ GPIO_FN_VIO_CKO1,
+ GPIO_FN_VIO_CKO2,
+ GPIO_FN_VIO_CKO_1,
+ GPIO_FN_VIO_CKO,
+
+ /* VIO0 */
+ GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2,
+ GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5,
+ GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8,
+ GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11,
+ GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD,
+ GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD,
+
+ GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
+ GPIO_FN_VIO0_D14_PORT25,
+ GPIO_FN_VIO0_D15_PORT24,
+
+ GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
+ GPIO_FN_VIO0_D14_PORT95,
+ GPIO_FN_VIO0_D15_PORT96,
+
+ /* VIO1 */
+ GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2,
+ GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5,
+ GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD,
+ GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD,
+
+ /* TPU0 */
+ GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1,
+ GPIO_FN_TPU0TO3,
+ GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
+ GPIO_FN_TPU0TO2_PORT202,
+
+ /* SSP1 0 */
+ GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2,
+ GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5,
+ GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN,
+ GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC,
+
+ /* SSP1 1 */
+ GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3,
+ GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6,
+ GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC,
+
+ GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
+ GPIO_FN_STP1_IPEN_PORT187,
+
+ GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
+ GPIO_FN_STP1_IPEN_PORT193,
+
+ /* SIM */
+ GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK,
+ GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */
+ GPIO_FN_SIM_D_PORT199,
+
+ /* SDHI0 */
+ GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2,
+ GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP,
+ GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK,
+
+ /* SDHI1 */
+ GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2,
+ GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP,
+ GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK,
+
+ /* SDHI2 */
+ GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2,
+ GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD,
+
+ GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
+ GPIO_FN_SDHI2_WP_PORT25,
+
+ GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
+ GPIO_FN_SDHI2_CD_PORT202,
+
+ /* MSIOF2 */
+ GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK,
+ GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1,
+ GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC,
+ GPIO_FN_MSIOF2_RSCK,
+
+ /* KEYSC */
+ GPIO_FN_KEYIN4, GPIO_FN_KEYIN5,
+ GPIO_FN_KEYIN6, GPIO_FN_KEYIN7,
+ GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2,
+ GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5,
+ GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7,
+
+ GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
+ GPIO_FN_KEYIN1_PORT44,
+ GPIO_FN_KEYIN2_PORT45,
+ GPIO_FN_KEYIN3_PORT46,
+
+ GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
+ GPIO_FN_KEYIN1_PORT57,
+ GPIO_FN_KEYIN2_PORT56,
+ GPIO_FN_KEYIN3_PORT55,
+
+ /* VOU */
+ GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3,
+ GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7,
+ GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11,
+ GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15,
+ GPIO_FN_DV_CLK,
+ GPIO_FN_DV_VSYNC,
+ GPIO_FN_DV_HSYNC,
+
+ /* MEMC */
+ GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2,
+ GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5,
+ GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8,
+ GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11,
+ GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14,
+ GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT,
+ GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE,
+
+ GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
+ GPIO_FN_MEMC_ADV,
+ GPIO_FN_MEMC_WAIT,
+ GPIO_FN_MEMC_BUSCLK,
+
+ GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
+ GPIO_FN_MEMC_DREQ0,
+ GPIO_FN_MEMC_DREQ1,
+ GPIO_FN_MEMC_A0,
+
+ /* MMC */
+ GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69,
+ GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71,
+ GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73,
+ GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75,
+ GPIO_FN_MMC0_CLK_PORT66,
+ GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */
+
+ GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148,
+ GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146,
+ GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144,
+ GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142,
+ GPIO_FN_MMC1_CLK_PORT103,
+ GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */
+
+ /* MSIOF0 */
+ GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
+ GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
+ GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1,
+ GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK,
+ GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC,
+
+ /* MSIOF1 */
+ GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC,
+ GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1,
+
+ GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117,
+ GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119,
+ GPIO_FN_MSIOF1_TSYNC_PORT120,
+ GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */
+
+ GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72,
+ GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74,
+ GPIO_FN_MSIOF1_RXD_PORT75,
+ GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */
+
+ /* GPIO */
+ GPIO_FN_GPO0, GPIO_FN_GPI0,
+ GPIO_FN_GPO1, GPIO_FN_GPI1,
+
+ /* USB0 */
+ GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS,
+
+ /* USB1 */
+ GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON,
+
+ /* BBIF1 */
+ GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC,
+ GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC,
+ GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N,
+
+ /* BBIF2 */
+ GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
+ GPIO_FN_BBIF2_RXD2_PORT60,
+ GPIO_FN_BBIF2_TSYNC2_PORT6,
+ GPIO_FN_BBIF2_TSCK2_PORT59,
+
+ GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
+ GPIO_FN_BBIF2_TXD2_PORT183,
+ GPIO_FN_BBIF2_TSCK2_PORT89,
+ GPIO_FN_BBIF2_TSYNC2_PORT184,
+
+ /* BSC / FLCTL / PCMCIA */
+ GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4,
+ GPIO_FN_CS5B, GPIO_FN_CS6A,
+ GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
+ GPIO_FN_CS5A_PORT19,
+ GPIO_FN_IOIS16, /* ? */
+
+ GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3,
+ GPIO_FN_A4_FOE, /* share with FLCTL */
+ GPIO_FN_A5_FCDE, /* share with FLCTL */
+ GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9,
+ GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13,
+ GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17,
+ GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21,
+ GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25,
+ GPIO_FN_A26,
+
+ GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */
+ GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */
+ GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */
+ GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */
+ GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */
+ GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */
+ GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */
+ GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */
+
+ GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19,
+ GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23,
+ GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27,
+ GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31,
+
+ GPIO_FN_WE0_FWE, /* share with FLCTL */
+ GPIO_FN_WE1,
+ GPIO_FN_WE2_ICIORD, /* share with PCMCIA */
+ GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */
+ GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR,
+ GPIO_FN_RD_FSC, /* share with FLCTL */
+ GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */
+ GPIO_FN_WAIT_PORT90,
+
+ GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */
+
+ /* IRDA */
+ GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT,
+
+ /* ATAPI */
+ GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2,
+ GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5,
+ GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8,
+ GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11,
+ GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14,
+ GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1,
+ GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1,
+ GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY,
+ GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION,
+ GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ,
+
+ /* RMII */
+ GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0,
+ GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0,
+ GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO,
+ GPIO_FN_RMII_REF50CK, /* for RMII */
+ GPIO_FN_RMII_REF125CK, /* for GMII */
+
+ /* GEther */
+ GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0,
+ GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3,
+ GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */
+ GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */
+ GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER,
+ GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV,
+ GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1,
+ GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3,
+ GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */
+ GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */
+ GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS,
+ GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO,
+ GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT,
+ GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK,
+
+ /* DMA0 */
+ GPIO_FN_DREQ0, GPIO_FN_DACK0,
+
+ /* DMA1 */
+ GPIO_FN_DREQ1, GPIO_FN_DACK1,
+
+ /* SYSC */
+ GPIO_FN_RESETOUTS,
+ GPIO_FN_RESETP_PULLUP,
+ GPIO_FN_RESETP_PLAIN,
+
+ /* SDENC */
+ GPIO_FN_SDENC_CPG,
+ GPIO_FN_SDENC_DV_CLKI,
+
+ /* IRREM */
+ GPIO_FN_IROUT,
+
+ /* DEBUG */
+ GPIO_FN_EDEBGREQ_PULLDOWN,
+ GPIO_FN_EDEBGREQ_PULLUP,
+
+ GPIO_FN_TRACEAUD_FROM_VIO,
+ GPIO_FN_TRACEAUD_FROM_LCDC0,
+ GPIO_FN_TRACEAUD_FROM_MEMC,
+};
+
+#endif /* __ASM_R8A7740_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_R8A7740_H
+#define __ASM_ARCH_R8A7740_H
+
+/*
+ * R8A7740 I/O Addresses
+ */
+
+#define MERAM_BASE 0xE5580000
+#define DDRP_BASE 0xC12A0000
+#define HPB_BASE 0xE6000000
+#define RWDT0_BASE 0xE6020000
+#define RWDT1_BASE 0xE6030000
+#define GPIO_BASE 0xE6050000
+#define CMT1_BASE 0xE6138000
+#define CPG_BASE 0xE6150000
+#define SYSC_BASE 0xE6180000
+#define SDHI0_BASE 0xE6850000
+#define SDHI1_BASE 0xE6860000
+#define MMCIF_BASE 0xE6BD0000
+#define SCIF5_BASE 0xE6CB0000
+#define SCIF6_BASE 0xE6CC0000
+#define DBSC_BASE 0xFE400000
+#define BSC_BASE 0xFEC10000
+#define I2C0_BASE 0xFFF20000
+#define I2C1_BASE 0xE6C20000
+#define TMU_BASE 0xFFF80000
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* RWDT */
+struct r8a7740_rwdt {
+ u16 rwtcnt0; /* 0x00 */
+ u16 dummy0; /* 0x02 */
+ u16 rwtcsra0; /* 0x04 */
+ u16 dummy1; /* 0x06 */
+ u16 rwtcsrb0; /* 0x08 */
+ u16 dummy2; /* 0x0A */
+};
+
+/* HPB Semaphore Control Registers */
+struct r8a7740_hpb {
+ u32 hpbctrl0;
+ u32 hpbctrl1;
+ u32 hpbctrl2;
+ u32 cccr;
+ u32 dummy0; /* 0x20 */
+ u32 hpbctrl4;
+ u32 hpbctrl5;
+};
+
+/* CPG */
+struct r8a7740_cpg {
+ u32 frqcra;
+ u32 frqcrb;
+ u32 vclkcr1;
+ u32 vclkcr2;
+ u32 fmsickcr;
+ u32 fmsockcr;
+ u32 fsiackcr;
+ u32 dummy0; /* 0x1c */
+ u32 rtstbcr;
+ u32 systbcr;
+ u32 pllc01cr;
+ u32 pllc2cr;
+ u32 mstpsr0;
+ u32 dummy1; /* 0x34 */
+ u32 mstpsr1;
+ u32 mstpsr5;
+ u32 mstpsr2;
+ u32 dummy2; /* 0x44 */
+ u32 mstpsr3;
+ u32 mstpsr4;
+ u32 dummy3; /* 0x50 */
+ u32 astat;
+ u32 dummy4[4]; /* 0x58 .. 0x64 */
+ u32 ztrckcr;
+ u32 dummy5[5]; /* 0x6c .. 0x7c */
+ u32 subckcr;
+ u32 spuckcr;
+ u32 vouckcr;
+ u32 usbckcr;
+ u32 dummy6[3]; /* 0x90 .. 0x98 */
+ u32 stprckcr;
+ u32 srcr0;
+ u32 dummy7; /* 0xa4 */
+ u32 srcr1;
+ u32 dummy8; /* 0xac */
+ u32 srcr2;
+ u32 dummy9; /* 0xb4 */
+ u32 srcr3;
+ u32 srcr4;
+ u32 dummy10; /* 0xc0 */
+ u32 srcr5;
+ u32 pllc01stpcr;
+ u32 dummy11[5]; /* 0xcc .. 0xdc */
+ u32 frqcrc;
+ u32 frqcrd;
+ u32 dummy12[10]; /* 0xe8 .. 0x10c */
+ u32 rmstpcr0;
+ u32 rmstpcr1;
+ u32 rmstpcr2;
+ u32 rmstpcr3;
+ u32 rmstpcr4;
+ u32 rmstpcr5;
+ u32 dummy13[2]; /* 0x128 .. 0x12c */
+ u32 smstpcr0;
+ u32 smstpcr1;
+ u32 smstpcr2;
+ u32 smstpcr3;
+ u32 smstpcr4;
+ u32 smstpcr5;
+};
+
+/* BSC */
+struct r8a7740_bsc {
+ u32 cmncr;
+ u32 cs0bcr;
+ u32 cs2bcr;
+ u32 dummy0; /* 0x0c */
+ u32 cs4bcr;
+ u32 cs5abcr;
+ u32 cs5bbcr;
+ u32 cs6abcr;
+ u32 dummy1; /* 0x20 */
+ u32 cs0wcr;
+ u32 cs2wcr;
+ u32 dummy2; /* 0x2c */
+ u32 cs4wcr;
+ u32 cs5awcr;
+ u32 cs5bwcr;
+ u32 cs6awcr;
+ u32 dummy3[5]; /* 0x40 .. 0x50 */
+ u32 rbwtcnt;
+ u32 busycr;
+ u32 dummy4[5]; /* 0x5c .. 0x6c */
+ u32 bromtimcr;
+ u32 dummy5[7]; /* 0x74 .. 0x8c */
+ u32 bptcr00;
+ u32 bptcr01;
+ u32 bptcr02;
+ u32 bptcr03;
+ u32 bptcr04;
+ u32 bptcr05;
+ u32 bptcr06;
+ u32 bptcr07;
+ u32 bptcr08;
+ u32 bptcr09;
+ u32 bptcr10;
+ u32 bptcr11;
+ u32 bptcr12;
+ u32 bptcr13;
+ u32 bptcr14;
+ u32 bptcr15;
+ u32 bptcr16;
+ u32 bptcr17;
+ u32 bptcr18;
+ u32 bptcr19;
+ u32 bptcr20;
+ u32 bptcr21;
+ u32 bptcr22;
+ u32 bptcr23;
+ u32 bptcr24;
+ u32 bptcr25;
+ u32 bptcr26;
+ u32 bptcr27;
+ u32 bptcr28;
+ u32 bptcr29;
+ u32 bptcr30;
+ u32 bptcr31;
+ u32 bswcr;
+ u32 dummy6[68]; /* 0x114 .. 0x220 */
+ u32 cs0wcr2;
+ u32 cs2wcr2;
+ u32 dummy7; /* 0x22c */
+ u32 cs4wcr2;
+};
+
+#define CS0WCR2 0xFEC10224
+#define CS2WCR2 0xFEC10228
+#define CS4WCR2 0xFEC10230
+
+/* DDRP */
+struct r8a7740_ddrp {
+ u32 funcctrl;
+ u32 dllctrl;
+ u32 zqcalctrl;
+ u32 zqodtctrl;
+ u32 rdctrl;
+ u32 rdtmg;
+ u32 fifoinit;
+ u32 outctrl;
+ u32 dummy0[50]; /* 0x20 .. 0xe4 */
+ u32 dqcalofs1;
+ u32 dqcalofs2;
+ u32 dummy1[2]; /* 0xf0 .. 0xf4 */
+ u32 dqcalexp;
+};
+
+#define DDRPNCNT 0xE605803C
+#define DDRVREFCNT 0xE61500EC
+
+/* DBSC */
+struct r8a7740_dbsc {
+ u32 dummy0;
+ u32 dbsvcr;
+ u32 dbstate0;
+ u32 dbstate1;
+ u32 dbacen;
+ u32 dbrfen;
+ u32 dbcmd;
+ u32 dbwait;
+ u32 dbkind;
+ u32 dbconf0;
+ u32 dummy1[2]; /* 0x28 .. 0x2c */
+ u32 dbphytype;
+ u32 dummy2[3]; /* 0x34 .. 0x3c */
+ u32 dbtr0;
+ u32 dbtr1;
+ u32 dbtr2;
+ u32 dummy3; /* 0x4c */
+ u32 dbtr3;
+ u32 dbtr4;
+ u32 dbtr5;
+ u32 dbtr6;
+ u32 dbtr7;
+ u32 dbtr8;
+ u32 dbtr9;
+ u32 dbtr10;
+ u32 dbtr11;
+ u32 dbtr12;
+ u32 dbtr13;
+ u32 dbtr14;
+ u32 dbtr15;
+ u32 dbtr16;
+ u32 dbtr17;
+ u32 dbtr18;
+ u32 dbtr19;
+ u32 dummy4[7]; /* 0x94 .. 0xac */
+ u32 dbbl;
+ u32 dummy5[3]; /* 0xb4 .. 0xbc */
+ u32 dbadj0;
+ u32 dbadj1;
+ u32 dbadj2;
+ u32 dummy6[5]; /* 0xcc .. 0xdc */
+ u32 dbrfcnf0;
+ u32 dbrfcnf1;
+ u32 dbrfcnf2;
+ u32 dbrfcnf3;
+ u32 dummy7; /* 0xf0 */
+ u32 dbcalcnf;
+ u32 dbcaltr;
+ u32 dummy8; /* 0xfc */;
+ u32 dbrnk0;
+ u32 dummy9[31]; /* 0x104 .. 0x17C */
+ u32 dbpdncnf;
+ u32 dummy10[7]; /* 0x184 .. 0x19C */
+ u32 dbmrrdr;
+ u32 dummy11[39]; /* 0x1A4 .. 0x23C */
+ u32 dbdfistat;
+ u32 dbdficnt;
+ u32 dummy12[46]; /* 0x248 .. 0x2FC */
+ u32 dbbs0cnt0;
+ u32 dbbs0cnt1;
+};
+
+#endif
+
+#endif /* __ASM_ARCH_R8A7740_H */
--- /dev/null
+#ifndef __ASM_ARCH_RMOBILE_H
+#define __ASM_ARCH_RMOBILE_H
+
+#if defined(CONFIG_RMOBILE)
+#if defined(CONFIG_SH73A0)
+#include <asm/arch/sh73a0.h>
+#elif defined(CONFIG_R8A7740)
+#include <asm/arch/r8a7740.h>
+#else
+#error "SOC Name not defined"
+#endif
+#endif /* CONFIG_RMOBILE */
+
+#endif /* __ASM_ARCH_RMOBILE_H */
--- /dev/null
+#ifndef __ASM_SH73A0_H__
+#define __ASM_SH73A0_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function and MSEL switch
+ * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+ /* Hardware manual Table 25-1 (GPIO) */
+ GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
+ GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
+
+ GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
+ GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
+
+ GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
+ GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
+
+ GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
+ GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
+
+ GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
+ GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
+
+ GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
+ GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
+
+ GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
+ GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
+
+ GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
+ GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
+
+ GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
+ GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
+
+ GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
+ GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
+
+ GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
+ GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
+
+ GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
+ GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118,
+
+ GPIO_PORT128, GPIO_PORT129,
+
+ GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
+ GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
+
+ GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
+ GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
+
+ GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
+ GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
+
+ GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
+
+ GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
+ GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
+
+ GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
+ GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
+
+ GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
+ GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
+
+ GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
+ GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
+
+ GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
+ GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
+
+ GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
+ GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
+
+ GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
+ GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
+
+ GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
+ GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
+
+ GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274,
+ GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279,
+
+ GPIO_PORT280, GPIO_PORT281, GPIO_PORT282,
+
+ GPIO_PORT288, GPIO_PORT289,
+
+ GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294,
+ GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299,
+
+ GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304,
+ GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
+
+ /* Table 25-1 (Function 0-7) */
+ GPIO_FN_VBUS_0,
+ GPIO_FN_GPI0,
+ GPIO_FN_GPI1,
+ GPIO_FN_GPI2,
+ GPIO_FN_GPI3,
+ GPIO_FN_GPI4,
+ GPIO_FN_GPI5,
+ GPIO_FN_GPI6,
+ GPIO_FN_GPI7,
+ GPIO_FN_SCIFA7_RXD,
+ GPIO_FN_SCIFA7_CTS_,
+ GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
+ GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
+ GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \
+ GPIO_FN_PORT16_VIO_CKOR,
+ GPIO_FN_SCIFA0_TXD,
+ GPIO_FN_SCIFA7_TXD,
+ GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2,
+ GPIO_FN_GPO0,
+ GPIO_FN_GPO1,
+ GPIO_FN_GPO2, GPIO_FN_STATUS0,
+ GPIO_FN_GPO3, GPIO_FN_STATUS1,
+ GPIO_FN_GPO4, GPIO_FN_STATUS2,
+ GPIO_FN_VINT,
+ GPIO_FN_TCKON,
+ GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \
+ GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
+ GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \
+ GPIO_FN_PORT28_TPU1TO1,
+ GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
+ GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
+ GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
+ GPIO_FN_SCIFA4_TXD,
+ GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
+ GPIO_FN_SCIFA4_RTS_,
+ GPIO_FN_SCIFA4_CTS_,
+ GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
+ GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
+ GPIO_FN_FSIBOSLD,
+ GPIO_FN_FSIBISLD,
+ GPIO_FN_VACK,
+ GPIO_FN_XTAL1L,
+ GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2,
+ GPIO_FN_SCIFA0_RXD,
+ GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1,
+ GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT,
+ GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR,
+ GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF,
+ GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD,
+ GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \
+ GPIO_FN_FSIAOMC,
+ GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR,
+
+ GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT,
+ GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2,
+ GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \
+ GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF,
+ GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \
+ GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC,
+ GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0,
+ GPIO_FN_A0, GPIO_FN_BS_,
+ GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2,
+ GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1,
+ GPIO_FN_A14, GPIO_FN_KEYOUT5,
+ GPIO_FN_A15, GPIO_FN_KEYOUT4,
+ GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1,
+ GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
+ GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
+ GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD,
+ GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK,
+ GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
+ GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0,
+ GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1,
+ GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD,
+ GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2,
+ GPIO_FN_A26, GPIO_FN_KEYIN6,
+ GPIO_FN_KEYIN7,
+ GPIO_FN_D0_NAF0,
+ GPIO_FN_D1_NAF1,
+ GPIO_FN_D2_NAF2,
+ GPIO_FN_D3_NAF3,
+ GPIO_FN_D4_NAF4,
+ GPIO_FN_D5_NAF5,
+ GPIO_FN_D6_NAF6,
+ GPIO_FN_D7_NAF7,
+ GPIO_FN_D8_NAF8,
+ GPIO_FN_D9_NAF9,
+ GPIO_FN_D10_NAF10,
+ GPIO_FN_D11_NAF11,
+ GPIO_FN_D12_NAF12,
+ GPIO_FN_D13_NAF13,
+ GPIO_FN_D14_NAF14,
+ GPIO_FN_D15_NAF15,
+ GPIO_FN_CS4_,
+ GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR,
+ GPIO_FN_CS5B_, GPIO_FN_FCE1_,
+ GPIO_FN_CS6B_, GPIO_FN_DACK0,
+ GPIO_FN_FCE0_, GPIO_FN_CS6A_,
+ GPIO_FN_WAIT_, GPIO_FN_DREQ0,
+ GPIO_FN_RD__FSC,
+ GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE,
+ GPIO_FN_WE1_,
+ GPIO_FN_FRB,
+ GPIO_FN_CKO,
+ GPIO_FN_NBRSTOUT_,
+ GPIO_FN_NBRST_,
+ GPIO_FN_BBIF2_TXD,
+ GPIO_FN_BBIF2_RXD,
+ GPIO_FN_BBIF2_SYNC,
+ GPIO_FN_BBIF2_SCK,
+ GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2,
+ GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1,
+ GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1,
+ GPIO_FN_SCIFA3_TXD,
+ GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
+ GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
+ GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
+ GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
+ GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \
+ GPIO_FN_PORT115_I2C_SCL3,
+ GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \
+ GPIO_FN_PORT116_I2C_SDA3,
+ GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
+ GPIO_FN_HSI_TX_FLAG,
+ GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \
+ GPIO_FN_LCD2D0,
+
+ GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \
+ GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1,
+ GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10,
+ GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \
+ GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11,
+ GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \
+ GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12,
+ GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13,
+ GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14,
+ GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15,
+ GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16,
+ GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17,
+ GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \
+ GPIO_FN_LCD2D6,
+ GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \
+ GPIO_FN_LCD2D7,
+ GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8,
+ GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9,
+ GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \
+ GPIO_FN_LCD2D2,
+ GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \
+ GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3,
+ GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
+ GPIO_FN_LCD2D4,
+ GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \
+ GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5,
+ GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \
+ GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18,
+ GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19,
+ GPIO_FN_VIO_CKO,
+ GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \
+ GPIO_FN_PORT149_KEYOUT9,
+ GPIO_FN_MFG0_IN2,
+ GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
+ GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
+ GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
+ GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
+ GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
+ GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2,
+ GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD,
+ GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
+ GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
+ GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD,
+ GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_,
+ GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
+ GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
+ GPIO_FN_TPU3TO0,
+ GPIO_FN_LCDD0,
+ GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1,
+ GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1,
+ GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1,
+ GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD,
+ GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \
+ GPIO_FN_TPU2TO1,
+ GPIO_FN_LCDD6,
+ GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
+ GPIO_FN_LCDD8, GPIO_FN_D16,
+ GPIO_FN_LCDD9, GPIO_FN_D17,
+ GPIO_FN_LCDD10, GPIO_FN_D18,
+ GPIO_FN_LCDD11, GPIO_FN_D19,
+ GPIO_FN_LCDD12, GPIO_FN_D20,
+ GPIO_FN_LCDD13, GPIO_FN_D21,
+ GPIO_FN_LCDD14, GPIO_FN_D22,
+ GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
+ GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
+ GPIO_FN_LCDD17, GPIO_FN_D25,
+ GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
+ GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
+ GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
+ GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
+ GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
+ GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
+ GPIO_FN_LCDDCK, GPIO_FN_LCDWR_,
+ GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \
+ GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP,
+ GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \
+ GPIO_FN_PORT218_VIO_CKOR,
+ GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \
+ GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
+ GPIO_FN_LCD2DCK_2,
+ GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2,
+ GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \
+ GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
+ GPIO_FN_PORT221_LCD2HSYN,
+ GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \
+ GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN,
+
+ GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
+ GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2,
+ GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN,
+ GPIO_FN_SCIFA1_RXD,
+ GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1,
+ GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2,
+ GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_,
+ GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2,
+ GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
+ GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
+ GPIO_FN_LCD2D20,
+ GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
+ GPIO_FN_LCD2D21,
+ GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2,
+ GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2,
+ GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22,
+ GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23,
+ GPIO_FN_SCIFA6_TXD,
+ GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
+ GPIO_FN_TPU4TO0,
+ GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
+ GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
+ GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \
+ GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD,
+ GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \
+ GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD,
+ GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \
+ GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
+ GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \
+ GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
+ GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \
+ GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \
+ GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK,
+ GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
+ GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC,
+ GPIO_FN_SDHICLK0,
+ GPIO_FN_SDHICD0,
+ GPIO_FN_SDHID0_0,
+ GPIO_FN_SDHID0_1,
+ GPIO_FN_SDHID0_2,
+ GPIO_FN_SDHID0_3,
+ GPIO_FN_SDHICMD0,
+ GPIO_FN_SDHIWP0,
+ GPIO_FN_SDHICLK1,
+ GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2,
+ GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2,
+ GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2,
+ GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2,
+ GPIO_FN_SDHICMD1,
+ GPIO_FN_SDHICLK2,
+ GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4,
+ GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4,
+ GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4,
+ GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4,
+ GPIO_FN_SDHICMD2,
+ GPIO_FN_MMCCLK0,
+ GPIO_FN_MMCD0_0,
+ GPIO_FN_MMCD0_1,
+ GPIO_FN_MMCD0_2,
+ GPIO_FN_MMCD0_3,
+ GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5,
+ GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5,
+ GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5,
+ GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5,
+ GPIO_FN_MMCCMD0,
+ GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT,
+ GPIO_FN_MCP_WAIT__MCP_FRB,
+ GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1,
+ GPIO_FN_MCP_D15_MCP_NAF15,
+ GPIO_FN_MCP_D14_MCP_NAF14,
+ GPIO_FN_MCP_D13_MCP_NAF13,
+ GPIO_FN_MCP_D12_MCP_NAF12,
+ GPIO_FN_MCP_D11_MCP_NAF11,
+ GPIO_FN_MCP_D10_MCP_NAF10,
+ GPIO_FN_MCP_D9_MCP_NAF9,
+ GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1,
+ GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7,
+
+ GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6,
+ GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5,
+ GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4,
+ GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3,
+ GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2,
+ GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1,
+ GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0,
+ GPIO_FN_MCP_NBRSTOUT_,
+ GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE,
+
+ /* MSEL2 special case */
+ GPIO_FN_TSIF2_TS_XX1,
+ GPIO_FN_TSIF2_TS_XX2,
+ GPIO_FN_TSIF2_TS_XX3,
+ GPIO_FN_TSIF2_TS_XX4,
+ GPIO_FN_TSIF2_TS_XX5,
+ GPIO_FN_TSIF1_TS_XX1,
+ GPIO_FN_TSIF1_TS_XX2,
+ GPIO_FN_TSIF1_TS_XX3,
+ GPIO_FN_TSIF1_TS_XX4,
+ GPIO_FN_TSIF1_TS_XX5,
+ GPIO_FN_TSIF0_TS_XX1,
+ GPIO_FN_TSIF0_TS_XX2,
+ GPIO_FN_TSIF0_TS_XX3,
+ GPIO_FN_TSIF0_TS_XX4,
+ GPIO_FN_TSIF0_TS_XX5,
+ GPIO_FN_MST1_TS_XX1,
+ GPIO_FN_MST1_TS_XX2,
+ GPIO_FN_MST1_TS_XX3,
+ GPIO_FN_MST1_TS_XX4,
+ GPIO_FN_MST1_TS_XX5,
+ GPIO_FN_MST0_TS_XX1,
+ GPIO_FN_MST0_TS_XX2,
+ GPIO_FN_MST0_TS_XX3,
+ GPIO_FN_MST0_TS_XX4,
+ GPIO_FN_MST0_TS_XX5,
+
+ /* MSEL3 special cases */
+ GPIO_FN_SDHI0_VCCQ_MC0_ON,
+ GPIO_FN_SDHI0_VCCQ_MC0_OFF,
+ GPIO_FN_DEBUG_MON_VIO,
+ GPIO_FN_DEBUG_MON_LCDD,
+ GPIO_FN_LCDC_LCDC0,
+ GPIO_FN_LCDC_LCDC1,
+
+ /* MSEL4 special cases */
+ GPIO_FN_IRQ9_MEM_INT,
+ GPIO_FN_IRQ9_MCP_INT,
+ GPIO_FN_A11,
+ GPIO_FN_KEYOUT8,
+ GPIO_FN_TPU4TO3,
+ GPIO_FN_RESETA_N_PU_ON,
+ GPIO_FN_RESETA_N_PU_OFF,
+ GPIO_FN_EDBGREQ_PD,
+ GPIO_FN_EDBGREQ_PU,
+
+ /* Functions with pull-ups */
+ GPIO_FN_KEYIN0_PU,
+ GPIO_FN_KEYIN1_PU,
+ GPIO_FN_KEYIN2_PU,
+ GPIO_FN_KEYIN3_PU,
+ GPIO_FN_KEYIN4_PU,
+ GPIO_FN_KEYIN5_PU,
+ GPIO_FN_KEYIN6_PU,
+ GPIO_FN_KEYIN7_PU,
+ GPIO_FN_SDHICD0_PU,
+ GPIO_FN_SDHID0_0_PU,
+ GPIO_FN_SDHID0_1_PU,
+ GPIO_FN_SDHID0_2_PU,
+ GPIO_FN_SDHID0_3_PU,
+ GPIO_FN_SDHICMD0_PU,
+ GPIO_FN_SDHIWP0_PU,
+ GPIO_FN_SDHID1_0_PU,
+ GPIO_FN_SDHID1_1_PU,
+ GPIO_FN_SDHID1_2_PU,
+ GPIO_FN_SDHID1_3_PU,
+ GPIO_FN_SDHICMD1_PU,
+ GPIO_FN_SDHID2_0_PU,
+ GPIO_FN_SDHID2_1_PU,
+ GPIO_FN_SDHID2_2_PU,
+ GPIO_FN_SDHID2_3_PU,
+ GPIO_FN_SDHICMD2_PU,
+ GPIO_FN_MMCCMD0_PU,
+ GPIO_FN_MMCCMD1_PU,
+ GPIO_FN_MMCD0_0_PU,
+ GPIO_FN_MMCD0_1_PU,
+ GPIO_FN_MMCD0_2_PU,
+ GPIO_FN_MMCD0_3_PU,
+ GPIO_FN_MMCD0_4_PU,
+ GPIO_FN_MMCD0_5_PU,
+ GPIO_FN_MMCD0_6_PU,
+ GPIO_FN_MMCD0_7_PU,
+ GPIO_FN_FSIACK_PU,
+ GPIO_FN_FSIAILR_PU,
+ GPIO_FN_FSIAIBT_PU,
+ GPIO_FN_FSIAISLD_PU,
+
+ /* end of GPIO */
+ GPIO_NR,
+};
+
+/* DMA slave IDs */
+enum {
+ SHDMA_SLAVE_INVALID,
+ SHDMA_SLAVE_SCIF0_TX,
+ SHDMA_SLAVE_SCIF0_RX,
+ SHDMA_SLAVE_SCIF1_TX,
+ SHDMA_SLAVE_SCIF1_RX,
+ SHDMA_SLAVE_SCIF2_TX,
+ SHDMA_SLAVE_SCIF2_RX,
+ SHDMA_SLAVE_SCIF3_TX,
+ SHDMA_SLAVE_SCIF3_RX,
+ SHDMA_SLAVE_SCIF4_TX,
+ SHDMA_SLAVE_SCIF4_RX,
+ SHDMA_SLAVE_SCIF5_TX,
+ SHDMA_SLAVE_SCIF5_RX,
+ SHDMA_SLAVE_SCIF6_TX,
+ SHDMA_SLAVE_SCIF6_RX,
+ SHDMA_SLAVE_SCIF7_TX,
+ SHDMA_SLAVE_SCIF7_RX,
+ SHDMA_SLAVE_SCIF8_TX,
+ SHDMA_SLAVE_SCIF8_RX,
+ SHDMA_SLAVE_SDHI0_TX,
+ SHDMA_SLAVE_SDHI0_RX,
+ SHDMA_SLAVE_SDHI1_TX,
+ SHDMA_SLAVE_SDHI1_RX,
+ SHDMA_SLAVE_SDHI2_TX,
+ SHDMA_SLAVE_SDHI2_RX,
+ SHDMA_SLAVE_MMCIF_TX,
+ SHDMA_SLAVE_MMCIF_RX,
+};
+
+/*
+ * SH73A0 IRQ LOCATION TABLE
+ *
+ * 416 -----------------------------------------
+ * IRQ0-IRQ15
+ * 431 -----------------------------------------
+ * ...
+ * 448 -----------------------------------------
+ * sh73a0-intcs
+ * sh73a0-intca-irq-pins
+ * 680 -----------------------------------------
+ * ...
+ * 700 -----------------------------------------
+ * sh73a0-pint0
+ * 731 -----------------------------------------
+ * 732 -----------------------------------------
+ * sh73a0-pint1
+ * 739 -----------------------------------------
+ * ...
+ * 800 -----------------------------------------
+ * IRQ16-IRQ31
+ * 815 -----------------------------------------
+ * ...
+ * 928 -----------------------------------------
+ * sh73a0-intca-irq-pins
+ * 943 -----------------------------------------
+ */
+
+/* PINT interrupts are located at Linux IRQ 700 and up */
+#define SH73A0_PINT0_IRQ(irq) ((irq) + 700)
+#define SH73A0_PINT1_IRQ(irq) ((irq) + 732)
+
+#endif /* __ASM_SH73A0_H__ */
--- /dev/null
+#ifndef __ASM_ARCH_RMOBILE_SH73A0_H
+#define __ASM_ARCH_RMOBILE_SH73A0_H
+
+/* Global Timer */
+#define GLOBAL_TIMER_BASE_ADDR (0xF0000200)
+#define MERAM_BASE (0xE5580000)
+
+/* GIC */
+#define GIC_BASE (0xF0000100)
+#define ICCICR GIC_BASE
+
+/* Secure control register */
+#define LIFEC_SEC_SRC (0xE6110008)
+
+/* RWDT */
+#define RWDT_BASE (0xE6020000)
+
+/* HPB Semaphore Control Registers */
+#define HPB_BASE (0xE6001010)
+
+/* Bus Semaphore Control Registers */
+#define HPBSCR_BASE (0xE6001600)
+
+/* SBSC1 */
+#define SBSC1_BASE (0xFE400000)
+#define SDMRA1A (SBSC1_BASE + 0x100000)
+#define SDMRA2A (SBSC1_BASE + 0x1C0000)
+#define SDMRA3A (SBSC1_BASE + 0x104000)
+
+/* SBSC2 */
+#define SBSC2_BASE (0xFB400000)
+#define SDMRA1B (SBSC2_BASE + 0x100000)
+#define SDMRA2B (SBSC2_BASE + 0x1C0000)
+#define SDMRA3B (SBSC2_BASE + 0x104000)
+
+/* CPG */
+#define CPG_BASE (0xE6150000)
+#define CPG_SRCR_BASE (CPG_BASE + 0x80A0)
+#define WUPCR (CPG_BASE + 0x1010)
+#define SRESCR (CPG_BASE + 0x1018)
+#define PCLKCR (CPG_BASE + 0x1020)
+
+/* SYSC */
+#define SYSC_BASE (0xE6180000)
+#define RESCNT2 (SYSC_BASE + 0x8020)
+
+/* BSC */
+#define BSC_BASE (0xFEC10000)
+
+/* SCIF */
+#define SCIF0_BASE (0xE6C40000)
+#define SCIF1_BASE (0xE6C50000)
+#define SCIF2_BASE (0xE6C60000)
+#define SCIF3_BASE (0xE6C70000)
+#define SCIF4_BASE (0xE6C80000)
+#define SCIF5_BASE (0xE6CB0000)
+#define SCIF6_BASE (0xE6CC0000)
+#define SCIF7_BASE (0xE6CD0000)
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* RWDT */
+struct sh73a0_rwdt {
+ u16 rwtcnt0; /* 0x00 */
+ u16 dummy0; /* 0x02 */
+ u16 rwtcsra0; /* 0x04 */
+ u16 dummy1; /* 0x06 */
+ u16 rwtcsrb0; /* 0x08 */
+};
+
+/* HPB Semaphore Control Registers */
+struct sh73a0_hpb {
+ u32 hpbctrl0;
+ u32 hpbctrl1;
+ u32 hpbctrl2;
+ u32 cccr;
+ u32 dummy0; /* 0x20 */
+ u32 hpbctrl4;
+ u32 hpbctrl5;
+ u32 dummy1; /* 0x2C */
+ u32 hpbctrl6;
+};
+
+/* Bus Semaphore Control Registers */
+struct sh73a0_hpb_bscr {
+ u32 mpsrc; /* 0x00 */
+ u32 mpacctl; /* 0x04 */
+ u32 dummy0[6];
+ u32 smgpiosrc; /* 0x20 */
+ u32 smgpioerr;
+ u32 smgpiotime;
+ u32 smgpiocnt;
+ u32 dummy1[4]; /* 0x30 .. 0x3C */
+ u32 smcmt2src;
+ u32 smcmt2err;
+ u32 smcmt2time;
+ u32 smcmt2cnt;
+ u32 smcpgsrc;
+ u32 smcpgerr;
+ u32 smcpgtime;
+ u32 smcpgcnt;
+ u32 dummy2[4]; /* 0x60 - 0x6C */
+ u32 smsyscsrc;
+ u32 smsyscerr;
+ u32 smsysctime;
+ u32 smsysccnt;
+};
+
+/* SBSC */
+struct sh73a0_sbsc {
+ u32 dummy0[2]; /* 0x00, 0x04 */
+ u32 sdcr0;
+ u32 sdcr1;
+ u32 sdpcr;
+ u32 dummy1; /* 0x14 */
+ u32 sdcr0s;
+ u32 sdcr1s;
+ u32 rtcsr;
+ u32 dummy2; /* 0x24 */
+ u32 rtcor;
+ u32 rtcorh;
+ u32 rtcors;
+ u32 rtcorsh;
+ u32 dummy3[2]; /* 0x38, 0x3C */
+ u32 sdwcrc0;
+ u32 sdwcrc1;
+ u32 sdwcr00;
+ u32 sdwcr01;
+ u32 sdwcr10;
+ u32 sdwcr11;
+ u32 sdpdcr0;
+ u32 dummy4; /* 0x5C */
+ u32 sdwcr2;
+ u32 sdwcrc2;
+ u32 zqccr;
+ u32 dummy5[6]; /* 0x6C .. 0x80 */
+ u32 sdmracr0;
+ u32 dummy6; /* 0x88 */
+ u32 sdmrtmpcr;
+ u32 dummy7; /* 0x90 */
+ u32 sdmrtmpmsk;
+ u32 dummy8; /* 0x98 */
+ u32 sdgencnt;
+ u32 dphycnt0;
+ u32 dphycnt1;
+ u32 dphycnt2;
+ u32 dummy9[2]; /* 0xAC .. 0xB0 */
+ u32 sddrvcr0;
+ u32 dummy10[14]; /* 0xB8 .. 0xEC */
+ u32 dptdivcr0;
+ u32 dptdivcr1;
+ u32 dptdivcr2;
+ u32 dummy11; /* 0xFC */
+ u32 sdptcr0;
+ u32 sdptcr1;
+ u32 sdptcr2;
+ u32 sdptcr3; /* 0x10C */
+ u32 dummy12[145]; /* 0x110 .. 0x350 */
+ u32 dllcnt0; /* 0x354 */
+ u32 sbscmon0;
+};
+
+/* CPG */
+struct sh73a0_sbsc_cpg {
+ u32 frqcra; /* 0x00 */
+ u32 frqcrb;
+ u32 vclkcr1;
+ u32 vclkcr2;
+ u32 zbckcr;
+ u32 flckcr;
+ u32 fsiackcr;
+ u32 vclkcr3;
+ u32 rtstbcr;
+ u32 systbcr;
+ u32 pll1cr;
+ u32 pll2cr;
+ u32 mstpsr0;
+ u32 dummy0; /* 0x34 */
+ u32 mstpsr1;
+ u32 mstpsr5;
+ u32 mstpsr2;
+ u32 dummy1; /* 0x44 */
+ u32 mstpsr3;
+ u32 mstpsr4;
+ u32 dummy2; /* 0x50 */
+ u32 astat;
+ u32 dvfscr0;
+ u32 dvfscr1;
+ u32 dsitckcr;
+ u32 dsi0pckcr;
+ u32 dsi1pckcr;
+ u32 dsi0phycr;
+ u32 dsi1phycr;
+ u32 sd0ckcr;
+ u32 sd1ckcr;
+ u32 sd2ckcr;
+ u32 subckcr;
+ u32 spuackcr;
+ u32 msuckcr;
+ u32 hsickcr;
+ u32 fsibckcr;
+ u32 spuvckcr;
+ u32 mfck1cr;
+ u32 mfck2cr;
+ u32 dummy3[8]; /* 0xA0 .. 0xBC */
+ u32 ckscr;
+ u32 dummy4; /* 0xC4 */
+ u32 pll1stpcr;
+ u32 mpmode;
+ u32 pllecr;
+ u32 dummy5; /* 0xD4 */
+ u32 pll0cr;
+ u32 pll3cr;
+ u32 dummy6; /* 0xE0 */
+ u32 frqcrd;
+ u32 dummyi7; /* 0xE8 */
+ u32 vrefcr;
+ u32 pll0stpcr;
+ u32 dummy8; /* 0xF4 */
+ u32 pll2stpcr;
+ u32 pll3stpcr;
+ u32 dummy9[4]; /* 0x100 .. 0x10c */
+ u32 rmstpcr0;
+ u32 rmstpcr1;
+ u32 rmstpcr2;
+ u32 rmstpcr3;
+ u32 rmstpcr4;
+ u32 rmstpcr5;
+ u32 dummy10[2]; /* 0x128 .. 0x12c */
+ u32 smstpcr0;
+ u32 smstpcr1;
+ u32 smstpcr2;
+ u32 smstpcr3;
+ u32 smstpcr4;
+ u32 smstpcr5;
+ u32 dummy11[2]; /* 0x148 .. 0x14c */
+ u32 cpgxxcs4;
+ u32 dummy12[7]; /* 0x154 .. 0x16c */
+ u32 dvfscr2;
+ u32 dvfscr3;
+ u32 dvfscr4;
+ u32 dvfscr5; /* 0x17C */
+};
+
+/* CPG SRCR part OK */
+struct sh73a0_sbsc_cpg_srcr {
+ u32 srcr0;
+ u32 dummy0; /* 0xA4 */
+ u32 srcr1;
+ u32 dummy1; /* 0xAC */
+ u32 srcr2;
+ u32 dummy2; /* 0xB4 */
+ u32 srcr3;
+ u32 srcr4;
+ u32 dummy3; /* 0xC0 */
+ u32 srcr5;
+};
+
+/* BSC */
+struct sh73a0_bsc {
+ u32 cmncr;
+ u32 cs0bcr;
+ u32 cs2bcr;
+ u32 dummy0; /* 0x0C */
+ u32 cs4bcr;
+ u32 cs5abcr;
+ u32 cs5bbcr;
+ u32 cs6abcr;
+ u32 cs6bbcr;
+ u32 cs0wcr;
+ u32 cs2wcr;
+ u32 dummy1; /* 0x2C */
+ u32 cs4wcr;
+ u32 cs5awcr;
+ u32 cs5bwcr;
+ u32 cs6awcr;
+ u32 cs6bwcr;
+ u32 rbwtcnt;
+ u32 busycr;
+ u32 dummy2; /* 0x5c */
+ u32 cs7abcr;
+ u32 cs7awcr;
+ u32 dummy3[2]; /* 0x68, 0x6C */
+ u32 bromtimcr;
+};
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARCH_RMOBILE_SH73A0_H */
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+struct rmobile_sysinfo {
+ char *board_string;
+};
+extern const struct rmobile_sysinfo sysinfo;
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2012.
+ *
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_GPIO_H_
+#define _S3C24X0_GPIO_H_
+
+enum s3c2440_gpio {
+ GPA0,
+ GPA1,
+ GPA2,
+ GPA3,
+ GPA4,
+ GPA5,
+ GPA6,
+ GPA7,
+ GPA8,
+ GPA9,
+ GPA10,
+ GPA11,
+ GPA12,
+ GPA13,
+ GPA14,
+ GPA15,
+ GPA16,
+ GPA17,
+ GPA18,
+ GPA19,
+ GPA20,
+ GPA21,
+ GPA22,
+ GPA23,
+ GPA24,
+
+ GPB0 = 32,
+ GPB1,
+ GPB2,
+ GPB3,
+ GPB4,
+ GPB5,
+ GPB6,
+ GPB7,
+ GPB8,
+ GPB9,
+ GPB10,
+
+ GPC0 = 64,
+ GPC1,
+ GPC2,
+ GPC3,
+ GPC4,
+ GPC5,
+ GPC6,
+ GPC7,
+ GPC8,
+ GPC9,
+ GPC10,
+ GPC11,
+ GPC12,
+ GPC13,
+ GPC14,
+ GPC15,
+
+ GPD0 = 96,
+ GPD1,
+ GPD2,
+ GPD3,
+ GPD4,
+ GPD5,
+ GPD6,
+ GPD7,
+ GPD8,
+ GPD9,
+ GPD10,
+ GPD11,
+ GPD12,
+ GPD13,
+ GPD14,
+ GPD15,
+
+ GPE0 = 128,
+ GPE1,
+ GPE2,
+ GPE3,
+ GPE4,
+ GPE5,
+ GPE6,
+ GPE7,
+ GPE8,
+ GPE9,
+ GPE10,
+ GPE11,
+ GPE12,
+ GPE13,
+ GPE14,
+ GPE15,
+
+ GPF0 = 160,
+ GPF1,
+ GPF2,
+ GPF3,
+ GPF4,
+ GPF5,
+ GPF6,
+ GPF7,
+
+ GPG0 = 192,
+ GPG1,
+ GPG2,
+ GPG3,
+ GPG4,
+ GPG5,
+ GPG6,
+ GPG7,
+ GPG8,
+ GPG9,
+ GPG10,
+ GPG11,
+ GPG12,
+ GPG13,
+ GPG14,
+ GPG15,
+
+ GPH0 = 224,
+ GPH1,
+ GPH2,
+ GPH3,
+ GPH4,
+ GPH5,
+ GPH6,
+ GPH7,
+ GPH8,
+ GPH9,
+ GPH10,
+
+ GPJ0 = 256,
+ GPJ1,
+ GPJ2,
+ GPJ3,
+ GPJ4,
+ GPJ5,
+ GPJ6,
+ GPJ7,
+ GPJ8,
+ GPJ9,
+ GPJ10,
+ GPJ11,
+ GPJ12,
+};
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2012
+ *
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_IOMUX_H_
+#define _S3C24X0_IOMUX_H_
+
+enum s3c2440_iomux_func {
+ /* PORT A */
+ IOMUXA_ADDR0 = 1,
+ IOMUXA_ADDR16 = (1 << 1),
+ IOMUXA_ADDR17 = (1 << 2),
+ IOMUXA_ADDR18 = (1 << 3),
+ IOMUXA_ADDR19 = (1 << 4),
+ IOMUXA_ADDR20 = (1 << 5),
+ IOMUXA_ADDR21 = (1 << 6),
+ IOMUXA_ADDR22 = (1 << 7),
+ IOMUXA_ADDR23 = (1 << 8),
+ IOMUXA_ADDR24 = (1 << 9),
+ IOMUXA_ADDR25 = (1 << 10),
+ IOMUXA_ADDR26 = (1 << 11),
+ IOMUXA_nGCS1 = (1 << 12),
+ IOMUXA_nGCS2 = (1 << 13),
+ IOMUXA_nGCS3 = (1 << 14),
+ IOMUXA_nGCS4 = (1 << 15),
+ IOMUXA_nGCS5 = (1 << 16),
+ IOMUXA_CLE = (1 << 17),
+ IOMUXA_ALE = (1 << 18),
+ IOMUXA_nFWE = (1 << 19),
+ IOMUXA_nFRE = (1 << 20),
+ IOMUXA_nRSTOUT = (1 << 21),
+ IOMUXA_nFCE = (1 << 22),
+
+ /* PORT B */
+ IOMUXB_nXDREQ0 = (2 << 20),
+ IOMUXB_nXDACK0 = (2 << 18),
+ IOMUXB_nXDREQ1 = (2 << 16),
+ IOMUXB_nXDACK1 = (2 << 14),
+ IOMUXB_nXBREQ = (2 << 12),
+ IOMUXB_nXBACK = (2 << 10),
+ IOMUXB_TCLK0 = (2 << 8),
+ IOMUXB_TOUT3 = (2 << 6),
+ IOMUXB_TOUT2 = (2 << 4),
+ IOMUXB_TOUT1 = (2 << 2),
+ IOMUXB_TOUT0 = 2,
+
+ /* PORT C */
+ IOMUXC_VS7 = (2 << 30),
+ IOMUXC_VS6 = (2 << 28),
+ IOMUXC_VS5 = (2 << 26),
+ IOMUXC_VS4 = (2 << 24),
+ IOMUXC_VS3 = (2 << 22),
+ IOMUXC_VS2 = (2 << 20),
+ IOMUXC_VS1 = (2 << 18),
+ IOMUXC_VS0 = (2 << 16),
+ IOMUXC_LCD_LPCREVB = (2 << 14),
+ IOMUXC_LCD_LPCREV = (2 << 12),
+ IOMUXC_LCD_LPCOE = (2 << 10),
+ IOMUXC_VM = (2 << 8),
+ IOMUXC_VFRAME = (2 << 6),
+ IOMUXC_VLINE = (2 << 4),
+ IOMUXC_VCLK = (2 << 2),
+ IOMUXC_LEND = 2,
+ IOMUXC_I2SSDI = (3 << 8),
+
+ /* PORT D */
+ IOMUXD_VS23 = (2 << 30),
+ IOMUXD_VS22 = (2 << 28),
+ IOMUXD_VS21 = (2 << 26),
+ IOMUXD_VS20 = (2 << 24),
+ IOMUXD_VS19 = (2 << 22),
+ IOMUXD_VS18 = (2 << 20),
+ IOMUXD_VS17 = (2 << 18),
+ IOMUXD_VS16 = (2 << 16),
+ IOMUXD_VS15 = (2 << 14),
+ IOMUXD_VS14 = (2 << 12),
+ IOMUXD_VS13 = (2 << 10),
+ IOMUXD_VS12 = (2 << 8),
+ IOMUXD_VS11 = (2 << 6),
+ IOMUXD_VS10 = (2 << 4),
+ IOMUXD_VS9 = (2 << 2),
+ IOMUXD_VS8 = 2,
+ IOMUXD_nSS0 = (3 << 30),
+ IOMUXD_nSS1 = (3 << 28),
+ IOMUXD_SPICLK1 = (3 << 20),
+ IOMUXD_SPIMOSI1 = (3 << 18),
+ IOMUXD_SPIMISO1 = (3 << 16),
+
+ /* PORT E */
+ IOMUXE_IICSDA = (2 << 30),
+ IOMUXE_IICSCL = (2 << 28),
+ IOMUXE_SPICLK0 = (2 << 26),
+ IOMUXE_SPIMOSI0 = (2 << 24),
+ IOMUXE_SPIMISO0 = (2 << 22),
+ IOMUXE_SDDAT3 = (2 << 20),
+ IOMUXE_SDDAT2 = (2 << 18),
+ IOMUXE_SDDAT1 = (2 << 16),
+ IOMUXE_SDDAT0 = (2 << 14),
+ IOMUXE_SDCMD = (2 << 12),
+ IOMUXE_SDCLK = (2 << 10),
+ IOMUXE_I2SDO = (2 << 8),
+ IOMUXE_I2SDI = (2 << 6),
+ IOMUXE_CDCLK = (2 << 4),
+ IOMUXE_I2SSCLK = (2 << 2),
+ IOMUXE_I2SLRCK = 2,
+ IOMUXE_AC_SDATA_OUT = (3 << 8),
+ IOMUXE_AC_SDATA_IN = (3 << 6),
+ IOMUXE_AC_nRESET = (3 << 4),
+ IOMUXE_AC_BIT_CLK = (3 << 2),
+ IOMUXE_AC_SYNC = 3,
+
+ /* PORT F */
+ IOMUXF_EINT7 = (2 << 14),
+ IOMUXF_EINT6 = (2 << 12),
+ IOMUXF_EINT5 = (2 << 10),
+ IOMUXF_EINT4 = (2 << 8),
+ IOMUXF_EINT3 = (2 << 6),
+ IOMUXF_EINT2 = (2 << 4),
+ IOMUXF_EINT1 = (2 << 2),
+ IOMUXF_EINT0 = 2,
+
+ /* PORT G */
+ IOMUXG_EINT23 = (2 << 30),
+ IOMUXG_EINT22 = (2 << 28),
+ IOMUXG_EINT21 = (2 << 26),
+ IOMUXG_EINT20 = (2 << 24),
+ IOMUXG_EINT19 = (2 << 22),
+ IOMUXG_EINT18 = (2 << 20),
+ IOMUXG_EINT17 = (2 << 18),
+ IOMUXG_EINT16 = (2 << 16),
+ IOMUXG_EINT15 = (2 << 14),
+ IOMUXG_EINT14 = (2 << 12),
+ IOMUXG_EINT13 = (2 << 10),
+ IOMUXG_EINT12 = (2 << 8),
+ IOMUXG_EINT11 = (2 << 6),
+ IOMUXG_EINT10 = (2 << 4),
+ IOMUXG_EINT9 = (2 << 2),
+ IOMUXG_EINT8 = 2,
+ IOMUXG_TCLK1 = (3 << 22),
+ IOMUXG_nCTS1 = (3 << 20),
+ IOMUXG_nRTS1 = (3 << 18),
+ IOMUXG_SPICLK1 = (3 << 14),
+ IOMUXG_SPIMOSI1 = (3 << 12),
+ IOMUXG_SPIMISO1 = (3 << 10),
+ IOMUXG_LCD_PWRDN = (3 << 8),
+ IOMUXG_nSS1 = (3 << 6),
+ IOMUXG_nSS0 = (3 << 4),
+
+ /* PORT H */
+ IOMUXH_CLKOUT1 = (2 << 20),
+ IOMUXH_CLKOUT0 = (2 << 18),
+ IOMUXH_UEXTCLK = (2 << 16),
+ IOMUXH_RXD2 = (2 << 14),
+ IOMUXH_TXD2 = (2 << 12),
+ IOMUXH_RXD1 = (2 << 10),
+ IOMUXH_TXD1 = (2 << 8),
+ IOMUXH_RXD0 = (2 << 6),
+ IOMUXH_TXD0 = (2 << 4),
+ IOMUXH_nRTS0 = (2 << 2),
+ IOMUXH_nCTS0 = 2,
+ IOMUXH_nCTS1 = (3 << 14),
+ IOMUXH_nRTS1 = (3 << 12),
+
+ /* PORT J */
+ IOMUXJ_CAMRESET = (2 << 24),
+ IOMUXJ_CAMCLKOUT = (2 << 22),
+ IOMUXJ_CAMHREF = (2 << 20),
+ IOMUXJ_CAMVSYNC = (2 << 18),
+ IOMUXJ_CAMPCLK = (2 << 16),
+ IOMUXJ_CAMDATA7 = (2 << 14),
+ IOMUXJ_CAMDATA6 = (2 << 12),
+ IOMUXJ_CAMDATA5 = (2 << 10),
+ IOMUXJ_CAMDATA4 = (2 << 8),
+ IOMUXJ_CAMDATA3 = (2 << 6),
+ IOMUXJ_CAMDATA2 = (2 << 4),
+ IOMUXJ_CAMDATA1 = (2 << 2),
+ IOMUXJ_CAMDATA0 = 2
+};
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _RESET_MANAGER_H_
+#define _RESET_MANAGER_H_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+struct socfpga_reset_manager {
+ u32 padding1;
+ u32 ctrl;
+ u32 padding2;
+ u32 padding3;
+ u32 mpu_mod_reset;
+ u32 per_mod_reset;
+ u32 per2_mod_reset;
+ u32 brg_mod_reset;
+};
+
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+
+#endif /* _RESET_MANAGER_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_BASE_ADDRS_H_
+#define _SOCFPGA_BASE_ADDRS_H_
+
+#define SOCFPGA_L3REGS_ADDRESS 0xff800000
+#define SOCFPGA_UART0_ADDRESS 0xffc02000
+#define SOCFPGA_UART1_ADDRESS 0xffc03000
+#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+
+#endif /* _SOCFPGA_BASE_ADDRS_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2012 Pavel Machek <pavel@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_SPL_H_
+#define _SOCFPGA_SPL_H_
+
+/* Symbols from linker script */
+extern char __malloc_start, __malloc_end, __stack_start;
+
+#define BOOT_DEVICE_RAM 1
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_TIMER_H_
+#define _SOCFPGA_TIMER_H_
+
+struct socfpga_timer {
+ u32 load_val;
+ u32 curr_val;
+ u32 ctrl;
+ u32 eoi;
+ u32 int_stat;
+};
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_BOARD_H_
+#define _TEGRA_BOARD_H_
+
+/* Set up pinmux to make UART usable */
+void gpio_config_uart(void); /* CONFIG_SPI_UART_SWITCH */
+void gpio_early_init_uart(void); /*!CONFIG_SPI_UART_SWITCH */
+
+/* Set up early UART output */
+void board_init_uart_f(void);
+
+/* Set up any early GPIOs the board might need for proper operation */
+void gpio_early_init(void); /* overrideable GPIO config */
+
+/*
+ * Hooks to allow boards to set up the pinmux for a specific function.
+ * Has to be implemented in the board files as we don't yet support pinmux
+ * setup from FTD. If a board file does not implement one of those functions
+ * an empty stub function will be called.
+ */
+
+void pin_mux_usb(void); /* overrideable USB pinmux setup */
+void pin_mux_spi(void); /* overrideable SPI pinmux setup */
+void pin_mux_nand(void); /* overrideable NAND pinmux setup */
+
+#endif
/* PLL registers - there are several PLLs in the clock controller */
struct clk_pll {
uint pll_base; /* the control register */
- uint pll_out; /* output control */
- uint reserved;
+ uint pll_out[2]; /* output control */
uint pll_misc; /* other misc things */
};
#define PLL_DIVM_SHIFT 0
#define PLL_DIVM_MASK (0x1f << PLL_DIVM_SHIFT)
+/* CLK_RST_CONTROLLER_PLLx_OUTx_0 */
+#define PLL_OUT_RSTN (1 << 0)
+#define PLL_OUT_CLKEN (1 << 1)
+#define PLL_OUT_OVRRIDE (1 << 2)
+
+#define PLL_OUT_RATIO_SHIFT 8
+#define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT)
+
/* CLK_RST_CONTROLLER_PLLx_MISC_0 */
#define PLL_CPCON_SHIFT 8
#define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT)
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Tegra clock control functions */
+
+#ifndef _CLOCK_H
+#define _CLOCK_H
+
+/* Set of oscillator frequencies supported in the internal API. */
+enum clock_osc_freq {
+ /* All in MHz, so 13_0 is 13.0MHz */
+ CLOCK_OSC_FREQ_13_0,
+ CLOCK_OSC_FREQ_19_2,
+ CLOCK_OSC_FREQ_12_0,
+ CLOCK_OSC_FREQ_26_0,
+
+ CLOCK_OSC_FREQ_COUNT,
+};
+
+#include <asm/arch/clock-tables.h>
+/* PLL stabilization delay in usec */
+#define CLOCK_PLL_STABLE_DELAY_US 300
+
+/* return the current oscillator clock frequency */
+enum clock_osc_freq clock_get_osc_freq(void);
+
+/**
+ * Start PLL using the provided configuration parameters.
+ *
+ * @param id clock id
+ * @param divm input divider
+ * @param divn feedback divider
+ * @param divp post divider 2^n
+ * @param cpcon charge pump setup control
+ * @param lfcon loop filter setup control
+ *
+ * @returns monotonic time in us that the PLL will be stable
+ */
+unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
+ u32 divp, u32 cpcon, u32 lfcon);
+
+/**
+ * Set PLL output frequency
+ *
+ * @param clkid clock id
+ * @param pllout pll output id
+ * @param rate desired output rate
+ *
+ * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
+ */
+int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout,
+ unsigned rate);
+
+/**
+ * Read low-level parameters of a PLL.
+ *
+ * @param id clock id to read (note: USB is not supported)
+ * @param divm returns input divider
+ * @param divn returns feedback divider
+ * @param divp returns post divider 2^n
+ * @param cpcon returns charge pump setup control
+ * @param lfcon returns loop filter setup control
+ *
+ * @returns 0 if ok, -1 on error (invalid clock id)
+ */
+int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
+ u32 *divp, u32 *cpcon, u32 *lfcon);
+
+/*
+ * Enable a clock
+ *
+ * @param id clock id
+ */
+void clock_enable(enum periph_id clkid);
+
+/*
+ * Disable a clock
+ *
+ * @param id clock id
+ */
+void clock_disable(enum periph_id clkid);
+
+/*
+ * Set whether a clock is enabled or disabled.
+ *
+ * @param id clock id
+ * @param enable 1 to enable, 0 to disable
+ */
+void clock_set_enable(enum periph_id clkid, int enable);
+
+/**
+ * Reset a peripheral. This puts it in reset, waits for a delay, then takes
+ * it out of reset and waits for th delay again.
+ *
+ * @param periph_id peripheral to reset
+ * @param us_delay time to delay in microseconds
+ */
+void reset_periph(enum periph_id periph_id, int us_delay);
+
+/**
+ * Put a peripheral into or out of reset.
+ *
+ * @param periph_id peripheral to reset
+ * @param enable 1 to put into reset, 0 to take out of reset
+ */
+void reset_set_enable(enum periph_id periph_id, int enable);
+
+
+/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
+enum crc_reset_id {
+ /* Things we can hold in reset for each CPU */
+ crc_rst_cpu = 1,
+ crc_rst_de = 1 << 2, /* What is de? */
+ crc_rst_watchdog = 1 << 3,
+ crc_rst_debug = 1 << 4,
+};
+
+/**
+ * Put parts of the CPU complex into or out of reset.\
+ *
+ * @param cpu cpu number (0 or 1 on Tegra2)
+ * @param which which parts of the complex to affect (OR of crc_reset_id)
+ * @param reset 1 to assert reset, 0 to de-assert
+ */
+void reset_cmplx_set_enable(int cpu, int which, int reset);
+
+/**
+ * Set the source for a peripheral clock. This plus the divisor sets the
+ * clock rate. You need to look up the datasheet to see the meaning of the
+ * source parameter as it changes for each peripheral.
+ *
+ * Warning: This function is only for use pre-relocation. Please use
+ * clock_start_periph_pll() instead.
+ *
+ * @param periph_id peripheral to adjust
+ * @param source source clock (0, 1, 2 or 3)
+ */
+void clock_ll_set_source(enum periph_id periph_id, unsigned source);
+
+/**
+ * Set the source and divisor for a peripheral clock. This sets the
+ * clock rate. You need to look up the datasheet to see the meaning of the
+ * source parameter as it changes for each peripheral.
+ *
+ * Warning: This function is only for use pre-relocation. Please use
+ * clock_start_periph_pll() instead.
+ *
+ * @param periph_id peripheral to adjust
+ * @param source source clock (0, 1, 2 or 3)
+ * @param divisor divisor value to use
+ */
+void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
+ unsigned divisor);
+
+/**
+ * Start a peripheral PLL clock at the given rate. This also resets the
+ * peripheral.
+ *
+ * @param periph_id peripheral to start
+ * @param parent PLL id of required parent clock
+ * @param rate Required clock rate in Hz
+ * @return rate selected in Hz, or -1U if something went wrong
+ */
+unsigned clock_start_periph_pll(enum periph_id periph_id,
+ enum clock_id parent, unsigned rate);
+
+/**
+ * Returns the rate of a peripheral clock in Hz. Since the caller almost
+ * certainly knows the parent clock (having just set it) we require that
+ * this be passed in so we don't need to work it out.
+ *
+ * @param periph_id peripheral to start
+ * @param parent PLL id of parent clock (used to calculate rate, you
+ * must know this!)
+ * @return clock rate of peripheral in Hz
+ */
+unsigned long clock_get_periph_rate(enum periph_id periph_id,
+ enum clock_id parent);
+
+/**
+ * Adjust peripheral PLL clock to the given rate. This does not reset the
+ * peripheral. If a second stage divisor is not available, pass NULL for
+ * extra_div. If it is available, then this parameter will return the
+ * divisor selected (which will be a power of 2 from 1 to 256).
+ *
+ * @param periph_id peripheral to start
+ * @param parent PLL id of required parent clock
+ * @param rate Required clock rate in Hz
+ * @param extra_div value for the second-stage divisor (NULL if one is
+ not available)
+ * @return rate selected in Hz, or -1U if something went wrong
+ */
+unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
+ enum clock_id parent, unsigned rate, int *extra_div);
+
+/**
+ * Returns the clock rate of a specified clock, in Hz.
+ *
+ * @param parent PLL id of clock to check
+ * @return rate of clock in Hz
+ */
+unsigned clock_get_rate(enum clock_id clkid);
+
+/**
+ * Start up a UART using low-level calls
+ *
+ * Prior to relocation clock_start_periph_pll() cannot be called. This
+ * function provides a way to set up a UART using low-level calls which
+ * do not require BSS.
+ *
+ * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1)
+ */
+void clock_ll_start_uart(enum periph_id periph_id);
+
+/**
+ * Decode a peripheral ID from a device tree node.
+ *
+ * This works by looking up the peripheral's 'clocks' node and reading out
+ * the second cell, which is the clock number / peripheral ID.
+ *
+ * @param blob FDT blob to use
+ * @param node Node to look at
+ * @return peripheral ID, or PERIPH_ID_NONE if none
+ */
+enum periph_id clock_decode_periph_id(const void *blob, int node);
+
+/**
+ * Checks if the oscillator bypass is enabled (XOBP bit)
+ *
+ * @return 1 if bypass is enabled, 0 if not
+ */
+int clock_get_osc_bypass(void);
+
+/*
+ * Checks that clocks are valid and prints a warning if not
+ *
+ * @return 0 if ok, -1 on error
+ */
+int clock_verify(void);
+
+/* Initialize the clocks */
+void clock_init(void);
+
+/* Initialize the PLLs */
+void clock_early_init(void);
+
+#endif /* _CLOCK_H_ */
/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- *
+ * Copyright (c) 2011, Google Inc. All rights reserved.
* See file CREDITS for list of people who contributed to this
* project.
*
* MA 02111-1307 USA
*/
-#ifndef _BOARD_H_
-#define _BOARD_H_
+#ifndef _TEGRA_GPIO_H_
+#define _TEGRA_GPIO_H_
+
+#define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8)
+#define GPIO_NAME_SIZE 20 /* gpio_request max label len */
-void gpio_config_uart(void);
-void gpio_early_init(void);
-void gpio_early_init_uart(void);
+#define GPIO_BANK(x) ((x) >> 5)
+#define GPIO_PORT(x) (((x) >> 3) & 0x3)
+#define GPIO_FULLPORT(x) ((x) >> 3)
+#define GPIO_BIT(x) ((x) & 0x7)
/*
- * Set up any pin muxing needed for USB (for now, since fdt doesn't support
- * it). Boards can overwrite the default fucction which does nothing.
+ * Tegra-specific GPIO API
*/
-void pin_mux_usb(void);
-#endif /* BOARD_H */
+void gpio_info(void);
+
+#define gpio_status() gpio_info()
+#endif /* TEGRA_GPIO_H_ */
* MA 02111-1307 USA
*/
-#ifndef _TEGRA20_H_
-#define _TEGRA20_H_
+#ifndef _TEGRA_H_
+#define _TEGRA_H_
-#define NV_PA_SDRAM_BASE 0x00000000
#define NV_PA_ARM_PERIPHBASE 0x50040000
#define NV_PA_PG_UP_BASE 0x60000000
#define NV_PA_TMRUS_BASE 0x60005010
#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000)
#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
+#define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000)
#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
+#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400)
#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
#define NV_PA_CSITE_BASE 0x70040000
-#define TEGRA_USB1_BASE 0xC5000000
-#define TEGRA_USB3_BASE 0xC5008000
#define TEGRA_USB_ADDR_MASK 0xFFFFC000
#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE
};
/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
-#define AP20_WB_RUN_ADDRESS 0x40020000
+#define NV_WB_RUN_ADDRESS 0x40020000
#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */
#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */
-#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */
/* These are the available SKUs (product types) for Tegra */
enum {
#define PRM_RSTCTRL NV_PA_PMC_BASE
#endif
-#endif /* TEGRA20_H */
+#endif /* TEGRA_H */
/*
- * NVIDIA Tegra20 I2C controller
+ * NVIDIA Tegra I2C controller
*
* Copyright 2010-2011 NVIDIA Corporation
*
*/
int tegra_i2c_get_dvc_bus_num(void);
-#endif
+#endif /* _TEGRA_I2C_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2010-2012 NVIDIA Corporation <www.nvidia.com>
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Tegra20 clock PLL tables */
+
+#ifndef _CLOCK_TABLES_H_
+#define _CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+ CLOCK_ID_FIRST,
+ CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+ CLOCK_ID_MEMORY,
+ CLOCK_ID_PERIPH,
+ CLOCK_ID_AUDIO,
+ CLOCK_ID_USB,
+ CLOCK_ID_DISPLAY,
+
+ /* now the simple ones */
+ CLOCK_ID_FIRST_SIMPLE,
+ CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+ CLOCK_ID_EPCI,
+ CLOCK_ID_SFROM32KHZ,
+
+ /* These are the base clocks (inputs to the Tegra SOC) */
+ CLOCK_ID_32KHZ,
+ CLOCK_ID_OSC,
+
+ CLOCK_ID_COUNT, /* number of clocks */
+ CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+ PERIPH_ID_FIRST,
+
+ /* Low word: 31:0 */
+ PERIPH_ID_CPU = PERIPH_ID_FIRST,
+ PERIPH_ID_RESERVED1,
+ PERIPH_ID_RESERVED2,
+ PERIPH_ID_AC97,
+ PERIPH_ID_RTC,
+ PERIPH_ID_TMR,
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+
+ /* 8 */
+ PERIPH_ID_GPIO,
+ PERIPH_ID_SDMMC2,
+ PERIPH_ID_SPDIF,
+ PERIPH_ID_I2S1,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_NDFLASH,
+ PERIPH_ID_SDMMC1,
+ PERIPH_ID_SDMMC4,
+
+ /* 16 */
+ PERIPH_ID_TWC,
+ PERIPH_ID_PWM,
+ PERIPH_ID_I2S2,
+ PERIPH_ID_EPP,
+ PERIPH_ID_VI,
+ PERIPH_ID_2D,
+ PERIPH_ID_USBD,
+ PERIPH_ID_ISP,
+
+ /* 24 */
+ PERIPH_ID_3D,
+ PERIPH_ID_IDE,
+ PERIPH_ID_DISP2,
+ PERIPH_ID_DISP1,
+ PERIPH_ID_HOST1X,
+ PERIPH_ID_VCP,
+ PERIPH_ID_RESERVED30,
+ PERIPH_ID_CACHE2,
+
+ /* Middle word: 63:32 */
+ PERIPH_ID_MEM,
+ PERIPH_ID_AHBDMA,
+ PERIPH_ID_APBDMA,
+ PERIPH_ID_RESERVED35,
+ PERIPH_ID_KBC,
+ PERIPH_ID_STAT_MON,
+ PERIPH_ID_PMC,
+ PERIPH_ID_FUSE,
+
+ /* 40 */
+ PERIPH_ID_KFUSE,
+ PERIPH_ID_SBC1,
+ PERIPH_ID_SNOR,
+ PERIPH_ID_SPI1,
+ PERIPH_ID_SBC2,
+ PERIPH_ID_XIO,
+ PERIPH_ID_SBC3,
+ PERIPH_ID_DVC_I2C,
+
+ /* 48 */
+ PERIPH_ID_DSI,
+ PERIPH_ID_TVO,
+ PERIPH_ID_MIPI,
+ PERIPH_ID_HDMI,
+ PERIPH_ID_CSI,
+ PERIPH_ID_TVDAC,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_UART3,
+
+ /* 56 */
+ PERIPH_ID_RESERVED56,
+ PERIPH_ID_EMC,
+ PERIPH_ID_USB2,
+ PERIPH_ID_USB3,
+ PERIPH_ID_MPE,
+ PERIPH_ID_VDE,
+ PERIPH_ID_BSEA,
+ PERIPH_ID_BSEV,
+
+ /* Upper word 95:64 */
+ PERIPH_ID_SPEEDO,
+ PERIPH_ID_UART4,
+ PERIPH_ID_UART5,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_SBC4,
+ PERIPH_ID_SDMMC3,
+ PERIPH_ID_PCIE,
+ PERIPH_ID_OWR,
+
+ /* 72 */
+ PERIPH_ID_AFI,
+ PERIPH_ID_CORESIGHT,
+ PERIPH_ID_RESERVED74,
+ PERIPH_ID_AVPUCQ,
+ PERIPH_ID_RESERVED76,
+ PERIPH_ID_RESERVED77,
+ PERIPH_ID_RESERVED78,
+ PERIPH_ID_RESERVED79,
+
+ /* 80 */
+ PERIPH_ID_RESERVED80,
+ PERIPH_ID_RESERVED81,
+ PERIPH_ID_RESERVED82,
+ PERIPH_ID_RESERVED83,
+ PERIPH_ID_IRAMA,
+ PERIPH_ID_IRAMB,
+ PERIPH_ID_IRAMC,
+ PERIPH_ID_IRAMD,
+
+ /* 88 */
+ PERIPH_ID_CRAM2,
+ PERIPH_ID_SYNC_CLK_DOUBLER,
+ PERIPH_ID_CLK_M_DOUBLER,
+ PERIPH_ID_RESERVED91,
+ PERIPH_ID_SUS_OUT,
+ PERIPH_ID_DEV2_OUT,
+ PERIPH_ID_DEV1_OUT,
+
+ PERIPH_ID_COUNT,
+ PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+ PLL_OUT1,
+ PLL_OUT2,
+ PLL_OUT3,
+ PLL_OUT4
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
+#define PERIPH_REG(id) ((id) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range, and not a simple PLL */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
+ (id) < CLOCK_ID_FIRST_SIMPLE)
+
+#endif /* _CLOCK_TABLES_H_ */
* MA 02111-1307 USA
*/
-/* Tegra2 clock control functions */
+/* Tegra20 clock control functions */
-#ifndef _CLOCK_H
-#define _CLOCK_H
+#ifndef _TEGRA20_CLOCK_H
+#define _TEGRA20_CLOCK_H
-/* Set of oscillator frequencies supported in the internal API. */
-enum clock_osc_freq {
- /* All in MHz, so 13_0 is 13.0MHz */
- CLOCK_OSC_FREQ_13_0,
- CLOCK_OSC_FREQ_19_2,
- CLOCK_OSC_FREQ_12_0,
- CLOCK_OSC_FREQ_26_0,
+#include <asm/arch-tegra/clock.h>
- CLOCK_OSC_FREQ_COUNT,
-};
-
-/* The PLLs supported by the hardware */
-enum clock_id {
- CLOCK_ID_FIRST,
- CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
- CLOCK_ID_MEMORY,
- CLOCK_ID_PERIPH,
- CLOCK_ID_AUDIO,
- CLOCK_ID_USB,
- CLOCK_ID_DISPLAY,
-
- /* now the simple ones */
- CLOCK_ID_FIRST_SIMPLE,
- CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
- CLOCK_ID_EPCI,
- CLOCK_ID_SFROM32KHZ,
-
- /* These are the base clocks (inputs to the Tegra SOC) */
- CLOCK_ID_32KHZ,
- CLOCK_ID_OSC,
-
- CLOCK_ID_COUNT, /* number of clocks */
- CLOCK_ID_NONE = -1,
-};
-
-/* The clocks supported by the hardware */
-enum periph_id {
- PERIPH_ID_FIRST,
-
- /* Low word: 31:0 */
- PERIPH_ID_CPU = PERIPH_ID_FIRST,
- PERIPH_ID_RESERVED1,
- PERIPH_ID_RESERVED2,
- PERIPH_ID_AC97,
- PERIPH_ID_RTC,
- PERIPH_ID_TMR,
- PERIPH_ID_UART1,
- PERIPH_ID_UART2,
-
- /* 8 */
- PERIPH_ID_GPIO,
- PERIPH_ID_SDMMC2,
- PERIPH_ID_SPDIF,
- PERIPH_ID_I2S1,
- PERIPH_ID_I2C1,
- PERIPH_ID_NDFLASH,
- PERIPH_ID_SDMMC1,
- PERIPH_ID_SDMMC4,
-
- /* 16 */
- PERIPH_ID_TWC,
- PERIPH_ID_PWM,
- PERIPH_ID_I2S2,
- PERIPH_ID_EPP,
- PERIPH_ID_VI,
- PERIPH_ID_2D,
- PERIPH_ID_USBD,
- PERIPH_ID_ISP,
-
- /* 24 */
- PERIPH_ID_3D,
- PERIPH_ID_IDE,
- PERIPH_ID_DISP2,
- PERIPH_ID_DISP1,
- PERIPH_ID_HOST1X,
- PERIPH_ID_VCP,
- PERIPH_ID_RESERVED30,
- PERIPH_ID_CACHE2,
-
- /* Middle word: 63:32 */
- PERIPH_ID_MEM,
- PERIPH_ID_AHBDMA,
- PERIPH_ID_APBDMA,
- PERIPH_ID_RESERVED35,
- PERIPH_ID_KBC,
- PERIPH_ID_STAT_MON,
- PERIPH_ID_PMC,
- PERIPH_ID_FUSE,
-
- /* 40 */
- PERIPH_ID_KFUSE,
- PERIPH_ID_SBC1,
- PERIPH_ID_SNOR,
- PERIPH_ID_SPI1,
- PERIPH_ID_SBC2,
- PERIPH_ID_XIO,
- PERIPH_ID_SBC3,
- PERIPH_ID_DVC_I2C,
-
- /* 48 */
- PERIPH_ID_DSI,
- PERIPH_ID_TVO,
- PERIPH_ID_MIPI,
- PERIPH_ID_HDMI,
- PERIPH_ID_CSI,
- PERIPH_ID_TVDAC,
- PERIPH_ID_I2C2,
- PERIPH_ID_UART3,
-
- /* 56 */
- PERIPH_ID_RESERVED56,
- PERIPH_ID_EMC,
- PERIPH_ID_USB2,
- PERIPH_ID_USB3,
- PERIPH_ID_MPE,
- PERIPH_ID_VDE,
- PERIPH_ID_BSEA,
- PERIPH_ID_BSEV,
-
- /* Upper word 95:64 */
- PERIPH_ID_SPEEDO,
- PERIPH_ID_UART4,
- PERIPH_ID_UART5,
- PERIPH_ID_I2C3,
- PERIPH_ID_SBC4,
- PERIPH_ID_SDMMC3,
- PERIPH_ID_PCIE,
- PERIPH_ID_OWR,
-
- /* 72 */
- PERIPH_ID_AFI,
- PERIPH_ID_CORESIGHT,
- PERIPH_ID_RESERVED74,
- PERIPH_ID_AVPUCQ,
- PERIPH_ID_RESERVED76,
- PERIPH_ID_RESERVED77,
- PERIPH_ID_RESERVED78,
- PERIPH_ID_RESERVED79,
-
- /* 80 */
- PERIPH_ID_RESERVED80,
- PERIPH_ID_RESERVED81,
- PERIPH_ID_RESERVED82,
- PERIPH_ID_RESERVED83,
- PERIPH_ID_IRAMA,
- PERIPH_ID_IRAMB,
- PERIPH_ID_IRAMC,
- PERIPH_ID_IRAMD,
-
- /* 88 */
- PERIPH_ID_CRAM2,
-
- PERIPH_ID_COUNT,
- PERIPH_ID_NONE = -1,
-};
-
-/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
-#define PERIPH_REG(id) ((id) >> 5)
-
-/* Mask value for a clock (within PERIPH_REG(id)) */
-#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
-
-/* return 1 if a PLL ID is in range, and not a simple PLL */
-#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
- (id) < CLOCK_ID_FIRST_SIMPLE)
-
-/* PLL stabilization delay in usec */
-#define CLOCK_PLL_STABLE_DELAY_US 300
-
-/* return the current oscillator clock frequency */
-enum clock_osc_freq clock_get_osc_freq(void);
-
-/**
- * Start PLL using the provided configuration parameters.
- *
- * @param id clock id
- * @param divm input divider
- * @param divn feedback divider
- * @param divp post divider 2^n
- * @param cpcon charge pump setup control
- * @param lfcon loop filter setup control
- *
- * @returns monotonic time in us that the PLL will be stable
- */
-unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
- u32 divp, u32 cpcon, u32 lfcon);
-
-/**
- * Read low-level parameters of a PLL.
- *
- * @param id clock id to read (note: USB is not supported)
- * @param divm returns input divider
- * @param divn returns feedback divider
- * @param divp returns post divider 2^n
- * @param cpcon returns charge pump setup control
- * @param lfcon returns loop filter setup control
- *
- * @returns 0 if ok, -1 on error (invalid clock id)
- */
-int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
- u32 *divp, u32 *cpcon, u32 *lfcon);
-
-/*
- * Enable a clock
- *
- * @param id clock id
- */
-void clock_enable(enum periph_id clkid);
-
-/*
- * Disable a clock
- *
- * @param id clock id
- */
-void clock_disable(enum periph_id clkid);
-
-/*
- * Set whether a clock is enabled or disabled.
- *
- * @param id clock id
- * @param enable 1 to enable, 0 to disable
- */
-void clock_set_enable(enum periph_id clkid, int enable);
-
-/**
- * Reset a peripheral. This puts it in reset, waits for a delay, then takes
- * it out of reset and waits for th delay again.
- *
- * @param periph_id peripheral to reset
- * @param us_delay time to delay in microseconds
- */
-void reset_periph(enum periph_id periph_id, int us_delay);
-
-/**
- * Put a peripheral into or out of reset.
- *
- * @param periph_id peripheral to reset
- * @param enable 1 to put into reset, 0 to take out of reset
- */
-void reset_set_enable(enum periph_id periph_id, int enable);
-
-
-/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
-enum crc_reset_id {
- /* Things we can hold in reset for each CPU */
- crc_rst_cpu = 1,
- crc_rst_de = 1 << 2, /* What is de? */
- crc_rst_watchdog = 1 << 3,
- crc_rst_debug = 1 << 4,
-};
-
-/**
- * Put parts of the CPU complex into or out of reset.\
- *
- * @param cpu cpu number (0 or 1 on Tegra2)
- * @param which which parts of the complex to affect (OR of crc_reset_id)
- * @param reset 1 to assert reset, 0 to de-assert
- */
-void reset_cmplx_set_enable(int cpu, int which, int reset);
-
-/**
- * Set the source for a peripheral clock. This plus the divisor sets the
- * clock rate. You need to look up the datasheet to see the meaning of the
- * source parameter as it changes for each peripheral.
- *
- * Warning: This function is only for use pre-relocation. Please use
- * clock_start_periph_pll() instead.
- *
- * @param periph_id peripheral to adjust
- * @param source source clock (0, 1, 2 or 3)
- */
-void clock_ll_set_source(enum periph_id periph_id, unsigned source);
-
-/**
- * Set the source and divisor for a peripheral clock. This sets the
- * clock rate. You need to look up the datasheet to see the meaning of the
- * source parameter as it changes for each peripheral.
- *
- * Warning: This function is only for use pre-relocation. Please use
- * clock_start_periph_pll() instead.
- *
- * @param periph_id peripheral to adjust
- * @param source source clock (0, 1, 2 or 3)
- * @param divisor divisor value to use
- */
-void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
- unsigned divisor);
-
-/**
- * Start a peripheral PLL clock at the given rate. This also resets the
- * peripheral.
- *
- * @param periph_id peripheral to start
- * @param parent PLL id of required parent clock
- * @param rate Required clock rate in Hz
- * @return rate selected in Hz, or -1U if something went wrong
- */
-unsigned clock_start_periph_pll(enum periph_id periph_id,
- enum clock_id parent, unsigned rate);
-
-/**
- * Returns the rate of a peripheral clock in Hz. Since the caller almost
- * certainly knows the parent clock (having just set it) we require that
- * this be passed in so we don't need to work it out.
- *
- * @param periph_id peripheral to start
- * @param parent PLL id of parent clock (used to calculate rate, you
- * must know this!)
- * @return clock rate of peripheral in Hz
- */
-unsigned long clock_get_periph_rate(enum periph_id periph_id,
- enum clock_id parent);
-
-/**
- * Adjust peripheral PLL clock to the given rate. This does not reset the
- * peripheral. If a second stage divisor is not available, pass NULL for
- * extra_div. If it is available, then this parameter will return the
- * divisor selected (which will be a power of 2 from 1 to 256).
- *
- * @param periph_id peripheral to start
- * @param parent PLL id of required parent clock
- * @param rate Required clock rate in Hz
- * @param extra_div value for the second-stage divisor (NULL if one is
- not available)
- * @return rate selected in Hz, or -1U if something went wrong
- */
-unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
- enum clock_id parent, unsigned rate, int *extra_div);
-
-/**
- * Returns the clock rate of a specified clock, in Hz.
- *
- * @param parent PLL id of clock to check
- * @return rate of clock in Hz
- */
-unsigned clock_get_rate(enum clock_id clkid);
-
-/**
- * Start up a UART using low-level calls
- *
- * Prior to relocation clock_start_periph_pll() cannot be called. This
- * function provides a way to set up a UART using low-level calls which
- * do not require BSS.
- *
- * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1)
- */
-void clock_ll_start_uart(enum periph_id periph_id);
-
-/**
- * Decode a peripheral ID from a device tree node.
- *
- * This works by looking up the peripheral's 'clocks' node and reading out
- * the second cell, which is the clock number / peripheral ID.
- *
- * @param blob FDT blob to use
- * @param node Node to look at
- * @return peripheral ID, or PERIPH_ID_NONE if none
- */
-enum periph_id clock_decode_periph_id(const void *blob, int node);
-
-/**
- * Checks if the oscillator bypass is enabled (XOBP bit)
- *
- * @return 1 if bypass is enabled, 0 if not
- */
-int clock_get_osc_bypass(void);
-
-/*
- * Checks that clocks are valid and prints a warning if not
- *
- * @return 0 if ok, -1 on error
- */
-int clock_verify(void);
-
-/* Initialize the clocks */
-void clock_init(void);
-
-/* Initialize the PLLs */
-void clock_early_init(void);
-
-#endif
+#endif /* _TEGRA20_CLOCK_H */
/* NAND flags */
FUNCMUX_NDFLASH_ATC = 0,
+ FUNCMUX_NDFLASH_KBC_8_BIT,
};
/**
* MA 02111-1307 USA
*/
-#ifndef _TEGRA_GPIO_H_
-#define _TEGRA_GPIO_H_
+#ifndef _TEGRA20_GPIO_H_
+#define _TEGRA20_GPIO_H_
/*
* The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports,
*/
#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */
#define TEGRA_GPIO_BANKS 7 /* number of banks */
-#define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8)
-#define GPIO_NAME_SIZE 20 /* gpio_request max label len */
+
+#include <asm/arch-tegra/gpio.h>
/* GPIO Controller registers for a single bank */
struct gpio_ctlr_bank {
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
};
-#define GPIO_BANK(x) ((x) >> 5)
-#define GPIO_PORT(x) (((x) >> 3) & 0x3)
-#define GPIO_FULLPORT(x) ((x) >> 3)
-#define GPIO_BIT(x) ((x) & 0x7)
-
enum gpio_pin {
GPIO_PA0 = 0, /* pin 0 */
GPIO_PA1,
GPIO_PBB7, /* pin 223 */
};
-/*
- * Tegra20-specific GPIO API
- */
-
-void gpio_info(void);
-
-#define gpio_status() gpio_info()
-#endif /* TEGRA_GPIO_H_ */
+#endif /* TEGRA20_GPIO_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA20_H_
+#define _TEGRA20_H_
+
+#define NV_PA_SDRAM_BASE 0x00000000
+
+#include <asm/arch-tegra/tegra.h>
+
+#define TEGRA_USB1_BASE 0xC5000000
+#define TEGRA_USB3_BASE 0xC5008000
+
+#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */
+
+#endif /* TEGRA20_H */
/* 0x410 */
uint usb1_legacy_ctrl;
- uint reserved12[3];
+ uint reserved12[4];
- /* 0x420 */
- uint reserved13[56];
+ /* 0x424 */
+ uint ulpi_timing_ctrl_0;
+ uint ulpi_timing_ctrl_1;
+ uint reserved13[53];
/* 0x500 */
uint reserved14[64 * 3];
#define VBUS_SENSE_CTL_AB_SESS_VLD 2
#define VBUS_SENSE_CTL_A_SESS_VLD 3
+/* USB2_IF_ULPI_TIMING_CTRL_0 */
+#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
+#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
+
+/* USB2_IF_ULPI_TIMING_CTRL_1 */
+#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
+#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
+#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
+#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
+#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
+#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
+
/* USBx_IF_USB_SUSP_CTRL_0 */
+#define ULPI_PHY_ENB (1 << 13)
#define UTMIP_PHY_ENB (1 << 12)
#define UTMIP_RESET (1 << 11)
#define USB_PHY_CLK_VALID (1 << 7)
+#define USB_SUSP_CLR (1 << 5)
/* USBx_UTMIP_MISC_CFG1 */
#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
#define PTS_SHIFT 30
#define PTS_MASK (3U << PTS_SHIFT)
-#define PTS_UTMI 0
+#define PTS_UTMI 0
#define PTS_RESERVED 1
-#define PTS_ULP 2
+#define PTS_ULPI 2
#define PTS_ICUSB_SER 3
#define STS (1 << 29)
+#define WKOC (1 << 22)
+#define WKDS (1 << 21)
+#define WKCN (1 << 20)
/* USBx_UTMIP_XCVR_CFG0_0 */
#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
* @param hcor returns start address of EHCI HCOR registers
* @return 0 if ok, -1 on error (generally invalid port number)
*/
-int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor);
+int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor);
/**
* Stop the current port
*
* @return 0 if ok, -1 if no port was active
*/
-int tegrausb_stop_port(void);
+int tegrausb_stop_port(int portnum);
#endif /* _TEGRA_USB_H_ */
u32 insreg08; /* 0xb0 */
};
-int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata);
+/*
+ * FIXME: forward declaration of this structs needed because omap got the
+ * ehci implementation backwards. move out ehci_hcd_x from board files
+ */
+struct ehci_hccr;
+struct ehci_hcor;
+
+int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor);
int omap_ehci_hcd_stop(void);
#endif /* _OMAP_COMMON_EHCI_H_ */
#define MACH_TYPE_UBISYS_P9D_EVP 3493
#define MACH_TYPE_ATDGP318 3494
#define MACH_TYPE_OMAP5_SEVM 3777
+#define MACH_TYPE_ARMADILLO_800EVA 3863
+#define MACH_TYPE_KZM9G 4140
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
# define machine_is_omap5_sevm() (0)
#endif
+#ifdef CONFIG_MACH_ARMADILLO800EVA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ARMADILLO800EVA
+# endif
+# define machine_is_armadillo800eva() (machine_arch_type == MACH_TYPE_ARMADILLO800EVA)
+#else
+# define machine_is_armadillo800eva() (0)
+#endif
+
+#ifdef CONFIG_MACH_KZM9G
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KZM9G
+# endif
+# define machine_is_kzm9g() (machine_arch_type == MACH_TYPE_KZM9G)
+#else
+# define machine_is_kzm9g() (0)
+#endif
+
/*
* These have not yet been registered
*/
#ifdef CONFIG_CLOCKS
set_cpu_clk_info(); /* Setup clock information */
#endif
-#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
-#endif
debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
sp = get_sp();
debug("## Current stack ends at 0x%08lx ", sp);
- /* adjust sp by 1K to be safe */
- sp -= 1024;
+ /* adjust sp by 4K to be safe */
+ sp -= 4096;
lmb_reserve(lmb, sp,
gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp);
}
fixup_memory_node(*of_flat_tree);
fdt_fixup_ethernet(*of_flat_tree);
fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1);
+#ifdef CONFIG_OF_BOARD_SETUP
+ ft_board_setup(*of_flat_tree, gd->bd);
+#endif
return 0;
}
void do_data_abort (struct pt_regs *pt_regs)
{
- printf ("data abort\n");
+ printf ("data abort\n\n MAYBE you should read doc/README.arm-unaligned-accesses\n\n");
show_regs (pt_regs);
bad_mode ();
}
}
#ifdef CONFIG_UART_CONSOLE_IS_JTAG
+#include <serial.h>
/* Since the JTAG is always available (at power on), allow it to fake a UART */
-void serial_set_baud(uint32_t baud) {}
-void serial_setbrg(void) {}
-int serial_init(void) { return 0; }
-void serial_putc(const char c) __attribute__((alias("jtag_putc")));
-void serial_puts(const char *s) __attribute__((alias("jtag_puts")));
-int serial_tstc(void) __attribute__((alias("jtag_tstc")));
-int serial_getc(void) __attribute__((alias("jtag_getc")));
+void jtag_serial_setbrg(void)
+{
+}
+
+int jtag_serial_init(void)
+{
+ return 0;
+}
+
+static struct serial_device serial_jtag_drv = {
+ .name = "jtag",
+ .start = jtag_serial_init,
+ .stop = NULL,
+ .setbrg = jtag_serial_setbrg,
+ .putc = jtag_putc,
+ .puts = jtag_puts,
+ .tstc = jtag_tstc,
+ .getc = jtag_getc,
+};
+
+void bfin_jtag_initialize(void)
+{
+ serial_register(&serial_jtag_drv);
+}
+
+struct serial_device *default_serial_console(void)
+{
+ return &serial_jtag_drv;
+}
#endif
\
struct serial_device bfin_serial##n##_device = { \
.name = "bfin_uart"#n, \
- .init = uart##n##_init, \
- .uninit = uart##n##_uninit, \
+ .start = uart##n##_init, \
+ .stop = uart##n##_uninit, \
.setbrg = uart##n##_setbrg, \
.getc = uart##n##_getc, \
.tstc = uart##n##_tstc, \
#endif
}
-void serial_register_bfin_uart(void)
+void bfin_serial_initialize(void)
{
#ifdef UART0_DLL
serial_register(&bfin_serial0_device);
#define __ASM_BLACKFIN_CONFIG_PRE_H__
/* Misc helper functions */
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
/* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE.
gd->bd = bd;
bd->bi_r_version = version_string;
- bd->bi_cpu = MK_STR(CONFIG_BFIN_CPU);
+ bd->bi_cpu = __stringify(CONFIG_BFIN_CPU);
bd->bi_board_name = BFIN_BOARD_NAME;
bd->bi_vco = get_vco();
bd->bi_cclk = get_cclk();
init_baudrate();
serial_early_puts("Serial init\n");
serial_init();
-#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
-#endif
serial_early_puts("Console init flash\n");
console_init_f();
serial_early_puts("End of early debugging\n");
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
-#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
-#endif
debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
*/
mem_malloc_init (CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
-#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
-#endif
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
WATCHDOG_RESET ();
#include <config.h>
#include <common.h>
#include <asm/au1x00.h>
+#include <serial.h>
+#include <linux/compiler.h>
/******************************************************************************
*
* RETURNS: N/A
*/
-int serial_init (void)
+static int au1x00_serial_init(void)
{
volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR);
volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE);
}
-void serial_setbrg (void)
+static void au1x00_serial_setbrg(void)
{
volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
*uart_lcr = UART_LCR_WLEN8;
}
-void serial_putc (const char c)
+static void au1x00_serial_putc(const char c)
{
volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX);
- if (c == '\n') serial_putc ('\r');
+ if (c == '\n')
+ au1x00_serial_putc('\r');
/* Wait for fifo to shift out some bytes */
while((*uart_lsr&UART_LSR_THRE)==0);
*uart_tx = (u32)c;
}
-void serial_puts (const char *s)
+static void au1x00_serial_puts(const char *s)
{
while (*s)
- {
- serial_putc (*s++);
- }
+ serial_putc(*s++);
}
-int serial_getc (void)
+static int au1x00_serial_getc(void)
{
volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
char c;
return c;
}
-int serial_tstc (void)
+static int au1x00_serial_tstc(void)
{
volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
}
return 0;
}
+
+static struct serial_device au1x00_serial_drv = {
+ .name = "au1x00_serial",
+ .start = au1x00_serial_init,
+ .stop = NULL,
+ .setbrg = au1x00_serial_setbrg,
+ .putc = au1x00_serial_putc,
+ .puts = au1x00_serial_puts,
+ .getc = au1x00_serial_getc,
+ .tstc = au1x00_serial_tstc,
+};
+
+void au1x00_serial_initialize(void)
+{
+ serial_register(&au1x00_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &au1x00_serial_drv;
+}
*/
static char ohci_inited = 0;
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
u32 pin_func;
u32 sys_freqctrl, sys_clksrc;
return -1;
}
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
/* this gets called really early - before the controller has */
/* even been initialized! */
#include <config.h>
#include <common.h>
#include <asm/inca-ip.h>
+#include <serial.h>
+#include <linux/compiler.h>
#include "asc_serial.h"
* RETURNS: N/A
*/
-int serial_init (void)
+static int asc_serial_init(void)
{
/* we have to set PMU.EN13 bit to enable an ASC device*/
INCAASC_PMU_ENABLE(13);
return 0;
}
-void serial_setbrg (void)
+static void asc_serial_setbrg(void)
{
ulong uiReloadValue, fdv;
ulong f_ASC;
return 0;
}
-void serial_putc (const char c)
+static void asc_serial_putc(const char c)
{
uint txFl = 0;
}
}
-void serial_puts (const char *s)
+static void asc_serial_puts(const char *s)
{
while (*s)
{
}
}
-int serial_getc (void)
+static int asc_serial_getc(void)
{
ulong symbol_mask;
char c;
return c;
}
-int serial_tstc (void)
+static int asc_serial_tstc(void)
{
int res = 1;
return res;
}
+
+static struct serial_device asc_serial_drv = {
+ .name = "asc_serial",
+ .start = asc_serial_init,
+ .stop = NULL,
+ .setbrg = asc_serial_setbrg,
+ .putc = asc_serial_putc,
+ .puts = asc_serial_puts,
+ .getc = asc_serial_getc,
+ .tstc = asc_serial_tstc,
+};
+
+void asc_serial_initialize(void)
+{
+ serial_register(&asc_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &asc_serial_drv;
+}
#include <common.h>
#include <asm/io.h>
#include <asm/jz4740.h>
+#include <serial.h>
+#include <linux/compiler.h>
/*
* serial_init - initialize a channel
*/
struct jz4740_uart *uart = (struct jz4740_uart *)CONFIG_SYS_UART_BASE;
-int serial_init(void)
+static int jz_serial_init(void)
{
/* Disable port interrupts while changing hardware */
writeb(0, &uart->dlhr_ier);
return 0;
}
-void serial_setbrg(void)
+static void jz_serial_setbrg(void)
{
u32 baud_div, tmp;
writeb(tmp, &uart->lcr);
}
-int serial_tstc(void)
+static int jz_serial_tstc(void)
{
if (readb(&uart->lsr) & UART_LSR_DR)
return 1;
return 0;
}
-void serial_putc(const char c)
+static void jz_serial_putc(const char c)
{
if (c == '\n')
serial_putc('\r');
writeb((u8)c, &uart->rbr_thr_dllr);
}
-int serial_getc(void)
+static int jz_serial_getc(void)
{
while (!serial_tstc())
;
return readb(&uart->rbr_thr_dllr);
}
-void serial_puts(const char *s)
+static void jz_serial_puts(const char *s)
{
while (*s)
serial_putc(*s++);
}
+
+static struct serial_device jz_serial_drv = {
+ .name = "jz_serial",
+ .start = jz_serial_init,
+ .stop = NULL,
+ .setbrg = jz_serial_setbrg,
+ .putc = jz_serial_putc,
+ .puts = jz_serial_puts,
+ .getc = jz_serial_getc,
+ .tstc = jz_serial_tstc,
+};
+
+void jz_serial_initialize(void)
+{
+ serial_register(&jz_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &jz_serial_drv;
+}
(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
-#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
-#endif
debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
#define PLATFORM_FFS
#include <asm/bitops/ffs.h>
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
#endif /* __ASM_GENERIC_BITOPS_H */
timestamp = t;
}
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
+
void __udelay(ulong usec)
{
ulong elapsed = 0;
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_PSC_CONSOLE) || defined(CONFIG_SERIAL_MULTI)
+#if defined(CONFIG_PSC_CONSOLE)
static void fifo_init (volatile psc512x_t *psc)
{
out_be32(&psc->rfintmask, 0);
out_be32(&psc->tfintmask, 0);
-#if defined(CONFIG_SERIAL_MULTI)
switch (((u32)psc & 0xf00) >> 8) {
case 0:
tfsize = FIFOC_PSC0_TX_SIZE | (FIFOC_PSC0_TX_ADDR << 16);
default:
return;
}
-#else
- tfsize = CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16);
- rfsize = CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16);
-#endif
+
out_be32(&psc->tfsize, tfsize);
out_be32(&psc->rfsize, rfsize);
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
-#if defined(CONFIG_SERIAL_MULTI)
u32 reg;
reg = in_be32(&im->clk.sccr[0]);
out_be32(&im->clk.sccr[0], reg | CLOCK_SCCR1_PSC_EN(idx));
-#endif
fifo_init (psc);
return (in_8(&psc->ip) & 0x1) ? 0 : 1;
}
-#endif /* CONFIG_PSC_CONSOLE || CONFIG_SERIAL_MULTI */
-
-#if defined(CONFIG_SERIAL_MULTI)
+#endif /* CONFIG_PSC_CONSOLE */
#define DECLARE_PSC_SERIAL_FUNCTIONS(port) \
int serial##port##_init(void) \
serial_puts_dev(port, s); \
}
-#define INIT_PSC_SERIAL_STRUCTURE(port, name) { \
- name, \
- serial##port##_init, \
- serial##port##_uninit, \
- serial##port##_setbrg, \
- serial##port##_getc, \
- serial##port##_tstc, \
- serial##port##_putc, \
- serial##port##_puts, \
+#define INIT_PSC_SERIAL_STRUCTURE(port, __name) { \
+ .name = __name, \
+ .start = serial##port##_init, \
+ .stop = serial##port##_uninit, \
+ .setbrg = serial##port##_setbrg, \
+ .getc = serial##port##_getc, \
+ .tstc = serial##port##_tstc, \
+ .putc = serial##port##_putc, \
+ .puts = serial##port##_puts, \
}
#if defined(CONFIG_SYS_PSC1)
#endif
}
-#else
-
-void serial_setbrg(void)
-{
- serial_setbrg_dev(CONFIG_PSC_CONSOLE);
-}
-
-int serial_init(void)
+void mpc512x_serial_initialize(void)
{
- return serial_init_dev(CONFIG_PSC_CONSOLE);
-}
-
-void serial_putc(const char c)
-{
- serial_putc_dev(CONFIG_PSC_CONSOLE, c);
-}
-
-void serial_putc_raw(const char c)
-{
- serial_putc_raw_dev(CONFIG_PSC_CONSOLE, c);
-}
-
-void serial_puts(const char *s)
-{
- serial_puts_dev(CONFIG_PSC_CONSOLE, s);
-}
-
-int serial_getc(void)
-{
- return serial_getc_dev(CONFIG_PSC_CONSOLE);
-}
-
-int serial_tstc(void)
-{
- return serial_tstc_dev(CONFIG_PSC_CONSOLE);
-}
-
-void serial_setrts(int s)
-{
- return serial_setrts_dev(CONFIG_PSC_CONSOLE, s);
-}
-
-int serial_getcts(void)
-{
- return serial_getcts_dev(CONFIG_PSC_CONSOLE);
+#if defined(CONFIG_SYS_PSC1)
+ serial_register(&serial1_device);
+#endif
+#if defined(CONFIG_SYS_PSC3)
+ serial_register(&serial3_device);
+#endif
+#if defined(CONFIG_SYS_PSC4)
+ serial_register(&serial4_device);
+#endif
+#if defined(CONFIG_SYS_PSC6)
+ serial_register(&serial6_device);
+#endif
}
-#endif /* CONFIG_PSC_CONSOLE */
-#if defined(CONFIG_SERIAL_MULTI)
#include <stdio_dev.h>
/*
* Routines for communication with serial devices over PSC
return cnt;
}
-#endif /* CONFIG_SERIAL_MULTI */
#include <watchdog.h>
#include <command.h>
#include <mpc5xx.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
/*
- * Local function prototypes
+ * Local functions
*/
-static int ready_to_send(void);
+static int ready_to_send(void)
+{
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ volatile short status;
+
+ do {
+#if defined(CONFIG_5xx_CONS_SCI1)
+ status = immr->im_qsmcm.qsmcm_sc1sr;
+#else
+ status = immr->im_qsmcm.qsmcm_sc2sr;
+#endif
+
+#if defined(CONFIG_WATCHDOG)
+ reset_5xx_watchdog (immr);
+#endif
+ } while ((status & SCI_TDRE) == 0);
+ return 1;
+
+}
/*
* Minimal global serial functions needed to use one of the SCI modules.
*/
-int serial_init (void)
+static int mpc5xx_serial_init(void)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
return 0;
}
-void serial_putc(const char c)
+static void mpc5xx_serial_putc(const char c)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
}
}
-int serial_getc(void)
+static int mpc5xx_serial_getc(void)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile short status;
return tmp;
}
-int serial_tstc()
+static int mpc5xx_serial_tstc(void)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
short status;
return (status & SCI_RDRF);
}
-void serial_setbrg (void)
+static void mpc5xx_serial_setbrg(void)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
short scxbr;
#endif
}
-void serial_puts (const char *s)
+static void mpc5xx_serial_puts(const char *s)
{
while (*s) {
serial_putc(*s);
}
}
-int ready_to_send(void)
+static struct serial_device mpc5xx_serial_drv = {
+ .name = "mpc5xx_serial",
+ .start = mpc5xx_serial_init,
+ .stop = NULL,
+ .setbrg = mpc5xx_serial_setbrg,
+ .putc = mpc5xx_serial_putc,
+ .puts = mpc5xx_serial_puts,
+ .getc = mpc5xx_serial_getc,
+ .tstc = mpc5xx_serial_tstc,
+};
+
+void mpc5xx_serial_initialize(void)
{
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- volatile short status;
-
- do {
-#if defined(CONFIG_5xx_CONS_SCI1)
- status = immr->im_qsmcm.qsmcm_sc1sr;
-#else
- status = immr->im_qsmcm.qsmcm_sc2sr;
-#endif
-
-#if defined(CONFIG_WATCHDOG)
- reset_5xx_watchdog (immr);
-#endif
- } while ((status & SCI_TDRE) == 0);
- return 1;
+ serial_register(&mpc5xx_serial_drv);
+}
+__weak struct serial_device *default_serial_console(void)
+{
+ return &mpc5xx_serial_drv;
}
* Linux/PPC sources (m8260_tty.c had no copyright info in it).
*
* Martin Krause, 8 Jun 2006
- * Added CONFIG_SERIAL_MULTI support
+ * Added SERIAL_MULTI support
*/
/*
#include <common.h>
#include <linux/compiler.h>
#include <mpc5xxx.h>
-
-#if defined (CONFIG_SERIAL_MULTI)
#include <serial.h>
-#endif
DECLARE_GLOBAL_DATA_PTR;
#error CONFIG_PSC_CONSOLE must be in 1 ... 6
#endif
-#if defined(CONFIG_SERIAL_MULTI) && !defined(CONFIG_PSC_CONSOLE2)
-#error you must define CONFIG_PSC_CONSOLE2 if CONFIG_SERIAL_MULTI is set
-#endif
+#if defined(CONFIG_PSC_CONSOLE2)
-#if defined(CONFIG_SERIAL_MULTI)
#if CONFIG_PSC_CONSOLE2 == 1
#define PSC_BASE2 MPC5XXX_PSC1
#elif CONFIG_PSC_CONSOLE2 == 2
#else
#error CONFIG_PSC_CONSOLE2 must be in 1 ... 6
#endif
-#endif /* CONFIG_SERIAL_MULTI */
-#if defined(CONFIG_SERIAL_MULTI)
-int serial_init_dev (unsigned long dev_base)
-#else
-int serial_init (void)
#endif
+
+int serial_init_dev (unsigned long dev_base)
{
-#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-#else
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#endif
unsigned long baseclk;
int div;
return (0);
}
-#if defined(CONFIG_SERIAL_MULTI)
void serial_putc_dev (unsigned long dev_base, const char c)
-#else
-void serial_putc(const char c)
-#endif
{
-#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-#else
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#endif
if (c == '\n')
-#if defined(CONFIG_SERIAL_MULTI)
serial_putc_dev (dev_base, '\r');
-#else
- serial_putc('\r');
-#endif
/* Wait for last character to go. */
while (!(psc->psc_status & PSC_SR_TXEMP))
psc->psc_buffer_8 = c;
}
-#if defined(CONFIG_SERIAL_MULTI)
void serial_putc_raw_dev(unsigned long dev_base, const char c)
-#else
-void serial_putc_raw(const char c)
-#endif
{
-#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-#else
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#endif
/* Wait for last character to go. */
while (!(psc->psc_status & PSC_SR_TXEMP))
;
}
-#if defined(CONFIG_SERIAL_MULTI)
void serial_puts_dev (unsigned long dev_base, const char *s)
-#else
-void serial_puts (const char *s)
-#endif
{
while (*s) {
-#if defined(CONFIG_SERIAL_MULTI)
serial_putc_dev (dev_base, *s++);
-#else
- serial_putc (*s++);
-#endif
}
}
-#if defined(CONFIG_SERIAL_MULTI)
int serial_getc_dev (unsigned long dev_base)
-#else
-int serial_getc(void)
-#endif
{
-#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-#else
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#endif
/* Wait for a character to arrive. */
while (!(psc->psc_status & PSC_SR_RXRDY))
return psc->psc_buffer_8;
}
-#if defined(CONFIG_SERIAL_MULTI)
int serial_tstc_dev (unsigned long dev_base)
-#else
-int serial_tstc(void)
-#endif
{
-#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-#else
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#endif
return (psc->psc_status & PSC_SR_RXRDY);
}
-#if defined(CONFIG_SERIAL_MULTI)
void serial_setbrg_dev (unsigned long dev_base)
-#else
-void serial_setbrg(void)
-#endif
{
-#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-#else
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#endif
unsigned long baseclk, div;
baseclk = (gd->ipb_clk + 16) / 32;
psc->ctlr = div & 0xff;
}
-#if defined(CONFIG_SERIAL_MULTI)
void serial_setrts_dev (unsigned long dev_base, int s)
-#else
-void serial_setrts(int s)
-#endif
{
-#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-#else
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#endif
if (s) {
/* Assert RTS (become LOW) */
}
}
-#if defined(CONFIG_SERIAL_MULTI)
int serial_getcts_dev (unsigned long dev_base)
-#else
-int serial_getcts(void)
-#endif
{
-#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-#else
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#endif
return (psc->ip & 0x1) ? 0 : 1;
}
-#if defined(CONFIG_SERIAL_MULTI)
int serial0_init(void)
{
return (serial_init_dev(PSC_BASE));
}
-int serial1_init(void)
-{
- return (serial_init_dev(PSC_BASE2));
-}
void serial0_setbrg (void)
{
serial_setbrg_dev(PSC_BASE);
}
-void serial1_setbrg (void)
-{
- serial_setbrg_dev(PSC_BASE2);
-}
void serial0_putc(const char c)
{
serial_putc_dev(PSC_BASE,c);
}
-void serial1_putc(const char c)
-{
- serial_putc_dev(PSC_BASE2, c);
-}
void serial0_puts(const char *s)
{
serial_puts_dev(PSC_BASE, s);
}
-void serial1_puts(const char *s)
-{
- serial_puts_dev(PSC_BASE2, s);
-}
-
int serial0_getc(void)
{
return(serial_getc_dev(PSC_BASE));
}
-int serial1_getc(void)
-{
- return(serial_getc_dev(PSC_BASE2));
-}
int serial0_tstc(void)
{
return (serial_tstc_dev(PSC_BASE));
}
-int serial1_tstc(void)
-{
- return (serial_tstc_dev(PSC_BASE2));
-}
-
struct serial_device serial0_device =
{
- "serial0",
- serial0_init,
- NULL,
- serial0_setbrg,
- serial0_getc,
- serial0_tstc,
- serial0_putc,
- serial0_puts,
+ .name = "serial0",
+ .start = serial0_init,
+ .stop = NULL,
+ .setbrg = serial0_setbrg,
+ .getc = serial0_getc,
+ .tstc = serial0_tstc,
+ .putc = serial0_putc,
+ .puts = serial0_puts,
};
__weak struct serial_device *default_serial_console(void)
return &serial0_device;
}
+#ifdef CONFIG_PSC_CONSOLE2
+int serial1_init(void)
+{
+ return serial_init_dev(PSC_BASE2);
+}
+
+void serial1_setbrg(void)
+{
+ serial_setbrg_dev(PSC_BASE2);
+}
+
+void serial1_putc(const char c)
+{
+ serial_putc_dev(PSC_BASE2, c);
+}
+
+void serial1_puts(const char *s)
+{
+ serial_puts_dev(PSC_BASE2, s);
+}
+
+int serial1_getc(void)
+{
+ return serial_getc_dev(PSC_BASE2);
+}
+
+int serial1_tstc(void)
+{
+ return serial_tstc_dev(PSC_BASE2);
+}
+
struct serial_device serial1_device =
{
- "serial1",
- serial1_init,
- NULL,
- serial1_setbrg,
- serial1_getc,
- serial1_tstc,
- serial1_putc,
- serial1_puts,
+ .name = "serial1",
+ .start = serial1_init,
+ .stop = NULL,
+ .setbrg = serial1_setbrg,
+ .getc = serial1_getc,
+ .tstc = serial1_tstc,
+ .putc = serial1_putc,
+ .puts = serial1_puts,
};
-#endif /* CONFIG_SERIAL_MULTI */
+#endif /* CONFIG_PSC_CONSOLE2 */
#endif /* CONFIG_PSC_CONSOLE */
*/
static char ohci_inited = 0;
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
/* Set the USB Clock */
return 0;
}
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
/* this gets called really early - before the controller has */
/* even been initialized! */
#include <common.h>
#include <mpc8220.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
#define PSC_BASE MMAP_PSC1
#if defined(CONFIG_PSC_CONSOLE)
-int serial_init (void)
+static int mpc8220_serial_init(void)
{
volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
u32 counter;
return (0);
}
-void serial_putc (const char c)
+static void mpc8220_serial_putc(const char c)
{
volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
psc->xmitbuf[0] = c;
}
-void serial_puts (const char *s)
+static void mpc8220_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
-int serial_getc (void)
+static int mpc8220_serial_getc(void)
{
volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
return psc->xmitbuf[2];
}
-int serial_tstc (void)
+static int mpc8220_serial_tstc(void)
{
volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
return (psc->sr_csr & PSC_SR_RXRDY);
}
-void serial_setbrg (void)
+static void mpc8220_serial_setbrg(void)
{
volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
u32 counter;
psc->cr = PSC_CR_RX_ENABLE | PSC_CR_TX_ENABLE;
}
+
+static struct serial_device mpc8220_serial_drv = {
+ .name = "mpc8220_serial",
+ .start = mpc8220_serial_init,
+ .stop = NULL,
+ .setbrg = mpc8220_serial_setbrg,
+ .putc = mpc8220_serial_putc,
+ .puts = mpc8220_serial_puts,
+ .getc = mpc8220_serial_getc,
+ .tstc = mpc8220_serial_tstc,
+};
+
+void mpc8220_serial_initialize(void)
+{
+ serial_register(&mpc8220_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &mpc8220_serial_drv;
+}
#endif /* CONFIG_PSC_CONSOLE */
#include <common.h>
#include <mpc8260.h>
#include <asm/cpm_8260.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
-int serial_init (void)
+static int mpc8260_scc_serial_init(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile scc_t *sp;
return (0);
}
-void
-serial_setbrg (void)
+static void mpc8260_scc_serial_setbrg(void)
{
#if defined(CONFIG_CONS_USE_EXTC)
m8260_cpm_extcbrg(SCC_INDEX, gd->baudrate,
#endif
}
-void
-serial_putc(const char c)
+static void mpc8260_scc_serial_putc(const char c)
{
volatile scc_uart_t *up;
volatile cbd_t *tbdf;
tbdf->cbd_sc |= BD_SC_READY;
}
-void
-serial_puts (const char *s)
+static void mpc8260_scc_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
-int
-serial_getc(void)
+static int mpc8260_scc_serial_getc(void)
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
return (c);
}
-int
-serial_tstc()
+static int mpc8260_scc_serial_tstc(void)
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
}
+static struct serial_device mpc8260_scc_serial_drv = {
+ .name = "mpc8260_scc_uart",
+ .start = mpc8260_scc_serial_init,
+ .stop = NULL,
+ .setbrg = mpc8260_scc_serial_setbrg,
+ .putc = mpc8260_scc_serial_putc,
+ .puts = mpc8260_scc_serial_puts,
+ .getc = mpc8260_scc_serial_getc,
+ .tstc = mpc8260_scc_serial_tstc,
+};
+
+void mpc8260_scc_serial_initialize(void)
+{
+ serial_register(&mpc8260_scc_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &mpc8260_scc_serial_drv;
+}
#endif /* CONFIG_CONS_ON_SCC */
#if defined(CONFIG_KGDB_ON_SCC)
#include <common.h>
#include <mpc8260.h>
#include <asm/cpm_8260.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
3, /* BRG1 for SCC4 */
};
-int serial_init (void)
+static int mpc8260_smc_serial_init(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile smc_t *sp;
return (0);
}
-void
-serial_setbrg (void)
+static void mpc8260_smc_serial_setbrg(void)
{
#if defined(CONFIG_CONS_USE_EXTC)
m8260_cpm_extcbrg(brg_map[SMC_INDEX], gd->baudrate,
#endif
}
-void
-serial_putc(const char c)
+static void mpc8260_smc_serial_putc(const char c)
{
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
rtx->txbd.cbd_sc |= BD_SC_READY;
}
-void
-serial_puts (const char *s)
+static void mpc8260_smc_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
-int
-serial_getc(void)
+static int mpc8260_smc_serial_getc(void)
{
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
return(c);
}
-int
-serial_tstc()
+static int mpc8260_smc_serial_tstc(void)
{
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
}
+static struct serial_device mpc8260_smc_serial_drv = {
+ .name = "mpc8260_smc_uart",
+ .start = mpc8260_smc_serial_init,
+ .stop = NULL,
+ .setbrg = mpc8260_smc_serial_setbrg,
+ .putc = mpc8260_smc_serial_putc,
+ .puts = mpc8260_smc_serial_puts,
+ .getc = mpc8260_smc_serial_getc,
+ .tstc = mpc8260_smc_serial_tstc,
+};
+
+void mpc8260_smc_serial_initialize(void)
+{
+ serial_register(&mpc8260_smc_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &mpc8260_smc_serial_drv;
+}
#endif /* CONFIG_CONS_ON_SMC */
#if defined(CONFIG_KGDB_ON_SMC)
#include <common.h>
#include <asm/cpm_85xx.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
-int serial_init (void)
+static int mpc85xx_serial_init(void)
{
volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
volatile ccsr_cpm_scc_t *sp;
return (0);
}
-void
-serial_setbrg (void)
+static void mpc85xx_serial_setbrg(void)
{
#if defined(CONFIG_CONS_USE_EXTC)
m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate,
#endif
}
-void
-serial_putc(const char c)
+static void mpc85xx_serial_putc(const char c)
{
volatile scc_uart_t *up;
volatile cbd_t *tbdf;
tbdf->cbd_sc |= BD_SC_READY;
}
-void
-serial_puts (const char *s)
+static void mpc85xx_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
-int
-serial_getc(void)
+static int mpc85xx_serial_getc(void)
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
return (c);
}
-int
-serial_tstc()
+static int mpc85xx_serial_tstc(void)
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
}
+static struct serial_device mpc85xx_serial_drv = {
+ .name = "mpc85xx_serial",
+ .start = mpc85xx_serial_init,
+ .stop = NULL,
+ .setbrg = mpc85xx_serial_setbrg,
+ .putc = mpc85xx_serial_putc,
+ .puts = mpc85xx_serial_puts,
+ .getc = mpc85xx_serial_getc,
+ .tstc = mpc85xx_serial_tstc,
+};
+
+void mpc85xx_serial_initialize(void)
+{
+ serial_register(&mpc85xx_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &mpc85xx_serial_drv;
+}
#endif /* CONFIG_CONS_ON_SCC */
struct serial_device serial_smc_device =
{
- "serial_smc",
- smc_init,
- NULL,
- smc_setbrg,
- smc_getc,
- smc_tstc,
- smc_putc,
- smc_puts,
+ .name = "serial_smc",
+ .start = smc_init,
+ .stop = NULL,
+ .setbrg = smc_setbrg,
+ .getc = smc_getc,
+ .tstc = smc_tstc,
+ .putc = smc_putc,
+ .puts = smc_puts,
};
#endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
struct serial_device serial_scc_device =
{
- "serial_scc",
- scc_init,
- NULL,
- scc_setbrg,
- scc_getc,
- scc_tstc,
- scc_putc,
- scc_puts,
+ .name = "serial_scc",
+ .start = scc_init,
+ .stop = NULL,
+ .setbrg = scc_setbrg,
+ .getc = scc_getc,
+ .tstc = scc_tstc,
+ .putc = scc_putc,
+ .puts = scc_puts,
};
#endif /* CONFIG_8xx_CONS_SCCx */
#endif
}
+void mpc8xx_serial_initialize(void)
+{
+#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
+ serial_register(&serial_smc_device);
+#endif
+#if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
+ defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
+ serial_register(&serial_scc_device);
+#endif
+}
+
#ifdef CONFIG_MODEM_SUPPORT
void disable_putc(void)
{
COBJS-$(CONFIG_CMD_ECCTEST) += cmd_ecctest.o
COBJS += fdt.o
COBJS += interrupts.o
-COBJS += iop480_uart.o
COBJS-$(CONFIG_CMD_REGINFO) += reginfo.o
COBJS += sdram.o
COBJS += speed.o
#endif
#endif /* CONFIG_PCI */
-#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
+#if defined(CONFIG_PCI) && \
!defined(CONFIG_405) && !defined(CONFIG_405EX)
int pci_arbiter_enabled(void)
{
u32 reg;
#endif
-#if !defined(CONFIG_IOP480)
char addstr[64] = "";
sys_info_t sys_info;
int cpu_num;
printf (" 16 kB I-Cache %d kB D-Cache",
((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
#endif
-#endif /* !defined(CONFIG_IOP480) */
-
-#if defined(CONFIG_IOP480)
- printf ("PLX IOP480 (PVR=%08x)", pvr);
- printf (" at %s MHz:", strmhz(buf, clock));
- printf (" %u kB I-Cache", 4);
- printf (" %u kB D-Cache", 2);
-#endif
#endif /* !defined(CONFIG_405) */
*/
unsigned long get_tbclk (void)
{
-#if !defined(CONFIG_IOP480)
sys_info_t sys_info;
get_sys_info(&sys_info);
return (sys_info.freqProcessor);
-#else
- return (66000000);
-#endif
-
}
+++ /dev/null
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <commproc.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <watchdog.h>
-
-#ifdef CONFIG_SERIAL_MULTI
-#include <serial.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_IOP480
-
-#define SPU_BASE 0x40000000
-
-#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
-#define spu_LineStat_w 0x04 /* Line Status Register (Set) */
-#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
-#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
-#define spu_BRateDivh 0x10 /* Baud rate divisor high */
-#define spu_BRateDivl 0x14 /* Baud rate divisor low */
-#define spu_CtlReg 0x18 /* Control Register */
-#define spu_RxCmd 0x1c /* Rx Command Register */
-#define spu_TxCmd 0x20 /* Tx Command Register */
-#define spu_RxBuff 0x24 /* Rx data buffer */
-#define spu_TxBuff 0x24 /* Tx data buffer */
-
-/*-----------------------------------------------------------------------------+
- | Line Status Register.
- +-----------------------------------------------------------------------------*/
-#define asyncLSRport1 0x40000000
-#define asyncLSRport1set 0x40000004
-#define asyncLSRDataReady 0x80
-#define asyncLSRFramingError 0x40
-#define asyncLSROverrunError 0x20
-#define asyncLSRParityError 0x10
-#define asyncLSRBreakInterrupt 0x08
-#define asyncLSRTxHoldEmpty 0x04
-#define asyncLSRTxShiftEmpty 0x02
-
-/*-----------------------------------------------------------------------------+
- | Handshake Status Register.
- +-----------------------------------------------------------------------------*/
-#define asyncHSRport1 0x40000008
-#define asyncHSRport1set 0x4000000c
-#define asyncHSRDsr 0x80
-#define asyncLSRCts 0x40
-
-/*-----------------------------------------------------------------------------+
- | Control Register.
- +-----------------------------------------------------------------------------*/
-#define asyncCRport1 0x40000018
-#define asyncCRNormal 0x00
-#define asyncCRLoopback 0x40
-#define asyncCRAutoEcho 0x80
-#define asyncCRDtr 0x20
-#define asyncCRRts 0x10
-#define asyncCRWordLength7 0x00
-#define asyncCRWordLength8 0x08
-#define asyncCRParityDisable 0x00
-#define asyncCRParityEnable 0x04
-#define asyncCREvenParity 0x00
-#define asyncCROddParity 0x02
-#define asyncCRStopBitsOne 0x00
-#define asyncCRStopBitsTwo 0x01
-#define asyncCRDisableDtrRts 0x00
-
-/*-----------------------------------------------------------------------------+
- | Receiver Command Register.
- +-----------------------------------------------------------------------------*/
-#define asyncRCRport1 0x4000001c
-#define asyncRCRDisable 0x00
-#define asyncRCREnable 0x80
-#define asyncRCRIntDisable 0x00
-#define asyncRCRIntEnabled 0x20
-#define asyncRCRDMACh2 0x40
-#define asyncRCRDMACh3 0x60
-#define asyncRCRErrorInt 0x10
-#define asyncRCRPauseEnable 0x08
-
-/*-----------------------------------------------------------------------------+
- | Transmitter Command Register.
- +-----------------------------------------------------------------------------*/
-#define asyncTCRport1 0x40000020
-#define asyncTCRDisable 0x00
-#define asyncTCREnable 0x80
-#define asyncTCRIntDisable 0x00
-#define asyncTCRIntEnabled 0x20
-#define asyncTCRDMACh2 0x40
-#define asyncTCRDMACh3 0x60
-#define asyncTCRTxEmpty 0x10
-#define asyncTCRErrorInt 0x08
-#define asyncTCRStopPause 0x04
-#define asyncTCRBreakGen 0x02
-
-/*-----------------------------------------------------------------------------+
- | Miscellanies defines.
- +-----------------------------------------------------------------------------*/
-#define asyncTxBufferport1 0x40000024
-#define asyncRxBufferport1 0x40000024
-#define asyncDLABLsbport1 0x40000014
-#define asyncDLABMsbport1 0x40000010
-#define asyncXOFFchar 0x13
-#define asyncXONchar 0x11
-
-/*
- * Minimal serial functions needed to use one of the SMC ports
- * as serial console interface.
- */
-
-int serial_init (void)
-{
- unsigned short br_reg;
-
- br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
-
- /*
- * Init onboard UART
- */
- out_8((u8 *)SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
- out_8((u8 *)SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
- out_8((u8 *)SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
- out_8((u8 *)SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
- out_8((u8 *)SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
- out_8((u8 *)SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
- out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
- in_8((u8 *)SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
-
- return (0);
-}
-
-void serial_setbrg (void)
-{
- unsigned short br_reg;
-
- br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
-
- out_8((u8 *)SPU_BASE + spu_BRateDivl,
- (br_reg & 0x00ff)); /* Set baud rate divisor... */
- out_8((u8 *)SPU_BASE + spu_BRateDivh,
- ((br_reg & 0xff00) >> 8)); /* ... */
-}
-
-void serial_putc (const char c)
-{
- if (c == '\n')
- serial_putc ('\r');
-
- /* load status from handshake register */
- if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00)
- out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
-
- out_8((u8 *)SPU_BASE + spu_TxBuff, c); /* Put char */
-
- while ((in_8((u8 *)SPU_BASE + spu_LineStat_rc) & 04) != 04) {
- if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00)
- out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
- }
-}
-
-void serial_puts (const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
-int serial_getc ()
-{
- unsigned char status = 0;
-
- while (1) {
- status = in_8((u8 *)asyncLSRport1);
- if ((status & asyncLSRDataReady) != 0x0) {
- break;
- }
- if ((status & ( asyncLSRFramingError |
- asyncLSROverrunError |
- asyncLSRParityError |
- asyncLSRBreakInterrupt )) != 0) {
- (void) out_8((u8 *)asyncLSRport1,
- asyncLSRFramingError |
- asyncLSROverrunError |
- asyncLSRParityError |
- asyncLSRBreakInterrupt );
- }
- }
- return (0x000000ff & (int) in_8((u8 *)asyncRxBufferport1));
-}
-
-int serial_tstc ()
-{
- unsigned char status;
-
- status = in_8((u8 *)asyncLSRport1);
- if ((status & asyncLSRDataReady) != 0x0) {
- return (1);
- }
- if ((status & ( asyncLSRFramingError |
- asyncLSROverrunError |
- asyncLSRParityError |
- asyncLSRBreakInterrupt )) != 0) {
- (void) out_8((u8 *)asyncLSRport1,
- asyncLSRFramingError |
- asyncLSROverrunError |
- asyncLSRParityError |
- asyncLSRBreakInterrupt);
- }
- return 0;
-}
-
-#endif /* CONFIG_IOP480 */
extern void get_sys_info (sys_info_t * sysInfo);
extern ulong get_PCI_freq (void);
-#elif defined(CONFIG_AP1000)
-void get_sys_info (sys_info_t * sysInfo)
-{
- sysInfo->freqProcessor = 240 * 1000 * 1000;
- sysInfo->freqPLB = 80 * 1000 * 1000;
- sysInfo->freqPCI = 33 * 1000 * 1000;
-}
-
#elif defined(CONFIG_405)
void get_sys_info (sys_info_t * sysInfo)
int get_clocks (void)
{
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
- defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
- defined(CONFIG_405EX) || defined(CONFIG_405) || \
- defined(CONFIG_440)
sys_info_t sys_info;
get_sys_info (&sys_info);
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqPLB;
-#endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
-
-#ifdef CONFIG_IOP480
- gd->cpu_clk = 66000000;
- gd->bus_clk = 66000000;
-#endif
return (0);
}
get_sys_info (&sys_info);
val = sys_info.freqPLB;
-
-#elif defined(CONFIG_IOP480)
-
- val = 66;
-
#else
# error get_bus_freq() not implemented
#endif
return val;
}
-#if !defined(CONFIG_IOP480)
ulong get_OPB_freq (void)
{
PPC4xx_SYS_INFO sys_info;
return sys_info.freqOPB;
}
-#endif
#endif /* CONFIG_440 */
/*****************************************************************************/
-#ifdef CONFIG_IOP480
- /*----------------------------------------------------------------------- */
- /* Set up some machine state registers. */
- /*----------------------------------------------------------------------- */
- addi r0,r0,0x0000 /* initialize r0 to zero */
- mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */
- mttcr r0 /* timer control register */
- mtexier r0 /* disable all interrupts */
- addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
- ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
- mtdbsr r4 /* clear/reset the dbsr */
- mtexisr r4 /* clear all pending interrupts */
- addis r4,r0,0x8000
- mtexier r4 /* enable critical exceptions */
- addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
- ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
- mtiocr r4 /* since bit not used) & DRC to latch */
- /* data bus on rising edge of CAS */
- /*----------------------------------------------------------------------- */
- /* Clear XER. */
- /*----------------------------------------------------------------------- */
- mtxer r0
- /*----------------------------------------------------------------------- */
- /* Invalidate i-cache and d-cache TAG arrays. */
- /*----------------------------------------------------------------------- */
- addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
- addi r4,0,1024 /* 1/4 of I-cache */
-..cloop:
- iccci 0,r3
- iccci r4,r3
- dccci 0,r3
- addic. r3,r3,-16 /* move back one cache line */
- bne ..cloop /* loop back to do rest until r3 = 0 */
-
- /* */
- /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
- /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
- /* */
-
- /* first copy IOP480 register base address into r3 */
- addis r3,0,0x5000 /* IOP480 register base address hi */
-/* ori r3,r3,0x0000 / IOP480 register base address lo */
-
-#ifdef CONFIG_ADCIOP
- /* use r4 as the working variable */
- /* turn on CS3 (LOCCTL.7) */
- lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
- andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
- stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
-#endif
-
-#ifdef CONFIG_DASA_SIM
- /* use r4 as the working variable */
- /* turn on MA17 (LOCCTL.7) */
- lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
- ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
- stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
-#endif
-
- /* turn on MA16..13 (LCS0BRD.12 = 0) */
- lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
- andi. r4,r4,0xefff /* make bit 12 = 0 */
- stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
-
- /* make sure above stores all comlete before going on */
- sync
-
- /* last thing, set local init status done bit (DEVINIT.31) */
- lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
- oris r4,r4,0x8000 /* make bit 31 = 1 */
- stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
-
- /* clear all pending interrupts and disable all interrupts */
- li r4,-1 /* set p1 to 0xffffffff */
- stw r4,0x1b0(r3) /* clear all pending interrupts */
- stw r4,0x1b8(r3) /* clear all pending interrupts */
- li r4,0 /* set r4 to 0 */
- stw r4,0x1b4(r3) /* disable all interrupts */
- stw r4,0x1bc(r3) /* disable all interrupts */
-
- /* make sure above stores all comlete before going on */
- sync
-
- /* Set-up icache cacheability. */
- lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
- ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
- mticcr r1
- isync
-
- /* Set-up dcache cacheability. */
- lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
- ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
- mtdccr r1
-
- addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
- ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
- li r0, 0 /* Make room for stack frame header and */
- stwu r0, -4(r1) /* clear final stack frame so that */
- stwu r0, -4(r1) /* stack backtraces terminate cleanly */
-
- GET_GOT /* initialize GOT access */
-
- bl board_init_f /* run first part of init code (from Flash) */
- /* NOTREACHED - board_init_f() does not return */
-
-#endif /* CONFIG_IOP480 */
-
-/*****************************************************************************/
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || defined(CONFIG_405)
*/
static char ohci_inited = 0;
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
memset (&gohci, 0, sizeof (ohci_t));
memset (&urb_priv, 0, sizeof (urb_priv_t));
return 0;
}
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
/* this gets called really early - before the controller has */
/* even been initialized! */
#include <asm/processor.h>
/* bytes per L1 cache line */
-#if defined(CONFIG_8xx) || defined(CONFIG_IOP480)
+#if defined(CONFIG_8xx)
#define L1_CACHE_SHIFT 4
#elif defined(CONFIG_PPC64BRIDGE)
#define L1_CACHE_SHIFT 7
#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27)
#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
-#ifndef CONFIG_IOP480
#define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
-#else
-#define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480(403)*/
-#endif
/* DCR registers */
#define PLB0_ACR 0x0087
#endif
/*
- * Configure which SDRAM/DDR/DDR2 controller is equipped
- */
-#if defined(CONFIG_AP1000) || defined(CONFIG_ML2)
-#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
-#endif
-
-/*
* Common registers for all SoC's
*/
/* DCR registers */
gd->env_addr += dest_addr - CONFIG_SYS_MONITOR_BASE;
#endif
-#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
-#endif
debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
-#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
-#endif
#ifdef CONFIG_POST
post_output_backlog();
#include <common.h>
#include <asm/processor.h>
#include <asm/leon.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
#define READ_DWORD(var) SPARC_NOCACHE_READ_DWORD((unsigned int)&(var))
#endif
-int serial_init(void)
+static int leon2_serial_init(void)
{
LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
LEON2_Uart_regs *regs;
return 0;
}
-void serial_putc(const char c)
-{
- if (c == '\n')
- serial_putc_raw('\r');
-
- serial_putc_raw(c);
-}
-
-void serial_putc_raw(const char c)
+static void leon2_serial_putc_raw(const char c)
{
LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
LEON2_Uart_regs *regs;
#endif
}
-void serial_puts(const char *s)
+static void leon2_serial_putc(const char c)
+{
+ if (c == '\n')
+ leon2_serial_putc_raw('\r');
+
+ leon2_serial_putc_raw(c);
+}
+
+static void leon2_serial_puts(const char *s)
{
while (*s) {
serial_putc(*s++);
}
}
-int serial_getc(void)
+static int leon2_serial_getc(void)
{
LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
LEON2_Uart_regs *regs;
return READ_WORD(regs->UART_Channel);
}
-int serial_tstc(void)
+static int leon2_serial_tstc(void)
{
LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
LEON2_Uart_regs *regs;
}
/* set baud rate for uart */
-void serial_setbrg(void)
+static void leon2_serial_setbrg(void)
{
/* update baud rate settings, read it from gd->baudrate */
unsigned int scaler;
regs->UART_Scaler = scaler;
}
}
+
+static struct serial_device leon2_serial_drv = {
+ .name = "leon2_serial",
+ .start = leon2_serial_init,
+ .stop = NULL,
+ .setbrg = leon2_serial_setbrg,
+ .putc = leon2_serial_putc,
+ .puts = leon2_serial_puts,
+ .getc = leon2_serial_getc,
+ .tstc = leon2_serial_tstc,
+};
+
+void leon2_serial_initialize(void)
+{
+ serial_register(&leon2_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &leon2_serial_drv;
+}
#include <asm/processor.h>
#include <asm/leon.h>
#include <ambapp.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
ambapp_dev_apbuart *leon3_apbuart = NULL;
-int serial_init(void)
+static int leon3_serial_init(void)
{
ambapp_apbdev apbdev;
unsigned int tmp;
return -1; /* didn't find hardware */
}
-void serial_putc(const char c)
-{
- if (c == '\n')
- serial_putc_raw('\r');
-
- serial_putc_raw(c);
-}
-
-void serial_putc_raw(const char c)
+static void leon3_serial_putc_raw(const char c)
{
if (!leon3_apbuart)
return;
#endif
}
-void serial_puts(const char *s)
+static void leon3_serial_putc(const char c)
+{
+ if (c == '\n')
+ leon3_serial_putc_raw('\r');
+
+ leon3_serial_putc_raw(c);
+}
+
+static void leon3_serial_puts(const char *s)
{
while (*s) {
serial_putc(*s++);
}
}
-int serial_getc(void)
+static int leon3_serial_getc(void)
{
if (!leon3_apbuart)
return 0;
return READ_WORD(leon3_apbuart->data);
}
-int serial_tstc(void)
+static int leon3_serial_tstc(void)
{
if (leon3_apbuart)
return (READ_WORD(leon3_apbuart->status) &
}
/* set baud rate for uart */
-void serial_setbrg(void)
+static void leon3_serial_setbrg(void)
{
/* update baud rate settings, read it from gd->baudrate */
unsigned int scaler;
}
return;
}
+
+static struct serial_device leon3_serial_drv = {
+ .name = "leon3_serial",
+ .start = leon3_serial_init,
+ .stop = NULL,
+ .setbrg = leon3_serial_setbrg,
+ .putc = leon3_serial_putc,
+ .puts = leon3_serial_puts,
+ .getc = leon3_serial_getc,
+ .tstc = leon3_serial_tstc,
+};
+
+void leon3_serial_initialize(void)
+{
+ serial_register(&leon3_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &leon3_serial_drv;
+}
/* init uhci
*/
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
unsigned char temp;
ambapp_ahbdev ahbdev;
/* stop uhci
*/
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
if (grusb_irq == -1)
return 1;
extern void prepare_bootargs(char *bootargs);
#ifdef CONFIG_USB_UHCI
-extern int usb_lowlevel_stop(void);
+extern int usb_lowlevel_stop(int index);
#endif
/* sparc kernel argument (the ROM vector) */
timer_init,
display_banner,
display_dram_config,
-#ifdef CONFIG_SERIAL_MULTI
serial_initialize_r,
-#endif
#ifndef CONFIG_SYS_NO_FLASH
flash_init_r,
#endif
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+#define MII_MARVELL_PHY_PAGE 22
+
#define MV88E1116_LED_FCTRL_REG 10
#define MV88E1116_CPRSP_CR3_REG 21
#define MV88E1116_MAC_CTRL_REG 21
-#define MV88E1116_PGADR_REG 22
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
- miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
+ miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®);
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
- miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
+ miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
if (miiphy_reset(name, phyaddr) == 0)
printf("88E1116 Initialized on %s\n", name);
}
+
+void mv_phy_88e1318_init(const char *name, u16 phyaddr)
+{
+ u16 reg;
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /*
+ * Set control mode 4 for LED[0].
+ */
+ miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
+ miiphy_read(name, phyaddr, 16, ®);
+ reg |= 0xf;
+ miiphy_write(name, phyaddr, 16, reg);
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
+ miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL);
+ miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
+
+ if (miiphy_reset(name, phyaddr) == 0)
+ printf("88E1318 Initialized on %s\n", name);
+}
#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */
#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
void mv_phy_88e1116_init(const char *name, u16 phyaddr);
+void mv_phy_88e1318_init(const char *name, u16 phyaddr);
#endif
#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
int lacie_read_mac_address(uchar *mac);
--- /dev/null
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000618 # DDR Configuration register
+# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x34143000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000DDDD # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 10, Cs0size=512Mb
+# bit5-4: 00, Cs2width=nonexistent
+# bit7-6: 00, Cs1size =nonexistent
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000632 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000004 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 1, DDR drive strenght reduced
+# bit2: 1, DDR ODT control lsd enabled
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, enabled
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 1 , D2P Latency enabled
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
+# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
+# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit11-10:1, DQ_ODTSel. ODT select turned on
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
/* Configure and initialize PHY */
void reset_phy(void)
{
+#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
+ mv_phy_88e1318_init("egiga0", 0);
+#else
mv_phy_88e1116_init("egiga0", 8);
+#endif
}
#endif
#include <common.h>
#include <command.h>
+#include <serial.h>
+#include <linux/compiler.h>
+
#include "../include/memory.h"
#include "serial.h"
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_MPSC
-
-
-int serial_init (void)
+static int marvell_serial_init(void)
{
#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
int clock_divisor = 230400 / gd->baudrate;
return (0);
}
-void serial_putc (const char c)
+static void marvell_serial_putc(const char c)
{
if (c == '\n')
mpsc_putchar ('\r');
mpsc_putchar (c);
}
-int serial_getc (void)
+static int marvell_serial_getc(void)
{
return mpsc_getchar ();
}
-int serial_tstc (void)
+static int marvell_serial_tstc(void)
{
return mpsc_test_char ();
}
-void serial_setbrg (void)
+static void marvell_serial_setbrg(void)
{
galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
}
#else /* ! CONFIG_MPSC */
-int serial_init (void)
+static int marvell_serial_init(void)
{
int clock_divisor = 230400 / gd->baudrate;
return (0);
}
-void serial_putc (const char c)
+static void marvell_serial_putc(const char c)
{
if (c == '\n')
NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
}
-int serial_getc (void)
+static int marvell_serial_getc(void)
{
return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
}
-int serial_tstc (void)
+static int marvell_serial_tstc(void)
{
return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
}
-void serial_setbrg (void)
+static void marvell_serial_setbrg(void)
{
int clock_divisor = 230400 / gd->baudrate;
#endif /* CONFIG_MPSC */
-void serial_puts (const char *s)
+static void marvell_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
+static struct serial_device marvell_serial_drv = {
+ .name = "marvell_serial",
+ .start = marvell_serial_init,
+ .stop = NULL,
+ .setbrg = marvell_serial_setbrg,
+ .putc = marvell_serial_putc,
+ .puts = marvell_serial_puts,
+ .getc = marvell_serial_getc,
+ .tstc = marvell_serial_tstc,
+};
+
+void marvell_serial_initialize(void)
+{
+ serial_register(&marvell_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &marvell_serial_drv;
+}
+
#if defined(CONFIG_CMD_KGDB)
void kgdb_serial_init (void)
{
DBKIND_A: .long 0xFE800020
DBKIND_D: .long 0x00000005
DBCONF_A: .long 0xFE800024
-DBCONF_D: .long 0x0D020901
+DBCONF_D: .long 0x0D020A01
DBTR0_A: .long 0xFE800040
DBTR0_D_533:.long 0x00000004
#
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
#
# See file CREDITS for list of people who contributed to this
# project.
LIB = $(obj)lib$(BOARD).o
-COBJS-y += $(BOARD).o
-COBJS-y += sdram.o
-COBJS-y += law.o
-COBJS-y += tlb.o
+COBJS := socfpga_cyclone5.o
-COBJS-$(CONFIG_NAND) += nand.o
-
-COBJS := $(COBJS-y)
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
#########################################################################
# defines $(obj).depend target
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+ puts("CPU : Altera SOCFPGA Platform\n");
+ return 0;
+}
+
+/*
+ * Print Board information
+ */
+int checkboard(void)
+{
+ puts("BOARD : Altera SOCFPGA Cyclone5 Board\n");
+ return 0;
+}
+
+/*
+ * Initialization function which happen at early stage of c code
+ */
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ icache_enable();
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+ return 0;
+}
+#endif
+
+/*
+ * DesignWare Ethernet initialization
+ */
+/* We know all the init functions have been run now */
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+++ /dev/null
-/*
- * amirix.c: ppcboot platform support for AMIRIX board
- *
- * Copyright 2002 Mind NV
- * Copyright 2003 AMIRIX Systems Inc.
- *
- * http://www.mind.be/
- * http://www.amirix.com/
- *
- * Author : Peter De Schrijver (p2@mind.be)
- * Frank Smith (smith@amirix.com)
- *
- * Derived from : Other platform support files in this tree, ml2
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL) version 2, incorporated herein by
- * reference. Drivers based on or derived from this code fall under the GPL
- * and must retain the authorship, copyright and this license notice. This
- * file is not a complete program and may only be used when the entire
- * program is licensed under the GPL.
- *
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/processor.h>
-
-#include "powerspan.h"
-#include "ap1000.h"
-
-int board_pre_init (void)
-{
- return 0;
-}
-
-/** serial number and platform display at startup */
-int checkboard (void)
-{
- char buf[64];
- int l = getenv_f("serial#", buf, sizeof(buf));
-
- /* After a loadace command, the SystemAce control register is left in a wonky state. */
- /* this code did not work in board_pre_init */
- unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE;
- unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR;
- unsigned int device = (*revision_reg_ptr & AP1xx_TARGET_MASK);
-
- p[SYSACE_CTRLREG0] = 0x0;
-
- /* add platform and device to banner */
- switch (device) {
- case AP1xx_AP107_TARGET:
- puts (AP1xx_AP107_TARGET_STR);
- break;
- case AP1xx_AP120_TARGET:
- puts (AP1xx_AP120_TARGET_STR);
- break;
- case AP1xx_AP130_TARGET:
- puts (AP1xx_AP130_TARGET_STR);
- break;
- case AP1xx_AP1070_TARGET:
- puts (AP1xx_AP1070_TARGET_STR);
- break;
- case AP1xx_AP1100_TARGET:
- puts (AP1xx_AP1100_TARGET_STR);
- break;
- default:
- puts (AP1xx_UNKNOWN_STR);
- break;
- }
- puts (AP1xx_TARGET_STR);
- puts (" with ");
-
- switch (get_platform ()) {
- case AP100_BASELINE_PLATFORM:
- case AP1000_BASELINE_PLATFORM:
- puts (AP1xx_BASELINE_PLATFORM_STR);
- break;
- case AP1xx_QUADGE_PLATFORM:
- puts (AP1xx_QUADGE_PLATFORM_STR);
- break;
- case AP1xx_MGT_REF_PLATFORM:
- puts (AP1xx_MGT_REF_PLATFORM_STR);
- break;
- case AP1xx_STANDARD_PLATFORM:
- puts (AP1xx_STANDARD_PLATFORM_STR);
- break;
- case AP1xx_DUAL_PLATFORM:
- puts (AP1xx_DUAL_PLATFORM_STR);
- break;
- case AP1xx_BASE_SRAM_PLATFORM:
- puts (AP1xx_BASE_SRAM_PLATFORM_STR);
- break;
- case AP1xx_PCI_PCB_TESTPLATFORM:
- case AP1000_PCI_PCB_TESTPLATFORM:
- puts (AP1xx_PCI_PCB_TESTPLATFORM_STR);
- break;
- case AP1xx_DUAL_GE_MEZZ_TESTPLATFORM:
- puts (AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR);
- break;
- case AP1xx_SFP_MEZZ_TESTPLATFORM:
- puts (AP1xx_SFP_MEZZ_TESTPLATFORM_STR);
- break;
- default:
- puts (AP1xx_UNKNOWN_STR);
- break;
- }
-
- if ((get_platform () & AP1xx_TESTPLATFORM_MASK) != 0) {
- puts (AP1xx_TESTPLATFORM_STR);
- } else {
- puts (AP1xx_PLATFORM_STR);
- }
-
- putc ('\n');
-
- puts ("Serial#: ");
-
- if (l < 0) {
- printf ("### No HW ID - assuming AMIRIX");
- } else {
- int i;
-
- for (i = 0; i < l; ++i) {
- if (buf[i] == ' ') {
- buf[i] = '\0';
- break;
- }
- }
-
- puts(buf);
- }
-
- putc ('\n');
-
- return (0);
-}
-
-
-phys_size_t initdram (int board_type)
-{
- char buf[64];
- int i = getenv_f("dramsize", buf, sizeof(buf));
-
- if (i > 0) {
- char *s = buf;
- if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) {
- s += 2;
- }
- return (long int)simple_strtoul (s, NULL, 16);
- } else {
- /* give all 64 MB */
- return 64 * 1024 * 1024;
- }
-}
-
-unsigned int get_platform (void)
-{
- unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR;
-
- return (*revision_reg_ptr & AP1xx_PLATFORM_MASK);
-}
-
-#if 0 /* loadace is not working; it appears to be a hardware issue with the system ace. */
-/*
- This function loads FPGA configurations from the SystemACE CompactFlash
-*/
-int do_loadace (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE;
- int cfg;
-
- if ((p[SYSACE_STATREG0] & 0x10) == 0) {
- p[SYSACE_CTRLREG0] = 0x80;
- printf ("\nNo CompactFlash Detected\n\n");
- p[SYSACE_CTRLREG0] = 0x00;
- return 1;
- }
-
- /* reset configuration controller: | 0x80 */
- /* select cpflash & ~0x40 */
- /* cfg start | 0x20 */
- /* wait for cfgstart & ~0x10 */
- /* force cfgmode: | 0x08 */
- /* do no force cfgaddr: & ~0x04 */
- /* clear mpulock: & ~0x02 */
- /* do not force lock request & ~0x01 */
-
- p[SYSACE_CTRLREG0] = 0x80 | 0x20 | 0x08;
- p[SYSACE_CTRLREG1] = 0x00;
-
- /* force config address if arg2 exists */
- if (argc == 2) {
- cfg = simple_strtoul (argv[1], NULL, 10);
-
- if (cfg > 7) {
- printf ("\nInvalid Configuration\n\n");
- p[SYSACE_CTRLREG0] = 0x00;
- return 1;
- }
- /* Set config address */
- p[SYSACE_CTRLREG1] = (cfg << 5);
- /* force cfgaddr */
- p[SYSACE_CTRLREG0] |= 0x04;
-
- } else {
- cfg = (p[SYSACE_STATREG1] & 0xE0) >> 5;
- }
-
- /* release configuration controller */
- printf ("\nLoading V2PRO with config %d...\n", cfg);
- p[SYSACE_CTRLREG0] &= ~0x80;
-
-
- while ((p[SYSACE_STATREG1] & 0x01) == 0) {
-
- if (p[SYSACE_ERRREG0] & 0x80) {
- /* attempting to load an invalid configuration makes the cpflash */
- /* appear to be removed. Reset here to avoid that problem */
- p[SYSACE_CTRLREG0] = 0x80;
- printf ("\nConfiguration %d Read Error\n\n", cfg);
- p[SYSACE_CTRLREG0] = 0x00;
- return 1;
- }
- }
-
- p[SYSACE_CTRLREG0] |= 0x20;
-
- return 0;
-}
-#endif
-
-/** Console command to display and set the software reconfigure byte
- * <pre>
- * swconfig - display the current value of the software reconfigure byte
- * swconfig [#] - change the software reconfigure byte to #
- * </pre>
- * @param *cmdtp [IN] as passed by run_command (ignored)
- * @param flag [IN] as passed by run_command (ignored)
- * @param argc [IN] as passed by run_command if 1, display, if 2 change
- * @param *argv[] [IN] contains the parameters to use
- * @return
- * <pre>
- * 0 if passed
- * -1 if failed
- * </pre>
- */
-int do_swconfigbyte (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned char *sector_buffer = NULL;
- unsigned char input_char;
- int write_result;
- unsigned int input_uint;
-
- /* display value if no argument */
- if (argc < 2) {
- printf ("Software configuration byte is currently: 0x%02x\n",
- *((unsigned char *) (SW_BYTE_SECTOR_ADDR +
- SW_BYTE_SECTOR_OFFSET)));
- return 0;
- } else if (argc > 3) {
- printf ("Too many arguments\n");
- return -1;
- }
-
- /* if 3 arguments, 3rd argument is the address to use */
- if (argc == 3) {
- input_uint = simple_strtoul (argv[1], NULL, 16);
- sector_buffer = (unsigned char *) input_uint;
- } else {
- sector_buffer = (unsigned char *) DEFAULT_TEMP_ADDR;
- }
-
- input_char = simple_strtoul (argv[1], NULL, 0);
- if ((input_char & ~SW_BYTE_MASK) != 0) {
- printf ("Input of 0x%02x will be masked to 0x%02x\n",
- input_char, (input_char & SW_BYTE_MASK));
- input_char = input_char & SW_BYTE_MASK;
- }
-
- memcpy (sector_buffer, (void *) SW_BYTE_SECTOR_ADDR,
- SW_BYTE_SECTOR_SIZE);
- sector_buffer[SW_BYTE_SECTOR_OFFSET] = input_char;
-
-
- printf ("Erasing Flash...");
- if (flash_sect_erase
- (SW_BYTE_SECTOR_ADDR,
- (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET))) {
- return -1;
- }
-
- printf ("Writing to Flash... ");
- write_result =
- flash_write ((char *)sector_buffer, SW_BYTE_SECTOR_ADDR,
- SW_BYTE_SECTOR_SIZE);
- if (write_result != 0) {
- flash_perror (write_result);
- return -1;
- } else {
- printf ("done\n");
- printf ("Software configuration byte is now: 0x%02x\n",
- *((unsigned char *) (SW_BYTE_SECTOR_ADDR +
- SW_BYTE_SECTOR_OFFSET)));
- }
-
- return 0;
-}
-
-#define ONE_SECOND 1000000
-
-int do_pause (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- int pause_time;
- unsigned int delay_time;
- int break_loop = 0;
-
- /* display value if no argument */
- if (argc < 2) {
- pause_time = 1;
- }
-
- else if (argc > 2) {
- printf ("Too many arguments\n");
- return -1;
- } else {
- pause_time = simple_strtoul (argv[1], NULL, 0);
- }
-
- printf ("Pausing with a poll time of %d, press any key to reactivate\n", pause_time);
- delay_time = pause_time * ONE_SECOND;
- while (break_loop == 0) {
- udelay (delay_time);
- if (serial_tstc () != 0) {
- break_loop = 1;
- /* eat user key presses */
- while (serial_tstc () != 0) {
- serial_getc ();
- }
- }
- }
-
- return 0;
-}
-
-int do_swreconfig (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- printf ("Triggering software reconfigure (software config byte is 0x%02x)...\n",
- *((unsigned char *) (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET)));
- udelay (1000);
- *((unsigned char *) AP1000_CPLD_BASE) = 1;
-
- return 0;
-}
-
-#define GET_DECIMAL(low_byte) ((low_byte >> 5) * 125)
-#define TEMP_BUSY_BIT 0x80
-#define TEMP_LHIGH_BIT 0x40
-#define TEMP_LLOW_BIT 0x20
-#define TEMP_EHIGH_BIT 0x10
-#define TEMP_ELOW_BIT 0x08
-#define TEMP_OPEN_BIT 0x04
-#define TEMP_ETHERM_BIT 0x02
-#define TEMP_LTHERM_BIT 0x01
-
-int do_temp_sensor (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- char cmd;
- int ret_val = 0;
- unsigned char temp_byte;
- int temp;
- int temp_low;
- int low;
- int low_low;
- int high;
- int high_low;
- int therm;
- unsigned char user_data[4] = { 0 };
- int user_data_count = 0;
- int ii;
-
- if (argc > 1) {
- cmd = argv[1][0];
- } else {
- cmd = 's'; /* default to status */
- }
-
- user_data_count = argc - 2;
- for (ii = 0; ii < user_data_count; ii++) {
- user_data[ii] = simple_strtoul (argv[2 + ii], NULL, 0);
- }
- switch (cmd) {
- case 's':
- if (I2CAccess
- (0x2, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- printf ("Status : 0x%02x ", temp_byte);
- if (temp_byte & TEMP_BUSY_BIT)
- printf ("BUSY ");
-
- if (temp_byte & TEMP_LHIGH_BIT)
- printf ("LHIGH ");
-
- if (temp_byte & TEMP_LLOW_BIT)
- printf ("LLOW ");
-
- if (temp_byte & TEMP_EHIGH_BIT)
- printf ("EHIGH ");
-
- if (temp_byte & TEMP_ELOW_BIT)
- printf ("ELOW ");
-
- if (temp_byte & TEMP_OPEN_BIT)
- printf ("OPEN ");
-
- if (temp_byte & TEMP_ETHERM_BIT)
- printf ("ETHERM ");
-
- if (temp_byte & TEMP_LTHERM_BIT)
- printf ("LTHERM");
-
- printf ("\n");
-
- if (I2CAccess
- (0x3, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- printf ("Config : 0x%02x ", temp_byte);
-
- if (I2CAccess
- (0x4, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- printf ("\n");
- goto fail;
- }
- printf ("Conversion: 0x%02x\n", temp_byte);
- if (I2CAccess
- (0x22, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- printf ("Cons Alert: 0x%02x ", temp_byte);
-
- if (I2CAccess
- (0x21, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- printf ("\n");
- goto fail;
- }
- printf ("Therm Hyst: %d\n", temp_byte);
-
- if (I2CAccess
- (0x0, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- temp = temp_byte;
- if (I2CAccess
- (0x6, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- low = temp_byte;
- if (I2CAccess
- (0x5, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- high = temp_byte;
- if (I2CAccess
- (0x20, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- therm = temp_byte;
- printf ("Local Temp: %2d Low: %2d High: %2d THERM: %2d\n", temp, low, high, therm);
-
- if (I2CAccess
- (0x1, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- temp = temp_byte;
- if (I2CAccess
- (0x10, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- temp_low = temp_byte;
- if (I2CAccess
- (0x8, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- low = temp_byte;
- if (I2CAccess
- (0x14, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- low_low = temp_byte;
- if (I2CAccess
- (0x7, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- high = temp_byte;
- if (I2CAccess
- (0x13, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- high_low = temp_byte;
- if (I2CAccess
- (0x19, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- therm = temp_byte;
- if (I2CAccess
- (0x11, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- printf ("Ext Temp : %2d.%03d Low: %2d.%03d High: %2d.%03d THERM: %2d Offset: %2d\n", temp, GET_DECIMAL (temp_low), low, GET_DECIMAL (low_low), high, GET_DECIMAL (high_low), therm, temp_byte);
- break;
- case 'l': /* alter local limits : low, high, therm */
- if (argc < 3) {
- goto usage;
- }
-
- /* low */
- if (I2CAccess
- (0xC, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &user_data[0], I2C_WRITE) != 0) {
- goto fail;
- }
-
- if (user_data_count > 1) {
- /* high */
- if (I2CAccess
- (0xB, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &user_data[1], I2C_WRITE) != 0) {
- goto fail;
- }
- }
-
- if (user_data_count > 2) {
- /* therm */
- if (I2CAccess
- (0x20, I2C_SENSOR_DEV,
- I2C_SENSOR_CHIP_SEL, &user_data[2],
- I2C_WRITE) != 0) {
- goto fail;
- }
- }
- break;
- case 'e': /* alter external limits: low, high, therm, offset */
- if (argc < 3) {
- goto usage;
- }
-
- /* low */
- if (I2CAccess
- (0xE, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &user_data[0], I2C_WRITE) != 0) {
- goto fail;
- }
-
- if (user_data_count > 1) {
- /* high */
- if (I2CAccess
- (0xD, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &user_data[1], I2C_WRITE) != 0) {
- goto fail;
- }
- }
-
- if (user_data_count > 2) {
- /* therm */
- if (I2CAccess
- (0x19, I2C_SENSOR_DEV,
- I2C_SENSOR_CHIP_SEL, &user_data[2],
- I2C_WRITE) != 0) {
- goto fail;
- }
- }
-
- if (user_data_count > 3) {
- /* offset */
- if (I2CAccess
- (0x11, I2C_SENSOR_DEV,
- I2C_SENSOR_CHIP_SEL, &user_data[3],
- I2C_WRITE) != 0) {
- goto fail;
- }
- }
- break;
- case 'c': /* alter config settings: config, conv, cons alert, therm hyst */
- if (argc < 3) {
- goto usage;
- }
-
- /* config */
- if (I2CAccess
- (0x9, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &user_data[0], I2C_WRITE) != 0) {
- goto fail;
- }
-
- if (user_data_count > 1) {
- /* conversion */
- if (I2CAccess
- (0xA, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &user_data[1], I2C_WRITE) != 0) {
- goto fail;
- }
- }
-
- if (user_data_count > 2) {
- /* cons alert */
- if (I2CAccess
- (0x22, I2C_SENSOR_DEV,
- I2C_SENSOR_CHIP_SEL, &user_data[2],
- I2C_WRITE) != 0) {
- goto fail;
- }
- }
-
- if (user_data_count > 3) {
- /* therm hyst */
- if (I2CAccess
- (0x21, I2C_SENSOR_DEV,
- I2C_SENSOR_CHIP_SEL, &user_data[3],
- I2C_WRITE) != 0) {
- goto fail;
- }
- }
- break;
- default:
- goto usage;
- }
-
- goto done;
-fail:
- printf ("Access to sensor failed\n");
- ret_val = -1;
- goto done;
-usage:
- printf ("Usage:\n%s\n", cmdtp->help);
-
-done:
- return ret_val;
-}
-
-U_BOOT_CMD (temp, 6, 0, do_temp_sensor,
- "interact with the temperature sensor",
- "temp [s]\n"
- " - Show status.\n"
- "temp l LOW [HIGH] [THERM]\n"
- " - Set local limits.\n"
- "temp e LOW [HIGH] [THERM] [OFFSET]\n"
- " - Set external limits.\n"
- "temp c CONFIG [CONVERSION] [CONS. ALERT] [THERM HYST]\n"
- " - Set config options.\n"
- "\n"
- "All values can be decimal or hex (hex preceded with 0x).\n"
- "Only whole numbers are supported for external limits.");
-
-#if 0
-U_BOOT_CMD (loadace, 2, 0, do_loadace,
- "load fpga configuration from System ACE compact flash",
- "N\n"
- " - Load configuration N (0-7) from System ACE compact flash\n"
- "loadace\n" " - loads default configuration");
-#endif
-
-U_BOOT_CMD (swconfig, 2, 0, do_swconfigbyte,
- "display or modify the software configuration byte",
- "N [ADDRESS]\n"
- " - set software configuration byte to N, optionally use ADDRESS as\n"
- " location of buffer for flash copy\n"
- "swconfig\n" " - display software configuration byte");
-
-U_BOOT_CMD (pause, 2, 0, do_pause,
- "sleep processor until any key is pressed with poll time of N seconds",
- "N\n"
- " - sleep processor until any key is pressed with poll time of N seconds\n"
- "pause\n"
- " - sleep processor until any key is pressed with poll time of 1 second");
-
-U_BOOT_CMD (swrecon, 1, 0, do_swreconfig,
- "trigger a board reconfigure to the software selected configuration",
- "\n"
- " - trigger a board reconfigure to the software selected configuration");
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
+++ /dev/null
-/*
- * ap1000.h: AP1000 (e.g. AP1070, AP1100) board specific definitions and functions that are needed globally
- *
- * Author : James MacAulay
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL) version 2, incorporated herein by
- * reference. Drivers based on or derived from this code fall under the GPL
- * and must retain the authorship, copyright and this license notice. This
- * file is not a complete program and may only be used when the entire
- * program is licensed under the GPL.
- *
- */
-
-#ifndef __AP1000_H
-#define __AP1000_H
-
-/*
- * Revision Register stuff
- */
-#define AP1xx_FPGA_REV_ADDR 0x29000000
-
-#define AP1xx_PLATFORM_MASK 0xFF000000
-#define AP100_BASELINE_PLATFORM 0x01000000
-#define AP1xx_QUADGE_PLATFORM 0x02000000
-#define AP1xx_MGT_REF_PLATFORM 0x03000000
-#define AP1xx_STANDARD_PLATFORM 0x04000000
-#define AP1xx_DUAL_PLATFORM 0x05000000
-#define AP1xx_BASE_SRAM_PLATFORM 0x06000000
-
-#define AP1000_BASELINE_PLATFORM 0x21000000
-
-#define AP1xx_TESTPLATFORM_MASK 0xC0000000
-#define AP1xx_PCI_PCB_TESTPLATFORM 0xC0000000
-#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM 0xC1000000
-#define AP1xx_SFP_MEZZ_TESTPLATFORM 0xC2000000
-
-#define AP1000_PCI_PCB_TESTPLATFORM 0xC3000000
-
-#define AP1xx_TARGET_MASK 0x00FF0000
-#define AP1xx_AP107_TARGET 0x00010000
-#define AP1xx_AP120_TARGET 0x00020000
-#define AP1xx_AP130_TARGET 0x00030000
-#define AP1xx_AP1070_TARGET 0x00040000
-#define AP1xx_AP1100_TARGET 0x00050000
-
-#define AP1xx_UNKNOWN_STR "Unknown"
-
-#define AP1xx_PLATFORM_STR " Platform"
-#define AP1xx_BASELINE_PLATFORM_STR "Baseline"
-#define AP1xx_QUADGE_PLATFORM_STR "Quad GE"
-#define AP1xx_MGT_REF_PLATFORM_STR "MGT Reference"
-#define AP1xx_STANDARD_PLATFORM_STR "Standard"
-#define AP1xx_DUAL_PLATFORM_STR "Dual"
-#define AP1xx_BASE_SRAM_PLATFORM_STR "Baseline with SRAM"
-
-#define AP1xx_TESTPLATFORM_STR " Test Platform"
-#define AP1xx_PCI_PCB_TESTPLATFORM_STR "Base"
-#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR "Dual GE Mezzanine"
-#define AP1xx_SFP_MEZZ_TESTPLATFORM_STR "SFP Mezzanine"
-
-#define AP1xx_TARGET_STR " Board"
-#define AP1xx_AP107_TARGET_STR "AP107"
-#define AP1xx_AP120_TARGET_STR "AP120"
-#define AP1xx_AP130_TARGET_STR "AP130"
-
-#define AP1xx_AP1070_TARGET_STR "AP1070"
-#define AP1xx_AP1100_TARGET_STR "AP1100"
-
-/*
- * Flash Stuff
- */
-#define AP1xx_PROGRAM_FLASH_INDEX 0
-#define AP1xx_CONFIG_FLASH_INDEX 1
-
-/*
- * System Ace Stuff
- */
-#define AP1000_SYSACE_REGBASE 0x28000000
-
-#define SYSACE_STATREG0 0x04 /* 7:0 */
-#define SYSACE_STATREG1 0x05 /* 15:8 */
-#define SYSACE_STATREG2 0x06 /* 23:16 */
-#define SYSACE_STATREG3 0x07 /* 31:24 */
-
-#define SYSACE_ERRREG0 0x08 /* 7:0 */
-#define SYSACE_ERRREG1 0x09 /* 15:8 */
-#define SYSACE_ERRREG2 0x0a /* 23:16 */
-#define SYSACE_ERRREG3 0x0b /* 31:24 */
-
-#define SYSACE_CTRLREG0 0x18 /* 7:0 */
-#define SYSACE_CTRLREG1 0x19 /* 15:8 */
-#define SYSACE_CTRLREG2 0x1A /* 23:16 */
-#define SYSACE_CTRLREG3 0x1B /* 31:24 */
-
-/*
- * Software reconfig thing
- */
-#define SW_BYTE_SECTOR_ADDR 0x24FE0000
-#define SW_BYTE_SECTOR_OFFSET 0x0001FFFF
-#define SW_BYTE_SECTOR_SIZE 0x00020000
-#define SW_BYTE_MASK 0x00000003
-
-#define DEFAULT_TEMP_ADDR 0x00100000
-
-#define AP1000_CPLD_BASE 0x26000000
-
-/* PowerSpan II Stuff */
-#define PSII_SYNC() asm("eieio")
-#define PSPAN_BASEADDR 0x30000000
-#define EEPROM_DEFAULT { 0x01, /* Byte 0 - Long Load = 0x02, short = 01, use 0xff for try no load */ \
- 0x0,0x0,0x0, /* Bytes 1 - 3 Power span reserved */ \
- 0x0, /* Byte 4 - Powerspan reserved - start of short load */ \
- 0x0F, /* Byte 5 - Enable PCI 1 & 2 as Bus masters and Memory targets. */ \
- 0x0E, /* Byte 6 - PCI 1 Target image prefetch - on for image 0,1,2, off for i20 & 3. */ \
- 0x00, 0x00, /* Byte 7,8 - PCI-1 Subsystem ID - */ \
- 0x00, 0x00, /* Byte 9,10 - PCI-1 Subsystem Vendor Id - */ \
- 0x00, /* Byte 11 - No PCI interrupt generation on PCI-1 PCI-2 int A */ \
- 0x1F, /* Byte 12 - PCI-1 enable bridge registers, all target images */ \
- 0xBA, /* Byte 13 - Target 0 image 128 Meg(Ram), Target 1 image 64 Meg. (config Flash/CPLD )*/ \
- 0xA0, /* Byte 14 - Target 2 image 64 Meg(program Flash), target 3 64k. */ \
- 0x00, /* Byte 15 - Vital Product Data Disabled. */ \
- 0x88, /* Byte 16 - PCI arbiter config complete, all requests routed through PCI-1, Unlock PCI-1 */ \
- 0x40, /* Byte 17 - Interrupt direction control - PCI-1 Int A out, everything else in. */ \
- 0x00, /* Byte 18 - I2O disabled */ \
- 0x00, /* Byte 19 - PCI-2 Target image prefetch - off for all images. */ \
- 0x00,0x00, /* Bytes 20,21 - PCI 2 Subsystem Id */ \
- 0x00,0x00, /* Bytes 22,23 - PCI 2 Subsystem Vendor id */ \
- 0x0C, /* Byte 24 - PCI-2 BAR enables, target image 0, & 1 */ \
- 0xBB, /* Byte 25 - PCI-2 target 0 - 128 Meg(Ram), target 1 - 128 Meg (program/config flash) */ \
- 0x00, /* Byte 26 - PCI-2 target 2 & 3 unused. */ \
- 0x00,0x00,0x00,0x00,0x00, /* Bytes 27,28,29,30, 31 - Reserved */ \
- /* Long Load Information */ \
- 0x82,0x60, /* Bytes 32,33 - PCI-1 Device ID - Powerspan II */ \
- 0x10,0xE3, /* Bytes 24,35 - PCI-1 Vendor ID - Tundra */ \
- 0x06, /* Byte 36 - PCI-1 Class Base - Bridge device. */ \
- 0x80, /* Byte 37 - PCI-1 Class sub class - Other bridge. */ \
- 0x00, /* Byte 38 - PCI-1 Class programing interface - Other bridge */ \
- 0x01, /* Byte 39 - Power span revision 1. */ \
- 0x6E, /* Byte 40 - PB SI0 enabled, translation enabled, decode enabled, 64 Meg */ \
- 0x40, /* Byte 41 - PB SI0 memory command mode, PCI-1 dest */ \
- 0x22, /* Byte 42 - Prefetch discard after read, PCI-little endian conversion, 32 byte prefetch */ \
- 0x00,0x00, /* Bytes 43, 44 - Translation address for SI0, set to zero for now. */ \
- 0x0E, /* Byte 45 - Translation address (0) and PB bus master enables - all. */ \
- 0x2c,00,00, /* Bytes 46,47,48 - PB SI0 processor base address - 0x2C000000 */ \
- 0x30,00,00, /* Bytes 49,50,51 - PB Address for Powerspan registers - 0x30000000, big Endian */ \
- 0x82,0x60, /* Bytes 52, 53 - PCI-2 Device ID - Powerspan II */ \
- 0x10,0xE3, /* Bytes 54,55 - PCI 2 Vendor Id - Tundra */ \
- 0x06, /* Byte 56 - PCI-2 Class Base - Bridge device */ \
- 0x80, /* Byte 57 - PCI-2 Class sub class - Other Bridge. */ \
- 0x00, /* Byte 58 - PCI-2 class programming interface - Other bridge */ \
- 0x01, /* Byte 59 - PCI-2 class revision 1 */ \
- 0x00,0x00,0x00,0x00 }; /* Bytes 60,61, 62, 63 - Powerspan reserved */
-
-
-#define EEPROM_LENGTH 64 /* Long Load */
-
-#define I2C_SENSOR_DEV 0x9
-#define I2C_SENSOR_CHIP_SEL 0x4
-
-/*
- * Board Functions
- */
-void set_eat_machine_checks(int a_flag);
-int get_eat_machine_checks(void);
-unsigned int get_platform(void);
-void* memcpyb(void * dest,const void *src,size_t count);
-int process_bootflag(ulong bootflag);
-void user_led_on(void);
-void user_led_off(void);
-
-#endif /* __COMMON_H_ */
+++ /dev/null
-/**
- * @file flash.c
- */
-
-/*
- * (C) Copyright 2003
- * AMIRIX Systems Inc.
- *
- * Originated from ppcboot-2.0.0/board/esd/cpci440/strataflash.c
- *
- * (C) Copyright 2002
- * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-#undef DEBUG_FLASH
-/*
- * This file implements a Common Flash Interface (CFI) driver for ppcboot.
- * The width of the port and the width of the chips are determined at initialization.
- * These widths are used to calculate the address for access CFI data structures.
- * It has been tested on an Intel Strataflash implementation.
- *
- * References
- * JEDEC Standard JESD68 - Common Flash Interface (CFI)
- * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
- * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
- * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
- *
- * TODO
- * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
- * Add support for other command sets Use the PRI and ALT to determine command set
- * Verify erase and program timeouts.
- */
-
-#define FLASH_CMD_CFI 0x98
-#define FLASH_CMD_READ_ID 0x90
-#define FLASH_CMD_RESET 0xff
-#define FLASH_CMD_BLOCK_ERASE 0x20
-#define FLASH_CMD_ERASE_CONFIRM 0xD0
-#define FLASH_CMD_WRITE 0x40
-#define FLASH_CMD_PROTECT 0x60
-#define FLASH_CMD_PROTECT_SET 0x01
-#define FLASH_CMD_PROTECT_CLEAR 0xD0
-#define FLASH_CMD_CLEAR_STATUS 0x50
-#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
-#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
-
-#define FLASH_STATUS_DONE 0x80
-#define FLASH_STATUS_ESS 0x40
-#define FLASH_STATUS_ECLBS 0x20
-#define FLASH_STATUS_PSLBS 0x10
-#define FLASH_STATUS_VPENS 0x08
-#define FLASH_STATUS_PSS 0x04
-#define FLASH_STATUS_DPS 0x02
-#define FLASH_STATUS_R 0x01
-#define FLASH_STATUS_PROTECT 0x01
-
-#define FLASH_OFFSET_CFI 0x55
-#define FLASH_OFFSET_CFI_RESP 0x10
-#define FLASH_OFFSET_WTOUT 0x1F
-#define FLASH_OFFSET_WBTOUT 0x20
-#define FLASH_OFFSET_ETOUT 0x21
-#define FLASH_OFFSET_CETOUT 0x22
-#define FLASH_OFFSET_WMAX_TOUT 0x23
-#define FLASH_OFFSET_WBMAX_TOUT 0x24
-#define FLASH_OFFSET_EMAX_TOUT 0x25
-#define FLASH_OFFSET_CEMAX_TOUT 0x26
-#define FLASH_OFFSET_SIZE 0x27
-#define FLASH_OFFSET_INTERFACE 0x28
-#define FLASH_OFFSET_BUFFER_SIZE 0x2A
-#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
-#define FLASH_OFFSET_ERASE_REGIONS 0x2D
-#define FLASH_OFFSET_PROTECT 0x02
-#define FLASH_OFFSET_USER_PROTECTION 0x85
-#define FLASH_OFFSET_INTEL_PROTECTION 0x81
-
-#define FLASH_MAN_CFI 0x01000000
-
-typedef union {
- unsigned char c;
- unsigned short w;
- unsigned long l;
-} cfiword_t;
-
-typedef union {
- unsigned char *cp;
- unsigned short *wp;
- unsigned long *lp;
-} cfiptr_t;
-
-#define NUM_ERASE_REGIONS 4
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-
-static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c);
-static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf);
-static void flash_write_cmd (flash_info_t * info, int sect, uchar offset,
- uchar cmd);
-static int flash_isequal (flash_info_t * info, int sect, uchar offset,
- uchar cmd);
-static int flash_isset (flash_info_t * info, int sect, uchar offset,
- uchar cmd);
-static int flash_detect_cfi (flash_info_t * info);
-static ulong flash_get_size (ulong base, int banknum);
-static int flash_write_cfiword (flash_info_t * info, ulong dest,
- cfiword_t cword);
-static int flash_full_status_check (flash_info_t * info, ulong sector,
- ulong tout, char *prompt);
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
- int len);
-#endif
-/*-----------------------------------------------------------------------
- * create an address based on the offset and the port width
- */
-uchar *flash_make_addr (flash_info_t * info, int sect, int offset)
-{
- return ((uchar *) (info->start[sect] + (offset * info->chipwidth)));
-}
-
-/*-----------------------------------------------------------------------
- * read a character at a port width address
- */
-uchar flash_read_uchar (flash_info_t * info, uchar offset)
-{
- if (info->portwidth == FLASH_CFI_8BIT) {
- volatile uchar *cp;
- uchar c;
-
- cp = flash_make_addr (info, 0, offset);
- c = *cp;
-#ifdef DEBUG_FLASH
- printf ("flash_read_uchar offset=%04x ptr=%08x c=%02x\n",
- offset, (unsigned int) cp, c);
-#endif
- return (c);
-
- } else if (info->portwidth == FLASH_CFI_16BIT) {
- volatile ushort *sp;
- ushort s;
- uchar c;
-
- sp = (ushort *) flash_make_addr (info, 0, offset);
- s = *sp;
- c = (uchar) s;
-#ifdef DEBUG_FLASH
- printf ("flash_read_uchar offset=%04x ptr=%08x s=%04x c=%02x\n", offset, (unsigned int) sp, s, c);
-#endif
- return (c);
-
- }
-
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * read a short word by swapping for ppc format.
- */
-ushort flash_read_ushort (flash_info_t * info, int sect, uchar offset)
-{
- if (info->portwidth == FLASH_CFI_8BIT) {
- volatile uchar *cp;
- uchar c0, c1;
- ushort s;
-
- cp = flash_make_addr (info, 0, offset);
- c1 = cp[2];
- c0 = cp[0];
- s = c1 << 8 | c0;
-#ifdef DEBUG_FLASH
- printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) cp, c1, c0, s);
-#endif
- return (s);
-
- } else if (info->portwidth == FLASH_CFI_16BIT) {
- volatile ushort *sp;
- ushort s;
- uchar c0, c1;
-
- sp = (ushort *) flash_make_addr (info, 0, offset);
- s = *sp;
- c1 = (uchar) sp[1];
- c0 = (uchar) sp[0];
- s = c1 << 8 | c0;
-#ifdef DEBUG_FLASH
- printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) sp, c1, c0, s);
-#endif
- return (s);
-
- }
-
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * read a long word by picking the least significant byte of each maiximum
- * port size word. Swap for ppc format.
- */
-ulong flash_read_long (flash_info_t * info, int sect, uchar offset)
-{
- if (info->portwidth == FLASH_CFI_8BIT) {
- volatile uchar *cp;
- uchar c0, c1, c2, c3;
- ulong l;
-
- cp = flash_make_addr (info, 0, offset);
- c3 = cp[6];
- c2 = cp[4];
- c1 = cp[2];
- c0 = cp[0];
- l = c3 << 24 | c2 << 16 | c1 << 8 | c0;
-#ifdef DEBUG_FLASH
- printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) cp, c3, c2, c1, c0, l);
-#endif
- return (l);
-
- } else if (info->portwidth == FLASH_CFI_16BIT) {
- volatile ushort *sp;
- uchar c0, c1, c2, c3;
- ulong l;
-
- sp = (ushort *) flash_make_addr (info, 0, offset);
- c3 = (uchar) sp[3];
- c2 = (uchar) sp[2];
- c1 = (uchar) sp[1];
- c0 = (uchar) sp[0];
- l = c3 << 24 | c2 << 16 | c1 << 8 | c0;
-#ifdef DEBUG_FLASH
- printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) sp, c3, c2, c1, c0, l);
-#endif
- return (l);
-
- }
-
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- unsigned long size;
-
- size = 0;
-
- flash_info[0].flash_id = FLASH_UNKNOWN;
- flash_info[0].portwidth = FLASH_CFI_16BIT;
- flash_info[0].chipwidth = FLASH_CFI_16BIT;
- size += flash_info[0].size = flash_get_size (CONFIG_SYS_PROGFLASH_BASE, 0);
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 1, flash_info[0].size, flash_info[0].size << 20);
- };
-
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].portwidth = FLASH_CFI_8BIT;
- flash_info[1].chipwidth = FLASH_CFI_16BIT;
- size += flash_info[1].size = flash_get_size (CONFIG_SYS_CONFFLASH_BASE, 1);
- if (flash_info[1].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 2, flash_info[1].size, flash_info[1].size << 20);
- };
-
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int rcode = 0;
- int prot;
- int sect;
-
- if (info->flash_id != FLASH_MAN_CFI) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
- if ((s_first < 0) || (s_first > s_last)) {
- printf ("- no sectors to erase\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- flash_write_cmd (info, sect, 0,
- FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd (info, sect, 0,
- FLASH_CMD_BLOCK_ERASE);
- flash_write_cmd (info, sect, 0,
- FLASH_CMD_ERASE_CONFIRM);
-
- if (flash_full_status_check
- (info, sect, info->erase_blk_tout, "erase")) {
- rcode = 1;
- } else
- printf (".");
- }
- }
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id != FLASH_MAN_CFI) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- printf ("CFI conformant FLASH (x%d device in x%d mode)",
- (info->chipwidth << 3), (info->portwidth << 3));
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
- printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n");
- printf (" %08lX%5s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong wp;
- ulong cp;
- int aln;
- cfiword_t cword;
- int i, rc;
-
- /* get lower aligned address */
- wp = (addr & ~(info->portwidth - 1));
-
- /* handle unaligned start */
- if ((aln = addr - wp) != 0) {
- cword.l = 0;
- cp = wp;
- for (i = 0; i < aln; ++i, ++cp)
- flash_add_byte (info, &cword, (*(uchar *) cp));
-
- for (; (i < info->portwidth) && (cnt > 0); i++) {
- flash_add_byte (info, &cword, *src++);
- cnt--;
- cp++;
- }
- for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
- flash_add_byte (info, &cword, (*(uchar *) cp));
- if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
- return rc;
- wp = cp;
- }
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
- while (cnt >= info->portwidth) {
- i = info->buffer_size > cnt ? cnt : info->buffer_size;
- if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
- return rc;
- wp += i;
- src += i;
- cnt -= i;
- }
-#else
- /* handle the aligned part */
- while (cnt >= info->portwidth) {
- cword.l = 0;
- for (i = 0; i < info->portwidth; i++) {
- flash_add_byte (info, &cword, *src++);
- }
- if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
- return rc;
- wp += info->portwidth;
- cnt -= info->portwidth;
- }
-#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- cword.l = 0;
- for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
- flash_add_byte (info, &cword, *src++);
- --cnt;
- }
- for (; i < info->portwidth; ++i, ++cp) {
- flash_add_byte (info, &cword, (*(uchar *) cp));
- }
-
- return flash_write_cfiword (info, wp, cword);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_real_protect (flash_info_t * info, long sector, int prot)
-{
- int retcode = 0;
-
- flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
- if (prot)
- flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
- else
- flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
-
- if ((retcode =
- flash_full_status_check (info, sector, info->erase_blk_tout,
- prot ? "protect" : "unprotect")) == 0) {
-
- info->protect[sector] = prot;
- /* Intel's unprotect unprotects all locking */
- if (prot == 0) {
- int i;
-
- for (i = 0; i < info->sector_count; i++) {
- if (info->protect[i])
- flash_real_protect (info, i, 1);
- }
- }
- }
-
- return retcode;
-}
-
-/*-----------------------------------------------------------------------
- * wait for XSR.7 to be set. Time out with an error if it does not.
- * This routine does not set the flash to read-array mode.
- */
-static int flash_status_check (flash_info_t * info, ulong sector, ulong tout,
- char *prompt)
-{
- ulong start;
-
- /* Wait for command completion */
- start = get_timer (0);
- while (!flash_isset (info, sector, 0, FLASH_STATUS_DONE)) {
- if (get_timer (start) > info->erase_blk_tout) {
- printf ("Flash %s timeout at address %lx\n", prompt,
- info->start[sector]);
- flash_write_cmd (info, sector, 0, FLASH_CMD_RESET);
- return ERR_TIMOUT;
- }
- }
- return ERR_OK;
-}
-
-/*-----------------------------------------------------------------------
- * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
- * This routine sets the flash to read-array mode.
- */
-static int flash_full_status_check (flash_info_t * info, ulong sector,
- ulong tout, char *prompt)
-{
- int retcode;
-
- retcode = flash_status_check (info, sector, tout, prompt);
- if ((retcode == ERR_OK)
- && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
- retcode = ERR_INVAL;
- printf ("Flash %s error at address %lx\n", prompt,
- info->start[sector]);
- if (flash_isset
- (info, sector, 0,
- FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
- printf ("Command Sequence Error.\n");
- } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) {
- printf ("Block Erase Error.\n");
- retcode = ERR_NOT_ERASED;
- } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) {
- printf ("Locking Error\n");
- }
- if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
- printf ("Block locked.\n");
- retcode = ERR_PROTECTED;
- }
- if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
- printf ("Vpp Low Error.\n");
- }
- flash_write_cmd (info, sector, 0, FLASH_CMD_RESET);
- return retcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
-{
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- cword->c = c;
- break;
- case FLASH_CFI_16BIT:
- cword->w = (cword->w << 8) | c;
- break;
- case FLASH_CFI_32BIT:
- cword->l = (cword->l << 8) | c;
- }
-}
-
-/*-----------------------------------------------------------------------
- * make a proper sized command based on the port and chip widths
- */
-static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
-{
- /*int i; */
- uchar *cp = (uchar *) cmdbuf;
-
- /* for(i=0; i< info->portwidth; i++) */
- /* *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; */
- if (info->portwidth == FLASH_CFI_8BIT
- && info->chipwidth == FLASH_CFI_16BIT) {
- cp[0] = cmd;
- } else if (info->portwidth == FLASH_CFI_16BIT
- && info->chipwidth == FLASH_CFI_16BIT) {
- cp[0] = '\0';
- cp[1] = cmd;
- };
-}
-
-/*
- * Write a proper sized command to the correct address
- */
-static void flash_write_cmd (flash_info_t * info, int sect, uchar offset,
- uchar cmd)
-{
-
- volatile cfiptr_t addr;
- cfiword_t cword;
-
- addr.cp = flash_make_addr (info, sect, offset);
- flash_make_cmd (info, cmd, &cword);
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- *addr.cp = cword.c;
- break;
- case FLASH_CFI_16BIT:
- *addr.wp = cword.w;
- break;
- case FLASH_CFI_32BIT:
- *addr.lp = cword.l;
- break;
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_isequal (flash_info_t * info, int sect, uchar offset,
- uchar cmd)
-{
- cfiptr_t cptr;
- cfiword_t cword;
- int retval;
-
- cptr.cp = flash_make_addr (info, sect, offset);
- flash_make_cmd (info, cmd, &cword);
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- retval = (cptr.cp[0] == cword.c);
- break;
- case FLASH_CFI_16BIT:
- retval = (cptr.wp[0] == cword.w);
- break;
- case FLASH_CFI_32BIT:
- retval = (cptr.lp[0] == cword.l);
- break;
- default:
- retval = 0;
- break;
- }
- return retval;
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_isset (flash_info_t * info, int sect, uchar offset,
- uchar cmd)
-{
- cfiptr_t cptr;
- cfiword_t cword;
- int retval;
-
- cptr.cp = flash_make_addr (info, sect, offset);
- flash_make_cmd (info, cmd, &cword);
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- retval = ((cptr.cp[0] & cword.c) == cword.c);
- break;
- case FLASH_CFI_16BIT:
- retval = ((cptr.wp[0] & cword.w) == cword.w);
- break;
- case FLASH_CFI_32BIT:
- retval = ((cptr.lp[0] & cword.l) == cword.l);
- break;
- default:
- retval = 0;
- break;
- }
- return retval;
-}
-
-/*-----------------------------------------------------------------------
- * detect if flash is compatible with the Common Flash Interface (CFI)
- * http://www.jedec.org/download/search/jesd68.pdf
- *
-*/
-static int flash_detect_cfi (flash_info_t * info)
-{
-
-#if 0
- for (info->portwidth = FLASH_CFI_8BIT;
- info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) {
- for (info->chipwidth = FLASH_CFI_BY8;
- info->chipwidth <= info->portwidth;
- info->chipwidth <<= 1) {
- flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
- flash_write_cmd (info, 0, FLASH_OFFSET_CFI,
- FLASH_CMD_CFI);
- if (flash_isequal
- (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
- && flash_isequal (info, 0,
- FLASH_OFFSET_CFI_RESP + 1, 'R')
- && flash_isequal (info, 0,
- FLASH_OFFSET_CFI_RESP + 2, 'Y'))
- return 1;
- }
- }
-#endif
- flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
- flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
- if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') &&
- flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
- flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
- return 1;
- } else {
- return 0;
- };
-}
-
-/*
- * The following code cannot be run from FLASH!
- *
- */
-static ulong flash_get_size (ulong base, int banknum)
-{
- flash_info_t *info = &flash_info[banknum];
- int i, j;
- int sect_cnt;
- unsigned long sector;
- unsigned long tmp;
- int size_ratio;
- uchar num_erase_regions;
- int erase_region_size;
- int erase_region_count;
-
- info->start[0] = base;
-
- if (flash_detect_cfi (info)) {
-#ifdef DEBUG_FLASH
- printf ("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
-#endif
- size_ratio = 1; /* info->portwidth / info->chipwidth; */
- num_erase_regions =
- flash_read_uchar (info,
- FLASH_OFFSET_NUM_ERASE_REGIONS);
-#ifdef DEBUG_FLASH
- printf ("found %d erase regions\n", num_erase_regions);
-#endif
- sect_cnt = 0;
- sector = base;
- for (i = 0; i < num_erase_regions; i++) {
- if (i > NUM_ERASE_REGIONS) {
- printf ("%d erase regions found, only %d used\n", num_erase_regions, NUM_ERASE_REGIONS);
- break;
- }
- tmp = flash_read_long (info, 0,
- FLASH_OFFSET_ERASE_REGIONS);
- erase_region_count = (tmp & 0xffff) + 1;
- tmp >>= 16;
- erase_region_size =
- (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
- for (j = 0; j < erase_region_count; j++) {
- info->start[sect_cnt] = sector;
- sector += (erase_region_size * size_ratio);
- info->protect[sect_cnt] =
- flash_isset (info, sect_cnt,
- FLASH_OFFSET_PROTECT,
- FLASH_STATUS_PROTECT);
- sect_cnt++;
- }
- }
-
- info->sector_count = sect_cnt;
- /* multiply the size by the number of chips */
- info->size =
- (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) *
- size_ratio;
- info->buffer_size =
- (1 <<
- flash_read_ushort (info, 0,
- FLASH_OFFSET_BUFFER_SIZE));
- tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
- info->erase_blk_tout =
- (tmp *
- (1 <<
- flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
- tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
- info->buffer_write_tout =
- (tmp *
- (1 <<
- flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
- tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
- info->write_tout =
- (tmp *
- (1 <<
- flash_read_uchar (info,
- FLASH_OFFSET_WMAX_TOUT))) / 1000;
- info->flash_id = FLASH_MAN_CFI;
- }
-
- flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
- return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_write_cfiword (flash_info_t * info, ulong dest,
- cfiword_t cword)
-{
- cfiptr_t cptr;
- int flag;
-
- cptr.cp = (uchar *) dest;
-
- /* Check if Flash is (sufficiently) erased */
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- flag = ((cptr.cp[0] & cword.c) == cword.c);
- break;
- case FLASH_CFI_16BIT:
- flag = ((cptr.wp[0] & cword.w) == cword.w);
- break;
- case FLASH_CFI_32BIT:
- flag = ((cptr.lp[0] & cword.l) == cword.l);
- break;
- default:
- return 2;
- }
- if (!flag)
- return 2;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
-
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- cptr.cp[0] = cword.c;
- break;
- case FLASH_CFI_16BIT:
- cptr.wp[0] = cword.w;
- break;
- case FLASH_CFI_32BIT:
- cptr.lp[0] = cword.l;
- break;
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- return flash_full_status_check (info, 0, info->write_tout, "write");
-}
-
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/* loop through the sectors from the highest address
- * when the passed address is greater or equal to the sector address
- * we have a match
- */
-static int find_sector (flash_info_t * info, ulong addr)
-{
- int sector;
-
- for (sector = info->sector_count - 1; sector >= 0; sector--) {
- if (addr >= info->start[sector])
- break;
- }
- return sector;
-}
-
-static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
- int len)
-{
-
- int sector;
- int cnt;
- int retcode;
- volatile cfiptr_t src;
- volatile cfiptr_t dst;
-
- src.cp = cp;
- dst.cp = (uchar *) dest;
- sector = find_sector (info, dest);
- flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
- if ((retcode =
- flash_status_check (info, sector, info->buffer_write_tout,
- "write to buffer")) == ERR_OK) {
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- cnt = len;
- break;
- case FLASH_CFI_16BIT:
- cnt = len >> 1;
- break;
- case FLASH_CFI_32BIT:
- cnt = len >> 2;
- break;
- default:
- return ERR_INVAL;
- break;
- }
- flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
- while (cnt-- > 0) {
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- *dst.cp++ = *src.cp++;
- break;
- case FLASH_CFI_16BIT:
- *dst.wp++ = *src.wp++;
- break;
- case FLASH_CFI_32BIT:
- *dst.lp++ = *src.lp++;
- break;
- default:
- return ERR_INVAL;
- break;
- }
- }
- flash_write_cmd (info, sector, 0,
- FLASH_CMD_WRITE_BUFFER_CONFIRM);
- retcode =
- flash_full_status_check (info, sector,
- info->buffer_write_tout,
- "buffer write");
- }
- flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- return retcode;
-}
-#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
+++ /dev/null
-/*
- * init.S: Stubs for ppcboot initialization
- *
- * Copyright 2002 Mind NV
- *
- * http://www.mind.be/
- *
- * Author : Peter De Schrijver (p2@mind.be)
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL) version 2, incorporated herein by
- * reference. Drivers based on or derived from this code fall under the GPL
- * and must retain the authorship, copyright and this license notice. This
- * file is not a complete program and may only be used when the entire
- * program is licensed under the GPL.
- *
- */
-
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- blr
+++ /dev/null
-/*
- * (C) Copyright 2003
- * AMIRIX Systems Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <pci.h>
-
-#define PCI_MEM_82559ER_CSR_BASE 0x30200000
-#define PCI_IO_82559ER_CSR_BASE 0x40000200
-
-/** AP1100 specific values */
-#define PSII_BASE 0x30000000 /**< PowerSpan II dual bridge local bus register address */
-#define PSII_CONFIG_ADDR 0x30000290 /**< PowerSpan II Configuration Cycle Address configuration register */
-#define PSII_CONFIG_DATA 0x30000294 /**< PowerSpan II Configuration Cycle Data register. */
-#define PSII_CONFIG_DEST_PCI2 0x01000000 /**< PowerSpan II configuration cycle destination selection, set for PCI2 bus */
-#define PSII_PCI_MEM_BASE 0x30200000 /**< Local Bus address for start of PCI memory space on PCI2 bus. */
-#define PSII_PCI_MEM_SIZE 0x1BE00000 /**< PCI Memory space about 510 Meg. */
-#define AP1000_SYS_MEM_START 0x00000000 /**< System memory starts at 0. */
-#define AP1000_SYS_MEM_SIZE 0x08000000 /**< System memory is 128 Meg. */
-
-/* static int G_verbosity_level = 1; */
-#define G_verbosity_level 1
-
-void write1 (unsigned long addr, unsigned char val)
-{
- volatile unsigned char *p = (volatile unsigned char *) addr;
-
- if (G_verbosity_level > 1)
- printf ("write1: addr=%08x val=%02x\n", (unsigned int) addr,
- val);
- *p = val;
- asm ("eieio");
-}
-
-unsigned char read1 (unsigned long addr)
-{
- unsigned char val;
- volatile unsigned char *p = (volatile unsigned char *) addr;
-
- if (G_verbosity_level > 1)
- printf ("read1: addr=%08x ", (unsigned int) addr);
- val = *p;
- asm ("eieio");
- if (G_verbosity_level > 1)
- printf ("val=%08x\n", val);
- return val;
-}
-
-void write2 (unsigned long addr, unsigned short val)
-{
- volatile unsigned short *p = (volatile unsigned short *) addr;
-
- if (G_verbosity_level > 1)
- printf ("write2: addr=%08x val=%04x -> *p=%04x\n",
- (unsigned int) addr, val,
- ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8));
-
- *p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
- asm ("eieio");
-}
-
-unsigned short read2 (unsigned long addr)
-{
- unsigned short val;
- volatile unsigned short *p = (volatile unsigned short *) addr;
-
- if (G_verbosity_level > 1)
- printf ("read2: addr=%08x ", (unsigned int) addr);
- val = *p;
- val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
- asm ("eieio");
- if (G_verbosity_level > 1)
- printf ("*p=%04x -> val=%04x\n",
- ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8), val);
- return val;
-}
-
-void write4 (unsigned long addr, unsigned long val)
-{
- volatile unsigned long *p = (volatile unsigned long *) addr;
-
- if (G_verbosity_level > 1)
- printf ("write4: addr=%08x val=%08x -> *p=%08x\n",
- (unsigned int) addr, (unsigned int) val,
- (unsigned int) (((val & 0xFF000000) >> 24) |
- ((val & 0x000000FF) << 24) |
- ((val & 0x00FF0000) >> 8) |
- ((val & 0x0000FF00) << 8)));
-
- *p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
- ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
- asm ("eieio");
-}
-
-unsigned long read4 (unsigned long addr)
-{
- unsigned long val;
- volatile unsigned long *p = (volatile unsigned long *) addr;
-
- if (G_verbosity_level > 1)
- printf ("read4: addr=%08x", (unsigned int) addr);
-
- val = *p;
- val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
- ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
- asm ("eieio");
-
- if (G_verbosity_level > 1)
- printf ("*p=%04x -> val=%04x\n",
- (unsigned int) (((val & 0xFF000000) >> 24) |
- ((val & 0x000000FF) << 24) |
- ((val & 0x00FF0000) >> 8) |
- ((val & 0x0000FF00) << 8)),
- (unsigned int) val);
- return val;
-}
-
-void write4be (unsigned long addr, unsigned long val)
-{
- volatile unsigned long *p = (volatile unsigned long *) addr;
-
- if (G_verbosity_level > 1)
- printf ("write4: addr=%08x val=%08x\n", (unsigned int) addr,
- (unsigned int) val);
- *p = val;
- asm ("eieio");
-}
-
-/** One byte configuration write on PSII.
- * Currently fixes destination PCI bus to PCI2, onboard
- * pci.
- * @param hose PCI Host controller information. Ignored.
- * @param dev Encoded PCI device/Bus and Function value.
- * @param reg PCI Configuration register number.
- * @param val Address of location for received byte.
- * @return Always Zero.
- */
-static int psII_read_config_byte (struct pci_controller *hose,
- pci_dev_t dev, int reg, u8 * val)
-{
- write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
- (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
-
- *val = read1 (PSII_CONFIG_DATA + (reg & 0x03));
- return (0);
-}
-
-/** One byte configuration write on PSII.
- * Currently fixes destination bus to PCI2, onboard
- * pci.
- * @param hose PCI Host controller information. Ignored.
- * @param dev Encoded PCI device/Bus and Function value.
- * @param reg PCI Configuration register number.
- * @param val Output byte.
- * @return Always Zero.
- */
-static int psII_write_config_byte (struct pci_controller *hose,
- pci_dev_t dev, int reg, u8 val)
-{
- write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
- (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
-
- write1 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned char) val);
-
- return (0);
-}
-
-/** One word (16 bit) configuration read on PSII.
- * Currently fixes destination PCI bus to PCI2, onboard
- * pci.
- * @param hose PCI Host controller information. Ignored.
- * @param dev Encoded PCI device/Bus and Function value.
- * @param reg PCI Configuration register number.
- * @param val Address of location for received word.
- * @return Always Zero.
- */
-static int psII_read_config_word (struct pci_controller *hose,
- pci_dev_t dev, int reg, u16 * val)
-{
- write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
- (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
-
- *val = read2 (PSII_CONFIG_DATA + (reg & 0x03));
- return (0);
-}
-
-/** One word (16 bit) configuration write on PSII.
- * Currently fixes destination bus to PCI2, onboard
- * pci.
- * @param hose PCI Host controller information. Ignored.
- * @param dev Encoded PCI device/Bus and Function value.
- * @param reg PCI Configuration register number.
- * @param val Output word.
- * @return Always Zero.
- */
-static int psII_write_config_word (struct pci_controller *hose,
- pci_dev_t dev, int reg, u16 val)
-{
- write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
- (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
-
- write2 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned short) val);
-
- return (0);
-}
-
-/** One DWord (32 bit) configuration read on PSII.
- * Currently fixes destination PCI bus to PCI2, onboard
- * pci.
- * @param hose PCI Host controller information. Ignored.
- * @param dev Encoded PCI device/Bus and Function value.
- * @param reg PCI Configuration register number.
- * @param val Address of location for received byte.
- * @return Always Zero.
- */
-static int psII_read_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int reg, u32 * val)
-{
- write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
- (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
-
- *val = read4 (PSII_CONFIG_DATA);
- return (0);
-}
-
-/** One DWord (32 bit) configuration write on PSII.
- * Currently fixes destination bus to PCI2, onboard
- * pci.
- * @param hose PCI Host controller information. Ignored.
- * @param dev Encoded PCI device/Bus and Function value.
- * @param reg PCI Configuration register number.
- * @param val Output Dword.
- * @return Always Zero.
- */
-static int psII_write_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int reg, u32 val)
-{
- write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
- (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
-
- write4 (PSII_CONFIG_DATA, (unsigned long) val);
-
- return (0);
-}
-
-static struct pci_config_table ap1000_config_table[] = {
-#ifdef CONFIG_AP1000
- {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_BUS (CONFIG_SYS_ETH_DEV_FN), PCI_DEV (CONFIG_SYS_ETH_DEV_FN),
- PCI_FUNC (CONFIG_SYS_ETH_DEV_FN),
- pci_cfgfunc_config_device,
- {CONFIG_SYS_ETH_IOBASE, CONFIG_SYS_ETH_MEMBASE,
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
-#endif
- {}
-};
-
-static struct pci_controller psII_hose = {
- config_table:ap1000_config_table,
-};
-
-void pci_init_board (void)
-{
- struct pci_controller *hose = &psII_hose;
-
- /*
- * Register the hose
- */
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- /* System memory space */
- pci_set_region (hose->regions + 0,
- AP1000_SYS_MEM_START, AP1000_SYS_MEM_START,
- AP1000_SYS_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- /* PCI Memory space */
- pci_set_region (hose->regions + 1,
- PSII_PCI_MEM_BASE, PSII_PCI_MEM_BASE,
- PSII_PCI_MEM_SIZE, PCI_REGION_MEM);
-
- /* No IO Memory space - for now */
-
- pci_set_ops (hose,
- psII_read_config_byte,
- psII_read_config_word,
- psII_read_config_dword,
- psII_write_config_byte,
- psII_write_config_word, psII_write_config_dword);
-
- hose->region_count = 2;
-
- pci_register_hose (hose);
-
- hose->last_busno = pci_hose_scan (hose);
-}
+++ /dev/null
-/**
- * @file powerspan.c Source file for PowerSpan II code.
- */
-
-/*
- * (C) Copyright 2005
- * AMIRIX Systems Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include "powerspan.h"
-#define tolower(x) x
-#include "ap1000.h"
-
-#ifdef INCLUDE_PCI
-
-/** Write one byte with byte swapping.
- * @param addr [IN] the address to write to
- * @param val [IN] the value to write
- */
-void write1 (unsigned long addr, unsigned char val)
-{
- volatile unsigned char *p = (volatile unsigned char *) addr;
-
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("write1: addr=%08x val=%02x\n", addr, val);
- }
-#endif
- *p = val;
- PSII_SYNC ();
-}
-
-/** Read one byte with byte swapping.
- * @param addr [IN] the address to read from
- * @return the value at addr
- */
-unsigned char read1 (unsigned long addr)
-{
- unsigned char val;
- volatile unsigned char *p = (volatile unsigned char *) addr;
-
- val = *p;
- PSII_SYNC ();
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("read1: addr=%08x val=%02x\n", addr, val);
- }
-#endif
- return val;
-}
-
-/** Write one 2-byte word with byte swapping.
- * @param addr [IN] the address to write to
- * @param val [IN] the value to write
- */
-void write2 (unsigned long addr, unsigned short val)
-{
- volatile unsigned short *p = (volatile unsigned short *) addr;
-
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("write2: addr=%08x val=%04x -> *p=%04x\n", addr, val,
- ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8));
- }
-#endif
- *p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
- PSII_SYNC ();
-}
-
-/** Read one 2-byte word with byte swapping.
- * @param addr [IN] the address to read from
- * @return the value at addr
- */
-unsigned short read2 (unsigned long addr)
-{
- unsigned short val;
- volatile unsigned short *p = (volatile unsigned short *) addr;
-
- val = *p;
- val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
- PSII_SYNC ();
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("read2: addr=%08x *p=%04x -> val=%04x\n", addr, *p,
- val);
- }
-#endif
- return val;
-}
-
-/** Write one 4-byte word with byte swapping.
- * @param addr [IN] the address to write to
- * @param val [IN] the value to write
- */
-void write4 (unsigned long addr, unsigned long val)
-{
- volatile unsigned long *p = (volatile unsigned long *) addr;
-
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("write4: addr=%08x val=%08x -> *p=%08x\n", addr, val,
- ((val & 0xFF000000) >> 24) |
- ((val & 0x000000FF) << 24) |
- ((val & 0x00FF0000) >> 8) |
- ((val & 0x0000FF00) << 8));
- }
-#endif
- *p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
- ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
- PSII_SYNC ();
-}
-
-/** Read one 4-byte word with byte swapping.
- * @param addr [IN] the address to read from
- * @return the value at addr
- */
-unsigned long read4 (unsigned long addr)
-{
- unsigned long val;
- volatile unsigned long *p = (volatile unsigned long *) addr;
-
- val = *p;
- val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
- ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
- PSII_SYNC ();
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("read4: addr=%08x *p=%08x -> val=%08x\n", addr, *p,
- val);
- }
-#endif
- return val;
-}
-
-int PCIReadConfig (int bus, int dev, int fn, int reg, int width,
- unsigned long *val)
-{
- unsigned int conAdrVal;
- unsigned int conDataReg = REG_CONFIG_DATA;
- unsigned int status;
- int ret_val = 0;
-
-
- /* DEST bit hardcoded to 1: local pci is PCI-2 */
- /* TYPE bit is hardcoded to 1: all config cycles are local */
- conAdrVal = (1 << 24)
- | ((bus & 0xFF) << 16)
- | ((dev & 0xFF) << 11)
- | ((fn & 0x07) << 8)
- | (reg & 0xFC);
-
- /* clear any pending master aborts */
- write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
-
- /* Load the conAdrVal value first, then read from pb_conf_data */
- write4 (REG_CONFIG_ADDRESS, conAdrVal);
- PSII_SYNC ();
-
-
- /* Note: documentation does not match the pspan library code */
- /* Note: *pData comes back as -1 if device is not present */
- switch (width) {
- case 4:
- *(unsigned int *) val = read4 (conDataReg);
- break;
- case 2:
- *(unsigned short *) val = read2 (conDataReg);
- break;
- case 1:
- *(unsigned char *) val = read1 (conDataReg);
- break;
- default:
- ret_val = ILLEGAL_REG_OFFSET;
- break;
- }
- PSII_SYNC ();
-
- /* clear any pending master aborts */
- status = read4 (REG_P1_CSR);
- if (status & CLEAR_MASTER_ABORT) {
- ret_val = NO_DEVICE_FOUND;
- write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
- }
-
- return ret_val;
-}
-
-
-int PCIWriteConfig (int bus, int dev, int fn, int reg, int width,
- unsigned long val)
-{
- unsigned int conAdrVal;
- unsigned int conDataReg = REG_CONFIG_DATA;
- unsigned int status;
- int ret_val = 0;
-
-
- /* DEST bit hardcoded to 1: local pci is PCI-2 */
- /* TYPE bit is hardcoded to 1: all config cycles are local */
- conAdrVal = (1 << 24)
- | ((bus & 0xFF) << 16)
- | ((dev & 0xFF) << 11)
- | ((fn & 0x07) << 8)
- | (reg & 0xFC);
-
- /* clear any pending master aborts */
- write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
-
- /* Load the conAdrVal value first, then read from pb_conf_data */
- write4 (REG_CONFIG_ADDRESS, conAdrVal);
- PSII_SYNC ();
-
-
- /* Note: documentation does not match the pspan library code */
- /* Note: *pData comes back as -1 if device is not present */
- switch (width) {
- case 4:
- write4 (conDataReg, val);
- break;
- case 2:
- write2 (conDataReg, val);
- break;
- case 1:
- write1 (conDataReg, val);
- break;
- default:
- ret_val = ILLEGAL_REG_OFFSET;
- break;
- }
- PSII_SYNC ();
-
- /* clear any pending master aborts */
- status = read4 (REG_P1_CSR);
- if (status & CLEAR_MASTER_ABORT) {
- ret_val = NO_DEVICE_FOUND;
- write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
- }
-
- return ret_val;
-}
-
-
-int pci_read_config_byte (int bus, int dev, int fn, int reg,
- unsigned char *val)
-{
- unsigned long read_val;
- int ret_val;
-
- ret_val = PCIReadConfig (bus, dev, fn, reg, 1, &read_val);
- *val = read_val & 0xFF;
-
- return ret_val;
-}
-
-int pci_write_config_byte (int bus, int dev, int fn, int reg,
- unsigned char val)
-{
- return PCIWriteConfig (bus, dev, fn, reg, 1, val);
-}
-
-int pci_read_config_word (int bus, int dev, int fn, int reg,
- unsigned short *val)
-{
- unsigned long read_val;
- int ret_val;
-
- ret_val = PCIReadConfig (bus, dev, fn, reg, 2, &read_val);
- *val = read_val & 0xFFFF;
-
- return ret_val;
-}
-
-int pci_write_config_word (int bus, int dev, int fn, int reg,
- unsigned short val)
-{
- return PCIWriteConfig (bus, dev, fn, reg, 2, val);
-}
-
-int pci_read_config_dword (int bus, int dev, int fn, int reg,
- unsigned long *val)
-{
- return PCIReadConfig (bus, dev, fn, reg, 4, val);
-}
-
-int pci_write_config_dword (int bus, int dev, int fn, int reg,
- unsigned long val)
-{
- return PCIWriteConfig (bus, dev, fn, reg, 4, val);
-}
-
-#endif /* INCLUDE_PCI */
-
-int I2CAccess (unsigned char theI2CAddress, unsigned char theDevCode,
- unsigned char theChipSel, unsigned char *theValue, int RWFlag)
-{
- int ret_val = 0;
- unsigned int reg_value;
-
- reg_value = PowerSpanRead (REG_I2C_CSR);
-
- if (reg_value & I2C_CSR_ACT) {
- printf ("Error: I2C busy\n");
- ret_val = I2C_BUSY;
- } else {
- reg_value = ((theI2CAddress & 0xFF) << 24)
- | ((theDevCode & 0x0F) << 12)
- | ((theChipSel & 0x07) << 9)
- | I2C_CSR_ERR;
- if (RWFlag == I2C_WRITE) {
- reg_value |= I2C_CSR_RW | ((*theValue & 0xFF) << 16);
- }
-
- PowerSpanWrite (REG_I2C_CSR, reg_value);
- udelay (1);
-
- do {
- reg_value = PowerSpanRead (REG_I2C_CSR);
-
- if ((reg_value & I2C_CSR_ACT) == 0) {
- if (reg_value & I2C_CSR_ERR) {
- ret_val = I2C_ERR;
- } else {
- *theValue =
- (reg_value & I2C_CSR_DATA) >>
- 16;
- }
- }
- } while (reg_value & I2C_CSR_ACT);
- }
-
- return ret_val;
-}
-
-int EEPROMRead (unsigned char theI2CAddress, unsigned char *theValue)
-{
- return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL,
- theValue, I2C_READ);
-}
-
-int EEPROMWrite (unsigned char theI2CAddress, unsigned char theValue)
-{
- return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL,
- &theValue, I2C_WRITE);
-}
-
-int do_eeprom (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- char cmd;
- int ret_val = 0;
- unsigned int address = 0;
- unsigned char value = 1;
- unsigned char read_value;
- int ii;
- int error = 0;
- unsigned char *mem_ptr;
- unsigned char default_eeprom[] = EEPROM_DEFAULT;
-
- if (argc < 2) {
- goto usage;
- }
-
- cmd = argv[1][0];
- if (argc > 2) {
- address = simple_strtoul (argv[2], NULL, 16);
- if (argc > 3) {
- value = simple_strtoul (argv[3], NULL, 16) & 0xFF;
- }
- }
-
- switch (cmd) {
- case 'r':
- if (address > 256) {
- printf ("Illegal Address\n");
- goto usage;
- }
- printf ("@0x%x: ", address);
- for (ii = 0; ii < value; ii++) {
- if (EEPROMRead (address + ii, &read_value) !=
- 0) {
- printf ("Read Error\n");
- } else {
- printf ("0x%02x ", read_value);
- }
-
- if (((ii + 1) % 16) == 0) {
- printf ("\n");
- }
- }
- printf ("\n");
- break;
- case 'w':
- if (address > 256) {
- printf ("Illegal Address\n");
- goto usage;
- }
- if (argc < 4) {
- goto usage;
- }
- if (EEPROMWrite (address, value) != 0) {
- printf ("Write Error\n");
- }
- break;
- case 'g':
- if (argc != 3) {
- goto usage;
- }
- mem_ptr = (unsigned char *) address;
- for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
- ii++) {
- if (EEPROMRead (ii, &read_value) != 0) {
- printf ("Read Error\n");
- error = 1;
- } else {
- *mem_ptr = read_value;
- mem_ptr++;
- }
- }
- break;
- case 'p':
- if (argc != 3) {
- goto usage;
- }
- mem_ptr = (unsigned char *) address;
- for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
- ii++) {
- if (EEPROMWrite (ii, *mem_ptr) != 0) {
- printf ("Write Error\n");
- error = 1;
- }
-
- mem_ptr++;
- }
- break;
- case 'd':
- if (argc != 2) {
- goto usage;
- }
- for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
- ii++) {
- if (EEPROMWrite (ii, default_eeprom[ii]) != 0) {
- printf ("Write Error\n");
- error = 1;
- }
- }
- break;
- default:
- goto usage;
- }
-
- goto done;
- usage:
- printf ("Usage:\n%s\n", cmdtp->help);
-
- done:
- return ret_val;
-
-}
-
-U_BOOT_CMD (eeprom, 4, 0, do_eeprom,
- "read/write/copy to/from the PowerSpan II eeprom",
- "eeprom r OFF [NUM]\n"
- " - read NUM words starting at OFF\n"
- "eeprom w OFF VAL\n"
- " - write word VAL at offset OFF\n"
- "eeprom g ADD\n"
- " - store contents of eeprom at address ADD\n"
- "eeprom p ADD\n"
- " - put data stored at address ADD into the eeprom\n"
- "eeprom d\n" " - return eeprom to default contents");
-
-unsigned int PowerSpanRead (unsigned int theOffset)
-{
- volatile unsigned int *ptr =
- (volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
- unsigned int ret_val;
-
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("PowerSpanRead: offset=%08x ", theOffset);
- }
-#endif
- ret_val = *ptr;
- PSII_SYNC ();
-
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("value=%08x\n", ret_val);
- }
-#endif
-
- return ret_val;
-}
-
-void PowerSpanWrite (unsigned int theOffset, unsigned int theValue)
-{
- volatile unsigned int *ptr =
- (volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("PowerSpanWrite: offset=%08x val=%02x\n", theOffset,
- theValue);
- }
-#endif
- *ptr = theValue;
- PSII_SYNC ();
-}
-
-/**
- * Sets the indicated bits in the indicated register.
- * @param theOffset [IN] the register to access.
- * @param theMask [IN] bits set in theMask will be set in the register.
- */
-void PowerSpanSetBits (unsigned int theOffset, unsigned int theMask)
-{
- volatile unsigned int *ptr =
- (volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
- unsigned int register_value;
-
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("PowerSpanSetBits: offset=%08x mask=%02x\n",
- theOffset, theMask);
- }
-#endif
- register_value = *ptr;
- PSII_SYNC ();
-
- register_value |= theMask;
- *ptr = register_value;
- PSII_SYNC ();
-}
-
-/**
- * Clears the indicated bits in the indicated register.
- * @param theOffset [IN] the register to access.
- * @param theMask [IN] bits set in theMask will be cleared in the register.
- */
-void PowerSpanClearBits (unsigned int theOffset, unsigned int theMask)
-{
- volatile unsigned int *ptr =
- (volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
- unsigned int register_value;
-
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("PowerSpanClearBits: offset=%08x mask=%02x\n",
- theOffset, theMask);
- }
-#endif
- register_value = *ptr;
- PSII_SYNC ();
-
- register_value &= ~theMask;
- *ptr = register_value;
- PSII_SYNC ();
-}
-
-/**
- * Configures a slave image on the local bus, based on the parameters and some hardcoded system values.
- * Slave Images are images that cause the PowerSpan II to be a master on the PCI bus. Thus, they
- * are outgoing from the standpoint of the local bus.
- * @param theImageIndex [IN] the PowerSpan II image to set (assumed to be 0-7).
- * @param theBlockSize [IN] the block size of the image (as used by PowerSpan II: PB_SIx_CTL[BS]).
- * @param theMemIOFlag [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set.
- * @param theEndianness [IN] the endian bits for the image (already shifted, use defines).
- * @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size).
- * @param thePCIBaseAddr [IN] the PCI address for the image (assumed to be valid with provided block size).
- */
-int SetSlaveImage (int theImageIndex, unsigned int theBlockSize,
- int theMemIOFlag, int theEndianness,
- unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr)
-{
- unsigned int reg_offset = theImageIndex * PB_SLAVE_IMAGE_OFF;
- unsigned int reg_value = 0;
-
- /* Make sure that the Slave Image is disabled */
- PowerSpanClearBits ((REGS_PB_SLAVE_CSR + reg_offset),
- PB_SLAVE_CSR_IMG_EN);
-
- /* Setup the mask required for requested PB Slave Image configuration */
- reg_value = PB_SLAVE_CSR_TA_EN | theEndianness | (theBlockSize << 24);
- if (theMemIOFlag == PB_SLAVE_USE_MEM_IO) {
- reg_value |= PB_SLAVE_CSR_MEM_IO;
- }
-
- /* hardcoding the following:
- TA_EN = 1
- MD_EN = 0
- MODE = 0
- PRKEEP = 0
- RD_AMT = 0
- */
- PowerSpanWrite ((REGS_PB_SLAVE_CSR + reg_offset), reg_value);
-
- /* these values are not checked by software */
- PowerSpanWrite ((REGS_PB_SLAVE_BADDR + reg_offset), theLocalBaseAddr);
- PowerSpanWrite ((REGS_PB_SLAVE_TADDR + reg_offset), thePCIBaseAddr);
-
- /* Enable the Slave Image */
- PowerSpanSetBits ((REGS_PB_SLAVE_CSR + reg_offset),
- PB_SLAVE_CSR_IMG_EN);
-
- return 0;
-}
-
-/**
- * Configures a target image on the local bus, based on the parameters and some hardcoded system values.
- * Target Images are used when the PowerSpan II is acting as a target for an access. Thus, they
- * are incoming from the standpoint of the local bus.
- * In order to behave better on the host PCI bus, if thePCIBaseAddr is NULL (0x00000000), then the PCI
- * base address will not be updated; makes sense given that the hosts own memory should be mapped to
- * PCI address 0x00000000.
- * @param theImageIndex [IN] the PowerSpan II image to set.
- * @param theBlockSize [IN] the block size of the image (as used by PowerSpan II: Px_TIx_CTL[BS]).
- * @param theMemIOFlag [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set.
- * @param theEndianness [IN] the endian bits for the image (already shifted, use defines).
- * @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size).
- * @param thePCIBaseAddr [IN] the PCI address for the image (assumed to be valid with provided block size).
- */
-int SetTargetImage (int theImageIndex, unsigned int theBlockSize,
- int theMemIOFlag, int theEndianness,
- unsigned int theLocalBaseAddr,
- unsigned int thePCIBaseAddr)
-{
- unsigned int csr_reg_offset = theImageIndex * P1_TGT_IMAGE_OFF;
- unsigned int pci_reg_offset = theImageIndex * P1_BST_OFF;
- unsigned int reg_value = 0;
-
- /* Make sure that the Slave Image is disabled */
- PowerSpanClearBits ((REGS_P1_TGT_CSR + csr_reg_offset),
- PB_SLAVE_CSR_IMG_EN);
-
- /* Setup the mask required for requested PB Slave Image configuration */
- reg_value =
- PX_TGT_CSR_TA_EN | PX_TGT_CSR_BAR_EN | (theBlockSize << 24) |
- PX_TGT_CSR_RTT_READ | PX_TGT_CSR_WTT_WFLUSH | theEndianness;
- if (theMemIOFlag == PX_TGT_USE_MEM_IO) {
- reg_value |= PX_TGT_MEM_IO;
- }
-
- /* hardcoding the following:
- TA_EN = 1
- BAR_EN = 1
- MD_EN = 0
- MODE = 0
- DEST = 0
- RTT = 01010
- GBL = 0
- CI = 0
- WTT = 00010
- PRKEEP = 0
- MRA = 0
- RD_AMT = 0
- */
- PowerSpanWrite ((REGS_P1_TGT_CSR + csr_reg_offset), reg_value);
-
- PowerSpanWrite ((REGS_P1_TGT_TADDR + csr_reg_offset),
- theLocalBaseAddr);
-
- if (thePCIBaseAddr != (unsigned int) NULL) {
- PowerSpanWrite ((REGS_P1_BST + pci_reg_offset),
- thePCIBaseAddr);
- }
-
- /* Enable the Slave Image */
- PowerSpanSetBits ((REGS_P1_TGT_CSR + csr_reg_offset),
- PB_SLAVE_CSR_IMG_EN);
-
- return 0;
-}
-
-int do_bridge (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- char cmd;
- int ret_val = 1;
- unsigned int image_index;
- unsigned int block_size;
- unsigned int mem_io;
- unsigned int local_addr;
- unsigned int pci_addr;
- int endianness;
-
- if (argc != 8) {
- goto usage;
- }
-
- cmd = argv[1][0];
- image_index = simple_strtoul (argv[2], NULL, 16);
- block_size = simple_strtoul (argv[3], NULL, 16);
- mem_io = simple_strtoul (argv[4], NULL, 16);
- endianness = argv[5][0];
- local_addr = simple_strtoul (argv[6], NULL, 16);
- pci_addr = simple_strtoul (argv[7], NULL, 16);
-
-
- switch (cmd) {
- case 'i':
- if (tolower (endianness) == 'b') {
- endianness = PX_TGT_CSR_BIG_END;
- } else if (tolower (endianness) == 'l') {
- endianness = PX_TGT_CSR_TRUE_LEND;
- } else {
- goto usage;
- }
- SetTargetImage (image_index, block_size, mem_io,
- endianness, local_addr, pci_addr);
- break;
- case 'o':
- if (tolower (endianness) == 'b') {
- endianness = PB_SLAVE_CSR_BIG_END;
- } else if (tolower (endianness) == 'l') {
- endianness = PB_SLAVE_CSR_TRUE_LEND;
- } else {
- goto usage;
- }
- SetSlaveImage (image_index, block_size, mem_io,
- endianness, local_addr, pci_addr);
- break;
- default:
- goto usage;
- }
-
- goto done;
-usage:
- printf ("Usage:\n%s\n", cmdtp->help);
-
-done:
- return ret_val;
-}
+++ /dev/null
-/**
- * @file powerspan.h Header file for PowerSpan II code.
- */
-
-/*
- * (C) Copyright 2005
- * AMIRIX Systems Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef POWERSPAN_H
-#define POWERSPAN_H
-
-#define CLEAR_MASTER_ABORT 0xdeadbeef
-#define NO_DEVICE_FOUND -1
-#define ILLEGAL_REG_OFFSET -2
-#define I2C_BUSY -3
-#define I2C_ERR -4
-
-#define REG_P1_CSR 0x004
-#define REGS_P1_BST 0x018
-#define REG_P1_ERR_CSR 0x150
-#define REG_P1_MISC_CSR 0x160
-#define REGS_P1_TGT_CSR 0x100
-#define REGS_P1_TGT_TADDR 0x104
-#define REGS_PB_SLAVE_CSR 0x200
-#define REGS_PB_SLAVE_TADDR 0x204
-#define REGS_PB_SLAVE_BADDR 0x208
-#define REG_CONFIG_ADDRESS 0x290
-#define REG_CONFIG_DATA 0x294
-#define REG_PB_ERR_CSR 0x2B0
-#define REG_PB_MISC_CSR 0x2C0
-#define REG_MISC_CSR 0x400
-#define REG_I2C_CSR 0x408
-#define REG_RESET_CSR 0x40C
-#define REG_ISR0 0x410
-#define REG_ISR1 0x414
-#define REG_IER0 0x418
-#define REG_MBOX_MAP 0x420
-#define REG_HW_MAP 0x42C
-#define REG_IDR 0x444
-
-#define CSR_MEMORY_SPACE_ENABLE 0x00000002
-#define CSR_PCI_MASTER_ENABLE 0x00000004
-
-#define P1_BST_OFF 0x04
-
-#define PX_ERR_ERR_STATUS 0x01000000
-
-#define PX_MISC_CSR_MAX_RETRY_MASK 0x00000F00
-#define PX_MISC_CSR_MAX_RETRY 0x00000F00
-#define PX_MISC_REG_BAR_ENABLE 0x00008000
-#define PB_MISC_TEA_ENABLE 0x00000010
-#define PB_MISC_MAC_TEA 0x00000040
-
-#define P1_TGT_IMAGE_OFF 0x010
-#define PX_TGT_CSR_IMG_EN 0x80000000
-#define PX_TGT_CSR_TA_EN 0x40000000
-#define PX_TGT_CSR_BAR_EN 0x20000000
-#define PX_TGT_CSR_MD_EN 0x10000000
-#define PX_TGT_CSR_MODE 0x00800000
-#define PX_TGT_CSR_DEST 0x00400000
-#define PX_TGT_CSR_MEM_IO 0x00200000
-#define PX_TGT_CSR_GBL 0x00080000
-#define PX_TGT_CSR_CL 0x00040000
-#define PX_TGT_CSR_PRKEEP 0x00000080
-
-#define PX_TGT_CSR_BS_MASK 0x0F000000
-#define PX_TGT_MEM_IO 0x00200000
-#define PX_TGT_CSR_RTT_MASK 0x001F0000
-#define PX_TGT_CSR_RTT_READ 0x000A0000
-#define PX_TGT_CSR_WTT_MASK 0x00001F00
-#define PX_TGT_CSR_WTT_WFLUSH 0x00000200
-#define PX_TGT_CSR_END_MASK 0x00000060
-#define PX_TGT_CSR_BIG_END 0x00000040
-#define PX_TGT_CSR_TRUE_LEND 0x00000060
-#define PX_TGT_CSR_RDAMT_MASK 0x00000007
-
-#define PX_TGT_CSR_BS_64MB 0xa
-#define PX_TGT_CSR_BS_16MB 0x8
-
-#define PX_TGT_USE_MEM_IO 1
-#define PX_TGT_NOT_MEM_IO 0
-
-#define PB_SLAVE_IMAGE_OFF 0x010
-#define PB_SLAVE_CSR_IMG_EN 0x80000000
-#define PB_SLAVE_CSR_TA_EN 0x40000000
-#define PB_SLAVE_CSR_MD_EN 0x20000000
-#define PB_SLAVE_CSR_MODE 0x00800000
-#define PB_SLAVE_CSR_DEST 0x00400000
-#define PB_SLAVE_CSR_MEM_IO 0x00200000
-#define PB_SLAVE_CSR_PRKEEP 0x00000080
-
-#define PB_SLAVE_CSR_BS_MASK 0x1F000000
-#define PB_SLAVE_CSR_END_MASK 0x00000060
-#define PB_SLAVE_CSR_BIG_END 0x00000040
-#define PB_SLAVE_CSR_TRUE_LEND 0x00000060
-#define PB_SLAVE_CSR_RDAMT_MASK 0x00000007
-
-#define PB_SLAVE_USE_MEM_IO 1
-#define PB_SLAVE_NOT_MEM_IO 0
-
-
-#define MISC_CSR_PCI1_LOCK 0x00000080
-
-#define I2C_CSR_ADDR 0xFF000000 /* Specifies I2C Device Address to be Accessed */
-#define I2C_CSR_DATA 0x00FF0000 /* Specifies the Required Data for a Write */
-#define I2C_CSR_DEV_CODE 0x0000F000 /* Device Select. I2C 4-bit Device Code */
-#define I2C_CSR_CS 0x00000E00 /* Chip Select */
-#define I2C_CSR_RW 0x00000100 /* Read/Write */
-#define I2C_CSR_ACT 0x00000080 /* I2C Interface Active */
-#define I2C_CSR_ERR 0x00000040 /* Error */
-
-#define I2C_EEPROM_DEV 0xa
-#define I2C_EEPROM_CHIP_SEL 0
-
-#define I2C_READ 0
-#define I2C_WRITE 1
-
-#define RESET_CSR_EEPROM_LOAD 0x00000010
-
-#define ISR_CLEAR_ALL 0xFFFFFFFF
-
-#define IER0_DMA_INTS_EN 0x0F000000
-#define IER0_PCI_1_EN 0x00400000
-#define IER0_HW_INTS_EN 0x003F0000
-#define IER0_MB_INTS_EN 0x000000FF
-#define IER0_DEFAULT (IER0_DMA_INTS_EN | IER0_PCI_1_EN | IER0_HW_INTS_EN | IER0_MB_INTS_EN)
-
-#define MBOX_MAP_TO_INT4 0xCCCCCCCC
-
-#define HW_MAP_HW4_TO_INT4 0x000C0000
-
-#define IDR_PCI_A_OUT 0x40000000
-#define IDR_MBOX_OUT 0x10000000
-
-
-int pci_read_config_byte(int bus, int dev, int fn, int reg, unsigned char* val);
-int pci_write_config_byte(int bus, int dev, int fn, int reg, unsigned char val);
-int pci_read_config_word(int bus, int dev, int fn, int reg, unsigned short* val);
-int pci_write_config_word(int bus, int dev, int fn, int reg, unsigned short val);
-int pci_read_config_dword(int bus, int dev, int fn, int reg, unsigned long* val);
-int pci_write_config_dword(int bus, int dev, int fn, int reg, unsigned long val);
-
-unsigned int PowerSpanRead(unsigned int theOffset);
-void PowerSpanWrite(unsigned int theOffset, unsigned int theValue);
-
-int I2CAccess(unsigned char theI2CAddress, unsigned char theDevCode, unsigned char theChipSel, unsigned char* theValue, int RWFlag);
-
-int PCIWriteConfig(int bus, int dev, int fn, int reg, int width, unsigned long val);
-int PCIReadConfig(int bus, int dev, int fn, int reg, int width, unsigned long* val);
-
-int SetSlaveImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr);
-int SetTargetImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr);
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Peter De Schrijver (p2@mind.be), Mind Linux Solutions, NV.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <asm/u-boot.h>
-#include <asm/processor.h>
-#include <command.h>
-#include <config.h>
-
-#include <ns16550.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const NS16550_t COM_PORTS[] =
- { (NS16550_t) CONFIG_SYS_NS16550_COM1, (NS16550_t) CONFIG_SYS_NS16550_COM2 };
-
-#undef CONFIG_SYS_DUART_CHAN
-#define CONFIG_SYS_DUART_CHAN gComPort
-static int gComPort = 0;
-
-int serial_init (void)
-{
- int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
-
- (void) NS16550_init (COM_PORTS[0], clock_divisor);
- gComPort = 0;
-
- return 0;
-}
-
-void serial_putc (const char c)
-{
- if (c == '\n') {
- NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
- }
-
- NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
-}
-
-int serial_getc (void)
-{
- return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-int serial_tstc (void)
-{
- return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-void serial_setbrg (void)
-{
- int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
-
-#ifdef CONFIG_SYS_INIT_CHAN1
- NS16550_reinit (COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
- NS16550_reinit (COM_PORTS[1], clock_divisor);
-#endif
-}
-
-void serial_puts (const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
-#if defined(CONFIG_CMD_KGDB)
-void kgdb_serial_init (void)
-{
-}
-
-void putDebugChar (int c)
-{
- serial_putc (c);
-}
-
-void putDebugStr (const char *str)
-{
- serial_puts (str);
-}
-
-int getDebugChar (void)
-{
- return serial_getc ();
-}
-
-void kgdb_interruptible (int yes)
-{
- return;
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text)
- board/amirix/ap1000/init.o (.text)
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end__ = . ;
- PROVIDE (end = .);
-}
--- /dev/null
+#
+# Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += armadillo-800eva.o
+COBJS := $(COBJS-y)
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+
--- /dev/null
+/*
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+
+#define s_init_wait(cnt) \
+ ({ \
+ volatile u32 i = 0x10000 * cnt; \
+ while (i > 0) \
+ i--; \
+ })
+
+#define USBCR1 0xE605810A
+
+void s_init(void)
+{
+ struct r8a7740_rwdt *rwdt0 = (struct r8a7740_rwdt *)RWDT0_BASE;
+ struct r8a7740_rwdt *rwdt1 = (struct r8a7740_rwdt *)RWDT1_BASE;
+ struct r8a7740_cpg *cpg = (struct r8a7740_cpg *)CPG_BASE;
+ struct r8a7740_bsc *bsc = (struct r8a7740_bsc *)BSC_BASE;
+ struct r8a7740_ddrp *ddrp = (struct r8a7740_ddrp *)DDRP_BASE;
+ struct r8a7740_dbsc *dbsc = (struct r8a7740_dbsc *)DBSC_BASE;
+
+ /* Watchdog init */
+ writew(0xA500, &rwdt0->rwtcsra0);
+ writew(0xA500, &rwdt1->rwtcsra0);
+
+ /* CPG */
+ writel(0xFF800080, &cpg->rmstpcr4);
+ writel(0xFF800080, &cpg->smstpcr4);
+
+ /* USB clock */
+ writel(0x00000080, &cpg->usbckcr);
+ s_init_wait(1);
+
+ /* USBCR1 */
+ writew(0x0710, USBCR1);
+
+ /* FRQCR */
+ writel(0x00000000, &cpg->frqcrb);
+ writel(0x62030533, &cpg->frqcra);
+ writel(0x208A354E, &cpg->frqcrc);
+ writel(0x80331050, &cpg->frqcrb);
+ s_init_wait(1);
+
+ writel(0x00000000, &cpg->frqcrd);
+ s_init_wait(1);
+
+ /* SUBClk */
+ writel(0x0000010B, &cpg->subckcr);
+
+ /* PLL */
+ writel(0x00004004, &cpg->pllc01cr);
+ s_init_wait(1);
+
+ writel(0xa0000000, &cpg->pllc2cr);
+ s_init_wait(2);
+
+ /* BSC */
+ writel(0x0000001B, &bsc->cmncr);
+
+ writel(0x20000000, &dbsc->dbcmd);
+ writel(0x10009C40, &dbsc->dbcmd);
+ s_init_wait(1);
+
+ writel(0x00000007, &dbsc->dbkind);
+ writel(0x0E030A02, &dbsc->dbconf0);
+ writel(0x00000001, &dbsc->dbphytype);
+ writel(0x00000000, &dbsc->dbbl);
+ writel(0x00000006, &dbsc->dbtr0);
+ writel(0x00000005, &dbsc->dbtr1);
+ writel(0x00000000, &dbsc->dbtr2);
+ writel(0x00000006, &dbsc->dbtr3);
+ writel(0x00080006, &dbsc->dbtr4);
+ writel(0x00000015, &dbsc->dbtr5);
+ writel(0x0000000f, &dbsc->dbtr6);
+ writel(0x00000004, &dbsc->dbtr7);
+ writel(0x00000018, &dbsc->dbtr8);
+ writel(0x00000006, &dbsc->dbtr9);
+ writel(0x00000006, &dbsc->dbtr10);
+ writel(0x0000000F, &dbsc->dbtr11);
+ writel(0x0000000D, &dbsc->dbtr12);
+ writel(0x000000A0, &dbsc->dbtr13);
+ writel(0x000A0003, &dbsc->dbtr14);
+ writel(0x00000003, &dbsc->dbtr15);
+ writel(0x40005005, &dbsc->dbtr16);
+ writel(0x0C0C0000, &dbsc->dbtr17);
+ writel(0x00000200, &dbsc->dbtr18);
+ writel(0x00000040, &dbsc->dbtr19);
+ writel(0x00000001, &dbsc->dbrnk0);
+ writel(0x00000110, &dbsc->dbdficnt);
+ writel(0x00000101, &ddrp->funcctrl);
+ writel(0x00000001, &ddrp->dllctrl);
+ writel(0x00000186, &ddrp->zqcalctrl);
+ writel(0xB3440051, &ddrp->zqodtctrl);
+ writel(0x94449443, &ddrp->rdctrl);
+ writel(0x000000C0, &ddrp->rdtmg);
+ writel(0x00000101, &ddrp->fifoinit);
+ writel(0x02060506, &ddrp->outctrl);
+ writel(0x00004646, &ddrp->dqcalofs1);
+ writel(0x00004646, &ddrp->dqcalofs2);
+ writel(0x800000aa, &ddrp->dqcalexp);
+ writel(0x00000000, &ddrp->dllctrl);
+ writel(0x00000000, DDRPNCNT);
+
+ writel(0x0000000C, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x00000002, DDRPNCNT);
+
+ writel(0x0000000C, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x00000187, &ddrp->zqcalctrl);
+
+ writel(0x00009C40, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x00009C40, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x00000010, &dbsc->dbdficnt);
+ writel(0x02060507, &ddrp->outctrl);
+
+ writel(0x00009C40, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x21009C40, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x00009C40, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x00009C40, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x00009C40, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x00009C40, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x11000044, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x2A000000, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x2B000000, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+
+ writel(0x29000004, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+
+ writel(0x28001520, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x03000200, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x000001FF, &dbsc->dbrfcnf0);
+ writel(0x00010C30, &dbsc->dbrfcnf1);
+ writel(0x00000000, &dbsc->dbrfcnf2);
+
+ writel(0x00000001, &dbsc->dbrfen);
+ writel(0x00000001, &dbsc->dbacen);
+
+ /* BSC */
+ writel(0x00410400, &bsc->cs0bcr);
+ writel(0x00410400, &bsc->cs2bcr);
+ writel(0x00410400, &bsc->cs5bbcr);
+ writel(0x02CB0400, &bsc->cs6abcr);
+
+ writel(0x00000440, &bsc->cs0wcr);
+ writel(0x00000440, &bsc->cs2wcr);
+ writel(0x00000240, &bsc->cs5bwcr);
+ writel(0x00000240, &bsc->cs6awcr);
+
+ writel(0x00000005, &bsc->rbwtcnt);
+ writel(0x00000002, &bsc->cs0wcr2);
+ writel(0x00000002, &bsc->cs2wcr2);
+ writel(0x00000002, &bsc->cs4wcr2);
+}
+
+#define GPIO_ICCR (0xE60581A0)
+#define ICCR_15BIT (1 << 15) /* any time 1 */
+#define IIC0_CONTA (1 << 7)
+#define IIC0_CONTB (1 << 6)
+#define IIC1_CONTA (1 << 5)
+#define IIC1_CONTB (1 << 4)
+#define IIC0_PS33E (1 << 1)
+#define IIC1_PS33E (1 << 0)
+#define GPIO_ICCR_DATA \
+ (ICCR_15BIT | \
+ IIC0_CONTA | IIC0_CONTB | IIC1_CONTA | \
+ IIC1_CONTB | IIC0_PS33E | IIC1_PS33E)
+
+#define MSTPCR1 0xE6150134
+#define TMU0_MSTP125 (1 << 25)
+#define I2C0_MSTP116 (1 << 16)
+
+#define MSTPCR3 0xE615013C
+#define I2C1_MSTP323 (1 << 23)
+#define GETHER_MSTP309 (1 << 9)
+
+#define GPIO_SCIFA1_TXD (0xE60520C4)
+#define GPIO_SCIFA1_RXD (0xE60520C3)
+
+int board_early_init_f(void)
+{
+ /* TMU */
+ clrbits_le32(MSTPCR1, TMU0_MSTP125);
+
+ /* GETHER */
+ clrbits_le32(MSTPCR3, GETHER_MSTP309);
+
+ /* I2C 0/1 */
+ clrbits_le32(MSTPCR1, I2C0_MSTP116);
+ clrbits_le32(MSTPCR3, I2C1_MSTP323);
+
+ /* SCIFA1 */
+ writeb(1, GPIO_SCIFA1_TXD); /* SCIFA1_TXD */
+ writeb(1, GPIO_SCIFA1_RXD); /* SCIFA1_RXD */
+
+ /* IICCR */
+ writew(GPIO_ICCR_DATA, GPIO_ICCR);
+
+ return 0;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+int board_init(void)
+{
+ /* board id for linux */
+ gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO_800EVA;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100;
+
+ /* Init PFC controller */
+ r8a7740_pinmux_init();
+
+ /* GETHER Enable */
+ gpio_request(GPIO_FN_ET_CRS, NULL);
+ gpio_request(GPIO_FN_ET_MDC, NULL);
+ gpio_request(GPIO_FN_ET_MDIO, NULL);
+ gpio_request(GPIO_FN_ET_TX_ER, NULL);
+ gpio_request(GPIO_FN_ET_RX_ER, NULL);
+ gpio_request(GPIO_FN_ET_ERXD0, NULL);
+ gpio_request(GPIO_FN_ET_ERXD1, NULL);
+ gpio_request(GPIO_FN_ET_ERXD2, NULL);
+ gpio_request(GPIO_FN_ET_ERXD3, NULL);
+ gpio_request(GPIO_FN_ET_TX_CLK, NULL);
+ gpio_request(GPIO_FN_ET_TX_EN, NULL);
+ gpio_request(GPIO_FN_ET_ETXD0, NULL);
+ gpio_request(GPIO_FN_ET_ETXD1, NULL);
+ gpio_request(GPIO_FN_ET_ETXD2, NULL);
+ gpio_request(GPIO_FN_ET_ETXD3, NULL);
+ gpio_request(GPIO_FN_ET_PHY_INT, NULL);
+ gpio_request(GPIO_FN_ET_COL, NULL);
+ gpio_request(GPIO_FN_ET_RX_DV, NULL);
+ gpio_request(GPIO_FN_ET_RX_CLK, NULL);
+
+ gpio_request(GPIO_PORT18, NULL); /* PHY_RST */
+ gpio_direction_output(GPIO_PORT18, 1);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+ CONFIG_RMOBILE_BOARD_STRING
+};
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
/* NAND flash on D16 */
csa |= AT91_MATRIX_NFD0_ON_D16;
+
+ /* Configure IO drive */
+ csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+
writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */
#include <ns16550.h>
#include <asm/io.h>
#include <asm/gpio.h>
-#include <asm/arch/board.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/uart.h>
-#include <asm/arch/mmc.h>
-
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/mmc.h>
+#include <asm/arch-tegra/sys_proto.h>
+#include <asm/arch-tegra/uart.h>
#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
#endif
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on Tamonten - no conflict w/SPI.
- */
-void gpio_config_uart(void)
-{
-}
#ifdef CONFIG_BOARD_EARLY_INIT_F
void gpio_early_init(void)
/ {
model = "Avionic Design Medcom-Wide";
- compatible = "avionic-design,medcom", "nvidia,tegra20";
+ compatible = "ad,medcom-wide", "nvidia,tegra20";
aliases {
usb0 = "/usb@c5008000";
/ {
model = "Avionic Design Plutux";
- compatible = "avionic-design,plutux", "nvidia,tegra20";
+ compatible = "ad,plutux", "nvidia,tegra20";
aliases {
usb0 = "/usb@c5008000";
/ {
model = "Avionic Design Tamonten Evaluation Carrier";
- compatible = "avionic-design,tec", "nvidia,tegra20";
+ compatible = "ad,tec", "nvidia,tegra20";
aliases {
usb0 = "/usb@c5008000";
return 0;
}
-struct serial_device *default_serial_console(void)
-{
- return &serial_stuart_device;
-}
-
int dram_init(void)
{
pxa2xx_dram_init();
*/
#include <common.h>
+#include <serial.h>
+#include <linux/compiler.h>
+
#include "ns16550.h"
DECLARE_GLOBAL_DATA_PTR;
extern ulong get_bus_freq (ulong);
-int serial_init (void)
+static int bmw_serial_init(void)
{
int clock_divisor = gd->bus_clk / 16 / gd->baudrate;
return (0);
}
-void serial_putc (const char c)
+static void bmw_serial_putc(const char c)
{
if (c == '\n') {
serial_putc ('\r');
NS16550_putc (console, c);
}
-void serial_puts (const char *s)
+static void bmw_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
}
-int serial_getc (void)
+static int bmw_serial_getc(void)
{
return NS16550_getc (console);
}
-int serial_tstc (void)
+static int bmw_serial_tstc(void)
{
return NS16550_tstc (console);
}
-void serial_setbrg (void)
+static void bmw_serial_setbrg(void)
{
int clock_divisor = get_bus_freq (0) / 16 / gd->baudrate;
NS16550_reinit (console, clock_divisor);
}
+
+static struct serial_device bmw_serial_drv = {
+ .name = "bmw_serial",
+ .start = bmw_serial_init,
+ .stop = NULL,
+ .setbrg = bmw_serial_setbrg,
+ .putc = bmw_serial_putc,
+ .puts = bmw_serial_puts,
+ .getc = bmw_serial_getc,
+ .tstc = bmw_serial_tstc,
+};
+
+void bmw_serial_initialize(void)
+{
+ serial_register(&bmw_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &bmw_serial_drv;
+}
static void check_power_switch(void)
{
if (kw_gpio_get_value(GPIO_POWER_SWITCH)) {
- /* turn off HDD and USB power */
+ /* turn off fan, HDD and USB power */
kw_gpio_set_value(GPIO_HDD_POWER, 0);
kw_gpio_set_value(GPIO_USB_VBUS, 0);
+ kw_gpio_set_value(GPIO_FAN_HIGH, 1);
+ kw_gpio_set_value(GPIO_FAN_LOW, 1);
set_led(LED_OFF);
/* loop until released */
/* turn power on again */
kw_gpio_set_value(GPIO_HDD_POWER, 1);
kw_gpio_set_value(GPIO_USB_VBUS, 1);
+ kw_gpio_set_value(GPIO_FAN_HIGH, 0);
+ kw_gpio_set_value(GPIO_FAN_LOW, 0);
set_led(LED_POWER_BLINKING);
}
}
#include <common.h>
#include <board/cogent/serial.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
#error CONFIG_CONS_INDEX must be configured for Cogent motherboard serial
#endif
-int serial_init (void)
+static int cogent_serial_init(void)
{
cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
return (0);
}
-void serial_setbrg (void)
+static void cogent_serial_setbrg(void)
{
cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
unsigned int divisor;
cma_mb_reg_write (&mbsp->ser_lcr, lcr); /* unset DLAB */
}
-void serial_putc (const char c)
+static void cogent_serial_putc(const char c)
{
cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
cma_mb_reg_write (&mbsp->ser_thr, c);
}
-void serial_puts (const char *s)
+static void cogent_serial_puts(const char *s)
{
while (*s != '\0')
serial_putc (*s++);
}
-int serial_getc (void)
+static int cogent_serial_getc(void)
{
cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
return ((int) cma_mb_reg_read (&mbsp->ser_rhr) & 0x7f);
}
-int serial_tstc (void)
+static int cogent_serial_tstc(void)
{
cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
return ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) != 0);
}
+static struct serial_device cogent_serial_drv = {
+ .name = "cogent_serial",
+ .start = cogent_serial_init,
+ .stop = NULL,
+ .setbrg = cogent_serial_setbrg,
+ .putc = cogent_serial_putc,
+ .puts = cogent_serial_puts,
+ .getc = cogent_serial_getc,
+ .tstc = cogent_serial_tstc,
+};
+
+void cogent_serial_initialize(void)
+{
+ serial_register(&cogent_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &cogent_serial_drv;
+}
#endif /* CONS_NONE */
#if defined(CONFIG_CMD_KGDB) && \
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
+#include <asm/arch/tegra.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/mmc.h>
+#include <asm/arch-tegra/mmc.h>
#include <asm/gpio.h>
#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
#endif
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on Paz00 - no conflict w/SPI.
- */
-void gpio_config_uart(void)
-{
-}
#ifdef CONFIG_TEGRA_MMC
/*
*/
#include <common.h>
-#include <i2c.h>
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
+#include <asm/arch/tegra.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/mmc.h>
+#include <asm/arch-tegra/mmc.h>
#include <asm/gpio.h>
+#include <i2c.h>
#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
#endif
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on TrimSlice - no UART-related GPIOs.
- */
-void gpio_config_uart(void)
-{
-}
void pin_mux_spi(void)
{
if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
return 1;
+ /* Set DISP_ON high to enable LCD output*/
+ gpio_direction_output(97, 1);
+
/* Set the RESETOUTn low */
gpio_direction_output(111, 0);
/* Set LCD_B_PWR low to power down LCD Backlight*/
gpio_direction_output(102, 0);
- /* Set DISP_ON low to disable LCD output*/
- gpio_direction_output(97, 0);
-
#ifndef CONFIG_USE_IRQ
irq_init();
#endif
writel(readl(&davinci_syscfg_regs->mstpri[2]) & 0x0fffffff,
&davinci_syscfg_regs->mstpri[2]);
- /* Set LCD_B_PWR low to power up LCD Backlight*/
- gpio_set_value(102, 1);
-
- /* Set DISP_ON low to disable LCD output*/
- gpio_set_value(97, 1);
return 0;
}
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
int board_init(void)
{
/* arch number of the board */
int board_late_init(void)
{
+ unsigned char buf[2];
+ int ret;
+
/* PinMux for HALTEN */
if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0)
return 1;
/* Set HALTEN to high */
gpio_direction_output(134, 1);
- setenv("stdout", "serial");
+ /* Set fixed contrast settings for LCD via I2C potentiometer */
+ buf[0] = 0x00;
+ buf[1] = 0xd7;
+ ret = i2c_write(0x2e, 6, 1, buf, 2);
+ if (ret)
+ puts("\nContrast Settings FAILED\n");
+ /* Set LCD_B_PWR high to power up LCD Backlight*/
+ gpio_set_value(102, 1);
return 0;
}
#endif /* CONFIG_BOARD_LATE_INIT */
#include <common.h>
#include <command.h>
+#include <serial.h>
+#include <linux/compiler.h>
+
#include "../../Marvell/include/memory.h"
#include "serial.h"
DECLARE_GLOBAL_DATA_PTR;
-int serial_init (void)
+static int cpci750_serial_init(void)
{
mpsc_init (gd->baudrate);
return (0);
}
-void serial_putc (const char c)
+static void cpci750_serial_putc(const char c)
{
if (c == '\n')
mpsc_putchar ('\r');
mpsc_putchar (c);
}
-int serial_getc (void)
+static int cpci750_serial_getc(void)
{
return mpsc_getchar ();
}
-int serial_tstc (void)
+static int cpci750_serial_tstc(void)
{
return mpsc_test_char ();
}
-void serial_setbrg (void)
+static void cpci750_serial_setbrg(void)
{
galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
}
-void serial_puts (const char *s)
+static void cpci750_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
+static struct serial_device cpci750_serial_drv = {
+ .name = "cpci750_serial",
+ .start = cpci750_serial_init,
+ .stop = NULL,
+ .setbrg = cpci750_serial_setbrg,
+ .putc = cpci750_serial_putc,
+ .puts = cpci750_serial_puts,
+ .getc = cpci750_serial_getc,
+ .tstc = cpci750_serial_tstc,
+};
+
+void cpci750_serial_initialize(void)
+{
+ serial_register(&cpci750_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &cpci750_serial_drv;
+}
+
#if defined(CONFIG_CMD_KGDB)
void kgdb_serial_init (void)
{
#if defined(CONFIG_PRAM)
#include <environment.h>
-extern env_t *env_ptr;
int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#include <common.h>
#include <command.h>
#include <galileo/memory.h>
+#include <serial.h>
+#include <linux/compiler.h>
#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
#include <ns16550.h>
#ifdef CONFIG_MPSC
-int serial_init (void)
+static int evb64260_serial_init(void)
{
#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
return (0);
}
-void
-serial_putc(const char c)
+static void evb64260_serial_putc(const char c)
{
if (c == '\n')
mpsc_putchar('\r');
mpsc_putchar(c);
}
-int
-serial_getc(void)
+static int evb64260_serial_getc(void)
{
return mpsc_getchar();
}
-int
-serial_tstc(void)
+static int evb64260_serial_tstc(void)
{
return mpsc_test_char();
}
-void
-serial_setbrg (void)
+static void evb64260_serial_setbrg(void)
{
galbrg_set_baudrate(CONFIG_MPSC_PORT, gd->baudrate);
}
#else /* ! CONFIG_MPSC */
-int serial_init (void)
+static int evb64260_serial_init(void)
{
int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
return (0);
}
-void
-serial_putc(const char c)
+static void evb64260_serial_putc(const char c)
{
if (c == '\n')
NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
}
-int
-serial_getc(void)
+static int evb64260_serial_getc(void)
{
return NS16550_getc(COM_PORTS[CONFIG_SYS_DUART_CHAN]);
}
-int
-serial_tstc(void)
+static int evb64260_serial_tstc(void)
{
return NS16550_tstc(COM_PORTS[CONFIG_SYS_DUART_CHAN]);
}
-void
-serial_setbrg (void)
+static void evb64260_serial_setbrg(void)
{
int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
#endif /* CONFIG_MPSC */
-void
-serial_puts (const char *s)
+static void evb64260_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
+static struct serial_device evb64260_serial_drv = {
+ .name = "evb64260_serial",
+ .start = evb64260_serial_init,
+ .stop = NULL,
+ .setbrg = evb64260_serial_setbrg,
+ .putc = evb64260_serial_putc,
+ .puts = evb64260_serial_puts,
+ .getc = evb64260_serial_getc,
+ .tstc = evb64260_serial_tstc,
+};
+
+void evb64260_serial_initialize(void)
+{
+ serial_register(&evb64260_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &evb64260_serial_drv;
+}
+
#if defined(CONFIG_CMD_KGDB)
void
kgdb_serial_init(void)
#ifdef CONFIG_CMD_NET
-#define MII_OPMODE_STRAP_OVERRIDE 0x16
-#define MII_PHY_CTRL1 0x1e
-#define MII_PHY_CTRL2 0x1f
-
-int fecmxc_mii_postcall(int phy)
-{
- miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
- miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
- if (phy == 3)
- miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
- return 0;
-}
-
int board_eth_init(bd_t *bis)
{
struct mxs_clkctrl_regs *clkctrl_regs =
return -EINVAL;
}
- ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
- if (ret) {
- puts("FEC MXS: Unable to register FEC0 mii postcall\n");
- return ret;
- }
-
dev = eth_get_dev_by_name("FEC1");
if (!dev) {
puts("FEC MXS: Unable to get FEC1 device entry\n");
return -EINVAL;
}
- ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
- if (ret) {
- puts("FEC MXS: Unable to register FEC1 mii postcall\n");
- return ret;
- }
-
return ret;
}
/* COSR */
str r1, [r0, #0x1c]
- /* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */
-/* REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
+ /* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */
+/* REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
/* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/
return 0;
}
+u32 get_board_rev(void)
+{
+ u32 rev = get_cpu_rev();
+ if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
+ rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
+ return rev;
+}
+
static void setup_iomux_uart(void)
{
unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
static void clock_1GHz(void)
{
int ret;
- u32 ref_clk = CONFIG_SYS_MX5_HCLK;
+ u32 ref_clk = MXC_HCLK;
/*
* After increasing voltage to 1.25V, we can switch
* CPU clock to 1GHz and DDR to 400MHz safely
--- /dev/null
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := mx6qsabreauto.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+# Copyright (C) 2012 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# image version
+
+IMAGE_VERSION 2
+
+# Boot Device : one of
+# spi, sd (the board has no nand neither onenand)
+
+BOOT_FROM sd
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type Address Value
+#
+# where:
+# Addr-type register length (1,2 or 4 bytes)
+# Address absolute address of the register
+# value value to be stored in the register
+DATA 4 0x020e05a8 0x00000028
+DATA 4 0x020e05b0 0x00000028
+DATA 4 0x020e0524 0x00000028
+DATA 4 0x020e051c 0x00000028
+
+DATA 4 0x020e0518 0x00000028
+DATA 4 0x020e050c 0x00000028
+DATA 4 0x020e05b8 0x00000028
+DATA 4 0x020e05c0 0x00000028
+
+DATA 4 0x020e05ac 0x00000028
+DATA 4 0x020e05b4 0x00000028
+DATA 4 0x020e0528 0x00000028
+DATA 4 0x020e0520 0x00000028
+
+DATA 4 0x020e0514 0x00000028
+DATA 4 0x020e0510 0x00000028
+DATA 4 0x020e05bc 0x00000028
+DATA 4 0x020e05c4 0x00000028
+
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e0588 0x00000030
+DATA 4 0x020e0594 0x00000030
+
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e0590 0x00000030
+DATA 4 0x020e0598 0x00000030
+DATA 4 0x020e058c 0x00000000
+
+DATA 4 0x020e059c 0x00003030
+DATA 4 0x020e05a0 0x00003030
+DATA 4 0x020e0784 0x00000028
+DATA 4 0x020e0788 0x00000028
+
+DATA 4 0x020e0794 0x00000028
+DATA 4 0x020e079c 0x00000028
+DATA 4 0x020e07a0 0x00000028
+DATA 4 0x020e07a4 0x00000028
+
+DATA 4 0x020e07a8 0x00000028
+DATA 4 0x020e0748 0x00000028
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e0750 0x00020000
+
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0798 0x000C0000
+
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+
+DATA 4 0x021b0018 0x00001740
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b000c 0x8A8F7975
+DATA 4 0x021b0010 0xFF538E64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b002c 0x000026D2
+
+DATA 4 0x021b0030 0x008F0E21
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0040 0x00000047
+DATA 4 0x021b0000 0x841A0000
+
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00428031
+DATA 4 0x021b001c 0x09408030
+
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0800 0xA1380003
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00000007
+DATA 4 0x021b4818 0x00000007
+
+# Calibration values based on ARD and 528MHz
+DATA 4 0x021b083c 0x434B0358
+DATA 4 0x021b0840 0x033D033C
+DATA 4 0x021b483c 0x03520362
+DATA 4 0x021b4840 0x03480318
+DATA 4 0x021b0848 0x41383A3C
+DATA 4 0x021b4848 0x3F3C374A
+DATA 4 0x021b0850 0x42434444
+DATA 4 0x021b4850 0x4932473A
+
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+
+DATA 4 0x021b480c 0x001F001F
+DATA 4 0x021b4810 0x001F001F
+
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b0004 0x00025576
+
+DATA 4 0x021b001c 0x00000000
+
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC00
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
--- /dev/null
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6x_pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+iomux_v3_cfg_t uart4_pads[] = {
+ MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t enet_pads[] = {
+ MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+}
+
+iomux_v3_cfg_t usdhc3_pads[] = {
+ MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ gpio_direction_input(IMX_GPIO_NR(6, 15));
+ return !gpio_get_value(IMX_GPIO_NR(6, 15));
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= 0xffe3;
+ val |= 0x18;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ mx6_rgmii_rework(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+
+ setup_iomux_enet();
+
+ ret = cpu_eth_init(bis);
+ if (ret)
+ printf("FEC MXC: %s:failed\n", __func__);
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ return 0x63000;
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX6Q-Sabreauto\n");
+
+ return 0;
+}
--- /dev/null
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := mx6qsabresd.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6x_pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+iomux_v3_cfg_t uart1_pads[] = {
+ MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t enet_pads[] = {
+ MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* AR8031 PHY Reset */
+ MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+ /* Reset AR8031 PHY */
+ gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
+ udelay(500);
+ gpio_set_value(IMX_GPIO_NR(1, 25), 1);
+}
+
+iomux_v3_cfg_t usdhc3_pads[] = {
+ MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ gpio_direction_input(IMX_GPIO_NR(2, 0));
+ return !gpio_get_value(IMX_GPIO_NR(2, 0));
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= 0xffe3;
+ val |= 0x18;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ mx6_rgmii_rework(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+
+ setup_iomux_enet();
+
+ ret = cpu_eth_init(bis);
+ if (ret)
+ printf("FEC MXC: %s:failed\n", __func__);
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ return 0x63000;
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX6Q-SabreSD\n");
+
+ return 0;
+}
#
-# (C) Copyright 2005-2006
+# (C) Copyright 2012
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
LIB = $(obj)lib$(BOARD).o
-COBJS = $(BOARD).o flash.o ee_access.o
-SOBJS = lowlevel_init.o
+COBJS := mini2440.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2009
+ * Michel Pollet <buserror@gmail.com>
+ *
+ * (C) Copyright 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/s3c2440.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <netdev.h>
+#include "mini2440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline void pll_delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+int board_early_init_f(void)
+{
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+
+ /* to reduce PLL lock time, adjust the LOCKTIME register */
+ clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
+ clk_power->clkdivn = CLKDIVN_VAL;
+
+ /* configure UPLL */
+ clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+ /* some delay between MPLL and UPLL */
+ pll_delay(100);
+
+ /* configure MPLL */
+ clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ pll_delay(10000);
+
+ return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+ /* IOMUX Port H : UART Configuration */
+ gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
+ IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
+
+ gpio_direction_output(GPH8, 0);
+ gpio_direction_output(GPH9, 0);
+ gpio_direction_output(GPH10, 0);
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
+
+ /*
+ * Configuring bus width and timing
+ * Initialize clocks for each bank 0..5
+ * Bank 3 and 4 are used for DM9000
+ */
+ writel(BANK_CONF, &memctl->bwscon);
+ writel(B0_CONF, &memctl->bankcon[0]);
+ writel(B1_CONF, &memctl->bankcon[1]);
+ writel(B2_CONF, &memctl->bankcon[2]);
+ writel(B3_CONF, &memctl->bankcon[3]);
+ writel(B4_CONF, &memctl->bankcon[4]);
+ writel(B5_CONF, &memctl->bankcon[5]);
+
+ /* Bank 6 and 7 are used for DRAM */
+ writel(SDRAM_64MB, &memctl->bankcon[6]);
+ writel(SDRAM_64MB, &memctl->bankcon[7]);
+
+ writel(MEM_TIMING, &memctl->refresh);
+ writel(BANKSIZE_CONF, &memctl->banksize);
+ writel(B6_MRSR, &memctl->mrsrb6);
+ writel(B7_MRSR, &memctl->mrsrb7);
+
+ gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_DRIVER_DM9000
+ return dm9000_initialize(bis);
+#else
+ return 0;
+#endif
+}
--- /dev/null
+#ifndef __MINI2440_BOARD_CONF_H__
+#define __MINI2440_BOARD_CONF_H__
+
+/* PLL Parameters */
+#define CLKDIVN_VAL 7
+#define M_MDIV 0x7f
+#define M_PDIV 0x2
+#define M_SDIV 0x1
+
+#define U_M_MDIV 0x38
+#define U_M_PDIV 0x2
+#define U_M_SDIV 0x2
+
+/* BWSCON */
+#define DW8 0x0
+#define DW16 0x1
+#define DW32 0x2
+#define WAIT (0x1<<2)
+#define UBLB (0x1<<3)
+
+#define B1_BWSCON (DW32)
+#define B2_BWSCON (DW16)
+#define B3_BWSCON (DW16 + WAIT + UBLB)
+#define B4_BWSCON (DW16 + WAIT + UBLB)
+#define B5_BWSCON (DW16)
+#define B6_BWSCON (DW32)
+#define B7_BWSCON (DW32)
+
+/*
+ * Bank Configuration
+ */
+#define B0_Tacs 0x0 /* 0clk */
+#define B0_Tcos 0x0 /* 0clk */
+#define B0_Tacc 0x7 /* 14clk */
+#define B0_Tcoh 0x0 /* 0clk */
+#define B0_Tah 0x0 /* 0clk */
+#define B0_Tacp 0x0 /* 0clk */
+#define B0_PMC 0x0 /* normal */
+
+#define B1_Tacs 0x0
+#define B1_Tcos 0x0
+#define B1_Tacc 0x7
+#define B1_Tcoh 0x0
+#define B1_Tah 0x0
+#define B1_Tacp 0x0
+#define B1_PMC 0x0
+
+#define B2_Tacs 0x0
+#define B2_Tcos 0x0
+#define B2_Tacc 0x7
+#define B2_Tcoh 0x0
+#define B2_Tah 0x0
+#define B2_Tacp 0x0
+#define B2_PMC 0x0
+
+#define B3_Tacs 0x0
+#define B3_Tcos 0x3 /* 4clk */
+#define B3_Tacc 0x7
+#define B3_Tcoh 0x1 /* 1clk */
+#define B3_Tah 0x3 /* 4clk */
+#define B3_Tacp 0x0
+#define B3_PMC 0x0
+
+#define B4_Tacs 0x0
+#define B4_Tcos 0x3
+#define B4_Tacc 0x7
+#define B4_Tcoh 0x1
+#define B4_Tah 0x3
+#define B4_Tacp 0x0
+#define B4_PMC 0x0
+
+#define B5_Tacs 0x0
+#define B5_Tcos 0x0
+#define B5_Tacc 0x7
+#define B5_Tcoh 0x0
+#define B5_Tah 0x0
+#define B5_Tacp 0x0
+#define B5_PMC 0x0
+
+/*
+ * SDRAM Configuration
+ */
+#define SDRAM_MT 0x3 /* SDRAM */
+#define SDRAM_Trcd 0x0 /* 2clk */
+#define SDRAM_SCAN_9 0x1 /* 9bit */
+#define SDRAM_SCAN_10 0x2 /* 10bit */
+
+#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
+
+/*
+ * Refresh Parameter
+ */
+#define REFEN 0x1 /* Refresh enable */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
+#define Trp 0x1 /* 3clk */
+#define Trc 0x3 /* 7clk */
+#define Tchr 0x0 /* unused */
+#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */
+
+/*
+ * MRSR Parameter
+ */
+#define BL 0x0
+#define BT 0x0
+#define CL 0x3 /* 3 clocks */
+#define TM 0x0
+#define WBL 0x0
+
+/*
+ * BankSize Parameter
+ */
+#define BK76MAP 0x2 /* 128MB/128MB */
+#define SCLK_EN 0x1 /* SCLK active */
+#define SCKE_EN 0x1 /* SDRAM power down mode enable */
+#define BURST_EN 0x1 /* Burst enable */
+
+/*
+ * Register values
+ */
+#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \
+ (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
+ (B7_BWSCON<<28)))
+
+#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \
+ (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))
+#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \
+ (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))
+#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \
+ (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))
+#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \
+ (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))
+#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \
+ (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))
+#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \
+ (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))
+
+#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \
+ (Trc<<18) + (Tchr<<16) + REFCNT
+
+#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7)
+#define B6_MRSR (CL<<4)
+#define B7_MRSR (CL<<4)
+
+#endif
+++ /dev/null
-/* Module for handling DALLAS DS2438, smart battery monitor
- Chip can store up to 40 bytes of user data in EEPROM,
- perform temp, voltage and current measurements.
- Chip also contains a unique serial number.
-
- Always read/write LSb first
-
- For documentaion, see data sheet for DS2438, 2438.pdf
-
- By Thomas.Lange@corelatus.com 001025
-
- Copyright (C) 2000-2005 Corelatus AB */
-
-/* This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/au1x00.h>
-#include <asm/io.h>
-#include "ee_dev.h"
-#include "ee_access.h"
-
-/* static int Debug = 1; */
-#undef E_DEBUG
-#define E_DEBUG(fmt,args...) /* */
-/* #define E_DEBUG(fmt,args...) printk("EEA:"fmt,##args); */
-
-/* We dont have kernel functions */
-#define printk printf
-#define KERN_DEBUG
-#define KERN_ERR
-#define EIO 1
-
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
-/* lookup table ripped from DS app note 17, understanding and using cyclic redundancy checks... */
-
-static u8 crc_lookup[256] = {
- 0, 94, 188, 226, 97, 63, 221, 131,
- 194, 156, 126, 32, 163, 253, 31, 65,
- 157, 195, 33, 127, 252, 162, 64, 30,
- 95, 1, 227, 189, 62, 96, 130, 220,
- 35, 125, 159, 193, 66, 28, 254, 160,
- 225, 191, 93, 3, 128, 222, 60, 98,
- 190, 224, 2, 92, 223, 129, 99, 61,
- 124, 34, 192, 158, 29, 67, 161, 255,
- 70, 24, 250, 164, 39, 121, 155, 197,
- 132, 218, 56, 102, 229, 187, 89, 7,
- 219, 133, 103, 57, 186, 228, 6, 88,
- 25, 71, 165, 251, 120, 38, 196, 154,
- 101, 59, 217, 135, 4, 90, 184, 230,
- 167, 249, 27, 69, 198, 152, 122, 36,
- 248, 166, 68, 26, 153, 199, 37, 123,
- 58, 100, 134, 216, 91, 5, 231, 185,
- 140, 210, 48, 110, 237, 179, 81, 15,
- 78, 16, 242, 172, 47, 113, 147, 205,
- 17, 79, 173, 243, 112, 46, 204, 146,
- 211, 141, 111, 49, 178, 236, 14, 80,
- 175, 241, 19, 77, 206, 144, 114, 44,
- 109, 51, 209, 143, 12, 82, 176, 238,
- 50, 108, 142, 208, 83, 13, 239, 177,
- 240, 174, 76, 18, 145, 207, 45, 115,
- 202, 148, 118, 40, 171, 245, 23, 73,
- 8, 86, 180, 234, 105, 55, 213, 139,
- 87, 9, 235, 181, 54, 104, 138, 212,
- 149, 203, 41, 119, 244, 170, 72, 22,
- 233, 183, 85, 11, 136, 214, 52, 106,
- 43, 117, 151, 201, 74, 20, 246, 168,
- 116, 42, 200, 150, 21, 75, 169, 247,
- 182, 232, 10, 84, 215, 137, 107, 53
-};
-
-static void
-write_gpio_data(int value ){
- if(value){
- /* Tristate */
- gpio_tristate(GPIO_EEDQ);
- }
- else{
- /* Drive 0 */
- gpio_clear(GPIO_EEDQ);
- }
-}
-
-static u8 make_new_crc( u8 Old_crc, u8 New_value ){
- /* Compute a new checksum with new byte, using previous checksum as input
- See DS app note 17, understanding and using cyclic redundancy checks...
- Also see DS2438, page 11 */
- return( crc_lookup[Old_crc ^ New_value ]);
-}
-
-int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){
- /* Check if the checksum for this buffer is correct */
- u8 Curr_crc=0;
- int i;
- u8 *Curr_byte = Buffer;
-
- for(i=0;i<Len;i++){
- Curr_crc = make_new_crc( Curr_crc, *Curr_byte);
- Curr_byte++;
- }
- E_DEBUG("Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
-
- if(Curr_crc == Crc){
- /* Good */
- return(TRUE);
- }
- printk(KERN_ERR"EE checksum error, Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
- return(FALSE);
-}
-
-static void
-set_idle(void){
- /* Send idle and keep start time
- Continous 1 is idle */
- WRITE_PORT(1);
-}
-
-
-static int
-do_cpu_reset(void){
- /* Release reset and verify that chip responds with presence pulse */
- int Retries=0;
- while(Retries<15){
- udelay(RESET_LOW_TIME);
-
- /* Send reset */
- WRITE_PORT(0);
- udelay(RESET_LOW_TIME);
-
- /* Release reset */
- WRITE_PORT(1);
-
- /* Wait for EEPROM to drive output */
- udelay(PRESENCE_TIMEOUT);
- if(!READ_PORT){
- /* Ok, EEPROM is driving a 0 */
- E_DEBUG("Presence detected\n");
- if(Retries){
- E_DEBUG("Retries %d\n",Retries);
- }
- /* Make sure chip releases pin */
- udelay(PRESENCE_LOW_TIME);
- return 0;
- }
- Retries++;
- }
-
- printk(KERN_ERR"eeprom did not respond when releasing reset\n");
-
- /* Make sure chip releases pin */
- udelay(PRESENCE_LOW_TIME);
-
- /* Set to idle again */
- set_idle();
-
- return(-EIO);
-}
-
-static u8
-read_cpu_byte(void){
- /* Read a single byte from EEPROM
- Read LSb first */
- int i;
- int Value;
- u8 Result=0;
- u32 Flags;
-
- E_DEBUG("Reading byte\n");
-
- for(i=0;i<8;i++){
- /* Small delay between pulses */
- udelay(1);
-
-#ifdef __KERNEL__
- /* Disable irq */
- save_flags(Flags);
- cli();
-#endif
-
- /* Pull down pin short time to start read
- See page 26 in data sheet */
-
- WRITE_PORT(0);
- udelay(READ_LOW);
- WRITE_PORT(1);
-
- /* Wait for chip to drive pin */
- udelay(READ_TIMEOUT);
-
- Value = READ_PORT;
- if(Value)
- Value=1;
-
-#ifdef __KERNEL__
- /* Enable irq */
- restore_flags(Flags);
-#endif
-
- /* Wait for chip to release pin */
- udelay(TOTAL_READ_LOW-READ_TIMEOUT);
-
- /* LSb first */
- Result|=Value<<i;
- /* E_DEBUG("Read %d\n",Value); */
-
- }
-
- E_DEBUG("Read byte 0x%x\n",Result);
-
- return(Result);
-}
-
-static void
-write_cpu_byte(u8 Byte){
- /* Write a single byte to EEPROM
- Write LSb first */
- int i;
- int Value;
- u32 Flags;
-
- E_DEBUG("Writing byte 0x%x\n",Byte);
-
- for(i=0;i<8;i++){
- /* Small delay between pulses */
- udelay(1);
- Value = Byte&1;
-
-#ifdef __KERNEL__
- /* Disable irq */
- save_flags(Flags);
- cli();
-#endif
-
- /* Pull down pin short time for a 1, long time for a 0
- See page 26 in data sheet */
-
- WRITE_PORT(0);
- if(Value){
- /* Write a 1 */
- udelay(WRITE_1_LOW);
- }
- else{
- /* Write a 0 */
- udelay(WRITE_0_LOW);
- }
-
- WRITE_PORT(1);
-
-#ifdef __KERNEL__
- /* Enable irq */
- restore_flags(Flags);
-#endif
-
- if(Value)
- /* Wait for chip to read the 1 */
- udelay(TOTAL_WRITE_LOW-WRITE_1_LOW);
-
- /* E_DEBUG("Wrote %d\n",Value); */
- Byte>>=1;
- }
-}
-
-int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){
- /* Execute this command string, including
- giving reset and setting to idle after command
- if Rx_len is set, we read out data from EEPROM */
- int i;
-
- E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len );
-
- if(do_cpu_reset()){
- /* Failed! */
- return(-EIO);
- }
-
- if(Send_skip)
- /* Always send SKIP_ROM first to tell chip we are sending a command,
- except when we read out rom data for chip */
- write_cpu_byte(SKIP_ROM);
-
- /* Always have Tx data */
- for(i=0;i<Tx_len;i++){
- write_cpu_byte(Tx[i]);
- }
-
- if(Rx_len){
- for(i=0;i<Rx_len;i++){
- Rx[i]=read_cpu_byte();
- }
- }
-
- set_idle();
-
- E_DEBUG("Command done\n");
-
- return(0);
-}
-
-int ee_init_cpu_data(void){
- int i;
- u8 Tx[10];
-
- /* Leave it floting since altera is driving the same pin */
- set_idle();
-
- /* Copy all User EEPROM data to scratchpad */
- for(i=0;i<USER_PAGES;i++){
- Tx[0]=RECALL_MEMORY;
- Tx[1]=EE_USER_PAGE_0+i;
- if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO);
- }
-
- /* Make sure chip doesnt store measurements in NVRAM */
- Tx[0]=WRITE_SCRATCHPAD;
- Tx[1]=0; /* Page */
- Tx[2]=9;
- if(ee_do_cpu_command(Tx,3,NULL,0,TRUE)) return(-EIO);
-
- Tx[0]=COPY_SCRATCHPAD;
- if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO);
-
- for(i=0;i<10;i++){
- udelay(1000);
- }
-
- return(0);
-}
+++ /dev/null
-/* By Thomas.Lange@Corelatus.com 001025 */
-
-/* Definitions for EEPROM/VOLT METER DS2438 */
-/* Copyright (C) 2000-2005 Corelatus AB */
-
-#ifndef INCeeaccessh
-#define INCeeaccessh
-
-#include <asm/types.h>
-#include "ee_dev.h"
-
-int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip );
-int ee_init_cpu_data(void);
-
-int ee_crc_ok( u8 *Buffer, int Len, u8 Crc );
-
-/* Defs for altera reg */
-#define EE_WRITE_SHIFT 8 /* bits to shift left */
-#define EE_READ_SHIFT 16 /* bits to shift left */
-#define EE_DONE 0x80000000
-#define EE_BUSY 0x40000000
-#define EE_ERROR 0x20000000
-
-/* Commands */
-#define EE_CMD_NOP 0
-#define EE_CMD_INIT_RES 1
-#define EE_CMD_WR_BYTE 2
-#define EE_CMD_RD_BYTE 3
-
-#endif /* INCeeaccessh */
+++ /dev/null
-/* By Thomas.Lange@Corelatus.com 001025 */
-/* Definitions for EEPROM/VOLT METER DS2438 */
-/* Copyright (C) 2000-2005 Corelatus AB */
-
-/* This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef INCeedevh
-#define INCeedevh
-
-#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args)
-
-/* MIPS */
-#define WRITE_PORT(Value) write_gpio_data(Value)
-
-#define READ_PORT (gpio_read()&GPIO_EEDQ)
-
-/* 64 bytes chip */
-#define EE_CHIP_SIZE 64
-
-/* Board with new current resistor */
-#define EE_GTH_0304 1
-
-/* new dsp and 64 MB SDRAM */
-#define EE_DSP_64 0x10
-
-/* microsecs */
-/* Pull line down at least this long for reset pulse */
-#define RESET_LOW_TIME 490
-
-/* Read presence pulse after we release reset pulse */
-#define PRESENCE_TIMEOUT 100
-#define PRESENCE_LOW_TIME 200
-
-#define WRITE_0_LOW 60
-#define WRITE_1_LOW 1
-#define TOTAL_WRITE_LOW 60
-
-#define READ_LOW 1
-#define READ_TIMEOUT 10
-#define TOTAL_READ_LOW 70
-
-/* Rom function commands */
-#define READ_ROM 0x33
-#define MATCH_ROM 0x55
-#define SKIP_ROM 0xCC
-#define SEARCH_ROM 0xF0
-
-
-/* Memory_command_function */
-#define WRITE_SCRATCHPAD 0x4E
-#define READ_SCRATCHPAD 0xBE
-#define COPY_SCRATCHPAD 0x48
-#define RECALL_MEMORY 0xB8
-#define CONVERT_TEMP 0x44
-#define CONVERT_VOLTAGE 0xB4
-
-/* Chip is divided in 8 pages, 8 bytes each */
-
-#define EE_PAGE_SIZE 8
-
-/* All chip data we want are in page 0 */
-
-/* Bytes in page 0 */
-#define EE_P0_STATUS 0
-#define EE_P0_TEMP_LSB 1
-#define EE_P0_TEMP_MSB 2
-#define EE_P0_VOLT_LSB 3
-#define EE_P0_VOLT_MSB 4
-#define EE_P0_CURRENT_LSB 5
-#define EE_P0_CURRENT_MSB 6
-
-
-/* 40 byte user data is located at page 3-7 */
-#define EE_USER_PAGE_0 3
-#define USER_PAGES 5
-
-/* Layout of gth user pages usage */
-/* Bytes 0-16 ethernet addr in ascii ( len 17 ) */
-
-#define EE_ETHERNET_OFFSET 0
-
-#endif /* INCeedevh */
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Thomas.Lange@corelatus.se
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/au1x00.h>
-#include <asm/addrspace.h>
-#include <asm/mipsregs.h>
-#include <asm/io.h>
-#include <watchdog.h>
-
-#include "ee_access.h"
-
-static int wdi_status = 0;
-
-#define SDRAM_SIZE ((64*1024*1024)-(12*4096))
-
-
-#define SERIAL_LOG_BUFFER CKSEG1ADDR(SDRAM_SIZE + (8*4096))
-
-void inline log_serial_char(char c){
- char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
- int serial_log_offset;
- u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER;
-
- serial_log_offset = *serial_log_offsetp;
-
- *(serial_log_buffer + serial_log_offset) = c;
-
- serial_log_offset++;
-
- if(serial_log_offset >= 4096){
- serial_log_offset = 4;
- }
- *serial_log_offsetp = serial_log_offset;
-}
-
-void init_log_serial(void){
- char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
- u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER;
-
- /* Copy buffer from last run */
- memcpy(serial_log_buffer + 4096,
- serial_log_buffer,
- 4096);
-
- memset(serial_log_buffer, 0, 4096);
-
- *serial_log_offsetp = 4;
-}
-
-
-void hw_watchdog_reset(void){
- volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
- volatile u32 *sys_outputclear = (volatile u32*)SYS_OUTPUTCLR;
- if(wdi_status){
- *sys_outputset = GPIO_CPU_LED|GPIO_WDI;
- wdi_status = 0;
- }
- else{
- *sys_outputclear = GPIO_CPU_LED|GPIO_WDI;
- wdi_status = 1;
- }
-}
-
-phys_size_t initdram(int board_type)
-{
- /* Sdram is setup by assembler code */
- /* If memory could be changed, we should return the true value here */
-
- WATCHDOG_RESET();
-
- return (SDRAM_SIZE);
-}
-
-/* In arch/mips/cpu/cpu.c */
-void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
-
-void set_ledcard(u32 value){
- /* Clock 24 bits to led card */
- int i;
- volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
- volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR;
-
- /* Start with known values */
- *sys_outputclr = GPIO_LEDCLK|GPIO_LEDD;
-
- for(i=0;i<24;i++){
- if(value&0x00800000){
- *sys_outputset = GPIO_LEDD;
- }
- else{
- *sys_outputclr = GPIO_LEDD;
- }
- udelay(1);
- *sys_outputset = GPIO_LEDCLK;
- udelay(1);
- *sys_outputclr = GPIO_LEDCLK;
- udelay(1);
-
- value<<=1;
- }
- /* Data is enable output */
- *sys_outputset = GPIO_LEDD;
-}
-
-int checkboard (void)
-{
- volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
- volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
- volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR;
- u32 proc_id;
-
- WATCHDOG_RESET();
-
- *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
-
- proc_id = read_c0_prid();
-
- switch (proc_id >> 24) {
- case 0:
- puts ("Board: GTH2\n");
- printf ("CPU: Au1000 500 MHz, id: 0x%02x, rev: 0x%02x\n",
- (proc_id >> 8) & 0xFF, proc_id & 0xFF);
- break;
- default:
- printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
- }
-
- set_io_port_base(0);
-
-#ifdef CONFIG_IDE_PCMCIA
- /* PCMCIA is on a 36 bit physical address.
- We need to map it into a 32 bit addresses */
- write_one_tlb(20, /* index */
- 0x01ffe000, /* Pagemask, 16 MB pages */
- CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
- 0x3C000017, /* Lo0 */
- 0x3C200017); /* Lo1 */
-
- write_one_tlb(21, /* index */
- 0x01ffe000, /* Pagemask, 16 MB pages */
- CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
- 0x3D000017, /* Lo0 */
- 0x3D200017); /* Lo1 */
-
- write_one_tlb(22, /* index */
- 0x01ffe000, /* Pagemask, 16 MB pages */
- CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */
- 0x3E000017, /* Lo0 */
- 0x3E200017); /* Lo1 */
-
-#endif /* CONFIG_IDE_PCMCIA */
-
- /* Wait for GPIO ports to become stable */
- udelay(5000); /* FIXME */
-
- /* Release reset of ethernet PHY chips */
- /* Always do this, because linux does not know about it */
- *sys_outputset = GPIO_ERESET;
-
- /* Kill FPGA:s */
- *sys_outputclr = GPIO_CACONFIG|GPIO_DPACONFIG;
- udelay(2);
- *sys_outputset = GPIO_CACONFIG|GPIO_DPACONFIG;
-
- /* Turn front led yellow */
- set_ledcard(0x00100000);
-
- return 0;
-}
-
-#define POWER_OFFSET 0xF0000
-#define SW_WATCHDOG_REASON 13
-
-#define BOOTDATA_OFFSET 0xF8000
-#define MAX_ATTEMPTS 5
-
-#define FAILSAFE_BOOT 1
-#define SYSTEM_BOOT 2
-#define SYSTEM2_BOOT 3
-
-#define WRITE_FLASH16(a, d) \
-do \
-{ \
- *((volatile u16 *) (a)) = (d);\
- } while(0)
-
-static void write_bootdata (volatile u16 * addr, u8 System, u8 Count)
-{
- u16 data;
- volatile u16 *flash = (u16 *) (CONFIG_SYS_FLASH_BASE);
-
- switch(System){
- case FAILSAFE_BOOT:
- printf ("Setting failsafe boot in flash\n");
- break;
- case SYSTEM_BOOT:
- printf ("Setting system boot in flash\n");
- break;
- case SYSTEM2_BOOT:
- printf ("Setting system2 boot in flash\n");
- break;
- default:
- printf ("Invalid system data %u, setting failsafe\n", System);
- System = FAILSAFE_BOOT;
- }
-
- if ((Count < 1) | (Count > MAX_ATTEMPTS)) {
- printf ("Invalid boot count %u, setting 1\n", Count);
- Count = 1;
- }
-
- printf ("Boot attempt %d\n", Count);
-
- data = (System << 8) | Count;
- /* AMD 16 bit */
- WRITE_FLASH16 (&flash[0x555], 0xAAAA);
- WRITE_FLASH16 (&flash[0x2AA], 0x5555);
- WRITE_FLASH16 (&flash[0x555], 0xA0A0);
-
- WRITE_FLASH16 (addr, data);
-}
-
-static int random_system(void){
- /* EEPROM read failed. Just try to choose one
- system release and hope it works */
-
- /* FIXME */
- return(SYSTEM_BOOT);
-}
-
-static int switch_system(int old_system){
- u8 Rx[10];
- u8 Tx[5];
- int valid_release;
-
- if(old_system==FAILSAFE_BOOT){
- /* Find out which system release to use */
-
- /* Copy from nvram to scratchpad */
- Tx[0] = RECALL_MEMORY;
- Tx[1] = 7; /* Page */
- if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) {
- printf ("EE user page 7 recall failed\n");
- return (random_system());
- }
-
- Tx[0] = READ_SCRATCHPAD;
- if (ee_do_cpu_command (Tx, 2, Rx, 9, 1)) {
- printf ("EE user page 7 read failed\n");
- return (random_system());
- }
- /* Crc in 9:th byte */
- if (!ee_crc_ok (Rx, 8, *(Rx + 8))) {
- printf ("EE read failed, page 7. CRC error\n");
- return (random_system());
- }
-
- valid_release = Rx[7];
- if((valid_release==0xFF)|
- ((valid_release&1) == 0)){
- return(SYSTEM_BOOT);
- }
- else{
- return(SYSTEM2_BOOT);
- }
- }
- else{
- return(FAILSAFE_BOOT);
- }
-}
-
-static void check_boot_tries (void)
-{
- /* Count the number of boot attemps
- switch system if too many */
-
- int i;
- volatile u16 *addr;
- volatile u16 data;
- u8 system = FAILSAFE_BOOT;
- u8 count;
-
- addr = (u16 *) (CONFIG_SYS_FLASH_BASE + BOOTDATA_OFFSET);
-
- if (*addr == 0xFFFF) {
- printf ("*** No bootdata exists. ***\n");
- write_bootdata (addr, FAILSAFE_BOOT, 1);
- } else {
- /* Search for latest written bootdata */
- i = 0;
- while ((*(addr + 1) != 0xFFFF) & (i < 8000)) {
- addr++;
- i++;
- }
- if (i >= 8000) {
- /* Whoa, dont write any more */
- printf ("*** No bootdata found. Not updating flash***\n");
- } else {
- /* See how many times we have tried to boot real system */
- data = *addr;
- system = data >> 8;
- count = data & 0xFF;
- if ((system != SYSTEM_BOOT) &
- (system != SYSTEM2_BOOT) &
- (system != FAILSAFE_BOOT)) {
- printf ("*** Wrong system %d\n", system);
- system = FAILSAFE_BOOT;
- count = 1;
- } else {
- switch (count) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- /* Try same system again if needed */
- count++;
- break;
-
- case 5:
- /* Switch system and reset tries */
- count = 1;
- system = switch_system(system);
- printf ("***Too many boot attempts, switching system***\n");
- break;
- default:
- /* Switch system, start over and hope it works */
- printf ("***Unexpected data on addr 0x%x, %u***\n",
- (u32) addr, data);
- count = 1;
- system = switch_system(system);
- }
- }
- write_bootdata (addr + 1, system, count);
- }
- }
- switch(system){
- case FAILSAFE_BOOT:
- printf ("Booting failsafe system\n");
- setenv ("bootargs", "panic=1 root=/dev/hda7");
- setenv ("bootcmd", "ide reset;disk 0x81000000 0:5;run addmisc;bootm");
- break;
-
- case SYSTEM_BOOT:
- printf ("Using normal system\n");
- setenv ("bootargs", "panic=1 root=/dev/hda4");
- setenv ("bootcmd", "ide reset;disk 0x81000000 0:2;run addmisc;bootm");
- break;
-
- case SYSTEM2_BOOT:
- printf ("Using normal system2\n");
- setenv ("bootargs", "panic=1 root=/dev/hda9");
- setenv ("bootcmd", "ide reset;disk 0x81000000 0:8;run addmisc;bootm");
- break;
- default:
- printf ("Invalid system %d\n", system);
- printf ("Hanging\n");
- while(1);
- }
-}
-
-int misc_init_r(void){
- u8 Rx[80];
- u8 Tx[5];
- int page;
- int read = 0;
-
- WATCHDOG_RESET();
-
- if (ee_init_cpu_data ()) {
- printf ("EEPROM init failed\n");
- return (0);
- }
-
- /* Check which release to boot */
- check_boot_tries ();
-
- /* Read the pages where ethernet address is stored */
-
- for (page = EE_USER_PAGE_0; page <= EE_USER_PAGE_0 + 2; page++) {
- /* Copy from nvram to scratchpad */
- Tx[0] = RECALL_MEMORY;
- Tx[1] = page;
- if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) {
- printf ("EE user page %d recall failed\n", page);
- return (0);
- }
-
- Tx[0] = READ_SCRATCHPAD;
- if (ee_do_cpu_command (Tx, 2, Rx + read, 9, 1)) {
- printf ("EE user page %d read failed\n", page);
- return (0);
- }
- /* Crc in 9:th byte */
- if (!ee_crc_ok (Rx + read, 8, *(Rx + read + 8))) {
- printf ("EE read failed, page %d. CRC error\n", page);
- return (0);
- }
- read += 8;
- }
-
- /* Add eos after eth addr */
- Rx[17] = 0;
-
- printf ("Ethernet addr read from eeprom: %s\n\n", Rx);
-
- if ((Rx[2] != ':') |
- (Rx[5] != ':') |
- (Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) {
- printf ("*** ethernet addr invalid, using default ***\n");
- } else {
- setenv ("ethaddr", (char *)Rx);
- }
- return (0);
-}
+++ /dev/null
-/* Memory sub-system initialization code */
-
-#include <config.h>
-#include <asm/regdef.h>
-#include <asm/au1x00.h>
-#include <asm/mipsregs.h>
-
-#define CP0_Config0 $16
-#define MEM_1MS ((CONFIG_SYS_MHZ) * 1000)
-#define GPIO_RJ1LY (1<<22)
-#define GPIO_CFRESET (1<<10)
-
- .text
- .set noreorder
- .set mips32
-
- .globl lowlevel_init
-lowlevel_init:
- /*
- * Step 2) Establish Status Register
- * (set BEV, clear ERL, clear EXL, clear IE)
- */
- li t1, 0x00400000
- mtc0 t1, CP0_STATUS
-
- /*
- * Step 3) Establish CP0 Config0
- * (set OD, set K0=3)
- */
- li t1, 0x00080003
- mtc0 t1, CP0_CONFIG
-
- /*
- * Step 4) Disable Watchpoint facilities
- */
- li t1, 0x00000000
- mtc0 t1, CP0_WATCHLO
- mtc0 t1, CP0_IWATCHLO
- /*
- * Step 5) Disable the performance counters
- */
- mtc0 zero, CP0_PERFORMANCE
- nop
-
- /*
- * Step 6) Establish EJTAG Debug register
- */
- mtc0 zero, CP0_DEBUG
- nop
-
- /*
- * Step 7) Establish Cause
- * (set IV bit)
- */
- li t1, 0x00800000
- mtc0 t1, CP0_CAUSE
-
- /* Establish Wired (and Random) */
- mtc0 zero, CP0_WIRED
- nop
-
- /* No workaround if running from ram */
- lui t0, 0xffc0
- lui t3, 0xbfc0
- and t1, ra, t0
- bne t1, t3, noCacheJump
- nop
-
- /*** From AMD YAMON ***/
- /*
- * Step 8) Initialize the caches
- */
- li t0, (16*1024)
- li t1, 32
- li t2, 0x80000000
- addu t3, t0, t2
-cacheloop:
- cache 0, 0(t2)
- cache 1, 0(t2)
- addu t2, t1
- bne t2, t3, cacheloop
- nop
-
- /* Save return address */
- move t3, ra
-
- /* Run from cacheable space now */
- bal cachehere
- nop
-cachehere:
- li t1, ~0x20000000 /* convert to KSEG0 */
- and t0, ra, t1
- addi t0, 5*4 /* 5 insns beyond cachehere */
- jr t0
- nop
-
- /* Restore return address */
- move ra, t3
-
- /*
- * Step 9) Initialize the TLB
- */
- li t0, 0 # index value
- li t1, 0x00000000 # entryhi value
- li t2, 32 # 32 entries
-
-tlbloop:
- /* Probe TLB for matching EntryHi */
- mtc0 t1, CP0_ENTRYHI
- tlbp
- nop
-
- /* Examine Index[P], 1=no matching entry */
- mfc0 t3, CP0_INDEX
- li t4, 0x80000000
- and t3, t4, t3
- addiu t1, t1, 1 # increment t1 (asid)
- beq zero, t3, tlbloop
- nop
-
- /* Initialize the TLB entry */
- mtc0 t0, CP0_INDEX
- mtc0 zero, CP0_ENTRYLO0
- mtc0 zero, CP0_ENTRYLO1
- mtc0 zero, CP0_PAGEMASK
- tlbwi
-
- /* Do it again */
- addiu t0, t0, 1
- bne t0, t2, tlbloop
- nop
-
- /* First setup pll:s to make serial work ok */
- /* We have a 12.5 MHz crystal */
- li t0, SYS_CPUPLL
- li t1, 0x28 /* CPU clock, 500 MHz */
- sw t1, 0(t0)
- sync
- nop
- nop
-
- /* wait 1mS for clocks to settle */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
- /* Setup AUX PLL */
- li t0, SYS_AUXPLL
- li t1, 0
- sw t1, 0(t0) /* aux pll */
- sync
-
- /* Static memory controller */
- /* RCE0 - can not change while fetching, do so from icache */
- move t2, ra /* Store return address */
- bal getAddr
- nop
-
-getAddr:
- move t1, ra
- move ra, t2 /* Move return addess back */
-
- cache 0x14,0(t1)
- cache 0x14,32(t1)
- /*** /From YAMON ***/
-
-noCacheJump:
-
- /* Static memory controller */
-
- /* RCE0 AMD 29LV800 Flash */
- li t0, MEM_STCFG0
- li t1, 0x00000243
- sw t1, 0(t0)
-
- li t0, MEM_STTIME0
- li t1, 0x040181D7 /* FIXME */
- sw t1, 0(t0)
-
- li t0, MEM_STADDR0
- li t1, 0x11E03F80
- sw t1, 0(t0)
-
- /* RCE1 PCMCIA 250ns */
- li t0, MEM_STCFG1
- li t1, 0x00000002
- sw t1, 0(t0)
-
- li t0, MEM_STTIME1
- li t1, 0x280E3E07
- sw t1, 0(t0)
-
- li t0, MEM_STADDR1
- li t1, 0x10000000
- sw t1, 0(t0)
-
- /* RCE2 CP Altera */
- li t0, MEM_STCFG2
- li t1, 0x00000280 /* BE, EW */
- sw t1, 0(t0)
-
- li t0, MEM_STTIME2
- li t1, 0x0303000c
- sw t1, 0(t0)
-
- li t0, MEM_STADDR2
- li t1, 0x10c03f80 /* 1 MB */
- sw t1, 0(t0)
-
- /* RCE3 DP Altera */
- li t0, MEM_STCFG3
- li t1, 0x00000280 /* BE, EW */
- sw t1, 0(t0)
-
- li t0, MEM_STTIME3
- li t1, 0x0303000c
- sw t1, 0(t0)
-
- li t0, MEM_STADDR3
- li t1, 0x10e03f80 /* 1 MB */
- sw t1, 0(t0)
-
- sync
-
- /* Set peripherals to a known state */
- li t0, IC0_CFG0CLR
- li t1, 0xFFFFFFFF
- sw t1, 0(t0)
-
- li t0, IC0_CFG0CLR
- sw t1, 0(t0)
-
- li t0, IC0_CFG1CLR
- sw t1, 0(t0)
-
- li t0, IC0_CFG2CLR
- sw t1, 0(t0)
-
- li t0, IC0_SRCSET
- sw t1, 0(t0)
-
- li t0, IC0_ASSIGNSET
- sw t1, 0(t0)
-
- li t0, IC0_WAKECLR
- sw t1, 0(t0)
-
- li t0, IC0_RISINGCLR
- sw t1, 0(t0)
-
- li t0, IC0_FALLINGCLR
- sw t1, 0(t0)
-
- li t0, IC0_TESTBIT
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, IC1_CFG0CLR
- li t1, 0xFFFFFFFF
- sw t1, 0(t0)
-
- li t0, IC1_CFG0CLR
- sw t1, 0(t0)
-
- li t0, IC1_CFG1CLR
- sw t1, 0(t0)
-
- li t0, IC1_CFG2CLR
- sw t1, 0(t0)
-
- li t0, IC1_SRCSET
- sw t1, 0(t0)
-
- li t0, IC1_ASSIGNSET
- sw t1, 0(t0)
-
- li t0, IC1_WAKECLR
- sw t1, 0(t0)
-
- li t0, IC1_RISINGCLR
- sw t1, 0(t0)
-
- li t0, IC1_FALLINGCLR
- sw t1, 0(t0)
-
- li t0, IC1_TESTBIT
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, SYS_FREQCTRL0
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_FREQCTRL1
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_CLKSRC
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_PININPUTEN
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, 0xB1100100
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, 0xB1400100
- li t1, 0x00000000
- sw t1, 0(t0)
-
-
- li t0, SYS_WAKEMSK
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_WAKESRC
- li t1, 0x00000000
- sw t1, 0(t0)
-
- /* wait 1mS before setup */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
-
-
-/* SDCS 0 SDRAM */
- li t0, MEM_SDMODE0
- li t1, 0x592CD1
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE1
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE2
- li t1, 0x00000000
- sw t1, 0(t0)
-
-/* 64 MB SDRAM at addr 0 */
- li t0, MEM_SDADDR0
- li t1, 0x001003F0
- sw t1, 0(t0)
-
-
- li t0, MEM_SDADDR1
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR2
- li t1, 0x00000000
- sw t1, 0(t0)
-
- sync
-
- li t0, MEM_SDREFCFG
- li t1, 0x880007A1 /* Disable */
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDPRECMD
- sw zero, 0(t0)
- sync
-
- li t0, MEM_SDAUTOREF
- sw zero, 0(t0)
- sync
- sw zero, 0(t0)
- sync
-
- li t0, MEM_SDREFCFG
- li t1, 0x8A0007A1 /* Enable */
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD0
- li t1, 0x00000023
- sw t1, 0(t0)
- sync
-
- /* wait 1mS after setup */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
-
- /* Setup GPIO pins */
-
- li t0, SYS_PINFUNC
- li t1, 0x00007025 /* 0x8080 */
- sw t1, 0(t0)
-
- li t0, SYS_TRIOUTCLR
- li t1, 0xFFFFFFFF /* 0x1FFF */
- sw t1, 0(t0)
-
- /* Turn yellow front led on */
- /* Release reset on CF */
- li t0, SYS_OUTPUTCLR
- li t1, GPIO_RJ1LG
- sw t1, 0(t0)
- li t0, SYS_OUTPUTSET
- li t1, GPIO_RJ1LY|GPIO_CFRESET
- sw t1, 0(t0)
- sync
- j clearmem
- nop
-
-#if 0
- .globl memtest
-#endif
-memtest:
- /* Fill memory with address */
- li t0, 0x80000000
- li t1, 0xFFF000 /* 64 MB */
-mt0: sw t0, 0(t0)
- add t1, -1
- add t0, 4
- bne t1, zero, mt0
- nop
- nop
- /* Verify addr */
- li t0, 0x80000000
- li t1, 0xFFF000 /* 64 MB */
-mt1: lw t2, 0(t0)
- bne t0, t2, memhang
- add t1, -1
- add t0, 4
- bne t1, zero, mt1
- nop
- nop
-#if 0
- .globl clearmem
-#endif
-clearmem:
- /* Clear memory */
- li t0, 0x80000000
- li t1, 0xFFF000 /* 64 MB */
-mtc: sw zero, 0(t0)
- add t1, -1
- add t0, 4
- bne t1, zero, mtc
- nop
- nop
-memtestend:
- jr ra
- nop
-
-memhang:
- b memhang
- nop
+++ /dev/null
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data*) }
-
- . = .;
- _gp = ALIGN(16) + 0x7ff0;
-
- .got : {
- __got_start = .;
- *(.got)
- __got_end = .;
- }
-
- .sdata : { *(.sdata*) }
-
- .u_boot_cmd : {
- __u_boot_cmd_start = .;
- *(.u_boot_cmd)
- __u_boot_cmd_end = .;
- }
-
- uboot_end_data = .;
- num_got_entries = (__got_end - __got_start) >> 2;
-
- . = ALIGN(4);
- .sbss (NOLOAD) : { *(.sbss*) }
- .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
- uboot_end = .;
-}
writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr);
/* Set up clock to 532MHz */
- writel(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) |
+ writel(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) |
PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |
PDR0_MCU_PODF(0), &ccm->pdr0);
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- return omap_ehci_hcd_init(&usbhs_bdata);
+ return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return omap_ehci_hcd_stop();
}
REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
- REG CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
+ REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
--- /dev/null
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := iconnect.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <uboot@lukaperkov.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "iconnect.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ kw_config_gpio(ICONNECT_OE_VAL_LOW,
+ ICONNECT_OE_VAL_HIGH,
+ ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn, /* Reset signal */
+ MPP7_GPO,
+ MPP8_TW_SDA, /* I2C */
+ MPP9_TW_SCK, /* I2C */
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO, /* Reset button */
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GE1_0,
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GE1_14,
+ MPP35_GPIO, /* OTB button */
+ MPP36_AUDIO_SPDIFI,
+ MPP37_AUDIO_SPDIFO,
+ MPP38_GPIO,
+ MPP39_TDM_SPI_CS0,
+ MPP40_TDM_SPI_SCK,
+ MPP41_GPIO, /* LED brightness */
+ MPP42_GPIO, /* LED power (blue) */
+ MPP43_GPIO, /* LED power (red) */
+ MPP44_GPIO, /* LED USB 1 */
+ MPP45_GPIO, /* LED USB 2 */
+ MPP46_GPIO, /* LED USB 3 */
+ MPP47_GPIO, /* LED USB 4 */
+ MPP48_GPIO, /* LED OTB */
+ MPP49_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <uboot@lukaperkov.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ICONNECT_H
+#define __ICONNECT_H
+
+#define ICONNECT_OE_LOW (~(1 << 7))
+#define ICONNECT_OE_HIGH (~(1 << 10))
+#define ICONNECT_OE_VAL_LOW (0)
+#define ICONNECT_OE_VAL_HIGH (1 << 10)
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __ICONNECT_H */
--- /dev/null
+#
+# (C) Copyright 2009-2012
+# Wojciech Dubowik <wojciech.dubowik@neratec.com>
+# Luka Perkov <uboot@lukaperkov.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xffd100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xffd01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
+# bit23-14: 0x0,
+# bit24: 0x1, enable exit self refresh mode on DDR access
+# bit25: 0x1, required
+# bit29-26: 0x0,
+# bit31-30: 0x1,
+
+DATA 0xffd01404 0x37543000 # DDR Controller Control Low
+# bit4: 0x0, addr/cmd in smame cycle
+# bit5: 0x0, clk is driven during self refresh, we don't care for APX
+# bit6: 0x0, use recommended falling edge of clk for addr/cmd
+# bit14: 0x0, input buffer always powered up
+# bit18: 0x1, cpu lock transaction enabled
+# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 0x3, required
+# bit31: 0x0, no additional STARTBURST delay
+
+DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11-8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: 0x0, required
+
+DATA 0xffd01410 0x000000cc # DDR Address Control
+# bit1-0: 00, Cs0width (x8)
+# bit3-2: 11, Cs0size (1Gb)
+# bit5-4: 00, Cs1width (x8)
+# bit7-6: 11, Cs1size (1Gb)
+# bit9-8: 00, Cs2width (nonexistent)
+# bit11-10: 00, Cs2size (nonexistent)
+# bit13-12: 00, Cs3width (nonexistent)
+# bit15-14: 00, Cs3size (nonexistent)
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0x0, required
+
+DATA 0xffd01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0x0, required
+
+DATA 0xffd01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0x0, required
+
+DATA 0xffd0141c 0x00000c52 # DDR Mode
+# bit2-0: 0x2, BurstLen=2 required
+# bit3: 0x0, BurstType=0 required
+# bit6-4: 0x4, CL=5
+# bit7: 0x0, TestMode=0 normal
+# bit8: 0x0, DLL reset=0 normal
+# bit11-9: 0x6, auto-precharge write recovery ????????????
+# bit12: 0x0, PD must be zero
+# bit31-13: 0x0, required
+
+DATA 0xffd01420 0x00000040 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 0x0, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 0x0, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0x0, required
+
+DATA 0xffd01424 0x0000f17f # DDR Controller Control High
+# bit2-0: 0x7, required
+# bit3: 0x1, MBUS Burst Chop disabled
+# bit6-4: 0x7, required
+# bit7: 0x0,
+# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9: 0x0, no half clock cycle addition to dataout
+# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf, required
+# bit31-16: 0x0, required
+
+DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xffd01504 0x0ffffff1 # CS[0]n Size
+# bit0: 0x1, Window enabled
+# bit1: 0x0, Write Protect disabled
+# bit3-2: 0x0, CS0 hit selected
+# bit23-4: 0xfffff, required
+# bit31-24: 0x0f, Size (i.e. 256MB)
+
+DATA 0xffd01508 0x00000000 # CS[1]n Base address to 256Mb
+DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled
+
+DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
+# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
+# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 0x1, ODT1 active NEVER!
+# bit31-4: 0x0, required
+
+DATA 0xffd0149c 0x0000e803 # CPU ODT Control
+DATA 0xffd01480 0x00000001 # DDR Initialization Control
+# bit0: 0x1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
*/
#include <asm/macro.h>
-
-.macro init_aips
- write32 0x43f00000, 0x77777777
- write32 0x43f00004, 0x77777777
- write32 0x43f00000, 0x77777777
- write32 0x53f00004, 0x77777777
-.endm
-
-.macro init_max
- write32 0x43f04000, 0x43210
- write32 0x43f04100, 0x43210
- write32 0x43f04200, 0x43210
- write32 0x43f04300, 0x43210
- write32 0x43f04400, 0x43210
-
- write32 0x43f04010, 0x10
- write32 0x43f04110, 0x10
- write32 0x43f04210, 0x10
- write32 0x43f04310, 0x10
- write32 0x43f04410, 0x10
-
- write32 0x43f04800, 0x0
- write32 0x43f04900, 0x0
- write32 0x43f04a00, 0x0
- write32 0x43f04b00, 0x0
- write32 0x43f04c00, 0x0
-.endm
-
-.macro init_m3if
- write32 0xb8003000, 0x1
-.endm
+#include <asm/arch/macro.h>
.macro init_clocks
/*
* 0x00600000 makes CLKO parent clk the USB clk
*/
write32 0x53f80064, 0x45600000
+
+ /* CCTL: ARM = 399 MHz, AHB = 133 MHz */
write32 0x53f80008, 0x20034000
/*
+ * PCDR2: NFC = 33.25 MHz
+ * This is required for the NAND Flash of this board, which is a Samsung
+ * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with
+ * the NFC driver in symmetric (i.e. one-cycle) mode.
+ */
+ write32 0x53f80020, 0x01010103
+
+ /*
* enable all implemented clocks in all three
* clock control registers
*/
tmp = readl(KW_GPIO0_BASE + 4);
writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
#endif
-
+ /* adjust SDRAM size for bank 0 */
+ kw_sdram_size_adjust(0);
kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
/* reset the phy */
miiphy_reset(name, CONFIG_PHY_BASE_ADR);
}
+#elif defined(CONFIG_KM_PIGGY4_88E6352)
+
+#include <mv88e6352.h>
+
+#if defined(CONFIG_KM_NUSA)
+struct mv88e_sw_reg extsw_conf[] = {
+ /*
+ * port 0, PIGGY4, autoneg
+ * first the fix for the 1000Mbits Autoneg, this is from
+ * a Marvell errata, the regs are undocumented
+ */
+ { PHY(0), PHY_PAGE, AN1000FIX_PAGE },
+ { PHY(0), PHY_STATUS, AN1000FIX },
+ { PHY(0), PHY_PAGE, 0 },
+ /* now the real port and phy configuration */
+ { PORT(0), PORT_PHY, NO_SPEED_FOR },
+ { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ { PHY(0), PHY_1000_CTRL, NO_ADV },
+ { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
+ { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
+ FULL_DUPLEX },
+ /* port 1, unused */
+ { PORT(1), PORT_CTRL, PORT_DIS },
+ { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
+ { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+ /* port 2, unused */
+ { PORT(2), PORT_CTRL, PORT_DIS },
+ { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
+ { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+ /* port 3, unused */
+ { PORT(3), PORT_CTRL, PORT_DIS },
+ { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
+ { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+ /* port 4, ICNEV, SerDes, SGMII */
+ { PORT(4), PORT_STATUS, NO_PHY_DETECT },
+ { PORT(4), PORT_PHY, SPEED_1000_FOR },
+ { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
+ { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+ /* port 5, CPU_RGMII */
+ { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
+ FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
+ FULL_DPX_FOR | SPEED_1000_FOR },
+ { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ /* port 6, unused, this port has no phy */
+ { PORT(6), PORT_CTRL, PORT_DIS },
+};
+#else
+struct mv88e_sw_reg extsw_conf[] = {};
+#endif
+
+void reset_phy(void)
+{
+#if defined(CONFIG_KM_MVEXTSW_ADDR)
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
+ ARRAY_SIZE(extsw_conf));
+ mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
+#endif
+}
+
#else
/* Configure and enable MV88E1118 PHY on the piggy*/
void reset_phy(void)
--- /dev/null
+#
+# (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+# (C) Copyright 2012 Renesas Solutions Corp.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := kzm9g.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj) .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <netdev.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CS0BCR_D (0x06C00400)
+#define CS4BCR_D (0x16c90400)
+#define CS0WCR_D (0x55062C42)
+#define CS4WCR_D (0x1e071dc3)
+
+#define CMNCR_BROMMD0 (1 << 21)
+#define CMNCR_BROMMD1 (1 << 22)
+#define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1)
+#define VCLKCR1_D (0x27)
+
+#define SMSTPCR1_CMT0 (1 << 24)
+#define SMSTPCR1_I2C0 (1 << 16)
+#define SMSTPCR3_USB (1 << 22)
+
+#define PORT32CR (0xE6051020)
+#define PORT33CR (0xE6051021)
+#define PORT34CR (0xE6051022)
+#define PORT35CR (0xE6051023)
+
+static int cmp_loop(u32 *addr, u32 data, u32 cmp)
+{
+ int err = -1;
+ int timeout = 100;
+ u32 value;
+
+ while (timeout > 0) {
+ value = readl(addr);
+ if ((value & data) == cmp) {
+ err = 0;
+ break;
+ }
+ timeout--;
+ }
+
+ return err;
+}
+
+/* SBSC Init function */
+static void sbsc_init(struct sh73a0_sbsc *sbsc)
+{
+ writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0);
+ writel(0x5, &sbsc->sdgencnt);
+ cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+
+ writel(0xacc90159, &sbsc->sdcr0);
+ writel(0x00010059, &sbsc->sdcr1);
+ writel(0x50874114, &sbsc->sdwcrc0);
+ writel(0x33199b37, &sbsc->sdwcrc1);
+ writel(0x008f2313, &sbsc->sdwcrc2);
+ writel(0x31020707, &sbsc->sdwcr00);
+ writel(0x0017040a, &sbsc->sdwcr01);
+ writel(0x31020707, &sbsc->sdwcr10);
+ writel(0x0017040a, &sbsc->sdwcr11);
+ writel(0x05555555, &sbsc->sddrvcr0);
+ writel(0x30000000, &sbsc->sdwcr2);
+
+ writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr);
+ cmp_loop(&sbsc->sdpcr, 0x80, 0x80);
+
+ writel(0x00002710, &sbsc->sdgencnt);
+ cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+
+ writel(0x0000003f, &sbsc->sdmracr0);
+ writel(0x0, SDMRA1A);
+ writel(0x000001f4, &sbsc->sdgencnt);
+ cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+
+ writel(0x0000ff0a, &sbsc->sdmracr0);
+ if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE)
+ writel(0x0, SDMRA3A);
+ else
+ writel(0x0, SDMRA3B);
+
+ writel(0x00000032, &sbsc->sdgencnt);
+ cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+
+ if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) {
+ writel(0x00002201, &sbsc->sdmracr0);
+ writel(0x0, SDMRA1A);
+ writel(0x00000402, &sbsc->sdmracr0);
+ writel(0x0, SDMRA1A);
+ writel(0x00000403, &sbsc->sdmracr0);
+ writel(0x0, SDMRA1A);
+ writel(0x0, SDMRA2A);
+ } else {
+ writel(0x00002201, &sbsc->sdmracr0);
+ writel(0x0, SDMRA1B);
+ writel(0x00000402, &sbsc->sdmracr0);
+ writel(0x0, SDMRA1B);
+ writel(0x00000403, &sbsc->sdmracr0);
+ writel(0x0, SDMRA1B);
+ writel(0x0, SDMRA2B);
+ }
+
+ writel(0x88800004, &sbsc->sdmrtmpcr);
+ writel(0x00000004, &sbsc->sdmrtmpmsk);
+ writel(0xa55a0032, &sbsc->rtcor);
+ writel(0xa55a000c, &sbsc->rtcorh);
+ writel(0xa55a2048, &sbsc->rtcsr);
+ writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0);
+ writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1);
+ writel(0xfff20000, &sbsc->zqccr);
+
+ /* SCBS2 only */
+ if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) {
+ writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0);
+ writel(0xa5390000, &sbsc->dphycnt1);
+ writel(0x00001200, &sbsc->dphycnt0);
+ writel(0x07ce0000, &sbsc->dphycnt1);
+ writel(0x00001247, &sbsc->dphycnt0);
+ cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000);
+ writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0);
+ }
+}
+
+void s_init(void)
+{
+ struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE;
+ struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
+ struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
+ (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
+ struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE;
+ struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE;
+ struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+ struct sh73a0_hpb_bscr *hpb_bscr =
+ (struct sh73a0_hpb_bscr *)HPBSCR_BASE;
+
+ /* Watchdog init */
+ writew(0xA507, &rwdt->rwtcsra0);
+
+ /* Secure control register Init */
+ #define LIFEC_SEC_SRC_BIT (1 << 15)
+ writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC);
+
+ clrbits_le32(&cpg->smstpcr3, (1 << 15));
+ clrbits_le32(&cpg_srcr->srcr3, (1 << 15));
+ clrbits_le32(&cpg->smstpcr2, (1 << 18));
+ clrbits_le32(&cpg_srcr->srcr2, (1 << 18));
+ writel(0x0, &cpg->pllecr);
+
+ cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
+ cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
+
+ writel(0x2D000000, &cpg->pll0cr);
+ writel(0x17100000, &cpg->pll1cr);
+ writel(0x96235880, &cpg->frqcrb);
+ cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
+
+ writel(0xB, &cpg->flckcr);
+ clrbits_le32(&cpg->smstpcr0, (1 << 1));
+
+ clrbits_le32(&cpg_srcr->srcr0, (1 << 1));
+ writel(0x0514, &hpb_bscr->smgpiotime);
+ writel(0x0514, &hpb_bscr->smcmt2time);
+ writel(0x0514, &hpb_bscr->smcpgtime);
+ writel(0x0514, &hpb_bscr->smsysctime);
+
+ writel(0x00092000, &cpg->dvfscr4);
+ writel(0x000000DC, &cpg->dvfscr5);
+ writel(0x0, &cpg->pllecr);
+ cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
+
+ /* FRQCR Init */
+ writel(0x0012453C, &cpg->frqcra);
+ writel(0x80331350, &cpg->frqcrb);
+ cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
+ writel(0x00000B0B, &cpg->frqcrd);
+ cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
+
+ /* Clock Init */
+ writel(0x00000003, PCLKCR);
+ writel(0x0000012F, &cpg->vclkcr1);
+ writel(0x00000119, &cpg->vclkcr2);
+ writel(0x00000119, &cpg->vclkcr3);
+ writel(0x00000002, &cpg->zbckcr);
+ writel(0x00000005, &cpg->flckcr);
+ writel(0x00000080, &cpg->sd0ckcr);
+ writel(0x00000080, &cpg->sd1ckcr);
+ writel(0x00000080, &cpg->sd2ckcr);
+ writel(0x0000003F, &cpg->fsiackcr);
+ writel(0x0000003F, &cpg->fsibckcr);
+ writel(0x00000080, &cpg->subckcr);
+ writel(0x0000000B, &cpg->spuackcr);
+ writel(0x0000000B, &cpg->spuvckcr);
+ writel(0x0000013F, &cpg->msuckcr);
+ writel(0x00000080, &cpg->hsickcr);
+ writel(0x0000003F, &cpg->mfck1cr);
+ writel(0x0000003F, &cpg->mfck2cr);
+ writel(0x00000107, &cpg->dsitckcr);
+ writel(0x00000313, &cpg->dsi0pckcr);
+ writel(0x0000130D, &cpg->dsi1pckcr);
+ writel(0x2A800E0E, &cpg->dsi0phycr);
+ writel(0x1E000000, &cpg->pll0cr);
+ writel(0x2D000000, &cpg->pll0cr);
+ writel(0x17100000, &cpg->pll1cr);
+ writel(0x27000080, &cpg->pll2cr);
+ writel(0x1D000000, &cpg->pll3cr);
+ writel(0x00080000, &cpg->pll0stpcr);
+ writel(0x000120C0, &cpg->pll1stpcr);
+ writel(0x00012000, &cpg->pll2stpcr);
+ writel(0x00000030, &cpg->pll3stpcr);
+
+ writel(0x0000000B, &cpg->pllecr);
+ cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00);
+
+ writel(0x000120F0, &cpg->dvfscr3);
+ writel(0x00000020, &cpg->mpmode);
+ writel(0x0000028A, &cpg->vrefcr);
+ writel(0xE4628087, &cpg->rmstpcr0);
+ writel(0xFFFFFFFF, &cpg->rmstpcr1);
+ writel(0x53FFFFFF, &cpg->rmstpcr2);
+ writel(0xFFFFFFFF, &cpg->rmstpcr3);
+ writel(0x00800D3D, &cpg->rmstpcr4);
+ writel(0xFFFFF3FF, &cpg->rmstpcr5);
+ writel(0x00000000, &cpg->smstpcr2);
+ writel(0x00040000, &cpg_srcr->srcr2);
+
+ clrbits_le32(&cpg->pllecr, (1 << 3));
+ cmp_loop(&cpg->pllecr, 0x00000800, 0x0);
+
+ writel(0x00000001, &hpb->hpbctrl6);
+ cmp_loop(&hpb->hpbctrl6, 0x1, 0x1);
+
+ writel(0x00001414, &cpg->frqcrd);
+ cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
+
+ writel(0x1d000000, &cpg->pll3cr);
+ setbits_le32(&cpg->pllecr, (1 << 3));
+ cmp_loop(&cpg->pllecr, 0x800, 0x800);
+
+ /* SBSC1 Init*/
+ sbsc_init(sbsc1);
+
+ /* SBSC2 Init*/
+ sbsc_init(sbsc2);
+
+ writel(0x00000b0b, &cpg->frqcrd);
+ cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
+ writel(0xfffffffc, &cpg->cpgxxcs4);
+}
+
+int board_early_init_f(void)
+{
+ struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
+ struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE;
+ struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
+ (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
+
+ writel(CS0BCR_D, &bsc->cs0bcr);
+ writel(CS4BCR_D, &bsc->cs4bcr);
+ writel(CS0WCR_D, &bsc->cs0wcr);
+ writel(CS4WCR_D, &bsc->cs4wcr);
+
+ clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD);
+
+ clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
+ clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
+ clrbits_le32(&cpg->smstpcr3, SMSTPCR3_USB);
+ clrbits_le32(&cpg_srcr->srcr3, SMSTPCR3_USB);
+ writel(VCLKCR1_D, &cpg->vclkcr1);
+
+ /* Setup SCIF4 / workaround */
+ writeb(0x12, PORT32CR);
+ writeb(0x22, PORT33CR);
+ writeb(0x12, PORT34CR);
+ writeb(0x22, PORT35CR);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ sh73a0_pinmux_init();
+
+ /* SCIFA 4 */
+ gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
+ gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
+ gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
+ gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
+
+ /* Ethernet/SMSC */
+ gpio_request(GPIO_PORT224, NULL);
+ gpio_direction_input(GPIO_PORT224);
+
+ /* SMSC/USB */
+ gpio_request(GPIO_FN_CS4_, NULL);
+
+ /* MMCIF */
+ gpio_request(GPIO_FN_MMCCLK0, NULL);
+ gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
+ gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
+ gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
+ gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
+ gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
+ gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
+ gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
+ gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
+ gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
+
+ /* SDHI */
+ gpio_request(GPIO_FN_SDHIWP0, NULL);
+ gpio_request(GPIO_FN_SDHICD0, NULL);
+ gpio_request(GPIO_FN_SDHICMD0, NULL);
+ gpio_request(GPIO_FN_SDHICLK0, NULL);
+ gpio_request(GPIO_FN_SDHID0_3, NULL);
+ gpio_request(GPIO_FN_SDHID0_2, NULL);
+ gpio_request(GPIO_FN_SDHID0_1, NULL);
+ gpio_request(GPIO_FN_SDHID0_0, NULL);
+ gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
+ gpio_request(GPIO_PORT15, NULL);
+ gpio_direction_output(GPIO_PORT15, 1);
+
+ /* I2C */
+ gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
+ gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
+
+ gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+
+ return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+ CONFIG_RMOBILE_BOARD_STRING
+};
+
+int dram_init(void)
+{
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+#ifdef CONFIG_SMC911X
+ ret = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return ret;
+}
+
+void reset_cpu(ulong addr)
+{
+ /* Soft Power On Reset */
+ writel((1 << 31), RESCNT2);
+}
REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
- REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
+ REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)
REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
struct serial_device *default_serial_console(void)
{
- return ZOOM2_DEFAULT_SERIAL_DEVICE;
+ switch (ZOOM2_DEFAULT_SERIAL_DEVICE) {
+ case 0: return &zoom2_serial_device0;
+ case 1: return &zoom2_serial_device1;
+ case 2: return &zoom2_serial_device2;
+ case 3: return &zoom2_serial_device3;
+ }
}
#ifndef ZOOM2_SERIAL_H
#define ZOOM2_SERIAL_H
+#include <linux/stringify.h>
+
extern int zoom2_debug_board_connected (void);
#define SERIAL_TL16CP754C_BASE 0x10000000 /* Zoom2 Serial chip address */
#define QUAD_BASE_2 (SERIAL_TL16CP754C_BASE + 0x200)
#define QUAD_BASE_3 (SERIAL_TL16CP754C_BASE + 0x300)
-#define S(a) #a
-#define N(a) S(quad##a)
-
#define QUAD_INIT(n) \
int quad_init_##n(void) \
{ \
} \
struct serial_device zoom2_serial_device##n = \
{ \
- N(n), \
- quad_init_##n, \
- NULL, \
- quad_setbrg_##n, \
- quad_getc_##n, \
- quad_tstc_##n, \
- quad_putc_##n, \
- quad_puts_##n, \
+ .name = __stringify(n), \
+ .start = quad_init_##n, \
+ .stop = NULL, \
+ .setbrg = quad_setbrg_##n, \
+ .getc = quad_getc_##n, \
+ .tstc = quad_tstc_##n, \
+ .putc = quad_putc_##n, \
+ .puts = quad_puts_##n, \
};
#endif /* ZOOM2_SERIAL_H */
+++ /dev/null
-/*
- * flash.c: Support code for the flash chips on the Xilinx ML2 board
- *
- * Copyright 2002 Mind NV
- *
- * http://www.mind.be/
- *
- * Author : Peter De Schrijver (p2@mind.be)
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL) version 2, incorporated herein by
- * reference. Drivers based on or derived from this code fall under the GPL
- * and must retain the authorship, copyright and this license notice. This
- * file is not a complete program and may only be used when the entire program
- * is licensed under the GPL.
- *
- */
-
-#include <common.h>
-#include <asm/u-boot.h>
-#include <configs/ML2.h>
-
-#define FLASH_BANK_SIZE (64*1024*1024)
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-#define SECT_SIZE (512*1024)
-
-#define CMD_READ_ARRAY 0x00FF00FF00FF00FULL
-#define CMD_IDENTIFY 0x0090009000900090ULL
-#define CMD_ERASE_SETUP 0x0020002000200020ULL
-#define CMD_ERASE_CONFIRM 0x00D000D000D000D0ULL
-#define CMD_PROGRAM 0x0040004000400040ULL
-#define CMD_RESUME 0x00D000D000D000D0ULL
-#define CMD_SUSPEND 0x00B000B000B000B0ULL
-#define CMD_STATUS_READ 0x0070007000700070ULL
-#define CMD_STATUS_RESET 0x0050005000500050ULL
-
-#define BIT_BUSY 0x0080008000800080ULL
-#define BIT_ERASE_SUSPEND 0x004000400400040ULL
-#define BIT_ERASE_ERROR 0x0020002000200020ULL
-#define BIT_PROGRAM_ERROR 0x0010001000100010ULL
-#define BIT_VPP_RANGE_ERROR 0x0008000800080008ULL
-#define BIT_PROGRAM_SUSPEND 0x0004000400040004ULL
-#define BIT_PROTECT_ERROR 0x0002000200020002ULL
-#define BIT_UNDEFINED 0x0001000100010001ULL
-
-#define BIT_SEQUENCE_ERROR 0x0030003000300030ULL
-
-#define BIT_TIMEOUT 0x80000000
-
-
-inline void eieio(void) {
-
- __asm__ __volatile__ ("eieio" : : : "memory");
-
-}
-
-ulong flash_init(void) {
-
- int i, j;
- ulong size = 0;
-
- for(i=0;i<CONFIG_SYS_MAX_FLASH_BANKS;i++) {
- ulong flashbase = 0;
-
- flash_info[i].flash_id = (INTEL_MANUFACT & FLASH_VENDMASK) |
- (INTEL_ID_28F128J3A & FLASH_TYPEMASK);
- flash_info[i].size = FLASH_BANK_SIZE;
- flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
- if (i==0)
- flashbase = CONFIG_SYS_FLASH_BASE;
- else
- panic("configured too many flash banks!\n");
- for (j = 0; j < flash_info[i].sector_count; j++)
- flash_info[i].start[j]=flashbase + j * SECT_SIZE;
-
- size += flash_info[i].size;
- }
-
- return size;
-}
-
-void flash_print_info (flash_info_t *info) {
-
- int i;
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case (INTEL_MANUFACT & FLASH_VENDMASK):
- printf("Intel: ");
- break;
- default:
- printf("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case (INTEL_ID_28F128J3A & FLASH_TYPEMASK):
- printf("4x 28F128J3A (128Mbit)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- break;
- }
-
- printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; i++) {
- if ((i % 5) == 0)
- printf("\n ");
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
-}
-
-int flash_error (unsigned long long code) {
-
- if (code & BIT_TIMEOUT) {
- printf ("Timeout\n");
- return ERR_TIMOUT;
- }
-
- if (~code & BIT_BUSY) {
- printf ("Busy\n");
- return ERR_PROG_ERROR;
- }
-
- if (code & BIT_VPP_RANGE_ERROR) {
- printf ("Vpp range error\n");
- return ERR_PROG_ERROR;
- }
-
- if (code & BIT_PROTECT_ERROR) {
- printf ("Device protect error\n");
- return ERR_PROG_ERROR;
- }
-
- if (code & BIT_SEQUENCE_ERROR) {
- printf ("Command seqence error\n");
- return ERR_PROG_ERROR;
- }
-
- if (code & BIT_ERASE_ERROR) {
- printf ("Block erase error\n");
- return ERR_PROG_ERROR;
- }
-
- if (code & BIT_PROGRAM_ERROR) {
- printf ("Program error\n");
- return ERR_PROG_ERROR;
- }
-
- if (code & BIT_ERASE_SUSPEND) {
- printf ("Block erase suspended\n");
- return ERR_PROG_ERROR;
- }
-
- if (code & BIT_PROGRAM_SUSPEND) {
- printf ("Program suspended\n");
- return ERR_PROG_ERROR;
- }
-
- return ERR_OK;
-
-}
-
-int flash_erase (flash_info_t *info, int s_first, int s_last) {
-
- int rc = ERR_OK;
- int sect;
- unsigned long long result;
-
- if (info->flash_id == FLASH_UNKNOWN)
- return ERR_UNKNOWN_FLASH_TYPE;
-
- if ((s_first < 0) || (s_first > s_last))
- return ERR_INVAL;
-
- if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
- return ERR_UNKNOWN_FLASH_VENDOR;
-
- for (sect=s_first; sect<=s_last; ++sect)
- if (info->protect[sect])
- return ERR_PROTECTED;
-
- for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
- volatile unsigned long long *addr=
- (unsigned long long *)(info->start[sect]);
-
- printf("Erasing sector %2d ... ", sect);
-
- *addr=CMD_STATUS_RESET;
- eieio();
- *addr=CMD_ERASE_SETUP;
- eieio();
- *addr=CMD_ERASE_CONFIRM;
- eieio();
-
- do {
- result = *addr;
- } while(~result & BIT_BUSY);
-
- *addr=CMD_READ_ARRAY;
-
- if ((rc = flash_error(result)) == ERR_OK)
- printf("ok.\n");
- else
- break;
- }
-
- if (ctrlc())
- printf("User Interrupt!\n");
-
- return rc;
-}
-
-static int write_word (flash_info_t *info, ulong dest, unsigned long long data) {
-
- volatile unsigned long long *addr=(unsigned long long *)dest;
- unsigned long long result;
- int rc = ERR_OK;
-
- result = *addr;
- if ((result & data) != data)
- return ERR_NOT_ERASED;
-
- *addr=CMD_STATUS_RESET;
- eieio();
- *addr=CMD_PROGRAM;
- eieio();
- *addr=data;
- eieio();
-
- do {
- result = *addr;
- } while(~result & BIT_BUSY);
-
- *addr=CMD_READ_ARRAY;
-
- rc = flash_error(result);
-
- return rc;
-
-}
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
-
- ulong cp, wp;
- unsigned long long data;
- int l;
- int i,rc;
-
- wp=(addr & ~7);
-
- if((l=addr-wp) != 0) {
- data=0;
- for(i=0,cp=wp;i<l;++i,++cp)
- data = (data >> 8) | (*(uchar *)cp << 24);
-
- for (; i<8 && cnt>0; ++i) {
- data = (data >> 8) | (*src++ << 24);
- --cnt;
- ++cp;
- }
-
- for (; i<8; ++i, ++cp)
- data = (data >> 8) | (*(uchar *)cp << 24);
-
- if ((rc = write_word(info, wp, data)) != 0)
- return rc;
-
- wp+=8;
- }
-
- while(cnt>=8) {
- data = *((unsigned long long *)src);
- if ((rc = write_word(info, wp, data)) != 0)
- return rc;
- src+=8;
- wp+=8;
- cnt-=8;
- }
-
- if(cnt == 0)
- return ERR_OK;
-
- data = 0;
- for (i=0, cp=wp; i<8 && cnt>0; ++i, ++cp) {
- data = (data >> 8) | (*src++ << 24);
- --cnt;
- }
- for (; i<8; ++i, ++cp) {
- data = (data >> 8) | (*(uchar *)cp << 24);
- }
-
- return write_word(info, wp, data);
-
-}
+++ /dev/null
-/*
- * init.S: Stubs for U-Boot initialization
- *
- * Copyright 2002 Mind NV
- *
- * http://www.mind.be/
- *
- * Author : Peter De Schrijver (p2@mind.be)
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL) version 2, incorporated herein by
- * reference. Drivers based on or derived from this code fall under the GPL
- * and must retain the authorship, copyright and this license notice. This
- * file is not a complete program and may only be used when the entire
- * program is licensed under the GPL.
- *
- */
-
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- blr
+++ /dev/null
-/*
- * ml2.c: U-Boot platform support for Xilinx ML2 board
- *
- * Copyright 2002 Mind NV
- *
- * http://www.mind.be/
- *
- * Author : Peter De Schrijver (p2@mind.be)
- *
- * Derived from : Other platform support files in this tree
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL) version 2, incorporated herein by
- * reference. Drivers based on or derived from this code fall under the GPL
- * and must retain the authorship, copyright and this license notice. This
- * file is not a complete program and may only be used when the entire
- * program is licensed under the GPL.
- *
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-
-int board_early_init_f (void)
-{
- return 0;
-}
-
-
-int checkboard (void)
-{
- char buf[64];
- int i;
- int l = getenv_f("serial#", buf, sizeof(buf));
-
- if (l < 0 || strncmp(buf, "ML2", 9)) {
- printf ("### No HW ID - assuming ML2");
- } else {
- for (i = 0; i < l; i++) {
- if (buf[i] == ' ')
- break;
- putc(buf[i]);
- }
- }
- putc ('\n');
-
- return (0);
-}
-
-
-phys_size_t initdram (int board_type)
-{
- return 32 * 1024 * 1024;
-}
-
-int testdram (void)
-{
- printf ("test: xxx MB - ok\n");
-
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Peter De Schrijver (p2@mind.be), Mind Linux Solutions, NV.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <asm/u-boot.h>
-#include <asm/processor.h>
-#include <command.h>
-#include <configs/ML2.h>
-
-#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
-#include <ns16550.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
-const NS16550_t COM_PORTS[] = { (NS16550_t) CONFIG_SYS_NS16550_COM1,
- (NS16550_t) CONFIG_SYS_NS16550_COM2
-};
-#endif
-
-int serial_init (void)
-{
- int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
-
-#ifdef CONFIG_SYS_INIT_CHAN1
- (void) NS16550_init (COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
- (void) NS16550_init (COM_PORTS[1], clock_divisor);
-#endif
- return 0;
-
-}
-
-void serial_putc (const char c)
-{
- if (c == '\n')
- NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
-
- NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
-}
-
-int serial_getc (void)
-{
- return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-int serial_tstc (void)
-{
- return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-void serial_setbrg (void)
-{
- int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
-
-#ifdef CONFIG_SYS_INIT_CHAN1
- NS16550_reinit (COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
- NS16550_reinit (COM_PORTS[1], clock_divisor);
-#endif
-}
-
-void serial_puts (const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
-#if defined(CONFIG_CMD_KGDB)
-void kgdb_serial_init (void)
-{
-}
-
-void putDebugChar (int c)
-{
- serial_putc (c);
-}
-
-void putDebugStr (const char *str)
-{
- serial_puts (str);
-}
-
-int getDebugChar (void)
-{
- return serial_getc ();
-}
-
-void kgdb_interruptible (int yes)
-{
- return;
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end__ = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
-
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end__ = . ;
- PROVIDE (end = .);
-}
/* init uhci
*/
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
unsigned char temp;
int busdevfunc;
/* stop uhci
*/
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
if(irqvec==-1)
return 1;
#include <ns16550.h>
#include <linux/compiler.h>
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/sys_proto.h>
-
-#include <asm/arch/board.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/emc.h>
+#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/pmc.h>
#include <asm/arch/pmu.h>
-#include <asm/arch/uart.h>
-#include <asm/arch/warmboot.h>
-#include <spi.h>
+#include <asm/arch/tegra.h>
#include <asm/arch/usb.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/sys_proto.h>
+#include <asm/arch-tegra/uart.h>
+#include <asm/arch-tegra/warmboot.h>
+#include <spi.h>
#include <i2c.h>
-#include "board.h"
#include "emc.h"
DECLARE_GLOBAL_DATA_PTR;
void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi")));
+void __gpio_early_init_uart(void)
+{
+}
+
+void gpio_early_init_uart(void)
+__attribute__((weak, alias("__gpio_early_init_uart")));
+
+void __pin_mux_nand(void)
+{
+ funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
+}
+
+void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand")));
+
/*
* Routine: power_det_init
* Description: turn off power detects
board_usb_init(gd->fdt_blob);
#endif
+#ifdef CONFIG_TEGRA_NAND
+ pin_mux_nand();
+#endif
+
#ifdef CONFIG_TEGRA_LP0
/* save Sdram params to PMC 2, 4, and 24 for WB0 */
warmboot_save_sdram_params();
/* Initialize periph GPIOs */
gpio_early_init();
-#ifdef CONFIG_SPI_UART_SWITCH
gpio_early_init_uart();
-#else
- gpio_config_uart();
-#endif
+
return 0;
}
#endif /* EARLY_INIT */
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/ap20.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/emc.h>
#include <asm/arch/pmu.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/tegra20.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/gpio.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/uart-spi-switch.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/tegra_spi.h>
-
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/tegra_spi.h>
+#include <asm/arch-tegra/board.h>
/* position of the UART/SPI select switch */
enum spi_uart_switch {
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/mmc.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/mmc.h>
#include <asm/gpio.h>
#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
#endif
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on Harmony - no conflict w/SPI.
- */
-void gpio_config_uart(void)
-{
-}
#ifdef CONFIG_TEGRA_MMC
/*
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
+#include <asm/arch/tegra.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/mmc.h>
+#include <asm/arch-tegra/mmc.h>
#include <asm/gpio.h>
#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
gpio_direction_output(GPIO_PI3, 0);
}
-void gpio_config_uart(void)
+void gpio_early_init_uart(void)
{
if (machine_is_ventana())
return;
*/
#include <common.h>
-#include <i2c.h>
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
+#include <asm/arch/tegra.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/mmc.h>
+#include <asm/arch-tegra/mmc.h>
#include <asm/gpio.h>
+#include <i2c.h>
#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
#endif
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on Whistler - no UART-related GPIOs.
- */
-void gpio_config_uart(void)
-{
-}
/*
* Routine: pin_mux_mmc
return 0;
}
-struct serial_device *default_serial_console(void)
-{
- return &serial_ffuart_device;
-}
-
int dram_init(void)
{
pxa2xx_dram_init();
return 0;
}
-struct serial_device *default_serial_console(void)
-{
- return &serial_ffuart_device;
-}
-
int dram_init(void)
{
pxa2xx_dram_init();
#include <config.h>
#include <common.h>
+#include <serial.h>
+#include <linux/compiler.h>
#include "sconsole.h"
int (*sconsole_tstc) (void) = 0;
void (*sconsole_setbrg) (void) = 0;
-int serial_init (void)
+static int sconsole_serial_init(void)
{
sconsole_buffer_t *sb = SCONSOLE_BUFFER;
return (0);
}
-void serial_putc (char c)
+static void sconsole_serial_putc(char c)
{
if (sconsole_putc) {
(*sconsole_putc) (c);
}
}
-void serial_puts (const char *s)
+static void sconsole_serial_puts(const char *s)
{
if (sconsole_puts) {
(*sconsole_puts) (s);
}
}
-int serial_getc (void)
+static int sconsole_serial_getc(void)
{
if (sconsole_getc) {
return (*sconsole_getc) ();
}
}
-int serial_tstc (void)
+static int sconsole_serial_tstc(void)
{
if (sconsole_tstc) {
return (*sconsole_tstc) ();
}
}
-void serial_setbrg (void)
+static void sconsole_serial_setbrg(void)
{
if (sconsole_setbrg) {
(*sconsole_setbrg) ();
}
}
+static struct serial_device sconsole_serial_drv = {
+ .name = "sconsole_serial",
+ .start = sconsole_serial_init,
+ .stop = NULL,
+ .setbrg = sconsole_serial_setbrg,
+ .putc = sconsole_serial_putc,
+ .puts = sconsole_serial_puts,
+ .getc = sconsole_serial_getc,
+ .tstc = sconsole_serial_tstc,
+};
+
+void sconsole_serial_initialize(void)
+{
+ serial_register(&sconsole_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &sconsole_serial_drv;
+}
+
int sconsole_get_baudrate (void)
{
sconsole_buffer_t *sb = SCONSOLE_BUFFER;
return msize;
}
-#if defined(CONFIG_SERIAL_MULTI)
static int set_lcd_brightness(char *);
-#endif
int misc_init_r(void)
{
#endif
#ifdef CONFIG_FSL_DIU_FB
-#if defined(CONFIG_SERIAL_MULTI)
set_lcd_brightness(0);
-#endif
/* Switch LCD-Backlight and LVDS-Interface on */
setbits_be32(&im->gpio.gpdir, 0x01040000);
clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-#if defined(CONFIG_SERIAL_MULTI)
/*
* If argument is NULL, set the LCD brightness to the
* value from "brightness" environment variable. Set
"set LCD brightness",
"<brightness> - set LCD backlight level to <brightness>.\n"
);
-#endif /* CONFIG_SERIAL_MULTI */
#include <common.h>
#include <command.h>
+#include <serial.h>
+#include <linux/compiler.h>
+
#include "../../Marvell/include/memory.h"
#include "serial.h"
DECLARE_GLOBAL_DATA_PTR;
-int serial_init (void)
+static int p3mx_serial_init(void)
{
mpsc_init (gd->baudrate);
return (0);
}
-void serial_putc (const char c)
+static void p3mx_serial_putc(const char c)
{
if (c == '\n')
mpsc_putchar ('\r');
mpsc_putchar (c);
}
-int serial_getc (void)
+static int p3mx_serial_getc(void)
{
return mpsc_getchar ();
}
-int serial_tstc (void)
+static int p3mx_serial_tstc(void)
{
return mpsc_test_char ();
}
-void serial_setbrg (void)
+static void p3mx_serial_setbrg(void)
{
galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
}
-void serial_puts (const char *s)
+static void p3mx_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
+static struct serial_device p3mx_serial_drv = {
+ .name = "p3mx_serial",
+ .start = p3mx_serial_init,
+ .stop = NULL,
+ .setbrg = p3mx_serial_setbrg,
+ .putc = p3mx_serial_putc,
+ .puts = p3mx_serial_puts,
+ .getc = p3mx_serial_getc,
+ .tstc = p3mx_serial_tstc,
+};
+
+void p3mx_serial_initialize(void)
+{
+ serial_register(&p3mx_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &p3mx_serial_drv;
+}
+
#if defined(CONFIG_CMD_KGDB)
void kgdb_serial_init (void)
{
#include <common.h>
#include <miiphy.h>
+#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
IB62x0_OE_VAL_HIGH,
IB62x0_OE_LOW, IB62x0_OE_HIGH);
+ /* Set SATA activity LEDs to default off */
+ writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG);
/* Multi-Purpose Pins Functionality configuration */
u32 kwmpp_config[] = {
MPP0_NF_IO2,
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+/* SATAHC related */
+#define MVSATAHC_LED_CONF_REG (MV_SATA_BASE + 0x2C)
+#define MVSATAHC_LED_POLARITY_CTRL (1 << 3)
+
#endif /* __IB62x0_H */
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
LIB = $(obj)lib$(BOARD).o
-COBJS = $(BOARD).o flash.o serial.o
-SOBJS = init.o
+ifndef CONFIG_SPL_BUILD
+COBJS := fpga.o $(BOARD).o
+endif
+SOBJS :=
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spartan3.h>
+#include <command.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_ssp.h>
+
+/*
+ * FPGA program pin configuration on X600:
+ *
+ * Only PROG and DONE are connected to GPIOs. INIT is not connected to the
+ * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use
+ * 16bit serial writes via this SSP port to write the data bits into the
+ * FPGA.
+ */
+#define CONFIG_SYS_FPGA_PROG 2
+#define CONFIG_SYS_FPGA_DONE 3
+
+/*
+ * Set the active-low FPGA reset signal.
+ */
+static void fpga_reset(int assert)
+{
+ /*
+ * On x600 we have no means to toggle the FPGA reset signal
+ */
+ debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert);
+}
+
+/*
+ * Set the FPGA's active-low SelectMap program line to the specified level
+ */
+static int fpga_pgm_fn(int assert, int flush, int cookie)
+{
+ debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert);
+
+ gpio_set_value(CONFIG_SYS_FPGA_PROG, assert);
+
+ return assert;
+}
+
+/*
+ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
+ * asserted (low).
+ */
+static int fpga_init_fn(int cookie)
+{
+ static int state;
+
+ debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state);
+
+ /*
+ * On x600, the FPGA INIT signal is not connected to the SoC.
+ * We can't read the INIT status. Let's return the "correct"
+ * INIT signal state generated via a local state-machine.
+ */
+ if (++state == 1) {
+ return 1;
+ } else {
+ state = 0;
+ return 0;
+ }
+}
+
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
+static int fpga_done_fn(int cookie)
+{
+ struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
+
+ /*
+ * Wait for Tx-FIFO to become empty before looking for DONE
+ */
+ while (!(readl(&ssp->sspsr) & SSPSR_TFE))
+ ;
+
+ if (gpio_get_value(CONFIG_SYS_FPGA_DONE))
+ return 1;
+ else
+ return 0;
+}
+
+/*
+ * FPGA pre-configuration function. Just make sure that
+ * FPGA reset is asserted to keep the FPGA from starting up after
+ * configuration.
+ */
+static int fpga_pre_config_fn(int cookie)
+{
+ debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
+ fpga_reset(TRUE);
+
+ return 0;
+}
+
+/*
+ * FPGA post configuration function. Blip the FPGA reset line and then see if
+ * the FPGA appears to be running.
+ */
+static int fpga_post_config_fn(int cookie)
+{
+ int rc = 0;
+
+ debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
+
+ fpga_reset(TRUE);
+ udelay(100);
+ fpga_reset(FALSE);
+ udelay(100);
+
+ return rc;
+}
+
+static int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+ /*
+ * No dedicated clock signal on x600 (data & clock generated)
+ * in SSP interface. So we don't have to do anything here.
+ */
+ return assert_clk;
+}
+
+static int fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+ struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
+ static int count;
+ static u16 data;
+
+ /*
+ * First collect 16 bits of data
+ */
+ data = data << 1;
+ if (assert_write)
+ data |= 1;
+
+ /*
+ * If 16 bits are not available, return for more bits
+ */
+ count++;
+ if (count != 16)
+ return assert_write;
+
+ count = 0;
+
+ /*
+ * Wait for Tx-FIFO to become ready
+ */
+ while (!(readl(&ssp->sspsr) & SSPSR_TNF))
+ ;
+
+ /* Send 16 bits to FPGA via SSP bus */
+ writel(data, &ssp->sspdr);
+
+ return assert_write;
+}
+
+static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = {
+ fpga_pre_config_fn,
+ fpga_pgm_fn,
+ fpga_clk_fn,
+ fpga_init_fn,
+ fpga_done_fn,
+ fpga_wr_fn,
+ fpga_post_config_fn,
+};
+
+static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+ XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
+};
+
+/*
+ * Initialize the SelectMap interface. We assume that the mode and the
+ * initial state of all of the port pins have already been set!
+ */
+static void fpga_serialslave_init(void)
+{
+ debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
+ fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */
+}
+
+static int expi_setup(int freq)
+{
+ struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ int pll2_m, pll2_n, pll2_p, expi_x, expi_y;
+
+ pll2_m = (freq * 2) / 1000;
+ pll2_n = 15;
+ pll2_p = 1;
+ expi_x = 1;
+ expi_y = 2;
+
+ /*
+ * Disable reset, Low compression, Disable retiming, Enable Expi,
+ * Enable soft reset, DMA, PLL2, Internal
+ */
+ writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST |
+ EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 |
+ EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24),
+ &misc->expi_clk_cfg);
+
+ /*
+ * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters,
+ * Enable PLL2, Disable reset
+ */
+ writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq);
+ writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE |
+ PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl);
+
+ /*
+ * Disable soft reset
+ */
+ clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST);
+
+ return 0;
+}
+
+/*
+ * Initialize the fpga
+ */
+int x600_init_fpga(void)
+{
+ struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
+ struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+ /* Enable SSP2 clock */
+ writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB,
+ &misc->periph1_clken);
+
+ /* Set EXPI clock to 45 MHz */
+ expi_setup(45000);
+
+ /* Configure GPIO directions */
+ gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0);
+ gpio_direction_input(CONFIG_SYS_FPGA_DONE);
+
+ writel(SSPCR0_DSS_16BITS, &ssp->sspcr0);
+ writel(SSPCR1_SSE, &ssp->sspcr1);
+
+ /*
+ * Set lowest prescale divisor value (CPSDVSR) of 2 for max download
+ * speed.
+ *
+ * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1))
+ * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz.
+ */
+ writel(2, &ssp->sspcpsr);
+
+ fpga_init();
+ fpga_serialslave_init();
+
+ debug("%s:%d: Adding fpga 0\n", __func__, __LINE__);
+ fpga_add(fpga_xilinx, &fpga[0]);
+
+ return 0;
+}
/*
- * (C) Copyright 2010-2011
- * NVIDIA Corporation <www.nvidia.com>
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
-void board_init_uart_f(void);
-void gpio_config_uart(void);
+int x600_init_fpga(void);
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <netdev.h>
+#include <phy.h>
+#include <rtc.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+#include <linux/mtd/fsmc_nand.h>
+#include "fpga.h"
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+int board_init(void)
+{
+ /*
+ * X600 is equipped with an M41T82 RTC. This RTC has the
+ * HT bit (Halt Update), which needs to be cleared upon
+ * power-up. Otherwise the RTC is halted.
+ */
+ rtc_reset();
+
+ return spear_board_init(MACH_TYPE_SPEAR600);
+}
+
+int board_late_init(void)
+{
+ /*
+ * Monitor and env protection on by default
+ */
+ flash_protect(FLAG_PROTECT_SET,
+ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE +
+ CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN +
+ 2 * CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+
+ /* Init FPGA subsystem */
+ x600_init_fpga();
+
+ return 0;
+}
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand: mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+void board_nand_init(void)
+{
+ struct misc_regs *const misc_regs_p =
+ (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ struct nand_chip *nand = &nand_chip[0];
+
+ if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
+ fsmc_nand_init(nand);
+}
+
+int designware_board_phy_init(struct eth_device *dev, int phy_addr,
+ int (*mii_write)(struct eth_device *, u8, u8, u16),
+ int dw_reset_phy(struct eth_device *))
+{
+ /* Extended PHY control 1, select GMII */
+ mii_write(dev, phy_addr, 23, 0x0020);
+
+ /* Software reset necessary after GMII mode selction */
+ dw_reset_phy(dev);
+
+ /* Enable extended page register access */
+ mii_write(dev, phy_addr, 31, 0x0001);
+
+ /* 17e: Enhanced LED behavior, needs to be written twice */
+ mii_write(dev, phy_addr, 17, 0x09ff);
+ mii_write(dev, phy_addr, 17, 0x09ff);
+
+ /* 16e: Enhanced LED method select */
+ mii_write(dev, phy_addr, 16, 0xe0ea);
+
+ /* Disable extended page register access */
+ mii_write(dev, phy_addr, 31, 0x0000);
+
+ /* Enable clock output pin */
+ mii_write(dev, phy_addr, 18, 0x0049);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+ if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR,
+ PHY_INTERFACE_MODE_GMII) >= 0)
+ ret++;
+
+ return ret;
+}
if ((raise_ab8500_gpio16() < 0))
printf("error: cant' raise GPIO16\n");
+ /* empty UART RX FIFO */
+ while (tstc())
+ (void) getc();
+
return 0;
}
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- return omap_ehci_hcd_init(&usbhs_bdata);
+ return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return omap_ehci_hcd_stop();
}
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- return omap_ehci_hcd_init(&usbhs_bdata);
+ return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return omap_ehci_hcd_stop();
}
}
#endif
-#ifdef CONFIG_USB_EHCI
+#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
/* Call usb_stop() before starting the kernel */
void show_boot_progress(int val)
{
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
};
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- return omap_ehci_hcd_init(&usbhs_bdata);
+ return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return omap_ehci_hcd_stop();
}
*********************************************************************/
void display_board_info(u32 btype)
{
- char cpu_2420[] = "2420"; /* cpu type */
- char cpu_2422[] = "2422";
- char cpu_2423[] = "2423";
- char db_men[] = "Menelaus"; /* board type */
- char db_ip[] = "IP";
- char mem_sdr[] = "mSDR"; /* memory type */
- char mem_ddr[] = "mDDR";
- char t_tst[] = "TST"; /* security level */
- char t_emu[] = "EMU";
- char t_hs[] = "HS";
- char t_gp[] = "GP";
- char unk[] = "?";
-
- char *cpu_s, *db_s, *mem_s, *sec_s;
+ static const char cpu_2420 [] = "2420"; /* cpu type */
+ static const char cpu_2422 [] = "2422";
+ static const char cpu_2423 [] = "2423";
+ static const char db_men [] = "Menelaus"; /* board type */
+ static const char db_ip [] = "IP";
+ static const char mem_sdr [] = "mSDR"; /* memory type */
+ static const char mem_ddr [] = "mDDR";
+ static const char t_tst [] = "TST"; /* security level */
+ static const char t_emu [] = "EMU";
+ static const char t_hs [] = "HS";
+ static const char t_gp [] = "GP";
+ static const char unk [] = "?";
+
+ const char *cpu_s, *db_s, *mem_s, *sec_s;
u32 cpu, rev, sec;
rev = get_cpu_rev();
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
int ret;
unsigned int utmi_clk;
utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
sr32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, utmi_clk);
- ret = omap_ehci_hcd_init(&usbhs_bdata);
+ ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
if (ret < 0)
return ret;
return 0;
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return omap_ehci_hcd_stop();
}
DECLARE_GLOBAL_DATA_PTR;
-struct serial_device *default_serial_console(void)
-{
- return &serial_ffuart_device;
-}
-
int board_init(void)
{
/* We have RAM, disable cache */
+++ /dev/null
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * Standard mapping:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xc000_0000 0xdfff_ffff RapidIO or PCI express 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xe300_0000 0xe3ff_ffff CAN and NAND Flash 16M
- * 0xef00_0000 0xefff_ffff PCI express IO 16M
- * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 128M
- *
- * Big FLASH mapping:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xa000_0000 0xa000_ffff CCSR 1M
- * 0xa200_0000 0xa2ff_ffff PCI1 IO 16M
- * 0xa300_0000 0xa3ff_ffff CAN and NAND Flash 16M
- * 0xaf00_0000 0xafff_ffff PCI express IO 16M
- * 0xb000_0000 0xbfff_ffff RapidIO or PCI express 256M
- * 0xc000_0000 0xffff_ffff FLASH (boot bank) 1G
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-#ifdef CONFIG_TQM_BIGFLASH
-#define LAW_3_SIZE LAW_SIZE_1G
-#define LAW_5_SIZE LAW_SIZE_256M
-#else
-#define LAW_3_SIZE LAW_SIZE_128M
-#define LAW_5_SIZE LAW_SIZE_512M
-#endif
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_2G, LAW_TRGT_IF_DDR),
- SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
-#ifndef CONFIG_PCIE1
- SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
-#endif /* CONFIG_PCIE1 */
-#if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND)
- SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
-#endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */
-};
-
-int num_law_entries = ARRAY_SIZE (law_table);
+++ /dev/null
-/*
- * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de>
- *
- * (C) Copyright 2006
- * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/fsl_upm.h>
-#include <ioports.h>
-
-#include <nand.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern uint get_lbc_clock (void);
-
-/* index of UPM RAM array run pattern for NAND command cycle */
-#define CONFIG_SYS_NAN_UPM_WRITE_CMD_OFS 0x08
-
-/* index of UPM RAM array run pattern for NAND address cycle */
-#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS 0x10
-
-/* Structure for table with supported UPM timings */
-struct upm_freq {
- ulong freq;
- const u32 *upm_patt;
- uchar gpl4_disable;
- uchar ehtr;
- uchar ead;
-};
-
-/* NAND-FLASH UPM tables for TQM85XX according to TQM8548.pq.timing.101.doc */
-
-/* UPM pattern for bus clock = 25 MHz */
-static const u32 upm_patt_25[] = {
- /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
- /* 0x00 */ 0x0ff32000, 0x0fa32000, 0x3fb32005, 0xfffffc00,
- /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> NAND Write CMD */
- /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00,
- /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> NAND Write ADDR */
- /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00,
- /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Single RAM array entry -> NAND Write Data */
- /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00,
- /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Burst RAM array entry -> unused */
- /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Refresh Timer RAM array entry -> unused */
- /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Exception RAM array entry -> unsused */
- /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 33.3 MHz */
-static const u32 upm_patt_33[] = {
- /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
- /* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00,
- /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> NAND Write CMD */
- /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00,
- /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> NAND Write ADDR */
- /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00,
- /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Single RAM array entry -> NAND Write Data */
- /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00,
- /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Burst RAM array entry -> unused */
- /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Refresh Timer RAM array entry -> unused */
- /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Exception RAM array entry -> unsused */
- /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 41.7 MHz */
-static const u32 upm_patt_42[] = {
- /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
- /* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00,
- /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> NAND Write CMD */
- /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00,
- /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> NAND Write ADDR */
- /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00,
- /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Single RAM array entry -> NAND Write Data */
- /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00,
- /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Burst RAM array entry -> unused */
- /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Refresh Timer RAM array entry -> unused */
- /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Exception RAM array entry -> unsused */
- /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 50 MHz */
-static const u32 upm_patt_50[] = {
- /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
- /* 0x00 */ 0x0ff33000, 0x0fa33100, 0x0fa33005, 0xfffffc00,
- /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> NAND Write CMD */
- /* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c35, 0xfffffc00,
- /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> NAND Write ADDR */
- /* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc35, 0xfffffc00,
- /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Single RAM array entry -> NAND Write Data */
- /* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c05, 0xfffffc00,
- /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Burst RAM array entry -> unused */
- /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Refresh Timer RAM array entry -> unused */
- /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Exception RAM array entry -> unsused */
- /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 66.7 MHz */
-static const u32 upm_patt_67[] = {
- /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
- /* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000,
- /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> NAND Write CMD */
- /* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35,
- /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> NAND Write ADDR */
- /* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35,
- /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Single RAM array entry -> NAND Write Data */
- /* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05,
- /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Burst RAM array entry -> unused */
- /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Refresh Timer RAM array entry -> unused */
- /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Exception RAM array entry -> unsused */
- /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 83.3 MHz */
-static const u32 upm_patt_83[] = {
- /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
- /* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000,
- /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> NAND Write CMD */
- /* 0x08 */ 0x00ff3e30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35,
- /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> NAND Write ADDR */
- /* 0x10 */ 0x00f3fe30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35,
- /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Single RAM array entry -> NAND Write Data */
- /* 0x18 */ 0x00f33e00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05,
- /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Burst RAM array entry -> unused */
- /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Refresh Timer RAM array entry -> unused */
- /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Exception RAM array entry -> unsused */
- /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 100 MHz */
-static const u32 upm_patt_100[] = {
- /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
- /* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33200, 0x0fa33000,
- /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> NAND Write CMD */
- /* 0x08 */ 0x00ff3f30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35,
- /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> NAND Write ADDR */
- /* 0x10 */ 0x00f3ff30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35,
- /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Single RAM array entry -> NAND Write Data */
- /* 0x18 */ 0x00f33f00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05,
- /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Burst RAM array entry -> unused */
- /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Refresh Timer RAM array entry -> unused */
- /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Exception RAM array entry -> unsused */
- /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 133.3 MHz */
-static const u32 upm_patt_133[] = {
- /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
- /* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33300, 0x0fa33000,
- /* 0x04 */ 0x0fa33000, 0x0fa33005, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> NAND Write CMD */
- /* 0x08 */ 0x00ff3f30, 0x00ff3d30, 0x0fff3d30, 0x0fff3c35,
- /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> NAND Write ADDR */
- /* 0x10 */ 0x00f3ff30, 0x00f3fd30, 0x0ff3fd30, 0x0ff3fc35,
- /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Single RAM array entry -> NAND Write Data */
- /* 0x18 */ 0x00f33f00, 0x00f33d00, 0x0ff33d00, 0x0ff33c05,
- /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Burst RAM array entry -> unused */
- /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Refresh Timer RAM array entry -> unused */
- /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Exception RAM array entry -> unsused */
- /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 166.7 MHz */
-static const u32 upm_patt_167[] = {
- /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
- /* 0x00 */ 0x0ff33200, 0x0fe33000, 0x0fa33300, 0x0fa33300,
- /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> NAND Write CMD */
- /* 0x08 */ 0x00ff3f30, 0x00ff3f30, 0x0fff3e30, 0xffff3c35,
- /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> NAND Write ADDR */
- /* 0x10 */ 0x00f3ff30, 0x00f3ff30, 0x0ff3fe30, 0x0ff3fc35,
- /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Single RAM array entry -> NAND Write Data */
- /* 0x18 */ 0x00f33f00, 0x00f33f00, 0x0ff33e00, 0x0ff33c05,
- /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Burst RAM array entry -> unused */
- /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Refresh Timer RAM array entry -> unused */
- /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Exception RAM array entry -> unsused */
- /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* Supported UPM timings */
-struct upm_freq upm_freq_table[] = {
- /* nominal freq. | ptr to table | GPL4 dis. | EHTR | EAD */
- {25000000, upm_patt_25, 1, 0, 0},
- {33333333, upm_patt_33, 1, 0, 0},
- {41666666, upm_patt_42, 1, 0, 0},
- {50000000, upm_patt_50, 0, 0, 0},
- {66666666, upm_patt_67, 0, 0, 0},
- {83333333, upm_patt_83, 0, 0, 0},
- {100000000, upm_patt_100, 0, 1, 1},
- {133333333, upm_patt_133, 0, 1, 1},
- {166666666, upm_patt_167, 0, 1, 1},
-};
-
-#define UPM_FREQS (sizeof(upm_freq_table) / sizeof(struct upm_freq))
-
-volatile const u32 *nand_upm_patt;
-
-/*
- * write into UPMB ram
- */
-static void upmb_write (u_char addr, ulong val)
-{
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
- out_be32 (&lbc->mdr, val);
-
- clrsetbits_be32(&lbc->mbmr, MxMR_MAD_MSK,
- MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
-
- /* dummy access to perform write */
- out_8 ((void __iomem *)CONFIG_SYS_NAND_BASE, 0);
-
- clrbits_be32(&lbc->mbmr, MxMR_OP_WARR);
-}
-
-/*
- * Initialize UPM for NAND flash access.
- */
-static void nand_upm_setup (volatile fsl_lbc_t *lbc)
-{
- uint i, j;
- uint or3 = CONFIG_SYS_OR3_PRELIM;
- uint clock = get_lbc_clock ();
-
- set_lbc_br(3, 0); /* disable bank and reset all bits */
- set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
-
- /*
- * Search appropriate UPM table for bus clock.
- * If the bus clock exceeds a tolerated value, take the UPM timing for
- * the next higher supported frequency to ensure that access works
- * (even the access may be slower then).
- */
- for (i = 0; (i < UPM_FREQS) && (clock > upm_freq_table[i].freq); i++)
- ;
-
- if (i >= UPM_FREQS)
- /* no valid entry found */
- /* take last entry with configuration for max. bus clock */
- i--;
-
- if (upm_freq_table[i].ehtr) {
- /* EHTR must be set due to TQM8548 timing specification */
- or3 |= OR_UPM_EHTR;
- }
- if (upm_freq_table[i].ead)
- /* EAD must be set due to TQM8548 timing specification */
- or3 |= OR_UPM_EAD;
-
- set_lbc_or(3, or3);
-
- /* Assign address of table */
- nand_upm_patt = upm_freq_table[i].upm_patt;
-
- for (j = 0; j < 64; j++) {
- upmb_write (j, *nand_upm_patt);
- nand_upm_patt++;
- }
-
- /* Put UPM back to normal operation mode */
- if (upm_freq_table[i].gpl4_disable)
- /* GPL4 must be disabled according to timing specification */
- out_be32 (&lbc->mbmr, MxMR_OP_NORM | MxMR_GPL_x4DIS);
-
- return;
-}
-
-static struct fsl_upm_nand fun = {
- .width = 8,
- .upm_cmd_offset = 0x08,
- .upm_addr_offset = 0x10,
- .upm_mar_chip_offset = CONFIG_SYS_NAND_CS_DIST,
- .chip_offset = CONFIG_SYS_NAND_CS_DIST,
- .chip_delay = NAND_BIG_DELAY_US,
- .wait_flags = FSL_UPM_WAIT_RUN_PATTERN | FSL_UPM_WAIT_WRITE_BUFFER,
-};
-
-void board_nand_select_device (struct nand_chip *nand, int chip)
-{
-}
-
-int board_nand_init (struct nand_chip *nand)
-{
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
- if (!nand_upm_patt)
- nand_upm_setup (lbc);
-
- fun.upm.io_addr = nand->IO_ADDR_R;
- fun.upm.mxmr = (void __iomem *)&lbc->mbmr;
- fun.upm.mdr = (void __iomem *)&lbc->mdr;
- fun.upm.mar = (void __iomem *)&lbc->mar;
-
- return fsl_upm_nand_init (nand, &fun);
-}
+++ /dev/null
-
-/*
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-
-struct sdram_conf_s {
- unsigned long size;
- unsigned long reg;
-#ifdef CONFIG_TQM8548
- unsigned long refresh;
-#endif /* CONFIG_TQM8548 */
-};
-
-typedef struct sdram_conf_s sdram_conf_t;
-
-#ifdef CONFIG_TQM8548
-#ifdef CONFIG_TQM8548_AG
-sdram_conf_t ddr_cs_conf[] = {
- {(1024 << 20), 0x80044202, 0x0002D000}, /* 1024MB, 14x10(4) */
- { (512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
- { (256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
- { (128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
-};
-#else /* !CONFIG_TQM8548_AG */
-sdram_conf_t ddr_cs_conf[] = {
- {(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
- {(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
- {(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
-};
-#endif /* CONFIG_TQM8548_AG */
-#else /* !CONFIG_TQM8548 */
-sdram_conf_t ddr_cs_conf[] = {
- {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
- {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
- {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
- {( 64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
-};
-#endif /* CONFIG_TQM8548 */
-
-#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
-
-int cas_latency (void);
-static phys_size_t sdram_setup(int);
-
-/*
- * Autodetect onboard DDR SDRAM on 85xx platforms
- *
- * NOTE: Some of the hardcoded values are hardware dependant,
- * so this should be extended for other future boards
- * using this routine!
- */
-phys_size_t fixed_sdram(void)
-{
- int casl = 0;
- phys_size_t dram_size = 0;
-
- casl = cas_latency();
- dram_size = sdram_setup(casl);
- if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
- /*
- * Try again with default CAS latency
- */
- printf("Problem with CAS lantency, using default CL %d/10!\n",
- CONFIG_DDR_DEFAULT_CL);
- dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL);
- puts(" ");
- }
- return dram_size;
-}
-
-static phys_size_t sdram_setup(int casl)
-{
- int i;
- volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
-#ifdef CONFIG_TQM8548
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
- volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
-#endif
-#else /* !CONFIG_TQM8548 */
- unsigned long cfg_ddr_timing1;
- unsigned long cfg_ddr_mode;
-#endif /* CONFIG_TQM8548 */
-
- /*
- * Disable memory controller.
- */
- ddr->cs0_config = 0;
- ddr->sdram_cfg = 0;
-
-#ifdef CONFIG_TQM8548
- /* Timing and refresh settings for DDR2-533 and below */
-
- ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
- ddr->cs0_config = ddr_cs_conf[0].reg;
- ddr->timing_cfg_3 = 0x00020000;
-
- /* TIMING CFG 1, 533MHz
- * PRETOACT: 4 Clocks
- * ACTTOPRE: 12 Clocks
- * ACTTORW: 4 Clocks
- * CASLAT: 4 Clocks
- * REFREC: EXT_REFREC:REFREC 53 Clocks
- * WRREC: 4 Clocks
- * ACTTOACT: 3 Clocks
- * WRTORD: 2 Clocks
- */
- ddr->timing_cfg_1 = 0x4C47D432;
-
- /* TIMING CFG 2, 533MHz
- * ADD_LAT: 3 Clocks
- * CPO: READLAT + 1
- * WR_LAT: 3 Clocks
- * RD_TO_PRE: 2 Clocks
- * WR_DATA_DELAY: 1/2 Clock
- * CKE_PLS: 3 Clock
- * FOUR_ACT: 14 Clocks
- */
- ddr->timing_cfg_2 = 0x331848CE;
-
- /* DDR SDRAM Mode, 533MHz
- * MRS: Extended Mode Register
- * OUT: Outputs enabled
- * RDQS: no
- * DQS: enabled
- * OCD: default state
- * RTT: 75 Ohms
- * Posted CAS: 3 Clocks
- * ODS: reduced strength
- * DLL: enabled
- * MR: Mode Register
- * PD: fast exit
- * WR: 4 Clocks
- * DLL: no DLL reset
- * TM: normal
- * CAS latency: 4 Clocks
- * BT: sequential
- * Burst length: 4
- */
- ddr->sdram_mode = 0x439E0642;
-
- /* DDR SDRAM Interval, 533MHz
- * REFINT: 1040 Clocks
- * BSTOPRE: 256
- */
- ddr->sdram_interval = (1040 << 16) | 0x100;
-
- /*
- * Workaround for erratum DDR19 according to MPC8548 Device Errata
- * document, Rev. 1: DDR IO receiver must be set to an acceptable
- * bias point by modifying a hidden register.
- */
- if (SVR_REV (get_svr ()) < 0x21)
- gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */
-
- /* DDR SDRAM CFG 2
- * FRC_SR: normal mode
- * SR_IE: no self-refresh interrupt
- * DLL_RST_DIS: don't care, leave at reset value
- * DQS_CFG: differential DQS signals
- * ODT_CFG: assert ODT to internal IOs only during reads to DRAM
- * LVWx_CFG: don't care, leave at reset value
- * NUM_PR: 1 refresh will be issued at a time
- * DM_CFG: don't care, leave at reset value
- * D_INIT: no data initialization
- */
- ddr->sdram_cfg_2 = 0x04401000;
-
- /* DDR SDRAM MODE 2
- * MRS: Extended Mode Register 2
- */
- ddr->sdram_mode_2 = 0x8000C000;
-
- /* DDR SDRAM CLK CNTL
- * CLK_ADJUST: 1/2 Clock 0x02000000
- * CLK_ADJUST: 5/8 Clock 0x02800000
- */
- ddr->sdram_clk_cntl = 0x02800000;
-
- /* wait for clock stabilization */
- asm ("sync;isync;msync");
- udelay (1000);
-
-#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
- /*
- * Workaround for erratum DDR20 according to MPC8548 Device Errata
- * document, Rev. 1: "CKE signal may not function correctly after
- * assertion of HRESET"
- */
-
- /* 1. Configure DDR register as is done in normal DDR configuration.
- * Do not set DDR_SDRAM_CFG[MEM_EN].
- *
- * 2. Set reserved bit EEBACR[3] at offset 0x1000
- */
- ecm->eebacr |= 0x10000000;
-
- /*
- * 3. Before DDR_SDRAM_CFG[MEM_EN] is set, write DDR_SDRAM_CFG_2[D_INIT]
- *
- * DDR_SDRAM_CFG_2:
- * FRC_SR: normal mode
- * SR_IE: no self-refresh interrupt
- * DLL_RST_DIS: don't care, leave at reset value
- * DQS_CFG: differential DQS signals
- * ODT_CFG: assert ODT to internal IOs only during reads to DRAM
- * LVWx_CFG: don't care, leave at reset value
- * NUM_PR: 1 refresh will be issued at a time
- * DM_CFG: don't care, leave at reset value
- * D_INIT: enable data initialization
- */
- ddr->sdram_cfg_2 |= 0x00000010;
-
- /*
- * 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data
- * training
- */
- ddr->debug[2] |= 0x00000400;
-
- /*
- * 5. Wait 200 micro-seconds
- */
- udelay (200);
-
- /*
- * 6. Set DDR_SDRAM_CFG[MEM_EN]
- *
- * BTW, initialize DDR_SDRAM_CFG:
- * MEM_EN: enabled
- * SREN: don't care, leave at reset value
- * ECC_EN: no error report
- * RD_EN: no registered DIMMs
- * SDRAM_TYPE: DDR2
- * DYN_PWR: no power management
- * 32_BE: don't care, leave at reset value
- * 8_BE: 4 beat burst
- * NCAP: don't care, leave at reset value
- * 2T_EN: 1T Timing
- * BA_INTLV_CTL: no interleaving
- * x32_EN: x16 organization
- * PCHB8: MA[10] for auto-precharge
- * HSE: half strength for single and 2-layer stacks
- * (full strength for 3- and 4-layer stacks not
- * yet considered)
- * MEM_HALT: no halt
- * BI: automatic initialization
- */
- ddr->sdram_cfg = 0x83000008;
-
- /*
- * 7. Poll DDR_SDRAM_CFG_2[D_INIT] until it is cleared by hardware
- */
- asm ("sync;isync;msync");
- while (ddr->sdram_cfg_2 & 0x00000010)
- asm ("eieio");
-
- /*
- * 8. Clear D3[21] to re-enable data training
- */
- ddr->debug[2] &= ~0x00000400;
-
- /*
- * 9. Set D2(21) to force data training to run
- */
- ddr->debug[1] |= 0x00000400;
-
- /*
- * 10. Poll on D2[21] until it is cleared by hardware
- */
- asm ("sync;isync;msync");
- while (ddr->debug[1] & 0x00000400)
- asm ("eieio");
-
- /*
- * 11. Clear reserved bit EEBACR[3] at offset 0x1000
- */
- ecm->eebacr &= ~0x10000000;
-
-#else /* !(CONFIG_TQM8548_AG || CONFIG_TQM8548_BE) */
-
- /* DDR SDRAM CLK CNTL
- * MEM_EN: enabled
- * SREN: don't care, leave at reset value
- * ECC_EN: no error report
- * RD_EN: no register DIMMs
- * SDRAM_TYPE: DDR2
- * DYN_PWR: no power management
- * 32_BE: don't care, leave at reset value
- * 8_BE: 4 beat burst
- * NCAP: don't care, leave at reset value
- * 2T_EN: 1T Timing
- * BA_INTLV_CTL: no interleaving
- * x32_EN: x16 organization
- * PCHB8: MA[10] for auto-precharge
- * HSE: half strength for single and 2-layer stacks
- * (full strength for 3- and 4-layer stacks no yet considered)
- * MEM_HALT: no halt
- * BI: automatic initialization
- */
- ddr->sdram_cfg = 0x83000008;
-
-#endif /* CONFIG_TQM8548_AG || CONFIG_TQM8548_BE */
-
- asm ("sync; isync; msync");
- udelay (1000);
-#else /* !CONFIG_TQM8548 */
- switch (casl) {
- case 20:
- cfg_ddr_timing1 = 0x47405331 | (3 << 16);
- cfg_ddr_mode = 0x40020002 | (2 << 4);
- break;
-
- case 25:
- cfg_ddr_timing1 = 0x47405331 | (4 << 16);
- cfg_ddr_mode = 0x40020002 | (6 << 4);
- break;
-
- case 30:
- default:
- cfg_ddr_timing1 = 0x47405331 | (5 << 16);
- cfg_ddr_mode = 0x40020002 | (3 << 4);
- break;
- }
-
- ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
- ddr->cs0_config = ddr_cs_conf[0].reg;
- ddr->timing_cfg_1 = cfg_ddr_timing1;
- ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */
- ddr->sdram_mode = cfg_ddr_mode;
- ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
- ddr->err_disable = 0x0000000D;
-
- asm ("sync; isync; msync");
- udelay (1000);
-
- ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
- asm ("sync; isync; msync");
- udelay (1000);
-#endif /* CONFIG_TQM8548 */
-
- /*
- * get_ram_size() depends on having tlbs for the DDR, but they are
- * not yet setup because we don't know the size. Set up a temp
- * mapping and delete it when done.
- */
- setup_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB);
- for (i = 0; i < N_DDR_CS_CONF; i++) {
- ddr->cs0_config = ddr_cs_conf[i].reg;
-
- if (get_ram_size (0, ddr_cs_conf[i].size) ==
- ddr_cs_conf[i].size) {
- /*
- * size detected -> set Chip Select Bounds Register
- */
- ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24;
-
- break;
- }
- }
- clear_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB);
-
-#ifdef CONFIG_TQM8548
- if (i < N_DDR_CS_CONF) {
- /* Adjust refresh rate for DDR2 */
-
- ddr->timing_cfg_3 = ddr_cs_conf[i].refresh & 0x00070000;
-
- ddr->timing_cfg_1 = (ddr->timing_cfg_1 & 0xFFFF0FFF) |
- (ddr_cs_conf[i].refresh & 0x0000F000);
-
- return ddr_cs_conf[i].size;
- }
-#endif /* CONFIG_TQM8548 */
-
- /* return size if detected, else return 0 */
- return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
-}
-
-#if defined(CONFIG_SYS_DRAM_TEST)
-int testdram (void)
-{
- uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
- uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
- uint *p;
-
- printf ("SDRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf ("SDRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf ("SDRAM test passed.\n");
- return 0;
-}
-#endif
+++ /dev/null
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
-#ifndef CONFIG_TQM_BIGFLASH
- /*
- * TLB 0, 1: 128M Non-cacheable, guarded
- * 0xf8000000 128M FLASH
- * Out of reset this entry is only 4K.
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 1, BOOKE_PAGESZ_64M, 1),
- SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x4000000,
- CONFIG_SYS_FLASH_BASE + 0x4000000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 0, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLB 2: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM First half
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 3: 256M Non-cacheable, guarded
- * 0x90000000 256M PCI1 MEM Second half
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
- CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
-
-#ifdef CONFIG_PCIE1
- /*
- * TLB 4: 256M Non-cacheable, guarded
- * 0xc0000000 256M PCI express MEM First half
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 5: 256M Non-cacheable, guarded
- * 0xd0000000 256M PCI express MEM Second half
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
- CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-#else /* !CONFIG_PCIE */
- /*
- * TLB 4: 256M Non-cacheable, guarded
- * 0xc0000000 256M Rapid IO MEM First half
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 5: 256M Non-cacheable, guarded
- * 0xd0000000 256M Rapid IO MEM Second half
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
- CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-#endif /* CONFIG_PCIE */
-
- /*
- * TLB 6: 64M Non-cacheable, guarded
- * 0xe0000000 1M CCSRBAR
- * 0xe2000000 16M PCI1 IO
- * 0xe3000000 16M CAN and NAND Flash
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 6, BOOKE_PAGESZ_64M, 1),
-#ifdef CONFIG_PCIE1
- /*
- * TLB 9: 16M Non-cacheable, guarded
- * 0xef000000 16M PCI express IO
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_BUS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 9, BOOKE_PAGESZ_16M, 1),
-#endif /* CONFIG_PCIE */
-
-#else /* CONFIG_TQM_BIGFLASH */
-
- /*
- * TLB 0,1,2,3: 1G Non-cacheable, guarded
- * 0xc0000000 1G FLASH
- * Out of reset this entry is only 4K.
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x10000000,
- CONFIG_SYS_FLASH_BASE + 0x10000000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x20000000,
- CONFIG_SYS_FLASH_BASE + 0x20000000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 1, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x30000000,
- CONFIG_SYS_FLASH_BASE + 0x30000000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 0, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 4: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM First half
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 5: 256M Non-cacheable, guarded
- * 0x90000000 256M PCI1 MEM Second half
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
- CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-
-#ifdef CONFIG_PCIE1
- /*
- * TLB 6: 256M Non-cacheable, guarded
- * 0xc0000000 256M PCI express MEM First half
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 6, BOOKE_PAGESZ_256M, 1),
-#else /* !CONFIG_PCIE */
- /*
- * TLB 6: 256M Non-cacheable, guarded
- * 0xb0000000 256M Rapid IO MEM First half
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 6, BOOKE_PAGESZ_256M, 1),
-
-#endif /* CONFIG_PCIE */
-
- /*
- * TLB 7: 64M Non-cacheable, guarded
- * 0xa0000000 1M CCSRBAR
- * 0xa2000000 16M PCI1 IO
- * 0xa3000000 16M CAN and NAND Flash
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 7, BOOKE_PAGESZ_64M, 1),
-#ifdef CONFIG_PCIE1
- /*
- * TLB 10: 16M Non-cacheable, guarded
- * 0xaf000000 16M PCI express IO
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 10, BOOKE_PAGESZ_16M, 1),
-#endif /* CONFIG_PCIE */
-
-#endif /* CONFIG_TQM_BIGFLASH */
-};
-
-int num_tlb_entries = ARRAY_SIZE (tlb_table);
+++ /dev/null
-/*
- * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de>
- *
- * (C) Copyright 2006
- * Thomas Waehner, TQ-Systems GmbH, thomas.waehner@tqs.de.
- *
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Copyright 2004 Freescale Semiconductor.
- * (C) Copyright 2002,2003, Motorola Inc.
- * Xianghua Xiao, (X.Xiao@motorola.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <linux/compiler.h>
-#include <ioports.h>
-#include <flash.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[]; /* FLASH chips info */
-
-void local_bus_init (void);
-ulong flash_get_size (ulong base, int banknum);
-
-#ifdef CONFIG_PS2MULT
-void ps2mult_early_init (void);
-#endif
-
-#ifdef CONFIG_CPM2
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A: conf, ppar, psor, pdir, podr, pdat */
- {
- {1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */
- {1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */
- {1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */
- {1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */
- {1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */
- {1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */
- {0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */
- {0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */
- {0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */
- {0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */
- {1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */
- {1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */
- {1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */
- {1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */
- {1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */
- {1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */
- {1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */
- {1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */
- {0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */
- {0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */
- {0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */
- {0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */
- {0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */
- {0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */
- {0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */
- {0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */
- {0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */
- {0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */
- {0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */
- {0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */
- {0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */
- {0, 0, 0, 1, 0, 0} /* PA0 : PA0 */
- },
-
- /* Port B: conf, ppar, psor, pdir, podr, pdat */
- {
- {1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */
- {1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */
- {1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */
- {1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */
- {1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */
- {1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */
- {1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */
- {1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */
- {1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */
- {1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */
- {1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */
- {1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */
- {1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */
- {1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */
- {1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */
- {1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */
- {1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */
- {1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */
- {1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */
- {1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */
- {1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */
- {1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */
- {1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */
- {1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */
- {1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */
- {1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */
- {1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */
- {1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */
- {0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */
- {0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */
- {0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */
- {0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */
- },
-
- /* Port C: conf, ppar, psor, pdir, podr, pdat */
- {
- {0, 0, 0, 1, 0, 0}, /* PC31: PC31 */
- {0, 0, 0, 1, 0, 0}, /* PC30: PC30 */
- {0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */
- {0, 0, 0, 1, 0, 0}, /* PC28: PC28 */
- {0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */
- {0, 0, 0, 1, 0, 0}, /* PC26: PC26 */
- {0, 0, 0, 1, 0, 0}, /* PC25: PC25 */
- {0, 0, 0, 1, 0, 0}, /* PC24: PC24 */
- {0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */
- {0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */
- {1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */
- {1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */
- {1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */
- {1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */
- {1, 1, 0, 0, 0, 0}, /* PC17: PC17 */
- {1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */
- {0, 1, 0, 0, 0, 0}, /* PC15: PC15 */
- {0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */
- {0, 1, 0, 0, 0, 0}, /* PC13: PC13 */
- {0, 1, 0, 1, 0, 0}, /* PC12: PC12 */
- {0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */
- {0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */
- {0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */
- {0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */
- {0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */
- {0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */
- {0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */
- {0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */
- {0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */
- {0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */
- {0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */
- {0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */
- },
-
- /* Port D: conf, ppar, psor, pdir, podr, pdat */
- {
-#ifdef CONFIG_TQM8560
- {1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */
- {1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */
- {1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */
-#else /* !CONFIG_TQM8560 */
- {0, 0, 0, 0, 0, 0}, /* PD31: PD31 */
- {0, 0, 0, 0, 0, 0}, /* PD30: PD30 */
- {0, 0, 0, 0, 0, 0}, /* PD29: PD29 */
-#endif /* CONFIG_TQM8560 */
- {1, 1, 0, 0, 0, 0}, /* PD28: PD28 */
- {1, 1, 0, 1, 0, 0}, /* PD27: PD27 */
- {1, 1, 0, 1, 0, 0}, /* PD26: PD26 */
- {0, 0, 0, 1, 0, 0}, /* PD25: PD25 */
- {0, 0, 0, 1, 0, 0}, /* PD24: PD24 */
- {0, 0, 0, 1, 0, 0}, /* PD23: PD23 */
- {0, 0, 0, 1, 0, 0}, /* PD22: PD22 */
- {0, 0, 0, 1, 0, 0}, /* PD21: PD21 */
- {0, 0, 0, 1, 0, 0}, /* PD20: PD20 */
- {0, 0, 0, 1, 0, 0}, /* PD19: PD19 */
- {0, 0, 0, 1, 0, 0}, /* PD18: PD18 */
- {0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */
- {0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */
- {0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */
- {0, 0, 0, 1, 0, 0}, /* PD14: LED */
- {0, 0, 0, 0, 0, 0}, /* PD13: PD13 */
- {0, 0, 0, 0, 0, 0}, /* PD12: PD12 */
- {0, 0, 0, 0, 0, 0}, /* PD11: PD11 */
- {0, 0, 0, 0, 0, 0}, /* PD10: PD10 */
- {0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */
- {0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */
- {0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */
- {0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */
- {0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */
- {0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */
- {0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */
- {0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */
- {0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */
- {0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */
- }
-};
-#endif /* CONFIG_CPM2 */
-
-#define CASL_STRING1 "casl=xx"
-#define CASL_STRING2 "casl="
-
-static const int casl_table[] = { 20, 25, 30 };
-#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
-
-int cas_latency (void)
-{
- char buf[128];
- int casl;
- int val;
- int i;
-
- casl = CONFIG_DDR_DEFAULT_CL;
-
- i = getenv_f("serial#", buf, sizeof(buf));
-
- if (i >0) {
- if (strncmp(buf + strlen (buf) - strlen (CASL_STRING1),
- CASL_STRING2, strlen (CASL_STRING2)) == 0) {
- val = simple_strtoul (buf + strlen (buf) - 2, NULL, 10);
-
- for (i = 0; i < N_CASL; ++i) {
- if (val == casl_table[i]) {
- return val;
- }
- }
- }
- }
-
- return casl;
-}
-
-int checkboard (void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- printf ("Board: %s", CONFIG_BOARDNAME);
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc ('\n');
-
- /*
- * Initialize local bus.
- */
- local_bus_init ();
-
- return 0;
-}
-
-int misc_init_r (void)
-{
- /*
- * Adjust flash start and offset to detected values
- */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
- /*
- * Recalculate CS configuration if second FLASH bank is available
- */
- if (flash_info[0].size > 0) {
- set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) |
- (CONFIG_SYS_OR1_PRELIM & 0x00007fff));
- set_lbc_br(1, gd->bd->bi_flashstart |
- (CONFIG_SYS_BR1_PRELIM & 0x00007fff));
- /*
- * Re-check to get correct base address for bank 1
- */
- flash_get_size (gd->bd->bi_flashstart, 0);
- } else {
- set_lbc_or(1, 0);
- set_lbc_br(1, 0);
- }
-
- /*
- * If bank 1 is equipped, bank 0 is mapped after bank 1
- */
- set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
- (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
- set_lbc_br(0, (gd->bd->bi_flashstart + flash_info[0].size) |
- (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
-
- /*
- * Re-check to get correct base address for bank 0
- */
- flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1);
-
- /*
- * Re-do flash protection upon new addresses
- */
- flash_protect (FLAG_PROTECT_CLEAR,
- gd->bd->bi_flashstart, 0xffffffff,
- &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-
- /* Monitor protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE, 0xffffffff,
- &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-
- /* Environment protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-
-#ifdef CONFIG_ENV_ADDR_REDUND
- /* Redundant environment protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_CAN_DRIVER
-/*
- * Initialize UPMC RAM
- */
-static void upmc_write (u_char addr, uint val)
-{
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
- out_be32 (&lbc->mdr, val);
-
- clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK,
- MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
-
- /* dummy access to perform write */
- out_8 ((void __iomem *)CONFIG_SYS_CAN_BASE, 0);
-
- /* normal operation */
- clrbits_be32(&lbc->mcmr, MxMR_OP_WARR);
-}
-#endif /* CONFIG_CAN_DRIVER */
-
-uint get_lbc_clock (void)
-{
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- sys_info_t sys_info;
- ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
-
- get_sys_info (&sys_info);
-
- if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
-#ifdef CONFIG_MPC8548
- /*
- * Yes, the entire PQ38 family use the same
- * bit-representation for twice the clock divider value.
- */
- clkdiv *= 2;
-#endif
- return sys_info.freqSystemBus / clkdiv;
- }
-
- puts("Invalid clock divider value in CONFIG_SYS_LBC_LCRR\n");
-
- return 0;
-}
-
-/*
- * Initialize Local Bus
- */
-void local_bus_init (void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- uint lbc_mhz = get_lbc_clock () / 1000000;
-
-#ifdef CONFIG_MPC8548
- uint svr = get_svr ();
- uint lcrr;
-
- /*
- * MPC revision < 2.0
- * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1:
- * Modify engineering use only register at address 0xE_0F20.
- * "1. Read register at offset 0xE_0F20
- * 2. And value with 0x0000_FFFF
- * 3. OR result with 0x0000_0004
- * 4. Write result back to offset 0xE_0F20."
- *
- * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2:
- * Modify engineering use only register at address 0xE_0F20.
- * "1. Read register at offset 0xE_0F20
- * 2. And value with 0xFFFF_FFDF
- * 3. Write result back to offset 0xE_0F20."
- *
- * Since it is the same register, we do the modification in one step.
- */
- if (SVR_MAJ (svr) < 2) {
- uint dummy = gur->lbiuiplldcr1;
- dummy &= 0x0000FFDF;
- dummy |= 0x00000004;
- gur->lbiuiplldcr1 = dummy;
- }
-
- lcrr = CONFIG_SYS_LBC_LCRR;
-
- /*
- * Local Bus Clock > 83.3 MHz. According to timing
- * specifications set LCRR[EADC] to 2 delay cycles.
- */
- if (lbc_mhz > 83) {
- lcrr &= ~LCRR_EADC;
- lcrr |= LCRR_EADC_2;
- }
-
- /*
- * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
- * disable PLL bypass for Local Bus Clock > 83 MHz.
- */
- if (lbc_mhz >= 66)
- lcrr &= (~LCRR_DBYP); /* DLL Enabled */
-
- else
- lcrr |= LCRR_DBYP; /* DLL Bypass */
-
- lbc->lcrr = lcrr;
- asm ("sync;isync;msync");
-
- /*
- * According to MPC8548ERMAD Rev.1.3 read back LCRR
- * and terminate with isync
- */
- lcrr = lbc->lcrr;
- asm ("isync;");
-
- /* let DLL stabilize */
- udelay (500);
-
-#else /* !CONFIG_MPC8548 */
-
- /*
- * Errata LBC11.
- * Fix Local Bus clock glitch when DLL is enabled.
- *
- * If localbus freq is < 66MHz, DLL bypass mode must be used.
- * If localbus freq is > 133MHz, DLL can be safely enabled.
- * Between 66 and 133, the DLL is enabled with an override workaround.
- */
-
- if (lbc_mhz < 66) {
- lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
- lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA |
- LTEDR_RAWA | LTEDR_CSD; /* Disable all error checking */
-
- } else if (lbc_mhz >= 133) {
- lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
-
- } else {
- /*
- * On REV1 boards, need to change CLKDIV before enable DLL.
- * Default CLKDIV is 8, change it to 4 temporarily.
- */
- uint pvr = get_pvr ();
- uint temp_lbcdll = 0;
-
- if (pvr == PVR_85xx_REV1) {
- /* FIXME: Justify the high bit here. */
- lbc->lcrr = 0x10000004;
- }
-
- lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
- udelay (200);
-
- /*
- * Sample LBC DLL ctrl reg, upshift it to set the
- * override bits.
- */
- temp_lbcdll = gur->lbcdllcr;
- gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
- asm ("sync;isync;msync");
- }
-#endif /* !CONFIG_MPC8548 */
-
-#ifdef CONFIG_CAN_DRIVER
- /*
- * According to timing specifications EAD must be
- * set if Local Bus Clock is > 83 MHz.
- */
- if (lbc_mhz > 83)
- set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
- else
- set_lbc_or(2, CONFIG_SYS_OR2_CAN);
- set_lbc_br(2, CONFIG_SYS_BR2_CAN);
-
- /* LGPL4 is UPWAIT */
- out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
-
- /* Initialize UPMC for CAN: single read */
- upmc_write (0x00, 0xFFFFED00);
- upmc_write (0x01, 0xCCFFCC00);
- upmc_write (0x02, 0x00FFCF00);
- upmc_write (0x03, 0x00FFCF00);
- upmc_write (0x04, 0x00FFDC00);
- upmc_write (0x05, 0x00FFCF00);
- upmc_write (0x06, 0x00FFED00);
- upmc_write (0x07, 0x3FFFCC07);
-
- /* Initialize UPMC for CAN: single write */
- upmc_write (0x18, 0xFFFFED00);
- upmc_write (0x19, 0xCCFFEC00);
- upmc_write (0x1A, 0x00FFED80);
- upmc_write (0x1B, 0x00FFED80);
- upmc_write (0x1C, 0x00FFFC00);
- upmc_write (0x1D, 0x0FFFEC00);
- upmc_write (0x1E, 0x0FFFEF00);
- upmc_write (0x1F, 0x3FFFEC05);
-#endif /* CONFIG_CAN_DRIVER */
-}
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifdef CONFIG_PCI1
-static struct pci_controller pci1_hose;
-#endif /* CONFIG_PCI1 */
-
-void pci_init_board (void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- int first_free_busno = 0;
-#ifdef CONFIG_PCI1
- struct fsl_pci_info pci_info;
- int pcie_ep;
-
- u32 devdisr = in_be32(&gur->devdisr);
-
- uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
- uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
- uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */
- uint pci_clk_sel = in_be32(&gur->porpllsr) & MPC85xx_PORDEVSR_PCI1_SPD;
-
- if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
- SET_STD_PCI_INFO(pci_info, 1);
- set_next_law(pci_info.mem_phys,
- law_size_bits(pci_info.mem_size), pci_info.law);
- set_next_law(pci_info.io_phys,
- law_size_bits(pci_info.io_size), pci_info.law);
-
- pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
- printf("PCI1: %d bit, %s MHz, %s, %s, %s\n",
- (pci_32) ? 32 : 64,
- (pci_speed == 33333333) ? "33" :
- (pci_speed == 66666666) ? "66" : "unknown",
- pci_clk_sel ? "sync" : "async",
- pcie_ep ? "agent" : "host",
- pci_arb ? "arbiter" : "external-arbiter");
- first_free_busno = fsl_pci_init_port(&pci_info,
- &pci1_hose, first_free_busno);
-#ifdef CONFIG_PCIX_CHECK
- if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1)) {
- ushort reg16 =
- PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
- PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
- uint dev = PCI_BDF(0, 0, 0);
-
- /* PCI-X init */
- if (CONFIG_SYS_CLK_FREQ < 66000000)
- puts ("PCI-X will only work at 66 MHz\n");
-
- pci_write_config_word(dev, PCIX_COMMAND, reg16);
- }
-#endif
- } else {
- printf("PCI1: disabled\n");
- }
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
-#endif
-
- fsl_pcie_init_board(first_free_busno);
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-void ft_board_setup (void *blob, bd_t *bd)
-{
- ft_cpu_setup (blob, bd);
-
- FT_FSL_PCI_SETUP;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-#ifdef CONFIG_BOARD_EARLY_INIT_R
-int board_early_init_r (void)
-{
-#ifdef CONFIG_PS2MULT
- ps2mult_early_init ();
-#endif /* CONFIG_PS2MULT */
- return (0);
-}
-#endif /* CONFIG_BOARD_EARLY_INIT_R */
-
-int board_eth_init(bd_t *bis)
-{
- cpu_eth_init(bis); /* Intialize TSECs first */
- return pci_eth_init(bis);
-}
drivers/pcmcia/libpcmcia.o (.text.pcmcia_hardware_enable)
drivers/rtc/librtc.o (.text*)
drivers/misc/libmisc.o (.text*)
- *(.text.print_buffer)
- *(.text.print_size)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv*)
int board_late_init(void)
{
-#if defined(CONFIG_SERIAL_MULTI)
char *console=getenv("boot_console");
if ((console == NULL) || (strcmp(console,"serial_btuart") &&
setenv("stdout",console);
setenv("stdin", console);
setenv("stderr",console);
-#endif
return 0;
}
-struct serial_device *default_serial_console (void)
-{
- return &serial_ffuart_device;
-}
-
int dram_init(void)
{
pxa2xx_dram_init();
return 0;
}
-struct serial_device *default_serial_console(void)
-{
- return &serial_ffuart_device;
-}
-
int dram_init(void)
{
#ifndef CONFIG_ONENAND
unsigned long get_dram_size (void);
void sdram_init(void);
-/*
- * Macros to transform values
- * into environment strings.
- */
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
/* ------------------------------------------------------------------------- */
int board_early_init_f (void)
/* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
eth = (char *)(vpd->ethAddrs[0]);
if (ethaddr
- && (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) {
+ && (strcmp(ethaddr, __stringify(CONFIG_ETHADDR)) == 0)) {
/* Now setup ethaddr */
sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
eth[0], eth[1], eth[2], eth[3], eth[4],
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y := board.o
+
+COBJS := $(sort $(COBJS-y))
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ icache_enable();
+
+ return 0;
+}
+
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ u32 ret = 0;
+
+#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0)
+ ret = zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
+#endif
+
+ return ret;
+}
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
#define REBOOT_DO_POST 0x00000001
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-extern env_t *env_ptr;
ulong flash_get_size(ulong base, int banknum);
void env_crc_update(void);
return 0;
}
-struct serial_device *default_serial_console (void)
-{
- return &serial_stuart_device;
-}
-
int dram_init(void)
{
pxa2xx_dram_init();
scb9328 arm arm920t - - imx
cm4008 arm arm920t - - ks8695
cm41xx arm arm920t - - ks8695
+mini2440 arm arm920t mini2440 friendlyarm s3c24x0
VCMA9 arm arm920t vcma9 mpl s3c24x0
smdk2410 arm arm920t - samsung s3c24x0
omap1510inn arm arm925t - ti
calimain arm arm926ejs calimain omicron davinci
pogo_e02 arm arm926ejs - cloudengines kirkwood
dns325 arm arm926ejs - d-link kirkwood
+iconnect arm arm926ejs - iomega kirkwood
lschlv2 arm arm926ejs lsxl buffalo kirkwood lsxl:LSCHLV2
lsxhl arm arm926ejs lsxl buffalo kirkwood lsxl:LSXHL
km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD
mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN
kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN
portl2 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_PORTL2
+d2net_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:D2NET_V2
inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2
net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2
+netspace_lite_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_LITE_V2
netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MAX_V2
+netspace_mini_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MINI_V2
netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_V2
dreamplug arm arm926ejs - Marvell kirkwood
guruplug arm arm926ejs - Marvell kirkwood
spear600_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,nand
spear600_usbtty arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty
spear600_usbtty_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty,nand
+x600 arm arm926ejs - spear spear x600
versatileab arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_AB
versatilepb arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_PB
versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB
ima3-mx53 arm armv7 ima3-mx53 esg mx5 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg
vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
-mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/mx6qsabrelite/imximage.cfg
+mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
+mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
cm_t35 arm armv7 cm_t35 - omap3
omap3_overo arm armv7 overo - omap3
omap3_pandora arm armv7 pandora - omap3
whistler arm armv7:arm720t whistler nvidia tegra20
u8500_href arm armv7 u8500 st-ericsson u8500
snowball arm armv7 snowball st-ericsson u8500
+kzm9g arm armv7 kzm9g kmc rmobile
+armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile
+zynq arm armv7 zynq xilinx zynq
+socfpga_cyclone5 arm armv7 socfpga_cyclone5 altera socfpga
actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2
actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB
actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8
colibri_pxa270 arm pxa - toradex
jornada arm sa1100
plutux arm armv7:arm720t plutux avionic-design tegra20
-medcom arm armv7:arm720t medcom avionic-design tegra20
+medcom-wide arm armv7:arm720t medcom-wide avionic-design tegra20
tec arm armv7:arm720t tec avionic-design tegra20
paz00 arm armv7:arm720t paz00 compal tegra20
trimslice arm armv7:arm720t trimslice compulab tegra20
dbau1500 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1500
dbau1550 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1550
dbau1550_el mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN
-gth2 mips mips32 - - au1x00
pb1000 mips mips32 pb1x00 - au1x00 pb1x00:PB1000
incaip mips mips32 incaip - incaip
incaip_100MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=100000000
stxgp3 powerpc mpc85xx stxgp3 stx
stxssa powerpc mpc85xx stxssa stx - stxssa
stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M
-TQM8540 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8540,TQM8540=y,HOSTNAME=tqm8540,BOARDNAME="TQM8540"
-TQM8541 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8541,TQM8541=y,HOSTNAME=tqm8541,BOARDNAME="TQM8541"
-TQM8548 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8548,TQM8548=y,HOSTNAME=tqm8548,BOARDNAME="TQM8548"
-TQM8548_AG powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8548,TQM8548_AG=y,HOSTNAME=tqm8485,BOARDNAME="TQM8548_AG"
-TQM8548_BE powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8548,TQM8548_BE=y,HOSTNAME=tqm8548,BOARDNAME="TQM8548_BE"
-TQM8555 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8555,TQM8555=y,HOSTNAME=tqm8555,BOARDNAME="TQM8555"
-TQM8560 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8560,TQM8560=y,HOSTNAME=tqm8560,BOARDNAME="TQM8560"
xpedite520x powerpc mpc85xx - xes
xpedite537x powerpc mpc85xx - xes
xpedite550x powerpc mpc85xx - xes
korat powerpc ppc4xx
korat_perm powerpc ppc4xx korat - - korat:KORAT_PERMANENT
lwmon5 powerpc ppc4xx
-ML2 powerpc ppc4xx ml2
pcs440ep powerpc ppc4xx
quad100hd powerpc ppc4xx
sbc405 powerpc ppc4xx
yellowstone powerpc ppc4xx yosemite amcc - yosemite:YELLOWSTONE
yosemite powerpc ppc4xx yosemite amcc - yosemite:YOSEMITE
yucca powerpc ppc4xx - amcc
-AP1000 powerpc ppc4xx ap1000 amirix
fx12mm powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o
fx12mm_flash powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o
v5fx30teval powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o
PPChameleonEVB_HI_33 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_33
PPChameleonEVB_ME_25 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25
PPChameleonEVB_ME_33 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33
-ADCIOP powerpc ppc4xx adciop esd
APC405 powerpc ppc4xx apc405 esd
AR405 powerpc ppc4xx ar405 esd
ASH405 powerpc ppc4xx ash405 esd
CPCI405AB powerpc ppc4xx cpci405 esd
CPCI405DT powerpc ppc4xx cpci405 esd
CPCIISER4 powerpc ppc4xx cpciiser4 esd
-DASA_SIM powerpc ppc4xx dasa_sim esd
DP405 powerpc ppc4xx dp405 esd
DU405 powerpc ppc4xx du405 esd
DU440 powerpc ppc4xx du440 esd
COBJS-y += exports.o
COBJS-$(CONFIG_SYS_HUSH_PARSER) += hush.o
COBJS-y += s_record.o
-COBJS-$(CONFIG_SERIAL_MULTI) += serial.o
COBJS-y += xyzModem.o
COBJS-y += cmd_disk.o
COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o
COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o
COBJS-$(CONFIG_CMD_IMMAP) += cmd_immap.o
+COBJS-$(CONFIG_CMD_INI) += cmd_ini.o
COBJS-$(CONFIG_CMD_IRQ) += cmd_irq.o
COBJS-$(CONFIG_CMD_ITEST) += cmd_itest.o
COBJS-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o
ifdef CONFIG_SPL_BUILD
COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
+COBJS-$(CONFIG_SPL_NET_SUPPORT) += cmd_nvedit.o
+COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_common.o
+COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_nowhere.o
+COBJS-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
endif
COBJS-y += console.o
COBJS-y += dlmalloc.o
$(obj)../tools/envcrc:
$(MAKE) -C ../tools
+# SEE README.arm-unaligned-accesses
+$(obj)hush.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
+$(obj)fdt_support.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
+
#########################################################################
# defines $(obj).depend target
}
__maybe_unused
-static void print_lnum(const char *name, u64 value)
+static void print_lnum(const char *name, unsigned long long value)
{
printf("%-12s= 0x%.8llX\n", name, value);
}
puts("No arch specific invalidate_icache_all available!\n");
}
-int do_icache ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_icache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
switch (argc) {
case 2: /* on / off */
switch (parse_argv(argv[1])) {
- case 0: icache_disable();
+ case 0:
+ icache_disable();
break;
- case 1: icache_enable ();
+ case 1:
+ icache_enable();
break;
- case 2: invalidate_icache_all();
+ case 2:
+ invalidate_icache_all();
break;
}
- /* FALL TROUGH */
+ break;
case 1: /* get status */
- printf ("Instruction Cache is %s\n",
+ printf("Instruction Cache is %s\n",
icache_status() ? "ON" : "OFF");
return 0;
default:
/* please define arch specific flush_dcache_all */
}
-int do_dcache ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_dcache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
switch (argc) {
- case 2: /* on / off */
+ case 2: /* on / off */
switch (parse_argv(argv[1])) {
- case 0: dcache_disable();
+ case 0:
+ dcache_disable();
break;
- case 1: dcache_enable ();
+ case 1:
+ dcache_enable();
break;
- case 2: flush_dcache_all();
+ case 2:
+ flush_dcache_all();
break;
}
- /* FALL TROUGH */
+ break;
case 1: /* get status */
- printf ("Data (writethrough) Cache is %s\n",
+ printf("Data (writethrough) Cache is %s\n",
dcache_status() ? "ON" : "OFF");
return 0;
default:
return CMD_RET_USAGE;
}
return 0;
-
}
static int parse_argv(const char *s)
{
- if (strcmp(s, "flush") == 0) {
- return (2);
- } else if (strcmp(s, "on") == 0) {
- return (1);
- } else if (strcmp(s, "off") == 0) {
- return (0);
- }
- return (-1);
+ if (strcmp(s, "flush") == 0)
+ return 2;
+ else if (strcmp(s, "on") == 0)
+ return 1;
+ else if (strcmp(s, "off") == 0)
+ return 0;
+
+ return -1;
}
static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
const char *str_env;
- char s[] = "dfu";
+ char *s = "dfu";
char *env_bkp;
int ret;
int putnl = 1;
for (i = 1; i < argc; i++) {
- char *p = argv[i], c;
+ char *p = argv[i];
+ char *nls; /* new-line suppression */
if (i > 1)
putc(' ');
- while ((c = *p++) != '\0') {
- if (c == '\\' && *p == 'c') {
- putnl = 0;
- p++;
- } else {
- putc(c);
+
+ nls = strstr(p, "\\c");
+ if (nls) {
+ char *prenls = p;
+
+ putnl = 0;
+ /*
+ * be paranoid and guess that someone might
+ * say \c more than once
+ */
+ while (nls) {
+ *nls = '\0';
+ puts(prenls);
+ *nls = '\\';
+ prenls = nls + 2;
+ nls = strstr(prenls, "\\c");
}
+ puts(prenls);
+ } else {
+ puts(p);
}
}
DECLARE_GLOBAL_DATA_PTR;
#endif
-int valid_elf_image (unsigned long addr);
static unsigned long load_elf_image_phdr(unsigned long addr);
static unsigned long load_elf_image_shdr(unsigned long addr);
/* Allow ports to override the default behavior */
__attribute__((weak))
-unsigned long do_bootelf_exec (ulong (*entry)(int, char * const[]),
+unsigned long do_bootelf_exec(ulong (*entry)(int, char * const[]),
int argc, char * const argv[])
{
unsigned long ret;
* QNX images require the data cache is disabled.
* Data cache is already flushed, so just turn it off.
*/
- int dcache = dcache_status ();
+ int dcache = dcache_status();
if (dcache)
- dcache_disable ();
+ dcache_disable();
/*
* pass address parameter as argv[0] (aka command name),
* and all remaining args
*/
- ret = entry (argc, argv);
+ ret = entry(argc, argv);
if (dcache)
- dcache_enable ();
+ dcache_enable();
return ret;
}
/* ======================================================================
+ * Determine if a valid ELF image exists at the given memory location.
+ * First looks at the ELF header magic field, the makes sure that it is
+ * executable and makes sure that it is for a PowerPC.
+ * ====================================================================== */
+int valid_elf_image(unsigned long addr)
+{
+ Elf32_Ehdr *ehdr; /* Elf header structure pointer */
+
+ /* -------------------------------------------------- */
+
+ ehdr = (Elf32_Ehdr *) addr;
+
+ if (!IS_ELF(*ehdr)) {
+ printf("## No elf image at address 0x%08lx\n", addr);
+ return 0;
+ }
+
+ if (ehdr->e_type != ET_EXEC) {
+ printf("## Not a 32-bit elf image at address 0x%08lx\n", addr);
+ return 0;
+ }
+
+#if 0
+ if (ehdr->e_machine != EM_PPC) {
+ printf("## Not a PowerPC elf image at address 0x%08lx\n", addr);
+ return 0;
+ }
+#endif
+
+ return 1;
+}
+
+/* ======================================================================
* Interpreter command to boot an arbitrary ELF image from memory.
* ====================================================================== */
-int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned long addr; /* Address of the ELF image */
unsigned long rc; /* Return value from user code */
else
addr = load_addr;
- if (!valid_elf_image (addr))
+ if (!valid_elf_image(addr))
return 1;
if (sload && sload[1] == 'p')
else
addr = load_elf_image_shdr(addr);
- printf ("## Starting application at 0x%08lx ...\n", addr);
+ printf("## Starting application at 0x%08lx ...\n", addr);
/*
* pass address parameter as argv[0] (aka command name),
* and all remaining args
*/
- rc = do_bootelf_exec ((void *)addr, argc - 1, argv + 1);
+ rc = do_bootelf_exec((void *)addr, argc - 1, argv + 1);
if (rc != 0)
rcode = 1;
- printf ("## Application terminated, rc = 0x%lx\n", rc);
+ printf("## Application terminated, rc = 0x%lx\n", rc);
return rcode;
}
* be either an ELF image or a raw binary. Will attempt to setup the
* bootline and other parameters correctly.
* ====================================================================== */
-int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned long addr; /* Address of image */
- unsigned long bootaddr; /* Address to put the bootline */
+ unsigned long bootaddr; /* Address to put the bootline */
char *bootline; /* Text of the bootline */
char *tmp; /* Temporary char pointer */
char build_buf[128]; /* Buffer for building the bootline */
if (argc < 2)
addr = load_addr;
else
- addr = simple_strtoul (argv[1], NULL, 16);
+ addr = simple_strtoul(argv[1], NULL, 16);
#if defined(CONFIG_CMD_NET)
- /* Check to see if we need to tftp the image ourselves before starting */
-
- if ((argc == 2) && (strcmp (argv[1], "tftp") == 0)) {
+ /*
+ * Check to see if we need to tftp the image ourselves before starting
+ */
+ if ((argc == 2) && (strcmp(argv[1], "tftp") == 0)) {
if (NetLoop(TFTPGET) <= 0)
return 1;
- printf("Automatic boot of VxWorks image at address 0x%08lx "
- "...\n", addr);
+ printf("Automatic boot of VxWorks image at address 0x%08lx ...\n",
+ addr);
}
#endif
eth_getenv_enetaddr("ethaddr", (uchar *)build_buf);
memcpy(tmp, build_buf, 6);
#else
- puts ("## Ethernet MAC address not copied to NV RAM\n");
+ puts("## Ethernet MAC address not copied to NV RAM\n");
#endif
/*
* PowerPC is LOCAL_MEM_LOCAL_ADRS + BOOT_LINE_OFFSET which
* defaults to 0x4200
*/
-
- if ((tmp = getenv ("bootaddr")) == NULL)
+ tmp = getenv("bootaddr");
+ if (tmp)
bootaddr = CONFIG_SYS_VXWORKS_BOOT_ADDR;
else
- bootaddr = simple_strtoul (tmp, NULL, 16);
+ bootaddr = simple_strtoul(tmp, NULL, 16);
/*
* Check to see if the bootline is defined in the 'bootargs'
* parameter. If it is not defined, we may be able to
* construct the info
*/
-
- if ((bootline = getenv ("bootargs")) != NULL) {
- memcpy ((void *) bootaddr, bootline,
- max (strlen (bootline), 255));
- flush_cache (bootaddr, max (strlen (bootline), 255));
+ bootline = getenv("bootargs");
+ if (bootline) {
+ memcpy((void *) bootaddr, bootline,
+ max(strlen(bootline), 255));
+ flush_cache(bootaddr, max(strlen(bootline), 255));
} else {
-
-
- sprintf (build_buf, CONFIG_SYS_VXWORKS_BOOT_DEVICE);
- if ((tmp = getenv ("bootfile")) != NULL) {
- sprintf (&build_buf[strlen (build_buf)],
+ sprintf(build_buf, CONFIG_SYS_VXWORKS_BOOT_DEVICE);
+ tmp = getenv("bootfile");
+ if (tmp)
+ sprintf(&build_buf[strlen(build_buf)],
"%s:%s ", CONFIG_SYS_VXWORKS_SERVERNAME, tmp);
- } else {
- sprintf (&build_buf[strlen (build_buf)],
+ else
+ sprintf(&build_buf[strlen(build_buf)],
"%s:file ", CONFIG_SYS_VXWORKS_SERVERNAME);
- }
- if ((tmp = getenv ("ipaddr")) != NULL) {
- sprintf (&build_buf[strlen (build_buf)], "e=%s ", tmp);
- }
+ tmp = getenv("ipaddr");
+ if (tmp)
+ sprintf(&build_buf[strlen(build_buf)], "e=%s ", tmp);
- if ((tmp = getenv ("serverip")) != NULL) {
- sprintf (&build_buf[strlen (build_buf)], "h=%s ", tmp);
- }
+ tmp = getenv("serverip");
+ if (tmp)
+ sprintf(&build_buf[strlen(build_buf)], "h=%s ", tmp);
+
+ tmp = getenv("hostname");
+ if (tmp)
+ sprintf(&build_buf[strlen(build_buf)], "tn=%s ", tmp);
- if ((tmp = getenv ("hostname")) != NULL) {
- sprintf (&build_buf[strlen (build_buf)], "tn=%s ", tmp);
- }
#ifdef CONFIG_SYS_VXWORKS_ADD_PARAMS
- sprintf (&build_buf[strlen (build_buf)],
+ sprintf(&build_buf[strlen(build_buf)],
CONFIG_SYS_VXWORKS_ADD_PARAMS);
#endif
- memcpy ((void *) bootaddr, build_buf,
- max (strlen (build_buf), 255));
- flush_cache (bootaddr, max (strlen (build_buf), 255));
+ memcpy((void *) bootaddr, build_buf,
+ max(strlen(build_buf), 255));
+ flush_cache(bootaddr, max(strlen(build_buf), 255));
}
/*
* binary image
*/
- if (valid_elf_image (addr)) {
- addr = load_elf_image_shdr (addr);
+ if (valid_elf_image(addr)) {
+ addr = load_elf_image_shdr(addr);
} else {
- puts ("## Not an ELF image, assuming binary\n");
+ puts("## Not an ELF image, assuming binary\n");
/* leave addr as load_addr */
}
- printf ("## Using bootline (@ 0x%lx): %s\n", bootaddr,
+ printf("## Using bootline (@ 0x%lx): %s\n", bootaddr,
(char *) bootaddr);
- printf ("## Starting vxWorks at 0x%08lx ...\n", addr);
+ printf("## Starting vxWorks at 0x%08lx ...\n", addr);
dcache_disable();
((void (*)(int)) addr) (0);
- puts ("## vxWorks terminated\n");
- return 1;
-}
-
-/* ======================================================================
- * Determine if a valid ELF image exists at the given memory location.
- * First looks at the ELF header magic field, the makes sure that it is
- * executable and makes sure that it is for a PowerPC.
- * ====================================================================== */
-int valid_elf_image (unsigned long addr)
-{
- Elf32_Ehdr *ehdr; /* Elf header structure pointer */
-
- /* -------------------------------------------------- */
-
- ehdr = (Elf32_Ehdr *) addr;
-
- if (!IS_ELF (*ehdr)) {
- printf ("## No elf image at address 0x%08lx\n", addr);
- return 0;
- }
-
- if (ehdr->e_type != ET_EXEC) {
- printf ("## Not a 32-bit elf image at address 0x%08lx\n", addr);
- return 0;
- }
-
-#if 0
- if (ehdr->e_machine != EM_PPC) {
- printf ("## Not a PowerPC elf image at address 0x%08lx\n",
- addr);
- return 0;
- }
-#endif
-
+ puts("## vxWorks terminated\n");
return 1;
}
/* Load each program header */
for (i = 0; i < ehdr->e_phnum; ++i) {
- void *dst = (void *) phdr->p_paddr;
+ void *dst = (void *)(uintptr_t) phdr->p_paddr;
void *src = (void *) addr + phdr->p_offset;
debug("Loading phdr %i to 0x%p (%i bytes)\n",
i, dst, phdr->p_filesz);
if (phdr->p_filesz)
memcpy(dst, src, phdr->p_filesz);
if (phdr->p_filesz != phdr->p_memsz)
- memset(dst + phdr->p_filesz, 0x00, phdr->p_memsz - phdr->p_filesz);
+ memset(dst + phdr->p_filesz, 0x00,
+ phdr->p_memsz - phdr->p_filesz);
flush_cache((unsigned long)dst, phdr->p_filesz);
++phdr;
}
/* Find the section header string table for output info */
shdr = (Elf32_Shdr *) (addr + ehdr->e_shoff +
- (ehdr->e_shstrndx * sizeof (Elf32_Shdr)));
+ (ehdr->e_shstrndx * sizeof(Elf32_Shdr)));
if (shdr->sh_type == SHT_STRTAB)
strtab = (unsigned char *) (addr + shdr->sh_offset);
/* Load each appropriate section */
for (i = 0; i < ehdr->e_shnum; ++i) {
shdr = (Elf32_Shdr *) (addr + ehdr->e_shoff +
- (i * sizeof (Elf32_Shdr)));
+ (i * sizeof(Elf32_Shdr)));
if (!(shdr->sh_flags & SHF_ALLOC)
|| shdr->sh_addr == 0 || shdr->sh_size == 0) {
}
if (shdr->sh_type == SHT_NOBITS) {
- memset ((void *)shdr->sh_addr, 0, shdr->sh_size);
+ memset((void *)(uintptr_t) shdr->sh_addr, 0,
+ shdr->sh_size);
} else {
image = (unsigned char *) addr + shdr->sh_offset;
- memcpy ((void *) shdr->sh_addr,
+ memcpy((void *)(uintptr_t) shdr->sh_addr,
(const void *) image,
shdr->sh_size);
}
- flush_cache (shdr->sh_addr, shdr->sh_size);
+ flush_cache(shdr->sh_addr, shdr->sh_size);
}
return ehdr->e_entry;
/* We only need to swap data if we are running on a big endian cpu. */
/* But Au1x00 cpu:s already swaps data in big endian mode! */
-#if defined(__LITTLE_ENDIAN) || \
- (defined(CONFIG_SOC_AU1X00) && !defined(CONFIG_GTH2))
+#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SOC_AU1X00)
#define input_swap_data(x,y,z) input_data(x,y,z)
#else
static void input_swap_data(int dev, ulong *sect_buf, int words)
--- /dev/null
+/*
+ * inih -- simple .INI file parser
+ *
+ * Copyright (c) 2009, Brush Technology
+ * Copyright (c) 2012:
+ * Joe Hershberger, National Instruments, joe.hershberger@ni.com
+ * All rights reserved.
+ *
+ * The "inih" library is distributed under the following license, which is
+ * derived from and very similar to the 3-clause BSD license:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Brush Technology nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BRUSH TECHNOLOGY ''AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL BRUSH TECHNOLOGY BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Go to the project home page for more info:
+ * http://code.google.com/p/inih/
+ */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+
+#ifdef CONFIG_INI_MAX_LINE
+#define MAX_LINE CONFIG_INI_MAX_LINE
+#else
+#define MAX_LINE 200
+#endif
+
+#ifdef CONFIG_INI_MAX_SECTION
+#define MAX_SECTION CONFIG_INI_MAX_SECTION
+#else
+#define MAX_SECTION 50
+#endif
+
+#ifdef CONFIG_INI_MAX_NAME
+#define MAX_NAME CONFIG_INI_MAX_NAME
+#else
+#define MAX_NAME 50
+#endif
+
+/* Strip whitespace chars off end of given string, in place. Return s. */
+static char *rstrip(char *s)
+{
+ char *p = s + strlen(s);
+
+ while (p > s && isspace(*--p))
+ *p = '\0';
+ return s;
+}
+
+/* Return pointer to first non-whitespace char in given string. */
+static char *lskip(const char *s)
+{
+ while (*s && isspace(*s))
+ s++;
+ return (char *)s;
+}
+
+/* Return pointer to first char c or ';' comment in given string, or pointer to
+ null at end of string if neither found. ';' must be prefixed by a whitespace
+ character to register as a comment. */
+static char *find_char_or_comment(const char *s, char c)
+{
+ int was_whitespace = 0;
+
+ while (*s && *s != c && !(was_whitespace && *s == ';')) {
+ was_whitespace = isspace(*s);
+ s++;
+ }
+ return (char *)s;
+}
+
+/* Version of strncpy that ensures dest (size bytes) is null-terminated. */
+static char *strncpy0(char *dest, const char *src, size_t size)
+{
+ strncpy(dest, src, size);
+ dest[size - 1] = '\0';
+ return dest;
+}
+
+/* Emulate the behavior of fgets but on memory */
+static char *memgets(char *str, int num, char **mem, size_t *memsize)
+{
+ char *end;
+ int len;
+ int newline = 1;
+
+ end = memchr(*mem, '\n', *memsize);
+ if (end == NULL) {
+ if (*memsize == 0)
+ return NULL;
+ end = *mem + *memsize;
+ newline = 0;
+ }
+ len = min((end - *mem) + newline, num);
+ memcpy(str, *mem, len);
+ if (len < num)
+ str[len] = '\0';
+
+ /* prepare the mem vars for the next call */
+ *memsize -= (end - *mem) + newline;
+ *mem += (end - *mem) + newline;
+
+ return str;
+}
+
+/* Parse given INI-style file. May have [section]s, name=value pairs
+ (whitespace stripped), and comments starting with ';' (semicolon). Section
+ is "" if name=value pair parsed before any section heading. name:value
+ pairs are also supported as a concession to Python's ConfigParser.
+
+ For each name=value pair parsed, call handler function with given user
+ pointer as well as section, name, and value (data only valid for duration
+ of handler call). Handler should return nonzero on success, zero on error.
+
+ Returns 0 on success, line number of first error on parse error (doesn't
+ stop on first error).
+*/
+static int ini_parse(char *filestart, size_t filelen,
+ int (*handler)(void *, char *, char *, char *), void *user)
+{
+ /* Uses a fair bit of stack (use heap instead if you need to) */
+ char line[MAX_LINE];
+ char section[MAX_SECTION] = "";
+ char prev_name[MAX_NAME] = "";
+
+ char *curmem = filestart;
+ char *start;
+ char *end;
+ char *name;
+ char *value;
+ size_t memleft = filelen;
+ int lineno = 0;
+ int error = 0;
+
+ /* Scan through file line by line */
+ while (memgets(line, sizeof(line), &curmem, &memleft) != NULL) {
+ lineno++;
+ start = lskip(rstrip(line));
+
+ if (*start == ';' || *start == '#') {
+ /*
+ * Per Python ConfigParser, allow '#' comments at start
+ * of line
+ */
+ }
+#if CONFIG_INI_ALLOW_MULTILINE
+ else if (*prev_name && *start && start > line) {
+ /*
+ * Non-blank line with leading whitespace, treat as
+ * continuation of previous name's value (as per Python
+ * ConfigParser).
+ */
+ if (!handler(user, section, prev_name, start) && !error)
+ error = lineno;
+ }
+#endif
+ else if (*start == '[') {
+ /* A "[section]" line */
+ end = find_char_or_comment(start + 1, ']');
+ if (*end == ']') {
+ *end = '\0';
+ strncpy0(section, start + 1, sizeof(section));
+ *prev_name = '\0';
+ } else if (!error) {
+ /* No ']' found on section line */
+ error = lineno;
+ }
+ } else if (*start && *start != ';') {
+ /* Not a comment, must be a name[=:]value pair */
+ end = find_char_or_comment(start, '=');
+ if (*end != '=')
+ end = find_char_or_comment(start, ':');
+ if (*end == '=' || *end == ':') {
+ *end = '\0';
+ name = rstrip(start);
+ value = lskip(end + 1);
+ end = find_char_or_comment(value, '\0');
+ if (*end == ';')
+ *end = '\0';
+ rstrip(value);
+ /* Strip double-quotes */
+ if (value[0] == '"' &&
+ value[strlen(value)-1] == '"') {
+ value[strlen(value)-1] = '\0';
+ value += 1;
+ }
+
+ /*
+ * Valid name[=:]value pair found, call handler
+ */
+ strncpy0(prev_name, name, sizeof(prev_name));
+ if (!handler(user, section, name, value) &&
+ !error)
+ error = lineno;
+ } else if (!error)
+ /* No '=' or ':' found on name[=:]value line */
+ error = lineno;
+ }
+ }
+
+ return error;
+}
+
+static int ini_handler(void *user, char *section, char *name, char *value)
+{
+ char *requested_section = (char *)user;
+#ifdef CONFIG_INI_CASE_INSENSITIVE
+ int i;
+
+ for (i = 0; i < strlen(requested_section); i++)
+ requested_section[i] = tolower(requested_section[i]);
+ for (i = 0; i < strlen(section); i++)
+ section[i] = tolower(section[i]);
+#endif
+
+ if (!strcmp(section, requested_section)) {
+#ifdef CONFIG_INI_CASE_INSENSITIVE
+ for (i = 0; i < strlen(name); i++)
+ name[i] = tolower(name[i]);
+ for (i = 0; i < strlen(value); i++)
+ value[i] = tolower(value[i]);
+#endif
+ setenv(name, value);
+ printf("ini: Imported %s as %s\n", name, value);
+ }
+
+ /* success */
+ return 1;
+}
+
+static int do_ini(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ const char *section;
+ char *file_address;
+ size_t file_size;
+
+ if (argc == 1)
+ return CMD_RET_USAGE;
+
+ section = argv[1];
+ file_address = (char *)simple_strtoul(
+ argc < 3 ? getenv("loadaddr") : argv[2], NULL, 16);
+ file_size = (size_t)simple_strtoul(
+ argc < 4 ? getenv("filesize") : argv[3], NULL, 16);
+
+ return ini_parse(file_address, file_size, ini_handler, (void *)section);
+}
+
+U_BOOT_CMD(
+ ini, 4, 0, do_ini,
+ "parse an ini file in memory and merge the specified section into the env",
+ "section [[file-address] file-size]"
+);
/*
+ * (C) Copyright 2011
+ * Joe Hershberger, National Instruments, joe.hershberger@ni.com
+ *
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
#include <command.h>
#include <u-boot/md5.h>
+/*
+ * Store the resulting sum to an address or variable
+ */
+static void store_result(const u8 *sum, const char *dest)
+{
+ unsigned int i;
+
+ if (*dest == '*') {
+ u8 *ptr;
+
+ ptr = (u8 *)simple_strtoul(dest + 1, NULL, 16);
+ for (i = 0; i < 16; i++)
+ *ptr++ = sum[i];
+ } else {
+ char str_output[33];
+ char *str_ptr = str_output;
+
+ for (i = 0; i < 16; i++) {
+ sprintf(str_ptr, "%02x", sum[i]);
+ str_ptr += 2;
+ }
+ str_ptr = '\0';
+ setenv(dest, str_output);
+ }
+}
+
+#ifdef CONFIG_MD5SUM_VERIFY
+static int parse_verify_sum(char *verify_str, u8 *vsum)
+{
+ if (*verify_str == '*') {
+ u8 *ptr;
+
+ ptr = (u8 *)simple_strtoul(verify_str + 1, NULL, 16);
+ memcpy(vsum, ptr, 16);
+ } else {
+ unsigned int i;
+ char *vsum_str;
+
+ if (strlen(verify_str) == 32)
+ vsum_str = verify_str;
+ else {
+ vsum_str = getenv(verify_str);
+ if (vsum_str == NULL || strlen(vsum_str) != 32)
+ return 1;
+ }
+
+ for (i = 0; i < 16; i++) {
+ char *nullp = vsum_str + (i + 1) * 2;
+ char end = *nullp;
+
+ *nullp = '\0';
+ *(u8 *)(vsum + i) =
+ simple_strtoul(vsum_str + (i * 2), NULL, 16);
+ *nullp = end;
+ }
+ }
+ return 0;
+}
+
+int do_md5sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong addr, len;
+ unsigned int i;
+ u8 output[16];
+ u8 vsum[16];
+ int verify = 0;
+ int ac;
+ char * const *av;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ av = argv + 1;
+ ac = argc - 1;
+ if (strcmp(*av, "-v") == 0) {
+ verify = 1;
+ av++;
+ ac--;
+ if (ac < 3)
+ return CMD_RET_USAGE;
+ }
+
+ addr = simple_strtoul(*av++, NULL, 16);
+ len = simple_strtoul(*av++, NULL, 16);
+
+ md5_wd((unsigned char *) addr, len, output, CHUNKSZ_MD5);
+
+ if (!verify) {
+ printf("md5 for %08lx ... %08lx ==> ", addr, addr + len - 1);
+ for (i = 0; i < 16; i++)
+ printf("%02x", output[i]);
+ printf("\n");
+
+ if (ac > 2)
+ store_result(output, *av);
+ } else {
+ char *verify_str = *av++;
+
+ if (parse_verify_sum(verify_str, vsum)) {
+ printf("ERROR: %s does not contain a valid md5 sum\n",
+ verify_str);
+ return 1;
+ }
+ if (memcmp(output, vsum, 16) != 0) {
+ printf("md5 for %08lx ... %08lx ==> ", addr,
+ addr + len - 1);
+ for (i = 0; i < 16; i++)
+ printf("%02x", output[i]);
+ printf(" != ");
+ for (i = 0; i < 16; i++)
+ printf("%02x", vsum[i]);
+ printf(" ** ERROR **\n");
+ return 1;
+ }
+ }
+
+ return 0;
+}
+#else
static int do_md5sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned long addr, len;
printf("%02x", output[i]);
printf("\n");
+ if (argc > 3)
+ store_result(output, argv[3]);
+
return 0;
}
+#endif
+#ifdef CONFIG_MD5SUM_VERIFY
+U_BOOT_CMD(
+ md5sum, 5, 1, do_md5sum,
+ "compute MD5 message digest",
+ "address count [[*]sum]\n"
+ " - compute MD5 message digest [save to sum]\n"
+ "md5sum -v address count [*]sum\n"
+ " - verify md5sum of memory area"
+);
+#else
U_BOOT_CMD(
- md5sum, 3, 1, do_md5sum,
+ md5sum, 4, 1, do_md5sum,
"compute MD5 message digest",
- "address count"
+ "address count [[*]sum]\n"
+ " - compute MD5 message digest [save to sum]"
);
+#endif
"N\n"
" - delay execution for N seconds (N is _decimal_ !!!)"
);
+
+#ifdef CONFIG_CMD_TIMER
+static int do_timer(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ static ulong start;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ if (!strcmp(argv[1], "start"))
+ start = get_timer(0);
+
+ if (!strcmp(argv[1], "get")) {
+ ulong msecs = get_timer(start) * 1000 / CONFIG_SYS_HZ;
+ printf("%ld.%03d\n", msecs / 1000, (int)(msecs % 1000));
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ timer, 2, 1, do_timer,
+ "access the system timer",
+ "start - Reset the timer reference.\n"
+ "timer get - Print the time since 'start'."
+);
+#endif
SPI_FLASH|NVRAM|MMC|FAT|REMOTE} or CONFIG_ENV_IS_NOWHERE
#endif
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
/*
* Maximum expected input data size for import command
*/
return env_id;
}
+#ifndef CONFIG_SPL_BUILD
/*
* Command interface: print one or all environment variables
*
return rcode;
}
#endif
+#endif /* CONFIG_SPL_BUILD */
/*
* Perform consistency checking before setting, replacing, or deleting an
{
int console = -1;
+ /* Default value for NULL to protect string-manipulating functions */
+ newval = newval ? : "";
+
/* Check for console redirection */
if (strcmp(name, "stdin") == 0)
console = stdin;
if (console_assign(console, newval) < 0)
return 1;
-#ifdef CONFIG_SERIAL_MULTI
if (serial_assign(newval) < 0)
return 1;
-#endif
#endif /* CONFIG_CONSOLE_MUX */
}
if (strcmp(name, "serial#") == 0 ||
(strcmp(name, "ethaddr") == 0
#if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR)
- && strcmp(oldval, MK_STR(CONFIG_ETHADDR)) != 0
+ && strcmp(oldval, __stringify(CONFIG_ETHADDR)) != 0
#endif /* CONFIG_OVERWRITE_ETHADDR_ONCE && CONFIG_ETHADDR */
)) {
printf("Can't overwrite \"%s\"\n", name);
return setenv(varname, str);
}
+#ifndef CONFIG_SPL_BUILD
int do_env_set(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc < 2)
return setenv(argv[1], buffer);
}
#endif /* CONFIG_CMD_EDITENV */
+#endif /* CONFIG_SPL_BUILD */
/*
* Look up variable from environment,
return str ? simple_strtoul(str, NULL, base) : default_val;
}
+#ifndef CONFIG_SPL_BUILD
#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
int do_env_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
""
);
#endif
+#endif /* CONFIG_SPL_BUILD */
/*
*/
int envmatch(uchar *s1, int i2)
{
+ if (s1 == NULL)
+ return -1;
+
while (*s1 == env_get_char(i2++))
if (*s1++ == '=')
return i2;
return -1;
}
+#ifndef CONFIG_SPL_BUILD
static int do_env_default(cmd_tbl_t *cmdtp, int __flag,
int argc, char * const argv[])
{
var_complete
);
#endif
+#endif /* CONFIG_SPL_BUILD */
/*
+ * (C) Copyright 2011
+ * Joe Hershberger, National Instruments, joe.hershberger@ni.com
+ *
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
#include <command.h>
#include <sha1.h>
+/*
+ * Store the resulting sum to an address or variable
+ */
+static void store_result(const u8 *sum, const char *dest)
+{
+ unsigned int i;
+
+ if (*dest == '*') {
+ u8 *ptr;
+
+ ptr = (u8 *)simple_strtoul(dest + 1, NULL, 16);
+ for (i = 0; i < 20; i++)
+ *ptr++ = sum[i];
+ } else {
+ char str_output[41];
+ char *str_ptr = str_output;
+
+ for (i = 0; i < 20; i++) {
+ sprintf(str_ptr, "%02x", sum[i]);
+ str_ptr += 2;
+ }
+ str_ptr = '\0';
+ setenv(dest, str_output);
+ }
+}
+
+#ifdef CONFIG_SHA1SUM_VERIFY
+static int parse_verify_sum(char *verify_str, u8 *vsum)
+{
+ if (*verify_str == '*') {
+ u8 *ptr;
+
+ ptr = (u8 *)simple_strtoul(verify_str + 1, NULL, 16);
+ memcpy(vsum, ptr, 20);
+ } else {
+ unsigned int i;
+ char *vsum_str;
+
+ if (strlen(verify_str) == 40)
+ vsum_str = verify_str;
+ else {
+ vsum_str = getenv(verify_str);
+ if (vsum_str == NULL || strlen(vsum_str) != 40)
+ return 1;
+ }
+
+ for (i = 0; i < 20; i++) {
+ char *nullp = vsum_str + (i + 1) * 2;
+ char end = *nullp;
+
+ *nullp = '\0';
+ *(u8 *)(vsum + i) =
+ simple_strtoul(vsum_str + (i * 2), NULL, 16);
+ *nullp = end;
+ }
+ }
+ return 0;
+}
+
+int do_sha1sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong addr, len;
+ unsigned int i;
+ u8 output[20];
+ u8 vsum[20];
+ int verify = 0;
+ int ac;
+ char * const *av;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ av = argv + 1;
+ ac = argc - 1;
+ if (strcmp(*av, "-v") == 0) {
+ verify = 1;
+ av++;
+ ac--;
+ if (ac < 3)
+ return CMD_RET_USAGE;
+ }
+
+ addr = simple_strtoul(*av++, NULL, 16);
+ len = simple_strtoul(*av++, NULL, 16);
+
+ sha1_csum_wd((unsigned char *) addr, len, output, CHUNKSZ_SHA1);
+
+ if (!verify) {
+ printf("SHA1 for %08lx ... %08lx ==> ", addr, addr + len - 1);
+ for (i = 0; i < 20; i++)
+ printf("%02x", output[i]);
+ printf("\n");
+
+ if (ac > 2)
+ store_result(output, *av);
+ } else {
+ char *verify_str = *av++;
+
+ if (parse_verify_sum(verify_str, vsum)) {
+ printf("ERROR: %s does not contain a valid SHA1 sum\n",
+ verify_str);
+ return 1;
+ }
+ if (memcmp(output, vsum, 20) != 0) {
+ printf("SHA1 for %08lx ... %08lx ==> ", addr,
+ addr + len - 1);
+ for (i = 0; i < 20; i++)
+ printf("%02x", output[i]);
+ printf(" != ");
+ for (i = 0; i < 20; i++)
+ printf("%02x", vsum[i]);
+ printf(" ** ERROR **\n");
+ return 1;
+ }
+ }
+
+ return 0;
+}
+#else
static int do_sha1sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned long addr, len;
printf("%02x", output[i]);
printf("\n");
+ if (argc > 3)
+ store_result(output, argv[3]);
+
return 0;
}
+#endif
+#ifdef CONFIG_SHA1SUM_VERIFY
+U_BOOT_CMD(
+ sha1sum, 5, 1, do_sha1sum,
+ "compute SHA1 message digest",
+ "address count [[*]sum]\n"
+ " - compute SHA1 message digest [save to sum]\n"
+ "sha1sum -v address count [*]sum\n"
+ " - verify sha1sum of memory area"
+);
+#else
U_BOOT_CMD(
- sha1sum, 3, 1, do_sha1sum,
+ sha1sum, 4, 1, do_sha1sum,
"compute SHA1 message digest",
- "address count"
+ "address count [[*]sum]\n"
+ " - compute SHA1 message digest [save to sum]"
);
+#endif
if (argc < 3)
return 1;
-#if 0
+#ifdef DEBUG
{
- printf("test:");
+ debug("test(%d):", argc);
left = 1;
while (argv[left])
- printf(" %s", argv[left++]);
+ debug(" '%s'", argv[left++]);
}
#endif
bootstage_mark_name(BOOTSTAGE_ID_USB_START, "usb_start");
usb_stop();
printf("(Re)start USB...\n");
- i = usb_init();
- if (i >= 0) {
+ if (usb_init() >= 0) {
#ifdef CONFIG_USB_STORAGE
/* try to recognize storage devices immediately */
usb_stor_curr_dev = usb_stor_scan(1);
/* try to recognize ethernet devices immediately */
usb_ether_curr_dev = usb_host_eth_scan(1);
#endif
+#ifdef CONFIG_USB_KEYBOARD
+ drv_usb_kbd_init();
+#endif
}
return 0;
}
return 1;
}
if (strncmp(argv[1], "tree", 4) == 0) {
- printf("\nDevice Tree:\n");
- usb_show_tree(usb_get_dev_index(0));
+ puts("USB device tree:\n");
+ for (i = 0; i < USB_MAX_DEVICE; i++) {
+ dev = usb_get_dev_index(i);
+ if (dev == NULL)
+ break;
+ if (dev->parent == NULL)
+ usb_show_tree(dev);
+ }
return 0;
}
if (strncmp(argv[1], "inf", 3) == 0) {
/************************************************************************
* Default settings to be used when no valid environment is found
*/
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
const uchar default_environment[] = {
#ifdef CONFIG_BOOTARGS
"nfsboot=" CONFIG_NFSBOOTCOMMAND "\0"
#endif
#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
- "bootdelay=" MK_STR(CONFIG_BOOTDELAY) "\0"
+ "bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0"
#endif
#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
- "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0"
+ "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"
#endif
#ifdef CONFIG_LOADS_ECHO
- "loads_echo=" MK_STR(CONFIG_LOADS_ECHO) "\0"
+ "loads_echo=" __stringify(CONFIG_LOADS_ECHO) "\0"
#endif
#ifdef CONFIG_ETHADDR
- "ethaddr=" MK_STR(CONFIG_ETHADDR) "\0"
+ "ethaddr=" __stringify(CONFIG_ETHADDR) "\0"
#endif
#ifdef CONFIG_ETH1ADDR
- "eth1addr=" MK_STR(CONFIG_ETH1ADDR) "\0"
+ "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"
#endif
#ifdef CONFIG_ETH2ADDR
- "eth2addr=" MK_STR(CONFIG_ETH2ADDR) "\0"
+ "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"
#endif
#ifdef CONFIG_ETH3ADDR
- "eth3addr=" MK_STR(CONFIG_ETH3ADDR) "\0"
+ "eth3addr=" __stringify(CONFIG_ETH3ADDR) "\0"
#endif
#ifdef CONFIG_ETH4ADDR
- "eth4addr=" MK_STR(CONFIG_ETH4ADDR) "\0"
+ "eth4addr=" __stringify(CONFIG_ETH4ADDR) "\0"
#endif
#ifdef CONFIG_ETH5ADDR
- "eth5addr=" MK_STR(CONFIG_ETH5ADDR) "\0"
+ "eth5addr=" __stringify(CONFIG_ETH5ADDR) "\0"
#endif
#ifdef CONFIG_ETHPRIME
"ethprime=" CONFIG_ETHPRIME "\0"
#endif
#ifdef CONFIG_IPADDR
- "ipaddr=" MK_STR(CONFIG_IPADDR) "\0"
+ "ipaddr=" __stringify(CONFIG_IPADDR) "\0"
#endif
#ifdef CONFIG_SERVERIP
- "serverip=" MK_STR(CONFIG_SERVERIP) "\0"
+ "serverip=" __stringify(CONFIG_SERVERIP) "\0"
#endif
#ifdef CONFIG_SYS_AUTOLOAD
"autoload=" CONFIG_SYS_AUTOLOAD "\0"
"rootpath=" CONFIG_ROOTPATH "\0"
#endif
#ifdef CONFIG_GATEWAYIP
- "gatewayip=" MK_STR(CONFIG_GATEWAYIP) "\0"
+ "gatewayip=" __stringify(CONFIG_GATEWAYIP) "\0"
#endif
#ifdef CONFIG_NETMASK
- "netmask=" MK_STR(CONFIG_NETMASK) "\0"
+ "netmask=" __stringify(CONFIG_NETMASK) "\0"
#endif
#ifdef CONFIG_HOSTNAME
- "hostname=" MK_STR(CONFIG_HOSTNAME) "\0"
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0"
#endif
#ifdef CONFIG_BOOTFILE
"bootfile=" CONFIG_BOOTFILE "\0"
#endif
#ifdef CONFIG_LOADADDR
- "loadaddr=" MK_STR(CONFIG_LOADADDR) "\0"
+ "loadaddr=" __stringify(CONFIG_LOADADDR) "\0"
#endif
#ifdef CONFIG_CLOCKS_IN_MHZ
"clocks_in_mhz=1\0"
#endif
#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
- "pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY) "\0"
+ "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0"
#endif
#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG
"arch=" CONFIG_SYS_ARCH "\0"
nvars, vars, 1 /* do_apply */);
}
+#ifndef CONFIG_SPL_BUILD
/*
* Check if CRC is valid and (if yes) import the environment.
* Note that "buf" may or may not be aligned.
return 0;
}
+#endif
void env_relocate(void)
{
env_reloc();
#endif
if (gd->env_valid == 0) {
-#if defined(CONFIG_ENV_IS_NOWHERE) /* Environment not changable */
+#if defined(CONFIG_ENV_IS_NOWHERE) || defined(CONFIG_SPL_BUILD)
+ /* Environment not changable */
set_default_env(NULL);
#else
bootstage_error(BOOTSTAGE_ID_NET_CHECKSUM);
}
}
-#ifdef CONFIG_AUTO_COMPLETE
+#if defined(CONFIG_AUTO_COMPLETE) && !defined(CONFIG_SPL_BUILD)
int env_complete(char *var, int maxv, char *cmdv[], int bufsz, char *buf)
{
ENTRY *match;
#include <config.h>
#undef __ASSEMBLY__
#include <environment.h>
+#include <linux/stringify.h>
/* Handle HOSTS that have prepended crap on symbol names, not TARGETS. */
#if defined(__APPLE__)
GEN_SET_VALUE(name, value)
/*
- * Macros to transform values
- * into environment strings.
- */
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
-/*
* Check to see if we are building with a
* computed CRC. Otherwise define it as ~0.
*/
"nfsboot=" CONFIG_NFSBOOTCOMMAND "\0"
#endif
#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
- "bootdelay=" MK_STR(CONFIG_BOOTDELAY) "\0"
+ "bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0"
#endif
#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
- "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0"
+ "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"
#endif
#ifdef CONFIG_LOADS_ECHO
- "loads_echo=" MK_STR(CONFIG_LOADS_ECHO) "\0"
+ "loads_echo=" __stringify(CONFIG_LOADS_ECHO) "\0"
#endif
#ifdef CONFIG_ETHADDR
- "ethaddr=" MK_STR(CONFIG_ETHADDR) "\0"
+ "ethaddr=" __stringify(CONFIG_ETHADDR) "\0"
#endif
#ifdef CONFIG_ETH1ADDR
- "eth1addr=" MK_STR(CONFIG_ETH1ADDR) "\0"
+ "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"
#endif
#ifdef CONFIG_ETH2ADDR
- "eth2addr=" MK_STR(CONFIG_ETH2ADDR) "\0"
+ "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"
#endif
#ifdef CONFIG_ETH3ADDR
- "eth3addr=" MK_STR(CONFIG_ETH3ADDR) "\0"
+ "eth3addr=" __stringify(CONFIG_ETH3ADDR) "\0"
#endif
#ifdef CONFIG_ETH4ADDR
- "eth4addr=" MK_STR(CONFIG_ETH4ADDR) "\0"
+ "eth4addr=" __stringify(CONFIG_ETH4ADDR) "\0"
#endif
#ifdef CONFIG_ETH5ADDR
- "eth5addr=" MK_STR(CONFIG_ETH5ADDR) "\0"
+ "eth5addr=" __stringify(CONFIG_ETH5ADDR) "\0"
#endif
#ifdef CONFIG_ETHPRIME
"ethprime=" CONFIG_ETHPRIME "\0"
#endif
#ifdef CONFIG_IPADDR
- "ipaddr=" MK_STR(CONFIG_IPADDR) "\0"
+ "ipaddr=" __stringify(CONFIG_IPADDR) "\0"
#endif
#ifdef CONFIG_SERVERIP
- "serverip=" MK_STR(CONFIG_SERVERIP) "\0"
+ "serverip=" __stringify(CONFIG_SERVERIP) "\0"
#endif
#ifdef CONFIG_SYS_AUTOLOAD
"autoload=" CONFIG_SYS_AUTOLOAD "\0"
"rootpath=" CONFIG_ROOTPATH "\0"
#endif
#ifdef CONFIG_GATEWAYIP
- "gatewayip=" MK_STR(CONFIG_GATEWAYIP) "\0"
+ "gatewayip=" __stringify(CONFIG_GATEWAYIP) "\0"
#endif
#ifdef CONFIG_NETMASK
- "netmask=" MK_STR(CONFIG_NETMASK) "\0"
+ "netmask=" __stringify(CONFIG_NETMASK) "\0"
#endif
#ifdef CONFIG_HOSTNAME
- "hostname=" MK_STR(CONFIG_HOSTNAME) "\0"
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0"
#endif
#ifdef CONFIG_BOOTFILE
"bootfile=" CONFIG_BOOTFILE "\0"
#endif
#ifdef CONFIG_LOADADDR
- "loadaddr=" MK_STR(CONFIG_LOADADDR) "\0"
+ "loadaddr=" __stringify(CONFIG_LOADADDR) "\0"
#endif
#ifdef CONFIG_PREBOOT
"preboot=" CONFIG_PREBOOT "\0"
"clocks_in_mhz=" "1" "\0"
#endif
#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
- "pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY) "\0"
+ "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0"
#endif
#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG
"arch=" CONFIG_SYS_ARCH "\0"
#ifdef CONFIG_OF_STDOUT_VIA_ALIAS
-#ifdef CONFIG_SERIAL_MULTI
+#ifdef CONFIG_CONS_INDEX
static void fdt_fill_multisername(char *sername, size_t maxlen)
{
const char *outname = stdio_devices[stdout]->name;
if (strcmp(outname + 1, "serial") > 0)
strncpy(sername, outname + 1, maxlen);
}
-#else
-static inline void fdt_fill_multisername(char *sername, size_t maxlen) {}
-#endif /* CONFIG_SERIAL_MULTI */
+#endif
static int fdt_fixup_stdout(void *fdt, int chosenoff)
{
*/
if (console_assign(console, start[j]) < 0)
continue;
-#ifdef CONFIG_SERIAL_MULTI
/*
* This was taken from common/cmd_nvedit.c.
* This will never work because serial_assign() returns
*/
if (serial_assign(start[j]) < 0)
continue;
-#endif
cons_set[cs_idx++] = dev;
}
free(console_args);
#ifdef CONFIG_MENUPROMPT
printf(CONFIG_MENUPROMPT);
#else
- printf("Hit any key to stop autoboot: %2d ", bootdelay);
+ if (bootdelay >= 0)
+ printf("Hit any key to stop autoboot: %2d ", bootdelay);
#endif
#if defined CONFIG_ZERO_BOOTDELAY_CHECK
debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
- if (bootdelay >= 0 && s && !abortboot (bootdelay)) {
+ if (bootdelay != -1 && s && !abortboot(bootdelay)) {
# ifdef CONFIG_AUTOBOOT_KEYED
int prev = disable_ctrlc(1); /* disable Control C checking */
# endif
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <serial.h>
-#include <stdio_dev.h>
-#include <post.h>
-#include <linux/compiler.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct serial_device *serial_devices;
-static struct serial_device *serial_current;
-
-void serial_register(struct serial_device *dev)
-{
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- dev->init += gd->reloc_off;
- dev->setbrg += gd->reloc_off;
- dev->getc += gd->reloc_off;
- dev->tstc += gd->reloc_off;
- dev->putc += gd->reloc_off;
- dev->puts += gd->reloc_off;
-#endif
-
- dev->next = serial_devices;
- serial_devices = dev;
-}
-
-void serial_initialize(void)
-{
-#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
- serial_register(&serial_smc_device);
-#endif
-#if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
- defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
- serial_register(&serial_scc_device);
-#endif
-
-#if defined(CONFIG_SYS_NS16550_SERIAL)
-#if defined(CONFIG_SYS_NS16550_COM1)
- serial_register(&eserial1_device);
-#endif
-#if defined(CONFIG_SYS_NS16550_COM2)
- serial_register(&eserial2_device);
-#endif
-#if defined(CONFIG_SYS_NS16550_COM3)
- serial_register(&eserial3_device);
-#endif
-#if defined(CONFIG_SYS_NS16550_COM4)
- serial_register(&eserial4_device);
-#endif
-#endif /* CONFIG_SYS_NS16550_SERIAL */
-#if defined(CONFIG_FFUART)
- serial_register(&serial_ffuart_device);
-#endif
-#if defined(CONFIG_BTUART)
- serial_register(&serial_btuart_device);
-#endif
-#if defined(CONFIG_STUART)
- serial_register(&serial_stuart_device);
-#endif
-#if defined(CONFIG_S3C2410)
- serial_register(&s3c24xx_serial0_device);
- serial_register(&s3c24xx_serial1_device);
- serial_register(&s3c24xx_serial2_device);
-#endif
-#if defined(CONFIG_S5P)
- serial_register(&s5p_serial0_device);
- serial_register(&s5p_serial1_device);
- serial_register(&s5p_serial2_device);
- serial_register(&s5p_serial3_device);
-#endif
-#if defined(CONFIG_MPC512X)
-#if defined(CONFIG_SYS_PSC1)
- serial_register(&serial1_device);
-#endif
-#if defined(CONFIG_SYS_PSC3)
- serial_register(&serial3_device);
-#endif
-#if defined(CONFIG_SYS_PSC4)
- serial_register(&serial4_device);
-#endif
-#if defined(CONFIG_SYS_PSC6)
- serial_register(&serial6_device);
-#endif
-#endif
-#if defined(CONFIG_SYS_BFIN_UART)
- serial_register_bfin_uart();
-#endif
-#if defined(CONFIG_XILINX_UARTLITE)
-# ifdef XILINX_UARTLITE_BASEADDR
- serial_register(&uartlite_serial0_device);
-# endif /* XILINX_UARTLITE_BASEADDR */
-# ifdef XILINX_UARTLITE_BASEADDR1
- serial_register(&uartlite_serial1_device);
-# endif /* XILINX_UARTLITE_BASEADDR1 */
-# ifdef XILINX_UARTLITE_BASEADDR2
- serial_register(&uartlite_serial2_device);
-# endif /* XILINX_UARTLITE_BASEADDR2 */
-# ifdef XILINX_UARTLITE_BASEADDR3
- serial_register(&uartlite_serial3_device);
-# endif /* XILINX_UARTLITE_BASEADDR3 */
-#endif /* CONFIG_XILINX_UARTLITE */
- serial_assign(default_serial_console()->name);
-}
-
-void serial_stdio_init(void)
-{
- struct stdio_dev dev;
- struct serial_device *s = serial_devices;
-
- while (s) {
- memset(&dev, 0, sizeof(dev));
-
- strcpy(dev.name, s->name);
- dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
-
- dev.start = s->init;
- dev.stop = s->uninit;
- dev.putc = s->putc;
- dev.puts = s->puts;
- dev.getc = s->getc;
- dev.tstc = s->tstc;
-
- stdio_register(&dev);
-
- s = s->next;
- }
-}
-
-int serial_assign(const char *name)
-{
- struct serial_device *s;
-
- for (s = serial_devices; s; s = s->next) {
- if (strcmp(s->name, name) == 0) {
- serial_current = s;
- return 0;
- }
- }
-
- return 1;
-}
-
-void serial_reinit_all(void)
-{
- struct serial_device *s;
-
- for (s = serial_devices; s; s = s->next)
- s->init();
-}
-
-static struct serial_device *get_current(void)
-{
- struct serial_device *dev;
-
- if (!(gd->flags & GD_FLG_RELOC) || !serial_current) {
- dev = default_serial_console();
-
- /* We must have a console device */
- if (!dev)
- panic("Cannot find console");
- } else
- dev = serial_current;
- return dev;
-}
-
-int serial_init(void)
-{
- return get_current()->init();
-}
-
-void serial_setbrg(void)
-{
- get_current()->setbrg();
-}
-
-int serial_getc(void)
-{
- return get_current()->getc();
-}
-
-int serial_tstc(void)
-{
- return get_current()->tstc();
-}
-
-void serial_putc(const char c)
-{
- get_current()->putc(c);
-}
-
-void serial_puts(const char *s)
-{
- get_current()->puts(s);
-}
-
-#if CONFIG_POST & CONFIG_SYS_POST_UART
-static const int bauds[] = CONFIG_SYS_BAUDRATE_TABLE;
-
-/* Mark weak until post/cpu/.../uart.c migrate over */
-__weak
-int uart_post_test(int flags)
-{
- unsigned char c;
- int ret, saved_baud, b;
- struct serial_device *saved_dev, *s;
- bd_t *bd = gd->bd;
-
- /* Save current serial state */
- ret = 0;
- saved_dev = serial_current;
- saved_baud = bd->bi_baudrate;
-
- for (s = serial_devices; s; s = s->next) {
- /* If this driver doesn't support loop back, skip it */
- if (!s->loop)
- continue;
-
- /* Test the next device */
- serial_current = s;
-
- ret = serial_init();
- if (ret)
- goto done;
-
- /* Consume anything that happens to be queued */
- while (serial_tstc())
- serial_getc();
-
- /* Enable loop back */
- s->loop(1);
-
- /* Test every available baud rate */
- for (b = 0; b < ARRAY_SIZE(bauds); ++b) {
- bd->bi_baudrate = bauds[b];
- serial_setbrg();
-
- /*
- * Stick to printable chars to avoid issues:
- * - terminal corruption
- * - serial program reacting to sequences and sending
- * back random extra data
- * - most serial drivers add in extra chars (like \r\n)
- */
- for (c = 0x20; c < 0x7f; ++c) {
- /* Send it out */
- serial_putc(c);
-
- /* Make sure it's the same one */
- ret = (c != serial_getc());
- if (ret) {
- s->loop(0);
- goto done;
- }
-
- /* Clean up the output in case it was sent */
- serial_putc('\b');
- ret = ('\b' != serial_getc());
- if (ret) {
- s->loop(0);
- goto done;
- }
- }
- }
-
- /* Disable loop back */
- s->loop(0);
-
- /* XXX: There is no serial_uninit() !? */
- if (s->uninit)
- s->uninit();
- }
-
- done:
- /* Restore previous serial state */
- serial_current = saved_dev;
- bd->bi_baudrate = saved_baud;
- serial_reinit_all();
- serial_setbrg();
-
- return ret;
-}
-#endif
COBJS-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o
COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o
COBJS-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o
+COBJS-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o
endif
COBJS := $(sort $(COBJS-y))
CONFIG_SYS_SPL_MALLOC_SIZE);
#endif
+ timer_init();
+
#ifdef CONFIG_SPL_BOARD_INIT
spl_board_init();
#endif
spl_spi_load_image();
break;
#endif
+#ifdef CONFIG_SPL_ETH_SUPPORT
+ case BOOT_DEVICE_CPGMAC:
+#ifdef CONFIG_SPL_ETH_DEVICE
+ spl_net_load_image(CONFIG_SPL_ETH_DEVICE);
+#else
+ spl_net_load_image(NULL);
+#endif
+ break;
+#endif
default:
debug("SPL: Un-supported Boot Device\n");
hang();
void preloader_console_init(void)
{
gd->bd = &bdata;
- gd->flags |= GD_FLG_RELOC;
gd->baudrate = CONFIG_BAUDRATE;
serial_init(); /* serial communications setup */
--- /dev/null
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2012
+ * Ilya Yanok <ilya.yanok@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#include <common.h>
+#include <spl.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_net_load_image(const char *device)
+{
+ int rv;
+
+ env_init();
+ env_relocate();
+ setenv("autoload", "yes");
+ load_addr = CONFIG_SYS_TEXT_BASE - sizeof(struct image_header);
+ rv = eth_initialize(gd->bd);
+ if (rv == 0) {
+ printf("No Ethernet devices found\n");
+ hang();
+ }
+ if (device)
+ setenv("ethact", device);
+ rv = NetLoop(BOOTP);
+ if (rv < 0) {
+ printf("Problem booting with BOOTP\n");
+ hang();
+ }
+ spl_parse_image_header((struct image_header *)load_addr);
+}
drv_logbuff_init ();
#endif
drv_system_init ();
-#ifdef CONFIG_SERIAL_MULTI
serial_stdio_init ();
-#endif
#ifdef CONFIG_USB_TTY
drv_usbtty_init ();
#endif
static struct usb_device usb_dev[USB_MAX_DEVICE];
static int dev_index;
-static int running;
static int asynch_allowed;
char usb_started; /* flag for the started/stopped USB status */
-/**********************************************************************
- * some forward declerations...
- */
-static void usb_scan_devices(void);
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
/***************************************************************************
* Init USB Device
*/
-
int usb_init(void)
{
- int result;
+ void *ctrl;
+ struct usb_device *dev;
+ int i, start_index = 0;
- running = 0;
dev_index = 0;
asynch_allowed = 1;
usb_hub_reset();
+
+ /* first make all devices unknown */
+ for (i = 0; i < USB_MAX_DEVICE; i++) {
+ memset(&usb_dev[i], 0, sizeof(struct usb_device));
+ usb_dev[i].devnum = -1;
+ }
+
/* init low_level USB */
- printf("USB: ");
- result = usb_lowlevel_init();
- /* if lowlevel init is OK, scan the bus for devices
- * i.e. search HUBs and configure them */
- if (result == 0) {
- printf("scanning bus for devices... ");
- running = 1;
- usb_scan_devices();
+ for (i = 0; i < CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
+ /* init low_level USB */
+ printf("USB%d: ", i);
+ if (usb_lowlevel_init(i, &ctrl)) {
+ puts("lowlevel init failed\n");
+ continue;
+ }
+ /*
+ * lowlevel init is OK, now scan the bus for devices
+ * i.e. search HUBs and configure them
+ */
+ start_index = dev_index;
+ printf("scanning bus %d for devices... ", i);
+ dev = usb_alloc_new_device(ctrl);
+ /*
+ * device 0 is always present
+ * (root hub, so let it analyze)
+ */
+ if (dev)
+ usb_new_device(dev);
+
+ if (start_index == dev_index)
+ puts("No USB Device found\n");
+ else
+ printf("%d USB Device(s) found\n",
+ dev_index - start_index);
+
usb_started = 1;
- return 0;
- } else {
- printf("Error, couldn't init Lowlevel part\n");
- usb_started = 0;
+ }
+
+ USB_PRINTF("scan end\n");
+ /* if we were not able to find at least one working bus, bail out */
+ if (!usb_started) {
+ puts("USB error: all controllers failed lowlevel init\n");
return -1;
}
+
+ return 0;
}
/******************************************************************************
*/
int usb_stop(void)
{
- int res = 0;
+ int i;
if (usb_started) {
asynch_allowed = 1;
usb_started = 0;
usb_hub_reset();
- res = usb_lowlevel_stop();
+
+ for (i = 0; i < CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
+ if (usb_lowlevel_stop(i))
+ printf("failed to stop USB controller %d\n", i);
+ }
}
- return res;
+
+ return 0;
}
/*
return &usb_dev[index];
}
-
/* returns a pointer of a new device structure or NULL, if
* no device struct is available
*/
-struct usb_device *usb_alloc_new_device(void)
+struct usb_device *usb_alloc_new_device(void *controller)
{
int i;
USB_PRINTF("New Device %d\n", dev_index);
for (i = 0; i < USB_MAXCHILDREN; i++)
usb_dev[dev_index].children[i] = NULL;
usb_dev[dev_index].parent = NULL;
+ usb_dev[dev_index].controller = controller;
dev_index++;
return &usb_dev[dev_index - 1];
}
return 0;
}
-/* build device Tree */
-static void usb_scan_devices(void)
-{
- int i;
- struct usb_device *dev;
-
- /* first make all devices unknown */
- for (i = 0; i < USB_MAX_DEVICE; i++) {
- memset(&usb_dev[i], 0, sizeof(struct usb_device));
- usb_dev[i].devnum = -1;
- }
- dev_index = 0;
- /* device 0 is always present (root hub, so let it analyze) */
- dev = usb_alloc_new_device();
- if (usb_new_device(dev))
- printf("No USB Device found\n");
- else
- printf("%d USB Device(s) found\n", dev_index);
- /* insert "driver" if possible */
-#ifdef CONFIG_USB_KEYBOARD
- drv_usb_kbd_init();
-#endif
- USB_PRINTF("scan end\n");
-}
-
/* EOF */
mdelay(200);
/* Allocate a new device struct for it */
- usb = usb_alloc_new_device();
+ usb = usb_alloc_new_device(dev->controller);
if (portstatus & USB_PORT_STAT_HIGH_SPEED)
usb->speed = USB_SPEED_HIGH;
struct usb_device *dev;
if (mode == 1)
- printf(" scanning bus for storage devices... ");
+ printf(" scanning usb for storage devices... ");
usb_disable_asynch(1); /* asynch transfer not allowed */
# cc-version
# Usage gcc-ver := $(call cc-version)
cc-version = $(shell $(SHELL) $(SRCTREE)/tools/gcc-version.sh $(CC))
+binutils-version = $(shell $(SHELL) $(SRCTREE)/tools/binutils-version.sh $(AS))
#
# Include the make variables (CC, etc...)
OBJDUMP = $(CROSS_COMPILE)objdump
RANLIB = $(CROSS_COMPILE)RANLIB
DTC = dtc
+CHECK = sparse
#########################################################################
LDFLAGS_u-boot-spl += -Ttext $(CONFIG_SPL_TEXT_BASE)
endif
+# Linus' kernel sanity checking tool
+CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
+ -Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF)
+
# Location of a usable BFD library, where we define "usable" as
# "built for ${HOST}, supports ${TARGET}". Sensible values are
# - When cross-compiling: the root of the cross-environment
$(obj)%.o: %.S
$(CC) $(ALL_AFLAGS) -o $@ $< -c
$(obj)%.o: %.c
+ifneq ($(CHECKSRC),0)
+ $(CHECK) $(CHECKFLAGS) $(ALL_CFLAGS) $<
+endif
$(CC) $(ALL_CFLAGS) -o $@ $< -c
$(obj)%.i: %.c
$(CPP) $(ALL_CFLAGS) -o $@ $< -c
{
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
- if ((dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *) buffer) != 1) ||
- (buffer[DOS_PART_MAGIC_OFFSET + 0] != 0x55) ||
- (buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) ) {
- return (-1);
- }
- return (0);
+ if (dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *) buffer) != 1)
+ return -1;
+
+ if (test_block_type(buffer) != DOS_MBR)
+ return -1;
+
+ return 0;
}
/* Print a partition that is relative to its Extended partition table
return;
}
i=test_block_type(buffer);
- if(i==-1) {
+ if (i != DOS_MBR) {
printf ("bad MBR sector signature 0x%02x%02x\n",
buffer[DOS_PART_MAGIC_OFFSET],
buffer[DOS_PART_MAGIC_OFFSET + 1]);
return;
}
- if(i==DOS_PBR) {
- printf (" 1\t\t 0\t%10ld\t%2x\n",
- dev_desc->lba, buffer[DOS_PBR_MEDIA_TYPE_OFFSET]);
- return;
- }
+
/* Print all primary/logical partitions */
pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET);
for (i = 0; i < 4; i++, pt++) {
--- /dev/null
+*/
+*.xml
+*.ps
+*.pdf
+*.html
+*.9.gz
+*.9
+*.aux
+*.dvi
+*.log
+*.out
+*.png
+*.gif
+media-indices.tmpl
+media-entities.tmpl
--- /dev/null
+###
+# This makefile is used to generate the kernel documentation,
+# primarily based on in-line comments in various source files.
+# See doc/kernel-doc-nano-HOWTO.txt for instruction in how
+# to document the SRC - and how to read it.
+# To add a new book the only step required is to add the book to the
+# list of DOCBOOKS.
+
+include $(TOPDIR)/config.mk
+
+DOCBOOKS :=
+
+###
+# The build process is as follows (targets):
+# (xmldocs) [by docproc]
+# file.tmpl --> file.xml +--> file.ps (psdocs) [by db2ps or xmlto]
+# +--> file.pdf (pdfdocs) [by db2pdf or xmlto]
+# +--> DIR=file (htmldocs) [by xmlto]
+# +--> man/ (mandocs) [by xmlto]
+
+
+# for PDF and PS output you can choose between xmlto and docbook-utils tools
+PDF_METHOD = $(prefer-db2x)
+PS_METHOD = $(prefer-db2x)
+
+
+###
+# The targets that may be used.
+PHONY += $(obj).depend xmldocs sgmldocs psdocs pdfdocs htmldocs mandocs installmandocs cleandocs
+
+BOOKS := $(addprefix $(OBJTREE)/doc/DocBook/,$(DOCBOOKS))
+xmldocs: $(BOOKS)
+sgmldocs: xmldocs
+
+PS := $(patsubst %.xml, %.ps, $(BOOKS))
+psdocs: $(PS)
+
+PDF := $(patsubst %.xml, %.pdf, $(BOOKS))
+pdfdocs: $(PDF)
+
+HTML := $(sort $(patsubst %.xml, %.html, $(BOOKS)))
+htmldocs: $(HTML)
+ $(call build_main_index)
+ $(call build_images)
+ $(call install_media_images)
+
+MAN := $(patsubst %.xml, %.9, $(BOOKS))
+mandocs: $(MAN)
+
+installmandocs: mandocs
+ mkdir -p /usr/local/man/man9/
+ install doc/DocBook/man/*.9.gz /usr/local/man/man9/
+
+###
+#External programs used
+KERNELDOC = $(SRCTREE)/tools/kernel-doc/kernel-doc
+DOCPROC = $(OBJTREE)/tools/kernel-doc/docproc
+
+XMLTOFLAGS = -m $(SRCTREE)/doc/DocBook/stylesheet.xsl
+XMLTOFLAGS += --skip-validation
+
+###
+# DOCPROC is used for two purposes:
+# 1) To generate a dependency list for a .tmpl file
+# 2) To preprocess a .tmpl file and call kernel-doc with
+# appropriate parameters.
+# The following rules are used to generate the .xml documentation
+# required to generate the final targets. (ps, pdf, html).
+%.xml: %.tmpl
+ $(DOCPROC) doc $< >$@
+
+ifeq ($@, "cleandocs")
+sinclude $(obj).depend
+$(obj).depend: $(patsubst %.xml, %.tmpl, $(DOCBOOKS))
+ rm -f $(obj).depend ; \
+ touch $(obj).depend ; \
+ for file in $^ ; do \
+ xmlfile=`echo "$${file}" | \
+ sed "s/tmpl$$/xml/"` ; \
+ echo -n "$${xmlfile}: ">> $(obj).depend ; \
+ $(DOCPROC) depend $$file >> $(obj).depend ; \
+ echo -e "\n\t$(DOCPROC) doc $< >$${xmlfile} " >> \
+ $(obj).depend ; \
+ done
+endif
+
+###
+# Changes in kernel-doc force a rebuild of all documentation
+$(BOOKS): $(KERNELDOC)
+
+notfoundtemplate = echo "*** You have to install docbook-utils or xmlto ***"; \
+ exit 1
+db2xtemplate = db2TYPE -o $(dir $@) $<
+xmltotemplate = xmlto TYPE $(XMLTOFLAGS) -o $(dir $@) $<
+
+# determine which methods are available
+ifeq ($(shell which db2ps >/dev/null 2>&1 && echo found),found)
+ use-db2x = db2x
+ prefer-db2x = db2x
+else
+ use-db2x = notfound
+ prefer-db2x = $(use-xmlto)
+endif
+ifeq ($(shell which xmlto >/dev/null 2>&1 && echo found),found)
+ use-xmlto = xmlto
+ prefer-xmlto = xmlto
+else
+ use-xmlto = notfound
+ prefer-xmlto = $(use-db2x)
+endif
+
+# the commands, generated from the chosen template
+quiet_cmd_db2ps = PS $@
+ cmd_db2ps = $(subst TYPE,ps, $($(PS_METHOD)template))
+%.ps : %.xml
+ $(call cmd_db2ps)
+
+quiet_cmd_db2pdf = PDF $@
+ cmd_db2pdf = $(subst TYPE,pdf, $($(PDF_METHOD)template))
+%.pdf : %.xml
+ $(call cmd_db2pdf)
+
+
+index = index.html
+main_idx = $(index)
+build_main_index = rm -rf $(main_idx); \
+ echo '<h1>U-Boot Bootloader HTML Documentation</h1>' >> $(main_idx) && \
+ echo '<h2>U-Boot Version: $(U_BOOT_VERSION)</h2>' >> $(main_idx) && \
+ cat $(HTML) >> $(main_idx)
+
+# To work around bug [1] in docbook-xsl-stylesheets 1.76.1 , generate only html
+# docs instead of xhtml with xmlto.
+# [1] http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=654338
+quiet_cmd_db2html = HTML $@
+ cmd_db2html = xmlto html $(XMLTOFLAGS) -o $(patsubst %.html,%,$@) $< && \
+ echo '<a HREF="$(patsubst %.html,%,$(notdir $@))/index.html"> \
+ $(patsubst %.html,%,$(notdir $@))</a><p>' > $@
+
+%.html: %.xml
+ @(which xmlto > /dev/null 2>&1) || \
+ (echo "*** You need to install xmlto ***"; \
+ exit 1)
+ @rm -rf $@ $(patsubst %.html,%,$@)
+ $(call cmd_db2html)
+ @if [ ! -z "$(PNG-$(basename $(notdir $@)))" ]; then \
+ cp $(PNG-$(basename $(notdir $@))) $(patsubst %.html,%,$@); fi
+
+quiet_cmd_db2man = MAN $@
+ cmd_db2man = if grep -q refentry $<; then xmlto man $(XMLTOFLAGS) -o $(obj)/man $< ; gzip -f $(obj)/man/*.9; fi
+%.9 : %.xml
+ @(which xmlto > /dev/null 2>&1) || \
+ (echo "*** You need to install xmlto ***"; \
+ exit 1)
+ $(Q)mkdir -p $(obj)man
+ $(call cmd_db2man)
+ @touch $@
+
+###
+# Rules to generate postscripts and PNG images from .fig format files
+quiet_cmd_fig2eps = FIG2EPS $@
+ cmd_fig2eps = fig2dev -Leps $< $@
+
+%.eps: %.fig
+ @(which fig2dev > /dev/null 2>&1) || \
+ (echo "*** You need to install transfig ***"; \
+ exit 1)
+ $(call cmd_fig2eps)
+
+quiet_cmd_fig2png = FIG2PNG $@
+ cmd_fig2png = fig2dev -Lpng $< $@
+
+%.png: %.fig
+ @(which fig2dev > /dev/null 2>&1) || \
+ (echo "*** You need to install transfig ***"; \
+ exit 1)
+ $(call cmd_fig2png)
+
+###
+# Rule to convert a .c file to inline XML documentation
+ gen_xml = :
+ quiet_gen_xml = echo ' GEN $@'
+silent_gen_xml = :
+%.xml: %.c
+ @$($(quiet)gen_xml)
+ @( \
+ echo "<programlisting>"; \
+ expand --tabs=8 < $< | \
+ sed -e "s/&/\\&/g" \
+ -e "s/</\\</g" \
+ -e "s/>/\\>/g"; \
+ echo "</programlisting>") > $@
+
+###
+# Help targets as used by the top-level makefile
+dochelp:
+ @echo ' U-Boot bootloader internal documentation in different formats:'
+ @echo ' htmldocs - HTML'
+ @echo ' pdfdocs - PDF'
+ @echo ' psdocs - Postscript'
+ @echo ' xmldocs - XML DocBook'
+ @echo ' mandocs - man pages'
+ @echo ' installmandocs - install man pages generated by mandocs'
+ @echo ' cleandocs - clean all generated DocBook files'
+
+###
+# Temporary files left by various tools
+clean-files := $(DOCBOOKS) \
+ $(patsubst %.xml, %.dvi, $(DOCBOOKS)) \
+ $(patsubst %.xml, %.aux, $(DOCBOOKS)) \
+ $(patsubst %.xml, %.tex, $(DOCBOOKS)) \
+ $(patsubst %.xml, %.log, $(DOCBOOKS)) \
+ $(patsubst %.xml, %.out, $(DOCBOOKS)) \
+ $(patsubst %.xml, %.ps, $(DOCBOOKS)) \
+ $(patsubst %.xml, %.pdf, $(DOCBOOKS)) \
+ $(patsubst %.xml, %.html, $(DOCBOOKS)) \
+ $(patsubst %.xml, %.9, $(DOCBOOKS)) \
+ $(index)
+
+clean-dirs := $(patsubst %.xml,%,$(DOCBOOKS)) man
+
+cleandocs:
+ @rm -f $(obj).depend
+ @$(Q)rm -f $(call objectify, $(clean-files))
+ @$(Q)rm -rf $(call objectify, $(clean-dirs))
+
+# Declare the contents of the .PHONY variable as phony. We keep that
+# information in a variable se we can use it in if_changed and friends.
+
+.PHONY: $(PHONY)
--- /dev/null
+body {
+ font-family: sans-serif;
+}
+
+.programlisting {
+ font-family: monospace;
+ font-size: 1em;
+ display: block;
+ padding: 10px;
+ border: 1px solid #aaa;
+ color: #000;
+ background-color: #eee;
+ overflow: auto;
+ margin: 1em 0em;
+ border-radius: 6px;
+}
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<stylesheet xmlns="http://www.w3.org/1999/XSL/Transform" version="1.0">
+<param name="chunk.quietly">1</param>
+<param name="funcsynopsis.style">ansi</param>
+<param name="funcsynopsis.tabular.threshold">80</param>
+<param name="callout.graphics">0</param>
+<!-- <param name="paper.type">A4</param> -->
+<param name="generate.section.toc.level">2</param>
+<param name="use.id.as.filename">1</param>
+<param name="html.stylesheet">../docbook.css</param>
+</stylesheet>
--- /dev/null
+If you are reading this because of a data abort: the following MIGHT
+be relevant to your abort, if it was caused by an alignment violation.
+In order to determine this, use the PC from the abort dump along with
+an objdump -s -S of the u-boot ELF binary to locate the function where
+the abort happened; then compare this function with the examples below.
+If they match, then you've been hit with a compiler generated unaligned
+access, and you should rewrite your code or add -mno-unaligned-access
+to the command line of the offending file.
+
+Note that the PC shown in the abort message is relocated. In order to
+be able to match it to an address in the ELF binary dump, you will need
+to know the relocation offset. If your target defines CONFIG_CMD_BDI
+and if you can get to the prompt and enter commands before the abort
+happens, then command "bdinfo" will give you the offset. Otherwise you
+will need to try a build with DEBUG set, which will display the offset,
+or use a debugger and set a breakpoint at relocate_code() to see the
+offset (passed as an argument).
+
+*
+
+Since U-Boot runs on a variety of hardware, some only able to perform
+unaligned accesses with a strong penalty, some unable to perform them
+at all, the policy regarding unaligned accesses is to not perform any,
+unless absolutely necessary because of hardware or standards.
+
+Also, on hardware which permits it, the core is configured to throw
+data abort exceptions on unaligned accesses in order to catch these
+unallowed accesses as early as possible.
+
+Until version 4.7, the gcc default for performing unaligned accesses
+(-mno-unaligned-access) is to emulate unaligned accesses using aligned
+loads and stores plus shifts and masks. Emulated unaligned accesses
+will not be caught by hardware. These accesses may be costly and may
+be actually unnecessary. In order to catch these accesses and remove
+or optimize them, option -munaligned-access is explicitly set for all
+versions of gcc which support it.
+
+From gcc 4.7 onward starting at armv7 architectures, the default for
+performing unaligned accesses is to use unaligned native loads and
+stores (-munaligned-access), because the cost of unaligned accesses
+has dropped on armv7 and beyond. This should not affect U-Boot's
+policy of controlling unaligned accesses, however the compiler may
+generate uncontrolled unaligned accesses on its own in at least one
+known case: when declaring a local initialized char array, e.g.
+
+function foo()
+{
+ char buffer[] = "initial value";
+/* or */
+ char buffer[] = { 'i', 'n', 'i', 't', 0 };
+ ...
+}
+
+Under -munaligned-accesses with optimizations on, this declaration
+causes the compiler to generate native loads from the literal string
+and native stores to the buffer, and the literal string alignment
+cannot be controlled. If it is misaligned, then the core will throw
+a data abort exception.
+
+Quite probably the same might happen for 16-bit array initializations
+where the constant is aligned on a boundary which is a multiple of 2
+but not of 4:
+
+function foo()
+{
+ u16 buffer[] = { 1, 2, 3 };
+ ...
+}
+
+The long term solution to this issue is to add an option to gcc to
+allow controlling the general alignment of data, including constant
+initialization values.
+
+However this will only apply to the version of gcc which will have such
+an option. For other versions, there are four workarounds:
+
+a) Enforce as a rule that array initializations as described above
+ are forbidden. This is generally not acceptable as they are valid,
+ and usual, C constructs. The only case where they could be rejected
+ is when they actually equate to a const char* declaration, i.e. the
+ array is initialized and never modified in the function's scope.
+
+b) Drop the requirement on unaligned accesses at least for ARMv7,
+ i.e. do not throw a data abort exception upon unaligned accesses.
+ But that will allow adding badly aligned code to U-Boot, only for
+ it to fail when re-used with a stricter target, possibly once the
+ bad code is already in mainline.
+
+c) Relax the -munaligned-access rule globally. This will prevent native
+ unaligned accesses of course, but that will also hide any bug caused
+ by a bad unaligned access, making it much harder to diagnose it. It
+ is actually what already happens when building ARM targets with a
+ pre-4.7 gcc, and it may actually already hide some bugs yet unseen
+ until the target gets compiled with -munaligned-access.
+
+d) Relax the -munaligned-access rule only for for files susceptible to
+ the local initialized array issue and for armv7 architectures and
+ beyond. This minimizes the quantity of code which can hide unwanted
+ misaligned accesses.
+
+The option retained is d).
+
+Considering that actual occurrences of the issue are rare (as of this
+writing, 5 files out of 7840 in U-Boot, or .3%, contain an initialized
+local char array which cannot actually be replaced with a const char*),
+contributors should not be required to systematically try and detect
+the issue in their patches.
+
+Detecting files susceptible to the issue can be automated through a
+filter installed as a hook in .git which recognizes local char array
+initializations. Automation should err on the false positive side, for
+instance flagging non-local arrays as if they were local if they cannot
+be told apart.
+
+In any case, detection shall not prevent committing the patch, but
+shall pre-populate the commit message with a note to the effect that
+this patch contains an initialized local char or 16-bit array and thus
+should be protected from the gcc 4.7 issue.
+
+Upon a positive detection, either $(PLATFORM_NO_UNALIGNED) should be
+added to CFLAGS for the affected file(s), or if the array is a pseudo
+const char*, it should be replaced by an actual one.
--- /dev/null
+U-Boot for FriendlyARM Mini2440 (s3c2440)
+
+This file contains information for the port of U-Boot to FriendlyARM
+mini2440
+
+All information about the board can be found on :
+http://www.friendlyarm.net/products/mini2440
+
+To build u-boot : ./MAKEALL mini2440
+
+Overview :
+--------
+FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440
+ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9
+systems. It's a low cost board.
+
+Boot Methods :
+------------
+Mini2440 can boot from NOR or NAND.
+
+Build :
+-----
+./MAKEALL mini2440
+
+or
+
+make mini2440_config
+make
--- /dev/null
+Summary
+=======
+
+This README is about U-Boot support for Renesas's ARM Cortex-A9 based RMOBILE[1]
+family of SoCs. Renesas's RMOBILE SoC family contains an ARM Cortex-A9.
+
+Currently the following boards are supported:
+
+* KMC KZM-A9-GT [2]
+
+* Atmark-Techno Armadillo-800-EVA [3]
+
+Toolchain
+=========
+
+ARM Cortex-A9 support ARM v7 instruction set (-march=armv7a).
+But currently we compile with -march=armv5 to allow more compilers to work.
+(For U-Boot code this has no performance impact.)
+Because there was no compiler which is supporting armv7a not much before.
+Currently, ELDK[4], Linaro[5], CodeSourcey[6] and Emdebian[7] supports -march=armv7a
+and you can get.
+
+Build
+=====
+
+* KZM-A9-GT
+
+make kzm9g_config
+make
+
+* Armadillo-800-EVA
+
+make armadillo-800eva_config
+make
+
+Links
+=====
+
+[1] Renesas RMOBILE:
+
+http://am.renesas.com/products/soc/assp/mobile/r_mobile/index.jsp
+
+[2] KZM-A9-GT
+
+http://www.kmckk.co.jp/kzma9-gt/index.html
+
+[3] Armadillo-800-EVA
+
+http://armadillo.atmark-techno.com/armadillo-800-EVA
+
+[4] ELDK
+
+http://www.denx.de/wiki/view/ELDK-5/WebHome#Section_1.6.
+
+[5] Linaro
+
+http://www.linaro.org/downloads/
+
+[6] CodeSourcey
+
+http://www.mentor.com/embedded-software/codesourcery
+
+[7] Emdebian
+
+http://www.emdebian.org/crosstools.html
Board Arch CPU removed Commit last known maintainer/contact
=============================================================================
-apollon arm omap24xx - 2012-09-06 Kyungmin Park <kyungmin.park@samsung.com>
-tb0229 mips mips32 - 2011-12-12
+TQM85xx powerpc MPC85xx - - Stefan Roese <sr@denx.de>
+apollon arm omap24xx 535c74f 2012-09-18 Kyungmin Park <kyungmin.park@samsung.com>
+tb0229 mips mips32 3f3110d 2011-12-12
rmu powerpc MPC850 fb82fd7 2011-12-07 Wolfgang Denk <wd@denx.de>
OXC powerpc MPC8240 309a292 2011-12-07
BAB7xx powerpc MPC740/MPC750 c53043b 2011-12-07 Frank Gottschling <fgottschling@eltec.de>
alias kirkwood uboot, prafulla
alias omap ti
alias pxa uboot, marex
+alias rmobile uboot, iwamatsu
alias s3c samsung
alias s5pc samsung
alias samsung uboot, prom
# Subsystem aliases
alias cfi uboot, stroese
+alias kerneldoc uboot, marex
alias fdt uboot, Jerry Van Baren <vanbaren@cideas.com>
alias i2c uboot, hs
alias mmc uboot, afleming
#include <part.h>
#include <ide.h>
#include <ata.h>
+#include <sata.h>
-extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-extern int sata_curr_device;
-
-#define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */
+#define DEBUG_SATA 0 /* For debug prints set DEBUG_SATA to 1 */
#define SATA_DECL
-#define DRV_DECL /*For file specific declarations */
+#define DRV_DECL /* For file specific declarations */
#include "ata_piix.h"
-/*Macros realted to PCI*/
+/* Macros realted to PCI */
#define PCI_SATA_BUS 0x00
#define PCI_SATA_DEV 0x1f
#define PCI_SATA_FUNC 0x02
#define PORT_ENABLED (1<<4)
u32 bdf;
-u32 iobase1 = 0; /*Primary cmd block */
-u32 iobase2 = 0; /*Primary ctl block */
-u32 iobase3 = 0; /*Sec cmd block */
-u32 iobase4 = 0; /*sec ctl block */
-u32 iobase5 = 0; /*BMDMA*/
-int
-pci_sata_init (void)
+u32 iobase1; /* Primary cmd block */
+u32 iobase2; /* Primary ctl block */
+u32 iobase3; /* Sec cmd block */
+u32 iobase4; /* sec ctl block */
+u32 iobase5; /* BMDMA*/
+
+int pci_sata_init(void)
{
u32 bus = PCI_SATA_BUS;
u32 dev = PCI_SATA_DEV;
u32 fun = PCI_SATA_FUNC;
u16 cmd = 0;
u8 lat = 0, pcibios_max_latency = 0xff;
- u8 pmr; /*Port mapping reg */
- u8 pi; /*Prgming Interface reg */
+ u8 pmr; /* Port mapping reg */
+ u8 pi; /* Prgming Interface reg */
- bdf = PCI_BDF (bus, dev, fun);
- pci_read_config_dword (bdf, PCI_SATA_BASE1, &iobase1);
- pci_read_config_dword (bdf, PCI_SATA_BASE2, &iobase2);
- pci_read_config_dword (bdf, PCI_SATA_BASE3, &iobase3);
- pci_read_config_dword (bdf, PCI_SATA_BASE4, &iobase4);
- pci_read_config_dword (bdf, PCI_SATA_BASE5, &iobase5);
+ bdf = PCI_BDF(bus, dev, fun);
+ pci_read_config_dword(bdf, PCI_SATA_BASE1, &iobase1);
+ pci_read_config_dword(bdf, PCI_SATA_BASE2, &iobase2);
+ pci_read_config_dword(bdf, PCI_SATA_BASE3, &iobase3);
+ pci_read_config_dword(bdf, PCI_SATA_BASE4, &iobase4);
+ pci_read_config_dword(bdf, PCI_SATA_BASE5, &iobase5);
if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) ||
(iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) ||
(iobase5 == 0xFFFFFFFF)) {
- printf ("error no base addr for SATA controller\n");
+ /* ERROR */
+ printf("error no base addr for SATA controller\n");
return 1;
- /*ERROR*/}
+ }
iobase1 &= 0xFFFFFFFE;
iobase2 &= 0xFFFFFFFE;
iobase4 &= 0xFFFFFFFE;
iobase5 &= 0xFFFFFFFE;
- /*check for mode */
- pci_read_config_byte (bdf, PCI_PMR, &pmr);
+ /* check for mode */
+ pci_read_config_byte(bdf, PCI_PMR, &pmr);
if (pmr > 1) {
- printf ("combined mode not supported\n");
+ puts("combined mode not supported\n");
return 1;
}
- pci_read_config_byte (bdf, PCI_PI, &pi);
+ pci_read_config_byte(bdf, PCI_PI, &pi);
if ((pi & 0x05) != 0x05) {
- printf ("Sata is in Legacy mode\n");
+ puts("Sata is in Legacy mode\n");
return 1;
- } else {
- printf ("sata is in Native mode\n");
- }
+ } else
+ puts("sata is in Native mode\n");
- /*MASTER CFG AND IO CFG */
- pci_read_config_word (bdf, PCI_COMMAND, &cmd);
+ /* MASTER CFG AND IO CFG */
+ pci_read_config_word(bdf, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
- pci_write_config_word (bdf, PCI_COMMAND, cmd);
- pci_read_config_byte (dev, PCI_LATENCY_TIMER, &lat);
+ pci_write_config_word(bdf, PCI_COMMAND, cmd);
+ pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
if (lat < 16)
lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
else if (lat > pcibios_max_latency)
lat = pcibios_max_latency;
- pci_write_config_byte (dev, PCI_LATENCY_TIMER, lat);
+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
return 0;
}
-int
-sata_bus_probe (int port_no)
+int sata_bus_probe(int port_no)
{
int orig_mask, mask;
u16 pcs;
mask = (PORT_PRESENT << port_no);
- pci_read_config_word (bdf, PCI_PCS, &pcs);
+ pci_read_config_word(bdf, PCI_PCS, &pcs);
orig_mask = (int) pcs & 0xff;
if ((orig_mask & mask) != mask)
return 0;
return 1;
}
-int
-init_sata (int dev)
+int init_sata(int dev)
{
- static int done = 0;
+ static int done;
u8 i, rv = 0;
if (!done)
else
return 0;
- rv = pci_sata_init ();
+ rv = pci_sata_init();
if (rv == 1) {
- printf ("pci initialization failed\n");
+ puts("pci initialization failed\n");
return 1;
}
port[1].ioaddr.bmdma_addr = iobase5 + 0x8;
for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++)
- sata_port (&port[i].ioaddr);
+ sata_port(&port[i].ioaddr);
for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
- if (!(sata_bus_probe (i))) {
+ if (!(sata_bus_probe(i))) {
port[i].port_state = 0;
- printf ("SATA#%d port is not present \n", i);
+ printf("SATA#%d port is not present\n", i);
} else {
- printf ("SATA#%d port is present\n", i);
- if (sata_bus_softreset (i)) {
+ printf("SATA#%d port is present\n", i);
+ if (sata_bus_softreset(i))
port[i].port_state = 0;
- } else {
+ else
port[i].port_state = 1;
- }
}
}
if (port[i].port_state == 0)
continue;
for (j = 0; j < CONFIG_SYS_SATA_DEVS_PER_BUS; j++) {
- sata_identify (i, j);
- set_Feature_cmd (i, j);
+ sata_identify(i, j);
+ set_Feature_cmd(i, j);
devno = i * CONFIG_SYS_SATA_DEVS_PER_BUS + j;
if ((sata_dev_desc[devno].lba > 0) &&
(sata_dev_desc[devno].blksz > 0)) {
- dev_print (&sata_dev_desc[devno]);
+ dev_print(&sata_dev_desc[devno]);
/* initialize partition type */
- init_part (&sata_dev_desc[devno]);
+ init_part(&sata_dev_desc[devno]);
}
}
}
return 0;
}
-static u8 __inline__
-sata_inb (unsigned long ioaddr)
+static inline u8 sata_inb(unsigned long ioaddr)
{
- return inb (ioaddr);
+ return inb(ioaddr);
}
-static void __inline__
-sata_outb (unsigned char val, unsigned long ioaddr)
+static inline void sata_outb(unsigned char val, unsigned long ioaddr)
{
- outb (val, ioaddr);
+ outb(val, ioaddr);
}
-static void
-output_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
+static void output_data(struct sata_ioports *ioaddr, ulong * sect_buf,
+ int words)
{
- outsw (ioaddr->data_addr, sect_buf, words << 1);
+ outsw(ioaddr->data_addr, sect_buf, words << 1);
}
-static int
-input_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
+static int input_data(struct sata_ioports *ioaddr, ulong * sect_buf, int words)
{
- insw (ioaddr->data_addr, sect_buf, words << 1);
+ insw(ioaddr->data_addr, sect_buf, words << 1);
return 0;
}
-static void
-sata_cpy (unsigned char *dst, unsigned char *src, unsigned int len)
+static void sata_cpy(unsigned char *dst, unsigned char *src, unsigned int len)
{
unsigned char *end, *last;
if (*src++ != ' ')
last = dst;
}
- OUT:
+OUT:
*last = '\0';
}
-int
-sata_bus_softreset (int num)
+int sata_bus_softreset(int num)
{
u8 dev = 0, status = 0, i;
port[num].dev_mask = 0;
for (i = 0; i < CONFIG_SYS_SATA_DEVS_PER_BUS; i++) {
- if (!(sata_devchk (&port[num].ioaddr, i))) {
- PRINTF ("dev_chk failed for dev#%d\n", i);
+ if (!(sata_devchk(&port[num].ioaddr, i))) {
+ debug("dev_chk failed for dev#%d\n", i);
} else {
port[num].dev_mask |= (1 << i);
- PRINTF ("dev_chk passed for dev#%d\n", i);
+ debug("dev_chk passed for dev#%d\n", i);
}
}
if (!(port[num].dev_mask)) {
- printf ("no devices on port%d\n", num);
+ printf("no devices on port%d\n", num);
return 1;
}
- dev_select (&port[num].ioaddr, dev);
+ dev_select(&port[num].ioaddr, dev);
- port[num].ctl_reg = 0x08; /*Default value of control reg */
- sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
- udelay (10);
- sata_outb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
- udelay (10);
- sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
+ port[num].ctl_reg = 0x08; /* Default value of control reg */
+ sata_outb(port[num].ctl_reg, port[num].ioaddr.ctl_addr);
+ udelay(10);
+ sata_outb(port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
+ udelay(10);
+ sata_outb(port[num].ctl_reg, port[num].ioaddr.ctl_addr);
- /* spec mandates ">= 2ms" before checking status.
+ /*
+ * spec mandates ">= 2ms" before checking status.
* We wait 150ms, because that was the magic delay used for
* ATAPI devices in Hale Landis's ATADRVR, for the period of time
* between when the ATA command register is written, and then
* checking status is fine, post SRST, we perform this magic
* delay here as well.
*/
- msleep (150);
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300);
+ mdelay(150);
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 300);
while ((status & ATA_BUSY)) {
- msleep (100);
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3);
+ mdelay(100);
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 3);
}
if (status & ATA_BUSY)
- printf ("ata%u is slow to respond,plz be patient\n", num);
+ printf("ata%u is slow to respond,plz be patient\n", num);
while ((status & ATA_BUSY)) {
- msleep (100);
- status = sata_chk_status (&port[num].ioaddr);
+ mdelay(100);
+ status = sata_chk_status(&port[num].ioaddr);
}
if (status & ATA_BUSY) {
- printf ("ata%u failed to respond : ", num);
- printf ("bus reset failed\n");
+ printf("ata%u failed to respond : bus reset failed\n", num);
return 1;
}
return 0;
}
-void
-sata_identify (int num, int dev)
+void sata_identify(int num, int dev)
{
- u8 cmd = 0, status = 0, devno = num * CONFIG_SYS_SATA_DEVS_PER_BUS + dev;
+ u8 cmd = 0, status = 0;
+ u8 devno = num * CONFIG_SYS_SATA_DEVS_PER_BUS + dev;
u16 iobuf[ATA_SECT_SIZE];
u64 n_sectors = 0;
u8 mask = 0;
- memset (iobuf, 0, sizeof (iobuf));
+ memset(iobuf, 0, sizeof(iobuf));
hd_driveid_t *iop = (hd_driveid_t *) iobuf;
if (dev == 0)
mask = 0x02;
if (!(port[num].dev_mask & mask)) {
- printf ("dev%d is not present on port#%d\n", dev, num);
+ printf("dev%d is not present on port#%d\n", dev, num);
return;
}
- printf ("port=%d dev=%d\n", num, dev);
+ printf("port=%d dev=%d\n", num, dev);
- dev_select (&port[num].ioaddr, dev);
+ dev_select(&port[num].ioaddr, dev);
status = 0;
- cmd = ATA_CMD_IDENT; /*Device Identify Command */
- sata_outb (cmd, port[num].ioaddr.command_addr);
- sata_inb (port[num].ioaddr.altstatus_addr);
- udelay (10);
+ cmd = ATA_CMD_IDENT; /* Device Identify Command */
+ sata_outb(cmd, port[num].ioaddr.command_addr);
+ sata_inb(port[num].ioaddr.altstatus_addr);
+ udelay(10);
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000);
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 1000);
if (status & ATA_ERR) {
- printf ("\ndevice not responding\n");
+ puts("\ndevice not responding\n");
port[num].dev_mask &= ~mask;
return;
}
- input_data (&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS);
+ input_data(&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS);
- PRINTF ("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
+ debug("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
"86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49],
iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86],
iobuf[87], iobuf[88]);
/* we require LBA and DMA support (bits 8 & 9 of word 49) */
- if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
- PRINTF ("ata%u: no dma/lba\n", num);
- }
- ata_dump_id (iobuf);
+ if (!ata_id_has_dma(iobuf) || !ata_id_has_lba(iobuf))
+ debug("ata%u: no dma/lba\n", num);
+ ata_dump_id(iobuf);
- if (ata_id_has_lba48 (iobuf)) {
- n_sectors = ata_id_u64 (iobuf, 100);
- } else {
- n_sectors = ata_id_u32 (iobuf, 60);
- }
- PRINTF ("no. of sectors %u\n", ata_id_u64 (iobuf, 100));
- PRINTF ("no. of sectors %u\n", ata_id_u32 (iobuf, 60));
+ if (ata_id_has_lba48(iobuf))
+ n_sectors = ata_id_u64(iobuf, 100);
+ else
+ n_sectors = ata_id_u32(iobuf, 60);
+ debug("no. of sectors %u\n", ata_id_u64(iobuf, 100));
+ debug("no. of sectors %u\n", ata_id_u32(iobuf, 60));
if (n_sectors == 0) {
port[num].dev_mask &= ~mask;
return;
}
- sata_cpy ((unsigned char *)sata_dev_desc[devno].revision, iop->fw_rev,
- sizeof (sata_dev_desc[devno].revision));
- sata_cpy ((unsigned char *)sata_dev_desc[devno].vendor, iop->model,
- sizeof (sata_dev_desc[devno].vendor));
- sata_cpy ((unsigned char *)sata_dev_desc[devno].product, iop->serial_no,
- sizeof (sata_dev_desc[devno].product));
- strswab (sata_dev_desc[devno].revision);
- strswab (sata_dev_desc[devno].vendor);
+ sata_cpy((unsigned char *)sata_dev_desc[devno].revision, iop->fw_rev,
+ sizeof(sata_dev_desc[devno].revision));
+ sata_cpy((unsigned char *)sata_dev_desc[devno].vendor, iop->model,
+ sizeof(sata_dev_desc[devno].vendor));
+ sata_cpy((unsigned char *)sata_dev_desc[devno].product, iop->serial_no,
+ sizeof(sata_dev_desc[devno].product));
+ strswab(sata_dev_desc[devno].revision);
+ strswab(sata_dev_desc[devno].vendor);
- if ((iop->config & 0x0080) == 0x0080) {
+ if ((iop->config & 0x0080) == 0x0080)
sata_dev_desc[devno].removable = 1;
- } else {
+ else
sata_dev_desc[devno].removable = 0;
- }
sata_dev_desc[devno].lba = iop->lba_capacity;
- PRINTF ("lba=0x%x", sata_dev_desc[devno].lba);
+ debug("lba=0x%x", sata_dev_desc[devno].lba);
#ifdef CONFIG_LBA48
if (iop->command_set_2 & 0x0400) {
sata_dev_desc[devno].lun = 0; /* just to fill something in... */
}
-void
-set_Feature_cmd (int num, int dev)
+void set_Feature_cmd(int num, int dev)
{
u8 mask = 0x00, status = 0;
mask = 0x02;
if (!(port[num].dev_mask & mask)) {
- PRINTF ("dev%d is not present on port#%d\n", dev, num);
+ debug("dev%d is not present on port#%d\n", dev, num);
return;
}
- dev_select (&port[num].ioaddr, dev);
+ dev_select(&port[num].ioaddr, dev);
- sata_outb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
- sata_outb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
- sata_outb (0, port[num].ioaddr.lbal_addr);
- sata_outb (0, port[num].ioaddr.lbam_addr);
- sata_outb (0, port[num].ioaddr.lbah_addr);
+ sata_outb(SETFEATURES_XFER, port[num].ioaddr.feature_addr);
+ sata_outb(XFER_PIO_4, port[num].ioaddr.nsect_addr);
+ sata_outb(0, port[num].ioaddr.lbal_addr);
+ sata_outb(0, port[num].ioaddr.lbam_addr);
+ sata_outb(0, port[num].ioaddr.lbah_addr);
- sata_outb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
- sata_outb (ATA_CMD_SETF, port[num].ioaddr.command_addr);
+ sata_outb(ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
+ sata_outb(ATA_CMD_SETF, port[num].ioaddr.command_addr);
- udelay (50);
- msleep (150);
+ udelay(50);
+ mdelay(150);
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000);
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 5000);
if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) {
- printf ("Error : status 0x%02x\n", status);
+ printf("Error : status 0x%02x\n", status);
port[num].dev_mask &= ~mask;
}
}
-void
-sata_port (struct sata_ioports *ioport)
+void sata_port(struct sata_ioports *ioport)
{
ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
}
-int
-sata_devchk (struct sata_ioports *ioaddr, int dev)
+int sata_devchk(struct sata_ioports *ioaddr, int dev)
{
u8 nsect, lbal;
- dev_select (ioaddr, dev);
+ dev_select(ioaddr, dev);
- sata_outb (0x55, ioaddr->nsect_addr);
- sata_outb (0xaa, ioaddr->lbal_addr);
+ sata_outb(0x55, ioaddr->nsect_addr);
+ sata_outb(0xaa, ioaddr->lbal_addr);
- sata_outb (0xaa, ioaddr->nsect_addr);
- sata_outb (0x55, ioaddr->lbal_addr);
+ sata_outb(0xaa, ioaddr->nsect_addr);
+ sata_outb(0x55, ioaddr->lbal_addr);
- sata_outb (0x55, ioaddr->nsect_addr);
- sata_outb (0xaa, ioaddr->lbal_addr);
+ sata_outb(0x55, ioaddr->nsect_addr);
+ sata_outb(0xaa, ioaddr->lbal_addr);
- nsect = sata_inb (ioaddr->nsect_addr);
- lbal = sata_inb (ioaddr->lbal_addr);
+ nsect = sata_inb(ioaddr->nsect_addr);
+ lbal = sata_inb(ioaddr->lbal_addr);
if ((nsect == 0x55) && (lbal == 0xaa))
return 1; /* we found a device */
return 0; /* nothing found */
}
-void
-dev_select (struct sata_ioports *ioaddr, int dev)
+void dev_select(struct sata_ioports *ioaddr, int dev)
{
u8 tmp = 0;
else
tmp = ATA_DEVICE_OBS | ATA_DEV1;
- sata_outb (tmp, ioaddr->device_addr);
- sata_inb (ioaddr->altstatus_addr);
- udelay (5);
+ sata_outb(tmp, ioaddr->device_addr);
+ sata_inb(ioaddr->altstatus_addr);
+ udelay(5);
}
-u8
-sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max)
+u8 sata_busy_wait(struct sata_ioports *ioaddr, int bits, unsigned int max)
{
u8 status;
do {
- udelay (1000);
- status = sata_chk_status (ioaddr);
+ udelay(1000);
+ status = sata_chk_status(ioaddr);
max--;
} while ((status & bits) && (max > 0));
return status;
}
-u8
-sata_chk_status (struct sata_ioports * ioaddr)
+u8 sata_chk_status(struct sata_ioports *ioaddr)
{
- return sata_inb (ioaddr->status_addr);
+ return sata_inb(ioaddr->status_addr);
}
-void
-msleep (int count)
-{
- int i;
- for (i = 0; i < count; i++)
- udelay (1000);
-}
-
-ulong
-sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buff)
+ulong sata_read(int device, ulong blknr, lbaint_t blkcnt, void *buff)
{
ulong n = 0, *buffer = (ulong *)buff;
u8 dev = 0, num = 0, mask = 0, status = 0;
if (blknr & 0x0000fffff0000000) {
if (!sata_dev_desc[devno].lba48) {
- printf ("Drive doesn't support 48-bit addressing\n");
+ printf("Drive doesn't support 48-bit addressing\n");
return 0;
}
/* more than 28 bits used, use 48bit mode */
lba48 = 1;
}
#endif
- /*Port Number */
+ /* Port Number */
num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
- /*dev on the port */
+ /* dev on the port */
if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
else
mask = 0x02;
if (!(port[num].dev_mask & mask)) {
- printf ("dev%d is not present on port#%d\n", dev, num);
+ printf("dev%d is not present on port#%d\n", dev, num);
return 0;
}
/* Select device */
- dev_select (&port[num].ioaddr, dev);
+ dev_select(&port[num].ioaddr, dev);
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
- printf ("ata%u failed to respond\n", port[num].port_no);
+ printf("ata%u failed to respond\n", port[num].port_no);
return n;
}
while (blkcnt-- > 0) {
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
- printf ("ata%u failed to respond\n", 0);
+ printf("ata%u failed to respond\n", 0);
return n;
}
#ifdef CONFIG_LBA48
if (lba48) {
/* write high bits */
- sata_outb (0, port[num].ioaddr.nsect_addr);
- sata_outb ((blknr >> 24) & 0xFF,
+ sata_outb(0, port[num].ioaddr.nsect_addr);
+ sata_outb((blknr >> 24) & 0xFF,
port[num].ioaddr.lbal_addr);
- sata_outb ((blknr >> 32) & 0xFF,
+ sata_outb((blknr >> 32) & 0xFF,
port[num].ioaddr.lbam_addr);
- sata_outb ((blknr >> 40) & 0xFF,
+ sata_outb((blknr >> 40) & 0xFF,
port[num].ioaddr.lbah_addr);
}
#endif
- sata_outb (1, port[num].ioaddr.nsect_addr);
- sata_outb (((blknr) >> 0) & 0xFF,
+ sata_outb(1, port[num].ioaddr.nsect_addr);
+ sata_outb(((blknr) >> 0) & 0xFF,
port[num].ioaddr.lbal_addr);
- sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
- sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
+ sata_outb((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
+ sata_outb((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
#ifdef CONFIG_LBA48
if (lba48) {
- sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
- sata_outb (ATA_CMD_READ_EXT,
+ sata_outb(ATA_LBA, port[num].ioaddr.device_addr);
+ sata_outb(ATA_CMD_READ_EXT,
port[num].ioaddr.command_addr);
} else
#endif
{
- sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
+ sata_outb(ATA_LBA | ((blknr >> 24) & 0xF),
port[num].ioaddr.device_addr);
- sata_outb (ATA_CMD_READ,
+ sata_outb(ATA_CMD_READ,
port[num].ioaddr.command_addr);
}
- msleep (50);
- /*may take up to 4 sec */
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
+ mdelay(50);
+ /* may take up to 4 sec */
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 4000);
if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
!= ATA_STAT_DRQ) {
u8 err = 0;
- printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
+ printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
device, (ulong) blknr, status);
- err = sata_inb (port[num].ioaddr.error_addr);
- printf ("Error reg = 0x%x\n", err);
- return (n);
+ err = sata_inb(port[num].ioaddr.error_addr);
+ printf("Error reg = 0x%x\n", err);
+ return n;
}
- input_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
- sata_inb (port[num].ioaddr.altstatus_addr);
- udelay (50);
+ input_data(&port[num].ioaddr, buffer, ATA_SECTORWORDS);
+ sata_inb(port[num].ioaddr.altstatus_addr);
+ udelay(50);
++n;
++blknr;
return n;
}
-ulong
-sata_write (int device, ulong blknr,lbaint_t blkcnt, void * buff)
+ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, const void *buff)
{
ulong n = 0, *buffer = (ulong *)buff;
unsigned char status = 0, num = 0, dev = 0, mask = 0;
if (blknr & 0x0000fffff0000000) {
if (!sata_dev_desc[devno].lba48) {
- printf ("Drive doesn't support 48-bit addressing\n");
+ printf("Drive doesn't support 48-bit addressing\n");
return 0;
}
/* more than 28 bits used, use 48bit mode */
lba48 = 1;
}
#endif
- /*Port Number */
+ /* Port Number */
num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
- /*dev on the Port */
+ /* dev on the Port */
if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
else
mask = 0x02;
/* Select device */
- dev_select (&port[num].ioaddr, dev);
+ dev_select(&port[num].ioaddr, dev);
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
- printf ("ata%u failed to respond\n", port[num].port_no);
+ printf("ata%u failed to respond\n", port[num].port_no);
return n;
}
while (blkcnt-- > 0) {
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
- printf ("ata%u failed to respond\n",
+ printf("ata%u failed to respond\n",
port[num].port_no);
return n;
}
#ifdef CONFIG_LBA48
if (lba48) {
/* write high bits */
- sata_outb (0, port[num].ioaddr.nsect_addr);
- sata_outb ((blknr >> 24) & 0xFF,
+ sata_outb(0, port[num].ioaddr.nsect_addr);
+ sata_outb((blknr >> 24) & 0xFF,
port[num].ioaddr.lbal_addr);
- sata_outb ((blknr >> 32) & 0xFF,
+ sata_outb((blknr >> 32) & 0xFF,
port[num].ioaddr.lbam_addr);
- sata_outb ((blknr >> 40) & 0xFF,
+ sata_outb((blknr >> 40) & 0xFF,
port[num].ioaddr.lbah_addr);
}
#endif
- sata_outb (1, port[num].ioaddr.nsect_addr);
- sata_outb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
- sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
- sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
+ sata_outb(1, port[num].ioaddr.nsect_addr);
+ sata_outb((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
+ sata_outb((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
+ sata_outb((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
#ifdef CONFIG_LBA48
if (lba48) {
- sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
- sata_outb (ATA_CMD_WRITE_EXT,
+ sata_outb(ATA_LBA, port[num].ioaddr.device_addr);
+ sata_outb(ATA_CMD_WRITE_EXT,
port[num].ioaddr.command_addr);
} else
#endif
{
- sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
+ sata_outb(ATA_LBA | ((blknr >> 24) & 0xF),
port[num].ioaddr.device_addr);
- sata_outb (ATA_CMD_WRITE,
+ sata_outb(ATA_CMD_WRITE,
port[num].ioaddr.command_addr);
}
- msleep (50);
- /*may take up to 4 sec */
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
+ mdelay(50);
+ /* may take up to 4 sec */
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 4000);
if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
!= ATA_STAT_DRQ) {
- printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
+ printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
device, (ulong) blknr, status);
- return (n);
+ return n;
}
- output_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
- sata_inb (port[num].ioaddr.altstatus_addr);
- udelay (50);
+ output_data(&port[num].ioaddr, buffer, ATA_SECTORWORDS);
+ sata_inb(port[num].ioaddr.altstatus_addr);
+ udelay(50);
++n;
++blknr;
#ifndef __ATA_PIIX_H__
#define __ATA_PIIX_H__
-#if (DEBUG_SATA)
-#define PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
struct sata_ioports {
unsigned long cmd_addr;
unsigned long data_addr;
};
/***********SATA LIBRARY SPECIFIC DEFINITIONS AND DECLARATIONS**************/
-#ifdef SATA_DECL /*SATA library specific declarations */
-inline void
-ata_dump_id (u16 * id)
+#ifdef SATA_DECL /* SATA library specific declarations */
+inline void ata_dump_id(u16 *id)
{
- PRINTF ("49 = 0x%04x "
+ debug("49 = 0x%04x "
"53 = 0x%04x "
"63 = 0x%04x "
"64 = 0x%04x "
- "75 = 0x%04x \n", id[49], id[53], id[63], id[64], id[75]);
- PRINTF ("80 = 0x%04x "
+ "75 = 0x%04x\n", id[49], id[53], id[63], id[64], id[75]);
+ debug("80 = 0x%04x "
"81 = 0x%04x "
"82 = 0x%04x "
"83 = 0x%04x "
- "84 = 0x%04x \n", id[80], id[81], id[82], id[83], id[84]);
- PRINTF ("88 = 0x%04x " "93 = 0x%04x\n", id[88], id[93]);
+ "84 = 0x%04x\n", id[80], id[81], id[82], id[83], id[84]);
+ debug("88 = 0x%04x " "93 = 0x%04x\n", id[88], id[93]);
}
#endif
#ifdef SATA_DECL /*SATA library specific declarations */
-int sata_bus_softreset (int num);
-void sata_identify (int num, int dev);
-void sata_port (struct sata_ioports *ioport);
-void set_Feature_cmd (int num, int dev);
-int sata_devchk (struct sata_ioports *ioaddr, int dev);
-void dev_select (struct sata_ioports *ioaddr, int dev);
-u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max);
-u8 sata_chk_status (struct sata_ioports *ioaddr);
-ulong sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buffer);
-ulong sata_write (int device,ulong blknr, lbaint_t blkcnt, void * buffer);
-void msleep (int count);
+int sata_bus_softreset(int num);
+void sata_identify(int num, int dev);
+void sata_port(struct sata_ioports *ioport);
+void set_Feature_cmd(int num, int dev);
+int sata_devchk(struct sata_ioports *ioaddr, int dev);
+void dev_select(struct sata_ioports *ioaddr, int dev);
+u8 sata_busy_wait(struct sata_ioports *ioaddr, int bits, unsigned int max);
+u8 sata_chk_status(struct sata_ioports *ioaddr);
#endif
/************DRIVER SPECIFIC DEFINITIONS AND DECLARATIONS**************/
-#ifdef DRV_DECL /*Driver specific declaration */
-int init_sata (int dev);
+#ifdef DRV_DECL /* Driver specific declaration */
+int init_sata(int dev);
#endif
-#ifdef DRV_DECL /*Defines Driver Specific variables */
+#ifdef DRV_DECL /* Defines Driver Specific variables */
struct sata_port port[CONFIG_SYS_SATA_MAXBUS];
#endif
#include <libata.h>
#include <ahci.h>
#include <fis.h>
+#include <sata.h>
#include <common.h>
#include <malloc.h>
}
u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
- void *buffer, int is_write)
+ const void *buffer, int is_write)
{
u32 start, blks;
u8 *addr;
}
u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt,
- void *buffer, int is_write)
+ const void *buffer, int is_write)
{
u32 start, blks;
u8 *addr;
/*
* SATA interface between low level driver and command layer
*/
-ulong sata_read(int dev, unsigned long blknr, lbaint_t blkcnt, void *buffer)
+ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
{
u32 rc;
return rc;
}
-ulong sata_write(int dev, unsigned long blknr, lbaint_t blkcnt, void *buffer)
+ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
{
u32 rc;
struct ahci_probe_ent *probe_ent =
#define READ_CMD 0
#define WRITE_CMD 1
-extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-
#endif /* __FSL_SATA_H__ */
#include <malloc.h>
#include <libata.h>
#include <fis.h>
+#include <sata.h>
#include "fsl_sata.h"
-extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-
#ifndef CONFIG_SYS_SATA1_FLAGS
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
#endif
return sata->flush_ext;
}
-u32 ata_low_level_rw_lba48(int dev, u32 blknr, u32 blkcnt, void *buffer, int is_write)
+u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
+ const void *buffer, int is_write)
{
u32 start, blks;
u8 *addr;
return blkcnt;
}
-u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt, void *buffer, int is_write)
+u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt, const void *buffer,
+ int is_write)
{
u32 start, blks;
u8 *addr;
/*
* SATA interface between low level driver and command layer
*/
-ulong sata_read(int dev, u32 blknr, u32 blkcnt, void *buffer)
+ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
{
u32 rc;
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
return rc;
}
-ulong sata_write(int dev, u32 blknr, u32 blkcnt, void *buffer)
+ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
{
u32 rc;
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
#include <asm/portmux.h>
#include <asm/mach-common/bits/pata.h>
#include <ata.h>
+#include <sata.h>
#include <libata.h>
#include "pata_bfin.h"
return sr;
}
-ulong sata_read(int dev, ulong block, ulong blkcnt, void *buff)
+ulong sata_read(int dev, ulong block, lbaint_t blkcnt, void *buff)
{
struct ata_port *ap = &port[dev];
ulong n = 0, sread;
return n;
}
-ulong sata_write(int dev, ulong block, ulong blkcnt, const void *buff)
+ulong sata_write(int dev, ulong block, lbaint_t blkcnt, const void *buff)
{
struct ata_port *ap = &port[dev];
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
unsigned char dev_mask;
};
-extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-
#define DRV_NAME "pata-bfin"
#define DRV_VERSION "0.9"
#define __iomem
#include <asm/io.h>
#include <malloc.h>
#include <ata.h>
+#include <sata.h>
#include <linux/ctype.h>
#include "sata_dwc.h"
unsigned int flags, u16 *id);
static int check_sata_dev_state(void);
-extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-
static const struct ata_port_info sata_dwc_port_info[] = {
{
.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
#define SATA_MAX_WRITE_BLK 0xFFFF
#endif
-ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, void *buffer)
+ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, const void *buffer)
{
ulong start,blks, buf_addr;
unsigned short smallblks;
#include <malloc.h>
#include <asm/io.h>
#include <fis.h>
+#include <sata.h>
#include <libata.h>
#include "sata_sil.h"
}
ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt,
- void *buffer, int is_write)
+ const void *buffer, int is_write)
{
ulong start, blks, max_blks;
u8 *addr;
}
ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt,
- void *buffer, int is_write)
+ const void *buffer, int is_write)
{
ulong start, blks, max_blks;
u8 *addr;
/*
* SATA interface between low level driver and command layer
*/
-ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
+ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
{
struct sil_sata *sata = sata_dev_desc[dev].priv;
ulong rc;
#define READ_CMD 0
#define WRITE_CMD 1
-extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-
/*
* SATA device driver struct for each dev
*/
#include <asm/byteorder.h>
#include <asm/io.h>
#include <ide.h>
+#include <sata.h>
#include <libata.h>
#include "sata_sil3114.h"
static void msleep (int count);
static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */
-extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
static struct sata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
COBJS-$(CONFIG_OMAP_GPIO) += omap_gpio.o
COBJS-$(CONFIG_DB8500_GPIO) += db8500_gpio.o
COBJS-$(CONFIG_BCM2835_GPIO) += bcm2835_gpio.o
+COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
static uint8_t chip = CONFIG_SYS_I2C_PCA953X_ADDR;
- int val;
+ int ret = CMD_RET_USAGE, val;
ulong ul_arg2 = 0;
ulong ul_arg3 = 0;
cmd_tbl_t *c;
if (!c || !((argc == (c->maxargs)) ||
(((int)c->cmd == PCA953X_CMD_DEVICE) &&
(argc == (c->maxargs - 1))))) {
- return cmd_usage(cmdtp);
+ return CMD_RET_USAGE;
}
/* arg2 used as chip number or pin number */
switch ((int)c->cmd) {
#ifdef CONFIG_CMD_PCA953X_INFO
case PCA953X_CMD_INFO:
- return pca953x_info(chip);
+ ret = pca953x_info(chip);
+ if (ret)
+ ret = CMD_RET_FAILURE;
+ break;
#endif
+
case PCA953X_CMD_DEVICE:
if (argc == 3)
chip = (uint8_t)ul_arg2;
printf("Current device address: 0x%x\n", chip);
- return 0;
+ ret = CMD_RET_SUCCESS;
+ break;
+
case PCA953X_CMD_INPUT:
- pca953x_set_dir(chip, (1 << ul_arg2),
+ ret = pca953x_set_dir(chip, (1 << ul_arg2),
PCA953X_DIR_IN << ul_arg2);
val = (pca953x_get_val(chip) & (1 << ul_arg2)) != 0;
- printf("chip 0x%02x, pin 0x%lx = %d\n", chip, ul_arg2, val);
- return val;
+ if (ret)
+ ret = CMD_RET_FAILURE;
+ else
+ printf("chip 0x%02x, pin 0x%lx = %d\n", chip, ul_arg2,
+ val);
+ break;
+
case PCA953X_CMD_OUTPUT:
- pca953x_set_dir(chip, (1 << ul_arg2),
+ ret = pca953x_set_dir(chip, (1 << ul_arg2),
(PCA953X_DIR_OUT << ul_arg2));
- return pca953x_set_val(chip, (1 << ul_arg2),
- (ul_arg3 << ul_arg2));
+ if (!ret)
+ ret = pca953x_set_val(chip, (1 << ul_arg2),
+ (ul_arg3 << ul_arg2));
+ if (ret)
+ ret = CMD_RET_FAILURE;
+ break;
+
case PCA953X_CMD_INVERT:
- return pca953x_set_pol(chip, (1 << ul_arg2),
+ ret = pca953x_set_pol(chip, (1 << ul_arg2),
(ul_arg3 << ul_arg2));
- default:
- /* We should never get here */
- return 1;
+ if (ret)
+ ret = CMD_RET_FAILURE;
+ break;
}
+
+ if (ret == CMD_RET_FAILURE)
+ eprintf("Error talking to chip at 0x%x\n", chip);
+
+ return ret;
}
U_BOOT_CMD(
" - set pin as output and drive low or high\n"
"pca953x invert pin 0|1\n"
" - disable/enable polarity inversion for reads\n"
- "pca953x intput pin\n"
+ "pca953x input pin\n"
" - set pin as input and read value"
);
--- /dev/null
+/*
+ * Copyright (C) 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/s3c2440.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+#define GPIO_INPUT 0x0
+#define GPIO_OUTPUT 0x1
+
+/* 0x4 means that we want DAT and not CON register */
+#define GPIO_PORT(x) ((((x) >> 5) & 0x3) + 0x4)
+#define GPIO_BIT(x) ((x) & 0x3f)
+
+/*
+ * It's how we calculate the full port address
+ * We have to get the number of the port + 1 (Port A is at 0x56000001 ...)
+ * We move it at the second digit, and finally we add 0x4 because we want
+ * to modify GPIO DAT and not CON
+ */
+#define GPIO_FULLPORT(x) (S3C24X0_GPIO_BASE | ((GPIO_PORT(gpio) + 1) << 1))
+
+int gpio_set_value(unsigned gpio, int value)
+{
+ unsigned l = readl(GPIO_FULLPORT(gpio));
+ unsigned bit;
+ unsigned port = GPIO_FULLPORT(gpio);
+
+ /*
+ * All GPIO Port have a configuration on
+ * 2 bits excepted the first GPIO (A) which
+ * have only 1 bit of configuration.
+ */
+ if (!GPIO_PORT(gpio))
+ bit = (0x1 << GPIO_BIT(gpio));
+ else
+ bit = (0x3 << GPIO_BIT(gpio));
+
+ if (value)
+ l |= bit;
+ else
+ l &= ~bit;
+
+ return writel(port, l);
+}
+
+int gpio_get_value(unsigned gpio)
+{
+ unsigned l = readl(GPIO_FULLPORT(gpio));
+
+ if (GPIO_PORT(gpio) == 0) /* PORT A */
+ return (l >> GPIO_BIT(gpio)) & 0x1;
+ return (l >> GPIO_BIT(gpio)) & 0x3;
+}
+
+int gpio_request(unsigned gpio, const char *label)
+{
+ return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+ return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ return writel(GPIO_FULLPORT(gpio), GPIO_INPUT << GPIO_BIT(gpio));
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ writel(GPIO_FULLPORT(gpio), GPIO_OUTPUT << GPIO_BIT(gpio));
+ return gpio_set_value(gpio, value);
+}
#include <common.h>
#include <asm/io.h>
#include <asm/bitops.h>
-#include <asm/arch/tegra20.h>
+#include <asm/arch/tegra.h>
#include <asm/gpio.h>
enum {
#endif
/* Divider value calculation */
- i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK);
+ i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
div = (i2c_clk_rate + rate - 1) / rate;
if (div < i2c_clk_div[0][0])
clk_div = 0;
for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
;
- return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0];
+ return mxc_get_clock(MXC_I2C_CLK) / i2c_clk_div[clk_div][0];
}
#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
#define IRQ_WAIT 1000
-static void irq_wait(struct sh_i2c *base)
-{
- int i;
- u8 status;
-
- for (i = 0 ; i < IRQ_WAIT ; i++) {
- status = readb(&base->icsr);
- if (SH_IC_WAIT & status)
- break;
-
- udelay(10);
- }
-
- writeb(status & ~SH_IC_WAIT, &base->icsr);
-}
-
static void irq_dte(struct sh_i2c *base)
{
int i;
#include <fdtdec.h>
#include <i2c.h>
#include <asm/io.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra_i2c.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/tegra_i2c.h>
DECLARE_GLOBAL_DATA_PTR;
* insert another character if we later realise that we
* have missed a repeat slot.
*/
- is_repeat = (int)get_timer(config->next_repeat_ms) >= 0;
+ is_repeat = config->repeat_rate_ms &&
+ (int)get_timer(config->next_repeat_ms) >= 0;
if (!is_repeat)
return 0;
}
return 0;
}
-int input_init(struct input_config *config, int leds, int repeat_delay_ms,
+void input_set_delays(struct input_config *config, int repeat_delay_ms,
int repeat_rate_ms)
{
- memset(config, '\0', sizeof(*config));
- config->leds = leds;
config->repeat_delay_ms = repeat_delay_ms;
config->repeat_rate_ms = repeat_rate_ms;
+}
+
+int input_init(struct input_config *config, int leds)
+{
+ memset(config, '\0', sizeof(*config));
+ config->leds = leds;
if (input_add_table(config, -1, -1,
kbd_plain_xlate, ARRAY_SIZE(kbd_plain_xlate)) ||
input_add_table(config, KEY_LEFTSHIFT, KEY_RIGHTSHIFT,
int key_in_same_col = 0, key_in_same_row = 0;
int i, j;
+ if (!config->ghost_filter || valid < 3)
+ return 0;
+
for (i = 0; i < valid; i++) {
/*
* Find 2 keys such that one key is in the same row
}
/* For a ghost key config, ignore the keypresses for this iteration. */
- if (valid >= 3 && has_ghosting(config, keys, valid)) {
+ if (has_ghosting(config, keys, valid)) {
valid = 0;
debug(" ghosting detected!\n");
}
key_code = tmp & 0xffff;
entry = row * config->num_cols + col;
map[entry] = key_code;
+ debug(" map %d, %d: pos=%d, keycode=%d\n", row, col,
+ entry, key_code);
if (pos && map_keycode == key_code)
*pos = entry;
}
int node)
{
const struct fdt_property *prop;
+ const char prefix[] = "linux,";
+ int plen = sizeof(prefix) - 1;
int offset;
/* Check each property name for ones that we understand */
/* Name needs to match "1,<type>keymap" */
debug("%s: property '%s'\n", __func__, name);
- if (strncmp(name, "1,", 2) || len < 8 ||
- strcmp(name + len - 6, "keymap"))
+ if (strncmp(name, prefix, plen) ||
+ len < plen + 6 ||
+ strcmp(name + len - 6, "keymap"))
continue;
- len -= 8;
+ len -= plen + 6;
if (len == 0) {
config->plain_keycode = create_keymap(config,
(u32 *)prop->data, fdt32_to_cpu(prop->len),
KEY_FN, &config->fn_pos);
- } else if (0 == strncmp(name + 2, "fn-", len)) {
+ } else if (0 == strncmp(name + plen, "fn-", len)) {
config->fn_keycode = create_keymap(config,
(u32 *)prop->data, fdt32_to_cpu(prop->len),
-1, NULL);
return 0;
}
-int key_matrix_init(struct key_matrix *config, int rows, int cols)
+int key_matrix_init(struct key_matrix *config, int rows, int cols,
+ int ghost_filter)
{
memset(config, '\0', sizeof(*config));
config->num_rows = rows;
config->num_cols = cols;
config->key_count = rows * cols;
+ config->ghost_filter = ghost_filter;
assert(config->key_count > 0);
return 0;
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
-#include <asm/arch/timer.h>
+#include <asm/arch-tegra/timer.h>
#include <linux/input.h>
DECLARE_GLOBAL_DATA_PTR;
debug("%s: No keyboard register found\n", __func__);
return -1;
}
+ input_set_delays(&config.input, KBC_REPEAT_DELAY_MS,
+ KBC_REPEAT_RATE_MS);
/* Decode the keyboard matrix information (16 rows, 8 columns) */
- if (key_matrix_init(&config.matrix, 16, 8)) {
+ if (key_matrix_init(&config.matrix, 16, 8, 1)) {
debug("%s: Could not init key matrix\n", __func__);
return -1;
}
{
struct stdio_dev dev;
- if (input_init(&config.input, 0, KBC_REPEAT_DELAY_MS,
- KBC_REPEAT_RATE_MS)) {
+ if (input_init(&config.input, 0)) {
debug("%s: Cannot set up input\n", __func__);
return -1;
}
*/
#include <common.h>
-#include <mmc.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
-#include <asm/arch/tegra_mmc.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/tegra_mmc.h>
+#include <mmc.h>
/* support 4 mmc hosts */
struct mmc mmc_dev[4];
sector_size = host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
host->pmecc_index_table_offset = CONFIG_PMECC_INDEX_TABLE_OFFSET;
- printk(KERN_INFO "Initialize PMECC params, cap: %d, sector: %d\n",
- cap, sector_size);
+ MTDDEBUG(MTD_DEBUG_LEVEL1,
+ "Initialize PMECC params, cap: %d, sector: %d\n",
+ cap, sector_size);
host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
debug("unexpected busy state\n");
} else {
/*
- * If the R/B pin is not connected, like on the TQM8548,
+ * If the R/B pin is not connected,
* a short delay is necessary.
*/
udelay(1);
fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar);
/*
- * Some boards/chips needs this. At least the MPC8360E-RDK and
- * TQM8548 need it. Probably weird chip, because I don't see
- * any need for this on MPC8555E + Samsung K9F1G08U0A. Usually
- * here are 0-2 unexpected busy states per block read.
+ * Some boards/chips needs this. At least the MPC8360E-RDK
+ * needs it. Probably weird chip, because I don't see any
+ * need for this on MPC8555E + Samsung K9F1G08U0A. Usually
+ * here are 0-2 unexpected busy states per block read.
*/
if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
fun_wait(fun);
#include <common.h>
#include <asm/io.h>
#include <nand.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
-#include <asm/arch/gpio.h>
+#include <asm/arch-tegra/clk_rst.h>
#include <asm/errno.h>
-#include <asm-generic/gpio.h>
+#include <asm/gpio.h>
#include <fdtdec.h>
#include "tegra_nand.h"
/* Adjust timing for NAND device */
setup_timing(config->timing, info->reg);
- funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
fdtdec_setup_gpio(&config->wp_gpio);
gpio_direction_output(config->wp_gpio.gpio, 1);
.nr_sectors = 32,
.name = "AT45DB642D",
},
+ {
+ .idcode1 = 0x47,
+ .l2_page_size = 8,
+ .pages_per_block = 16,
+ .blocks_per_sector = 16,
+ .nr_sectors = 64,
+ .name = "AT25DF321",
+ },
};
static int at45_wait_ready(struct spi_flash *flash, unsigned long timeout)
asf->flash.erase = dataflash_erase_p2;
}
+ asf->flash.page_size = page_size;
+ asf->flash.sector_size = page_size;
break;
case DF_FAMILY_AT26F:
case DF_FAMILY_AT26DF:
asf->flash.read = spi_flash_cmd_read_fast;
+ asf->flash.write = spi_flash_cmd_write_multi;
+ asf->flash.erase = spi_flash_cmd_erase;
+ asf->flash.page_size = page_size;
+ asf->flash.sector_size = 4096;
+ /* clear SPRL# bit for locked flash */
+ spi_flash_cmd_write_status(&asf->flash, 0);
break;
default:
goto err;
}
- asf->flash.sector_size = page_size;
asf->flash.size = page_size * params->pages_per_block
* params->blocks_per_sector
* params->nr_sectors;
}
#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
- defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+ defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
+ !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE)
for (i = 0; i < num_phy; i++) {
if (phy[i].is_phy_connected(i))
phy[i].auto_negotiate(i);
static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
-#ifndef CONFIG_AP1000 /* remove for warnings */
static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
uint16_t words,
uint16_t *data);
return E1000_SUCCESS;
}
-#endif /* #ifndef CONFIG_AP1000 */
/***************************************************************************
*
static int
e1000_read_mac_addr(struct eth_device *nic)
{
-#ifndef CONFIG_AP1000
struct e1000_hw *hw = nic->priv;
uint16_t offset;
uint16_t eeprom_data;
memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
}
#endif
-#else
- /*
- * The AP1000's e1000 has no eeprom; the MAC address is stored in the
- * environment variables. Currently this does not support the addition
- * of a PMC e1000 card, which is certainly a possibility, so this should
- * be updated to properly use the env variable only for the onboard e1000
- */
-
- int ii;
- char *s, *e;
-
- DEBUGFUNC();
-
- s = getenv ("ethaddr");
- if (s == NULL) {
- return -E1000_ERR_EEPROM;
- } else {
- for(ii = 0; ii < 6; ii++) {
- nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0;
- if (s){
- s = (*e) ? e + 1 : e;
- }
- }
- }
-#endif
return 0;
}
if (e1000_check_phy_reset_block(hw))
return E1000_SUCCESS;
-#ifndef CONFIG_AP1000
/* Read and store word 0x0F of the EEPROM. This word contains bits
* that determine the hardware's default PAUSE (flow control) mode,
* a bit that determines whether the HW defaults to enabling or
DEBUGOUT("EEPROM Read Error\n");
return -E1000_ERR_EEPROM;
}
-#else
- /* we have to hardcode the proper value for our hardware. */
- /* this value is for the 82540EM pci card used for prototyping, and it works. */
- eeprom_data = 0xb220;
-#endif
if (hw->fc == e1000_fc_default) {
switch (hw->mac_type) {
hw->fc = e1000_fc_full;
break;
default:
-#ifndef CONFIG_AP1000
ret_val = e1000_read_eeprom(hw,
EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
if (ret_val) {
DEBUGOUT("EEPROM Read Error\n");
return -E1000_ERR_EEPROM;
}
-#else
- eeprom_data = 0xb220;
-#endif
if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
hw->fc = e1000_fc_none;
else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
}
DEBUGOUT("Phy ID = %x \n", hw->phy_id);
-#ifndef CONFIG_AP1000
/* Set PHY to class A mode (if necessary) */
ret_val = e1000_set_phy_mode(hw);
if (ret_val)
return ret_val;
-#endif
if ((hw->mac_type == e1000_82545_rev_3) ||
(hw->mac_type == e1000_82546_rev_3)) {
ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
list_add_tail(&hw->list_node, &e1000_hw_list);
/* Validate the EEPROM and get chipset information */
-#if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
+#if !defined(CONFIG_MVBC_1G)
if (e1000_init_eeprom_params(hw)) {
E1000_ERR(nic, "EEPROM is invalid!\n");
continue;
LIB := $(obj)libserial.o
+COBJS-y += serial.o
+
COBJS-$(CONFIG_ALTERA_UART) += altera_uart.o
COBJS-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o
COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o
COBJS-$(CONFIG_S3C64XX) += s3c64xx.o
COBJS-$(CONFIG_S5P) += serial_s5p.o
-COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial.o
+COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
COBJS-$(CONFIG_CLPS7111_SERIAL) += serial_clps7111.o
COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o
COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o
COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
+COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_USB_TTY) += usbtty.o
#include <watchdog.h>
#include <asm/io.h>
#include <nios2-io.h>
+#include <linux/compiler.h>
+#include <serial.h>
DECLARE_GLOBAL_DATA_PTR;
*-----------------------------------------------------------------*/
static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE;
-void serial_setbrg( void ){ return; }
-int serial_init( void ) { return(0);}
+static void altera_jtag_serial_setbrg(void)
+{
+}
+
+static int altera_jtag_serial_init(void)
+{
+ return 0;
+}
-void serial_putc (char c)
+static void altera_jtag_serial_putc(char c)
{
while (1) {
unsigned st = readl(&jtag->control);
writel ((unsigned char)c, &jtag->data);
}
-void serial_puts (const char *s)
+static void altera_jtag_serial_puts(const char *s)
{
while (*s != 0)
serial_putc (*s++);
}
-int serial_tstc (void)
+static int altera_jtag_serial_tstc(void)
{
return ( readl (&jtag->control) & NIOS_JTAG_RRDY);
}
-int serial_getc (void)
+static int altera_jtag_serial_getc(void)
{
int c;
unsigned val;
c = val & 0x0ff;
return (c);
}
+
+static struct serial_device altera_jtag_serial_drv = {
+ .name = "altera_jtag_uart",
+ .start = altera_jtag_serial_init,
+ .stop = NULL,
+ .setbrg = altera_jtag_serial_setbrg,
+ .putc = altera_jtag_serial_putc,
+ .puts = altera_jtag_serial_puts,
+ .getc = altera_jtag_serial_getc,
+ .tstc = altera_jtag_serial_tstc,
+};
+
+void altera_jtag_serial_initialize(void)
+{
+ serial_register(&altera_jtag_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &altera_jtag_serial_drv;
+}
#include <watchdog.h>
#include <asm/io.h>
#include <nios2-io.h>
+#include <linux/compiler.h>
+#include <serial.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SYS_NIOS_FIXEDBAUD)
-/* Everything's already setup for fixed-baud PTF
+/*
+ * Everything's already setup for fixed-baud PTF
* assignment
*/
-void serial_setbrg (void){ return; }
-int serial_init (void) { return (0);}
+static void altera_serial_setbrg(void)
+{
+}
+
+static int altera_serial_init(void)
+{
+ return 0;
+}
#else
-void serial_setbrg (void)
+static void altera_serial_setbrg(void)
{
unsigned div;
div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1;
writel (div, &uart->divisor);
- return;
}
-int serial_init (void)
+static int altera_serial_init(void)
{
- serial_setbrg ();
- return (0);
+ serial_setbrg();
+ return 0;
}
#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */
/*-----------------------------------------------------------------------
* UART CONSOLE
*---------------------------------------------------------------------*/
-void serial_putc (char c)
+static void altera_serial_putc(char c)
{
if (c == '\n')
serial_putc ('\r');
writel ((unsigned char)c, &uart->txdata);
}
-void serial_puts (const char *s)
+static void altera_serial_puts(const char *s)
{
while (*s != 0) {
serial_putc (*s++);
}
}
-int serial_tstc (void)
+static int altera_serial_tstc(void)
{
return (readl (&uart->status) & NIOS_UART_RRDY);
}
-int serial_getc (void)
+static int altera_serial_getc(void)
{
while (serial_tstc () == 0)
WATCHDOG_RESET ();
return (readl (&uart->rxdata) & 0x00ff );
}
+
+static struct serial_device altera_serial_drv = {
+ .name = "altera_serial",
+ .start = altera_serial_init,
+ .stop = NULL,
+ .setbrg = altera_serial_setbrg,
+ .putc = altera_serial_putc,
+ .puts = altera_serial_puts,
+ .getc = altera_serial_getc,
+ .tstc = altera_serial_tstc,
+};
+
+void altera_serial_initialize(void)
+{
+ serial_register(&altera_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &altera_serial_drv;
+}
*/
#include <common.h>
#include <watchdog.h>
+#include <serial.h>
+#include <linux/compiler.h>
#include <asm/io.h>
#include <asm/arch/clk.h>
DECLARE_GLOBAL_DATA_PTR;
-void serial_setbrg(void)
+static void atmel_serial_setbrg(void)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
unsigned long divisor;
writel(USART3_BF(CD, divisor), &usart->brgr);
}
-int serial_init(void)
+static int atmel_serial_init(void)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
return 0;
}
-void serial_putc(char c)
+static void atmel_serial_putc(char c)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
writel(c, &usart->thr);
}
-void serial_puts(const char *s)
+static void atmel_serial_puts(const char *s)
{
while (*s)
serial_putc(*s++);
}
-int serial_getc(void)
+static int atmel_serial_getc(void)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
return readl(&usart->rhr);
}
-int serial_tstc(void)
+static int atmel_serial_tstc(void)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
}
+
+static struct serial_device atmel_serial_drv = {
+ .name = "atmel_serial",
+ .start = atmel_serial_init,
+ .stop = NULL,
+ .setbrg = atmel_serial_setbrg,
+ .putc = atmel_serial_putc,
+ .puts = atmel_serial_puts,
+ .getc = atmel_serial_getc,
+ .tstc = atmel_serial_tstc,
+};
+
+void atmel_serial_initialize(void)
+{
+ serial_register(&atmel_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &atmel_serial_drv;
+}
#include <asm/arch/clk.h>
#include <asm/arch/uart.h>
#include <asm/io.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
static struct hsuart_regs *hsuart = (struct hsuart_regs *)HS_UART_BASE;
-static void lpc32xx_hsuart_set_baudrate(void)
+static void lpc32xx_serial_setbrg(void)
{
u32 div;
writel(div, &hsuart->rate);
}
-static int lpc32xx_hsuart_getc(void)
+static int lpc32xx_serial_getc(void)
{
while (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
/* NOP */;
return readl(&hsuart->rx) & HSUART_RX_DATA;
}
-static void lpc32xx_hsuart_putc(const char c)
+static void lpc32xx_serial_putc(const char c)
{
writel(c, &hsuart->tx);
/* NOP */;
}
-static int lpc32xx_hsuart_tstc(void)
+static int lpc32xx_serial_tstc(void)
{
if (readl(&hsuart->level) & HSUART_LEVEL_RX)
return 1;
return 0;
}
-static void lpc32xx_hsuart_init(void)
+static int lpc32xx_serial_init(void)
{
- lpc32xx_hsuart_set_baudrate();
+ lpc32xx_serial_setbrg();
/* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */
writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) |
HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0,
&hsuart->ctrl);
+ return 0;
}
-void serial_setbrg(void)
-{
- return lpc32xx_hsuart_set_baudrate();
-}
-
-void serial_putc(const char c)
-{
- lpc32xx_hsuart_putc(c);
-
- /* If \n, also do \r */
- if (c == '\n')
- lpc32xx_hsuart_putc('\r');
-}
-
-int serial_getc(void)
-{
- return lpc32xx_hsuart_getc();
-}
-
-void serial_puts(const char *s)
+static void lpc32xx_serial_puts(const char *s)
{
while (*s)
serial_putc(*s++);
}
-int serial_tstc(void)
+static struct serial_device lpc32xx_serial_drv = {
+ .name = "lpc32xx_serial",
+ .start = lpc32xx_serial_init,
+ .stop = NULL,
+ .setbrg = lpc32xx_serial_setbrg,
+ .putc = lpc32xx_serial_putc,
+ .puts = lpc32xx_serial_puts,
+ .getc = lpc32xx_serial_getc,
+ .tstc = lpc32xx_serial_tstc,
+};
+
+void lpc32xx_serial_initialize(void)
{
- return lpc32xx_hsuart_tstc();
+ serial_register(&lpc32xx_serial_drv);
}
-int serial_init(void)
+__weak struct serial_device *default_serial_console(void)
{
- lpc32xx_hsuart_init();
-
- return 0;
+ return &lpc32xx_serial_drv;
}
extern void uart_port_conf(int port);
-int serial_init(void)
+static int mcf_serial_init(void)
{
volatile uart_t *uart;
u32 counter;
return (0);
}
-void serial_putc(const char c)
+static void mcf_serial_putc(const char c)
{
volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
uart->utb = c;
}
-void serial_puts(const char *s)
+static void mcf_serial_puts(const char *s)
{
while (*s) {
serial_putc(*s++);
}
}
-int serial_getc(void)
+static int mcf_serial_getc(void)
{
volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
return uart->urb;
}
-int serial_tstc(void)
+static int mcf_serial_tstc(void)
{
volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
return (uart->usr & UART_USR_RXRDY);
}
-void serial_setbrg(void)
+static void mcf_serial_setbrg(void)
{
volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
u32 counter;
uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED;
}
+
+static struct serial_device mcf_serial_drv = {
+ .name = "mcf_serial",
+ .start = mcf_serial_init,
+ .stop = NULL,
+ .setbrg = mcf_serial_setbrg,
+ .putc = mcf_serial_putc,
+ .puts = mcf_serial_puts,
+ .getc = mcf_serial_getc,
+ .tstc = mcf_serial_tstc,
+};
+
+void mcf_serial_initialize(void)
+{
+ serial_register(&mcf_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &mcf_serial_drv;
+}
char NS16550_getc(NS16550_t com_port)
{
while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) {
-#ifdef CONFIG_USB_TTY
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_TTY)
extern void usbtty_poll(void);
usbtty_poll();
#endif
* @Descr: configures GPIOs and UART. Requires BBUS Master Reset turned off
***********************************************************************/
-int serial_init( void )
+static int ns9750_serial_init(void)
{
unsigned int aunGPIOTxD[] = { 0, 8, 40, 44 };
unsigned int aunGPIORxD[] = { 1, 9, 41, 45 };
* @Descr: writes one character to the FIFO. Blocks until FIFO is not full
***********************************************************************/
-void serial_putc( const char c )
+static void ns9750_serial_putc(const char c)
{
if (c == '\n')
serial_putc( '\r' );
* @Descr: writes non-zero string to the FIFO.
***********************************************************************/
-void serial_puts( const char *s )
+static void ns9750_serial_puts(const char *s)
{
while (*s) {
serial_putc( *s++ );
* @Descr: performs only 8bit accesses to the FIFO. No error handling
***********************************************************************/
-int serial_getc( void )
+static int ns9750_serial_getc(void)
{
int i;
* unCharCache and the numbers of characters in cCharsAvailable
***********************************************************************/
-int serial_tstc( void )
+static int ns9750_serial_tstc(void)
{
unsigned int unRegCache;
return 0;
}
-void serial_setbrg( void )
+static void ns9750_serial_setbrg(void)
{
*get_ser_reg_addr_channel( NS9750_SER_BITRATE, CONSOLE ) =
calcBitrateRegister();
{
return NS9750_SER_RX_CHAR_TIMER_TRUN;
}
+
+static struct serial_device ns9750_serial_drv = {
+ .name = "ns9750_serial",
+ .start = ns9750_serial_init,
+ .stop = NULL,
+ .setbrg = ns9750_serial_setbrg,
+ .putc = ns9750_serial_putc,
+ .puts = ns9750_serial_puts,
+ .getc = ns9750_serial_getc,
+ .tstc = ns9750_serial_tstc,
+};
+
+void ns9750_serial_initialize(void)
+{
+ serial_register(&ns9750_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &ns9750_serial_drv;
+}
/* Everything's already setup for fixed-baud PTF assignment*/
-void serial_setbrg (void)
+static void oc_serial_setbrg(void)
{
int n, k;
const unsigned max_uns = 0xFFFFFFFF;
#else
-void serial_setbrg (void)
+static void oc_serial_setbrg(void)
{
int n, k;
const unsigned max_uns = 0xFFFFFFFF;
#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */
-int serial_init (void)
+static int oc_serial_init(void)
{
unsigned action,control;
/*-----------------------------------------------------------------------
* YANU CONSOLE
*---------------------------------------------------------------------*/
-void serial_putc (char c)
+static void oc_serial_putc(char c)
{
int tx_chars;
unsigned status;
writel((unsigned char)c, &uart->data);
}
-void serial_puts (const char *s)
+static void oc_serial_puts(const char *s)
{
while (*s != 0) {
serial_putc (*s++);
}
-int serial_tstc(void)
+static int oc_serial_tstc(void)
{
unsigned status ;
((1 << YANU_RFIFO_CHARS_N) - 1)) > 0);
}
-int serial_getc (void)
+statoc int oc_serial_getc(void)
{
while (serial_tstc() == 0)
WATCHDOG_RESET ();
return(readl(&uart->data) & YANU_DATA_CHAR_MASK);
}
+
+static struct serial_device oc_serial_drv = {
+ .name = "oc_serial",
+ .start = oc_serial_init,
+ .stop = NULL,
+ .setbrg = oc_serial_setbrg,
+ .putc = oc_serial_putc,
+ .puts = oc_serial_puts,
+ .getc = oc_serial_getc,
+ .tstc = oc_serial_tstc,
+};
+
+void oc_serial_initialize(void)
+{
+ serial_register(&oc_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &oc_serial_drv;
+}
}
-void serial_setbrg (void)
+static void s3c4510b_serial_setbrg(void)
{
UART_LINE_CTRL ulctrl;
UART_CTRL uctrl;
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
-int serial_init (void)
+static int s3c4510b_serial_init(void)
{
#if CONFIG_SERIAL1 == 1
/*
* Output a single byte to the serial port.
*/
-void serial_putc (const char c)
+static void s3c4510_serial_putc(const char c)
{
/* wait for room in the transmit FIFO */
while( !uart->m_stat.bf.txBufEmpty);
* Test if an input byte is ready from the serial port. Returns non-zero on
* success, 0 otherwise.
*/
-int serial_tstc (void)
+static int s3c4510b_serial_tstc(void)
{
return uart->m_stat.bf.rxReady;
}
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_getc (void)
+static int s3c4510b_serial_getc(void)
{
int rv;
}
}
-void serial_puts (const char *s)
+static void s3c4510b_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
uart->m_ctrl.bf.sendBreak = 0;
}
+
+static struct serial_device s3c4510b_serial_drv = {
+ .name = "s3c4510b_serial",
+ .start = s3c4510b_serial_init,
+ .stop = NULL,
+ .setbrg = s3c4510b_serial_setbrg,
+ .putc = s3c4510b_serial_putc,
+ .puts = s3c4510b_serial_puts,
+ .getc = s3c4510b_serial_getc,
+ .tstc = s3c4510b_serial_tstc,
+};
+
+void s3c4510b_serial_initialize(void)
+{
+ serial_register(&s3c4510b_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &s3c4510b_serial_drv;
+}
0xffdf,
};
-void serial_setbrg(void)
+static void s3c64xx_serial_setbrg(void)
{
s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
u32 pclk = get_PCLK();
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
-int serial_init(void)
+static int s3c64xx_serial_init(void)
{
s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_getc(void)
+static int s3c64xx_serial_getc(void)
{
s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
/*
* Output a single byte to the serial port.
*/
-void serial_putc(const char c)
+static void s3c64xx_serial_putc(const char c)
{
s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
/*
* Test whether a character is in the RX buffer
*/
-int serial_tstc(void)
+static int s3c64xx_serial_tstc(void)
{
s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
return uart->UTRSTAT & 0x1;
}
-void serial_puts(const char *s)
+static void s3c64xx_serial_puts(const char *s)
{
while (*s)
serial_putc(*s++);
}
+
+static struct serial_device s3c64xx_serial_drv = {
+ .name = "s3c64xx_serial",
+ .start = s3c64xx_serial_init,
+ .stop = NULL,
+ .setbrg = s3c64xx_serial_setbrg,
+ .putc = s3c64xx_serial_putc,
+ .puts = s3c64xx_serial_puts,
+ .getc = s3c64xx_serial_getc,
+ .tstc = s3c64xx_serial_tstc,
+};
+
+void s3c64xx_serial_initialize(void)
+{
+ serial_register(&s3c64xx_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &s3c64xx_serial_drv;
+}
#include <common.h>
#include <os.h>
+#include <serial.h>
+#include <linux/compiler.h>
-int serial_init(void)
+static int sandbox_serial_init(void)
{
os_tty_raw(0);
return 0;
}
-void serial_setbrg(void)
+static void sandbox_serial_setbrg(void)
{
}
-void serial_putc(const char ch)
+static void sandbox_serial_putc(const char ch)
{
os_write(1, &ch, 1);
}
-void serial_puts(const char *str)
+static void sandbox_serial_puts(const char *str)
{
os_write(1, str, strlen(str));
}
-int serial_getc(void)
+static int sandbox_serial_getc(void)
{
char buf;
ssize_t count;
return count == 1 ? buf : 0;
}
-int serial_tstc(void)
+static int sandbox_serial_tstc(void)
{
return 0;
}
+
+static struct serial_device sandbox_serial_drv = {
+ .name = "sandbox_serial",
+ .start = sandbox_serial_init,
+ .stop = NULL,
+ .setbrg = sandbox_serial_setbrg,
+ .putc = sandbox_serial_putc,
+ .puts = sandbox_serial_puts,
+ .getc = sandbox_serial_getc,
+ .tstc = sandbox_serial_tstc,
+};
+
+void sandbox_serial_initialize(void)
+{
+ serial_register(&sandbox_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &sandbox_serial_drv;
+}
/*
- * (C) Copyright 2000
- * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*/
#include <common.h>
-#include <linux/compiler.h>
-
-#include <ns16550.h>
-#ifdef CONFIG_NS87308
-#include <ns87308.h>
-#endif
-
-#if defined (CONFIG_SERIAL_MULTI)
#include <serial.h>
-#endif
+#include <stdio_dev.h>
+#include <post.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
-#if !defined(CONFIG_CONS_INDEX)
-#if defined (CONFIG_SERIAL_MULTI)
-/* with CONFIG_SERIAL_MULTI we might have no console
- * on these devices
- */
-#else
-#error "No console index specified."
-#endif /* CONFIG_SERIAL_MULTI */
-#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 4)
-#error "Invalid console index value."
-#endif
+static struct serial_device *serial_devices;
+static struct serial_device *serial_current;
-#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1)
-#error "Console port 1 defined but not configured."
-#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2)
-#error "Console port 2 defined but not configured."
-#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3)
-#error "Console port 3 defined but not configured."
-#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4)
-#error "Console port 4 defined but not configured."
-#endif
+static void serial_null(void)
+{
+}
-/* Note: The port number specified in the functions is 1 based.
- * the array is 0 based.
- */
-static NS16550_t serial_ports[4] = {
-#ifdef CONFIG_SYS_NS16550_COM1
- (NS16550_t)CONFIG_SYS_NS16550_COM1,
-#else
- NULL,
-#endif
-#ifdef CONFIG_SYS_NS16550_COM2
- (NS16550_t)CONFIG_SYS_NS16550_COM2,
-#else
- NULL,
-#endif
-#ifdef CONFIG_SYS_NS16550_COM3
- (NS16550_t)CONFIG_SYS_NS16550_COM3,
-#else
- NULL,
-#endif
-#ifdef CONFIG_SYS_NS16550_COM4
- (NS16550_t)CONFIG_SYS_NS16550_COM4
-#else
- NULL
-#endif
-};
-
-#define PORT serial_ports[port-1]
-
-#if defined(CONFIG_SERIAL_MULTI)
-
-/* Multi serial device functions */
-#define DECLARE_ESERIAL_FUNCTIONS(port) \
- int eserial##port##_init (void) {\
- int clock_divisor; \
- clock_divisor = calc_divisor(serial_ports[port-1]); \
- NS16550_init(serial_ports[port-1], clock_divisor); \
- return(0);}\
- void eserial##port##_setbrg (void) {\
- serial_setbrg_dev(port);}\
- int eserial##port##_getc (void) {\
- return serial_getc_dev(port);}\
- int eserial##port##_tstc (void) {\
- return serial_tstc_dev(port);}\
- void eserial##port##_putc (const char c) {\
- serial_putc_dev(port, c);}\
- void eserial##port##_puts (const char *s) {\
- serial_puts_dev(port, s);}
-
-/* Serial device descriptor */
-#define INIT_ESERIAL_STRUCTURE(port, name) {\
- name,\
- eserial##port##_init,\
- NULL,\
- eserial##port##_setbrg,\
- eserial##port##_getc,\
- eserial##port##_tstc,\
- eserial##port##_putc,\
- eserial##port##_puts, }
-
-#endif /* CONFIG_SERIAL_MULTI */
-
-static int calc_divisor (NS16550_t port)
+#define serial_initfunc(name) \
+ void name(void) \
+ __attribute__((weak, alias("serial_null")));
+
+serial_initfunc(mpc8xx_serial_initialize);
+serial_initfunc(ns16550_serial_initialize);
+serial_initfunc(pxa_serial_initialize);
+serial_initfunc(s3c24xx_serial_initialize);
+serial_initfunc(s5p_serial_initialize);
+serial_initfunc(zynq_serial_initalize);
+serial_initfunc(bfin_serial_initialize);
+serial_initfunc(bfin_jtag_initialize);
+serial_initfunc(mpc512x_serial_initialize);
+serial_initfunc(uartlite_serial_initialize);
+serial_initfunc(au1x00_serial_initialize);
+serial_initfunc(asc_serial_initialize);
+serial_initfunc(jz_serial_initialize);
+serial_initfunc(mpc5xx_serial_initialize);
+serial_initfunc(mpc8220_serial_initialize);
+serial_initfunc(mpc8260_scc_serial_initialize);
+serial_initfunc(mpc8260_smc_serial_initialize);
+serial_initfunc(mpc85xx_serial_initialize);
+serial_initfunc(iop480_serial_initialize);
+serial_initfunc(leon2_serial_initialize);
+serial_initfunc(leon3_serial_initialize);
+serial_initfunc(marvell_serial_initialize);
+serial_initfunc(amirix_serial_initialize);
+serial_initfunc(bmw_serial_initialize);
+serial_initfunc(cogent_serial_initialize);
+serial_initfunc(cpci750_serial_initialize);
+serial_initfunc(evb64260_serial_initialize);
+serial_initfunc(ml2_serial_initialize);
+serial_initfunc(sconsole_serial_initialize);
+serial_initfunc(p3mx_serial_initialize);
+serial_initfunc(altera_jtag_serial_initialize);
+serial_initfunc(altera_serial_initialize);
+serial_initfunc(atmel_serial_initialize);
+serial_initfunc(lpc32xx_serial_initialize);
+serial_initfunc(mcf_serial_initialize);
+serial_initfunc(ns9750_serial_initialize);
+serial_initfunc(oc_serial_initialize);
+serial_initfunc(s3c4510b_serial_initialize);
+serial_initfunc(s3c64xx_serial_initialize);
+serial_initfunc(sandbox_serial_initialize);
+serial_initfunc(clps7111_serial_initialize);
+serial_initfunc(imx_serial_initialize);
+serial_initfunc(ixp_serial_initialize);
+serial_initfunc(ks8695_serial_initialize);
+serial_initfunc(lh7a40x_serial_initialize);
+serial_initfunc(lpc2292_serial_initialize);
+serial_initfunc(max3100_serial_initialize);
+serial_initfunc(mxc_serial_initialize);
+serial_initfunc(netarm_serial_initialize);
+serial_initfunc(pl01x_serial_initialize);
+serial_initfunc(s3c44b0_serial_initialize);
+serial_initfunc(sa1100_serial_initialize);
+serial_initfunc(sh_serial_initialize);
+
+void serial_register(struct serial_device *dev)
{
-#ifdef CONFIG_OMAP1510
- /* If can't cleanly clock 115200 set div to 1 */
- if ((CONFIG_SYS_NS16550_CLK == 12000000) && (gd->baudrate == 115200)) {
- port->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */
- return (1); /* return 1 for base divisor */
- }
- port->osc_12m_sel = 0; /* clear if previsouly set */
-#endif
-#ifdef CONFIG_OMAP1610
- /* If can't cleanly clock 115200 set div to 1 */
- if ((CONFIG_SYS_NS16550_CLK == 48000000) && (gd->baudrate == 115200)) {
- return (26); /* return 26 for base divisor */
- }
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+ if (dev->start)
+ dev->start += gd->reloc_off;
+ if (dev->stop)
+ dev->stop += gd->reloc_off;
+ if (dev->setbrg)
+ dev->setbrg += gd->reloc_off;
+ if (dev->getc)
+ dev->getc += gd->reloc_off;
+ if (dev->tstc)
+ dev->tstc += gd->reloc_off;
+ if (dev->putc)
+ dev->putc += gd->reloc_off;
+ if (dev->puts)
+ dev->puts += gd->reloc_off;
#endif
-#ifdef CONFIG_APTIX
-#define MODE_X_DIV 13
-#else
-#define MODE_X_DIV 16
-#endif
+ dev->next = serial_devices;
+ serial_devices = dev;
+}
- /* Compute divisor value. Normally, we should simply return:
- * CONFIG_SYS_NS16550_CLK) / MODE_X_DIV / gd->baudrate
- * but we need to round that value by adding 0.5.
- * Rounding is especially important at high baud rates.
- */
- return (CONFIG_SYS_NS16550_CLK + (gd->baudrate * (MODE_X_DIV / 2))) /
- (MODE_X_DIV * gd->baudrate);
+void serial_initialize(void)
+{
+ mpc8xx_serial_initialize();
+ ns16550_serial_initialize();
+ pxa_serial_initialize();
+ s3c24xx_serial_initialize();
+ s5p_serial_initialize();
+ mpc512x_serial_initialize();
+ bfin_serial_initialize();
+ bfin_jtag_initialize();
+ uartlite_serial_initialize();
+ zynq_serial_initalize();
+ au1x00_serial_initialize();
+ asc_serial_initialize();
+ jz_serial_initialize();
+ mpc5xx_serial_initialize();
+ mpc8220_serial_initialize();
+ mpc8260_scc_serial_initialize();
+ mpc8260_smc_serial_initialize();
+ mpc85xx_serial_initialize();
+ iop480_serial_initialize();
+ leon2_serial_initialize();
+ leon3_serial_initialize();
+ marvell_serial_initialize();
+ amirix_serial_initialize();
+ bmw_serial_initialize();
+ cogent_serial_initialize();
+ cpci750_serial_initialize();
+ evb64260_serial_initialize();
+ ml2_serial_initialize();
+ sconsole_serial_initialize();
+ p3mx_serial_initialize();
+ altera_jtag_serial_initialize();
+ altera_serial_initialize();
+ atmel_serial_initialize();
+ lpc32xx_serial_initialize();
+ mcf_serial_initialize();
+ ns9750_serial_initialize();
+ oc_serial_initialize();
+ s3c4510b_serial_initialize();
+ s3c64xx_serial_initialize();
+ sandbox_serial_initialize();
+ clps7111_serial_initialize();
+ imx_serial_initialize();
+ ixp_serial_initialize();
+ ks8695_serial_initialize();
+ lh7a40x_serial_initialize();
+ lpc2292_serial_initialize();
+ max3100_serial_initialize();
+ mxc_serial_initialize();
+ netarm_serial_initialize();
+ pl01x_serial_initialize();
+ s3c44b0_serial_initialize();
+ sa1100_serial_initialize();
+ sh_serial_initialize();
+
+ serial_assign(default_serial_console()->name);
}
-#if !defined(CONFIG_SERIAL_MULTI)
-int serial_init (void)
+void serial_stdio_init(void)
{
- int clock_divisor;
+ struct stdio_dev dev;
+ struct serial_device *s = serial_devices;
-#ifdef CONFIG_NS87308
- initialise_ns87308();
-#endif
+ while (s) {
+ memset(&dev, 0, sizeof(dev));
-#ifdef CONFIG_SYS_NS16550_COM1
- clock_divisor = calc_divisor(serial_ports[0]);
- NS16550_init(serial_ports[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_NS16550_COM2
- clock_divisor = calc_divisor(serial_ports[1]);
- NS16550_init(serial_ports[1], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_NS16550_COM3
- clock_divisor = calc_divisor(serial_ports[2]);
- NS16550_init(serial_ports[2], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_NS16550_COM4
- clock_divisor = calc_divisor(serial_ports[3]);
- NS16550_init(serial_ports[3], clock_divisor);
-#endif
+ strcpy(dev.name, s->name);
+ dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
- return (0);
-}
-#endif
+ dev.start = s->start;
+ dev.stop = s->stop;
+ dev.putc = s->putc;
+ dev.puts = s->puts;
+ dev.getc = s->getc;
+ dev.tstc = s->tstc;
-void
-_serial_putc(const char c,const int port)
-{
- if (c == '\n')
- NS16550_putc(PORT, '\r');
+ stdio_register(&dev);
- NS16550_putc(PORT, c);
+ s = s->next;
+ }
}
-void
-_serial_putc_raw(const char c,const int port)
+int serial_assign(const char *name)
{
- NS16550_putc(PORT, c);
-}
+ struct serial_device *s;
-void
-_serial_puts (const char *s,const int port)
-{
- while (*s) {
- _serial_putc (*s++,port);
+ for (s = serial_devices; s; s = s->next) {
+ if (strcmp(s->name, name) == 0) {
+ serial_current = s;
+ return 0;
+ }
}
-}
-
-int
-_serial_getc(const int port)
-{
- return NS16550_getc(PORT);
+ return 1;
}
-int
-_serial_tstc(const int port)
+void serial_reinit_all(void)
{
- return NS16550_tstc(PORT);
+ struct serial_device *s;
+
+ for (s = serial_devices; s; s = s->next)
+ s->start();
}
-void
-_serial_setbrg (const int port)
+static struct serial_device *get_current(void)
{
- int clock_divisor;
+ struct serial_device *dev;
- clock_divisor = calc_divisor(PORT);
- NS16550_reinit(PORT, clock_divisor);
-}
+ if (!(gd->flags & GD_FLG_RELOC) || !serial_current) {
+ dev = default_serial_console();
-#if defined(CONFIG_SERIAL_MULTI)
-static inline void
-serial_putc_dev(unsigned int dev_index,const char c)
-{
- _serial_putc(c,dev_index);
-}
+ /* We must have a console device */
+ if (!dev) {
+#ifdef CONFIG_SPL_BUILD
+ puts("Cannot find console\n");
+ hang();
#else
-void
-serial_putc(const char c)
-{
- _serial_putc(c,CONFIG_CONS_INDEX);
-}
+ panic("Cannot find console\n");
#endif
-
-#if defined(CONFIG_SERIAL_MULTI)
-static inline void
-serial_putc_raw_dev(unsigned int dev_index,const char c)
-{
- _serial_putc_raw(c,dev_index);
-}
-#else
-void
-serial_putc_raw(const char c)
-{
- _serial_putc_raw(c,CONFIG_CONS_INDEX);
+ }
+ } else
+ dev = serial_current;
+ return dev;
}
-#endif
-#if defined(CONFIG_SERIAL_MULTI)
-static inline void
-serial_puts_dev(unsigned int dev_index,const char *s)
-{
- _serial_puts(s,dev_index);
-}
-#else
-void
-serial_puts(const char *s)
+int serial_init(void)
{
- _serial_puts(s,CONFIG_CONS_INDEX);
+ return get_current()->start();
}
-#endif
-#if defined(CONFIG_SERIAL_MULTI)
-static inline int
-serial_getc_dev(unsigned int dev_index)
+void serial_setbrg(void)
{
- return _serial_getc(dev_index);
+ get_current()->setbrg();
}
-#else
-int
-serial_getc(void)
-{
- return _serial_getc(CONFIG_CONS_INDEX);
-}
-#endif
-#if defined(CONFIG_SERIAL_MULTI)
-static inline int
-serial_tstc_dev(unsigned int dev_index)
+int serial_getc(void)
{
- return _serial_tstc(dev_index);
+ return get_current()->getc();
}
-#else
-int
-serial_tstc(void)
+
+int serial_tstc(void)
{
- return _serial_tstc(CONFIG_CONS_INDEX);
+ return get_current()->tstc();
}
-#endif
-#if defined(CONFIG_SERIAL_MULTI)
-static inline void
-serial_setbrg_dev(unsigned int dev_index)
+void serial_putc(const char c)
{
- _serial_setbrg(dev_index);
+ get_current()->putc(c);
}
-#else
-void
-serial_setbrg(void)
+
+void serial_puts(const char *s)
{
- _serial_setbrg(CONFIG_CONS_INDEX);
+ get_current()->puts(s);
}
-#endif
-#if defined(CONFIG_SERIAL_MULTI)
-
-DECLARE_ESERIAL_FUNCTIONS(1);
-struct serial_device eserial1_device =
- INIT_ESERIAL_STRUCTURE(1, "eserial0");
-DECLARE_ESERIAL_FUNCTIONS(2);
-struct serial_device eserial2_device =
- INIT_ESERIAL_STRUCTURE(2, "eserial1");
-DECLARE_ESERIAL_FUNCTIONS(3);
-struct serial_device eserial3_device =
- INIT_ESERIAL_STRUCTURE(3, "eserial2");
-DECLARE_ESERIAL_FUNCTIONS(4);
-struct serial_device eserial4_device =
- INIT_ESERIAL_STRUCTURE(4, "eserial3");
-
-__weak struct serial_device *default_serial_console(void)
+#if CONFIG_POST & CONFIG_SYS_POST_UART
+static const int bauds[] = CONFIG_SYS_BAUDRATE_TABLE;
+
+/* Mark weak until post/cpu/.../uart.c migrate over */
+__weak
+int uart_post_test(int flags)
{
-#if CONFIG_CONS_INDEX == 1
- return &eserial1_device;
-#elif CONFIG_CONS_INDEX == 2
- return &eserial2_device;
-#elif CONFIG_CONS_INDEX == 3
- return &eserial3_device;
-#elif CONFIG_CONS_INDEX == 4
- return &eserial4_device;
-#else
-#error "Bad CONFIG_CONS_INDEX."
-#endif
-}
+ unsigned char c;
+ int ret, saved_baud, b;
+ struct serial_device *saved_dev, *s;
+ bd_t *bd = gd->bd;
+
+ /* Save current serial state */
+ ret = 0;
+ saved_dev = serial_current;
+ saved_baud = bd->bi_baudrate;
+
+ for (s = serial_devices; s; s = s->next) {
+ /* If this driver doesn't support loop back, skip it */
+ if (!s->loop)
+ continue;
+
+ /* Test the next device */
+ serial_current = s;
+
+ ret = serial_init();
+ if (ret)
+ goto done;
+
+ /* Consume anything that happens to be queued */
+ while (serial_tstc())
+ serial_getc();
+
+ /* Enable loop back */
+ s->loop(1);
+
+ /* Test every available baud rate */
+ for (b = 0; b < ARRAY_SIZE(bauds); ++b) {
+ bd->bi_baudrate = bauds[b];
+ serial_setbrg();
+
+ /*
+ * Stick to printable chars to avoid issues:
+ * - terminal corruption
+ * - serial program reacting to sequences and sending
+ * back random extra data
+ * - most serial drivers add in extra chars (like \r\n)
+ */
+ for (c = 0x20; c < 0x7f; ++c) {
+ /* Send it out */
+ serial_putc(c);
+
+ /* Make sure it's the same one */
+ ret = (c != serial_getc());
+ if (ret) {
+ s->loop(0);
+ goto done;
+ }
+
+ /* Clean up the output in case it was sent */
+ serial_putc('\b');
+ ret = ('\b' != serial_getc());
+ if (ret) {
+ s->loop(0);
+ goto done;
+ }
+ }
+ }
+
+ /* Disable loop back */
+ s->loop(0);
+
+ /* XXX: There is no serial_stop() !? */
+ if (s->stop)
+ s->stop();
+ }
+
+ done:
+ /* Restore previous serial state */
+ serial_current = saved_dev;
+ bd->bi_baudrate = saved_baud;
+ serial_reinit_all();
+ serial_setbrg();
-#endif /* CONFIG_SERIAL_MULTI */
+ return ret;
+}
+#endif
DECLARE_GLOBAL_DATA_PTR;
-void serial_setbrg (void)
+static void clps7111_serial_setbrg(void)
{
unsigned int reg = 0;
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
-int serial_init (void)
+static int clps7111_serial_init(void)
{
serial_setbrg ();
/*
* Output a single byte to the serial port.
*/
-void serial_putc (const char c)
+static void clps7111_serial_putc(const char c)
{
int tmo;
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_tstc (void)
+static int clps7111_serial_tstc(void)
{
return !(IO_SYSFLG1 & SYSFLG1_URXFE);
}
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_getc (void)
+static int clps7111_serial_getc(void)
{
while (IO_SYSFLG1 & SYSFLG1_URXFE);
return IO_UARTDR1 & 0xff;
}
-void
-serial_puts (const char *s)
+static void clps7111_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
+
+static struct serial_device clps7111_serial_drv = {
+ .name = "clps7111_serial",
+ .start = clps7111_serial_init,
+ .stop = NULL,
+ .setbrg = clps7111_serial_setbrg,
+ .putc = clps7111_serial_putc,
+ .puts = clps7111_serial_puts,
+ .getc = clps7111_serial_getc,
+ .tstc = clps7111_serial_tstc,
+};
+
+void clps7111_serial_initialize(void)
+{
+ serial_register(&clps7111_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &clps7111_serial_drv;
+}
#include <common.h>
#include <asm/arch/imx-regs.h>
+#include <serial.h>
+#include <linux/compiler.h>
#if defined CONFIG_IMX_SERIAL1
#define UART_BASE IMX_UART1_BASE
DECLARE_GLOBAL_DATA_PTR;
-void serial_setbrg (void)
+static void imx_serial_setbrg(void)
{
serial_init();
}
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
-int serial_init (void)
+static int imx_serial_init(void)
{
volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
unsigned int ufcr_rfdiv;
* otherwise. When the function is successful, the character read is
* written into its argument c.
*/
-int serial_getc (void)
+static int imx_serial_getc(void)
{
volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
unsigned char ch;
/*
* Output a single byte to the serial port.
*/
-void serial_putc (const char c)
+static void imx_serial_putc(const char c)
{
volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
/*
* Test whether a character is in the RX buffer
*/
-int serial_tstc (void)
+static int imx_serial_tstc(void)
{
volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
return 1;
}
-void
-serial_puts (const char *s)
+static void imx_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
+
+static struct serial_device imx_serial_drv = {
+ .name = "imx_serial",
+ .start = imx_serial_init,
+ .stop = NULL,
+ .setbrg = imx_serial_setbrg,
+ .putc = imx_serial_putc,
+ .puts = imx_serial_puts,
+ .getc = imx_serial_getc,
+ .tstc = imx_serial_tstc,
+};
+
+void imx_serial_initialize(void)
+{
+ serial_register(&imx_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &imx_serial_drv;
+}
#include <common.h>
#include <asm/arch/ixp425.h>
#include <watchdog.h>
+#include <serial.h>
+#include <linux/compiler.h>
/*
* 14.7456 MHz
DECLARE_GLOBAL_DATA_PTR;
-void serial_setbrg (void)
+static void ixp_serial_setbrg(void)
{
unsigned int quot = 0;
int uart = CONFIG_SYS_IXP425_CONSOLE;
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
-int serial_init (void)
+static int ixp_serial_init(void)
{
serial_setbrg ();
/*
* Output a single byte to the serial port.
*/
-void serial_putc (const char c)
+static void ixp_serial_putc(const char c)
{
/* wait for room in the tx FIFO on UART */
while ((LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_TEMT) == 0)
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_tstc (void)
+static int ixp_serial_tstc(void)
{
return LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR;
}
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_getc (void)
+static int ixp_serial_getc(void)
{
while (!(LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR))
WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */
return (char) RBR(CONFIG_SYS_IXP425_CONSOLE) & 0xff;
}
-void
-serial_puts (const char *s)
+static void ixp_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
+
+static struct serial_device ixp_serial_drv = {
+ .name = "ixp_serial",
+ .start = ixp_serial_init,
+ .stop = NULL,
+ .setbrg = ixp_serial_setbrg,
+ .putc = ixp_serial_putc,
+ .puts = ixp_serial_puts,
+ .getc = ixp_serial_getc,
+ .tstc = ixp_serial_tstc,
+};
+
+void ixp_serial_initialize(void)
+{
+ serial_register(&ixp_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &ixp_serial_drv;
+}
#include <common.h>
#include <asm/arch/platform.h>
+#include <serial.h>
+#include <linux/compiler.h>
#ifndef CONFIG_SERIAL1
#error "Bad: you didn't configure serial ..."
int serial_console = 1;
-void serial_setbrg(void)
+static void ks8695_serial_setbrg(void)
{
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
uartp->LCR = KS8695_UART_LINEC_WLEN8;
}
-int serial_init(void)
+static int ks8695_serial_init(void)
{
serial_console = 1;
serial_setbrg();
return 0;
}
-void serial_raw_putc(const char c)
+static void ks8695_serial_raw_putc(const char c)
{
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
int i;
uartp->TX = c;
}
-void serial_putc(const char c)
+static void ks8695_serial_putc(const char c)
{
if (serial_console) {
- serial_raw_putc(c);
+ ks8695_serial_raw_putc(c);
if (c == '\n')
- serial_raw_putc('\r');
+ ks8695_serial_raw_putc('\r');
}
}
-int serial_tstc(void)
+static int ks8695_serial_tstc(void)
{
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
if (serial_console)
return 0;
}
-void serial_puts(const char *s)
+static void ks8695_serial_puts(const char *s)
{
char c;
while ((c = *s++) != 0)
serial_putc(c);
}
-int serial_getc(void)
+static int ks8695_serial_getc(void)
{
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
;
return (uartp->RX);
}
+
+static struct serial_device ks8695_serial_drv = {
+ .name = "ks8695_serial",
+ .start = ks8695_serial_init,
+ .stop = NULL,
+ .setbrg = ks8695_serial_setbrg,
+ .putc = ks8695_serial_putc,
+ .puts = ks8695_serial_puts,
+ .getc = ks8695_serial_getc,
+ .tstc = ks8695_serial_tstc,
+};
+
+void ks8695_serial_initialize(void)
+{
+ serial_register(&ks8695_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &ks8695_serial_drv;
+}
# error "No console configured ... "
#endif
-void serial_setbrg (void)
+static void lh7a40x_serial_setbrg(void)
{
lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
int i;
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
-int serial_init (void)
+static int lh7a40x_serial_init(void)
{
lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_getc (void)
+static int lh7a40x_serial_getc(void)
{
lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
/*
* Output a single byte to the serial port.
*/
-void serial_putc (const char c)
+static void lh7a40x_serial_putc(const char c)
{
lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
/*
* Test whether a character is in the RX buffer
*/
-int serial_tstc (void)
+static int lh7a40x_serial_tstc(void)
{
lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
return(!(uart->status & UART_RXFE));
}
-void
-serial_puts (const char *s)
+static void lh7a40x_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
+
+static struct serial_device lh7a40x_serial_drv = {
+ .name = "lh7a40x_serial",
+ .start = lh7a40x_serial_init,
+ .stop = NULL,
+ .setbrg = lh7a40x_serial_setbrg,
+ .putc = lh7a40x_serial_putc,
+ .puts = lh7a40x_serial_puts,
+ .getc = lh7a40x_serial_getc,
+ .tstc = lh7a40x_serial_tstc,
+};
+
+void lh7a40x_serial_initialize(void)
+{
+ serial_register(&lh7a40x_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &lh7a40x_serial_drv;
+}
DECLARE_GLOBAL_DATA_PTR;
-void serial_setbrg (void)
+static void lpc2292_serial_setbrg(void)
{
unsigned short divisor = 0;
PUT8(U0FCR, 1); /* Enable RX and TX FIFOs */
}
-int serial_init (void)
+static int lpc2292_serial_init(void)
{
unsigned long pinsel0;
return (0);
}
-void serial_putc (const char c)
+static void lpc2292_serial_putc(const char c)
{
if (c == '\n')
{
PUT8(U0THR, c);
}
-int serial_getc (void)
+static int lpc2292_serial_getc(void)
{
while((GET8(U0LSR) & 1) == 0);
return GET8(U0RBR);
}
-void
-serial_puts (const char *s)
+static void lpc2292_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
}
/* Test if there is a byte to read */
-int serial_tstc (void)
+static int lpc2292_serial_tstc(void)
{
return (GET8(U0LSR) & 1);
}
+
+static struct serial_device lpc2292_serial_drv = {
+ .name = "lpc2292_serial",
+ .start = lpc2292_serial_init,
+ .stop = NULL,
+ .setbrg = lpc2292_serial_setbrg,
+ .putc = lpc2292_serial_putc,
+ .puts = lpc2292_serial_puts,
+ .getc = lpc2292_serial_getc,
+ .tstc = lpc2292_serial_tstc,
+};
+
+void lpc2292_serial_initialize(void)
+{
+ serial_register(&lpc2292_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &lpc2292_serial_drv;
+}
#include <common.h>
#include <watchdog.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
static int rxfifo_out;
static unsigned char rxfifo_buf[16];
-static void max3100_putc(int c)
+static void max3100_serial_putc_raw(int c)
{
unsigned int rx;
}
}
-static int max3100_getc(void)
+static int max3100_serial_getc(void)
{
int c;
unsigned int rx;
return c;
}
-static int max3100_tstc(void)
+static int max3100_serial_tstc(void)
{
unsigned int rx;
return 1;
}
-int serial_init(void)
+static int max3100_serial_init(void)
{
unsigned int wconf, rconf;
int i;
return (0);
}
-void serial_putc(const char c)
+static void max3100_serial_putc(const char c)
{
if (c == '\n')
- max3100_putc('\r');
+ max3100_serial_putc_raw('\r');
- max3100_putc(c);
+ max3100_serial_putc_raw(c);
}
-void serial_puts(const char *s)
+static void max3100_serial_puts(const char *s)
{
while (*s)
- serial_putc (*s++);
+ max3100_serial_putc_raw(*s++);
}
-int serial_getc(void)
+static void max3100_serial_setbrg(void)
{
- return max3100_getc();
}
-int serial_tstc(void)
+static struct serial_device max3100_serial_drv = {
+ .name = "max3100_serial",
+ .start = max3100_serial_init,
+ .stop = NULL,
+ .setbrg = max3100_serial_setbrg,
+ .putc = max3100_serial_putc,
+ .puts = max3100_serial_puts,
+ .getc = max3100_serial_getc,
+ .tstc = max3100_serial_tstc,
+};
+
+void max3100_serial_initialize(void)
{
- return max3100_tstc();
+ serial_register(&max3100_serial_drv);
}
-/* XXX WTF? */
-void serial_setbrg(void)
+__weak struct serial_device *default_serial_console(void)
{
+ return &max3100_serial_drv;
}
#include <watchdog.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
+#include <serial.h>
+#include <linux/compiler.h>
#define __REG(x) (*((volatile u32 *)(x)))
#define UART_PHYS CONFIG_MXC_UART_BASE
-#ifdef CONFIG_SERIAL_MULTI
-#warning "MXC driver does not support MULTI serials."
-#endif
-
/* Register definitions */
#define URXD 0x0 /* Receiver Register */
#define UTXD 0x40 /* Transmitter Register */
DECLARE_GLOBAL_DATA_PTR;
-void serial_setbrg (void)
+static void mxc_serial_setbrg(void)
{
u32 clk = imx_get_uartclk();
}
-int serial_getc (void)
+static int mxc_serial_getc(void)
{
while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
WATCHDOG_RESET();
return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */
}
-void serial_putc (const char c)
+static void mxc_serial_putc(const char c)
{
__REG(UART_PHYS + UTXD) = c;
/*
* Test whether a character is in the RX buffer
*/
-int serial_tstc (void)
+static int mxc_serial_tstc(void)
{
/* If receive fifo is empty, return false */
if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
return 1;
}
-void
-serial_puts (const char *s)
+static void mxc_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
-int serial_init (void)
+static int mxc_serial_init(void)
{
__REG(UART_PHYS + UCR1) = 0x0;
__REG(UART_PHYS + UCR2) = 0x0;
return 0;
}
+
+static struct serial_device mxc_serial_drv = {
+ .name = "mxc_serial",
+ .start = mxc_serial_init,
+ .stop = NULL,
+ .setbrg = mxc_serial_setbrg,
+ .putc = mxc_serial_putc,
+ .puts = mxc_serial_puts,
+ .getc = mxc_serial_getc,
+ .tstc = mxc_serial_tstc,
+};
+
+void mxc_serial_initialize(void)
+{
+ serial_register(&mxc_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &mxc_serial_drv;
+}
/*
* Setup both serial i/f with given baudrate
*/
-void serial_setbrg (void)
+static void netarm_serial_setbrg(void)
{
/* set 0 ... make sure pins are configured for serial */
#if !defined(CONFIG_NETARM_NS7520)
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
-int serial_init (void)
+static int netarm_serial_init(void)
{
serial_setbrg ();
return 0;
/*
* Output a single byte to the serial port.
*/
-void serial_putc (const char c)
+static void netarm_serial_putc(const char c)
{
volatile unsigned char *fifo;
* Test of a single byte from the serial port. Returns 1 on success, 0
* otherwise.
*/
-int serial_tstc(void)
+static int netarm_serial_tstc(void)
{
return serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY;
}
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise.
*/
-int serial_getc (void)
+static int netarm_serial_getc(void)
{
unsigned int ch_uint;
volatile unsigned int *fifo;
return ch_uint & 0xff;
}
-void serial_puts (const char *s)
+static void netarm_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
+
+static struct serial_device netarm_serial_drv = {
+ .name = "netarm_serial",
+ .start = netarm_serial_init,
+ .stop = NULL,
+ .setbrg = netarm_serial_setbrg,
+ .putc = netarm_serial_putc,
+ .puts = netarm_serial_puts,
+ .getc = netarm_serial_getc,
+ .tstc = netarm_serial_tstc,
+};
+
+void netarm_serial_initialize(void)
+{
+ serial_register(&netarm_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &netarm_serial_drv;
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/compiler.h>
+
+#include <ns16550.h>
+#ifdef CONFIG_NS87308
+#include <ns87308.h>
+#endif
+
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !defined(CONFIG_CONS_INDEX)
+#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 4)
+#error "Invalid console index value."
+#endif
+
+#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1)
+#error "Console port 1 defined but not configured."
+#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2)
+#error "Console port 2 defined but not configured."
+#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3)
+#error "Console port 3 defined but not configured."
+#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4)
+#error "Console port 4 defined but not configured."
+#endif
+
+/* Note: The port number specified in the functions is 1 based.
+ * the array is 0 based.
+ */
+static NS16550_t serial_ports[4] = {
+#ifdef CONFIG_SYS_NS16550_COM1
+ (NS16550_t)CONFIG_SYS_NS16550_COM1,
+#else
+ NULL,
+#endif
+#ifdef CONFIG_SYS_NS16550_COM2
+ (NS16550_t)CONFIG_SYS_NS16550_COM2,
+#else
+ NULL,
+#endif
+#ifdef CONFIG_SYS_NS16550_COM3
+ (NS16550_t)CONFIG_SYS_NS16550_COM3,
+#else
+ NULL,
+#endif
+#ifdef CONFIG_SYS_NS16550_COM4
+ (NS16550_t)CONFIG_SYS_NS16550_COM4
+#else
+ NULL
+#endif
+};
+
+#define PORT serial_ports[port-1]
+
+/* Multi serial device functions */
+#define DECLARE_ESERIAL_FUNCTIONS(port) \
+ int eserial##port##_init (void) {\
+ int clock_divisor; \
+ clock_divisor = calc_divisor(serial_ports[port-1]); \
+ NS16550_init(serial_ports[port-1], clock_divisor); \
+ return(0);}\
+ void eserial##port##_setbrg (void) {\
+ serial_setbrg_dev(port);}\
+ int eserial##port##_getc (void) {\
+ return serial_getc_dev(port);}\
+ int eserial##port##_tstc (void) {\
+ return serial_tstc_dev(port);}\
+ void eserial##port##_putc (const char c) {\
+ serial_putc_dev(port, c);}\
+ void eserial##port##_puts (const char *s) {\
+ serial_puts_dev(port, s);}
+
+/* Serial device descriptor */
+#define INIT_ESERIAL_STRUCTURE(port, __name) { \
+ .name = __name, \
+ .start = eserial##port##_init, \
+ .stop = NULL, \
+ .setbrg = eserial##port##_setbrg, \
+ .getc = eserial##port##_getc, \
+ .tstc = eserial##port##_tstc, \
+ .putc = eserial##port##_putc, \
+ .puts = eserial##port##_puts, \
+}
+
+static int calc_divisor (NS16550_t port)
+{
+#ifdef CONFIG_OMAP1510
+ /* If can't cleanly clock 115200 set div to 1 */
+ if ((CONFIG_SYS_NS16550_CLK == 12000000) && (gd->baudrate == 115200)) {
+ port->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */
+ return (1); /* return 1 for base divisor */
+ }
+ port->osc_12m_sel = 0; /* clear if previsouly set */
+#endif
+#ifdef CONFIG_OMAP1610
+ /* If can't cleanly clock 115200 set div to 1 */
+ if ((CONFIG_SYS_NS16550_CLK == 48000000) && (gd->baudrate == 115200)) {
+ return (26); /* return 26 for base divisor */
+ }
+#endif
+
+#ifdef CONFIG_APTIX
+#define MODE_X_DIV 13
+#else
+#define MODE_X_DIV 16
+#endif
+
+ /* Compute divisor value. Normally, we should simply return:
+ * CONFIG_SYS_NS16550_CLK) / MODE_X_DIV / gd->baudrate
+ * but we need to round that value by adding 0.5.
+ * Rounding is especially important at high baud rates.
+ */
+ return (CONFIG_SYS_NS16550_CLK + (gd->baudrate * (MODE_X_DIV / 2))) /
+ (MODE_X_DIV * gd->baudrate);
+}
+
+void
+_serial_putc(const char c,const int port)
+{
+ if (c == '\n')
+ NS16550_putc(PORT, '\r');
+
+ NS16550_putc(PORT, c);
+}
+
+void
+_serial_putc_raw(const char c,const int port)
+{
+ NS16550_putc(PORT, c);
+}
+
+void
+_serial_puts (const char *s,const int port)
+{
+ while (*s) {
+ _serial_putc (*s++,port);
+ }
+}
+
+
+int
+_serial_getc(const int port)
+{
+ return NS16550_getc(PORT);
+}
+
+int
+_serial_tstc(const int port)
+{
+ return NS16550_tstc(PORT);
+}
+
+void
+_serial_setbrg (const int port)
+{
+ int clock_divisor;
+
+ clock_divisor = calc_divisor(PORT);
+ NS16550_reinit(PORT, clock_divisor);
+}
+
+static inline void
+serial_putc_dev(unsigned int dev_index,const char c)
+{
+ _serial_putc(c,dev_index);
+}
+
+static inline void
+serial_putc_raw_dev(unsigned int dev_index,const char c)
+{
+ _serial_putc_raw(c,dev_index);
+}
+
+static inline void
+serial_puts_dev(unsigned int dev_index,const char *s)
+{
+ _serial_puts(s,dev_index);
+}
+
+static inline int
+serial_getc_dev(unsigned int dev_index)
+{
+ return _serial_getc(dev_index);
+}
+
+static inline int
+serial_tstc_dev(unsigned int dev_index)
+{
+ return _serial_tstc(dev_index);
+}
+
+static inline void
+serial_setbrg_dev(unsigned int dev_index)
+{
+ _serial_setbrg(dev_index);
+}
+
+DECLARE_ESERIAL_FUNCTIONS(1);
+struct serial_device eserial1_device =
+ INIT_ESERIAL_STRUCTURE(1, "eserial0");
+DECLARE_ESERIAL_FUNCTIONS(2);
+struct serial_device eserial2_device =
+ INIT_ESERIAL_STRUCTURE(2, "eserial1");
+DECLARE_ESERIAL_FUNCTIONS(3);
+struct serial_device eserial3_device =
+ INIT_ESERIAL_STRUCTURE(3, "eserial2");
+DECLARE_ESERIAL_FUNCTIONS(4);
+struct serial_device eserial4_device =
+ INIT_ESERIAL_STRUCTURE(4, "eserial3");
+
+__weak struct serial_device *default_serial_console(void)
+{
+#if CONFIG_CONS_INDEX == 1
+ return &eserial1_device;
+#elif CONFIG_CONS_INDEX == 2
+ return &eserial2_device;
+#elif CONFIG_CONS_INDEX == 3
+ return &eserial3_device;
+#elif CONFIG_CONS_INDEX == 4
+ return &eserial4_device;
+#else
+#error "Bad CONFIG_CONS_INDEX."
+#endif
+}
+
+void ns16550_serial_initialize(void)
+{
+#if defined(CONFIG_SYS_NS16550_COM1)
+ serial_register(&eserial1_device);
+#endif
+#if defined(CONFIG_SYS_NS16550_COM2)
+ serial_register(&eserial2_device);
+#endif
+#if defined(CONFIG_SYS_NS16550_COM3)
+ serial_register(&eserial3_device);
+#endif
+#if defined(CONFIG_SYS_NS16550_COM4)
+ serial_register(&eserial4_device);
+#endif
+}
#include <common.h>
#include <watchdog.h>
#include <asm/io.h>
+#include <serial.h>
+#include <linux/compiler.h>
#include "serial_pl01x.h"
/*
#ifdef CONFIG_PL010_SERIAL
-int serial_init (void)
+static int pl01x_serial_init(void)
{
struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
unsigned int divisor;
#ifdef CONFIG_PL011_SERIAL
-int serial_init (void)
+static int pl01x_serial_init(void)
{
struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
unsigned int temp;
#endif /* CONFIG_PL011_SERIAL */
-void serial_putc (const char c)
+static void pl01x_serial_putc(const char c)
{
if (c == '\n')
pl01x_putc (CONSOLE_PORT, '\r');
pl01x_putc (CONSOLE_PORT, c);
}
-void serial_puts (const char *s)
+static void pl01x_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
-int serial_getc (void)
+static int pl01x_serial_getc(void)
{
return pl01x_getc (CONSOLE_PORT);
}
-int serial_tstc (void)
+static int pl01x_serial_tstc(void)
{
return pl01x_tstc (CONSOLE_PORT);
}
-void serial_setbrg (void)
+static void pl01x_serial_setbrg(void)
{
struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
WATCHDOG_RESET();
return !(readl(®s->fr) & UART_PL01x_FR_RXFE);
}
+
+static struct serial_device pl01x_serial_drv = {
+ .name = "pl01x_serial",
+ .start = pl01x_serial_init,
+ .stop = NULL,
+ .setbrg = pl01x_serial_setbrg,
+ .putc = pl01x_serial_putc,
+ .puts = pl01x_serial_puts,
+ .getc = pl01x_serial_getc,
+ .tstc = pl01x_serial_tstc,
+};
+
+void pl01x_serial_initialize(void)
+{
+ serial_register(&pl01x_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &pl01x_serial_drv;
+}
#include <asm/arch/pxa-regs.h>
#include <asm/arch/regs-uart.h>
#include <asm/io.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
#define HWUART_INDEX 0xff
#endif
-#ifndef CONFIG_SERIAL_MULTI
-#if defined(CONFIG_FFUART)
-#define UART_INDEX FFUART_INDEX
-#elif defined(CONFIG_BTUART)
-#define UART_INDEX BTUART_INDEX
-#elif defined(CONFIG_STUART)
-#define UART_INDEX STUART_INDEX
-#elif defined(CONFIG_HWUART)
-#define UART_INDEX HWUART_INDEX
-#else
-#error "Please select CONFIG_(FF|BT|ST|HW)UART in board config file."
-#endif
-#endif
-
-uint32_t pxa_uart_get_baud_divider(void)
+static uint32_t pxa_uart_get_baud_divider(void)
{
if (gd->baudrate == 1200)
return 768;
return 0;
}
-struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index)
+static struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index)
{
switch (uart_index) {
case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE;
}
}
-void pxa_uart_toggle_clock(uint32_t uart_index, int enable)
+static void pxa_uart_toggle_clock(uint32_t uart_index, int enable)
{
uint32_t clk_reg, clk_offset, reg;
#define pxa_uart_desc(uart) \
struct serial_device serial_##uart##_device = \
{ \
- "serial_"#uart, \
- uart##_init, \
- NULL, \
- uart##_setbrg, \
- uart##_getc, \
- uart##_tstc, \
- uart##_putc, \
- uart##_puts, \
+ .name = "serial_"#uart, \
+ .start = uart##_init, \
+ .stop = NULL, \
+ .setbrg = uart##_setbrg, \
+ .getc = uart##_getc, \
+ .tstc = uart##_tstc, \
+ .putc = uart##_putc, \
+ .puts = uart##_puts, \
};
#define pxa_uart_multi(uart, UART) \
pxa_uart_multi(btuart, BTUART)
#endif
-#ifndef CONFIG_SERIAL_MULTI
- pxa_uart(serial, UART)
+__weak struct serial_device *default_serial_console(void)
+{
+#if CONFIG_CONS_INDEX == 1
+ return &serial_hwuart_device;
+#elif CONFIG_CONS_INDEX == 2
+ return &serial_stuart_device;
+#elif CONFIG_CONS_INDEX == 3
+ return &serial_ffuart_device;
+#elif CONFIG_CONS_INDEX == 4
+ return &serial_btuart_device;
+#else
+#error "Bad CONFIG_CONS_INDEX."
#endif
+}
+
+void pxa_serial_initialize(void)
+{
+#if defined(CONFIG_FFUART)
+ serial_register(&serial_ffuart_device);
+#endif
+#if defined(CONFIG_BTUART)
+ serial_register(&serial_btuart_device);
+#endif
+#if defined(CONFIG_STUART)
+ serial_register(&serial_stuart_device);
+#endif
+}
#endif
#include <asm/io.h>
-
-#if defined(CONFIG_SERIAL_MULTI)
#include <serial.h>
/* Multi serial device functions */
serial_puts_dev(port, s); \
}
-#define INIT_S3C_SERIAL_STRUCTURE(port, name) { \
- name, \
- s3serial##port##_init, \
- NULL,\
- s3serial##port##_setbrg, \
- s3serial##port##_getc, \
- s3serial##port##_tstc, \
- s3serial##port##_putc, \
- s3serial##port##_puts, \
+#define INIT_S3C_SERIAL_STRUCTURE(port, __name) { \
+ .name = __name, \
+ .start = s3serial##port##_init, \
+ .stop = NULL, \
+ .setbrg = s3serial##port##_setbrg, \
+ .getc = s3serial##port##_getc, \
+ .tstc = s3serial##port##_tstc, \
+ .putc = s3serial##port##_putc, \
+ .puts = s3serial##port##_puts, \
}
-#endif /* CONFIG_SERIAL_MULTI */
-
#ifdef CONFIG_HWFLOW
static int hwflow;
#endif
/* Delay */ ;
}
-#if defined(CONFIG_SERIAL_MULTI)
static inline void serial_setbrg_dev(unsigned int dev_index)
{
_serial_setbrg(dev_index);
}
-#else
-void serial_setbrg(void)
-{
- _serial_setbrg(UART_NR);
-}
-#endif
-
/* Initialise the serial port. The settings are always 8 data bits, no parity,
* 1 stop bit, no start bits.
return (0);
}
-#if !defined(CONFIG_SERIAL_MULTI)
-/* Initialise the serial port. The settings are always 8 data bits, no parity,
- * 1 stop bit, no start bits.
- */
-int serial_init(void)
-{
- return serial_init_dev(UART_NR);
-}
-#endif
-
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
return readb(&uart->urxh) & 0xff;
}
-#if defined(CONFIG_SERIAL_MULTI)
static inline int serial_getc_dev(unsigned int dev_index)
{
return _serial_getc(dev_index);
}
-#else
-int serial_getc(void)
-{
- return _serial_getc(UART_NR);
-}
-#endif
#ifdef CONFIG_HWFLOW
int hwflow_onoff(int on)
serial_putc('\r');
}
-#if defined(CONFIG_SERIAL_MULTI)
static inline void serial_putc_dev(unsigned int dev_index, const char c)
{
_serial_putc(c, dev_index);
}
-#else
-void serial_putc(const char c)
-{
- _serial_putc(c, UART_NR);
-}
-#endif
-
/*
* Test whether a character is in the RX buffer
return readl(&uart->utrstat) & 0x1;
}
-#if defined(CONFIG_SERIAL_MULTI)
static inline int serial_tstc_dev(unsigned int dev_index)
{
return _serial_tstc(dev_index);
}
-#else
-int serial_tstc(void)
-{
- return _serial_tstc(UART_NR);
-}
-#endif
void _serial_puts(const char *s, const int dev_index)
{
}
}
-#if defined(CONFIG_SERIAL_MULTI)
static inline void serial_puts_dev(int dev_index, const char *s)
{
_serial_puts(s, dev_index);
}
-#else
-void serial_puts(const char *s)
-{
- _serial_puts(s, UART_NR);
-}
-#endif
-#if defined(CONFIG_SERIAL_MULTI)
DECLARE_S3C_SERIAL_FUNCTIONS(0);
struct serial_device s3c24xx_serial0_device =
INIT_S3C_SERIAL_STRUCTURE(0, "s3ser0");
#error "CONFIG_SERIAL? missing."
#endif
}
-#endif /* CONFIG_SERIAL_MULTI */
+
+void s3c24xx_serial_initialize(void)
+{
+ serial_register(&s3c24xx_serial0_device);
+ serial_register(&s3c24xx_serial1_device);
+ serial_register(&s3c24xx_serial2_device);
+}
}
-void serial_setbrg (void)
+static void s3c44b0_serial_setbrg(void)
{
u32 divisor = 0;
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
-int serial_init (void)
+static int s3c44b0_serial_init(void)
{
serial_setbrg ();
/*
* Output a single byte to the serial port.
*/
-void serial_putc (const char c)
+static void s3c44b0_serial_putc(const char c)
{
/* wait for room in the transmit FIFO */
while(!(UTRSTAT0 & 0x02));
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_tstc (void)
+static int s3c44b0_serial_tstc(void)
{
return (UTRSTAT0 & 0x01);
}
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_getc (void)
+static int s3c44b0_serial_getc(void)
{
int rv;
for(;;) {
- rv = serial_tstc();
+ rv = s3c44b0_serial_tstc();
if(rv > 0)
return URXH0;
}
}
-void
-serial_puts (const char *s)
+static void s3c44b0_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
+
+static struct serial_device s3c44b0_serial_drv = {
+ .name = "s3c44b0_serial",
+ .start = s3c44b0_serial_init,
+ .stop = NULL,
+ .setbrg = s3c44b0_serial_setbrg,
+ .putc = s3c44b0_serial_putc,
+ .puts = s3c44b0_serial_puts,
+ .getc = s3c44b0_serial_getc,
+ .tstc = s3c44b0_serial_tstc,
+};
+
+void s3c44b0_serial_initialize(void)
+{
+ serial_register(&s3c44b0_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &s3c44b0_serial_drv;
+}
void s5p_serial##port##_putc(const char c) { serial_putc_dev(c, port); } \
void s5p_serial##port##_puts(const char *s) { serial_puts_dev(s, port); }
-#define INIT_S5P_SERIAL_STRUCTURE(port, name) { \
- name, \
- s5p_serial##port##_init, \
- NULL, \
- s5p_serial##port##_setbrg, \
- s5p_serial##port##_getc, \
- s5p_serial##port##_tstc, \
- s5p_serial##port##_putc, \
- s5p_serial##port##_puts, }
+#define INIT_S5P_SERIAL_STRUCTURE(port, __name) { \
+ .name = __name, \
+ .start = s5p_serial##port##_init, \
+ .stop = NULL, \
+ .setbrg = s5p_serial##port##_setbrg, \
+ .getc = s5p_serial##port##_getc, \
+ .tstc = s5p_serial##port##_tstc, \
+ .putc = s5p_serial##port##_putc, \
+ .puts = s5p_serial##port##_puts, \
+}
DECLARE_S5P_SERIAL_FUNCTIONS(0);
struct serial_device s5p_serial0_device =
#error "CONFIG_SERIAL? missing."
#endif
}
+
+void s5p_serial_initialize(void)
+{
+ serial_register(&s5p_serial0_device);
+ serial_register(&s5p_serial1_device);
+ serial_register(&s5p_serial2_device);
+ serial_register(&s5p_serial3_device);
+}
#include <common.h>
#include <SA-1100.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
-void serial_setbrg (void)
+static void sa1100_serial_setbrg(void)
{
unsigned int reg = 0;
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
-int serial_init (void)
+static int sa1100_serial_init(void)
{
serial_setbrg ();
/*
* Output a single byte to the serial port.
*/
-void serial_putc (const char c)
+static void sa1100_serial_putc(const char c)
{
#ifdef CONFIG_SERIAL1
/* wait for room in the tx FIFO on SERIAL1 */
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_tstc (void)
+static int sa1100_serial_tstc(void)
{
#ifdef CONFIG_SERIAL1
return Ser1UTSR1 & UTSR1_RNE;
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_getc (void)
+static int sa1100_serial_getc(void)
{
#ifdef CONFIG_SERIAL1
while (!(Ser1UTSR1 & UTSR1_RNE));
#endif
}
-void
-serial_puts (const char *s)
+static void sa1100_serial_puts(const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
+
+static struct serial_device sa1100_serial_drv = {
+ .name = "sa1100_serial",
+ .start = sa1100_serial_init,
+ .stop = NULL,
+ .setbrg = sa1100_serial_setbrg,
+ .putc = sa1100_serial_putc,
+ .puts = sa1100_serial_puts,
+ .getc = sa1100_serial_getc,
+ .tstc = sa1100_serial_tstc,
+};
+
+void sa1100_serial_initialize(void)
+{
+ serial_register(&sa1100_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &sa1100_serial_drv;
+}
#include <asm/io.h>
#include <asm/processor.h>
#include "serial_sh.h"
+#include <serial.h>
+#include <linux/compiler.h>
#if defined(CONFIG_CONS_SCIF0)
# define SCIF_BASE SCIF0_BASE
.type = SCIF_BASE_PORT,
};
-void serial_setbrg(void)
+static void sh_serial_setbrg(void)
{
DECLARE_GLOBAL_DATA_PTR;
sci_out(&sh_sci, SCBRR, SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ));
}
-int serial_init(void)
+static int sh_serial_init(void)
{
sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
sci_out(&sh_sci, SCxSR, sci_in(&sh_sci, SCxSR) & ~SCxSR_TEND(&sh_sci));
}
-void serial_putc(const char c)
+static void sh_serial_putc(const char c)
{
if (c == '\n')
serial_raw_putc('\r');
serial_raw_putc(c);
}
-void serial_puts(const char *s)
+static void sh_serial_puts(const char *s)
{
char c;
while ((c = *s++) != 0)
serial_putc(c);
}
-int serial_tstc(void)
+static int sh_serial_tstc(void)
{
return serial_rx_fifo_level() ? 1 : 0;
}
return status & (SCIF_DR | SCxSR_RDxF(&sh_sci));
}
-int serial_getc(void)
+static int sh_serial_getc(void)
{
unsigned short status;
char ch;
handle_error();
return ch;
}
+
+static struct serial_device sh_serial_drv = {
+ .name = "sh_serial",
+ .start = sh_serial_init,
+ .stop = NULL,
+ .setbrg = sh_serial_setbrg,
+ .putc = sh_serial_putc,
+ .puts = sh_serial_puts,
+ .getc = sh_serial_getc,
+ .tstc = sh_serial_tstc,
+};
+
+void sh_serial_initialize(void)
+{
+ serial_register(&sh_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &sh_serial_drv;
+}
return -1;
}
-#if !defined(CONFIG_SERIAL_MULTI)
-int serial_init(void)
-{
- return uartlite_serial_init(0);
-}
-
-void serial_setbrg(void)
-{
- /* FIXME: what's this for? */
-}
-
-void serial_putc(const char c)
-{
- uartlite_serial_putc(c, 0);
-}
-
-void serial_puts(const char *s)
-{
- uartlite_serial_puts(s, 0);
-}
-
-int serial_getc(void)
-{
- return uartlite_serial_getc(0);
-}
-
-int serial_tstc(void)
-{
- return uartlite_serial_tstc(0);
-}
-#endif
-
-#if defined(CONFIG_SERIAL_MULTI)
/* Multi serial device functions */
#define DECLARE_ESERIAL_FUNCTIONS(port) \
int userial##port##_init(void) \
{ uartlite_serial_puts(s, port); }
/* Serial device descriptor */
-#define INIT_ESERIAL_STRUCTURE(port, name) {\
- name,\
- userial##port##_init,\
- NULL,\
- userial##port##_setbrg,\
- userial##port##_getc,\
- userial##port##_tstc,\
- userial##port##_putc,\
- userial##port##_puts, }
+#define INIT_ESERIAL_STRUCTURE(port, __name) { \
+ .name = __name, \
+ .start = userial##port##_init, \
+ .stop = NULL, \
+ .setbrg = userial##port##_setbrg, \
+ .getc = userial##port##_getc, \
+ .tstc = userial##port##_tstc, \
+ .putc = userial##port##_putc, \
+ .puts = userial##port##_puts, \
+}
DECLARE_ESERIAL_FUNCTIONS(0);
struct serial_device uartlite_serial0_device =
return NULL;
}
-#endif /* CONFIG_SERIAL_MULTI */
+
+void uartlite_serial_initialize(void)
+{
+#ifdef XILINX_UARTLITE_BASEADDR
+ serial_register(&uartlite_serial0_device);
+#endif /* XILINX_UARTLITE_BASEADDR */
+#ifdef XILINX_UARTLITE_BASEADDR1
+ serial_register(&uartlite_serial1_device);
+#endif /* XILINX_UARTLITE_BASEADDR1 */
+#ifdef XILINX_UARTLITE_BASEADDR2
+ serial_register(&uartlite_serial2_device);
+#endif /* XILINX_UARTLITE_BASEADDR2 */
+#ifdef XILINX_UARTLITE_BASEADDR3
+ serial_register(&uartlite_serial3_device);
+#endif /* XILINX_UARTLITE_BASEADDR3 */
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <serial.h>
+
+#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
+#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
+
+#define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */
+#define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */
+#define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */
+#define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */
+
+#define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
+
+/* Some clock/baud constants */
+#define ZYNQ_UART_BDIV 15 /* Default/reset BDIV value */
+#define ZYNQ_UART_BASECLK 3125000L /* master / (bdiv + 1) */
+
+struct uart_zynq {
+ u32 control; /* Control Register [8:0] */
+ u32 mode; /* Mode Register [10:0] */
+ u32 reserved1[4];
+ u32 baud_rate_gen; /* Baud Rate Generator [15:0] */
+ u32 reserved2[4];
+ u32 channel_sts; /* Channel Status [11:0] */
+ u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */
+ u32 baud_rate_divider; /* Baud Rate Divider [7:0] */
+};
+
+static struct uart_zynq *uart_zynq_ports[2] = {
+#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
+ [0] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR0,
+#endif
+#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
+ [1] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR1,
+#endif
+};
+
+struct uart_zynq_params {
+ u32 baudrate;
+ u32 clock;
+};
+
+static struct uart_zynq_params uart_zynq_ports_param[2] = {
+#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) && defined(CONFIG_ZYNQ_SERIAL_CLOCK0)
+ [0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0,
+ [0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0,
+#endif
+#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) && defined(CONFIG_ZYNQ_SERIAL_CLOCK1)
+ [1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1,
+ [1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1,
+#endif
+};
+
+/* Set up the baud rate in gd struct */
+static void uart_zynq_serial_setbrg(const int port)
+{
+ /* Calculation results. */
+ unsigned int calc_bauderror, bdiv, bgen;
+ unsigned long calc_baud = 0;
+ unsigned long baud = uart_zynq_ports_param[port].baudrate;
+ unsigned long clock = uart_zynq_ports_param[port].clock;
+ struct uart_zynq *regs = uart_zynq_ports[port];
+
+ /* master clock
+ * Baud rate = ------------------
+ * bgen * (bdiv + 1)
+ *
+ * Find acceptable values for baud generation.
+ */
+ for (bdiv = 4; bdiv < 255; bdiv++) {
+ bgen = clock / (baud * (bdiv + 1));
+ if (bgen < 2 || bgen > 65535)
+ continue;
+
+ calc_baud = clock / (bgen * (bdiv + 1));
+
+ /*
+ * Use first calculated baudrate with
+ * an acceptable (<3%) error
+ */
+ if (baud > calc_baud)
+ calc_bauderror = baud - calc_baud;
+ else
+ calc_bauderror = calc_baud - baud;
+ if (((calc_bauderror * 100) / baud) < 3)
+ break;
+ }
+
+ writel(bdiv, ®s->baud_rate_divider);
+ writel(bgen, ®s->baud_rate_gen);
+}
+
+/* Initialize the UART, with...some settings. */
+static int uart_zynq_serial_init(const int port)
+{
+ struct uart_zynq *regs = uart_zynq_ports[port];
+
+ if (!regs)
+ return -1;
+
+ /* RX/TX enabled & reset */
+ writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
+ ZYNQ_UART_CR_RXRST, ®s->control);
+ writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */
+ uart_zynq_serial_setbrg(port);
+
+ return 0;
+}
+
+static void uart_zynq_serial_putc(const char c, const int port)
+{
+ struct uart_zynq *regs = uart_zynq_ports[port];
+
+ while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
+ WATCHDOG_RESET();
+
+ if (c == '\n') {
+ writel('\r', ®s->tx_rx_fifo);
+ while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
+ WATCHDOG_RESET();
+ }
+ writel(c, ®s->tx_rx_fifo);
+}
+
+static void uart_zynq_serial_puts(const char *s, const int port)
+{
+ while (*s)
+ uart_zynq_serial_putc(*s++, port);
+}
+
+static int uart_zynq_serial_tstc(const int port)
+{
+ struct uart_zynq *regs = uart_zynq_ports[port];
+
+ return (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0;
+}
+
+static int uart_zynq_serial_getc(const int port)
+{
+ struct uart_zynq *regs = uart_zynq_ports[port];
+
+ while (!uart_zynq_serial_tstc(port))
+ WATCHDOG_RESET();
+ return readl(®s->tx_rx_fifo);
+}
+
+/* Multi serial device functions */
+#define DECLARE_PSSERIAL_FUNCTIONS(port) \
+ int uart_zynq##port##_init(void) \
+ { return uart_zynq_serial_init(port); } \
+ void uart_zynq##port##_setbrg(void) \
+ { return uart_zynq_serial_setbrg(port); } \
+ int uart_zynq##port##_getc(void) \
+ { return uart_zynq_serial_getc(port); } \
+ int uart_zynq##port##_tstc(void) \
+ { return uart_zynq_serial_tstc(port); } \
+ void uart_zynq##port##_putc(const char c) \
+ { uart_zynq_serial_putc(c, port); } \
+ void uart_zynq##port##_puts(const char *s) \
+ { uart_zynq_serial_puts(s, port); }
+
+/* Serial device descriptor */
+#define INIT_PSSERIAL_STRUCTURE(port, __name) { \
+ .name = __name, \
+ .start = uart_zynq##port##_init, \
+ .stop = NULL, \
+ .setbrg = uart_zynq##port##_setbrg, \
+ .getc = uart_zynq##port##_getc, \
+ .tstc = uart_zynq##port##_tstc, \
+ .putc = uart_zynq##port##_putc, \
+ .puts = uart_zynq##port##_puts, \
+}
+
+DECLARE_PSSERIAL_FUNCTIONS(0);
+struct serial_device uart_zynq_serial0_device =
+ INIT_PSSERIAL_STRUCTURE(0, "ttyPS0");
+DECLARE_PSSERIAL_FUNCTIONS(1);
+struct serial_device uart_zynq_serial1_device =
+ INIT_PSSERIAL_STRUCTURE(1, "ttyPS1");
+
+__weak struct serial_device *default_serial_console(void)
+{
+ if (uart_zynq_ports[0])
+ return &uart_zynq_serial0_device;
+ if (uart_zynq_ports[1])
+ return &uart_zynq_serial1_device;
+
+ return NULL;
+}
+
+void zynq_serial_initalize(void)
+{
+#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
+ serial_register(&uart_zynq_serial0_device);
+#endif
+#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
+ serial_register(&uart_zynq_serial1_device);
+#endif
+}
*/
#include <common.h>
-
#include <malloc.h>
-#include <spi.h>
#include <asm/io.h>
#include <asm/gpio.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/uart-spi-switch.h>
-#include <asm/arch/tegra_spi.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/tegra_spi.h>
+#include <spi.h>
#if defined(CONFIG_SPI_CORRUPTS_UART)
#define corrupt_delay() udelay(CONFIG_SPI_CORRUPTS_UART_DLY);
if (mode == 1)
- printf(" scanning bus for ethernet devices... ");
+ printf(" scanning usb for ethernet devices... ");
old_async = usb_disable_asynch(1); /* asynch transfer not allowed */
COBJS-y += ether.o epautoconf.o config.o usbstring.o
COBJS-$(CONFIG_USB_ETH_RNDIS) += rndis.o
COBJS-$(CONFIG_MV_UDC) += mv_udc.o
+COBJS-$(CONFIG_CPU_PXA25X) += pxa25x_udc.o
else
# Devices not related to the new gadget layer depend on CONFIG_USB_DEVICE
ifdef CONFIG_USB_DEVICE
unsigned packet_received, packet_sent;
-#define DEV_CONFIG_CDC 1
#define GFP_ATOMIC ((gfp_t) 0)
#define GFP_KERNEL ((gfp_t) 0)
/* "main" config is either CDC, or its simple subset */
static inline int is_cdc(struct eth_dev *dev)
{
-#if !defined(DEV_CONFIG_SUBSET)
+#if !defined(CONFIG_USB_ETH_SUBSET)
return 1; /* only cdc possible */
-#elif !defined(DEV_CONFIG_CDC)
+#elif !defined(CONFIG_USB_ETH_CDC)
return 0; /* only subset possible */
#else
return dev->cdc; /* depends on what hardware we found */
* get those drivers from MCCI, or bundled with various products.
*/
-#ifdef DEV_CONFIG_CDC
+#ifdef CONFIG_USB_ETH_CDC
static struct usb_interface_descriptor
control_intf = {
.bLength = sizeof control_intf,
.bcdCDC = __constant_cpu_to_le16(0x0110),
};
-#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
+#if defined(CONFIG_USB_ETH_CDC) || defined(CONFIG_USB_ETH_RNDIS)
static const struct usb_cdc_union_desc union_desc = {
.bLength = sizeof union_desc,
#endif
-#ifndef DEV_CONFIG_CDC
+#ifndef CONFIG_USB_ETH_CDC
/*
* "SAFE" loosely follows CDC WMC MDLM, violating the spec in various
.bNumberPowerFilters = 0,
};
-#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
+#if defined(CONFIG_USB_ETH_CDC) || defined(CONFIG_USB_ETH_RNDIS)
/*
* include the status endpoint if we can, even where it's optional.
};
#endif
-#ifdef DEV_CONFIG_CDC
+#ifdef CONFIG_USB_ETH_CDC
/* the default data interface has no endpoints ... */
#endif
-#ifdef DEV_CONFIG_SUBSET
+#ifdef CONFIG_USB_ETH_SUBSET
/*
* "Simple" CDC-subset option is a simple vendor-neutral model that most
static const struct usb_descriptor_header *fs_eth_function[11] = {
(struct usb_descriptor_header *) &otg_descriptor,
-#ifdef DEV_CONFIG_CDC
+#ifdef CONFIG_USB_ETH_CDC
/* "cdc" mode descriptors */
(struct usb_descriptor_header *) &control_intf,
(struct usb_descriptor_header *) &header_desc,
(struct usb_descriptor_header *) &fs_source_desc,
(struct usb_descriptor_header *) &fs_sink_desc,
NULL,
-#endif /* DEV_CONFIG_CDC */
+#endif /* CONFIG_USB_ETH_CDC */
};
static inline void fs_subset_descriptors(void)
{
-#ifdef DEV_CONFIG_SUBSET
+#ifdef CONFIG_USB_ETH_SUBSET
/* behavior is "CDC Subset"; extra descriptors say "SAFE" */
fs_eth_function[1] = (struct usb_descriptor_header *) &subset_data_intf;
fs_eth_function[2] = (struct usb_descriptor_header *) &header_desc;
* descriptors, unless they only run at full speed.
*/
-#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
+#if defined(CONFIG_USB_ETH_CDC) || defined(CONFIG_USB_ETH_RNDIS)
static struct usb_endpoint_descriptor
hs_status_desc = {
.bLength = USB_DT_ENDPOINT_SIZE,
.wMaxPacketSize = __constant_cpu_to_le16(STATUS_BYTECOUNT),
.bInterval = LOG2_STATUS_INTERVAL_MSEC + 4,
};
-#endif /* DEV_CONFIG_CDC */
+#endif /* CONFIG_USB_ETH_CDC */
static struct usb_endpoint_descriptor
hs_source_desc = {
static const struct usb_descriptor_header *hs_eth_function[11] = {
(struct usb_descriptor_header *) &otg_descriptor,
-#ifdef DEV_CONFIG_CDC
+#ifdef CONFIG_USB_ETH_CDC
/* "cdc" mode descriptors */
(struct usb_descriptor_header *) &control_intf,
(struct usb_descriptor_header *) &header_desc,
(struct usb_descriptor_header *) &hs_source_desc,
(struct usb_descriptor_header *) &hs_sink_desc,
NULL,
-#endif /* DEV_CONFIG_CDC */
+#endif /* CONFIG_USB_ETH_CDC */
};
static inline void hs_subset_descriptors(void)
{
-#ifdef DEV_CONFIG_SUBSET
+#ifdef CONFIG_USB_ETH_SUBSET
/* behavior is "CDC Subset"; extra descriptors say "SAFE" */
hs_eth_function[1] = (struct usb_descriptor_header *) &subset_data_intf;
hs_eth_function[2] = (struct usb_descriptor_header *) &header_desc;
{ STRING_SERIALNUMBER, serial_number, },
{ STRING_DATA, "Ethernet Data", },
{ STRING_ETHADDR, ethaddr, },
-#ifdef DEV_CONFIG_CDC
+#ifdef CONFIG_USB_ETH_CDC
{ STRING_CDC, "CDC Ethernet", },
{ STRING_CONTROL, "CDC Communications Control", },
#endif
-#ifdef DEV_CONFIG_SUBSET
+#ifdef CONFIG_USB_ETH_SUBSET
{ STRING_SUBSET, "CDC Ethernet Subset", },
#endif
#ifdef CONFIG_USB_ETH_RNDIS
/*============================================================================*/
static u8 control_req[USB_BUFSIZ];
+#if defined(CONFIG_USB_ETH_CDC) || defined(CONFIG_USB_ETH_RNDIS)
static u8 status_req[STATUS_BYTECOUNT] __attribute__ ((aligned(4)));
+#endif
/**
int result = 0;
struct usb_gadget *gadget = dev->gadget;
-#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
+#if defined(CONFIG_USB_ETH_CDC) || defined(CONFIG_USB_ETH_RNDIS)
/* status endpoint used for RNDIS and (optionally) CDC */
if (!subset_active(dev) && dev->status_ep) {
dev->status = ep_desc(gadget, &hs_status_desc,
/*-------------------------------------------------------------------------*/
-#ifdef DEV_CONFIG_CDC
+#ifdef CONFIG_USB_ETH_CDC
/*
* The interrupt endpoint is used in CDC networking models (Ethernet, ATM)
if (gadget_is_pxa(gadget)) {
value = eth_set_config(dev, DEV_CONFIG_VALUE,
GFP_ATOMIC);
+ /*
+ * PXA25x driver use non-CDC ethernet gadget.
+ * But only _CDC and _RNDIS code can signalize
+ * that network is working. So we signalize it
+ * here.
+ */
+ l_ethdev.network_started = 1;
+ debug("USB network up!\n");
goto done_set_intf;
}
-#ifdef DEV_CONFIG_CDC
+#ifdef CONFIG_USB_ETH_CDC
switch (wIndex) {
case 0: /* control/master intf */
if (wValue != 0)
* all non-PXA hardware talks real CDC ...
*/
debug("set_interface ignored!\n");
-#endif /* DEV_CONFIG_CDC */
+#endif /* CONFIG_USB_ETH_CDC */
done_set_intf:
break;
value = min(wLength, (u16) 1);
break;
-#ifdef DEV_CONFIG_CDC
+#ifdef CONFIG_USB_ETH_CDC
case USB_CDC_SET_ETHERNET_PACKET_FILTER:
/*
* see 6.2.30: no data, wIndex = interface,
* case USB_CDC_GET_ETHERNET_STATISTIC:
*/
-#endif /* DEV_CONFIG_CDC */
+#endif /* CONFIG_USB_ETH_CDC */
#ifdef CONFIG_USB_ETH_RNDIS
/*
u8 tmp[7];
/* these flags are only ever cleared; compiler take note */
-#ifndef DEV_CONFIG_CDC
+#ifndef CONFIG_USB_ETH_CDC
cdc = 0;
#endif
#ifndef CONFIG_USB_ETH_RNDIS
goto autoconf_fail;
out_ep->driver_data = out_ep; /* claim */
-#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
+#if defined(CONFIG_USB_ETH_CDC) || defined(CONFIG_USB_ETH_RNDIS)
/*
* CDC Ethernet control interface doesn't require a status endpoint.
* Since some hosts expect one, try to allocate one anyway.
} else if (rndis) {
error("can't run RNDIS on %s", gadget->name);
return -ENODEV;
-#ifdef DEV_CONFIG_CDC
+#ifdef CONFIG_USB_ETH_CDC
} else if (cdc) {
control_intf.bNumEndpoints = 0;
/* FIXME remove endpoint from descriptor list */
fs_source_desc.bEndpointAddress;
hs_sink_desc.bEndpointAddress =
fs_sink_desc.bEndpointAddress;
-#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
+#if defined(CONFIG_USB_ETH_CDC) || defined(CONFIG_USB_ETH_RNDIS)
if (status_ep)
hs_status_desc.bEndpointAddress =
fs_status_desc.bEndpointAddress;
dev->req->complete = eth_setup_complete;
/* ... and maybe likewise for status transfer */
-#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
+#if defined(CONFIG_USB_ETH_CDC) || defined(CONFIG_USB_ETH_RNDIS)
if (dev->status_ep) {
dev->stat_req = usb_ep_alloc_request(dev->status_ep,
GFP_KERNEL);
--- /dev/null
+/*
+ * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
+ *
+ * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
+ * Copyright (C) 2003 Robert Schwebel, Pengutronix
+ * Copyright (C) 2003 Benedikt Spranger, Pengutronix
+ * Copyright (C) 2003 David Brownell
+ * Copyright (C) 2003 Joshua Wise
+ * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
+ */
+
+#define CONFIG_USB_PXA25X_SMALL
+#define DRIVER_NAME "pxa25x_udc_linux"
+#define ARCH_HAS_PREFETCH
+
+#include <common.h>
+#include <errno.h>
+#include <asm/byteorder.h>
+#include <asm/system.h>
+#include <asm/mach-types.h>
+#include <asm/unaligned.h>
+#include <linux/compat.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/arch/pxa.h>
+
+#include <usbdescriptors.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <usb/lin_gadget_compat.h>
+#include <asm/arch/pxa-regs.h>
+
+#include "pxa25x_udc.h"
+
+/*
+ * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
+ * series processors. The UDC for the IXP 4xx series is very similar.
+ * There are fifteen endpoints, in addition to ep0.
+ *
+ * Such controller drivers work with a gadget driver. The gadget driver
+ * returns descriptors, implements configuration and data protocols used
+ * by the host to interact with this device, and allocates endpoints to
+ * the different protocol interfaces. The controller driver virtualizes
+ * usb hardware so that the gadget drivers will be more portable.
+ *
+ * This UDC hardware wants to implement a bit too much USB protocol, so
+ * it constrains the sorts of USB configuration change events that work.
+ * The errata for these chips are misleading; some "fixed" bugs from
+ * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
+ *
+ * Note that the UDC hardware supports DMA (except on IXP) but that's
+ * not used here. IN-DMA (to host) is simple enough, when the data is
+ * suitably aligned (16 bytes) ... the network stack doesn't do that,
+ * other software can. OUT-DMA is buggy in most chip versions, as well
+ * as poorly designed (data toggle not automatic). So this driver won't
+ * bother using DMA. (Mostly-working IN-DMA support was available in
+ * kernels before 2.6.23, but was never enabled or well tested.)
+ */
+
+#define DRIVER_VERSION "18-August-2012"
+#define DRIVER_DESC "PXA 25x USB Device Controller driver"
+
+static const char driver_name[] = "pxa25x_udc";
+static const char ep0name[] = "ep0";
+
+/* Watchdog */
+static inline void start_watchdog(struct pxa25x_udc *udc)
+{
+ debug("Started watchdog\n");
+ udc->watchdog.base = get_timer(0);
+ udc->watchdog.running = 1;
+}
+
+static inline void stop_watchdog(struct pxa25x_udc *udc)
+{
+ udc->watchdog.running = 0;
+ debug("Stopped watchdog\n");
+}
+
+static inline void test_watchdog(struct pxa25x_udc *udc)
+{
+ if (!udc->watchdog.running)
+ return;
+
+ debug("watchdog %ld %ld\n", get_timer(udc->watchdog.base),
+ udc->watchdog.period);
+
+ if (get_timer(udc->watchdog.base) >= udc->watchdog.period) {
+ stop_watchdog(udc);
+ udc->watchdog.function(udc);
+ }
+}
+
+static void udc_watchdog(struct pxa25x_udc *dev)
+{
+ uint32_t udccs0 = readl(&dev->regs->udccs[0]);
+
+ debug("Fired up udc_watchdog\n");
+
+ local_irq_disable();
+ if (dev->ep0state == EP0_STALL
+ && (udccs0 & UDCCS0_FST) == 0
+ && (udccs0 & UDCCS0_SST) == 0) {
+ writel(UDCCS0_FST|UDCCS0_FTF, &dev->regs->udccs[0]);
+ debug("ep0 re-stall\n");
+ start_watchdog(dev);
+ }
+ local_irq_enable();
+}
+
+#ifdef DEBUG
+
+static const char * const state_name[] = {
+ "EP0_IDLE",
+ "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE",
+ "EP0_END_XFER", "EP0_STALL"
+};
+
+static void
+dump_udccr(const char *label)
+{
+ u32 udccr = readl(&UDC_REGS->udccr);
+ debug("%s %02X =%s%s%s%s%s%s%s%s\n",
+ label, udccr,
+ (udccr & UDCCR_REM) ? " rem" : "",
+ (udccr & UDCCR_RSTIR) ? " rstir" : "",
+ (udccr & UDCCR_SRM) ? " srm" : "",
+ (udccr & UDCCR_SUSIR) ? " susir" : "",
+ (udccr & UDCCR_RESIR) ? " resir" : "",
+ (udccr & UDCCR_RSM) ? " rsm" : "",
+ (udccr & UDCCR_UDA) ? " uda" : "",
+ (udccr & UDCCR_UDE) ? " ude" : "");
+}
+
+static void
+dump_udccs0(const char *label)
+{
+ u32 udccs0 = readl(&UDC_REGS->udccs[0]);
+
+ debug("%s %s %02X =%s%s%s%s%s%s%s%s\n",
+ label, state_name[the_controller->ep0state], udccs0,
+ (udccs0 & UDCCS0_SA) ? " sa" : "",
+ (udccs0 & UDCCS0_RNE) ? " rne" : "",
+ (udccs0 & UDCCS0_FST) ? " fst" : "",
+ (udccs0 & UDCCS0_SST) ? " sst" : "",
+ (udccs0 & UDCCS0_DRWF) ? " dwrf" : "",
+ (udccs0 & UDCCS0_FTF) ? " ftf" : "",
+ (udccs0 & UDCCS0_IPR) ? " ipr" : "",
+ (udccs0 & UDCCS0_OPR) ? " opr" : "");
+}
+
+static void
+dump_state(struct pxa25x_udc *dev)
+{
+ u32 tmp;
+ unsigned i;
+
+ debug("%s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
+ state_name[dev->ep0state],
+ readl(&UDC_REGS->uicr1), readl(&UDC_REGS->uicr0),
+ readl(&UDC_REGS->usir1), readl(&UDC_REGS->usir0),
+ readl(&UDC_REGS->ufnrh), readl(&UDC_REGS->ufnrl));
+ dump_udccr("udccr");
+ if (dev->has_cfr) {
+ tmp = readl(&UDC_REGS->udccfr);
+ debug("udccfr %02X =%s%s\n", tmp,
+ (tmp & UDCCFR_AREN) ? " aren" : "",
+ (tmp & UDCCFR_ACM) ? " acm" : "");
+ }
+
+ if (!dev->driver) {
+ debug("no gadget driver bound\n");
+ return;
+ } else
+ debug("ep0 driver '%s'\n", "ether");
+
+ dump_udccs0("udccs0");
+ debug("ep0 IN %lu/%lu, OUT %lu/%lu\n",
+ dev->stats.write.bytes, dev->stats.write.ops,
+ dev->stats.read.bytes, dev->stats.read.ops);
+
+ for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) {
+ if (dev->ep[i].desc == NULL)
+ continue;
+ debug("udccs%d = %02x\n", i, *dev->ep->reg_udccs);
+ }
+}
+
+#else /* DEBUG */
+
+static inline void dump_udccr(const char *label) { }
+static inline void dump_udccs0(const char *label) { }
+static inline void dump_state(struct pxa25x_udc *dev) { }
+
+#endif /* DEBUG */
+
+/*
+ * ---------------------------------------------------------------------------
+ * endpoint related parts of the api to the usb controller hardware,
+ * used by gadget driver; and the inner talker-to-hardware core.
+ * ---------------------------------------------------------------------------
+ */
+
+static void pxa25x_ep_fifo_flush(struct usb_ep *ep);
+static void nuke(struct pxa25x_ep *, int status);
+
+/* one GPIO should control a D+ pullup, so host sees this device (or not) */
+static void pullup_off(void)
+{
+ struct pxa2xx_udc_mach_info *mach = the_controller->mach;
+
+ if (mach->udc_command)
+ mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
+}
+
+static void pullup_on(void)
+{
+ struct pxa2xx_udc_mach_info *mach = the_controller->mach;
+
+ if (mach->udc_command)
+ mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
+}
+
+static void pio_irq_enable(int bEndpointAddress)
+{
+ bEndpointAddress &= 0xf;
+ if (bEndpointAddress < 8) {
+ clrbits_le32(&the_controller->regs->uicr0,
+ 1 << bEndpointAddress);
+ } else {
+ bEndpointAddress -= 8;
+ clrbits_le32(&the_controller->regs->uicr1,
+ 1 << bEndpointAddress);
+ }
+}
+
+static void pio_irq_disable(int bEndpointAddress)
+{
+ bEndpointAddress &= 0xf;
+ if (bEndpointAddress < 8) {
+ setbits_le32(&the_controller->regs->uicr0,
+ 1 << bEndpointAddress);
+ } else {
+ bEndpointAddress -= 8;
+ setbits_le32(&the_controller->regs->uicr1,
+ 1 << bEndpointAddress);
+ }
+}
+
+static inline void udc_set_mask_UDCCR(int mask)
+{
+ /*
+ * The UDCCR reg contains mask and interrupt status bits,
+ * so using '|=' isn't safe as it may ack an interrupt.
+ */
+ const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
+
+ mask &= mask_bits;
+ clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask);
+}
+
+static inline void udc_clear_mask_UDCCR(int mask)
+{
+ const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
+
+ mask = ~mask & mask_bits;
+ clrbits_le32(&the_controller->regs->udccr, ~mask);
+}
+
+static inline void udc_ack_int_UDCCR(int mask)
+{
+ const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
+
+ mask &= ~mask_bits;
+ clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask);
+}
+
+/*
+ * endpoint enable/disable
+ *
+ * we need to verify the descriptors used to enable endpoints. since pxa25x
+ * endpoint configurations are fixed, and are pretty much always enabled,
+ * there's not a lot to manage here.
+ *
+ * because pxa25x can't selectively initialize bulk (or interrupt) endpoints,
+ * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
+ * for a single interface (with only the default altsetting) and for gadget
+ * drivers that don't halt endpoints (not reset by set_interface). that also
+ * means that if you use ISO, you must violate the USB spec rule that all
+ * iso endpoints must be in non-default altsettings.
+ */
+static int pxa25x_ep_enable(struct usb_ep *_ep,
+ const struct usb_endpoint_descriptor *desc)
+{
+ struct pxa25x_ep *ep;
+ struct pxa25x_udc *dev;
+
+ ep = container_of(_ep, struct pxa25x_ep, ep);
+ if (!_ep || !desc || ep->desc || _ep->name == ep0name
+ || desc->bDescriptorType != USB_DT_ENDPOINT
+ || ep->bEndpointAddress != desc->bEndpointAddress
+ || ep->fifo_size < le16_to_cpu(desc->wMaxPacketSize)) {
+ printf("%s, bad ep or descriptor\n", __func__);
+ return -EINVAL;
+ }
+
+ /* xfer types must match, except that interrupt ~= bulk */
+ if (ep->bmAttributes != desc->bmAttributes
+ && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
+ && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
+ printf("%s, %s type mismatch\n", __func__, _ep->name);
+ return -EINVAL;
+ }
+
+ /* hardware _could_ do smaller, but driver doesn't */
+ if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
+ && le16_to_cpu(desc->wMaxPacketSize)
+ != BULK_FIFO_SIZE)
+ || !desc->wMaxPacketSize) {
+ printf("%s, bad %s maxpacket\n", __func__, _ep->name);
+ return -ERANGE;
+ }
+
+ dev = ep->dev;
+ if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
+ printf("%s, bogus device state\n", __func__);
+ return -ESHUTDOWN;
+ }
+
+ ep->desc = desc;
+ ep->stopped = 0;
+ ep->pio_irqs = 0;
+ ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
+
+ /* flush fifo (mostly for OUT buffers) */
+ pxa25x_ep_fifo_flush(_ep);
+
+ /* ... reset halt state too, if we could ... */
+
+ debug("enabled %s\n", _ep->name);
+ return 0;
+}
+
+static int pxa25x_ep_disable(struct usb_ep *_ep)
+{
+ struct pxa25x_ep *ep;
+ unsigned long flags;
+
+ ep = container_of(_ep, struct pxa25x_ep, ep);
+ if (!_ep || !ep->desc) {
+ printf("%s, %s not enabled\n", __func__,
+ _ep ? ep->ep.name : NULL);
+ return -EINVAL;
+ }
+ local_irq_save(flags);
+
+ nuke(ep, -ESHUTDOWN);
+
+ /* flush fifo (mostly for IN buffers) */
+ pxa25x_ep_fifo_flush(_ep);
+
+ ep->desc = NULL;
+ ep->stopped = 1;
+
+ local_irq_restore(flags);
+ debug("%s disabled\n", _ep->name);
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * for the pxa25x, these can just wrap kmalloc/kfree. gadget drivers
+ * must still pass correctly initialized endpoints, since other controller
+ * drivers may care about how it's currently set up (dma issues etc).
+ */
+
+/*
+ * pxa25x_ep_alloc_request - allocate a request data structure
+ */
+static struct usb_request *
+pxa25x_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
+{
+ struct pxa25x_request *req;
+
+ req = kzalloc(sizeof(*req), gfp_flags);
+ if (!req)
+ return NULL;
+
+ INIT_LIST_HEAD(&req->queue);
+ return &req->req;
+}
+
+
+/*
+ * pxa25x_ep_free_request - deallocate a request data structure
+ */
+static void
+pxa25x_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
+{
+ struct pxa25x_request *req;
+
+ req = container_of(_req, struct pxa25x_request, req);
+ WARN_ON(!list_empty(&req->queue));
+ kfree(req);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * done - retire a request; caller blocked irqs
+ */
+static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status)
+{
+ unsigned stopped = ep->stopped;
+
+ list_del_init(&req->queue);
+
+ if (likely(req->req.status == -EINPROGRESS))
+ req->req.status = status;
+ else
+ status = req->req.status;
+
+ if (status && status != -ESHUTDOWN)
+ debug("complete %s req %p stat %d len %u/%u\n",
+ ep->ep.name, &req->req, status,
+ req->req.actual, req->req.length);
+
+ /* don't modify queue heads during completion callback */
+ ep->stopped = 1;
+ req->req.complete(&ep->ep, &req->req);
+ ep->stopped = stopped;
+}
+
+
+static inline void ep0_idle(struct pxa25x_udc *dev)
+{
+ dev->ep0state = EP0_IDLE;
+}
+
+static int
+write_packet(u32 *uddr, struct pxa25x_request *req, unsigned max)
+{
+ u8 *buf;
+ unsigned length, count;
+
+ debug("%s(): uddr %p\n", __func__, uddr);
+
+ buf = req->req.buf + req->req.actual;
+ prefetch(buf);
+
+ /* how big will this packet be? */
+ length = min(req->req.length - req->req.actual, max);
+ req->req.actual += length;
+
+ count = length;
+ while (likely(count--))
+ writeb(*buf++, uddr);
+
+ return length;
+}
+
+/*
+ * write to an IN endpoint fifo, as many packets as possible.
+ * irqs will use this to write the rest later.
+ * caller guarantees at least one packet buffer is ready (or a zlp).
+ */
+static int
+write_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
+{
+ unsigned max;
+
+ max = le16_to_cpu(ep->desc->wMaxPacketSize);
+ do {
+ unsigned count;
+ int is_last, is_short;
+
+ count = write_packet(ep->reg_uddr, req, max);
+
+ /* last packet is usually short (or a zlp) */
+ if (unlikely(count != max))
+ is_last = is_short = 1;
+ else {
+ if (likely(req->req.length != req->req.actual)
+ || req->req.zero)
+ is_last = 0;
+ else
+ is_last = 1;
+ /* interrupt/iso maxpacket may not fill the fifo */
+ is_short = unlikely(max < ep->fifo_size);
+ }
+
+ debug_cond(NOISY, "wrote %s %d bytes%s%s %d left %p\n",
+ ep->ep.name, count,
+ is_last ? "/L" : "", is_short ? "/S" : "",
+ req->req.length - req->req.actual, req);
+
+ /*
+ * let loose that packet. maybe try writing another one,
+ * double buffering might work. TSP, TPC, and TFS
+ * bit values are the same for all normal IN endpoints.
+ */
+ writel(UDCCS_BI_TPC, ep->reg_udccs);
+ if (is_short)
+ writel(UDCCS_BI_TSP, ep->reg_udccs);
+
+ /* requests complete when all IN data is in the FIFO */
+ if (is_last) {
+ done(ep, req, 0);
+ if (list_empty(&ep->queue))
+ pio_irq_disable(ep->bEndpointAddress);
+ return 1;
+ }
+
+ /*
+ * TODO experiment: how robust can fifo mode tweaking be?
+ * double buffering is off in the default fifo mode, which
+ * prevents TFS from being set here.
+ */
+
+ } while (readl(ep->reg_udccs) & UDCCS_BI_TFS);
+ return 0;
+}
+
+/*
+ * caller asserts req->pending (ep0 irq status nyet cleared); starts
+ * ep0 data stage. these chips want very simple state transitions.
+ */
+static inline
+void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag)
+{
+ writel(flags|UDCCS0_SA|UDCCS0_OPR, &dev->regs->udccs[0]);
+ writel(USIR0_IR0, &dev->regs->usir0);
+ dev->req_pending = 0;
+ debug_cond(NOISY, "%s() %s, udccs0: %02x/%02x usir: %X.%X\n",
+ __func__, tag, readl(&dev->regs->udccs[0]), flags,
+ readl(&dev->regs->usir1), readl(&dev->regs->usir0));
+}
+
+static int
+write_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
+{
+ unsigned count;
+ int is_short;
+
+ count = write_packet(&ep->dev->regs->uddr0, req, EP0_FIFO_SIZE);
+ ep->dev->stats.write.bytes += count;
+
+ /* last packet "must be" short (or a zlp) */
+ is_short = (count != EP0_FIFO_SIZE);
+
+ debug_cond(NOISY, "ep0in %d bytes %d left %p\n", count,
+ req->req.length - req->req.actual, req);
+
+ if (unlikely(is_short)) {
+ if (ep->dev->req_pending)
+ ep0start(ep->dev, UDCCS0_IPR, "short IN");
+ else
+ writel(UDCCS0_IPR, &ep->dev->regs->udccs[0]);
+
+ count = req->req.length;
+ done(ep, req, 0);
+ ep0_idle(ep->dev);
+
+ /*
+ * This seems to get rid of lost status irqs in some cases:
+ * host responds quickly, or next request involves config
+ * change automagic, or should have been hidden, or ...
+ *
+ * FIXME get rid of all udelays possible...
+ */
+ if (count >= EP0_FIFO_SIZE) {
+ count = 100;
+ do {
+ if ((readl(&ep->dev->regs->udccs[0]) &
+ UDCCS0_OPR) != 0) {
+ /* clear OPR, generate ack */
+ writel(UDCCS0_OPR,
+ &ep->dev->regs->udccs[0]);
+ break;
+ }
+ count--;
+ udelay(1);
+ } while (count);
+ }
+ } else if (ep->dev->req_pending)
+ ep0start(ep->dev, 0, "IN");
+
+ return is_short;
+}
+
+
+/*
+ * read_fifo - unload packet(s) from the fifo we use for usb OUT
+ * transfers and put them into the request. caller should have made
+ * sure there's at least one packet ready.
+ *
+ * returns true if the request completed because of short packet or the
+ * request buffer having filled (and maybe overran till end-of-packet).
+ */
+static int
+read_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
+{
+ u32 udccs;
+ u8 *buf;
+ unsigned bufferspace, count, is_short;
+
+ for (;;) {
+ /*
+ * make sure there's a packet in the FIFO.
+ * UDCCS_{BO,IO}_RPC are all the same bit value.
+ * UDCCS_{BO,IO}_RNE are all the same bit value.
+ */
+ udccs = readl(ep->reg_udccs);
+ if (unlikely((udccs & UDCCS_BO_RPC) == 0))
+ break;
+ buf = req->req.buf + req->req.actual;
+ prefetchw(buf);
+ bufferspace = req->req.length - req->req.actual;
+
+ /* read all bytes from this packet */
+ if (likely(udccs & UDCCS_BO_RNE)) {
+ count = 1 + (0x0ff & readl(ep->reg_ubcr));
+ req->req.actual += min(count, bufferspace);
+ } else /* zlp */
+ count = 0;
+ is_short = (count < ep->ep.maxpacket);
+ debug_cond(NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
+ ep->ep.name, udccs, count,
+ is_short ? "/S" : "",
+ req, req->req.actual, req->req.length);
+ while (likely(count-- != 0)) {
+ u8 byte = readb(ep->reg_uddr);
+
+ if (unlikely(bufferspace == 0)) {
+ /*
+ * this happens when the driver's buffer
+ * is smaller than what the host sent.
+ * discard the extra data.
+ */
+ if (req->req.status != -EOVERFLOW)
+ printf("%s overflow %d\n",
+ ep->ep.name, count);
+ req->req.status = -EOVERFLOW;
+ } else {
+ *buf++ = byte;
+ bufferspace--;
+ }
+ }
+ writel(UDCCS_BO_RPC, ep->reg_udccs);
+ /* RPC/RSP/RNE could now reflect the other packet buffer */
+
+ /* iso is one request per packet */
+ if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
+ if (udccs & UDCCS_IO_ROF)
+ req->req.status = -EHOSTUNREACH;
+ /* more like "is_done" */
+ is_short = 1;
+ }
+
+ /* completion */
+ if (is_short || req->req.actual == req->req.length) {
+ done(ep, req, 0);
+ if (list_empty(&ep->queue))
+ pio_irq_disable(ep->bEndpointAddress);
+ return 1;
+ }
+
+ /* finished that packet. the next one may be waiting... */
+ }
+ return 0;
+}
+
+/*
+ * special ep0 version of the above. no UBCR0 or double buffering; status
+ * handshaking is magic. most device protocols don't need control-OUT.
+ * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
+ * protocols do use them.
+ */
+static int
+read_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
+{
+ u8 *buf, byte;
+ unsigned bufferspace;
+
+ buf = req->req.buf + req->req.actual;
+ bufferspace = req->req.length - req->req.actual;
+
+ while (readl(&ep->dev->regs->udccs[0]) & UDCCS0_RNE) {
+ byte = (u8)readb(&ep->dev->regs->uddr0);
+
+ if (unlikely(bufferspace == 0)) {
+ /*
+ * this happens when the driver's buffer
+ * is smaller than what the host sent.
+ * discard the extra data.
+ */
+ if (req->req.status != -EOVERFLOW)
+ printf("%s overflow\n", ep->ep.name);
+ req->req.status = -EOVERFLOW;
+ } else {
+ *buf++ = byte;
+ req->req.actual++;
+ bufferspace--;
+ }
+ }
+
+ writel(UDCCS0_OPR | UDCCS0_IPR, &ep->dev->regs->udccs[0]);
+
+ /* completion */
+ if (req->req.actual >= req->req.length)
+ return 1;
+
+ /* finished that packet. the next one may be waiting... */
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static int
+pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
+{
+ struct pxa25x_request *req;
+ struct pxa25x_ep *ep;
+ struct pxa25x_udc *dev;
+ unsigned long flags;
+
+ req = container_of(_req, struct pxa25x_request, req);
+ if (unlikely(!_req || !_req->complete || !_req->buf
+ || !list_empty(&req->queue))) {
+ printf("%s, bad params\n", __func__);
+ return -EINVAL;
+ }
+
+ ep = container_of(_ep, struct pxa25x_ep, ep);
+ if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
+ printf("%s, bad ep\n", __func__);
+ return -EINVAL;
+ }
+
+ dev = ep->dev;
+ if (unlikely(!dev->driver
+ || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
+ printf("%s, bogus device state\n", __func__);
+ return -ESHUTDOWN;
+ }
+
+ /*
+ * iso is always one packet per request, that's the only way
+ * we can report per-packet status. that also helps with dma.
+ */
+ if (unlikely(ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
+ && req->req.length >
+ le16_to_cpu(ep->desc->wMaxPacketSize)))
+ return -EMSGSIZE;
+
+ debug_cond(NOISY, "%s queue req %p, len %d buf %p\n",
+ _ep->name, _req, _req->length, _req->buf);
+
+ local_irq_save(flags);
+
+ _req->status = -EINPROGRESS;
+ _req->actual = 0;
+
+ /* kickstart this i/o queue? */
+ if (list_empty(&ep->queue) && !ep->stopped) {
+ if (ep->desc == NULL/* ep0 */) {
+ unsigned length = _req->length;
+
+ switch (dev->ep0state) {
+ case EP0_IN_DATA_PHASE:
+ dev->stats.write.ops++;
+ if (write_ep0_fifo(ep, req))
+ req = NULL;
+ break;
+
+ case EP0_OUT_DATA_PHASE:
+ dev->stats.read.ops++;
+ /* messy ... */
+ if (dev->req_config) {
+ debug("ep0 config ack%s\n",
+ dev->has_cfr ? "" : " raced");
+ if (dev->has_cfr)
+ writel(UDCCFR_AREN|UDCCFR_ACM
+ |UDCCFR_MB1,
+ &ep->dev->regs->udccfr);
+ done(ep, req, 0);
+ dev->ep0state = EP0_END_XFER;
+ local_irq_restore(flags);
+ return 0;
+ }
+ if (dev->req_pending)
+ ep0start(dev, UDCCS0_IPR, "OUT");
+ if (length == 0 ||
+ ((readl(
+ &ep->dev->regs->udccs[0])
+ & UDCCS0_RNE) != 0
+ && read_ep0_fifo(ep, req))) {
+ ep0_idle(dev);
+ done(ep, req, 0);
+ req = NULL;
+ }
+ break;
+
+ default:
+ printf("ep0 i/o, odd state %d\n",
+ dev->ep0state);
+ local_irq_restore(flags);
+ return -EL2HLT;
+ }
+ /* can the FIFO can satisfy the request immediately? */
+ } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
+ if ((readl(ep->reg_udccs) & UDCCS_BI_TFS) != 0
+ && write_fifo(ep, req))
+ req = NULL;
+ } else if ((readl(ep->reg_udccs) & UDCCS_BO_RFS) != 0
+ && read_fifo(ep, req)) {
+ req = NULL;
+ }
+
+ if (likely(req && ep->desc))
+ pio_irq_enable(ep->bEndpointAddress);
+ }
+
+ /* pio or dma irq handler advances the queue. */
+ if (likely(req != NULL))
+ list_add_tail(&req->queue, &ep->queue);
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+
+/*
+ * nuke - dequeue ALL requests
+ */
+static void nuke(struct pxa25x_ep *ep, int status)
+{
+ struct pxa25x_request *req;
+
+ /* called with irqs blocked */
+ while (!list_empty(&ep->queue)) {
+ req = list_entry(ep->queue.next,
+ struct pxa25x_request,
+ queue);
+ done(ep, req, status);
+ }
+ if (ep->desc)
+ pio_irq_disable(ep->bEndpointAddress);
+}
+
+
+/* dequeue JUST ONE request */
+static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+{
+ struct pxa25x_ep *ep;
+ struct pxa25x_request *req;
+ unsigned long flags;
+
+ ep = container_of(_ep, struct pxa25x_ep, ep);
+ if (!_ep || ep->ep.name == ep0name)
+ return -EINVAL;
+
+ local_irq_save(flags);
+
+ /* make sure it's actually queued on this endpoint */
+ list_for_each_entry(req, &ep->queue, queue) {
+ if (&req->req == _req)
+ break;
+ }
+ if (&req->req != _req) {
+ local_irq_restore(flags);
+ return -EINVAL;
+ }
+
+ done(ep, req, -ECONNRESET);
+
+ local_irq_restore(flags);
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value)
+{
+ struct pxa25x_ep *ep;
+ unsigned long flags;
+
+ ep = container_of(_ep, struct pxa25x_ep, ep);
+ if (unlikely(!_ep
+ || (!ep->desc && ep->ep.name != ep0name))
+ || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
+ printf("%s, bad ep\n", __func__);
+ return -EINVAL;
+ }
+ if (value == 0) {
+ /*
+ * this path (reset toggle+halt) is needed to implement
+ * SET_INTERFACE on normal hardware. but it can't be
+ * done from software on the PXA UDC, and the hardware
+ * forgets to do it as part of SET_INTERFACE automagic.
+ */
+ printf("only host can clear %s halt\n", _ep->name);
+ return -EROFS;
+ }
+
+ local_irq_save(flags);
+
+ if ((ep->bEndpointAddress & USB_DIR_IN) != 0
+ && ((readl(ep->reg_udccs) & UDCCS_BI_TFS) == 0
+ || !list_empty(&ep->queue))) {
+ local_irq_restore(flags);
+ return -EAGAIN;
+ }
+
+ /* FST bit is the same for control, bulk in, bulk out, interrupt in */
+ writel(UDCCS_BI_FST|UDCCS_BI_FTF, ep->reg_udccs);
+
+ /* ep0 needs special care */
+ if (!ep->desc) {
+ start_watchdog(ep->dev);
+ ep->dev->req_pending = 0;
+ ep->dev->ep0state = EP0_STALL;
+
+ /* and bulk/intr endpoints like dropping stalls too */
+ } else {
+ unsigned i;
+ for (i = 0; i < 1000; i += 20) {
+ if (readl(ep->reg_udccs) & UDCCS_BI_SST)
+ break;
+ udelay(20);
+ }
+ }
+ local_irq_restore(flags);
+
+ debug("%s halt\n", _ep->name);
+ return 0;
+}
+
+static int pxa25x_ep_fifo_status(struct usb_ep *_ep)
+{
+ struct pxa25x_ep *ep;
+
+ ep = container_of(_ep, struct pxa25x_ep, ep);
+ if (!_ep) {
+ printf("%s, bad ep\n", __func__);
+ return -ENODEV;
+ }
+ /* pxa can't report unclaimed bytes from IN fifos */
+ if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
+ return -EOPNOTSUPP;
+ if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
+ || (readl(ep->reg_udccs) & UDCCS_BO_RFS) == 0)
+ return 0;
+ else
+ return (readl(ep->reg_ubcr) & 0xfff) + 1;
+}
+
+static void pxa25x_ep_fifo_flush(struct usb_ep *_ep)
+{
+ struct pxa25x_ep *ep;
+
+ ep = container_of(_ep, struct pxa25x_ep, ep);
+ if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
+ printf("%s, bad ep\n", __func__);
+ return;
+ }
+
+ /* toggle and halt bits stay unchanged */
+
+ /* for OUT, just read and discard the FIFO contents. */
+ if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
+ while (((readl(ep->reg_udccs)) & UDCCS_BO_RNE) != 0)
+ (void)readb(ep->reg_uddr);
+ return;
+ }
+
+ /* most IN status is the same, but ISO can't stall */
+ writel(UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
+ | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
+ ? 0 : UDCCS_BI_SST), ep->reg_udccs);
+}
+
+
+static struct usb_ep_ops pxa25x_ep_ops = {
+ .enable = pxa25x_ep_enable,
+ .disable = pxa25x_ep_disable,
+
+ .alloc_request = pxa25x_ep_alloc_request,
+ .free_request = pxa25x_ep_free_request,
+
+ .queue = pxa25x_ep_queue,
+ .dequeue = pxa25x_ep_dequeue,
+
+ .set_halt = pxa25x_ep_set_halt,
+ .fifo_status = pxa25x_ep_fifo_status,
+ .fifo_flush = pxa25x_ep_fifo_flush,
+};
+
+
+/* ---------------------------------------------------------------------------
+ * device-scoped parts of the api to the usb controller hardware
+ * ---------------------------------------------------------------------------
+ */
+
+static int pxa25x_udc_get_frame(struct usb_gadget *_gadget)
+{
+ return ((readl(&the_controller->regs->ufnrh) & 0x07) << 8) |
+ (readl(&the_controller->regs->ufnrl) & 0xff);
+}
+
+static int pxa25x_udc_wakeup(struct usb_gadget *_gadget)
+{
+ /* host may not have enabled remote wakeup */
+ if ((readl(&the_controller->regs->udccs[0]) & UDCCS0_DRWF) == 0)
+ return -EHOSTUNREACH;
+ udc_set_mask_UDCCR(UDCCR_RSM);
+ return 0;
+}
+
+static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *);
+static void udc_enable(struct pxa25x_udc *);
+static void udc_disable(struct pxa25x_udc *);
+
+/*
+ * We disable the UDC -- and its 48 MHz clock -- whenever it's not
+ * in active use.
+ */
+static int pullup(struct pxa25x_udc *udc)
+{
+ if (udc->pullup)
+ pullup_on();
+ else
+ pullup_off();
+
+
+ int is_active = udc->pullup;
+ if (is_active) {
+ if (!udc->active) {
+ udc->active = 1;
+ udc_enable(udc);
+ }
+ } else {
+ if (udc->active) {
+ if (udc->gadget.speed != USB_SPEED_UNKNOWN)
+ stop_activity(udc, udc->driver);
+ udc_disable(udc);
+ udc->active = 0;
+ }
+
+ }
+ return 0;
+}
+
+/* VBUS reporting logically comes from a transceiver */
+static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
+{
+ struct pxa25x_udc *udc;
+
+ udc = container_of(_gadget, struct pxa25x_udc, gadget);
+ printf("vbus %s\n", is_active ? "supplied" : "inactive");
+ pullup(udc);
+ return 0;
+}
+
+/* drivers may have software control over D+ pullup */
+static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active)
+{
+ struct pxa25x_udc *udc;
+
+ udc = container_of(_gadget, struct pxa25x_udc, gadget);
+
+ /* not all boards support pullup control */
+ if (!udc->mach->udc_command)
+ return -EOPNOTSUPP;
+
+ udc->pullup = (is_active != 0);
+ pullup(udc);
+ return 0;
+}
+
+/*
+ * boards may consume current from VBUS, up to 100-500mA based on config.
+ * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs
+ * violate USB specs.
+ */
+static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
+{
+ return -EOPNOTSUPP;
+}
+
+static const struct usb_gadget_ops pxa25x_udc_ops = {
+ .get_frame = pxa25x_udc_get_frame,
+ .wakeup = pxa25x_udc_wakeup,
+ .vbus_session = pxa25x_udc_vbus_session,
+ .pullup = pxa25x_udc_pullup,
+ .vbus_draw = pxa25x_udc_vbus_draw,
+};
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * udc_disable - disable USB device controller
+ */
+static void udc_disable(struct pxa25x_udc *dev)
+{
+ /* block all irqs */
+ udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
+ writel(0xff, &dev->regs->uicr0);
+ writel(0xff, &dev->regs->uicr1);
+ writel(UFNRH_SIM, &dev->regs->ufnrh);
+
+ /* if hardware supports it, disconnect from usb */
+ pullup_off();
+
+ udc_clear_mask_UDCCR(UDCCR_UDE);
+
+ ep0_idle(dev);
+ dev->gadget.speed = USB_SPEED_UNKNOWN;
+}
+
+/*
+ * udc_reinit - initialize software state
+ */
+static void udc_reinit(struct pxa25x_udc *dev)
+{
+ u32 i;
+
+ /* device/ep0 records init */
+ INIT_LIST_HEAD(&dev->gadget.ep_list);
+ INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
+ dev->ep0state = EP0_IDLE;
+
+ /* basic endpoint records init */
+ for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
+ struct pxa25x_ep *ep = &dev->ep[i];
+
+ if (i != 0)
+ list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
+
+ ep->desc = NULL;
+ ep->stopped = 0;
+ INIT_LIST_HEAD(&ep->queue);
+ ep->pio_irqs = 0;
+ }
+
+ /* the rest was statically initialized, and is read-only */
+}
+
+/*
+ * until it's enabled, this UDC should be completely invisible
+ * to any USB host.
+ */
+static void udc_enable(struct pxa25x_udc *dev)
+{
+ debug("udc: enabling udc\n");
+
+ udc_clear_mask_UDCCR(UDCCR_UDE);
+
+ /*
+ * Try to clear these bits before we enable the udc.
+ * Do not touch reset ack bit, we would take care of it in
+ * interrupt handle routine
+ */
+ udc_ack_int_UDCCR(UDCCR_SUSIR|UDCCR_RESIR);
+
+ ep0_idle(dev);
+ dev->gadget.speed = USB_SPEED_UNKNOWN;
+ dev->stats.irqs = 0;
+
+ /*
+ * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
+ * - enable UDC
+ * - if RESET is already in progress, ack interrupt
+ * - unmask reset interrupt
+ */
+ udc_set_mask_UDCCR(UDCCR_UDE);
+ if (!(readl(&dev->regs->udccr) & UDCCR_UDA))
+ udc_ack_int_UDCCR(UDCCR_RSTIR);
+
+ if (dev->has_cfr /* UDC_RES2 is defined */) {
+ /*
+ * pxa255 (a0+) can avoid a set_config race that could
+ * prevent gadget drivers from configuring correctly
+ */
+ writel(UDCCFR_ACM | UDCCFR_MB1, &dev->regs->udccfr);
+ }
+
+ /* enable suspend/resume and reset irqs */
+ udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
+
+ /* enable ep0 irqs */
+ clrbits_le32(&dev->regs->uicr0, UICR0_IM0);
+
+ /* if hardware supports it, pullup D+ and wait for reset */
+ pullup_on();
+}
+
+static inline void clear_ep_state(struct pxa25x_udc *dev)
+{
+ unsigned i;
+
+ /*
+ * hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
+ * fifos, and pending transactions mustn't be continued in any case.
+ */
+ for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
+ nuke(&dev->ep[i], -ECONNABORTED);
+}
+
+static void handle_ep0(struct pxa25x_udc *dev)
+{
+ u32 udccs0 = readl(&dev->regs->udccs[0]);
+ struct pxa25x_ep *ep = &dev->ep[0];
+ struct pxa25x_request *req;
+ union {
+ struct usb_ctrlrequest r;
+ u8 raw[8];
+ u32 word[2];
+ } u;
+
+ if (list_empty(&ep->queue))
+ req = NULL;
+ else
+ req = list_entry(ep->queue.next, struct pxa25x_request, queue);
+
+ /* clear stall status */
+ if (udccs0 & UDCCS0_SST) {
+ nuke(ep, -EPIPE);
+ writel(UDCCS0_SST, &dev->regs->udccs[0]);
+ stop_watchdog(dev);
+ ep0_idle(dev);
+ }
+
+ /* previous request unfinished? non-error iff back-to-back ... */
+ if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
+ nuke(ep, 0);
+ stop_watchdog(dev);
+ ep0_idle(dev);
+ }
+
+ switch (dev->ep0state) {
+ case EP0_IDLE:
+ /* late-breaking status? */
+ udccs0 = readl(&dev->regs->udccs[0]);
+
+ /* start control request? */
+ if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
+ == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
+ int i;
+
+ nuke(ep, -EPROTO);
+
+ /* read SETUP packet */
+ for (i = 0; i < 8; i++) {
+ if (unlikely(!(readl(&dev->regs->udccs[0]) &
+ UDCCS0_RNE))) {
+bad_setup:
+ debug("SETUP %d!\n", i);
+ goto stall;
+ }
+ u.raw[i] = (u8)readb(&dev->regs->uddr0);
+ }
+ if (unlikely((readl(&dev->regs->udccs[0]) &
+ UDCCS0_RNE) != 0))
+ goto bad_setup;
+
+got_setup:
+ debug("SETUP %02x.%02x v%04x i%04x l%04x\n",
+ u.r.bRequestType, u.r.bRequest,
+ le16_to_cpu(u.r.wValue),
+ le16_to_cpu(u.r.wIndex),
+ le16_to_cpu(u.r.wLength));
+
+ /* cope with automagic for some standard requests. */
+ dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
+ == USB_TYPE_STANDARD;
+ dev->req_config = 0;
+ dev->req_pending = 1;
+ switch (u.r.bRequest) {
+ /* hardware restricts gadget drivers here! */
+ case USB_REQ_SET_CONFIGURATION:
+ debug("GOT SET_CONFIGURATION\n");
+ if (u.r.bRequestType == USB_RECIP_DEVICE) {
+ /*
+ * reflect hardware's automagic
+ * up to the gadget driver.
+ */
+config_change:
+ dev->req_config = 1;
+ clear_ep_state(dev);
+ /*
+ * if !has_cfr, there's no synch
+ * else use AREN (later) not SA|OPR
+ * USIR0_IR0 acts edge sensitive
+ */
+ }
+ break;
+ /* ... and here, even more ... */
+ case USB_REQ_SET_INTERFACE:
+ if (u.r.bRequestType == USB_RECIP_INTERFACE) {
+ /*
+ * udc hardware is broken by design:
+ * - altsetting may only be zero;
+ * - hw resets all interfaces' eps;
+ * - ep reset doesn't include halt(?).
+ */
+ printf("broken set_interface (%d/%d)\n",
+ le16_to_cpu(u.r.wIndex),
+ le16_to_cpu(u.r.wValue));
+ goto config_change;
+ }
+ break;
+ /* hardware was supposed to hide this */
+ case USB_REQ_SET_ADDRESS:
+ debug("GOT SET ADDRESS\n");
+ if (u.r.bRequestType == USB_RECIP_DEVICE) {
+ ep0start(dev, 0, "address");
+ return;
+ }
+ break;
+ }
+
+ if (u.r.bRequestType & USB_DIR_IN)
+ dev->ep0state = EP0_IN_DATA_PHASE;
+ else
+ dev->ep0state = EP0_OUT_DATA_PHASE;
+
+ i = dev->driver->setup(&dev->gadget, &u.r);
+ if (i < 0) {
+ /* hardware automagic preventing STALL... */
+ if (dev->req_config) {
+ /*
+ * hardware sometimes neglects to tell
+ * tell us about config change events,
+ * so later ones may fail...
+ */
+ printf("config change %02x fail %d?\n",
+ u.r.bRequest, i);
+ return;
+ /*
+ * TODO experiment: if has_cfr,
+ * hardware didn't ACK; maybe we
+ * could actually STALL!
+ */
+ }
+ if (0) {
+stall:
+ /* uninitialized when goto stall */
+ i = 0;
+ }
+ debug("protocol STALL, "
+ "%02x err %d\n",
+ readl(&dev->regs->udccs[0]), i);
+
+ /*
+ * the watchdog timer helps deal with cases
+ * where udc seems to clear FST wrongly, and
+ * then NAKs instead of STALLing.
+ */
+ ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
+ start_watchdog(dev);
+ dev->ep0state = EP0_STALL;
+
+ /* deferred i/o == no response yet */
+ } else if (dev->req_pending) {
+ if (likely(dev->ep0state == EP0_IN_DATA_PHASE
+ || dev->req_std || u.r.wLength))
+ ep0start(dev, 0, "defer");
+ else
+ ep0start(dev, UDCCS0_IPR, "defer/IPR");
+ }
+
+ /* expect at least one data or status stage irq */
+ return;
+
+ } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
+ == (UDCCS0_OPR|UDCCS0_SA))) {
+ unsigned i;
+
+ /*
+ * pxa210/250 erratum 131 for B0/B1 says RNE lies.
+ * still observed on a pxa255 a0.
+ */
+ debug("e131\n");
+ nuke(ep, -EPROTO);
+
+ /* read SETUP data, but don't trust it too much */
+ for (i = 0; i < 8; i++)
+ u.raw[i] = (u8)readb(&dev->regs->uddr0);
+ if ((u.r.bRequestType & USB_RECIP_MASK)
+ > USB_RECIP_OTHER)
+ goto stall;
+ if (u.word[0] == 0 && u.word[1] == 0)
+ goto stall;
+ goto got_setup;
+ } else {
+ /*
+ * some random early IRQ:
+ * - we acked FST
+ * - IPR cleared
+ * - OPR got set, without SA (likely status stage)
+ */
+ debug("random IRQ %X %X\n", udccs0,
+ readl(&dev->regs->udccs[0]));
+ writel(udccs0 & (UDCCS0_SA|UDCCS0_OPR),
+ &dev->regs->udccs[0]);
+ }
+ break;
+ case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
+ if (udccs0 & UDCCS0_OPR) {
+ debug("ep0in premature status\n");
+ if (req)
+ done(ep, req, 0);
+ ep0_idle(dev);
+ } else /* irq was IPR clearing */ {
+ if (req) {
+ debug("next ep0 in packet\n");
+ /* this IN packet might finish the request */
+ (void) write_ep0_fifo(ep, req);
+ } /* else IN token before response was written */
+ }
+ break;
+ case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
+ if (udccs0 & UDCCS0_OPR) {
+ if (req) {
+ /* this OUT packet might finish the request */
+ if (read_ep0_fifo(ep, req))
+ done(ep, req, 0);
+ /* else more OUT packets expected */
+ } /* else OUT token before read was issued */
+ } else /* irq was IPR clearing */ {
+ debug("ep0out premature status\n");
+ if (req)
+ done(ep, req, 0);
+ ep0_idle(dev);
+ }
+ break;
+ case EP0_END_XFER:
+ if (req)
+ done(ep, req, 0);
+ /*
+ * ack control-IN status (maybe in-zlp was skipped)
+ * also appears after some config change events.
+ */
+ if (udccs0 & UDCCS0_OPR)
+ writel(UDCCS0_OPR, &dev->regs->udccs[0]);
+ ep0_idle(dev);
+ break;
+ case EP0_STALL:
+ writel(UDCCS0_FST, &dev->regs->udccs[0]);
+ break;
+ }
+
+ writel(USIR0_IR0, &dev->regs->usir0);
+}
+
+static void handle_ep(struct pxa25x_ep *ep)
+{
+ struct pxa25x_request *req;
+ int is_in = ep->bEndpointAddress & USB_DIR_IN;
+ int completed;
+ u32 udccs, tmp;
+
+ do {
+ completed = 0;
+ if (likely(!list_empty(&ep->queue)))
+ req = list_entry(ep->queue.next,
+ struct pxa25x_request, queue);
+ else
+ req = NULL;
+
+ /* TODO check FST handling */
+
+ udccs = readl(ep->reg_udccs);
+ if (unlikely(is_in)) { /* irq from TPC, SST, or (ISO) TUR */
+ tmp = UDCCS_BI_TUR;
+ if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
+ tmp |= UDCCS_BI_SST;
+ tmp &= udccs;
+ if (likely(tmp))
+ writel(tmp, ep->reg_udccs);
+ if (req && likely((udccs & UDCCS_BI_TFS) != 0))
+ completed = write_fifo(ep, req);
+
+ } else { /* irq from RPC (or for ISO, ROF) */
+ if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
+ tmp = UDCCS_BO_SST | UDCCS_BO_DME;
+ else
+ tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
+ tmp &= udccs;
+ if (likely(tmp))
+ writel(tmp, ep->reg_udccs);
+
+ /* fifos can hold packets, ready for reading... */
+ if (likely(req))
+ completed = read_fifo(ep, req);
+ else
+ pio_irq_disable(ep->bEndpointAddress);
+ }
+ ep->pio_irqs++;
+ } while (completed);
+}
+
+/*
+ * pxa25x_udc_irq - interrupt handler
+ *
+ * avoid delays in ep0 processing. the control handshaking isn't always
+ * under software control (pxa250c0 and the pxa255 are better), and delays
+ * could cause usb protocol errors.
+ */
+static struct pxa25x_udc memory;
+static int
+pxa25x_udc_irq(void)
+{
+ struct pxa25x_udc *dev = &memory;
+ int handled;
+
+ test_watchdog(dev);
+
+ dev->stats.irqs++;
+ do {
+ u32 udccr = readl(&dev->regs->udccr);
+
+ handled = 0;
+
+ /* SUSpend Interrupt Request */
+ if (unlikely(udccr & UDCCR_SUSIR)) {
+ udc_ack_int_UDCCR(UDCCR_SUSIR);
+ handled = 1;
+ debug("USB suspend\n");
+
+ if (dev->gadget.speed != USB_SPEED_UNKNOWN
+ && dev->driver
+ && dev->driver->suspend)
+ dev->driver->suspend(&dev->gadget);
+ ep0_idle(dev);
+ }
+
+ /* RESume Interrupt Request */
+ if (unlikely(udccr & UDCCR_RESIR)) {
+ udc_ack_int_UDCCR(UDCCR_RESIR);
+ handled = 1;
+ debug("USB resume\n");
+
+ if (dev->gadget.speed != USB_SPEED_UNKNOWN
+ && dev->driver
+ && dev->driver->resume)
+ dev->driver->resume(&dev->gadget);
+ }
+
+ /* ReSeT Interrupt Request - USB reset */
+ if (unlikely(udccr & UDCCR_RSTIR)) {
+ udc_ack_int_UDCCR(UDCCR_RSTIR);
+ handled = 1;
+
+ if ((readl(&dev->regs->udccr) & UDCCR_UDA) == 0) {
+ debug("USB reset start\n");
+
+ /*
+ * reset driver and endpoints,
+ * in case that's not yet done
+ */
+ stop_activity(dev, dev->driver);
+
+ } else {
+ debug("USB reset end\n");
+ dev->gadget.speed = USB_SPEED_FULL;
+ memset(&dev->stats, 0, sizeof dev->stats);
+ /* driver and endpoints are still reset */
+ }
+
+ } else {
+ u32 uicr0 = readl(&dev->regs->uicr0);
+ u32 uicr1 = readl(&dev->regs->uicr1);
+ u32 usir0 = readl(&dev->regs->usir0);
+ u32 usir1 = readl(&dev->regs->usir1);
+
+ usir0 = usir0 & ~uicr0;
+ usir1 = usir1 & ~uicr1;
+ int i;
+
+ if (unlikely(!usir0 && !usir1))
+ continue;
+
+ debug_cond(NOISY, "irq %02x.%02x\n", usir1, usir0);
+
+ /* control traffic */
+ if (usir0 & USIR0_IR0) {
+ dev->ep[0].pio_irqs++;
+ handle_ep0(dev);
+ handled = 1;
+ }
+
+ /* endpoint data transfers */
+ for (i = 0; i < 8; i++) {
+ u32 tmp = 1 << i;
+
+ if (i && (usir0 & tmp)) {
+ handle_ep(&dev->ep[i]);
+ setbits_le32(&dev->regs->usir0, tmp);
+ handled = 1;
+ }
+#ifndef CONFIG_USB_PXA25X_SMALL
+ if (usir1 & tmp) {
+ handle_ep(&dev->ep[i+8]);
+ setbits_le32(&dev->regs->usir1, tmp);
+ handled = 1;
+ }
+#endif
+ }
+ }
+
+ /* we could also ask for 1 msec SOF (SIR) interrupts */
+
+ } while (handled);
+ return IRQ_HANDLED;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * this uses load-time allocation and initialization (instead of
+ * doing it at run-time) to save code, eliminate fault paths, and
+ * be more obviously correct.
+ */
+static struct pxa25x_udc memory = {
+ .regs = UDC_REGS,
+
+ .gadget = {
+ .ops = &pxa25x_udc_ops,
+ .ep0 = &memory.ep[0].ep,
+ .name = driver_name,
+ },
+
+ /* control endpoint */
+ .ep[0] = {
+ .ep = {
+ .name = ep0name,
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = EP0_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .reg_udccs = &UDC_REGS->udccs[0],
+ .reg_uddr = &UDC_REGS->uddr0,
+ },
+
+ /* first group of endpoints */
+ .ep[1] = {
+ .ep = {
+ .name = "ep1in-bulk",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = BULK_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = BULK_FIFO_SIZE,
+ .bEndpointAddress = USB_DIR_IN | 1,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .reg_udccs = &UDC_REGS->udccs[1],
+ .reg_uddr = &UDC_REGS->uddr1,
+ },
+ .ep[2] = {
+ .ep = {
+ .name = "ep2out-bulk",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = BULK_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = BULK_FIFO_SIZE,
+ .bEndpointAddress = 2,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .reg_udccs = &UDC_REGS->udccs[2],
+ .reg_ubcr = &UDC_REGS->ubcr2,
+ .reg_uddr = &UDC_REGS->uddr2,
+ },
+#ifndef CONFIG_USB_PXA25X_SMALL
+ .ep[3] = {
+ .ep = {
+ .name = "ep3in-iso",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = ISO_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = ISO_FIFO_SIZE,
+ .bEndpointAddress = USB_DIR_IN | 3,
+ .bmAttributes = USB_ENDPOINT_XFER_ISOC,
+ .reg_udccs = &UDC_REGS->udccs[3],
+ .reg_uddr = &UDC_REGS->uddr3,
+ },
+ .ep[4] = {
+ .ep = {
+ .name = "ep4out-iso",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = ISO_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = ISO_FIFO_SIZE,
+ .bEndpointAddress = 4,
+ .bmAttributes = USB_ENDPOINT_XFER_ISOC,
+ .reg_udccs = &UDC_REGS->udccs[4],
+ .reg_ubcr = &UDC_REGS->ubcr4,
+ .reg_uddr = &UDC_REGS->uddr4,
+ },
+ .ep[5] = {
+ .ep = {
+ .name = "ep5in-int",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = INT_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = INT_FIFO_SIZE,
+ .bEndpointAddress = USB_DIR_IN | 5,
+ .bmAttributes = USB_ENDPOINT_XFER_INT,
+ .reg_udccs = &UDC_REGS->udccs[5],
+ .reg_uddr = &UDC_REGS->uddr5,
+ },
+
+ /* second group of endpoints */
+ .ep[6] = {
+ .ep = {
+ .name = "ep6in-bulk",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = BULK_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = BULK_FIFO_SIZE,
+ .bEndpointAddress = USB_DIR_IN | 6,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .reg_udccs = &UDC_REGS->udccs[6],
+ .reg_uddr = &UDC_REGS->uddr6,
+ },
+ .ep[7] = {
+ .ep = {
+ .name = "ep7out-bulk",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = BULK_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = BULK_FIFO_SIZE,
+ .bEndpointAddress = 7,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .reg_udccs = &UDC_REGS->udccs[7],
+ .reg_ubcr = &UDC_REGS->ubcr7,
+ .reg_uddr = &UDC_REGS->uddr7,
+ },
+ .ep[8] = {
+ .ep = {
+ .name = "ep8in-iso",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = ISO_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = ISO_FIFO_SIZE,
+ .bEndpointAddress = USB_DIR_IN | 8,
+ .bmAttributes = USB_ENDPOINT_XFER_ISOC,
+ .reg_udccs = &UDC_REGS->udccs[8],
+ .reg_uddr = &UDC_REGS->uddr8,
+ },
+ .ep[9] = {
+ .ep = {
+ .name = "ep9out-iso",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = ISO_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = ISO_FIFO_SIZE,
+ .bEndpointAddress = 9,
+ .bmAttributes = USB_ENDPOINT_XFER_ISOC,
+ .reg_udccs = &UDC_REGS->udccs[9],
+ .reg_ubcr = &UDC_REGS->ubcr9,
+ .reg_uddr = &UDC_REGS->uddr9,
+ },
+ .ep[10] = {
+ .ep = {
+ .name = "ep10in-int",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = INT_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = INT_FIFO_SIZE,
+ .bEndpointAddress = USB_DIR_IN | 10,
+ .bmAttributes = USB_ENDPOINT_XFER_INT,
+ .reg_udccs = &UDC_REGS->udccs[10],
+ .reg_uddr = &UDC_REGS->uddr10,
+ },
+
+ /* third group of endpoints */
+ .ep[11] = {
+ .ep = {
+ .name = "ep11in-bulk",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = BULK_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = BULK_FIFO_SIZE,
+ .bEndpointAddress = USB_DIR_IN | 11,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .reg_udccs = &UDC_REGS->udccs[11],
+ .reg_uddr = &UDC_REGS->uddr11,
+ },
+ .ep[12] = {
+ .ep = {
+ .name = "ep12out-bulk",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = BULK_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = BULK_FIFO_SIZE,
+ .bEndpointAddress = 12,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .reg_udccs = &UDC_REGS->udccs[12],
+ .reg_ubcr = &UDC_REGS->ubcr12,
+ .reg_uddr = &UDC_REGS->uddr12,
+ },
+ .ep[13] = {
+ .ep = {
+ .name = "ep13in-iso",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = ISO_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = ISO_FIFO_SIZE,
+ .bEndpointAddress = USB_DIR_IN | 13,
+ .bmAttributes = USB_ENDPOINT_XFER_ISOC,
+ .reg_udccs = &UDC_REGS->udccs[13],
+ .reg_uddr = &UDC_REGS->uddr13,
+ },
+ .ep[14] = {
+ .ep = {
+ .name = "ep14out-iso",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = ISO_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = ISO_FIFO_SIZE,
+ .bEndpointAddress = 14,
+ .bmAttributes = USB_ENDPOINT_XFER_ISOC,
+ .reg_udccs = &UDC_REGS->udccs[14],
+ .reg_ubcr = &UDC_REGS->ubcr14,
+ .reg_uddr = &UDC_REGS->uddr14,
+ },
+ .ep[15] = {
+ .ep = {
+ .name = "ep15in-int",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = INT_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = INT_FIFO_SIZE,
+ .bEndpointAddress = USB_DIR_IN | 15,
+ .bmAttributes = USB_ENDPOINT_XFER_INT,
+ .reg_udccs = &UDC_REGS->udccs[15],
+ .reg_uddr = &UDC_REGS->uddr15,
+ },
+#endif /* !CONFIG_USB_PXA25X_SMALL */
+};
+
+static void udc_command(int cmd)
+{
+ switch (cmd) {
+ case PXA2XX_UDC_CMD_CONNECT:
+ setbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO),
+ GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO));
+
+ /* enable pullup */
+ writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
+ GPCR(CONFIG_USB_DEV_PULLUP_GPIO));
+
+ debug("Connected to USB\n");
+ break;
+
+ case PXA2XX_UDC_CMD_DISCONNECT:
+ /* disable pullup resistor */
+ writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
+ GPSR(CONFIG_USB_DEV_PULLUP_GPIO));
+
+ /* setup pin as input, line will float */
+ clrbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO),
+ GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO));
+
+ debug("Disconnected from USB\n");
+ break;
+ }
+}
+
+static struct pxa2xx_udc_mach_info mach_info = {
+ .udc_command = udc_command,
+};
+
+/*
+ * when a driver is successfully registered, it will receive
+ * control requests including set_configuration(), which enables
+ * non-control requests. then usb traffic follows until a
+ * disconnect is reported. then a host may connect again, or
+ * the driver might get unbound.
+ */
+int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+{
+ struct pxa25x_udc *dev = &memory;
+ int retval;
+ uint32_t chiprev;
+
+ if (!driver
+ || driver->speed < USB_SPEED_FULL
+ || !driver->disconnect
+ || !driver->setup)
+ return -EINVAL;
+ if (!dev)
+ return -ENODEV;
+ if (dev->driver)
+ return -EBUSY;
+
+ /* Enable clock for usb controller */
+ setbits_le32(CKEN, CKEN11_USB);
+
+ /* first hook up the driver ... */
+ dev->driver = driver;
+ dev->pullup = 1;
+
+ /* trigger chiprev-specific logic */
+ switch ((chiprev = pxa_get_cpu_revision())) {
+ case PXA255_A0:
+ dev->has_cfr = 1;
+ break;
+ case PXA250_A0:
+ case PXA250_A1:
+ /* A0/A1 "not released"; ep 13, 15 unusable */
+ /* fall through */
+ case PXA250_B2: case PXA210_B2:
+ case PXA250_B1: case PXA210_B1:
+ case PXA250_B0: case PXA210_B0:
+ /* OUT-DMA is broken ... */
+ /* fall through */
+ case PXA250_C0: case PXA210_C0:
+ break;
+ default:
+ printf("%s: unrecognized processor: %08x\n",
+ DRIVER_NAME, chiprev);
+ return -ENODEV;
+ }
+
+ the_controller = dev;
+
+ /* prepare watchdog timer */
+ dev->watchdog.running = 0;
+ dev->watchdog.period = 5000 * CONFIG_SYS_HZ / 1000000; /* 5 ms */
+ dev->watchdog.function = udc_watchdog;
+
+ udc_disable(dev);
+ udc_reinit(dev);
+
+ dev->mach = &mach_info;
+
+ dev->gadget.name = "pxa2xx_udc";
+ retval = driver->bind(&dev->gadget);
+ if (retval) {
+ printf("bind to driver %s --> error %d\n",
+ DRIVER_NAME, retval);
+ dev->driver = NULL;
+ return retval;
+ }
+
+ /*
+ * ... then enable host detection and ep0; and we're ready
+ * for set_configuration as well as eventual disconnect.
+ */
+ printf("registered gadget driver '%s'\n", DRIVER_NAME);
+
+ pullup(dev);
+ dump_state(dev);
+ return 0;
+}
+
+static void
+stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver)
+{
+ int i;
+
+ /* don't disconnect drivers more than once */
+ if (dev->gadget.speed == USB_SPEED_UNKNOWN)
+ driver = NULL;
+ dev->gadget.speed = USB_SPEED_UNKNOWN;
+
+ /* prevent new request submissions, kill any outstanding requests */
+ for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
+ struct pxa25x_ep *ep = &dev->ep[i];
+
+ ep->stopped = 1;
+ nuke(ep, -ESHUTDOWN);
+ }
+ stop_watchdog(dev);
+
+ /* report disconnect; the driver is already quiesced */
+ if (driver)
+ driver->disconnect(&dev->gadget);
+
+ /* re-init driver-visible data structures */
+ udc_reinit(dev);
+}
+
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+ struct pxa25x_udc *dev = the_controller;
+
+ if (!dev)
+ return -ENODEV;
+ if (!driver || driver != dev->driver || !driver->unbind)
+ return -EINVAL;
+
+ local_irq_disable();
+ dev->pullup = 0;
+ pullup(dev);
+ stop_activity(dev, driver);
+ local_irq_enable();
+
+ driver->unbind(&dev->gadget);
+ dev->driver = NULL;
+
+ printf("unregistered gadget driver '%s'\n", DRIVER_NAME);
+ dump_state(dev);
+
+ the_controller = NULL;
+
+ clrbits_le32(CKEN, CKEN11_USB);
+
+ return 0;
+}
+
+extern void udc_disconnect(void)
+{
+ setbits_le32(CKEN, CKEN11_USB);
+ udc_clear_mask_UDCCR(UDCCR_UDE);
+ udc_command(PXA2XX_UDC_CMD_DISCONNECT);
+ clrbits_le32(CKEN, CKEN11_USB);
+}
+
+/*-------------------------------------------------------------------------*/
+
+extern int
+usb_gadget_handle_interrupts(void)
+{
+ return pxa25x_udc_irq();
+}
--- /dev/null
+/*
+ * Intel PXA25x on-chip full speed USB device controller
+ *
+ * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+ * Copyright (C) 2003 David Brownell
+ * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __LINUX_USB_GADGET_PXA25X_H
+#define __LINUX_USB_GADGET_PXA25X_H
+
+#include <linux/types.h>
+#include <asm/arch/regs-usb.h>
+
+/*
+ * Prefetching support - only ARMv5.
+ */
+
+#ifdef ARCH_HAS_PREFETCH
+static inline void prefetch(const void *ptr)
+{
+ __asm__ __volatile__(
+ "pld\t%a0"
+ :
+ : "p" (ptr)
+ : "cc");
+}
+
+#define prefetchw(ptr) prefetch(ptr)
+#endif /* ARCH_HAS_PREFETCH */
+
+/*-------------------------------------------------------------------------*/
+
+#define UDC_REGS ((struct pxa25x_udc_regs *)PXA25X_UDC_BASE)
+
+/*-------------------------------------------------------------------------*/
+
+struct pxa2xx_udc_mach_info {
+ int (*udc_is_connected)(void); /* do we see host? */
+ void (*udc_command)(int cmd);
+#define PXA2XX_UDC_CMD_CONNECT 0 /* let host see us */
+#define PXA2XX_UDC_CMD_DISCONNECT 1 /* so host won't see us */
+};
+
+struct pxa25x_udc;
+
+struct pxa25x_ep {
+ struct usb_ep ep;
+ struct pxa25x_udc *dev;
+
+ const struct usb_endpoint_descriptor *desc;
+ struct list_head queue;
+ unsigned long pio_irqs;
+
+ unsigned short fifo_size;
+ u8 bEndpointAddress;
+ u8 bmAttributes;
+
+ unsigned stopped:1;
+
+ /* UDCCS = UDC Control/Status for this EP
+ * UBCR = UDC Byte Count Remaining (contents of OUT fifo)
+ * UDDR = UDC Endpoint Data Register (the fifo)
+ * DRCM = DMA Request Channel Map
+ */
+ u32 *reg_udccs;
+ u32 *reg_ubcr;
+ u32 *reg_uddr;
+};
+
+struct pxa25x_request {
+ struct usb_request req;
+ struct list_head queue;
+};
+
+enum ep0_state {
+ EP0_IDLE,
+ EP0_IN_DATA_PHASE,
+ EP0_OUT_DATA_PHASE,
+ EP0_END_XFER,
+ EP0_STALL,
+};
+
+#define EP0_FIFO_SIZE 16U
+#define BULK_FIFO_SIZE 64U
+#define ISO_FIFO_SIZE 256U
+#define INT_FIFO_SIZE 8U
+
+struct udc_stats {
+ struct ep0stats {
+ unsigned long ops;
+ unsigned long bytes;
+ } read, write;
+ unsigned long irqs;
+};
+
+#ifdef CONFIG_USB_PXA25X_SMALL
+/* when memory's tight, SMALL config saves code+data. */
+#define PXA_UDC_NUM_ENDPOINTS 3
+#endif
+
+#ifndef PXA_UDC_NUM_ENDPOINTS
+#define PXA_UDC_NUM_ENDPOINTS 16
+#endif
+
+struct pxa25x_watchdog {
+ unsigned running:1;
+ ulong period;
+ ulong base;
+ struct pxa25x_udc *udc;
+
+ void (*function)(struct pxa25x_udc *udc);
+};
+
+struct pxa25x_udc {
+ struct usb_gadget gadget;
+ struct usb_gadget_driver *driver;
+ struct pxa25x_udc_regs *regs;
+
+ enum ep0_state ep0state;
+ struct udc_stats stats;
+ unsigned got_irq:1,
+ pullup:1,
+ has_cfr:1,
+ req_pending:1,
+ req_std:1,
+ req_config:1,
+ active:1;
+
+ struct clk *clk;
+ struct pxa2xx_udc_mach_info *mach;
+ u64 dma_mask;
+ struct pxa25x_ep ep[PXA_UDC_NUM_ENDPOINTS];
+
+ struct pxa25x_watchdog watchdog;
+};
+
+/*-------------------------------------------------------------------------*/
+
+static struct pxa25x_udc *the_controller;
+
+/*-------------------------------------------------------------------------*/
+
+#ifndef DEBUG
+# define NOISY 0
+#endif
+
+#endif /* __LINUX_USB_GADGET_PXA25X_H */
#include <asm/io.h>
#include <usb.h>
#include "ehci.h"
-#include "ehci-core.h"
#include <asm/arch/cpu.h>
#include <asm/arch/armada100.h>
#include <asm/arch/utmi-armada100.h>
/*
* EHCI host controller init
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
if (utmi_init() < 0)
return -1;
- hccr = (struct ehci_hccr *)(ARMD1_USB_HOST_BASE + 0x100);
- hcor = (struct ehci_hcor *)((uint32_t) hccr
- + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)(ARMD1_USB_HOST_BASE + 0x100);
+ *hcor = (struct ehci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
debug("armada100-ehci: init hccr %x and hcor %x hc_length %d\n",
- (uint32_t)hccr, (uint32_t)hcor,
- (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
return 0;
}
/*
* EHCI host controller stop
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
#include <asm/arch/clk.h>
#include "ehci.h"
-#include "ehci-core.h"
/* Enable UTMI PLL time out 500us
* 10 times as datasheet specified
*/
#define EN_UPLL_TIMEOUT 500UL
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
ulong start_time, tmp_time;
/* Enable USB Host clock */
writel(1 << ATMEL_ID_UHPHS, &pmc->pcer);
- hccr = (struct ehci_hccr *)ATMEL_BASE_EHCI;
- hcor = (struct ehci_hcor *)((uint32_t)hccr +
- HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)ATMEL_BASE_EHCI;
+ *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
return 0;
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
ulong start_time, tmp_time;
+++ /dev/null
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Excito Elektronik i Skåne AB
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_CORE_H
-#define USB_EHCI_CORE_H
-
-extern int rootdev;
-extern struct ehci_hccr *hccr;
-extern volatile struct ehci_hcor *hcor;
-
-#endif
#include <asm/arch/system.h>
#include <asm/arch/power.h>
#include "ehci.h"
-#include "ehci-core.h"
/* Setup the EHCI host controller. */
static void setup_usb_phy(struct exynos_usb_phy *usb)
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct exynos_usb_phy *usb;
usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
setup_usb_phy(usb);
- hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci();
- hcor = (struct ehci_hcor *)((uint32_t) hccr
- + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci();
+ *hcor = (struct ehci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
- (uint32_t)hccr, (uint32_t)hcor,
- (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
return 0;
}
* Destroy the appropriate control structures corresponding
* the EHCI host controller.
*/
-int ehci_hcd_stop()
+int ehci_hcd_stop(int index)
{
struct exynos_usb_phy *usb;
#include <hwconfig.h>
#include "ehci.h"
-#include "ehci-core.h"
/*
* Create the appropriate control structures to manage
*
* Excerpts from linux ehci fsl driver.
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
const char *phy_type = NULL;
#endif
ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
- hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
- hcor = (struct ehci_hcor *)((uint32_t) hccr +
- HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
/* Set to Host mode */
setbits_le32(&ehci->usbmode, CM_HOST);
setbits_be32(&ehci->control, UTMI_PHY_EN);
udelay(1000); /* delay required for PHY Clk to appear */
#endif
- out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI);
+ out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
} else {
#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
clrbits_be32(&ehci->control, UTMI_PHY_EN);
setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
udelay(1000); /* delay required for PHY Clk to appear */
#endif
- out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI);
+ out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
}
/* Enable interface. */
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
#include "ehci.h"
-int rootdev;
-struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
-volatile struct ehci_hcor *hcor;
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
-static uint16_t portreset;
-DEFINE_ALIGN_BUFFER(struct QH, qh_list, 1, USB_DMA_MINALIGN);
+static struct ehci_ctrl {
+ struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
+ struct ehci_hcor *hcor;
+ int rootdev;
+ uint16_t portreset;
+ struct QH qh_list __attribute__((aligned(USB_DMA_MINALIGN)));
+} ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
#define ALIGN_END_ADDR(type, ptr, size) \
((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
return -1;
}
-static int ehci_reset(void)
+static int ehci_reset(int index)
{
uint32_t cmd;
uint32_t tmp;
uint32_t *reg_ptr;
int ret = 0;
- cmd = ehci_readl(&hcor->or_usbcmd);
+ cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
cmd = (cmd & ~CMD_RUN) | CMD_RESET;
- ehci_writel(&hcor->or_usbcmd, cmd);
- ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000);
+ ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
+ ret = handshake((uint32_t *)&ehcic[index].hcor->or_usbcmd,
+ CMD_RESET, 0, 250 * 1000);
if (ret < 0) {
printf("EHCI fail to reset\n");
goto out;
}
if (ehci_is_TDI()) {
- reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE);
+ reg_ptr = (uint32_t *)((u8 *)ehcic[index].hcor + USBMODE);
tmp = ehci_readl(reg_ptr);
tmp |= USBMODE_CM_HC;
#if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
}
#ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
- cmd = ehci_readl(&hcor->or_txfilltuning);
+ cmd = ehci_readl(&ehcic[index].hcor->or_txfilltuning);
cmd &= ~TXFIFO_THRESH_MASK;
cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
- ehci_writel(&hcor->or_txfilltuning, cmd);
+ ehci_writel(&ehcic[index].hcor->or_txfilltuning, cmd);
#endif
out:
return ret;
struct qTD *qtd;
int qtd_count = 0;
int qtd_counter = 0;
-
volatile struct qTD *vtd;
unsigned long ts;
uint32_t *tdp;
uint32_t cmd;
int timeout;
int ret = 0;
+ struct ehci_ctrl *ctrl = dev->controller;
debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
buffer, length, req);
* qh_overlay.qt_next ...... 13-10 H
* - qh_overlay.qt_altnext
*/
- qh->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
+ qh->qh_link = cpu_to_hc32((uint32_t)&ctrl->qh_list | QH_LINK_TYPE_QH);
c = usb_pipespeed(pipe) != USB_SPEED_HIGH && !usb_pipeendpoint(pipe);
maxpacket = usb_maxpacket(dev, pipe);
endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
tdp = &qtd[qtd_counter++].qt_next;
}
- qh_list->qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH);
+ ctrl->qh_list.qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH);
/* Flush dcache */
- flush_dcache_range((uint32_t)qh_list,
- ALIGN_END_ADDR(struct QH, qh_list, 1));
+ flush_dcache_range((uint32_t)&ctrl->qh_list,
+ ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1));
flush_dcache_range((uint32_t)qtd,
ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
/* Set async. queue head pointer. */
- ehci_writel(&hcor->or_asynclistaddr, (uint32_t)qh_list);
+ ehci_writel(&ctrl->hcor->or_asynclistaddr, (uint32_t)&ctrl->qh_list);
- usbsts = ehci_readl(&hcor->or_usbsts);
- ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f));
+ usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
+ ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
/* Enable async. schedule. */
- cmd = ehci_readl(&hcor->or_usbcmd);
+ cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
cmd |= CMD_ASE;
- ehci_writel(&hcor->or_usbcmd, cmd);
+ ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
- ret = handshake((uint32_t *)&hcor->or_usbsts, STS_ASS, STS_ASS,
+ ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
100 * 1000);
if (ret < 0) {
printf("EHCI fail timeout STS_ASS set\n");
timeout = USB_TIMEOUT_MS(pipe);
do {
/* Invalidate dcache */
- invalidate_dcache_range((uint32_t)qh_list,
- ALIGN_END_ADDR(struct QH, qh_list, 1));
+ invalidate_dcache_range((uint32_t)&ctrl->qh_list,
+ ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
invalidate_dcache_range((uint32_t)qh,
ALIGN_END_ADDR(struct QH, qh, 1));
invalidate_dcache_range((uint32_t)qtd,
printf("EHCI timed out on TD - token=%#x\n", token);
/* Disable async schedule. */
- cmd = ehci_readl(&hcor->or_usbcmd);
+ cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
cmd &= ~CMD_ASE;
- ehci_writel(&hcor->or_usbcmd, cmd);
+ ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
- ret = handshake((uint32_t *)&hcor->or_usbsts, STS_ASS, 0,
+ ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
100 * 1000);
if (ret < 0) {
printf("EHCI fail timeout STS_ASS reset\n");
} else {
dev->act_len = 0;
debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
- dev->devnum, ehci_readl(&hcor->or_usbsts),
- ehci_readl(&hcor->or_portsc[0]),
- ehci_readl(&hcor->or_portsc[1]));
+ dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
+ ehci_readl(&ctrl->hcor->or_portsc[0]),
+ ehci_readl(&ctrl->hcor->or_portsc[1]));
}
free(qtd);
int len, srclen;
uint32_t reg;
uint32_t *status_reg;
+ struct ehci_ctrl *ctrl = dev->controller;
if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
printf("The request port(%d) is not configured\n",
le16_to_cpu(req->index) - 1);
return -1;
}
- status_reg = (uint32_t *)&hcor->or_portsc[
+ status_reg = (uint32_t *)&ctrl->hcor->or_portsc[
le16_to_cpu(req->index) - 1];
srclen = 0;
break;
case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
debug("USB_REQ_SET_ADDRESS\n");
- rootdev = le16_to_cpu(req->value);
+ ctrl->rootdev = le16_to_cpu(req->value);
break;
case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
debug("USB_REQ_SET_CONFIGURATION\n");
tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
if (reg & EHCI_PS_OCC)
tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
- if (portreset & (1 << le16_to_cpu(req->index)))
+ if (ctrl->portreset & (1 << le16_to_cpu(req->index)))
tmpbuf[2] |= USB_PORT_STAT_C_RESET;
srcptr = tmpbuf;
ehci_writel(status_reg, reg);
break;
case USB_PORT_FEAT_POWER:
- if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) {
+ if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
reg |= EHCI_PS_PP;
ehci_writel(status_reg, reg);
}
ret = handshake(status_reg, EHCI_PS_PR, 0,
2 * 1000);
if (!ret)
- portreset |=
+ ctrl->portreset |=
1 << le16_to_cpu(req->index);
else
printf("port(%d) reset error\n",
goto unknown;
}
/* unblock posted writes */
- (void) ehci_readl(&hcor->or_usbcmd);
+ (void) ehci_readl(&ctrl->hcor->or_usbcmd);
break;
case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
reg = ehci_readl(status_reg);
reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE;
break;
case USB_PORT_FEAT_POWER:
- if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams)))
+ if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP);
case USB_PORT_FEAT_C_CONNECTION:
reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC;
reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
break;
case USB_PORT_FEAT_C_RESET:
- portreset &= ~(1 << le16_to_cpu(req->index));
+ ctrl->portreset &= ~(1 << le16_to_cpu(req->index));
break;
default:
debug("unknown feature %x\n", le16_to_cpu(req->value));
}
ehci_writel(status_reg, reg);
/* unblock posted write */
- (void) ehci_readl(&hcor->or_usbcmd);
+ (void) ehci_readl(&ctrl->hcor->or_usbcmd);
break;
default:
debug("Unknown request\n");
return -1;
}
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
- return ehci_hcd_stop();
+ return ehci_hcd_stop(index);
}
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
uint32_t reg;
uint32_t cmd;
+ struct QH *qh_list;
- if (ehci_hcd_init())
+ if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor))
return -1;
/* EHCI spec section 4.1 */
- if (ehci_reset())
+ if (ehci_reset(index))
return -1;
#if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
- if (ehci_hcd_init())
+ if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor))
return -1;
#endif
+ qh_list = &ehcic[index].qh_list;
+
/* Set head of reclaim list */
memset(qh_list, 0, sizeof(*qh_list));
qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
qh_list->qh_overlay.qt_token =
cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
- reg = ehci_readl(&hccr->cr_hcsparams);
+ reg = ehci_readl(&ehcic[index].hccr->cr_hcsparams);
descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
- printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
+ debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
/* Port Indicators */
if (HCS_INDICATOR(reg))
put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
| 0x01, &descriptor.hub.wHubCharacteristics);
/* Start the host controller. */
- cmd = ehci_readl(&hcor->or_usbcmd);
+ cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
/*
* Philips, Intel, and maybe others need CMD_RUN before the
* root hub will detect new devices (why?); NEC doesn't
*/
cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
cmd |= CMD_RUN;
- ehci_writel(&hcor->or_usbcmd, cmd);
+ ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
/* take control over the ports */
- cmd = ehci_readl(&hcor->or_configflag);
+ cmd = ehci_readl(&ehcic[index].hcor->or_configflag);
cmd |= FLAG_CF;
- ehci_writel(&hcor->or_configflag, cmd);
+ ehci_writel(&ehcic[index].hcor->or_configflag, cmd);
/* unblock posted write */
- cmd = ehci_readl(&hcor->or_usbcmd);
+ cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
mdelay(5);
- reg = HC_VERSION(ehci_readl(&hccr->cr_capbase));
+ reg = HC_VERSION(ehci_readl(&ehcic[index].hccr->cr_capbase));
printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
- rootdev = 0;
+ ehcic[index].rootdev = 0;
+ *controller = &ehcic[index];
return 0;
}
submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
int length, struct devrequest *setup)
{
+ struct ehci_ctrl *ctrl = dev->controller;
if (usb_pipetype(pipe) != PIPE_CONTROL) {
debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
return -1;
}
- if (usb_pipedevice(pipe) == rootdev) {
- if (!rootdev)
+ if (usb_pipedevice(pipe) == ctrl->rootdev) {
+ if (!ctrl->rootdev)
dev->speed = USB_SPEED_HIGH;
return ehci_submit_root(dev, pipe, buffer, length, setup);
}
#include <usb.h>
#include "ehci.h"
-#include "ehci-core.h"
/*
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- hccr = (struct ehci_hccr *)(0xcd000100);
- hcor = (struct ehci_hcor *)((uint32_t) hccr
- + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)(0xcd000100);
+ *hcor = (struct ehci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
printf("IXP4XX init hccr %x and hcor %x hc_length %d\n",
- (uint32_t)hccr, (uint32_t)hcor,
- (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
return 0;
}
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
#include <asm/io.h>
#include <usb.h>
#include "ehci.h"
-#include "ehci-core.h"
#include <asm/arch/cpu.h>
#if defined(CONFIG_KIRKWOOD)
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
usb_brg_adrdec_setup();
- hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
- hcor = (struct ehci_hcor *)((uint32_t) hccr
- + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
+ *hcor = (struct ehci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
- (uint32_t)hccr, (uint32_t)hcor,
- (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
return 0;
}
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
#include <usb/ehci-fsl.h>
#include "ehci.h"
-#include "ehci-core.h"
static void fsl_setup_phy(volatile struct ehci_hcor *);
static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci);
* This code is derived from EHCI FSL USB Linux driver for MPC5121
*
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
volatile struct usb_ehci *ehci;
/* Hook the memory mapped registers for EHCI-Controller */
ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
- hccr = (struct ehci_hccr *)((uint32_t)&(ehci->caplength));
- hcor = (struct ehci_hcor *)((uint32_t) hccr +
- HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)((uint32_t)&(ehci->caplength));
+ *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
/* configure interface for UTMI_WIDE */
usb_platform_dr_init(ehci);
/* Init Phy USB0 to UTMI+ */
- fsl_setup_phy(hcor);
+ fsl_setup_phy(*hcor);
/* Set to host mode */
fsl_platform_set_host_mode(ehci);
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
volatile struct usb_ehci *ehci;
int exit_status = 0;
- if (hcor) {
- /* Unhook struct */
- hccr = NULL;
- hcor = NULL;
-
- /* Reset the USB controller */
- ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
- exit_status = reset_usb_controller(ehci);
- }
+ /* Reset the USB controller */
+ ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
+ exit_status = reset_usb_controller(ehci);
return exit_status;
}
#include <asm/arch/iomux.h>
#include "ehci.h"
-#include "ehci-core.h"
#define MX5_USBOTHER_REGS_OFFSET 0x800
void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
__attribute((weak, alias("__board_ehci_hcd_postinit")));
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
#ifdef CONFIG_MX53
set_usboh3_clk();
enable_usboh3_clk(1);
- set_usb_phy2_clk();
+ set_usb_phy_clk();
+ enable_usb_phy1_clk(1);
enable_usb_phy2_clk(1);
mdelay(1);
ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
(0x200 * CONFIG_MXC_USB_PORT));
- hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
- hcor = (struct ehci_hcor *)((uint32_t)hccr +
- HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
setbits_le32(&ehci->usbmode, CM_HOST);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
return 0;
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
#include <asm/imx-common/iomux-v3.h>
#include "ehci.h"
-#include "ehci-core.h"
#define USB_OTGREGS_OFFSET 0x000
#define USB_H1REGS_OFFSET 0x200
__raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
}
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
(0x200 * CONFIG_MXC_USB_PORT));
- hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
- hcor = (struct ehci_hcor *)((uint32_t)hccr +
- HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
setbits_le32(&ehci->usbmode, CM_HOST);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
return 0;
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
#include <errno.h>
#include "ehci.h"
-#include "ehci-core.h"
#define USBCTRL_OTGBASE_OFFSET 0x600
return 0;
}
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
#ifdef CONFIG_MX31
ehci = (struct usb_ehci *)(IMX_USB_BASE +
(0x200 * CONFIG_MXC_USB_PORT));
- hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
- hcor = (struct ehci_hcor *)((uint32_t) hccr +
- HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
setbits_le32(&ehci->usbmode, CM_HOST);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
#include <asm/arch/regs-usb.h>
#include <asm/arch/regs-usbphy.h>
-#include "ehci-core.h"
#include "ehci.h"
#if (CONFIG_EHCI_MXS_PORT != 0) && (CONFIG_EHCI_MXS_PORT != 1)
#define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2)
#define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16)
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
int ret;
&ehci_mxs.phy_regs->hw_usbphy_ctrl_set);
usb_base = ((uint32_t)ehci_mxs.usb_regs) + 0x100;
- hccr = (struct ehci_hccr *)usb_base;
+ *hccr = (struct ehci_hccr *)usb_base;
- cap_base = ehci_readl(&hccr->cr_capbase);
- hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
+ cap_base = ehci_readl(&(*hccr)->cr_capbase);
+ *hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
return 0;
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
int ret;
- uint32_t tmp;
+ uint32_t usb_base, cap_base, tmp;
struct mxs_register_32 *digctl_ctrl =
(struct mxs_register_32 *)HW_DIGCTL_CTRL;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct ehci_hccr *hccr;
+ struct ehci_hcor *hcor;
ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT);
if (ret)
return ret;
/* Stop the USB port */
+ usb_base = ((uint32_t)ehci_mxs.usb_regs) + 0x100;
+ hccr = (struct ehci_hccr *)usb_base;
+ cap_base = ehci_readl(&hccr->cr_capbase);
+ hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
+
tmp = ehci_readl(&hcor->or_usbcmd);
tmp &= ~CMD_RUN;
ehci_writel(tmp, &hcor->or_usbcmd);
#include <asm/gpio.h>
#include <asm/arch/ehci.h>
#include <asm/ehci-omap.h>
-#include "ehci-core.h"
+
+#include "ehci.h"
static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE;
static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE;
* Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
* See there for additional Copyrights.
*/
-int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata)
+int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
int ret;
unsigned int i, reg = 0, rev = 0;
if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
omap_ehci_soft_phy_reset(i);
- hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE);
- hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10);
+ *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE);
+ *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10);
debug("OMAP EHCI init done\n");
return 0;
#include <usb.h>
#include "ehci.h"
-#include "ehci-core.h"
#ifdef CONFIG_PCI_EHCI_DEVICE
static struct pci_device_id ehci_pci_ids[] = {
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
pci_dev_t pdev;
return -1;
}
- hccr = (struct ehci_hccr *)pci_map_bar(pdev,
+ *hccr = (struct ehci_hccr *)pci_map_bar(pdev,
PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
- hcor = (struct ehci_hcor *)((uint32_t) hccr +
- HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
- (uint32_t)hccr, (uint32_t)hcor,
- (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
return 0;
}
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
#include <usb.h>
#include "ehci.h"
-#include "ehci-core.h"
/*
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- hccr = (struct ehci_hccr *)(CONFIG_SYS_PPC4XX_USB_ADDR);
- hcor = (struct ehci_hcor *)((uint32_t) hccr +
- HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)(CONFIG_SYS_PPC4XX_USB_ADDR);
+ *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
return 0;
}
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
#include <usb.h>
#include "ehci.h"
-#include "ehci-core.h"
#include <asm/errno.h>
#include <asm/arch/usb.h>
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
u32 our_hccr, our_hcor;
* Select the first port, as we don't have a way of selecting others
* yet
*/
- if (tegrausb_start_port(0, &our_hccr, &our_hcor))
+ if (tegrausb_start_port(index, &our_hccr, &our_hcor))
return -1;
- hccr = (struct ehci_hccr *)our_hccr;
- hcor = (struct ehci_hcor *)our_hcor;
+ *hccr = (struct ehci_hccr *)our_hccr;
+ *hcor = (struct ehci_hcor *)our_hcor;
return 0;
}
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
- tegrausb_stop_port();
- return 0;
+ return tegrausb_stop_port(index);
}
#include <usb.h>
#include "ehci.h"
-#include "ehci-core.h"
int vct_ehci_hcd_init(u32 *hccr, u32 *hcor);
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
int ret;
u32 vct_hccr;
if (ret)
return ret;
- hccr = (struct ehci_hccr *)vct_hccr;
- hcor = (struct ehci_hcor *)vct_hcor;
+ *hccr = (struct ehci_hccr *)vct_hccr;
+ *hcor = (struct ehci_hcor *)vct_hcor;
return 0;
}
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
};
/* Low level init functions */
-int ehci_hcd_init(void);
-int ehci_hcd_stop(void);
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor);
+int ehci_hcd_stop(int index);
#endif /* USB_EHCI_H */
return 0;
}
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller))
{
struct isp116x *isp116x = &isp116x_dev;
return 0;
}
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
struct isp116x *isp116x = &isp116x_dev;
*/
static char ohci_inited = 0;
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
#ifdef CONFIG_PCI_OHCI
pci_dev_t pdev;
return 0;
}
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
/* this gets called really early - before the controller has */
/* even been initialized! */
return 0;
}
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller))
{
struct r8a66597 *r8a66597 = &gr8a66597;
return 0;
}
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
disable_controller(&gr8a66597);
return 1;
}
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
root_hub_devnum = 0;
sl811_hc_reset();
return 0;
}
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
sl811_hc_reset();
return 0;
/*
* This function initializes the usb controller module.
*/
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
u8 power;
u32 timeout;
/*
* This function stops the operation of the davinci usb module.
*/
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
/* Reset the USB module */
musb_platform_deinit();
return ulpi_write(ulpi_vp, &ulpi->function_ctrl, val);
}
-int ulpi_set_vbus(struct ulpi_viewport *ulpi_vp, int on, int ext_power,
- int ext_ind)
+int ulpi_set_vbus(struct ulpi_viewport *ulpi_vp, int on, int ext_power)
{
u32 flags = ULPI_OTG_DRVVBUS;
u8 *reg = on ? &ulpi->otg_ctrl_set : &ulpi->otg_ctrl_clear;
if (ext_power)
flags |= ULPI_OTG_DRVVBUS_EXT;
- if (ext_ind)
- flags |= ULPI_OTG_EXTVBUSIND;
return ulpi_write(ulpi_vp, reg, flags);
}
+int ulpi_set_vbus_indicator(struct ulpi_viewport *ulpi_vp, int external,
+ int passthu, int complement)
+{
+ u32 flags, val;
+ u8 *reg;
+
+ reg = external ? &ulpi->otg_ctrl_set : &ulpi->otg_ctrl_clear;
+ val = ulpi_write(ulpi_vp, reg, ULPI_OTG_EXTVBUSIND);
+ if (val)
+ return val;
+
+ flags = passthu ? ULPI_IFACE_PASSTHRU : 0;
+ flags |= complement ? ULPI_IFACE_EXTVBUS_COMPLEMENT : 0;
+
+ val = ulpi_read(ulpi_vp, &ulpi->iface_ctrl);
+ if (val == ULPI_ERROR)
+ return val;
+
+ val = val & ~(ULPI_IFACE_PASSTHRU & ULPI_IFACE_EXTVBUS_COMPLEMENT);
+ val |= flags;
+ val = ulpi_write(ulpi_vp, &ulpi->iface_ctrl, val);
+ if (val)
+ return val;
+
+ return 0;
+}
+
int ulpi_set_pd(struct ulpi_viewport *ulpi_vp, int enable)
{
u32 val = ULPI_OTG_DP_PULLDOWN | ULPI_OTG_DM_PULLDOWN;
* CONFIG_CONSOLE_TIME - display time/date in upper right
* corner, needs CONFIG_CMD_DATE and
* CONFIG_CONSOLE_CURSOR
- * CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner
+ * CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner.
+ * Use CONFIG_SPLASH_SCREEN_ALIGN with
+ * environment variable "splashpos" to place
+ * the logo on other position. In this case
+ * no CONSOLE_EXTRA_INFO is possible.
* CONFIG_VIDEO_BMP_LOGO - use bmp_logo instead of linux_logo
* CONFIG_CONSOLE_EXTRA_INFO - display additional board information
* strings that normaly goes to serial
#ifdef CONFIG_VIDEO_LOGO
-void logo_plot(void *screen, int width, int x, int y)
+static int video_logo_xpos;
+static int video_logo_ypos;
+
+static void plot_logo_or_black(void *screen, int width, int x, int y, \
+ int black);
+
+static void logo_plot(void *screen, int width, int x, int y)
+{
+ plot_logo_or_black(screen, width, x, y, 0);
+}
+
+static void logo_black(void)
+{
+ plot_logo_or_black(video_fb_address, \
+ VIDEO_COLS, \
+ video_logo_xpos, \
+ video_logo_ypos, \
+ 1);
+}
+
+static int do_clrlogo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc != 1)
+ return cmd_usage(cmdtp);
+
+ logo_black();
+ return 0;
+}
+
+U_BOOT_CMD(
+ clrlogo, 1, 0, do_clrlogo,
+ "fill the boot logo area with black",
+ " "
+ );
+
+static void plot_logo_or_black(void *screen, int width, int x, int y, int black)
{
int xcount, i;
int ycount = video_logo_height;
unsigned char r, g, b, *logo_red, *logo_blue, *logo_green;
unsigned char *source;
- unsigned char *dest = (unsigned char *) screen +
- ((y * width * VIDEO_PIXEL_SIZE) + x * VIDEO_PIXEL_SIZE);
+ unsigned char *dest;
+
+#ifdef CONFIG_SPLASH_SCREEN_ALIGN
+ if (x == BMP_ALIGN_CENTER)
+ x = max(0, (VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH) / 2);
+ else if (x < 0)
+ x = max(0, VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH + x + 1);
+
+ if (y == BMP_ALIGN_CENTER)
+ y = max(0, (VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT) / 2);
+ else if (y < 0)
+ y = max(0, VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT + y + 1);
+#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
+
+ dest = (unsigned char *)screen + (y * width + x) * VIDEO_PIXEL_SIZE;
#ifdef CONFIG_VIDEO_BMP_LOGO
source = bmp_logo_bitmap;
#endif
xcount = VIDEO_LOGO_WIDTH;
while (xcount--) {
- r = logo_red[*source - VIDEO_LOGO_LUT_OFFSET];
- g = logo_green[*source - VIDEO_LOGO_LUT_OFFSET];
- b = logo_blue[*source - VIDEO_LOGO_LUT_OFFSET];
+ if (black) {
+ r = 0x00;
+ g = 0x00;
+ b = 0x00;
+ } else {
+ r = logo_red[*source - VIDEO_LOGO_LUT_OFFSET];
+ g = logo_green[*source - VIDEO_LOGO_LUT_OFFSET];
+ b = logo_blue[*source - VIDEO_LOGO_LUT_OFFSET];
+ }
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_INDEX:
char info[128];
int space, len;
__maybe_unused int y_off = 0;
+ __maybe_unused ulong addr;
+ __maybe_unused char *s;
-#ifdef CONFIG_SPLASH_SCREEN
- char *s;
- ulong addr;
-
- s = getenv("splashimage");
+#ifdef CONFIG_SPLASH_SCREEN_ALIGN
+ s = getenv("splashpos");
if (s != NULL) {
- int x = 0, y = 0;
+ if (s[0] == 'm')
+ video_logo_xpos = BMP_ALIGN_CENTER;
+ else
+ video_logo_xpos = simple_strtol(s, NULL, 0);
- addr = simple_strtoul(s, NULL, 16);
-#ifdef CONFIG_SPLASH_SCREEN_ALIGN
- s = getenv("splashpos");
+ s = strchr(s + 1, ',');
if (s != NULL) {
- if (s[0] == 'm')
- x = BMP_ALIGN_CENTER;
+ if (s[1] == 'm')
+ video_logo_ypos = BMP_ALIGN_CENTER;
else
- x = simple_strtol(s, NULL, 0);
-
- s = strchr(s + 1, ',');
- if (s != NULL) {
- if (s[1] == 'm')
- y = BMP_ALIGN_CENTER;
- else
- y = simple_strtol(s + 1, NULL, 0);
- }
+ video_logo_ypos = simple_strtol(s + 1, NULL, 0);
}
+ }
#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
- if (video_display_bitmap(addr, x, y) == 0) {
+#ifdef CONFIG_SPLASH_SCREEN
+ s = getenv("splashimage");
+ if (s != NULL) {
+
+ addr = simple_strtoul(s, NULL, 16);
+
+
+ if (video_display_bitmap(addr,
+ video_logo_xpos,
+ video_logo_ypos) == 0) {
video_logo_height = 0;
return ((void *) (video_fb_address));
}
}
#endif /* CONFIG_SPLASH_SCREEN */
- logo_plot(video_fb_address, VIDEO_COLS, 0, 0);
+ logo_plot(video_fb_address, VIDEO_COLS,
+ video_logo_xpos, video_logo_ypos);
+
+#ifdef CONFIG_SPLASH_SCREEN_ALIGN
+ /*
+ * when using splashpos for video_logo, skip any info
+ * output on video console if the logo is not at 0,0
+ */
+ if (video_logo_xpos || video_logo_ypos) {
+ /*
+ * video_logo_height is used in text and cursor offset
+ * calculations. Since the console is below the logo,
+ * we need to adjust the logo height
+ */
+ if (video_logo_ypos == BMP_ALIGN_CENTER)
+ video_logo_height += max(0, (VIDEO_VISIBLE_ROWS - \
+ VIDEO_LOGO_HEIGHT) / 2);
+ else if (video_logo_ypos > 0)
+ video_logo_height += video_logo_ypos;
+
+ return video_fb_address + video_logo_height * VIDEO_LINE_LEN;
+ }
+#endif
sprintf(info, " %s", version_string);
static int clk_ipu_enable(struct clk *clk)
{
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
u32 reg;
reg = __raw_readl(clk->enable_reg);
reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift;
__raw_writel(reg, clk->enable_reg);
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
/* Handshake with IPU when certain clock rates are changed. */
reg = __raw_readl(&mxc_ccm->ccdr);
reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
static void clk_ipu_disable(struct clk *clk)
{
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
u32 reg;
reg = __raw_readl(clk->enable_reg);
reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift);
__raw_writel(reg, clk->enable_reg);
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
/*
* No handshake with IPU whe dividers are changed
* as its not enabled.
static struct clk ipu_clk = {
.name = "ipu_clk",
.rate = CONFIG_IPUV3_CLK,
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
.enable_reg = (u32 *)(CCM_BASE_ADDR +
offsetof(struct mxc_ccm_reg, CCGR5)),
- .enable_shift = MXC_CCM_CCGR5_CG5_OFFSET,
+ .enable_shift = MXC_CCM_CCGR5_IPU_OFFSET,
+#else
+ .enable_reg = (u32 *)(CCM_BASE_ADDR +
+ offsetof(struct mxc_ccm_reg, CCGR3)),
+ .enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET,
+#endif
.enable = clk_ipu_enable,
.disable = clk_ipu_disable,
.usecount = 0,
#include "videomodes.h"
#include "ipu.h"
#include "mxcfb.h"
+#include "ipu_regs.h"
static int mxcfb_map_video_memory(struct fb_info *fbi);
static int mxcfb_unmap_video_memory(struct fb_info *fbi);
return ret;
}
+void ipuv3_fb_shutdown(void)
+{
+ int i;
+ struct ipu_stat *stat = (struct ipu_stat *)IPU_STAT;
+
+ for (i = 0; i < ARRAY_SIZE(mxcfb_info); i++) {
+ struct fb_info *fbi = mxcfb_info[i];
+ if (fbi) {
+ struct mxcfb_info *mxc_fbi = fbi->par;
+ ipu_disable_channel(mxc_fbi->ipu_ch);
+ ipu_uninit_channel(mxc_fbi->ipu_ch);
+ }
+ }
+ for (i = 0; i < ARRAY_SIZE(stat->int_stat); i++) {
+ __raw_writel(__raw_readl(&stat->int_stat[i]),
+ &stat->int_stat[i]);
+ }
+}
+
void *video_hw_init(void)
{
int ret;
struct ext_filesystem *fs = get_fs();
__u16 crc = 0;
- desc = (struct ext2_block_group *)&fs->gd[i];
+ desc = (struct ext2_block_group *)&fs->bgd[i];
if (fs->sb->feature_ro_compat & EXT4_FEATURE_RO_COMPAT_GDT_CSUM) {
int offset = offsetof(struct ext2_block_group, bg_checksum);
char *zero_buffer = zalloc(fs->blksz);
if (!journal_buffer || !zero_buffer)
goto fail;
- struct ext2_block_group *gd = (struct ext2_block_group *)fs->gdtable;
+ struct ext2_block_group *bgd = (struct ext2_block_group *)fs->gdtable;
if (fs->first_pass_bbmap == 0) {
for (i = 0; i < fs->no_blkgrp; i++) {
- if (gd[i].free_blocks) {
- if (gd[i].bg_flags & EXT4_BG_BLOCK_UNINIT) {
- put_ext4(((uint64_t) (gd[i].block_id *
+ if (bgd[i].free_blocks) {
+ if (bgd[i].bg_flags & EXT4_BG_BLOCK_UNINIT) {
+ put_ext4(((uint64_t) (bgd[i].block_id *
fs->blksz)),
zero_buffer, fs->blksz);
- gd[i].bg_flags =
- gd[i].
+ bgd[i].bg_flags =
+ bgd[i].
bg_flags & ~EXT4_BG_BLOCK_UNINIT;
memcpy(fs->blk_bmaps[i], zero_buffer,
fs->blksz);
fs->curr_blkno = fs->curr_blkno +
(i * fs->blksz * 8);
fs->first_pass_bbmap++;
- gd[i].free_blocks--;
+ bgd[i].free_blocks--;
fs->sb->free_blocks--;
- status = ext4fs_devread(gd[i].block_id *
+ status = ext4fs_devread(bgd[i].block_id *
fs->sect_perblk, 0,
fs->blksz,
journal_buffer);
if (status == 0)
goto fail;
if (ext4fs_log_journal(journal_buffer,
- gd[i].block_id))
+ bgd[i].block_id))
goto fail;
goto success;
} else {
if (bg_idx >= fs->no_blkgrp)
goto fail;
- if (gd[bg_idx].free_blocks == 0) {
+ if (bgd[bg_idx].free_blocks == 0) {
debug("block group %u is full. Skipping\n", bg_idx);
fs->curr_blkno = fs->curr_blkno + blk_per_grp;
fs->curr_blkno--;
goto restart;
}
- if (gd[bg_idx].bg_flags & EXT4_BG_BLOCK_UNINIT) {
+ if (bgd[bg_idx].bg_flags & EXT4_BG_BLOCK_UNINIT) {
memset(zero_buffer, '\0', fs->blksz);
- put_ext4(((uint64_t) (gd[bg_idx].block_id * fs->blksz)),
- zero_buffer, fs->blksz);
+ put_ext4(((uint64_t) (bgd[bg_idx].block_id *
+ fs->blksz)), zero_buffer, fs->blksz);
memcpy(fs->blk_bmaps[bg_idx], zero_buffer, fs->blksz);
- gd[bg_idx].bg_flags = gd[bg_idx].bg_flags &
+ bgd[bg_idx].bg_flags = bgd[bg_idx].bg_flags &
~EXT4_BG_BLOCK_UNINIT;
}
/* journal backup */
if (prev_bg_bitmap_index != bg_idx) {
memset(journal_buffer, '\0', fs->blksz);
- status = ext4fs_devread(gd[bg_idx].block_id
+ status = ext4fs_devread(bgd[bg_idx].block_id
* fs->sect_perblk,
0, fs->blksz, journal_buffer);
if (status == 0)
goto fail;
if (ext4fs_log_journal(journal_buffer,
- gd[bg_idx].block_id))
+ bgd[bg_idx].block_id))
goto fail;
prev_bg_bitmap_index = bg_idx;
}
- gd[bg_idx].free_blocks--;
+ bgd[bg_idx].free_blocks--;
fs->sb->free_blocks--;
goto success;
}
char *zero_buffer = zalloc(fs->blksz);
if (!journal_buffer || !zero_buffer)
goto fail;
- struct ext2_block_group *gd = (struct ext2_block_group *)fs->gdtable;
+ struct ext2_block_group *bgd = (struct ext2_block_group *)fs->gdtable;
if (fs->first_pass_ibmap == 0) {
for (i = 0; i < fs->no_blkgrp; i++) {
- if (gd[i].free_inodes) {
- if (gd[i].bg_itable_unused != gd[i].free_inodes)
- gd[i].bg_itable_unused =
- gd[i].free_inodes;
- if (gd[i].bg_flags & EXT4_BG_INODE_UNINIT) {
+ if (bgd[i].free_inodes) {
+ if (bgd[i].bg_itable_unused !=
+ bgd[i].free_inodes)
+ bgd[i].bg_itable_unused =
+ bgd[i].free_inodes;
+ if (bgd[i].bg_flags & EXT4_BG_INODE_UNINIT) {
put_ext4(((uint64_t)
- (gd[i].inode_id * fs->blksz)),
+ (bgd[i].inode_id *
+ fs->blksz)),
zero_buffer, fs->blksz);
- gd[i].bg_flags = gd[i].bg_flags &
+ bgd[i].bg_flags = bgd[i].bg_flags &
~EXT4_BG_INODE_UNINIT;
memcpy(fs->inode_bmaps[i],
zero_buffer, fs->blksz);
fs->curr_inode_no = fs->curr_inode_no +
(i * inodes_per_grp);
fs->first_pass_ibmap++;
- gd[i].free_inodes--;
- gd[i].bg_itable_unused--;
+ bgd[i].free_inodes--;
+ bgd[i].bg_itable_unused--;
fs->sb->free_inodes--;
- status = ext4fs_devread(gd[i].inode_id *
+ status = ext4fs_devread(bgd[i].inode_id *
fs->sect_perblk, 0,
fs->blksz,
journal_buffer);
if (status == 0)
goto fail;
if (ext4fs_log_journal(journal_buffer,
- gd[i].inode_id))
+ bgd[i].inode_id))
goto fail;
goto success;
} else
fs->curr_inode_no++;
/* get the blockbitmap index respective to blockno */
ibmap_idx = fs->curr_inode_no / inodes_per_grp;
- if (gd[ibmap_idx].bg_flags & EXT4_BG_INODE_UNINIT) {
+ if (bgd[ibmap_idx].bg_flags & EXT4_BG_INODE_UNINIT) {
memset(zero_buffer, '\0', fs->blksz);
- put_ext4(((uint64_t) (gd[ibmap_idx].inode_id *
+ put_ext4(((uint64_t) (bgd[ibmap_idx].inode_id *
fs->blksz)), zero_buffer,
fs->blksz);
- gd[ibmap_idx].bg_flags =
- gd[ibmap_idx].bg_flags & ~EXT4_BG_INODE_UNINIT;
+ bgd[ibmap_idx].bg_flags =
+ bgd[ibmap_idx].bg_flags & ~EXT4_BG_INODE_UNINIT;
memcpy(fs->inode_bmaps[ibmap_idx], zero_buffer,
fs->blksz);
}
/* journal backup */
if (prev_inode_bitmap_index != ibmap_idx) {
memset(journal_buffer, '\0', fs->blksz);
- status = ext4fs_devread(gd[ibmap_idx].inode_id
+ status = ext4fs_devread(bgd[ibmap_idx].inode_id
* fs->sect_perblk,
0, fs->blksz, journal_buffer);
if (status == 0)
goto fail;
if (ext4fs_log_journal(journal_buffer,
- gd[ibmap_idx].inode_id))
+ bgd[ibmap_idx].inode_id))
goto fail;
prev_inode_bitmap_index = ibmap_idx;
}
- if (gd[ibmap_idx].bg_itable_unused != gd[ibmap_idx].free_inodes)
- gd[ibmap_idx].bg_itable_unused =
- gd[ibmap_idx].free_inodes;
- gd[ibmap_idx].free_inodes--;
- gd[ibmap_idx].bg_itable_unused--;
+ if (bgd[ibmap_idx].bg_itable_unused !=
+ bgd[ibmap_idx].free_inodes)
+ bgd[ibmap_idx].bg_itable_unused =
+ bgd[ibmap_idx].free_inodes;
+ bgd[ibmap_idx].free_inodes--;
+ bgd[ibmap_idx].bg_itable_unused--;
fs->sb->free_inodes--;
goto success;
}
/* update block groups */
for (i = 0; i < fs->no_blkgrp; i++) {
- fs->gd[i].bg_checksum = ext4fs_checksum_update(i);
- put_ext4((uint64_t)(fs->gd[i].block_id * fs->blksz),
+ fs->bgd[i].bg_checksum = ext4fs_checksum_update(i);
+ put_ext4((uint64_t)(fs->bgd[i].block_id * fs->blksz),
fs->blk_bmaps[i], fs->blksz);
}
/* update inode table groups */
for (i = 0; i < fs->no_blkgrp; i++) {
- put_ext4((uint64_t) (fs->gd[i].inode_id * fs->blksz),
+ put_ext4((uint64_t) (fs->bgd[i].inode_id * fs->blksz),
fs->inode_bmaps[i], fs->blksz);
}
static void delete_single_indirect_block(struct ext2_inode *inode)
{
- struct ext2_block_group *gd = NULL;
+ struct ext2_block_group *bgd = NULL;
static int prev_bg_bmap_idx = -1;
long int blknr;
int remainder;
return;
}
/* get block group descriptor table */
- gd = (struct ext2_block_group *)fs->gdtable;
+ bgd = (struct ext2_block_group *)fs->gdtable;
/* deleting the single indirect block associated with inode */
if (inode->b.blocks.indir_block != 0) {
bg_idx--;
}
ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
- gd[bg_idx].free_blocks++;
+ bgd[bg_idx].free_blocks++;
fs->sb->free_blocks++;
/* journal backup */
if (prev_bg_bmap_idx != bg_idx) {
status =
- ext4fs_devread(gd[bg_idx].block_id *
+ ext4fs_devread(bgd[bg_idx].block_id *
fs->sect_perblk, 0, fs->blksz,
journal_buffer);
if (status == 0)
goto fail;
if (ext4fs_log_journal
- (journal_buffer, gd[bg_idx].block_id))
+ (journal_buffer, bgd[bg_idx].block_id))
goto fail;
prev_bg_bmap_idx = bg_idx;
}
unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
unsigned int *di_buffer = NULL;
unsigned int *DIB_start_addr = NULL;
- struct ext2_block_group *gd = NULL;
+ struct ext2_block_group *bgd = NULL;
struct ext_filesystem *fs = get_fs();
char *journal_buffer = zalloc(fs->blksz);
if (!journal_buffer) {
return;
}
/* get the block group descriptor table */
- gd = (struct ext2_block_group *)fs->gdtable;
+ bgd = (struct ext2_block_group *)fs->gdtable;
if (inode->b.blocks.double_indir_block != 0) {
di_buffer = zalloc(fs->blksz);
ext4fs_reset_block_bmap(*di_buffer,
fs->blk_bmaps[bg_idx], bg_idx);
di_buffer++;
- gd[bg_idx].free_blocks++;
+ bgd[bg_idx].free_blocks++;
fs->sb->free_blocks++;
/* journal backup */
if (prev_bg_bmap_idx != bg_idx) {
- status = ext4fs_devread(gd[bg_idx].block_id
+ status = ext4fs_devread(bgd[bg_idx].block_id
* fs->sect_perblk, 0,
fs->blksz,
journal_buffer);
goto fail;
if (ext4fs_log_journal(journal_buffer,
- gd[bg_idx].block_id))
+ bgd[bg_idx].block_id))
goto fail;
prev_bg_bmap_idx = bg_idx;
}
bg_idx--;
}
ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
- gd[bg_idx].free_blocks++;
+ bgd[bg_idx].free_blocks++;
fs->sb->free_blocks++;
/* journal backup */
if (prev_bg_bmap_idx != bg_idx) {
memset(journal_buffer, '\0', fs->blksz);
- status = ext4fs_devread(gd[bg_idx].block_id *
+ status = ext4fs_devread(bgd[bg_idx].block_id *
fs->sect_perblk, 0, fs->blksz,
journal_buffer);
if (status == 0)
goto fail;
if (ext4fs_log_journal(journal_buffer,
- gd[bg_idx].block_id))
+ bgd[bg_idx].block_id))
goto fail;
prev_bg_bmap_idx = bg_idx;
}
unsigned int *tib_start_addr = NULL;
unsigned int *tip_buffer = NULL;
unsigned int *tipb_start_addr = NULL;
- struct ext2_block_group *gd = NULL;
+ struct ext2_block_group *bgd = NULL;
struct ext_filesystem *fs = get_fs();
char *journal_buffer = zalloc(fs->blksz);
if (!journal_buffer) {
return;
}
/* get block group descriptor table */
- gd = (struct ext2_block_group *)fs->gdtable;
+ bgd = (struct ext2_block_group *)fs->gdtable;
if (inode->b.blocks.triple_indir_block != 0) {
tigp_buffer = zalloc(fs->blksz);
bg_idx);
tip_buffer++;
- gd[bg_idx].free_blocks++;
+ bgd[bg_idx].free_blocks++;
fs->sb->free_blocks++;
/* journal backup */
if (prev_bg_bmap_idx != bg_idx) {
status =
- ext4fs_devread(gd[bg_idx].block_id *
- fs->sect_perblk, 0,
- fs->blksz,
- journal_buffer);
+ ext4fs_devread(
+ bgd[bg_idx].block_id *
+ fs->sect_perblk, 0,
+ fs->blksz,
+ journal_buffer);
if (status == 0)
goto fail;
if (ext4fs_log_journal(journal_buffer,
- gd[bg_idx].
+ bgd[bg_idx].
block_id))
goto fail;
prev_bg_bmap_idx = bg_idx;
fs->blk_bmaps[bg_idx], bg_idx);
tigp_buffer++;
- gd[bg_idx].free_blocks++;
+ bgd[bg_idx].free_blocks++;
fs->sb->free_blocks++;
/* journal backup */
if (prev_bg_bmap_idx != bg_idx) {
memset(journal_buffer, '\0', fs->blksz);
status =
- ext4fs_devread(gd[bg_idx].block_id *
+ ext4fs_devread(bgd[bg_idx].block_id *
fs->sect_perblk, 0,
fs->blksz, journal_buffer);
if (status == 0)
goto fail;
if (ext4fs_log_journal(journal_buffer,
- gd[bg_idx].block_id))
+ bgd[bg_idx].block_id))
goto fail;
prev_bg_bmap_idx = bg_idx;
}
bg_idx--;
}
ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
- gd[bg_idx].free_blocks++;
+ bgd[bg_idx].free_blocks++;
fs->sb->free_blocks++;
/* journal backup */
if (prev_bg_bmap_idx != bg_idx) {
memset(journal_buffer, '\0', fs->blksz);
- status = ext4fs_devread(gd[bg_idx].block_id *
+ status = ext4fs_devread(bgd[bg_idx].block_id *
fs->sect_perblk, 0, fs->blksz,
journal_buffer);
if (status == 0)
goto fail;
if (ext4fs_log_journal(journal_buffer,
- gd[bg_idx].block_id))
+ bgd[bg_idx].block_id))
goto fail;
prev_bg_bmap_idx = bg_idx;
}
unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
unsigned int inode_per_grp = ext4fs_root->sblock.inodes_per_group;
struct ext2_inode *inode_buffer = NULL;
- struct ext2_block_group *gd = NULL;
+ struct ext2_block_group *bgd = NULL;
struct ext_filesystem *fs = get_fs();
char *journal_buffer = zalloc(fs->blksz);
if (!journal_buffer)
return -ENOMEM;
/* get the block group descriptor table */
- gd = (struct ext2_block_group *)fs->gdtable;
+ bgd = (struct ext2_block_group *)fs->gdtable;
status = ext4fs_read_inode(ext4fs_root, inodeno, &inode);
if (status == 0)
goto fail;
debug("EXT4_EXTENTS Block releasing %ld: %d\n",
blknr, bg_idx);
- gd[bg_idx].free_blocks++;
+ bgd[bg_idx].free_blocks++;
fs->sb->free_blocks++;
/* journal backup */
if (prev_bg_bmap_idx != bg_idx) {
status =
- ext4fs_devread(gd[bg_idx].block_id *
+ ext4fs_devread(bgd[bg_idx].block_id *
fs->sect_perblk, 0,
fs->blksz, journal_buffer);
if (status == 0)
goto fail;
if (ext4fs_log_journal(journal_buffer,
- gd[bg_idx].block_id))
+ bgd[bg_idx].block_id))
goto fail;
prev_bg_bmap_idx = bg_idx;
}
bg_idx);
debug("ActualB releasing %ld: %d\n", blknr, bg_idx);
- gd[bg_idx].free_blocks++;
+ bgd[bg_idx].free_blocks++;
fs->sb->free_blocks++;
/* journal backup */
if (prev_bg_bmap_idx != bg_idx) {
memset(journal_buffer, '\0', fs->blksz);
- status = ext4fs_devread(gd[bg_idx].block_id
+ status = ext4fs_devread(bgd[bg_idx].block_id
* fs->sect_perblk,
0, fs->blksz,
journal_buffer);
if (status == 0)
goto fail;
if (ext4fs_log_journal(journal_buffer,
- gd[bg_idx].block_id))
+ bgd[bg_idx].block_id))
goto fail;
prev_bg_bmap_idx = bg_idx;
}
/* get the block no */
inodeno--;
- blkno = __le32_to_cpu(gd[ibmap_idx].inode_table_id) +
+ blkno = __le32_to_cpu(bgd[ibmap_idx].inode_table_id) +
(inodeno % __le32_to_cpu(inode_per_grp)) / inodes_per_block;
/* get the offset of the inode */
/* update the respective inode bitmaps */
inodeno++;
ext4fs_reset_inode_bmap(inodeno, fs->inode_bmaps[ibmap_idx], ibmap_idx);
- gd[ibmap_idx].free_inodes++;
+ bgd[ibmap_idx].free_inodes++;
fs->sb->free_inodes++;
/* journal backup */
memset(journal_buffer, '\0', fs->blksz);
- status = ext4fs_devread(gd[ibmap_idx].inode_id *
+ status = ext4fs_devread(bgd[ibmap_idx].inode_id *
fs->sect_perblk, 0, fs->blksz, journal_buffer);
if (status == 0)
goto fail;
- if (ext4fs_log_journal(journal_buffer, gd[ibmap_idx].inode_id))
+ if (ext4fs_log_journal(journal_buffer, bgd[ibmap_idx].inode_id))
goto fail;
ext4fs_update();
printf("Error in getting the block group descriptor table\n");
goto fail;
}
- fs->gd = (struct ext2_block_group *)fs->gdtable;
+ fs->bgd = (struct ext2_block_group *)fs->gdtable;
/* load all the available bitmap block of the partition */
fs->blk_bmaps = zalloc(fs->no_blkgrp * sizeof(char *));
for (i = 0; i < fs->no_blkgrp; i++) {
status =
- ext4fs_devread(fs->gd[i].block_id * fs->sect_perblk, 0,
+ ext4fs_devread(fs->bgd[i].block_id * fs->sect_perblk, 0,
fs->blksz, (char *)fs->blk_bmaps[i]);
if (status == 0)
goto fail;
}
for (i = 0; i < fs->no_blkgrp; i++) {
- status = ext4fs_devread(fs->gd[i].inode_id * fs->sect_perblk,
+ status = ext4fs_devread(fs->bgd[i].inode_id * fs->sect_perblk,
0, fs->blksz,
(char *)fs->inode_bmaps[i]);
if (status == 0)
* reboot of a linux kernel
*/
for (i = 0; i < fs->no_blkgrp; i++)
- real_free_blocks = real_free_blocks + fs->gd[i].free_blocks;
+ real_free_blocks = real_free_blocks + fs->bgd[i].free_blocks;
if (real_free_blocks != fs->sb->free_blocks)
fs->sb->free_blocks = real_free_blocks;
free(fs->gdtable);
fs->gdtable = NULL;
- fs->gd = NULL;
+ fs->bgd = NULL;
/*
* reinitiliazed the global inode and
* block bitmap first execution check variables
goto fail;
ibmap_idx = inodeno / ext4fs_root->sblock.inodes_per_group;
inodeno--;
- itable_blkno = __le32_to_cpu(fs->gd[ibmap_idx].inode_table_id) +
+ itable_blkno = __le32_to_cpu(fs->bgd[ibmap_idx].inode_table_id) +
(inodeno % __le32_to_cpu(sblock->inodes_per_group)) /
inodes_per_block;
blkoff = (inodeno % inodes_per_block) * fs->inodesz;
}
ibmap_idx = parent_inodeno / ext4fs_root->sblock.inodes_per_group;
parent_inodeno--;
- parent_itable_blkno = __le32_to_cpu(fs->gd[ibmap_idx].inode_table_id) +
+ parent_itable_blkno = __le32_to_cpu(fs->bgd[ibmap_idx].inode_table_id) +
(parent_inodeno %
__le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block;
blkoff = (parent_inodeno % inodes_per_block) * fs->inodesz;
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+# SEE README.arm-unaligned-accesses
+$(obj)file.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
#########################################################################
/* Otherwise it might be a superfloppy (whole-disk FAT filesystem) */
if (!cur_dev) {
- if (part_no != 1) {
+ if (part_no != 0) {
printf("** Partition %d not valid on device %d **\n",
part_no, dev_desc->dev);
return -1;
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+# SEE README.arm-unaligned-accesses
+$(obj)super.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
+
#########################################################################
# defines $(obj).depend target
int retval = YAFFS_OK;
u8 *data = yaffs_get_temp_buffer(dev);
struct yaffs_ext_tags tags;
- int result;
- result = yaffs_rd_chunk_tags_nand(dev, nand_chunk, data, &tags);
+ yaffs_rd_chunk_tags_nand(dev, nand_chunk, data, &tags);
if (tags.ecc_result > YAFFS_ECC_RESULT_NO_ERROR)
retval = YAFFS_FAIL;
int retval = YAFFS_OK;
struct yaffs_ext_tags temp_tags;
u8 *buffer = yaffs_get_temp_buffer(dev);
- int result;
- result = yaffs_rd_chunk_tags_nand(dev, nand_chunk, buffer, &temp_tags);
+ yaffs_rd_chunk_tags_nand(dev, nand_chunk, buffer, &temp_tags);
if (memcmp(buffer, data, dev->data_bytes_per_chunk) ||
temp_tags.obj_id != tags->obj_id ||
temp_tags.chunk_id != tags->chunk_id ||
struct yaffs_obj *the_obj;
int usage;
int i;
- int pushout;
if (dev->param.n_caches < 1)
return NULL;
the_obj = dev->cache[0].object;
usage = -1;
cache = NULL;
- pushout = -1;
for (i = 0; i < dev->param.n_caches; i++) {
if (dev->cache[i].object &&
usage = dev->cache[i].last_use;
the_obj = dev->cache[i].object;
cache = &dev->cache[i];
- pushout = i;
}
}
struct yaffs_obj_hdr *oh;
struct yaffs_dev *dev;
struct yaffs_ext_tags tags;
- int result;
- int alloc_failed = 0;
if (!in || !in->lazy_loaded || in->hdr_chunk < 1)
return;
in->lazy_loaded = 0;
buf = yaffs_get_temp_buffer(dev);
- result = yaffs_rd_chunk_tags_nand(dev, in->hdr_chunk, buf, &tags);
+ yaffs_rd_chunk_tags_nand(dev, in->hdr_chunk, buf, &tags);
oh = (struct yaffs_obj_hdr *)buf;
in->yst_mode = oh->yst_mode;
if (in->variant_type == YAFFS_OBJECT_TYPE_SYMLINK) {
in->variant.symlink_variant.alias =
yaffs_clone_str(oh->alias);
- if (!in->variant.symlink_variant.alias)
- alloc_failed = 1; /* Not returned */
}
yaffs_release_temp_buffer(dev, buf);
}
struct yaffs_dev *dev = in->my_dev;
int prev_chunk_id;
int ret_val = 0;
- int result = 0;
int new_chunk_id;
struct yaffs_ext_tags new_tags;
struct yaffs_ext_tags old_tags;
prev_chunk_id = in->hdr_chunk;
if (prev_chunk_id > 0) {
- result = yaffs_rd_chunk_tags_nand(dev, prev_chunk_id,
- buffer, &old_tags);
+ yaffs_rd_chunk_tags_nand(dev, prev_chunk_id,
+ buffer, &old_tags);
yaffs_verify_oh(in, oh, &old_tags, 0);
memcpy(old_name, oh->name, sizeof(oh->name));
} else if (obj->short_name[0]) {
yaffs_strcpy(name, obj->short_name);
} else if (obj->hdr_chunk > 0) {
- int result;
u8 *buffer = yaffs_get_temp_buffer(obj->my_dev);
struct yaffs_obj_hdr *oh = (struct yaffs_obj_hdr *)buffer;
memset(buffer, 0, obj->my_dev->data_bytes_per_chunk);
if (obj->hdr_chunk > 0) {
- result = yaffs_rd_chunk_tags_nand(obj->my_dev,
- obj->hdr_chunk,
- buffer, NULL);
+ yaffs_rd_chunk_tags_nand(obj->my_dev,
+ obj->hdr_chunk,
+ buffer, NULL);
}
yaffs_load_name_from_oh(obj->my_dev, name, oh->name,
buffer_size);
struct yaffs_summary_header hdr;
struct yaffs_block_info *bi = yaffs_get_block_info(dev, blk);
int sum_bytes_per_chunk = dev->data_bytes_per_chunk - sizeof(hdr);
- int sum_tags_bytes;
- sum_tags_bytes = sizeof(struct yaffs_summary_tags) *
- dev->chunks_per_summary;
buffer = yaffs_get_temp_buffer(dev);
n_bytes = sizeof(struct yaffs_summary_tags) * dev->chunks_per_summary;
chunk_in_block = dev->chunks_per_summary;
{
u32 x;
int required_depth;
- int actual_depth;
int last_chunk;
u32 offset_in_chunk;
u32 the_chunk;
required_depth++;
}
- actual_depth = obj->variant.file_variant.top_level;
-
/* Check that the chunks in the tnode tree are all correct.
* We do this by scanning through the tnode tree and
* checking the tags for every chunk match.
{
struct yaffs_ext_tags tags;
int blk;
- int result;
int chunk;
int c;
int deleted;
/* Read the tags and decide what to do */
chunk = blk * dev->param.chunks_per_block + c;
- result = yaffs_rd_chunk_tags_nand(dev, chunk, NULL,
- &tags);
+ yaffs_rd_chunk_tags_nand(dev, chunk, NULL, &tags);
/* Let's have a good look at this chunk... */
yaffs_set_chunk_bit(dev, blk, c);
bi->pages_in_use++;
- result = yaffs_rd_chunk_tags_nand(dev, chunk,
- chunk_data,
- NULL);
+ yaffs_rd_chunk_tags_nand(dev, chunk,
+ chunk_data, NULL);
oh = (struct yaffs_obj_hdr *)chunk_data;
int is_shrink;
int is_unlinked;
struct yaffs_ext_tags tags;
- int result;
int alloc_failed = 0;
int chunk = blk * dev->param.chunks_per_block + chunk_in_block;
struct yaffs_file_var *file_var;
struct yaffs_symlink_var *sl_var;
if (summary_available) {
- result = yaffs_summary_fetch(dev, &tags, chunk_in_block);
+ yaffs_summary_fetch(dev, &tags, chunk_in_block);
tags.seq_number = bi->seq_number;
}
if (!summary_available || tags.obj_id == 0) {
- result = yaffs_rd_chunk_tags_nand(dev, chunk, NULL, &tags);
+ yaffs_rd_chunk_tags_nand(dev, chunk, NULL, &tags);
dev->tags_used++;
} else {
dev->summary_used++;
* invalid data until needed.
*/
- result = yaffs_rd_chunk_tags_nand(dev,
- chunk,
- chunk_data,
- NULL);
+ yaffs_rd_chunk_tags_nand(dev, chunk, chunk_data, NULL);
oh = (struct yaffs_obj_hdr *)chunk_data;
int n_to_scan = 0;
enum yaffs_block_state state;
int c;
- int deleted;
LIST_HEAD(hard_list);
struct yaffs_block_info *bi;
u32 seq_number;
/* get the block to scan in the correct order */
blk = block_index[block_iter].block;
bi = yaffs_get_block_info(dev, blk);
- deleted = 0;
summary_available = yaffs_summary_read(dev, dev->sum_tags, blk);
*/
ulong timer_get_boot_us(void);
+#ifndef CONFIG_SPL_BUILD
/*
* Board code can implement show_boot_progress() if needed.
*
* has occurred.
*/
void show_boot_progress(int val);
+#else
+#define show_boot_progress(val) do {} while (0)
+#endif
-#ifdef CONFIG_BOOTSTAGE
+#if defined(CONFIG_BOOTSTAGE) && !defined(CONFIG_SPL_BUILD)
/* This is the full bootstage implementation */
/**
#include <linux/bitops.h>
#include <linux/types.h>
#include <linux/string.h>
+#include <linux/stringify.h>
#include <asm/ptrace.h>
#include <stdarg.h>
-#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
+#if defined(CONFIG_PCI) && defined(CONFIG_4xx)
#include <pci.h>
#endif
#if defined(CONFIG_8xx)
# endif
#endif
-#ifndef CONFIG_SERIAL_MULTI
-
-#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) \
- || defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \
- || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
-
-#define CONFIG_SERIAL_MULTI 1
-
-#endif
-
-#endif /* CONFIG_SERIAL_MULTI */
-
/*
* General Purpose Utilities
*/
void pci_init_board(void);
void pciinfo (int, int);
-#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
+#if defined(CONFIG_PCI) && defined(CONFIG_4xx)
int pci_pre_init (struct pci_controller *);
int is_pci_host (struct pci_controller *);
#endif
}
#endif
-#if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
+#if defined(CONFIG_4xx)
# if defined(CONFIG_440)
# if defined(CONFIG_440SPE)
unsigned long determine_sysper(void);
--- /dev/null
+/*
+ * (C) Copyright 2012
+ * Ilya Yanok, ilya.yanok@gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ *
+ * We don't use any commands in SPL, but generic networking code
+ * has some features enabled/disabled based on CONFIG_CMD_*
+ * options. As we want a minimal set of features included
+ * into network SPL image, we undefine some config options here.
+ */
+
+#ifndef __CONFIG_UNCMD_SPL_H__
+#define __CONFIG_UNCMD_SPL_H__
+
+#ifdef CONFIG_SPL_BUILD
+/* SPL needs only BOOTP + TFTP so undefine other stuff to save space */
+#undef CONFIG_CMD_CDP
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DNS
+#undef CONFIG_CMD_LINK_LOCAL
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_PING
+#undef CONFIG_CMD_RARP
+#undef CONFIG_CMD_SNTP
+#undef CONFIG_CMD_TFTPPUT
+#undef CONFIG_CMD_TFTPSRV
+#endif /* CONFIG_SPL_BUILD */
+#endif /* __CONFIG_UNCMD_SPL_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_IOP480 1 /* This is a IOP480 CPU */
-#define CONFIG_ADCIOP 1 /* ...on a ADCIOP board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_CPUCLOCK 66
-#define CONFIG_BUSCLOCK (CONFIG_CPUCLOCK)
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-
-#define CONFIG_IPADDR 10.0.18.222
-#define CONFIG_SERVERIP 10.0.18.190
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_ASKENV
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x0f00 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x0AA9 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x0556 /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0002 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0000 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0004 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#if 1 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0x10000000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
-#define CONFIG_ENV_SIZE 0x0400 /* Size of Environment vars */
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
-#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x7800) /* VxWorks eth-addr*/
-
-#else /* Use FLASH for environment variables */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-
-#define CONFIG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */
-
-#endif
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- */
-#define CONFIG_PCI /* include pci support */
-#undef CONFIG_PCI_PNP
-
-
-#define CONFIG_TULIP
-
-#define CONFIG_SYS_ETH_DEV_FN 0x0000
-#define CONFIG_SYS_ETH_IOBASE 0x0fff0000
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0xFFE00000 /* FLASH bank #1 */
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * AMIRIX.h: AMIRIX specific config options
- *
- * Author : Frank Smith (smith at amirix dot com)
- *
- * Derived from : other configuration header files in this tree
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL) version 2, incorporated herein by
- * reference. Drivers based on or derived from this code fall under the GPL
- * and must retain the authorship, copyright and this license notice. This
- * file is not a complete program and may only be used when the entire
- * program is licensed under the GPL.
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-
-#define CONFIG_AP1000 1 /* ...on an AP1000 board */
-
-/*
- * Start at bottom of RAM, but at an aliased address so that it looks
- * like it's not in RAM. This is a bit of voodoo to allow it to be
- * run from RAM instead of Flash.
- */
-#define CONFIG_SYS_TEXT_BASE 0x08000000
-#define CONFIG_SYS_LDSCRIPT "board/amirix/ap1000/u-boot.lds"
-
-#define CONFIG_PCI 1
-
-#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "0> "
-
-#define CONFIG_COMMAND_EDIT 1
-#define CONFIG_COMPLETE_ADDRESSES 1
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-#ifdef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#else
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NVRAM
-#endif
-#endif
-
-#define CONFIG_BAUDRATE 57600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#define CONFIG_BOOTCOMMAND "" /* autoboot command */
-
-#define CONFIG_BOOTARGS "console=ttyS0,57600"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MVENV
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SYS_CLK_FREQ 30000000
-
-#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
-
-/*
- * I2C
- */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_SPEED 400000
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-/* usually: (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+4+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_ALT_MEMTEST 1
-#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 4 ... 16 MB in DRAM */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-
-#define CONFIG_SYS_NS16550_CLK 40000000
-#define CONFIG_SYS_DUART_CHAN 0
-#define CONFIG_SYS_NS16550_COM1 (0x4C000000 + 0x1000)
-#define CONFIG_SYS_NS16550_COM2 (0x4C800000 + 0x1000)
-#define CONFIG_SYS_NS16550_REG_SIZE 4
-#define CONFIG_SYS_NS16550 1
-#define CONFIG_SYS_INIT_CHAN1 1
-#define CONFIG_SYS_INIT_CHAN2 0
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CONFIG_SYS_LOAD_ADDR 0x00200000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_SYS_PROGFLASH_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CONFFLASH_BASE 0x24000000
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
-
-/* BEG ENVIRONNEMENT FLASH */
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* see README - env sector total size */
-#endif
-/* END ENVIRONNEMENT FLASH */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */
-
-#ifdef CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR 0xF0000500
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x400000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS 0x50
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/* JFFS2 stuff */
-
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 1
-
-#define CONFIG_E1000
-
-#define CONFIG_SYS_ETH_DEV_FN 0x0800
-#define CONFIG_SYS_ETH_IOBASE 0x31000000
-#define CONFIG_SYS_ETH_MEMBASE 0x32000000
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_IOP480 1 /* This is a IOP480 CPU */
-#define CONFIG_DASA_SIM 1 /* ...on a DASA_SIM board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-#define CONFIG_SYS_LDSCRIPT "board/esd/dasa_sim/u-boot.lds"
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_CPUCLOCK 66
-#define CONFIG_BUSCLOCK (CONFIG_CPUCLOCK)
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND "bootm ffe00000" /* autoboot command */
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_IPADDR 10.0.18.222
-#define CONFIG_SERVERIP 10.0.18.190
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BSP
-
-
-#if 0 /* Does not appear to be used?! If it is used, needs to be fixed */
-#define CONFIG_SOFT_I2C /* Software I2C support enabled */
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x0f00 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x0AA9 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x0556 /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0002 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0000 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0004 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-
-#if 0
-#define CONFIG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */
-#else
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
-#endif
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- */
-#define CONFIG_PCI /* include pci support */
-#undef CONFIG_PCI_PNP
-
-
-#define CONFIG_TULIP
-
-#define CONFIG_SYS_ETH_DEV_FN 0x0000
-#define CONFIG_SYS_ETH_IOBASE 0x0fff0000
-#define CONFIG_SYS_PCI9054_DEV_FN 0x0800
-#define CONFIG_SYS_PCI9054_IOBASE 0x0eff0000
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_BAUDRATE 9600
#define CONFIG_SYS_BAUDRATE_TABLE \
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
+ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=0x40010000\0" \
"uboot=u-boot.bin\0" \
"load=loadb ${loadaddr} ${baudrate};" \
- "loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
+ "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
"upd=run load; run prog\0" \
"prog=sf probe 0:2 10000 1;" \
"sf erase 0 30000;" \
#endif
#ifdef CONFIG_SYS_SPANSION_BOOT
#define CONFIG_EXTRA_ENV_SETTINGS \
- "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
+ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=0x40010000\0" \
"uboot=u-boot.bin\0" \
"load=loadb ${loadaddr} ${baudrate}\0" \
"upd=run load; run prog\0" \
- "prog=prot off " MK_STR(CONFIG_SYS_FLASH_BASE) \
- " " MK_STR(CONFIG_SYS_UBOOT_END) ";" \
- "era " MK_STR(CONFIG_SYS_FLASH_BASE) " " \
- MK_STR(CONFIG_SYS_UBOOT_END) ";" \
- "cp.b ${loadaddr} " MK_STR(CONFIG_SYS_FLASH_BASE) \
+ "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
+ " " __stringify(CONFIG_SYS_UBOOT_END) ";" \
+ "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
+ __stringify(CONFIG_SYS_UBOOT_END) ";" \
+ "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
" ${filesize}; save\0" \
"updsbf=run loadsbf; run progsbf\0" \
"loadsbf=loadb ${loadaddr} ${baudrate};" \
- "loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
+ "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
"progsbf=sf probe 0:2 10000 1;" \
"sf erase 0 30000;" \
"sf write ${loadaddr} 0 30000;" \
# define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
+ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=10000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
#define CONFIG_HOSTNAME M5373EVB
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
#define CONFIG_SYS_LOAD_ADDR2 0x40010007
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
+ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=0x40010000\0" \
"sbfhdr=sbfhdr.bin\0" \
"uboot=u-boot.bin\0" \
"load=tftp ${loadaddr} ${sbfhdr};" \
- "tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
+ "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
"upd=run load; run prog\0" \
"prog=sf probe 0:1 1000000 3;" \
"sf erase 0 30000;" \
#define CONFIG_SYS_UBOOT_END 0x3FFFF
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
+ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=40010000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
- "prog=prot off 0 " MK_STR(CONFIG_SYS_UBOOT_END) \
- "; era 0 " MK_STR(CONFIG_SYS_UBOOT_END) " ;" \
+ "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \
+ "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \
""
#define CONFIG_SYS_LOAD_ADDR2 0x40010013
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
+ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=0x40010000\0" \
"sbfhdr=sbfhdr.bin\0" \
"uboot=u-boot.bin\0" \
"load=tftp ${loadaddr} ${sbfhdr};" \
- "tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
+ "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
"upd=run load; run prog\0" \
"prog=sf probe 0:1 1000000 3;" \
"sf erase 0 30000;" \
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
+ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=0x40010000\0" \
"uboot=u-boot.bin\0" \
"load=tftp ${loadaddr} ${uboot}\0" \
"upd=run load; run prog\0" \
- "prog=prot off " MK_STR(CONFIG_SYS_FLASH_BASE) \
- " " MK_STR(CONFIG_SYS_UBOOT_END) ";" \
- "era " MK_STR(CONFIG_SYS_FLASH_BASE) " " \
- MK_STR(CONFIG_SYS_UBOOT_END) ";" \
- "cp.b ${loadaddr} " MK_STR(CONFIG_SYS_FLASH_BASE) \
+ "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
+ " " __stringify(CONFIG_SYS_UBOOT_END) ";" \
+ "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
+ __stringify(CONFIG_SYS_UBOOT_END) ";" \
+ "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
" ${filesize}; save\0" \
""
#endif
"then; run fitboot;else;run ubiboot;fi;"
#define CONFIG_BOOTARGS "console=ttyS0,115200n8"
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"console_nr=0\0"\
"stdin=serial\0"\
"boot_sqfs=1\0"\
"usb_dr_mode=host\0"\
"bootfile=MergerBox.fit\0"\
- "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0"\
+ "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"\
"fpga=0\0"\
- "fpgadata=" MK_STR(MV_FPGA_DATA) "\0"\
- "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0"\
- "mv_kernel_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0"\
- "mv_initrd_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0"\
- "mv_dtb_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0"\
- "uboota=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0"\
- "fitaddr=" MK_STR(MV_FITADDR) "\0"\
+ "fpgadata=" __stringify(MV_FPGA_DATA) "\0"\
+ "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"\
+ "mv_kernel_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"\
+ "mv_initrd_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"\
+ "mv_dtb_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"\
+ "uboota=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"\
+ "fitaddr=" __stringify(MV_FITADDR) "\0"\
"mv_version=" U_BOOT_VERSION "\0"\
"mtdids=" MTDIDS_DEFAULT "\0"\
"mtdparts=" MTDPARTS_DEFAULT "\0"\
"i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\
"init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\
"i2c mw 21 2 ff;i2c mw 21 3 3c\0"\
- "splashimage=" MK_STR(MV_SPLAH_ADDR) "\0"\
+ "splashimage=" __stringify(MV_SPLAH_ADDR) "\0"\
""
-#undef MK_STR
-#undef XMK_STR
-
/*
* FPGA
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_BAUDRATE 9600
#define CONFIG_SYS_BAUDRATE_TABLE \
+++ /dev/null
-/*
- * ML2.h: ML2 specific config options
- *
- * Copyright 2002 Mind NV
- *
- * http://www.mind.be/
- *
- * Author : Peter De Schrijver (p2@mind.be)
- *
- * Derived from : other configuration header files in this tree
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL) version 2, incorporated herein by
- * reference. Drivers based on or derived from this code fall under the GPL
- * and must retain the authorship, copyright and this license notice. This
- * file is not a complete program and may only be used when the entire
- * program is licensed under the GPL.
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-#define CONFIG_ML2 1 /* ...on a ML2 board */
-
-#define CONFIG_SYS_TEXT_BASE 0x18000000
-#define CONFIG_SYS_LDSCRIPT "board/ml2/u-boot.lds"
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-
-#ifdef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#else
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NVRAM
-#endif
-#endif
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#if 1
-#define CONFIG_BOOTCOMMAND "bootm" /* autoboot command */
-#else
-#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
-#endif
-
-#define CONFIG_PREBOOT "fsload 0x00100000 /boot/image"
-
-#if 0
-#define CONFIG_BOOTARGS "root=/dev/nfs " \
- "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
- "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
-#else
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2 " \
- "console=ttyS0 console=tty"
-
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_KGDB
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_JFFS2
-
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_RTC
-#undef CONFIG_CMD_PCI
-#undef CONFIG_CMD_I2C
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SYS_CLK_FREQ 50000000
-
-#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
-
-/*
- * I2C
- */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_SPEED 400000
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-
-#define CONFIG_SYS_BASE_BAUD (3125000*16)
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_BASE_BAUD
-#define CONFIG_SYS_DUART_CHAN 0
-#define CONFIG_SYS_NS16550_COM1 0xa0001003
-#define CONFIG_SYS_NS16550_COM2 0xa0011003
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550 1
-#define CONFIG_SYS_INIT_CHAN1 1
-#define CONFIG_SYS_INIT_CHAN2 1
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x18000000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/* BEG ENVIRONNEMENT FLASH */
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
-#endif
-/* END ENVIRONNEMENT FLASH */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */
-
-#ifdef CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR 0xF0000500
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS 0x50
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00080000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=ml2-0"
-#define MTDPARTS_DEFAULT "mtdparts=ml2-0:-@512k(jffs2)"
-*/
-
-#endif /* __CONFIG_H */
#define CONFIG_NETDEV eth0
#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
+ "netdev=" __stringify(CONFIG_NETDEV) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
"fdtaddr=400000\0" \
"console=ttyCPM0\0" \
"setbootargs=setenv bootargs " \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#undef MK_STR
-#undef XMK_STR
-
#endif /* __CONFIG_H */
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
"bootcmd=run flash_self\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
- "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
- " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
" +${filesize};cp.b ${fileaddr} " \
- xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
+ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
#endif /* __CONFIG_H */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=" CONFIG_NETDEV "\0" \
"ethprime=TSEC1\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
"fdtaddr=780000\0" \
"fdtfile=" CONFIG_FDTFILE "\0" \
"console=ttyS0\0" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#undef MK_STR
-#undef XMK_STR
-
#endif /* __CONFIG_H */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=" CONFIG_NETDEV "\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftp $loadaddr $uboot;" \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
"fdtaddr=780000\0" \
"fdtfile=" CONFIG_FDTFILE "\0" \
"ramdiskaddr=1000000\0" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#undef MK_STR
-#undef XMK_STR
-
#endif /* __CONFIG_H */
#define CONFIG_BOOTDELAY 6
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_BOOTARGS \
"root=/dev/nfs rw" \
- " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \
- " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \
- MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
+ " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \
+ " ip=" __stringify(CONFIG_IPADDR) ":" \
+ __stringify(CONFIG_SERVERIP) ":" \
+ __stringify(CONFIG_GATEWAYIP) ":" \
+ __stringify(CONFIG_NETMASK) ":" \
CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \
- " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE)
+ " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE)
#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=" MK_STR(CONFIG_CONSOLE) "\0" \
+ "console=" __stringify(CONFIG_CONSOLE) "\0" \
"netdev=" CONFIG_NETDEV "\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
"fdtaddr=780000\0" \
"fdtfile=" CONFIG_FDTFILE "\0"
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#undef MK_STR
-#undef XMK_STR
-
#endif
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=" CONFIG_NETDEV "\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftp $loadaddr $uboot;" \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
"fdtaddr=780000\0" \
"fdtfile=" CONFIG_FDTFILE "\0" \
"ramdiskaddr=1000000\0" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#undef MK_STR
-#undef XMK_STR
-
#endif /* __CONFIG_H */
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=8536ds/ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=8536ds/mpc8536ds.dtb\0" \
- "bdev=sda3\0" \
- "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
+"netdev=eth0\0" \
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+"tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
+"consoledev=ttyS0\0" \
+"ramdiskaddr=2000000\0" \
+"ramdiskfile=8536ds/ramdisk.uboot\0" \
+"fdtaddr=c00000\0" \
+"fdtfile=8536ds/mpc8536ds.dtb\0" \
+"bdev=sda3\0" \
+"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=8544ds/ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=8544ds/mpc8544ds.dtb\0" \
- "bdev=sda3\0"
+"netdev=eth0\0" \
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+"tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
+"consoledev=ttyS0\0" \
+"ramdiskaddr=2000000\0" \
+"ramdiskfile=8544ds/ramdisk.uboot\0" \
+"fdtaddr=c00000\0" \
+"fdtfile=8544ds/mpc8544ds.dtb\0" \
+"bdev=sda3\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ecc=off\0" \
"netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
"consoledev=ttyS1\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=ramdisk.uboot\0" \
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ctlr_intlv=bank,ecc=off\0" \
- "netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=8572ds/ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=8572ds/mpc8572ds.dtb\0" \
- "bdev=sda3\0"
+"hwconfig=fsl_ddr:ctlr_intlv=bank,ecc=off\0" \
+"netdev=eth0\0" \
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+"tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
+"consoledev=ttyS0\0" \
+"ramdiskaddr=2000000\0" \
+"ramdiskfile=8572ds/ramdisk.uboot\0" \
+"fdtaddr=c00000\0" \
+"fdtfile=8572ds/mpc8572ds.dtb\0" \
+"bdev=sda3\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
#ifdef ENV_DEBUG
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
- "bdev=sda3\0" \
- "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
- "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
- "maxcpus=1" \
- "eoi=mw e00400b0 0\0" \
- "iack=md e00400a0 1\0" \
- "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
+"netdev=eth0\0" \
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+"tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
+"consoledev=ttyS0\0" \
+"ramdiskaddr=2000000\0" \
+"ramdiskfile=8610hpcd/ramdisk.uboot\0" \
+"fdtaddr=c00000\0" \
+"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
+"bdev=sda3\0" \
+"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
+"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+"maxcpus=1" \
+"eoi=mw e00400b0 0\0" \
+"iack=md e00400a0 1\0" \
+"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
"md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
"md ${a}f00 5\0" \
- "ddr1regs=setenv a e0002; run ddrreg\0" \
- "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
+"ddr1regs=setenv a e0002; run ddrreg\0" \
+"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
"md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
"md ${a}e60 1; md ${a}ef0 1d\0" \
- "guregs=setenv a e00e0; run gureg\0" \
- "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
- "mcmregs=setenv a e0001; run mcmreg\0" \
- "diuregs=md e002c000 1d\0" \
- "dium=mw e002c01c\0" \
- "diuerr=md e002c014 1\0" \
- "pmregs=md e00e1000 2b\0" \
- "lawregs=md e0000c08 4b\0" \
- "lbcregs=md e0005000 36\0" \
- "dma0regs=md e0021100 12\0" \
- "dma1regs=md e0021180 12\0" \
- "dma2regs=md e0021200 12\0" \
- "dma3regs=md e0021280 12\0" \
+"guregs=setenv a e00e0; run gureg\0" \
+"mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
+"mcmregs=setenv a e0001; run mcmreg\0" \
+"diuregs=md e002c000 1d\0" \
+"dium=mw e002c01c\0" \
+"diuerr=md e002c014 1\0" \
+"pmregs=md e00e1000 2b\0" \
+"lawregs=md e0000c08 4b\0" \
+"lbcregs=md e0005000 36\0" \
+"dma0regs=md e0021100 12\0" \
+"dma1regs=md e0021180 12\0" \
+"dma2regs=md e0021200 12\0" \
+"dma3regs=md e0021280 12\0" \
PCI_ENV \
PCIE_ENV \
DMA_ENV
#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
- "bdev=sda3\0"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
+ "bdev=sda3\0"
#endif
#define CONFIG_NFSBOOTCOMMAND \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=your.ramdisk.u-boot\0" \
#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
#define CONFIG_ENV_OVERWRITE
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"console_nr=0\0" \
"console=yes\0" \
"stdout=serial\0" \
"stderr=serial\0" \
"fpga=0\0" \
- "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
- "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
- "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
- "script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \
- "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
- "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
- "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
- "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
- "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
- "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
- "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
- "dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
- "mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0" \
- "mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0" \
+ "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
+ "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
+ "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
+ "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \
+ "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
+ "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
+ "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
+ "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
+ "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
+ "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \
+ "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \
+ "dtb_name=" __stringify(MV_DTB_NAME) "\0" \
+ "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \
+ "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \
"mv_version=" U_BOOT_VERSION "\0" \
- "dhcp_client_id=" MK_STR(MV_CI) "\0" \
- "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
+ "dhcp_client_id=" __stringify(MV_CI) "\0" \
+ "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \
"netretry=no\0" \
"use_static_ipaddr=no\0" \
"static_ipaddr=192.168.90.10\0" \
"sensor_cnt=1\0" \
""
-#undef XMK_STR
-#undef MK_STR
-
/*
* IPB Bus clocking configuration.
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"console_nr=0\0" \
- "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \
+ "baudrate=" __stringify(CONFIG_BAUDRATE) "\0" \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0" \
"fpga=0\0" \
- "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
- "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
- "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
- "script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \
- "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
- "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
- "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
- "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
- "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
- "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
- "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
- "dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
+ "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
+ "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
+ "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
+ "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \
+ "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
+ "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
+ "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
+ "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
+ "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
+ "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \
+ "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \
+ "dtb_name=" __stringify(MV_DTB_NAME) "\0" \
"mv_version=" U_BOOT_VERSION "\0" \
"dhcp_client_id=" MV_CI "\0" \
"dhcp_vendor-class-identifier=" MV_VCI "\0" \
#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" \
" allocate=6M"
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"console_nr=0\0" \
"console=no\0" \
"stdout=serial\0" \
"stderr=serial\0" \
"fpga=0\0" \
- "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
- "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
- "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
- "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
- "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
- "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
- "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
- "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
- "mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0" \
- "mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0" \
+ "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
+ "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
+ "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
+ "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
+ "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
+ "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
+ "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
+ "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
+ "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \
+ "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \
"mv_version=" U_BOOT_VERSION "\0" \
- "dhcp_client_id=" MK_STR(MV_CI) "\0" \
- "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
+ "dhcp_client_id=" __stringify(MV_CI) "\0" \
+ "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \
"netretry=no\0" \
"use_static_ipaddr=no\0" \
"static_ipaddr=192.168.0.101\0" \
"netboot=no\0" \
""
-#undef XMK_STR
-#undef MK_STR
-
/*
* IPB Bus clocking configuration.
*/
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
-#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=" MK_STR(CONFIG_DEF_HWCONFIG) "\0" \
+ "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
"netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"loadaddr=1000000\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
"tftpflash=tftpboot $loadaddr $uboot && " \
"protect off $ubootaddr +$filesize && " \
"erase $ubootaddr +$filesize && " \
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
-#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "loadaddr=1000000\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "loadaddr=1000000\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
- "perf_mode=performance\0" \
+"perf_mode=performance\0" \
"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \
"usb1:dr_mode=host,phy_type=ulpi\0" \
- "netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
- "satabootcmd=setenv bootargs root=/dev/$bdev rw " \
+"netdev=eth0\0" \
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+"tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+"satabootcmd=setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=p2020ds/ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "othbootargs=cache-sram-size=0x10000\0" \
- "fdtfile=p2020ds/p2020ds.dtb\0" \
- "bdev=sda3\0" \
- "partition=scsi 0:0\0"
+"consoledev=ttyS0\0" \
+"ramdiskaddr=2000000\0" \
+"ramdiskfile=p2020ds/ramdisk.uboot\0" \
+"fdtaddr=c00000\0" \
+"othbootargs=cache-sram-size=0x10000\0" \
+"fdtfile=p2020ds/p2020ds.dtb\0" \
+"bdev=sda3\0" \
+"partition=scsi 0:0\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
"bank_intlv=cs0_cs1\0" \
"netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
"tftpflash=tftpboot $loadaddr $uboot && " \
"protect off $ubootaddr +$filesize && " \
"erase $ubootaddr +$filesize && " \
"protect on $ubootaddr +$filesize && " \
"cmp.b $loadaddr $ubootaddr $filesize\0" \
"consoledev=ttyS0\0" \
- "usb_phy_type=" MK_STR(__USB_PHY_TYPE) "\0" \
+ "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
"usb_dr_mode=host\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=p2041rdb/ramdisk.uboot\0" \
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;" \
"bootm $loadaddr - $fdtaddr"
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=" CONFIG_NETDEV "\0" \
"ethprime=TSEC1\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
"fdtaddr=ae0000\0" \
"fdtfile=" CONFIG_FDTFILE "\0" \
"console=ttyS0\0" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#undef MK_STR
-#undef XMK_STR
-
#endif /* __CONFIG_H */
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 1 /* default console is on PSC1 */
-#define CONFIG_SERIAL_MULTI 1 /* support multiple consoles */
#define CONFIG_PSC_CONSOLE2 6 /* second console is on PSC6 */
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
- *
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Wolfgang Denk <wd@denx.de>
- * Copyright 2004 Freescale Semiconductor.
- * (C) Copyright 2002,2003 Motorola,Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * TQM85xx (8560/40/55/41/48) board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
-
-#if defined(CONFIG_TQM8548_BE)
-#define CONFIG_SYS_TEXT_BASE 0xfff80000
-#else
-#define CONFIG_SYS_TEXT_BASE 0xfffc0000
-#endif
-
-#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
-#define CONFIG_TQM8548
-#endif
-
-#define CONFIG_PCI
-#ifndef CONFIG_TQM8548_AG
-#define CONFIG_PCI1 /* PCI/PCI-X controller */
-#endif
-#ifdef CONFIG_TQM8548
-#define CONFIG_PCIE1 /* PCI Express interface */
-#endif
-
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCIX_CHECK /* PCIX olny works at 66 MHz */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
-
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-
- /*
- * Configuration for big NOR Flashes
- *
- * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash.
- * Please be aware, that this changes the whole memory map (new CCSRBAR
- * address, etc). You have to use an adapted Linux kernel or FDT blob
- * if this option is set.
- */
-#undef CONFIG_TQM_BIGFLASH
-
-/*
- * NAND flash support (disabled by default)
- *
- * Warning: NAND support will likely increase the U-Boot image size
- * to more than 256 KB. Please adjust CONFIG_SYS_TEXT_BASE if necessary.
- */
-#ifdef CONFIG_TQM8548_BE
-#define CONFIG_NAND
-#endif
-
-/*
- * MPC8540 and MPC8548 don't have CPM module
- */
-#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548)
-#define CONFIG_CPM2 1 /* has CPM2 */
-#endif
-
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-
-#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
-#define CONFIG_CAN_DRIVER /* CAN Driver support */
-#endif
-
-/*
- * sysclk for MPC85xx
- *
- * Two valid values are:
- * 33333333
- * 66666666
- *
- * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
- * is likely the desired value here, so that is now the default.
- * The board, however, can run at 66MHz. In any event, this value
- * must match the settings of some switches. Details can be found
- * in the README.mpc85xxads.
- */
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 33333333
-#endif
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
-
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START 0x00000000
-#define CONFIG_SYS_MEMTEST_END 0x10000000
-
-#ifdef CONFIG_TQM_BIGFLASH
-#define CONFIG_SYS_CCSRBAR 0xA0000000
-#else
-#define CONFIG_SYS_CCSRBAR 0xE0000000
-#endif
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
-
-#if defined(CONFIG_TQM_BIGFLASH) || \
- (!defined(CONFIG_TQM8548_AG) && !defined(CONFIG_TQM8548_BE))
-#define CONFIG_SYS_PPC_DDR_WIMGE (MAS2_I | MAS2_G)
-#define CONFIG_SYS_DDR_EARLY_SIZE_MB (512)
-#else
-#define CONFIG_SYS_PPC_DDR_WIMGE (0)
-#define CONFIG_SYS_DDR_EARLY_SIZE_MB (2 * 1024)
-#endif
-
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#ifdef CONFIG_TQM8548_AG
-#define CONFIG_VERY_BIG_RAM
-#endif
-
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
-/* TQM8540 & 8560 need DLL-override */
-#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
-#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
-#endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
-
-#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \
- defined(CONFIG_TQM8548)
-#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
-#endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */
-
-/*
- * Flash on the Local Bus
- */
-#ifdef CONFIG_TQM_BIGFLASH
-#define CONFIG_SYS_FLASH0 0xE0000000
-#define CONFIG_SYS_FLASH1 0xC0000000
-#else /* !CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_FLASH0 0xFC000000
-#define CONFIG_SYS_FLASH1 0xF8000000
-#endif /* CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
-
-#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
-
-/* Default ORx timings are for <= 41.7 MHz Local Bus Clock.
- *
- * Note: According to timing specifications external addr latch delay
- * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz.
- *
- * For other Local Bus Clocks see following table:
- *
- * Clock/MHz CONFIG_SYS_ORx_PRELIM
- * 166 0x.....CA5
- * 133 0x.....C85
- * 100 0x.....C65
- * 83 0x.....FA2
- * 66 0x.....C82
- * 50 0x.....C60
- * 42 0x.....040
- * 33 0x.....030
- * 25 0x.....020
- *
- */
-#ifdef CONFIG_TQM_BIGFLASH
-#define CONFIG_SYS_BR0_PRELIM 0xE0001801 /* port size 32bit */
-#define CONFIG_SYS_OR0_PRELIM 0xE0000040 /* 512MB Flash */
-#define CONFIG_SYS_BR1_PRELIM 0xC0001801 /* port size 32bit */
-#define CONFIG_SYS_OR1_PRELIM 0xE0000040 /* 512MB Flash */
-#else /* !CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_BR0_PRELIM 0xfc001801 /* port size 32bit */
-#define CONFIG_SYS_OR0_PRELIM 0xfc000040 /* 64MB Flash */
-#define CONFIG_SYS_BR1_PRELIM 0xf8001801 /* port size 32bit */
-#define CONFIG_SYS_OR1_PRELIM 0xfc000040 /* 64MB Flash */
-#endif /* CONFIG_TQM_BIGFLASH */
-
-#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* speed up output to Flash */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-/*
- * Note: when changing the Local Bus clock divider you have to
- * change the timing values in CONFIG_SYS_ORx_PRELIM.
- *
- * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8.
- * LCRR[16:17] EADC : External address delay cycles. It should be set to 2
- * for Local Bus Clock > 83.3 MHz.
- */
-#define CONFIG_SYS_LBC_LCRR 0x00030008 /* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
-#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_CCSRBAR \
- + 0x04010000) /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)/* Reserved for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (384 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#if defined(CONFIG_TQM8560)
-
-#define CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else */
-#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
-
-#else /* !CONFIG_TQM8560 */
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* PS/2 Keyboard */
-#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
-#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
-#define CONFIG_PS2SERIAL 2 /* .. on DUART2 */
-#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
-#define CONFIG_BOARD_EARLY_INIT_R 1
-
-#endif /* CONFIG_TQM8560 */
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/* CAN */
-#define CONFIG_SYS_CAN_BASE (CONFIG_SYS_CCSRBAR \
- + 0x03000000) /* CAN base address */
-#ifdef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */
-#define CONFIG_SYS_OR2_CAN (CONFIG_SYS_CAN_OR_AM | OR_UPM_BI)
-#define CONFIG_SYS_BR2_CAN ((CONFIG_SYS_CAN_BASE & BR_BA) | \
- BR_PS_8 | BR_MS_UPMC | BR_V)
-#endif /* CONFIG_CAN_DRIVER */
-
-/*
- * I2C
- */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x48} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-
-/* I2C RTC */
-#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
-
-/* I2C EEPROM */
-/*
- * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
-
-/* I2C SYSMON (LM75) */
-#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
-#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-
-#ifndef CONFIG_PCIE1
-/* RapidIO MMU */
-#ifdef CONFIG_TQM_BIGFLASH
-#define CONFIG_SYS_RIO_MEM_BASE 0xb0000000 /* base address */
-#define CONFIG_SYS_RIO_MEM_SIZE 0x10000000 /* 256M */
-#else /* !CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
-#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
-#endif /* CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
-#endif /* CONFIG_PCIE1 */
-
-/* NAND FLASH */
-#ifdef CONFIG_NAND
-
-#define CONFIG_NAND_FSL_UPM 1
-
-#define CONFIG_MTD_NAND_ECC_JFFS2 1 /* use JFFS2 ECC */
-
-/* address distance between chip selects */
-#define CONFIG_SYS_NAND_SELECT_DEVICE 1
-#define CONFIG_SYS_NAND_CS_DIST 0x200
-
-#define CONFIG_SYS_NAND_SIZE 0x8000
-#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_CCSRBAR + 0x03010000)
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define CONFIG_SYS_NAND_MAX_CHIPS 2 /* Number of chips per device */
-
-/* CS3 for NAND Flash */
-#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_NAND_BASE & BR_BA) | \
- BR_PS_8 | BR_MS_UPMB | BR_V)
-#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI)
-
-#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */
-
-#endif /* CONFIG_NAND */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BUS (CONFIG_SYS_CCSRBAR + 0x02000000)
-#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS
-#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
-
-#ifdef CONFIG_PCIE1
-/*
- * General PCI express
- * Addresses are mapped 1-1.
- */
-#ifdef CONFIG_TQM_BIGFLASH
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xb0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0xaf000000
-#else /* !CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0xef000000
-#endif /* CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
-#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
-#endif /* CONFIG_PCIE1 */
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-#define CONFIG_EEPRO100
-#undef CONFIG_TULIP
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-
-#endif /* CONFIG_PCI */
-
-
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define TSEC1_PHY_ADDR 2
-#define TSEC2_PHY_ADDR 1
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-#define FEC_PHY_ADDR 3
-#define FEC_PHYIDX 0
-#define FEC_FLAGS 0
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-
-#ifdef CONFIG_TQM8548
-/*
- * TQM8548 has 4 ethernet ports. 4 ETSEC's.
- *
- * On the STK85xx Starterkit the ETSEC3/4 ports are on an
- * additional adapter (AIO) between module and Starterkit.
- */
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "TSEC2"
-#define CONFIG_TSEC4 1
-#define CONFIG_TSEC4_NAME "TSEC3"
-#define TSEC3_PHY_ADDR 4
-#define TSEC4_PHY_ADDR 5
-#define TSEC3_PHYIDX 0
-#define TSEC4_PHYIDX 0
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define CONFIG_HAS_ETH3
-#define CONFIG_HAS_ETH4
-#endif /* CONFIG_TQM8548 */
-
-/* Options are TSEC[0-1], FEC */
-#define CONFIG_ETHPRIME "TSEC0"
-
-#if defined(CONFIG_TQM8540)
-/*
- * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
- * The FEC port is connected on the same signals as the FCC3 port
- * of the TQM8560 to the baseboard (STK85xx Starterkit).
- *
- * On the STK85xx Starterkit the X47/X50 jumper has to be set to
- * a - d (X50.2 - 3) to enable the FEC port.
- */
-#define CONFIG_MPC85XX_FEC 1
-#define CONFIG_MPC85XX_FEC_NAME "FEC"
-#endif
-
-#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
-/*
- * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
- * can be used at once, since only one FCC port is available on the STK85xx
- * Starterkit.
- *
- * To use this port you have to configure U-Boot to use the FCC port 1...2
- * and set the X47/X50 jumper to:
- * FCC1: a - b (X47.2 - X50.2)
- * FCC2: a - c (X50.2 - 1)
- */
-#define CONFIG_ETHER_ON_FCC
-#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
-#endif
-
-#if defined(CONFIG_TQM8560)
-/*
- * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
- * can be used at once, since only one FCC port is available on the STK85xx
- * Starterkit.
- *
- * To use this port you have to configure U-Boot to use the FCC port 1...3
- * and set the X47/X50 jumper to:
- * FCC1: a - b (X47.2 - X50.2)
- * FCC2: a - c (X50.2 - 1)
- * FCC3: a - d (X50.2 - 3)
- */
-#define CONFIG_ETHER_ON_FCC
-#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
-#endif
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
-#define CONFIG_ETHER_ON_FCC1
-#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
- CMXFCR_TF1CS_MSK)
-#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
-#define CONFIG_SYS_CPMFCR_RAMTYPE 0
-#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-#endif
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-#define CONFIG_ETHER_ON_FCC2
-#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
- CMXFCR_TF2CS_MSK)
-#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
-#define CONFIG_SYS_CPMFCR_RAMTYPE 0
-#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-#endif
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
-#define CONFIG_ETHER_ON_FCC3
-#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
- CMXFCR_TF3CS_MSK)
-#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
-#define CONFIG_SYS_CPMFCR_RAMTYPE 0
-#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K (one sector) for env */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_TIMESTAMP /* Print image info with ts */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-#ifdef CONFIG_NAND
-/*
- * Use NAND-FLash as JFFS2 device
- */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_JFFS2
-
-#define CONFIG_JFFS2_NAND 1
-
-#ifdef CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nand0=TQM85xx-nand"
-#define MTDPARTS_DEFAULT "mtdparts=TQM85xx-nand:-"
-#else
-#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
-#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
-#define CONFIG_JFFS2_PART_SIZE 0x200000 /* size of jffs2 partition */
-#endif /* CONFIG_CMD_MTDPARTS */
-
-#endif /* CONFIG_NAND */
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-#ifndef CONFIG_TQM8548_AG
-#define CONFIG_CMD_DATE
-#endif
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buf Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
-
-#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
-
-
-/*
- * Setup some board specific values for the default environment variables
- */
-#ifdef CONFIG_CPM2
-#define CONFIG_ENV_CONSDEV "consdev=ttyCPM0\0"
-#else
-#define CONFIG_ENV_CONSDEV "consdev=ttyS0\0"
-#endif
-#define CONFIG_ENV_FDT_FILE "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \
- MK_STR(CONFIG_HOSTNAME)".dtb\0"
-#define CONFIG_ENV_BOOTFILE "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
-#define CONFIG_ENV_UBOOT "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
- "uboot_addr="MK_STR(CONFIG_SYS_TEXT_BASE)"\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_ENV_BOOTFILE \
- CONFIG_ENV_FDT_FILE \
- CONFIG_ENV_CONSDEV \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $bootargs " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
- ":$hostname:$netdev:off panic=1\0" \
- "addcons=setenv bootargs $bootargs " \
- "console=$consdev,$baudrate\0" \
- "flash_nfs=run nfsargs addip addcons;" \
- "bootm $kernel_addr - $fdt_addr\0" \
- "flash_self=run ramargs addip addcons;" \
- "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
- "net_nfs=tftp $kernel_addr_r $bootfile;" \
- "tftp $fdt_addr_r $fdt_file;" \
- "run nfsargs addip addcons;" \
- "bootm $kernel_addr_r - $fdt_addr_r\0" \
- "rootpath=/opt/eldk/ppc_85xx\0" \
- "fdt_addr_r=900000\0" \
- "kernel_addr_r=1000000\0" \
- "fdt_addr=ffec0000\0" \
- "kernel_addr=ffd00000\0" \
- "ramdisk_addr=ff800000\0" \
- CONFIG_ENV_UBOOT \
- "load=tftp 100000 $uboot\0" \
- "update=protect off $uboot_addr +$filesize;" \
- "erase $uboot_addr +$filesize;" \
- "cp.b 100000 $uboot_addr $filesize" \
- "upd=run load update\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#endif /* __CONFIG_H */
#define CONFIG_VERSION_VARIABLE
/* set to negative value for no autoboot */
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
"fdtaddr=0x80F80000\0" \
"console=ttyO0,115200n8\0" \
"optargs=\0" \
"mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcroot=/dev/mmcblk0p2 ro\0" \
"mmcrootfstype=ext4 rootwait\0" \
"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
"ramrootfstype=ext2\0" \
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x402F0400
-#define CONFIG_SPL_MAX_SIZE (46 * 1024)
+#define CONFIG_SPL_MAX_SIZE (101 * 1024)
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
+#define CONFIG_SPL_ETH_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
/*
/*
* UART
*/
-#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs}\0"
#endif
-#define xstr(s) str(s)
-#define str(s) #s
-
/*
* General common environment variables shared on all AMCC eval boards
*/
#define CONFIG_AMCC_DEF_ENV \
- "netdev=" xstr(CONFIG_USE_NETDEV) "\0" \
+ "netdev=" __stringify(CONFIG_USE_NETDEV) "\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs}" \
- " console=" xstr(CONFIG_USE_TTY) ",${baudrate}\0" \
+ " console=" __stringify(CONFIG_USE_TTY) ",${baudrate}\0" \
CONFIG_ADDMISC \
"initrd_high=30000000\0" \
"kernel_addr_r=1000000\0" \
"fdt_addr_r=1800000\0" \
"ramdisk_addr_r=1900000\0" \
- "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
- "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
CONFIG_AMCC_DEF_ENV_ROOTPATH
/*
"net_self=run net_self_load;" \
"run ramargs addip addtty addmisc;" \
"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
- "fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0"
+ "fdt_file=" __stringify(CONFIG_HOSTNAME) "/" __stringify(CONFIG_HOSTNAME) ".dtb\0"
/*
* Default environment for arch/ppc booting,
"bootm ${kernel_addr_r}\0"
#define CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
- "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
- "era " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
- "cp.b ${fileaddr} " xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
+ "era " __stringify(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
+ "cp.b ${fileaddr} " __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
#define CONFIG_AMCC_DEF_ENV_NAND_UPD \
- "u-boot-nand=" xstr(CONFIG_HOSTNAME) "/u-boot-nand.bin\0" \
+ "u-boot-nand=" __stringify(CONFIG_HOSTNAME) "/u-boot-nand.bin\0"\
"nload=tftp 200000 ${u-boot-nand}\0" \
"nupdate=nand erase 0 100000;nand write 200000 0 100000\0" \
"nupd=run nload nupdate\0"
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */
+#define CONFIG_SYS_PSC3
#if CONFIG_PSC_CONSOLE != 3
#error CONFIG_PSC_CONSOLE must be 3
#endif
--- /dev/null
+/*
+ * Configuation settings for the bonito board
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARMADILLO_800EVA_H
+#define __ARMADILLO_800EVA_H
+
+#undef DEBUG
+#define CONFIG_ARMV7
+#define CONFIG_R8A7740
+#define CONFIG_RMOBILE
+#define CONFIG_RMOBILE_BOARD_STRING "Armadillo-800EVA Board\n"
+#define CONFIG_SH_GPIO_PFC
+
+#include <asm/arch/rmobile.h>
+
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_BOOTZ
+
+#define CONFIG_OF_LIBFDT
+#define BOARD_LATE_INIT
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS ""
+
+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_TMU_TIMER
+#define CONFIG_SYS_DCACHE_OFF
+
+/* STACK */
+#define CONFIG_SYS_INIT_SP_ADDR 0xE8083000
+#define STACK_AREA_SIZE 0xC000
+#define LOW_LEVEL_MERAM_STACK \
+ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define ARMADILLO_800EVA_SDRAM_BASE 0x40000000
+#define ARMADILLO_800EVA_SDRAM_SIZE (512 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE 512
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF1
+#define SCIF0_BASE 0xe6c40000
+#define SCIF1_BASE 0xe6c50000
+#define SCIF2_BASE 0xe6c60000
+#define SCIF4_BASE 0xe6c80000
+#define CONFIG_SCIF_A
+#undef CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START (ARMADILLO_800EVA_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
+ 504 * 1024 * 1024)
+#undef CONFIG_SYS_ALT_MEMTEST
+#undef CONFIG_SYS_MEMTEST_SCRATCH
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE (ARMADILLO_800EVA_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ 64 * 1024 * 1024)
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE (256)
+#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
+#define CONFIG_SYS_TEXT_BASE 0xE80C0000
+
+/* FLASH */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_BASE 0x00000000
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
+#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
+#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
+
+/* SH Ether */
+#define CONFIG_NET_MULTI
+#define CONFIG_SH_ETHER
+#define CONFIG_SH_ETHER_USE_PORT 0
+#define CONFIG_SH_ETHER_PHY_ADDR 0x0
+#define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000
+#define CONFIG_SH_ETHER_SH7734_MII (0x01)
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ 50000000
+#define CONFIG_SYS_TMU_CLK_DIV 4
+#define CONFIG_SYS_HZ 1000
+
+#endif /* __ARMADILLO_800EVA_H */
#ifndef _CONFIG_ASTRO_MCF5373L_H
#define _CONFIG_ASTRO_MCF5373L_H
+#include <linux/stringify.h>
+
/*
* set the card type to actually compile for; either of
* the possibilities listed below has to be used!
* u-boot: 'set' command
*/
-#define _QUOTEME(x) #x
-#define QUOTEME(x) _QUOTEME(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"loaderversion=11\0" \
- "card_id="QUOTEME(ASTRO_ID)"\0" \
+ "card_id="__stringify(ASTRO_ID)"\0" \
"alterafile=0\0" \
"xilinxfile=0\0" \
"xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_OF_LIBFDT
+
#define CONFIG_ATMEL_LEGACY
#define CONFIG_SYS_TEXT_BASE 0x21f00000
/* Address and size of Primary Environment Sector */
#define CONFIG_ENV_SIZE 0x10000
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_EXTRA_ENV_SETTINGS \
- "monitor_base=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
"update=" \
"protect off ${monitor_base} +${filesize};" \
"erase ${monitor_base} +${filesize};" \
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_OF_LIBFDT
+
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#define CONFIG_AT91_GPIO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_OF_LIBFDT
+
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#define CONFIG_AT91_GPIO
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_STUART 1
+#define CONFIG_CONS_INDEX 2
#define CONFIG_BAUDRATE 115200
/*
#define BOOT_ENV_SETTINGS \
"update=tftpboot $(loadaddr) u-boot.ldr;" \
- "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \
+ "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
"sf erase 0 0x30000;" \
"sf write $(loadaddr) 0 $(filesize)" \
"flashboot=sf read 0x1000000 0x30000 0x320000;" \
#define BOOT_ENV_SETTINGS \
"update=tftpboot $(loadaddr) u-boot.ldr;" \
- "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \
+ "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
"sf erase 0 0x30000;" \
"sf write $(loadaddr) 0 $(filesize)" \
"flashboot=sf read 0x1000000 0x30000 0x320000;" \
# define CONFIG_BAUDRATE 57600
#endif
#ifndef CONFIG_DEBUG_EARLY_SERIAL
-# define CONFIG_SERIAL_MULTI
# define CONFIG_SYS_BFIN_UART
#endif
#endif
#define CONFIG_BOOTARGS \
"root=" CONFIG_BOOTARGS_ROOT " " \
- "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \
+ "clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
"earlyprintk=" \
"serial," \
- "uart" MK_STR(CONFIG_UART_CONSOLE) "," \
- MK_STR(CONFIG_BAUDRATE) " " \
+ "uart" __stringify(CONFIG_UART_CONSOLE) "," \
+ __stringify(CONFIG_BAUDRATE) " " \
CONFIG_BOOTARGS_VIDEO \
- "console=ttyBF" MK_STR(CONFIG_UART_CONSOLE) "," MK_STR(CONFIG_BAUDRATE)
+ "console=ttyBF" __stringify(CONFIG_UART_CONSOLE) "," \
+ __stringify(CONFIG_BAUDRATE)
#if defined(CONFIG_CMD_NAND)
# define NAND_ENV_SETTINGS \
"nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
# define CONFIG_BFIN_SPI_IMG_SIZE 0x40000
# endif
# define UBOOT_ENV_UPDATE \
- "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \
- "sf erase 0 " MK_STR(CONFIG_BFIN_SPI_IMG_SIZE) ";" \
+ "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
+ "sf erase 0 " __stringify(CONFIG_BFIN_SPI_IMG_SIZE) ";" \
"sf write $(loadaddr) 0 $(filesize)"
# endif
# elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
#define CONFIG_BOOTCOMMAND "run ramboot"
#define CONFIG_BOOTARGS \
"root=/dev/mtdblock0 rw " \
- "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \
+ "clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
"earlyprintk=" \
"serial," \
- "uart" MK_STR(CONFIG_UART_CONSOLE) "," \
- MK_STR(CONFIG_BAUDRATE) " " \
- "console=ttyBF0," MK_STR(CONFIG_BAUDRATE)
+ "uart" __stringify(CONFIG_UART_CONSOLE) "," \
+ __stringify(CONFIG_BAUDRATE) " " \
+ "console=ttyBF0," __stringify(CONFIG_BAUDRATE)
#if defined(CONFIG_CMD_NET)
# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
"eeprom write $(loadaddr) 0x0 $(filesize)"
# else
# define UBOOT_ENV_UPDATE \
- "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \
+ "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
"sf erase 0 0x40000;" \
"sf write $(loadaddr) 0 $(filesize)"
# endif
*/
#define CONFIG_BOOTARGS \
"root=/dev/mtdblock0 rw " \
- "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \
+ "clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
"earlyprintk=serial,uart0," \
- MK_STR(CONFIG_BAUDRATE) " " \
- "console=ttyBF0," MK_STR(CONFIG_BAUDRATE) " "
+ __stringify(CONFIG_BAUDRATE) " " \
+ "console=ttyBF0," __stringify(CONFIG_BAUDRATE) " "
/* Convenience env variables & commands.
* Reserve kernstart = 0x20000 = 128 kB for U-Boot.
/*
* Default environment settings
*/
-#define xstr(s) str(s)
-#define str(s) #s
#define DVN4XX_UBOOT_ADDR_R_RAM 0x80000000
/* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
#define DVN4XX_UBOOT_ADDR_R_UBOOT 0x80003800
#define CONFIG_EXTRA_ENV_SETTINGS \
- "u_boot_addr_r=" xstr(DVN4XX_UBOOT_ADDR_R_RAM) "\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.ubl\0" \
+ "u_boot_addr_r=" __stringify(DVN4XX_UBOOT_ADDR_R_RAM) "\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.ubl\0" \
"load=tftp ${u_boot_addr_r} ${u-boot}\0" \
- "pagesz=" xstr(CONFIG_SYS_NAND_PAGE_SIZE) "\0" \
+ "pagesz=" __stringify(CONFIG_SYS_NAND_PAGE_SIZE) "\0" \
"writeheader=nandrbl rbl;nand erase 20000 ${pagesz};" \
"nand write ${u_boot_addr_r} 20000 ${pagesz};" \
"nandrbl uboot\0" \
"writenand_spl=nandrbl rbl;nand erase 0 3000;" \
- "nand write " xstr(DVN4XX_UBOOT_ADDR_R_NAND_SPL) \
+ "nand write " __stringify(DVN4XX_UBOOT_ADDR_R_NAND_SPL) \
" 0 3000;nandrbl uboot\0" \
"writeuboot=nandrbl uboot;" \
- "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
- xstr(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
- ";nand write " xstr(DVN4XX_UBOOT_ADDR_R_UBOOT) \
- " " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
- xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
+ "nand erase " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "\
+ __stringify(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
+ ";nand write " __stringify(DVN4XX_UBOOT_ADDR_R_UBOOT) \
+ " " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
+ __stringify(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
"update=run load writenand_spl writeuboot\0" \
"bootcmd=run net_nfs\0" \
"rootpath=/opt/eldk-arm/arm\0" \
"rootpath=/opt/eldk-arm/arm\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
- "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage \0" \
+ "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
"kernel_addr_r=80600000\0" \
"load_kernel=tftp ${kernel_addr_r} ${bootfile}\0" \
"ubi_load_kernel=ubi part ubi 2048;ubifsmount ${img_volume};" \
"ubifsload ${kernel_addr_r} boot/uImage\0" \
- "fit_addr_r=" xstr(CONFIG_BOARD_IMG_ADDR_R) "\0" \
- "img_addr_r=" xstr(CONFIG_BOARD_IMG_ADDR_R) "\0" \
- "img_file=" xstr(CONFIG_HOSTNAME) "/ait.itb\0" \
+ "fit_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0" \
+ "img_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0" \
+ "img_file=" __stringify(CONFIG_HOSTNAME) "/ait.itb\0" \
"header_addr=20000\0" \
"img_writeheader=nandrbl rbl;" \
"nand erase ${header_addr} ${pagesz};" \
"img_writespl=nandrbl rbl;nand erase 0 3000;" \
"nand write ${img_addr_r} 0 3000;nandrbl uboot\0" \
"img_writeuboot=nandrbl uboot;" \
- "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
- xstr(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
+ "nand erase " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "\
+ __stringify(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
";nand write ${img_addr_r} " \
- xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
- xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
+ __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
+ __stringify(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
"img_writedfenv=ubi part ubi 2048;" \
"ubi write ${img_addr_r} default ${filesize}\0" \
"img_volume=rootfs1\0" \
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART 1
+#define CONFIG_CONS_INDEX 3
#define CONFIG_BAUDRATE 115200
/*
/*-----------------------------------------------------------------------
* Serial Configuration
*/
-#define CONFIG_SERIAL_MULTI
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
"bank_intlv=cs0_cs1;" \
- "usb1:dr_mode=host,phy_type=" MK_STR(__USB_PHY_TYPE) "\0"\
+ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
"tftpflash=tftpboot $loadaddr $uboot && " \
"protect off $ubootaddr +$filesize && " \
"erase $ubootaddr +$filesize && " \
"run commonargs; " \
"setenv bootargs ${bootargs} " \
"root=/dev/mmcblk0p2 " \
+ "rootwait " \
"${kernelopts}\0" \
"nandargs=" \
"run commonargs; " \
/*-----------------------------------------------------------------------
* Serial Configuration
*/
-#define CONFIG_SERIAL_MULTI
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_USE_SPIFLASH
#define CONFIG_SYS_USE_NAND
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_VIDEO
* Network & Ethernet Configuration
*/
#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM 0
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_VIDEO_DA8XX
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_VIDEO_LOGO
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_CMD_BMP
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#endif
/*
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_NO_SUBPAGE
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
#undef CONFIG_SYS_NAND_HW_ECC
* Default environment and default scripts
* to update uboot and load kernel
*/
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_HOSTNAME ea20
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CONFIG_EXTRA_ENV_SETTINGS \
"as=3\0" \
- "netdev=eth0\0" \
+ "netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"rfsbargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rfsbpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "mtdids=nand0=davinci_nand.0\0" \
- "mtdparts=mtdparts=davinci_nand.0:8m(Settings),8m(aKernel)," \
- "8m(bKernel),76m(aRootfs),76m(bRootfs),-(MassSD)\0" \
+ "testrfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${testrfspath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw initrd=" \
+ "0x${ramdisk_addr_r},4M\0" \
+ "mtdids=nand0=davinci_nand.0\0" \
+ "serverip=192.168.5.249\0" \
+ "ipaddr=192.168.5.248\0" \
+ "rootpath=/opt/eldk/arm\0" \
+ "splashpos=230,180\0" \
+ "testrfspath=/opt/eldk/test_arm\0" \
+ "tempmac=setenv ethaddr 02:ea:20:ff:ff:ff\0" \
"nandargs=setenv bootargs rootfstype=ubifs ro chk_data_crc " \
"ubi.mtd=${as} root=ubi0:rootfs\0" \
+ "nandrwargs=setenv bootargs rootfstype=ubifs rw chk_data_crc " \
+ "ubi.mtd=${as} root=ubi0:rootfs\0" \
"addip_sta=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
- "addip=if test -n ${ipdyn};then run addip_dyn;" \
+ "addip=if test -n ${ipdyn};then run addip_dyn;" \
"else run addip_sta;fi\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addtty=setenv bootargs ${bootargs}" \
" console=${consoledev},${baudrate}n8\0" \
- "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
+ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
"addmem=setenv bootargs ${bootargs} mem=${memory}\0" \
"consoledev=ttyS0\0" \
"loadaddr=c0000014\0" \
"memory=32M\0" \
"kernel_addr_r=c0700000\0" \
- "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
- "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/image.ext2\0" \
"flash_self=run ramargs addip addtty addmtd addmisc addmem;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "bootm ${kernel_addr_r}\0" \
"flash_nfs=run nfsargs addip addtty addmtd addmisc addmem;" \
"bootm ${kernel_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
"run nfsargs addip addtty addmtd addmisc addmem;" \
- "bootm ${kernel_addr_r}\0" \
- "net_rfsb=tftp ${kernel_addr_r} ${bootfile}; " \
- "run rfsbargs addip addtty addmtd addmisc addmem; " \
- "bootm ${kernel_addr_r}\0" \
+ "bootm ${kernel_addr_r}\0" \
+ "net_rfsb=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run rfsbargs addip addtty addmtd addmisc addmem; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_testrfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run testrfsargs addip addtty addmtd addmisc addmem; " \
+ "bootm ${kernel_addr_r}\0" \
"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
- "nand_nand=ubi part nand0,${as};ubifsmount rootfs;" \
- "ubifsload ${kernel_addr_r} /boot/uImage;" \
- "ubifsumount; run nandargs addip addtty " \
- "addmtd addmisc addmem;bootm ${kernel_addr_r}\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
- "load_magic=if sf probe 0;then sf " \
- "read c0000000 0x10000 0x60000;fi\0" \
- "load_nand=ubi part nand0,${as};ubifsmount rootfs;" \
- "if ubifsload c0000014 /boot/u-boot.bin;" \
- "then mw c0000008 ${filesize};else echo Error reading " \
- "u-boot from nand!;fi\0" \
- "load_net=if sf probe 0;then sf read c0000000 0x10000 0x60000;" \
- "tftp c0000014 ${u-boot};" \
- "mw c0000008 ${filesize};" \
- "fi\0" \
- "upd=if sf probe 0;then sf erase 10000 60000;" \
- "sf write c0000000 10000 60000;" \
- "fi\0" \
- "ubootupd_net=if run load_net;then echo Updating u-boot;" \
- "if run upd; then echo U-Boot updated;" \
+ "nand_nand=ubi part nand0,${as};ubifsmount rootfs;" \
+ "ubifsload ${kernel_addr_r} /boot/uImage;" \
+ "ubifsumount; run nandargs addip addtty " \
+ "addmtd addmisc addmem;clrlogo;" \
+ "bootm ${kernel_addr_r}\0" \
+ "nand_nandrw=ubi part nand0,${as};ubifsmount rootfs;" \
+ "ubifsload ${kernel_addr_r} /boot/uImage;" \
+ "ubifsumount; run nandrwargs addip addtty " \
+ "addmtd addmisc addmem;clrlogo;" \
+ "bootm ${kernel_addr_r}\0" \
+ "net_nandrw=tftp ${kernel_addr_r} ${bootfile}; run nandrwargs" \
+ " addip addtty addmtd addmisc addmem;" \
+ "clrlogo;bootm ${kernel_addr_r}\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load_magic=if sf probe 0;then sf " \
+ "read c0000000 0x10000 0x60000;fi\0" \
+ "load_nand=ubi part nand0,${as};ubifsmount rootfs;" \
+ "if ubifsload c0000014 /boot/u-boot.bin;" \
+ "then mw c0000008 ${filesize};else echo Error reading" \
+ " u-boot from nand!;fi\0" \
+ "load_net=if sf probe 0;then sf read c0000000 0x10000 " \
+ "0x60000;tftp c0000014 ${u-boot};" \
+ "mw c0000008 ${filesize};fi\0" \
+ "upd=if sf probe 0;then sf erase 10000 60000;" \
+ "sf write c0000000 10000 60000;fi\0" \
+ "ublupdate=if tftp C0700000 ${ublname};then sf probe 0; " \
+ "sf erase 0 10000;" \
+ "sf write 0xc0700000 0 ${filesize};fi\0" \
+ "ubootupd_net=if run load_net;then echo Updating u-boot;" \
+ "if run upd; then echo U-Boot updated;" \
"else echo Error updating u-boot !;" \
"echo Board without bootloader !!;" \
"fi;" \
- "else echo U-Boot not downloaded..exiting;fi\0" \
- "ubootupd_nand=echo run load_magic,run load_nand,run upd;\0" \
- "bootcmd=run net_nfs\0"
+ "else echo U-Boot not downloaded..exiting;fi\0" \
+ "ubootupd_nand=echo run load_magic,run load_nand,run upd;\0" \
+ "bootcmd=run tempmac;run net_testrfs\0"
#endif /* __CONFIG_H */
/*
* Size of malloc() pool
*/
-#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */
/*
* Other required minimal configurations
#define CONFIG_DEFAULT_SETTINGS_ADDR (CONFIG_ENV_ADDR_REDUND + \
CONFIG_ENV_SECT_SIZE)
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"u-boot_addr_r=c0000000\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
- "update=protect off " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
- "erase " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
- "cp.b ${u-boot_addr_r} " xstr(CONFIG_SYS_FLASH_BASE) \
+ "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
+ "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
+ "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
" ${filesize};" \
- "protect on " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
+ "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
"netdev=eth0\0" \
"rootpath=/opt/eldk-arm/arm\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"kernel_addr_r=c0700000\0" \
"fdt_addr_r=c0600000\0" \
"ramdisk_addr_r=c0b00000\0" \
- "fdt_file=" xstr(CONFIG_HOSTNAME) "/" \
- xstr(CONFIG_HOSTNAME) ".dtb\0" \
- "kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" \
+ "fdt_file=" __stringify(CONFIG_HOSTNAME) "/" \
+ __stringify(CONFIG_HOSTNAME) ".dtb\0" \
+ "kernel_file=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
"nand_ld_ramdsk=nand read ${ramdisk_addr_r} 320000 400000\0" \
"nand_ld_kernel=nand read ${kernel_addr_r} 20000 300000\0" \
"nand_ld_fdt=nand read ${fdt_addr_r} 0 2000\0" \
* Default environment and default scripts
* to update uboot and load kernel
*/
-#define xstr(s) str(s)
-#define str(s) #s
#define CONFIG_HOSTNAME flea3
#define CONFIG_EXTRA_ENV_SETTINGS \
":${hostname}:${netdev}:off panic=1\0" \
"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
"addip=if test -n ${ipdyn};then run addip_dyn;" \
- "else run addip_sta;fi\0" \
+ "else run addip_sta;fi\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addtty=setenv bootargs ${bootargs}" \
" console=ttymxc2,${baudrate}\0" \
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
"loadaddr=80800000\0" \
"kernel_addr_r=80800000\0" \
- "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
- "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
"flash_self=run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
"run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
"else echo Images not loades;fi\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
- "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
"update=protect off ${uboot_addr} +40000;" \
"erase ${uboot_addr} +40000;" \
"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Thomas.Lange@corelatus.se
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * This file contains the configuration parameters for the gth2 board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
-#define CONFIG_GTH2 1
-#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
-
-#define CONFIG_SOC_AU1000 1
-
-#define CONFIG_MISC_INIT_R 1
-
-#define CONFIG_ETHADDR DE:AD:BE:EF:01:02 /* Ethernet address */
-
-#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
-
-#define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */
-
-#define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */
-
-#define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */
-
-#define CONFIG_BAUDRATE 115200
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-
-/* Only interrupt boot if space is pressed */
-/* If a long serial cable is connected but */
-/* other end is dead, garbage will be read */
-#define CONFIG_AUTOBOOT_KEYED 1
-#define CONFIG_AUTOBOOT_PROMPT \
- "Press space to abort autoboot in %d second\n", bootdelay
-#define CONFIG_AUTOBOOT_DELAY_STR "d"
-#define CONFIG_AUTOBOOT_STOP_STR " "
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_BOOTARGS "panic=1"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "addmisc=setenv bootargs $(bootargs) " \
- "ethaddr=$(ethaddr) \0" \
- "netboot=bootp;run addmisc;bootm\0" \
- ""
-
-/* Boot from Compact flash partition 2 as default */
-#define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;run addmisc;bootm"
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_DHCP
-
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_BEDBUG
-#undef CONFIG_CMD_ELF
-#undef CONFIG_CMD_FAT
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_SAVEENV
-#undef CONFIG_CMD_SOURCE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "GTH2 # " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
-
-#define CONFIG_SYS_MALLOC_LEN 128*1024
-
-#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
-
-#define CONFIG_SYS_MHZ 500
-
-#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-
-#define CONFIG_SYS_HZ 1000
-
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
-
-#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
-
-#define CONFIG_SYS_MEMTEST_START 0x80100000
-#define CONFIG_SYS_MEMTEST_END 0x83000000
-
-#define CONFIG_HW_WATCHDOG 1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
-
-#define PHYS_FLASH 0xbfc00000 /* Flash Bank #1 */
-
-/* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 << 10)
-
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-
-/* We boot from this flash, selected with dip switch */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_ENV_IS_NOWHERE 1
-
-/* Address and size of Primary Environment Sector */
-#define CONFIG_ENV_ADDR 0xB0030000
-#define CONFIG_ENV_SIZE 0x10000
-
-#define CONFIG_FLASH_16BIT
-
-#define CONFIG_NR_DRAM_BANKS 2
-
-
-#define CONFIG_MEMSIZE_IN_BYTES
-
-/*---ATA PCMCIA ------------------------------------*/
-#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
-
-#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
-#define CONFIG_SYS_PCMCIA_IO_BASE 0x28000000
-#define CONFIG_SYS_PCMCIA_ATTR_BASE 0x30000000
-
-#define CONFIG_PCMCIA_SLOT_A
-
-#define CONFIG_ATAPI 1
-#define CONFIG_MAC_PARTITION 1
-
-/* We run CF in "true ide" mode or a harddrive via pcmcia */
-#define CONFIG_IDE_PCMCIA 1
-
-/* We only support one slot for now */
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_IO_BASE
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET 0
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE 16384
-#define CONFIG_SYS_ICACHE_SIZE 16384
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
-#define GPIO_CACONFIG (1<<0)
-#define GPIO_DPACONFIG (1<<6)
-#define GPIO_ERESET (1<<11)
-#define GPIO_EEDQ (1<<17)
-#define GPIO_WDI (1<<18)
-#define GPIO_RJ1LY (1<<22)
-#define GPIO_RJ1LG (1<<23)
-#define GPIO_LEDCLK (1<<29)
-#define GPIO_LEDD (1<<30)
-#define GPIO_CPU_LED (1<<31)
-
-#endif /* __CONFIG_H */
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Harmony"
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTD
/* UARTD: keyboard satellite board UART, default */
--- /dev/null
+/*
+ * (C) Copyright 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <uboot@lukaperkov.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _CONFIG_ICONNECT_H
+#define _CONFIG_ICONNECT_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING " Iomega iConnect"
+
+/*
+ * High level configuration options
+ */
+#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
+#define CONFIG_KIRKWOOD /* SOC Family Name */
+#define CONFIG_KW88F6281 /* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+/*
+ * Machine type
+ */
+#define CONFIG_MACH_TYPE MACH_TYPE_ICONNECT
+
+/*
+ * Compression configuration
+ */
+#define CONFIG_BZIP2
+#define CONFIG_LZMA
+#define CONFIG_LZO
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* declare no flash (NOR/SPI) */
+#define CONFIG_SYS_MVFS
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT "iconnect => "
+
+/*
+ * Environment variables configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_OFFSET 0x80000
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
+ "ubi part rootfs; " \
+ "ubifsmount rootfs; " \
+ "ubifsload 0x800000 ${kernel}; " \
+ "bootm 0x800000"
+
+#define CONFIG_MTDPARTS \
+ "mtdparts=orion_nand:" \
+ "0x80000@0x0(uboot)," \
+ "0x20000@0x80000(uboot_env)," \
+ "-@0xa0000(rootfs)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=console=ttyS0,115200\0" \
+ "mtdids=nand0=orion_nand\0" \
+ "mtdparts="CONFIG_MTDPARTS \
+ "kernel=/boot/uImage\0" \
+ "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
+
+/*
+ * Ethernet driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 11
+#undef CONFIG_RESET_PHY_R
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+
+#endif /* _CONFIG_ICONNECT_H */
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx5x_pins.h>
-#define CONFIG_SYS_MX5_HCLK 24000000
-#define CONFIG_SYS_MX5_CLK32 32768
-
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
*/
#define HOSTNAME ima3-mx53
-#define xstr(s) str(s)
-#define str(s) #s
#define CONFIG_HOSTNAME ima3-mx53
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=70800000\0" \
"kernel_addr_r=70800000\0" \
"ramdisk_addr_r=71000000\0" \
- "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
- "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
"mmcargs=setenv bootargs root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
"mmcroot=/dev/mmcblk0p3 rw\0" \
"run satargs addip addtty addmtd addmisc;" \
"sata init;ext2load sata 0:1 ${kernel_addr_r} " \
"${satafile};bootm\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.imx\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.imx\0" \
"uimage=uImage\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"uboot_addr=0xf0001000\0" \
#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
" console=ttymxc0,${baudrate}\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addmisc=setenv bootargs ${bootargs}\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"kernel_addr_r=a0800000\0" \
- "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
"rootpath=/opt/eldk-4.2-arm/arm\0" \
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
"run nfsargs addip addtty addmtd addmisc;" \
"bootm\0" \
- "bootcmd=run net_nfs\0" \
+ "bootcmd=run net_nfs\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
- "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
- " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
" +${filesize};cp.b ${fileaddr} " \
- xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
+ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
/*
* Serial
*/
-#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
"ubi part " CONFIG_KM_UBI_PARTITION_NAME_APP "; fi\0"
#endif /* CONFIG_KM_UBI_PARTITION_NAME_APP */
-#define xstr(s) str(s)
-#define str(s) #s
-
/*
* boottargets
* - set 'subbootcmds'
":${hostname}:${netdev}:off3" \
" console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}" \
" mem=${kernelmem} init=${init}" \
- " phram.phram=phvar,${varaddr}," xstr(CONFIG_KM_PHRAM) \
+ " phram.phram=phvar,${varaddr}," __stringify(CONFIG_KM_PHRAM)\
" " CONFIG_KM_UBI_LINUX_MTD " " \
CONFIG_KM_DEF_BOOT_ARGS_CPU \
"\0" \
* - 'cramfsloadfdt': copy fdt from a cramfs to ram
*/
#define CONFIG_KM_DEF_ENV_FLASH_BOOT \
- "cramfsaddr=" xstr(CONFIG_KM_CRAMFS_ADDR) "\0" \
+ "cramfsaddr=" __stringify(CONFIG_KM_CRAMFS_ADDR) "\0" \
"cramfsloadkernel=cramfsload ${load_addr_r} uImage\0" \
- "ubicopy=ubi read "xstr(CONFIG_KM_CRAMFS_ADDR) \
+ "ubicopy=ubi read "__stringify(CONFIG_KM_CRAMFS_ADDR) \
" bootfs${boot_bank}\0" \
CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI
#define CONFIG_KM_DEF_ENV_CONSTANTS \
"backup_bank=0\0" \
"release=run newenv; reset\0" \
- "pnvramsize=" xstr(CONFIG_KM_PNVRAM) "\0" \
+ "pnvramsize=" __stringify(CONFIG_KM_PNVRAM) "\0" \
"testbootcmd=setenv boot_bank ${test_bank}; " \
"run ${subbootcmds}; reset\0" \
""
"saveenv && saveenv && boot\0" \
"bootlimit=3\0" \
"init=/sbin/init-overlay.sh\0" \
- "load_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \
+ "load_addr_r="__stringify(CONFIG_KM_KERNEL_ADDR) "\0" \
"load=tftpboot ${load_addr_r} ${u-boot}\0" \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"cramfsloadfdt=" \
"cramfsload ${fdt_addr_r} " \
"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
- "fdt_addr_r=" xstr(CONFIG_KM_FDT_ADDR) "\0" \
- "u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
+ "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"update=" \
- "protect off " xstr(BOOTFLASH_START) " +${filesize} && "\
- "erase " xstr(BOOTFLASH_START) " +${filesize} && " \
- "cp.b ${load_addr_r} " xstr(BOOTFLASH_START) \
+ "protect off " __stringify(BOOTFLASH_START) " +${filesize} && "\
+ "erase " __stringify(BOOTFLASH_START) " +${filesize} && "\
+ "cp.b ${load_addr_r} " __stringify(BOOTFLASH_START) \
" ${filesize} && " \
- "protect on " xstr(BOOTFLASH_START) " +${filesize}\0" \
+ "protect on " __stringify(BOOTFLASH_START) " +${filesize}\0"\
""
#endif /* __CONFIG_KEYMILE_POWERPC_H */
#define CONFIG_KM_DEF_ENV_CPU \
"boot=bootm ${load_addr_r} - -\0" \
"cramfsloadfdt=true\0" \
- "u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.kwb\0" \
+ "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.kwb\0" \
CONFIG_KM_UPDATE_UBOOT \
""
#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_KM_NEW_ENV \
"newenv=sf probe 0;" \
- "sf erase " xstr(CONFIG_ENV_OFFSET) " " \
- xstr(CONFIG_ENV_TOTAL_SIZE)"\0"
+ "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
+ __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
#else
#define CONFIG_KM_NEW_ENV \
"newenv=setenv addr 0x100000 && " \
"i2c dev 1; mw.b ${addr} 0 4 && " \
- "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
- " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \
- "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
- " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0"
+ "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \
+ " ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && " \
+ "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \
+ " ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0"
#endif
/*
#define CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_KM_FPGA_CONFIG
#define CONFIG_KM_PIGGY4_88E6352
+#define CONFIG_MV88E6352_SWITCH
+#define CONFIG_KM_MVEXTSW_ADDR 0x10
/* KM_MGCOGE3UN */
#elif defined(CONFIG_KM_MGCOGE3UN)
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
--- /dev/null
+/*
+ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __KZM9G_H
+#define __KZM9G_H
+
+#undef DEBUG
+
+#define CONFIG_RMOBILE
+#define CONFIG_SH73A0
+#define CONFIG_KZM_A9_GT
+#define CONFIG_RMOBILE_BOARD_STRING "KMC KZM-A9-GT"
+#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G
+
+#include <asm/arch/rmobile.h>
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_L2_OFF
+#define CONFIG_OF_LIBFDT
+
+#include <config_cmd_default.h>
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_BOOTZ
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTARGS "root=/dev/null console=ttySC4,115200"
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+/* MEMORY */
+#define KZM_SDRAM_BASE (0x40000000)
+#define PHYS_SDRAM KZM_SDRAM_BASE
+#define PHYS_SDRAM_SIZE (512 * 1024 * 1024)
+#define CONFIG_NR_DRAM_BANKS (1)
+
+/* NOR Flash */
+#define KZM_FLASH_BASE (0x00000000)
+#define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE)
+#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
+#define CONFIG_SYS_MAX_FLASH_BANKS (1)
+#define CONFIG_SYS_MAX_FLASH_SECT (512)
+
+/* prompt */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "KZM-A9-GT# "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE 512
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF4
+#undef CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END \
+ (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
+#undef CONFIG_SYS_ALT_MEMTEST
+#undef CONFIG_SYS_MEMTEST_SCRATCH
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */
+#define CONFIG_SYS_INIT_RAM_SIZE (0x10000)
+#define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024)
+#define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
+#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
+
+#define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE (256)
+#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
+
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000
+
+/* FLASH */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#undef CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */
+#define CONFIG_ENV_SIZE FLASH_SECTOR_SIZE
+#define CONFIG_ENV_OFFSET FLASH_SECTOR_SIZE
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+
+/* Timeout for Flash erase operations (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
+
+#undef CONFIG_SYS_FLASH_PROTECTION
+#undef CONFIG_SYS_DIRECT_FLASH_TFTP
+#define CONFIG_ENV_IS_IN_FLASH
+
+/* GPIO / PFC */
+#define CONFIG_SH_GPIO_PFC
+
+/* Clock */
+#define CONFIG_GLOBAL_TIMER
+#define CONFIG_SYS_CLK_FREQ (48000000)
+#define CONFIG_SYS_CPU_CLK (1196000000)
+#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
+#define CFG_HZ (1000)
+#define CONFIG_SYS_HZ CFG_HZ
+
+/* Ether */
+#define CONFIG_NET_MULTI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE (0x10000000)
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_NFS_TIMEOUT 10000UL
+
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SH_I2C 1
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS (2)
+#define CONFIG_SYS_I2C_MODULE
+#define CONFIG_SYS_I2C_SPEED (100000) /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE (0x7F)
+#define CONFIG_SH_I2C_DATA_HIGH (4)
+#define CONFIG_SH_I2C_DATA_LOW (5)
+#define CONFIG_SH_I2C_CLOCK (41666666)
+#define CONFIG_SH_I2C_BASE0 (0xE6820000)
+#define CONFIG_SH_I2C_BASE1 (0xE6822000)
+
+#endif /* __KZM9G_H */
#elif defined(CONFIG_NETSPACE_V2)
#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2
#define CONFIG_IDENT_STRING " NS v2"
+#elif defined(CONFIG_NETSPACE_LITE_V2)
+#define MACH_TYPE_NETSPACE_LITE_V2 2983 /* missing in mach-types.h */
+#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_LITE_V2
+#define CONFIG_IDENT_STRING " NS v2 Lite"
+#elif defined(CONFIG_NETSPACE_MINI_V2)
+#define MACH_TYPE_NETSPACE_MINI_V2 2831 /* missing in mach-types.h */
+#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MINI_V2
+#define CONFIG_IDENT_STRING " NS v2 Mini"
#elif defined(CONFIG_NETSPACE_MAX_V2)
#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2
#define CONFIG_IDENT_STRING " NS Max v2"
+#elif defined(CONFIG_D2NET_V2)
+#define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2
+#define CONFIG_IDENT_STRING " D2 v2"
#elif defined(CONFIG_NET2BIG_V2)
#define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2
#define CONFIG_IDENT_STRING " 2Big v2"
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-#define CONFIG_KIRKWOOD /* SOC Family Name */
-#define CONFIG_KW88F6281 /* SOC Name */
+#define CONFIG_KIRKWOOD /* SoC Family Name */
+/* SoC name */
+#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
+#define CONFIG_KW88F6192
+#else
+#define CONFIG_KW88F6281
+#endif
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
#define CONFIG_CMD_SF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
+#ifndef CONFIG_NETSPACE_MINI_V2 /* No USB ports on Network Space v2 Mini */
#define CONFIG_CMD_USB
+#endif
/*
* Core clock definition
*/
#define CONFIG_NR_DRAM_BANKS 1
-#ifdef CONFIG_INETSPACE_V2
-/* Different SDRAM configuration and size for Internet Space v2 */
+/*
+ * Different SDRAM configuration and size for some of the boards derived
+ * from the Network Space v2
+ */
+#if defined(CONFIG_INETSPACE_V2)
#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg
+#elif defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
+#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg
#endif
/*
#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */
#define CONFIG_SYS_IDE_MAXBUS 1
#define CONFIG_SYS_IDE_MAXDEVICE 1
-#if defined(CONFIG_NET2BIG_V2)
+#if defined(CONFIG_D2NET_V2)
+#define CONFIG_SYS_PROMPT "d2v2> "
+#elif defined(CONFIG_NET2BIG_V2)
#define CONFIG_SYS_PROMPT "2big2> "
#else
#define CONFIG_SYS_PROMPT "ns2> "
*/
#ifdef CONFIG_MVSATA_IDE
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_NET2BIG_V2)
+#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \
+ defined(CONFIG_NET2BIG_V2)
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
#endif
#endif /* CONFIG_MVSATA_IDE */
#endif /* CONFIG_CMD_I2C */
/*
+ * Partition support
+ */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/*
* File systems support
*/
#define CONFIG_CMD_EXT2
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#if defined(CONFIG_HLAN) || defined(CONFIG_LAN)
#define UBFILE "share/u-boot/u-boot-hd.flash.bin"
#elif defined(CONFIG_HGLAN)
"stdin=nc\0" \
"stdout=nc\0" \
"stderr=nc\0" \
- "ipaddr="MK_STR(CONFIG_IPADDR_LS)"\0" \
+ "ipaddr="__stringify(CONFIG_IPADDR_LS)"\0" \
"netmask=255.255.255.0\0" \
- "serverip="MK_STR(CONFIG_SERVERIP_LS)"\0" \
- "ncip="MK_STR(CONFIG_NCIP_LS)"\0" \
+ "serverip="__stringify(CONFIG_SERVERIP_LS)"\0" \
+ "ncip="__stringify(CONFIG_NCIP_LS)"\0" \
"netretry=no\0" \
"nc=setenv stdin nc;setenv stdout nc;setenv stderr nc\0" \
"ser=setenv stdin serial;setenv stdout serial;setenv stderr serial\0" \
"&& bootm 0x00100000 0x00800000\0" \
"bootcmd_rescue=run config_nc_dhcp; run nc\0" \
"eraseenv=sf probe 0 " \
- "&& sf erase " MK_STR(CONFIG_ENV_OFFSET) \
- " +" MK_STR(CONFIG_ENV_SIZE) "\0" \
+ "&& sf erase " __stringify(CONFIG_ENV_OFFSET) \
+ " +" __stringify(CONFIG_ENV_SIZE) "\0" \
"config_nc_dhcp=setenv autoload_old ${autoload}; " \
"setenv autoload no " \
"&& bootp " \
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
+#define CONFIG_CONS_INDEX 3
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_LCD_INFO 1 /* ... and some board info */
#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#define CONFIG_8xx_CONS_SCC2 1 /* Console is on SCC2 */
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_MXS_SPI_DMA_ENABLE
#define CONFIG_SPI_HALF_DUPLEX
#define CONFIG_DEFAULT_SPI_BUS 2
+#define CONFIG_DEFAULT_SPI_CS 0
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
/* SPI FLASH */
#ifdef CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SF_DEFAULT_CS 2
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_BUS 2
+#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 40000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_BUS 2
+#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 40000000
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
#endif
#undef CONFIG_BOOTARGS
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"kernel_addr=ff810000\0" \
- "fdt_addr="xstr(CONFIG_SYS_FLASH_BASE)"\0" \
+ "fdt_addr="__stringify(CONFIG_SYS_FLASH_BASE)"\0" \
"flash_nfs=run nfsargs addip addcon addwdt addlog;" \
"bootm ${kernel_addr} - ${fdt_addr}\0" \
"rootpath=/opt/eldk/ppc_82xx\0" \
"kernel_addr_r=300000\0" \
"fdt_addr_r=200000\0" \
- "fdt_file=" xstr(CONFIG_HOSTNAME) "/" \
- xstr(CONFIG_HOSTNAME) ".dtb\0" \
- "kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" \
+ "fdt_file=" __stringify(CONFIG_HOSTNAME) "/" \
+ __stringify(CONFIG_HOSTNAME) ".dtb\0" \
+ "kernel_file=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
"load_fdt=tftp ${fdt_addr_r} ${fdt_file};\0" \
"load_kernel=tftp ${kernel_addr_r} ${kernel_file};\0" \
"addcon=setenv bootargs ${bootargs} console=ttyPSC0,${baudrate}\0"\
"net_nfs=run load_fdt load_kernel; " \
"run nfsargs addip addcon addwdt addlog;" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin \0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin \0" \
"u-boot_addr_r=200000\0" \
"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
- "update=protect off " xstr(CONFIG_SYS_TEXT_BASE) " +${filesize};" \
- "erase " xstr(CONFIG_SYS_TEXT_BASE) " +${filesize};" \
- "cp.b ${u-boot_addr_r} " xstr(CONFIG_SYS_TEXT_BASE) \
+ "update=protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +${filesize};"\
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +${filesize};"\
+ "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_TEXT_BASE) \
" ${filesize};" \
- "protect on " xstr(CONFIG_SYS_TEXT_BASE) " +${filesize}\0" \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +${filesize}\0"\
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
*/
#if !defined(CONFIG_PRS200)
/* MCC200 configuration: */
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */
#define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */
#else
/* PRS200 configuration: */
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#endif
-#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) && \
- !defined(CONFIG_SERIAL_MULTI)
-#error "Select only one console device!"
-#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#undef CONFIG_BOOTARGS
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#ifdef CONFIG_PRS200
# define CONFIG_SYS__BOARDNAME "prs200"
# define CONFIG_SYS__LINUX_CONSOLE "ttyS0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"ubootver=" U_BOOT_VERSION "\0" \
"netdev=eth0\0" \
- "hostname=" CONFIG_SYS__BOARDNAME "\0" \
+ "hostname=" CONFIG_SYS__BOARDNAME "\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/mtdblock2 " \
"rootpath=/opt/eldk/ppc_6xx\0" \
"bootfile=/tftpboot/" CONFIG_SYS__BOARDNAME "/uImage\0" \
"load=tftp 200000 /tftpboot/" CONFIG_SYS__BOARDNAME "/u-boot.bin\0" \
- "text_base=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
+ "text_base=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
"kernel_addr=0xFC0C0000\0" \
"update=protect off ${text_base} +${filesize};" \
"era ${text_base} +${filesize};" \
"cp.b 200000 ${text_base} ${filesize}\0" \
"unlock=yes\0" \
""
-#undef MK_STR
-#undef XMK_STR
#define CONFIG_BOOTCOMMAND "run flash_self"
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
+#define CONFIG_SYS_PSC3
#if CONFIG_PSC_CONSOLE != 3
#error CONFIG_PSC_CONSOLE must be 3
#endif
#include "tegra20-common.h"
-/* Enable fdt support for Medcom. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra20-medcom
+/* Enable fdt support for Medcom-Wide. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE tegra20-medcom-wide
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
-#define V_PROMPT "Tegra20 (Medcom) # "
-#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Medcom"
+#define V_PROMPT "Tegra20 (Medcom-Wide) # "
+#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide"
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <gj@denx.de>
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2009-2010
+ * Michel Pollet <buserror@gmail.com>
+ *
+ * (C) Copyright 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * Configuation settings for the MINI2440 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE 0x0
+#define CONFIG_S3C2440_GPIO
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARM920T /* This is an ARM920T Core */
+#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */
+#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */
+#define CONFIG_MINI2440 /* on a MIN2440 Board */
+
+#define MACH_TYPE_MINI2440 1999
+#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440
+
+/*
+ * We don't use lowlevel_init
+ */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/*
+ * input clock of PLL
+ */
+/* MINI2440 has 12.0000MHz input clock */
+#define CONFIG_SYS_CLK_FREQ 12000000
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_DM9000
+#define CONFIG_DRIVER_DM9000_NO_EEPROM
+#define CONFIG_DM9000_BASE 0x20000300
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE+4)
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_S3C24X0_SERIAL
+#define CONFIG_SERIAL1
+
+/*
+ * allow to overwrite serial and ethaddr
+ */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Command definition
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_LONGHELP
+#define CONFIG_SYS_PROMPT "MINI2440 => "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 32
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x30000000
+#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x32000000
+
+/* boot parameters address */
+#define CONFIG_BOOT_PARAM_ADDR 0x30000100
+
+/*
+ * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
+ * it to wrap 100 times (total 1562500) to get 1 sec.
+ */
+#define CONFIG_SYS_HZ 1562500
+
+/*
+ * valid baudrates
+ */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */
+#define CONFIG_SYS_SDRAM_BASE 0x30000000
+#define CONFIG_SYS_FLASH_BASE 0x0
+
+/*
+ * Stack should be on the SRAM because
+ * DRAM is not init
+ */
+#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * NOR FLASH organization
+ * Now uses the standard CFI interface
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_MONITOR_BASE 0x0
+/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+/* 512 * 4096 sectors, or 32 * 64k blocks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+#define CONFIG_FLASH_SHOW_PROGRESS 1
+
+/*
+ * Config for NOR flash
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_MY_ENV_OFFSET 0x40000
+/* addr of environment */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET)
+/* 16k Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE 0x4000
+
+/* ATAG configuration */
+#define CONFIG_INITRD_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+#endif /* __CONFIG_H */
* (C) Copyright 2003-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Based on PRO Motion board config file by Andy Joseph, andy@promessdev.com
+ * Based on Motion-PRO board config file by Robert McCullough, rob@promessinc.com
*
* See file CREDITS for list of people who contributed to this
* project.
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_ETHADDR 00:50:C2:40:10:00
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=motionpro\0" \
- "netmask=255.255.0.0\0" \
- "ipaddr=192.168.160.22\0" \
- "serverip=192.168.1.1\0" \
- "gatewayip=192.168.1.1\0" \
+ "netmask=255.255.255.0\0" \
+ "ipaddr=192.168.1.106\0" \
+ "serverip=192.168.1.100\0" \
+ "gatewayip=192.168.1.100\0" \
"console=ttyPSC0,115200\0" \
"u-boot_addr=400000\0" \
"kernel_addr=400000\0" \
"fdt_addr=700000\0" \
"ramdisk_addr=800000\0" \
"multi_image_addr=800000\0" \
- "rootpath=/opt/eldk/ppc_6xx\0" \
- "u-boot=motionpro/u-boot.bin\0" \
- "bootfile=motionpro/uImage\0" \
- "fdt_file=motionpro/motionpro.dtb\0" \
- "ramdisk_file=motionpro/uRamdisk\0" \
+ "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
+ "u-boot=/tftpboot/motionpro/u-boot.bin\0" \
+ "bootfile=/tftpboot/motionpro/uImage\0" \
+ "fdt_file=/tftpboot/motionpro/motionpro.dtb\0" \
+ "ramdisk_file=/tftpboot/motionpro/uRamdisk\0" \
"multi_image_file=kernel+initrd+dtb.img\0" \
"load=tftp ${u-boot_addr} ${u-boot}\0" \
"update=prot off fff00000 +${filesize};" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
- "fat_args=setenv bootargs rw\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "fat_args=setenv bootargs root=/dev/sda rw\0" \
+ "mtdids=nor0=ff000000.flash\0" \
+ "mtdparts=ff000000.flash:13m(fs),2m(kernel),384k(uboot)," \
+ "128k(env),128k(redund_env)," \
+ "128k(dtb),128k(user_data)\0" \
+ "addcons=setenv bootargs ${bootargs} console=${console}\0" \
+ "addmtd=setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
"${netmask}:${hostname}:${netdev}:off panic=1 " \
"console=${console}\0" \
"net_nfs=tftp ${kernel_addr} ${bootfile}; " \
- "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip; " \
+ "tftp ${fdt_addr} ${fdt_file}; " \
+ "run nfsargs addip addmtd; " \
"bootm ${kernel_addr} - ${fdt_addr}\0" \
"net_self=tftp ${kernel_addr} ${bootfile}; " \
"tftp ${fdt_addr} ${fdt_file}; " \
"tftp ${ramdisk_addr} ${ramdisk_file}; " \
- "run ramargs addip; " \
+ "nfs ${ramdisk_addr} ${serverip}:${rootpath}/images/uRamdisk; " \
+ "run ramargs addip addcons addmtd; " \
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
- "fat_multi=run fat_args addip; fatload ide 0:1 " \
+ "fat_multi=run fat_args addip addmtd; fatload ide 0:1 " \
"${multi_image_addr} ${multi_image_file}; " \
"bootm ${multi_image_addr}\0" \
""
-#define CONFIG_BOOTCOMMAND "run net_nfs"
+#define CONFIG_BOOTCOMMAND "run fat_multi"
/*
* do board-specific init
#define CONFIG_SYS_RAMBOOT 1
#endif
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* 1 MiB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=motionpro-0"
#define MTDPARTS_DEFAULT "mtdparts=motionpro-0:" \
- "13m(fs),2m(kernel),256k(uboot)," \
+ "13m(fs),2m(kernel),384k(uboot)," \
"128k(env),128k(redund_env)," \
"128k(dtb),-(user_data)"
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
+#define CONFIG_SYS_PSC3
#if CONFIG_PSC_CONSOLE != 3
#error CONFIG_PSC_CONSOLE must be 3
#endif
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
"bootcmd=run flash_self\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
- "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
- " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
" +${filesize};cp.b ${fileaddr} " \
- xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
+ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
#endif /* __CONFIG_H */
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_CMD_USB
/* Configuration of lowlevel_init.S (clocks and SDRAM) */
#define CCM_CCMR_SETUP 0x074B0BF5
-#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
- PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \
- PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \
- PDR0_MCU_PODF(0))
-#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
+#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
+ PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \
+ PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \
+ PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
+#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
PLL_MFN(12))
#define ESDMISC_MDDR_SETUP 0x00000004
* Default environment and default scripts
* to update uboot and load kernel
*/
-#define xstr(s) str(s)
-#define str(s) #s
#define CONFIG_HOSTNAME "mx35pdk"
#define CONFIG_EXTRA_ENV_SETTINGS \
":${hostname}:${netdev}:off panic=1\0" \
"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
"addip=if test -n ${ipdyn};then run addip_dyn;" \
- "else run addip_sta;fi\0" \
+ "else run addip_sta;fi\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addtty=setenv bootargs ${bootargs}" \
" console=ttymxc0,${baudrate}\0" \
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
"loadaddr=80800000\0" \
"kernel_addr_r=80800000\0" \
- "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
- "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
"flash_self=run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr_r}\0" \
"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
- "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
"update=protect off ${uboot_addr} +80000;" \
"erase ${uboot_addr} +80000;" \
"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MX5_HCLK 24000000
-#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MX51 /* in a mx51 */
-#define CONFIG_SYS_MX5_HCLK 24000000
-#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
#define CONFIG_OF_LIBFDT
#define CONFIG_MX53
-#define CONFIG_SYS_MX5_HCLK 24000000
-#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MX53
-#define CONFIG_SYS_MX5_HCLK 24000000
-#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MX53
-#define CONFIG_SYS_MX5_HCLK 24000000
-#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO
#define CONFIG_MX53
-#define CONFIG_SYS_MX5_HCLK 24000000
-#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define __CONFIG_H
#define CONFIG_MX6Q
-#define CONFIG_SYS_MX6_HCLK 24000000
-#define CONFIG_SYS_MX6_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
--- /dev/null
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreSD board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MX6QSABRE_COMMON_CONFIG_H
+#define __MX6QSABRE_COMMON_CONFIG_H
+
+#define CONFIG_MX6Q
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 1
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x10800000
+#define CONFIG_SYS_TEXT_BASE 0x17800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "uimage=uImage\0" \
+ "console=" CONFIG_CONSOLE_DEV "\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "dhcp ${uimage}; bootm\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "if mmc rescan ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x10010000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE (128 * 1024)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#endif
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_SYS_DCACHE_OFF
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif /* __MX6QSABRE_COMMON_CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreSD board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __MX6QSABREAUTO_CONFIG_H
+#define __MX6QSABREAUTO_CONFIG_H
+
+#define CONFIG_MACH_TYPE 3529
+#define CONFIG_MXC_UART_BASE UART4_BASE
+#define CONFIG_CONSOLE_DEV "ttymxc3"
+#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
+
+#include "mx6qsabre_common.h"
+
+#endif /* __MX6QSABREAUTO_CONFIG_H */
#define __CONFIG_H
#define CONFIG_MX6Q
-#define CONFIG_SYS_MX6_HCLK 24000000
-#define CONFIG_SYS_MX6_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
--- /dev/null
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreSD board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MX6QSABRESD_CONFIG_H
+#define __MX6QSABRESD_CONFIG_H
+
+#define CONFIG_MACH_TYPE 3980
+#define CONFIG_MXC_UART_BASE UART1_BASE
+#define CONFIG_CONSOLE_DEV "ttymxc0"
+#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
+
+#include "mx6qsabre_common.h"
+
+#endif /* __MX6QSABRESD_CONFIG_H */
* NS16550 Configuration
* Zoom2 uses the TL16CP754C on the debug board
*/
-#define CONFIG_SERIAL_MULTI 1
/*
* 0 - 1 : first USB with respect to the left edge of the debug board
* 2 - 3 : second USB with respect to the left edge of the debug board
*/
-#define ZOOM2_DEFAULT_SERIAL_DEVICE (&zoom2_serial_device0)
+#define ZOOM2_DEFAULT_SERIAL_DEVICE 0
#define V_NS16550_CLK (1843200) /* 1.8432 Mhz */
/*
* High Level Configuration Options
*/
-#define CONFIG_PANDA /* working with Panda */
/* USB UHH support options */
#define CONFIG_CMD_USB
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
/* select serial console configuration */
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SERIAL2 1 /* use SERIAL 2 */
#define CONFIG_BAUDRATE 115200
#define EXYNOS4_DEFAULT_UART_OFFSET 0x020000
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
-"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"loadaddr=1000000\0" \
"bootfile=uImage\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdisk_size=120000\0" \
"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
-MK_STR(__NOR_RST_CMD)"\0" \
-MK_STR(__SPI_RST_CMD)"\0" \
-MK_STR(__SD_RST_CMD)"\0" \
-MK_STR(__NAND_RST_CMD)"\0" \
-MK_STR(__PCIE_RST_CMD)"\0"
+__stringify(__NOR_RST_CMD)"\0" \
+__stringify(__SPI_RST_CMD)"\0" \
+__stringify(__SD_RST_CMD)"\0" \
+__stringify(__NAND_RST_CMD)"\0" \
+__stringify(__PCIE_RST_CMD)"\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART 1
+#define CONFIG_CONS_INDEX 3
#define CONFIG_BAUDRATE 9600
/*
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART 1
+#define CONFIG_CONS_INDEX 3
#define CONFIG_BAUDRATE 115200
/*
#define CONFIG_TEGRA_BOARD_STRING "Compal Paz00"
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clk used */
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*
* Used PSC UART devices
*/
-#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_PSC1
#define CONFIG_SYS_PSC4
#define CONFIG_SYS_PSC6
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
-#ifdef CONFIG_SERIAL_MULTI
/* POST support */
#define CONFIG_POST (CONFIG_SYS_POST_COPROC)
-#endif
/*
* Environment Configuration
#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Plutux"
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
+#define CONFIG_CONS_INDEX 3
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"bootm\0" \
"bootcmd=run flash_self\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
- "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
- " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
" +${filesize};cp.b ${fileaddr} " \
- xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
+ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
"videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000," \
"le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296," \
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
#define CONFIG_SYS_BASE_BAUD 691200
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \
* select serial console configuration
*/
#define CONFIG_SERIAL2 1 /* use SERIAL2 */
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_BAUDRATE 115200
/* MMC */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
/* select serial console configuration */
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SERIAL2 1 /* use SERIAL 2 */
#define CONFIG_BAUDRATE 115200
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=uRamdisk\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=sbc8548.dtb\0"
+"netdev=eth0\0" \
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+"tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+"consoledev=ttyS0\0" \
+"ramdiskaddr=2000000\0" \
+"ramdiskfile=uRamdisk\0" \
+"fdtaddr=c00000\0" \
+"fdtfile=sbc8548.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#define CONFIG_SERIAL_MULTI
/*
* define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Seaboard"
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
/* select serial console configuration */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_SERIAL3 /* use SERIAL 3 */
#define CONFIG_BAUDRATE 115200
#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
* select serial console configuration
*/
#define CONFIG_SERIAL0 1 /* use SERIAL 0 on SMDKC100 */
-#define CONFIG_SERIAL_MULTI 1
/* PWM */
#define CONFIG_PWM 1
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
/* select serial console configuration */
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SERIAL1 1 /* use SERIAL 1 */
#define CONFIG_BAUDRATE 115200
#define EXYNOS4_DEFAULT_UART_OFFSET 0x010000
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/socfpga_base_addrs.h>
+
+/*
+ * High level configuration
+ */
+
+#define CONFIG_ARMV7
+#define CONFIG_L2_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#undef CONFIG_USE_IRQ
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SINGLE_BOOTLOADER
+#define CONFIG_SOCFPGA
+
+#define CONFIG_SYS_TEXT_BASE 0x08000040
+#define V_NS16550_CLK 1000000
+#define CONFIG_BAUDRATE 57600
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_TIMER_CLOCK_KHZ 2400
+#define CONFIG_SYS_LOAD_ADDR 0x7fc0
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # "
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * Display CPU and Board Info
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/*
+ * Enable early stage initialization at C environment
+ */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* flat device tree */
+#define CONFIG_OF_LIBFDT
+/* skip updating the FDT blob */
+#define CONFIG_FDT_BLOB_SKIP_UPDATE
+/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
+#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024))
+
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_STACK (&__stack_start)
+#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
+#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
+
+/*
+ * Memory allocation (MALLOC)
+ */
+/* Room required on the stack for the environment data */
+#define CONFIG_ENV_SIZE 1024
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
+
+/* SP location before relocation, must use scratch RAM */
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
+/* Reserving 0x100 space at back of scratch RAM for debug info */
+#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
+/* Stack pointer prior relocation, must situated at on-chip RAM */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+/* FAT file system support */
+#define CONFIG_CMD_FAT
+
+
+/*
+ * Misc
+ */
+#define CONFIG_DOS_PARTITION 1
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_PARTITIONS
+#endif
+
+/*
+ * Environment setup
+ */
+
+/* Delay before automatically booting the default image */
+#define CONFIG_BOOTDELAY 3
+/* Enable auto completion of commands using TAB */
+#define CONFIG_AUTO_COMPLETE
+/* use "hush" command parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMD_RUN
+
+#define CONFIG_BOOTCOMMAND "run ramboot"
+
+/*
+ * arguments passed to the bootm command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=n\0" \
+ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "bootimage=uImage\0" \
+ "fdt_addr=100\0" \
+ "fsloadcmd=ext2load\0" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "qspiroot=/dev/mtdblock0\0" \
+ "qspirootfstype=jffs2\0" \
+ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+ "bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* using environment setting for stdin, stdout, stderr */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+/* Enable the call to overwrite_console() */
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+/* Enable overwrite of previous console environment settings */
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * SDRAM Memory Map
+ */
+/* We have 1 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+/* SDRAM Bank #1 */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+/* SDRAM memory size */
+#define PHYS_SDRAM_1_SIZE 0x80000000
+
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START 0x00000000
+#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
+
+/*
+ * NS16550 Configuration
+ */
+#define UART0_BASE SOCFPGA_UART0_ADDRESS
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_COM1 UART0_BASE
+
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * FLASH
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* This timer use eosc1 where the clock frequency is fixed
+ * throughout any condition */
+#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
+
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL 0xFFFFFFFF
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/*
+ * SPL "Second Program Loader" aka Initial Software
+ */
+
+/* Enable building of SPL globally */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+
+/* TEXT_BASE for linking the SPL binary */
+#define CONFIG_SPL_TEXT_BASE 0xFFFF0000
+
+/* Stack size for SPL */
+#define CONFIG_SPL_STACK_SIZE (4 * 1024)
+
+/* MALLOC size for SPL */
+#define CONFIG_SPL_MALLOC_SIZE (5 * 1024)
+
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+
+#define CHUNKSZ_CRC32 (1 * 1024)
+
+#define CONFIG_CRC32_VERIFY
+
+/* Linker script for SPL */
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
+
+/* Support for common/libcommon.o in SPL binary */
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+/* Support for lib/libgeneric.o in SPL binary */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
+#endif /* __CONFIG_H */
"1m(u-boot),256k(env1)," \
"256k(env2),6m(kernel),-(rootfs)"
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_TAM3517_SETTINGS \
"netdev=eth0\0" \
"nandargs=setenv bootargs root=${nandroot} " \
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
"loadaddr=82000000\0" \
"kernel_addr_r=82000000\0" \
- "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
- "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
"flash_self=run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
"run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
"else echo Images not loades;fi\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.img\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"loadmlo=tftp ${loadaddr} ${mlo}\0" \
- "mlo=" xstr(CONFIG_HOSTNAME) "/MLO\0" \
+ "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
"uboot_addr=0x80000\0" \
"update=nandecc sw;nand erase ${uboot_addr} 100000;" \
"nand write ${loadaddr} ${uboot_addr} 80000\0" \
#define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#undef CONFIG_OF_CONTROL
#endif
-/* remove SERIAL_MULTI */
-#ifdef CONFIG_SERIAL_MULTI
-#undef CONFIG_SERIAL_MULTI
-#endif
-
/* remove I2C support */
#ifdef CONFIG_TEGRA_I2C
#undef CONFIG_TEGRA_I2C
#undef CONFIG_CMD_USB
#endif
+/* remove part command support */
+#ifdef CONFIG_PARTITION_UUIDS
+#undef CONFIG_PARTITION_UUIDS
+#endif
+
+#ifdef CONFIG_CMD_PART
+#undef CONFIG_CMD_PART
+#endif
+
#endif /* CONFIG_SPL_BUILD */
#endif /* __TEGRA_COMMON_POST_H */
#ifndef __TEGRA20_COMMON_H
#define __TEGRA20_COMMON_H
#include <asm/sizes.h>
-
-/*
- * QUOTE(m) will evaluate to a string version of the value of the macro m
- * passed in. The extra level of indirection here is to first evaluate the
- * macro m before applying the quoting operator.
- */
-#define QUOTE_(m) #m
-#define QUOTE(m) QUOTE_(m)
+#include <linux/stringify.h>
/*
* High Level Configuration Options
#define CONFIG_SYS_CACHELINE_SIZE 32
-#include <asm/arch/tegra20.h> /* get chip and board defs */
+#include <asm/arch/tegra.h> /* get chip and board defs */
/*
* Display CPU and Board information
#define TEGRA_LP0_ADDR 0x1C406000
#define TEGRA_LP0_SIZE 0x2000
#define TEGRA_LP0_VEC \
- "lp0_vec=" QUOTE(TEGRA_LP0_SIZE) "@" QUOTE(TEGRA_LP0_ADDR) " "
+ "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
+ "@" __stringify(TEGRA_LP0_ADDR) " "
#else
#define TEGRA_LP0_VEC
#endif
/* include default commands */
#include <config_cmd_default.h>
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
/* remove unused commands */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
/* select serial console configuration */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_SERIAL2 /* use SERIAL 2 */
#define CONFIG_BAUDRATE 115200
#define CONFIG_TEGRA_BOARD_STRING "Compulab Trimslice"
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_TEGRA_UARTA_GPU
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
* select serial console configuration
*/
#define CONFIG_PXA_SERIAL
-#define CONFIG_SERIAL_MULTI
#define CONFIG_FFUART 1 /* we use FFUART on Conxs */
#define CONFIG_BTUART 1 /* we use BTUART on Conxs */
#define CONFIG_STUART 1 /* we use STUART on Conxs */
+#define CONFIG_CONS_INDEX 3
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addmisc=setenv bootargs ${bootargs}\0" \
"u-boot=tx25/u-boot.bin\0" \
- "kernel_addr_r=" xstr(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"hostname=tx25\0" \
"bootfile=tx25/uImage\0" \
"rootpath=/opt/eldk/arm\0" \
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
- "ethprime=" MK_STR(CONFIG_TSEC1_NAME) "\0" \
- "u-boot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "netdev=" __stringify(CONFIG_NETDEV) "\0" \
+ "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \
+ "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"u-boot_addr_r=100000\0" \
"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
- "update=protect off " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
- "erase " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
- "cp.b ${u-boot_addr_r} " MK_STR(CONFIG_SYS_FLASH_BASE) \
+ "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
+ " +${filesize};" \
+ "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
+ "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
" ${filesize};" \
- "protect on " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
-
-#undef MK_STR
-#undef XMK_STR
+ "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
#endif /* __CONFIG_H */
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Ventana"
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MX5_HCLK 24000000
-#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART 1
+#define CONFIG_CONS_INDEX 3
#define CONFIG_BAUDRATE 115200
/*
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Whistler"
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_TEGRA_UARTA_UAA_UAB
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SPEAR600 /* SPEAr600 SoC */
+#define CONFIG_X600 /* on X600 board */
+
+#include <asm/arch/hardware.h>
+
+/* Timer, HZ specific defines */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_HZ_CLOCK 8300000
+
+#define CONFIG_SYS_TEXT_BASE 0x00800040
+#define CONFIG_SYS_FLASH_BASE 0xf8000000
+/* Reserve 8KiB for SPL */
+#define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */
+#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_SPL_LEN)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN 0x60000
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+/* Serial Configuration (PL011) */
+#define CONFIG_SYS_SERIAL0 0xD0000000
+#define CONFIG_SYS_SERIAL1 0xD0080000
+#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
+ (void *)CONFIG_SYS_SERIAL1 }
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
+ 57600, 115200 }
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/* NOR FLASH config options */
+#define CONFIG_ST_SMI
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
+#define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
+
+/* NAND FLASH config options */
+#define CONFIG_NAND_FSMC
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE
+#define CONFIG_MTD_ECC_SOFT
+#define CONFIG_SYS_FSMC_NAND_8BIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* UBI/UBI config options */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_RBTREE
+
+/* Ethernet config options */
+#define CONFIG_MII
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_DW_SEARCH_PHY
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
+#define CONFIG_DW_AUTONEG
+#define CONFIG_PHY_ADDR 0 /* PHY address */
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+
+#define CONFIG_SPEAR_GPIO
+
+/* I2C config options */
+#define CONFIG_HARD_I2C
+#define CONFIG_DW_I2C
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_I2C_SLAVE 0x02
+#define CONFIG_I2C_CHIPADDRESS 0x50
+
+#define CONFIG_RTC_M41T62 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/* FPGA config options */
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_SPARTAN3
+#define CONFIG_FPGA_COUNT 1
+
+/*
+ * Command support defines
+ */
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_LZO
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <config_cmd_default.h>
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * U-Boot Environment placing definitions.
+ */
+#define CONFIG_ENV_SECT_SIZE 0x00010000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE 0x02000
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
+ CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+/* Miscellaneous configurable options */
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_LOOPW /* enable loopw command */
+#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR " "
+#define CONFIG_AUTOBOOT_PROMPT \
+ "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay
+
+#define CONFIG_SYS_MEMTEST_START 0x00800000
+#define CONFIG_SYS_MEMTEST_END 0x04000000
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+#define CONFIG_IDENT_STRING "-SPEAr"
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "X600> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LOAD_ADDR 0x00800000
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+/* Use last 2 lwords in internal SRAM for bootcounter */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_SYS_BOOTCOUNT_ADDR 0xd2801ff8
+
+#define CONFIG_HOSTNAME x600
+#define CONFIG_UBI_PART ubi0
+#define CONFIG_UBIFS_VOLUME rootfs
+
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define MTDIDS_DEFAULT "nand0=nand"
+#define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "u-boot_addr=1000000\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.spr\0" \
+ "load=tftp ${u-boot_addr} ${u-boot}\0" \
+ "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};"\
+ "erase " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
+ "cp.b ${u-boot_addr} " xstr(CONFIG_SYS_MONITOR_BASE) \
+ " ${filesize};" \
+ "protect on " xstr(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize}\0" \
+ "upd=run load update\0" \
+ "ubifs=" xstr(CONFIG_HOSTNAME) "/ubifs.img\0" \
+ "part=" xstr(CONFIG_UBI_PART) "\0" \
+ "vol=" xstr(CONFIG_UBIFS_VOLUME) "\0" \
+ "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
+ "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
+ " ${filesize}\0" \
+ "upd_ubifs=run load_ubifs update_ubifs\0" \
+ "init_ubifs=nand erase.part ubi0;ubi part ${part};" \
+ "ubi create ${vol} 4000000\0" \
+ "netdev=eth0\0" \
+ "rootpath=/opt/eldk-4.2/arm\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "boot_part=0\0" \
+ "altbootcmd=if test $boot_part -eq 0;then " \
+ "echo Switching to partition 1!;" \
+ "setenv boot_part 1;" \
+ "else; " \
+ "echo Switching to partition 0!;" \
+ "setenv boot_part 0;" \
+ "fi;" \
+ "saveenv;boot\0" \
+ "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \
+ "root=ubi0:rootfs rootfstype=ubifs\0" \
+ "kernel=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "kernel_fs=/boot/uImage \0" \
+ "kernel_addr=1000000\0" \
+ "dtb=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" \
+ "dtb_fs=/boot/" xstr(CONFIG_HOSTNAME) ".dtb\0" \
+ "dtb_addr=1800000\0" \
+ "load_kernel=tftp ${kernel_addr} ${kernel}\0" \
+ "load_dtb=tftp ${dtb_addr} ${dtb}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \
+ "${baudrate}\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "net_nfs=run load_dtb load_kernel; " \
+ "run nfsargs addip addcon addmtd addmisc;" \
+ "bootm ${kernel_addr} - ${dtb_addr}\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
+ " addcon addmisc addmtd;" \
+ "bootm ${kernel_addr} - ${dtb_addr}\0" \
+ "ubifs_mount=ubi part ubi${boot_part};ubifsmount rootfs\0" \
+ "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
+ "ubifsload ${dtb_addr} ${dtb_fs};\0" \
+ "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
+ "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \
+ "bootcmd=run nand_ubifs\0" \
+ "\0"
+
+/* Stack sizes */
+#define CONFIG_STACKSIZE (512 * 1024)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x00000000
+#define PHYS_SDRAM_1_MAXSIZE 0x40000000
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/*
+ * SPL related defines
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_TEXT_BASE 0xd2800b00
+#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
+
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
+#define CONFIG_SPL_NO_PRINTF
+
+/*
+ * Please select/define only one of the following
+ * Each definition corresponds to a supported DDR chip.
+ * DDR configuration is based on the following selection
+ */
+#define CONFIG_DDR_MT47H64M16 1
+#define CONFIG_DDR_MT47H32M16 0
+#define CONFIG_DDR_MT47H128M8 0
+
+/*
+ * Synchronous/Asynchronous operation of DDR
+ *
+ * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
+ * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
+ * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
+ */
+#define CONFIG_DDR_2HCLK 1
+#define CONFIG_DDR_HCLK 0
+#define CONFIG_DDR_PLL2 0
+
+/*
+ * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
+ * or not. Modify/Add to only these macros to define new boot types
+ */
+#define USB_BOOT_SUPPORTED 0
+#define PCIE_BOOT_SUPPORTED 0
+#define SNOR_BOOT_SUPPORTED 1
+#define NAND_BOOT_SUPPORTED 1
+#define PNOR_BOOT_SUPPORTED 0
+#define TFTP_BOOT_SUPPORTED 0
+#define UART_BOOT_SUPPORTED 0
+#define SPI_BOOT_SUPPORTED 0
+#define I2C_BOOT_SUPPORTED 0
+#define MMC_BOOT_SUPPORTED 0
+
+#endif /* __CONFIG_H */
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_BTUART 1 /* we use BTUART on XAENIAX */
-
+#define CONFIG_CONS_INDEX 4
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/* serial communication */
#ifdef XPAR_UARTLITE_0_BASEADDR
#define CONFIG_XILINX_UARTLITE
-#define CONFIG_SERIAL_BASE XPAR_UARTLITE_0_BASEADDR
+#define XILINX_UARTLITE_BASEADDR XPAR_UARTLITE_0_BASEADDR
#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE
#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
#else
* ff000000 - ffbfffff OS Use/Filesystem (12MB)
*/
-#define CONFIG_UBOOT_ENV_ADDR MK_STR(CONFIG_SYS_TEXT_BASE)
-#define CONFIG_FDT_ENV_ADDR MK_STR(0xfff00000)
-#define CONFIG_OS_ENV_ADDR MK_STR(0xffc00000)
+#define CONFIG_UBOOT_ENV_ADDR __stringify(CONFIG_SYS_TEXT_BASE)
+#define CONFIG_FDT_ENV_ADDR __stringify(0xfff00000)
+#define CONFIG_OS_ENV_ADDR __stringify(0xffc00000)
#define CONFIG_PROG_UBOOT \
"$download_cmd $loadaddr $ubootfile; " \
* f6f00000 - f7efffff Sec OS image (16MB)
* f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
*/
-#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff00000)
-#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f00000)
-#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfffc0000)
-#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7fc0000)
-#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
-#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
+#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
+#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
+#define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
+#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
+#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
#define CONFIG_PROG_UBOOT1 \
"$download_cmd $loadaddr $ubootfile; " \
* faf00000 - fbefffff Sec OS image (16MB)
* f8000000 - faefffff Sec OS Use/Filesystem (47MB)
*/
-#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
-#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xfbf80000)
-#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
-#define CONFIG_FDT2_ENV_ADDR MK_STR(0xfbf00000)
-#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
-#define CONFIG_OS2_ENV_ADDR MK_STR(0xfaf00000)
+#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000)
+#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000)
+#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000)
#define CONFIG_PROG_UBOOT1 \
"$download_cmd $loadaddr $ubootfile; " \
* f6f00000 - f7efffff Sec OS image (16MB)
* f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
*/
-#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
-#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000)
-#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
-#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000)
-#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
-#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
+#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
+#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
+#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
#define CONFIG_PROG_UBOOT1 \
"$download_cmd $loadaddr $ubootfile; " \
* f6f00000 - f7efffff Sec OS image (16MB)
* f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
*/
-#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
-#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000)
-#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
-#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000)
-#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
-#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
+#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
+#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
+#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
#define CONFIG_PROG_UBOOT1 \
"$download_cmd $loadaddr $ubootfile; " \
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
#define CONFIG_SYS_BASE_BAUD 691200
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_STUART 1
+#define CONFIG_CONS_INDEX 2
#define CONFIG_BAUDRATE 115200
/*
--- /dev/null
+/*
+ * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_ZYNQ_H
+#define __CONFIG_ZYNQ_H
+
+#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
+#define CONFIG_ZYNQ
+
+/* CPU clock */
+#define CONFIG_CPU_FREQ_HZ 800000000
+#define CONFIG_SYS_HZ 1000
+
+/* Ram */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_TEXT_BASE 0
+#define CONFIG_SYS_SDRAM_BASE 0
+#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CONFIG_BAUDRATE 115200
+
+/* XPSS Serial driver */
+#define CONFIG_ZYNQ_SERIAL
+#define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0001000
+#define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE
+#define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000
+
+/* SCU timer address is hardcoded */
+#define CONFIG_SCUTIMER_BASEADDR 0xF8F00600
+
+/* Ethernet driver */
+#define CONFIG_NET_MULTI
+#define CONFIG_ZYNQ_GEM
+#define CONFIG_ZYNQ_GEM_BASEADDR0 0xE000B000
+
+#define CONFIG_BOOTP_SERVERIP
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_MAY_FAIL
+
+/* MII and Phylib */
+#define CONFIG_MII
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MARVELL
+
+/* Environment */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x10000
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_MALLOC_LEN 0x400000
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_PROMPT "U-Boot> "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_SYS_LOAD_ADDR 0
+#define CONFIG_SYS_MAXARGS 15 /* max number of command args */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* OF */
+#define CONFIG_FIT
+#define CONFIG_OF_LIBFDT
+
+/* Commands */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+
+#endif /* __CONFIG_ZYNQ_H */
/* Superblock */
struct ext2_sblock *sb;
/* Block group descritpor table */
- struct ext2_block_group *gd;
+ struct ext2_block_group *bgd;
char *gdtable;
/* Block Bitmap Related */
#ifndef _IDE_H
#define _IDE_H
-#define IDE_BUS(dev) (dev >> 1)
+#define IDE_BUS(dev) (dev / (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS))
#define ATA_CURR_BASE(dev) (CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])
*/
void ide_init(void);
-ulong ide_read(int device, lbaint_t blknr, ulong blkcnt, void *buffer);
-ulong ide_write(int device, lbaint_t blknr, ulong blkcnt, const void *buffer);
+ulong ide_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer);
+ulong ide_write(int device, ulong blknr, lbaint_t blkcnt, const void *buffer);
#if defined(CONFIG_OF_IDE_FIXUP)
int ide_device_present(int dev);
int input_stdio_register(struct stdio_dev *dev);
/**
+ * Set up the keyboard autorepeat delays
+ *
+ * @param repeat_delay_ms Delay before key auto-repeat starts (in ms)
+ * @param repeat_rate_ms Delay between successive key repeats (in ms)
+ */
+void input_set_delays(struct input_config *config, int repeat_delay_ms,
+ int repeat_rate_ms);
+
+/**
* Set up the input handler with basic key maps.
*
* @param config Input state
* @param leds Initial LED value (INPUT_LED_ mask), 0 suggested
- * @param repeat_delay_ms Delay before key auto-repeat starts (in ms)
- * @param repeat_rate_ms Delay between successive key repeats (in ms)
* @return 0 if ok, -1 on error
*/
-int input_init(struct input_config *config, int leds, int repeat_delay_ms,
- int repeat_rate_ms);
+int input_init(struct input_config *config, int leds);
#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
extern int overwrite_console(void);
#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*< 16 YUV 4:2:2 */
int ipuv3_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt);
+void ipuv3_fb_shutdown(void);
#endif
const u8 *plain_keycode; /* key code for each row / column */
const u8 *fn_keycode; /* ...when Fn held down */
int fn_pos; /* position of Fn key in key (or -1) */
+ int ghost_filter; /* non-zero to enable ghost filter */
};
/* Information about a particular key (row, column pair) in the matrix */
* @param config Keyboard matrix config
* @param rows Number of rows in key matrix
* @param cols Number of columns in key matrix
+ * @param ghost_filter Non-zero to enable ghost filtering
* @return 0 if ok, -1 on error
*/
-int key_matrix_init(struct key_matrix *config, int rows, int cols);
+int key_matrix_init(struct key_matrix *config, int rows, int cols,
+ int ghost_filter);
#endif
--- /dev/null
+#ifndef __LINUX_STRINGIFY_H
+#define __LINUX_STRINGIFY_H
+
+/* Indirect stringification. Doing two levels allows the parameter to be a
+ * macro itself. For example, compile with -DFOO=bar, __stringify(FOO)
+ * converts to "bar".
+ */
+
+#define __stringify_1(x...) #x
+#define __stringify(x...) __stringify_1(x)
+
+#endif /* !__LINUX_STRINGIFY_H */
#ifndef __NIOS2_H__
#define __NIOS2_H__
+#include <linux/stringify.h>
+
/*------------------------------------------------------------------------
* Control registers -- use with wrctl() & rdctl()
*----------------------------------------------------------------------*/
/*------------------------------------------------------------------------
* Access to control regs
*----------------------------------------------------------------------*/
-#define _str_(x) #x
#define rdctl(reg)\
({unsigned int val;\
- asm volatile( "rdctl %0, ctl" _str_(reg)\
+ asm volatile("rdctl %0, ctl" __stringify(reg) \
: "=r" (val) ); val;})
#define wrctl(reg,val)\
#ifndef __SATA_H__
#define __SATA_H__
+#include <part.h>
int init_sata(int dev);
int scan_sata(int dev);
-ulong sata_read(int dev, ulong blknr, ulong blkcnt, void *buffer);
-ulong sata_write(int dev, ulong blknr, ulong blkcnt, const void *buffer);
+ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer);
+ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer);
int sata_initialize(void);
int __sata_initialize(void);
+extern block_dev_desc_t sata_dev_desc[];
+
#endif
struct serial_device {
/* enough bytes to match alignment of following func pointer */
- char name[16];
-
- int (*init) (void);
- int (*uninit) (void);
- void (*setbrg) (void);
- int (*getc) (void);
- int (*tstc) (void);
- void (*putc) (const char c);
- void (*puts) (const char *s);
+ char name[16];
+
+ int (*start)(void);
+ int (*stop)(void);
+ void (*setbrg)(void);
+ int (*getc)(void);
+ int (*tstc)(void);
+ void (*putc)(const char c);
+ void (*puts)(const char *s);
#if CONFIG_POST & CONFIG_SYS_POST_UART
- void (*loop) (int);
+ void (*loop)(int);
#endif
-
- struct serial_device *next;
+ struct serial_device *next;
};
extern struct serial_device serial_smc_device;
defined(CONFIG_MICROBLAZE)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
-#if defined(CONFIG_SYS_NS16550_SERIAL)
-extern struct serial_device eserial1_device;
-extern struct serial_device eserial2_device;
-extern struct serial_device eserial3_device;
-extern struct serial_device eserial4_device;
-#endif /* CONFIG_SYS_NS16550_SERIAL */
-
-#endif
-
-#if defined(CONFIG_MPC512X)
-extern struct serial_device serial1_device;
-extern struct serial_device serial3_device;
-extern struct serial_device serial4_device;
-extern struct serial_device serial6_device;
-#endif
-
-#if defined(CONFIG_XILINX_UARTLITE)
-extern struct serial_device uartlite_serial0_device;
-extern struct serial_device uartlite_serial1_device;
-extern struct serial_device uartlite_serial2_device;
-extern struct serial_device uartlite_serial3_device;
#endif
-#if defined(CONFIG_S3C2410)
-extern struct serial_device s3c24xx_serial0_device;
-extern struct serial_device s3c24xx_serial1_device;
-extern struct serial_device s3c24xx_serial2_device;
-#endif
-
-#if defined(CONFIG_S5P)
-extern struct serial_device s5p_serial0_device;
-extern struct serial_device s5p_serial1_device;
-extern struct serial_device s5p_serial2_device;
-extern struct serial_device s5p_serial3_device;
-#endif
-
-#if defined(CONFIG_OMAP3_ZOOM2)
-extern struct serial_device zoom2_serial_device0;
-extern struct serial_device zoom2_serial_device1;
-extern struct serial_device zoom2_serial_device2;
-extern struct serial_device zoom2_serial_device3;
-#endif
-
-extern struct serial_device serial_ffuart_device;
-extern struct serial_device serial_btuart_device;
-extern struct serial_device serial_stuart_device;
-
-#if defined(CONFIG_SYS_BFIN_UART)
-extern void serial_register_bfin_uart(void);
-extern struct serial_device bfin_serial0_device;
-extern struct serial_device bfin_serial1_device;
-extern struct serial_device bfin_serial2_device;
-extern struct serial_device bfin_serial3_device;
-#endif
+extern struct serial_device eserial1_device;
+extern struct serial_device eserial2_device;
extern void serial_register(struct serial_device *);
extern void serial_initialize(void);
#endif /* CONFIG_USB_TTY */
-#if defined(CONFIG_MPC512X) && defined(CONFIG_SERIAL_MULTI)
+#if defined(CONFIG_MPC512X)
extern struct stdio_dev *open_port(int num, int baudrate);
extern int close_port(int num);
extern int write_port(struct stdio_dev *port, char *buf);
};
#endif /* CONFIG_SH3 */
-#if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
+#if defined(CONFIG_SH4) || defined(CONFIG_SH4A) || defined(CONFIG_RMOBILE)
struct tmu_regs {
u32 reserved;
u8 tstr;
/* SPI SPL functions */
void spl_spi_load_image(void);
+/* Ethernet SPL functions */
+void spl_net_load_image(const char *device);
+
#ifdef CONFIG_SPL_BOARD_INIT
void spl_board_init(void);
#endif
int portnr;
struct usb_device *parent;
struct usb_device *children[USB_MAXCHILDREN];
+
+ void *controller; /* hardware controller private data */
};
/**********************************************************************
defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \
defined(CONFIG_USB_BLACKFIN) || defined(CONFIG_USB_AM35X)
-int usb_lowlevel_init(void);
-int usb_lowlevel_stop(void);
+int usb_lowlevel_init(int index, void **controller);
+int usb_lowlevel_stop(int index);
+
int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
void *buffer, int transfer_len);
int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
#define USB_UHCI_VEND_ID 0x8086
#define USB_UHCI_DEV_ID 0x7112
+/*
+ * PXA25x can only act as USB device. There are drivers
+ * which works with USB CDC gadgets implementations.
+ * Some of them have common routines which can be used
+ * in boards init functions e.g. udc_disconnect() used for
+ * forced device disconnection from host.
+ */
+#elif defined(CONFIG_USB_GADGET_PXA2XX)
+
+extern void udc_disconnect(void);
+
#else
#error USB Lowlevel not defined
#endif
int hub_port_reset(struct usb_device *dev, int port,
unsigned short *portstat);
-struct usb_device *usb_alloc_new_device(void);
+struct usb_device *usb_alloc_new_device(void *controller);
+
int usb_new_device(struct usb_device *dev);
#endif /*_USB_H_ */
#define INFO_BUFFER_ERROR (1 << 5)
#define INFO_TX_ERROR (1 << 3)
-extern int usb_lowlevel_init(void);
+extern int usb_lowlevel_init(int index, void **controller);
#endif /* __MV_UDC_H__ */
*
* returns 0 on success, ULPI_ERROR on failure.
*/
-int ulpi_set_vbus(struct ulpi_viewport *ulpi_vp,
- int on, int ext_power, int ext_ind);
+int ulpi_set_vbus(struct ulpi_viewport *ulpi_vp, int on, int ext_power);
+
+/*
+ * Configure VBUS indicator
+ * @external - external VBUS over-current indicator is used
+ * @passthru - disables ANDing of internal VBUS comparator
+ * with external VBUS input
+ * @complement - inverts the external VBUS input
+ */
+int ulpi_set_vbus_indicator(struct ulpi_viewport *ulpi_vp, int external,
+ int passthru, int complement);
/*
* Enable/disable pull-down resistors on D+ and D- USB lines.
#ifndef CONFIG_SYS_VXWORKS_BOOT_DEVICE
#if defined(CONFIG_4xx)
#define CONFIG_SYS_VXWORKS_BOOT_DEVICE "emac(0,0)"
-#elif defined(CONFIG_IOP480)
-#define CONFIG_SYS_VXWORKS_BOOT_DEVICE "dc(0,0)"
#else
#define CONFIG_SYS_VXWORKS_BOOT_DEVICE "eth(0,0)"
#endif
COBJS-$(CONFIG_SHA256) += sha256.o
COBJS-y += strmhz.o
COBJS-$(CONFIG_RBTREE) += rbtree.o
-else
-COBJS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += display_options.o
endif
ifdef CONFIG_SPL_BUILD
COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o
+COBJS-$(CONFIG_SPL_NET_SUPPORT) += crc32.o
+ifneq ($(CONFIG_SPL_SPI_FLASH_SUPPORT)$(CONFIG_SPL_NET_SUPPORT),)
+COBJS-y += display_options.o
+endif
+COBJS-$(CONFIG_SPL_NET_SUPPORT) += errno.o
+COBJS-$(CONFIG_SPL_NET_SUPPORT) += hashtable.o
+COBJS-$(CONFIG_SPL_NET_SUPPORT) += net_utils.o
endif
COBJS-y += crc32.o
COBJS-y += ctype.o
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+# SEE README.arm-unaligned-accesses
+$(obj)bzlib.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
+
#########################################################################
# defines $(obj).depend target
* hexport()
*/
+#ifndef CONFIG_SPL_BUILD
/*
* Export the data stored in the hash table in linearized form.
*
return size;
}
+#endif
/*
#include <errno.h>
#include <common.h>
-#if !defined (CONFIG_PANIC_HANG)
+#if !defined(CONFIG_PANIC_HANG)
#include <command.h>
#endif
#include <div64.h>
-# define NUM_TYPE long long
#define noinline __attribute__((noinline))
/* some reluctance to put this into a new limits.h, so it is here */
return buf;
}
-unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base)
+unsigned long simple_strtoul(const char *cp, char **endp,
+ unsigned int base)
{
- unsigned long result = 0,value;
+ unsigned long result = 0;
+ unsigned long value;
if (*cp == '0') {
cp++;
base = 16;
cp++;
}
- if (!base) {
+
+ if (!base)
base = 8;
- }
}
- if (!base) {
+
+ if (!base)
base = 10;
- }
+
while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp)
? toupper(*cp) : *cp)-'A'+10) < base) {
result = result*base + value;
cp++;
}
+
if (endp)
*endp = (char *)cp;
+
return result;
}
return -EINVAL;
}
-long simple_strtol(const char *cp,char **endp,unsigned int base)
+long simple_strtol(const char *cp, char **endp, unsigned int base)
{
- if(*cp=='-')
- return -simple_strtoul(cp+1,endp,base);
- return simple_strtoul(cp,endp,base);
+ if (*cp == '-')
+ return -simple_strtoul(cp + 1, endp, base);
+
+ return simple_strtoul(cp, endp, base);
}
int ustrtoul(const char *cp, char **endp, unsigned int base)
{
unsigned long result = simple_strtoul(cp, endp, base);
switch (**endp) {
- case 'G' :
+ case 'G':
result *= 1024;
/* fall through */
case 'M':
return result;
}
-unsigned long long simple_strtoull (const char *cp, char **endp, unsigned int base)
+unsigned long long simple_strtoull(const char *cp, char **endp,
+ unsigned int base)
{
unsigned long long result = 0, value;
if (*cp == '0') {
cp++;
- if ((*cp == 'x') && isxdigit (cp[1])) {
+ if ((*cp == 'x') && isxdigit(cp[1])) {
base = 16;
cp++;
}
- if (!base) {
+
+ if (!base)
base = 8;
- }
}
- if (!base) {
+
+ if (!base)
base = 10;
- }
- while (isxdigit (*cp) && (value = isdigit (*cp)
- ? *cp - '0'
- : (islower (*cp) ? toupper (*cp) : *cp) - 'A' + 10) < base) {
+
+ while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp - '0'
+ : (islower(*cp) ? toupper(*cp) : *cp) - 'A' + 10) < base) {
result = result * base + value;
cp++;
}
+
if (endp)
*endp = (char *) cp;
+
return result;
}
static int skip_atoi(const char **s)
{
- int i=0;
+ int i = 0;
while (is_digit(**s))
- i = i*10 + *((*s)++) - '0';
+ i = i * 10 + *((*s)++) - '0';
+
return i;
}
/* Formats correctly any integer in [0,99999].
* Outputs from one to five digits depending on input.
* On i386 gcc 4.1.2 -O2: ~250 bytes of code. */
-static char* put_dec_trunc(char *buf, unsigned q)
+static char *put_dec_trunc(char *buf, unsigned q)
{
unsigned d3, d2, d1, d0;
d1 = (q>>4) & 0xf;
d3 = d3 - 10*q;
*buf++ = d3 + '0'; /* next digit */
if (q != 0)
- *buf++ = q + '0'; /* most sign. digit */
+ *buf++ = q + '0'; /* most sign. digit */
}
}
}
return buf;
}
/* Same with if's removed. Always emits five digits */
-static char* put_dec_full(char *buf, unsigned q)
+static char *put_dec_full(char *buf, unsigned q)
{
/* BTW, if q is in [0,9999], 8-bit ints will be enough, */
/* but anyway, gcc produces better code with full-sized ints */
return buf;
}
/* No inlining helps gcc to use registers better */
-static noinline char* put_dec(char *buf, unsigned NUM_TYPE num)
+static noinline char *put_dec(char *buf, u64 num)
{
while (1) {
unsigned rem;
#define ADDCH(str, ch) (*(str)++ = (ch))
#endif
-static char *number(char *buf, char *end, unsigned NUM_TYPE num,
+static char *number(char *buf, char *end, u64 num,
int base, int size, int precision, int type)
{
/* we are called with base 8, 10 or 16, only, thus don't need "G..." */
- static const char digits[16] = "0123456789ABCDEF"; /* "GHIJKLMNOPQRSTUVWXYZ"; */
+ static const char digits[16] = "0123456789ABCDEF";
char tmp[66];
char sign;
type &= ~ZEROPAD;
sign = 0;
if (type & SIGN) {
- if ((signed NUM_TYPE) num < 0) {
+ if ((s64) num < 0) {
sign = '-';
- num = - (signed NUM_TYPE) num;
+ num = -(s64) num;
size--;
} else if (type & PLUS) {
sign = '+';
else if (base != 10) { /* 8 or 16 */
int mask = base - 1;
int shift = 3;
- if (base == 16) shift = 4;
+
+ if (base == 16)
+ shift = 4;
+
do {
- tmp[i++] = (digits[((unsigned char)num) & mask] | locase);
+ tmp[i++] = (digits[((unsigned char)num) & mask]
+ | locase);
num >>= shift;
} while (num);
} else { /* base 10 */
static char *mac_address_string(char *buf, char *end, u8 *addr, int field_width,
int precision, int flags)
{
- char mac_addr[6 * 3]; /* (6 * 2 hex digits), 5 colons and trailing zero */
+ /* (6 * 2 hex digits), 5 colons and trailing zero */
+ char mac_addr[6 * 3];
char *p = mac_addr;
int i;
static char *ip6_addr_string(char *buf, char *end, u8 *addr, int field_width,
int precision, int flags)
{
- char ip6_addr[8 * 5]; /* (8 * 4 hex digits), 7 colons and trailing zero */
+ /* (8 * 4 hex digits), 7 colons and trailing zero */
+ char ip6_addr[8 * 5];
char *p = ip6_addr;
int i;
static char *ip4_addr_string(char *buf, char *end, u8 *addr, int field_width,
int precision, int flags)
{
- char ip4_addr[4 * 4]; /* (4 * 3 decimal digits), 3 dots and trailing zero */
+ /* (4 * 3 decimal digits), 3 dots and trailing zero */
+ char ip4_addr[4 * 4];
char temp[3]; /* hold each IP quad in reverse order */
char *p = ip4_addr;
int i, digits;
static int vsnprintf_internal(char *buf, size_t size, const char *fmt,
va_list args)
{
- unsigned NUM_TYPE num;
+ u64 num;
int base;
char *str;
/* process flags */
flags = 0;
- repeat:
+repeat:
++fmt; /* this also skips first '%' */
switch (*fmt) {
- case '-': flags |= LEFT; goto repeat;
- case '+': flags |= PLUS; goto repeat;
- case ' ': flags |= SPACE; goto repeat;
- case '#': flags |= SPECIAL; goto repeat;
- case '0': flags |= ZEROPAD; goto repeat;
+ case '-':
+ flags |= LEFT;
+ goto repeat;
+ case '+':
+ flags |= PLUS;
+ goto repeat;
+ case ' ':
+ flags |= SPACE;
+ goto repeat;
+ case '#':
+ flags |= SPECIAL;
+ goto repeat;
+ case '0':
+ flags |= ZEROPAD;
+ goto repeat;
}
/* get field width */
continue;
case 'p':
- str = pointer(fmt+1, str, end,
+ str = pointer(fmt + 1, str, end,
va_arg(args, void *),
field_width, precision, flags);
/* Skip all alphanumeric pointer suffixes */
case 'n':
if (qualifier == 'l') {
- long * ip = va_arg(args, long *);
+ long *ip = va_arg(args, long *);
*ip = (str - buf);
} else {
- int * ip = va_arg(args, int *);
+ int *ip = va_arg(args, int *);
*ip = (str - buf);
}
continue;
*str = '\0';
#endif
/* the trailing null byte doesn't count towards the total */
- return str-buf;
+ return str - buf;
}
#ifdef CONFIG_SYS_VSNPRINTF
return vsnprintf_internal(buf, INT_MAX, fmt, args);
}
-int sprintf(char * buf, const char *fmt, ...)
+int sprintf(char *buf, const char *fmt, ...)
{
va_list args;
int i;
va_start(args, fmt);
- i=vsprintf(buf,fmt,args);
+ i = vsprintf(buf, fmt, args);
va_end(args);
return i;
}
void panic(const char *fmt, ...)
{
- va_list args;
+ va_list args;
va_start(args, fmt);
vprintf(fmt, args);
putc('\n');
va_end(args);
-#if defined (CONFIG_PANIC_HANG)
+#if defined(CONFIG_PANIC_HANG)
hang();
#else
- udelay (100000); /* allow messages to go out */
- do_reset (NULL, 0, 0, NULL);
+ udelay(100000); /* allow messages to go out */
+ do_reset(NULL, 0, 0, NULL);
#endif
while (1)
;
#include <configs/${CONFIG_NAME}.h>
#include <asm/config.h>
#include <config_fallbacks.h>
+#include <config_uncmd_spl.h>
EOF
exit 0
}
}
+#define put_vci(e, str) \
+ do { \
+ size_t vci_strlen = strlen(str); \
+ *e++ = 60; /* Vendor Class Identifier */ \
+ *e++ = vci_strlen; \
+ memcpy(e, str, vci_strlen); \
+ e += vci_strlen; \
+ } while (0)
+
/*
* Initialize BOOTP extension fields in the request.
*/
u8 *cnt;
#if defined(CONFIG_BOOTP_PXE)
char *uuid;
- size_t vci_strlen;
u16 clientarch;
#endif
printf("Invalid pxeuuid: %s\n", uuid);
}
}
+#endif
- *e++ = 60; /* Vendor Class Identifier */
- vci_strlen = strlen(CONFIG_BOOTP_VCI_STRING);
- *e++ = vci_strlen;
- memcpy(e, CONFIG_BOOTP_VCI_STRING, vci_strlen);
- e += vci_strlen;
+#ifdef CONFIG_BOOTP_VCI_STRING
+ put_vci(e, CONFIG_BOOTP_VCI_STRING);
#endif
#if defined(CONFIG_BOOTP_VENDOREX)
*e++ = (576 - 312 + OPT_FIELD_SIZE) & 0xff;
#endif
+#if defined(CONFIG_BOOTP_VCI_STRING) || \
+ (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_NET_VCI_STRING))
+#ifdef CONFIG_SPL_BUILD
+ put_vci(e, CONFIG_SPL_NET_VCI_STRING);
+#else
+ put_vci(e, CONFIG_BOOTP_VCI_STRING);
+#endif
+#endif
+
#if defined(CONFIG_BOOTP_SUBNETMASK)
*e++ = 1; /* Subnet mask request */
*e++ = 4;
#ifdef CONFIG_NETCONSOLE
nc_input_packet((uchar *)ip + IP_UDP_HDR_SIZE,
- ntohl(ip->ip_src),
+ src_ip,
ntohs(ip->udp_dst),
ntohs(ip->udp_src),
ntohs(ip->udp_len) - UDP_HDR_SIZE);
#include <post.h>
#include <serial.h>
-#if defined(CONFIG_SERIAL_MULTI)
-
/*
* Actually the termination sequence of the coprocessor
* commands is "\r\n" (CR LF), but here we use a side effect of
return 0;
}
-#endif /* CONFIG_SERIAL_MULTI */
LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o
LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o
LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/memory.o
+LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/libnet.o
+LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o
+LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
ifeq ($(SOC),tegra20)
LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
+LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
+LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o
endif
# Add GCC lib
/env/fw_printenv
/gdb/gdbcont
/gdb/gdbsend
+/kernel-doc/docproc
# MA 02111-1307 USA
#
-TOOLSUBDIRS =
+TOOLSUBDIRS = kernel-doc
#
# Include this after HOSTOS HOSTARCH check
--- /dev/null
+#!/bin/sh
+#
+# binutils-version [-p] gas-command
+#
+# Prints the binutils version of `gas-command' in a canonical 4-digit form
+# such as `0222' for binutils 2.22
+#
+
+gas="$*"
+
+if [ ${#gas} -eq 0 ]; then
+ echo "Error: No assembler specified."
+ printf "Usage:\n\t$0 <gas-command>\n"
+ exit 1
+fi
+
+MAJOR=$($gas --version | head -1 | awk '{print $NF}' | cut -d . -f 1)
+MINOR=$($gas --version | head -1 | awk '{print $NF}' | cut -d . -f 2)
+
+printf "%02d%02d\\n" $MAJOR $MINOR
--- /dev/null
+#!/usr/bin/perl -w
+#
+# Clean a patch file -- or directory of patch files -- of stealth whitespace.
+# WARNING: this can be a highly destructive operation. Use with caution.
+#
+
+use bytes;
+use File::Basename;
+
+# Default options
+$max_width = 79;
+
+# Clean up space-tab sequences, either by removing spaces or
+# replacing them with tabs.
+sub clean_space_tabs($)
+{
+ no bytes; # Tab alignment depends on characters
+
+ my($li) = @_;
+ my($lo) = '';
+ my $pos = 0;
+ my $nsp = 0;
+ my($i, $c);
+
+ for ($i = 0; $i < length($li); $i++) {
+ $c = substr($li, $i, 1);
+ if ($c eq "\t") {
+ my $npos = ($pos+$nsp+8) & ~7;
+ my $ntab = ($npos >> 3) - ($pos >> 3);
+ $lo .= "\t" x $ntab;
+ $pos = $npos;
+ $nsp = 0;
+ } elsif ($c eq "\n" || $c eq "\r") {
+ $lo .= " " x $nsp;
+ $pos += $nsp;
+ $nsp = 0;
+ $lo .= $c;
+ $pos = 0;
+ } elsif ($c eq " ") {
+ $nsp++;
+ } else {
+ $lo .= " " x $nsp;
+ $pos += $nsp;
+ $nsp = 0;
+ $lo .= $c;
+ $pos++;
+ }
+ }
+ $lo .= " " x $nsp;
+ return $lo;
+}
+
+# Compute the visual width of a string
+sub strwidth($) {
+ no bytes; # Tab alignment depends on characters
+
+ my($li) = @_;
+ my($c, $i);
+ my $pos = 0;
+ my $mlen = 0;
+
+ for ($i = 0; $i < length($li); $i++) {
+ $c = substr($li,$i,1);
+ if ($c eq "\t") {
+ $pos = ($pos+8) & ~7;
+ } elsif ($c eq "\n") {
+ $mlen = $pos if ($pos > $mlen);
+ $pos = 0;
+ } else {
+ $pos++;
+ }
+ }
+
+ $mlen = $pos if ($pos > $mlen);
+ return $mlen;
+}
+
+$name = basename($0);
+
+@files = ();
+
+while (defined($a = shift(@ARGV))) {
+ if ($a =~ /^-/) {
+ if ($a eq '-width' || $a eq '-w') {
+ $max_width = shift(@ARGV)+0;
+ } else {
+ print STDERR "Usage: $name [-width #] files...\n";
+ exit 1;
+ }
+ } else {
+ push(@files, $a);
+ }
+}
+
+foreach $f ( @files ) {
+ print STDERR "$name: $f\n";
+
+ if (! -f $f) {
+ print STDERR "$f: not a file\n";
+ next;
+ }
+
+ if (!open(FILE, '+<', $f)) {
+ print STDERR "$name: Cannot open file: $f: $!\n";
+ next;
+ }
+
+ binmode FILE;
+
+ # First, verify that it is not a binary file; consider any file
+ # with a zero byte to be a binary file. Is there any better, or
+ # additional, heuristic that should be applied?
+ $is_binary = 0;
+
+ while (read(FILE, $data, 65536) > 0) {
+ if ($data =~ /\0/) {
+ $is_binary = 1;
+ last;
+ }
+ }
+
+ if ($is_binary) {
+ print STDERR "$name: $f: binary file\n";
+ next;
+ }
+
+ seek(FILE, 0, 0);
+
+ $in_bytes = 0;
+ $out_bytes = 0;
+ $lineno = 0;
+
+ @lines = ();
+
+ $in_hunk = 0;
+ $err = 0;
+
+ while ( defined($line = <FILE>) ) {
+ $lineno++;
+ $in_bytes += length($line);
+
+ if (!$in_hunk) {
+ if ($line =~
+ /^\@\@\s+\-([0-9]+),([0-9]+)\s+\+([0-9]+),([0-9]+)\s\@\@/) {
+ $minus_lines = $2;
+ $plus_lines = $4;
+ if ($minus_lines || $plus_lines) {
+ $in_hunk = 1;
+ @hunk_lines = ($line);
+ }
+ } else {
+ push(@lines, $line);
+ $out_bytes += length($line);
+ }
+ } else {
+ # We're in a hunk
+
+ if ($line =~ /^\+/) {
+ $plus_lines--;
+
+ $text = substr($line, 1);
+ $text =~ s/[ \t\r]*$//; # Remove trailing spaces
+ $text = clean_space_tabs($text);
+
+ $l_width = strwidth($text);
+ if ($max_width && $l_width > $max_width) {
+ print STDERR
+ "$f:$lineno: adds line exceeds $max_width ",
+ "characters ($l_width)\n";
+ }
+
+ push(@hunk_lines, '+'.$text);
+ } elsif ($line =~ /^\-/) {
+ $minus_lines--;
+ push(@hunk_lines, $line);
+ } elsif ($line =~ /^ /) {
+ $plus_lines--;
+ $minus_lines--;
+ push(@hunk_lines, $line);
+ } else {
+ print STDERR "$name: $f: malformed patch\n";
+ $err = 1;
+ last;
+ }
+
+ if ($plus_lines < 0 || $minus_lines < 0) {
+ print STDERR "$name: $f: malformed patch\n";
+ $err = 1;
+ last;
+ } elsif ($plus_lines == 0 && $minus_lines == 0) {
+ # End of a hunk. Process this hunk.
+ my $i;
+ my $l;
+ my @h = ();
+ my $adj = 0;
+ my $done = 0;
+
+ for ($i = scalar(@hunk_lines)-1; $i > 0; $i--) {
+ $l = $hunk_lines[$i];
+ if (!$done && $l eq "+\n") {
+ $adj++; # Skip this line
+ } elsif ($l =~ /^[ +]/) {
+ $done = 1;
+ unshift(@h, $l);
+ } else {
+ unshift(@h, $l);
+ }
+ }
+
+ $l = $hunk_lines[0]; # Hunk header
+ undef @hunk_lines; # Free memory
+
+ if ($adj) {
+ die unless
+ ($l =~ /^\@\@\s+\-([0-9]+),([0-9]+)\s+\+([0-9]+),([0-9]+)\s\@\@(.*)$/);
+ my $mstart = $1;
+ my $mlin = $2;
+ my $pstart = $3;
+ my $plin = $4;
+ my $tail = $5; # doesn't include the final newline
+
+ $l = sprintf("@@ -%d,%d +%d,%d @@%s\n",
+ $mstart, $mlin, $pstart, $plin-$adj,
+ $tail);
+ }
+ unshift(@h, $l);
+
+ # Transfer to the output array
+ foreach $l (@h) {
+ $out_bytes += length($l);
+ push(@lines, $l);
+ }
+
+ $in_hunk = 0;
+ }
+ }
+ }
+
+ if ($in_hunk) {
+ print STDERR "$name: $f: malformed patch\n";
+ $err = 1;
+ }
+
+ if (!$err) {
+ if ($in_bytes != $out_bytes) {
+ # Only write to the file if changed
+ seek(FILE, 0, 0);
+ print FILE @lines;
+
+ if ( !defined($where = tell(FILE)) ||
+ !truncate(FILE, $where) ) {
+ die "$name: Failed to truncate modified file: $f: $!\n";
+ }
+ }
+ }
+
+ close(FILE);
+}
include $(TOPDIR)/config.mk
HOSTSRCS := $(SRCTREE)/lib/crc32.c fw_env.c fw_env_main.c
-HEADERS := fw_env.h
+HEADERS := fw_env.h $(OBJTREE)/include/config.h
# Compile for a hosted environment on the target
HOSTCPPFLAGS = -idirafter $(SRCTREE)/include \
-idirafter $(OBJTREE)/include2 \
-idirafter $(OBJTREE)/include \
- -DUSE_HOSTCC
+ -DUSE_HOSTCC \
+ -DTEXT_BASE=$(TEXT_BASE)
ifeq ($(MTD_VERSION),old)
HOSTCPPFLAGS += -DMTD_OLD
DEVICEx_ENVSECTORS defines the number of sectors that may be used for
this environment instance. On NAND this is used to limit the range
within which bad blocks are skipped, on NOR it is not used.
+
+To prevent losing changes to the environment and to prevent confusing the MTD
+drivers, a lock file at /var/lock/fw_printenv.lock is used to serialize access
+to the environment.
#include <errno.h>
#include <fcntl.h>
+#include <linux/stringify.h>
#include <stdio.h>
#include <stdlib.h>
#include <stddef.h>
#include "fw_env.h"
-#include <config.h>
-
#define WHITESPACE(c) ((c == '\t') || (c == ' '))
#define min(x, y) ({ \
#define ENVSECTORS(i) envdevices[(i)].env_sectors
#define DEVTYPE(i) envdevices[(i)].mtd_type
-#define CONFIG_ENV_SIZE ENVSIZE(dev_current)
+#define CUR_ENVSIZE ENVSIZE(dev_current)
#define ENV_SIZE getenvsize()
static unsigned char obsolete_flag = 0;
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
static char default_environment[] = {
#if defined(CONFIG_BOOTARGS)
"bootargs=" CONFIG_BOOTARGS "\0"
"nfsboot=" CONFIG_NFSBOOTCOMMAND "\0"
#endif
#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
- "bootdelay=" MK_STR (CONFIG_BOOTDELAY) "\0"
+ "bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0"
#endif
#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
- "baudrate=" MK_STR (CONFIG_BAUDRATE) "\0"
+ "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"
#endif
#ifdef CONFIG_LOADS_ECHO
- "loads_echo=" MK_STR (CONFIG_LOADS_ECHO) "\0"
+ "loads_echo=" __stringify(CONFIG_LOADS_ECHO) "\0"
#endif
#ifdef CONFIG_ETHADDR
- "ethaddr=" MK_STR (CONFIG_ETHADDR) "\0"
+ "ethaddr=" __stringify(CONFIG_ETHADDR) "\0"
#endif
#ifdef CONFIG_ETH1ADDR
- "eth1addr=" MK_STR (CONFIG_ETH1ADDR) "\0"
+ "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"
#endif
#ifdef CONFIG_ETH2ADDR
- "eth2addr=" MK_STR (CONFIG_ETH2ADDR) "\0"
+ "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"
#endif
#ifdef CONFIG_ETH3ADDR
- "eth3addr=" MK_STR (CONFIG_ETH3ADDR) "\0"
+ "eth3addr=" __stringify(CONFIG_ETH3ADDR) "\0"
#endif
#ifdef CONFIG_ETH4ADDR
- "eth4addr=" MK_STR (CONFIG_ETH4ADDR) "\0"
+ "eth4addr=" __stringify(CONFIG_ETH4ADDR) "\0"
#endif
#ifdef CONFIG_ETH5ADDR
- "eth5addr=" MK_STR (CONFIG_ETH5ADDR) "\0"
+ "eth5addr=" __stringify(CONFIG_ETH5ADDR) "\0"
#endif
#ifdef CONFIG_ETHPRIME
"ethprime=" CONFIG_ETHPRIME "\0"
#endif
#ifdef CONFIG_IPADDR
- "ipaddr=" MK_STR (CONFIG_IPADDR) "\0"
+ "ipaddr=" __stringify(CONFIG_IPADDR) "\0"
#endif
#ifdef CONFIG_SERVERIP
- "serverip=" MK_STR (CONFIG_SERVERIP) "\0"
+ "serverip=" __stringify(CONFIG_SERVERIP) "\0"
#endif
#ifdef CONFIG_SYS_AUTOLOAD
"autoload=" CONFIG_SYS_AUTOLOAD "\0"
"rootpath=" CONFIG_ROOTPATH "\0"
#endif
#ifdef CONFIG_GATEWAYIP
- "gatewayip=" MK_STR (CONFIG_GATEWAYIP) "\0"
+ "gatewayip=" __stringify(CONFIG_GATEWAYIP) "\0"
#endif
#ifdef CONFIG_NETMASK
- "netmask=" MK_STR (CONFIG_NETMASK) "\0"
+ "netmask=" __stringify(CONFIG_NETMASK) "\0"
#endif
#ifdef CONFIG_HOSTNAME
- "hostname=" MK_STR (CONFIG_HOSTNAME) "\0"
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0"
#endif
#ifdef CONFIG_BOOTFILE
"bootfile=" CONFIG_BOOTFILE "\0"
#endif
#ifdef CONFIG_LOADADDR
- "loadaddr=" MK_STR (CONFIG_LOADADDR) "\0"
+ "loadaddr=" __stringify(CONFIG_LOADADDR) "\0"
#endif
#ifdef CONFIG_PREBOOT
"preboot=" CONFIG_PREBOOT "\0"
"clocks_in_mhz=" "1" "\0"
#endif
#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
- "pcidelay=" MK_STR (CONFIG_PCI_BOOTDELAY) "\0"
+ "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY) "\0"
#endif
#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG
"arch=" CONFIG_SYS_ARCH "\0"
#endif
static inline ulong getenvsize (void)
{
- ulong rc = CONFIG_ENV_SIZE - sizeof (long);
+ ulong rc = CUR_ENVSIZE - sizeof(long);
if (HaveRedundEnv)
rc -= sizeof (char);
{
char *env, *nxt;
- if (fw_env_open())
- return NULL;
-
for (env = environment.data; *env; env = nxt + 1) {
char *val;
(strcmp(name, "serial#") == 0) ||
((strcmp(name, "ethaddr") == 0)
#if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR)
- && (strcmp(oldval, MK_STR(CONFIG_ETHADDR)) != 0)
+ && (strcmp(oldval, __stringify(CONFIG_ETHADDR)) != 0)
#endif /* CONFIG_OVERWRITE_ETHADDR_ONCE && CONFIG_ETHADDR */
) ) {
fprintf (stderr, "Can't overwrite \"%s\"\n", name);
++env;
/*
* Overflow when:
- * "name" + "=" + "val" +"\0\0" > CONFIG_ENV_SIZE - (env-environment)
+ * "name" + "=" + "val" +"\0\0" > CUR_ENVSIZE - (env-environment)
*/
len = strlen (name) + 2;
/* add '=' for first arg, ' ' for all others */
int i, len;
char *name;
char *value = NULL;
- char *tmpval = NULL;
if (argc < 2) {
errno = EINVAL;
name = argv[1];
- len = strlen(name) + 2;
- for (i = 2; i < argc; ++i)
- len += strlen(argv[i]) + 1;
-
- /* Allocate enough place to the data string */
+ len = 0;
for (i = 2; i < argc; ++i) {
char *val = argv[i];
+ size_t val_len = strlen(val);
+
+ value = realloc(value, len + val_len + 1);
if (!value) {
- value = (char *)malloc(len - strlen(name));
- if (!value) {
- fprintf(stderr,
+ fprintf(stderr,
"Cannot malloc %zu bytes: %s\n",
- len - strlen(name), strerror(errno));
- return -1;
- }
- memset(value, 0, len - strlen(name));
- tmpval = value;
+ len, strerror(errno));
+ return -1;
}
- if (i != 2)
- *tmpval++ = ' ';
- while (*val != '\0')
- *tmpval++ = *val++;
+
+ memcpy(value + len, val, val_len);
+ len += val_len;
+ value[len++] = ' ';
}
+ value[len - 1] = '\0';
fw_env_write(name, value);
- if (value)
- free(value);
+ free(value);
return fw_env_close();
}
printf ("Writing new environment at 0x%lx on %s\n",
DEVOFFSET (dev_target), DEVNAME (dev_target));
#endif
- rc = flash_write_buf (dev_target, fd_target, environment.image,
- CONFIG_ENV_SIZE, DEVOFFSET (dev_target),
+ rc = flash_write_buf(dev_target, fd_target, environment.image,
+ CUR_ENVSIZE, DEVOFFSET(dev_target),
DEVTYPE(dev_target));
if (rc < 0)
return rc;
DEVTYPE(dev_current) = mtdinfo.type;
- rc = flash_read_buf (dev_current, fd, environment.image, CONFIG_ENV_SIZE,
+ rc = flash_read_buf(dev_current, fd, environment.image, CUR_ENVSIZE,
DEVOFFSET (dev_current), mtdinfo.type);
- return (rc != CONFIG_ENV_SIZE) ? -1 : 0;
+ return (rc != CUR_ENVSIZE) ? -1 : 0;
}
static int flash_io (int mode)
static char *envmatch (char * s1, char * s2)
{
+ if (s1 == NULL || s2 == NULL)
+ return NULL;
while (*s1 == *s2++)
if (*s1++ == '=')
if (parse_config ()) /* should fill envdevices */
return -1;
- addr0 = calloc (1, CONFIG_ENV_SIZE);
+ addr0 = calloc(1, CUR_ENVSIZE);
if (addr0 == NULL) {
- fprintf (stderr,
+ fprintf(stderr,
"Not enough memory for environment (%ld bytes)\n",
- CONFIG_ENV_SIZE);
+ CUR_ENVSIZE);
return -1;
}
flag0 = *environment.flags;
dev_current = 1;
- addr1 = calloc (1, CONFIG_ENV_SIZE);
+ addr1 = calloc(1, CUR_ENVSIZE);
if (addr1 == NULL) {
- fprintf (stderr,
+ fprintf(stderr,
"Not enough memory for environment (%ld bytes)\n",
- CONFIG_ENV_SIZE);
+ CUR_ENVSIZE);
return -1;
}
redundant = addr1;
* MA 02111-1307 USA
*/
+/* Pull in the current config to define the default environment */
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__ /* get only #defines from config.h */
+#include <config.h>
+#undef __ASSEMBLY__
+#else
+#include <config.h>
+#endif
+
/*
* To build the utility with the static configuration
* comment out the next line.
*/
#define CONFIG_FILE "/etc/fw_env.config"
+#ifndef CONFIG_FILE
#define HAVE_REDUND /* For systems with 2 env sectors */
#define DEVICE1_NAME "/dev/mtd1"
#define DEVICE2_NAME "/dev/mtd2"
#define ENV2_SIZE 0x4000
#define DEVICE2_ESIZE 0x4000
#define DEVICE2_ENVSECTORS 2
+#endif
+#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
+#endif
+
+#ifndef CONFIG_BOOTDELAY
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#ifndef CONFIG_BOOTCOMMAND
#define CONFIG_BOOTCOMMAND \
"bootp; " \
"setenv bootargs root=/dev/nfs nfsroot=${serverip}:${rootpath} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
+#endif
extern int fw_printenv(int argc, char *argv[]);
extern char *fw_getenv (char *name);
* variable "name"
*/
+#include <fcntl.h>
+#include <getopt.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
-#include <getopt.h>
+#include <sys/file.h>
+#include <unistd.h>
#include "fw_env.h"
#define CMD_PRINTENV "fw_printenv"
);
}
-int
-main(int argc, char *argv[])
+int main(int argc, char *argv[])
{
char *p;
char *cmdname = *argv;
char *script_file = NULL;
int c;
+ const char *lockname = "/var/lock/" CMD_PRINTENV ".lock";
+ int lockfd = -1;
+ int retval = EXIT_SUCCESS;
+
+ lockfd = open(lockname, O_WRONLY | O_CREAT | O_TRUNC);
+ if (-1 == lockfd) {
+ fprintf(stderr, "Error opening lock file %s\n", lockname);
+ return EXIT_FAILURE;
+ }
+
+ if (-1 == flock(lockfd, LOCK_EX)) {
+ fprintf(stderr, "Error locking file %s\n", lockname);
+ close(lockfd);
+ return EXIT_FAILURE;
+ }
if ((p = strrchr (cmdname, '/')) != NULL) {
cmdname = p + 1;
break;
case 'h':
usage();
- return EXIT_SUCCESS;
+ goto exit;
default: /* '?' */
fprintf(stderr, "Try `%s --help' for more information."
"\n", cmdname);
- return EXIT_FAILURE;
+ retval = EXIT_FAILURE;
+ goto exit;
}
}
-
if (strcmp(cmdname, CMD_PRINTENV) == 0) {
-
- if (fw_printenv (argc, argv) != 0)
- return EXIT_FAILURE;
-
- return EXIT_SUCCESS;
-
+ if (fw_printenv(argc, argv) != 0)
+ retval = EXIT_FAILURE;
} else if (strcmp(cmdname, CMD_SETENV) == 0) {
if (!script_file) {
if (fw_setenv(argc, argv) != 0)
- return EXIT_FAILURE;
+ retval = EXIT_FAILURE;
} else {
if (fw_parse_script(script_file) != 0)
- return EXIT_FAILURE;
+ retval = EXIT_FAILURE;
}
-
- return EXIT_SUCCESS;
-
+ } else {
+ fprintf(stderr,
+ "Identity crisis - may be called as `" CMD_PRINTENV
+ "' or as `" CMD_SETENV "' but not as `%s'\n",
+ cmdname);
+ retval = EXIT_FAILURE;
}
- fprintf (stderr,
- "Identity crisis - may be called as `" CMD_PRINTENV
- "' or as `" CMD_SETENV "' but not as `%s'\n",
- cmdname);
- return EXIT_FAILURE;
+exit:
+ flock(lockfd, LOCK_UN);
+ close(lockfd);
+ return retval;
}
--- /dev/null
+#
+# Copyright (C) 2012 Marek Vasut <marex@denx.de>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+all: $(obj)docproc
+
+$(obj)docproc: docproc.c
+ $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
+ $(HOSTSTRIP) $@
+
+clean:
+ rm -rf docproc
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * docproc is a simple preprocessor for the template files
+ * used as placeholders for the kernel internal documentation.
+ * docproc is used for documentation-frontend and
+ * dependency-generator.
+ * The two usages have in common that they require
+ * some knowledge of the .tmpl syntax, therefore they
+ * are kept together.
+ *
+ * documentation-frontend
+ * Scans the template file and call kernel-doc for
+ * all occurrences of ![EIF]file
+ * Beforehand each referenced file is scanned for
+ * any symbols that are exported via these macros:
+ * EXPORT_SYMBOL(), EXPORT_SYMBOL_GPL(), &
+ * EXPORT_SYMBOL_GPL_FUTURE()
+ * This is used to create proper -function and
+ * -nofunction arguments in calls to kernel-doc.
+ * Usage: docproc doc file.tmpl
+ *
+ * dependency-generator:
+ * Scans the template file and list all files
+ * referenced in a format recognized by make.
+ * Usage: docproc depend file.tmpl
+ * Writes dependency information to stdout
+ * in the following format:
+ * file.tmpl src.c src2.c
+ * The filenames are obtained from the following constructs:
+ * !Efilename
+ * !Ifilename
+ * !Dfilename
+ * !Ffilename
+ * !Pfilename
+ *
+ */
+
+#define _GNU_SOURCE
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+#include <unistd.h>
+#include <limits.h>
+#include <errno.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+
+/* exitstatus is used to keep track of any failing calls to kernel-doc,
+ * but execution continues. */
+int exitstatus = 0;
+
+typedef void DFL(char *);
+DFL *defaultline;
+
+typedef void FILEONLY(char * file);
+FILEONLY *internalfunctions;
+FILEONLY *externalfunctions;
+FILEONLY *symbolsonly;
+FILEONLY *findall;
+
+typedef void FILELINE(char * file, char * line);
+FILELINE * singlefunctions;
+FILELINE * entity_system;
+FILELINE * docsection;
+
+#define MAXLINESZ 2048
+#define MAXFILES 250
+#define KERNELDOCPATH "tools/kernel-doc/"
+#define KERNELDOC "kernel-doc"
+#define DOCBOOK "-docbook"
+#define LIST "-list"
+#define FUNCTION "-function"
+#define NOFUNCTION "-nofunction"
+#define NODOCSECTIONS "-no-doc-sections"
+
+static char *srctree, *kernsrctree;
+
+static char **all_list = NULL;
+static int all_list_len = 0;
+
+static void consume_symbol(const char *sym)
+{
+ int i;
+
+ for (i = 0; i < all_list_len; i++) {
+ if (!all_list[i])
+ continue;
+ if (strcmp(sym, all_list[i]))
+ continue;
+ all_list[i] = NULL;
+ break;
+ }
+}
+
+static void usage (void)
+{
+ fprintf(stderr, "Usage: docproc {doc|depend} file\n");
+ fprintf(stderr, "Input is read from file.tmpl. Output is sent to stdout\n");
+ fprintf(stderr, "doc: frontend when generating kernel documentation\n");
+ fprintf(stderr, "depend: generate list of files referenced within file\n");
+ fprintf(stderr, "Environment variable SRCTREE: absolute path to sources.\n");
+ fprintf(stderr, " KBUILD_SRC: absolute path to kernel source tree.\n");
+}
+
+/*
+ * Execute kernel-doc with parameters given in svec
+ */
+static void exec_kernel_doc(char **svec)
+{
+ pid_t pid;
+ int ret;
+ char real_filename[PATH_MAX + 1];
+ /* Make sure output generated so far are flushed */
+ fflush(stdout);
+ switch (pid=fork()) {
+ case -1:
+ perror("fork");
+ exit(1);
+ case 0:
+ memset(real_filename, 0, sizeof(real_filename));
+ strncat(real_filename, kernsrctree, PATH_MAX);
+ strncat(real_filename, "/" KERNELDOCPATH KERNELDOC,
+ PATH_MAX - strlen(real_filename));
+ execvp(real_filename, svec);
+ fprintf(stderr, "exec ");
+ perror(real_filename);
+ exit(1);
+ default:
+ waitpid(pid, &ret ,0);
+ }
+ if (WIFEXITED(ret))
+ exitstatus |= WEXITSTATUS(ret);
+ else
+ exitstatus = 0xff;
+}
+
+/* Types used to create list of all exported symbols in a number of files */
+struct symbols
+{
+ char *name;
+};
+
+struct symfile
+{
+ char *filename;
+ struct symbols *symbollist;
+ int symbolcnt;
+};
+
+struct symfile symfilelist[MAXFILES];
+int symfilecnt = 0;
+
+static void add_new_symbol(struct symfile *sym, char * symname)
+{
+ sym->symbollist =
+ realloc(sym->symbollist, (sym->symbolcnt + 1) * sizeof(char *));
+ sym->symbollist[sym->symbolcnt++].name = strdup(symname);
+}
+
+/* Add a filename to the list */
+static struct symfile * add_new_file(char * filename)
+{
+ symfilelist[symfilecnt++].filename = strdup(filename);
+ return &symfilelist[symfilecnt - 1];
+}
+
+/* Check if file already are present in the list */
+static struct symfile * filename_exist(char * filename)
+{
+ int i;
+ for (i=0; i < symfilecnt; i++)
+ if (strcmp(symfilelist[i].filename, filename) == 0)
+ return &symfilelist[i];
+ return NULL;
+}
+
+/*
+ * List all files referenced within the template file.
+ * Files are separated by tabs.
+ */
+static void adddep(char * file) { printf("\t%s", file); }
+static void adddep2(char * file, char * line) { line = line; adddep(file); }
+static void noaction(char * line) { line = line; }
+static void noaction2(char * file, char * line) { file = file; line = line; }
+
+/* Echo the line without further action */
+static void printline(char * line) { printf("%s", line); }
+
+/*
+ * Find all symbols in filename that are exported with EXPORT_SYMBOL &
+ * EXPORT_SYMBOL_GPL (& EXPORT_SYMBOL_GPL_FUTURE implicitly).
+ * All symbols located are stored in symfilelist.
+ */
+static void find_export_symbols(char * filename)
+{
+ FILE * fp;
+ struct symfile *sym;
+ char line[MAXLINESZ];
+ if (filename_exist(filename) == NULL) {
+ char real_filename[PATH_MAX + 1];
+ memset(real_filename, 0, sizeof(real_filename));
+ strncat(real_filename, srctree, PATH_MAX);
+ strncat(real_filename, "/", PATH_MAX - strlen(real_filename));
+ strncat(real_filename, filename,
+ PATH_MAX - strlen(real_filename));
+ sym = add_new_file(filename);
+ fp = fopen(real_filename, "r");
+ if (fp == NULL) {
+ fprintf(stderr, "docproc: ");
+ perror(real_filename);
+ exit(1);
+ }
+ while (fgets(line, MAXLINESZ, fp)) {
+ char *p;
+ char *e;
+ if (((p = strstr(line, "EXPORT_SYMBOL_GPL")) != NULL) ||
+ ((p = strstr(line, "EXPORT_SYMBOL")) != NULL)) {
+ /* Skip EXPORT_SYMBOL{_GPL} */
+ while (isalnum(*p) || *p == '_')
+ p++;
+ /* Remove parentheses & additional whitespace */
+ while (isspace(*p))
+ p++;
+ if (*p != '(')
+ continue; /* Syntax error? */
+ else
+ p++;
+ while (isspace(*p))
+ p++;
+ e = p;
+ while (isalnum(*e) || *e == '_')
+ e++;
+ *e = '\0';
+ add_new_symbol(sym, p);
+ }
+ }
+ fclose(fp);
+ }
+}
+
+/*
+ * Document all external or internal functions in a file.
+ * Call kernel-doc with following parameters:
+ * kernel-doc -docbook -nofunction function_name1 filename
+ * Function names are obtained from all the src files
+ * by find_export_symbols.
+ * intfunc uses -nofunction
+ * extfunc uses -function
+ */
+static void docfunctions(char * filename, char * type)
+{
+ int i,j;
+ int symcnt = 0;
+ int idx = 0;
+ char **vec;
+
+ for (i=0; i <= symfilecnt; i++)
+ symcnt += symfilelist[i].symbolcnt;
+ vec = malloc((2 + 2 * symcnt + 3) * sizeof(char *));
+ if (vec == NULL) {
+ perror("docproc: ");
+ exit(1);
+ }
+ vec[idx++] = KERNELDOC;
+ vec[idx++] = DOCBOOK;
+ vec[idx++] = NODOCSECTIONS;
+ for (i=0; i < symfilecnt; i++) {
+ struct symfile * sym = &symfilelist[i];
+ for (j=0; j < sym->symbolcnt; j++) {
+ vec[idx++] = type;
+ consume_symbol(sym->symbollist[j].name);
+ vec[idx++] = sym->symbollist[j].name;
+ }
+ }
+ vec[idx++] = filename;
+ vec[idx] = NULL;
+ printf("<!-- %s -->\n", filename);
+ exec_kernel_doc(vec);
+ fflush(stdout);
+ free(vec);
+}
+static void intfunc(char * filename) { docfunctions(filename, NOFUNCTION); }
+static void extfunc(char * filename) { docfunctions(filename, FUNCTION); }
+
+/*
+ * Document specific function(s) in a file.
+ * Call kernel-doc with the following parameters:
+ * kernel-doc -docbook -function function1 [-function function2]
+ */
+static void singfunc(char * filename, char * line)
+{
+ char *vec[200]; /* Enough for specific functions */
+ int i, idx = 0;
+ int startofsym = 1;
+ vec[idx++] = KERNELDOC;
+ vec[idx++] = DOCBOOK;
+
+ /* Split line up in individual parameters preceded by FUNCTION */
+ for (i=0; line[i]; i++) {
+ if (isspace(line[i])) {
+ line[i] = '\0';
+ startofsym = 1;
+ continue;
+ }
+ if (startofsym) {
+ startofsym = 0;
+ vec[idx++] = FUNCTION;
+ vec[idx++] = &line[i];
+ }
+ }
+ for (i = 0; i < idx; i++) {
+ if (strcmp(vec[i], FUNCTION))
+ continue;
+ consume_symbol(vec[i + 1]);
+ }
+ vec[idx++] = filename;
+ vec[idx] = NULL;
+ exec_kernel_doc(vec);
+}
+
+/*
+ * Insert specific documentation section from a file.
+ * Call kernel-doc with the following parameters:
+ * kernel-doc -docbook -function "doc section" filename
+ */
+static void docsect(char *filename, char *line)
+{
+ char *vec[6]; /* kerneldoc -docbook -function "section" file NULL */
+ char *s;
+
+ for (s = line; *s; s++)
+ if (*s == '\n')
+ *s = '\0';
+
+ if (asprintf(&s, "DOC: %s", line) < 0) {
+ perror("asprintf");
+ exit(1);
+ }
+ consume_symbol(s);
+ free(s);
+
+ vec[0] = KERNELDOC;
+ vec[1] = DOCBOOK;
+ vec[2] = FUNCTION;
+ vec[3] = line;
+ vec[4] = filename;
+ vec[5] = NULL;
+ exec_kernel_doc(vec);
+}
+
+static void find_all_symbols(char *filename)
+{
+ char *vec[4]; /* kerneldoc -list file NULL */
+ pid_t pid;
+ int ret, i, count, start;
+ char real_filename[PATH_MAX + 1];
+ int pipefd[2];
+ char *data, *str;
+ size_t data_len = 0;
+
+ vec[0] = KERNELDOC;
+ vec[1] = LIST;
+ vec[2] = filename;
+ vec[3] = NULL;
+
+ if (pipe(pipefd)) {
+ perror("pipe");
+ exit(1);
+ }
+
+ switch (pid=fork()) {
+ case -1:
+ perror("fork");
+ exit(1);
+ case 0:
+ close(pipefd[0]);
+ dup2(pipefd[1], 1);
+ memset(real_filename, 0, sizeof(real_filename));
+ strncat(real_filename, kernsrctree, PATH_MAX);
+ strncat(real_filename, "/" KERNELDOCPATH KERNELDOC,
+ PATH_MAX - strlen(real_filename));
+ execvp(real_filename, vec);
+ fprintf(stderr, "exec ");
+ perror(real_filename);
+ exit(1);
+ default:
+ close(pipefd[1]);
+ data = malloc(4096);
+ do {
+ while ((ret = read(pipefd[0],
+ data + data_len,
+ 4096)) > 0) {
+ data_len += ret;
+ data = realloc(data, data_len + 4096);
+ }
+ } while (ret == -EAGAIN);
+ if (ret != 0) {
+ perror("read");
+ exit(1);
+ }
+ waitpid(pid, &ret ,0);
+ }
+ if (WIFEXITED(ret))
+ exitstatus |= WEXITSTATUS(ret);
+ else
+ exitstatus = 0xff;
+
+ count = 0;
+ /* poor man's strtok, but with counting */
+ for (i = 0; i < data_len; i++) {
+ if (data[i] == '\n') {
+ count++;
+ data[i] = '\0';
+ }
+ }
+ start = all_list_len;
+ all_list_len += count;
+ all_list = realloc(all_list, sizeof(char *) * all_list_len);
+ str = data;
+ for (i = 0; i < data_len && start != all_list_len; i++) {
+ if (data[i] == '\0') {
+ all_list[start] = str;
+ str = data + i + 1;
+ start++;
+ }
+ }
+}
+
+/*
+ * Parse file, calling action specific functions for:
+ * 1) Lines containing !E
+ * 2) Lines containing !I
+ * 3) Lines containing !D
+ * 4) Lines containing !F
+ * 5) Lines containing !P
+ * 6) Lines containing !C
+ * 7) Default lines - lines not matching the above
+ */
+static void parse_file(FILE *infile)
+{
+ char line[MAXLINESZ];
+ char * s;
+ while (fgets(line, MAXLINESZ, infile)) {
+ if (line[0] == '!') {
+ s = line + 2;
+ switch (line[1]) {
+ case 'E':
+ while (*s && !isspace(*s)) s++;
+ *s = '\0';
+ externalfunctions(line+2);
+ break;
+ case 'I':
+ while (*s && !isspace(*s)) s++;
+ *s = '\0';
+ internalfunctions(line+2);
+ break;
+ case 'D':
+ while (*s && !isspace(*s)) s++;
+ *s = '\0';
+ symbolsonly(line+2);
+ break;
+ case 'F':
+ /* filename */
+ while (*s && !isspace(*s)) s++;
+ *s++ = '\0';
+ /* function names */
+ while (isspace(*s))
+ s++;
+ singlefunctions(line +2, s);
+ break;
+ case 'P':
+ /* filename */
+ while (*s && !isspace(*s)) s++;
+ *s++ = '\0';
+ /* DOC: section name */
+ while (isspace(*s))
+ s++;
+ docsection(line + 2, s);
+ break;
+ case 'C':
+ while (*s && !isspace(*s)) s++;
+ *s = '\0';
+ if (findall)
+ findall(line+2);
+ break;
+ default:
+ defaultline(line);
+ }
+ } else {
+ defaultline(line);
+ }
+ }
+ fflush(stdout);
+}
+
+
+int main(int argc, char *argv[])
+{
+ FILE * infile;
+ int i;
+
+ srctree = getenv("SRCTREE");
+ if (!srctree)
+ srctree = getcwd(NULL, 0);
+ kernsrctree = getenv("KBUILD_SRC");
+ if (!kernsrctree || !*kernsrctree)
+ kernsrctree = srctree;
+ if (argc != 3) {
+ usage();
+ exit(1);
+ }
+ /* Open file, exit on error */
+ infile = fopen(argv[2], "r");
+ if (infile == NULL) {
+ fprintf(stderr, "docproc: ");
+ perror(argv[2]);
+ exit(2);
+ }
+
+ if (strcmp("doc", argv[1]) == 0) {
+ /* Need to do this in two passes.
+ * First pass is used to collect all symbols exported
+ * in the various files;
+ * Second pass generate the documentation.
+ * This is required because some functions are declared
+ * and exported in different files :-((
+ */
+ /* Collect symbols */
+ defaultline = noaction;
+ internalfunctions = find_export_symbols;
+ externalfunctions = find_export_symbols;
+ symbolsonly = find_export_symbols;
+ singlefunctions = noaction2;
+ docsection = noaction2;
+ findall = find_all_symbols;
+ parse_file(infile);
+
+ /* Rewind to start from beginning of file again */
+ fseek(infile, 0, SEEK_SET);
+ defaultline = printline;
+ internalfunctions = intfunc;
+ externalfunctions = extfunc;
+ symbolsonly = printline;
+ singlefunctions = singfunc;
+ docsection = docsect;
+ findall = NULL;
+
+ parse_file(infile);
+
+ for (i = 0; i < all_list_len; i++) {
+ if (!all_list[i])
+ continue;
+ fprintf(stderr, "Warning: didn't use docs for %s\n",
+ all_list[i]);
+ }
+ } else if (strcmp("depend", argv[1]) == 0) {
+ /* Create first part of dependency chain
+ * file.tmpl */
+ printf("%s\t", argv[2]);
+ defaultline = noaction;
+ internalfunctions = adddep;
+ externalfunctions = adddep;
+ symbolsonly = adddep;
+ singlefunctions = adddep2;
+ docsection = adddep2;
+ findall = adddep;
+ parse_file(infile);
+ printf("\n");
+ } else {
+ fprintf(stderr, "Unknown option: %s\n", argv[1]);
+ exit(1);
+ }
+ fclose(infile);
+ fflush(stdout);
+ return exitstatus;
+}
--- /dev/null
+#!/usr/bin/perl -w
+
+use strict;
+
+## Copyright (c) 1998 Michael Zucchi, All Rights Reserved ##
+## Copyright (C) 2000, 1 Tim Waugh <twaugh@redhat.com> ##
+## Copyright (C) 2001 Simon Huggins ##
+## Copyright (C) 2005-2012 Randy Dunlap ##
+## Copyright (C) 2012 Dan Luedtke ##
+## ##
+## #define enhancements by Armin Kuster <akuster@mvista.com> ##
+## Copyright (c) 2000 MontaVista Software, Inc. ##
+## ##
+## This software falls under the GNU General Public License. ##
+## Please read the COPYING file for more information ##
+
+# 18/01/2001 - Cleanups
+# Functions prototyped as foo(void) same as foo()
+# Stop eval'ing where we don't need to.
+# -- huggie@earth.li
+
+# 27/06/2001 - Allowed whitespace after initial "/**" and
+# allowed comments before function declarations.
+# -- Christian Kreibich <ck@whoop.org>
+
+# Still to do:
+# - add perldoc documentation
+# - Look more closely at some of the scarier bits :)
+
+# 26/05/2001 - Support for separate source and object trees.
+# Return error code.
+# Keith Owens <kaos@ocs.com.au>
+
+# 23/09/2001 - Added support for typedefs, structs, enums and unions
+# Support for Context section; can be terminated using empty line
+# Small fixes (like spaces vs. \s in regex)
+# -- Tim Jansen <tim@tjansen.de>
+
+# 25/07/2012 - Added support for HTML5
+# -- Dan Luedtke <mail@danrl.de>
+
+#
+# This will read a 'c' file and scan for embedded comments in the
+# style of gnome comments (+minor extensions - see below).
+#
+
+# Note: This only supports 'c'.
+
+# usage:
+# kernel-doc [ -docbook | -html | -html5 | -text | -man | -list ]
+# [ -no-doc-sections ]
+# [ -function funcname [ -function funcname ...] ]
+# c file(s)s > outputfile
+# or
+# [ -nofunction funcname [ -function funcname ...] ]
+# c file(s)s > outputfile
+#
+# Set output format using one of -docbook -html -html5 -text or -man.
+# Default is man.
+# The -list format is for internal use by docproc.
+#
+# -no-doc-sections
+# Do not output DOC: sections
+#
+# -function funcname
+# If set, then only generate documentation for the given function(s) or
+# DOC: section titles. All other functions and DOC: sections are ignored.
+#
+# -nofunction funcname
+# If set, then only generate documentation for the other function(s)/DOC:
+# sections. Cannot be used together with -function (yes, that's a bug --
+# perl hackers can fix it 8))
+#
+# c files - list of 'c' files to process
+#
+# All output goes to stdout, with errors to stderr.
+
+#
+# format of comments.
+# In the following table, (...)? signifies optional structure.
+# (...)* signifies 0 or more structure elements
+# /**
+# * function_name(:)? (- short description)?
+# (* @parameterx: (description of parameter x)?)*
+# (* a blank line)?
+# * (Description:)? (Description of function)?
+# * (section header: (section description)? )*
+# (*)?*/
+#
+# So .. the trivial example would be:
+#
+# /**
+# * my_function
+# */
+#
+# If the Description: header tag is omitted, then there must be a blank line
+# after the last parameter specification.
+# e.g.
+# /**
+# * my_function - does my stuff
+# * @my_arg: its mine damnit
+# *
+# * Does my stuff explained.
+# */
+#
+# or, could also use:
+# /**
+# * my_function - does my stuff
+# * @my_arg: its mine damnit
+# * Description: Does my stuff explained.
+# */
+# etc.
+#
+# Besides functions you can also write documentation for structs, unions,
+# enums and typedefs. Instead of the function name you must write the name
+# of the declaration; the struct/union/enum/typedef must always precede
+# the name. Nesting of declarations is not supported.
+# Use the argument mechanism to document members or constants.
+# e.g.
+# /**
+# * struct my_struct - short description
+# * @a: first member
+# * @b: second member
+# *
+# * Longer description
+# */
+# struct my_struct {
+# int a;
+# int b;
+# /* private: */
+# int c;
+# };
+#
+# All descriptions can be multiline, except the short function description.
+#
+# You can also add additional sections. When documenting kernel functions you
+# should document the "Context:" of the function, e.g. whether the functions
+# can be called form interrupts. Unlike other sections you can end it with an
+# empty line.
+# Example-sections should contain the string EXAMPLE so that they are marked
+# appropriately in DocBook.
+#
+# Example:
+# /**
+# * user_function - function that can only be called in user context
+# * @a: some argument
+# * Context: !in_interrupt()
+# *
+# * Some description
+# * Example:
+# * user_function(22);
+# */
+# ...
+#
+#
+# All descriptive text is further processed, scanning for the following special
+# patterns, which are highlighted appropriately.
+#
+# 'funcname()' - function
+# '$ENVVAR' - environmental variable
+# '&struct_name' - name of a structure (up to two words including 'struct')
+# '@parameter' - name of a parameter
+# '%CONST' - name of a constant.
+
+## init lots of data
+
+my $errors = 0;
+my $warnings = 0;
+my $anon_struct_union = 0;
+
+# match expressions used to find embedded type information
+my $type_constant = '\%([-_\w]+)';
+my $type_func = '(\w+)\(\)';
+my $type_param = '\@(\w+)';
+my $type_struct = '\&((struct\s*)*[_\w]+)';
+my $type_struct_xml = '\\&((struct\s*)*[_\w]+)';
+my $type_env = '(\$\w+)';
+
+# Output conversion substitutions.
+# One for each output format
+
+# these work fairly well
+my %highlights_html = ( $type_constant, "<i>\$1</i>",
+ $type_func, "<b>\$1</b>",
+ $type_struct_xml, "<i>\$1</i>",
+ $type_env, "<b><i>\$1</i></b>",
+ $type_param, "<tt><b>\$1</b></tt>" );
+my $local_lt = "\\\\\\\\lt:";
+my $local_gt = "\\\\\\\\gt:";
+my $blankline_html = $local_lt . "p" . $local_gt; # was "<p>"
+
+# html version 5
+my %highlights_html5 = ( $type_constant, "<span class=\"const\">\$1</span>",
+ $type_func, "<span class=\"func\">\$1</span>",
+ $type_struct_xml, "<span class=\"struct\">\$1</span>",
+ $type_env, "<span class=\"env\">\$1</span>",
+ $type_param, "<span class=\"param\">\$1</span>" );
+my $blankline_html5 = $local_lt . "br /" . $local_gt;
+
+# XML, docbook format
+my %highlights_xml = ( "([^=])\\\"([^\\\"<]+)\\\"", "\$1<quote>\$2</quote>",
+ $type_constant, "<constant>\$1</constant>",
+ $type_func, "<function>\$1</function>",
+ $type_struct_xml, "<structname>\$1</structname>",
+ $type_env, "<envar>\$1</envar>",
+ $type_param, "<parameter>\$1</parameter>" );
+my $blankline_xml = $local_lt . "/para" . $local_gt . $local_lt . "para" . $local_gt . "\n";
+
+# gnome, docbook format
+my %highlights_gnome = ( $type_constant, "<replaceable class=\"option\">\$1</replaceable>",
+ $type_func, "<function>\$1</function>",
+ $type_struct, "<structname>\$1</structname>",
+ $type_env, "<envar>\$1</envar>",
+ $type_param, "<parameter>\$1</parameter>" );
+my $blankline_gnome = "</para><para>\n";
+
+# these are pretty rough
+my %highlights_man = ( $type_constant, "\$1",
+ $type_func, "\\\\fB\$1\\\\fP",
+ $type_struct, "\\\\fI\$1\\\\fP",
+ $type_param, "\\\\fI\$1\\\\fP" );
+my $blankline_man = "";
+
+# text-mode
+my %highlights_text = ( $type_constant, "\$1",
+ $type_func, "\$1",
+ $type_struct, "\$1",
+ $type_param, "\$1" );
+my $blankline_text = "";
+
+# list mode
+my %highlights_list = ( $type_constant, "\$1",
+ $type_func, "\$1",
+ $type_struct, "\$1",
+ $type_param, "\$1" );
+my $blankline_list = "";
+
+# read arguments
+if ($#ARGV == -1) {
+ usage();
+}
+
+my $kernelversion;
+my $dohighlight = "";
+
+my $verbose = 0;
+my $output_mode = "man";
+my $no_doc_sections = 0;
+my %highlights = %highlights_man;
+my $blankline = $blankline_man;
+my $modulename = "Bootloader API";
+my $function_only = 0;
+my $man_date = ('January', 'February', 'March', 'April', 'May', 'June',
+ 'July', 'August', 'September', 'October',
+ 'November', 'December')[(localtime)[4]] .
+ " " . ((localtime)[5]+1900);
+
+# Essentially these are globals.
+# They probably want to be tidied up, made more localised or something.
+# CAVEAT EMPTOR! Some of the others I localised may not want to be, which
+# could cause "use of undefined value" or other bugs.
+my ($function, %function_table, %parametertypes, $declaration_purpose);
+my ($type, $declaration_name, $return_type);
+my ($newsection, $newcontents, $prototype, $brcount, %source_map);
+
+if (defined($ENV{'KBUILD_VERBOSE'})) {
+ $verbose = "$ENV{'KBUILD_VERBOSE'}";
+}
+
+# Generated docbook code is inserted in a template at a point where
+# docbook v3.1 requires a non-zero sequence of RefEntry's; see:
+# http://www.oasis-open.org/docbook/documentation/reference/html/refentry.html
+# We keep track of number of generated entries and generate a dummy
+# if needs be to ensure the expanded template can be postprocessed
+# into html.
+my $section_counter = 0;
+
+my $lineprefix="";
+
+# states
+# 0 - normal code
+# 1 - looking for function name
+# 2 - scanning field start.
+# 3 - scanning prototype.
+# 4 - documentation block
+my $state;
+my $in_doc_sect;
+
+#declaration types: can be
+# 'function', 'struct', 'union', 'enum', 'typedef'
+my $decl_type;
+
+my $doc_special = "\@\%\$\&";
+
+my $doc_start = '^/\*\*\s*$'; # Allow whitespace at end of comment start.
+my $doc_end = '\*/';
+my $doc_com = '\s*\*\s*';
+my $doc_decl = $doc_com . '(\w+)';
+my $doc_sect = $doc_com . '([' . $doc_special . ']?[\w\s]+):(.*)';
+my $doc_content = $doc_com . '(.*)';
+my $doc_block = $doc_com . 'DOC:\s*(.*)?';
+
+my %constants;
+my %parameterdescs;
+my @parameterlist;
+my %sections;
+my @sectionlist;
+my $sectcheck;
+my $struct_actual;
+
+my $contents = "";
+my $section_default = "Description"; # default section
+my $section_intro = "Introduction";
+my $section = $section_default;
+my $section_context = "Context";
+
+my $undescribed = "-- undescribed --";
+
+reset_state();
+
+while ($ARGV[0] =~ m/^-(.*)/) {
+ my $cmd = shift @ARGV;
+ if ($cmd eq "-html") {
+ $output_mode = "html";
+ %highlights = %highlights_html;
+ $blankline = $blankline_html;
+ } elsif ($cmd eq "-html5") {
+ $output_mode = "html5";
+ %highlights = %highlights_html5;
+ $blankline = $blankline_html5;
+ } elsif ($cmd eq "-man") {
+ $output_mode = "man";
+ %highlights = %highlights_man;
+ $blankline = $blankline_man;
+ } elsif ($cmd eq "-text") {
+ $output_mode = "text";
+ %highlights = %highlights_text;
+ $blankline = $blankline_text;
+ } elsif ($cmd eq "-docbook") {
+ $output_mode = "xml";
+ %highlights = %highlights_xml;
+ $blankline = $blankline_xml;
+ } elsif ($cmd eq "-list") {
+ $output_mode = "list";
+ %highlights = %highlights_list;
+ $blankline = $blankline_list;
+ } elsif ($cmd eq "-gnome") {
+ $output_mode = "gnome";
+ %highlights = %highlights_gnome;
+ $blankline = $blankline_gnome;
+ } elsif ($cmd eq "-module") { # not needed for XML, inherits from calling document
+ $modulename = shift @ARGV;
+ } elsif ($cmd eq "-function") { # to only output specific functions
+ $function_only = 1;
+ $function = shift @ARGV;
+ $function_table{$function} = 1;
+ } elsif ($cmd eq "-nofunction") { # to only output specific functions
+ $function_only = 2;
+ $function = shift @ARGV;
+ $function_table{$function} = 1;
+ } elsif ($cmd eq "-v") {
+ $verbose = 1;
+ } elsif (($cmd eq "-h") || ($cmd eq "--help")) {
+ usage();
+ } elsif ($cmd eq '-no-doc-sections') {
+ $no_doc_sections = 1;
+ }
+}
+
+# continue execution near EOF;
+
+sub usage {
+ print "Usage: $0 [ -docbook | -html | -html5 | -text | -man | -list ]\n";
+ print " [ -no-doc-sections ]\n";
+ print " [ -function funcname [ -function funcname ...] ]\n";
+ print " [ -nofunction funcname [ -nofunction funcname ...] ]\n";
+ print " [ -v ]\n";
+ print " c source file(s) > outputfile\n";
+ print " -v : verbose output, more warnings & other info listed\n";
+ exit 1;
+}
+
+# get kernel version from env
+sub get_kernel_version() {
+ my $version = 'unknown kernel version';
+
+ if (defined($ENV{'U_BOOT_VERSION'})) {
+ $version = $ENV{'U_BOOT_VERSION'};
+ }
+ return $version;
+}
+
+##
+# dumps section contents to arrays/hashes intended for that purpose.
+#
+sub dump_section {
+ my $file = shift;
+ my $name = shift;
+ my $contents = join "\n", @_;
+
+ if ($name =~ m/$type_constant/) {
+ $name = $1;
+# print STDERR "constant section '$1' = '$contents'\n";
+ $constants{$name} = $contents;
+ } elsif ($name =~ m/$type_param/) {
+# print STDERR "parameter def '$1' = '$contents'\n";
+ $name = $1;
+ $parameterdescs{$name} = $contents;
+ $sectcheck = $sectcheck . $name . " ";
+ } elsif ($name eq "@\.\.\.") {
+# print STDERR "parameter def '...' = '$contents'\n";
+ $name = "...";
+ $parameterdescs{$name} = $contents;
+ $sectcheck = $sectcheck . $name . " ";
+ } else {
+# print STDERR "other section '$name' = '$contents'\n";
+ if (defined($sections{$name}) && ($sections{$name} ne "")) {
+ print STDERR "Error(${file}:$.): duplicate section name '$name'\n";
+ ++$errors;
+ }
+ $sections{$name} = $contents;
+ push @sectionlist, $name;
+ }
+}
+
+##
+# dump DOC: section after checking that it should go out
+#
+sub dump_doc_section {
+ my $file = shift;
+ my $name = shift;
+ my $contents = join "\n", @_;
+
+ if ($no_doc_sections) {
+ return;
+ }
+
+ if (($function_only == 0) ||
+ ( $function_only == 1 && defined($function_table{$name})) ||
+ ( $function_only == 2 && !defined($function_table{$name})))
+ {
+ dump_section($file, $name, $contents);
+ output_blockhead({'sectionlist' => \@sectionlist,
+ 'sections' => \%sections,
+ 'module' => $modulename,
+ 'content-only' => ($function_only != 0), });
+ }
+}
+
+##
+# output function
+#
+# parameterdescs, a hash.
+# function => "function name"
+# parameterlist => @list of parameters
+# parameterdescs => %parameter descriptions
+# sectionlist => @list of sections
+# sections => %section descriptions
+#
+
+sub output_highlight {
+ my $contents = join "\n",@_;
+ my $line;
+
+# DEBUG
+# if (!defined $contents) {
+# use Carp;
+# confess "output_highlight got called with no args?\n";
+# }
+
+ if ($output_mode eq "html" || $output_mode eq "html5" ||
+ $output_mode eq "xml") {
+ $contents = local_unescape($contents);
+ # convert data read & converted thru xml_escape() into &xyz; format:
+ $contents =~ s/\\\\\\/\&/g;
+ }
+# print STDERR "contents b4:$contents\n";
+ eval $dohighlight;
+ die $@ if $@;
+# print STDERR "contents af:$contents\n";
+
+# strip whitespaces when generating html5
+ if ($output_mode eq "html5") {
+ $contents =~ s/^\s+//;
+ $contents =~ s/\s+$//;
+ }
+ foreach $line (split "\n", $contents) {
+ if ($line eq ""){
+ print $lineprefix, local_unescape($blankline);
+ } else {
+ $line =~ s/\\\\\\/\&/g;
+ if ($output_mode eq "man" && substr($line, 0, 1) eq ".") {
+ print "\\&$line";
+ } else {
+ print $lineprefix, $line;
+ }
+ }
+ print "\n";
+ }
+}
+
+# output sections in html
+sub output_section_html(%) {
+ my %args = %{$_[0]};
+ my $section;
+
+ foreach $section (@{$args{'sectionlist'}}) {
+ print "<h3>$section</h3>\n";
+ print "<blockquote>\n";
+ output_highlight($args{'sections'}{$section});
+ print "</blockquote>\n";
+ }
+}
+
+# output enum in html
+sub output_enum_html(%) {
+ my %args = %{$_[0]};
+ my ($parameter);
+ my $count;
+ print "<h2>enum " . $args{'enum'} . "</h2>\n";
+
+ print "<b>enum " . $args{'enum'} . "</b> {<br>\n";
+ $count = 0;
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ print " <b>" . $parameter . "</b>";
+ if ($count != $#{$args{'parameterlist'}}) {
+ $count++;
+ print ",\n";
+ }
+ print "<br>";
+ }
+ print "};<br>\n";
+
+ print "<h3>Constants</h3>\n";
+ print "<dl>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ print "<dt><b>" . $parameter . "</b>\n";
+ print "<dd>";
+ output_highlight($args{'parameterdescs'}{$parameter});
+ }
+ print "</dl>\n";
+ output_section_html(@_);
+ print "<hr>\n";
+}
+
+# output typedef in html
+sub output_typedef_html(%) {
+ my %args = %{$_[0]};
+ my ($parameter);
+ my $count;
+ print "<h2>typedef " . $args{'typedef'} . "</h2>\n";
+
+ print "<b>typedef " . $args{'typedef'} . "</b>\n";
+ output_section_html(@_);
+ print "<hr>\n";
+}
+
+# output struct in html
+sub output_struct_html(%) {
+ my %args = %{$_[0]};
+ my ($parameter);
+
+ print "<h2>" . $args{'type'} . " " . $args{'struct'} . " - " . $args{'purpose'} . "</h2>\n";
+ print "<b>" . $args{'type'} . " " . $args{'struct'} . "</b> {<br>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ if ($parameter =~ /^#/) {
+ print "$parameter<br>\n";
+ next;
+ }
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print " <i>$1</i><b>$parameter</b>) <i>($2)</i>;<br>\n";
+ } elsif ($type =~ m/^(.*?)\s*(:.*)/) {
+ # bitfield
+ print " <i>$1</i> <b>$parameter</b>$2;<br>\n";
+ } else {
+ print " <i>$type</i> <b>$parameter</b>;<br>\n";
+ }
+ }
+ print "};<br>\n";
+
+ print "<h3>Members</h3>\n";
+ print "<dl>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ ($parameter =~ /^#/) && next;
+
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ print "<dt><b>" . $parameter . "</b>\n";
+ print "<dd>";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ }
+ print "</dl>\n";
+ output_section_html(@_);
+ print "<hr>\n";
+}
+
+# output function in html
+sub output_function_html(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+
+ print "<h2>" . $args{'function'} . " - " . $args{'purpose'} . "</h2>\n";
+ print "<i>" . $args{'functiontype'} . "</i>\n";
+ print "<b>" . $args{'function'} . "</b>\n";
+ print "(";
+ $count = 0;
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print "<i>$1</i><b>$parameter</b>) <i>($2)</i>";
+ } else {
+ print "<i>" . $type . "</i> <b>" . $parameter . "</b>";
+ }
+ if ($count != $#{$args{'parameterlist'}}) {
+ $count++;
+ print ",\n";
+ }
+ }
+ print ")\n";
+
+ print "<h3>Arguments</h3>\n";
+ print "<dl>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ print "<dt><b>" . $parameter . "</b>\n";
+ print "<dd>";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ }
+ print "</dl>\n";
+ output_section_html(@_);
+ print "<hr>\n";
+}
+
+# output DOC: block header in html
+sub output_blockhead_html(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+
+ foreach $section (@{$args{'sectionlist'}}) {
+ print "<h3>$section</h3>\n";
+ print "<ul>\n";
+ output_highlight($args{'sections'}{$section});
+ print "</ul>\n";
+ }
+ print "<hr>\n";
+}
+
+# output sections in html5
+sub output_section_html5(%) {
+ my %args = %{$_[0]};
+ my $section;
+
+ foreach $section (@{$args{'sectionlist'}}) {
+ print "<section>\n";
+ print "<h1>$section</h1>\n";
+ print "<p>\n";
+ output_highlight($args{'sections'}{$section});
+ print "</p>\n";
+ print "</section>\n";
+ }
+}
+
+# output enum in html5
+sub output_enum_html5(%) {
+ my %args = %{$_[0]};
+ my ($parameter);
+ my $count;
+ my $html5id;
+
+ $html5id = $args{'enum'};
+ $html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
+ print "<article class=\"enum\" id=\"enum:". $html5id . "\">";
+ print "<h1>enum " . $args{'enum'} . "</h1>\n";
+ print "<ol class=\"code\">\n";
+ print "<li>";
+ print "<span class=\"keyword\">enum</span> ";
+ print "<span class=\"identifier\">" . $args{'enum'} . "</span> {";
+ print "</li>\n";
+ $count = 0;
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ print "<li class=\"indent\">";
+ print "<span class=\"param\">" . $parameter . "</span>";
+ if ($count != $#{$args{'parameterlist'}}) {
+ $count++;
+ print ",";
+ }
+ print "</li>\n";
+ }
+ print "<li>};</li>\n";
+ print "</ol>\n";
+
+ print "<section>\n";
+ print "<h1>Constants</h1>\n";
+ print "<dl>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ print "<dt>" . $parameter . "</dt>\n";
+ print "<dd>";
+ output_highlight($args{'parameterdescs'}{$parameter});
+ print "</dd>\n";
+ }
+ print "</dl>\n";
+ print "</section>\n";
+ output_section_html5(@_);
+ print "</article>\n";
+}
+
+# output typedef in html5
+sub output_typedef_html5(%) {
+ my %args = %{$_[0]};
+ my ($parameter);
+ my $count;
+ my $html5id;
+
+ $html5id = $args{'typedef'};
+ $html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
+ print "<article class=\"typedef\" id=\"typedef:" . $html5id . "\">\n";
+ print "<h1>typedef " . $args{'typedef'} . "</h1>\n";
+
+ print "<ol class=\"code\">\n";
+ print "<li>";
+ print "<span class=\"keyword\">typedef</span> ";
+ print "<span class=\"identifier\">" . $args{'typedef'} . "</span>";
+ print "</li>\n";
+ print "</ol>\n";
+ output_section_html5(@_);
+ print "</article>\n";
+}
+
+# output struct in html5
+sub output_struct_html5(%) {
+ my %args = %{$_[0]};
+ my ($parameter);
+ my $html5id;
+
+ $html5id = $args{'struct'};
+ $html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
+ print "<article class=\"struct\" id=\"struct:" . $html5id . "\">\n";
+ print "<hgroup>\n";
+ print "<h1>" . $args{'type'} . " " . $args{'struct'} . "</h1>";
+ print "<h2>". $args{'purpose'} . "</h2>\n";
+ print "</hgroup>\n";
+ print "<ol class=\"code\">\n";
+ print "<li>";
+ print "<span class=\"type\">" . $args{'type'} . "</span> ";
+ print "<span class=\"identifier\">" . $args{'struct'} . "</span> {";
+ print "</li>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ print "<li class=\"indent\">";
+ if ($parameter =~ /^#/) {
+ print "<span class=\"param\">" . $parameter ."</span>\n";
+ print "</li>\n";
+ next;
+ }
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print "<span class=\"type\">$1</span> ";
+ print "<span class=\"param\">$parameter</span>";
+ print "<span class=\"type\">)</span> ";
+ print "(<span class=\"args\">$2</span>);";
+ } elsif ($type =~ m/^(.*?)\s*(:.*)/) {
+ # bitfield
+ print "<span class=\"type\">$1</span> ";
+ print "<span class=\"param\">$parameter</span>";
+ print "<span class=\"bits\">$2</span>;";
+ } else {
+ print "<span class=\"type\">$type</span> ";
+ print "<span class=\"param\">$parameter</span>;";
+ }
+ print "</li>\n";
+ }
+ print "<li>};</li>\n";
+ print "</ol>\n";
+
+ print "<section>\n";
+ print "<h1>Members</h1>\n";
+ print "<dl>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ ($parameter =~ /^#/) && next;
+
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ print "<dt>" . $parameter . "</dt>\n";
+ print "<dd>";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ print "</dd>\n";
+ }
+ print "</dl>\n";
+ print "</section>\n";
+ output_section_html5(@_);
+ print "</article>\n";
+}
+
+# output function in html5
+sub output_function_html5(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+ my $html5id;
+
+ $html5id = $args{'function'};
+ $html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
+ print "<article class=\"function\" id=\"func:". $html5id . "\">\n";
+ print "<hgroup>\n";
+ print "<h1>" . $args{'function'} . "</h1>";
+ print "<h2>" . $args{'purpose'} . "</h2>\n";
+ print "</hgroup>\n";
+ print "<ol class=\"code\">\n";
+ print "<li>";
+ print "<span class=\"type\">" . $args{'functiontype'} . "</span> ";
+ print "<span class=\"identifier\">" . $args{'function'} . "</span> (";
+ print "</li>";
+ $count = 0;
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ print "<li class=\"indent\">";
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print "<span class=\"type\">$1</span> ";
+ print "<span class=\"param\">$parameter</span>";
+ print "<span class=\"type\">)</span> ";
+ print "(<span class=\"args\">$2</span>)";
+ } else {
+ print "<span class=\"type\">$type</span> ";
+ print "<span class=\"param\">$parameter</span>";
+ }
+ if ($count != $#{$args{'parameterlist'}}) {
+ $count++;
+ print ",";
+ }
+ print "</li>\n";
+ }
+ print "<li>)</li>\n";
+ print "</ol>\n";
+
+ print "<section>\n";
+ print "<h1>Arguments</h1>\n";
+ print "<p>\n";
+ print "<dl>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ print "<dt>" . $parameter . "</dt>\n";
+ print "<dd>";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ print "</dd>\n";
+ }
+ print "</dl>\n";
+ print "</section>\n";
+ output_section_html5(@_);
+ print "</article>\n";
+}
+
+# output DOC: block header in html5
+sub output_blockhead_html5(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+ my $html5id;
+
+ foreach $section (@{$args{'sectionlist'}}) {
+ $html5id = $section;
+ $html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
+ print "<article class=\"doc\" id=\"doc:". $html5id . "\">\n";
+ print "<h1>$section</h1>\n";
+ print "<p>\n";
+ output_highlight($args{'sections'}{$section});
+ print "</p>\n";
+ }
+ print "</article>\n";
+}
+
+sub output_section_xml(%) {
+ my %args = %{$_[0]};
+ my $section;
+ # print out each section
+ $lineprefix=" ";
+ foreach $section (@{$args{'sectionlist'}}) {
+ print "<refsect1>\n";
+ print "<title>$section</title>\n";
+ if ($section =~ m/EXAMPLE/i) {
+ print "<informalexample><programlisting>\n";
+ } else {
+ print "<para>\n";
+ }
+ output_highlight($args{'sections'}{$section});
+ if ($section =~ m/EXAMPLE/i) {
+ print "</programlisting></informalexample>\n";
+ } else {
+ print "</para>\n";
+ }
+ print "</refsect1>\n";
+ }
+}
+
+# output function in XML DocBook
+sub output_function_xml(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+ my $id;
+
+ $id = "API-" . $args{'function'};
+ $id =~ s/[^A-Za-z0-9]/-/g;
+
+ print "<refentry id=\"$id\">\n";
+ print "<refentryinfo>\n";
+ print " <title>U-BOOT</title>\n";
+ print " <productname>Bootloader Hackers Manual</productname>\n";
+ print " <date>$man_date</date>\n";
+ print "</refentryinfo>\n";
+ print "<refmeta>\n";
+ print " <refentrytitle><phrase>" . $args{'function'} . "</phrase></refentrytitle>\n";
+ print " <manvolnum>9</manvolnum>\n";
+ print " <refmiscinfo class=\"version\">" . $kernelversion . "</refmiscinfo>\n";
+ print "</refmeta>\n";
+ print "<refnamediv>\n";
+ print " <refname>" . $args{'function'} . "</refname>\n";
+ print " <refpurpose>\n";
+ print " ";
+ output_highlight ($args{'purpose'});
+ print " </refpurpose>\n";
+ print "</refnamediv>\n";
+
+ print "<refsynopsisdiv>\n";
+ print " <title>Synopsis</title>\n";
+ print " <funcsynopsis><funcprototype>\n";
+ print " <funcdef>" . $args{'functiontype'} . " ";
+ print "<function>" . $args{'function'} . " </function></funcdef>\n";
+
+ $count = 0;
+ if ($#{$args{'parameterlist'}} >= 0) {
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print " <paramdef>$1<parameter>$parameter</parameter>)\n";
+ print " <funcparams>$2</funcparams></paramdef>\n";
+ } else {
+ print " <paramdef>" . $type;
+ print " <parameter>$parameter</parameter></paramdef>\n";
+ }
+ }
+ } else {
+ print " <void/>\n";
+ }
+ print " </funcprototype></funcsynopsis>\n";
+ print "</refsynopsisdiv>\n";
+
+ # print parameters
+ print "<refsect1>\n <title>Arguments</title>\n";
+ if ($#{$args{'parameterlist'}} >= 0) {
+ print " <variablelist>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ print " <varlistentry>\n <term><parameter>$parameter</parameter></term>\n";
+ print " <listitem>\n <para>\n";
+ $lineprefix=" ";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ print " </para>\n </listitem>\n </varlistentry>\n";
+ }
+ print " </variablelist>\n";
+ } else {
+ print " <para>\n None\n </para>\n";
+ }
+ print "</refsect1>\n";
+
+ output_section_xml(@_);
+ print "</refentry>\n\n";
+}
+
+# output struct in XML DocBook
+sub output_struct_xml(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $id;
+
+ $id = "API-struct-" . $args{'struct'};
+ $id =~ s/[^A-Za-z0-9]/-/g;
+
+ print "<refentry id=\"$id\">\n";
+ print "<refentryinfo>\n";
+ print " <title>U-BOOT</title>\n";
+ print " <productname>Bootloader Hackers Manual</productname>\n";
+ print " <date>$man_date</date>\n";
+ print "</refentryinfo>\n";
+ print "<refmeta>\n";
+ print " <refentrytitle><phrase>" . $args{'type'} . " " . $args{'struct'} . "</phrase></refentrytitle>\n";
+ print " <manvolnum>9</manvolnum>\n";
+ print " <refmiscinfo class=\"version\">" . $kernelversion . "</refmiscinfo>\n";
+ print "</refmeta>\n";
+ print "<refnamediv>\n";
+ print " <refname>" . $args{'type'} . " " . $args{'struct'} . "</refname>\n";
+ print " <refpurpose>\n";
+ print " ";
+ output_highlight ($args{'purpose'});
+ print " </refpurpose>\n";
+ print "</refnamediv>\n";
+
+ print "<refsynopsisdiv>\n";
+ print " <title>Synopsis</title>\n";
+ print " <programlisting>\n";
+ print $args{'type'} . " " . $args{'struct'} . " {\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ if ($parameter =~ /^#/) {
+ my $prm = $parameter;
+ # convert data read & converted thru xml_escape() into &xyz; format:
+ # This allows us to have #define macros interspersed in a struct.
+ $prm =~ s/\\\\\\/\&/g;
+ print "$prm\n";
+ next;
+ }
+
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ defined($args{'parameterdescs'}{$parameter_name}) || next;
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print " $1 $parameter) ($2);\n";
+ } elsif ($type =~ m/^(.*?)\s*(:.*)/) {
+ # bitfield
+ print " $1 $parameter$2;\n";
+ } else {
+ print " " . $type . " " . $parameter . ";\n";
+ }
+ }
+ print "};";
+ print " </programlisting>\n";
+ print "</refsynopsisdiv>\n";
+
+ print " <refsect1>\n";
+ print " <title>Members</title>\n";
+
+ if ($#{$args{'parameterlist'}} >= 0) {
+ print " <variablelist>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ ($parameter =~ /^#/) && next;
+
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ defined($args{'parameterdescs'}{$parameter_name}) || next;
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ print " <varlistentry>";
+ print " <term>$parameter</term>\n";
+ print " <listitem><para>\n";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ print " </para></listitem>\n";
+ print " </varlistentry>\n";
+ }
+ print " </variablelist>\n";
+ } else {
+ print " <para>\n None\n </para>\n";
+ }
+ print " </refsect1>\n";
+
+ output_section_xml(@_);
+
+ print "</refentry>\n\n";
+}
+
+# output enum in XML DocBook
+sub output_enum_xml(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+ my $id;
+
+ $id = "API-enum-" . $args{'enum'};
+ $id =~ s/[^A-Za-z0-9]/-/g;
+
+ print "<refentry id=\"$id\">\n";
+ print "<refentryinfo>\n";
+ print " <title>U-BOOT</title>\n";
+ print " <productname>Bootloader Hackers Manual</productname>\n";
+ print " <date>$man_date</date>\n";
+ print "</refentryinfo>\n";
+ print "<refmeta>\n";
+ print " <refentrytitle><phrase>enum " . $args{'enum'} . "</phrase></refentrytitle>\n";
+ print " <manvolnum>9</manvolnum>\n";
+ print " <refmiscinfo class=\"version\">" . $kernelversion . "</refmiscinfo>\n";
+ print "</refmeta>\n";
+ print "<refnamediv>\n";
+ print " <refname>enum " . $args{'enum'} . "</refname>\n";
+ print " <refpurpose>\n";
+ print " ";
+ output_highlight ($args{'purpose'});
+ print " </refpurpose>\n";
+ print "</refnamediv>\n";
+
+ print "<refsynopsisdiv>\n";
+ print " <title>Synopsis</title>\n";
+ print " <programlisting>\n";
+ print "enum " . $args{'enum'} . " {\n";
+ $count = 0;
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ print " $parameter";
+ if ($count != $#{$args{'parameterlist'}}) {
+ $count++;
+ print ",";
+ }
+ print "\n";
+ }
+ print "};";
+ print " </programlisting>\n";
+ print "</refsynopsisdiv>\n";
+
+ print "<refsect1>\n";
+ print " <title>Constants</title>\n";
+ print " <variablelist>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ print " <varlistentry>";
+ print " <term>$parameter</term>\n";
+ print " <listitem><para>\n";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ print " </para></listitem>\n";
+ print " </varlistentry>\n";
+ }
+ print " </variablelist>\n";
+ print "</refsect1>\n";
+
+ output_section_xml(@_);
+
+ print "</refentry>\n\n";
+}
+
+# output typedef in XML DocBook
+sub output_typedef_xml(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $id;
+
+ $id = "API-typedef-" . $args{'typedef'};
+ $id =~ s/[^A-Za-z0-9]/-/g;
+
+ print "<refentry id=\"$id\">\n";
+ print "<refentryinfo>\n";
+ print " <title>U-BOOT</title>\n";
+ print " <productname>Bootloader Hackers Manual</productname>\n";
+ print " <date>$man_date</date>\n";
+ print "</refentryinfo>\n";
+ print "<refmeta>\n";
+ print " <refentrytitle><phrase>typedef " . $args{'typedef'} . "</phrase></refentrytitle>\n";
+ print " <manvolnum>9</manvolnum>\n";
+ print "</refmeta>\n";
+ print "<refnamediv>\n";
+ print " <refname>typedef " . $args{'typedef'} . "</refname>\n";
+ print " <refpurpose>\n";
+ print " ";
+ output_highlight ($args{'purpose'});
+ print " </refpurpose>\n";
+ print "</refnamediv>\n";
+
+ print "<refsynopsisdiv>\n";
+ print " <title>Synopsis</title>\n";
+ print " <synopsis>typedef " . $args{'typedef'} . ";</synopsis>\n";
+ print "</refsynopsisdiv>\n";
+
+ output_section_xml(@_);
+
+ print "</refentry>\n\n";
+}
+
+# output in XML DocBook
+sub output_blockhead_xml(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+
+ my $id = $args{'module'};
+ $id =~ s/[^A-Za-z0-9]/-/g;
+
+ # print out each section
+ $lineprefix=" ";
+ foreach $section (@{$args{'sectionlist'}}) {
+ if (!$args{'content-only'}) {
+ print "<refsect1>\n <title>$section</title>\n";
+ }
+ if ($section =~ m/EXAMPLE/i) {
+ print "<example><para>\n";
+ } else {
+ print "<para>\n";
+ }
+ output_highlight($args{'sections'}{$section});
+ if ($section =~ m/EXAMPLE/i) {
+ print "</para></example>\n";
+ } else {
+ print "</para>";
+ }
+ if (!$args{'content-only'}) {
+ print "\n</refsect1>\n";
+ }
+ }
+
+ print "\n\n";
+}
+
+# output in XML DocBook
+sub output_function_gnome {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+ my $id;
+
+ $id = $args{'module'} . "-" . $args{'function'};
+ $id =~ s/[^A-Za-z0-9]/-/g;
+
+ print "<sect2>\n";
+ print " <title id=\"$id\">" . $args{'function'} . "</title>\n";
+
+ print " <funcsynopsis>\n";
+ print " <funcdef>" . $args{'functiontype'} . " ";
+ print "<function>" . $args{'function'} . " ";
+ print "</function></funcdef>\n";
+
+ $count = 0;
+ if ($#{$args{'parameterlist'}} >= 0) {
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print " <paramdef>$1 <parameter>$parameter</parameter>)\n";
+ print " <funcparams>$2</funcparams></paramdef>\n";
+ } else {
+ print " <paramdef>" . $type;
+ print " <parameter>$parameter</parameter></paramdef>\n";
+ }
+ }
+ } else {
+ print " <void>\n";
+ }
+ print " </funcsynopsis>\n";
+ if ($#{$args{'parameterlist'}} >= 0) {
+ print " <informaltable pgwide=\"1\" frame=\"none\" role=\"params\">\n";
+ print "<tgroup cols=\"2\">\n";
+ print "<colspec colwidth=\"2*\">\n";
+ print "<colspec colwidth=\"8*\">\n";
+ print "<tbody>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ print " <row><entry align=\"right\"><parameter>$parameter</parameter></entry>\n";
+ print " <entry>\n";
+ $lineprefix=" ";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ print " </entry></row>\n";
+ }
+ print " </tbody></tgroup></informaltable>\n";
+ } else {
+ print " <para>\n None\n </para>\n";
+ }
+
+ # print out each section
+ $lineprefix=" ";
+ foreach $section (@{$args{'sectionlist'}}) {
+ print "<simplesect>\n <title>$section</title>\n";
+ if ($section =~ m/EXAMPLE/i) {
+ print "<example><programlisting>\n";
+ } else {
+ }
+ print "<para>\n";
+ output_highlight($args{'sections'}{$section});
+ print "</para>\n";
+ if ($section =~ m/EXAMPLE/i) {
+ print "</programlisting></example>\n";
+ } else {
+ }
+ print " </simplesect>\n";
+ }
+
+ print "</sect2>\n\n";
+}
+
+##
+# output function in man
+sub output_function_man(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+
+ print ".TH \"$args{'function'}\" 9 \"$args{'function'}\" \"$man_date\" \"Bootloader Hacker's Manual\" U-BOOT\n";
+
+ print ".SH NAME\n";
+ print $args{'function'} . " \\- " . $args{'purpose'} . "\n";
+
+ print ".SH SYNOPSIS\n";
+ if ($args{'functiontype'} ne "") {
+ print ".B \"" . $args{'functiontype'} . "\" " . $args{'function'} . "\n";
+ } else {
+ print ".B \"" . $args{'function'} . "\n";
+ }
+ $count = 0;
+ my $parenth = "(";
+ my $post = ",";
+ foreach my $parameter (@{$args{'parameterlist'}}) {
+ if ($count == $#{$args{'parameterlist'}}) {
+ $post = ");";
+ }
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print ".BI \"" . $parenth . $1 . "\" " . $parameter . " \") (" . $2 . ")" . $post . "\"\n";
+ } else {
+ $type =~ s/([^\*])$/$1 /;
+ print ".BI \"" . $parenth . $type . "\" " . $parameter . " \"" . $post . "\"\n";
+ }
+ $count++;
+ $parenth = "";
+ }
+
+ print ".SH ARGUMENTS\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ print ".IP \"" . $parameter . "\" 12\n";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ }
+ foreach $section (@{$args{'sectionlist'}}) {
+ print ".SH \"", uc $section, "\"\n";
+ output_highlight($args{'sections'}{$section});
+ }
+}
+
+##
+# output enum in man
+sub output_enum_man(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+
+ print ".TH \"$args{'module'}\" 9 \"enum $args{'enum'}\" \"$man_date\" \"API Manual\" U-BOOT\n";
+
+ print ".SH NAME\n";
+ print "enum " . $args{'enum'} . " \\- " . $args{'purpose'} . "\n";
+
+ print ".SH SYNOPSIS\n";
+ print "enum " . $args{'enum'} . " {\n";
+ $count = 0;
+ foreach my $parameter (@{$args{'parameterlist'}}) {
+ print ".br\n.BI \" $parameter\"\n";
+ if ($count == $#{$args{'parameterlist'}}) {
+ print "\n};\n";
+ last;
+ }
+ else {
+ print ", \n.br\n";
+ }
+ $count++;
+ }
+
+ print ".SH Constants\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ print ".IP \"" . $parameter . "\" 12\n";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ }
+ foreach $section (@{$args{'sectionlist'}}) {
+ print ".SH \"$section\"\n";
+ output_highlight($args{'sections'}{$section});
+ }
+}
+
+##
+# output struct in man
+sub output_struct_man(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+
+ print ".TH \"$args{'module'}\" 9 \"" . $args{'type'} . " " . $args{'struct'} . "\" \"$man_date\" \"API Manual\" U-BOOT\n";
+
+ print ".SH NAME\n";
+ print $args{'type'} . " " . $args{'struct'} . " \\- " . $args{'purpose'} . "\n";
+
+ print ".SH SYNOPSIS\n";
+ print $args{'type'} . " " . $args{'struct'} . " {\n.br\n";
+
+ foreach my $parameter (@{$args{'parameterlist'}}) {
+ if ($parameter =~ /^#/) {
+ print ".BI \"$parameter\"\n.br\n";
+ next;
+ }
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print ".BI \" " . $1 . "\" " . $parameter . " \") (" . $2 . ")" . "\"\n;\n";
+ } elsif ($type =~ m/^(.*?)\s*(:.*)/) {
+ # bitfield
+ print ".BI \" " . $1 . "\ \" " . $parameter . $2 . " \"" . "\"\n;\n";
+ } else {
+ $type =~ s/([^\*])$/$1 /;
+ print ".BI \" " . $type . "\" " . $parameter . " \"" . "\"\n;\n";
+ }
+ print "\n.br\n";
+ }
+ print "};\n.br\n";
+
+ print ".SH Members\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ ($parameter =~ /^#/) && next;
+
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ print ".IP \"" . $parameter . "\" 12\n";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ }
+ foreach $section (@{$args{'sectionlist'}}) {
+ print ".SH \"$section\"\n";
+ output_highlight($args{'sections'}{$section});
+ }
+}
+
+##
+# output typedef in man
+sub output_typedef_man(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+
+ print ".TH \"$args{'module'}\" 9 \"$args{'typedef'}\" \"$man_date\" \"API Manual\" U-BOOT\n";
+
+ print ".SH NAME\n";
+ print "typedef " . $args{'typedef'} . " \\- " . $args{'purpose'} . "\n";
+
+ foreach $section (@{$args{'sectionlist'}}) {
+ print ".SH \"$section\"\n";
+ output_highlight($args{'sections'}{$section});
+ }
+}
+
+sub output_blockhead_man(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+
+ print ".TH \"$args{'module'}\" 9 \"$args{'module'}\" \"$man_date\" \"API Manual\" U-BOOT\n";
+
+ foreach $section (@{$args{'sectionlist'}}) {
+ print ".SH \"$section\"\n";
+ output_highlight($args{'sections'}{$section});
+ }
+}
+
+##
+# output in text
+sub output_function_text(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $start;
+
+ print "Name:\n\n";
+ print $args{'function'} . " - " . $args{'purpose'} . "\n";
+
+ print "\nSynopsis:\n\n";
+ if ($args{'functiontype'} ne "") {
+ $start = $args{'functiontype'} . " " . $args{'function'} . " (";
+ } else {
+ $start = $args{'function'} . " (";
+ }
+ print $start;
+
+ my $count = 0;
+ foreach my $parameter (@{$args{'parameterlist'}}) {
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print $1 . $parameter . ") (" . $2;
+ } else {
+ print $type . " " . $parameter;
+ }
+ if ($count != $#{$args{'parameterlist'}}) {
+ $count++;
+ print ",\n";
+ print " " x length($start);
+ } else {
+ print ");\n\n";
+ }
+ }
+
+ print "Arguments:\n\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ print $parameter . "\n\t" . $args{'parameterdescs'}{$parameter_name} . "\n";
+ }
+ output_section_text(@_);
+}
+
+#output sections in text
+sub output_section_text(%) {
+ my %args = %{$_[0]};
+ my $section;
+
+ print "\n";
+ foreach $section (@{$args{'sectionlist'}}) {
+ print "$section:\n\n";
+ output_highlight($args{'sections'}{$section});
+ }
+ print "\n\n";
+}
+
+# output enum in text
+sub output_enum_text(%) {
+ my %args = %{$_[0]};
+ my ($parameter);
+ my $count;
+ print "Enum:\n\n";
+
+ print "enum " . $args{'enum'} . " - " . $args{'purpose'} . "\n\n";
+ print "enum " . $args{'enum'} . " {\n";
+ $count = 0;
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ print "\t$parameter";
+ if ($count != $#{$args{'parameterlist'}}) {
+ $count++;
+ print ",";
+ }
+ print "\n";
+ }
+ print "};\n\n";
+
+ print "Constants:\n\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ print "$parameter\n\t";
+ print $args{'parameterdescs'}{$parameter} . "\n";
+ }
+
+ output_section_text(@_);
+}
+
+# output typedef in text
+sub output_typedef_text(%) {
+ my %args = %{$_[0]};
+ my ($parameter);
+ my $count;
+ print "Typedef:\n\n";
+
+ print "typedef " . $args{'typedef'} . " - " . $args{'purpose'} . "\n";
+ output_section_text(@_);
+}
+
+# output struct as text
+sub output_struct_text(%) {
+ my %args = %{$_[0]};
+ my ($parameter);
+
+ print $args{'type'} . " " . $args{'struct'} . " - " . $args{'purpose'} . "\n\n";
+ print $args{'type'} . " " . $args{'struct'} . " {\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ if ($parameter =~ /^#/) {
+ print "$parameter\n";
+ next;
+ }
+
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print "\t$1 $parameter) ($2);\n";
+ } elsif ($type =~ m/^(.*?)\s*(:.*)/) {
+ # bitfield
+ print "\t$1 $parameter$2;\n";
+ } else {
+ print "\t" . $type . " " . $parameter . ";\n";
+ }
+ }
+ print "};\n\n";
+
+ print "Members:\n\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ ($parameter =~ /^#/) && next;
+
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ print "$parameter\n\t";
+ print $args{'parameterdescs'}{$parameter_name} . "\n";
+ }
+ print "\n";
+ output_section_text(@_);
+}
+
+sub output_blockhead_text(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+
+ foreach $section (@{$args{'sectionlist'}}) {
+ print " $section:\n";
+ print " -> ";
+ output_highlight($args{'sections'}{$section});
+ }
+}
+
+## list mode output functions
+
+sub output_function_list(%) {
+ my %args = %{$_[0]};
+
+ print $args{'function'} . "\n";
+}
+
+# output enum in list
+sub output_enum_list(%) {
+ my %args = %{$_[0]};
+ print $args{'enum'} . "\n";
+}
+
+# output typedef in list
+sub output_typedef_list(%) {
+ my %args = %{$_[0]};
+ print $args{'typedef'} . "\n";
+}
+
+# output struct as list
+sub output_struct_list(%) {
+ my %args = %{$_[0]};
+
+ print $args{'struct'} . "\n";
+}
+
+sub output_blockhead_list(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+
+ foreach $section (@{$args{'sectionlist'}}) {
+ print "DOC: $section\n";
+ }
+}
+
+##
+# generic output function for all types (function, struct/union, typedef, enum);
+# calls the generated, variable output_ function name based on
+# functype and output_mode
+sub output_declaration {
+ no strict 'refs';
+ my $name = shift;
+ my $functype = shift;
+ my $func = "output_${functype}_$output_mode";
+ if (($function_only==0) ||
+ ( $function_only == 1 && defined($function_table{$name})) ||
+ ( $function_only == 2 && !defined($function_table{$name})))
+ {
+ &$func(@_);
+ $section_counter++;
+ }
+}
+
+##
+# generic output function - calls the right one based on current output mode.
+sub output_blockhead {
+ no strict 'refs';
+ my $func = "output_blockhead_" . $output_mode;
+ &$func(@_);
+ $section_counter++;
+}
+
+##
+# takes a declaration (struct, union, enum, typedef) and
+# invokes the right handler. NOT called for functions.
+sub dump_declaration($$) {
+ no strict 'refs';
+ my ($prototype, $file) = @_;
+ my $func = "dump_" . $decl_type;
+ &$func(@_);
+}
+
+sub dump_union($$) {
+ dump_struct(@_);
+}
+
+sub dump_struct($$) {
+ my $x = shift;
+ my $file = shift;
+ my $nested;
+
+ if ($x =~ /(struct|union)\s+(\w+)\s*{(.*)}/) {
+ #my $decl_type = $1;
+ $declaration_name = $2;
+ my $members = $3;
+
+ # ignore embedded structs or unions
+ $members =~ s/({.*})//g;
+ $nested = $1;
+
+ # ignore members marked private:
+ $members =~ s/\/\*\s*private:.*?\/\*\s*public:.*?\*\///gos;
+ $members =~ s/\/\*\s*private:.*//gos;
+ # strip comments:
+ $members =~ s/\/\*.*?\*\///gos;
+ $nested =~ s/\/\*.*?\*\///gos;
+ # strip kmemcheck_bitfield_{begin,end}.*;
+ $members =~ s/kmemcheck_bitfield_.*?;//gos;
+ # strip attributes
+ $members =~ s/__aligned\s*\(\d+\)//gos;
+
+ create_parameterlist($members, ';', $file);
+ check_sections($file, $declaration_name, "struct", $sectcheck, $struct_actual, $nested);
+
+ output_declaration($declaration_name,
+ 'struct',
+ {'struct' => $declaration_name,
+ 'module' => $modulename,
+ 'parameterlist' => \@parameterlist,
+ 'parameterdescs' => \%parameterdescs,
+ 'parametertypes' => \%parametertypes,
+ 'sectionlist' => \@sectionlist,
+ 'sections' => \%sections,
+ 'purpose' => $declaration_purpose,
+ 'type' => $decl_type
+ });
+ }
+ else {
+ print STDERR "Error(${file}:$.): Cannot parse struct or union!\n";
+ ++$errors;
+ }
+}
+
+sub dump_enum($$) {
+ my $x = shift;
+ my $file = shift;
+
+ $x =~ s@/\*.*?\*/@@gos; # strip comments.
+ $x =~ s/^#\s*define\s+.*$//; # strip #define macros inside enums
+
+ if ($x =~ /enum\s+(\w+)\s*{(.*)}/) {
+ $declaration_name = $1;
+ my $members = $2;
+
+ foreach my $arg (split ',', $members) {
+ $arg =~ s/^\s*(\w+).*/$1/;
+ push @parameterlist, $arg;
+ if (!$parameterdescs{$arg}) {
+ $parameterdescs{$arg} = $undescribed;
+ print STDERR "Warning(${file}:$.): Enum value '$arg' ".
+ "not described in enum '$declaration_name'\n";
+ }
+
+ }
+
+ output_declaration($declaration_name,
+ 'enum',
+ {'enum' => $declaration_name,
+ 'module' => $modulename,
+ 'parameterlist' => \@parameterlist,
+ 'parameterdescs' => \%parameterdescs,
+ 'sectionlist' => \@sectionlist,
+ 'sections' => \%sections,
+ 'purpose' => $declaration_purpose
+ });
+ }
+ else {
+ print STDERR "Error(${file}:$.): Cannot parse enum!\n";
+ ++$errors;
+ }
+}
+
+sub dump_typedef($$) {
+ my $x = shift;
+ my $file = shift;
+
+ $x =~ s@/\*.*?\*/@@gos; # strip comments.
+ while (($x =~ /\(*.\)\s*;$/) || ($x =~ /\[*.\]\s*;$/)) {
+ $x =~ s/\(*.\)\s*;$/;/;
+ $x =~ s/\[*.\]\s*;$/;/;
+ }
+
+ if ($x =~ /typedef.*\s+(\w+)\s*;/) {
+ $declaration_name = $1;
+
+ output_declaration($declaration_name,
+ 'typedef',
+ {'typedef' => $declaration_name,
+ 'module' => $modulename,
+ 'sectionlist' => \@sectionlist,
+ 'sections' => \%sections,
+ 'purpose' => $declaration_purpose
+ });
+ }
+ else {
+ print STDERR "Error(${file}:$.): Cannot parse typedef!\n";
+ ++$errors;
+ }
+}
+
+sub save_struct_actual($) {
+ my $actual = shift;
+
+ # strip all spaces from the actual param so that it looks like one string item
+ $actual =~ s/\s*//g;
+ $struct_actual = $struct_actual . $actual . " ";
+}
+
+sub create_parameterlist($$$) {
+ my $args = shift;
+ my $splitter = shift;
+ my $file = shift;
+ my $type;
+ my $param;
+
+ # temporarily replace commas inside function pointer definition
+ while ($args =~ /(\([^\),]+),/) {
+ $args =~ s/(\([^\),]+),/$1#/g;
+ }
+
+ foreach my $arg (split($splitter, $args)) {
+ # strip comments
+ $arg =~ s/\/\*.*\*\///;
+ # strip leading/trailing spaces
+ $arg =~ s/^\s*//;
+ $arg =~ s/\s*$//;
+ $arg =~ s/\s+/ /;
+
+ if ($arg =~ /^#/) {
+ # Treat preprocessor directive as a typeless variable just to fill
+ # corresponding data structures "correctly". Catch it later in
+ # output_* subs.
+ push_parameter($arg, "", $file);
+ } elsif ($arg =~ m/\(.+\)\s*\(/) {
+ # pointer-to-function
+ $arg =~ tr/#/,/;
+ $arg =~ m/[^\(]+\(\*?\s*(\w*)\s*\)/;
+ $param = $1;
+ $type = $arg;
+ $type =~ s/([^\(]+\(\*?)\s*$param/$1/;
+ save_struct_actual($param);
+ push_parameter($param, $type, $file);
+ } elsif ($arg) {
+ $arg =~ s/\s*:\s*/:/g;
+ $arg =~ s/\s*\[/\[/g;
+
+ my @args = split('\s*,\s*', $arg);
+ if ($args[0] =~ m/\*/) {
+ $args[0] =~ s/(\*+)\s*/ $1/;
+ }
+
+ my @first_arg;
+ if ($args[0] =~ /^(.*\s+)(.*?\[.*\].*)$/) {
+ shift @args;
+ push(@first_arg, split('\s+', $1));
+ push(@first_arg, $2);
+ } else {
+ @first_arg = split('\s+', shift @args);
+ }
+
+ unshift(@args, pop @first_arg);
+ $type = join " ", @first_arg;
+
+ foreach $param (@args) {
+ if ($param =~ m/^(\*+)\s*(.*)/) {
+ save_struct_actual($2);
+ push_parameter($2, "$type $1", $file);
+ }
+ elsif ($param =~ m/(.*?):(\d+)/) {
+ if ($type ne "") { # skip unnamed bit-fields
+ save_struct_actual($1);
+ push_parameter($1, "$type:$2", $file)
+ }
+ }
+ else {
+ save_struct_actual($param);
+ push_parameter($param, $type, $file);
+ }
+ }
+ }
+ }
+}
+
+sub push_parameter($$$) {
+ my $param = shift;
+ my $type = shift;
+ my $file = shift;
+
+ if (($anon_struct_union == 1) && ($type eq "") &&
+ ($param eq "}")) {
+ return; # ignore the ending }; from anon. struct/union
+ }
+
+ $anon_struct_union = 0;
+ my $param_name = $param;
+ $param_name =~ s/\[.*//;
+
+ if ($type eq "" && $param =~ /\.\.\.$/)
+ {
+ if (!defined $parameterdescs{$param} || $parameterdescs{$param} eq "") {
+ $parameterdescs{$param} = "variable arguments";
+ }
+ }
+ elsif ($type eq "" && ($param eq "" or $param eq "void"))
+ {
+ $param="void";
+ $parameterdescs{void} = "no arguments";
+ }
+ elsif ($type eq "" && ($param eq "struct" or $param eq "union"))
+ # handle unnamed (anonymous) union or struct:
+ {
+ $type = $param;
+ $param = "{unnamed_" . $param . "}";
+ $parameterdescs{$param} = "anonymous\n";
+ $anon_struct_union = 1;
+ }
+
+ # warn if parameter has no description
+ # (but ignore ones starting with # as these are not parameters
+ # but inline preprocessor statements);
+ # also ignore unnamed structs/unions;
+ if (!$anon_struct_union) {
+ if (!defined $parameterdescs{$param_name} && $param_name !~ /^#/) {
+
+ $parameterdescs{$param_name} = $undescribed;
+
+ if (($type eq 'function') || ($type eq 'enum')) {
+ print STDERR "Warning(${file}:$.): Function parameter ".
+ "or member '$param' not " .
+ "described in '$declaration_name'\n";
+ }
+ print STDERR "Warning(${file}:$.):" .
+ " No description found for parameter '$param'\n";
+ ++$warnings;
+ }
+ }
+
+ $param = xml_escape($param);
+
+ # strip spaces from $param so that it is one continuous string
+ # on @parameterlist;
+ # this fixes a problem where check_sections() cannot find
+ # a parameter like "addr[6 + 2]" because it actually appears
+ # as "addr[6", "+", "2]" on the parameter list;
+ # but it's better to maintain the param string unchanged for output,
+ # so just weaken the string compare in check_sections() to ignore
+ # "[blah" in a parameter string;
+ ###$param =~ s/\s*//g;
+ push @parameterlist, $param;
+ $parametertypes{$param} = $type;
+}
+
+sub check_sections($$$$$$) {
+ my ($file, $decl_name, $decl_type, $sectcheck, $prmscheck, $nested) = @_;
+ my @sects = split ' ', $sectcheck;
+ my @prms = split ' ', $prmscheck;
+ my $err;
+ my ($px, $sx);
+ my $prm_clean; # strip trailing "[array size]" and/or beginning "*"
+
+ foreach $sx (0 .. $#sects) {
+ $err = 1;
+ foreach $px (0 .. $#prms) {
+ $prm_clean = $prms[$px];
+ $prm_clean =~ s/\[.*\]//;
+ $prm_clean =~ s/__attribute__\s*\(\([a-z,_\*\s\(\)]*\)\)//i;
+ # ignore array size in a parameter string;
+ # however, the original param string may contain
+ # spaces, e.g.: addr[6 + 2]
+ # and this appears in @prms as "addr[6" since the
+ # parameter list is split at spaces;
+ # hence just ignore "[..." for the sections check;
+ $prm_clean =~ s/\[.*//;
+
+ ##$prm_clean =~ s/^\**//;
+ if ($prm_clean eq $sects[$sx]) {
+ $err = 0;
+ last;
+ }
+ }
+ if ($err) {
+ if ($decl_type eq "function") {
+ print STDERR "Warning(${file}:$.): " .
+ "Excess function parameter " .
+ "'$sects[$sx]' " .
+ "description in '$decl_name'\n";
+ ++$warnings;
+ } else {
+ if ($nested !~ m/\Q$sects[$sx]\E/) {
+ print STDERR "Warning(${file}:$.): " .
+ "Excess struct/union/enum/typedef member " .
+ "'$sects[$sx]' " .
+ "description in '$decl_name'\n";
+ ++$warnings;
+ }
+ }
+ }
+ }
+}
+
+##
+# takes a function prototype and the name of the current file being
+# processed and spits out all the details stored in the global
+# arrays/hashes.
+sub dump_function($$) {
+ my $prototype = shift;
+ my $file = shift;
+
+ $prototype =~ s/^static +//;
+ $prototype =~ s/^extern +//;
+ $prototype =~ s/^asmlinkage +//;
+ $prototype =~ s/^inline +//;
+ $prototype =~ s/^__inline__ +//;
+ $prototype =~ s/^__inline +//;
+ $prototype =~ s/^__always_inline +//;
+ $prototype =~ s/^noinline +//;
+ $prototype =~ s/__devinit +//;
+ $prototype =~ s/__init +//;
+ $prototype =~ s/__init_or_module +//;
+ $prototype =~ s/__must_check +//;
+ $prototype =~ s/__weak +//;
+ $prototype =~ s/^#\s*define\s+//; #ak added
+ $prototype =~ s/__attribute__\s*\(\([a-z,]*\)\)//;
+
+ # Yes, this truly is vile. We are looking for:
+ # 1. Return type (may be nothing if we're looking at a macro)
+ # 2. Function name
+ # 3. Function parameters.
+ #
+ # All the while we have to watch out for function pointer parameters
+ # (which IIRC is what the two sections are for), C types (these
+ # regexps don't even start to express all the possibilities), and
+ # so on.
+ #
+ # If you mess with these regexps, it's a good idea to check that
+ # the following functions' documentation still comes out right:
+ # - parport_register_device (function pointer parameters)
+ # - atomic_set (macro)
+ # - pci_match_device, __copy_to_user (long return type)
+
+ if ($prototype =~ m/^()([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+ $prototype =~ m/^(\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+ $prototype =~ m/^(\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+\s*\*+)\s*([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+\s+\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+ $prototype =~ m/^()([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+ $prototype =~ m/^(\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+ $prototype =~ m/^(\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+\s+\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+\s+\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+\s+\w+\s+\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+\s*\*\s*\w+\s*\*\s*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/) {
+ $return_type = $1;
+ $declaration_name = $2;
+ my $args = $3;
+
+ create_parameterlist($args, ',', $file);
+ } else {
+ print STDERR "Error(${file}:$.): cannot understand prototype: '$prototype'\n";
+ ++$errors;
+ return;
+ }
+
+ my $prms = join " ", @parameterlist;
+ check_sections($file, $declaration_name, "function", $sectcheck, $prms, "");
+
+ output_declaration($declaration_name,
+ 'function',
+ {'function' => $declaration_name,
+ 'module' => $modulename,
+ 'functiontype' => $return_type,
+ 'parameterlist' => \@parameterlist,
+ 'parameterdescs' => \%parameterdescs,
+ 'parametertypes' => \%parametertypes,
+ 'sectionlist' => \@sectionlist,
+ 'sections' => \%sections,
+ 'purpose' => $declaration_purpose
+ });
+}
+
+sub reset_state {
+ $function = "";
+ %constants = ();
+ %parameterdescs = ();
+ %parametertypes = ();
+ @parameterlist = ();
+ %sections = ();
+ @sectionlist = ();
+ $sectcheck = "";
+ $struct_actual = "";
+ $prototype = "";
+
+ $state = 0;
+}
+
+sub tracepoint_munge($) {
+ my $file = shift;
+ my $tracepointname = 0;
+ my $tracepointargs = 0;
+
+ if ($prototype =~ m/TRACE_EVENT\((.*?),/) {
+ $tracepointname = $1;
+ }
+ if ($prototype =~ m/DEFINE_SINGLE_EVENT\((.*?),/) {
+ $tracepointname = $1;
+ }
+ if ($prototype =~ m/DEFINE_EVENT\((.*?),(.*?),/) {
+ $tracepointname = $2;
+ }
+ $tracepointname =~ s/^\s+//; #strip leading whitespace
+ if ($prototype =~ m/TP_PROTO\((.*?)\)/) {
+ $tracepointargs = $1;
+ }
+ if (($tracepointname eq 0) || ($tracepointargs eq 0)) {
+ print STDERR "Warning(${file}:$.): Unrecognized tracepoint format: \n".
+ "$prototype\n";
+ } else {
+ $prototype = "static inline void trace_$tracepointname($tracepointargs)";
+ }
+}
+
+sub syscall_munge() {
+ my $void = 0;
+
+ $prototype =~ s@[\r\n\t]+@ @gos; # strip newlines/CR's/tabs
+## if ($prototype =~ m/SYSCALL_DEFINE0\s*\(\s*(a-zA-Z0-9_)*\s*\)/) {
+ if ($prototype =~ m/SYSCALL_DEFINE0/) {
+ $void = 1;
+## $prototype = "long sys_$1(void)";
+ }
+
+ $prototype =~ s/SYSCALL_DEFINE.*\(/long sys_/; # fix return type & func name
+ if ($prototype =~ m/long (sys_.*?),/) {
+ $prototype =~ s/,/\(/;
+ } elsif ($void) {
+ $prototype =~ s/\)/\(void\)/;
+ }
+
+ # now delete all of the odd-number commas in $prototype
+ # so that arg types & arg names don't have a comma between them
+ my $count = 0;
+ my $len = length($prototype);
+ if ($void) {
+ $len = 0; # skip the for-loop
+ }
+ for (my $ix = 0; $ix < $len; $ix++) {
+ if (substr($prototype, $ix, 1) eq ',') {
+ $count++;
+ if ($count % 2 == 1) {
+ substr($prototype, $ix, 1) = ' ';
+ }
+ }
+ }
+}
+
+sub process_state3_function($$) {
+ my $x = shift;
+ my $file = shift;
+
+ $x =~ s@\/\/.*$@@gos; # strip C99-style comments to end of line
+
+ if ($x =~ m#\s*/\*\s+MACDOC\s*#io || ($x =~ /^#/ && $x !~ /^#\s*define/)) {
+ # do nothing
+ }
+ elsif ($x =~ /([^\{]*)/) {
+ $prototype .= $1;
+ }
+
+ if (($x =~ /\{/) || ($x =~ /\#\s*define/) || ($x =~ /;/)) {
+ $prototype =~ s@/\*.*?\*/@@gos; # strip comments.
+ $prototype =~ s@[\r\n]+@ @gos; # strip newlines/cr's.
+ $prototype =~ s@^\s+@@gos; # strip leading spaces
+ if ($prototype =~ /SYSCALL_DEFINE/) {
+ syscall_munge();
+ }
+ if ($prototype =~ /TRACE_EVENT/ || $prototype =~ /DEFINE_EVENT/ ||
+ $prototype =~ /DEFINE_SINGLE_EVENT/)
+ {
+ tracepoint_munge($file);
+ }
+ dump_function($prototype, $file);
+ reset_state();
+ }
+}
+
+sub process_state3_type($$) {
+ my $x = shift;
+ my $file = shift;
+
+ $x =~ s@[\r\n]+@ @gos; # strip newlines/cr's.
+ $x =~ s@^\s+@@gos; # strip leading spaces
+ $x =~ s@\s+$@@gos; # strip trailing spaces
+ $x =~ s@\/\/.*$@@gos; # strip C99-style comments to end of line
+
+ if ($x =~ /^#/) {
+ # To distinguish preprocessor directive from regular declaration later.
+ $x .= ";";
+ }
+
+ while (1) {
+ if ( $x =~ /([^{};]*)([{};])(.*)/ ) {
+ $prototype .= $1 . $2;
+ ($2 eq '{') && $brcount++;
+ ($2 eq '}') && $brcount--;
+ if (($2 eq ';') && ($brcount == 0)) {
+ dump_declaration($prototype, $file);
+ reset_state();
+ last;
+ }
+ $x = $3;
+ } else {
+ $prototype .= $x;
+ last;
+ }
+ }
+}
+
+# xml_escape: replace <, >, and & in the text stream;
+#
+# however, formatting controls that are generated internally/locally in the
+# kernel-doc script are not escaped here; instead, they begin life like
+# $blankline_html (4 of '\' followed by a mnemonic + ':'), then these strings
+# are converted to their mnemonic-expected output, without the 4 * '\' & ':',
+# just before actual output; (this is done by local_unescape())
+sub xml_escape($) {
+ my $text = shift;
+ if (($output_mode eq "text") || ($output_mode eq "man")) {
+ return $text;
+ }
+ $text =~ s/\&/\\\\\\amp;/g;
+ $text =~ s/\</\\\\\\lt;/g;
+ $text =~ s/\>/\\\\\\gt;/g;
+ return $text;
+}
+
+# convert local escape strings to html
+# local escape strings look like: '\\\\menmonic:' (that's 4 backslashes)
+sub local_unescape($) {
+ my $text = shift;
+ if (($output_mode eq "text") || ($output_mode eq "man")) {
+ return $text;
+ }
+ $text =~ s/\\\\\\\\lt:/</g;
+ $text =~ s/\\\\\\\\gt:/>/g;
+ return $text;
+}
+
+sub process_file($) {
+ my $file;
+ my $identifier;
+ my $func;
+ my $descr;
+ my $in_purpose = 0;
+ my $initial_section_counter = $section_counter;
+
+ if (defined($ENV{'SRCTREE'})) {
+ $file = "$ENV{'SRCTREE'}" . "/" . "@_";
+ }
+ else {
+ $file = "@_";
+ }
+ if (defined($source_map{$file})) {
+ $file = $source_map{$file};
+ }
+
+ if (!open(IN,"<$file")) {
+ print STDERR "Error: Cannot open file $file\n";
+ ++$errors;
+ return;
+ }
+
+ $. = 1;
+
+ $section_counter = 0;
+ while (<IN>) {
+ if ($state == 0) {
+ if (/$doc_start/o) {
+ $state = 1; # next line is always the function name
+ $in_doc_sect = 0;
+ }
+ } elsif ($state == 1) { # this line is the function name (always)
+ if (/$doc_block/o) {
+ $state = 4;
+ $contents = "";
+ if ( $1 eq "" ) {
+ $section = $section_intro;
+ } else {
+ $section = $1;
+ }
+ }
+ elsif (/$doc_decl/o) {
+ $identifier = $1;
+ if (/\s*([\w\s]+?)\s*-/) {
+ $identifier = $1;
+ }
+
+ $state = 2;
+ if (/-(.*)/) {
+ # strip leading/trailing/multiple spaces
+ $descr= $1;
+ $descr =~ s/^\s*//;
+ $descr =~ s/\s*$//;
+ $descr =~ s/\s+/ /;
+ $declaration_purpose = xml_escape($descr);
+ $in_purpose = 1;
+ } else {
+ $declaration_purpose = "";
+ }
+
+ if (($declaration_purpose eq "") && $verbose) {
+ print STDERR "Warning(${file}:$.): missing initial short description on line:\n";
+ print STDERR $_;
+ ++$warnings;
+ }
+
+ if ($identifier =~ m/^struct/) {
+ $decl_type = 'struct';
+ } elsif ($identifier =~ m/^union/) {
+ $decl_type = 'union';
+ } elsif ($identifier =~ m/^enum/) {
+ $decl_type = 'enum';
+ } elsif ($identifier =~ m/^typedef/) {
+ $decl_type = 'typedef';
+ } else {
+ $decl_type = 'function';
+ }
+
+ if ($verbose) {
+ print STDERR "Info(${file}:$.): Scanning doc for $identifier\n";
+ }
+ } else {
+ print STDERR "Warning(${file}:$.): Cannot understand $_ on line $.",
+ " - I thought it was a doc line\n";
+ ++$warnings;
+ $state = 0;
+ }
+ } elsif ($state == 2) { # look for head: lines, and include content
+ if (/$doc_sect/o) {
+ $newsection = $1;
+ $newcontents = $2;
+
+ if (($contents ne "") && ($contents ne "\n")) {
+ if (!$in_doc_sect && $verbose) {
+ print STDERR "Warning(${file}:$.): contents before sections\n";
+ ++$warnings;
+ }
+ dump_section($file, $section, xml_escape($contents));
+ $section = $section_default;
+ }
+
+ $in_doc_sect = 1;
+ $in_purpose = 0;
+ $contents = $newcontents;
+ if ($contents ne "") {
+ while ((substr($contents, 0, 1) eq " ") ||
+ substr($contents, 0, 1) eq "\t") {
+ $contents = substr($contents, 1);
+ }
+ $contents .= "\n";
+ }
+ $section = $newsection;
+ } elsif (/$doc_end/) {
+
+ if (($contents ne "") && ($contents ne "\n")) {
+ dump_section($file, $section, xml_escape($contents));
+ $section = $section_default;
+ $contents = "";
+ }
+ # look for doc_com + <text> + doc_end:
+ if ($_ =~ m'\s*\*\s*[a-zA-Z_0-9:\.]+\*/') {
+ print STDERR "Warning(${file}:$.): suspicious ending line: $_";
+ ++$warnings;
+ }
+
+ $prototype = "";
+ $state = 3;
+ $brcount = 0;
+# print STDERR "end of doc comment, looking for prototype\n";
+ } elsif (/$doc_content/) {
+ # miguel-style comment kludge, look for blank lines after
+ # @parameter line to signify start of description
+ if ($1 eq "") {
+ if ($section =~ m/^@/ || $section eq $section_context) {
+ dump_section($file, $section, xml_escape($contents));
+ $section = $section_default;
+ $contents = "";
+ } else {
+ $contents .= "\n";
+ }
+ $in_purpose = 0;
+ } elsif ($in_purpose == 1) {
+ # Continued declaration purpose
+ chomp($declaration_purpose);
+ $declaration_purpose .= " " . xml_escape($1);
+ } elsif ($section =~ m/^Example/) {
+ $_ =~ s/^\s*\*//;
+ $contents .= $_;
+ } else {
+ $contents .= $1 . "\n";
+ }
+ } else {
+ # i dont know - bad line? ignore.
+ print STDERR "Warning(${file}:$.): bad line: $_";
+ ++$warnings;
+ }
+ } elsif ($state == 3) { # scanning for function '{' (end of prototype)
+ if ($decl_type eq 'function') {
+ process_state3_function($_, $file);
+ } else {
+ process_state3_type($_, $file);
+ }
+ } elsif ($state == 4) {
+ # Documentation block
+ if (/$doc_block/) {
+ dump_doc_section($file, $section, xml_escape($contents));
+ $contents = "";
+ $function = "";
+ %constants = ();
+ %parameterdescs = ();
+ %parametertypes = ();
+ @parameterlist = ();
+ %sections = ();
+ @sectionlist = ();
+ $prototype = "";
+ if ( $1 eq "" ) {
+ $section = $section_intro;
+ } else {
+ $section = $1;
+ }
+ }
+ elsif (/$doc_end/)
+ {
+ dump_doc_section($file, $section, xml_escape($contents));
+ $contents = "";
+ $function = "";
+ %constants = ();
+ %parameterdescs = ();
+ %parametertypes = ();
+ @parameterlist = ();
+ %sections = ();
+ @sectionlist = ();
+ $prototype = "";
+ $state = 0;
+ }
+ elsif (/$doc_content/)
+ {
+ if ( $1 eq "" )
+ {
+ $contents .= $blankline;
+ }
+ else
+ {
+ $contents .= $1 . "\n";
+ }
+ }
+ }
+ }
+ if ($initial_section_counter == $section_counter) {
+ print STDERR "Warning(${file}): no structured comments found\n";
+ if ($output_mode eq "xml") {
+ # The template wants at least one RefEntry here; make one.
+ print "<refentry>\n";
+ print " <refnamediv>\n";
+ print " <refname>\n";
+ print " ${file}\n";
+ print " </refname>\n";
+ print " <refpurpose>\n";
+ print " Document generation inconsistency\n";
+ print " </refpurpose>\n";
+ print " </refnamediv>\n";
+ print " <refsect1>\n";
+ print " <title>\n";
+ print " Oops\n";
+ print " </title>\n";
+ print " <warning>\n";
+ print " <para>\n";
+ print " The template for this document tried to insert\n";
+ print " the structured comment from the file\n";
+ print " <filename>${file}</filename> at this point,\n";
+ print " but none was found.\n";
+ print " This dummy section is inserted to allow\n";
+ print " generation to continue.\n";
+ print " </para>\n";
+ print " </warning>\n";
+ print " </refsect1>\n";
+ print "</refentry>\n";
+ }
+ }
+}
+
+
+$kernelversion = get_kernel_version();
+
+# generate a sequence of code that will splice in highlighting information
+# using the s// operator.
+foreach my $pattern (keys %highlights) {
+# print STDERR "scanning pattern:$pattern, highlight:($highlights{$pattern})\n";
+ $dohighlight .= "\$contents =~ s:$pattern:$highlights{$pattern}:gs;\n";
+}
+
+# Read the file that maps relative names to absolute names for
+# separate source and object directories and for shadow trees.
+if (open(SOURCE_MAP, "<.tmp_filelist.txt")) {
+ my ($relname, $absname);
+ while(<SOURCE_MAP>) {
+ chop();
+ ($relname, $absname) = (split())[0..1];
+ $relname =~ s:^/+::;
+ $source_map{$relname} = $absname;
+ }
+ close(SOURCE_MAP);
+}
+
+foreach (@ARGV) {
+ chomp;
+ process_file($_);
+}
+if ($verbose && $errors) {
+ print STDERR "$errors errors\n";
+}
+if ($verbose && $warnings) {
+ print STDERR "$warnings warnings\n";
+}
+
+exit($errors);
Sets the subject prefix. Normally empty but it can be RFC for
RFC patches, or RESEND if you are being ignored.
+Series-name: name
+ Sets the name of the series. You don't need to have a name, and
+ patman does not yet use it, but it is convenient to put the branch
+ name here to help you keep track of multiple upstreaming efforts.
+
Cover-letter:
This is the patch set title
blah blah
if len(problems) != error_count + warning_count:
print "Internal error: some problems lost"
for item in problems:
- print GetWarningMsg(col, item['type'], item['file'],
- item['line'], item['msg'])
+ print GetWarningMsg(col, item['type'],
+ item.get('file', '<unknown>'),
+ item.get('line', 0), item['msg'])
#print stdout
if error_count != 0 or warning_count != 0:
str = 'checkpatch.pl found %d error(s), %d warning(s)' % (
import terminal
# Series-xxx tags that we understand
-valid_series = ['to', 'cc', 'version', 'changes', 'prefix', 'notes'];
+valid_series = ['to', 'cc', 'version', 'changes', 'prefix', 'notes', 'name'];
class Series(dict):
"""Holds information about a patch series, including all tags.
self[name] = value
else:
raise ValueError("In %s: line '%s': Unknown 'Series-%s': valid "
- "options are %s" % (self.commit.hash, line, name,
+ "options are %s" % (commit.hash, line, name,
', '.join(valid_series)))
def AddCommit(self, commit):
projects / platform / kernel / u-boot.git / commitdiff