config ARM64
bool
+config HAS_VBAR
+ bool
+
+config CPU_ARM720T
+ bool
+
+config CPU_ARM920T
+ bool
+
+config CPU_ARM926EJS
+ bool
+
+config CPU_ARM946ES
+ bool
+
+config CPU_ARM1136
+ bool
+
+config CPU_ARM1176
+ bool
+ select HAS_VBAR
+
+config CPU_V7
+ bool
+ select HAS_VBAR
+
+config CPU_PXA
+ bool
+
+config CPU_SA1100
+ bool
+
+config SYS_CPU
+ default "arm720t" if CPU_ARM720T
+ default "arm920t" if CPU_ARM920T
+ default "arm926ejs" if CPU_ARM926EJS
+ default "arm946es" if CPU_ARM946ES
+ default "arm1136" if CPU_ARM1136
+ default "arm1176" if CPU_ARM1176
+ default "armv7" if CPU_V7
+ default "pxa" if CPU_PXA
+ default "sa1100" if CPU_SA1100
+
choice
prompt "Target select"
config TARGET_INTEGRATORAP_CM720T
bool "Support integratorap_cm720t"
+ select CPU_ARM720T
config TARGET_INTEGRATORAP_CM920T
bool "Support integratorap_cm920t"
+ select CPU_ARM920T
config TARGET_INTEGRATORCP_CM920T
bool "Support integratorcp_cm920t"
+ select CPU_ARM920T
config TARGET_A320EVB
bool "Support a320evb"
+ select CPU_ARM920T
config TARGET_AT91RM9200EK
bool "Support at91rm9200ek"
+ select CPU_ARM920T
config TARGET_EB_CPUX9K2
bool "Support eb_cpux9k2"
+ select CPU_ARM920T
config TARGET_CPUAT91
bool "Support cpuat91"
+ select CPU_ARM920T
config TARGET_EDB93XX
bool "Support edb93xx"
+ select CPU_ARM920T
config TARGET_SCB9328
bool "Support scb9328"
+ select CPU_ARM920T
config TARGET_CM4008
bool "Support cm4008"
+ select CPU_ARM920T
config TARGET_CM41XX
bool "Support cm41xx"
+ select CPU_ARM920T
config TARGET_VCMA9
bool "Support VCMA9"
+ select CPU_ARM920T
config TARGET_SMDK2410
bool "Support smdk2410"
+ select CPU_ARM920T
config TARGET_INTEGRATORAP_CM926EJS
bool "Support integratorap_cm926ejs"
+ select CPU_ARM926EJS
config TARGET_INTEGRATORCP_CM926EJS
bool "Support integratorcp_cm926ejs"
+ select CPU_ARM926EJS
config TARGET_ASPENITE
bool "Support aspenite"
+ select CPU_ARM926EJS
config TARGET_GPLUGD
bool "Support gplugd"
+ select CPU_ARM926EJS
config TARGET_AFEB9260
bool "Support afeb9260"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9260EK
bool "Support at91sam9260ek"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9261EK
bool "Support at91sam9261ek"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9263EK
bool "Support at91sam9263ek"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9M10G45EK
bool "Support at91sam9m10g45ek"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9N12EK
bool "Support at91sam9n12ek"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9RLEK
bool "Support at91sam9rlek"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9X5EK
bool "Support at91sam9x5ek"
+ select CPU_ARM926EJS
config TARGET_SNAPPER9260
bool "Support snapper9260"
+ select CPU_ARM926EJS
config TARGET_VL_MA2SC
bool "Support vl_ma2sc"
+ select CPU_ARM926EJS
config TARGET_SBC35_A9G20
bool "Support sbc35_a9g20"
+ select CPU_ARM926EJS
config TARGET_TNY_A9260
bool "Support tny_a9260"
+ select CPU_ARM926EJS
config TARGET_USB_A9263
bool "Support usb_a9263"
+ select CPU_ARM926EJS
config TARGET_ETHERNUT5
bool "Support ethernut5"
+ select CPU_ARM926EJS
config TARGET_TOP9000
bool "Support top9000"
+ select CPU_ARM926EJS
config TARGET_MEESC
bool "Support meesc"
+ select CPU_ARM926EJS
config TARGET_OTC570
bool "Support otc570"
+ select CPU_ARM926EJS
config TARGET_CPU9260
bool "Support cpu9260"
+ select CPU_ARM926EJS
config TARGET_PM9261
bool "Support pm9261"
+ select CPU_ARM926EJS
config TARGET_PM9263
bool "Support pm9263"
+ select CPU_ARM926EJS
config TARGET_PM9G45
bool "Support pm9g45"
+ select CPU_ARM926EJS
config TARGET_CORVUS
bool "Support corvus"
+ select CPU_ARM926EJS
config TARGET_TAURUS
bool "Support taurus"
+ select CPU_ARM926EJS
config TARGET_STAMP9G20
bool "Support stamp9g20"
+ select CPU_ARM926EJS
config ARCH_DAVINCI
bool "TI DaVinci"
+ select CPU_ARM926EJS
help
Support for TI's DaVinci platform.
config KIRKWOOD
bool "Marvell Kirkwood"
+ select CPU_ARM926EJS
config TARGET_DB_MV784MP_GP
bool "Support db-mv784mp-gp"
config TARGET_DEVKIT3250
bool "Support devkit3250"
+ select CPU_ARM926EJS
config TARGET_JADECPU
bool "Support jadecpu"
+ select CPU_ARM926EJS
config TARGET_MX25PDK
bool "Support mx25pdk"
+ select CPU_ARM926EJS
config TARGET_TX25
bool "Support tx25"
+ select CPU_ARM926EJS
select SUPPORT_SPL
config TARGET_ZMX25
bool "Support zmx25"
+ select CPU_ARM926EJS
config TARGET_APF27
bool "Support apf27"
+ select CPU_ARM926EJS
select SUPPORT_SPL
config TARGET_IMX27LITE
bool "Support imx27lite"
+ select CPU_ARM926EJS
config TARGET_MAGNESIUM
bool "Support magnesium"
+ select CPU_ARM926EJS
config TARGET_APX4DEVKIT
bool "Support apx4devkit"
+ select CPU_ARM926EJS
select SUPPORT_SPL
config TARGET_XFI3
bool "Support xfi3"
+ select CPU_ARM926EJS
select SUPPORT_SPL
config TARGET_M28EVK
bool "Support m28evk"
+ select CPU_ARM926EJS
select SUPPORT_SPL
config TARGET_MX23EVK
bool "Support mx23evk"
+ select CPU_ARM926EJS
select SUPPORT_SPL
config TARGET_MX28EVK
bool "Support mx28evk"
+ select CPU_ARM926EJS
select SUPPORT_SPL
config TARGET_MX23_OLINUXINO
bool "Support mx23_olinuxino"
+ select CPU_ARM926EJS
select SUPPORT_SPL
config TARGET_BG0900
bool "Support bg0900"
+ select CPU_ARM926EJS
select SUPPORT_SPL
config TARGET_SANSA_FUZE_PLUS
bool "Support sansa_fuze_plus"
+ select CPU_ARM926EJS
select SUPPORT_SPL
config TARGET_SC_SPS_1
bool "Support sc_sps_1"
+ select CPU_ARM926EJS
select SUPPORT_SPL
config ARCH_NOMADIK
bool "ST-Ericsson Nomadik"
+ select CPU_ARM926EJS
config ORION5X
bool "Marvell Orion"
+ select CPU_ARM926EJS
config TARGET_DKB
bool "Support dkb"
+ select CPU_ARM926EJS
config TARGET_SPEAR300
bool "Support spear300"
+ select CPU_ARM926EJS
config TARGET_SPEAR310
bool "Support spear310"
+ select CPU_ARM926EJS
config TARGET_SPEAR320
bool "Support spear320"
+ select CPU_ARM926EJS
config TARGET_SPEAR600
bool "Support spear600"
+ select CPU_ARM926EJS
config TARGET_X600
bool "Support x600"
+ select CPU_ARM926EJS
select SUPPORT_SPL
config ARCH_VERSATILE
bool "ARM Ltd. Versatile family"
+ select CPU_ARM926EJS
config TARGET_INTEGRATORCP_CM1136
bool "Support integratorcp_cm1136"
+ select CPU_ARM1136
config TARGET_IMX31_PHYCORE
bool "Support imx31_phycore"
+ select CPU_ARM1136
config TARGET_QONG
bool "Support qong"
+ select CPU_ARM1136
config TARGET_MX31ADS
bool "Support mx31ads"
+ select CPU_ARM1136
config TARGET_MX31PDK
bool "Support mx31pdk"
+ select CPU_ARM1136
select SUPPORT_SPL
config TARGET_TT01
bool "Support tt01"
+ select CPU_ARM1136
config TARGET_IMX31_LITEKIT
bool "Support imx31_litekit"
+ select CPU_ARM1136
config TARGET_WOODBURN
bool "Support woodburn"
+ select CPU_ARM1136
config TARGET_WOODBURN_SD
bool "Support woodburn_sd"
+ select CPU_ARM1136
select SUPPORT_SPL
config TARGET_FLEA3
bool "Support flea3"
+ select CPU_ARM1136
config TARGET_MX35PDK
bool "Support mx35pdk"
+ select CPU_ARM1136
config TARGET_RPI_B
bool "Support rpi_b"
+ select CPU_ARM1176
config TARGET_TNETV107X_EVM
bool "Support tnetv107x_evm"
+ select CPU_ARM1176
config TARGET_INTEGRATORAP_CM946ES
bool "Support integratorap_cm946es"
+ select CPU_ARM946ES
config TARGET_INTEGRATORCP_CM946ES
bool "Support integratorcp_cm946es"
+ select CPU_ARM946ES
config TARGET_VEXPRESS_CA15_TC2
bool "Support vexpress_ca15_tc2"
+ select CPU_V7
config TARGET_VEXPRESS_CA5X2
bool "Support vexpress_ca5x2"
+ select CPU_V7
config TARGET_VEXPRESS_CA9X4
bool "Support vexpress_ca9x4"
+ select CPU_V7
config TARGET_KWB
bool "Support kwb"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_TSERIES
bool "Support tseries"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_CM_T335
bool "Support cm_t335"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_PEPPER
bool "Support pepper"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_AM335X_IGEP0033
bool "Support am335x_igep0033"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_PCM051
bool "Support pcm051"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_DRACO
bool "Support draco"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_DXR2
bool "Support dxr2"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_PXM2
bool "Support pxm2"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_RUT
bool "Support rut"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_PENGWYN
bool "Support pengwyn"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_AM335X_EVM
bool "Support am335x_evm"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_AM43XX_EVM
bool "Support am43xx_evm"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_TI814X_EVM
bool "Support ti814x_evm"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_TI816X_EVM
bool "Support ti816x_evm"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_SAMA5D3_XPLAINED
bool "Support sama5d3_xplained"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_SAMA5D3XEK
bool "Support sama5d3xek"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_BCM28155_AP
bool "Support bcm28155_ap"
+ select CPU_V7
config TARGET_BCM958300K
bool "Support bcm958300k"
+ select CPU_V7
config TARGET_BCM958622HR
bool "Support bcm958622hr"
+ select CPU_V7
config ARCH_EXYNOS
bool "Samsung EXYNOS"
+ select CPU_V7
config ARCH_S5PC1XX
bool "Samsung S5PC1XX"
+ select CPU_V7
config ARCH_HIGHBANK
bool "Calxeda Highbank"
+ select CPU_V7
config ARCH_KEYSTONE
bool "TI Keystone"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_M53EVK
bool "Support m53evk"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_IMA3_MX53
bool "Support ima3-mx53"
+ select CPU_V7
config TARGET_MX51EVK
bool "Support mx51evk"
+ select CPU_V7
config TARGET_MX53ARD
bool "Support mx53ard"
+ select CPU_V7
config TARGET_MX53EVK
bool "Support mx53evk"
+ select CPU_V7
config TARGET_MX53LOCO
bool "Support mx53loco"
+ select CPU_V7
config TARGET_MX53SMD
bool "Support mx53smd"
+ select CPU_V7
config TARGET_MX51_EFIKAMX
bool "Support mx51_efikamx"
+ select CPU_V7
config TARGET_VISION2
bool "Support vision2"
+ select CPU_V7
config TARGET_UDOO
bool "Support udoo"
+ select CPU_V7
config TARGET_WANDBOARD
bool "Support wandboard"
+ select CPU_V7
config TARGET_TITANIUM
bool "Support titanium"
+ select CPU_V7
config TARGET_NITROGEN6X
bool "Support nitrogen6x"
+ select CPU_V7
config TARGET_CGTQMX6EVAL
bool "Support cgtqmx6eval"
+ select CPU_V7
config TARGET_EMBESTMX6BOARDS
bool "Support embestmx6boards"
+ select CPU_V7
config TARGET_ARISTAINETOS
bool "Support aristainetos"
+ select CPU_V7
config TARGET_MX6QARM2
bool "Support mx6qarm2"
+ select CPU_V7
config TARGET_MX6QSABREAUTO
bool "Support mx6qsabreauto"
+ select CPU_V7
config TARGET_MX6SABRESD
bool "Support mx6sabresd"
+ select CPU_V7
config TARGET_MX6SLEVK
bool "Support mx6slevk"
+ select CPU_V7
config TARGET_MX6SXSABRESD
bool "Support mx6sxsabresd"
+ select CPU_V7
config TARGET_GW_VENTANA
bool "Support gw_ventana"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_HUMMINGBOARD
bool "Support hummingboard"
+ select CPU_V7
config TARGET_TQMA6
bool "TQ Systems TQMa6 board"
+ select CPU_V7
config TARGET_OT1200
bool "Bachmann OT1200"
+ select CPU_V7
config OMAP34XX
bool "OMAP34XX SoC"
+ select CPU_V7
config OMAP44XX
bool "OMAP44XX SoC"
+ select CPU_V7
select SUPPORT_SPL
config OMAP54XX
bool "OMAP54XX SoC"
+ select CPU_V7
select SUPPORT_SPL
config RMOBILE
bool "Renesas ARM SoCs"
+ select CPU_V7
config TARGET_CM_FX6
bool "Support cm_fx6"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_SOCFPGA_CYCLONE5
bool "Support socfpga_cyclone5"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_SUN4I
bool "Support sun4i"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_SUN5I
bool "Support sun5i"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_SUN6I
bool "Support sun6i"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_SUN7I
bool "Support sun7i"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_SUN8I
bool "Support sun8i"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_SNOWBALL
bool "Support snowball"
+ select CPU_V7
config TARGET_U8500_HREF
bool "Support u8500_href"
+ select CPU_V7
config TARGET_VF610TWR
bool "Support vf610twr"
+ select CPU_V7
config ZYNQ
bool "Xilinx Zynq Platform"
+ select CPU_V7
select SUPPORT_SPL
config TEGRA
select SUPPORT_SPL
select SPL
select OF_CONTROL if !SPL_BUILD
+ select CPU_ARM720T if SPL_BUILD
+ select CPU_V7 if !SPL_BUILD
config TARGET_VEXPRESS_AEMV8A
bool "Support vexpress_aemv8a"
config TARGET_LS1021AQDS
bool "Support ls1021aqds_nor"
+ select CPU_V7
config TARGET_LS1021ATWR
bool "Support ls1021atwr_nor"
+ select CPU_V7
config TARGET_BALLOON3
bool "Support balloon3"
+ select CPU_PXA
config TARGET_H2200
bool "Support h2200"
+ select CPU_PXA
config TARGET_PALMLD
bool "Support palmld"
+ select CPU_PXA
config TARGET_PALMTC
bool "Support palmtc"
+ select CPU_PXA
config TARGET_PALMTREO680
bool "Support palmtreo680"
+ select CPU_PXA
select SUPPORT_SPL
config TARGET_PXA255_IDP
bool "Support pxa255_idp"
+ select CPU_PXA
config TARGET_TRIZEPSIV
bool "Support trizepsiv"
+ select CPU_PXA
config TARGET_VPAC270
bool "Support vpac270"
+ select CPU_PXA
select SUPPORT_SPL
config TARGET_XAENIAX
bool "Support xaeniax"
+ select CPU_PXA
config TARGET_ZIPITZ2
bool "Support zipitz2"
+ select CPU_PXA
config TARGET_LP8X4X
bool "Support lp8x4x"
+ select CPU_PXA
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
+ select CPU_PXA
config TARGET_JORNADA
bool "Support jornada"
+ select CPU_SA1100
config ARCH_UNIPHIER
bool "Panasonic UniPhier platform"
+ select CPU_V7
select SUPPORT_SPL
endchoice
endchoice
-config SYS_CPU
- default "arm926ejs"
-
config SYS_SOC
default "davinci"
endchoice
-config SYS_CPU
- default "arm926ejs"
-
config SYS_SOC
default "kirkwood"
endchoice
-config SYS_CPU
- default "arm926ejs"
-
config SYS_SOC
default "nomadik"
endchoice
-config SYS_CPU
- default "arm926ejs"
-
config SYS_SOC
default "orion5x"
#if defined(CONFIG_DW_UDC)
periph1_clken |= MISC_USBDENB;
#endif
-#if defined(CONFIG_DW_I2C)
+#if defined(CONFIG_SYS_I2C_DW)
periph1_clken |= MISC_I2CENB;
#endif
#if defined(CONFIG_ST_SMI)
if ARCH_VERSATILE
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "versatile"
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_SOC
default "exynos"
if ARCH_HIGHBANK
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "highbank"
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_SOC
default "keystone"
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_SOC
default "omap3"
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_SOC
default "omap4"
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_SOC
default "omap5"
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_SOC
default "rmobile"
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_SOC
default "s5pc1xx"
mcr p15, 0, r0, c7, c10, 4 @ DSB
mcr p15, 0, r0, c7, c5, 4 @ ISB
#endif
-/*
- * Move vector table
- */
- /* Set vector address in CP15 VBAR register */
- ldr r0, =_start
- mcr p15, 0, r0, c12, c0, 0 @Set VBAR
bx lr
menu "Panasonic UniPhier platform"
depends on ARCH_UNIPHIER
-config SYS_CPU
- string
- default "armv7"
-
config SYS_SOC
- string
default "uniphier"
config SYS_CONFIG_NAME
- string
default "ph1_pro4" if MACH_PH1_PRO4
default "ph1_ld4" if MACH_PH1_LD4
default "ph1_sld8" if MACH_PH1_SLD8
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "zynq"
#ifdef CONFIG_USE_IRQ
int interrupt_init (void)
{
+ unsigned long cpsr;
+
/*
* setup up stacks if necessary
*/
IRQ_STACK_START_IN = gd->irq_sp + 8;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
+
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ : "=r" (cpsr)
+ :
+ : "memory");
+
+ __asm__ __volatile__("msr cpsr_c, %0\n"
+ "mov sp, %1\n"
+ :
+ : "r" (IRQ_MODE | I_BIT | F_BIT | (cpsr & ~FIQ_MODE)),
+ "r" (IRQ_STACK_START)
+ : "memory");
+
+ __asm__ __volatile__("msr cpsr_c, %0\n"
+ "mov sp, %1\n"
+ :
+ : "r" (FIQ_MODE | I_BIT | F_BIT | (cpsr & ~IRQ_MODE)),
+ "r" (FIQ_STACK_START)
+ : "memory");
+
+ __asm__ __volatile__("msr cpsr_c, %0"
+ :
+ : "r" (cpsr)
+ : "memory");
+
return arch_interrupt_init();
}
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <asm-offsets.h>
+#include <config.h>
#include <linux/linkage.h>
/*
cmp r2, r3
blo fixloop
+ /*
+ * Relocate the exception vectors
+ */
+#ifdef CONFIG_HAS_VBAR
+ /*
+ * If the ARM processor has the security extensions,
+ * use VBAR to relocate the exception vectors.
+ */
+ ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
+ mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
+#else
+ /*
+ * Copy the relocated exception vectors to the
+ * correct address
+ * CP15 c1 V bit gives us the location of the vectors:
+ * 0x00000000 or 0xFFFF0000.
+ */
+ ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
+ mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */
+ ands r2, r2, #(1 << 13)
+ ldreq r1, =0x00000000 /* If V=0 */
+ ldrne r1, =0xFFFF0000 /* If V=1 */
+ ldmia r0!, {r2-r8,r10}
+ stmia r1!, {r2-r8,r10}
+ ldmia r0!, {r2-r8,r10}
+ stmia r1!, {r2-r8,r10}
+#endif
+
relocate_done:
#ifdef __XSCALE__
*************************************************************************
*/
- .section ".vectors", "x"
+ .section ".vectors", "ax"
/*
*************************************************************************
if TARGET_KWB
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "kwb"
if TARGET_TSERIES
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "tseries"
if TARGET_EB_CPUX9K2
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "eb_cpux9k2"
if TARGET_VL_MA2SC
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "vl_ma2sc"
if TARGET_FLEA3
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "flea3"
if TARGET_ASPENITE
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "aspenite"
if TARGET_DKB
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "dkb"
if TARGET_GPLUGD
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "gplugd"
if TARGET_AFEB9260
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "afeb9260"
if TARGET_SOCFPGA_CYCLONE5
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "socfpga"
if TARGET_ARISTAINETOS
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "aristainetos"
if TARGET_APF27
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "apf27"
if TARGET_INTEGRATORAP_CM720T
-config SYS_CPU
- default "arm720t"
-
config SYS_BOARD
default "integrator"
if TARGET_INTEGRATORAP_CM920T
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "integrator"
if TARGET_INTEGRATORCP_CM920T
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "integrator"
if TARGET_INTEGRATORAP_CM926EJS
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "integrator"
if TARGET_INTEGRATORCP_CM926EJS
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "integrator"
if TARGET_INTEGRATORCP_CM1136
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "integrator"
if TARGET_INTEGRATORAP_CM946ES
-config SYS_CPU
- default "arm946es"
-
config SYS_BOARD
default "integrator"
if TARGET_INTEGRATORCP_CM946ES
-config SYS_CPU
- default "arm946es"
-
config SYS_BOARD
default "integrator"
if TARGET_VEXPRESS_CA15_TC2
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "vexpress"
if TARGET_VEXPRESS_CA5X2
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "vexpress"
if TARGET_VEXPRESS_CA9X4
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "vexpress"
if TARGET_AT91RM9200EK
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "at91rm9200ek"
if TARGET_AT91SAM9260EK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "at91sam9260ek"
if TARGET_AT91SAM9261EK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "at91sam9261ek"
if TARGET_AT91SAM9263EK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "at91sam9263ek"
if TARGET_AT91SAM9M10G45EK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "at91sam9m10g45ek"
if TARGET_AT91SAM9N12EK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "at91sam9n12ek"
if TARGET_AT91SAM9RLEK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "at91sam9rlek"
if TARGET_AT91SAM9X5EK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "at91sam9x5ek"
if TARGET_SAMA5D3_XPLAINED
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "sama5d3_xplained"
if TARGET_SAMA5D3XEK
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "sama5d3xek"
if TARGET_OT1200
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "ot1200"
if TARGET_BALLOON3
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "balloon3"
if TARGET_TITANIUM
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "titanium"
if TARGET_APX4DEVKIT
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "apx4devkit"
if TARGET_SNAPPER9260
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "snapper9260"
if TARGET_NITROGEN6X
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "nitrogen6x"
if TARGET_BCM28155_AP
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "bcm28155_ap"
if TARGET_BCM958300K
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "bcm_ep"
if TARGET_BCM958622HR
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "bcm_ep"
if TARGET_SBC35_A9G20
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "sbc35_a9g20"
if TARGET_TNY_A9260
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "tny_a9260"
if TARGET_USB_A9263
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "usb_a9263"
if TARGET_EDB93XX
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "edb93xx"
if TARGET_CM4008
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "cm4008"
if TARGET_CM41XX
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "cm41xx"
if TARGET_CM_FX6
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
- string
default "cm_fx6"
config SYS_VENDOR
- string
default "compulab"
config SYS_SOC
- string
default "mx6"
config SYS_CONFIG_NAME
- string
default "cm_fx6"
endif
if TARGET_CM_T335
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "cm_t335"
if TARGET_CGTQMX6EVAL
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "cgtqmx6eval"
if TARGET_XFI3
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "xfi3"
if TARGET_QONG
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "qong"
if TARGET_M28EVK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "m28evk"
if TARGET_M53EVK
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "m53evk"
if TARGET_ETHERNUT5
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "ethernut5"
if TARGET_EMBESTMX6BOARDS
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx6boards"
if TARGET_MEESC
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "meesc"
if TARGET_OTC570
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "otc570"
if TARGET_IMA3_MX53
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "ima3-mx53"
if TARGET_CPU9260
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "cpu9260"
if TARGET_CPUAT91
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "cpuat91"
if TARGET_A320EVB
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "a320evb"
if TARGET_LS1021AQDS
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "ls1021aqds"
if TARGET_LS1021ATWR
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "ls1021atwr"
if TARGET_MX23EVK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "mx23evk"
if TARGET_MX25PDK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "mx25pdk"
if TARGET_MX28EVK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "mx28evk"
if TARGET_MX31ADS
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "mx31ads"
if TARGET_MX31PDK
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "mx31pdk"
if TARGET_MX35PDK
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "mx35pdk"
if TARGET_MX51EVK
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx51evk"
if TARGET_MX53ARD
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx53ard"
if TARGET_MX53EVK
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx53evk"
if TARGET_MX53LOCO
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx53loco"
if TARGET_MX53SMD
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx53smd"
if TARGET_MX6QARM2
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx6qarm2"
if TARGET_MX6QSABREAUTO
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx6qsabreauto"
if TARGET_MX6SABRESD
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx6sabresd"
if TARGET_MX6SLEVK
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx6slevk"
if TARGET_MX6SXSABRESD
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx6sxsabresd"
if TARGET_VF610TWR
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "vf610twr"
if TARGET_GW_VENTANA
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "gw_ventana"
if TARGET_MX51_EFIKAMX
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx51_efikamx"
if TARGET_PEPPER
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "pepper"
if TARGET_H2200
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "h2200"
if TARGET_TT01
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "tt01"
if TARGET_LP8X4X
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "lp8x4x"
if TARGET_IMX31_PHYCORE
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "imx31_phycore"
if TARGET_AM335X_IGEP0033
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "igep0033"
if TARGET_JORNADA
-config SYS_CPU
- default "sa1100"
-
config SYS_BOARD
default "jornada"
if TARGET_TX25
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "tx25"
if TARGET_IMX27LITE
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "imx27lite"
if TARGET_MAGNESIUM
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "imx27lite"
if TARGET_IMX31_LITEKIT
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "imx31_litekit"
if TARGET_VCMA9
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "vcma9"
if TARGET_MX23_OLINUXINO
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "mx23_olinuxino"
if TARGET_PALMLD
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "palmld"
if TARGET_PALMTC
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "palmtc"
if TARGET_PALMTREO680
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "palmtreo680"
if TARGET_PCM051
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "pcm051"
if TARGET_BG0900
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "bg0900"
if TARGET_PXA255_IDP
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "pxa255_idp"
if TARGET_RPI_B
-config SYS_CPU
- default "arm1176"
-
config SYS_BOARD
default "rpi_b"
if TARGET_PM9261
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "pm9261"
if TARGET_PM9263
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "pm9263"
if TARGET_PM9G45
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "pm9g45"
if TARGET_S5P_GONI
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "goni"
if TARGET_SMDK2410
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "smdk2410"
if TARGET_SMDKC100
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "smdkc100"
if TARGET_SANSA_FUZE_PLUS
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "sansa_fuze_plus"
if TARGET_SCB9328
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "scb9328"
if TARGET_SC_SPS_1
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "sc_sps_1"
if TARGET_CORVUS
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "corvus"
if TARGET_DRACO
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "draco"
if TARGET_DXR2
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "draco"
if TARGET_PXM2
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "pxm2"
if TARGET_RUT
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "rut"
if TARGET_TAURUS
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "taurus"
if TARGET_PENGWYN
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "pengwyn"
if TARGET_HUMMINGBOARD
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "hummingboard"
if TARGET_SPEAR300
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "spear300"
if TARGET_SPEAR310
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "spear310"
if TARGET_SPEAR320
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "spear320"
if TARGET_SPEAR600
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "spear600"
if TARGET_X600
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "x600"
if TARGET_SNOWBALL
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "snowball"
if TARGET_U8500_HREF
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "u8500"
default "sun7i" if TARGET_SUN7I
default "sun8i" if TARGET_SUN8I
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "sunxi"
if TARGET_JADECPU
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "jadecpu"
if TARGET_ZMX25
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "zmx25"
if TARGET_STAMP9G20
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "stamp9g20"
if TARGET_AM335X_EVM
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "am335x"
if TARGET_AM43XX_EVM
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "am43xx"
if TARGET_TI814X_EVM
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "ti814x"
if TARGET_TI816X_EVM
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "ti816x"
if TARGET_TNETV107X_EVM
-config SYS_CPU
- default "arm1176"
-
config SYS_BOARD
default "tnetv107xevm"
if TARGET_DEVKIT3250
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "devkit3250"
if TARGET_COLIBRI_PXA270
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "colibri_pxa270"
if TARGET_TQMA6
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "tqma6"
if TARGET_TRIZEPSIV
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "trizepsiv"
if TARGET_VISION2
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "vision2"
if TARGET_UDOO
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "udoo"
if TARGET_VPAC270
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "vpac270"
if TARGET_WANDBOARD
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "wandboard"
if TARGET_WOODBURN
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "woodburn"
if TARGET_WOODBURN_SD
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "woodburn"
if TARGET_XAENIAX
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "xaeniax"
if TARGET_ZIPITZ2
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "zipitz2"
#if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
defined(CONFIG_CPU_MONAHANS)
-#define CONFIG_CPU_PXA
#include <asm/byteorder.h>
#endif
#
obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
-obj-$(CONFIG_DW_I2C) += designware_i2c.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
-obj-$(CONFIG_I2C_MXS) += mxs_i2c.o
obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
+obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
+obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
*/
#include <common.h>
+#include <i2c.h>
#include <asm/io.h>
#include "designware_i2c.h"
-#include <i2c.h>
-#ifdef CONFIG_I2C_MULTI_BUS
-static unsigned int bus_initialized[CONFIG_SYS_I2C_BUS_MAX];
-static unsigned int current_bus = 0;
+static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
+{
+ switch (adap->hwadapnr) {
+#if CONFIG_SYS_I2C_BUS_MAX >= 4
+ case 3:
+ return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
+#endif
+#if CONFIG_SYS_I2C_BUS_MAX >= 3
+ case 2:
+ return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
+#endif
+#if CONFIG_SYS_I2C_BUS_MAX >= 2
+ case 1:
+ return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
#endif
+ case 0:
+ return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
+ default:
+ printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
+ }
-static struct i2c_regs *i2c_regs_p =
- (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
+ return NULL;
+}
/*
* set_speed - Set the i2c speed mode (standard, high, fast)
*
* Set the i2c speed mode (standard, high, fast)
*/
-static void set_speed(int i2c_spd)
+static void set_speed(struct i2c_adapter *adap, int i2c_spd)
{
+ struct i2c_regs *i2c_base = i2c_get_base(adap);
unsigned int cntl;
unsigned int hcnt, lcnt;
unsigned int enbl;
/* to set speed cltr must be disabled */
- enbl = readl(&i2c_regs_p->ic_enable);
+ enbl = readl(&i2c_base->ic_enable);
enbl &= ~IC_ENABLE_0B;
- writel(enbl, &i2c_regs_p->ic_enable);
+ writel(enbl, &i2c_base->ic_enable);
- cntl = (readl(&i2c_regs_p->ic_con) & (~IC_CON_SPD_MSK));
+ cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
switch (i2c_spd) {
case IC_SPEED_MODE_MAX:
cntl |= IC_CON_SPD_HS;
hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
- writel(hcnt, &i2c_regs_p->ic_hs_scl_hcnt);
+ writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
- writel(lcnt, &i2c_regs_p->ic_hs_scl_lcnt);
+ writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
break;
case IC_SPEED_MODE_STANDARD:
cntl |= IC_CON_SPD_SS;
hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
- writel(hcnt, &i2c_regs_p->ic_ss_scl_hcnt);
+ writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
- writel(lcnt, &i2c_regs_p->ic_ss_scl_lcnt);
+ writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
break;
case IC_SPEED_MODE_FAST:
default:
cntl |= IC_CON_SPD_FS;
hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
- writel(hcnt, &i2c_regs_p->ic_fs_scl_hcnt);
+ writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
- writel(lcnt, &i2c_regs_p->ic_fs_scl_lcnt);
+ writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
break;
}
- writel(cntl, &i2c_regs_p->ic_con);
+ writel(cntl, &i2c_base->ic_con);
/* Enable back i2c now speed set */
enbl |= IC_ENABLE_0B;
- writel(enbl, &i2c_regs_p->ic_enable);
+ writel(enbl, &i2c_base->ic_enable);
}
/*
*
* Set the i2c speed.
*/
-int i2c_set_bus_speed(unsigned int speed)
+static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int speed)
{
int i2c_spd;
else
i2c_spd = IC_SPEED_MODE_STANDARD;
- set_speed(i2c_spd);
-
- return i2c_spd;
-}
-
-/*
- * i2c_get_bus_speed - Gets the i2c speed
- *
- * Gets the i2c speed.
- */
-unsigned int i2c_get_bus_speed(void)
-{
- u32 cntl;
-
- cntl = (readl(&i2c_regs_p->ic_con) & IC_CON_SPD_MSK);
-
- if (cntl == IC_CON_SPD_HS)
- return I2C_MAX_SPEED;
- else if (cntl == IC_CON_SPD_FS)
- return I2C_FAST_SPEED;
- else if (cntl == IC_CON_SPD_SS)
- return I2C_STANDARD_SPEED;
+ set_speed(adap, i2c_spd);
+ adap->speed = speed;
return 0;
}
/*
* i2c_init - Init function
* @speed: required i2c speed
- * @slaveadd: slave address for the device
+ * @slaveaddr: slave address for the device
*
* Initialization function.
*/
-void i2c_init(int speed, int slaveadd)
+static void dw_i2c_init(struct i2c_adapter *adap, int speed,
+ int slaveaddr)
{
+ struct i2c_regs *i2c_base = i2c_get_base(adap);
unsigned int enbl;
/* Disable i2c */
- enbl = readl(&i2c_regs_p->ic_enable);
+ enbl = readl(&i2c_base->ic_enable);
enbl &= ~IC_ENABLE_0B;
- writel(enbl, &i2c_regs_p->ic_enable);
+ writel(enbl, &i2c_base->ic_enable);
- writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_regs_p->ic_con);
- writel(IC_RX_TL, &i2c_regs_p->ic_rx_tl);
- writel(IC_TX_TL, &i2c_regs_p->ic_tx_tl);
- i2c_set_bus_speed(speed);
- writel(IC_STOP_DET, &i2c_regs_p->ic_intr_mask);
- writel(slaveadd, &i2c_regs_p->ic_sar);
+ writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
+ writel(IC_RX_TL, &i2c_base->ic_rx_tl);
+ writel(IC_TX_TL, &i2c_base->ic_tx_tl);
+ dw_i2c_set_bus_speed(adap, speed);
+ writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
+ writel(slaveaddr, &i2c_base->ic_sar);
/* Enable i2c */
- enbl = readl(&i2c_regs_p->ic_enable);
+ enbl = readl(&i2c_base->ic_enable);
enbl |= IC_ENABLE_0B;
- writel(enbl, &i2c_regs_p->ic_enable);
-
-#ifdef CONFIG_I2C_MULTI_BUS
- bus_initialized[current_bus] = 1;
-#endif
+ writel(enbl, &i2c_base->ic_enable);
}
/*
*
* Sets the target slave address.
*/
-static void i2c_setaddress(unsigned int i2c_addr)
+static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr)
{
+ struct i2c_regs *i2c_base = i2c_get_base(adap);
unsigned int enbl;
/* Disable i2c */
- enbl = readl(&i2c_regs_p->ic_enable);
+ enbl = readl(&i2c_base->ic_enable);
enbl &= ~IC_ENABLE_0B;
- writel(enbl, &i2c_regs_p->ic_enable);
+ writel(enbl, &i2c_base->ic_enable);
- writel(i2c_addr, &i2c_regs_p->ic_tar);
+ writel(i2c_addr, &i2c_base->ic_tar);
/* Enable i2c */
- enbl = readl(&i2c_regs_p->ic_enable);
+ enbl = readl(&i2c_base->ic_enable);
enbl |= IC_ENABLE_0B;
- writel(enbl, &i2c_regs_p->ic_enable);
+ writel(enbl, &i2c_base->ic_enable);
}
/*
*
* Flushes the i2c RX FIFO
*/
-static void i2c_flush_rxfifo(void)
+static void i2c_flush_rxfifo(struct i2c_adapter *adap)
{
- while (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE)
- readl(&i2c_regs_p->ic_cmd_data);
+ struct i2c_regs *i2c_base = i2c_get_base(adap);
+
+ while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
+ readl(&i2c_base->ic_cmd_data);
}
/*
*
* Waits for bus busy
*/
-static int i2c_wait_for_bb(void)
+static int i2c_wait_for_bb(struct i2c_adapter *adap)
{
+ struct i2c_regs *i2c_base = i2c_get_base(adap);
unsigned long start_time_bb = get_timer(0);
- while ((readl(&i2c_regs_p->ic_status) & IC_STATUS_MA) ||
- !(readl(&i2c_regs_p->ic_status) & IC_STATUS_TFE)) {
+ while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
+ !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
/* Evaluate timeout */
if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
return 0;
}
-static int i2c_xfer_init(uchar chip, uint addr, int alen)
+static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen)
{
- if (i2c_wait_for_bb())
+ struct i2c_regs *i2c_base = i2c_get_base(adap);
+
+ if (i2c_wait_for_bb(adap))
return 1;
- i2c_setaddress(chip);
+ i2c_setaddress(adap, chip);
while (alen) {
alen--;
/* high byte address going out first */
writel((addr >> (alen * 8)) & 0xff,
- &i2c_regs_p->ic_cmd_data);
+ &i2c_base->ic_cmd_data);
}
return 0;
}
-static int i2c_xfer_finish(void)
+static int i2c_xfer_finish(struct i2c_adapter *adap)
{
+ struct i2c_regs *i2c_base = i2c_get_base(adap);
ulong start_stop_det = get_timer(0);
while (1) {
- if ((readl(&i2c_regs_p->ic_raw_intr_stat) & IC_STOP_DET)) {
- readl(&i2c_regs_p->ic_clr_stop_det);
+ if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
+ readl(&i2c_base->ic_clr_stop_det);
break;
} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
break;
}
}
- if (i2c_wait_for_bb()) {
+ if (i2c_wait_for_bb(adap)) {
printf("Timed out waiting for bus\n");
return 1;
}
- i2c_flush_rxfifo();
+ i2c_flush_rxfifo(adap);
return 0;
}
*
* Read from i2c memory.
*/
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
+ int alen, u8 *buffer, int len)
{
+ struct i2c_regs *i2c_base = i2c_get_base(adap);
unsigned long start_time_rx;
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
* still be one byte because the extra address bits are
* hidden in the chip address.
*/
- chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+ dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
- debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip,
+ debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
addr);
#endif
- if (i2c_xfer_init(chip, addr, alen))
+ if (i2c_xfer_init(adap, dev, addr, alen))
return 1;
start_time_rx = get_timer(0);
while (len) {
if (len == 1)
- writel(IC_CMD | IC_STOP, &i2c_regs_p->ic_cmd_data);
+ writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
else
- writel(IC_CMD, &i2c_regs_p->ic_cmd_data);
+ writel(IC_CMD, &i2c_base->ic_cmd_data);
- if (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) {
- *buffer++ = (uchar)readl(&i2c_regs_p->ic_cmd_data);
+ if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
+ *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
len--;
start_time_rx = get_timer(0);
}
}
- return i2c_xfer_finish();
+ return i2c_xfer_finish(adap);
}
/*
*
* Write to i2c memory.
*/
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
+ int alen, u8 *buffer, int len)
{
+ struct i2c_regs *i2c_base = i2c_get_base(adap);
int nb = len;
unsigned long start_time_tx;
* still be one byte because the extra address bits are
* hidden in the chip address.
*/
- chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+ dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
- debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip,
+ debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
addr);
#endif
- if (i2c_xfer_init(chip, addr, alen))
+ if (i2c_xfer_init(adap, dev, addr, alen))
return 1;
start_time_tx = get_timer(0);
while (len) {
- if (readl(&i2c_regs_p->ic_status) & IC_STATUS_TFNF) {
- if (--len == 0)
- writel(*buffer | IC_STOP, &i2c_regs_p->ic_cmd_data);
- else
- writel(*buffer, &i2c_regs_p->ic_cmd_data);
+ if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
+ if (--len == 0) {
+ writel(*buffer | IC_STOP,
+ &i2c_base->ic_cmd_data);
+ } else {
+ writel(*buffer, &i2c_base->ic_cmd_data);
+ }
buffer++;
start_time_tx = get_timer(0);
}
}
- return i2c_xfer_finish();
+ return i2c_xfer_finish(adap);
}
/*
* i2c_probe - Probe the i2c chip
*/
-int i2c_probe(uchar chip)
+static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
u32 tmp;
int ret;
/*
* Try to read the first location of the chip.
*/
- ret = i2c_read(chip, 0, 1, (uchar *)&tmp, 1);
+ ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1);
if (ret)
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ dw_i2c_init(adap, adap->speed, adap->slaveaddr);
return ret;
}
-#ifdef CONFIG_I2C_MULTI_BUS
-int i2c_set_bus_num(unsigned int bus)
-{
- switch (bus) {
- case 0:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE;
- break;
-#ifdef CONFIG_SYS_I2C_BASE1
- case 1:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE1;
- break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE2
- case 2:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE2;
- break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE3
- case 3:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE3;
- break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE4
- case 4:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE4;
- break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE5
- case 5:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE5;
- break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE6
- case 6:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE6;
- break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE7
- case 7:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE7;
- break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE8
- case 8:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE8;
- break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE9
- case 9:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE9;
- break;
-#endif
- default:
- printf("Bad bus: %d\n", bus);
- return -1;
- }
-
- current_bus = bus;
+U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
+ dw_i2c_write, dw_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
- if (!bus_initialized[current_bus])
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#if CONFIG_SYS_I2C_BUS_MAX >= 2
+U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
+ dw_i2c_write, dw_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
+#endif
- return 0;
-}
+#if CONFIG_SYS_I2C_BUS_MAX >= 3
+U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
+ dw_i2c_write, dw_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
+#endif
-unsigned int i2c_get_bus_num(void)
-{
- return current_bus;
-}
+#if CONFIG_SYS_I2C_BUS_MAX >= 4
+U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
+ dw_i2c_write, dw_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
#endif
#define MXS_I2C_MAX_TIMEOUT 1000000
-static void mxs_i2c_reset(void)
+static struct mxs_i2c_regs *mxs_i2c_get_base(struct i2c_adapter *adap)
{
- struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
+ if (adap->hwadapnr == 0)
+ return (struct mxs_i2c_regs *)MXS_I2C0_BASE;
+ else
+ return (struct mxs_i2c_regs *)MXS_I2C1_BASE;
+}
+
+static unsigned int mxs_i2c_get_bus_speed(struct i2c_adapter *adap)
+{
+ struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
+ uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
+ uint32_t timing0;
+
+ timing0 = readl(&i2c_regs->hw_i2c_timing0);
+ /*
+ * This is a reverse version of the algorithm presented in
+ * i2c_set_bus_speed(). Please refer there for details.
+ */
+ return clk / ((((timing0 >> 16) - 3) * 2) + 38);
+}
+
+static uint mxs_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
+{
+ struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
+ /*
+ * The timing derivation algorithm. There is no documentation for this
+ * algorithm available, it was derived by using the scope and fiddling
+ * with constants until the result observed on the scope was good enough
+ * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
+ * possible to assume the algorithm works for other frequencies as well.
+ *
+ * Note it was necessary to cap the frequency on both ends as it's not
+ * possible to configure completely arbitrary frequency for the I2C bus
+ * clock.
+ */
+ uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
+ uint32_t base = ((clk / speed) - 38) / 2;
+ uint16_t high_count = base + 3;
+ uint16_t low_count = base - 3;
+ uint16_t rcv_count = (high_count * 3) / 4;
+ uint16_t xmit_count = low_count / 4;
+
+ if (speed > 540000) {
+ printf("MXS I2C: Speed too high (%d Hz)\n", speed);
+ return -EINVAL;
+ }
+
+ if (speed < 12000) {
+ printf("MXS I2C: Speed too low (%d Hz)\n", speed);
+ return -EINVAL;
+ }
+
+ writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0);
+ writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1);
+
+ writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) |
+ (0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET),
+ &i2c_regs->hw_i2c_timing2);
+
+ return 0;
+}
+
+static void mxs_i2c_reset(struct i2c_adapter *adap)
+{
+ struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
int ret;
- int speed = i2c_get_bus_speed();
+ int speed = mxs_i2c_get_bus_speed(adap);
ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
if (ret) {
writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set);
- i2c_set_bus_speed(speed);
+ mxs_i2c_set_bus_speed(adap, speed);
}
-static void mxs_i2c_setup_read(uint8_t chip, int len)
+static void mxs_i2c_setup_read(struct i2c_adapter *adap, uint8_t chip, int len)
{
- struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
+ struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START |
I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
}
-static int mxs_i2c_write(uchar chip, uint addr, int alen,
- uchar *buf, int blen, int stop)
+static int mxs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buf, int blen, int stop)
{
- struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
+ struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
uint32_t data, tmp;
int i, remain, off;
int timeout = MXS_I2C_MAX_TIMEOUT;
return 0;
}
-static int mxs_i2c_wait_for_ack(void)
+static int mxs_i2c_wait_for_ack(struct i2c_adapter *adap)
{
- struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
+ struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
uint32_t tmp;
int timeout = MXS_I2C_MAX_TIMEOUT;
return 0;
err:
- mxs_i2c_reset();
+ mxs_i2c_reset(adap);
return 1;
}
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int mxs_i2c_if_read(struct i2c_adapter *adap, uint8_t chip,
+ uint addr, int alen, uint8_t *buffer,
+ int len)
{
- struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
+ struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
uint32_t tmp = 0;
int timeout = MXS_I2C_MAX_TIMEOUT;
int ret;
int i;
- ret = mxs_i2c_write(chip, addr, alen, NULL, 0, 0);
+ ret = mxs_i2c_write(adap, chip, addr, alen, NULL, 0, 0);
if (ret) {
debug("MXS I2C: Failed writing address\n");
return ret;
}
- ret = mxs_i2c_wait_for_ack();
+ ret = mxs_i2c_wait_for_ack(adap);
if (ret) {
debug("MXS I2C: Failed writing address\n");
return ret;
}
- mxs_i2c_setup_read(chip, len);
- ret = mxs_i2c_wait_for_ack();
+ mxs_i2c_setup_read(adap, chip, len);
+ ret = mxs_i2c_wait_for_ack(adap);
if (ret) {
debug("MXS I2C: Failed reading address\n");
return ret;
return 0;
}
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int mxs_i2c_if_write(struct i2c_adapter *adap, uint8_t chip,
+ uint addr, int alen, uint8_t *buffer,
+ int len)
{
int ret;
- ret = mxs_i2c_write(chip, addr, alen, buffer, len, 1);
+ ret = mxs_i2c_write(adap, chip, addr, alen, buffer, len, 1);
if (ret) {
debug("MXS I2C: Failed writing address\n");
return ret;
}
- ret = mxs_i2c_wait_for_ack();
+ ret = mxs_i2c_wait_for_ack(adap);
if (ret)
debug("MXS I2C: Failed writing address\n");
return ret;
}
-int i2c_probe(uchar chip)
+static int mxs_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
{
int ret;
- ret = mxs_i2c_write(chip, 0, 1, NULL, 0, 1);
+ ret = mxs_i2c_write(adap, chip, 0, 1, NULL, 0, 1);
if (!ret)
- ret = mxs_i2c_wait_for_ack();
- mxs_i2c_reset();
+ ret = mxs_i2c_wait_for_ack(adap);
+ mxs_i2c_reset(adap);
return ret;
}
-int i2c_set_bus_speed(unsigned int speed)
+static void mxs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
- struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
- /*
- * The timing derivation algorithm. There is no documentation for this
- * algorithm available, it was derived by using the scope and fiddling
- * with constants until the result observed on the scope was good enough
- * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
- * possible to assume the algorithm works for other frequencies as well.
- *
- * Note it was necessary to cap the frequency on both ends as it's not
- * possible to configure completely arbitrary frequency for the I2C bus
- * clock.
- */
- uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
- uint32_t base = ((clk / speed) - 38) / 2;
- uint16_t high_count = base + 3;
- uint16_t low_count = base - 3;
- uint16_t rcv_count = (high_count * 3) / 4;
- uint16_t xmit_count = low_count / 4;
-
- if (speed > 540000) {
- printf("MXS I2C: Speed too high (%d Hz)\n", speed);
- return -EINVAL;
- }
-
- if (speed < 12000) {
- printf("MXS I2C: Speed too low (%d Hz)\n", speed);
- return -EINVAL;
- }
-
- writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0);
- writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1);
-
- writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) |
- (0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET),
- &i2c_regs->hw_i2c_timing2);
-
- return 0;
-}
-
-unsigned int i2c_get_bus_speed(void)
-{
- struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
- uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
- uint32_t timing0;
-
- timing0 = readl(&i2c_regs->hw_i2c_timing0);
- /*
- * This is a reverse version of the algorithm presented in
- * i2c_set_bus_speed(). Please refer there for details.
- */
- return clk / ((((timing0 >> 16) - 3) * 2) + 38);
-}
-
-void i2c_init(int speed, int slaveadd)
-{
- mxs_i2c_reset();
- i2c_set_bus_speed(speed);
+ mxs_i2c_reset(adap);
+ mxs_i2c_set_bus_speed(adap, speed);
return;
}
+
+U_BOOT_I2C_ADAP_COMPLETE(mxs0, mxs_i2c_init, mxs_i2c_probe,
+ mxs_i2c_if_read, mxs_i2c_if_write,
+ mxs_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_SPEED, 0, 0)
+U_BOOT_I2C_ADAP_COMPLETE(mxs1, mxs_i2c_init, mxs_i2c_probe,
+ mxs_i2c_if_read, mxs_i2c_if_write,
+ mxs_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_SPEED, 0, 1)
/*
* I2C configuration
*/
-#define CONFIG_HARD_I2C
-#define CONFIG_DW_I2C
-#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DW
#define CONFIG_I2C_ENV_EEPROM_BUS 2
#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SPEED1 100000
+#define CONFIG_SYS_I2C_SPEED2 100000
#define CONFIG_SYS_I2C_SLAVE 0
+#define CONFIG_SYS_I2C_SLAVE1 0
+#define CONFIG_SYS_I2C_SLAVE2 0
#define CONFIG_SYS_I2C_BASE 0xE001D000
#define CONFIG_SYS_I2C_BASE1 0xE001E000
#define CONFIG_SYS_I2C_BASE2 0xE001F000
/* I2C */
#ifdef CONFIG_CMD_I2C
-#define CONFIG_I2C_MXS
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXS
#define CONFIG_HARD_I2C
#ifndef CONFIG_SYS_I2C_SPEED
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0"
/* I2C driver configuration */
-#define CONFIG_HARD_I2C
-#define CONFIG_DW_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DW
#if defined(CONFIG_SPEAR600)
#define CONFIG_SYS_I2C_BASE 0xD0200000
#elif defined(CONFIG_SPEAR300)
#define CONFIG_SPEAR_GPIO
/* I2C config options */
-#define CONFIG_HARD_I2C
-#define CONFIG_DW_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DW
#define CONFIG_SYS_I2C_BASE 0xD0200000
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0x02
projects / platform / kernel / u-boot.git / commitdiff