include:
# we need to build by vendor due to 50min time limit for builds
# each env setting here is a dedicated build
- - env:
+ - name: "buildman arc"
+ env:
- BUILDMAN="arc"
TOOLCHAIN="arc"
- - env:
+ - name: "buildman arm11 arm7 arm920t arm946es"
+ env:
- BUILDMAN="arm11 arm7 arm920t arm946es"
- - env:
+ - name: "buildman arm926ejs (non-mx,siemens,atmel,kirkwood)"
+ env:
- JOB="arm926ejs"
BUILDMAN="arm926ejs -x mx,siemens,atmel,kirkwood"
- - env:
+ - name: "buildman atmel"
+ env:
- BUILDMAN="atmel"
- - env:
- BUILDMAN="boundary engicam toradex"
- - env:
- - JOB="Freescale ARM32"
- BUILDMAN="freescale -x powerpc,m68k,aarch64"
- - env:
- - JOB="Freescale AArch64"
- BUILDMAN="freescale&aarch64"
- - env:
- - JOB="i.MX6 (non-Freescale)"
- BUILDMAN="mx6 -x freescale,toradex,boundary,engicam"
- - env:
- - JOB="i.MX (non-Freescale, non-i.MX6)"
- BUILDMAN="mx -x freescale,mx6,toradex"
- - env:
+ - name: "buildman boundary engicam toradex"
+ env:
+ - BUILDMAN="boundary engicam toradex"
+ - name: "buildman Freescale ARM32"
+ env:
+ - BUILDMAN="freescale -x powerpc,m68k,aarch64"
+ - name: "buildman Freescale AArch64"
+ env:
+ - BUILDMAN="freescale&aarch64"
+ - name: "buildman i.MX6 (non-Freescale)"
+ env:
+ - BUILDMAN="mx6 -x freescale,toradex,boundary,engicam"
+ - name: "buildman i.MX (non-Freescale,i.MX6,toradex)"
+ env:
+ - BUILDMAN="mx -x freescale,mx6,toradex"
+ - name: "buildman k2"
+ env:
- BUILDMAN="k2"
- - env:
+ - name: "buildman samsung socfpga"
+ env:
- BUILDMAN="samsung socfpga"
- - env:
+ - name: "buildman sun4i"
+ env:
- BUILDMAN="sun4i"
- - env:
+ - name: "buildman sun5i"
+ env:
- BUILDMAN="sun5i"
- - env:
+ - name: "buildman sun6i"
+ env:
- BUILDMAN="sun6i"
- - env:
+ - name: "builman sun7i"
+ env:
- BUILDMAN="sun7i"
- - env:
+ - name: "buildman sun8i"
+ env:
- BUILDMAN="sun8i"
- - env:
+ - name: "buildman sun9i"
+ env:
- BUILDMAN="sun9i"
- - env:
+ - name: "buildman sun50i"
+ env:
- BUILDMAN="sun50i"
- - env:
- - JOB="Catch-all ARM"
- BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,pxa,rockchip,toradex,socfpga,k2,xilinx"
- - env:
+ - name: "buildman catch-all ARM"
+ env:
+ - BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,pxa,rockchip,toradex,socfpga,k2,xilinx"
+ - name: "buildman sandbox x86"
+ env:
- BUILDMAN="sandbox x86"
TOOLCHAIN="x86_64"
- - env:
+ - name: "buildman kirkwood (excluding openrd)"
+ env:
- BUILDMAN="kirkwood -x openrd"
- - env:
+ - name: "buildman mvebu"
+ env:
- BUILDMAN="mvebu"
- - env:
- - JOB="PXA"
+ - name: "buildman PXA (non-toradex)"
+ env:
- BUILDMAN="pxa -x toradex"
- - env:
+ - name: "buildman m68k"
+ env:
- BUILDMAN="m68k"
TOOLCHAIN="m68k"
- - env:
+ - name: "buildman microblaze"
+ env:
- BUILDMAN="microblaze"
TOOLCHAIN="microblaze"
- - env:
+ - name: "buildman mips"
+ env:
- BUILDMAN="mips"
TOOLCHAIN="mips"
- - env:
- - JOB="Non-Freescale PowerPC"
- BUILDMAN="powerpc -x freescale"
+ - name: "buildman non-Freescale PowerPC"
+ env:
+ - BUILDMAN="powerpc -x freescale"
TOOLCHAIN="powerpc"
- - env:
+ - name: "buildman mpc85xx&freescale (excluding many)"
+ env:
- BUILDMAN="mpc85xx&freescale -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x bsc91*"
TOOLCHAIN="powerpc"
- - env:
+ - name: "buildman t208xrdb corenet_ds"
+ env:
- BUILDMAN="t208xrdb corenet_ds"
TOOLCHAIN="powerpc"
- - env:
+ - name: "buildman Freescale PowerPC"
+ env:
- BUILDMAN="t4qds b4860qds mpc83xx&freescale mpc86xx&freescale"
TOOLCHAIN="powerpc"
- - env:
+ - name: "buildman t102*"
+ env:
- BUILDMAN="t102*"
TOOLCHAIN="powerpc"
- - env:
+ - name: "buildman p1_p2_rdb_pc"
+ env:
- BUILDMAN="p1_p2_rdb_pc"
TOOLCHAIN="powerpc"
- - env:
+ - name: "buildman p1010rdb bsc91"
+ env:
- BUILDMAN="p1010rdb bsc91"
TOOLCHAIN="powerpc"
- - env:
+ - name: "buildman siemens"
+ env:
- BUILDMAN="siemens"
- - env:
- - JOB="tegra"
- BUILDMAN="tegra -x toradex"
- - env:
- - JOB="am33xx"
- BUILDMAN="am33xx -x siemens"
- - env:
+ - name: "buildman tegra"
+ env:
+ - BUILDMAN="tegra -x toradex"
+ - name: "buildman am33xx (no siemens)"
+ env:
+ - BUILDMAN="am33xx -x siemens"
+ - name: "buildman omap"
+ env:
- BUILDMAN="omap"
- - env:
+ - name: "buildman uniphier"
+ env:
- BUILDMAN="uniphier"
- - env:
- - JOB="Catch-all AArch64"
- BUILDMAN="aarch64 -x tegra,freescale,mvebu,uniphier,sunxi,samsung,rockchip,xilinx"
- - env:
+ - name: "buildman catch-all AArch64"
+ env:
+ - BUILDMAN="aarch64 -x tegra,freescale,mvebu,uniphier,sunxi,samsung,rockchip,xilinx"
+ - name: "buildman rockchip"
+ env:
- BUILDMAN="rockchip"
- - env:
- - JOB="sh"
- BUILDMAN="sh -x arm"
+ - name: "buildman sh"
+ env:
+ - BUILDMAN="sh -x arm"
TOOLCHAIN="sh"
- - env:
- - JOB="Xilinx (ARM)"
- BUILDMAN="xilinx -x microblaze"
- - env:
+ - name: "buildman Xilinx (ARM)"
+ env:
+ - BUILDMAN="xilinx -x microblaze"
+ - name: "buildman xtensa"
+ env:
- BUILDMAN="xtensa"
TOOLCHAIN="xtensa-dc233c-elf"
- - env:
+ - name: "buildman riscv"
+ env:
- BUILDMAN="riscv"
TOOLCHAIN="riscv"
# QA jobs for code analytics
# static code analysis with cppcheck (we can add --enable=all later)
- - env:
- - JOB="cppcheck"
+ - name: "cppcheck"
script:
- cppcheck --force --quiet --inline-suppr .
# search for TODO within source tree
- - env:
- - JOB="grep TODO"
+ - name: "grep TODO"
script:
- grep -r TODO .
# search for FIXME within source tree
- - env:
- - JOB="grep FIXME HACK"
+ - name: "grep FIXME HACK"
script:
- grep -r FIXME .
# search for HACK within source tree and ignore HACKKIT board
script:
- grep -r HACK . | grep -v HACKKIT
# some statistics about the code base
- - env:
- - JOB="sloccount"
+ - name: "sloccount"
script:
- sloccount .
# test/py
- - env:
+ - name: "test/py sandbox"
+ env:
- TEST_PY_BD="sandbox"
BUILDMAN="^sandbox$"
TOOLCHAIN="x86_64"
- - env:
+ - name: "test/py sandbox_spl"
+ env:
- TEST_PY_BD="sandbox_spl"
TEST_PY_TEST_SPEC="test_ofplatdata"
BUILDMAN="^sandbox$"
TOOLCHAIN="x86_64"
TEST_PY_TOOLS="yes"
- - env:
+ - name: "test/py sandbox_flattree"
+ env:
- TEST_PY_BD="sandbox_flattree"
BUILDMAN="^sandbox_flattree$"
TOOLCHAIN="x86_64"
- - env:
+ - name: "test/py vexpress_ca15_tc2"
+ env:
- TEST_PY_BD="vexpress_ca15_tc2"
TEST_PY_ID="--id qemu"
QEMU_TARGET="arm-softmmu"
BUILDMAN="^vexpress_ca15_tc2$"
- - env:
+ - name: "test/py vexpress_ca9x4"
+ env:
- TEST_PY_BD="vexpress_ca9x4"
TEST_PY_ID="--id qemu"
QEMU_TARGET="arm-softmmu"
BUILDMAN="^vexpress_ca9x4$"
- - env:
+ - name: "test/py integratorcp_cm926ejs"
+ env:
- TEST_PY_BD="integratorcp_cm926ejs"
TEST_PY_TEST_SPEC="not sleep"
TEST_PY_ID="--id qemu"
QEMU_TARGET="arm-softmmu"
BUILDMAN="^integratorcp_cm926ejs$"
- - env:
+ - name: "test/py qemu_arm"
+ env:
- TEST_PY_BD="qemu_arm"
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="arm-softmmu"
BUILDMAN="^qemu_arm$"
- - env:
+ - name: "test/py qemu_arm64"
+ env:
- TEST_PY_BD="qemu_arm64"
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="aarch64-softmmu"
BUILDMAN="^qemu_arm64$"
- - env:
+ - name: "test/py qemu_mips"
+ env:
- TEST_PY_BD="qemu_mips"
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="mips-softmmu"
BUILDMAN="^qemu_mips$"
TOOLCHAIN="mips"
- - env:
+ - name: "test/py qemu_mipsel"
+ env:
- TEST_PY_BD="qemu_mipsel"
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="mipsel-softmmu"
BUILDMAN="^qemu_mipsel$"
TOOLCHAIN="mips"
- - env:
+ - name: "test/py qemu_mips64"
+ env:
- TEST_PY_BD="qemu_mips64"
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="mips64-softmmu"
BUILDMAN="^qemu_mips64$"
TOOLCHAIN="mips"
- - env:
+ - name: "test/py qemu_mips64el"
+ env:
- TEST_PY_BD="qemu_mips64el"
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="mips64el-softmmu"
BUILDMAN="^qemu_mips64el$"
TOOLCHAIN="mips"
- - env:
+ - name: "test/py qemu-ppce500"
+ env:
- TEST_PY_BD="qemu-ppce500"
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="ppc-softmmu"
BUILDMAN="^qemu-ppce500$"
TOOLCHAIN="powerpc"
- - env:
+ - name: "test/py qemu-x86"
+ env:
- TEST_PY_BD="qemu-x86"
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="i386-softmmu"
BUILDMAN="^qemu-x86$"
TOOLCHAIN="x86_64"
BUILD_ROM="yes"
- - env:
+ - name: "test/py zynq_zc702"
+ env:
- TEST_PY_BD="zynq_zc702"
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="arm-softmmu"
TEST_PY_ID="--id qemu"
BUILDMAN="^zynq_zc702$"
- - env:
+ - name: "test/py xtfpga"
+ env:
- TEST_PY_BD="xtfpga"
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="xtensa-softmmu"
--- /dev/null
+gdsys AXI busses of IHS FPGA devices
+
+Certain gdsys IHS FPGAs offer a interface to their built-in AXI bus with which
+the connected devices (usually IP cores) can be controlled via software.
+
+Required properties:
+- compatible: must be "gdsys,ihs_axi"
+- reg: describes the address and length of the AXI bus's register map (within
+ the FPGA's register space)
+
+Example:
+
+fpga0_axi_video0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "gdsys,ihs_axi";
+ reg = <0x170 0x10>;
+
+ axi_dev_1 {
+ ...
+ };
+};
--- /dev/null
+gdsys IO endpoint of IHS FPGA devices
+
+The IO endpoint of IHS FPGA devices is a packet-based transmission interface
+that allows interconnected gdsys devices to send and receive data over the
+FPGA's main ethernet connection.
+
+Required properties:
+- compatible: must be "gdsys,io-endpoint"
+- reg: describes the address and length of the endpoint's register map (within
+ the FPGA's register space)
+
+Example:
+
+fpga0_ep0 {
+ compatible = "gdsys,io-endpoint";
+ reg = <0x020 0x10
+ 0x320 0x10
+ 0x340 0x10
+ 0x360 0x10>;
+};
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+EFI subsystem
+=============
+
+Boot services
+-------------
+
+.. kernel-doc:: lib/efi_loader/efi_boottime.c
+ :internal:
+
+Runtime services
+----------------
+
+.. kernel-doc:: lib/efi_loader/efi_runtime.c
+ :internal:
-====================
-U-Boot Hacker Manual
-====================
+.. SPDX-License-Identifier: GPL-2.0+
-Linker-Generated Arrays
-=======================
+#######################
+U-Boot Developer Manual
+#######################
-A linker list is constructed by grouping together linker input
-sections, each containing one entry of the list. Each input section
-contains a constant initialized variable which holds the entry's
-content. Linker list input sections are constructed from the list
-and entry names, plus a prefix which allows grouping all lists
-together. Assuming _list and _entry are the list and entry names,
-then the corresponding input section name is
+.. toctree::
-::
-
- .u_boot_list_ + 2_ + @_list + _2_ + @_entry
-
-and the C variable name is
-
-::
-
- _u_boot_list + _2_ + @_list + _2_ + @_entry
-
-This ensures uniqueness for both input section and C variable name.
-
-Note that the names differ only in the first character, "." for the
-section and "_" for the variable, so that the linker cannot confuse
-section and symbol names. From now on, both names will be referred
-to as
-
-::
-
- %u_boot_list_ + 2_ + @_list + _2_ + @_entry
-
-Entry variables need never be referred to directly.
-
-The naming scheme for input sections allows grouping all linker lists
-into a single linker output section and grouping all entries for a
-single list.
-
-Note the two '_2_' constant components in the names: their presence
-allows putting a start and end symbols around a list, by mapping
-these symbols to sections names with components "1" (before) and
-"3" (after) instead of "2" (within).
-Start and end symbols for a list can generally be defined as
-
-::
-
- %u_boot_list_2_ + @_list + _1_...
- %u_boot_list_2_ + @_list + _3_...
-
-Start and end symbols for the whole of the linker lists area can be
-defined as
-
-::
-
- %u_boot_list_1_...
- %u_boot_list_3_...
-
-Here is an example of the sorted sections which result from a list
-"array" made up of three entries : "first", "second" and "third",
-iterated at least once.
-
-::
-
- .u_boot_list_2_array_1
- .u_boot_list_2_array_2_first
- .u_boot_list_2_array_2_second
- .u_boot_list_2_array_2_third
- .u_boot_list_2_array_3
-
-If lists must be divided into sublists (e.g. for iterating only on
-part of a list), one can simply give the list a name of the form
-'outer_2_inner', where 'outer' is the global list name and 'inner'
-is the sub-list name. Iterators for the whole list should use the
-global list name ("outer"); iterators for only a sub-list should use
-the full sub-list name ("outer_2_inner").
-
-Here is an example of the sections generated from a global list
-named "drivers", two sub-lists named "i2c" and "pci", and iterators
-defined for the whole list and each sub-list:
-
-::
-
- %u_boot_list_2_drivers_1
- %u_boot_list_2_drivers_2_i2c_1
- %u_boot_list_2_drivers_2_i2c_2_first
- %u_boot_list_2_drivers_2_i2c_2_first
- %u_boot_list_2_drivers_2_i2c_2_second
- %u_boot_list_2_drivers_2_i2c_2_third
- %u_boot_list_2_drivers_2_i2c_3
- %u_boot_list_2_drivers_2_pci_1
- %u_boot_list_2_drivers_2_pci_2_first
- %u_boot_list_2_drivers_2_pci_2_second
- %u_boot_list_2_drivers_2_pci_2_third
- %u_boot_list_2_drivers_2_pci_3
- %u_boot_list_2_drivers_3
-
-.. kernel-doc:: include/linker_lists.h
- :internal:
-
-Serial system
-=============
-
-.. kernel-doc:: drivers/serial/serial.c
- :internal:
-
-The U-Boot EFI subsystem
-========================
-
-Boot services
--------------
-
-.. kernel-doc:: lib/efi_loader/efi_boottime.c
- :internal:
+ efi
+ linker_lists
+ serial
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Linker-Generated Arrays
+=======================
+
+A linker list is constructed by grouping together linker input
+sections, each containing one entry of the list. Each input section
+contains a constant initialized variable which holds the entry's
+content. Linker list input sections are constructed from the list
+and entry names, plus a prefix which allows grouping all lists
+together. Assuming _list and _entry are the list and entry names,
+then the corresponding input section name is
+
+::
+
+ .u_boot_list_ + 2_ + @_list + _2_ + @_entry
+
+and the C variable name is
+
+::
+
+ _u_boot_list + _2_ + @_list + _2_ + @_entry
+
+This ensures uniqueness for both input section and C variable name.
+
+Note that the names differ only in the first character, "." for the
+section and "_" for the variable, so that the linker cannot confuse
+section and symbol names. From now on, both names will be referred
+to as
+
+::
+
+ %u_boot_list_ + 2_ + @_list + _2_ + @_entry
+
+Entry variables need never be referred to directly.
+
+The naming scheme for input sections allows grouping all linker lists
+into a single linker output section and grouping all entries for a
+single list.
+
+Note the two '_2_' constant components in the names: their presence
+allows putting a start and end symbols around a list, by mapping
+these symbols to sections names with components "1" (before) and
+"3" (after) instead of "2" (within).
+Start and end symbols for a list can generally be defined as
+
+::
+
+ %u_boot_list_2_ + @_list + _1_...
+ %u_boot_list_2_ + @_list + _3_...
+
+Start and end symbols for the whole of the linker lists area can be
+defined as
+
+::
+
+ %u_boot_list_1_...
+ %u_boot_list_3_...
+
+Here is an example of the sorted sections which result from a list
+"array" made up of three entries : "first", "second" and "third",
+iterated at least once.
+
+::
+
+ .u_boot_list_2_array_1
+ .u_boot_list_2_array_2_first
+ .u_boot_list_2_array_2_second
+ .u_boot_list_2_array_2_third
+ .u_boot_list_2_array_3
+
+If lists must be divided into sublists (e.g. for iterating only on
+part of a list), one can simply give the list a name of the form
+'outer_2_inner', where 'outer' is the global list name and 'inner'
+is the sub-list name. Iterators for the whole list should use the
+global list name ("outer"); iterators for only a sub-list should use
+the full sub-list name ("outer_2_inner").
+
+Here is an example of the sections generated from a global list
+named "drivers", two sub-lists named "i2c" and "pci", and iterators
+defined for the whole list and each sub-list:
+
+::
+
+ %u_boot_list_2_drivers_1
+ %u_boot_list_2_drivers_2_i2c_1
+ %u_boot_list_2_drivers_2_i2c_2_first
+ %u_boot_list_2_drivers_2_i2c_2_first
+ %u_boot_list_2_drivers_2_i2c_2_second
+ %u_boot_list_2_drivers_2_i2c_2_third
+ %u_boot_list_2_drivers_2_i2c_3
+ %u_boot_list_2_drivers_2_pci_1
+ %u_boot_list_2_drivers_2_pci_2_first
+ %u_boot_list_2_drivers_2_pci_2_second
+ %u_boot_list_2_drivers_2_pci_2_third
+ %u_boot_list_2_drivers_2_pci_3
+ %u_boot_list_2_drivers_3
+
+.. kernel-doc:: include/linker_lists.h
+ :internal:
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Serial system
+=============
+
+.. kernel-doc:: drivers/serial/serial.c
+ :internal:
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
+config SYS_MALLOC_LEN
+ hex "Define memory for Dynamic allocation"
+ depends on ARCH_ZYNQ
+ help
+ This defines memory to be allocated for Dynamic allocation
+ TODO: Use for other architectures
+
config SPL_SYS_MALLOC_F_LEN
hex "Size of malloc() pool in SPL before relocation"
depends on SYS_MALLOC_F
F: drivers/watchdog/cdns_wdt.c
F: include/zynqmppl.h
F: tools/zynqmp*
+N: ultra96
N: zynqmp
ARM ZYNQMP R5
M: Alexander Graf <agraf@suse.de>
S: Maintained
T: git git://github.com/agraf/u-boot.git
-F: doc/DocBook/efi.tmpl
F: doc/README.uefi
F: doc/README.iscsi
+F: Documentation/efi.rst
F: include/efi*
F: include/pe.h
F: include/asm-generic/pe.h
regular expression. This allows multiple variables to be connected to
the same callback without explicitly listing them all out.
+The signature of the callback functions is:
+
+ int callback(const char *name, const char *value, enum env_op op, int flags)
+
+* name - changed environment variable
+* value - new value of the environment variable
+* op - operation (create, overwrite, or delete)
+* flags - attributes of the environment variable change, see flags H_* in
+ include/search.h
+
+The return value is 0 if the variable change is accepted and 1 otherwise.
Command Line Parsing:
=====================
source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/mx35pdk/Kconfig"
source "board/freescale/s32v234evb/Kconfig"
-source "board/gdsys/a38x/Kconfig"
source "board/grinn/chiliboard/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
zynq-zc770-xm013.dtb \
zynq-zed.dtb \
zynq-zturn.dtb \
- zynq-zybo.dtb
+ zynq-zybo.dtb \
+ zynq-zybo-z7.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
+ avnet-ultra96-rev1.dtb \
zynqmp-mini-emmc0.dtb \
zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb \
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+&spi1 {
+ u-boot,dm-spl;
+
+ spi-flash@0 {
+ u-boot,dm-spl;
+ };
+};
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "armada-388.dtsi"
+#include "armada-38x-solidrun-microsom.dtsi"
/ {
model = "SolidRun Clearfog A1";
stdout-path = "serial0:115200n8";
};
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>; /* 256 MB */
- };
-
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
};
soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
- MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
- MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
- MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
-
internal-regs {
- ethernet@30000 {
- mac-address = [00 50 43 02 02 02];
- phy-mode = "sgmii";
- status = "okay";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- ethernet@34000 {
- mac-address = [00 50 43 02 02 03];
- managed = "in-band-status";
- phy-mode = "sgmii";
- status = "okay";
- };
-
- ethernet@70000 {
- mac-address = [00 50 43 02 02 01];
- pinctrl-0 = <&ge0_rgmii_pins>;
- pinctrl-names = "default";
- phy = <&phy_dedicated>;
- phy-mode = "rgmii-id";
- status = "okay";
- };
-
- i2c@11000 {
- /* Is there anything on this? */
- clock-frequency = <100000>;
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- /*
- * PCA9655 GPIO expander, up to 1MHz clock.
- * 0-CON3 CLKREQ#
- * 1-CON3 PERST#
- * 2-CON2 PERST#
- * 3-CON3 W_DISABLE
- * 4-CON2 CLKREQ#
- * 5-USB3 overcurrent
- * 6-USB3 power
- * 7-CON2 W_DISABLE
- * 8-JP4 P1
- * 9-JP4 P4
- * 10-JP4 P5
- * 11-m.2 DEVSLP
- * 12-SFP_LOS
- * 13-SFP_TX_FAULT
- * 14-SFP_TX_DISABLE
- * 15-SFP_MOD_DEF0
- */
- expander0: gpio-expander@20 {
- /*
- * This is how it should be:
- * compatible = "onnn,pca9655",
- * "nxp,pca9555";
- * but you can't do this because of
- * the way I2C works.
- */
- compatible = "nxp,pca9555";
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x20>;
-
- pcie1_0_clkreq {
- gpio-hog;
- gpios = <0 GPIO_ACTIVE_LOW>;
- input;
- line-name = "pcie1.0-clkreq";
- };
- pcie1_0_w_disable {
- gpio-hog;
- gpios = <3 GPIO_ACTIVE_LOW>;
- output-low;
- line-name = "pcie1.0-w-disable";
- };
- pcie2_0_clkreq {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_LOW>;
- input;
- line-name = "pcie2.0-clkreq";
- };
- pcie2_0_w_disable {
- gpio-hog;
- gpios = <7 GPIO_ACTIVE_LOW>;
- output-low;
- line-name = "pcie2.0-w-disable";
- };
- usb3_ilimit {
- gpio-hog;
- gpios = <5 GPIO_ACTIVE_LOW>;
- input;
- line-name = "usb3-current-limit";
- };
- usb3_power {
- gpio-hog;
- gpios = <6 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "usb3-power";
- };
- m2_devslp {
- gpio-hog;
- gpios = <11 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "m.2 devslp";
- };
- };
-
- /* The MCP3021 is 100kHz clock only */
- mikrobus_adc: mcp3021@4c {
- compatible = "microchip,mcp3021";
- reg = <0x4c>;
- };
-
- /* Also something at 0x64 */
- };
-
- i2c@11100 {
- /*
- * Routed to SFP, mikrobus, and PCIe.
- * SFP limits this to 100kHz, and requires
- * an AT24C01A/02/04 with address pins tied
- * low, which takes addresses 0x50 and 0x51.
- * Mikrobus doesn't specify beyond an I2C
- * bus being present.
- * PCIe uses ARP to assign addresses, or
- * 0x63-0x64.
- */
- clock-frequency = <100000>;
- pinctrl-0 = <&clearfog_i2c1_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- mdio@72004 {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- phy_dedicated: ethernet-phy@0 {
- /*
- * Annoyingly, the marvell phy driver
- * configures the LED register, rather
- * than preserving reset-loaded setting.
- * We undo that rubbish here.
- */
- marvell,reg-init = <3 16 0 0x101e>;
- reg = <0>;
- };
- };
-
- pinctrl@18000 {
- clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
- marvell,pins = "mpp46";
- marvell,function = "ref";
- };
- clearfog_dsa0_pins: clearfog-dsa0-pins {
- marvell,pins = "mpp23", "mpp41";
- marvell,function = "gpio";
- };
- clearfog_i2c1_pins: i2c1-pins {
- /* SFP, PCIe, mSATA, mikrobus */
- marvell,pins = "mpp26", "mpp27";
- marvell,function = "i2c1";
- };
- clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
- marvell,pins = "mpp20";
- marvell,function = "gpio";
- };
- clearfog_sdhci_pins: clearfog-sdhci-pins {
- marvell,pins = "mpp21", "mpp28",
- "mpp37", "mpp38",
- "mpp39", "mpp40";
- marvell,function = "sd0";
- };
- clearfog_spi1_cs_pins: spi1-cs-pins {
- marvell,pins = "mpp55";
- marvell,function = "spi1";
- };
- mikro_pins: mikro-pins {
- /* int: mpp22 rst: mpp29 */
- marvell,pins = "mpp22", "mpp29";
- marvell,function = "gpio";
- };
- mikro_spi_pins: mikro-spi-pins {
- marvell,pins = "mpp43";
- marvell,function = "spi1";
- };
- mikro_uart_pins: mikro-uart-pins {
- marvell,pins = "mpp24", "mpp25";
- marvell,function = "ua1";
- };
- rear_button_pins: rear-button-pins {
- marvell,pins = "mpp34";
- marvell,function = "gpio";
- };
- };
-
rtc@a3800 {
/*
* If the rtc doesn't work, run "date reset"
bus-width = <4>;
cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
no-1-8-v;
- pinctrl-0 = <&clearfog_sdhci_pins
+ pinctrl-0 = <µsom_sdhci_pins
&clearfog_sdhci_cd_pins>;
pinctrl-names = "default";
status = "okay";
wp-inverted;
};
- serial@12000 {
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
- status = "okay";
- u-boot,dm-pre-reloc;
- };
-
serial@12100 {
/* mikrobus uart */
pinctrl-0 = <&mikro_uart_pins>;
pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
pinctrl-names = "default";
status = "okay";
-
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "w25q32", "jedec,spi-nor", "spi-flash";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <3000000>;
- };
};
- usb3@f8000 {
+ usb0: usb3@f8000 {
+ /* CON7, USB-A port on back of device */
status = "okay";
};
};
};
};
- sfp: sfp {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
- moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
- sfp,ethernet = <ð2>;
- tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
- };
-
- dsa@0 {
- compatible = "marvell,dsa";
- dsa,ethernet = <ð1>;
- dsa,mii-bus = <&mdio>;
- pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
- pinctrl-names = "default";
- #address-cells = <2>;
- #size-cells = <0>;
-
- switch@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <4 0>;
-
- port@0 {
- reg = <0>;
- label = "lan1";
- };
-
- port@1 {
- reg = <1>;
- label = "lan2";
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- };
-
- port@3 {
- reg = <3>;
- label = "lan4";
- };
-
- port@4 {
- reg = <4>;
- label = "lan5";
- };
-
- port@5 {
- reg = <5>;
- label = "cpu";
- };
-
- port@6 {
- /* 88E1512 external phy */
- reg = <6>;
- label = "lan6";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
- };
-
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&rear_button_pins>;
};
};
+&w25q32 {
+ status = "okay";
+};
+
+ð1 {
+ managed = "in-band-status";
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+ð2 {
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /*
+ * PCA9655 GPIO expander, up to 1MHz clock.
+ * 0-CON3 CLKREQ#
+ * 1-CON3 PERST#
+ * 2-CON2 PERST#
+ * 3-CON3 W_DISABLE
+ * 4-CON2 CLKREQ#
+ * 5-USB3 overcurrent
+ * 6-USB3 power
+ * 7-CON2 W_DISABLE
+ * 8-JP4 P1
+ * 9-JP4 P4
+ * 10-JP4 P5
+ * 11-m.2 DEVSLP
+ * 12-SFP_LOS
+ * 13-SFP_TX_FAULT
+ * 14-SFP_TX_DISABLE
+ * 15-SFP_MOD_DEF0
+ */
+ expander0: gpio-expander@20 {
+ /*
+ * This is how it should be:
+ * compatible = "onnn,pca9655",
+ * "nxp,pca9555";
+ * but you can't do this because of
+ * the way I2C works.
+ */
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+
+ pcie1_0_clkreq {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie1.0-clkreq";
+ };
+ pcie1_0_w_disable {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie1.0-w-disable";
+ };
+ pcie2_0_clkreq {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie2.0-clkreq";
+ };
+ pcie2_0_w_disable {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie2.0-w-disable";
+ };
+ usb3_ilimit {
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "usb3-current-limit";
+ };
+ usb3_power {
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb3-power";
+ };
+ m2_devslp {
+ gpio-hog;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "m.2 devslp";
+ };
+ };
+
+ mikrobus_adc: mcp3021@4c {
+ compatible = "microchip,mcp3021";
+ reg = <0x4c>;
+ };
+};
+
+&i2c1 {
+ /*
+ * Routed to SFP, mikrobus, and PCIe.
+ * SFP limits this to 100kHz, and requires
+ * an AT24C01A/02/04 with address pins tied
+ * low, which takes addresses 0x50 and 0x51.
+ * Mikrobus doesn't specify beyond an I2C
+ * bus being present.
+ * PCIe uses ARP to assign addresses, or
+ * 0x63-0x64.
+ */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&clearfog_i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pinctrl {
+ clearfog_i2c1_pins: i2c1-pins {
+ /* SFP, PCIe, mSATA, mikrobus */
+ marvell,pins = "mpp26", "mpp27";
+ marvell,function = "i2c1";
+ };
+ clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
+ marvell,pins = "mpp20";
+ marvell,function = "gpio";
+ };
+ clearfog_spi1_cs_pins: spi1-cs-pins {
+ marvell,pins = "mpp55";
+ marvell,function = "spi1";
+ };
+ mikro_pins: mikro-pins {
+ /* int: mpp22 rst: mpp29 */
+ marvell,pins = "mpp22", "mpp29";
+ marvell,function = "gpio";
+ };
+ mikro_spi_pins: mikro-spi-pins {
+ marvell,pins = "mpp43";
+ marvell,function = "spi1";
+ };
+ mikro_uart_pins: mikro-uart-pins {
+ marvell,pins = "mpp24", "mpp25";
+ marvell,function = "ua1";
+ };
+ rear_button_pins: rear-button-pins {
+ marvell,pins = "mpp34";
+ marvell,function = "gpio";
+ };
+};
+
/*
+#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
MPP18: gpio ? (pca9655 int?)
bus-width = <4>;
cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
no-1-8-v;
- pinctrl-0 = <&helios_sdhci_pins
+ pinctrl-0 = <µsom_sdhci_pins
&helios_sdhci_cd_pins>;
pinctrl-names = "default";
status = "okay";
marvell,pins = "mpp20";
marvell,function = "gpio";
};
- helios_sdhci_pins: helios-sdhci-pins {
- marvell,pins = "mpp21", "mpp28",
- "mpp37", "mpp38",
- "mpp39", "mpp40";
- marvell,function = "sd0";
- };
helios_led_pins: helios-led-pins {
marvell,pins = "mpp24", "mpp25",
"mpp49", "mpp50",
w25q32: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "w25q32", "jedec,spi-nor";
+ compatible = "w25q32", "jedec,spi-nor", "spi-flash";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <3000000>;
status = "disabled";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Avnet Ultra96 rev1
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp-zcu100-revC.dts"
+
+/ {
+ model = "Avnet Ultra96 Rev1";
+ compatible = "avnet,ultra96-rev1", "avnet,ultra96",
+ "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100",
+ "xlnx,zynqmp";
+};
/{
pinctrl_0: pinctrl@11400000 {
- #address-cells = <1>;
- #size-cells = <1>;
compatible = "samsung,exynos4210-pinctrl";
};
};
pinctrl_2: pinctrl@03860000 {
- #address-cells = <1>;
- #size-cells = <1>;
};
};
gpio-mosi = <&gpy3 3 0>;
gpio-miso = <&gpy3 0 0>;
spi-delay-us = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
cs@0 {
};
};
};
pinctrl_2: pinctrl@03860000 {
- #address-cells = <1>;
- #size-cells = <1>;
};
pinctrl_3: pinctrl@106E0000 {
- #address-cells = <1>;
- #size-cells = <1>;
};
};
dp: dp@145b0000 {
compatible = "samsung,exynos5-dp";
reg = <0x145b0000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
};
xhci0: xhci@12000000 {
};
pinctrl_1: pinctrl@13400000 {
- #address-cells = <1>;
- #size-cells = <1>;
};
pinctrl_2: pinctrl@10d10000 {
};
pinctrl_3: pinctrl@03860000 {
- #address-cells = <1>;
- #size-cells = <1>;
};
};
spi2 = "/spi@12d40000";
spi3 = "/spi@131a0000";
spi4 = "/spi@131b0000";
- mmc0 = "/mmc@12000000";
+ mmc0 = "/mmc@12200000";
serial0 = "/serial@12C30000";
console = "/serial@12C30000";
i2s = "/sound@3830000";
* numbers are not needed in U-Boot for exynos.
*/
pinctrl@14010000 {
- #address-cells = <1>;
- #size-cells = <1>;
};
pinctrl@13400000 {
#address-cells = <1>;
};
};
pinctrl@13410000 {
- #address-cells = <1>;
- #size-cells = <1>;
};
pinctrl@14000000 {
- #address-cells = <1>;
- #size-cells = <1>;
};
pinctrl@03860000 {
- #address-cells = <1>;
- #size-cells = <1>;
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-98dx4122.dtsi"
+
+/ {
+ model = "Allied Telesis SBx81LIFXCAT Board";
+ compatible = "atl,SBx8LIFXCAT", "marvell,kirkwood-98DX4122",
+ "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>; /* 128 MB */
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ ethernet0 = ð0;
+ i2c0 = &i2c0;
+ spi0 = &spi0;
+ };
+
+ dsa {
+ compatible = "marvell,dsa";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ dsa,ethernet = <ð0>;
+ dsa,mii-bus = <&mdio>;
+ status = "okay";
+
+ switch@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1 0>;
+
+ port@0 {
+ reg = <0>;
+ label = "internal0";
+ };
+ port@1 {
+ reg = <1>;
+ label = "internal1";
+ };
+ port@8 {
+ reg = <8>;
+ label = "internal8";
+ phy-mode = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ port@9 {
+ reg = <9>;
+ label = "internal9";
+ phy-mode = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ port@10 {
+ reg = <10>;
+ label = "cpu";
+ };
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ ledn {
+ label = "status:ledn";
+ gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+ };
+
+ ledp {
+ label = "status:ledp";
+ gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p128", "jedec,spi-nor", "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ mode = <0>;
+
+ partition@u-boot {
+ reg = <0x00000000 0x00c00000>;
+ label = "u-boot";
+ };
+ partition@u-boot-env {
+ reg = <0x00c00000 0x00040000>;
+ label = "u-boot-env";
+ };
+ partition@unused {
+ reg = <0x00100000 0x00f00000>;
+ label = "unused";
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@52 {
+ compatible = "atmel,24c04";
+ reg = <0x52>;
+ };
+
+ gpio3: gpio@76 {
+ #gpio-cells = <2>;
+ compatible = "nxp,pca9539";
+ reg = <0x76>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+};
+
+ð0 {
+ status = "okay";
+
+ ethernet0-port@0 {
+ speed = <1000>;
+ duplex = <1>;
+ };
+};
mmc1 = &sdmmc2;
i2c3 = &i2c4;
};
+
+ led {
+ compatible = "gpio-leds";
+
+ red {
+ label = "stm32mp:red:status";
+ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ green {
+ label = "stm32mp:green:user";
+ gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+ orange {
+ label = "stm32mp:orange:status";
+ gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ blue {
+ label = "stm32mp:blue:user";
+ gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
+ };
+ };
};
&uart4_pins_a {
#size-cells = <1>;
ranges;
- slcr: slcr@f8000000 {
+ slcr: slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
};
};
};
-
};
&dcc {
clkc: clkc@100 {
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
- fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll",
"iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x",
};
};
};
-
};
&dcc {
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
+ num-cs = <1>;
+ flash@0 {
+ compatible = "spansion,s25fl256s", "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <30000000>;
+ m25p,fast-read;
+ };
};
&sdhci0 {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 - 2015 Xilinx
+ * Copyright (C) 2012 National Instruments Corp.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Digilent Zybo Z7 board";
+ compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
+
+ aliases {
+ ethernet0 = &gem0;
+ serial0 = &uart1;
+ spi0 = &qspi;
+ mmc0 = &sdhci0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "";
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ ld4 {
+ label = "zynq-zybo-z7:green:ld4";
+ gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ usb_phy0: phy0 {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&clkc {
+ ps-clk-frequency = <33333333>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ device_type = "ethernet-phy";
+ };
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&sdhci0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&uart1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
reg = <0x0 0xff170000 0x0 0x1000>;
- clock-names = "clk_xin", "clk_xin";
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clk_xin &clk_xin>;
xlnx,device_id = <1>;
};
};
*/
#define RKUSB_BUF_SIZE EP_BUFFER_SIZE * 2
+#define RKBLOCK_BUF_SIZE 4096
#define RKUSB_STATUS_IDLE 0
#define RKUSB_STATUS_CMD 1
K_FW_SET_RESET_FLAG = 0x1E,
K_FW_SPI_READ_10 = 0x21,
K_FW_SPI_WRITE_10 = 0x22,
+K_FW_LBA_ERASE_10 = 0x25,
K_FW_SESSION = 0X30,
K_FW_RESET = 0xff,
unsigned int lba;
unsigned int dl_size;
unsigned int dl_bytes;
+ unsigned int ul_size;
+ unsigned int ul_bytes;
struct blk_desc *desc;
int reboot_flag;
void *buf;
config TARGET_SBx81LIFKW
bool "Allied Telesis SBx81GS24/SBx81GT40/SBx81XS6/SBx81XS16"
+config TARGET_SBx81LIFXCAT
+ bool "Allied Telesis SBx81GP24/SBx81GT24"
+
endchoice
config SYS_SOC
source "board/Seagate/nas220/Kconfig"
source "board/zyxel/nsa310s/Kconfig"
source "board/alliedtelesis/SBx81LIFKW/Kconfig"
+source "board/alliedtelesis/SBx81LIFXCAT/Kconfig"
endif
default "ds414" if TARGET_DS414
default "maxbcm" if TARGET_MAXBCM
default "theadorable" if TARGET_THEADORABLE
+ default "a38x" if TARGET_CONTROLCENTERDC
config SYS_CONFIG_NAME
default "clearfog" if TARGET_CLEARFOG
default "theadorable" if TARGET_THEADORABLE
default "turris_omnia" if TARGET_TURRIS_OMNIA
default "turris_mox" if TARGET_TURRIS_MOX
+ default "controlcenterdc" if TARGET_CONTROLCENTERDC
config SYS_VENDOR
default "Marvell" if TARGET_DB_MV784MP_GP
default "Synology" if TARGET_DS414
default "CZ.NIC" if TARGET_TURRIS_OMNIA
default "CZ.NIC" if TARGET_TURRIS_MOX
+ default "gdsys" if TARGET_CONTROLCENTERDC
config SYS_SOC
default "mvebu"
-if TARGET_TURRIS_OMNIA
-
choice
- prompt "Turris Omnia boot method"
+ prompt "Boot method"
-config TURRIS_OMNIA_SPL_BOOT_DEVICE_SPI
+config MVEBU_SPL_BOOT_DEVICE_SPI
bool "SPI NOR flash"
-config TURRIS_OMNIA_SPL_BOOT_DEVICE_MMC
+config MVEBU_SPL_BOOT_DEVICE_MMC
bool "SDIO/MMC card"
+ select SPL_LIBDISK_SUPPORT
-endchoice
+config MVEBU_SPL_BOOT_DEVICE_UART
+ bool "UART"
-endif
+endchoice
config MVEBU_EFUSE
bool "Enable eFuse support"
obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_MVEBU_EFUSE) += efuse.o
+
+extra-y += kwbimage.cfg
+
+KWB_REPLACE += BOOT_FROM
+ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI),)
+ KWB_CFG_BOOT_FROM=spi
+endif
+ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC),)
+ KWB_CFG_BOOT_FROM=sdio
+endif
+ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_UART),)
+ KWB_CFG_BOOT_FROM=uart
+endif
+
+ifneq ($(CONFIG_SECURED_MODE_IMAGE),)
+KWB_REPLACE += CSK_INDEX
+KWB_CFG_CSK_INDEX = $(CONFIG_SECURED_MODE_CSK_INDEX)
+
+KWB_REPLACE += SEC_BOOT_DEV
+KWB_CFG_SEC_BOOT_DEV=$(patsubst "%",%, \
+ $(if $(findstring BOOT_SPI_NOR_FLASH,$(CONFIG_SPL_BOOT_DEVICE)),0x34) \
+ $(if $(findstring BOOT_SDIO_MMC_CARD,$(CONFIG_SPL_BOOT_DEVICE)),0x31) \
+ )
+
+KWB_REPLACE += SEC_FUSE_DUMP
+KWB_CFG_SEC_FUSE_DUMP = a38x
+endif
+
+$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
+ include/config/auto.conf
+ $(Q)sed -ne '$(foreach V,$(KWB_REPLACE),s/^#@$(V)/$(V) $(KWB_CFG_$(V))/;)p' \
+ <$< >$(dir $<)$(@F)
+
endif # CONFIG_SPL_BUILD
obj-y += gpio.o
obj-y += mbus.o
#endif
/*
- * By default kwbimage.cfg from board specific folder is used
+ * By default the generated mvebu kwbimage.cfg is used
* If for some board, different configuration file need to be used,
* CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
*/
#ifndef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
+#define CONFIG_SYS_KWD_CONFIG arch/arm/mach-mvebu/kwbimage.cfg
#endif /* CONFIG_SYS_KWD_CONFIG */
/* Add target to build it automatically upon "make" */
obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-apq8016.o
obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-snapdragon.o
obj-y += clock-snapdragon.o
+obj-y += dram.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Onboard memory detection for Snapdragon boards
+ *
+ * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <smem.h>
+#include <fdt_support.h>
+#include <asm/arch/dram.h>
+
+#define SMEM_USABLE_RAM_PARTITION_TABLE 402
+#define RAM_PART_NAME_LENGTH 16
+#define RAM_NUM_PART_ENTRIES 32
+#define CATEGORY_SDRAM 0x0E
+#define TYPE_SYSMEM 0x01
+
+struct smem_ram_ptable_hdr {
+ u32 magic[2];
+ u32 version;
+ u32 reserved;
+ u32 len;
+} __attribute__ ((__packed__));
+
+struct smem_ram_ptn {
+ char name[RAM_PART_NAME_LENGTH];
+ u64 start;
+ u64 size;
+ u32 attr;
+ u32 category;
+ u32 domain;
+ u32 type;
+ u32 num_partitions;
+ u32 reserved[3];
+} __attribute__ ((__packed__));
+
+struct smem_ram_ptable {
+ struct smem_ram_ptable_hdr hdr;
+ u32 reserved; /* Added for 8 bytes alignment of header */
+ struct smem_ram_ptn parts[RAM_NUM_PART_ENTRIES];
+} __attribute__ ((__packed__));
+
+#ifndef MEMORY_BANKS_MAX
+#define MEMORY_BANKS_MAX 4
+#endif
+
+int msm_fixup_memory(void *blob)
+{
+ u64 bank_start[MEMORY_BANKS_MAX];
+ u64 bank_size[MEMORY_BANKS_MAX];
+ size_t size;
+ int i;
+ int count = 0;
+ struct udevice *smem;
+ int ret;
+ struct smem_ram_ptable *ram_ptable;
+ struct smem_ram_ptn *p;
+
+ ret = uclass_get_device_by_name(UCLASS_SMEM, "smem", &smem);
+ if (ret < 0) {
+ printf("Failed to find SMEM node. Check device tree\n");
+ return 0;
+ }
+
+ ram_ptable = smem_get(smem, -1, SMEM_USABLE_RAM_PARTITION_TABLE, &size);
+
+ if (!ram_ptable) {
+ printf("Failed to find SMEM partition.\n");
+ return -ENODEV;
+ }
+
+ /* Check validy of RAM */
+ for (i = 0; i < RAM_NUM_PART_ENTRIES; i++) {
+ p = &ram_ptable->parts[i];
+ if (p->category == CATEGORY_SDRAM && p->type == TYPE_SYSMEM) {
+ bank_start[count] = p->start;
+ bank_size[count] = p->size;
+ debug("Detected memory bank %u: start: 0x%llx size: 0x%llx\n",
+ count, p->start, p->size);
+ count++;
+ }
+ }
+
+ if (!count) {
+ printf("Failed to detect any memory bank\n");
+ return -ENODEV;
+ }
+
+ ret = fdt_fixup_memory_banks(blob, bank_start, bank_size, count);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Snapdragon DRAM
+ * Copyright (C) 2018 Ramon Fried <ramon.fried@gmail.com>
+ */
+
+#ifndef DRAM_H
+#define DRAM_H
+
+int msm_fixup_memory(void *blob);
+
+#endif
config SYS_MALLOC_F_LEN
default 0x600
+config SYS_MALLOC_LEN
+ default 0x1400000
+
config BOOT_INIT_FILE
string "boot.bin init register filename"
default ""
select SUPPORTS_CPU_MIPS32_R2
select SYS_MIPS_CACHE_INIT_RAM_LOAD
-config TARGET_DBAU1X00
- bool "Support dbau1x00"
- select MIPS_TUNE_4KC
- select ROM_EXCEPTION_VECTORS
- select SUPPORTS_BIG_ENDIAN
- select SUPPORTS_CPU_MIPS32_R1
- select SUPPORTS_CPU_MIPS32_R2
- select SUPPORTS_LITTLE_ENDIAN
- select SYS_MIPS_CACHE_INIT_RAM_LOAD
-
-config TARGET_PB1X00
- bool "Support pb1x00"
- select MIPS_TUNE_4KC
- select ROM_EXCEPTION_VECTORS
- select SUPPORTS_CPU_MIPS32_R1
- select SUPPORTS_CPU_MIPS32_R2
- select SUPPORTS_LITTLE_ENDIAN
- select SYS_MIPS_CACHE_INIT_RAM_LOAD
-
config ARCH_ATH79
bool "Support QCA/Atheros ath79"
select DM
endchoice
-source "board/dbau1x00/Kconfig"
source "board/imgtec/boston/Kconfig"
source "board/imgtec/malta/Kconfig"
source "board/imgtec/xilfpga/Kconfig"
source "board/micronas/vct/Kconfig"
-source "board/pb1x00/Kconfig"
source "board/qemu-mips/Kconfig"
source "arch/mips/mach-ath79/Kconfig"
source "arch/mips/mach-bmips/Kconfig"
libs-y += arch/mips/cpu/
libs-y += arch/mips/lib/
-machine-$(CONFIG_SOC_AU1X00) += au1x00
machine-$(CONFIG_ARCH_ATH79) += ath79
machine-$(CONFIG_ARCH_BMIPS) += bmips
machine-$(CONFIG_MACH_PIC32) += pic32
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "brcm,bcm6838";
+
+ cpus {
+ reg = <0x14e00000 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+
+ cpu@0 {
+ compatible = "brcm,bcm6838-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ cpu@1 {
+ compatible = "brcm,bcm6838-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <1>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ periph_osc: periph-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ ubus {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ memory: memory-controller@12000000 {
+ compatible = "brcm,bcm6328-mc";
+ reg = <0x12000000 0x1000>;
+ u-boot,dm-pre-reloc;
+ };
+
+ uart0: serial@14e00500 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x14e00500 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ leds: led-controller@14e00f00 {
+ compatible = "brcm,bcm6328-leds";
+ reg = <0x14e00f00 0x28>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm6838.dtsi"
+
+/ {
+ model = "Broadcom bcm68380gerg";
+ compatible = "broadcom,bcm68380gerg", "brcm,bcm6838";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&memory {
+ force-size = <0x10000000>;
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&leds {
+ status = "okay";
+
+ led@0 {
+ reg = <0>;
+ active-low;
+ label = "bcm968380gerg:green:usb";
+ };
+};
* Returns the uncached address of a sdram address
*/
#ifndef __ASSEMBLY__
-#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229)
+#if defined(CONFIG_TB0229)
/* We use a 36 bit physical address map here and
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
-#else /* !CONFIG_SOC_AU1X00 */
+#else /* !CONFIG_TB0229 */
#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
-#endif /* CONFIG_SOC_AU1X00 */
+#endif /* CONFIG_TB0229 */
#endif /* __ASSEMBLY__ */
/*
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2011
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y = au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o au1x00_ide.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/* Only eth0 supported for now
- *
- * (C) Copyright 2003
- * Thomas.Lange@corelatus.se
- */
-#include <config.h>
-
-#if defined(CONFIG_SYS_DISCOVER_PHY)
-#error "PHY not supported yet"
-/* We just assume that we are running 100FD for now */
-/* We all use switches, right? ;-) */
-#endif
-
-/* I assume ethernet behaves like au1000 */
-
-#ifdef CONFIG_SOC_AU1000
-/* Base address differ between cpu:s */
-#define ETH0_BASE AU1000_ETH0_BASE
-#define MAC0_ENABLE AU1000_MAC0_ENABLE
-#else
-#ifdef CONFIG_SOC_AU1100
-#define ETH0_BASE AU1100_ETH0_BASE
-#define MAC0_ENABLE AU1100_MAC0_ENABLE
-#else
-#ifdef CONFIG_SOC_AU1500
-#define ETH0_BASE AU1500_ETH0_BASE
-#define MAC0_ENABLE AU1500_MAC0_ENABLE
-#else
-#ifdef CONFIG_SOC_AU1550
-#define ETH0_BASE AU1550_ETH0_BASE
-#define MAC0_ENABLE AU1550_MAC0_ENABLE
-#else
-#error "No valid cpu set"
-#endif
-#endif
-#endif
-#endif
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <command.h>
-#include <asm/io.h>
-#include <mach/au1x00.h>
-
-#if defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-#endif
-
-/* Ethernet Transmit and Receive Buffers */
-#define DBUF_LENGTH 1520
-#define PKT_MAXBUF_SIZE 1518
-
-static char txbuf[DBUF_LENGTH];
-
-static int next_tx;
-static int next_rx;
-
-/* 4 rx and 4 tx fifos */
-#define NO_OF_FIFOS 4
-
-typedef struct{
- u32 status;
- u32 addr;
- u32 len; /* Only used for tx */
- u32 not_used;
-} mac_fifo_t;
-
-mac_fifo_t mac_fifo[NO_OF_FIFOS];
-
-#define MAX_WAIT 1000
-
-#if defined(CONFIG_CMD_MII)
-int au1x00_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
-{
- unsigned short value = 0;
- volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
- volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
- u32 mii_control;
- unsigned int timedout = 20;
-
- while (*mii_control_reg & MAC_MII_BUSY) {
- udelay(1000);
- if (--timedout == 0) {
- printf("au1x00_eth: miiphy_read busy timeout!!\n");
- return -1;
- }
- }
-
- mii_control = MAC_SET_MII_SELECT_REG(reg) |
- MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
-
- *mii_control_reg = mii_control;
-
- timedout = 20;
- while (*mii_control_reg & MAC_MII_BUSY) {
- udelay(1000);
- if (--timedout == 0) {
- printf("au1x00_eth: miiphy_read busy timeout!!\n");
- return -1;
- }
- }
- value = *mii_data_reg;
- return value;
-}
-
-int au1x00_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
- u16 value)
-{
- volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
- volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
- u32 mii_control;
- unsigned int timedout = 20;
-
- while (*mii_control_reg & MAC_MII_BUSY) {
- udelay(1000);
- if (--timedout == 0) {
- printf("au1x00_eth: miiphy_write busy timeout!!\n");
- return -1;
- }
- }
-
- mii_control = MAC_SET_MII_SELECT_REG(reg) |
- MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
-
- *mii_data_reg = value;
- *mii_control_reg = mii_control;
- return 0;
-}
-#endif
-
-static int au1x00_send(struct eth_device *dev, void *packet, int length)
-{
- volatile mac_fifo_t *fifo_tx =
- (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
- int i;
- int res;
-
- /* tx fifo should always be idle */
- fifo_tx[next_tx].len = length;
- fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
- au_sync();
-
- udelay(1);
- i=0;
- while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
- if(i>MAX_WAIT){
- printf("TX timeout\n");
- break;
- }
- udelay(1);
- i++;
- }
-
- /* Clear done bit */
- fifo_tx[next_tx].addr = 0;
- fifo_tx[next_tx].len = 0;
- au_sync();
-
- res = fifo_tx[next_tx].status;
-
- next_tx++;
- if(next_tx>=NO_OF_FIFOS){
- next_tx=0;
- }
- return(res);
-}
-
-static int au1x00_recv(struct eth_device* dev){
- volatile mac_fifo_t *fifo_rx =
- (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
-
- int length;
- u32 status;
-
- for(;;){
- if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
- /* Nothing has been received */
- return(-1);
- }
-
- status = fifo_rx[next_rx].status;
-
- length = status&0x3FFF;
-
- if(status&RX_ERROR){
- printf("Rx error 0x%x\n", status);
- } else {
- /* Pass the packet up to the protocol layers. */
- net_process_received_packet(net_rx_packets[next_rx],
- length - 4);
- }
-
- fifo_rx[next_rx].addr =
- (virt_to_phys(net_rx_packets[next_rx])) | RX_DMA_ENABLE;
-
- next_rx++;
- if(next_rx>=NO_OF_FIFOS){
- next_rx=0;
- }
- } /* for */
-
- return(0); /* Does anyone use this? */
-}
-
-static int au1x00_init(struct eth_device* dev, bd_t * bd){
-
- volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
- volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
- volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
- volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
- volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
- volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
- volatile mac_fifo_t *fifo_tx =
- (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
- volatile mac_fifo_t *fifo_rx =
- (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
- int i;
-
- next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
- next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
-
- /* We have to enable clocks before releasing reset */
- *macen = MAC_EN_CLOCK_ENABLE;
- udelay(10);
-
- /* Enable MAC0 */
- /* We have to release reset before accessing registers */
- *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
- MAC_EN_RESET1|MAC_EN_RESET2;
- udelay(10);
-
- for(i=0;i<NO_OF_FIFOS;i++){
- fifo_tx[i].len = 0;
- fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
- fifo_rx[i].addr = (virt_to_phys(net_rx_packets[i])) |
- RX_DMA_ENABLE;
- }
-
- /* Put mac addr in little endian */
-#define ea eth_get_ethaddr()
- *mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
- *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
- (ea[1] << 8) | (ea[0] ) ;
-#undef ea
- *mac_mcast_low = 0;
- *mac_mcast_high = 0;
-
- /* Make sure the MAC buffer is in the correct endian mode */
-#ifdef __LITTLE_ENDIAN
- *mac_ctrl = MAC_FULL_DUPLEX;
- udelay(1);
- *mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
-#else
- *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
- udelay(1);
- *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
-#endif
-
- return(1);
-}
-
-static void au1x00_halt(struct eth_device* dev){
- volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
-
- /* Put MAC0 in reset */
- *macen = 0;
-}
-
-int au1x00_enet_initialize(bd_t *bis){
- struct eth_device* dev;
-
- if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
- puts ("malloc failed\n");
- return -1;
- }
-
- memset(dev, 0, sizeof *dev);
-
- strcpy(dev->name, "Au1X00 ethernet");
- dev->iobase = 0;
- dev->priv = 0;
- dev->init = au1x00_init;
- dev->halt = au1x00_halt;
- dev->send = au1x00_send;
- dev->recv = au1x00_recv;
-
- eth_register(dev);
-
-#if defined(CONFIG_CMD_MII)
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = au1x00_miiphy_read;
- mdiodev->write = au1x00_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-#endif
-
- return 1;
-}
-
-int cpu_eth_init(bd_t *bis)
-{
- au1x00_enet_initialize(bis);
- return 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2011
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <ide.h>
-
-/* AU1X00 swaps data in big-endian mode, enforce little-endian function */
-void ide_input_swap_data(int dev, ulong *sect_buf, int words)
-{
- ide_input_data(dev, sect_buf, words);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * AU1X00 UART support
- *
- * Hardcoded to UART 0 for now
- * Speed and options also hardcoded to 115200 8N1
- *
- * Copyright (c) 2003 Thomas.Lange@corelatus.se
- */
-
-#include <config.h>
-#include <common.h>
-#include <mach/au1x00.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-/******************************************************************************
-*
-* serial_init - initialize a channel
-*
-* This routine initializes the number of data bits, parity
-* and set the selected baud rate. Interrupts are disabled.
-* Set the modem control signals if the option is selected.
-*
-* RETURNS: N/A
-*/
-
-static int au1x00_serial_init(void)
-{
- volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR);
- volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE);
-
- /* Enable clocks first */
- *uart_enable = UART_EN_CE;
-
- /* Then release reset */
- /* Must release reset before setting other regs */
- *uart_enable = UART_EN_CE|UART_EN_E;
-
- /* Activate fifos, reset tx and rx */
- /* Set tx trigger level to 12 */
- *uart_fifoctl = UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|
- UART_FCR_CLEAR_XMIT|UART_FCR_T_TRIGGER_12;
-
- serial_setbrg();
-
- return 0;
-}
-
-
-static void au1x00_serial_setbrg(void)
-{
- volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
- volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
- volatile u32 *sys_powerctrl = (u32 *)SYS_POWERCTRL;
- int sd;
- int divisorx2;
-
- /* sd is system clock divisor */
- /* see section 10.4.5 in au1550 datasheet */
- sd = (*sys_powerctrl & 0x03) + 2;
-
- /* calulate 2x baudrate and round */
- divisorx2 = ((CONFIG_SYS_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE)));
-
- if (divisorx2 & 0x01)
- divisorx2 = divisorx2 + 1;
-
- *uart_clk = divisorx2 / 2;
-
- /* Set parity, stop bits and word length to 8N1 */
- *uart_lcr = UART_LCR_WLEN8;
-}
-
-static void au1x00_serial_putc(const char c)
-{
- volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
- volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX);
-
- if (c == '\n')
- au1x00_serial_putc('\r');
-
- /* Wait for fifo to shift out some bytes */
- while((*uart_lsr&UART_LSR_THRE)==0);
-
- *uart_tx = (u32)c;
-}
-
-static int au1x00_serial_getc(void)
-{
- volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
- char c;
-
- while (!serial_tstc());
-
- c = (*uart_rx&0xFF);
- return c;
-}
-
-static int au1x00_serial_tstc(void)
-{
- volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
-
- if(*uart_lsr&UART_LSR_DR){
- /* Data in rfifo */
- return(1);
- }
- return 0;
-}
-
-static struct serial_device au1x00_serial_drv = {
- .name = "au1x00_serial",
- .start = au1x00_serial_init,
- .stop = NULL,
- .setbrg = au1x00_serial_setbrg,
- .putc = au1x00_serial_putc,
- .puts = default_serial_puts,
- .getc = au1x00_serial_getc,
- .tstc = au1x00_serial_tstc,
-};
-
-void au1x00_serial_initialize(void)
-{
- serial_register(&au1x00_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &au1x00_serial_drv;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00.
- *
- * (C) Copyright 2003
- * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
- * Note: Part of this code has been derived from linux
- *
- */
-/*
- * IMPORTANT NOTES
- * 1 - this driver is intended for use with USB Mass Storage Devices
- * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
- */
-
-#include <config.h>
-
-#ifdef CONFIG_USB_OHCI
-
-/* #include <pci.h> no PCI on the AU1x00 */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <mach/au1x00.h>
-#include <usb.h>
-#include "au1x00_usb_ohci.h"
-
-#define OHCI_USE_NPS /* force NoPowerSwitching mode */
-#define OHCI_VERBOSE_DEBUG /* not always helpful */
-#define OHCI_FILL_TRACE
-
-#define USBH_ENABLE_BE (1<<0)
-#define USBH_ENABLE_C (1<<1)
-#define USBH_ENABLE_E (1<<2)
-#define USBH_ENABLE_CE (1<<3)
-#define USBH_ENABLE_RD (1<<4)
-
-#ifdef __LITTLE_ENDIAN
-#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C)
-#else
-#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE)
-#endif
-
-
-/* For initializing controller (mask in an HCFS mode too) */
-#define OHCI_CONTROL_INIT \
- (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
-
-#undef readl
-#undef writel
-
-#define readl(a) au_readl((long)(a))
-#define writel(v,a) au_writel((v),(int)(a))
-
-#define DEBUG
-#ifdef DEBUG
-#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
-#else
-#define dbg(format, arg...) do {} while(0)
-#endif /* DEBUG */
-#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
-#define SHOW_INFO
-#ifdef SHOW_INFO
-#define info(format, arg...) printf("INFO: " format "\n", ## arg)
-#else
-#define info(format, arg...) do {} while(0)
-#endif
-
-#define m16_swap(x) swap_16(x)
-#define m32_swap(x) swap_32(x)
-
-/* global ohci_t */
-static ohci_t gohci;
-/* this must be aligned to a 256 byte boundary */
-struct ohci_hcca ghcca[1];
-/* a pointer to the aligned storage */
-struct ohci_hcca *phcca;
-/* this allocates EDs for all possible endpoints */
-struct ohci_device ohci_dev;
-/* urb_priv */
-urb_priv_t urb_priv;
-/* RHSC flag */
-int got_rhsc;
-/* device which was disconnected */
-struct usb_device *devgone;
-
-/*-------------------------------------------------------------------------*/
-
-/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
- * The erratum (#4) description is incorrect. AMD's workaround waits
- * till some bits (mostly reserved) are clear; ok for all revs.
- */
-#define OHCI_QUIRK_AMD756 0xabcd
-#define read_roothub(hc, register, mask) ({ \
- u32 temp = readl (&hc->regs->roothub.register); \
- if (hc->flags & OHCI_QUIRK_AMD756) \
- while (temp & mask) \
- temp = readl (&hc->regs->roothub.register); \
- temp; })
-
-static u32 roothub_a (struct ohci *hc)
- { return read_roothub (hc, a, 0xfc0fe000); }
-static inline u32 roothub_b (struct ohci *hc)
- { return readl (&hc->regs->roothub.b); }
-static inline u32 roothub_status (struct ohci *hc)
- { return readl (&hc->regs->roothub.status); }
-static u32 roothub_portstatus (struct ohci *hc, int i)
- { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
-
-
-/* forward declaration */
-static int hc_interrupt (void);
-static void
-td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
- int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
-
-/*-------------------------------------------------------------------------*
- * URB support functions
- *-------------------------------------------------------------------------*/
-
-/* free HCD-private data associated with this URB */
-
-static void urb_free_priv (urb_priv_t * urb)
-{
- int i;
- int last;
- struct td * td;
-
- last = urb->length - 1;
- if (last >= 0) {
- for (i = 0; i <= last; i++) {
- td = urb->td[i];
- if (td) {
- td->usb_dev = NULL;
- urb->td[i] = NULL;
- }
- }
- }
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-static int sohci_get_current_frame_number (struct usb_device * dev);
-
-/* debug| print the main components of an URB
- * small: 0) header + data packets 1) just header */
-
-static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
- int transfer_len, struct devrequest * setup, char * str, int small)
-{
- urb_priv_t * purb = &urb_priv;
-
- dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
- str,
- sohci_get_current_frame_number (dev),
- usb_pipedevice (pipe),
- usb_pipeendpoint (pipe),
- usb_pipeout (pipe)? 'O': 'I',
- usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
- (usb_pipecontrol (pipe)? "CTRL": "BULK"),
- purb->actual_length,
- transfer_len, dev->status);
-#ifdef OHCI_VERBOSE_DEBUG
- if (!small) {
- int i, len;
-
- if (usb_pipecontrol (pipe)) {
- printf (__FILE__ ": cmd(8):");
- for (i = 0; i < 8 ; i++)
- printf (" %02x", ((__u8 *) setup) [i]);
- printf ("\n");
- }
- if (transfer_len > 0 && buffer) {
- printf (__FILE__ ": data(%d/%d):",
- purb->actual_length,
- transfer_len);
- len = usb_pipeout (pipe)?
- transfer_len: purb->actual_length;
- for (i = 0; i < 16 && i < len; i++)
- printf (" %02x", ((__u8 *) buffer) [i]);
- printf ("%s\n", i < len? "...": "");
- }
- }
-#endif
-}
-
-/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
-void ep_print_int_eds (ohci_t *ohci, char * str) {
- int i, j;
- __u32 * ed_p;
- for (i= 0; i < 32; i++) {
- j = 5;
- ed_p = &(ohci->hcca->int_table [i]);
- if (*ed_p == 0)
- continue;
- printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
- while (*ed_p != 0 && j--) {
- ed_t *ed = (ed_t *)m32_swap(ed_p);
- printf (" ed: %4x;", ed->hwINFO);
- ed_p = &ed->hwNextED;
- }
- printf ("\n");
- }
-}
-
-static void ohci_dump_intr_mask (char *label, __u32 mask)
-{
- dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
- label,
- mask,
- (mask & OHCI_INTR_MIE) ? " MIE" : "",
- (mask & OHCI_INTR_OC) ? " OC" : "",
- (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
- (mask & OHCI_INTR_FNO) ? " FNO" : "",
- (mask & OHCI_INTR_UE) ? " UE" : "",
- (mask & OHCI_INTR_RD) ? " RD" : "",
- (mask & OHCI_INTR_SF) ? " SF" : "",
- (mask & OHCI_INTR_WDH) ? " WDH" : "",
- (mask & OHCI_INTR_SO) ? " SO" : ""
- );
-}
-
-static void maybe_print_eds (char *label, __u32 value)
-{
- ed_t *edp = (ed_t *)value;
-
- if (value) {
- dbg ("%s %08x", label, value);
- dbg ("%08x", edp->hwINFO);
- dbg ("%08x", edp->hwTailP);
- dbg ("%08x", edp->hwHeadP);
- dbg ("%08x", edp->hwNextED);
- }
-}
-
-static char * hcfs2string (int state)
-{
- switch (state) {
- case OHCI_USB_RESET: return "reset";
- case OHCI_USB_RESUME: return "resume";
- case OHCI_USB_OPER: return "operational";
- case OHCI_USB_SUSPEND: return "suspend";
- }
- return "?";
-}
-
-/* dump control and status registers */
-static void ohci_dump_status (ohci_t *controller)
-{
- struct ohci_regs *regs = controller->regs;
- __u32 temp;
-
- temp = readl (®s->revision) & 0xff;
- if (temp != 0x10)
- dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
-
- temp = readl (®s->control);
- dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
- (temp & OHCI_CTRL_RWE) ? " RWE" : "",
- (temp & OHCI_CTRL_RWC) ? " RWC" : "",
- (temp & OHCI_CTRL_IR) ? " IR" : "",
- hcfs2string (temp & OHCI_CTRL_HCFS),
- (temp & OHCI_CTRL_BLE) ? " BLE" : "",
- (temp & OHCI_CTRL_CLE) ? " CLE" : "",
- (temp & OHCI_CTRL_IE) ? " IE" : "",
- (temp & OHCI_CTRL_PLE) ? " PLE" : "",
- temp & OHCI_CTRL_CBSR
- );
-
- temp = readl (®s->cmdstatus);
- dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
- (temp & OHCI_SOC) >> 16,
- (temp & OHCI_OCR) ? " OCR" : "",
- (temp & OHCI_BLF) ? " BLF" : "",
- (temp & OHCI_CLF) ? " CLF" : "",
- (temp & OHCI_HCR) ? " HCR" : ""
- );
-
- ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus));
- ohci_dump_intr_mask ("intrenable", readl (®s->intrenable));
-
- maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent));
-
- maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead));
- maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent));
-
- maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead));
- maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent));
-
- maybe_print_eds ("donehead", readl (®s->donehead));
-}
-
-static void ohci_dump_roothub (ohci_t *controller, int verbose)
-{
- __u32 temp, ndp, i;
-
- temp = roothub_a (controller);
- ndp = (temp & RH_A_NDP);
-
- if (verbose) {
- dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
- ((temp & RH_A_POTPGT) >> 24) & 0xff,
- (temp & RH_A_NOCP) ? " NOCP" : "",
- (temp & RH_A_OCPM) ? " OCPM" : "",
- (temp & RH_A_DT) ? " DT" : "",
- (temp & RH_A_NPS) ? " NPS" : "",
- (temp & RH_A_PSM) ? " PSM" : "",
- ndp
- );
- temp = roothub_b (controller);
- dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
- temp,
- (temp & RH_B_PPCM) >> 16,
- (temp & RH_B_DR)
- );
- temp = roothub_status (controller);
- dbg ("roothub.status: %08x%s%s%s%s%s%s",
- temp,
- (temp & RH_HS_CRWE) ? " CRWE" : "",
- (temp & RH_HS_OCIC) ? " OCIC" : "",
- (temp & RH_HS_LPSC) ? " LPSC" : "",
- (temp & RH_HS_DRWE) ? " DRWE" : "",
- (temp & RH_HS_OCI) ? " OCI" : "",
- (temp & RH_HS_LPS) ? " LPS" : ""
- );
- }
-
- for (i = 0; i < ndp; i++) {
- temp = roothub_portstatus (controller, i);
- dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
- i,
- temp,
- (temp & RH_PS_PRSC) ? " PRSC" : "",
- (temp & RH_PS_OCIC) ? " OCIC" : "",
- (temp & RH_PS_PSSC) ? " PSSC" : "",
- (temp & RH_PS_PESC) ? " PESC" : "",
- (temp & RH_PS_CSC) ? " CSC" : "",
-
- (temp & RH_PS_LSDA) ? " LSDA" : "",
- (temp & RH_PS_PPS) ? " PPS" : "",
- (temp & RH_PS_PRS) ? " PRS" : "",
- (temp & RH_PS_POCI) ? " POCI" : "",
- (temp & RH_PS_PSS) ? " PSS" : "",
-
- (temp & RH_PS_PES) ? " PES" : "",
- (temp & RH_PS_CCS) ? " CCS" : ""
- );
- }
-}
-
-static void ohci_dump (ohci_t *controller, int verbose)
-{
- dbg ("OHCI controller usb-%s state", controller->slot_name);
-
- /* dumps some of the state we know about */
- ohci_dump_status (controller);
- if (verbose)
- ep_print_int_eds (controller, "hcca");
- dbg ("hcca frame #%04x", controller->hcca->frame_no);
- ohci_dump_roothub (controller, 1);
-}
-
-
-#endif /* DEBUG */
-
-/*-------------------------------------------------------------------------*
- * Interface functions (URB)
- *-------------------------------------------------------------------------*/
-
-/* get a transfer request */
-
-int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup, int interval)
-{
- ohci_t *ohci;
- ed_t * ed;
- urb_priv_t *purb_priv;
- int i, size = 0;
-
- ohci = &gohci;
-
- /* when controller's hung, permit only roothub cleanup attempts
- * such as powering down ports */
- if (ohci->disabled) {
- err("sohci_submit_job: EPIPE");
- return -1;
- }
-
- /* every endpoint has a ed, locate and fill it */
- if (!(ed = ep_add_ed (dev, pipe))) {
- err("sohci_submit_job: ENOMEM");
- return -1;
- }
-
- /* for the private part of the URB we need the number of TDs (size) */
- switch (usb_pipetype (pipe)) {
- case PIPE_BULK: /* one TD for every 4096 Byte */
- size = (transfer_len - 1) / 4096 + 1;
- break;
- case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
- size = (transfer_len == 0)? 2:
- (transfer_len - 1) / 4096 + 3;
- break;
- }
-
- if (size >= (N_URB_TD - 1)) {
- err("need %d TDs, only have %d", size, N_URB_TD);
- return -1;
- }
- purb_priv = &urb_priv;
- purb_priv->pipe = pipe;
-
- /* fill the private part of the URB */
- purb_priv->length = size;
- purb_priv->ed = ed;
- purb_priv->actual_length = 0;
-
- /* allocate the TDs */
- /* note that td[0] was allocated in ep_add_ed */
- for (i = 0; i < size; i++) {
- purb_priv->td[i] = td_alloc (dev);
- if (!purb_priv->td[i]) {
- purb_priv->length = i;
- urb_free_priv (purb_priv);
- err("sohci_submit_job: ENOMEM");
- return -1;
- }
- }
-
- if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
- urb_free_priv (purb_priv);
- err("sohci_submit_job: EINVAL");
- return -1;
- }
-
- /* link the ed into a chain if is not already */
- if (ed->state != ED_OPER)
- ep_link (ohci, ed);
-
- /* fill the TDs and link it to the ed */
- td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
-
- return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-/* tell us the current USB frame number */
-
-static int sohci_get_current_frame_number (struct usb_device *usb_dev)
-{
- ohci_t *ohci = &gohci;
-
- return m16_swap (ohci->hcca->frame_no);
-}
-#endif
-
-/*-------------------------------------------------------------------------*
- * ED handling functions
- *-------------------------------------------------------------------------*/
-
-/* link an ed into one of the HC chains */
-
-static int ep_link (ohci_t *ohci, ed_t *edi)
-{
- volatile ed_t *ed = edi;
-
- ed->state = ED_OPER;
-
- switch (ed->type) {
- case PIPE_CONTROL:
- ed->hwNextED = 0;
- if (ohci->ed_controltail == NULL) {
- writel ((long)ed, &ohci->regs->ed_controlhead);
- } else {
- ohci->ed_controltail->hwNextED = m32_swap (ed);
- }
- ed->ed_prev = ohci->ed_controltail;
- if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
- !ohci->ed_rm_list[1] && !ohci->sleeping) {
- ohci->hc_control |= OHCI_CTRL_CLE;
- writel (ohci->hc_control, &ohci->regs->control);
- }
- ohci->ed_controltail = edi;
- break;
-
- case PIPE_BULK:
- ed->hwNextED = 0;
- if (ohci->ed_bulktail == NULL) {
- writel ((long)ed, &ohci->regs->ed_bulkhead);
- } else {
- ohci->ed_bulktail->hwNextED = m32_swap (ed);
- }
- ed->ed_prev = ohci->ed_bulktail;
- if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
- !ohci->ed_rm_list[1] && !ohci->sleeping) {
- ohci->hc_control |= OHCI_CTRL_BLE;
- writel (ohci->hc_control, &ohci->regs->control);
- }
- ohci->ed_bulktail = edi;
- break;
- }
- return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* unlink an ed from one of the HC chains.
- * just the link to the ed is unlinked.
- * the link from the ed still points to another operational ed or 0
- * so the HC can eventually finish the processing of the unlinked ed */
-
-static int ep_unlink (ohci_t *ohci, ed_t *ed)
-{
- ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
-
- switch (ed->type) {
- case PIPE_CONTROL:
- if (ed->ed_prev == NULL) {
- if (!ed->hwNextED) {
- ohci->hc_control &= ~OHCI_CTRL_CLE;
- writel (ohci->hc_control, &ohci->regs->control);
- }
- writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
- } else {
- ed->ed_prev->hwNextED = ed->hwNextED;
- }
- if (ohci->ed_controltail == ed) {
- ohci->ed_controltail = ed->ed_prev;
- } else {
- ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
- }
- break;
-
- case PIPE_BULK:
- if (ed->ed_prev == NULL) {
- if (!ed->hwNextED) {
- ohci->hc_control &= ~OHCI_CTRL_BLE;
- writel (ohci->hc_control, &ohci->regs->control);
- }
- writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
- } else {
- ed->ed_prev->hwNextED = ed->hwNextED;
- }
- if (ohci->ed_bulktail == ed) {
- ohci->ed_bulktail = ed->ed_prev;
- } else {
- ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
- }
- break;
- }
- ed->state = ED_UNLINK;
- return 0;
-}
-
-
-/*-------------------------------------------------------------------------*/
-
-/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
- * but the USB stack is a little bit stateless so we do it at every transaction
- * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
- * in all other cases the state is left unchanged
- * the ed info fields are setted anyway even though most of them should not change */
-
-static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
-{
- td_t *td;
- ed_t *ed_ret;
- volatile ed_t *ed;
-
- ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
- (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
-
- if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
- err("ep_add_ed: pending delete");
- /* pending delete request */
- return NULL;
- }
-
- if (ed->state == ED_NEW) {
- ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
- /* dummy td; end of td list for ed */
- td = td_alloc (usb_dev);
- ed->hwTailP = m32_swap (td);
- ed->hwHeadP = ed->hwTailP;
- ed->state = ED_UNLINK;
- ed->type = usb_pipetype (pipe);
- ohci_dev.ed_cnt++;
- }
-
- ed->hwINFO = m32_swap (usb_pipedevice (pipe)
- | usb_pipeendpoint (pipe) << 7
- | (usb_pipeisoc (pipe)? 0x8000: 0)
- | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
- | (usb_dev->speed == USB_SPEED_LOW) << 13
- | usb_maxpacket (usb_dev, pipe) << 16);
-
- return ed_ret;
-}
-
-/*-------------------------------------------------------------------------*
- * TD handling functions
- *-------------------------------------------------------------------------*/
-
-/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
-
-static void td_fill (ohci_t *ohci, unsigned int info,
- void *data, int len,
- struct usb_device *dev, int index, urb_priv_t *urb_priv)
-{
- volatile td_t *td, *td_pt;
-#ifdef OHCI_FILL_TRACE
- int i;
-#endif
-
- if (index > urb_priv->length) {
- err("index > length");
- return;
- }
- /* use this td as the next dummy */
- td_pt = urb_priv->td [index];
- td_pt->hwNextTD = 0;
-
- /* fill the old dummy TD */
- td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
-
- td->ed = urb_priv->ed;
- td->next_dl_td = NULL;
- td->index = index;
- td->data = (__u32)data;
-#ifdef OHCI_FILL_TRACE
- if (1 || (usb_pipebulk(urb_priv->pipe) &&
- usb_pipeout(urb_priv->pipe))) {
- for (i = 0; i < len; i++)
- printf("td->data[%d] %#2x\n",i, ((unsigned char *)(td->data+0x80000000))[i]);
- }
-#endif
- if (!len)
- data = 0;
-
- td->hwINFO = m32_swap (info);
- td->hwCBP = m32_swap (data);
- if (data)
- td->hwBE = m32_swap (data + len - 1);
- else
- td->hwBE = 0;
- td->hwNextTD = m32_swap (td_pt);
- td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
-
- /* append to queue */
- td->ed->hwTailP = td->hwNextTD;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* prepare all TDs of a transfer */
-
-#define kseg_to_phys(x) ((void *)((__u32)(x) - 0x80000000))
-
-static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
-{
- ohci_t *ohci = &gohci;
- int data_len = transfer_len;
- void *data;
- int cnt = 0;
- __u32 info = 0;
- unsigned int toggle = 0;
-
- /* OHCI handles the DATA-toggles itself, we just use the
- USB-toggle bits for resetting */
- if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
- toggle = TD_T_TOGGLE;
- } else {
- toggle = TD_T_DATA0;
- usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
- }
- urb->td_cnt = 0;
- if (data_len)
- data = kseg_to_phys(buffer);
- else
- data = 0;
-
- switch (usb_pipetype (pipe)) {
- case PIPE_BULK:
- info = usb_pipeout (pipe)?
- TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
- while(data_len > 4096) {
- td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
- data += 4096; data_len -= 4096; cnt++;
- }
- info = usb_pipeout (pipe)?
- TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
- td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
- cnt++;
-
- if (!ohci->sleeping)
- writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
- break;
-
- case PIPE_CONTROL:
- info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
- td_fill (ohci, info, kseg_to_phys(setup), 8, dev, cnt++, urb);
- if (data_len > 0) {
- info = usb_pipeout (pipe)?
- TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
- /* NOTE: mishandles transfers >8K, some >4K */
- td_fill (ohci, info, data, data_len, dev, cnt++, urb);
- }
- info = usb_pipeout (pipe)?
- TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
- td_fill (ohci, info, data, 0, dev, cnt++, urb);
- if (!ohci->sleeping)
- writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
- break;
- }
- if (urb->length != cnt)
- dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
-}
-
-/*-------------------------------------------------------------------------*
- * Done List handling functions
- *-------------------------------------------------------------------------*/
-
-
-/* calculate the transfer length and update the urb */
-
-static void dl_transfer_length(td_t * td)
-{
- __u32 tdINFO, tdBE, tdCBP;
- urb_priv_t *lurb_priv = &urb_priv;
-
- tdINFO = m32_swap (td->hwINFO);
- tdBE = m32_swap (td->hwBE);
- tdCBP = m32_swap (td->hwCBP);
-
-
- if (!(usb_pipecontrol(lurb_priv->pipe) &&
- ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
- if (tdBE != 0) {
- if (td->hwCBP == 0)
- lurb_priv->actual_length += tdBE - td->data + 1;
- else
- lurb_priv->actual_length += tdCBP - td->data;
- }
- }
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* replies to the request have to be on a FIFO basis so
- * we reverse the reversed done-list */
-
-static td_t * dl_reverse_done_list (ohci_t *ohci)
-{
- __u32 td_list_hc;
- td_t *td_rev = NULL;
- td_t *td_list = NULL;
- urb_priv_t *lurb_priv = NULL;
-
- td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
- ohci->hcca->done_head = 0;
-
- while (td_list_hc) {
- td_list = (td_t *)td_list_hc;
-
- if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
- lurb_priv = &urb_priv;
- dbg(" USB-error/status: %x : %p",
- TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
- if (td_list->ed->hwHeadP & m32_swap (0x1)) {
- if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
- td_list->ed->hwHeadP =
- (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
- (td_list->ed->hwHeadP & m32_swap (0x2));
- lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
- } else
- td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
- }
- }
-
- td_list->next_dl_td = td_rev;
- td_rev = td_list;
- td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
- }
- return td_list;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* td done list */
-static int dl_done_list (ohci_t *ohci, td_t *td_list)
-{
- td_t *td_list_next = NULL;
- ed_t *ed;
- int cc = 0;
- int stat = 0;
- /* urb_t *urb; */
- urb_priv_t *lurb_priv;
- __u32 tdINFO, edHeadP, edTailP;
-
- while (td_list) {
- td_list_next = td_list->next_dl_td;
-
- lurb_priv = &urb_priv;
- tdINFO = m32_swap (td_list->hwINFO);
-
- ed = td_list->ed;
-
- dl_transfer_length(td_list);
-
- /* error code of transfer */
- cc = TD_CC_GET (tdINFO);
- if (cc != 0) {
- dbg("ConditionCode %#x", cc);
- stat = cc_to_error[cc];
- }
-
- if (ed->state != ED_NEW) {
- edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
- edTailP = m32_swap (ed->hwTailP);
-
- /* unlink eds if they are not busy */
- if ((edHeadP == edTailP) && (ed->state == ED_OPER))
- ep_unlink (ohci, ed);
- }
-
- td_list = td_list_next;
- }
- return stat;
-}
-
-/*-------------------------------------------------------------------------*
- * Virtual Root Hub
- *-------------------------------------------------------------------------*/
-
-#include <usbroothubdes.h>
-
-/* Hub class-specific descriptor is constructed dynamically */
-
-
-/*-------------------------------------------------------------------------*/
-
-#define OK(x) len = (x); break
-#ifdef DEBUG
-#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
-#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
-#else
-#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
-#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
-#endif
-#define RD_RH_STAT roothub_status(&gohci)
-#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
-
-/* request to virtual root hub */
-
-int rh_check_port_status(ohci_t *controller)
-{
- __u32 temp, ndp, i;
- int res;
-
- res = -1;
- temp = roothub_a (controller);
- ndp = (temp & RH_A_NDP);
- for (i = 0; i < ndp; i++) {
- temp = roothub_portstatus (controller, i);
- /* check for a device disconnect */
- if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
- (RH_PS_PESC | RH_PS_CSC)) &&
- ((temp & RH_PS_CCS) == 0)) {
- res = i;
- break;
- }
- }
- return res;
-}
-
-static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
- void *buffer, int transfer_len, struct devrequest *cmd)
-{
- void * data = buffer;
- int leni = transfer_len;
- int len = 0;
- int stat = 0;
- __u32 datab[4];
- __u8 *data_buf = (__u8 *)datab;
- __u16 bmRType_bReq;
- __u16 wValue;
- __u16 wIndex;
- __u16 wLength;
-
-#ifdef DEBUG
-urb_priv.actual_length = 0;
-pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
-#else
- mdelay(1);
-#endif
- if (usb_pipeint(pipe)) {
- info("Root-Hub submit IRQ: NOT implemented");
- return 0;
- }
-
- bmRType_bReq = cmd->requesttype | (cmd->request << 8);
- wValue = m16_swap (cmd->value);
- wIndex = m16_swap (cmd->index);
- wLength = m16_swap (cmd->length);
-
- info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
- dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
-
- switch (bmRType_bReq) {
- /* Request Destination:
- without flags: Device,
- RH_INTERFACE: interface,
- RH_ENDPOINT: endpoint,
- RH_CLASS means HUB here,
- RH_OTHER | RH_CLASS almost ever means HUB_PORT here
- */
-
- case RH_GET_STATUS:
- *(__u16 *) data_buf = m16_swap (1); OK (2);
- case RH_GET_STATUS | RH_INTERFACE:
- *(__u16 *) data_buf = m16_swap (0); OK (2);
- case RH_GET_STATUS | RH_ENDPOINT:
- *(__u16 *) data_buf = m16_swap (0); OK (2);
- case RH_GET_STATUS | RH_CLASS:
- *(__u32 *) data_buf = m32_swap (
- RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
- OK (4);
- case RH_GET_STATUS | RH_OTHER | RH_CLASS:
- *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
-
- case RH_CLEAR_FEATURE | RH_ENDPOINT:
- switch (wValue) {
- case (RH_ENDPOINT_STALL): OK (0);
- }
- break;
-
- case RH_CLEAR_FEATURE | RH_CLASS:
- switch (wValue) {
- case RH_C_HUB_LOCAL_POWER:
- OK(0);
- case (RH_C_HUB_OVER_CURRENT):
- WR_RH_STAT(RH_HS_OCIC); OK (0);
- }
- break;
-
- case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
- switch (wValue) {
- case (RH_PORT_ENABLE):
- WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
- case (RH_PORT_SUSPEND):
- WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
- case (RH_PORT_POWER):
- WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
- case (RH_C_PORT_CONNECTION):
- WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
- case (RH_C_PORT_ENABLE):
- WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
- case (RH_C_PORT_SUSPEND):
- WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
- case (RH_C_PORT_OVER_CURRENT):
- WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
- case (RH_C_PORT_RESET):
- WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
- }
- break;
-
- case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
- switch (wValue) {
- case (RH_PORT_SUSPEND):
- WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
- case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
- if (RD_RH_PORTSTAT & RH_PS_CCS)
- WR_RH_PORTSTAT (RH_PS_PRS);
- OK (0);
- case (RH_PORT_POWER):
- WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
- case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
- if (RD_RH_PORTSTAT & RH_PS_CCS)
- WR_RH_PORTSTAT (RH_PS_PES );
- OK (0);
- }
- break;
-
- case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
-
- case RH_GET_DESCRIPTOR:
- switch ((wValue & 0xff00) >> 8) {
- case (0x01): /* device descriptor */
- len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_dev_des),
- wLength));
- data_buf = root_hub_dev_des; OK(len);
- case (0x02): /* configuration descriptor */
- len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_config_des),
- wLength));
- data_buf = root_hub_config_des; OK(len);
- case (0x03): /* string descriptors */
- if(wValue==0x0300) {
- len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_str_index0),
- wLength));
- data_buf = root_hub_str_index0;
- OK(len);
- }
- if(wValue==0x0301) {
- len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_str_index1),
- wLength));
- data_buf = root_hub_str_index1;
- OK(len);
- }
- default:
- stat = USB_ST_STALLED;
- }
- break;
-
- case RH_GET_DESCRIPTOR | RH_CLASS:
- {
- __u32 temp = roothub_a (&gohci);
-
- data_buf [0] = 9; /* min length; */
- data_buf [1] = 0x29;
- data_buf [2] = temp & RH_A_NDP;
- data_buf [3] = 0;
- if (temp & RH_A_PSM) /* per-port power switching? */
- data_buf [3] |= 0x1;
- if (temp & RH_A_NOCP) /* no overcurrent reporting? */
- data_buf [3] |= 0x10;
- else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
- data_buf [3] |= 0x8;
-
- /* corresponds to data_buf[4-7] */
- datab [1] = 0;
- data_buf [5] = (temp & RH_A_POTPGT) >> 24;
- temp = roothub_b (&gohci);
- data_buf [7] = temp & RH_B_DR;
- if (data_buf [2] < 7) {
- data_buf [8] = 0xff;
- } else {
- data_buf [0] += 2;
- data_buf [8] = (temp & RH_B_DR) >> 8;
- data_buf [10] = data_buf [9] = 0xff;
- }
-
- len = min_t(unsigned int, leni,
- min_t(unsigned int, data_buf [0], wLength));
- OK (len);
- }
-
- case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
-
- case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
-
- default:
- dbg ("unsupported root hub command");
- stat = USB_ST_STALLED;
- }
-
-#ifdef DEBUG
- ohci_dump_roothub (&gohci, 1);
-#else
- mdelay(1);
-#endif
-
- len = min_t(int, len, leni);
- if (data != data_buf)
- memcpy (data, data_buf, len);
- dev->act_len = len;
- dev->status = stat;
-
-#ifdef DEBUG
- if (transfer_len)
- urb_priv.actual_length = transfer_len;
- pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
-#else
- mdelay(1);
-#endif
-
- return stat;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* common code for handling submit messages - used for all but root hub */
-/* accesses. */
-int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup, int interval)
-{
- int stat = 0;
- int maxsize = usb_maxpacket(dev, pipe);
- int timeout;
-
- /* device pulled? Shortcut the action. */
- if (devgone == dev) {
- dev->status = USB_ST_CRC_ERR;
- return 0;
- }
-
-#ifdef DEBUG
- urb_priv.actual_length = 0;
- pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
-#else
- mdelay(1);
-#endif
- if (!maxsize) {
- err("submit_common_message: pipesize for pipe %lx is zero",
- pipe);
- return -1;
- }
-
- if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
- err("sohci_submit_job failed");
- return -1;
- }
-
- mdelay(10);
- /* ohci_dump_status(&gohci); */
-
- /* allow more time for a BULK device to react - some are slow */
-#define BULK_TO 5000 /* timeout in milliseconds */
- if (usb_pipebulk(pipe))
- timeout = BULK_TO;
- else
- timeout = 100;
-
- timeout *= 4;
- /* wait for it to complete */
- for (;;) {
- /* check whether the controller is done */
- stat = hc_interrupt();
- if (stat < 0) {
- stat = USB_ST_CRC_ERR;
- break;
- }
- if (stat >= 0 && stat != 0xff) {
- /* 0xff is returned for an SF-interrupt */
- break;
- }
- if (--timeout) {
- udelay(250); /* mdelay(1); */
- } else {
- err("CTL:TIMEOUT ");
- stat = USB_ST_CRC_ERR;
- break;
- }
- }
- /* we got an Root Hub Status Change interrupt */
- if (got_rhsc) {
-#ifdef DEBUG
- ohci_dump_roothub (&gohci, 1);
-#endif
- got_rhsc = 0;
- /* abuse timeout */
- timeout = rh_check_port_status(&gohci);
- if (timeout >= 0) {
-#if 0 /* this does nothing useful, but leave it here in case that changes */
- /* the called routine adds 1 to the passed value */
- usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
-#endif
- /*
- * XXX
- * This is potentially dangerous because it assumes
- * that only one device is ever plugged in!
- */
- devgone = dev;
- }
- }
-
- dev->status = stat;
- dev->act_len = transfer_len;
-
-#ifdef DEBUG
- pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
-#else
- mdelay(1);
-#endif
-
- /* free TDs in urb_priv */
- urb_free_priv (&urb_priv);
- return 0;
-}
-
-/* submit routines called from usb.c */
-int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len)
-{
- info("submit_bulk_msg");
- return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
-}
-
-int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup)
-{
- int maxsize = usb_maxpacket(dev, pipe);
-
- info("submit_control_msg");
-#ifdef DEBUG
- urb_priv.actual_length = 0;
- pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
-#else
- mdelay(1);
-#endif
- if (!maxsize) {
- err("submit_control_message: pipesize for pipe %lx is zero",
- pipe);
- return -1;
- }
- if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
- gohci.rh.dev = dev;
- /* root hub - redirect */
- return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
- setup);
- }
-
- return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
-}
-
-int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, int interval)
-{
- info("submit_int_msg");
- return -1;
-}
-
-/*-------------------------------------------------------------------------*
- * HC functions
- *-------------------------------------------------------------------------*/
-
-/* reset the HC and BUS */
-
-static int hc_reset (ohci_t *ohci)
-{
- int timeout = 30;
- int smm_timeout = 50; /* 0,5 sec */
-
- if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
- writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
- info("USB HC TakeOver from SMM");
- while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
- mdelay (10);
- if (--smm_timeout == 0) {
- err("USB HC TakeOver failed!");
- return -1;
- }
- }
- }
-
- /* Disable HC interrupts */
- writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
-
- dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
- ohci->slot_name,
- readl (&ohci->regs->control));
-
- /* Reset USB (needed by some controllers) */
- writel (0, &ohci->regs->control);
-
- /* HC Reset requires max 10 us delay */
- writel (OHCI_HCR, &ohci->regs->cmdstatus);
- while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
- if (--timeout == 0) {
- err("USB HC reset timed out!");
- return -1;
- }
- udelay (1);
- }
- return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* Start an OHCI controller, set the BUS operational
- * enable interrupts
- * connect the virtual root hub */
-
-static int hc_start (ohci_t * ohci)
-{
- __u32 mask;
- unsigned int fminterval;
-
- ohci->disabled = 1;
-
- /* Tell the controller where the control and bulk lists are
- * The lists are empty now. */
-
- writel (0, &ohci->regs->ed_controlhead);
- writel (0, &ohci->regs->ed_bulkhead);
-
- writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
-
- fminterval = 0x2edf;
- writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
- fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
- writel (fminterval, &ohci->regs->fminterval);
- writel (0x628, &ohci->regs->lsthresh);
-
- /* start controller operations */
- ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
- ohci->disabled = 0;
- writel (ohci->hc_control, &ohci->regs->control);
-
- /* disable all interrupts */
- mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
- OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
- OHCI_INTR_OC | OHCI_INTR_MIE);
- writel (mask, &ohci->regs->intrdisable);
- /* clear all interrupts */
- mask &= ~OHCI_INTR_MIE;
- writel (mask, &ohci->regs->intrstatus);
- /* Choose the interrupts we care about now - but w/o MIE */
- mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
- writel (mask, &ohci->regs->intrenable);
-
-#ifdef OHCI_USE_NPS
- /* required for AMD-756 and some Mac platforms */
- writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
- &ohci->regs->roothub.a);
- writel (RH_HS_LPSC, &ohci->regs->roothub.status);
-#endif /* OHCI_USE_NPS */
-
- /* POTPGT delay is bits 24-31, in 2 ms units. */
- mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
-
- /* connect the virtual root hub */
- ohci->rh.devnum = 0;
-
- return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* an interrupt happens */
-
-static int
-hc_interrupt (void)
-{
- ohci_t *ohci = &gohci;
- struct ohci_regs *regs = ohci->regs;
- int ints;
- int stat = -1;
-
- if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
- ints = OHCI_INTR_WDH;
- } else {
- ints = readl (®s->intrstatus);
- }
-
- /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
-
- if (ints & OHCI_INTR_RHSC) {
- got_rhsc = 1;
- }
-
- if (ints & OHCI_INTR_UE) {
- ohci->disabled++;
- err ("OHCI Unrecoverable Error, controller usb-%s disabled",
- ohci->slot_name);
- /* e.g. due to PCI Master/Target Abort */
-
-#ifdef DEBUG
- ohci_dump (ohci, 1);
-#else
- mdelay(1);
-#endif
- /* FIXME: be optimistic, hope that bug won't repeat often. */
- /* Make some non-interrupt context restart the controller. */
- /* Count and limit the retries though; either hardware or */
- /* software errors can go forever... */
- hc_reset (ohci);
- return -1;
- }
-
- if (ints & OHCI_INTR_WDH) {
- mdelay(1);
- writel (OHCI_INTR_WDH, ®s->intrdisable);
- stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
- writel (OHCI_INTR_WDH, ®s->intrenable);
- }
-
- if (ints & OHCI_INTR_SO) {
- dbg("USB Schedule overrun\n");
- writel (OHCI_INTR_SO, ®s->intrenable);
- stat = -1;
- }
-
- /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
- if (ints & OHCI_INTR_SF) {
- unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
- mdelay(1);
- writel (OHCI_INTR_SF, ®s->intrdisable);
- if (ohci->ed_rm_list[frame] != NULL)
- writel (OHCI_INTR_SF, ®s->intrenable);
- stat = 0xff;
- }
-
- writel (ints, ®s->intrstatus);
- return stat;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/*-------------------------------------------------------------------------*/
-
-/* De-allocate all resources.. */
-
-static void hc_release_ohci (ohci_t *ohci)
-{
- dbg ("USB HC release ohci usb-%s", ohci->slot_name);
-
- if (!ohci->disabled)
- hc_reset (ohci);
-}
-
-/*-------------------------------------------------------------------------*/
-
-#define __read_32bit_c0_register(source, sel) \
-({ int __res; \
- if (sel == 0) \
- __asm__ __volatile__( \
- "mfc0\t%0, " #source "\n\t" \
- : "=r" (__res)); \
- else \
- __asm__ __volatile__( \
- ".set\tmips32\n\t" \
- "mfc0\t%0, " #source ", " #sel "\n\t" \
- ".set\tmips0\n\t" \
- : "=r" (__res)); \
- __res; \
-})
-
-#define read_c0_prid() __read_32bit_c0_register($15, 0)
-
-/*
- * low level initalisation routine, called from usb.c
- */
-static char ohci_inited = 0;
-
-int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
-{
- u32 pin_func;
- u32 sys_freqctrl, sys_clksrc;
- u32 prid = read_c0_prid();
-
- dbg("in usb_lowlevel_init\n");
-
- /* zero and disable FREQ2 */
- sys_freqctrl = au_readl(SYS_FREQCTRL0);
- sys_freqctrl &= ~0xFFF00000;
- au_writel(sys_freqctrl, SYS_FREQCTRL0);
-
- /* zero and disable USBH/USBD clocks */
- sys_clksrc = au_readl(SYS_CLKSRC);
- sys_clksrc &= ~0x00007FE0;
- au_writel(sys_clksrc, SYS_CLKSRC);
-
- sys_freqctrl = au_readl(SYS_FREQCTRL0);
- sys_freqctrl &= ~0xFFF00000;
-
- sys_clksrc = au_readl(SYS_CLKSRC);
- sys_clksrc &= ~0x00007FE0;
-
- switch (prid & 0x000000FF) {
- case 0x00: /* DA */
- case 0x01: /* HA */
- case 0x02: /* HB */
- /* CPU core freq to 48MHz to slow it way down... */
- au_writel(4, SYS_CPUPLL);
-
- /*
- * Setup 48MHz FREQ2 from CPUPLL for USB Host
- */
- /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
- sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
- au_writel(sys_freqctrl, SYS_FREQCTRL0);
-
- /* CPU core freq to 384MHz */
- au_writel(0x20, SYS_CPUPLL);
-
- printf("Au1000: 48MHz OHCI workaround enabled\n");
- break;
-
- default: /* HC and newer */
- /* FREQ2 = aux/2 = 48 MHz */
- sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
- au_writel(sys_freqctrl, SYS_FREQCTRL0);
- break;
- }
-
- /*
- * Route 48MHz FREQ2 into USB Host and/or Device
- */
- sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
- au_writel(sys_clksrc, SYS_CLKSRC);
-
- /* configure pins GPIO[14:9] as GPIO */
- pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
-
- au_writel(pin_func, SYS_PINFUNC);
- au_writel(0x2800, SYS_TRIOUTCLR);
- au_writel(0x0030, SYS_OUTPUTCLR);
-
- dbg("OHCI board setup complete\n");
-
- /* enable host controller */
- au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG);
- udelay(1000);
- au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG);
- udelay(1000);
-
- /* wait for reset complete (read register twice; see au1500 errata) */
- while (au_readl(USB_HOST_CONFIG),
- !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD))
- udelay(1000);
-
- dbg("OHCI clock running\n");
-
- memset (&gohci, 0, sizeof (ohci_t));
- memset (&urb_priv, 0, sizeof (urb_priv_t));
-
- /* align the storage */
- if ((__u32)&ghcca[0] & 0xff) {
- err("HCCA not aligned!!");
- return -1;
- }
- phcca = &ghcca[0];
- info("aligned ghcca %p", phcca);
- memset(&ohci_dev, 0, sizeof(struct ohci_device));
- if ((__u32)&ohci_dev.ed[0] & 0x7) {
- err("EDs not aligned!!");
- return -1;
- }
- memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
- if ((__u32)gtd & 0x7) {
- err("TDs not aligned!!");
- return -1;
- }
- ptd = gtd;
- gohci.hcca = phcca;
- memset (phcca, 0, sizeof (struct ohci_hcca));
-
- gohci.disabled = 1;
- gohci.sleeping = 0;
- gohci.irq = -1;
- gohci.regs = (struct ohci_regs *)(USB_OHCI_BASE | 0xA0000000);
-
- gohci.flags = 0;
- gohci.slot_name = "au1x00";
-
- dbg("OHCI revision: 0x%08x\n"
- " RH: a: 0x%08x b: 0x%08x\n",
- readl(&gohci.regs->revision),
- readl(&gohci.regs->roothub.a), readl(&gohci.regs->roothub.b));
-
- if (hc_reset (&gohci) < 0)
- goto errout;
-
- /* FIXME this is a second HC reset; why?? */
- writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
- mdelay (10);
-
- if (hc_start (&gohci) < 0)
- goto errout;
-
-#ifdef DEBUG
- ohci_dump (&gohci, 1);
-#else
- mdelay(1);
-#endif
- ohci_inited = 1;
- return 0;
-
- errout:
- err("OHCI initialization error\n");
- hc_release_ohci (&gohci);
- /* Initialization failed */
- au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
- return -1;
-}
-
-int usb_lowlevel_stop(int index)
-{
- /* this gets called really early - before the controller has */
- /* even been initialized! */
- if (!ohci_inited)
- return 0;
- /* TODO release any interrupts, etc. */
- /* call hc_release_ohci() here ? */
- hc_reset (&gohci);
- /* may not want to do this */
- /* Disable clock */
- au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
- return 0;
-}
-
-#endif /* CONFIG_USB_OHCI */
+++ /dev/null
-/*
- * URB OHCI HCD (Host Controller Driver) for USB.
- *
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
- *
- * usb-ohci.h
- */
-
-
-static int cc_to_error[16] = {
-
-/* mapping of the OHCI CC status to error codes */
- /* No Error */ 0,
- /* CRC Error */ USB_ST_CRC_ERR,
- /* Bit Stuff */ USB_ST_BIT_ERR,
- /* Data Togg */ USB_ST_CRC_ERR,
- /* Stall */ USB_ST_STALLED,
- /* DevNotResp */ -1,
- /* PIDCheck */ USB_ST_BIT_ERR,
- /* UnExpPID */ USB_ST_BIT_ERR,
- /* DataOver */ USB_ST_BUF_ERR,
- /* DataUnder */ USB_ST_BUF_ERR,
- /* reservd */ -1,
- /* reservd */ -1,
- /* BufferOver */ USB_ST_BUF_ERR,
- /* BuffUnder */ USB_ST_BUF_ERR,
- /* Not Access */ -1,
- /* Not Access */ -1
-};
-
-/* ED States */
-
-#define ED_NEW 0x00
-#define ED_UNLINK 0x01
-#define ED_OPER 0x02
-#define ED_DEL 0x04
-#define ED_URB_DEL 0x08
-
-/* usb_ohci_ed */
-struct ed {
- __u32 hwINFO;
- __u32 hwTailP;
- __u32 hwHeadP;
- __u32 hwNextED;
-
- struct ed *ed_prev;
- __u8 int_period;
- __u8 int_branch;
- __u8 int_load;
- __u8 int_interval;
- __u8 state;
- __u8 type;
- __u16 last_iso;
- struct ed *ed_rm_list;
-
- struct usb_device *usb_dev;
- __u32 unused[3];
-} __attribute__((aligned(16)));
-typedef struct ed ed_t;
-
-
-/* TD info field */
-#define TD_CC 0xf0000000
-#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
-#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
-#define TD_EC 0x0C000000
-#define TD_T 0x03000000
-#define TD_T_DATA0 0x02000000
-#define TD_T_DATA1 0x03000000
-#define TD_T_TOGGLE 0x00000000
-#define TD_R 0x00040000
-#define TD_DI 0x00E00000
-#define TD_DI_SET(X) (((X) & 0x07)<< 21)
-#define TD_DP 0x00180000
-#define TD_DP_SETUP 0x00000000
-#define TD_DP_IN 0x00100000
-#define TD_DP_OUT 0x00080000
-
-#define TD_ISO 0x00010000
-#define TD_DEL 0x00020000
-
-/* CC Codes */
-#define TD_CC_NOERROR 0x00
-#define TD_CC_CRC 0x01
-#define TD_CC_BITSTUFFING 0x02
-#define TD_CC_DATATOGGLEM 0x03
-#define TD_CC_STALL 0x04
-#define TD_DEVNOTRESP 0x05
-#define TD_PIDCHECKFAIL 0x06
-#define TD_UNEXPECTEDPID 0x07
-#define TD_DATAOVERRUN 0x08
-#define TD_DATAUNDERRUN 0x09
-#define TD_BUFFEROVERRUN 0x0C
-#define TD_BUFFERUNDERRUN 0x0D
-#define TD_NOTACCESSED 0x0F
-
-
-#define MAXPSW 1
-
-struct td {
- __u32 hwINFO;
- __u32 hwCBP; /* Current Buffer Pointer */
- __u32 hwNextTD; /* Next TD Pointer */
- __u32 hwBE; /* Memory Buffer End Pointer */
-
- __u16 hwPSW[MAXPSW];
- __u8 unused;
- __u8 index;
- struct ed *ed;
- struct td *next_dl_td;
- struct usb_device *usb_dev;
- int transfer_len;
- __u32 data;
-
- __u32 unused2[2];
-} __attribute__((aligned(32)));
-typedef struct td td_t;
-
-#define OHCI_ED_SKIP (1 << 14)
-
-/*
- * The HCCA (Host Controller Communications Area) is a 256 byte
- * structure defined in the OHCI spec. that the host controller is
- * told the base address of. It must be 256-byte aligned.
- */
-
-#define NUM_INTS 32 /* part of the OHCI standard */
-struct ohci_hcca {
- __u32 int_table[NUM_INTS]; /* Interrupt ED table */
- __u16 frame_no; /* current frame number */
- __u16 pad1; /* set to 0 on each frame_no change */
- __u32 done_head; /* info returned for an interrupt */
- u8 reserved_for_hc[116];
-} __attribute__((aligned(256)));
-
-
-/*
- * Maximum number of root hub ports.
- */
-#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */
-
-/*
- * This is the structure of the OHCI controller's memory mapped I/O
- * region. This is Memory Mapped I/O. You must use the readl() and
- * writel() macros defined in asm/io.h to access these!!
- */
-struct ohci_regs {
- /* control and status registers */
- __u32 revision;
- __u32 control;
- __u32 cmdstatus;
- __u32 intrstatus;
- __u32 intrenable;
- __u32 intrdisable;
- /* memory pointers */
- __u32 hcca;
- __u32 ed_periodcurrent;
- __u32 ed_controlhead;
- __u32 ed_controlcurrent;
- __u32 ed_bulkhead;
- __u32 ed_bulkcurrent;
- __u32 donehead;
- /* frame counters */
- __u32 fminterval;
- __u32 fmremaining;
- __u32 fmnumber;
- __u32 periodicstart;
- __u32 lsthresh;
- /* Root hub ports */
- struct ohci_roothub_regs {
- __u32 a;
- __u32 b;
- __u32 status;
- __u32 portstatus[MAX_ROOT_PORTS];
- } roothub;
-} __attribute__((aligned(32)));
-
-
-/* OHCI CONTROL AND STATUS REGISTER MASKS */
-
-/*
- * HcControl (control) register masks
- */
-#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
-#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
-#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
-#define OHCI_CTRL_CLE (1 << 4) /* control list enable */
-#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
-#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
-#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
-#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
-#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
-
-/* pre-shifted values for HCFS */
-# define OHCI_USB_RESET (0 << 6)
-# define OHCI_USB_RESUME (1 << 6)
-# define OHCI_USB_OPER (2 << 6)
-# define OHCI_USB_SUSPEND (3 << 6)
-
-/*
- * HcCommandStatus (cmdstatus) register masks
- */
-#define OHCI_HCR (1 << 0) /* host controller reset */
-#define OHCI_CLF (1 << 1) /* control list filled */
-#define OHCI_BLF (1 << 2) /* bulk list filled */
-#define OHCI_OCR (1 << 3) /* ownership change request */
-#define OHCI_SOC (3 << 16) /* scheduling overrun count */
-
-/*
- * masks used with interrupt registers:
- * HcInterruptStatus (intrstatus)
- * HcInterruptEnable (intrenable)
- * HcInterruptDisable (intrdisable)
- */
-#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
-#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
-#define OHCI_INTR_SF (1 << 2) /* start frame */
-#define OHCI_INTR_RD (1 << 3) /* resume detect */
-#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
-#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
-#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
-#define OHCI_INTR_OC (1 << 30) /* ownership change */
-#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
-
-
-/* Virtual Root HUB */
-struct virt_root_hub {
- int devnum; /* Address of Root Hub endpoint */
- void *dev; /* was urb */
- void *int_addr;
- int send;
- int interval;
-};
-
-/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
-
-/* destination of request */
-#define RH_INTERFACE 0x01
-#define RH_ENDPOINT 0x02
-#define RH_OTHER 0x03
-
-#define RH_CLASS 0x20
-#define RH_VENDOR 0x40
-
-/* Requests: bRequest << 8 | bmRequestType */
-#define RH_GET_STATUS 0x0080
-#define RH_CLEAR_FEATURE 0x0100
-#define RH_SET_FEATURE 0x0300
-#define RH_SET_ADDRESS 0x0500
-#define RH_GET_DESCRIPTOR 0x0680
-#define RH_SET_DESCRIPTOR 0x0700
-#define RH_GET_CONFIGURATION 0x0880
-#define RH_SET_CONFIGURATION 0x0900
-#define RH_GET_STATE 0x0280
-#define RH_GET_INTERFACE 0x0A80
-#define RH_SET_INTERFACE 0x0B00
-#define RH_SYNC_FRAME 0x0C80
-/* Our Vendor Specific Request */
-#define RH_SET_EP 0x2000
-
-
-/* Hub port features */
-#define RH_PORT_CONNECTION 0x00
-#define RH_PORT_ENABLE 0x01
-#define RH_PORT_SUSPEND 0x02
-#define RH_PORT_OVER_CURRENT 0x03
-#define RH_PORT_RESET 0x04
-#define RH_PORT_POWER 0x08
-#define RH_PORT_LOW_SPEED 0x09
-
-#define RH_C_PORT_CONNECTION 0x10
-#define RH_C_PORT_ENABLE 0x11
-#define RH_C_PORT_SUSPEND 0x12
-#define RH_C_PORT_OVER_CURRENT 0x13
-#define RH_C_PORT_RESET 0x14
-
-/* Hub features */
-#define RH_C_HUB_LOCAL_POWER 0x00
-#define RH_C_HUB_OVER_CURRENT 0x01
-
-#define RH_DEVICE_REMOTE_WAKEUP 0x00
-#define RH_ENDPOINT_STALL 0x01
-
-#define RH_ACK 0x01
-#define RH_REQ_ERR -1
-#define RH_NACK 0x00
-
-
-/* OHCI ROOT HUB REGISTER MASKS */
-
-/* roothub.portstatus [i] bits */
-#define RH_PS_CCS 0x00000001 /* current connect status */
-#define RH_PS_PES 0x00000002 /* port enable status*/
-#define RH_PS_PSS 0x00000004 /* port suspend status */
-#define RH_PS_POCI 0x00000008 /* port over current indicator */
-#define RH_PS_PRS 0x00000010 /* port reset status */
-#define RH_PS_PPS 0x00000100 /* port power status */
-#define RH_PS_LSDA 0x00000200 /* low speed device attached */
-#define RH_PS_CSC 0x00010000 /* connect status change */
-#define RH_PS_PESC 0x00020000 /* port enable status change */
-#define RH_PS_PSSC 0x00040000 /* port suspend status change */
-#define RH_PS_OCIC 0x00080000 /* over current indicator change */
-#define RH_PS_PRSC 0x00100000 /* port reset status change */
-
-/* roothub.status bits */
-#define RH_HS_LPS 0x00000001 /* local power status */
-#define RH_HS_OCI 0x00000002 /* over current indicator */
-#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
-#define RH_HS_LPSC 0x00010000 /* local power status change */
-#define RH_HS_OCIC 0x00020000 /* over current indicator change */
-#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
-
-/* roothub.b masks */
-#define RH_B_DR 0x0000ffff /* device removable flags */
-#define RH_B_PPCM 0xffff0000 /* port power control mask */
-
-/* roothub.a masks */
-#define RH_A_NDP (0xff << 0) /* number of downstream ports */
-#define RH_A_PSM (1 << 8) /* power switching mode */
-#define RH_A_NPS (1 << 9) /* no power switching */
-#define RH_A_DT (1 << 10) /* device type (mbz) */
-#define RH_A_OCPM (1 << 11) /* over current protection mode */
-#define RH_A_NOCP (1 << 12) /* no over current protection */
-#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
-
-/* urb */
-#define N_URB_TD 48
-typedef struct
-{
- ed_t *ed;
- __u16 length; /* number of tds associated with this request */
- __u16 td_cnt; /* number of tds already serviced */
- int state;
- unsigned long pipe;
- int actual_length;
- td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
-} urb_priv_t;
-#define URB_DEL 1
-
-/*
- * This is the full ohci controller description
- *
- * Note how the "proper" USB information is just
- * a subset of what the full implementation needs. (Linus)
- */
-
-
-typedef struct ohci {
- struct ohci_hcca *hcca; /* hcca */
- /*dma_addr_t hcca_dma;*/
-
- int irq;
- int disabled; /* e.g. got a UE, we're hung */
- int sleeping;
- unsigned long flags; /* for HC bugs */
-
- struct ohci_regs *regs; /* OHCI controller's memory */
-
- ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
- ed_t *ed_bulktail; /* last endpoint of bulk list */
- ed_t *ed_controltail; /* last endpoint of control list */
- int intrstatus;
- __u32 hc_control; /* copy of the hc control reg */
- struct usb_device *dev[32];
- struct virt_root_hub rh;
-
- const char *slot_name;
-} ohci_t;
-
-#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
-
-struct ohci_device {
- ed_t ed[NUM_EDS];
- int ed_cnt;
-};
-
-/* hcd */
-/* endpoint */
-static int ep_link(ohci_t * ohci, ed_t * ed);
-static int ep_unlink(ohci_t * ohci, ed_t * ed);
-static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
-
-/*-------------------------------------------------------------------------*/
-
-/* we need more TDs than EDs */
-#define NUM_TD 64
-
-/* +1 so we can align the storage */
-td_t gtd[NUM_TD+1];
-/* pointers to aligned storage */
-td_t *ptd;
-
-/* TDs ... */
-static inline struct td *
-td_alloc (struct usb_device *usb_dev)
-{
- int i;
- struct td *td;
-
- td = NULL;
- for (i = 0; i < NUM_TD; i++) {
- if (ptd[i].usb_dev == NULL) {
- td = &ptd[i];
- td->usb_dev = usb_dev;
- break;
- }
- }
- return td;
-}
-
-static inline void
-ed_free (struct ed *ed)
-{
- ed->usb_dev = NULL;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *
- * BRIEF MODULE DESCRIPTION
- * Include file for Alchemy Semiconductor's Au1k CPU.
- *
- * Copyright 2000,2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * ppopov@mvista.com or source@mvista.com
- */
-
- /*
- * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
- */
-
-#ifndef _AU1X00_H_
-#define _AU1X00_H_
-
-#ifndef __ASSEMBLY__
-/* cpu pipeline flush */
-void static inline au_sync(void)
-{
- __asm__ volatile ("sync");
-}
-
-void static inline au_sync_udelay(int us)
-{
- __asm__ volatile ("sync");
- udelay(us);
-}
-
-void static inline au_writeb(u8 val, int reg)
-{
- *(volatile u8 *)(reg) = val;
-}
-
-void static inline au_writew(u16 val, int reg)
-{
- *(volatile u16 *)(reg) = val;
-}
-
-void static inline au_writel(u32 val, int reg)
-{
- *(volatile u32 *)(reg) = val;
-}
-
-static inline u8 au_readb(unsigned long port)
-{
- return (*(volatile u8 *)port);
-}
-
-static inline u16 au_readw(unsigned long port)
-{
- return (*(volatile u16 *)port);
-}
-
-static inline u32 au_readl(unsigned long port)
-{
- return (*(volatile u32 *)port);
-}
-
-/* These next three functions should be a generic part of the MIPS
- * kernel (with the 'au_' removed from the name) and selected for
- * processors that support the instructions.
- * Taken from PPC tree. -- Dan
- */
-/* Return the bit position of the most significant 1 bit in a word */
-static __inline__ int __ilog2(unsigned int x)
-{
- int lz;
-
- asm volatile (
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips32\n\t"
- "clz\t%0,%1\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- : "=r" (lz)
- : "r" (x));
-
- return 31 - lz;
-}
-
-static __inline__ int au_ffz(unsigned int x)
-{
- if ((x = ~x) == 0)
- return 32;
- return __ilog2(x & -x);
-}
-
-/*
- * ffs: find first bit set. This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-static __inline__ int au_ffs(int x)
-{
- return __ilog2(x & -x) + 1;
-}
-
-#define gpio_set(Value) outl(Value, SYS_OUTPUTSET)
-#define gpio_clear(Value) outl(Value, SYS_OUTPUTCLR)
-#define gpio_read() inl(SYS_PINSTATERD)
-#define gpio_tristate(Value) outl(Value, SYS_TRIOUTCLR)
-
-#endif /* !ASSEMBLY */
-
-#ifdef CONFIG_PM
-/* no CP0 timer irq */
-#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
-#else
-#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
-#endif
-
-#define CP0_IWATCHLO $18,1
-#define CP0_DEBUG $23
-
-/* SDRAM Controller */
-#ifdef CONFIG_SOC_AU1550
-
-#define MEM_SDMODE0 0xB4000800
-#define MEM_SDMODE1 0xB4000808
-#define MEM_SDMODE2 0xB4000810
-
-#define MEM_SDADDR0 0xB4000820
-#define MEM_SDADDR1 0xB4000828
-#define MEM_SDADDR2 0xB4000830
-
-#define MEM_SDCONFIGA 0xB4000840
-#define MEM_SDCONFIGB 0xB4000848
-#define MEM_SDPRECMD 0xB40008c0
-#define MEM_SDAUTOREF 0xB40008c8
-
-#define MEM_SDWRMD0 0xB4000880
-#define MEM_SDWRMD1 0xB4000888
-#define MEM_SDWRMD2 0xB4000890
-
-#else /* CONFIG_SOC_AU1550 */
-
-#define MEM_SDMODE0 0xB4000000
-#define MEM_SDMODE1 0xB4000004
-#define MEM_SDMODE2 0xB4000008
-
-#define MEM_SDADDR0 0xB400000C
-#define MEM_SDADDR1 0xB4000010
-#define MEM_SDADDR2 0xB4000014
-
-#define MEM_SDREFCFG 0xB4000018
-#define MEM_SDPRECMD 0xB400001C
-#define MEM_SDAUTOREF 0xB4000020
-
-#define MEM_SDWRMD0 0xB4000024
-#define MEM_SDWRMD1 0xB4000028
-#define MEM_SDWRMD2 0xB400002C
-
-#endif /* CONFIG_SOC_AU1550 */
-
-#define MEM_SDSLEEP 0xB4000030
-#define MEM_SDSMCKE 0xB4000034
-
-/* Static Bus Controller */
-#define MEM_STCFG0 0xB4001000
-#define MEM_STTIME0 0xB4001004
-#define MEM_STADDR0 0xB4001008
-
-#define MEM_STCFG1 0xB4001010
-#define MEM_STTIME1 0xB4001014
-#define MEM_STADDR1 0xB4001018
-
-#define MEM_STCFG2 0xB4001020
-#define MEM_STTIME2 0xB4001024
-#define MEM_STADDR2 0xB4001028
-
-#define MEM_STCFG3 0xB4001030
-#define MEM_STTIME3 0xB4001034
-#define MEM_STADDR3 0xB4001038
-
-/* Interrupt Controller 0 */
-#define IC0_CFG0RD 0xB0400040
-#define IC0_CFG0SET 0xB0400040
-#define IC0_CFG0CLR 0xB0400044
-
-#define IC0_CFG1RD 0xB0400048
-#define IC0_CFG1SET 0xB0400048
-#define IC0_CFG1CLR 0xB040004C
-
-#define IC0_CFG2RD 0xB0400050
-#define IC0_CFG2SET 0xB0400050
-#define IC0_CFG2CLR 0xB0400054
-
-#define IC0_REQ0INT 0xB0400054
-#define IC0_SRCRD 0xB0400058
-#define IC0_SRCSET 0xB0400058
-#define IC0_SRCCLR 0xB040005C
-#define IC0_REQ1INT 0xB040005C
-
-#define IC0_ASSIGNRD 0xB0400060
-#define IC0_ASSIGNSET 0xB0400060
-#define IC0_ASSIGNCLR 0xB0400064
-
-#define IC0_WAKERD 0xB0400068
-#define IC0_WAKESET 0xB0400068
-#define IC0_WAKECLR 0xB040006C
-
-#define IC0_MASKRD 0xB0400070
-#define IC0_MASKSET 0xB0400070
-#define IC0_MASKCLR 0xB0400074
-
-#define IC0_RISINGRD 0xB0400078
-#define IC0_RISINGCLR 0xB0400078
-#define IC0_FALLINGRD 0xB040007C
-#define IC0_FALLINGCLR 0xB040007C
-
-#define IC0_TESTBIT 0xB0400080
-
-/* Interrupt Controller 1 */
-#define IC1_CFG0RD 0xB1800040
-#define IC1_CFG0SET 0xB1800040
-#define IC1_CFG0CLR 0xB1800044
-
-#define IC1_CFG1RD 0xB1800048
-#define IC1_CFG1SET 0xB1800048
-#define IC1_CFG1CLR 0xB180004C
-
-#define IC1_CFG2RD 0xB1800050
-#define IC1_CFG2SET 0xB1800050
-#define IC1_CFG2CLR 0xB1800054
-
-#define IC1_REQ0INT 0xB1800054
-#define IC1_SRCRD 0xB1800058
-#define IC1_SRCSET 0xB1800058
-#define IC1_SRCCLR 0xB180005C
-#define IC1_REQ1INT 0xB180005C
-
-#define IC1_ASSIGNRD 0xB1800060
-#define IC1_ASSIGNSET 0xB1800060
-#define IC1_ASSIGNCLR 0xB1800064
-
-#define IC1_WAKERD 0xB1800068
-#define IC1_WAKESET 0xB1800068
-#define IC1_WAKECLR 0xB180006C
-
-#define IC1_MASKRD 0xB1800070
-#define IC1_MASKSET 0xB1800070
-#define IC1_MASKCLR 0xB1800074
-
-#define IC1_RISINGRD 0xB1800078
-#define IC1_RISINGCLR 0xB1800078
-#define IC1_FALLINGRD 0xB180007C
-#define IC1_FALLINGCLR 0xB180007C
-
-#define IC1_TESTBIT 0xB1800080
-
-/* Interrupt Configuration Modes */
-#define INTC_INT_DISABLED 0
-#define INTC_INT_RISE_EDGE 0x1
-#define INTC_INT_FALL_EDGE 0x2
-#define INTC_INT_RISE_AND_FALL_EDGE 0x3
-#define INTC_INT_HIGH_LEVEL 0x5
-#define INTC_INT_LOW_LEVEL 0x6
-#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
-
-/* Interrupt Numbers */
-#define AU1X00_UART0_INT 0
-#define AU1000_UART1_INT 1 /* au1000 */
-#define AU1000_UART2_INT 2 /* au1000 */
-
-#define AU1500_PCI_INTA 1 /* au1500 */
-#define AU1500_PCI_INTB 2 /* au1500 */
-
-#define AU1X00_UART3_INT 3
-
-#define AU1000_SSI0_INT 4 /* au1000 */
-#define AU1000_SSI1_INT 5 /* au1000 */
-
-#define AU1500_PCI_INTC 4 /* au1500 */
-#define AU1500_PCI_INTD 5 /* au1500 */
-
-#define AU1X00_DMA_INT_BASE 6
-#define AU1X00_TOY_INT 14
-#define AU1X00_TOY_MATCH0_INT 15
-#define AU1X00_TOY_MATCH1_INT 16
-#define AU1X00_TOY_MATCH2_INT 17
-#define AU1X00_RTC_INT 18
-#define AU1X00_RTC_MATCH0_INT 19
-#define AU1X00_RTC_MATCH1_INT 20
-#define AU1X00_RTC_MATCH2_INT 21
-#define AU1000_IRDA_TX_INT 22 /* au1000 */
-#define AU1000_IRDA_RX_INT 23 /* au1000 */
-#define AU1X00_USB_DEV_REQ_INT 24
-#define AU1X00_USB_DEV_SUS_INT 25
-#define AU1X00_USB_HOST_INT 26
-#define AU1X00_ACSYNC_INT 27
-#define AU1X00_MAC0_DMA_INT 28
-#define AU1X00_MAC1_DMA_INT 29
-#define AU1X00_ETH0_IRQ AU1X00_MAC0_DMA_INT
-#define AU1X00_ETH1_IRQ AU1X00_MAC1_DMA_INT
-#define AU1000_I2S_UO_INT 30 /* au1000 */
-#define AU1X00_AC97C_INT 31
-#define AU1X00_LAST_INTC0_INT AU1X00_AC97C_INT
-#define AU1X00_GPIO_0 32
-#define AU1X00_GPIO_1 33
-#define AU1X00_GPIO_2 34
-#define AU1X00_GPIO_3 35
-#define AU1X00_GPIO_4 36
-#define AU1X00_GPIO_5 37
-#define AU1X00_GPIO_6 38
-#define AU1X00_GPIO_7 39
-#define AU1X00_GPIO_8 40
-#define AU1X00_GPIO_9 41
-#define AU1X00_GPIO_10 42
-#define AU1X00_GPIO_11 43
-#define AU1X00_GPIO_12 44
-#define AU1X00_GPIO_13 45
-#define AU1X00_GPIO_14 46
-#define AU1X00_GPIO_15 47
-
-/* Au1000 only */
-#define AU1000_GPIO_16 48
-#define AU1000_GPIO_17 49
-#define AU1000_GPIO_18 50
-#define AU1000_GPIO_19 51
-#define AU1000_GPIO_20 52
-#define AU1000_GPIO_21 53
-#define AU1000_GPIO_22 54
-#define AU1000_GPIO_23 55
-#define AU1000_GPIO_24 56
-#define AU1000_GPIO_25 57
-#define AU1000_GPIO_26 58
-#define AU1000_GPIO_27 59
-#define AU1000_GPIO_28 60
-#define AU1000_GPIO_29 61
-#define AU1000_GPIO_30 62
-#define AU1000_GPIO_31 63
-
-/* Au1500 only */
-#define AU1500_GPIO_200 48
-#define AU1500_GPIO_201 49
-#define AU1500_GPIO_202 50
-#define AU1500_GPIO_203 51
-#define AU1500_GPIO_20 52
-#define AU1500_GPIO_204 53
-#define AU1500_GPIO_205 54
-#define AU1500_GPIO_23 55
-#define AU1500_GPIO_24 56
-#define AU1500_GPIO_25 57
-#define AU1500_GPIO_26 58
-#define AU1500_GPIO_27 59
-#define AU1500_GPIO_28 60
-#define AU1500_GPIO_206 61
-#define AU1500_GPIO_207 62
-#define AU1500_GPIO_208_215 63
-
-#define AU1X00_MAX_INTR 63
-
-#define AU1100_SD 2
-#define AU1100_GPIO_208_215 29
-/* REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE */
-
-/* Programmable Counters 0 and 1 */
-#define SYS_BASE 0xB1900000
-#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
-#define SYS_CNTRL_E1S (1<<23)
-#define SYS_CNTRL_T1S (1<<20)
-#define SYS_CNTRL_M21 (1<<19)
-#define SYS_CNTRL_M11 (1<<18)
-#define SYS_CNTRL_M01 (1<<17)
-#define SYS_CNTRL_C1S (1<<16)
-#define SYS_CNTRL_BP (1<<14)
-#define SYS_CNTRL_EN1 (1<<13)
-#define SYS_CNTRL_BT1 (1<<12)
-#define SYS_CNTRL_EN0 (1<<11)
-#define SYS_CNTRL_BT0 (1<<10)
-#define SYS_CNTRL_E0 (1<<8)
-#define SYS_CNTRL_E0S (1<<7)
-#define SYS_CNTRL_32S (1<<5)
-#define SYS_CNTRL_T0S (1<<4)
-#define SYS_CNTRL_M20 (1<<3)
-#define SYS_CNTRL_M10 (1<<2)
-#define SYS_CNTRL_M00 (1<<1)
-#define SYS_CNTRL_C0S (1<<0)
-
-/* Programmable Counter 0 Registers */
-#define SYS_TOYTRIM (SYS_BASE + 0)
-#define SYS_TOYWRITE (SYS_BASE + 4)
-#define SYS_TOYMATCH0 (SYS_BASE + 8)
-#define SYS_TOYMATCH1 (SYS_BASE + 0xC)
-#define SYS_TOYMATCH2 (SYS_BASE + 0x10)
-#define SYS_TOYREAD (SYS_BASE + 0x40)
-
-/* Programmable Counter 1 Registers */
-#define SYS_RTCTRIM (SYS_BASE + 0x44)
-#define SYS_RTCWRITE (SYS_BASE + 0x48)
-#define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
-#define SYS_RTCMATCH1 (SYS_BASE + 0x50)
-#define SYS_RTCMATCH2 (SYS_BASE + 0x54)
-#define SYS_RTCREAD (SYS_BASE + 0x58)
-
-/* I2S Controller */
-#define I2S_DATA 0xB1000000
-#define I2S_DATA_MASK (0xffffff)
-#define I2S_CONFIG 0xB1000004
-#define I2S_CONFIG_XU (1<<25)
-#define I2S_CONFIG_XO (1<<24)
-#define I2S_CONFIG_RU (1<<23)
-#define I2S_CONFIG_RO (1<<22)
-#define I2S_CONFIG_TR (1<<21)
-#define I2S_CONFIG_TE (1<<20)
-#define I2S_CONFIG_TF (1<<19)
-#define I2S_CONFIG_RR (1<<18)
-#define I2S_CONFIG_RE (1<<17)
-#define I2S_CONFIG_RF (1<<16)
-#define I2S_CONFIG_PD (1<<11)
-#define I2S_CONFIG_LB (1<<10)
-#define I2S_CONFIG_IC (1<<9)
-#define I2S_CONFIG_FM_BIT 7
-#define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
-#define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
-#define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
-#define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
-#define I2S_CONFIG_TN (1<<6)
-#define I2S_CONFIG_RN (1<<5)
-#define I2S_CONFIG_SZ_BIT 0
-#define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
-
-#define I2S_CONTROL 0xB1000008
-#define I2S_CONTROL_D (1<<1)
-#define I2S_CONTROL_CE (1<<0)
-
-/* USB Host Controller */
-/* We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address */
-#define USB_OHCI_BASE 0x10100000
-#define USB_OHCI_LEN 0x00100000
-#define USB_HOST_CONFIG 0xB017fffc
-
-/* USB Device Controller */
-#define USBD_EP0RD 0xB0200000
-#define USBD_EP0WR 0xB0200004
-#define USBD_EP2WR 0xB0200008
-#define USBD_EP3WR 0xB020000C
-#define USBD_EP4RD 0xB0200010
-#define USBD_EP5RD 0xB0200014
-#define USBD_INTEN 0xB0200018
-#define USBD_INTSTAT 0xB020001C
-#define USBDEV_INT_SOF (1<<12)
-#define USBDEV_INT_HF_BIT 6
-#define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
-#define USBDEV_INT_CMPLT_BIT 0
-#define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
-#define USBD_CONFIG 0xB0200020
-#define USBD_EP0CS 0xB0200024
-#define USBD_EP2CS 0xB0200028
-#define USBD_EP3CS 0xB020002C
-#define USBD_EP4CS 0xB0200030
-#define USBD_EP5CS 0xB0200034
-#define USBDEV_CS_SU (1<<14)
-#define USBDEV_CS_NAK (1<<13)
-#define USBDEV_CS_ACK (1<<12)
-#define USBDEV_CS_BUSY (1<<11)
-#define USBDEV_CS_TSIZE_BIT 1
-#define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
-#define USBDEV_CS_STALL (1<<0)
-#define USBD_EP0RDSTAT 0xB0200040
-#define USBD_EP0WRSTAT 0xB0200044
-#define USBD_EP2WRSTAT 0xB0200048
-#define USBD_EP3WRSTAT 0xB020004C
-#define USBD_EP4RDSTAT 0xB0200050
-#define USBD_EP5RDSTAT 0xB0200054
-#define USBDEV_FSTAT_FLUSH (1<<6)
-#define USBDEV_FSTAT_UF (1<<5)
-#define USBDEV_FSTAT_OF (1<<4)
-#define USBDEV_FSTAT_FCNT_BIT 0
-#define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
-#define USBD_ENABLE 0xB0200058
-#define USBDEV_ENABLE (1<<1)
-#define USBDEV_CE (1<<0)
-
-/* Ethernet Controllers */
-#define AU1000_ETH0_BASE 0xB0500000
-#define AU1000_ETH1_BASE 0xB0510000
-#define AU1500_ETH0_BASE 0xB1500000
-#define AU1500_ETH1_BASE 0xB1510000
-#define AU1100_ETH0_BASE 0xB0500000
-#define AU1550_ETH0_BASE 0xB0500000
-#define AU1550_ETH1_BASE 0xB0510000
-
-/* 4 byte offsets from AU1000_ETH_BASE */
-#define MAC_CONTROL 0x0
-#define MAC_RX_ENABLE (1<<2)
-#define MAC_TX_ENABLE (1<<3)
-#define MAC_DEF_CHECK (1<<5)
-#define MAC_SET_BL(X) (((X)&0x3)<<6)
-#define MAC_AUTO_PAD (1<<8)
-#define MAC_DISABLE_RETRY (1<<10)
-#define MAC_DISABLE_BCAST (1<<11)
-#define MAC_LATE_COL (1<<12)
-#define MAC_HASH_MODE (1<<13)
-#define MAC_HASH_ONLY (1<<15)
-#define MAC_PASS_ALL (1<<16)
-#define MAC_INVERSE_FILTER (1<<17)
-#define MAC_PROMISCUOUS (1<<18)
-#define MAC_PASS_ALL_MULTI (1<<19)
-#define MAC_FULL_DUPLEX (1<<20)
-#define MAC_NORMAL_MODE 0
-#define MAC_INT_LOOPBACK (1<<21)
-#define MAC_EXT_LOOPBACK (1<<22)
-#define MAC_DISABLE_RX_OWN (1<<23)
-#define MAC_BIG_ENDIAN (1<<30)
-#define MAC_RX_ALL (1<<31)
-#define MAC_ADDRESS_HIGH 0x4
-#define MAC_ADDRESS_LOW 0x8
-#define MAC_MCAST_HIGH 0xC
-#define MAC_MCAST_LOW 0x10
-#define MAC_MII_CNTRL 0x14
-#define MAC_MII_BUSY (1<<0)
-#define MAC_MII_READ 0
-#define MAC_MII_WRITE (1<<1)
-#define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
-#define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
-#define MAC_MII_DATA 0x18
-#define MAC_FLOW_CNTRL 0x1C
-#define MAC_FLOW_CNTRL_BUSY (1<<0)
-#define MAC_FLOW_CNTRL_ENABLE (1<<1)
-#define MAC_PASS_CONTROL (1<<2)
-#define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
-#define MAC_VLAN1_TAG 0x20
-#define MAC_VLAN2_TAG 0x24
-
-/* Ethernet Controller Enable */
-#define AU1000_MAC0_ENABLE 0xB0520000
-#define AU1000_MAC1_ENABLE 0xB0520004
-#define AU1500_MAC0_ENABLE 0xB1520000
-#define AU1500_MAC1_ENABLE 0xB1520004
-#define AU1100_MAC0_ENABLE 0xB0520000
-#define AU1550_MAC0_ENABLE 0xB0520000
-#define AU1550_MAC1_ENABLE 0xB0520004
-
-#define MAC_EN_CLOCK_ENABLE (1<<0)
-#define MAC_EN_RESET0 (1<<1)
-#define MAC_EN_TOSS (0<<2)
-#define MAC_EN_CACHEABLE (1<<3)
-#define MAC_EN_RESET1 (1<<4)
-#define MAC_EN_RESET2 (1<<5)
-#define MAC_DMA_RESET (1<<6)
-
-/* Ethernet Controller DMA Channels */
-
-#define MAC0_TX_DMA_ADDR 0xB4004000
-#define MAC1_TX_DMA_ADDR 0xB4004200
-/* offsets from MAC_TX_RING_ADDR address */
-#define MAC_TX_BUFF0_STATUS 0x0
-#define TX_FRAME_ABORTED (1<<0)
-#define TX_JAB_TIMEOUT (1<<1)
-#define TX_NO_CARRIER (1<<2)
-#define TX_LOSS_CARRIER (1<<3)
-#define TX_EXC_DEF (1<<4)
-#define TX_LATE_COLL_ABORT (1<<5)
-#define TX_EXC_COLL (1<<6)
-#define TX_UNDERRUN (1<<7)
-#define TX_DEFERRED (1<<8)
-#define TX_LATE_COLL (1<<9)
-#define TX_COLL_CNT_MASK (0xF<<10)
-#define TX_PKT_RETRY (1<<31)
-#define MAC_TX_BUFF0_ADDR 0x4
-#define TX_DMA_ENABLE (1<<0)
-#define TX_T_DONE (1<<1)
-#define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
-#define MAC_TX_BUFF0_LEN 0x8
-#define MAC_TX_BUFF1_STATUS 0x10
-#define MAC_TX_BUFF1_ADDR 0x14
-#define MAC_TX_BUFF1_LEN 0x18
-#define MAC_TX_BUFF2_STATUS 0x20
-#define MAC_TX_BUFF2_ADDR 0x24
-#define MAC_TX_BUFF2_LEN 0x28
-#define MAC_TX_BUFF3_STATUS 0x30
-#define MAC_TX_BUFF3_ADDR 0x34
-#define MAC_TX_BUFF3_LEN 0x38
-
-#define MAC0_RX_DMA_ADDR 0xB4004100
-#define MAC1_RX_DMA_ADDR 0xB4004300
-/* offsets from MAC_RX_RING_ADDR */
-#define MAC_RX_BUFF0_STATUS 0x0
-#define RX_FRAME_LEN_MASK 0x3fff
-#define RX_WDOG_TIMER (1<<14)
-#define RX_RUNT (1<<15)
-#define RX_OVERLEN (1<<16)
-#define RX_COLL (1<<17)
-#define RX_ETHER (1<<18)
-#define RX_MII_ERROR (1<<19)
-#define RX_DRIBBLING (1<<20)
-#define RX_CRC_ERROR (1<<21)
-#define RX_VLAN1 (1<<22)
-#define RX_VLAN2 (1<<23)
-#define RX_LEN_ERROR (1<<24)
-#define RX_CNTRL_FRAME (1<<25)
-#define RX_U_CNTRL_FRAME (1<<26)
-#define RX_MCAST_FRAME (1<<27)
-#define RX_BCAST_FRAME (1<<28)
-#define RX_FILTER_FAIL (1<<29)
-#define RX_PACKET_FILTER (1<<30)
-#define RX_MISSED_FRAME (1<<31)
-
-#define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
- RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
- RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
-#define MAC_RX_BUFF0_ADDR 0x4
-#define RX_DMA_ENABLE (1<<0)
-#define RX_T_DONE (1<<1)
-#define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
-#define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
-#define MAC_RX_BUFF1_STATUS 0x10
-#define MAC_RX_BUFF1_ADDR 0x14
-#define MAC_RX_BUFF2_STATUS 0x20
-#define MAC_RX_BUFF2_ADDR 0x24
-#define MAC_RX_BUFF3_STATUS 0x30
-#define MAC_RX_BUFF3_ADDR 0x34
-
-
-/* UARTS 0-3 */
-#define UART0_ADDR 0xB1100000
-#define UART1_ADDR 0xB1200000
-#define UART2_ADDR 0xB1300000
-#define UART3_ADDR 0xB1400000
-#define UART_BASE UART0_ADDR
-#define UART_DEBUG_BASE UART2_ADDR
-
-#define UART_RX 0 /* Receive buffer */
-#define UART_TX 4 /* Transmit buffer */
-#define UART_IER 8 /* Interrupt Enable Register */
-#define UART_IIR 0xC /* Interrupt ID Register */
-#define UART_FCR 0x10 /* FIFO Control Register */
-#define UART_LCR 0x14 /* Line Control Register */
-#define UART_MCR 0x18 /* Modem Control Register */
-#define UART_LSR 0x1C /* Line Status Register */
-#define UART_MSR 0x20 /* Modem Status Register */
-#define UART_CLK 0x28 /* Baud Rate Clock Divider */
-#define UART_ENABLE 0x100 /* Uart enable */
-
-#define UART_EN_CE 1 /* Clock enable */
-#define UART_EN_E 2 /* Enable */
-
-#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
-#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
-#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
-#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
-#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
-#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
-#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
-#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
-#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
-#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
-#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
-#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
-#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
-
-/*
- * These are the definitions for the Line Control Register
- */
-#define UART_LCR_SBC 0x40 /* Set break control */
-#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
-#define UART_LCR_EPAR 0x10 /* Even parity select */
-#define UART_LCR_PARITY 0x08 /* Parity Enable */
-#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
-#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
-#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
-#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
-#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
-
-/*
- * These are the definitions for the Line Status Register
- */
-#define UART_LSR_TEMT 0x40 /* Transmitter empty */
-#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
-#define UART_LSR_BI 0x10 /* Break interrupt indicator */
-#define UART_LSR_FE 0x08 /* Frame error indicator */
-#define UART_LSR_PE 0x04 /* Parity error indicator */
-#define UART_LSR_OE 0x02 /* Overrun error indicator */
-#define UART_LSR_DR 0x01 /* Receiver data ready */
-
-/*
- * These are the definitions for the Interrupt Identification Register
- */
-#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
-#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
-#define UART_IIR_MSI 0x00 /* Modem status interrupt */
-#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
-#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
-#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
-
-/*
- * These are the definitions for the Interrupt Enable Register
- */
-#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
-#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
-#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
-#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
-
-/*
- * These are the definitions for the Modem Control Register
- */
-#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
-#define UART_MCR_OUT2 0x08 /* Out2 complement */
-#define UART_MCR_OUT1 0x04 /* Out1 complement */
-#define UART_MCR_RTS 0x02 /* RTS complement */
-#define UART_MCR_DTR 0x01 /* DTR complement */
-
-/*
- * These are the definitions for the Modem Status Register
- */
-#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
-#define UART_MSR_RI 0x40 /* Ring Indicator */
-#define UART_MSR_DSR 0x20 /* Data Set Ready */
-#define UART_MSR_CTS 0x10 /* Clear to Send */
-#define UART_MSR_DDCD 0x08 /* Delta DCD */
-#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
-#define UART_MSR_DDSR 0x02 /* Delta DSR */
-#define UART_MSR_DCTS 0x01 /* Delta CTS */
-#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
-
-
-/* SSIO */
-#define SSI0_STATUS 0xB1600000
-#define SSI_STATUS_BF (1<<4)
-#define SSI_STATUS_OF (1<<3)
-#define SSI_STATUS_UF (1<<2)
-#define SSI_STATUS_D (1<<1)
-#define SSI_STATUS_B (1<<0)
-#define SSI0_INT 0xB1600004
-#define SSI_INT_OI (1<<3)
-#define SSI_INT_UI (1<<2)
-#define SSI_INT_DI (1<<1)
-#define SSI0_INT_ENABLE 0xB1600008
-#define SSI_INTE_OIE (1<<3)
-#define SSI_INTE_UIE (1<<2)
-#define SSI_INTE_DIE (1<<1)
-#define SSI0_CONFIG 0xB1600020
-#define SSI_CONFIG_AO (1<<24)
-#define SSI_CONFIG_DO (1<<23)
-#define SSI_CONFIG_ALEN_BIT 20
-#define SSI_CONFIG_ALEN_MASK (0x7<<20)
-#define SSI_CONFIG_DLEN_BIT 16
-#define SSI_CONFIG_DLEN_MASK (0x7<<16)
-#define SSI_CONFIG_DD (1<<11)
-#define SSI_CONFIG_AD (1<<10)
-#define SSI_CONFIG_BM_BIT 8
-#define SSI_CONFIG_BM_MASK (0x3<<8)
-#define SSI_CONFIG_CE (1<<7)
-#define SSI_CONFIG_DP (1<<6)
-#define SSI_CONFIG_DL (1<<5)
-#define SSI_CONFIG_EP (1<<4)
-#define SSI0_ADATA 0xB1600024
-#define SSI_AD_D (1<<24)
-#define SSI_AD_ADDR_BIT 16
-#define SSI_AD_ADDR_MASK (0xff<<16)
-#define SSI_AD_DATA_BIT 0
-#define SSI_AD_DATA_MASK (0xfff<<0)
-#define SSI0_CLKDIV 0xB1600028
-#define SSI0_CONTROL 0xB1600100
-#define SSI_CONTROL_CD (1<<1)
-#define SSI_CONTROL_E (1<<0)
-
-/* SSI1 */
-#define SSI1_STATUS 0xB1680000
-#define SSI1_INT 0xB1680004
-#define SSI1_INT_ENABLE 0xB1680008
-#define SSI1_CONFIG 0xB1680020
-#define SSI1_ADATA 0xB1680024
-#define SSI1_CLKDIV 0xB1680028
-#define SSI1_ENABLE 0xB1680100
-
-/*
- * Register content definitions
- */
-#define SSI_STATUS_BF (1<<4)
-#define SSI_STATUS_OF (1<<3)
-#define SSI_STATUS_UF (1<<2)
-#define SSI_STATUS_D (1<<1)
-#define SSI_STATUS_B (1<<0)
-
-/* SSI_INT */
-#define SSI_INT_OI (1<<3)
-#define SSI_INT_UI (1<<2)
-#define SSI_INT_DI (1<<1)
-
-/* SSI_INTEN */
-#define SSI_INTEN_OIE (1<<3)
-#define SSI_INTEN_UIE (1<<2)
-#define SSI_INTEN_DIE (1<<1)
-
-#define SSI_CONFIG_AO (1<<24)
-#define SSI_CONFIG_DO (1<<23)
-#define SSI_CONFIG_ALEN (7<<20)
-#define SSI_CONFIG_DLEN (15<<16)
-#define SSI_CONFIG_DD (1<<11)
-#define SSI_CONFIG_AD (1<<10)
-#define SSI_CONFIG_BM (3<<8)
-#define SSI_CONFIG_CE (1<<7)
-#define SSI_CONFIG_DP (1<<6)
-#define SSI_CONFIG_DL (1<<5)
-#define SSI_CONFIG_EP (1<<4)
-#define SSI_CONFIG_ALEN_N(N) ((N-1)<<20)
-#define SSI_CONFIG_DLEN_N(N) ((N-1)<<16)
-#define SSI_CONFIG_BM_HI (0<<8)
-#define SSI_CONFIG_BM_LO (1<<8)
-#define SSI_CONFIG_BM_CY (2<<8)
-
-#define SSI_ADATA_D (1<<24)
-#define SSI_ADATA_ADDR (0xFF<<16)
-#define SSI_ADATA_DATA (0x0FFF)
-#define SSI_ADATA_ADDR_N(N) (N<<16)
-
-#define SSI_ENABLE_CD (1<<1)
-#define SSI_ENABLE_E (1<<0)
-
-
-/* IrDA Controller */
-#define IRDA_BASE 0xB0300000
-#define IR_RING_PTR_STATUS (IRDA_BASE+0x00)
-#define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04)
-#define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08)
-#define IR_RING_SIZE (IRDA_BASE+0x0C)
-#define IR_RING_PROMPT (IRDA_BASE+0x10)
-#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)
-#define IR_INT_CLEAR (IRDA_BASE+0x18)
-#define IR_CONFIG_1 (IRDA_BASE+0x20)
-#define IR_RX_INVERT_LED (1<<0)
-#define IR_TX_INVERT_LED (1<<1)
-#define IR_ST (1<<2)
-#define IR_SF (1<<3)
-#define IR_SIR (1<<4)
-#define IR_MIR (1<<5)
-#define IR_FIR (1<<6)
-#define IR_16CRC (1<<7)
-#define IR_TD (1<<8)
-#define IR_RX_ALL (1<<9)
-#define IR_DMA_ENABLE (1<<10)
-#define IR_RX_ENABLE (1<<11)
-#define IR_TX_ENABLE (1<<12)
-#define IR_LOOPBACK (1<<14)
-#define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
- IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
-#define IR_SIR_FLAGS (IRDA_BASE+0x24)
-#define IR_ENABLE (IRDA_BASE+0x28)
-#define IR_RX_STATUS (1<<9)
-#define IR_TX_STATUS (1<<10)
-#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)
-#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)
-#define IR_MAX_PKT_LEN (IRDA_BASE+0x34)
-#define IR_RX_BYTE_CNT (IRDA_BASE+0x38)
-#define IR_CONFIG_2 (IRDA_BASE+0x3C)
-#define IR_MODE_INV (1<<0)
-#define IR_ONE_PIN (1<<1)
-#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)
-
-/* GPIO */
-#define SYS_PINFUNC 0xB190002C
-#define SYS_PF_USB (1<<15) /* 2nd USB device/host */
-#define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */
-#define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */
-#define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */
-#define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */
-#define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */
-#define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */
-#define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */
-#define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */
-#define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */
-#define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */
-#define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */
-#define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */
-#define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */
-#define SYS_PF_A97 (1<<1) /* AC97/SSL1 */
-#define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */
-#define SYS_TRIOUTRD 0xB1900100
-#define SYS_TRIOUTCLR 0xB1900100
-#define SYS_OUTPUTRD 0xB1900108
-#define SYS_OUTPUTSET 0xB1900108
-#define SYS_OUTPUTCLR 0xB190010C
-#define SYS_PINSTATERD 0xB1900110
-#define SYS_PININPUTEN 0xB1900110
-
-/* GPIO2, Au1500 only */
-#define GPIO2_BASE 0xB1700000
-#define GPIO2_DIR (GPIO2_BASE + 0)
-#define GPIO2_DATA_EN (GPIO2_BASE + 8)
-#define GPIO2_PIN_STATE (GPIO2_BASE + 0xC)
-#define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10)
-#define GPIO2_ENABLE (GPIO2_BASE + 0x14)
-
-/* Power Management */
-#define SYS_SCRATCH0 0xB1900018
-#define SYS_SCRATCH1 0xB190001C
-#define SYS_WAKEMSK 0xB1900034
-#define SYS_ENDIAN 0xB1900038
-#define SYS_POWERCTRL 0xB190003C
-#define SYS_WAKESRC 0xB190005C
-#define SYS_SLPPWR 0xB1900078
-#define SYS_SLEEP 0xB190007C
-
-/* Clock Controller */
-#define SYS_FREQCTRL0 0xB1900020
-#define SYS_FC_FRDIV2_BIT 22
-#define SYS_FC_FRDIV2_MASK (0xff << FQC2_FRDIV2_BIT)
-#define SYS_FC_FE2 (1<<21)
-#define SYS_FC_FS2 (1<<20)
-#define SYS_FC_FRDIV1_BIT 12
-#define SYS_FC_FRDIV1_MASK (0xff << FQC2_FRDIV1_BIT)
-#define SYS_FC_FE1 (1<<11)
-#define SYS_FC_FS1 (1<<10)
-#define SYS_FC_FRDIV0_BIT 2
-#define SYS_FC_FRDIV0_MASK (0xff << FQC2_FRDIV0_BIT)
-#define SYS_FC_FE0 (1<<1)
-#define SYS_FC_FS0 (1<<0)
-#define SYS_FREQCTRL1 0xB1900024
-#define SYS_FC_FRDIV5_BIT 22
-#define SYS_FC_FRDIV5_MASK (0xff << FQC2_FRDIV5_BIT)
-#define SYS_FC_FE5 (1<<21)
-#define SYS_FC_FS5 (1<<20)
-#define SYS_FC_FRDIV4_BIT 12
-#define SYS_FC_FRDIV4_MASK (0xff << FQC2_FRDIV4_BIT)
-#define SYS_FC_FE4 (1<<11)
-#define SYS_FC_FS4 (1<<10)
-#define SYS_FC_FRDIV3_BIT 2
-#define SYS_FC_FRDIV3_MASK (0xff << FQC2_FRDIV3_BIT)
-#define SYS_FC_FE3 (1<<1)
-#define SYS_FC_FS3 (1<<0)
-#define SYS_CLKSRC 0xB1900028
-#define SYS_CS_ME1_BIT 27
-#define SYS_CS_ME1_MASK (0x7<<CSC_ME1_BIT)
-#define SYS_CS_DE1 (1<<26)
-#define SYS_CS_CE1 (1<<25)
-#define SYS_CS_ME0_BIT 22
-#define SYS_CS_ME0_MASK (0x7<<CSC_ME0_BIT)
-#define SYS_CS_DE0 (1<<21)
-#define SYS_CS_CE0 (1<<20)
-#define SYS_CS_MI2_BIT 17
-#define SYS_CS_MI2_MASK (0x7<<CSC_MI2_BIT)
-#define SYS_CS_DI2 (1<<16)
-#define SYS_CS_CI2 (1<<15)
-#define SYS_CS_MUH_BIT 12
-#define SYS_CS_MUH_MASK (0x7<<CSC_MUH_BIT)
-#define SYS_CS_DUH (1<<11)
-#define SYS_CS_CUH (1<<10)
-#define SYS_CS_MUD_BIT 7
-#define SYS_CS_MUD_MASK (0x7<<CSC_MUD_BIT)
-#define SYS_CS_DUD (1<<6)
-#define SYS_CS_CUD (1<<5)
-#define SYS_CS_MIR_BIT 2
-#define SYS_CS_MIR_MASK (0x7<<CSC_MIR_BIT)
-#define SYS_CS_DIR (1<<1)
-#define SYS_CS_CIR (1<<0)
-
-#define SYS_CS_MUX_AUX 0x1
-#define SYS_CS_MUX_FQ0 0x2
-#define SYS_CS_MUX_FQ1 0x3
-#define SYS_CS_MUX_FQ2 0x4
-#define SYS_CS_MUX_FQ3 0x5
-#define SYS_CS_MUX_FQ4 0x6
-#define SYS_CS_MUX_FQ5 0x7
-#define SYS_CPUPLL 0xB1900060
-#define SYS_AUXPLL 0xB1900064
-
-/* AC97 Controller */
-#define AC97C_CONFIG 0xB0000000
-#define AC97C_RECV_SLOTS_BIT 13
-#define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
-#define AC97C_XMIT_SLOTS_BIT 3
-#define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
-#define AC97C_SG (1<<2)
-#define AC97C_SYNC (1<<1)
-#define AC97C_RESET (1<<0)
-#define AC97C_STATUS 0xB0000004
-#define AC97C_XU (1<<11)
-#define AC97C_XO (1<<10)
-#define AC97C_RU (1<<9)
-#define AC97C_RO (1<<8)
-#define AC97C_READY (1<<7)
-#define AC97C_CP (1<<6)
-#define AC97C_TR (1<<5)
-#define AC97C_TE (1<<4)
-#define AC97C_TF (1<<3)
-#define AC97C_RR (1<<2)
-#define AC97C_RE (1<<1)
-#define AC97C_RF (1<<0)
-#define AC97C_DATA 0xB0000008
-#define AC97C_CMD 0xB000000C
-#define AC97C_WD_BIT 16
-#define AC97C_READ (1<<7)
-#define AC97C_INDEX_MASK 0x7f
-#define AC97C_CNTRL 0xB0000010
-#define AC97C_RS (1<<1)
-#define AC97C_CE (1<<0)
-
-#define DB1000_BCSR_ADDR 0xAE000000
-#define DB1550_BCSR_ADDR 0xAF000000
-
-#ifdef CONFIG_DBAU1550
-#define DB1XX0_BCSR_ADDR DB1550_BCSR_ADDR
-#else
-#define DB1XX0_BCSR_ADDR DB1000_BCSR_ADDR
-#endif
-
-#ifdef CONFIG_SOC_AU1500
-/* Au1500 PCI Controller */
-#define Au1500_CFG_BASE 0xB4005000 /* virtual, kseg0 addr */
-#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
-#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
-#define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
-#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
-#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
-#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
-#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
-#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
-#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
-#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
-#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
-#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
-#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
-#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
-#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
-
-#define Au1500_PCI_HDR 0xB4005100 /* virtual, kseg0 addr */
-
-/* All of our structures, like pci resource, have 32 bit members.
- * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
- * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch
- * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
- * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM
- * addresses. For PCI IO, it's simpler because we get to do the ioremap
- * ourselves and then adjust the device's resources.
- */
-#define Au1500_EXT_CFG 0x600000000
-#define Au1500_EXT_CFG_TYPE1 0x680000000
-#define Au1500_PCI_IO_START 0x500000000
-#define Au1500_PCI_IO_END 0x5000FFFFF
-#define Au1500_PCI_MEM_START 0x440000000
-#define Au1500_PCI_MEM_END 0x443FFFFFF
-
-#define PCI_IO_START (Au1500_PCI_IO_START + 0x300)
-#define PCI_IO_END (Au1500_PCI_IO_END)
-#define PCI_MEM_START (Au1500_PCI_MEM_START)
-#define PCI_MEM_END (Au1500_PCI_MEM_END)
-#define PCI_FIRST_DEVFN (0<<3)
-#define PCI_LAST_DEVFN (19<<3)
-
-#endif
-
-#if defined(CONFIG_SOC_AU1100) || (defined(CONFIG_SOC_AU1000) && !defined(CONFIG_MIPS_PB1000))
-/* no PCI bus controller */
-#define PCI_IO_START 0
-#define PCI_IO_END 0
-#define PCI_MEM_START 0
-#define PCI_MEM_END 0
-#define PCI_FIRST_DEVFN 0
-#define PCI_LAST_DEVFN 0
-#endif
-#define AU1X_SOCK0_IO 0xF00000000
-#define AU1X_SOCK0_PHYS_ATTR 0xF40000000
-#define AU1X_SOCK0_PHYS_MEM 0xF80000000
-
-/* pcmcia socket 1 needs external glue logic so the memory map
- * differs from board to board.
- */
-
-/* Only for db board, not older pb */
-#define AU1X_SOCK1_IO 0xF04000000
-#define AU1X_SOCK1_PHYS_ATTR 0xF44000000
-#define AU1X_SOCK1_PHYS_MEM 0xF84000000
-
-#endif
default "bcm6368" if SOC_BMIPS_BCM6368
default "bcm6362" if SOC_BMIPS_BCM6362
default "bcm63268" if SOC_BMIPS_BCM63268
+ default "bcm6838" if SOC_BMIPS_BCM6838
choice
prompt "Broadcom MIPS SoC select"
This supports BMIPS BCM63268 family including BCM63168, BCM63169,
BCM63268 and BCM63269.
+config SOC_BMIPS_BCM6838
+ bool "BMIPS BCM6838 family"
+ select MIPS_L1_CACHE_SHIFT_4
+ select MIPS_TUNE_4KC
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SWAP_IO_SPACE
+ select SYSRESET_SYSCON
+ help
+ This supports BMIPS BCM6838 family including BCM68380, BCM68381,
+ and BCM68385.
+
endchoice
choice
prompt "Board select"
+config BOARD_BROADCOM_BCM968380GERG
+ bool "Broadcom bcm968380gerg"
+ depends on SOC_BMIPS_BCM6838
+ select BMIPS_SUPPORTS_BOOT_RAM
+ help
+ Broadcom BCM968380GERG reference board with BCM68380 SoC with 512 MB
+ of RAM and 128 MB of flash (nand).
+ Between its different peripherals there's an integrated switch with 4
+ ethernet ports, 2 USB ports, 1 UART, GPIO buttons and LEDs, and
+ a BCM43217 (PCIe).
+
config BOARD_COMTREND_AR5315U
bool "Comtrend AR-5315u"
depends on SOC_BMIPS_BCM6318
config BMIPS_SUPPORTS_BOOT_RAM
bool
+source "board/broadcom/bcm968380gerg/Kconfig"
source "board/comtrend/ar5315u/Kconfig"
source "board/comtrend/ar5387un/Kconfig"
source "board/comtrend/ct5361/Kconfig"
i2c0 = &i2c_0;
pci0 = &pci;
rtc0 = &rtc_0;
+ axi0 = &axi;
};
chosen {
};
};
};
+
+ axi: axi@0 {
+ compatible = "sandbox,axi";
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ store@0 {
+ compatible = "sandbox,sandbox_store";
+ reg = <0x0 0x400>;
+ };
+ };
};
#include "cros-ec-keyboard.dtsi"
i2c0 = "/i2c@0";
mmc0 = "/mmc0";
mmc1 = "/mmc1";
- pci0 = &pci;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ pci2 = &pci2;
remoteproc1 = &rproc_1;
remoteproc2 = &rproc_2;
rtc0 = &rtc_0;
usb0 = &usb_0;
usb1 = &usb_1;
usb2 = &usb_2;
+ axi0 = &axi;
};
a-test {
mbox-names = "other", "test";
};
+ misc-test {
+ compatible = "sandbox,misc_sandbox";
+ };
+
mmc2 {
compatible = "sandbox,mmc";
};
compatible = "sandbox,mmc";
};
- pci: pci-controller {
+ pci0: pci-controller0 {
compatible = "sandbox,pci";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
0x01000000 0 0x20000000 0x20000000 0 0x2000>;
+ pci@0,0 {
+ compatible = "pci-generic";
+ reg = <0x0000 0 0 0 0>;
+ emul@0,0 {
+ compatible = "sandbox,swap-case";
+ };
+ };
+ pci@1f,0 {
+ compatible = "pci-generic";
+ reg = <0xf800 0 0 0 0>;
+ emul@1f,0 {
+ compatible = "sandbox,swap-case";
+ };
+ };
+ };
+
+ pci1: pci-controller1 {
+ compatible = "sandbox,pci";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
+ 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
+ sandbox,dev-info = <0x08 0x00 0x1234 0x5678
+ 0x0c 0x00 0x1234 0x5678>;
+ };
+
+ pci2: pci-controller2 {
+ compatible = "sandbox,pci";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
+ 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
+ sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
pci@1f,0 {
compatible = "pci-generic";
reg = <0xf800 0 0 0 0>;
compatible = "sandbox,wdt";
};
+ axi: axi@0 {
+ compatible = "sandbox,axi";
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ store@0 {
+ compatible = "sandbox,sandbox_store";
+ reg = <0x0 0x400>;
+ };
+ };
+
chosen {
#address-cells = <1>;
#size-cells = <1>;
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#ifndef __asm_axi_h
+#define __asm_axi_h
+
+#define axi_emul_get_ops(dev) ((struct axi_emul_ops *)(dev)->driver->ops)
+
+/**
+ * axi_sandbox_get_emul() - Retrieve a pointer to a AXI emulation device
+ * @bus: The AXI bus from which to retrieve a emulation device
+ * @address: The address of a transfer that should be handled by a emulation
+ * device
+ * @length: The data width of a transfer that should be handled by a emulation
+ * device
+ * @emulp: Pointer to a buffer receiving the emulation device that handles
+ * the transfer specified by the address and length parameters
+ *
+ * To test the AXI uclass, we implement a simple AXI emulation device, which is
+ * a virtual device on a AXI bus that exposes a simple storage interface: When
+ * reading and writing from the device, the addresses are translated to offsets
+ * within the device's storage. For write accesses the data is written to the
+ * specified storage offset, and for read accesses the data is read from the
+ * specified storage offset.
+ *
+ * A DTS entry might look like this:
+ *
+ * axi: axi@0 {
+ * compatible = "sandbox,axi";
+ * #address-cells = <0x1>;
+ * #size-cells = <0x1>;
+ * store@0 {
+ * compatible = "sandbox,sandbox_store";
+ * reg = <0x0 0x400>;
+ * };
+ * };
+ *
+ * This function may then be used to retrieve the pointer to the sandbox_store
+ * emulation device given the AXI bus device, and the data (address, data
+ * width) of a AXI transfer which should be handled by a emulation device.
+ *
+ * Return: 0 of OK, -ENODEV if no device capable of handling the specified
+ * transfer exists or the device could not be retrieved
+ */
+int axi_sandbox_get_emul(struct udevice *bus, ulong address, uint length,
+ struct udevice **emulp);
+/**
+ * axi_get_store() - Get address of internal storage of a emulated AXI device
+ * @dev: Emulated AXI device to get the pointer of the internal storage
+ * for.
+ * @storep: Pointer to the internal storage of the emulated AXI device.
+ *
+ * To preset or read back the contents internal storage of the emulated AXI
+ * device, this function returns the pointer to the storage. Changes to the
+ * contents of the storage are reflected when using the AXI read/write API
+ * methods, and vice versa, so by using this method expected read data can be
+ * set up in advance, and written data can be checked in unit tests.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+int axi_get_store(struct udevice *dev, u8 **storep);
+
+#endif /* __asm_axi_h */
#define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM
#define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL
+#define PCI_CAP_ID_PM_OFFSET 0x50
+#define PCI_CAP_ID_EXP_OFFSET 0x60
+#define PCI_CAP_ID_MSIX_OFFSET 0x70
+
+#define PCI_EXT_CAP_ID_ERR_OFFSET 0x100
+#define PCI_EXT_CAP_ID_VC_OFFSET 0x200
+#define PCI_EXT_CAP_ID_DSN_OFFSET 0x300
+
+/* Useful for PCI_VDEVICE() macro */
+#define PCI_VENDOR_ID_SANDBOX SANDBOX_PCI_VENDOR_ID
+#define SWAP_CASE_DRV_DATA 0x55aa
+
#define SANDBOX_CLK_RATE 32768
/* System controller driver data */
+++ /dev/null
-#
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
-#
-
-# Armada XP uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl.bin 0000005b 00000068
+++ /dev/null
-#
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
-#
-
-# Armada XP uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
+++ /dev/null
-#
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
-#
-
-# Armada XP uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
+++ /dev/null
-#
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
-#
-
-# Armada XP uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
+++ /dev/null
-#
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
-#
-
-# Armada XP uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
+++ /dev/null
-#
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
-#
-
-# Armada XP uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
--- /dev/null
+if TARGET_SBx81LIFXCAT
+
+config SYS_BOARD
+ default "SBx81LIFXCAT"
+
+config SYS_VENDOR
+ default "alliedtelesis"
+
+config SYS_CONFIG_NAME
+ default "SBx81LIFXCAT"
+
+endif
--- /dev/null
+SBx81LIFXCAT BOARD
+M: Chris Packham <chris.packham@alliedtelesis.co.nz>
+S: Maintained
+F: board/alliedtelesis/SBx81LIFXCAT/
+F: include/configs/SBx81LIFXCAT
+F: configs/SBx81LIFXCAT_defconfig
+F: arch/arm/dts/kirkwood-atl-sbx81lifxcat.dts
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010, 2018
+# Allied Telesis <www.alliedtelesis.com>
+#
+
+obj-y += sbx81lifxcat.o
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2018 Allied Telesis
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+DATA 0xffd100e0 0x1b1b1b1b
+DATA 0xffd20134 0xffffffff
+DATA 0xffd20138 0x009fffff
+DATA 0xffd20154 0x00000000
+DATA 0xffd2014c 0x00000000
+DATA 0xffd20148 0x00000001
+
+# Dram initalization for 1 x x16
+# DDR II Micron part number MT47H64M16HR-3
+# MClk 333MHz, Size 128MB, ECC disable
+#
+DATA 0xffd01400 0x43000618
+DATA 0xffd01404 0x38543000
+DATA 0xffd01408 0x23125441
+DATA 0xffd0140c 0x00000832
+DATA 0xffd01410 0x0000000D
+DATA 0xffd01414 0x00000000
+DATA 0xffd01418 0x00000000
+DATA 0xffd0141c 0x00000652
+DATA 0xffd01420 0x00000042
+DATA 0xffd01424 0x0000F0FF
+DATA 0xffd01428 0x00074410
+DATA 0xffd0147C 0x00007441
+DATA 0xffd01500 0x00000000 # SDRAM CS[0] Base address at 0x00000000
+DATA 0xffd01504 0x07FFFFF1 # SDRAM CS[0] Size 128MiB
+DATA 0xffd01508 0x10000000
+DATA 0xffd0150c 0x00FFFFF4 # SDRAM CS[1] Size, window disabled
+DATA 0xffd01514 0x00FFFFF8 # SDRAM CS[2] Size, window disabled
+DATA 0xffd0151c 0x00FFFFFC # SDRAM CS[3] Size, window disabled
+DATA 0xffd01494 0x84210000
+DATA 0xffd01498 0x00000000
+DATA 0xffd0149c 0x0000F80F
+DATA 0xffd01480 0x00000001
+
+# End of Header extension
+DATA 0x0 0x0
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010, 2018
+ * Allied Telesis <www.alliedtelesis.com>
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <led.h>
+#include <linux/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#define SBX81LIFXCAT_OE_LOW (~0)
+#define SBX81LIFXCAT_OE_HIGH (~BIT(11))
+#define SBX81LIFXCAT_OE_VAL_LOW (0)
+#define SBX81LIFXCAT_OE_VAL_HIGH (BIT(11))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(SBX81LIFXCAT_OE_VAL_LOW,
+ SBX81LIFXCAT_OE_VAL_HIGH,
+ SBX81LIFXCAT_OE_LOW, SBX81LIFXCAT_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_SPI_SCn,
+ MPP1_SPI_MOSI,
+ MPP2_SPI_SCK,
+ MPP3_SPI_MISO,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO,
+ MPP13_UART1_TXD,
+ MPP14_UART1_RXD,
+ MPP15_GPIO,
+ MPP16_GPIO,
+ MPP17_GPIO,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GE1_0,
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GE1_8,
+ MPP29_GE1_9,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_GPIO,
+ MPP41_GPIO,
+ MPP42_GPIO,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO,
+ MPP48_GPIO,
+ MPP49_GPIO,
+ 0
+ };
+
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* automatically defined by kirkwood config.h */
+void reset_phy(void)
+{
+}
+#endif
+
+#ifdef CONFIG_MV88E61XX_SWITCH
+int mv88e61xx_hw_reset(struct phy_device *phydev)
+{
+ phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = led_get_by_label("status:ledp", &dev);
+ if (!ret)
+ led_set_state(dev, LEDST_ON);
+
+ ret = led_get_by_label("status:ledn", &dev);
+ if (!ret)
+ led_set_state(dev, LEDST_OFF);
+
+ return 0;
+}
+#endif
--- /dev/null
+if BOARD_BROADCOM_BCM968380GERG
+
+config SYS_BOARD
+ default "bcm968380gerg"
+
+config SYS_VENDOR
+ default "broadcom"
+
+config SYS_CONFIG_NAME
+ default "broadcom_bcm968380gerg"
+
+endif
--- /dev/null
+BCM968380GERG BOARD
+M: Philippe Reynes <philippe.reynes@softathome.com>
+S: Maintained
+F: board/broadcom/bcm968380gerg/
+F: include/configs/broadcom_bcm968380gerg.h
+F: configs/bcm968380gerg_ram_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += bcm968380gerg.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include <common.h>
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include <common.h>
+++ /dev/null
-if TARGET_DBAU1X00
-
-config SYS_BOARD
- default "dbau1x00"
-
-config SYS_SOC
- default "au1x00"
-
-config SYS_CONFIG_NAME
- default "dbau1x00"
-
-config SYS_TEXT_BASE
- default 0xbfc00000
-
-config SYS_DCACHE_SIZE
- default 16384
-
-config SYS_DCACHE_LINE_SIZE
- default 32
-
-config SYS_ICACHE_SIZE
- default 16384
-
-config SYS_ICACHE_LINE_SIZE
- default 32
-
-menu "dbau1x00 board options"
-
-choice
- prompt "Select au1x00 SoC type"
- optional
-
-config DBAU1100
- bool "Select AU1100"
-
-config DBAU1500
- bool "Select AU1500"
-
-config DBAU1550
- bool "Select AU1550"
-
-endchoice
-
-endmenu
-
-endif
+++ /dev/null
-DBAU1X00 BOARD
-#M: -
-S: Orphan (since 2016-06)
-F: board/dbau1x00/
-F: include/configs/dbau1x00.h
-F: configs/dbau1000_defconfig
-F: configs/dbau1100_defconfig
-F: configs/dbau1500_defconfig
-F: configs/dbau1550_defconfig
-F: configs/dbau1550_el_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y = dbau1x00.o
-obj-y += lowlevel_init.o
+++ /dev/null
-By Thomas.Lange@corelatus.se 2004-Oct-05
-----------------------------------------
-DbAu1xx0 are development boards from AMD containing
-an Alchemy AU1xx0 series cpu with mips32 core.
-Existing cpu:s are Au1000, Au1100, Au1500 and Au1550
-
-Limitations & comments
-----------------------
-Support was originally big endian only.
-I have not tested, but several u-boot users report working
-configurations in little endian mode.
-
-I named the board dbau1x00, to allow
-support for all three development boards
-( dbau1000, dbau1100 and dbau1500 ).
-Now there is a new board called dbau1550 also, which
-should be supported RSN.
-
-I only have a dbau1000, so my testing is limited
-to this board.
-
-The board has two different flash banks, that can
-be selected via dip switch. This makes it possible
-to test new bootloaders without thrashing the YAMON
-boot loader delivered with board.
-
-NOTE! When you switch between the two boot flashes, the
-base addresses will be swapped.
-Have this in mind when you compile u-boot. CONFIG_SYS_TEXT_BASE has
-to match the address where u-boot is located when you
-actually launch.
-
-Ethernet only supported for mac0.
-
-PCMCIA only supported for slot 0, only 3.3V.
-
-PCMCIA IDE tested with Sandisk Compact Flash and
-IBM microdrive.
-
-###################################
-######## NOTE!!!!!! #########
-###################################
-If you partition a disk on another system (e.g. laptop),
-all bytes will be swapped on 16bit level when using
-PCMCIA and running cpu in big endian mode!!!!
-
-This is probably due to an error in Au1000 chip.
-
-Solution:
-
-a) Boot via network and partition disk directly from
-dbau1x00. The endian will then be correct.
-
-b) Partition disk on "laptop" and fill it with all files
-you need. Then write a simple program that endian swaps
-whole disk,
-
-Example:
-Original "laptop" byte order:
-B0 B1 B2 B3 B4 B5 B6 B7 B8 B9...
-
-Dbau1000 byte order will then be:
-B1 B0 B3 B2 B5 B4 B7 B6 B9 B8...
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2003
- * Thomas.Lange@corelatus.se
- */
-
-#include <common.h>
-#include <command.h>
-#include <mach/au1x00.h>
-#include <asm/mipsregs.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- /* Sdram is setup by assembler code */
- /* If memory could be changed, we should return the true value here */
- gd->ram_size = MEM_SIZE * 1024 * 1024;
-
- return 0;
-}
-
-#define BCSR_PCMCIA_PC0DRVEN 0x0010
-#define BCSR_PCMCIA_PC0RST 0x0080
-
-/* In arch/mips/cpu/cpu.c */
-void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
-
-int checkboard (void)
-{
-#ifdef CONFIG_IDE_PCMCIA
- u16 status;
- volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10);
-#endif /* CONFIG_IDE_PCMCIA */
- volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC);
- volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
- u32 proc_id;
-
- *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
-
- proc_id = read_c0_prid();
-
- switch (proc_id >> 24) {
- case 0:
- puts ("Board: Merlot (DbAu1000)\n");
- printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
- (proc_id >> 8) & 0xFF, proc_id & 0xFF);
- break;
- case 1:
- puts ("Board: DbAu1500\n");
- printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
- (proc_id >> 8) & 0xFF, proc_id & 0xFF);
- break;
- case 2:
- puts ("Board: DbAu1100\n");
- printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
- (proc_id >> 8) & 0xFF, proc_id & 0xFF);
- break;
- case 3:
- puts ("Board: DbAu1550\n");
- printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n",
- (proc_id >> 8) & 0xFF, proc_id & 0xFF);
- break;
- default:
- printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
- }
-
- set_io_port_base(0);
-
-#ifdef CONFIG_IDE_PCMCIA
- /* Enable 3.3 V on slot 0 ( VCC )
- No 5V */
- status = 4;
- *pcmcia_bcsr = status;
-
- status |= BCSR_PCMCIA_PC0DRVEN;
- *pcmcia_bcsr = status;
- au_sync();
-
- udelay(300*1000);
-
- status |= BCSR_PCMCIA_PC0RST;
- *pcmcia_bcsr = status;
- au_sync();
-
- udelay(100*1000);
-
- /* PCMCIA is on a 36 bit physical address.
- We need to map it into a 32 bit addresses */
-
-#if 0
- /* We dont need theese unless we run whole pcmcia package */
- write_one_tlb(20, /* index */
- 0x01ffe000, /* Pagemask, 16 MB pages */
- CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
- 0x3C000017, /* Lo0 */
- 0x3C200017); /* Lo1 */
-
- write_one_tlb(21, /* index */
- 0x01ffe000, /* Pagemask, 16 MB pages */
- CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
- 0x3D000017, /* Lo0 */
- 0x3D200017); /* Lo1 */
-#endif /* 0 */
- write_one_tlb(22, /* index */
- 0x01ffe000, /* Pagemask, 16 MB pages */
- CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */
- 0x3E000017, /* Lo0 */
- 0x3E200017); /* Lo1 */
-#endif /* CONFIG_IDE_PCMCIA */
-
- /* Release reset of ethernet PHY chips */
- /* Always do this, because linux does not know about it */
- *phy = 3;
-
- return 0;
-}
+++ /dev/null
-/* Memory sub-system initialization code */
-
-#include <config.h>
-#include <mach/au1x00.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-
-#define AU1500_SYS_ADDR 0xB1900000
-#define sys_endian 0x0038
-#define CP0_Config0 $16
-#define CPU_SCALE ((CONFIG_SYS_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
-#define MEM_1MS ((CONFIG_SYS_MHZ) * 1000)
-
- .text
- .set noreorder
- .set mips32
-
- .globl lowlevel_init
-lowlevel_init:
- /*
- * Step 1) Establish CPU endian mode.
- * Db1500-specific:
- * Switch S1.1 Off(bit7 reads 1) is Little Endian
- * Switch S1.1 On (bit7 reads 0) is Big Endian
- */
-#ifdef CONFIG_DBAU1550
- li t0, MEM_STCFG2
- li t1, 0x00000040
- sw t1, 0(t0)
-
- li t0, MEM_STTIME2
- li t1, 0x22080a20
- sw t1, 0(t0)
-
- li t0, MEM_STADDR2
- li t1, 0x10c03f00
- sw t1, 0(t0)
-#else
- li t0, MEM_STCFG1
- li t1, 0x00000080
- sw t1, 0(t0)
-
- li t0, MEM_STTIME1
- li t1, 0x22080a20
- sw t1, 0(t0)
-
- li t0, MEM_STADDR1
- li t1, 0x10c03f00
- sw t1, 0(t0)
-#endif
-
- li t0, DB1XX0_BCSR_ADDR
- lw t1,8(t0)
- andi t1,t1,0x80
- beq zero,t1,big_endian
- nop
-little_endian:
-
- /* Change Au1 core to little endian */
- li t0, AU1500_SYS_ADDR
- li t1, 1
- sw t1, sys_endian(t0)
- mfc0 t2, CP0_CONFIG
- mtc0 t2, CP0_CONFIG
- nop
- nop
-
- /* Big Endian is default so nothing to do but fall through */
-
-big_endian:
-
- /*
- * Step 2) Establish Status Register
- * (set BEV, clear ERL, clear EXL, clear IE)
- */
- li t1, 0x00400000
- mtc0 t1, CP0_STATUS
-
- /*
- * Step 3) Establish CP0 Config0
- * (set OD, set K0=3)
- */
- li t1, 0x00080003
- mtc0 t1, CP0_CONFIG
-
- /*
- * Step 4) Disable Watchpoint facilities
- */
- li t1, 0x00000000
- mtc0 t1, CP0_WATCHLO
- mtc0 t1, CP0_IWATCHLO
- /*
- * Step 5) Disable the performance counters
- */
- mtc0 zero, CP0_PERFORMANCE
- nop
-
- /*
- * Step 6) Establish EJTAG Debug register
- */
- mtc0 zero, CP0_DEBUG
- nop
-
- /*
- * Step 7) Establish Cause
- * (set IV bit)
- */
- li t1, 0x00800000
- mtc0 t1, CP0_CAUSE
-
- /* Establish Wired (and Random) */
- mtc0 zero, CP0_WIRED
- nop
-
-#ifdef CONFIG_DBAU1550
- /* No workaround if running from ram */
- lui t0, 0xffc0
- lui t3, 0xbfc0
- and t1, ra, t0
- bne t1, t3, noCacheJump
- nop
-
- /*** From AMD YAMON ***/
- /*
- * Step 8) Initialize the caches
- */
- li t0, (16*1024)
- li t1, 32
- li t2, 0x80000000
- addu t3, t0, t2
-cacheloop:
- cache 0, 0(t2)
- cache 1, 0(t2)
- addu t2, t1
- bne t2, t3, cacheloop
- nop
-
- /* Save return address */
- move t3, ra
-
- /* Run from cacheable space now */
- bal cachehere
- nop
-cachehere:
- li t1, ~0x20000000 /* convert to KSEG0 */
- and t0, ra, t1
- addi t0, 5*4 /* 5 insns beyond cachehere */
- jr t0
- nop
-
- /* Restore return address */
- move ra, t3
-
- /*
- * Step 9) Initialize the TLB
- */
- li t0, 0 # index value
- li t1, 0x00000000 # entryhi value
- li t2, 32 # 32 entries
-
-tlbloop:
- /* Probe TLB for matching EntryHi */
- mtc0 t1, CP0_ENTRYHI
- tlbp
- nop
-
- /* Examine Index[P], 1=no matching entry */
- mfc0 t3, CP0_INDEX
- li t4, 0x80000000
- and t3, t4, t3
- addiu t1, t1, 1 # increment t1 (asid)
- beq zero, t3, tlbloop
- nop
-
- /* Initialize the TLB entry */
- mtc0 t0, CP0_INDEX
- mtc0 zero, CP0_ENTRYLO0
- mtc0 zero, CP0_ENTRYLO1
- mtc0 zero, CP0_PAGEMASK
- tlbwi
-
- /* Do it again */
- addiu t0, t0, 1
- bne t0, t2, tlbloop
- nop
-
-#endif /* CONFIG_DBAU1550 */
-
- /* First setup pll:s to make serial work ok */
- /* We have a 12 MHz crystal */
- li t0, SYS_CPUPLL
- li t1, CPU_SCALE /* CPU clock */
- sw t1, 0(t0)
- sync
- nop
- nop
-
- /* wait 1mS for clocks to settle */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
- /* Setup AUX PLL */
- li t0, SYS_AUXPLL
- li t1, 0x20 /* 96 MHz */
- sw t1, 0(t0) /* aux pll */
- sync
-
-#ifdef CONFIG_DBAU1550
- /* Static memory controller */
- /* RCE0 - can not change while fetching, do so from icache */
- move t2, ra /* Store return address */
- bal getAddr
- nop
-
-getAddr:
- move t1, ra
- move ra, t2 /* Move return addess back */
-
- cache 0x14,0(t1)
- cache 0x14,32(t1)
- /*** /From YAMON ***/
-
-noCacheJump:
-#endif /* CONFIG_DBAU1550 */
-
-#ifdef CONFIG_DBAU1550
- li t0, MEM_STTIME0
- li t1, 0x040181D7
- sw t1, 0(t0)
-
- /* RCE0 AMD MirrorBit Flash (?) */
- li t0, MEM_STCFG0
- li t1, 0x00000003
- sw t1, 0(t0)
-
- li t0, MEM_STADDR0
- li t1, 0x11803E00
- sw t1, 0(t0)
-#else /* CONFIG_DBAU1550 */
- li t0, MEM_STTIME0
- li t1, 0x040181D7
- sw t1, 0(t0)
-
- /* RCE0 AMD 29LV640M MirrorBit Flash */
- li t0, MEM_STCFG0
- li t1, 0x00000013
- sw t1, 0(t0)
-
- li t0, MEM_STADDR0
- li t1, 0x11E03F80
- sw t1, 0(t0)
-#endif /* CONFIG_DBAU1550 */
-
- /* RCE1 CPLD Board Logic */
- li t0, MEM_STCFG1
- li t1, 0x00000080
- sw t1, 0(t0)
-
- li t0, MEM_STTIME1
- li t1, 0x22080a20
- sw t1, 0(t0)
-
- li t0, MEM_STADDR1
- li t1, 0x10c03f00
- sw t1, 0(t0)
-
-#ifdef CONFIG_DBAU1550
- /* RCE2 CPLD Board Logic */
- li t0, MEM_STCFG2
- li t1, 0x00000040
- sw t1, 0(t0)
-
- li t0, MEM_STTIME2
- li t1, 0x22080a20
- sw t1, 0(t0)
-
- li t0, MEM_STADDR2
- li t1, 0x10c03f00
- sw t1, 0(t0)
-#else
- li t0, MEM_STCFG2
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, MEM_STTIME2
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, MEM_STADDR2
- li t1, 0x00000000
- sw t1, 0(t0)
-#endif
-
- /* RCE3 PCMCIA 250ns */
- li t0, MEM_STCFG3
- li t1, 0x00000002
- sw t1, 0(t0)
-
- li t0, MEM_STTIME3
- li t1, 0x280E3E07
- sw t1, 0(t0)
-
- li t0, MEM_STADDR3
- li t1, 0x10000000
- sw t1, 0(t0)
-
- sync
-
- /* Set peripherals to a known state */
- li t0, IC0_CFG0CLR
- li t1, 0xFFFFFFFF
- sw t1, 0(t0)
-
- li t0, IC0_CFG0CLR
- sw t1, 0(t0)
-
- li t0, IC0_CFG1CLR
- sw t1, 0(t0)
-
- li t0, IC0_CFG2CLR
- sw t1, 0(t0)
-
- li t0, IC0_SRCSET
- sw t1, 0(t0)
-
- li t0, IC0_ASSIGNSET
- sw t1, 0(t0)
-
- li t0, IC0_WAKECLR
- sw t1, 0(t0)
-
- li t0, IC0_RISINGCLR
- sw t1, 0(t0)
-
- li t0, IC0_FALLINGCLR
- sw t1, 0(t0)
-
- li t0, IC0_TESTBIT
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, IC1_CFG0CLR
- li t1, 0xFFFFFFFF
- sw t1, 0(t0)
-
- li t0, IC1_CFG0CLR
- sw t1, 0(t0)
-
- li t0, IC1_CFG1CLR
- sw t1, 0(t0)
-
- li t0, IC1_CFG2CLR
- sw t1, 0(t0)
-
- li t0, IC1_SRCSET
- sw t1, 0(t0)
-
- li t0, IC1_ASSIGNSET
- sw t1, 0(t0)
-
- li t0, IC1_WAKECLR
- sw t1, 0(t0)
-
- li t0, IC1_RISINGCLR
- sw t1, 0(t0)
-
- li t0, IC1_FALLINGCLR
- sw t1, 0(t0)
-
- li t0, IC1_TESTBIT
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, SYS_FREQCTRL0
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_FREQCTRL1
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_CLKSRC
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_PININPUTEN
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, 0xB1100100
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, 0xB1400100
- li t1, 0x00000000
- sw t1, 0(t0)
-
-
- li t0, SYS_WAKEMSK
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_WAKESRC
- li t1, 0x00000000
- sw t1, 0(t0)
-
- /* wait 1mS before setup */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
-
-#ifdef CONFIG_DBAU1550
-/* SDCS 0,1,2 DDR SDRAM */
- li t0, MEM_SDMODE0
- li t1, 0x04276221
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE1
- li t1, 0x04276221
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE2
- li t1, 0x04276221
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR0
- li t1, 0xe21003f0
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR1
- li t1, 0xe21043f0
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR2
- li t1, 0xe21083f0
- sw t1, 0(t0)
-
- sync
-
- li t0, MEM_SDCONFIGA
- li t1, 0x9030060a /* Program refresh - disabled */
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDCONFIGB
- li t1, 0x00028000
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDPRECMD /* Precharge all */
- li t1, 0
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD0
- li t1, 0x40000000
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD1
- li t1, 0x40000000
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD2
- li t1, 0x40000000
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD0
- li t1, 0x00000063
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD1
- li t1, 0x00000063
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD2
- li t1, 0x00000063
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDPRECMD /* Precharge all */
- sw zero, 0(t0)
- sync
-
- /* Issue 2 autoref */
- li t0, MEM_SDAUTOREF
- sw zero, 0(t0)
- sync
-
- li t0, MEM_SDAUTOREF
- sw zero, 0(t0)
- sync
-
- /* Enable refresh */
- li t0, MEM_SDCONFIGA
- li t1, 0x9830060a /* Program refresh - enabled */
- sw t1, 0(t0)
- sync
-
-#else /* CONFIG_DBAU1550 */
-/* SDCS 0,1 SDRAM */
- li t0, MEM_SDMODE0
- li t1, 0x005522AA
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE1
- li t1, 0x005522AA
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE2
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR0
- li t1, 0x001003F8
- sw t1, 0(t0)
-
-
- li t0, MEM_SDADDR1
- li t1, 0x001023F8
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR2
- li t1, 0x00000000
- sw t1, 0(t0)
-
- sync
-
- li t0, MEM_SDREFCFG
- li t1, 0x64000C24 /* Disable */
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDPRECMD
- sw zero, 0(t0)
- sync
-
- li t0, MEM_SDAUTOREF
- sw zero, 0(t0)
- sync
- sw zero, 0(t0)
- sync
-
- li t0, MEM_SDREFCFG
- li t1, 0x66000C24 /* Enable */
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD0
- li t1, 0x00000033
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD1
- li t1, 0x00000033
- sw t1, 0(t0)
- sync
-
-#endif /* CONFIG_DBAU1550 */
- /* wait 1mS after setup */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
-
- li t0, SYS_PINFUNC
- li t1, 0x00008080
- sw t1, 0(t0)
-
- li t0, SYS_TRIOUTCLR
- li t1, 0x00001FFF
- sw t1, 0(t0)
-
- li t0, SYS_OUTPUTCLR
- li t1, 0x00008000
- sw t1, 0(t0)
- sync
-
- jr ra
- nop
+++ /dev/null
-if TARGET_CONTROLCENTERDC
-
-config SYS_BOARD
- default "a38x"
-
-config SYS_VENDOR
- default "gdsys"
-
-config SYS_SOC
- default "mvebu"
-
-config SYS_CONFIG_NAME
- default "controlcenterdc"
-
-menu "Controlcenter DC board options"
-
-choice
- prompt "Select boot method"
-
-config SPL_BOOT_DEVICE_SPI
- bool "SPI"
-
-config SPL_BOOT_DEVICE_MMC
- bool "MMC"
- select SPL_LIBDISK_SUPPORT
-
-endchoice
-
-#config SPL_BOOT_DEVICE
-# int
-# default 1 if SPL_BOOT_DEVICE_SPI
-# default 2 if SPL_BOOT_DEVICE_MMC
-
-endmenu
-
-endif
obj-$(CONFIG_TARGET_CONTROLCENTERDC) += controlcenterdc.o hre.o spl.o keyprogram.o dt_helpers.o
ifeq ($(CONFIG_SPL_BUILD),)
-
obj-$(CONFIG_TARGET_CONTROLCENTERDC) += hydra.o ihs_phys.o
-
-extra-$(CONFIG_TARGET_CONTROLCENTERDC) += kwbimage.cfg
-
-KWB_REPLACE += BOOT_FROM
-ifneq ($(CONFIG_SPL_BOOT_DEVICE_SPI),)
- KWB_CFG_BOOT_FROM=spi
-endif
-ifneq ($(CONFIG_SPL_BOOT_DEVICE_MMC),)
- KWB_CFG_BOOT_FROM=sdio
-endif
-
-ifneq ($(CONFIG_SECURED_MODE_IMAGE),)
-KWB_REPLACE += CSK_INDEX
-KWB_CFG_CSK_INDEX = $(CONFIG_SECURED_MODE_CSK_INDEX)
-
-KWB_REPLACE += SEC_BOOT_DEV
-KWB_CFG_SEC_BOOT_DEV=$(patsubst "%",%, \
- $(if $(findstring BOOT_SPI_NOR_FLASH,$(CONFIG_SPL_BOOT_DEVICE)),0x34) \
- $(if $(findstring BOOT_SDIO_MMC_CARD,$(CONFIG_SPL_BOOT_DEVICE)),0x31) \
- )
-
-KWB_REPLACE += SEC_FUSE_DUMP
-KWB_CFG_SEC_FUSE_DUMP = a38x
-endif
-
-$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
- include/config/auto.conf
- $(Q)sed -ne '$(foreach V,$(KWB_REPLACE),s/^#@$(V)/$(V) $(KWB_CFG_$(V))/;)p' \
- <$< >$(dir $<)$(@F)
-
endif
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2015 Stefan Roese <sr@denx.de>
-#
-
-# Armada 38x use version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM sdio
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
+++ /dev/null
-#
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
-#
-
-# Armada XP uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
+++ /dev/null
-if TARGET_PB1X00
-
-config SYS_BOARD
- default "pb1x00"
-
-config SYS_SOC
- default "au1x00"
-
-config SYS_CONFIG_NAME
- default "pb1x00"
-
-config SYS_TEXT_BASE
- default 0x83800000
-
-config SYS_DCACHE_SIZE
- default 16384
-
-config SYS_DCACHE_LINE_SIZE
- default 32
-
-config SYS_ICACHE_SIZE
- default 16384
-
-config SYS_ICACHE_LINE_SIZE
- default 32
-
-endif
+++ /dev/null
-PB1X00 BOARD
-#M: -
-S: Maintained
-F: board/pb1x00/
-F: include/configs/pb1x00.h
-F: configs/pb1000_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y = pb1x00.o flash.o
-obj-y += lowlevel_init.o
+++ /dev/null
-By Thomas.Lange@corelatus.se 2004-Oct-05
-----------------------------------------
-DbAu1xx0 are development boards from AMD containing
-an Alchemy AU1xx0 series cpu with mips32 core.
-Existing cpu:s are Au1000, Au1100, Au1500 and Au1550
-
-Limitations & comments
-----------------------
-Support was originally big endian only.
-I have not tested, but several u-boot users report working
-configurations in little endian mode.
-
-I named the board dbau1x00, to allow
-support for all three development boards
-( dbau1000, dbau1100 and dbau1500 ).
-Now there is a new board called dbau1550 also, which
-should be supported RSN.
-
-I only have a dbau1000, so my testing is limited
-to this board.
-
-The board has two different flash banks, that can
-be selected via dip switch. This makes it possible
-to test new bootloaders without thrashing the YAMON
-boot loader delivered with board.
-
-NOTE! When you switch between the two boot flashes, the
-base addresses will be swapped.
-Have this in mind when you compile u-boot. CONFIG_SYS_TEXT_BASE has
-to match the address where u-boot is located when you
-actually launch.
-
-Ethernet only supported for mac0.
-
-PCMCIA only supported for slot 0, only 3.3V.
-
-PCMCIA IDE tested with Sandisk Compact Flash and
-IBM microdrive.
-
-###################################
-######## NOTE!!!!!! #########
-###################################
-If you partition a disk on another system (e.g. laptop),
-all bytes will be swapped on 16bit level when using
-PCMCIA and running cpu in big endian mode!!!!
-
-This is probably due to an error in Au1000 chip.
-
-Solution:
-
-a) Boot via network and partition disk directly from
-dbau1x00. The endian will then be correct.
-
-b) Partition disk on "laptop" and fill it with all files
-you need. Then write a simple program that endian swaps
-whole disk,
-
-Example:
-Original "laptop" byte order:
-B0 B1 B2 B3 B4 B5 B6 B7 B8 B9...
-
-Dbau1000 byte order will then be:
-B1 B0 B3 B2 B5 B4 B7 B6 B9 B8...
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
- printf ("Skipping flash_init\n");
- return (0);
-}
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- printf ("write_buff not implemented\n");
- return (-1);
-}
+++ /dev/null
-/* Memory sub-system initialization code */
-
-#include <config.h>
-#include <mach/au1x00.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-
-#define AU1500_SYS_ADDR 0xB1900000
-#define sys_endian 0x0038
-#define CP0_Config0 $16
-#define MEM_1MS ((396000000/1000000) * 1000)
-
- .text
- .set noreorder
- .set mips32
-
- .globl lowlevel_init
-lowlevel_init:
- /*
- * Step 1) Establish CPU endian mode.
- * NOTE: A fair amount of code is necessary on the Pb1000 to
- * obtain the value of Switch S8.1 which is used to determine
- * endian at run-time.
- */
-
- /* RCE1 */
- li t0, MEM_STCFG1
- li t1, 0x00000083
- sw t1, 0(t0)
-
- li t0, MEM_STTIME1
- li t1, 0x33030A10
- sw t1, 0(t0)
-
- li t0, MEM_STADDR1
- li t1, 0x11803E40
- sw t1, 0(t0)
-
- /* Set DSTRB bits so switch will read correctly */
- li t1, 0xBE00000C
- lw t2, 0(t1)
- or t2, t2, 0x00000300
- sw t2, 0(t1)
-
- /* Check switch setting */
- li t1, 0xBE000014
- lw t2, 0(t1)
- and t2, t2, 0x00000100
- bne t2, zero, big_endian
- nop
-
-little_endian:
-
- /* Change Au1 core to little endian */
- li t0, AU1500_SYS_ADDR
- li t1, 1
- sw t1, sys_endian(t0)
- mfc0 t2, CP0_CONFIG
- mtc0 t2, CP0_CONFIG
- nop
- nop
-
- /* Big Endian is default so nothing to do but fall through */
-
-big_endian:
-
- /*
- * Step 2) Establish Status Register
- * (set BEV, clear ERL, clear EXL, clear IE)
- */
- li t1, 0x00400000
- mtc0 t1, CP0_STATUS
-
- /*
- * Step 3) Establish CP0 Config0
- * (set OD, set K0=3)
- */
- li t1, 0x00080003
- mtc0 t1, CP0_CONFIG
-
- /*
- * Step 4) Disable Watchpoint facilities
- */
- li t1, 0x00000000
- mtc0 t1, CP0_WATCHLO
- mtc0 t1, CP0_IWATCHLO
- /*
- * Step 5) Disable the performance counters
- */
- mtc0 zero, CP0_PERFORMANCE
- nop
-
- /*
- * Step 6) Establish EJTAG Debug register
- */
- mtc0 zero, CP0_DEBUG
- nop
-
- /*
- * Step 7) Establish Cause
- * (set IV bit)
- */
- li t1, 0x00800000
- mtc0 t1, CP0_CAUSE
-
- /* Establish Wired (and Random) */
- mtc0 zero, CP0_WIRED
- nop
-
- /* First setup pll:s to make serial work ok */
- /* We have a 12 MHz crystal */
- li t0, SYS_CPUPLL
- li t1, 0x21 /* 396 MHz */
- sw t1, 0(t0)
- sync
- nop
- nop
-
- /* wait 1mS for clocks to settle */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
- /* Setup AUX PLL */
- li t0, SYS_AUXPLL
- li t1, 8 /* 96 MHz */
- sw t1, 0(t0) /* aux pll */
- sync
-
- /* Static memory controller */
-
- /* RCE0 8MB AMD29D323 Flash */
- li t0, MEM_STCFG0
- li t1, 0x00001403
- sw t1, 0(t0)
-
- li t0, MEM_STTIME0
- li t1, 0xFFFFFFDD
- sw t1, 0(t0)
-
- li t0, MEM_STADDR0
- li t1, 0x11F83FE0
- sw t1, 0(t0)
-
- /* RCE1 CPLD Board Logic */
- li t0, MEM_STCFG1
- li t1, 0x00000083
- sw t1, 0(t0)
-
- li t0, MEM_STTIME1
- li t1, 0x33030A10
- sw t1, 0(t0)
-
- li t0, MEM_STADDR1
- li t1, 0x11803E40
- sw t1, 0(t0)
-
- /* RCE2 CPLD Board Logic */
- li t0, MEM_STCFG2
- li t1, 0x00000004
- sw t1, 0(t0)
-
- li t0, MEM_STTIME2
- li t1, 0x08061908
- sw t1, 0(t0)
-
- li t0, MEM_STADDR2
- li t1, 0x12A03FC0
- sw t1, 0(t0)
-
- /* RCE3 PCMCIA 250ns */
- li t0, MEM_STCFG3
- li t1, 0x00000002
- sw t1, 0(t0)
-
- li t0, MEM_STTIME3
- li t1, 0x280E3E07
- sw t1, 0(t0)
-
- li t0, MEM_STADDR3
- li t1, 0x10000000
- sw t1, 0(t0)
-
- sync
-
- /* Set peripherals to a known state */
- li t0, IC0_CFG0CLR
- li t1, 0xFFFFFFFF
- sw t1, 0(t0)
-
- li t0, IC0_CFG0CLR
- sw t1, 0(t0)
-
- li t0, IC0_CFG1CLR
- sw t1, 0(t0)
-
- li t0, IC0_CFG2CLR
- sw t1, 0(t0)
-
- li t0, IC0_SRCSET
- sw t1, 0(t0)
-
- li t0, IC0_ASSIGNSET
- sw t1, 0(t0)
-
- li t0, IC0_WAKECLR
- sw t1, 0(t0)
-
- li t0, IC0_RISINGCLR
- sw t1, 0(t0)
-
- li t0, IC0_FALLINGCLR
- sw t1, 0(t0)
-
- li t0, IC0_TESTBIT
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, IC1_CFG0CLR
- li t1, 0xFFFFFFFF
- sw t1, 0(t0)
-
- li t0, IC1_CFG0CLR
- sw t1, 0(t0)
-
- li t0, IC1_CFG1CLR
- sw t1, 0(t0)
-
- li t0, IC1_CFG2CLR
- sw t1, 0(t0)
-
- li t0, IC1_SRCSET
- sw t1, 0(t0)
-
- li t0, IC1_ASSIGNSET
- sw t1, 0(t0)
-
- li t0, IC1_WAKECLR
- sw t1, 0(t0)
-
- li t0, IC1_RISINGCLR
- sw t1, 0(t0)
-
- li t0, IC1_FALLINGCLR
- sw t1, 0(t0)
-
- li t0, IC1_TESTBIT
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, SYS_FREQCTRL0
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_FREQCTRL1
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_CLKSRC
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_PININPUTEN
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, 0xB1100100
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, 0xB1400100
- li t1, 0x00000000
- sw t1, 0(t0)
-
-
- li t0, SYS_WAKEMSK
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_WAKESRC
- li t1, 0x00000000
- sw t1, 0(t0)
-
- /* wait 1mS before setup */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
-
- /*
- * Skip memory setup if we are running from memory
- */
- li t0, 0x90000000
- sub t0, ra, t0
- bltz t0, skip_memsetup
- nop
-
- /*
- * SDCS0 - Not used, for SMROM
- * SDCS1 - 32MB Micron 48LCBM16A2
- * SDCS2 - 32MB Micron 48LCBM16A2
- */
- li t0, MEM_SDMODE0
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE1
- li t1, 0x00552229
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE2
- li t1, 0x00552229
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR0
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR1
- li t1, 0x001003F8
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR2
- li t1, 0x001023F8
- sw t1, 0(t0)
-
- sync
-
- li t0, MEM_SDREFCFG
- li t1, 0x74000c30 /* Disable */
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDPRECMD
- sw zero, 0(t0)
- sync
-
- li t0, MEM_SDAUTOREF
- sw zero, 0(t0)
- sync
- sw zero, 0(t0)
- sync
-
- li t0, MEM_SDREFCFG
- li t1, 0x76000c30 /* Enable */
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD0
- li t1, 0x00000023
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD1
- li t1, 0x00000023
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD2
- li t1, 0x00000023
- sw t1, 0(t0)
- sync
-
- /* wait 1mS after setup */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
-
-skip_memsetup:
-
- li t0, SYS_PINFUNC
- li t1, 0/*0x00008080*/
- sw t1, 0(t0)
-
- /*
- li t0, SYS_TRIOUTCLR
- li t1, 0x00001FFF
- sw t1, 0(t0)
-
- li t0, SYS_OUTPUTCLR
- li t1, 0x00008000
- sw t1, 0(t0)
- */
- sync
-
- jr ra
- nop
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2003
- * Thomas.Lange@corelatus.se
- */
-
-#include <common.h>
-#include <command.h>
-#include <mach/au1x00.h>
-#include <asm/mipsregs.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- /* Sdram is setup by assembler code */
- /* If memory could be changed, we should return the true value here */
- gd->ram_size = 64 * 1024 * 1024;
-
- return 0;
-}
-
-#define BCSR_PCMCIA_PC0DRVEN 0x0010
-#define BCSR_PCMCIA_PC0RST 0x0080
-
-/* In arch/mips/cpu/cpu.c */
-void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
-
-int checkboard (void)
-{
-#if defined(CONFIG_IDE_PCMCIA) && 0
- u16 status;
-#endif
- /* volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); */
- volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
- u32 proc_id;
-
- *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
-
- proc_id = read_c0_prid();
-
- switch (proc_id >> 24) {
- case 0:
- puts ("Board: Pb1000\n");
- printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
- (proc_id >> 8) & 0xFF, proc_id & 0xFF);
- break;
- case 1:
- puts ("Board: Pb1500\n");
- printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
- (proc_id >> 8) & 0xFF, proc_id & 0xFF);
- break;
- case 2:
- puts ("Board: Pb1100\n");
- printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
- (proc_id >> 8) & 0xFF, proc_id & 0xFF);
- break;
- default:
- printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
- }
-
- set_io_port_base(0);
-
-#if defined(CONFIG_IDE_PCMCIA) && 0
- /* Enable 3.3 V on slot 0 ( VCC )
- No 5V */
- status = 4;
- *pcmcia_bcsr = status;
-
- status |= BCSR_PCMCIA_PC0DRVEN;
- *pcmcia_bcsr = status;
- au_sync();
-
- udelay(300*1000);
-
- status |= BCSR_PCMCIA_PC0RST;
- *pcmcia_bcsr = status;
- au_sync();
-
- udelay(100*1000);
-
- /* PCMCIA is on a 36 bit physical address.
- We need to map it into a 32 bit addresses */
-
-#if 0
- /* We dont need theese unless we run whole pcmcia package */
- write_one_tlb(20, /* index */
- 0x01ffe000, /* Pagemask, 16 MB pages */
- CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
- 0x3C000017, /* Lo0 */
- 0x3C200017); /* Lo1 */
-
- write_one_tlb(21, /* index */
- 0x01ffe000, /* Pagemask, 16 MB pages */
- CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
- 0x3D000017, /* Lo0 */
- 0x3D200017); /* Lo1 */
-#endif /* 0 */
- write_one_tlb(22, /* index */
- 0x01ffe000, /* Pagemask, 16 MB pages */
- CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */
- 0x3E000017, /* Lo0 */
- 0x3E200017); /* Lo1 */
-#endif /* CONFIG_IDE_PCMCIA */
-
- return 0;
-}
#include <usb.h>
#include <asm/gpio.h>
#include <fdt_support.h>
+#include <asm/arch/dram.h>
DECLARE_GLOBAL_DATA_PTR;
fix[i].property, mac, ARP_HLEN, 1);
}
+ msm_fixup_memory(blob);
+
return 0;
}
#### Routine: autoboot - choose proper boot path
setenv autoboot "
-if test -e mmc 0:${mmcbootpart} Image.itb; then
+if test -e mmc ${mmcbootdev}:${mmcbootpart} Image.itb; then
echo Found kernel image: Image.itb;
run setboot_fit;
run boot_img;
-elif test -e mmc 0:${mmcbootpart} zImage; then
+elif test -e mmc ${mmcbootdev}:${mmcbootpart} zImage; then
echo Found kernel image: zImage;
run setboot_zimg;
run boot_img;
-elif test -e mmc 0:${mmcbootpart} uImage; then
+elif test -e mmc ${mmcbootdev}:${mmcbootpart} uImage; then
echo Found kernel image: uImage;
run setboot_uimg;
run boot_img;
ODROID-XU3 BOARD
M: Jaehoon Chung <jh80.chung@samsung.com>
+M: Lukasz Majewski <lukma@denx.de>
S: Maintained
F: board/samsung/smdk5420/
F: include/configs/odroid_xu3.h
#include <common.h>
#include <cros_ec.h>
#include <dm.h>
+#include <led.h>
#include <os.h>
#include <asm/test.h>
#include <asm/u-boot-sandbox.h>
return 0;
}
+int board_init(void)
+{
+ if (IS_ENABLED(CONFIG_LED))
+ led_default_state();
+
+ return 0;
+}
+
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
+++ /dev/null
-#
-# Copyright (C) 2015 Stefan Roese <sr@denx.de>
-#
-
-# Armada 38x use version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM sdio
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
*/
#include <config.h>
#include <common.h>
+#include <led.h>
#include <asm/arch/stm32.h>
/*
/* address of boot parameters */
gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
+ if (IS_ENABLED(CONFIG_LED))
+ led_default_state();
+
return 0;
}
+++ /dev/null
-#
-# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
-#
-
-# Armada XP uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
config XILINX_MICROBLAZE0_HW_VER
string "Core version number"
- default 7.10.d
+ default "7.10.d"
endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * Procedure to generate this file (using Vivado Webpack 2018.2):
+ * + Install board files from digilent/vivado-boards repository
+ * (commit 6a45981 from 2018-06-05)
+ * + Start Vivado and create a new RTL project with the Zybo-z7-20 board
+ * + Create a block design
+ * - Add "ZYNQ7 Processing System" IP
+ * - Run "Block Automation" (Check "Apply Board Preset")
+ * - Connect ports FCLK_CLK0 and M_AXI_GP0_ACLK
+ * - Save diagram changes
+ * - Go to sources view, select the block diagram,
+ * and select "Generate Output Products"
+ * + Copy the generated "ps7_init_gpl.c" file
+ * + Perform manual editions based on existing Zynq boards
+ * and the checkpatch.pl script
+ *
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+ EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A02U),
+ EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01EC044DU),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+ EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004281AU),
+ EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+ EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U),
+ EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00027000U),
+ EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00027000U),
+ EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00026C00U),
+ EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00028800U),
+ EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000007AU),
+ EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x0000007AU),
+ EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000073U),
+ EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000F1U),
+ EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000F1U),
+ EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F0U),
+ EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000F7U),
+ EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000BAU),
+ EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000BAU),
+ EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000BCU),
+ EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000B3U),
+ EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+ EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001602U),
+ EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001302U),
+ EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001302U),
+ EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001302U),
+ EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001302U),
+ EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001302U),
+ EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001302U),
+ EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001303U),
+ EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001303U),
+ EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001303U),
+ EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001303U),
+ EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001303U),
+ EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001303U),
+ EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001304U),
+ EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001305U),
+ EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001304U),
+ EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001305U),
+ EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001304U),
+ EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001304U),
+ EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001304U),
+ EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001304U),
+ EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001305U),
+ EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001304U),
+ EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001304U),
+ EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001304U),
+ EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00001200U),
+ EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00001201U),
+ EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U),
+ EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001200U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001200U),
+ EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002F0037U),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00004000U),
+ EMIT_MASKWRITE(0xE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+ EMIT_MASKWRITE(0xE000A248, 0x003FFFFFU, 0x00004000U),
+ EMIT_MASKWRITE(0xE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKWRITE(0xE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+ int ret = -1;
+
+ ret = ps7_config(ps7_post_config_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+ int ret;
+
+ ret = ps7_config(ps7_mio_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
F: board/xilinx/zynqmp/
F: include/configs/xilinx_zynqmp*
F: configs/xilinx_zynqmp*
+F: configs/avnet_ultra96_rev1_defconfig
--- /dev/null
+zynqmp-zcu100-revC
\ No newline at end of file
help
USB mass storage support
+config CMD_AXI
+ bool "axi"
+ depends on AXI
+ help
+ Enable the command "axi" for accessing AXI (Advanced eXtensible
+ Interface) busses, a on-chip interconnect specification for managing
+ functional blocks in SoC designs, which is also often used in designs
+ involving FPGAs (e.g. communication with IP cores in Xilinx FPGAs).
endmenu
obj-$(CONFIG_CMD_DFU) += dfu.o
obj-$(CONFIG_CMD_GPT) += gpt.o
obj-$(CONFIG_CMD_ETHSW) += ethsw.o
+obj-$(CONFIG_CMD_AXI) += axi.o
# Power
obj-$(CONFIG_CMD_PMIC) += pmic.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * (C) Copyright 2017, 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <axi.h>
+#include <command.h>
+#include <console.h>
+#include <dm.h>
+
+/* Currently selected AXI bus device */
+static struct udevice *axi_cur_bus;
+/* Transmission size from last command */
+static uint dp_last_size;
+/* Address from last command */
+static uint dp_last_addr;
+/* Number of bytes to display from last command; default = 64 */
+static uint dp_last_length = 0x40;
+
+/**
+ * show_bus() - Show devices on a single AXI bus
+ * @bus: The AXI bus device to printt information for
+ */
+static void show_bus(struct udevice *bus)
+{
+ struct udevice *dev;
+
+ printf("Bus %d:\t%s", bus->req_seq, bus->name);
+ if (device_active(bus))
+ printf(" (active %d)", bus->seq);
+ printf("\n");
+ for (device_find_first_child(bus, &dev);
+ dev;
+ device_find_next_child(&dev))
+ printf(" %s\n", dev->name);
+}
+
+/**
+ * axi_set_cur_bus() - Set the currently active AXI bus
+ * @busnum: The number of the bus (i.e. its sequence number) that should be
+ * made active
+ *
+ * The operations supplied by this command operate only on the currently active
+ * bus.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+static int axi_set_cur_bus(unsigned int busnum)
+{
+ struct udevice *bus;
+ struct udevice *dummy;
+ int ret;
+
+ /* Make sure that all sequence numbers are initialized */
+ for (uclass_first_device(UCLASS_AXI, &dummy);
+ dummy;
+ uclass_next_device(&dummy))
+ ;
+
+ ret = uclass_get_device_by_seq(UCLASS_AXI, busnum, &bus);
+ if (ret) {
+ debug("%s: No bus %d\n", __func__, busnum);
+ return ret;
+ }
+ axi_cur_bus = bus;
+
+ return 0;
+}
+
+/**
+ * axi_get_cur_bus() - Retrieve the currently active AXI bus device
+ * @busp: Pointer to a struct udevice that receives the currently active bus
+ * device
+ *
+ * Return: 0 if OK, -ve on error
+ */
+static int axi_get_cur_bus(struct udevice **busp)
+{
+ if (!axi_cur_bus) {
+ puts("No AXI bus selected\n");
+ return -ENODEV;
+ }
+ *busp = axi_cur_bus;
+
+ return 0;
+}
+
+/*
+ * Command handlers
+ */
+
+static int do_axi_show_bus(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct udevice *dummy;
+
+ /* Make sure that all sequence numbers are initialized */
+ for (uclass_first_device(UCLASS_AXI, &dummy);
+ dummy;
+ uclass_next_device(&dummy))
+ ;
+
+ if (argc == 1) {
+ /* show all busses */
+ struct udevice *bus;
+
+ for (uclass_first_device(UCLASS_AXI, &bus);
+ bus;
+ uclass_next_device(&bus))
+ show_bus(bus);
+ } else {
+ int i;
+
+ /* show specific bus */
+ i = simple_strtoul(argv[1], NULL, 10);
+
+ struct udevice *bus;
+ int ret;
+
+ ret = uclass_get_device_by_seq(UCLASS_AXI, i, &bus);
+ if (ret) {
+ printf("Invalid bus %d: err=%d\n", i, ret);
+ return CMD_RET_FAILURE;
+ }
+ show_bus(bus);
+ }
+
+ return 0;
+}
+
+static int do_axi_bus_num(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int ret = 0;
+ int bus_no;
+
+ if (argc == 1) {
+ /* querying current setting */
+ struct udevice *bus;
+
+ if (!axi_get_cur_bus(&bus))
+ bus_no = bus->seq;
+ else
+ bus_no = -1;
+
+ printf("Current bus is %d\n", bus_no);
+ } else {
+ bus_no = simple_strtoul(argv[1], NULL, 10);
+ printf("Setting bus to %d\n", bus_no);
+
+ ret = axi_set_cur_bus(bus_no);
+ if (ret)
+ printf("Failure changing bus number (%d)\n", ret);
+ }
+
+ return ret ? CMD_RET_FAILURE : 0;
+}
+
+static int do_axi_md(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ /* Print that many bytes per line */
+ const uint DISP_LINE_LEN = 16;
+ u8 linebuf[DISP_LINE_LEN];
+ unsigned int k;
+ ulong addr, length, size;
+ ulong nbytes;
+ enum axi_size_t axisize;
+ int unitsize;
+
+ /*
+ * We use the last specified parameters, unless new ones are
+ * entered.
+ */
+ size = dp_last_size;
+ addr = dp_last_addr;
+ length = dp_last_length;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ if (!axi_cur_bus) {
+ puts("No AXI bus selected\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if ((flag & CMD_FLAG_REPEAT) == 0) {
+ size = simple_strtoul(argv[1], NULL, 10);
+
+ /*
+ * Address is specified since argc >= 3
+ */
+ addr = simple_strtoul(argv[2], NULL, 16);
+
+ /*
+ * If there's another parameter, it is the length to display;
+ * length is the number of objects, not number of bytes
+ */
+ if (argc > 3)
+ length = simple_strtoul(argv[3], NULL, 16);
+ }
+
+ switch (size) {
+ case 8:
+ axisize = AXI_SIZE_8;
+ unitsize = 1;
+ break;
+ case 16:
+ axisize = AXI_SIZE_16;
+ unitsize = 2;
+ break;
+ case 32:
+ axisize = AXI_SIZE_32;
+ unitsize = 4;
+ break;
+ default:
+ printf("Unknown read size '%lu'\n", size);
+ return CMD_RET_USAGE;
+ };
+
+ nbytes = length * unitsize;
+ do {
+ ulong linebytes = (nbytes > DISP_LINE_LEN) ?
+ DISP_LINE_LEN : nbytes;
+
+ for (k = 0; k < linebytes / unitsize; ++k) {
+ int ret = axi_read(axi_cur_bus, addr + k * unitsize,
+ linebuf + k * unitsize, axisize);
+
+ if (!ret) /* Continue if axi_read was successful */
+ continue;
+
+ if (ret == -ENOSYS)
+ printf("axi_read failed; read size not supported?\n");
+ else
+ printf("axi_read failed: err = %d\n", ret);
+
+ return CMD_RET_FAILURE;
+ }
+ print_buffer(addr, (void *)linebuf, unitsize,
+ linebytes / unitsize,
+ DISP_LINE_LEN / unitsize);
+
+ nbytes -= max(linebytes, 1UL);
+ addr += linebytes;
+
+ if (ctrlc())
+ break;
+ } while (nbytes > 0);
+
+ dp_last_size = size;
+ dp_last_addr = addr;
+ dp_last_length = length;
+
+ return 0;
+}
+
+static int do_axi_mw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u32 writeval;
+ ulong addr, count, size;
+ enum axi_size_t axisize;
+
+ if (argc <= 3 || argc >= 6)
+ return CMD_RET_USAGE;
+
+ size = simple_strtoul(argv[1], NULL, 10);
+
+ switch (size) {
+ case 8:
+ axisize = AXI_SIZE_8;
+ break;
+ case 16:
+ axisize = AXI_SIZE_16;
+ break;
+ case 32:
+ axisize = AXI_SIZE_32;
+ break;
+ default:
+ printf("Unknown write size '%lu'\n", size);
+ return CMD_RET_USAGE;
+ };
+
+ /* Address is specified since argc > 4 */
+ addr = simple_strtoul(argv[2], NULL, 16);
+
+ /* Get the value to write */
+ writeval = simple_strtoul(argv[3], NULL, 16);
+
+ /* Count ? */
+ if (argc == 5)
+ count = simple_strtoul(argv[4], NULL, 16);
+ else
+ count = 1;
+
+ while (count-- > 0) {
+ int ret = axi_write(axi_cur_bus, addr + count * sizeof(u32),
+ &writeval, axisize);
+
+ if (ret) {
+ printf("axi_write failed: err = %d\n", ret);
+ return CMD_RET_FAILURE;
+ }
+ }
+
+ return 0;
+}
+
+static cmd_tbl_t cmd_axi_sub[] = {
+ U_BOOT_CMD_MKENT(bus, 1, 1, do_axi_show_bus, "", ""),
+ U_BOOT_CMD_MKENT(dev, 1, 1, do_axi_bus_num, "", ""),
+ U_BOOT_CMD_MKENT(md, 4, 1, do_axi_md, "", ""),
+ U_BOOT_CMD_MKENT(mw, 5, 1, do_axi_mw, "", ""),
+};
+
+static int do_ihs_axi(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ cmd_tbl_t *c;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ /* Strip off leading 'axi' command argument */
+ argc--;
+ argv++;
+
+ /* Hand off rest of command line to sub-commands */
+ c = find_cmd_tbl(argv[0], &cmd_axi_sub[0], ARRAY_SIZE(cmd_axi_sub));
+
+ if (c)
+ return c->cmd(cmdtp, flag, argc, argv);
+ else
+ return CMD_RET_USAGE;
+}
+
+static char axi_help_text[] =
+ "bus - show AXI bus info\n"
+ "axi dev [bus] - show or set current AXI bus to bus number [bus]\n"
+ "axi md size addr [# of objects] - read from AXI device at address [addr] and data width [size] (one of 8, 16, 32)\n"
+ "axi mw size addr value [count] - write data [value] to AXI device at address [addr] and data width [size] (one of 8, 16, 32)\n";
+
+U_BOOT_CMD(axi, 7, 1, do_ihs_axi,
+ "AXI sub-system",
+ axi_help_text
+);
++phdr;
}
+ if (ehdr->e_machine == EM_PPC64 && (ehdr->e_flags &
+ EF_PPC64_ELFV1_ABI)) {
+ /*
+ * For the 64-bit PowerPC ELF V1 ABI, e_entry is a function
+ * descriptor pointer with the first double word being the
+ * address of the entry point of the function.
+ */
+ uintptr_t addr = ehdr->e_entry;
+
+ return *(Elf64_Addr *)addr;
+ }
+
+ return ehdr->e_entry;
+}
+
+static unsigned long load_elf64_image_shdr(unsigned long addr)
+{
+ Elf64_Ehdr *ehdr; /* Elf header structure pointer */
+ Elf64_Shdr *shdr; /* Section header structure pointer */
+ unsigned char *strtab = 0; /* String table pointer */
+ unsigned char *image; /* Binary image pointer */
+ int i; /* Loop counter */
+
+ ehdr = (Elf64_Ehdr *)addr;
+
+ /* Find the section header string table for output info */
+ shdr = (Elf64_Shdr *)(addr + (ulong)ehdr->e_shoff +
+ (ehdr->e_shstrndx * sizeof(Elf64_Shdr)));
+
+ if (shdr->sh_type == SHT_STRTAB)
+ strtab = (unsigned char *)(addr + (ulong)shdr->sh_offset);
+
+ /* Load each appropriate section */
+ for (i = 0; i < ehdr->e_shnum; ++i) {
+ shdr = (Elf64_Shdr *)(addr + (ulong)ehdr->e_shoff +
+ (i * sizeof(Elf64_Shdr)));
+
+ if (!(shdr->sh_flags & SHF_ALLOC) ||
+ shdr->sh_addr == 0 || shdr->sh_size == 0) {
+ continue;
+ }
+
+ if (strtab) {
+ debug("%sing %s @ 0x%08lx (%ld bytes)\n",
+ (shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load",
+ &strtab[shdr->sh_name],
+ (unsigned long)shdr->sh_addr,
+ (long)shdr->sh_size);
+ }
+
+ if (shdr->sh_type == SHT_NOBITS) {
+ memset((void *)(uintptr_t)shdr->sh_addr, 0,
+ shdr->sh_size);
+ } else {
+ image = (unsigned char *)addr + (ulong)shdr->sh_offset;
+ memcpy((void *)(uintptr_t)shdr->sh_addr,
+ (const void *)image, shdr->sh_size);
+ }
+ flush_cache((ulong)shdr->sh_addr, shdr->sh_size);
+ }
+
+ if (ehdr->e_machine == EM_PPC64 && (ehdr->e_flags &
+ EF_PPC64_ELFV1_ABI)) {
+ /*
+ * For the 64-bit PowerPC ELF V1 ABI, e_entry is a function
+ * descriptor pointer with the first double word being the
+ * address of the entry point of the function.
+ */
+ uintptr_t addr = ehdr->e_entry;
+
+ return *(Elf64_Addr *)addr;
+ }
+
return ehdr->e_entry;
}
int i; /* Loop counter */
ehdr = (Elf32_Ehdr *)addr;
+ if (ehdr->e_ident[EI_CLASS] == ELFCLASS64)
+ return load_elf64_image_shdr(addr);
/* Find the section header string table for output info */
shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff +
/* If the user has not yet run `sata init`, do it now */
if (sata_curr_device == -1) {
rc = sata_probe(0);
- if (rc < 0)
- return CMD_RET_FAILURE;
+ if (rc)
+ return rc;
sata_curr_device = 0;
}
#ifdef CONFIG_DM
initr_dm,
#endif
-#if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || defined(CONFIG_RISCV)
+#if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || defined(CONFIG_RISCV) || \
+ defined(CONFIG_SANDBOX)
board_init, /* Setup chipselects */
#endif
/*
unsigned int r1;
};
-int fdt_del_subnodes(const void *blob, int parent_offset)
+static int fdt_del_subnodes(const void *blob, int parent_offset)
{
int off, ndepth;
int ret;
return 0;
}
-int fdt_del_partitions(void *blob, int parent_offset)
+static int fdt_del_partitions(void *blob, int parent_offset)
{
const void *prop;
int ndepth = 0;
CONFIG_DRAM_CLK=576
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
+CONFIG_MACPWR="PA17"
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
CONFIG_SCSI_AHCI=y
+CONFIG_RGMII=y
+CONFIG_SUN8I_EMAC=y
CONFIG_AXP_DLDO4_VOLT=2500
-CONFIG_AXP_ALDO2_VOLT=2500
CONFIG_AXP_ELDO3_VOLT=1200
CONFIG_SCSI=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
-CONFIG_SUN8I_EMAC=y
-CONFIG_RGMII=y
-CONFIG_MACPWR="PA17"
CONFIG_MV88E61XX_CPU_PORT=10
CONFIG_MV88E61XX_PHY_PORTS=0x003
CONFIG_MV88E61XX_FIXED_PORTS=0x300
+CONFIG_DM_RTC=y
+CONFIG_RTC_MV=y
CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
+CONFIG_SYS_TEXT_BASE=0x00600000
+CONFIG_TARGET_SBx81LIFXCAT=y
+CONFIG_IDENT_STRING="\nSBx81LIFXCAT"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-atl-sbx81lifxcat"
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SILENT_U_BOOT_ONLY=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_NTPSERVER=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+# CONFIG_CMD_LED is not set
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+# CONFIG_MMC is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_MV88E61XX_SWITCH=y
+CONFIG_MV88E61XX_CPU_PORT=10
+CONFIG_MV88E61XX_PHY_PORTS=0x003
+CONFIG_MV88E61XX_FIXED_PORTS=0x300
+CONFIG_SPI=y
+CONFIG_KIRKWOOD_SPI=y
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
-CONFIG_NAND_ATMEL=y
CONFIG_MTD_PARTITIONS=y
+CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu100"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff010000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000
+CONFIG_ZYNQMP_USB=y
+CONFIG_DEFAULT_DEVICE_TREE="avnet-ultra96-rev1"
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_MP=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_XILINX_GPIO=y
+CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C1=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ZYNQ_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_WDT=y
+CONFIG_WDT_CDNS=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_ARM=y
CONFIG_ARCH_BCMSTB=y
+CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TARGET_BCM7445=y
-CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_PRIOR_STAGE=y
-CONFIG_DM=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI=y
-CONFIG_SPI_FLASH=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_BCMSTB_SPI=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
-CONFIG_RSA=y
-CONFIG_BLK=n
-CONFIG_SDHCI=y
+CONFIG_BOOTDELAY=1
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot>"
+CONFIG_OF_PRIOR_STAGE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCMSTB=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
CONFIG_CONS_INDEX=3
-CONFIG_BOOTDELAY=1
-CONFIG_SYS_PROMPT="U-Boot>"
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_SYS_NS16550_COM3=0xf040ab00
-CONFIG_EFI_LOADER=n
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_BCMSTB_SPI=y
+# CONFIG_EFI_LOADER is not set
--- /dev/null
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x80010000
+CONFIG_ARCH_BMIPS=y
+CONFIG_SOC_BMIPS_BCM6838=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="brcm,bcm968380gerg"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="bcm968380gerg # "
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
+# CONFIG_NET is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_HAVE_BLOCK_DEVICE=y
+CONFIG_DM_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_BCM6328=y
+CONFIG_LED_BLINK=y
+CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY=y
+CONFIG_BCM6368_USBH_PHY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_BCM6328_POWER_DOMAIN=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_BCM6345=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_DM_SERIAL=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_LZO=y
CONFIG_TARGET_BRPPT1=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-mmc"
CONFIG_TPL_SYS_MALLOC_F_LEN=0x0
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_I2C_SUPPORT=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_MTD_DEVICE=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
CONFIG_ARCH_OWL=y
-CONFIG_TARGET_BUBBLEGUM_96=y
CONFIG_SYS_TEXT_BASE=0x11000000
+CONFIG_TARGET_BUBBLEGUM_96=y
CONFIG_IDENT_STRING="\nBubblegum-96"
CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
-CONFIG_ARM_SMCCC=y
CONFIG_BOOTARGS="console=ttyOWL5,115200n8"
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_PROMPT="U-Boot => "
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="U-Boot => "
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_CACHE=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_CLEARFOG=y
+CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_CLK_AT91=y
CONFIG_DFU_NAND=y
# CONFIG_MMC is not set
+CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_PHYLIB=y
CONFIG_ATMEL_USART=y
CONFIG_USB=y
+++ /dev/null
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0xBFC00000
-CONFIG_TARGET_DBAU1X00=y
-CONFIG_SYS_EXTRA_OPTIONS="DBAU1000"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="DbAu1xx0 # "
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_RUN is not set
-CONFIG_CMD_IMLS=y
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_MAC_PARTITION=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_MTD_NOR_FLASH=y
+++ /dev/null
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0xBFC00000
-CONFIG_TARGET_DBAU1X00=y
-CONFIG_DBAU1100=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="DbAu1xx0 # "
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_RUN is not set
-CONFIG_CMD_IMLS=y
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_MAC_PARTITION=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_MTD_NOR_FLASH=y
+++ /dev/null
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0xBFC00000
-CONFIG_TARGET_DBAU1X00=y
-CONFIG_DBAU1500=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="DbAu1xx0 # "
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_RUN is not set
-CONFIG_CMD_IMLS=y
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_MAC_PARTITION=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_MTD_NOR_FLASH=y
+++ /dev/null
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0xBFC00000
-CONFIG_TARGET_DBAU1X00=y
-CONFIG_DBAU1550=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="DbAu1xx0 # "
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_RUN is not set
-CONFIG_CMD_IMLS=y
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_ISO_PARTITION is not set
-CONFIG_MTD_NOR_FLASH=y
+++ /dev/null
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0xBFC00000
-CONFIG_TARGET_DBAU1X00=y
-CONFIG_DBAU1550=y
-CONFIG_SYS_LITTLE_ENDIAN=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="DbAu1xx0 # "
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_RUN is not set
-CONFIG_CMD_IMLS=y
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_ISO_PARTITION is not set
-CONFIG_MTD_NOR_FLASH=y
CONFIG_TARGET_DNS325=y
CONFIG_IDENT_STRING="\nD-Link DNS-325"
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dns325"
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_NETDEVICES=y
CONFIG_MVGBE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_TARGET_DREAMPLUG=y
CONFIG_IDENT_STRING="\nMarvell-DreamPlug"
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dreamplug"
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_NETDEVICES=y
CONFIG_MVGBE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DS109=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ds109"
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
CONFIG_MVSATA_IDE=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_MVGBE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_TARGET_GOFLEXHOME=y
CONFIG_IDENT_STRING="\nSeagate GoFlex Home"
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-goflexnet"
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_NETDEVICES=y
CONFIG_MVGBE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_TARGET_GURUPLUG=y
CONFIG_IDENT_STRING="\nMarvell-GuruPlug"
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-guruplug-server-plus"
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_NETDEVICES=y
CONFIG_MVGBE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_HELIOS4=y
+CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-helios4"
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_NAND_DAVINCI=y
-CONFIG_MTD_DEVICE=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_NAND_DAVINCI=y
-CONFIG_MTD_DEVICE=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
-CONFIG_ADC=y
-CONFIG_SARADC_MESON=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SARADC_MESON=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
-CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_MESON=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb"
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
-CONFIG_BLK=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_DM_SCSI=y
-CONFIG_SATA_CEVA=y
-CONFIG_SCSI=y
-CONFIG_AHCI=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
-CONFIG_BLK=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_DM_SCSI=y
-CONFIG_SATA_CEVA=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SCSI=y
-CONFIG_AHCI=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
-CONFIG_BLK=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_DM_SCSI=y
-CONFIG_SATA_CEVA=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SCSI=y
-CONFIG_AHCI=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
-CONFIG_BLK=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_DM_SCSI=y
-CONFIG_SATA_CEVA=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SCSI=y
-CONFIG_AHCI=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_SPL_CRYPTO_SUPPORT=y
+CONFIG_SPL_HASH_SUPPORT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_CRYPTO_SUPPORT=y
-CONFIG_SPL_HASH_SUPPORT=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_PHYLIB=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
-# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_RESET=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXBB=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_TARGET_NAS220=y
CONFIG_IDENT_STRING="\nNAS 220"
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-blackarmor-nas220"
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_NETDEVICES=y
CONFIG_MVGBE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_ADC=y
CONFIG_ADC_EXYNOS=y
CONFIG_DFU_MMC=y
+CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_S5P=y
CONFIG_NETDEVICES=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x5000000
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_OMAP3_LOGIC=y
+# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x08000000
CONFIG_SMC911X_32_BIT=y
-CONFIG_CONS_INDEX=3
+CONFIG_CONS_INDEX=1
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
CONFIG_MACH_SUN50I_H6=y
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC0_CD_PIN="PF6"
# CONFIG_PSCI_RESET is not set
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-one-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+++ /dev/null
-CONFIG_MIPS=y
-CONFIG_TARGET_PB1X00=y
-CONFIG_SYS_EXTRA_OPTIONS="PB1000"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="Pb1x00 # "
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_RUN is not set
-CONFIG_CMD_IMLS=y
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_MTD_NOR_FLASH=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
-CONFIG_MTD_DEVICE=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
CONFIG_MACH_SUN50I_H6=y
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC0_CD_PIN="PF6"
# CONFIG_PSCI_RESET is not set
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_LOG=y
CONFIG_MAC_PARTITION=y
CONFIG_AMIGA_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_SANDBOX_RESET=y
CONFIG_DM_RTC=y
CONFIG_SANDBOX_SERIAL=y
+CONFIG_SMEM=y
+CONFIG_SANDBOX_SMEM=y
CONFIG_SOUND=y
CONFIG_SOUND_SANDBOX=y
CONFIG_SANDBOX_SPI=y
CONFIG_TIMER=y
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y
-CONFIG_TPM_TIS_SANDBOX=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EMUL=y
CONFIG_UT_DM=y
CONFIG_UT_ENV=y
CONFIG_UT_OVERLAY=y
-CONFIG_SMEM=y
-CONFIG_SANDBOX_SMEM=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_AXI=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TFTPSRV=y
CONFIG_CMD_RARP=y
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_LOG=y
CONFIG_MAC_PARTITION=y
CONFIG_AMIGA_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_DEBUG_DEVRES=y
CONFIG_ADC=y
CONFIG_ADC_SANDBOX=y
+CONFIG_AXI=y
+CONFIG_AXI_SANDBOX=y
CONFIG_CLK=y
CONFIG_CPU=y
CONFIG_DM_DEMO=y
CONFIG_SANDBOX_RESET=y
CONFIG_DM_RTC=y
CONFIG_SANDBOX_SERIAL=y
+CONFIG_SMEM=y
+CONFIG_SANDBOX_SMEM=y
CONFIG_SOUND=y
CONFIG_SOUND_SANDBOX=y
CONFIG_SANDBOX_SPI=y
CONFIG_TIMER=y
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y
-CONFIG_TPM_TIS_SANDBOX=y
-CONFIG_TPM2_TIS_SANDBOX=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EMUL=y
CONFIG_FS_CRAMFS=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
-CONFIG_TPM_V1=y
-CONFIG_TPM_V2=y
CONFIG_LZ4=y
CONFIG_ERRNO_STR=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_UT_DM=y
CONFIG_UT_ENV=y
CONFIG_UT_OVERLAY=y
-CONFIG_SMEM=y
-CONFIG_SANDBOX_SMEM=y
CONFIG_TIMER=y
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y
-CONFIG_TPM_TIS_SANDBOX=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EMUL=y
CONFIG_TIMER=y
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y
-CONFIG_TPM_TIS_SANDBOX=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EMUL=y
CONFIG_TIMER=y
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y
-CONFIG_TPM_TIS_SANDBOX=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EMUL=y
CONFIG_TARGET_SHEEVAPLUG=y
CONFIG_IDENT_STRING="\nMarvell-Sheevaplug"
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-sheevaplug"
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_MVSATA_IDE=y
CONFIG_NETDEVICES=y
CONFIG_MVGBE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CLK_AT91=y
CONFIG_DFU_NAND=y
# CONFIG_MMC is not set
+CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_PHYLIB=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_STM32_ADC=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_STM32F7=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
CONFIG_DM_MMC=y
CONFIG_STM32_SDMMC2=y
# CONFIG_PINCTRL_FULL is not set
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_STPMU1=y
-CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_REGULATOR_STM32_VREFBUF=y
# CONFIG_NET is not set
CONFIG_MTD_DEVICE=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_SPI=y
CONFIG_CF_SPI=y
CONFIG_CLK_AT91=y
CONFIG_DFU_NAND=y
# CONFIG_MMC is not set
+CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_LOGLEVEL=6
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_CONFIG=y
-CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=uniphier-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=uniphier-nand.0:1m(firmware),-(UBI)"
CONFIG_LOGLEVEL=6
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_CONFIG=y
-CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=uniphier-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=uniphier-nand.0:1m(firmware),-(UBI)"
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_LOGLEVEL=6
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_CONFIG=y
CONFIG_CMD_IMLS=y
# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_MTDIDS_DEFAULT="nand0=uniphier-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=uniphier-nand.0:1m(firmware),-(UBI)"
CONFIG_CMD_UBI=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
-# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_ENV_IS_IN_NAND=y
-CONFIG_NAND=y
-CONFIG_NAND_ATMEL=y
CONFIG_MTD_DEVICE=y
CONFIG_MTD_PARTITIONS=y
+CONFIG_NAND=y
+CONFIG_NAND_ATMEL=y
CONFIG_LZMA=y
CONFIG_OF_LIBFDT=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
+CONFIG_XILINX_GPIO=y
CONFIG_SYS_I2C_ZYNQ=y
CONFIG_ZYNQ_I2C1=y
CONFIG_LED=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_CMD_PCA953X=y
+CONFIG_XILINX_GPIO=y
CONFIG_SYS_I2C_ZYNQ=y
CONFIG_ZYNQ_I2C0=y
CONFIG_ZYNQ_I2C1=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_CMD_PCA953X=y
+CONFIG_XILINX_GPIO=y
CONFIG_SYS_I2C_ZYNQ=y
CONFIG_ZYNQ_I2C0=y
CONFIG_ZYNQ_I2C1=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_CMD_PCA953X=y
+CONFIG_XILINX_GPIO=y
CONFIG_SYS_I2C_ZYNQ=y
CONFIG_ZYNQ_I2C0=y
CONFIG_ZYNQ_I2C1=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_ENV_SIZE=0x190
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x200000
+CONFIG_SYS_MALLOC_LEN=0x1000
CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_ENV_SIZE=0x190
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x200000
+CONFIG_SYS_MALLOC_LEN=0x1000
CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor"
CONFIG_BOOTDELAY=-1
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_CLOCK=0
CONFIG_SPL_STACK_R_ADDR=0x200000
# CONFIG_ZYNQ_DDRC_INIT is not set
+CONFIG_SYS_MALLOC_LEN=0x1000
# CONFIG_CMD_ZYNQ is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single"
CONFIG_DEBUG_UART=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo-z7"
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_DM_GPIO=y
+CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C0=y
+CONFIG_ZYNQ_I2C1=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_REALTEK=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_THOR=y
*dev_desc = get_dev_hwpart(ifname, dev, hwpart);
if (!(*dev_desc) || ((*dev_desc)->type == DEV_TYPE_UNKNOWN)) {
- printf("** Bad device %s %s **\n", ifname, dev_hwpart_str);
+ debug("** Bad device %s %s **\n", ifname, dev_hwpart_str);
dev = -ENOENT;
goto cleanup;
}
-# iSCSI booting with U-Boot and iPXE
+iSCSI booting with U-Boot and iPXE
+==================================
-## Motivation
+Motivation
+----------
U-Boot has only a reduced set of supported network protocols. The focus for
network booting has been on UDP based protocols. A TCP stack and HTTP support
same target where the operating system is installed.
An alternative to implementing these protocols in U-Boot is to use an existing
-software that can run on top of U-Boot. iPXE is the "swiss army knife" of
+software that can run on top of U-Boot. iPXE[1] is the "swiss army knife" of
network booting. It supports both HTTPS and iSCSI. It has a scripting engine for
fine grained control of the boot process and can provide a command shell.
iPXE can be built as an EFI application (named snp.efi) which can be loaded and
run by U-Boot.
-## Boot sequence
+Boot sequence
+-------------
U-Boot loads the EFI application iPXE snp.efi using the bootefi command. This
application has network access via the simple network protocol offered by
uses the ConnectController boot service of U-Boot to request U-Boot to connect a
file system driver. U-Boot reads from the iSCSI drive via the block IO protocol
offered by iPXE. It creates the partition handles and installs the simple file
-protocol. Now iPXE can call the simple file protocol to load Grub. U-Boot uses
-the block IO protocol offered by iPXE to fulfill the request.
-
-Once Grub is started it uses the same block IO protocol to load Linux. Via
-the EFI stub Linux is called as an EFI application.
-
-```
- +--------+ +--------+
- | | Runs | |
- | U-Boot |=========>| iPXE |
- | EFI | | snp.efi|
-+--------+ | | DHCP | |
-| |<====|********|<=========| |
-| DHCP | | | Get IP | |
-| Server | | | Address | |
-| |====>|********|=========>| |
-+--------+ | | Response | |
- | | | |
- | | | |
-+--------+ | | HTTPS | |
-| |<====|********|<=========| |
-| HTTPS | | | Load | |
-| Server | | | Script | |
-| |====>|********|=========>| |
-+--------+ | | | |
- | | | |
- | | | |
-+--------+ | | iSCSI | |
-| |<====|********|<=========| |
-| iSCSI | | | Auth | |
-| Server |====>|********|=========>| |
-| | | | | |
-| | | | Loads | |
-| |<====|********|<=========| | +--------+
-| | | | Grub | | Runs | |
-| |====>|********|=========>| |=======>| Grub |
-| | | | | | | |
-| | | | | | | |
-| | | | | | Loads | |
-| |<====|********|<=========|********|<=======| | +--------+
-| | | | | | Linux | | Runs | |
-| |====>|********|=========>|********|=======>| |=====>| Linux |
-| | | | | | | | | |
-+--------+ +--------+ +--------+ +--------+ | |
- | |
- | |
- | ~ ~ ~ ~|
-```
-
-## Security
+protocol. Now iPXE can call the simple file protocol to load GRUB[2]. U-Boot
+uses the block IO protocol offered by iPXE to fulfill the request.
+
+Once GRUB is started it uses the same block IO protocol to load Linux. Via
+the EFI stub Linux is called as an EFI application::
+
+ +--------+ +--------+
+ | | Runs | |
+ | U-Boot |========>| iPXE |
+ | EFI | | snp.efi|
+ +--------+ | | DHCP | |
+ | |<===|********|<========| |
+ | DHCP | | | Get IP | |
+ | Server | | | Address | |
+ | |===>|********|========>| |
+ +--------+ | | Response| |
+ | | | |
+ | | | |
+ +--------+ | | HTTPS | |
+ | |<===|********|<========| |
+ | HTTPS | | | Load | |
+ | Server | | | Script | |
+ | |===>|********|========>| |
+ +--------+ | | | |
+ | | | |
+ | | | |
+ +--------+ | | iSCSI | |
+ | |<===|********|<========| |
+ | iSCSI | | | Auth | |
+ | Server |===>|********|========>| |
+ | | | | | |
+ | | | | Loads | |
+ | |<===|********|<========| | +--------+
+ | | | | GRUB | | Runs | |
+ | |===>|********|========>| |======>| GRUB |
+ | | | | | | | |
+ | | | | | | | |
+ | | | | | | Loads | |
+ | |<===|********|<========|********|<======| | +--------+
+ | | | | | | Linux | | Runs | |
+ | |===>|********|========>|********|======>| |=====>| Linux |
+ | | | | | | | | | |
+ +--------+ +--------+ +--------+ +--------+ | |
+ | |
+ | |
+ | ~ ~ ~ ~|
+
+Security
+--------
The iSCSI protocol is not encrypted. The traffic could be secured using IPsec
but neither U-Boot nor iPXE does support this. So we should at least separate
the iSCSI traffic from all other network traffic. This can be achieved using a
virtual local area network (VLAN).
-## Configuration
+Configuration
+-------------
-### iPXE
+iPXE
+^^^^
-For running iPXE on arm64 the bin-arm64-efi/snp.efi build target is needed.
+For running iPXE on arm64 the bin-arm64-efi/snp.efi build target is needed::
git clone http://git.ipxe.org/ipxe.git
cd ipxe/src
iPXE by default will put the CPU to rest when waiting for input. U-Boot does
not wake it up due to missing interrupt support. To avoid this behavior create
-file src/config/local/nap.h.
+file src/config/local/nap.h::
/* nap.h */
#undef NAP_EFIX86
#define NAP_NULL
The supported commands in iPXE are controlled by an include, too. Putting the
-following into src/config/local/general.h is sufficient for most use cases.
+following into src/config/local/general.h is sufficient for most use cases::
/* general.h */
#define NSLOOKUP_CMD /* Name resolution command */
#define DOWNLOAD_PROTO_NFS /* Network File System Protocol */
#define DOWNLOAD_PROTO_FILE /* Local file system access */
-## Links
+Links
+-----
-* https://ipxe.org - iPXE open source boot firmware
-* https://www.gnu.org/software/grub/ - GNU Grub (Grand Unified Bootloader)
+* [1](https://ipxe.org) https://ipxe.org - iPXE open source boot firmware
+* [2](https://www.gnu.org/software/grub/) https://www.gnu.org/software/grub/ -
+ GNU GRUB (Grand Unified Bootloader)
sudo rkdeveloptool wl 64 <U-Boot binary>
-There are plenty of Rockusb command. but wl(write lba) and
-rd(reboot) command. These two command can let people flash
-image to device.
+Current set of rkdeveloptool commands supported:
+- rci: Read Chip Info
+- rfi: Read Flash Id
+- rd : Reset Device
+- td : Test Device Ready
+- rl : Read blocks using LBA
+- wl : Write blocks using LBA
+- wlx: Write partition
To do
-----
When accesses go to the pci@1f,0 device they are forwarded to its child, the
emulator.
+
+The sandbox PCI drivers also support dynamic driver binding, allowing device
+driver to declare the driver binding information via U_BOOT_PCI_DEVICE(),
+eliminating the need to provide any device tree node under the host controller
+node. It is required a "sandbox,dev-info" property must be provided in the
+host controller node for this functionality to work.
+
+ pci1: pci-controller1 {
+ compatible = "sandbox,pci";
+ ...
+ sandbox,dev-info = <0x08 0x00 0x1234 0x5678
+ 0x0c 0x00 0x1234 0x5678>;
+ };
+
+The "sandbox,dev-info" property specifies all dynamic PCI devices on this bus.
+Each dynamic PCI device is encoded as 4 cells a group. The first and second
+cells are PCI device number and function number respectively. The third and
+fourth cells are PCI vendor ID and device ID respectively.
+
+When this bus is scanned we will end up with something like this:
+
+ pci [ + ] pci_sandbo |-- pci-controller1
+ pci_emul [ ] sandbox_sw | |-- sandbox_swap_case_emul
+ pci_emul [ ] sandbox_sw | `-- sandbox_swap_case_emul
+
+Note the difference from the statically declared device nodes is that the
+device is directly attached to the host controller, instead of via a container
+device like pci@1f,0.
- data : Path to the external file which contains this node's binary data.
- compression : Compression used by included data. Supported compressions
are "gzip" and "bzip2". If no compression is used compression property
- should be set to "none".
+ should be set to "none". If the data is compressed but it should not be
+ uncompressed by U-Boot (e.g. compressed ramdisk), this should also be set
+ to "none".
Conditionally mandatory property:
- os : OS name, mandatory for types "kernel" and "ramdisk". Valid OS names
source "drivers/ata/Kconfig"
+source "drivers/axi/Kconfig"
+
source "drivers/block/Kconfig"
source "drivers/bootcount/Kconfig"
obj-y += soc/
obj-$(CONFIG_REMOTEPROC) += remoteproc/
obj-y += thermal/
+obj-y += axi/
obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
endif
--- /dev/null
+menuconfig AXI
+ bool "AXI bus drivers"
+ help
+ Support AXI (Advanced eXtensible Interface) busses, a on-chip
+ interconnect specification for managing functional blocks in SoC
+ designs, which is also often used in designs involving FPGAs (e.g.
+ communication with IP cores in Xilinx FPGAs).
+
+ These types of busses expose a virtual address space that can be
+ accessed using different address widths (8, 16, and 32 are supported
+ for now).
+
+ Other similar bus architectures may be compatible as well.
+
+if AXI
+
+config IHS_AXI
+ bool "Enable IHS AXI driver"
+ depends on DM
+ help
+ Support for gdsys Integrated Hardware Systems Advanced eXtensible
+ Interface (IHS AXI) bus on a gdsys IHS FPGA used to communicate with
+ IP cores in the FPGA (e.g. video transmitter cores).
+
+config AXI_SANDBOX
+ bool "Enable AXI sandbox driver"
+ depends on DM
+ help
+ Support AXI (Advanced eXtensible Interface) emulation for the sandbox
+ environment.
+
+endif
--- /dev/null
+#
+# (C) Copyright 2017
+# Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_AXI) += axi-uclass.o
+obj-$(CONFIG_IHS_AXI) += ihs_axi.o
+obj-$(CONFIG_SANDBOX) += axi-emul-uclass.o
+obj-$(CONFIG_SANDBOX) += sandbox_store.o
+obj-$(CONFIG_AXI_SANDBOX) += axi_sandbox.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <axi.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <asm/axi.h>
+
+int axi_sandbox_get_emul(struct udevice *bus, ulong address,
+ enum axi_size_t size, struct udevice **emulp)
+{
+ struct udevice *dev;
+ u32 reg[2];
+ uint offset;
+
+ switch (size) {
+ case AXI_SIZE_8:
+ offset = 1;
+ break;
+ case AXI_SIZE_16:
+ offset = 2;
+ break;
+ case AXI_SIZE_32:
+ offset = 4;
+ break;
+ default:
+ debug("%s: Unknown AXI transfer size '%d'", bus->name, size);
+ offset = 0;
+ }
+
+ /*
+ * Note: device_find_* don't activate the devices; they're activated
+ * as-needed below.
+ */
+ for (device_find_first_child(bus, &dev);
+ dev;
+ device_find_next_child(&dev)) {
+ int ret;
+
+ ret = dev_read_u32_array(dev, "reg", reg, ARRAY_SIZE(reg));
+ if (ret) {
+ debug("%s: Could not read 'reg' property of %s\n",
+ bus->name, dev->name);
+ continue;
+ }
+
+ /*
+ * Does the transfer's address fall into this device's address
+ * space?
+ */
+ if (address >= reg[0] && address <= reg[0] + reg[1] - offset) {
+ /* If yes, activate it... */
+ if (device_probe(dev)) {
+ debug("%s: Could not activate %s\n",
+ bus->name, dev->name);
+ return -ENODEV;
+ }
+
+ /* ...and return it */
+ *emulp = dev;
+ return 0;
+ }
+ }
+
+ return -ENODEV;
+}
+
+int axi_get_store(struct udevice *dev, u8 **storep)
+{
+ struct axi_emul_ops *ops = axi_emul_get_ops(dev);
+
+ if (!ops->get_store)
+ return -ENOSYS;
+
+ return ops->get_store(dev, storep);
+}
+
+UCLASS_DRIVER(axi_emul) = {
+ .id = UCLASS_AXI_EMUL,
+ .name = "axi_emul",
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2017
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <axi.h>
+
+int axi_read(struct udevice *dev, ulong address, void *data,
+ enum axi_size_t size)
+{
+ struct axi_ops *ops = axi_get_ops(dev);
+
+ if (!ops->read)
+ return -ENOSYS;
+
+ return ops->read(dev, address, data, size);
+}
+
+int axi_write(struct udevice *dev, ulong address, void *data,
+ enum axi_size_t size)
+{
+ struct axi_ops *ops = axi_get_ops(dev);
+
+ if (!ops->write)
+ return -ENOSYS;
+
+ return ops->write(dev, address, data, size);
+}
+
+UCLASS_DRIVER(axi) = {
+ .id = UCLASS_AXI,
+ .name = "axi",
+ .post_bind = dm_scan_fdt_dev,
+ .flags = DM_UC_FLAG_SEQ_ALIAS,
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <axi.h>
+#include <dm.h>
+#include <asm/axi.h>
+
+/*
+ * This driver implements a AXI bus for the sandbox architecture for testing
+ * purposes.
+ *
+ * The bus forwards every access to it to a special AXI emulation device (which
+ * it gets via the axi_emul_get_ops function) that implements a simple
+ * read/write storage.
+ *
+ * The emulator device must still be contained in the device tree in the usual
+ * way, since configuration data for the storage is read from the DT.
+ */
+
+static int axi_sandbox_read(struct udevice *bus, ulong address, void *data,
+ enum axi_size_t size)
+{
+ struct axi_emul_ops *ops;
+ struct udevice *emul;
+ int ret;
+
+ /* Get emulator device */
+ ret = axi_sandbox_get_emul(bus, address, size, &emul);
+ if (ret)
+ return ret == -ENODEV ? 0 : ret;
+ /* Forward all reads to the AXI emulator */
+ ops = axi_emul_get_ops(emul);
+ if (!ops || !ops->read)
+ return -ENOSYS;
+
+ return ops->read(emul, address, data, size);
+}
+
+static int axi_sandbox_write(struct udevice *bus, ulong address, void *data,
+ enum axi_size_t size)
+{
+ struct axi_emul_ops *ops;
+ struct udevice *emul;
+ int ret;
+
+ /* Get emulator device */
+ ret = axi_sandbox_get_emul(bus, address, size, &emul);
+ if (ret)
+ return ret == -ENODEV ? 0 : ret;
+ /* Forward all writes to the AXI emulator */
+ ops = axi_emul_get_ops(emul);
+ if (!ops || !ops->write)
+ return -ENOSYS;
+
+ return ops->write(emul, address, data, size);
+}
+
+static const struct udevice_id axi_sandbox_ids[] = {
+ { .compatible = "sandbox,axi" },
+ { /* sentinel */ }
+};
+
+static const struct axi_ops axi_sandbox_ops = {
+ .read = axi_sandbox_read,
+ .write = axi_sandbox_write,
+};
+
+U_BOOT_DRIVER(axi_sandbox_bus) = {
+ .name = "axi_sandbox_bus",
+ .id = UCLASS_AXI,
+ .of_match = axi_sandbox_ids,
+ .ops = &axi_sandbox_ops,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * (C) Copyright 2017, 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <axi.h>
+#include <dm.h>
+#include <regmap.h>
+
+/**
+ * struct ihs_axi_regs - Structure for the register map of a IHS AXI device
+ * @interrupt_status: Status register to indicate certain events (e.g.
+ * error during transfer, transfer complete, etc.)
+ * @interrupt_enable_control: Register to both control which statuses will be
+ * indicated in the interrupt_status register, and
+ * to change bus settings
+ * @address_lsb: Least significant 16-bit word of the address of a
+ * device to transfer data from/to
+ * @address_msb: Most significant 16-bit word of the address of a
+ * device to transfer data from/to
+ * @write_data_lsb: Least significant 16-bit word of the data to be
+ * written to a device
+ * @write_data_msb: Most significant 16-bit word of the data to be
+ * written to a device
+ * @read_data_lsb: Least significant 16-bit word of the data read
+ * from a device
+ * @read_data_msb: Most significant 16-bit word of the data read
+ * from a device
+ */
+struct ihs_axi_regs {
+ u16 interrupt_status;
+ u16 interrupt_enable_control;
+ u16 address_lsb;
+ u16 address_msb;
+ u16 write_data_lsb;
+ u16 write_data_msb;
+ u16 read_data_lsb;
+ u16 read_data_msb;
+};
+
+/**
+ * ihs_axi_set() - Convenience macro to set values in register map
+ * @map: The register map to write to
+ * @member: The member of the ihs_axi_regs structure to write
+ * @val: The value to write to the register map
+ */
+#define ihs_axi_set(map, member, val) \
+ regmap_set(map, struct ihs_axi_regs, member, val)
+
+/**
+ * ihs_axi_get() - Convenience macro to read values from register map
+ * @map: The register map to read from
+ * @member: The member of the ihs_axi_regs structure to read
+ * @valp: Pointer to a buffer to receive the value read
+ */
+#define ihs_axi_get(map, member, valp) \
+ regmap_get(map, struct ihs_axi_regs, member, valp)
+
+/**
+ * struct ihs_axi_priv - Private data structure of IHS AXI devices
+ * @map: Register map for the IHS AXI device
+ */
+struct ihs_axi_priv {
+ struct regmap *map;
+};
+
+/**
+ * enum status_reg - Description of bits in the interrupt_status register
+ * @STATUS_READ_COMPLETE_EVENT: A read transfer was completed
+ * @STATUS_WRITE_COMPLETE_EVENT: A write transfer was completed
+ * @STATUS_TIMEOUT_EVENT: A timeout has occurred during the transfer
+ * @STATUS_ERROR_EVENT: A error has occurred during the transfer
+ * @STATUS_AXI_INT: A AXI interrupt has occurred
+ * @STATUS_READ_DATA_AVAILABLE: Data is available to be read
+ * @STATUS_BUSY: The bus is busy
+ * @STATUS_INIT_DONE: The bus has finished initializing
+ */
+enum status_reg {
+ STATUS_READ_COMPLETE_EVENT = BIT(15),
+ STATUS_WRITE_COMPLETE_EVENT = BIT(14),
+ STATUS_TIMEOUT_EVENT = BIT(13),
+ STATUS_ERROR_EVENT = BIT(12),
+ STATUS_AXI_INT = BIT(11),
+ STATUS_READ_DATA_AVAILABLE = BIT(7),
+ STATUS_BUSY = BIT(6),
+ STATUS_INIT_DONE = BIT(5),
+};
+
+/**
+ * enum control_reg - Description of bit fields in the interrupt_enable_control
+ * register
+ * @CONTROL_READ_COMPLETE_EVENT_ENABLE: STATUS_READ_COMPLETE_EVENT will be
+ * raised in the interrupt_status register
+ * @CONTROL_WRITE_COMPLETE_EVENT_ENABLE: STATUS_WRITE_COMPLETE_EVENT will be
+ * raised in the interrupt_status register
+ * @CONTROL_TIMEOUT_EVENT_ENABLE: STATUS_TIMEOUT_EVENT will be raised in
+ * the interrupt_status register
+ * @CONTROL_ERROR_EVENT_ENABLE: STATUS_ERROR_EVENT will be raised in
+ * the interrupt_status register
+ * @CONTROL_AXI_INT_ENABLE: STATUS_AXI_INT will be raised in the
+ * interrupt_status register
+ * @CONTROL_CMD_NOP: Configure bus to send a NOP command
+ * for the next transfer
+ * @CONTROL_CMD_WRITE: Configure bus to do a write transfer
+ * @CONTROL_CMD_WRITE_POST_INC: Auto-increment address after write
+ * transfer
+ * @CONTROL_CMD_READ: Configure bus to do a read transfer
+ * @CONTROL_CMD_READ_POST_INC: Auto-increment address after read
+ * transfer
+ */
+enum control_reg {
+ CONTROL_READ_COMPLETE_EVENT_ENABLE = BIT(15),
+ CONTROL_WRITE_COMPLETE_EVENT_ENABLE = BIT(14),
+ CONTROL_TIMEOUT_EVENT_ENABLE = BIT(13),
+ CONTROL_ERROR_EVENT_ENABLE = BIT(12),
+ CONTROL_AXI_INT_ENABLE = BIT(11),
+
+ CONTROL_CMD_NOP = 0x0,
+ CONTROL_CMD_WRITE = 0x8,
+ CONTROL_CMD_WRITE_POST_INC = 0x9,
+ CONTROL_CMD_READ = 0xa,
+ CONTROL_CMD_READ_POST_INC = 0xb,
+};
+
+/**
+ * enum axi_cmd - Determine if transfer is read or write transfer
+ * @AXI_CMD_READ: The transfer should be a read transfer
+ * @AXI_CMD_WRITE: The transfer should be a write transfer
+ */
+enum axi_cmd {
+ AXI_CMD_READ,
+ AXI_CMD_WRITE,
+};
+
+/**
+ * ihs_axi_transfer() - Run transfer on the AXI bus
+ * @bus: The AXI bus device on which to run the transfer on
+ * @address: The address to use in the transfer (i.e. which address to
+ * read/write from/to)
+ * @cmd: Should the transfer be a read or write transfer?
+ *
+ * Return: 0 if OK, -ve on error
+ */
+static int ihs_axi_transfer(struct udevice *bus, ulong address,
+ enum axi_cmd cmd)
+{
+ struct ihs_axi_priv *priv = dev_get_priv(bus);
+ /* Try waiting for events up to 10 times */
+ const uint WAIT_TRIES = 10;
+ u16 wait_mask = STATUS_TIMEOUT_EVENT |
+ STATUS_ERROR_EVENT;
+ u16 complete_flag;
+ u16 status;
+ uint k;
+
+ if (cmd == AXI_CMD_READ) {
+ complete_flag = STATUS_READ_COMPLETE_EVENT;
+ cmd = CONTROL_CMD_READ;
+ } else {
+ complete_flag = STATUS_WRITE_COMPLETE_EVENT;
+ cmd = CONTROL_CMD_WRITE;
+ }
+
+ wait_mask |= complete_flag;
+
+ /* Lower 16 bit */
+ ihs_axi_set(priv->map, address_lsb, address & 0xffff);
+ /* Upper 16 bit */
+ ihs_axi_set(priv->map, address_msb, (address >> 16) & 0xffff);
+
+ ihs_axi_set(priv->map, interrupt_status, wait_mask);
+ ihs_axi_set(priv->map, interrupt_enable_control, cmd);
+
+ for (k = WAIT_TRIES; k > 0; --k) {
+ ihs_axi_get(priv->map, interrupt_status, &status);
+ if (status & wait_mask)
+ break;
+ udelay(1);
+ }
+
+ /*
+ * k == 0 -> Tries ran out with no event we were waiting for actually
+ * occurring.
+ */
+ if (!k)
+ ihs_axi_get(priv->map, interrupt_status, &status);
+
+ if (status & complete_flag)
+ return 0;
+
+ if (status & STATUS_ERROR_EVENT) {
+ debug("%s: Error occurred during transfer\n", bus->name);
+ return -EIO;
+ }
+
+ debug("%s: Transfer timed out\n", bus->name);
+ return -ETIMEDOUT;
+}
+
+/*
+ * API
+ */
+
+static int ihs_axi_read(struct udevice *dev, ulong address, void *data,
+ enum axi_size_t size)
+{
+ struct ihs_axi_priv *priv = dev_get_priv(dev);
+ int ret;
+ u16 data_lsb, data_msb;
+ u32 *p = data;
+
+ if (size != AXI_SIZE_32) {
+ debug("%s: transfer size '%d' not supported\n",
+ dev->name, size);
+ return -ENOSYS;
+ }
+
+ ret = ihs_axi_transfer(dev, address, AXI_CMD_READ);
+ if (ret < 0) {
+ debug("%s: Error during AXI transfer (err = %d)\n",
+ dev->name, ret);
+ return ret;
+ }
+
+ ihs_axi_get(priv->map, read_data_lsb, &data_lsb);
+ ihs_axi_get(priv->map, read_data_msb, &data_msb);
+
+ /* Assemble data from two 16-bit words */
+ *p = (data_msb << 16) | data_lsb;
+
+ return 0;
+}
+
+static int ihs_axi_write(struct udevice *dev, ulong address, void *data,
+ enum axi_size_t size)
+{
+ struct ihs_axi_priv *priv = dev_get_priv(dev);
+ int ret;
+ u32 *p = data;
+
+ if (size != AXI_SIZE_32) {
+ debug("%s: transfer size '%d' not supported\n",
+ dev->name, size);
+ return -ENOSYS;
+ }
+
+ /* Lower 16 bit */
+ ihs_axi_set(priv->map, write_data_lsb, *p & 0xffff);
+ /* Upper 16 bit */
+ ihs_axi_set(priv->map, write_data_msb, (*p >> 16) & 0xffff);
+
+ ret = ihs_axi_transfer(dev, address, AXI_CMD_WRITE);
+ if (ret < 0) {
+ debug("%s: Error during AXI transfer (err = %d)\n",
+ dev->name, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id ihs_axi_ids[] = {
+ { .compatible = "gdsys,ihs_axi" },
+ { /* sentinel */ }
+};
+
+static const struct axi_ops ihs_axi_ops = {
+ .read = ihs_axi_read,
+ .write = ihs_axi_write,
+};
+
+static int ihs_axi_probe(struct udevice *dev)
+{
+ struct ihs_axi_priv *priv = dev_get_priv(dev);
+
+ regmap_init_mem(dev_ofnode(dev), &priv->map);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(ihs_axi_bus) = {
+ .name = "ihs_axi_bus",
+ .id = UCLASS_AXI,
+ .of_match = ihs_axi_ids,
+ .ops = &ihs_axi_ops,
+ .priv_auto_alloc_size = sizeof(struct ihs_axi_priv),
+ .probe = ihs_axi_probe,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <axi.h>
+#include <dm.h>
+
+/**
+ * struct sandbox_store_priv - Private data structure of a AXI store device
+ * @store: The buffer holding the device's internal memory, which is read from
+ * and written to using the driver's methods
+ */
+struct sandbox_store_priv {
+ u8 *store;
+};
+
+/**
+ * copy_axi_data() - Copy data from source to destination with a given AXI
+ * transfer width
+ * @src: Pointer to the data source from where data will be read
+ * @dst: Pointer to the data destination where data will be written to
+ * @size: Size of the data to be copied given by a axi_size_t enum value
+ *
+ * Return: 0 if OK, -ve on error
+ */
+static int copy_axi_data(void *src, void *dst, enum axi_size_t size)
+{
+ switch (size) {
+ case AXI_SIZE_8:
+ *((u8 *)dst) = *((u8 *)src);
+ return 0;
+ case AXI_SIZE_16:
+ *((u16 *)dst) = be16_to_cpu(*((u16 *)src));
+ return 0;
+ case AXI_SIZE_32:
+ *((u32 *)dst) = be32_to_cpu(*((u32 *)src));
+ return 0;
+ default:
+ debug("%s: Unknown AXI transfer size '%d'\n", __func__, size);
+ return -EINVAL;
+ }
+}
+
+static int sandbox_store_read(struct udevice *dev, ulong address, void *data,
+ enum axi_size_t size)
+{
+ struct sandbox_store_priv *priv = dev_get_priv(dev);
+
+ return copy_axi_data(priv->store + address, data, size);
+}
+
+static int sandbox_store_write(struct udevice *dev, ulong address, void *data,
+ enum axi_size_t size)
+{
+ struct sandbox_store_priv *priv = dev_get_priv(dev);
+
+ return copy_axi_data(data, priv->store + address, size);
+}
+
+static int sandbox_store_get_store(struct udevice *dev, u8 **store)
+{
+ struct sandbox_store_priv *priv = dev_get_priv(dev);
+
+ *store = priv->store;
+
+ return 0;
+}
+
+static const struct udevice_id sandbox_store_ids[] = {
+ { .compatible = "sandbox,sandbox_store" },
+ { /* sentinel */ }
+};
+
+static const struct axi_emul_ops sandbox_store_ops = {
+ .read = sandbox_store_read,
+ .write = sandbox_store_write,
+ .get_store = sandbox_store_get_store,
+};
+
+static int sandbox_store_probe(struct udevice *dev)
+{
+ struct sandbox_store_priv *priv = dev_get_priv(dev);
+ u32 reg[2];
+ int ret;
+
+ ret = dev_read_u32_array(dev, "reg", reg, ARRAY_SIZE(reg));
+ if (ret) {
+ debug("%s: Could not read 'reg' property\n", dev->name);
+ return -EINVAL;
+ }
+
+ /*
+ * Allocate the device's internal storage that will be read
+ * from/written to
+ */
+ priv->store = calloc(reg[1], 1);
+ if (!priv->store)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static int sandbox_store_remove(struct udevice *dev)
+{
+ struct sandbox_store_priv *priv = dev_get_priv(dev);
+
+ free(priv->store);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(sandbox_axi_store) = {
+ .name = "sandbox_axi_store",
+ .id = UCLASS_AXI_EMUL,
+ .of_match = sandbox_store_ids,
+ .ops = &sandbox_store_ops,
+ .priv_auto_alloc_size = sizeof(struct sandbox_store_priv),
+ .probe = sandbox_store_probe,
+ .remove = sandbox_store_remove,
+};
return ret;
}
+int ofnode_read_pci_vendev(ofnode node, u16 *vendor, u16 *device)
+{
+ const char *list, *end;
+ int len;
+
+ list = ofnode_get_property(node, "compatible", &len);
+ if (!list)
+ return -ENOENT;
+
+ end = list + len;
+ while (list < end) {
+ len = strlen(list);
+ if (len >= strlen("pciVVVV,DDDD")) {
+ char *s = strstr(list, "pci");
+
+ /*
+ * check if the string is something like pciVVVV,DDDD.RR
+ * or just pciVVVV,DDDD
+ */
+ if (s && s[7] == ',' &&
+ (s[12] == '.' || s[12] == 0)) {
+ s += 3;
+ *vendor = simple_strtol(s, NULL, 16);
+
+ s += 5;
+ *device = simple_strtol(s, NULL, 16);
+
+ return 0;
+ }
+ }
+ list += (len + 1);
+ }
+
+ return -ENOENT;
+}
+
int ofnode_read_addr_cells(ofnode node)
{
if (ofnode_is_np(node))
#define STRAPBUS_63268_FCVO_SHIFT 21
#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
+#define REG_BCM6838_OTP_BRCMBITS0 0x440
+#define VIPER_6838_FREQ_SHIFT 18
+#define VIPER_6838_FREQ_MASK (0x7 << VIPER_6838_FREQ_SHIFT)
+
struct bmips_cpu_priv;
struct bmips_cpu_hw {
}
}
+static ulong bcm6838_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+ unsigned int mips_viper_freq;
+
+ mips_viper_freq = readl_be(priv->regs + REG_BCM6838_OTP_BRCMBITS0);
+ mips_viper_freq = (mips_viper_freq & VIPER_6838_FREQ_MASK)
+ >> VIPER_6838_FREQ_SHIFT;
+
+ switch (mips_viper_freq) {
+ case 0x0:
+ return 600000000;
+ case 0x1:
+ return 400000000;
+ case 0x2:
+ return 240000000;
+ default:
+ return 0;
+ }
+}
+
static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
{
u32 val = readl_be(priv->regs + REG_BCM6328_OTP);
.get_cpu_count = bcm6358_get_cpu_count,
};
+static const struct bmips_cpu_hw bmips_cpu_bcm6838 = {
+ .get_cpu_desc = bmips_short_cpu_desc,
+ .get_cpu_freq = bcm6838_get_cpu_freq,
+ .get_cpu_count = bcm6358_get_cpu_count,
+};
+
/* Generic CPU Ops */
static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size)
{
}, {
.compatible = "brcm,bcm63268-cpu",
.data = (ulong)&bmips_cpu_bcm63268,
+ }, {
+ .compatible = "brcm,bcm6838-cpu",
+ .data = (ulong)&bmips_cpu_bcm6838,
},
{ /* sentinel */ }
};
{
const char *str_env;
char *env_bkp;
- int ret;
+ int ret = 0;
#ifdef CONFIG_SET_DFU_ALT_INFO
set_dfu_alt_info(interface, devstr);
ret = dfu_config_entities(env_bkp, interface, devstr);
if (ret) {
pr_err("DFU entities configuration failed!\n");
- return ret;
+ pr_err("(partition table does not match dfu_alt_info?)\n");
+ goto done;
}
+done:
free(env_bkp);
- return 0;
+ return ret;
}
static unsigned char *dfu_buf;
ret = dfu_fill_entity(&dfu[i], s, alt_num_cnt, interface,
devstr);
if (ret) {
- free(dfu);
+ /* We will free "dfu" in dfu_free_entities() */
return -1;
}
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm.h>
+#include <dt-bindings/gpio/gpio.h>
-static LIST_HEAD(gpio_list);
-
-enum gpio_direction {
- GPIO_DIRECTION_OUT = 0,
- GPIO_DIRECTION_IN = 1,
-};
+#define XILINX_GPIO_MAX_BANK 2
/* Gpio simple map */
struct gpio_regs {
u32 gpiodir;
};
-#if !defined(CONFIG_DM_GPIO)
-
-#define GPIO_NAME_SIZE 10
-
-struct gpio_names {
- char name[GPIO_NAME_SIZE];
-};
-
-/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
-struct xilinx_gpio_priv {
- struct gpio_regs *regs;
- u32 gpio_min;
- u32 gpio_max;
- u32 gpiodata_store;
- char name[GPIO_NAME_SIZE];
- struct list_head list;
- struct gpio_names *gpio_name;
-};
-
-/* Store number of allocated gpio pins */
-static u32 xilinx_gpio_max;
-
-/* Get associated gpio controller */
-static struct xilinx_gpio_priv *gpio_get_controller(unsigned gpio)
-{
- struct list_head *entry;
- struct xilinx_gpio_priv *priv = NULL;
-
- list_for_each(entry, &gpio_list) {
- priv = list_entry(entry, struct xilinx_gpio_priv, list);
- if (gpio >= priv->gpio_min && gpio <= priv->gpio_max) {
- debug("%s: reg: %x, min-max: %d-%d\n", __func__,
- (u32)priv->regs, priv->gpio_min, priv->gpio_max);
- return priv;
- }
- }
- puts("!!!Can't get gpio controller!!!\n");
- return NULL;
-}
-
-/* Get gpio pin name if used/setup */
-static char *get_name(unsigned gpio)
-{
- u32 gpio_priv;
- struct xilinx_gpio_priv *priv;
-
- debug("%s\n", __func__);
-
- priv = gpio_get_controller(gpio);
- if (priv) {
- gpio_priv = gpio - priv->gpio_min;
-
- return *priv->gpio_name[gpio_priv].name ?
- priv->gpio_name[gpio_priv].name : "UNKNOWN";
- }
- return "UNKNOWN";
-}
-
-/* Get output value */
-static int gpio_get_output_value(unsigned gpio)
-{
- u32 val, gpio_priv;
- struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
-
- if (priv) {
- gpio_priv = gpio - priv->gpio_min;
- val = !!(priv->gpiodata_store & (1 << gpio_priv));
- debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
- (u32)priv->regs, gpio_priv, val);
-
- return val;
- }
- return -1;
-}
-
-/* Get input value */
-static int gpio_get_input_value(unsigned gpio)
-{
- u32 val, gpio_priv;
- struct gpio_regs *regs;
- struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
-
- if (priv) {
- regs = priv->regs;
- gpio_priv = gpio - priv->gpio_min;
- val = readl(®s->gpiodata);
- val = !!(val & (1 << gpio_priv));
- debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
- (u32)priv->regs, gpio_priv, val);
-
- return val;
- }
- return -1;
-}
-
-/* Set gpio direction */
-static int gpio_set_direction(unsigned gpio, enum gpio_direction direction)
-{
- u32 val, gpio_priv;
- struct gpio_regs *regs;
- struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
-
- if (priv) {
- regs = priv->regs;
- val = readl(®s->gpiodir);
-
- gpio_priv = gpio - priv->gpio_min;
- if (direction == GPIO_DIRECTION_OUT)
- val &= ~(1 << gpio_priv);
- else
- val |= 1 << gpio_priv;
-
- writel(val, ®s->gpiodir);
- debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
- (u32)priv->regs, gpio_priv, val);
-
- return 0;
- }
-
- return -1;
-}
-
-/* Get gpio direction */
-static int gpio_get_direction(unsigned gpio)
-{
- u32 val, gpio_priv;
- struct gpio_regs *regs;
- struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
-
- if (priv) {
- regs = priv->regs;
- gpio_priv = gpio - priv->gpio_min;
- val = readl(®s->gpiodir);
- val = !!(val & (1 << gpio_priv));
- debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
- (u32)priv->regs, gpio_priv, val);
-
- return val;
- }
-
- return -1;
-}
-
-/*
- * Get input value
- * for example gpio setup to output only can't get input value
- * which is breaking gpio toggle command
- */
-int gpio_get_value(unsigned gpio)
-{
- u32 val;
-
- if (gpio_get_direction(gpio) == GPIO_DIRECTION_OUT)
- val = gpio_get_output_value(gpio);
- else
- val = gpio_get_input_value(gpio);
-
- return val;
-}
-
-/* Set output value */
-static int gpio_set_output_value(unsigned gpio, int value)
-{
- u32 val, gpio_priv;
- struct gpio_regs *regs;
- struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
-
- if (priv) {
- regs = priv->regs;
- gpio_priv = gpio - priv->gpio_min;
- val = priv->gpiodata_store;
- if (value)
- val |= 1 << gpio_priv;
- else
- val &= ~(1 << gpio_priv);
-
- writel(val, ®s->gpiodata);
- debug("%s: reg: %x, gpio_no: %d, output_val: %d\n", __func__,
- (u32)priv->regs, gpio_priv, val);
- priv->gpiodata_store = val;
-
- return 0;
- }
-
- return -1;
-}
-
-int gpio_set_value(unsigned gpio, int value)
-{
- if (gpio_get_direction(gpio) == GPIO_DIRECTION_OUT)
- return gpio_set_output_value(gpio, value);
-
- return -1;
-}
-
-/* Set GPIO as input */
-int gpio_direction_input(unsigned gpio)
-{
- debug("%s\n", __func__);
- return gpio_set_direction(gpio, GPIO_DIRECTION_IN);
-}
-
-/* Setup GPIO as output and set output value */
-int gpio_direction_output(unsigned gpio, int value)
-{
- int ret = gpio_set_direction(gpio, GPIO_DIRECTION_OUT);
-
- debug("%s\n", __func__);
-
- if (ret < 0)
- return ret;
-
- return gpio_set_output_value(gpio, value);
-}
-
-/* Show gpio status */
-void gpio_info(void)
-{
- unsigned gpio;
-
- struct list_head *entry;
- struct xilinx_gpio_priv *priv = NULL;
-
- list_for_each(entry, &gpio_list) {
- priv = list_entry(entry, struct xilinx_gpio_priv, list);
- printf("\n%s: %s/%x (%d-%d)\n", __func__, priv->name,
- (u32)priv->regs, priv->gpio_min, priv->gpio_max);
-
- for (gpio = priv->gpio_min; gpio <= priv->gpio_max; gpio++) {
- printf("GPIO_%d:\t%s is an ", gpio, get_name(gpio));
- if (gpio_get_direction(gpio) == GPIO_DIRECTION_OUT)
- printf("OUTPUT value = %d\n",
- gpio_get_output_value(gpio));
- else
- printf("INPUT value = %d\n",
- gpio_get_input_value(gpio));
- }
- }
-}
-
-int gpio_request(unsigned gpio, const char *label)
-{
- u32 gpio_priv;
- struct xilinx_gpio_priv *priv;
-
- if (gpio >= xilinx_gpio_max)
- return -EINVAL;
-
- priv = gpio_get_controller(gpio);
- if (priv) {
- gpio_priv = gpio - priv->gpio_min;
-
- if (label != NULL) {
- strncpy(priv->gpio_name[gpio_priv].name, label,
- GPIO_NAME_SIZE);
- priv->gpio_name[gpio_priv].name[GPIO_NAME_SIZE - 1] =
- '\0';
- }
- return 0;
- }
-
- return -1;
-}
-
-int gpio_free(unsigned gpio)
-{
- u32 gpio_priv;
- struct xilinx_gpio_priv *priv;
-
- if (gpio >= xilinx_gpio_max)
- return -EINVAL;
-
- priv = gpio_get_controller(gpio);
- if (priv) {
- gpio_priv = gpio - priv->gpio_min;
- priv->gpio_name[gpio_priv].name[0] = '\0';
-
- /* Do nothing here */
- return 0;
- }
-
- return -1;
-}
-
-int gpio_alloc(u32 baseaddr, const char *name, u32 gpio_no)
-{
- struct xilinx_gpio_priv *priv;
-
- priv = calloc(1, sizeof(struct xilinx_gpio_priv));
-
- /* Setup gpio name */
- if (name != NULL) {
- strncpy(priv->name, name, GPIO_NAME_SIZE);
- priv->name[GPIO_NAME_SIZE - 1] = '\0';
- }
- priv->regs = (struct gpio_regs *)baseaddr;
-
- priv->gpio_min = xilinx_gpio_max;
- xilinx_gpio_max = priv->gpio_min + gpio_no;
- priv->gpio_max = xilinx_gpio_max - 1;
-
- priv->gpio_name = calloc(gpio_no, sizeof(struct gpio_names));
-
- INIT_LIST_HEAD(&priv->list);
- list_add_tail(&priv->list, &gpio_list);
-
- printf("%s: Add %s (%d-%d)\n", __func__, name,
- priv->gpio_min, priv->gpio_max);
-
- /* Return the first gpio allocated for this device */
- return priv->gpio_min;
-}
-
-/* Dual channel gpio is one IP with two independent channels */
-int gpio_alloc_dual(u32 baseaddr, const char *name, u32 gpio_no0, u32 gpio_no1)
-{
- int ret;
-
- ret = gpio_alloc(baseaddr, name, gpio_no0);
- gpio_alloc(baseaddr + 8, strcat((char *)name, "_1"), gpio_no1);
-
- /* Return the first gpio allocated for this device */
- return ret;
-}
-#else
-#include <dt-bindings/gpio/gpio.h>
-
-#define XILINX_GPIO_MAX_BANK 2
-
struct xilinx_gpio_platdata {
struct gpio_regs *regs;
int bank_max[XILINX_GPIO_MAX_BANK];
int bank_input[XILINX_GPIO_MAX_BANK];
int bank_output[XILINX_GPIO_MAX_BANK];
+ u32 dout_default[XILINX_GPIO_MAX_BANK];
+};
+
+struct xilinx_gpio_privdata {
+ u32 output_val[XILINX_GPIO_MAX_BANK];
};
static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num,
int value)
{
struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
int val, ret;
u32 bank, pin;
if (ret)
return ret;
- debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x\n",
- __func__, (ulong)platdata->regs, value, offset, bank, pin);
+ val = priv->output_val[bank];
- if (value) {
- val = readl(&platdata->regs->gpiodata + bank * 2);
+ debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x, out %x\n",
+ __func__, (ulong)platdata->regs, value, offset, bank, pin, val);
+
+ if (value)
val = val | (1 << pin);
- writel(val, &platdata->regs->gpiodata + bank * 2);
- } else {
- val = readl(&platdata->regs->gpiodata + bank * 2);
+ else
val = val & ~(1 << pin);
- writel(val, &platdata->regs->gpiodata + bank * 2);
- }
- return val;
+ writel(val, &platdata->regs->gpiodata + bank * 2);
+
+ priv->output_val[bank] = val;
+
+ return 0;
};
static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
{
struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
int val, ret;
u32 bank, pin;
debug("%s: regs: %lx, gpio: %x, bank %x, pin %x\n", __func__,
(ulong)platdata->regs, offset, bank, pin);
- val = readl(&platdata->regs->gpiodata + bank * 2);
+ if (platdata->bank_output[bank]) {
+ debug("%s: Read saved output value\n", __func__);
+ val = priv->output_val[bank];
+ } else {
+ debug("%s: Read input value from reg\n", __func__);
+ val = readl(&platdata->regs->gpiodata + bank * 2);
+ }
+
val = !!(val & (1 << pin));
return val;
int val, ret;
u32 bank, pin;
+ ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
+ if (ret)
+ return ret;
+
/* Check if all pins are inputs */
if (platdata->bank_input[bank])
return GPIOF_INPUT;
if (platdata->bank_output[bank])
return GPIOF_OUTPUT;
- ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
- if (ret)
- return ret;
-
/* FIXME test on dual */
val = readl(&platdata->regs->gpiodir + bank * 2);
val = !(val & (1 << pin));
if (platdata->bank_input[bank])
return -EINVAL;
+ xilinx_gpio_set_value(dev, offset, value);
+
if (!platdata->bank_output[bank]) {
val = readl(&platdata->regs->gpiodir + bank * 2);
val = val & ~(1 << pin);
writel(val, &platdata->regs->gpiodir + bank * 2);
}
- xilinx_gpio_set_value(dev, offset, value);
-
return 0;
}
static int xilinx_gpio_probe(struct udevice *dev)
{
struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ const void *label_ptr;
- uc_priv->bank_name = dev->name;
+ label_ptr = dev_read_prop(dev, "label", NULL);
+ if (label_ptr) {
+ uc_priv->bank_name = strdup(label_ptr);
+ if (!uc_priv->bank_name)
+ return -ENOMEM;
+ } else {
+ uc_priv->bank_name = dev->name;
+ }
uc_priv->gpio_count = platdata->bank_max[0] + platdata->bank_max[1];
+ priv->output_val[0] = platdata->dout_default[0];
+
+ if (platdata->bank_max[1])
+ priv->output_val[1] = platdata->dout_default[1];
+
return 0;
}
"xlnx,all-inputs", 0);
platdata->bank_output[0] = dev_read_u32_default(dev,
"xlnx,all-outputs", 0);
+ platdata->dout_default[0] = dev_read_u32_default(dev,
+ "xlnx,dout-default",
+ 0);
is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0);
if (is_dual) {
"xlnx,all-inputs-2", 0);
platdata->bank_output[1] = dev_read_u32_default(dev,
"xlnx,all-outputs-2", 0);
+ platdata->dout_default[1] = dev_read_u32_default(dev,
+ "xlnx,dout-default-2", 0);
}
return 0;
.ofdata_to_platdata = xilinx_gpio_ofdata_to_platdata,
.probe = xilinx_gpio_probe,
.platdata_auto_alloc_size = sizeof(struct xilinx_gpio_platdata),
+ .priv_auto_alloc_size = sizeof(struct xilinx_gpio_privdata),
};
-#endif
/* GPIO upper 16 bit mask */
#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
-struct zynq_gpio_privdata {
+struct zynq_gpio_platdata {
phys_addr_t base;
const struct zynq_platform_data *p_data;
};
unsigned int *bank_pin_num,
struct udevice *dev)
{
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
u32 bank;
- for (bank = 0; bank < priv->p_data->max_bank; bank++) {
- if ((pin_num >= priv->p_data->bank_min[bank]) &&
- (pin_num <= priv->p_data->bank_max[bank])) {
- *bank_num = bank;
- *bank_pin_num = pin_num -
- priv->p_data->bank_min[bank];
- return;
+ for (bank = 0; bank < platdata->p_data->max_bank; bank++) {
+ if (pin_num >= platdata->p_data->bank_min[bank] &&
+ pin_num <= platdata->p_data->bank_max[bank]) {
+ *bank_num = bank;
+ *bank_pin_num = pin_num -
+ platdata->p_data->bank_min[bank];
+ return;
}
}
- if (bank >= priv->p_data->max_bank) {
+ if (bank >= platdata->p_data->max_bank) {
printf("Invalid bank and pin num\n");
*bank_num = 0;
*bank_pin_num = 0;
static int gpio_is_valid(unsigned gpio, struct udevice *dev)
{
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
- return gpio < priv->p_data->ngpio;
+ return gpio < platdata->p_data->ngpio;
}
static int check_gpio(unsigned gpio, struct udevice *dev)
{
u32 data;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
- data = readl(priv->base +
+ data = readl(platdata->base +
ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
return (data >> bank_pin_num) & 1;
static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
{
unsigned int reg_offset, bank_num, bank_pin_num;
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
- writel(value, priv->base + reg_offset);
+ writel(value, platdata->base + reg_offset);
return 0;
}
{
u32 reg;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
return -1;
/* clear the bit in direction mode reg to set the pin as input */
- reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg &= ~BIT(bank_pin_num);
- writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
return 0;
}
{
u32 reg;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
/* set the GPIO pin as output */
- reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg |= BIT(bank_pin_num);
- writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
/* configure the output enable reg for the pin */
- reg = readl(priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
+ reg = readl(platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
reg |= BIT(bank_pin_num);
- writel(reg, priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
+ writel(reg, platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
/* set the state of the pin */
gpio_set_value(gpio, value);
{
u32 reg;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
if (check_gpio(offset, dev) < 0)
return -1;
zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev);
/* set the GPIO pin as output */
- reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg &= BIT(bank_pin_num);
if (reg)
return GPIOF_OUTPUT;
static int zynq_gpio_probe(struct udevice *dev)
{
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ const void *label_ptr;
- uc_priv->bank_name = dev->name;
+ label_ptr = dev_read_prop(dev, "label", NULL);
+ if (label_ptr) {
+ uc_priv->bank_name = strdup(label_ptr);
+ if (!uc_priv->bank_name)
+ return -ENOMEM;
+ } else {
+ uc_priv->bank_name = dev->name;
+ }
- if (priv->p_data)
- uc_priv->gpio_count = priv->p_data->ngpio;
+ if (platdata->p_data)
+ uc_priv->gpio_count = platdata->p_data->ngpio;
return 0;
}
static int zynq_gpio_ofdata_to_platdata(struct udevice *dev)
{
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
- priv->base = (phys_addr_t)dev_read_addr(dev);
+ platdata->base = (phys_addr_t)dev_read_addr(dev);
- priv->p_data = (struct zynq_platform_data *)dev_get_driver_data(dev);
+ platdata->p_data =
+ (struct zynq_platform_data *)dev_get_driver_data(dev);
return 0;
}
.of_match = zynq_gpio_ids,
.ofdata_to_platdata = zynq_gpio_ofdata_to_platdata,
.probe = zynq_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct zynq_gpio_privdata),
+ .platdata_auto_alloc_size = sizeof(struct zynq_gpio_platdata),
};
#include <dm.h>
#include <errno.h>
#include <led.h>
+#include <dm/device-internal.h>
#include <dm/root.h>
#include <dm/uclass-internal.h>
}
#endif
+int led_default_state(void)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ const char *default_state;
+ int ret;
+
+ ret = uclass_get(UCLASS_LED, &uc);
+ if (ret)
+ return ret;
+ for (uclass_find_first_device(UCLASS_LED, &dev);
+ dev;
+ uclass_find_next_device(&dev)) {
+ default_state = dev_read_string(dev, "default-state");
+ if (!default_state)
+ continue;
+ ret = device_probe(dev);
+ if (ret)
+ return ret;
+ if (!strncmp(default_state, "on", 2))
+ led_set_state(dev, LEDST_ON);
+ else if (!strncmp(default_state, "off", 3))
+ led_set_state(dev, LEDST_OFF);
+ /* default-state = "keep" : device is only probed */
+ }
+
+ return ret;
+}
+
UCLASS_DRIVER(led) = {
.id = UCLASS_LED,
.name = "led",
#include <led.h>
#include <asm/gpio.h>
#include <dm/lists.h>
-#include <dm/uclass-internal.h>
struct led_gpio_priv {
struct gpio_desc gpio;
{
struct led_uc_plat *uc_plat = dev_get_uclass_platdata(dev);
struct led_gpio_priv *priv = dev_get_priv(dev);
- const char *default_state;
int ret;
/* Ignore the top-level LED node */
if (ret)
return ret;
- default_state = dev_read_string(dev, "default-state");
- if (default_state) {
- if (!strncmp(default_state, "on", 2))
- gpio_led_set_state(dev, LEDST_ON);
- else if (!strncmp(default_state, "off", 3))
- gpio_led_set_state(dev, LEDST_OFF);
- }
return 0;
}
return ret;
uc_plat = dev_get_uclass_platdata(dev);
uc_plat->label = label;
-
- if (ofnode_read_bool(node, "default-state")) {
- struct udevice *devp;
-
- ret = uclass_get_device_tail(dev, 0, &devp);
- if (ret)
- return ret;
- }
}
return 0;
depends on MISC
help
Support gdsys FPGA's RXAUI control.
+
+config GDSYS_IOEP
+ bool "Enable gdsys IOEP driver"
+ depends on MISC
+ help
+ Support gdsys FPGA's IO endpoint driver.
endmenu
obj-$(CONFIG_SANDBOX) += spltest_sandbox.o
endif
endif
-obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
+obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o
obj-$(CONFIG_TEGRA_CAR) += tegra_car.o
obj-$(CONFIG_TEGRA186_BPMP) += tegra186_bpmp.o
obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
obj-$(CONFIG_STM32_RCC) += stm32_rcc.o
obj-$(CONFIG_STM32MP_FUSE) += stm32mp_fuse.o
obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o
+obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2017
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * based on the cmd_ioloop driver/command, which is
+ *
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <misc.h>
+#include <regmap.h>
+
+#include "gdsys_ioep.h"
+
+/**
+ * struct gdsys_ioep_priv - Private data structure for IOEP devices
+ * @map: Register map to be used for the device
+ * @state: Flag to keep the current status of the RX control (enabled/disabled)
+ */
+struct gdsys_ioep_priv {
+ struct regmap *map;
+ bool state;
+};
+
+/**
+ * enum last_spec - Convenience enum for read data sanity check
+ * @READ_DATA_IS_LAST: The data to be read should be the final data of the
+ * current packet
+ * @READ_DATA_IS_NOT_LAST: The data to be read should not be the final data of
+ * the current packet
+ */
+enum last_spec {
+ READ_DATA_IS_LAST,
+ READ_DATA_IS_NOT_LAST,
+};
+
+static int gdsys_ioep_set_receive(struct udevice *dev, bool val)
+{
+ struct gdsys_ioep_priv *priv = dev_get_priv(dev);
+ u16 state;
+
+ priv->state = !priv->state;
+
+ if (val)
+ state = CTRL_PROC_RECEIVE_ENABLE;
+ else
+ state = ~CTRL_PROC_RECEIVE_ENABLE;
+
+ gdsys_ioep_set(priv->map, tx_control, state);
+
+ if (val) {
+ /* Set device address to dummy 1 */
+ gdsys_ioep_set(priv->map, device_address, 1);
+ }
+
+ return !priv->state;
+}
+
+static int gdsys_ioep_send(struct udevice *dev, int offset,
+ const void *buf, int size)
+{
+ struct gdsys_ioep_priv *priv = dev_get_priv(dev);
+ int k;
+ u16 *p = (u16 *)buf;
+
+ for (k = 0; k < size; ++k)
+ gdsys_ioep_set(priv->map, transmit_data, *(p++));
+
+ gdsys_ioep_set(priv->map, tx_control, CTRL_PROC_RECEIVE_ENABLE |
+ CTRL_FLUSH_TRANSMIT_BUFFER);
+
+ return 0;
+}
+
+/**
+ * receive_byte_buffer() - Read data from a IOEP device
+ * @dev: The IOEP device to read data from
+ * @len: The length of the data to read
+ * @buffer: The buffer to read the data into
+ * @last_spec: Flag to indicate if the data to be read in this call should be
+ * the final data of the current packet (i.e. it should be empty
+ * after this read)
+ *
+ * Return: 0 if OK, -ve on error
+ */
+static int receive_byte_buffer(struct udevice *dev, uint len,
+ u16 *buffer, enum last_spec last_spec)
+{
+ struct gdsys_ioep_priv *priv = dev_get_priv(dev);
+ int k;
+ int ret = -EIO;
+
+ for (k = 0; k < len; ++k) {
+ u16 rx_tx_status;
+
+ gdsys_ioep_get(priv->map, receive_data, buffer++);
+
+ gdsys_ioep_get(priv->map, rx_tx_status, &rx_tx_status);
+ /*
+ * Sanity check: If the data read should have been the last,
+ * but wasn't, something is wrong
+ */
+ if (k == (len - 1) && (last_spec == READ_DATA_IS_NOT_LAST ||
+ rx_tx_status & STATE_RX_DATA_LAST))
+ ret = 0;
+ }
+
+ if (ret)
+ debug("%s: Error while receiving bufer (err = %d)\n",
+ dev->name, ret);
+
+ return ret;
+}
+
+static int gdsys_ioep_receive(struct udevice *dev, int offset, void *buf,
+ int size)
+{
+ int ret;
+ struct io_generic_packet header;
+ u16 *p = (u16 *)buf;
+ const int header_words = sizeof(struct io_generic_packet) / sizeof(u16);
+ uint len;
+
+ /* Read the packet header */
+ ret = receive_byte_buffer(dev, header_words, p, READ_DATA_IS_NOT_LAST);
+ if (ret) {
+ debug("%s: Failed to read header data (err = %d)\n",
+ dev->name, ret);
+ return ret;
+ }
+
+ memcpy(&header, p, header_words * sizeof(u16));
+ p += header_words;
+
+ /* Get payload data length */
+ len = (header.packet_length + 1) / sizeof(u16);
+
+ /* Read the packet payload */
+ ret = receive_byte_buffer(dev, len, p, READ_DATA_IS_LAST);
+ if (ret) {
+ debug("%s: Failed to read payload data (err = %d)\n",
+ dev->name, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int gdsys_ioep_get_and_reset_status(struct udevice *dev, int msgid,
+ void *tx_msg, int tx_size,
+ void *rx_msg, int rx_size)
+{
+ struct gdsys_ioep_priv *priv = dev_get_priv(dev);
+ const u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR |
+ STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR |
+ STATE_RX_PACKET_DROPPED | STATE_TX_ERR;
+ u16 *status = rx_msg;
+
+ gdsys_ioep_get(priv->map, rx_tx_status, status);
+
+ gdsys_ioep_set(priv->map, rx_tx_status, *status);
+
+ return (*status & mask) ? 1 : 0;
+}
+
+static const struct misc_ops gdsys_ioep_ops = {
+ .set_enabled = gdsys_ioep_set_receive,
+ .write = gdsys_ioep_send,
+ .read = gdsys_ioep_receive,
+ .call = gdsys_ioep_get_and_reset_status,
+};
+
+static int gdsys_ioep_probe(struct udevice *dev)
+{
+ struct gdsys_ioep_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = regmap_init_mem(dev_ofnode(dev), &priv->map);
+ if (ret) {
+ debug("%s: Could not initialize regmap (err = %d)",
+ dev->name, ret);
+ return ret;
+ }
+
+ priv->state = false;
+
+ return 0;
+}
+
+static const struct udevice_id gdsys_ioep_ids[] = {
+ { .compatible = "gdsys,io-endpoint" },
+ { }
+};
+
+U_BOOT_DRIVER(gdsys_ioep) = {
+ .name = "gdsys_ioep",
+ .id = UCLASS_MISC,
+ .ops = &gdsys_ioep_ops,
+ .flags = DM_UC_FLAG_SEQ_ALIAS,
+ .of_match = gdsys_ioep_ids,
+ .probe = gdsys_ioep_probe,
+ .priv_auto_alloc_size = sizeof(struct gdsys_ioep_priv),
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#ifndef __GDSYS_IOEP_H_
+#define __GDSYS_IOEP_H_
+
+/**
+ * struct io_generic_packet - header structure for GDSYS IOEP packets
+ * @target_address: Target protocol address of the packet.
+ * @source_address: Source protocol address of the packet.
+ * @packet_type: Packet type.
+ * @bc: Block counter (filled in by FPGA).
+ * @packet_length: Length of the packet's payload bytes.
+ */
+struct io_generic_packet {
+ u16 target_address;
+ u16 source_address;
+ u8 packet_type;
+ u8 bc;
+ u16 packet_length;
+} __attribute__((__packed__));
+
+/**
+ * struct gdsys_ioep_regs - Registers of a IOEP device
+ * @transmit_data: Register that receives data to be sent
+ * @tx_control: TX control register
+ * @receive_data: Register filled with the received data
+ * @rx_tx_status: RX/TX status register
+ * @device_address: Register for setting/reading the device's address
+ * @target_address: Register for setting/reading the remote endpoint's address
+ * @int_enable: Interrupt/Interrupt enable register
+ */
+struct gdsys_ioep_regs {
+ u16 transmit_data;
+ u16 tx_control;
+ u16 receive_data;
+ u16 rx_tx_status;
+ u16 device_address;
+ u16 target_address;
+ u16 int_enable;
+};
+
+/**
+ * gdsys_ioep_set() - Convenience macro to write registers of a IOEP device
+ * @map: Register map to write the value in
+ * @member: Name of the member in the gdsys_ioep_regs structure to write
+ * @val: Value to write to the register
+ */
+#define gdsys_ioep_set(map, member, val) \
+ regmap_set(map, struct gdsys_ioep_regs, member, val)
+
+/**
+ * gdsys_ioep_get() - Convenience macro to read registers of a IOEP device
+ * @map: Register map to read the value from
+ * @member: Name of the member in the gdsys_ioep_regs structure to read
+ * @valp: Pointer to buffer to read the register value into
+ */
+#define gdsys_ioep_get(map, member, valp) \
+ regmap_get(map, struct gdsys_ioep_regs, member, valp)
+
+/**
+ * enum rx_tx_status_values - Enum to describe the fields of the rx_tx_status
+ * register
+ * @STATE_TX_PACKET_BUILDING: The device is currently building a packet
+ * (and accepting data for it)
+ * @STATE_TX_TRANSMITTING: A packet is currenly being transmitted
+ * @STATE_TX_BUFFER_FULL: The TX buffer is full
+ * @STATE_TX_ERR: A TX error occurred
+ * @STATE_RECEIVE_TIMEOUT: A receive timeout occurred
+ * @STATE_PROC_RX_STORE_TIMEOUT: A RX store timeout for a processor packet
+ * occurred
+ * @STATE_PROC_RX_RECEIVE_TIMEOUT: A RX receive timeout for a processor packet
+ * occurred
+ * @STATE_RX_DIST_ERR: A error occurred in the distribution block
+ * @STATE_RX_LENGTH_ERR: A length invalid error occurred
+ * @STATE_RX_FRAME_CTR_ERR: A frame count error occurred (two
+ * non-increasing frame count numbers
+ * encountered)
+ * @STATE_RX_FCS_ERR: A CRC error occurred
+ * @STATE_RX_PACKET_DROPPED: A RX packet has been dropped
+ * @STATE_RX_DATA_LAST: The data to be read is the final data of the
+ * current packet
+ * @STATE_RX_DATA_FIRST: The data to be read is the first data of the
+ * current packet
+ * @STATE_RX_DATA_AVAILABLE: RX data is available to be read
+ */
+enum rx_tx_status_values {
+ STATE_TX_PACKET_BUILDING = BIT(0),
+ STATE_TX_TRANSMITTING = BIT(1),
+ STATE_TX_BUFFER_FULL = BIT(2),
+ STATE_TX_ERR = BIT(3),
+ STATE_RECEIVE_TIMEOUT = BIT(4),
+ STATE_PROC_RX_STORE_TIMEOUT = BIT(5),
+ STATE_PROC_RX_RECEIVE_TIMEOUT = BIT(6),
+ STATE_RX_DIST_ERR = BIT(7),
+ STATE_RX_LENGTH_ERR = BIT(8),
+ STATE_RX_FRAME_CTR_ERR = BIT(9),
+ STATE_RX_FCS_ERR = BIT(10),
+ STATE_RX_PACKET_DROPPED = BIT(11),
+ STATE_RX_DATA_LAST = BIT(12),
+ STATE_RX_DATA_FIRST = BIT(13),
+ STATE_RX_DATA_AVAILABLE = BIT(15),
+};
+
+/**
+ * enum tx_control_values - Enum to describe the fields of the tx_control
+ * register
+ * @CTRL_PROC_RECEIVE_ENABLE: Enable packet reception for the processor
+ * @CTRL_FLUSH_TRANSMIT_BUFFER: Flush the transmit buffer (and send packet data)
+ */
+enum tx_control_values {
+ CTRL_PROC_RECEIVE_ENABLE = BIT(12),
+ CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15),
+};
+
+/**
+ * enum int_enable_values - Enum to describe the fields of the int_enable
+ * register
+ * @IRQ_CPU_TRANSMITBUFFER_FREE_STATUS: The transmit buffer is free (packet
+ * data can be transmitted to the
+ * device)
+ * @IRQ_CPU_PACKET_TRANSMITTED_EVENT: A packet has been transmitted
+ * @IRQ_NEW_CPU_PACKET_RECEIVED_EVENT: A new packet has been received
+ * @IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS: RX packet data are available to be
+ * read
+ */
+enum int_enable_values {
+ IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5),
+ IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6),
+ IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = BIT(7),
+ IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8),
+};
+
+#endif /* __GDSYS_IOEP_H_ */
return ops->call(dev, msgid, tx_msg, tx_size, rx_msg, rx_size);
}
+int misc_set_enabled(struct udevice *dev, bool val)
+{
+ const struct misc_ops *ops = device_get_ops(dev);
+
+ if (!ops->set_enabled)
+ return -ENOSYS;
+
+ return ops->set_enabled(dev, val);
+}
+
UCLASS_DRIVER(misc) = {
.id = UCLASS_MISC,
.name = "misc",
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <misc.h>
+
+struct misc_sandbox_priv {
+ u8 mem[128];
+ ulong last_ioctl;
+ bool enabled;
+};
+
+int misc_sandbox_read(struct udevice *dev, int offset, void *buf, int size)
+{
+ struct misc_sandbox_priv *priv = dev_get_priv(dev);
+
+ memcpy(buf, priv->mem + offset, size);
+
+ return 0;
+}
+
+int misc_sandbox_write(struct udevice *dev, int offset, const void *buf,
+ int size)
+{
+ struct misc_sandbox_priv *priv = dev_get_priv(dev);
+
+ memcpy(priv->mem + offset, buf, size);
+
+ return 0;
+}
+
+int misc_sandbox_ioctl(struct udevice *dev, unsigned long request, void *buf)
+{
+ struct misc_sandbox_priv *priv = dev_get_priv(dev);
+
+ priv->last_ioctl = request;
+
+ return 0;
+}
+
+int misc_sandbox_call(struct udevice *dev, int msgid, void *tx_msg,
+ int tx_size, void *rx_msg, int rx_size)
+{
+ struct misc_sandbox_priv *priv = dev_get_priv(dev);
+
+ if (msgid == 0) {
+ int num = *(int *)tx_msg;
+
+ switch (num) {
+ case 0:
+ strncpy(rx_msg, "Zero", rx_size);
+ break;
+ case 1:
+ strncpy(rx_msg, "One", rx_size);
+ break;
+ case 2:
+ strncpy(rx_msg, "Two", rx_size);
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ if (msgid == 1) {
+ int num = *(int *)tx_msg;
+
+ switch (num) {
+ case 0:
+ strncpy(rx_msg, "Forty", rx_size);
+ break;
+ case 1:
+ strncpy(rx_msg, "Forty-one", rx_size);
+ break;
+ case 2:
+ strncpy(rx_msg, "Forty-two", rx_size);
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ if (msgid == 2)
+ memcpy(rx_msg, &priv->last_ioctl, sizeof(priv->last_ioctl));
+
+ if (msgid == 3)
+ memcpy(rx_msg, &priv->enabled, sizeof(priv->enabled));
+
+ return 0;
+}
+
+int misc_sandbox_set_enabled(struct udevice *dev, bool val)
+{
+ struct misc_sandbox_priv *priv = dev_get_priv(dev);
+
+ priv->enabled = !priv->enabled;
+
+ return 0;
+}
+
+static const struct misc_ops misc_sandbox_ops = {
+ .read = misc_sandbox_read,
+ .write = misc_sandbox_write,
+ .ioctl = misc_sandbox_ioctl,
+ .call = misc_sandbox_call,
+ .set_enabled = misc_sandbox_set_enabled,
+};
+
+int misc_sandbox_probe(struct udevice *dev)
+{
+ struct misc_sandbox_priv *priv = dev_get_priv(dev);
+
+ priv->enabled = true;
+
+ return 0;
+}
+
+static const struct udevice_id misc_sandbox_ids[] = {
+ { .compatible = "sandbox,misc_sandbox" },
+ { }
+};
+
+U_BOOT_DRIVER(misc_sandbox) = {
+ .name = "misc_sandbox",
+ .id = UCLASS_MISC,
+ .ops = &misc_sandbox_ops,
+ .of_match = misc_sandbox_ids,
+ .probe = misc_sandbox_probe,
+ .priv_auto_alloc_size = sizeof(struct misc_sandbox_priv),
+};
*valuep = result;
break;
}
+ case PCI_CAPABILITY_LIST:
+ *valuep = PCI_CAP_ID_PM_OFFSET;
+ break;
+ case PCI_CAP_ID_PM_OFFSET:
+ *valuep = (PCI_CAP_ID_EXP_OFFSET << 8) | PCI_CAP_ID_PM;
+ break;
+ case PCI_CAP_ID_EXP_OFFSET:
+ *valuep = (PCI_CAP_ID_MSIX_OFFSET << 8) | PCI_CAP_ID_EXP;
+ break;
+ case PCI_CAP_ID_MSIX_OFFSET:
+ *valuep = PCI_CAP_ID_MSIX;
+ break;
+ case PCI_EXT_CAP_ID_ERR_OFFSET:
+ *valuep = (PCI_EXT_CAP_ID_VC_OFFSET << 20) | PCI_EXT_CAP_ID_ERR;
+ break;
+ case PCI_EXT_CAP_ID_VC_OFFSET:
+ *valuep = (PCI_EXT_CAP_ID_DSN_OFFSET << 20) | PCI_EXT_CAP_ID_VC;
+ break;
+ case PCI_EXT_CAP_ID_DSN_OFFSET:
+ *valuep = PCI_EXT_CAP_ID_DSN;
+ break;
}
return 0;
debug("w bar %d=%lx\n", barnum, value);
*bar = value;
+ /* space indicator (bit#0) is read-only */
+ *bar |= barinfo[barnum].type;
break;
}
}
for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
unsigned int size = barinfo[barnum].size;
+ u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE;
- if (addr >= plat->bar[barnum] &&
- addr < plat->bar[barnum] + size) {
+ if (addr >= base && addr < base + size) {
*barnump = barnum;
- *offsetp = addr - plat->bar[barnum];
+ *offsetp = addr - base;
return 0;
}
}
.priv_auto_alloc_size = sizeof(struct swap_case_priv),
.platdata_auto_alloc_size = sizeof(struct swap_case_platdata),
};
+
+static struct pci_device_id sandbox_swap_case_supported[] = {
+ { PCI_VDEVICE(SANDBOX, SANDBOX_PCI_DEVICE_ID), SWAP_CASE_DRV_DATA },
+ {},
+};
+
+U_BOOT_PCI_DEVICE(sandbox_swap_case_emul, sandbox_swap_case_supported);
*/
static void exynos_dwmci_clksel(struct dwmci_host *host)
{
+#ifdef CONFIG_DM_MMC
+ struct dwmci_exynos_priv_data *priv =
+ container_of(host, struct dwmci_exynos_priv_data, host);
+#else
struct dwmci_exynos_priv_data *priv = host->priv;
-
+#endif
dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
}
}
static int exynos_dwmci_get_config(const void *blob, int node,
- struct dwmci_host *host)
+ struct dwmci_host *host,
+ struct dwmci_exynos_priv_data *priv)
{
int err = 0;
u32 base, timing[3];
- struct dwmci_exynos_priv_data *priv;
-
- priv = malloc(sizeof(struct dwmci_exynos_priv_data));
- if (!priv) {
- pr_err("dwmci_exynos_priv_data malloc fail!\n");
- return -ENOMEM;
- }
/* Extract device id for each mmc channel */
host->dev_id = pinmux_decode_periph_id(blob, node);
if (host->dev_index > 4) {
printf("DWMMC%d: Can't get the dev index\n", host->dev_index);
- free(priv);
return -EINVAL;
}
base = fdtdec_get_addr(blob, node, "reg");
if (!base) {
printf("DWMMC%d: Can't get base address\n", host->dev_index);
- free(priv);
return -EINVAL;
}
host->ioaddr = (void *)base;
if (err) {
printf("DWMMC%d: Can't get sdr-timings for devider\n",
host->dev_index);
- free(priv);
return -EINVAL;
}
host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
host->div = fdtdec_get_int(blob, node, "div", 0);
- host->priv = priv;
-
return 0;
}
static int exynos_dwmci_process_node(const void *blob,
int node_list[], int count)
{
+ struct dwmci_exynos_priv_data *priv;
struct dwmci_host *host;
int i, node, err;
if (node <= 0)
continue;
host = &dwmci_host[i];
- err = exynos_dwmci_get_config(blob, node, host);
+
+ priv = malloc(sizeof(struct dwmci_exynos_priv_data));
+ if (!priv) {
+ pr_err("dwmci_exynos_priv_data malloc fail!\n");
+ return -ENOMEM;
+ }
+
+ err = exynos_dwmci_get_config(blob, node, host, priv);
if (err) {
printf("%s: failed to decode dev %d\n", __func__, i);
+ free(priv);
return err;
}
+ host->priv = priv;
do_dwmci_init(host);
}
struct dwmci_host *host = &priv->host;
int err;
- err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host);
+ err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host,
+ priv);
if (err)
return err;
err = do_dwmci_init(host);
static const struct udevice_id exynos_dwmmc_ids[] = {
{ .compatible = "samsung,exynos4412-dw-mshc" },
+ { .compatible = "samsung,exynos-dwmmc" },
{ }
};
help
Add support for various GigaDevice SPI flash chips (GD25xxx)
+config SPI_FLASH_ISSI
+ bool "ISSI SPI flash support"
+ help
+ Add support for various ISSI SPI flash chips (ISxxx)
+
config SPI_FLASH_MACRONIX
bool "Macronix SPI flash support"
help
#include <pci.h>
#include <dm/lists.h>
-struct sandbox_pci_priv {
+struct sandbox_pci_emul_priv {
int dev_count;
};
int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,
- struct udevice **emulp)
+ struct udevice **containerp, struct udevice **emulp)
{
struct udevice *dev;
int ret;
- ret = pci_bus_find_devfn(bus, find_devfn, &dev);
+ *containerp = NULL;
+ ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(find_devfn), &dev);
if (ret) {
debug("%s: Could not find emulator for dev %x\n", __func__,
find_devfn);
return ret;
}
+ *containerp = dev;
- ret = device_find_first_child(dev, emulp);
- if (ret)
- return ret;
+ if (device_get_uclass_id(dev) == UCLASS_PCI_GENERIC) {
+ ret = device_find_first_child(dev, emulp);
+ if (ret)
+ return ret;
+ } else {
+ *emulp = dev;
+ }
return *emulp ? 0 : -ENODEV;
}
static int sandbox_pci_emul_post_probe(struct udevice *dev)
{
- struct sandbox_pci_priv *priv = dev->uclass->priv;
+ struct sandbox_pci_emul_priv *priv = dev->uclass->priv;
priv->dev_count++;
sandbox_set_enable_pci_map(true);
static int sandbox_pci_emul_pre_remove(struct udevice *dev)
{
- struct sandbox_pci_priv *priv = dev->uclass->priv;
+ struct sandbox_pci_emul_priv *priv = dev->uclass->priv;
priv->dev_count--;
sandbox_set_enable_pci_map(priv->dev_count > 0);
.name = "pci_emul",
.post_probe = sandbox_pci_emul_post_probe,
.pre_remove = sandbox_pci_emul_pre_remove,
- .priv_auto_alloc_size = sizeof(struct sandbox_pci_priv),
+ .priv_auto_alloc_size = sizeof(struct sandbox_pci_emul_priv),
};
if (ret)
goto error;
debug("%s: Match found: %s\n", __func__, drv->name);
- dev->driver_data = find_id->driver_data;
+ dev->driver_data = id->driver_data;
*devp = dev;
return 0;
}
struct udevice *dev;
ulong class;
+ if (!PCI_FUNC(bdf))
+ found_multi = false;
if (PCI_FUNC(bdf) && !found_multi)
continue;
/* Check only the first access, we don't expect problems */
if (!dev_of_valid(dev))
return 0;
- /*
- * We could read vendor, device, class if available. But for now we
- * just check the address.
- */
pplat = dev_get_parent_platdata(dev);
+
+ /* Extract vendor id and device id if available */
+ ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
+
+ /* Extract the devfn from fdt_pci_addr */
ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, "reg",
&addr);
-
if (ret) {
if (ret != -ENOENT)
return -EINVAL;
} else {
- /* extract the devfn from fdt_pci_addr */
pplat->devfn = addr.phys_hi & 0xff00;
}
return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
}
+int dm_pci_find_capability(struct udevice *dev, int cap)
+{
+ u16 status;
+ u8 header_type;
+ int ttl = PCI_FIND_CAP_TTL;
+ u8 id;
+ u16 ent;
+ u8 pos;
+
+ dm_pci_read_config16(dev, PCI_STATUS, &status);
+ if (!(status & PCI_STATUS_CAP_LIST))
+ return 0;
+
+ dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
+ if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
+ pos = PCI_CB_CAPABILITY_LIST;
+ else
+ pos = PCI_CAPABILITY_LIST;
+
+ dm_pci_read_config8(dev, pos, &pos);
+ while (ttl--) {
+ if (pos < PCI_STD_HEADER_SIZEOF)
+ break;
+ pos &= ~3;
+ dm_pci_read_config16(dev, pos, &ent);
+
+ id = ent & 0xff;
+ if (id == 0xff)
+ break;
+ if (id == cap)
+ return pos;
+ pos = (ent >> 8);
+ }
+
+ return 0;
+}
+
+int dm_pci_find_ext_capability(struct udevice *dev, int cap)
+{
+ u32 header;
+ int ttl;
+ int pos = PCI_CFG_SPACE_SIZE;
+
+ /* minimum 8 bytes per capability */
+ ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
+
+ dm_pci_read_config32(dev, pos, &header);
+ /*
+ * If we have no capabilities, this is indicated by cap ID,
+ * cap version and next pointer all being 0.
+ */
+ if (header == 0)
+ return 0;
+
+ while (ttl--) {
+ if (PCI_EXT_CAP_ID(header) == cap)
+ return pos;
+
+ pos = PCI_EXT_CAP_NEXT(header);
+ if (pos < PCI_CFG_SPACE_SIZE)
+ break;
+
+ dm_pci_read_config32(dev, pos, &header);
+ }
+
+ return 0;
+}
+
UCLASS_DRIVER(pci) = {
.id = UCLASS_PCI,
.name = "pci",
#include <inttypes.h>
#include <pci.h>
+#define FDT_DEV_INFO_CELLS 4
+#define FDT_DEV_INFO_SIZE (FDT_DEV_INFO_CELLS * sizeof(u32))
+
+#define SANDBOX_PCI_DEVFN(d, f) ((d << 3) | f)
+
+struct sandbox_pci_priv {
+ struct {
+ u16 vendor;
+ u16 device;
+ } vendev[256];
+};
+
static int sandbox_pci_write_config(struct udevice *bus, pci_dev_t devfn,
uint offset, ulong value,
enum pci_size_t size)
{
struct dm_pci_emul_ops *ops;
- struct udevice *emul;
+ struct udevice *container, *emul;
int ret;
- ret = sandbox_pci_get_emul(bus, devfn, &emul);
+ ret = sandbox_pci_get_emul(bus, devfn, &container, &emul);
if (ret)
return ret == -ENODEV ? 0 : ret;
ops = pci_get_emul_ops(emul);
enum pci_size_t size)
{
struct dm_pci_emul_ops *ops;
- struct udevice *emul;
+ struct udevice *container, *emul;
+ struct sandbox_pci_priv *priv = dev_get_priv(bus);
int ret;
/* Prepare the default response */
*valuep = pci_get_ff(size);
- ret = sandbox_pci_get_emul(bus, devfn, &emul);
- if (ret)
- return ret == -ENODEV ? 0 : ret;
+ ret = sandbox_pci_get_emul(bus, devfn, &container, &emul);
+ if (ret) {
+ if (!container) {
+ u16 vendor, device;
+
+ devfn = SANDBOX_PCI_DEVFN(PCI_DEV(devfn),
+ PCI_FUNC(devfn));
+ vendor = priv->vendev[devfn].vendor;
+ device = priv->vendev[devfn].device;
+ if (offset == PCI_VENDOR_ID && vendor)
+ *valuep = vendor;
+ else if (offset == PCI_DEVICE_ID && device)
+ *valuep = device;
+
+ return 0;
+ } else {
+ return ret == -ENODEV ? 0 : ret;
+ }
+ }
ops = pci_get_emul_ops(emul);
if (!ops || !ops->read_config)
return -ENOSYS;
return ops->read_config(emul, offset, valuep, size);
}
+static int sandbox_pci_probe(struct udevice *dev)
+{
+ struct sandbox_pci_priv *priv = dev_get_priv(dev);
+ const fdt32_t *cell;
+ u8 pdev, pfn, devfn;
+ int len;
+
+ cell = ofnode_get_property(dev_ofnode(dev), "sandbox,dev-info", &len);
+ if (!cell)
+ return 0;
+
+ if ((len % FDT_DEV_INFO_SIZE) == 0) {
+ int num = len / FDT_DEV_INFO_SIZE;
+ int i;
+
+ for (i = 0; i < num; i++) {
+ debug("dev info #%d: %02x %02x %04x %04x\n", i,
+ fdt32_to_cpu(cell[0]), fdt32_to_cpu(cell[1]),
+ fdt32_to_cpu(cell[2]), fdt32_to_cpu(cell[3]));
+
+ pdev = fdt32_to_cpu(cell[0]);
+ pfn = fdt32_to_cpu(cell[1]);
+ if (pdev > 31 || pfn > 7)
+ continue;
+ devfn = SANDBOX_PCI_DEVFN(pdev, pfn);
+ priv->vendev[devfn].vendor = fdt32_to_cpu(cell[2]);
+ priv->vendev[devfn].device = fdt32_to_cpu(cell[3]);
+
+ cell += FDT_DEV_INFO_CELLS;
+ }
+ }
+
+ return 0;
+}
+
static const struct dm_pci_ops sandbox_pci_ops = {
.read_config = sandbox_pci_read_config,
.write_config = sandbox_pci_write_config,
.id = UCLASS_PCI,
.of_match = sandbox_pci_ids,
.ops = &sandbox_pci_ops,
+ .probe = sandbox_pci_probe,
+ .priv_auto_alloc_size = sizeof(struct sandbox_pci_priv),
/* Attach an emulator if we can */
.child_post_bind = dm_scan_fdt_dev,
struct bmips_ram_priv {
void __iomem *regs;
+ u32 force_size;
const struct bmips_ram_hw *hw;
};
const struct bmips_ram_hw *hw = priv->hw;
info->base = 0x80000000;
- info->size = hw->get_ram_size(priv);
+ if (priv->force_size)
+ info->size = priv->force_size;
+ else
+ info->size = hw->get_ram_size(priv);
return 0;
}
if (!priv->regs)
return -EINVAL;
+ dev_read_u32(dev, "force-size", &priv->force_size);
+
priv->hw = hw;
return 0;
/**
* on_baudrate() - Update the actual baudrate when the env var changes
*
+ * @name: changed environment variable
+ * @value: new value of the environment variable
+ * @op: operation (create, overwrite, or delete)
+ * @flags: attributes of environment variable change,
+ * see flags H_* in include/search.h
+ *
* This will check for a valid baudrate and only apply it if valid.
+ *
+ * Return: 0 on success, 1 on error
*/
static int on_baudrate(const char *name, const char *value, enum env_op op,
int flags)
__attribute__((weak, alias("serial_null")));
serial_initfunc(atmel_serial_initialize);
-serial_initfunc(au1x00_serial_initialize);
serial_initfunc(mcf_serial_initialize);
serial_initfunc(mpc85xx_serial_initialize);
serial_initfunc(mpc8xx_serial_initialize);
void serial_initialize(void)
{
atmel_serial_initialize();
- au1x00_serial_initialize();
mcf_serial_initialize();
mpc85xx_serial_initialize();
mpc8xx_serial_initialize();
memcpy(in_req->buf, buffer, buffer_size);
in_req->length = buffer_size;
+ debug("Transferring 0x%x bytes\n", buffer_size);
usb_ep_dequeue(rockusb_func->in_ep, in_req);
ret = usb_ep_queue(rockusb_func->in_ep, in_req, 0);
if (ret)
csw->residue = cpu_to_be32(residue);
csw->status = status;
#ifdef DEBUG
- printcsw((char *)&csw);
+ printcsw((char *)csw);
#endif
return rockusb_tx_write((char *)csw, size);
}
+static void tx_handler_send_csw(struct usb_ep *ep, struct usb_request *req)
+{
+ struct f_rockusb *f_rkusb = get_rkusb();
+ int status = req->status;
+
+ if (status)
+ debug("status: %d ep '%s' trans: %d\n",
+ status, ep->name, req->actual);
+
+ /* Return back to default in_req complete function after sending CSW */
+ req->complete = rockusb_complete;
+ rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_GOOD, USB_BULK_CS_WRAP_LEN);
+}
+
static unsigned int rx_bytes_expected(struct usb_ep *ep)
{
struct f_rockusb *f_rkusb = get_rkusb();
return rx_remain;
}
+/* usb_request complete call back to handle upload image */
+static void tx_handler_ul_image(struct usb_ep *ep, struct usb_request *req)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(char, rbuffer, RKBLOCK_BUF_SIZE);
+ struct f_rockusb *f_rkusb = get_rkusb();
+ struct usb_request *in_req = rockusb_func->in_req;
+ int ret;
+
+ /* Print error status of previous transfer */
+ if (req->status)
+ debug("status: %d ep '%s' trans: %d len %d\n", req->status,
+ ep->name, req->actual, req->length);
+
+ /* On transfer complete reset in_req and feedback host with CSW_GOOD */
+ if (f_rkusb->ul_bytes >= f_rkusb->ul_size) {
+ in_req->length = 0;
+ in_req->complete = rockusb_complete;
+
+ rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_GOOD,
+ USB_BULK_CS_WRAP_LEN);
+ return;
+ }
+
+ /* Proceed with current chunk */
+ unsigned int transfer_size = f_rkusb->ul_size - f_rkusb->ul_bytes;
+
+ if (transfer_size > RKBLOCK_BUF_SIZE)
+ transfer_size = RKBLOCK_BUF_SIZE;
+ /* Read at least one block */
+ unsigned int blkcount = (transfer_size + f_rkusb->desc->blksz - 1) /
+ f_rkusb->desc->blksz;
+
+ debug("ul %x bytes, %x blks, read lba %x, ul_size:%x, ul_bytes:%x, ",
+ transfer_size, blkcount, f_rkusb->lba,
+ f_rkusb->ul_size, f_rkusb->ul_bytes);
+
+ int blks = blk_dread(f_rkusb->desc, f_rkusb->lba, blkcount, rbuffer);
+
+ if (blks != blkcount) {
+ printf("failed reading from device %s: %d\n",
+ f_rkusb->dev_type, f_rkusb->dev_index);
+ rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_FAIL,
+ USB_BULK_CS_WRAP_LEN);
+ return;
+ }
+ f_rkusb->lba += blkcount;
+ f_rkusb->ul_bytes += transfer_size;
+
+ /* Proceed with USB request */
+ memcpy(in_req->buf, rbuffer, transfer_size);
+ in_req->length = transfer_size;
+ in_req->complete = tx_handler_ul_image;
+ debug("Uploading 0x%x bytes\n", transfer_size);
+ usb_ep_dequeue(rockusb_func->in_ep, in_req);
+ ret = usb_ep_queue(rockusb_func->in_ep, in_req, 0);
+ if (ret)
+ printf("Error %d on queue\n", ret);
+}
+
/* usb_request complete call back to handle down load image */
static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req)
{
unsigned int buffer_size = req->actual;
transfer_size = f_rkusb->dl_size - f_rkusb->dl_bytes;
- if (!f_rkusb->desc) {
- char *type = f_rkusb->dev_type;
- int index = f_rkusb->dev_index;
-
- f_rkusb->desc = blk_get_dev(type, index);
- if (!f_rkusb->desc ||
- f_rkusb->desc->type == DEV_TYPE_UNKNOWN) {
- puts("invalid mmc device\n");
- rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_FAIL,
- USB_BULK_CS_WRAP_LEN);
- return;
- }
- }
if (req->status != 0) {
printf("Bad status: %d\n", req->status);
memcpy((void *)f_rkusb->buf, buffer, transfer_size);
f_rkusb->dl_bytes += transfer_size;
- int blks = 0, blkcnt = transfer_size / 512;
+ int blks = 0, blkcnt = transfer_size / f_rkusb->desc->blksz;
debug("dl %x bytes, %x blks, write lba %x, dl_size:%x, dl_bytes:%x, ",
transfer_size, blkcnt, f_rkusb->lba, f_rkusb->dl_size,
req->complete = rx_handler_command;
req->length = EP_BUFFER_SIZE;
f_rkusb->buf = f_rkusb->buf_head;
- printf("transfer 0x%x bytes done\n", f_rkusb->dl_size);
+ debug("transfer 0x%x bytes done\n", f_rkusb->dl_size);
f_rkusb->dl_size = 0;
rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_GOOD,
USB_BULK_CS_WRAP_LEN);
else
f_rkusb->buf = f_rkusb->buf_head;
- debug("remain %x bytes, %x sectors\n", req->length,
- req->length / 512);
+ debug("remain %x bytes, %lx sectors\n", req->length,
+ req->length / f_rkusb->desc->blksz);
}
req->actual = 0;
{
ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
sizeof(struct fsg_bulk_cb_wrap));
+ struct f_rockusb *f_rkusb = get_rkusb();
char emmc_id[] = "EMMC ";
printf("read storage id\n");
memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+
+ /* Prepare for sending subsequent CSW_GOOD */
+ f_rkusb->tag = cbw->tag;
+ f_rkusb->in_req->complete = tx_handler_send_csw;
+
rockusb_tx_write_str(emmc_id);
- rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length, CSW_GOOD,
- USB_BULK_CS_WRAP_LEN);
+}
+
+int __weak rk_get_bootrom_chip_version(unsigned int *chip_info, int size)
+{
+ return 0;
+}
+
+static void cb_get_chip_version(struct usb_ep *ep, struct usb_request *req)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+ sizeof(struct fsg_bulk_cb_wrap));
+ struct f_rockusb *f_rkusb = get_rkusb();
+ unsigned int chip_info[4], i;
+
+ memset(chip_info, 0, sizeof(chip_info));
+ rk_get_bootrom_chip_version(chip_info, 4);
+
+ /*
+ * Chip Version is a string saved in BOOTROM address space Little Endian
+ *
+ * Ex for rk3288: 0x33323041 0x32303134 0x30383133 0x56323030
+ * which brings: 320A20140813V200
+ *
+ * Note that memory version do invert MSB/LSB so printing the char
+ * buffer will show: A02341023180002V
+ */
+ printf("read chip version: ");
+ for (i = 0; i < 4; i++) {
+ printf("%c%c%c%c",
+ (chip_info[i] >> 24) & 0xFF,
+ (chip_info[i] >> 16) & 0xFF,
+ (chip_info[i] >> 8) & 0xFF,
+ (chip_info[i] >> 0) & 0xFF);
+ }
+ printf("\n");
+ memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+
+ /* Prepare for sending subsequent CSW_GOOD */
+ f_rkusb->tag = cbw->tag;
+ f_rkusb->in_req->complete = tx_handler_send_csw;
+
+ rockusb_tx_write((char *)chip_info, sizeof(chip_info));
+}
+
+static void cb_read_lba(struct usb_ep *ep, struct usb_request *req)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+ sizeof(struct fsg_bulk_cb_wrap));
+ struct f_rockusb *f_rkusb = get_rkusb();
+ int sector_count;
+
+ memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+ sector_count = (int)get_unaligned_be16(&cbw->CDB[7]);
+ f_rkusb->tag = cbw->tag;
+
+ if (!f_rkusb->desc) {
+ char *type = f_rkusb->dev_type;
+ int index = f_rkusb->dev_index;
+
+ f_rkusb->desc = blk_get_dev(type, index);
+ if (!f_rkusb->desc ||
+ f_rkusb->desc->type == DEV_TYPE_UNKNOWN) {
+ printf("invalid device \"%s\", %d\n", type, index);
+ rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_FAIL,
+ USB_BULK_CS_WRAP_LEN);
+ return;
+ }
+ }
+
+ f_rkusb->lba = get_unaligned_be32(&cbw->CDB[2]);
+ f_rkusb->ul_size = sector_count * f_rkusb->desc->blksz;
+ f_rkusb->ul_bytes = 0;
+
+ debug("require read %x bytes, %x sectors from lba %x\n",
+ f_rkusb->ul_size, sector_count, f_rkusb->lba);
+
+ if (f_rkusb->ul_size == 0) {
+ rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length,
+ CSW_FAIL, USB_BULK_CS_WRAP_LEN);
+ return;
+ }
+
+ /* Start right now sending first chunk */
+ tx_handler_ul_image(ep, req);
}
static void cb_write_lba(struct usb_ep *ep, struct usb_request *req)
memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
sector_count = (int)get_unaligned_be16(&cbw->CDB[7]);
+ f_rkusb->tag = cbw->tag;
+
+ if (!f_rkusb->desc) {
+ char *type = f_rkusb->dev_type;
+ int index = f_rkusb->dev_index;
+
+ f_rkusb->desc = blk_get_dev(type, index);
+ if (!f_rkusb->desc ||
+ f_rkusb->desc->type == DEV_TYPE_UNKNOWN) {
+ printf("invalid device \"%s\", %d\n", type, index);
+ rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_FAIL,
+ USB_BULK_CS_WRAP_LEN);
+ return;
+ }
+ }
+
f_rkusb->lba = get_unaligned_be32(&cbw->CDB[2]);
- f_rkusb->dl_size = sector_count * 512;
+ f_rkusb->dl_size = sector_count * f_rkusb->desc->blksz;
f_rkusb->dl_bytes = 0;
- f_rkusb->tag = cbw->tag;
+
debug("require write %x bytes, %x sectors to lba %x\n",
f_rkusb->dl_size, sector_count, f_rkusb->lba);
}
}
+static void cb_erase_lba(struct usb_ep *ep, struct usb_request *req)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+ sizeof(struct fsg_bulk_cb_wrap));
+ struct f_rockusb *f_rkusb = get_rkusb();
+ int sector_count, lba, blks;
+
+ memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+ sector_count = (int)get_unaligned_be16(&cbw->CDB[7]);
+ f_rkusb->tag = cbw->tag;
+
+ if (!f_rkusb->desc) {
+ char *type = f_rkusb->dev_type;
+ int index = f_rkusb->dev_index;
+
+ f_rkusb->desc = blk_get_dev(type, index);
+ if (!f_rkusb->desc ||
+ f_rkusb->desc->type == DEV_TYPE_UNKNOWN) {
+ printf("invalid device \"%s\", %d\n", type, index);
+ rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_FAIL,
+ USB_BULK_CS_WRAP_LEN);
+ return;
+ }
+ }
+
+ lba = get_unaligned_be32(&cbw->CDB[2]);
+
+ debug("require erase %x sectors from lba %x\n",
+ sector_count, lba);
+
+ blks = blk_derase(f_rkusb->desc, lba, sector_count);
+ if (blks != sector_count) {
+ printf("failed erasing device %s: %d\n", f_rkusb->dev_type,
+ f_rkusb->dev_index);
+ rockusb_tx_write_csw(f_rkusb->tag,
+ cbw->data_transfer_length, CSW_FAIL,
+ USB_BULK_CS_WRAP_LEN);
+ return;
+ }
+
+ rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length, CSW_GOOD,
+ USB_BULK_CS_WRAP_LEN);
+}
+
void __weak rkusb_set_reboot_flag(int flag)
{
struct f_rockusb *f_rkusb = get_rkusb();
},
{
.cmd = K_FW_LBA_READ_10,
- .cb = cb_not_support,
+ .cb = cb_read_lba,
},
{
.cmd = K_FW_LBA_WRITE_10,
},
{
.cmd = K_FW_GET_CHIP_VER,
- .cb = cb_not_support,
+ .cb = cb_get_chip_version,
},
{
.cmd = K_FW_LOW_FORMAT,
.cb = cb_not_support,
},
{
+ .cmd = K_FW_LBA_ERASE_10,
+ .cb = cb_erase_lba,
+ },
+ {
.cmd = K_FW_SESSION,
.cb = cb_not_support,
},
/* Avoid freeing memory when ep is still claimed */
if (dev->in_ep->driver_data) {
- free_ep_req(dev->in_ep, dev->in_req);
usb_ep_disable(dev->in_ep);
+ free_ep_req(dev->in_ep, dev->in_req);
dev->in_ep->driver_data = NULL;
}
if (dev->out_ep->driver_data) {
- usb_ep_free_request(dev->out_ep, dev->out_req);
usb_ep_disable(dev->out_ep);
+ usb_ep_free_request(dev->out_ep, dev->out_req);
dev->out_ep->driver_data = NULL;
}
#define gadget_is_dwc3(g) 0
#endif
-
-
-/*
- * CONFIG_USB_GADGET_SX2
- * CONFIG_USB_GADGET_AU1X00
- * ...
- */
-
/**
* usb_gadget_controller_number - support bcdDevice id convention
* @gadget: the controller being driven
help
HLCDC supports video output to an attached LCD panel.
+config LOGICORE_DP_TX
+ bool "Enable Logicore DP TX driver"
+ depends on DISPLAY
+ help
+ Enable the driver for the transmitter part of the Xilinx LogiCORE
+ DisplayPort, a IP core for Xilinx FPGAs that implements a DisplayPort
+ video interface as defined by VESA DisplayPort v1.2.
+
+ Note that this is a pure transmitter device, and has no display
+ capabilities by itself.
+
config VIDEO_BROADWELL_IGD
bool "Enable Intel Broadwell integrated graphics device"
depends on X86
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifdef CONFIG_DM
+obj-$(CONFIG_BACKLIGHT_GPIO) += backlight_gpio.o
+obj-$(CONFIG_BACKLIGHT_PWM) += pwm_backlight.o
+obj-$(CONFIG_CONSOLE_NORMAL) += console_normal.o
+obj-$(CONFIG_CONSOLE_ROTATION) += console_rotate.o
+obj-$(CONFIG_CONSOLE_TRUETYPE) += console_truetype.o fonts/
obj-$(CONFIG_DISPLAY) += display-uclass.o
obj-$(CONFIG_DM_VIDEO) += backlight-uclass.o
obj-$(CONFIG_DM_VIDEO) += panel-uclass.o simple_panel.o
obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o
obj-$(CONFIG_DM_VIDEO) += video_bmp.o
-obj-$(CONFIG_BACKLIGHT_PWM) += pwm_backlight.o
-obj-$(CONFIG_BACKLIGHT_GPIO) += backlight_gpio.o
-obj-$(CONFIG_CONSOLE_NORMAL) += console_normal.o
-obj-$(CONFIG_CONSOLE_ROTATION) += console_rotate.o
-obj-$(CONFIG_CONSOLE_TRUETYPE) += console_truetype.o fonts/
endif
-obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o
-obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o
+obj-${CONFIG_EXYNOS_FB} += exynos/
+obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
+obj-${CONFIG_VIDEO_STM32} += stm32/
+obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
+obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o
+obj-$(CONFIG_FORMIKE) += formike.o
obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
-obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
+obj-$(CONFIG_LD9040) += ld9040.o
+obj-$(CONFIG_LG4573) += lg4573.o
+obj-$(CONFIG_LOGICORE_DP_TX) += logicore_dp_tx.o
obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
-obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o
obj-$(CONFIG_S6E8AX0) += s6e8ax0.o
-obj-$(CONFIG_LD9040) += ld9040.o
+obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o
obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o
+obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o
obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
+obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
obj-$(CONFIG_VIDEO_EFI) += efi.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
+obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
+obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o
obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
-obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
-obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o
+obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
+obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o
obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
obj-$(CONFIG_VIDEO_VESA) += vesa.o
-obj-$(CONFIG_FORMIKE) += formike.o
-obj-$(CONFIG_LG4573) += lg4573.o
-obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
-obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
-obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
-obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
-obj-${CONFIG_EXYNOS_FB} += exynos/
-obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
-obj-${CONFIG_VIDEO_STM32} += stm32/
obj-y += bridge/
obj-y += sunxi/
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * logicore_dp_dpcd.h
+ *
+ * DPCD interface definition for XILINX LogiCore DisplayPort v6.1
+ * based on Xilinx dp_v3_1 driver sources
+ *
+ * (C) Copyright 2016
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ */
+
+#ifndef __GDSYS_LOGICORE_DP_DPCD_H__
+#define __GDSYS_LOGICORE_DP_DPCD_H__
+
+/* receiver capability field */
+#define DPCD_REV 0x00000
+#define DPCD_MAX_LINK_RATE 0x00001
+#define DPCD_MAX_LANE_COUNT 0x00002
+#define DPCD_MAX_DOWNSPREAD 0x00003
+#define DPCD_NORP_PWR_V_CAP 0x00004
+#define DPCD_DOWNSP_PRESENT 0x00005
+#define DPCD_ML_CH_CODING_CAP 0x00006
+#define DPCD_DOWNSP_COUNT_MSA_OUI 0x00007
+#define DPCD_RX_PORT0_CAP_0 0x00008
+#define DPCD_RX_PORT0_CAP_1 0x00009
+#define DPCD_RX_PORT1_CAP_0 0x0000A
+#define DPCD_RX_PORT1_CAP_1 0x0000B
+#define DPCD_I2C_SPEED_CTL_CAP 0x0000C
+#define DPCD_EDP_CFG_CAP 0x0000D
+#define DPCD_TRAIN_AUX_RD_INTERVAL 0x0000E
+#define DPCD_ADAPTER_CAP 0x0000F
+#define DPCD_FAUX_CAP 0x00020
+#define DPCD_MSTM_CAP 0x00021
+#define DPCD_NUM_AUDIO_EPS 0x00022
+#define DPCD_AV_GRANULARITY 0x00023
+#define DPCD_AUD_DEC_LAT_7_0 0x00024
+#define DPCD_AUD_DEC_LAT_15_8 0x00025
+#define DPCD_AUD_PP_LAT_7_0 0x00026
+#define DPCD_AUD_PP_LAT_15_8 0x00027
+#define DPCD_VID_INTER_LAT 0x00028
+#define DPCD_VID_PROG_LAT 0x00029
+#define DPCD_REP_LAT 0x0002A
+#define DPCD_AUD_DEL_INS_7_0 0x0002B
+#define DPCD_AUD_DEL_INS_15_8 0x0002C
+#define DPCD_AUD_DEL_INS_23_16 0x0002D
+#define DPCD_GUID 0x00030
+#define DPCD_RX_GTC_VALUE_7_0 0x00054
+#define DPCD_RX_GTC_VALUE_15_8 0x00055
+#define DPCD_RX_GTC_VALUE_23_16 0x00056
+#define DPCD_RX_GTC_VALUE_31_24 0x00057
+#define DPCD_RX_GTC_MSTR_REQ 0x00058
+#define DPCD_RX_GTC_FREQ_LOCK_DONE 0x00059
+#define DPCD_DOWNSP_0_CAP 0x00080
+#define DPCD_DOWNSP_1_CAP 0x00081
+#define DPCD_DOWNSP_2_CAP 0x00082
+#define DPCD_DOWNSP_3_CAP 0x00083
+#define DPCD_DOWNSP_0_DET_CAP 0x00080
+#define DPCD_DOWNSP_1_DET_CAP 0x00084
+#define DPCD_DOWNSP_2_DET_CAP 0x00088
+#define DPCD_DOWNSP_3_DET_CAP 0x0008C
+
+/* link configuration field */
+#define DPCD_LINK_BW_SET 0x00100
+#define DPCD_LANE_COUNT_SET 0x00101
+#define DPCD_TP_SET 0x00102
+#define DPCD_TRAINING_LANE0_SET 0x00103
+#define DPCD_TRAINING_LANE1_SET 0x00104
+#define DPCD_TRAINING_LANE2_SET 0x00105
+#define DPCD_TRAINING_LANE3_SET 0x00106
+#define DPCD_DOWNSPREAD_CTRL 0x00107
+#define DPCD_ML_CH_CODING_SET 0x00108
+#define DPCD_I2C_SPEED_CTL_SET 0x00109
+#define DPCD_EDP_CFG_SET 0x0010A
+#define DPCD_LINK_QUAL_LANE0_SET 0x0010B
+#define DPCD_LINK_QUAL_LANE1_SET 0x0010C
+#define DPCD_LINK_QUAL_LANE2_SET 0x0010D
+#define DPCD_LINK_QUAL_LANE3_SET 0x0010E
+#define DPCD_TRAINING_LANE0_1_SET2 0x0010F
+#define DPCD_TRAINING_LANE2_3_SET2 0x00110
+#define DPCD_MSTM_CTRL 0x00111
+#define DPCD_AUDIO_DELAY_7_0 0x00112
+#define DPCD_AUDIO_DELAY_15_8 0x00113
+#define DPCD_AUDIO_DELAY_23_6 0x00114
+#define DPCD_UPSTREAM_DEVICE_DP_PWR_NEED 0x00118
+#define DPCD_FAUX_MODE_CTRL 0x00120
+#define DPCD_FAUX_FORWARD_CH_DRIVE_SET 0x00121
+#define DPCD_BACK_CH_STATUS 0x00122
+#define DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT 0x00123
+#define DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME 0x00125
+#define DPCD_TX_GTC_VALUE_7_0 0x00154
+#define DPCD_TX_GTC_VALUE_15_8 0x00155
+#define DPCD_TX_GTC_VALUE_23_16 0x00156
+#define DPCD_TX_GTC_VALUE_31_24 0x00157
+#define DPCD_RX_GTC_VALUE_PHASE_SKEW_EN 0x00158
+#define DPCD_TX_GTC_FREQ_LOCK_DONE 0x00159
+#define DPCD_ADAPTER_CTRL 0x001A0
+#define DPCD_BRANCH_DEVICE_CTRL 0x001A1
+#define DPCD_PAYLOAD_ALLOCATE_SET 0x001C0
+#define DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x001C1
+#define DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x001C2
+
+/* link/sink status field */
+#define DPCD_SINK_COUNT 0x00200
+#define DPCD_DEVICE_SERVICE_IRQ 0x00201
+#define DPCD_STATUS_LANE_0_1 0x00202
+#define DPCD_STATUS_LANE_2_3 0x00203
+#define DPCD_LANE_ALIGN_STATUS_UPDATED 0x00204
+#define DPCD_SINK_STATUS 0x00205
+#define DPCD_ADJ_REQ_LANE_0_1 0x00206
+#define DPCD_ADJ_REQ_LANE_2_3 0x00207
+#define DPCD_TRAINING_SCORE_LANE_0 0x00208
+#define DPCD_TRAINING_SCORE_LANE_1 0x00209
+#define DPCD_TRAINING_SCORE_LANE_2 0x0020A
+#define DPCD_TRAINING_SCORE_LANE_3 0x0020B
+#define DPCD_ADJ_REQ_PC2 0x0020C
+#define DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT 0x0020D
+#define DPCD_SYMBOL_ERROR_COUNT_LANE_0 0x00210
+#define DPCD_SYMBOL_ERROR_COUNT_LANE_1 0x00212
+#define DPCD_SYMBOL_ERROR_COUNT_LANE_2 0x00214
+#define DPCD_SYMBOL_ERROR_COUNT_LANE_3 0x00216
+
+/* automated testing sub-field */
+#define DPCD_FAUX_FORWARD_CH_STATUS 0x00280
+#define DPCD_FAUX_BACK_CH_DRIVE_SET 0x00281
+#define DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL 0x00282
+#define DPCD_PAYLOAD_TABLE_UPDATE_STATUS 0x002C0
+#define DPCD_VC_PAYLOAD_ID_SLOT(slotnum) \
+ (DPCD_PAYLOAD_TABLE_UPDATE_STATUS + slotnum)
+
+/* sink control field */
+#define DPCD_SET_POWER_DP_PWR_VOLTAGE 0x00600
+
+/* sideband message buffers */
+#define DPCD_DOWN_REQ 0x01000
+#define DPCD_UP_REP 0x01200
+#define DPCD_DOWN_REP 0x01400
+#define DPCD_UP_REQ 0x01600
+
+/* event status indicator field */
+#define DPCD_SINK_COUNT_ESI 0x02002
+#define DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x02003
+#define DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x02004
+#define DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0 0x02005
+#define DPCD_SINK_LANE0_1_STATUS 0x0200C
+#define DPCD_SINK_LANE2_3_STATUS 0x0200D
+#define DPCD_SINK_ALIGN_STATUS_UPDATED_ESI 0x0200E
+#define DPCD_SINK_STATUS_ESI 0x0200F
+
+/*
+ * field addresses and sizes.
+ */
+#define DPCD_RECEIVER_CAP_FIELD_START DPCD_REV
+#define DPCD_RECEIVER_CAP_FIELD_SIZE 0x100
+#define DPCD_LINK_CFG_FIELD_START DPCD_LINK_BW_SET
+#define DPCD_LINK_CFG_FIELD_SIZE 0x100
+#define DPCD_LINK_SINK_STATUS_FIELD_START DPCD_SINK_COUNT
+#define DPCD_LINK_SINK_STATUS_FIELD_SIZE 0x17
+/* 0x00000: DPCD_REV */
+#define DPCD_REV_MNR_MASK 0x0F
+#define DPCD_REV_MJR_MASK 0xF0
+#define DPCD_REV_MJR_SHIFT 4
+/* 0x00001: MAX_LINK_RATE */
+#define DPCD_MAX_LINK_RATE_162GBPS 0x06
+#define DPCD_MAX_LINK_RATE_270GBPS 0x0A
+#define DPCD_MAX_LINK_RATE_540GBPS 0x14
+/* 0x00002: MAX_LANE_COUNT */
+#define DPCD_MAX_LANE_COUNT_MASK 0x1F
+#define DPCD_MAX_LANE_COUNT_1 0x01
+#define DPCD_MAX_LANE_COUNT_2 0x02
+#define DPCD_MAX_LANE_COUNT_4 0x04
+#define DPCD_TPS3_SUPPORT_MASK 0x40
+#define DPCD_ENHANCED_FRAME_SUPPORT_MASK 0x80
+/* 0x00003: MAX_DOWNSPREAD */
+#define DPCD_MAX_DOWNSPREAD_MASK 0x01
+#define DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK 0x40
+/* 0x00005: DOWNSP_PRESENT */
+#define DPCD_DOWNSP_PRESENT_MASK 0x01
+#define DPCD_DOWNSP_TYPE_MASK 0x06
+#define DPCD_DOWNSP_TYPE_SHIFT 1
+#define DPCD_DOWNSP_TYPE_DP 0x0
+#define DPCD_DOWNSP_TYPE_AVGA_ADVII 0x1
+#define DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP 0x2
+#define DPCD_DOWNSP_TYPE_OTHERS 0x3
+#define DPCD_DOWNSP_FORMAT_CONV_MASK 0x08
+#define DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK 0x10
+/* 0x00006, 0x00108: ML_CH_CODING_SUPPORT, ML_CH_CODING_SET */
+#define DPCD_ML_CH_CODING_MASK 0x01
+/* 0x00007: DOWNSP_COUNT_MSA_OUI */
+#define DPCD_DOWNSP_COUNT_MASK 0x0F
+#define DPCD_MSA_TIMING_PAR_IGNORED_MASK 0x40
+#define DPCD_OUI_SUPPORT_MASK 0x80
+/* 0x00008, 0x0000A: RX_PORT[0-1]_CAP_0 */
+#define DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK 0x02
+#define DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK 0x04
+/* 0x0000C, 0x00109: I2C_SPEED_CTL_CAP, I2C_SPEED_CTL_SET */
+#define DPCD_I2C_SPEED_CTL_NONE 0x00
+#define DPCD_I2C_SPEED_CTL_1KBIPS 0x01
+#define DPCD_I2C_SPEED_CTL_5KBIPS 0x02
+#define DPCD_I2C_SPEED_CTL_10KBIPS 0x04
+#define DPCD_I2C_SPEED_CTL_100KBIPS 0x08
+#define DPCD_I2C_SPEED_CTL_400KBIPS 0x10
+#define DPCD_I2C_SPEED_CTL_1MBIPS 0x20
+/* 0x0000E: TRAIN_AUX_RD_INTERVAL */
+#define DPCD_TRAIN_AUX_RD_INT_100_400US 0x00
+#define DPCD_TRAIN_AUX_RD_INT_4MS 0x01
+#define DPCD_TRAIN_AUX_RD_INT_8MS 0x02
+#define DPCD_TRAIN_AUX_RD_INT_12MS 0x03
+#define DPCD_TRAIN_AUX_RD_INT_16MS 0x04
+/* 0x00020: DPCD_FAUX_CAP */
+#define DPCD_FAUX_CAP_MASK 0x01
+/* 0x00021: MSTM_CAP */
+#define DPCD_MST_CAP_MASK 0x01
+/* 0x00080, 0x00081|4, 0x00082|8, 0x00083|C: DOWNSP_X_(DET_)CAP */
+#define DPCD_DOWNSP_X_CAP_TYPE_MASK 0x07
+#define DPCD_DOWNSP_X_CAP_TYPE_DP 0x0
+#define DPCD_DOWNSP_X_CAP_TYPE_AVGA 0x1
+#define DPCD_DOWNSP_X_CAP_TYPE_DVI 0x2
+#define DPCD_DOWNSP_X_CAP_TYPE_HDMI 0x3
+#define DPCD_DOWNSP_X_CAP_TYPE_OTHERS 0x4
+#define DPCD_DOWNSP_X_CAP_TYPE_DPPP 0x5
+#define DPCD_DOWNSP_X_CAP_HPD_MASK 0x80
+#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK 0xF0
+#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT 4
+#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60 0x1
+#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50 0x2
+#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60 0x3
+#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50 0x4
+#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60 0x5
+#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50 0x7
+/* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */
+#define DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK 0x03
+#define DPCD_DOWNSP_X_DCAP_MAX_BPC_8 0x0
+#define DPCD_DOWNSP_X_DCAP_MAX_BPC_10 0x1
+#define DPCD_DOWNSP_X_DCAP_MAX_BPC_12 0x2
+#define DPCD_DOWNSP_X_DCAP_MAX_BPC_16 0x3
+/* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */
+#define DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK 0x01
+#define DPCD_DOWNSP_X_DCAP_DVI_DL_MASK 0x02
+#define DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK 0x04
+
+/* link configuration field masks, shifts, and register values */
+/* 0x00100: DPCD_LINK_BW_SET */
+#define DPCD_LINK_BW_SET_162GBPS 0x06
+#define DPCD_LINK_BW_SET_270GBPS 0x0A
+#define DPCD_LINK_BW_SET_540GBPS 0x14
+/* 0x00101: LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET_MASK 0x1F
+#define DPCD_LANE_COUNT_SET_1 0x01
+#define DPCD_LANE_COUNT_SET_2 0x02
+#define DPCD_LANE_COUNT_SET_4 0x04
+#define DPCD_ENHANCED_FRAME_EN_MASK 0x80
+/* 0x00102: TP_SET */
+#define DPCD_TP_SEL_MASK 0x03
+#define DPCD_TP_SEL_OFF 0x0
+#define DPCD_TP_SEL_TP1 0x1
+#define DPCD_TP_SEL_TP2 0x2
+#define DPCD_TP_SEL_TP3 0x3
+#define DPCD_TP_SET_LQP_MASK 0x06
+#define DPCD_TP_SET_LQP_SHIFT 2
+#define DPCD_TP_SET_LQP_OFF 0x0
+#define DPCD_TP_SET_LQP_D102_TEST 0x1
+#define DPCD_TP_SET_LQP_SER_MES 0x2
+#define DPCD_TP_SET_LQP_PRBS7 0x3
+#define DPCD_TP_SET_REC_CLK_OUT_EN_MASK 0x10
+#define DPCD_TP_SET_SCRAMB_DIS_MASK 0x20
+#define DPCD_TP_SET_SE_COUNT_SEL_MASK 0xC0
+#define DPCD_TP_SET_SE_COUNT_SEL_SHIFT 6
+#define DPCD_TP_SET_SE_COUNT_SEL_DE_ISE 0x0
+#define DPCD_TP_SET_SE_COUNT_SEL_DE 0x1
+#define DPCD_TP_SET_SE_COUNT_SEL_ISE 0x2
+/* 0x00103-0x00106: TRAINING_LANE[0-3]_SET */
+#define DPCD_TRAINING_LANEX_SET_VS_MASK 0x03
+#define DPCD_TRAINING_LANEX_SET_MAX_VS_MASK 0x04
+#define DPCD_TRAINING_LANEX_SET_PE_MASK 0x18
+#define DPCD_TRAINING_LANEX_SET_PE_SHIFT 3
+#define DPCD_TRAINING_LANEX_SET_MAX_PE_MASK 0x20
+/* 0x00107: DOWNSPREAD_CTRL */
+#define DPCD_SPREAD_AMP_MASK 0x10
+#define DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK 0x80
+/* 0x00108: ML_CH_CODING_SET - Same as 0x00006: ML_CH_CODING_SUPPORT */
+/* 0x00109: I2C_SPEED_CTL_SET - Same as 0x0000C: I2C_SPEED_CTL_CAP */
+/* 0x0010F-0x00110: TRAINING_LANE[0_1-2_3]_SET2 */
+#define DPCD_TRAINING_LANE_0_2_SET_PC2_MASK 0x03
+#define DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK 0x04
+#define DPCD_TRAINING_LANE_1_3_SET_PC2_MASK 0x30
+#define DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT 4
+#define DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK 0x40
+/* 0x00111: MSTM_CTRL */
+#define DPCD_MST_EN_MASK 0x01
+#define DPCD_UP_REQ_EN_MASK 0x02
+#define DPCD_UP_IS_SRC_MASK 0x03
+
+/* link/sink status field masks, shifts, and register values */
+/* 0x00200: SINK_COUNT */
+#define DPCD_SINK_COUNT_LOW_MASK 0x3F
+#define DPCD_SINK_CP_READY_MASK 0x40
+#define DPCD_SINK_COUNT_HIGH_MASK 0x80
+#define DPCD_SINK_COUNT_HIGH_LOW_SHIFT 1
+/* 0x00202: STATUS_LANE_0_1 */
+#define DPCD_STATUS_LANE_0_CR_DONE_MASK 0x01
+#define DPCD_STATUS_LANE_0_CE_DONE_MASK 0x02
+#define DPCD_STATUS_LANE_0_SL_DONE_MASK 0x04
+#define DPCD_STATUS_LANE_1_CR_DONE_MASK 0x10
+#define DPCD_STATUS_LANE_1_CE_DONE_MASK 0x20
+#define DPCD_STATUS_LANE_1_SL_DONE_MASK 0x40
+/* 0x00202: STATUS_LANE_2_3 */
+#define DPCD_STATUS_LANE_2_CR_DONE_MASK 0x01
+#define DPCD_STATUS_LANE_2_CE_DONE_MASK 0x02
+#define DPCD_STATUS_LANE_2_SL_DONE_MASK 0x04
+#define DPCD_STATUS_LANE_3_CR_DONE_MASK 0x10
+#define DPCD_STATUS_LANE_3_CE_DONE_MASK 0x20
+#define DPCD_STATUS_LANE_3_SL_DONE_MASK 0x40
+/* 0x00204: LANE_ALIGN_STATUS_UPDATED */
+#define DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK \
+ 0x01
+#define DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK \
+ 0x40
+#define DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK \
+ 0x80
+/* 0x00205: SINK_STATUS */
+#define DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK 0x01
+#define DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK 0x02
+
+/* 0x00206, 0x00207: ADJ_REQ_LANE_[0,2]_[1,3] */
+#define DPCD_ADJ_REQ_LANE_0_2_VS_MASK 0x03
+#define DPCD_ADJ_REQ_LANE_0_2_PE_MASK 0x0C
+#define DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT 2
+#define DPCD_ADJ_REQ_LANE_1_3_VS_MASK 0x30
+#define DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT 4
+#define DPCD_ADJ_REQ_LANE_1_3_PE_MASK 0xC0
+#define DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT 6
+/* 0x0020C: ADJ_REQ_PC2 */
+#define DPCD_ADJ_REQ_PC2_LANE_0_MASK 0x03
+#define DPCD_ADJ_REQ_PC2_LANE_1_MASK 0x0C
+#define DPCD_ADJ_REQ_PC2_LANE_1_SHIFT 2
+#define DPCD_ADJ_REQ_PC2_LANE_2_MASK 0x30
+#define DPCD_ADJ_REQ_PC2_LANE_2_SHIFT 4
+#define DPCD_ADJ_REQ_PC2_LANE_3_MASK 0xC0
+#define DPCD_ADJ_REQ_PC2_LANE_3_SHIFT 6
+
+#endif /* __GDSYS_LOGICORE_DP_DPCD_H__ */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * logicore_dp_tx.c
+ *
+ * Driver for XILINX LogiCore DisplayPort v6.1 TX (Source)
+ * based on Xilinx dp_v3_1 driver sources, updated to dp_v4_0
+ *
+ * (C) Copyright 2016
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <display.h>
+#include <dm.h>
+#include <errno.h>
+
+#include "axi.h"
+#include "logicore_dp_dpcd.h"
+#include "logicore_dp_tx.h"
+#include "logicore_dp_tx_regif.h"
+
+/* Default AXI clock frequency value */
+#define S_AXI_CLK_DEFAULT 100000000
+
+/* Default DP phy clock value */
+#define PHY_CLOCK_SELECT_DEFAULT PHY_CLOCK_SELECT_540GBPS
+
+/* The maximum voltage swing level is 3 */
+#define MAXIMUM_VS_LEVEL 3
+/* The maximum pre-emphasis level is 3 */
+#define MAXIMUM_PE_LEVEL 3
+
+/* Error out if an AUX request yields a defer reply more than 50 times */
+#define AUX_MAX_DEFER_COUNT 50
+/* Error out if an AUX request times out more than 50 times awaiting a reply */
+#define AUX_MAX_TIMEOUT_COUNT 50
+/* Error out if checking for a connected device times out more than 50 times */
+#define IS_CONNECTED_MAX_TIMEOUT_COUNT 50
+
+/**
+ * enum link_training_states - States for link training state machine
+ * @TS_CLOCK_RECOVERY: State for clock recovery
+ * @TS_CHANNEL_EQUALIZATION: State for channel equalization
+ * @TS_ADJUST_LINK_RATE: State where link rate is reduced in reaction to
+ * failed link training
+ * @TS_ADJUST_LANE_COUNT: State where lane count is reduced in reaction to
+ * failed link training
+ * @TS_FAILURE: State of link training failure
+ * @TS_SUCCESS:: State for successfully completed link training
+ */
+enum link_training_states {
+ TS_CLOCK_RECOVERY,
+ TS_CHANNEL_EQUALIZATION,
+ TS_ADJUST_LINK_RATE,
+ TS_ADJUST_LANE_COUNT,
+ TS_FAILURE,
+ TS_SUCCESS
+};
+
+/**
+ * struct aux_transaction - Description of an AUX channel transaction
+ * @cmd_code: Command code of the transaction
+ * @num_bytes: The number of bytes in the transaction's payload data
+ * @address: The DPCD address of the transaction
+ * @data: Payload data of the AUX channel transaction
+ */
+struct aux_transaction {
+ u16 cmd_code;
+ u8 num_bytes;
+ u32 address;
+ u8 *data;
+};
+
+/**
+ * struct main_stream_attributes - Main stream attributes
+ * @pixel_clock_hz: Pixel clock of the stream (in Hz)
+ * @misc_0: Miscellaneous stream attributes 0 as specified
+ * by the DisplayPort 1.2 specification
+ * @misc_1: Miscellaneous stream attributes 1 as specified
+ * by the DisplayPort 1.2 specification
+ * @n_vid: N value for the video stream
+ * @m_vid: M value used to recover the video clock from the
+ * link clock
+ * @user_pixel_width: Width of the user data input port
+ * @data_per_lane: Used to translate the number of pixels per line
+ * to the native internal 16-bit datapath
+ * @avg_bytes_per_tu: Average number of bytes per transfer unit,
+ * scaled up by a factor of 1000
+ * @transfer_unit_size: Size of the transfer unit in the framing logic
+ * In MST mode, this is also the number of time
+ * slots that are alloted in the payload ID table
+ * @init_wait: Number of initial wait cycles at the start of a
+ * new line by the framing logic
+ * @bits_per_color: Bits per color component
+ * @component_format: The component format currently in use by the
+ * video stream
+ * @dynamic_range: The dynamic range currently in use by the video
+ * stream
+ * @y_cb_cr_colorimetry: The YCbCr colorimetry currently in use by the
+ * video stream
+ * @synchronous_clock_mode: Synchronous clock mode is currently in use by
+ * the video stream
+ * @override_user_pixel_width: If set to 1, the value stored for
+ * user_pixel_width will be used as the pixel width
+ * @h_start: Horizontal blank start (pixels)
+ * @h_active: Horizontal active resolution (pixels)
+ * @h_sync_width: Horizontal sync width (pixels)
+ * @h_total: Horizontal total (pixels)
+ * @h_sync_polarity: Horizontal sync polarity (0=neg|1=pos)
+ * @v_start: Vertical blank start (in lines)
+ * @v_active: Vertical active resolution (lines)
+ * @v_sync_width: Vertical sync width (lines)
+ * @v_total: Vertical total (lines)
+ * @v_sync_polarity: Vertical sync polarity (0=neg|1=pos)
+ *
+ * All porch parameters have been removed, because our videodata is
+ * hstart/vstart based, and there is no benefit in keeping the porches
+ */
+struct main_stream_attributes {
+ u32 pixel_clock_hz;
+ u32 misc_0;
+ u32 misc_1;
+ u32 n_vid;
+ //u32 m_vid;
+ u32 user_pixel_width;
+ u32 data_per_lane;
+ u32 avg_bytes_per_tu;
+ u32 transfer_unit_size;
+ u32 init_wait;
+ u32 bits_per_color;
+ u8 component_format;
+ u8 dynamic_range;
+ u8 y_cb_cr_colorimetry;
+ u8 synchronous_clock_mode;
+ u8 override_user_pixel_width;
+ u32 h_start;
+ u16 h_active;
+ u16 h_sync_width;
+ u16 h_total;
+ bool h_sync_polarity;
+ u32 v_start;
+ u16 v_active;
+ u16 v_sync_width;
+ u16 v_total;
+ bool v_sync_polarity;
+};
+
+/**
+ * struct link_config - Description of link configuration
+ * @lane_count: Currently selected lane count for this link
+ * @link_rate: Currently selected link rate for this link
+ * @scrambler_en: Flag to determine whether the scrambler is
+ * enabled for this link
+ * @enhanced_framing_mode: Flag to determine whether enhanced framing
+ * mode is active for this link
+ * @max_lane_count: Maximum lane count for this link
+ * @max_link_rate: Maximum link rate for this link
+ * @support_enhanced_framing_mode: Flag to indicate whether the link supports
+ * enhanced framing mode
+ * @vs_level: Voltage swing for each lane
+ * @pe_level: Pre-emphasis/cursor level for each lane
+ */
+struct link_config {
+ u8 lane_count;
+ u8 link_rate;
+ bool scrambler_en;
+ bool enhanced_framing_mode;
+ u8 max_lane_count;
+ u8 max_link_rate;
+ bool support_enhanced_framing_mode;
+ u8 vs_level;
+ u8 pe_level;
+};
+
+/**
+ * struct dp_tx - Private data structure of LogiCore DP TX devices
+ *
+ * @base: Address of register base of device
+ * @s_axi_clk: The AXI clock frequency in Hz
+ * @train_adaptive: Use adaptive link trainig (i.e. successively reduce
+ * link rate and/or lane count) for this device
+ * @max_link_rate: Maximum link rate for this device
+ * @max_lane_count: Maximum lane count for this device
+ * @dpcd_rx_caps: RX device's status registers, see below
+ * @lane_status_ajd_reqs: Lane status and adjustment requests information for
+ * this device
+ * @link_config: The link configuration for this device
+ * @main_stream_attributes: MSA set for this device
+ *
+ * dpcd_rx_caps is a raw read of the RX device's status registers. The first 4
+ * bytes correspond to the lane status associated with clock recovery, channel
+ * equalization, symbol lock, and interlane alignment. The remaining 2 bytes
+ * represent the pre-emphasis and voltage swing level adjustments requested by
+ * the RX device.
+ */
+struct dp_tx {
+ u32 base;
+ u32 s_axi_clk;
+ bool train_adaptive;
+ u8 max_link_rate;
+ u8 max_lane_count;
+ u8 dpcd_rx_caps[16];
+ u8 lane_status_ajd_reqs[6];
+ struct link_config link_config;
+ struct main_stream_attributes main_stream_attributes;
+};
+
+/*
+ * Internal API
+ */
+
+/**
+ * get_reg() - Read a register of a LogiCore DP TX device
+ * @dev: The LogiCore DP TX device in question
+ * @reg: The offset of the register to read
+ *
+ * Return: The read register value
+ */
+static u32 get_reg(struct udevice *dev, u32 reg)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ u32 value = 0;
+ int res;
+
+ /* TODO(mario.six@gdsys.cc): error handling */
+ res = axi_read(dev->parent, dp_tx->base + reg, &value, AXI_SIZE_32);
+ if (res < 0)
+ printf("%s() failed; res = %d\n", __func__, res);
+
+ return value;
+}
+
+/**
+ * set_reg() - Write a register of a LogiCore DP TX device
+ * @dev: The LogiCore DP TX device in question
+ * @reg: The offset of the register to write
+ * @value: The value to write to the register
+ */
+static void set_reg(struct udevice *dev, u32 reg, u32 value)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+
+ axi_write(dev->parent, dp_tx->base + reg, &value, AXI_SIZE_32);
+}
+
+/**
+ * is_connected() - Check if there is a connected RX device
+ * @dev: The LogiCore DP TX device in question
+ *
+ * The Xilinx original calls msleep_interruptible at least once, ignoring
+ * status.
+ *
+ * Return: true if a connected RX device was detected, false otherwise
+ */
+static bool is_connected(struct udevice *dev)
+{
+ u8 retries = 0;
+
+ do {
+ int status = get_reg(dev, REG_INTERRUPT_SIG_STATE) &
+ INTERRUPT_SIG_STATE_HPD_STATE_MASK;
+ if (status)
+ return true;
+
+ udelay(1000);
+ } while (retries++ < IS_CONNECTED_MAX_TIMEOUT_COUNT);
+
+ return false;
+}
+
+/**
+ * wait_phy_ready() - Wait for the DisplayPort PHY to come out of reset
+ * @dev: The LogiCore DP TX device in question
+ * @mask: Bit mask specifying which bit in the status register should be waited
+ * for
+ *
+ * Return: 0 if wait succeeded, -ve if error occurred
+ */
+static int wait_phy_ready(struct udevice *dev, u32 mask)
+{
+ u16 timeout = 20000;
+ u32 phy_status;
+
+ /* Wait until the PHY is ready. */
+ do {
+ phy_status = get_reg(dev, REG_PHY_STATUS) & mask;
+
+ /* Protect against an infinite loop. */
+ if (!timeout--)
+ return -ETIMEDOUT;
+
+ udelay(20);
+ } while (phy_status != mask);
+
+ return 0;
+}
+
+/* AUX channel access */
+
+/**
+ * aux_wait_ready() - Wait until another request is no longer in progress
+ * @dev: The LogiCore DP TX device in question
+ *
+ * Return: 0 if wait succeeded, -ve if error occurred
+ */
+static int aux_wait_ready(struct udevice *dev)
+{
+ int status;
+ u32 timeout = 100;
+
+ /* Wait until the DisplayPort TX core is ready. */
+ do {
+ status = get_reg(dev, REG_INTERRUPT_SIG_STATE);
+
+ /* Protect against an infinite loop. */
+ if (!timeout--)
+ return -ETIMEDOUT;
+ udelay(20);
+ } while (status & REPLY_STATUS_REPLY_IN_PROGRESS_MASK);
+
+ return 0;
+}
+
+/**
+ * aux_wait_reply() - Wait for reply on AUX channel
+ * @dev: The LogiCore DP TX device in question
+ *
+ * Wait for a reply indicating that the most recent AUX request
+ * has been received by the RX device.
+ *
+ * Return: 0 if wait succeeded, -ve if error occurred
+ */
+static int aux_wait_reply(struct udevice *dev)
+{
+ u32 timeout = 100;
+
+ while (timeout > 0) {
+ int status = get_reg(dev, REG_REPLY_STATUS);
+
+ /* Check for error. */
+ if (status & REPLY_STATUS_REPLY_ERROR_MASK)
+ return -ETIMEDOUT;
+
+ /* Check for a reply. */
+ if ((status & REPLY_STATUS_REPLY_RECEIVED_MASK) &&
+ !(status &
+ REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) &&
+ !(status &
+ REPLY_STATUS_REPLY_IN_PROGRESS_MASK)) {
+ return 0;
+ }
+
+ timeout--;
+ udelay(20);
+ }
+
+ return -ETIMEDOUT;
+}
+
+/**
+ * aux_request_send() - Send request on the AUX channel
+ * @dev: The LogiCore DP TX device in question
+ * @request: The request to send
+ *
+ * Submit the supplied AUX request to the RX device over the AUX
+ * channel by writing the command, the destination address, (the write buffer
+ * for write commands), and the data size to the DisplayPort TX core.
+ *
+ * This is the lower-level sending routine, which is called by aux_request().
+ *
+ * Return: 0 if request was sent successfully, -ve on error
+ */
+static int aux_request_send(struct udevice *dev,
+ struct aux_transaction *request)
+{
+ u32 timeout_count;
+ int status;
+ u8 index;
+
+ /* Ensure that any pending AUX transactions have completed. */
+ timeout_count = 0;
+ do {
+ status = get_reg(dev, REG_REPLY_STATUS);
+
+ udelay(20);
+ timeout_count++;
+ if (timeout_count >= AUX_MAX_TIMEOUT_COUNT)
+ return -ETIMEDOUT;
+ } while ((status & REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) ||
+ (status & REPLY_STATUS_REPLY_IN_PROGRESS_MASK));
+
+ set_reg(dev, REG_AUX_ADDRESS, request->address);
+
+ if (request->cmd_code == AUX_CMD_WRITE ||
+ request->cmd_code == AUX_CMD_I2C_WRITE ||
+ request->cmd_code == AUX_CMD_I2C_WRITE_MOT) {
+ /* Feed write data into the DisplayPort TX core's write FIFO. */
+ for (index = 0; index < request->num_bytes; index++) {
+ set_reg(dev,
+ REG_AUX_WRITE_FIFO, request->data[index]);
+ }
+ }
+
+ /* Submit the command and the data size. */
+ set_reg(dev, REG_AUX_CMD,
+ ((request->cmd_code << AUX_CMD_SHIFT) |
+ ((request->num_bytes - 1) &
+ AUX_CMD_NBYTES_TRANSFER_MASK)));
+
+ /* Check for a reply from the RX device to the submitted request. */
+ status = aux_wait_reply(dev);
+ if (status)
+ /* Waiting for a reply timed out. */
+ return -ETIMEDOUT;
+
+ /* Analyze the reply. */
+ status = get_reg(dev, REG_AUX_REPLY_CODE);
+ if (status == AUX_REPLY_CODE_DEFER ||
+ status == AUX_REPLY_CODE_I2C_DEFER) {
+ /* The request was deferred. */
+ return -EAGAIN;
+ } else if ((status == AUX_REPLY_CODE_NACK) ||
+ (status == AUX_REPLY_CODE_I2C_NACK)) {
+ /* The request was not acknowledged. */
+ return -EIO;
+ }
+
+ /* The request was acknowledged. */
+
+ if (request->cmd_code == AUX_CMD_READ ||
+ request->cmd_code == AUX_CMD_I2C_READ ||
+ request->cmd_code == AUX_CMD_I2C_READ_MOT) {
+ /* Wait until all data has been received. */
+ timeout_count = 0;
+ do {
+ status = get_reg(dev, REG_REPLY_DATA_COUNT);
+
+ udelay(100);
+ timeout_count++;
+ if (timeout_count >= AUX_MAX_TIMEOUT_COUNT)
+ return -ETIMEDOUT;
+ } while (status != request->num_bytes);
+
+ /* Obtain the read data from the reply FIFO. */
+ for (index = 0; index < request->num_bytes; index++)
+ request->data[index] = get_reg(dev, REG_AUX_REPLY_DATA);
+ }
+
+ return 0;
+}
+
+/**
+ * aux_request() - Submit request on the AUX channel
+ * @dev: The LogiCore DP TX device in question
+ * @request: The request to submit
+ *
+ * Submit the supplied AUX request to the RX device over the AUX
+ * channel. If waiting for a reply times out, or if the DisplayPort TX core
+ * indicates that the request was deferred, the request is sent again (up to a
+ * maximum specified by AUX_MAX_DEFER_COUNT|AUX_MAX_TIMEOUT_COUNT).
+ *
+ * Return: 0 if request was submitted successfully, -ve on error
+ */
+static int aux_request(struct udevice *dev, struct aux_transaction *request)
+{
+ u32 defer_count = 0;
+ u32 timeout_count = 0;
+
+ while ((defer_count < AUX_MAX_DEFER_COUNT) &&
+ (timeout_count < AUX_MAX_TIMEOUT_COUNT)) {
+ int status = aux_wait_ready(dev);
+
+ if (status) {
+ /* The RX device isn't ready yet. */
+ timeout_count++;
+ continue;
+ }
+
+ status = aux_request_send(dev, request);
+ if (status == -EAGAIN) {
+ /* The request was deferred. */
+ defer_count++;
+ } else if (status == -ETIMEDOUT) {
+ /* Waiting for a reply timed out. */
+ timeout_count++;
+ } else {
+ /*
+ * -EIO indicates that the request was NACK'ed,
+ * 0 indicates that the request was ACK'ed.
+ */
+ return status;
+ }
+
+ udelay(100);
+ }
+
+ /* The request was not successfully received by the RX device. */
+ return -ETIMEDOUT;
+}
+
+/**
+ * aux_common() - Common (read/write) AUX communication transmission
+ * @dev: The LogiCore DP TX device in question
+ * @cmd_type: Command code of the transaction
+ * @address: The DPCD address of the transaction
+ * @num_bytes: Number of bytes in the payload data
+ * @data: The payload data of the AUX command
+ *
+ * Common sequence of submitting an AUX command for AUX read, AUX write,
+ * I2C-over-AUX read, and I2C-over-AUX write transactions. If required, the
+ * reads and writes are split into multiple requests, each acting on a maximum
+ * of 16 bytes.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+static int aux_common(struct udevice *dev, u32 cmd_type, u32 address,
+ u32 num_bytes, u8 *data)
+{
+ struct aux_transaction request;
+ u32 bytes_left;
+
+ /*
+ * Set the start address for AUX transactions. For I2C transactions,
+ * this is the address of the I2C bus.
+ */
+ request.address = address;
+
+ bytes_left = num_bytes;
+ while (bytes_left) {
+ int status;
+
+ request.cmd_code = cmd_type;
+
+ if (cmd_type == AUX_CMD_READ ||
+ cmd_type == AUX_CMD_WRITE) {
+ /* Increment address for normal AUX transactions. */
+ request.address = address + (num_bytes - bytes_left);
+ }
+
+ /* Increment the pointer to the supplied data buffer. */
+ request.data = &data[num_bytes - bytes_left];
+
+ request.num_bytes = (bytes_left > 16) ? 16 : bytes_left;
+ bytes_left -= request.num_bytes;
+
+ if (cmd_type == AUX_CMD_I2C_READ && bytes_left) {
+ /*
+ * Middle of a transaction I2C read request. Override
+ * the command code that was set to cmd_type.
+ */
+ request.cmd_code = AUX_CMD_I2C_READ_MOT;
+ } else if ((cmd_type == AUX_CMD_I2C_WRITE) && bytes_left) {
+ /*
+ * Middle of a transaction I2C write request. Override
+ * the command code that was set to cmd_type.
+ */
+ request.cmd_code = AUX_CMD_I2C_WRITE_MOT;
+ }
+
+ status = aux_request(dev, &request);
+ if (status)
+ return status;
+ }
+
+ return 0;
+}
+
+/**
+ * aux_read() - Issue AUX read request
+ * @dev: The LogiCore DP TX device in question
+ * @dpcd_address: The DPCD address to read from
+ * @bytes_to_read: Number of bytes to read
+ * @read_data: Buffer to receive the read data
+ *
+ * Issue a read request over the AUX channel that will read from the RX
+ * device's DisplayPort Configuration data (DPCD) address space. The read
+ * message will be divided into multiple transactions which read a maximum of
+ * 16 bytes each.
+ *
+ * Return: 0 if read operation was successful, -ve on error
+ */
+static int aux_read(struct udevice *dev, u32 dpcd_address, u32 bytes_to_read,
+ void *read_data)
+{
+ int status;
+
+ if (!is_connected(dev))
+ return -ENODEV;
+
+ /* Send AUX read transaction. */
+ status = aux_common(dev, AUX_CMD_READ, dpcd_address,
+ bytes_to_read, (u8 *)read_data);
+
+ return status;
+}
+
+/**
+ * aux_write() - Issue AUX write request
+ * @dev: The LogiCore DP TX device in question
+ * @dpcd_address: The DPCD address to write to
+ * @bytes_to_write: Number of bytes to write
+ * @write_data: Buffer containig data to be written
+ *
+ * Issue a write request over the AUX channel that will write to
+ * the RX device's DisplayPort Configuration data (DPCD) address space. The
+ * write message will be divided into multiple transactions which write a
+ * maximum of 16 bytes each.
+ *
+ * Return: 0 if write operation was successful, -ve on error
+ */
+static int aux_write(struct udevice *dev, u32 dpcd_address, u32 bytes_to_write,
+ void *write_data)
+{
+ int status;
+
+ if (!is_connected(dev))
+ return -ENODEV;
+
+ /* Send AUX write transaction. */
+ status = aux_common(dev, AUX_CMD_WRITE, dpcd_address,
+ bytes_to_write, (u8 *)write_data);
+
+ return status;
+}
+
+/* Core initialization */
+
+/**
+ * initialize() - Initialize a LogiCore DP TX device
+ * @dev: The LogiCore DP TX device in question
+ *
+ * Return: Always 0
+ */
+static int initialize(struct udevice *dev)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ u32 val;
+ u32 phy_config;
+ unsigned int k;
+
+ /* place the PHY (and GTTXRESET) into reset. */
+ phy_config = get_reg(dev, REG_PHY_CONFIG);
+ set_reg(dev, REG_PHY_CONFIG, phy_config | PHY_CONFIG_GT_ALL_RESET_MASK);
+
+ /* reset the video streams and AUX logic. */
+ set_reg(dev, REG_SOFT_RESET,
+ SOFT_RESET_VIDEO_STREAM_ALL_MASK |
+ SOFT_RESET_AUX_MASK);
+
+ /* disable the DisplayPort TX core. */
+ set_reg(dev, REG_ENABLE, 0);
+
+ /* set the clock divider. */
+ val = get_reg(dev, REG_AUX_CLK_DIVIDER);
+ val &= ~AUX_CLK_DIVIDER_VAL_MASK;
+ val |= dp_tx->s_axi_clk / 1000000;
+ set_reg(dev, REG_AUX_CLK_DIVIDER, val);
+
+ /* set the DisplayPort TX core's clock speed. */
+ set_reg(dev, REG_PHY_CLOCK_SELECT, PHY_CLOCK_SELECT_DEFAULT);
+
+ /* bring the PHY (and GTTXRESET) out of reset. */
+ set_reg(dev, REG_PHY_CONFIG,
+ phy_config & ~PHY_CONFIG_GT_ALL_RESET_MASK);
+
+ /* enable the DisplayPort TX core. */
+ set_reg(dev, REG_ENABLE, 1);
+
+ /* Unmask Hot-Plug-Detect (HPD) interrupts. */
+ set_reg(dev, REG_INTERRUPT_MASK,
+ ~INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK &
+ ~INTERRUPT_MASK_HPD_EVENT_MASK &
+ ~INTERRUPT_MASK_HPD_IRQ_MASK);
+
+ for (k = 0; k < 4; k++) {
+ /* Disable pre-cursor levels. */
+ set_reg(dev, REG_PHY_PRECURSOR_LANE_0 + 4 * k, 0);
+
+ /* Write default voltage swing levels to the TX registers. */
+ set_reg(dev, REG_PHY_VOLTAGE_DIFF_LANE_0 + 4 * k, 0);
+
+ /* Write default pre-emphasis levels to the TX registers. */
+ set_reg(dev, REG_PHY_POSTCURSOR_LANE_0 + 4 * k, 0);
+ }
+
+ return 0;
+}
+
+/**
+ * is_link_rate_valid() - Check if given link rate is valif for device
+ * @dev: The LogiCore DP TX device in question
+ * @link_rate: The link rate to be checked for validity
+ *
+ * Return: true if he supplied link rate is valid, false otherwise
+ */
+static bool is_link_rate_valid(struct udevice *dev, u8 link_rate)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ bool valid = true;
+
+ if (link_rate != LINK_BW_SET_162GBPS &&
+ link_rate != LINK_BW_SET_270GBPS &&
+ link_rate != LINK_BW_SET_540GBPS)
+ valid = false;
+ else if (link_rate > dp_tx->link_config.max_link_rate)
+ valid = false;
+
+ return valid;
+}
+
+/**
+ * is_lane_count_valid() - Check if given lane count is valif for device
+ * @dev: The LogiCore DP TX device in question
+ * @lane_count: The lane count to be checked for validity
+ *
+ * Return: true if he supplied lane count is valid, false otherwise
+ */
+static bool is_lane_count_valid(struct udevice *dev, u8 lane_count)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ bool valid = true;
+
+ if (lane_count != LANE_COUNT_SET_1 &&
+ lane_count != LANE_COUNT_SET_2 &&
+ lane_count != LANE_COUNT_SET_4)
+ valid = false;
+ else if (lane_count > dp_tx->link_config.max_lane_count)
+ valid = false;
+
+ return valid;
+}
+
+/**
+ * get_rx_capabilities() - Check if capabilities of RX device are valid for TX
+ * device
+ * @dev: The LogiCore DP TX device in question
+ *
+ * Return: 0 if the capabilities of the RX device are valid for the TX device,
+ * -ve if not, of an error occurred during capability determination
+ */
+static int get_rx_capabilities(struct udevice *dev)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ int status;
+ u8 rx_max_link_rate;
+ u8 rx_max_lane_count;
+
+ if (!is_connected(dev))
+ return -ENODEV;
+
+ status = aux_read(dev, DPCD_RECEIVER_CAP_FIELD_START, 16,
+ dp_tx->dpcd_rx_caps);
+ if (status)
+ return -EIO;
+
+ rx_max_link_rate = dp_tx->dpcd_rx_caps[DPCD_MAX_LINK_RATE];
+ rx_max_lane_count = dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] &
+ DPCD_MAX_LANE_COUNT_MASK;
+
+ dp_tx->link_config.max_link_rate =
+ (rx_max_link_rate > dp_tx->max_link_rate) ?
+ dp_tx->max_link_rate : rx_max_link_rate;
+ if (!is_link_rate_valid(dev, rx_max_link_rate))
+ return -EINVAL;
+
+ dp_tx->link_config.max_lane_count =
+ (rx_max_lane_count > dp_tx->max_lane_count) ?
+ dp_tx->max_lane_count : rx_max_lane_count;
+ if (!is_lane_count_valid(dev, rx_max_lane_count))
+ return -EINVAL;
+
+ dp_tx->link_config.support_enhanced_framing_mode =
+ dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] &
+ DPCD_ENHANCED_FRAME_SUPPORT_MASK;
+
+ return 0;
+}
+
+/**
+ * enable_main_link() - Switch on main link for a device
+ * @dev: The LogiCore DP TX device in question
+ */
+static void enable_main_link(struct udevice *dev)
+{
+ /* reset the scrambler. */
+ set_reg(dev, REG_FORCE_SCRAMBLER_RESET, 0x1);
+
+ /* enable the main stream. */
+ set_reg(dev, REG_ENABLE_MAIN_STREAM, 0x1);
+}
+
+/**
+ * disable_main_link() - Switch off main link for a device
+ * @dev: The LogiCore DP TX device in question
+ */
+static void disable_main_link(struct udevice *dev)
+{
+ /* reset the scrambler. */
+ set_reg(dev, REG_FORCE_SCRAMBLER_RESET, 0x1);
+
+ /* Disable the main stream. */
+ set_reg(dev, REG_ENABLE_MAIN_STREAM, 0x0);
+}
+
+/**
+ * reset_dp_phy() - Reset a device
+ * @dev: The LogiCore DP TX device in question
+ * @reset: Bit mask determining which bits in the device's config register
+ * should be set for the reset
+ */
+static void reset_dp_phy(struct udevice *dev, u32 reset)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ u32 val;
+
+ set_reg(dev, REG_ENABLE, 0x0);
+
+ val = get_reg(dev, REG_PHY_CONFIG);
+
+ /* Apply reset. */
+ set_reg(dev, REG_PHY_CONFIG, val | reset);
+
+ /* Remove reset. */
+ set_reg(dev, REG_PHY_CONFIG, val);
+
+ /* Wait for the PHY to be ready. */
+ wait_phy_ready(dev, phy_status_lanes_ready_mask(dp_tx->max_lane_count));
+
+ set_reg(dev, REG_ENABLE, 0x1);
+}
+
+/**
+ * set_enhanced_frame_mode() - Enable/Disable enhanced frame mode
+ * @dev: The LogiCore DP TX device in question
+ * @enable: Flag to determine whether to enable (1) or disable (0) the enhanced
+ * frame mode
+ *
+ * Enable or disable the enhanced framing symbol sequence for
+ * both the DisplayPort TX core and the RX device.
+ *
+ * Return: 0 if enabling/disabling the enhanced frame mode was successful, -ve
+ * on error
+ */
+static int set_enhanced_frame_mode(struct udevice *dev, u8 enable)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ int status;
+ u8 val;
+
+ if (!is_connected(dev))
+ return -ENODEV;
+
+ if (dp_tx->link_config.support_enhanced_framing_mode)
+ dp_tx->link_config.enhanced_framing_mode = enable;
+ else
+ dp_tx->link_config.enhanced_framing_mode = false;
+
+ /* Write enhanced frame mode enable to the DisplayPort TX core. */
+ set_reg(dev, REG_ENHANCED_FRAME_EN,
+ dp_tx->link_config.enhanced_framing_mode);
+
+ /* Write enhanced frame mode enable to the RX device. */
+ status = aux_read(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
+ if (status)
+ return -EIO;
+
+ if (dp_tx->link_config.enhanced_framing_mode)
+ val |= DPCD_ENHANCED_FRAME_EN_MASK;
+ else
+ val &= ~DPCD_ENHANCED_FRAME_EN_MASK;
+
+ status = aux_write(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
+ if (status)
+ return -EIO;
+
+ return 0;
+}
+
+/**
+ * set_lane_count() - Set the lane count
+ * @dev: The LogiCore DP TX device in question
+ * @lane_count: Lane count to set
+ *
+ * Set the number of lanes to be used by the main link for both
+ * the DisplayPort TX core and the RX device.
+ *
+ * Return: 0 if setting the lane count was successful, -ve on error
+ */
+static int set_lane_count(struct udevice *dev, u8 lane_count)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ int status;
+ u8 val;
+
+ if (!is_connected(dev))
+ return -ENODEV;
+
+ printf(" set lane count to %u\n", lane_count);
+
+ dp_tx->link_config.lane_count = lane_count;
+
+ /* Write the new lane count to the DisplayPort TX core. */
+ set_reg(dev, REG_LANE_COUNT_SET, dp_tx->link_config.lane_count);
+
+ /* Write the new lane count to the RX device. */
+ status = aux_read(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
+ if (status)
+ return -EIO;
+ val &= ~DPCD_LANE_COUNT_SET_MASK;
+ val |= dp_tx->link_config.lane_count;
+
+ status = aux_write(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
+ if (status)
+ return -EIO;
+
+ return 0;
+}
+
+/**
+ * set_clk_speed() - Set DP phy clock speed
+ * @dev: The LogiCore DP TX device in question
+ * @speed: The clock frquency to set (one of PHY_CLOCK_SELECT_*)
+ *
+ * Set the clock frequency for the DisplayPort PHY corresponding to a desired
+ * data rate.
+ *
+ * Return: 0 if setting the DP phy clock speed was successful, -ve on error
+ */
+static int set_clk_speed(struct udevice *dev, u32 speed)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ int status;
+ u32 val;
+ u32 mask;
+
+ /* Disable the DisplayPort TX core first. */
+ val = get_reg(dev, REG_ENABLE);
+ set_reg(dev, REG_ENABLE, 0x0);
+
+ /* Change speed of the feedback clock. */
+ set_reg(dev, REG_PHY_CLOCK_SELECT, speed);
+
+ /* Re-enable the DisplayPort TX core if it was previously enabled. */
+ if (val)
+ set_reg(dev, REG_ENABLE, 0x1);
+
+ /* Wait until the PHY is ready. */
+ mask = phy_status_lanes_ready_mask(dp_tx->max_lane_count);
+ status = wait_phy_ready(dev, mask);
+ if (status)
+ return -EIO;
+
+ return 0;
+}
+
+/**
+ * set_link_rate() - Set the link rate
+ * @dev: The LogiCore DP TX device in question
+ * @link_rate: The link rate to set (one of LINK_BW_SET_*)
+ *
+ * Set the data rate to be used by the main link for both the DisplayPort TX
+ * core and the RX device.
+ *
+ * Return: 0 if setting the link rate was successful, -ve on error
+ */
+static int set_link_rate(struct udevice *dev, u8 link_rate)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ int status;
+
+ /* Write a corresponding clock frequency to the DisplayPort TX core. */
+ switch (link_rate) {
+ case LINK_BW_SET_162GBPS:
+ printf(" set link rate to 1.62 Gb/s\n");
+ status = set_clk_speed(dev, PHY_CLOCK_SELECT_162GBPS);
+ break;
+ case LINK_BW_SET_270GBPS:
+ printf(" set link rate to 2.70 Gb/s\n");
+ status = set_clk_speed(dev, PHY_CLOCK_SELECT_270GBPS);
+ break;
+ case LINK_BW_SET_540GBPS:
+ printf(" set link rate to 5.40 Gb/s\n");
+ status = set_clk_speed(dev, PHY_CLOCK_SELECT_540GBPS);
+ break;
+ default:
+ return -EINVAL;
+ }
+ if (status)
+ return -EIO;
+
+ dp_tx->link_config.link_rate = link_rate;
+
+ /* Write new link rate to the DisplayPort TX core. */
+ set_reg(dev, REG_LINK_BW_SET, dp_tx->link_config.link_rate);
+
+ /* Write new link rate to the RX device. */
+ status = aux_write(dev, DPCD_LINK_BW_SET, 1,
+ &dp_tx->link_config.link_rate);
+ if (status)
+ return -EIO;
+
+ return 0;
+}
+
+/* Link training */
+
+/**
+ * get_training_delay() - Get training delay
+ * @dev: The LogiCore DP TX device in question
+ * @training_state: The training state for which the required training delay
+ * should be queried
+ *
+ * Determine what the RX device's required training delay is for
+ * link training.
+ *
+ * Return: The training delay in us
+ */
+static int get_training_delay(struct udevice *dev, int training_state)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ u16 delay;
+
+ switch (dp_tx->dpcd_rx_caps[DPCD_TRAIN_AUX_RD_INTERVAL]) {
+ case DPCD_TRAIN_AUX_RD_INT_100_400US:
+ if (training_state == TS_CLOCK_RECOVERY)
+ /* delay for the clock recovery phase. */
+ delay = 100;
+ else
+ /* delay for the channel equalization phase. */
+ delay = 400;
+ break;
+ case DPCD_TRAIN_AUX_RD_INT_4MS:
+ delay = 4000;
+ break;
+ case DPCD_TRAIN_AUX_RD_INT_8MS:
+ delay = 8000;
+ break;
+ case DPCD_TRAIN_AUX_RD_INT_12MS:
+ delay = 12000;
+ break;
+ case DPCD_TRAIN_AUX_RD_INT_16MS:
+ delay = 16000;
+ break;
+ default:
+ /* Default to 20 ms. */
+ delay = 20000;
+ break;
+ }
+
+ return delay;
+}
+
+/**
+ * set_vswing_preemp() - Build AUX data to set voltage swing and pre-emphasis
+ * @dev: The LogiCore DP TX device in question
+ * @aux_data: Buffer to receive the built AUX data
+ *
+ * Build AUX data to set current voltage swing and pre-emphasis level settings;
+ * the necessary data is taken from the link_config structure.
+ */
+static void set_vswing_preemp(struct udevice *dev, u8 *aux_data)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ u8 data;
+ u8 vs_level_rx = dp_tx->link_config.vs_level;
+ u8 pe_level_rx = dp_tx->link_config.pe_level;
+
+ /* Set up the data buffer for writing to the RX device. */
+ data = (pe_level_rx << DPCD_TRAINING_LANEX_SET_PE_SHIFT) | vs_level_rx;
+ /* The maximum voltage swing has been reached. */
+ if (vs_level_rx == MAXIMUM_VS_LEVEL)
+ data |= DPCD_TRAINING_LANEX_SET_MAX_VS_MASK;
+
+ /* The maximum pre-emphasis level has been reached. */
+ if (pe_level_rx == MAXIMUM_PE_LEVEL)
+ data |= DPCD_TRAINING_LANEX_SET_MAX_PE_MASK;
+ memset(aux_data, data, 4);
+}
+
+/**
+ * adj_vswing_preemp() - Adjust voltage swing and pre-emphasis
+ * @dev: The LogiCore DP TX device in question
+ *
+ * Set new voltage swing and pre-emphasis levels using the
+ * adjustment requests obtained from the RX device.
+ *
+ * Return: 0 if voltage swing and pre-emphasis could be adjusted successfully,
+ * -ve on error
+ */
+static int adj_vswing_preemp(struct udevice *dev)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ int status;
+ u8 index;
+ u8 vs_level_adj_req[4];
+ u8 pe_level_adj_req[4];
+ u8 aux_data[4];
+ u8 *ajd_reqs = &dp_tx->lane_status_ajd_reqs[4];
+
+ /*
+ * Analyze the adjustment requests for changes in voltage swing and
+ * pre-emphasis levels.
+ */
+ vs_level_adj_req[0] = ajd_reqs[0] & DPCD_ADJ_REQ_LANE_0_2_VS_MASK;
+ vs_level_adj_req[1] = (ajd_reqs[0] & DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >>
+ DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT;
+ vs_level_adj_req[2] = ajd_reqs[1] & DPCD_ADJ_REQ_LANE_0_2_VS_MASK;
+ vs_level_adj_req[3] = (ajd_reqs[1] & DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >>
+ DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT;
+ pe_level_adj_req[0] = (ajd_reqs[0] & DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >>
+ DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT;
+ pe_level_adj_req[1] = (ajd_reqs[0] & DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >>
+ DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT;
+ pe_level_adj_req[2] = (ajd_reqs[1] & DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >>
+ DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT;
+ pe_level_adj_req[3] = (ajd_reqs[1] & DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >>
+ DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT;
+
+ /*
+ * Change the drive settings to match the adjustment requests. Use the
+ * greatest level requested.
+ */
+ dp_tx->link_config.vs_level = 0;
+ dp_tx->link_config.pe_level = 0;
+ for (index = 0; index < dp_tx->link_config.lane_count; index++) {
+ if (vs_level_adj_req[index] > dp_tx->link_config.vs_level)
+ dp_tx->link_config.vs_level = vs_level_adj_req[index];
+ if (pe_level_adj_req[index] > dp_tx->link_config.pe_level)
+ dp_tx->link_config.pe_level = pe_level_adj_req[index];
+ }
+
+ /*
+ * Verify that the voltage swing and pre-emphasis combination is
+ * allowed. Some combinations will result in a differential peak-to-peak
+ * voltage that is outside the permissible range. See the VESA
+ * DisplayPort v1.2 Specification, section 3.1.5.2.
+ * The valid combinations are:
+ * PE=0 PE=1 PE=2 PE=3
+ * VS=0 valid valid valid valid
+ * VS=1 valid valid valid
+ * VS=2 valid valid
+ * VS=3 valid
+ *
+ * NOTE:
+ * Xilinix dp_v3_1 driver seems to have an off by one error when
+ * limiting pe_level which is fixed here.
+ */
+ if (dp_tx->link_config.pe_level > (3 - dp_tx->link_config.vs_level))
+ dp_tx->link_config.pe_level = 3 - dp_tx->link_config.vs_level;
+
+ /*
+ * Make the adjustments to both the DisplayPort TX core and the RX
+ * device.
+ */
+ set_vswing_preemp(dev, aux_data);
+ /*
+ * Write the voltage swing and pre-emphasis levels for each lane to the
+ * RX device.
+ */
+ status = aux_write(dev, DPCD_TRAINING_LANE0_SET, 4, aux_data);
+ if (status)
+ return -EIO;
+
+ return 0;
+}
+
+/**
+ * get_lane_status_adj_reqs() - Read lane status and adjustment requests
+ * information from the device
+ * @dev: The LogiCore DP TX device in question
+ *
+ * Do a burst AUX read from the RX device over the AUX channel. The contents of
+ * the status registers will be stored for later use by check_clock_recovery,
+ * check_channel_equalization, and adj_vswing_preemp.
+ *
+ * Return: 0 if the status information were read successfully, -ve on error
+ */
+static int get_lane_status_adj_reqs(struct udevice *dev)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ int status;
+
+ /*
+ * Read and store 4 bytes of lane status and 2 bytes of adjustment
+ * requests.
+ */
+ status = aux_read(dev, DPCD_STATUS_LANE_0_1, 6,
+ dp_tx->lane_status_ajd_reqs);
+ if (status)
+ return -EIO;
+
+ return 0;
+}
+
+/**
+ * check_clock_recovery() - Check clock recovery success
+ * @dev: The LogiCore DP TX device in question
+ * @lane_count: The number of lanes for which to check clock recovery success
+ *
+ * Check if the RX device's DisplayPort Configuration data (DPCD) indicates
+ * that the clock recovery sequence during link training was successful - the
+ * RX device's link clock and data recovery unit has realized and maintained
+ * the frequency lock for all lanes currently in use.
+ *
+ * Return: 0 if clock recovery was successful on all lanes in question, -ve if
+ * not
+ */
+static int check_clock_recovery(struct udevice *dev, u8 lane_count)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ u8 *lane_status = dp_tx->lane_status_ajd_reqs;
+
+ /* Check that all LANEx_CR_DONE bits are set. */
+ switch (lane_count) {
+ case LANE_COUNT_SET_4:
+ if (!(lane_status[1] & DPCD_STATUS_LANE_3_CR_DONE_MASK))
+ goto out_fail;
+ if (!(lane_status[1] & DPCD_STATUS_LANE_2_CR_DONE_MASK))
+ goto out_fail;
+ /* Drop through and check lane 1. */
+ case LANE_COUNT_SET_2:
+ if (!(lane_status[0] & DPCD_STATUS_LANE_1_CR_DONE_MASK))
+ goto out_fail;
+ /* Drop through and check lane 0. */
+ case LANE_COUNT_SET_1:
+ if (!(lane_status[0] & DPCD_STATUS_LANE_0_CR_DONE_MASK))
+ goto out_fail;
+ default:
+ /* All (lane_count) lanes have achieved clock recovery. */
+ break;
+ }
+
+ return 0;
+
+out_fail:
+ return -EIO;
+}
+
+/**
+ * check_channel_equalization() - Check channel equalization success
+ * @dev: The LogiCore DP TX device in question
+ * @lane_count: The number of lanes for which to check channel equalization
+ * success
+ *
+ * Check if the RX device's DisplayPort Configuration data (DPCD) indicates
+ * that the channel equalization sequence during link training was successful -
+ * the RX device has achieved channel equalization, symbol lock, and interlane
+ * alignment for all lanes currently in use.
+ *
+ * Return: 0 if channel equalization was successful on all lanes in question,
+ * -ve if not
+ */
+static int check_channel_equalization(struct udevice *dev, u8 lane_count)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ u8 *lane_status = dp_tx->lane_status_ajd_reqs;
+
+ /* Check that all LANEx_CHANNEL_EQ_DONE bits are set. */
+ switch (lane_count) {
+ case LANE_COUNT_SET_4:
+ if (!(lane_status[1] & DPCD_STATUS_LANE_3_CE_DONE_MASK))
+ goto out_fail;
+ if (!(lane_status[1] & DPCD_STATUS_LANE_2_CE_DONE_MASK))
+ goto out_fail;
+ /* Drop through and check lane 1. */
+ case LANE_COUNT_SET_2:
+ if (!(lane_status[0] & DPCD_STATUS_LANE_1_CE_DONE_MASK))
+ goto out_fail;
+ /* Drop through and check lane 0. */
+ case LANE_COUNT_SET_1:
+ if (!(lane_status[0] & DPCD_STATUS_LANE_0_CE_DONE_MASK))
+ goto out_fail;
+ default:
+ /* All (lane_count) lanes have achieved channel equalization. */
+ break;
+ }
+
+ /* Check that all LANEx_SYMBOL_LOCKED bits are set. */
+ switch (lane_count) {
+ case LANE_COUNT_SET_4:
+ if (!(lane_status[1] & DPCD_STATUS_LANE_3_SL_DONE_MASK))
+ goto out_fail;
+ if (!(lane_status[1] & DPCD_STATUS_LANE_2_SL_DONE_MASK))
+ goto out_fail;
+ /* Drop through and check lane 1. */
+ case LANE_COUNT_SET_2:
+ if (!(lane_status[0] & DPCD_STATUS_LANE_1_SL_DONE_MASK))
+ goto out_fail;
+ /* Drop through and check lane 0. */
+ case LANE_COUNT_SET_1:
+ if (!(lane_status[0] & DPCD_STATUS_LANE_0_SL_DONE_MASK))
+ goto out_fail;
+ default:
+ /* All (lane_count) lanes have achieved symbol lock. */
+ break;
+ }
+
+ /* Check that interlane alignment is done. */
+ if (!(lane_status[2] & DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK))
+ goto out_fail;
+
+ return 0;
+
+out_fail:
+ return -EIO;
+}
+
+/**
+ * set_training_pattern() - Set training pattern for link training
+ * @dev: The LogiCore DP TX device in question
+ * @pattern: The training pattern to set
+ *
+ * Set the training pattern to be used during link training for both the
+ * DisplayPort TX core and the RX device.
+ *
+ * Return: 0 if the training pattern could be set successfully, -ve if not
+ */
+static int set_training_pattern(struct udevice *dev, u32 pattern)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ int status;
+ u8 aux_data[5];
+
+ /* Write to the DisplayPort TX core. */
+ set_reg(dev, REG_TRAINING_PATTERN_SET, pattern);
+
+ aux_data[0] = pattern;
+
+ /* Write scrambler disable to the DisplayPort TX core. */
+ switch (pattern) {
+ case TRAINING_PATTERN_SET_OFF:
+ set_reg(dev, REG_SCRAMBLING_DISABLE, 0);
+ dp_tx->link_config.scrambler_en = 1;
+ break;
+ case TRAINING_PATTERN_SET_TP1:
+ case TRAINING_PATTERN_SET_TP2:
+ case TRAINING_PATTERN_SET_TP3:
+ aux_data[0] |= DPCD_TP_SET_SCRAMB_DIS_MASK;
+ set_reg(dev, REG_SCRAMBLING_DISABLE, 1);
+ dp_tx->link_config.scrambler_en = 0;
+ break;
+ default:
+ break;
+ }
+
+ /*
+ * Make the adjustments to both the DisplayPort TX core and the RX
+ * device.
+ */
+ set_vswing_preemp(dev, &aux_data[1]);
+ /*
+ * Write the voltage swing and pre-emphasis levels for each lane to the
+ * RX device.
+ */
+ if (pattern == TRAINING_PATTERN_SET_OFF)
+ status = aux_write(dev, DPCD_TP_SET, 1, aux_data);
+ else
+ status = aux_write(dev, DPCD_TP_SET, 5, aux_data);
+ if (status)
+ return -EIO;
+
+ return 0;
+}
+
+/**
+ * training_state_clock_recovery() - Run clock recovery part of link training
+ * @dev: The LogiCore DP TX device in question
+ *
+ * Run the clock recovery sequence as part of link training. The
+ * sequence is as follows:
+ *
+ * 0) Start signaling at the minimum voltage swing, pre-emphasis, and
+ * post- cursor levels.
+ * 1) Transmit training pattern 1 over the main link with symbol
+ * scrambling disabled.
+ * 2) The clock recovery loop. If clock recovery is unsuccessful after
+ * MaxIterations loop iterations, return.
+ * 2a) Wait for at least the period of time specified in the RX device's
+ * DisplayPort Configuration data (DPCD) register,
+ * TRAINING_AUX_RD_INTERVAL.
+ * 2b) Check if all lanes have achieved clock recovery lock. If so,
+ * return.
+ * 2c) Check if the same voltage swing level has been used 5 consecutive
+ * times or if the maximum level has been reached. If so, return.
+ * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as
+ * requested by the RX device.
+ * 2e) Loop back to 2a.
+ *
+ * For a more detailed description of the clock recovery sequence, see section
+ * 3.5.1.2.1 of the DisplayPort 1.2a specification document.
+ *
+ * Return: The next state machine state to advance to
+ */
+static unsigned int training_state_clock_recovery(struct udevice *dev)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ int status;
+ u32 delay_us;
+ u8 prev_vs_level = 0;
+ u8 same_vs_level_count = 0;
+
+ /*
+ * Obtain the required delay for clock recovery as specified by the
+ * RX device.
+ */
+ delay_us = get_training_delay(dev, TS_CLOCK_RECOVERY);
+
+ /* Start CRLock. */
+
+ /* Transmit training pattern 1. */
+ /* Disable the scrambler. */
+ /* Start from minimal voltage swing and pre-emphasis levels. */
+ dp_tx->link_config.vs_level = 0;
+ dp_tx->link_config.pe_level = 0;
+ status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP1);
+ if (status)
+ return TS_FAILURE;
+
+ while (1) {
+ /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */
+ udelay(delay_us);
+
+ /* Get lane and adjustment requests. */
+ status = get_lane_status_adj_reqs(dev);
+ if (status)
+ return TS_FAILURE;
+
+ /*
+ * Check if all lanes have realized and maintained the frequency
+ * lock and get adjustment requests.
+ */
+ status = check_clock_recovery(dev,
+ dp_tx->link_config.lane_count);
+ if (!status)
+ return TS_CHANNEL_EQUALIZATION;
+
+ /*
+ * Check if the same voltage swing for each lane has been used 5
+ * consecutive times.
+ */
+ if (prev_vs_level == dp_tx->link_config.vs_level) {
+ same_vs_level_count++;
+ } else {
+ same_vs_level_count = 0;
+ prev_vs_level = dp_tx->link_config.vs_level;
+ }
+ if (same_vs_level_count >= 5)
+ break;
+
+ /* Only try maximum voltage swing once. */
+ if (dp_tx->link_config.vs_level == MAXIMUM_VS_LEVEL)
+ break;
+
+ /* Adjust the drive settings as requested by the RX device. */
+ status = adj_vswing_preemp(dev);
+ if (status)
+ /* The AUX write failed. */
+ return TS_FAILURE;
+ }
+
+ return TS_ADJUST_LINK_RATE;
+}
+
+/**
+ * training_state_channel_equalization() - Run channel equalization part of
+ * link training
+ * @dev: The LogiCore DP TX device in question
+ *
+ * Run the channel equalization sequence as part of link
+ * training. The sequence is as follows:
+ *
+ * 0) Start signaling with the same drive settings used at the end of the
+ * clock recovery sequence.
+ * 1) Transmit training pattern 2 (or 3) over the main link with symbol
+ * scrambling disabled.
+ * 2) The channel equalization loop. If channel equalization is
+ * unsuccessful after 5 loop iterations, return.
+ * 2a) Wait for at least the period of time specified in the RX device's
+ * DisplayPort Configuration data (DPCD) register,
+ * TRAINING_AUX_RD_INTERVAL.
+ * 2b) Check if all lanes have achieved channel equalization, symbol lock,
+ * and interlane alignment. If so, return.
+ * 2c) Check if the same voltage swing level has been used 5 consecutive
+ * times or if the maximum level has been reached. If so, return.
+ * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as
+ * requested by the RX device.
+ * 2e) Loop back to 2a.
+ *
+ * For a more detailed description of the channel equalization sequence, see
+ * section 3.5.1.2.2 of the DisplayPort 1.2a specification document.
+ *
+ * Return: The next state machine state to advance to
+ */
+static int training_state_channel_equalization(struct udevice *dev)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ int status;
+ u32 delay_us;
+ u32 iteration_count = 0;
+
+ /*
+ * Obtain the required delay for channel equalization as specified by
+ * the RX device.
+ */
+ delay_us = get_training_delay(dev, TS_CHANNEL_EQUALIZATION);
+
+ /* Start channel equalization. */
+
+ /* Write the current drive settings. */
+ /* Transmit training pattern 2/3. */
+ if (dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] & DPCD_TPS3_SUPPORT_MASK)
+ status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP3);
+ else
+ status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP2);
+
+ if (status)
+ return TS_FAILURE;
+
+ while (iteration_count < 5) {
+ /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */
+ udelay(delay_us);
+
+ /* Get lane and adjustment requests. */
+ status = get_lane_status_adj_reqs(dev);
+ if (status)
+ /* The AUX read failed. */
+ return TS_FAILURE;
+
+ /* Check that all lanes still have their clocks locked. */
+ status = check_clock_recovery(dev,
+ dp_tx->link_config.lane_count);
+ if (status)
+ break;
+
+ /*
+ * Check if all lanes have accomplished channel equalization,
+ * symbol lock, and interlane alignment.
+ */
+ status =
+ check_channel_equalization(dev,
+ dp_tx->link_config.lane_count);
+ if (!status)
+ return TS_SUCCESS;
+
+ /* Adjust the drive settings as requested by the RX device. */
+ status = adj_vswing_preemp(dev);
+ if (status)
+ /* The AUX write failed. */
+ return TS_FAILURE;
+
+ iteration_count++;
+ }
+
+ /*
+ * Tried 5 times with no success. Try a reduced bitrate first, then
+ * reduce the number of lanes.
+ */
+ return TS_ADJUST_LINK_RATE;
+}
+
+/**
+ * training_state_adjust_link_rate() - Downshift data rate and/or lane count
+ * @dev: The LogiCore DP TX device in question
+ *
+ * This function is reached if either the clock recovery or the channel
+ * equalization process failed during training. As a result, the data rate will
+ * be downshifted, and training will be re-attempted (starting with clock
+ * recovery) at the reduced data rate. If the data rate is already at 1.62
+ * Gbps, a downshift in lane count will be attempted.
+ *
+ * Return: The next state machine state to advance to
+ */
+static int training_state_adjust_link_rate(struct udevice *dev)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ int status;
+
+ switch (dp_tx->link_config.link_rate) {
+ case LINK_BW_SET_540GBPS:
+ status = set_link_rate(dev, LINK_BW_SET_270GBPS);
+ if (status) {
+ status = TS_FAILURE;
+ break;
+ }
+ status = TS_CLOCK_RECOVERY;
+ break;
+ case LINK_BW_SET_270GBPS:
+ status = set_link_rate(dev, LINK_BW_SET_162GBPS);
+ if (status) {
+ status = TS_FAILURE;
+ break;
+ }
+ status = TS_CLOCK_RECOVERY;
+ break;
+ default:
+ /*
+ * Already at the lowest link rate. Try reducing the lane
+ * count next.
+ */
+ status = TS_ADJUST_LANE_COUNT;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * trainig_state_adjust_lane_count - Downshift lane count
+ * @dev: The LogiCore DP TX device in question
+ *
+ * This function is reached if either the clock recovery or the channel
+ * equalization process failed during training, and a minimal data rate of 1.62
+ * Gbps was being used. As a result, the number of lanes in use will be
+ * reduced, and training will be re-attempted (starting with clock recovery) at
+ * this lower lane count.
+ *
+ * Return: The next state machine state to advance to
+ */
+static int trainig_state_adjust_lane_count(struct udevice *dev)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ int status;
+
+ switch (dp_tx->link_config.lane_count) {
+ case LANE_COUNT_SET_4:
+ status = set_lane_count(dev, LANE_COUNT_SET_2);
+ if (status) {
+ status = TS_FAILURE;
+ break;
+ }
+
+ status = set_link_rate(dev, dp_tx->link_config.max_link_rate);
+ if (status) {
+ status = TS_FAILURE;
+ break;
+ }
+ status = TS_CLOCK_RECOVERY;
+ break;
+ case LANE_COUNT_SET_2:
+ status = set_lane_count(dev, LANE_COUNT_SET_1);
+ if (status) {
+ status = TS_FAILURE;
+ break;
+ }
+
+ status = set_link_rate(dev, dp_tx->link_config.max_link_rate);
+ if (status) {
+ status = TS_FAILURE;
+ break;
+ }
+ status = TS_CLOCK_RECOVERY;
+ break;
+ default:
+ /*
+ * Already at the lowest lane count. Training has failed at the
+ * lowest lane count and link rate.
+ */
+ status = TS_FAILURE;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * check_link_status() - Check status of link
+ * @dev: The LogiCore DP TX device in question
+ * @lane_count: The lane count to use for the check
+ *
+ * Check if the receiver's DisplayPort Configuration data (DPCD) indicates the
+ * receiver has achieved and maintained clock recovery, channel equalization,
+ * symbol lock, and interlane alignment for all lanes currently in use.
+ *
+ * Return: 0 if the link status is OK, -ve if a error occurred during checking
+ */
+static int check_link_status(struct udevice *dev, u8 lane_count)
+{
+ u8 retry_count = 0;
+
+ if (!is_connected(dev))
+ return -ENODEV;
+
+ /* Retrieve AUX info. */
+ do {
+ int status;
+
+ /* Get lane and adjustment requests. */
+ status = get_lane_status_adj_reqs(dev);
+ if (status)
+ return -EIO;
+
+ /* Check if the link needs training. */
+ if ((check_clock_recovery(dev, lane_count) == 0) &&
+ (check_channel_equalization(dev, lane_count) == 0))
+ return 0;
+
+ retry_count++;
+ } while (retry_count < 5); /* Retry up to 5 times. */
+
+ return -EIO;
+}
+
+/**
+ * run_training() - Run link training
+ * @dev: The LogiCore DP TX device in question
+ *
+ * Run the link training process. It is implemented as a state machine, with
+ * each state returning the next state. First, the clock recovery sequence will
+ * be run; if successful, the channel equalization sequence will run. If either
+ * the clock recovery or channel equalization sequence failed, the link rate or
+ * the number of lanes used will be reduced and training will be re-attempted.
+ * If training fails at the minimal data rate, 1.62 Gbps with a single lane,
+ * training will no longer re-attempt and fail.
+ *
+ * ### Here be dragons ###
+ * There are undocumented timeout constraints in the link training process. In
+ * DP v1.2a spec, Chapter 3.5.1.2.2 a 10ms limit for the complete training
+ * process is mentioned. Which individual timeouts are derived and implemented
+ * by sink manufacturers is unknown. So each step should be as short as
+ * possible and link training should start as soon as possible after HPD.
+ *
+ * Return: 0 if the training sequence ran successfully, -ve if a error occurred
+ * or the training failed
+ */
+static int run_training(struct udevice *dev)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ int status;
+ int training_state = TS_CLOCK_RECOVERY;
+
+ while (1) {
+ switch (training_state) {
+ case TS_CLOCK_RECOVERY:
+ training_state =
+ training_state_clock_recovery(dev);
+ break;
+ case TS_CHANNEL_EQUALIZATION:
+ training_state =
+ training_state_channel_equalization(dev);
+ break;
+ case TS_ADJUST_LINK_RATE:
+ training_state =
+ training_state_adjust_link_rate(dev);
+ break;
+ case TS_ADJUST_LANE_COUNT:
+ training_state =
+ trainig_state_adjust_lane_count(dev);
+ break;
+ default:
+ break;
+ }
+
+ if (training_state == TS_SUCCESS)
+ break;
+ else if (training_state == TS_FAILURE)
+ return -EIO;
+
+ if (training_state == TS_ADJUST_LINK_RATE ||
+ training_state == TS_ADJUST_LANE_COUNT) {
+ if (!dp_tx->train_adaptive)
+ return -EIO;
+
+ status = set_training_pattern(dev,
+ TRAINING_PATTERN_SET_OFF);
+ if (status)
+ return -EIO;
+ }
+ }
+
+ /* Final status check. */
+ status = check_link_status(dev, dp_tx->link_config.lane_count);
+ if (status)
+ return -EIO;
+
+ return 0;
+}
+
+/* Link policy maker */
+
+/**
+ * cfg_main_link_max() - Determine best common capabilities
+ * @dev: The LogiCore DP TX device in question
+ *
+ * Determine the common capabilities between the DisplayPort TX core and the RX
+ * device.
+ *
+ * Return: 0 if the determination succeeded, -ve on error
+ */
+static int cfg_main_link_max(struct udevice *dev)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ int status;
+
+ if (!is_connected(dev))
+ return -ENODEV;
+
+ /*
+ * Configure the main link to the maximum common link rate between the
+ * DisplayPort TX core and the RX device.
+ */
+ status = set_link_rate(dev, dp_tx->link_config.max_link_rate);
+ if (status)
+ return status;
+
+ /*
+ * Configure the main link to the maximum common lane count between the
+ * DisplayPort TX core and the RX device.
+ */
+ status = set_lane_count(dev, dp_tx->link_config.max_lane_count);
+ if (status)
+ return status;
+
+ return 0;
+}
+
+/**
+ * establish_link() - Establish a link
+ * @dev: The LogiCore DP TX device in question
+ *
+ * Check if the link needs training and run the training sequence if training
+ * is required.
+ *
+ * Return: 0 if the link was established successfully, -ve on error
+ */
+static int establish_link(struct udevice *dev)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ int status;
+ int status2;
+ u32 mask;
+
+ reset_dp_phy(dev, PHY_CONFIG_PHY_RESET_MASK);
+
+ /* Disable main link during training. */
+ disable_main_link(dev);
+
+ /* Wait for the PHY to be ready. */
+ mask = phy_status_lanes_ready_mask(dp_tx->max_lane_count);
+ status = wait_phy_ready(dev, mask);
+ if (status)
+ return -EIO;
+
+ /* Train main link. */
+ status = run_training(dev);
+
+ /* Turn off the training pattern and enable scrambler. */
+ status2 = set_training_pattern(dev, TRAINING_PATTERN_SET_OFF);
+ if (status || status2)
+ return -EIO;
+
+ return 0;
+}
+
+/*
+ * Stream policy maker
+ */
+
+/**
+ * cfg_msa_recalculate() - Calculate MSA parameters
+ * @dev: The LogiCore DP TX device in question
+ *
+ * Calculate the following Main Stream Attributes (MSA):
+ * - Transfer unit size
+ * - User pixel width
+ * - Horizontal total clock
+ * - Vertical total clock
+ * - misc_0
+ * - misc_1
+ * - Data per lane
+ * - Average number of bytes per transfer unit
+ * - Number of initial wait cycles
+ *
+ * These values are derived from:
+ * - Bits per color
+ * - Horizontal resolution
+ * - Vertical resolution
+ * - Horizontal blank start
+ * - Vertical blank start
+ * - Pixel clock (in KHz)
+ * - Horizontal sync polarity
+ * - Vertical sync polarity
+ * - Horizontal sync pulse width
+ * - Vertical sync pulse width
+ */
+static void cfg_msa_recalculate(struct udevice *dev)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ u32 video_bw;
+ u32 link_bw;
+ u32 words_per_line;
+ u8 bits_per_pixel;
+ struct main_stream_attributes *msa_config;
+ struct link_config *link_config;
+
+ msa_config = &dp_tx->main_stream_attributes;
+ link_config = &dp_tx->link_config;
+
+ /*
+ * Set the user pixel width to handle clocks that exceed the
+ * capabilities of the DisplayPort TX core.
+ */
+ if (msa_config->override_user_pixel_width == 0) {
+ if (msa_config->pixel_clock_hz > 300000000 &&
+ link_config->lane_count == LANE_COUNT_SET_4) {
+ msa_config->user_pixel_width = 4;
+ } /*
+ * Xilinx driver used 75 MHz as a limit here, 150 MHZ should
+ * be more sane
+ */
+ else if ((msa_config->pixel_clock_hz > 150000000) &&
+ (link_config->lane_count != LANE_COUNT_SET_1)) {
+ msa_config->user_pixel_width = 2;
+ } else {
+ msa_config->user_pixel_width = 1;
+ }
+ }
+
+ /* Compute the rest of the MSA values. */
+ msa_config->n_vid = 27 * 1000 * link_config->link_rate;
+
+ /* Miscellaneous attributes. */
+ if (msa_config->bits_per_color == 6)
+ msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_6BPC;
+ else if (msa_config->bits_per_color == 8)
+ msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_8BPC;
+ else if (msa_config->bits_per_color == 10)
+ msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_10BPC;
+ else if (msa_config->bits_per_color == 12)
+ msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_12BPC;
+ else if (msa_config->bits_per_color == 16)
+ msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_16BPC;
+
+ msa_config->misc_0 = (msa_config->misc_0 <<
+ MAIN_STREAMX_MISC0_BDC_SHIFT) |
+ (msa_config->y_cb_cr_colorimetry <<
+ MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT) |
+ (msa_config->dynamic_range <<
+ MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT) |
+ (msa_config->component_format <<
+ MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT) |
+ (msa_config->synchronous_clock_mode);
+
+ msa_config->misc_1 = 0;
+
+ /*
+ * Determine the number of bits per pixel for the specified color
+ * component format.
+ */
+ if (msa_config->component_format ==
+ MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422)
+ /* YCbCr422 color component format. */
+ bits_per_pixel = msa_config->bits_per_color * 2;
+ else
+ /* RGB or YCbCr 4:4:4 color component format. */
+ bits_per_pixel = msa_config->bits_per_color * 3;
+
+ /* Calculate the data per lane. */
+ words_per_line = (msa_config->h_active * bits_per_pixel);
+ if (words_per_line % 16)
+ words_per_line += 16;
+ words_per_line /= 16;
+
+ msa_config->data_per_lane = words_per_line - link_config->lane_count;
+ if (words_per_line % link_config->lane_count)
+ msa_config->data_per_lane += (words_per_line %
+ link_config->lane_count);
+
+ /*
+ * Allocate a fixed size for single-stream transport (SST)
+ * operation.
+ */
+ msa_config->transfer_unit_size = 64;
+
+ /*
+ * Calculate the average number of bytes per transfer unit.
+ * Note: Both the integer and the fractional part is stored in
+ * avg_bytes_per_tu.
+ */
+ video_bw = ((msa_config->pixel_clock_hz / 1000) * bits_per_pixel) / 8;
+ link_bw = (link_config->lane_count * link_config->link_rate * 27);
+ msa_config->avg_bytes_per_tu = (video_bw *
+ msa_config->transfer_unit_size) /
+ link_bw;
+
+ /*
+ * The number of initial wait cycles at the start of a new line
+ * by the framing logic. This allows enough data to be buffered
+ * in the input FIFO before video is sent.
+ */
+ if ((msa_config->avg_bytes_per_tu / 1000) <= 4)
+ msa_config->init_wait = 64;
+ else
+ msa_config->init_wait = msa_config->transfer_unit_size -
+ (msa_config->avg_bytes_per_tu / 1000);
+}
+
+/**
+ * set_line_reset() - Enable/Disable end-of-line-reset
+ * @dev: The LogiCore DP TX device in question
+ *
+ * Disable/enable the end-of-line-reset to the internal video pipe in case of
+ * reduced blanking as required.
+ */
+static void set_line_reset(struct udevice *dev)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ u32 reg_val;
+ u16 h_blank;
+ u16 h_reduced_blank;
+ struct main_stream_attributes *msa_config =
+ &dp_tx->main_stream_attributes;
+
+ h_blank = msa_config->h_total - msa_config->h_active;
+ /* Reduced blanking starts at ceil(0.2 * HTotal). */
+ h_reduced_blank = 2 * msa_config->h_total;
+ if (h_reduced_blank % 10)
+ h_reduced_blank += 10;
+ h_reduced_blank /= 10;
+
+ /* CVT spec. states h_blank is either 80 or 160 for reduced blanking. */
+ reg_val = get_reg(dev, REG_LINE_RESET_DISABLE);
+ if (h_blank < h_reduced_blank &&
+ (h_blank == 80 || h_blank == 160)) {
+ reg_val |= LINE_RESET_DISABLE_MASK;
+ } else {
+ reg_val &= ~LINE_RESET_DISABLE_MASK;
+ }
+ set_reg(dev, REG_LINE_RESET_DISABLE, reg_val);
+}
+
+/**
+ * clear_msa_values() - Clear MSA values
+ * @dev: The LogiCore DP TX device in question
+ *
+ * Clear the main stream attributes registers of the DisplayPort TX core.
+ */
+static void clear_msa_values(struct udevice *dev)
+{
+ set_reg(dev, REG_MAIN_STREAM_HTOTAL, 0);
+ set_reg(dev, REG_MAIN_STREAM_VTOTAL, 0);
+ set_reg(dev, REG_MAIN_STREAM_POLARITY, 0);
+ set_reg(dev, REG_MAIN_STREAM_HSWIDTH, 0);
+ set_reg(dev, REG_MAIN_STREAM_VSWIDTH, 0);
+ set_reg(dev, REG_MAIN_STREAM_HRES, 0);
+ set_reg(dev, REG_MAIN_STREAM_VRES, 0);
+ set_reg(dev, REG_MAIN_STREAM_HSTART, 0);
+ set_reg(dev, REG_MAIN_STREAM_VSTART, 0);
+ set_reg(dev, REG_MAIN_STREAM_MISC0, 0);
+ set_reg(dev, REG_MAIN_STREAM_MISC1, 0);
+ set_reg(dev, REG_USER_PIXEL_WIDTH, 0);
+ set_reg(dev, REG_USER_DATA_COUNT_PER_LANE, 0);
+ set_reg(dev, REG_M_VID, 0);
+ set_reg(dev, REG_N_VID, 0);
+
+ set_reg(dev, REG_STREAM1, 0);
+ set_reg(dev, REG_TU_SIZE, 0);
+ set_reg(dev, REG_MIN_BYTES_PER_TU, 0);
+ set_reg(dev, REG_FRAC_BYTES_PER_TU, 0);
+ set_reg(dev, REG_INIT_WAIT, 0);
+}
+
+/**
+ * set_msa_values() - Set MSA values
+ * @dev: The LogiCore DP TX device in question
+ *
+ * Set the main stream attributes registers of the DisplayPort TX
+ * core with the values specified in the main stream attributes configuration
+ * structure.
+ */
+static void set_msa_values(struct udevice *dev)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ struct main_stream_attributes *msa_config =
+ &dp_tx->main_stream_attributes;
+
+ printf(" set MSA %u x %u\n", msa_config->h_active,
+ msa_config->v_active);
+
+ set_reg(dev, REG_MAIN_STREAM_HTOTAL, msa_config->h_total);
+ set_reg(dev, REG_MAIN_STREAM_VTOTAL, msa_config->v_total);
+ set_reg(dev, REG_MAIN_STREAM_POLARITY,
+ msa_config->h_sync_polarity |
+ (msa_config->v_sync_polarity <<
+ MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT));
+ set_reg(dev, REG_MAIN_STREAM_HSWIDTH, msa_config->h_sync_width);
+ set_reg(dev, REG_MAIN_STREAM_VSWIDTH, msa_config->v_sync_width);
+ set_reg(dev, REG_MAIN_STREAM_HRES, msa_config->h_active);
+ set_reg(dev, REG_MAIN_STREAM_VRES, msa_config->v_active);
+ set_reg(dev, REG_MAIN_STREAM_HSTART, msa_config->h_start);
+ set_reg(dev, REG_MAIN_STREAM_VSTART, msa_config->v_start);
+ set_reg(dev, REG_MAIN_STREAM_MISC0, msa_config->misc_0);
+ set_reg(dev, REG_MAIN_STREAM_MISC1, msa_config->misc_1);
+ set_reg(dev, REG_USER_PIXEL_WIDTH, msa_config->user_pixel_width);
+
+ set_reg(dev, REG_M_VID, msa_config->pixel_clock_hz / 1000);
+ set_reg(dev, REG_N_VID, msa_config->n_vid);
+ set_reg(dev, REG_USER_DATA_COUNT_PER_LANE, msa_config->data_per_lane);
+
+ set_line_reset(dev);
+
+ set_reg(dev, REG_TU_SIZE, msa_config->transfer_unit_size);
+ set_reg(dev, REG_MIN_BYTES_PER_TU, msa_config->avg_bytes_per_tu / 1000);
+ set_reg(dev, REG_FRAC_BYTES_PER_TU,
+ (msa_config->avg_bytes_per_tu % 1000) * 1024 / 1000);
+ set_reg(dev, REG_INIT_WAIT, msa_config->init_wait);
+}
+
+/*
+ * external API
+ */
+
+/**
+ * logicore_dp_tx_set_msa() - Set given MSA values on device
+ * @dev: The LogiCore DP TX device in question
+ * @msa: The MSA values to set for the device
+ */
+static void logicore_dp_tx_set_msa(struct udevice *dev,
+ struct logicore_dp_tx_msa *msa)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+
+ memset(&dp_tx->main_stream_attributes, 0,
+ sizeof(struct main_stream_attributes));
+
+ dp_tx->main_stream_attributes.pixel_clock_hz = msa->pixel_clock_hz;
+ dp_tx->main_stream_attributes.bits_per_color = msa->bits_per_color;
+ dp_tx->main_stream_attributes.h_active = msa->h_active;
+ dp_tx->main_stream_attributes.h_start = msa->h_start;
+ dp_tx->main_stream_attributes.h_sync_polarity = msa->h_sync_polarity;
+ dp_tx->main_stream_attributes.h_sync_width = msa->h_sync_width;
+ dp_tx->main_stream_attributes.h_total = msa->h_total;
+ dp_tx->main_stream_attributes.v_active = msa->v_active;
+ dp_tx->main_stream_attributes.v_start = msa->v_start;
+ dp_tx->main_stream_attributes.v_sync_polarity = msa->v_sync_polarity;
+ dp_tx->main_stream_attributes.v_sync_width = msa->v_sync_width;
+ dp_tx->main_stream_attributes.v_total = msa->v_total;
+ dp_tx->main_stream_attributes.override_user_pixel_width =
+ msa->override_user_pixel_width;
+ dp_tx->main_stream_attributes.user_pixel_width = msa->user_pixel_width;
+ dp_tx->main_stream_attributes.synchronous_clock_mode = 0;
+}
+
+/**
+ * logicore_dp_tx_video_enable() - Enable video output
+ * @dev: The LogiCore DP TX device in question
+ * @msa: The MSA values to set for the device
+ *
+ * Return: 0 if the video was enabled successfully, -ve on error
+ */
+static int logicore_dp_tx_video_enable(struct udevice *dev,
+ struct logicore_dp_tx_msa *msa)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+ int res;
+ u8 power = 0x01;
+
+ if (!is_connected(dev)) {
+ printf(" no DP sink connected\n");
+ return -EIO;
+ }
+
+ initialize(dev);
+
+ disable_main_link(dev);
+
+ logicore_dp_tx_set_msa(dev, msa);
+
+ get_rx_capabilities(dev);
+
+ printf(" DP sink connected\n");
+ aux_write(dev, DPCD_SET_POWER_DP_PWR_VOLTAGE, 1, &power);
+ set_enhanced_frame_mode(dev, true);
+ cfg_main_link_max(dev);
+ res = establish_link(dev);
+ printf(" establish_link: %s, vs: %d, pe: %d\n",
+ res ? "failed" : "ok", dp_tx->link_config.vs_level,
+ dp_tx->link_config.pe_level);
+
+ cfg_msa_recalculate(dev);
+
+ clear_msa_values(dev);
+ set_msa_values(dev);
+
+ enable_main_link(dev);
+
+ return 0;
+}
+
+/*
+ * Driver functions
+ */
+
+static int logicore_dp_tx_enable(struct udevice *dev, int panel_bpp,
+ const struct display_timing *timing)
+{
+ struct clk pixclock;
+ struct logicore_dp_tx_msa *msa;
+ struct logicore_dp_tx_msa mode_640_480_60 = {
+ .pixel_clock_hz = 25175000,
+ .bits_per_color = 8,
+ .h_active = 640,
+ .h_start = 144,
+ .h_sync_polarity = false,
+ .h_sync_width = 96,
+ .h_total = 800,
+ .v_active = 480,
+ .v_start = 35,
+ .v_sync_polarity = false,
+ .v_sync_width = 2,
+ .v_total = 525,
+ .override_user_pixel_width = false,
+ .user_pixel_width = 0,
+ };
+
+ struct logicore_dp_tx_msa mode_720_400_70 = {
+ .pixel_clock_hz = 28300000,
+ .bits_per_color = 8,
+ .h_active = 720,
+ .h_start = 162,
+ .h_sync_polarity = false,
+ .h_sync_width = 108,
+ .h_total = 900,
+ .v_active = 400,
+ .v_start = 37,
+ .v_sync_polarity = true,
+ .v_sync_width = 2,
+ .v_total = 449,
+ .override_user_pixel_width = false,
+ .user_pixel_width = 0,
+ };
+
+ struct logicore_dp_tx_msa mode_1024_768_60 = {
+ .pixel_clock_hz = 65000000,
+ .bits_per_color = 8,
+ .h_active = 1024,
+ .h_start = 296,
+ .h_sync_polarity = false,
+ .h_sync_width = 136,
+ .h_total = 1344,
+ .v_active = 768,
+ .v_start = 35,
+ .v_sync_polarity = false,
+ .v_sync_width = 2,
+ .v_total = 806,
+ .override_user_pixel_width = false,
+ .user_pixel_width = 0,
+ };
+
+ if (timing->hactive.typ == 1024 && timing->vactive.typ == 768)
+ msa = &mode_1024_768_60;
+ else if (timing->hactive.typ == 720 && timing->vactive.typ == 400)
+ msa = &mode_720_400_70;
+ else
+ msa = &mode_640_480_60;
+
+ if (clk_get_by_index(dev, 0, &pixclock)) {
+ printf("%s: Could not get pixelclock\n", dev->name);
+ return -1;
+ }
+ clk_set_rate(&pixclock, msa->pixel_clock_hz);
+
+ return logicore_dp_tx_video_enable(dev, msa);
+}
+
+static int logicore_dp_tx_probe(struct udevice *dev)
+{
+ struct dp_tx *dp_tx = dev_get_priv(dev);
+
+ dp_tx->s_axi_clk = S_AXI_CLK_DEFAULT;
+ dp_tx->train_adaptive = false;
+ dp_tx->max_link_rate = DPCD_MAX_LINK_RATE_540GBPS;
+ dp_tx->max_lane_count = DPCD_MAX_LANE_COUNT_4;
+
+ dp_tx->base = dev_read_u32_default(dev, "reg", -1);
+
+ return 0;
+}
+
+static const struct dm_display_ops logicore_dp_tx_ops = {
+ .enable = logicore_dp_tx_enable,
+};
+
+static const struct udevice_id logicore_dp_tx_ids[] = {
+ { .compatible = "gdsys,logicore_dp_tx" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(logicore_dp_tx) = {
+ .name = "logicore_dp_tx",
+ .id = UCLASS_DISPLAY,
+ .of_match = logicore_dp_tx_ids,
+ .probe = logicore_dp_tx_probe,
+ .priv_auto_alloc_size = sizeof(struct dp_tx),
+ .ops = &logicore_dp_tx_ops,
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * logicore_dp_tx.h
+ *
+ * Driver for XILINX LogiCore DisplayPort v6.1 TX (Source)
+ *
+ * (C) Copyright 2016
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ */
+
+#ifndef __GDSYS_LOGICORE_DP_TX_H__
+#define __GDSYS_LOGICORE_DP_TX_H__
+
+/*
+ * struct logicore_dp_tx_msa - Main Stream Attributes (MSA)
+ * @pixel_clock_hz: The pixel clock of the stream (in Hz)
+ * @bits_per_color: Number of bits per color component
+ * @h_active: Horizontal active resolution (pixels)
+ * @h_start: Horizontal blank start (in pixels)
+ * @h_sync_polarity: Horizontal sync polarity
+ * (0 = negative | 1 = positive)
+ * @h_sync_width: Horizontal sync width (pixels)
+ * @h_total: Horizontal total (pixels)
+ * @v_active: Vertical active resolution (lines)
+ * @v_start: Vertical blank start (in lines).
+ * @v_sync_polarity: Vertical sync polarity
+ * (0 = negative | 1 = positive)
+ * @v_sync_width: Vertical sync width (lines)
+ * @v_total: Vertical total (lines)
+ * @override_user_pixel_width: If true, the value stored for user_pixel_width
+ * will be used as the pixel width.
+ * @user_pixel_width: The width of the user data input port.
+ *
+ * This is a stripped down version of struct main_stream_attributes that
+ * contains only the parameters that are not set by cfg_msa_recalculate()
+ */
+struct logicore_dp_tx_msa {
+ u32 pixel_clock_hz;
+ u32 bits_per_color;
+ u16 h_active;
+ u32 h_start;
+ bool h_sync_polarity;
+ u16 h_sync_width;
+ u16 h_total;
+ u16 v_active;
+ u32 v_start;
+ bool v_sync_polarity;
+ u16 v_sync_width;
+ u16 v_total;
+ bool override_user_pixel_width;
+ u32 user_pixel_width;
+};
+
+#endif /* __GDSYS_LOGICORE_DP_TX_H__ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * logicore_dp_tx_regif.h
+ *
+ * Register interface definition for XILINX LogiCore DisplayPort v6.1 TX
+ * (Source) based on Xilinx dp_v3_1 driver sources
+ *
+ * (C) Copyright 2016
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ */
+
+#ifndef __GDSYS_LOGICORE_DP_TX_REGIF_H__
+#define __GDSYS_LOGICORE_DP_TX_REGIF_H__
+
+enum {
+ /* link configuration field */
+ REG_LINK_BW_SET = 0x000,
+ REG_LANE_COUNT_SET = 0x004,
+ REG_ENHANCED_FRAME_EN = 0x008,
+ REG_TRAINING_PATTERN_SET = 0x00C,
+ REG_LINK_QUAL_PATTERN_SET = 0x010,
+ REG_SCRAMBLING_DISABLE = 0x014,
+ REG_DOWNSPREAD_CTRL = 0x018,
+ REG_SOFT_RESET = 0x01C,
+};
+
+enum {
+ /* core enables */
+ REG_ENABLE = 0x080,
+ REG_ENABLE_MAIN_STREAM = 0x084,
+ REG_ENABLE_SEC_STREAM = 0x088,
+ REG_FORCE_SCRAMBLER_RESET = 0x0C0,
+ REG_MST_CONFIG = 0x0D0,
+ REG_LINE_RESET_DISABLE = 0x0F0,
+};
+
+enum {
+ /* core ID */
+ REG_VERSION = 0x0F8,
+ REG_CORE_ID = 0x0FC,
+};
+
+enum {
+ /* AUX channel interface */
+ REG_AUX_CMD = 0x100,
+ REG_AUX_WRITE_FIFO = 0x104,
+ REG_AUX_ADDRESS = 0x108,
+ REG_AUX_CLK_DIVIDER = 0x10C,
+ REG_USER_FIFO_OVERFLOW = 0x110,
+ REG_INTERRUPT_SIG_STATE = 0x130,
+ REG_AUX_REPLY_DATA = 0x134,
+ REG_AUX_REPLY_CODE = 0x138,
+ REG_AUX_REPLY_COUNT = 0x13C,
+ REG_INTERRUPT_STATUS = 0x140,
+ REG_INTERRUPT_MASK = 0x144,
+ REG_REPLY_DATA_COUNT = 0x148,
+ REG_REPLY_STATUS = 0x14C,
+ REG_HPD_DURATION = 0x150,
+};
+
+enum {
+ /* main stream attributes for SST / MST STREAM1 */
+ REG_STREAM1_MSA_START = 0x180,
+ REG_MAIN_STREAM_HTOTAL = 0x180,
+ REG_MAIN_STREAM_VTOTAL = 0x184,
+ REG_MAIN_STREAM_POLARITY = 0x188,
+ REG_MAIN_STREAM_HSWIDTH = 0x18C,
+ REG_MAIN_STREAM_VSWIDTH = 0x190,
+ REG_MAIN_STREAM_HRES = 0x194,
+ REG_MAIN_STREAM_VRES = 0x198,
+ REG_MAIN_STREAM_HSTART = 0x19C,
+ REG_MAIN_STREAM_VSTART = 0x1A0,
+ REG_MAIN_STREAM_MISC0 = 0x1A4,
+ REG_MAIN_STREAM_MISC1 = 0x1A8,
+ REG_M_VID = 0x1AC,
+ REG_TU_SIZE = 0x1B0,
+ REG_N_VID = 0x1B4,
+ REG_USER_PIXEL_WIDTH = 0x1B8,
+ REG_USER_DATA_COUNT_PER_LANE = 0x1BC,
+ REG_MAIN_STREAM_INTERLACED = 0x1C0,
+ REG_MIN_BYTES_PER_TU = 0x1C4,
+ REG_FRAC_BYTES_PER_TU = 0x1C8,
+ REG_INIT_WAIT = 0x1CC,
+ REG_STREAM1 = 0x1D0,
+ REG_STREAM2 = 0x1D4,
+ REG_STREAM3 = 0x1D8,
+ REG_STREAM4 = 0x1DC,
+};
+
+enum {
+ /* PHY configuration status */
+ REG_PHY_CONFIG = 0x200,
+ REG_PHY_VOLTAGE_DIFF_LANE_0 = 0x220,
+ REG_PHY_VOLTAGE_DIFF_LANE_1 = 0x224,
+ REG_PHY_VOLTAGE_DIFF_LANE_2 = 0x228,
+ REG_PHY_VOLTAGE_DIFF_LANE_3 = 0x22C,
+ REG_PHY_TRANSMIT_PRBS7 = 0x230,
+ REG_PHY_CLOCK_SELECT = 0x234,
+ REG_PHY_POWER_DOWN = 0x238,
+ REG_PHY_PRECURSOR_LANE_0 = 0x23C,
+ REG_PHY_PRECURSOR_LANE_1 = 0x240,
+ REG_PHY_PRECURSOR_LANE_2 = 0x244,
+ REG_PHY_PRECURSOR_LANE_3 = 0x248,
+ REG_PHY_POSTCURSOR_LANE_0 = 0x24C,
+ REG_PHY_POSTCURSOR_LANE_1 = 0x250,
+ REG_PHY_POSTCURSOR_LANE_2 = 0x254,
+ REG_PHY_POSTCURSOR_LANE_3 = 0x258,
+ REG_PHY_STATUS = 0x280,
+ REG_GT_DRP_COMMAND = 0x2A0,
+ REG_GT_DRP_READ_DATA = 0x2A4,
+ REG_GT_DRP_CHANNEL_STATUS = 0x2A8,
+};
+
+enum {
+ /* DisplayPort audio */
+ REG_AUDIO_CONTROL = 0x300,
+ REG_AUDIO_CHANNELS = 0x304,
+ REG_AUDIO_INFO_DATA = 0x308,
+ REG_AUDIO_MAUD = 0x328,
+ REG_AUDIO_NAUD = 0x32C,
+ REG_AUDIO_EXT_DATA = 0x330,
+};
+
+enum {
+ /* HDCP */
+ REG_HDCP_ENABLE = 0x400,
+};
+
+enum {
+ /* main stream attributes for MST STREAM2, 3, and 4 */
+ REG_STREAM2_MSA_START = 0x500,
+ REG_STREAM3_MSA_START = 0x550,
+ REG_STREAM4_MSA_START = 0x5A0,
+
+ REG_VC_PAYLOAD_BUFFER_ADDR = 0x800,
+};
+
+enum {
+ LINK_BW_SET_162GBPS = 0x06,
+ LINK_BW_SET_270GBPS = 0x0A,
+ LINK_BW_SET_540GBPS = 0x14,
+};
+
+enum {
+ LANE_COUNT_SET_1 = 0x1,
+ LANE_COUNT_SET_2 = 0x2,
+ LANE_COUNT_SET_4 = 0x4,
+};
+
+enum {
+ TRAINING_PATTERN_SET_OFF = 0x0,
+ /* training pattern 1 used for clock recovery */
+ TRAINING_PATTERN_SET_TP1 = 0x1,
+ /* training pattern 2 used for channel equalization */
+ TRAINING_PATTERN_SET_TP2 = 0x2,
+ /*
+ * training pattern 3 used for channel equalization for cores with DP
+ * v1.2
+ */
+ TRAINING_PATTERN_SET_TP3 = 0x3,
+};
+
+enum {
+ LINK_QUAL_PATTERN_SET_OFF = 0x0,
+ /* D10.2 unscrambled test pattern transmitted */
+ LINK_QUAL_PATTERN_SET_D102_TEST = 0x1,
+ /* symbol error rate measurement pattern transmitted */
+ LINK_QUAL_PATTERN_SET_SER_MES = 0x2,
+ /* pseudo random bit sequence 7 transmitted */
+ LINK_QUAL_PATTERN_SET_PRBS7 = 0x3,
+};
+
+enum {
+ SOFT_RESET_VIDEO_STREAM1_MASK = 0x00000001,
+ SOFT_RESET_VIDEO_STREAM2_MASK = 0x00000002,
+ SOFT_RESET_VIDEO_STREAM3_MASK = 0x00000004,
+ SOFT_RESET_VIDEO_STREAM4_MASK = 0x00000008,
+ SOFT_RESET_AUX_MASK = 0x00000080,
+ SOFT_RESET_VIDEO_STREAM_ALL_MASK = 0x0000000F,
+};
+
+enum {
+ MST_CONFIG_MST_EN_MASK = 0x00000001,
+};
+
+enum {
+ LINE_RESET_DISABLE_MASK = 0x1,
+};
+
+#define AUX_CMD_NBYTES_TRANSFER_MASK 0x0000000F
+
+#define AUX_CMD_SHIFT 8
+#define AUX_CMD_MASK 0x00000F00
+enum {
+ AUX_CMD_I2C_WRITE = 0x0,
+ AUX_CMD_I2C_READ = 0x1,
+ AUX_CMD_I2C_WRITE_STATUS = 0x2,
+ AUX_CMD_I2C_WRITE_MOT = 0x4,
+ AUX_CMD_I2C_READ_MOT = 0x5,
+ AUX_CMD_I2C_WRITE_STATUS_MOT = 0x6,
+ AUX_CMD_WRITE = 0x8,
+ AUX_CMD_READ = 0x9,
+};
+
+#define AUX_CLK_DIVIDER_VAL_MASK 0x00FF
+
+#define AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT 8
+#define AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK 0xFF00
+
+enum {
+ INTERRUPT_SIG_STATE_HPD_STATE_MASK = 0x00000001,
+ INTERRUPT_SIG_STATE_REQUEST_STATE_MASK = 0x00000002,
+ INTERRUPT_SIG_STATE_REPLY_STATE_MASK = 0x00000004,
+ INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK = 0x00000008,
+};
+
+enum {
+ AUX_REPLY_CODE_ACK = 0x0,
+ AUX_REPLY_CODE_I2C_ACK = 0x0,
+ AUX_REPLY_CODE_NACK = 0x1,
+ AUX_REPLY_CODE_DEFER = 0x2,
+ AUX_REPLY_CODE_I2C_NACK = 0x4,
+ AUX_REPLY_CODE_I2C_DEFER = 0x8,
+};
+
+enum {
+ INTERRUPT_STATUS_HPD_IRQ_MASK = 0x00000001,
+ INTERRUPT_STATUS_HPD_EVENT_MASK = 0x00000002,
+ INTERRUPT_STATUS_REPLY_RECEIVED_MASK = 0x00000004,
+ INTERRUPT_STATUS_REPLY_TIMEOUT_MASK = 0x00000008,
+ INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK = 0x00000010,
+ INTERRUPT_STATUS_EXT_PKT_TXD_MASK = 0x00000020,
+};
+
+enum {
+ INTERRUPT_MASK_HPD_IRQ_MASK = 0x00000001,
+ INTERRUPT_MASK_HPD_EVENT_MASK = 0x00000002,
+ INTERRUPT_MASK_REPLY_RECEIVED_MASK = 0x00000004,
+ INTERRUPT_MASK_REPLY_TIMEOUT_MASK = 0x00000008,
+ INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK = 0x00000010,
+ INTERRUPT_MASK_EXT_PKT_TXD_MASK = 0x00000020,
+};
+
+#define REPLY_STATUS_REPLY_STATUS_STATE_SHIFT 4
+#define REPLY_STATUS_REPLY_STATUS_STATE_MASK 0x00000FF0
+enum {
+ REPLY_STATUS_REPLY_RECEIVED_MASK = 0x00000001,
+ REPLY_STATUS_REPLY_IN_PROGRESS_MASK = 0x00000002,
+ REPLY_STATUS_REQUEST_IN_PROGRESS_MASK = 0x00000004,
+ REPLY_STATUS_REPLY_ERROR_MASK = 0x00000008,
+};
+
+#define MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT 1
+enum {
+ MAIN_STREAMX_POLARITY_HSYNC_POL_MASK = 0x00000001,
+ MAIN_STREAMX_POLARITY_VSYNC_POL_MASK = 0x00000002,
+};
+
+enum {
+ MAIN_STREAMX_MISC0_SYNC_CLK_MASK = 0x00000001,
+};
+
+#define MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT 1
+#define MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK 0x00000006
+enum {
+ MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB = 0x0,
+ MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422 = 0x1,
+ MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444 = 0x2,
+};
+
+#define MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT 3
+#define MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK 0x00000008
+
+#define MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT 4
+#define MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK 0x00000010
+
+#define MAIN_STREAMX_MISC0_BDC_SHIFT 5
+#define MAIN_STREAMX_MISC0_BDC_MASK 0x000000E0
+enum {
+ MAIN_STREAMX_MISC0_BDC_6BPC = 0x0,
+ MAIN_STREAMX_MISC0_BDC_8BPC = 0x1,
+ MAIN_STREAMX_MISC0_BDC_10BPC = 0x2,
+ MAIN_STREAMX_MISC0_BDC_12BPC = 0x3,
+ MAIN_STREAMX_MISC0_BDC_16BPC = 0x4,
+};
+
+enum {
+ PHY_CONFIG_PHY_RESET_ENABLE_MASK = 0x0000000,
+ PHY_CONFIG_PHY_RESET_MASK = 0x0000001,
+ PHY_CONFIG_GTTX_RESET_MASK = 0x0000002,
+ PHY_CONFIG_GT_ALL_RESET_MASK = 0x0000003,
+ PHY_CONFIG_TX_PHY_PMA_RESET_MASK = 0x0000100,
+ PHY_CONFIG_TX_PHY_PCS_RESET_MASK = 0x0000200,
+ PHY_CONFIG_TX_PHY_POLARITY_MASK = 0x0000800,
+ PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK = 0x0001000,
+ PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK = 0x0010000,
+ PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK = 0x0020000,
+ PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK = 0x0040000,
+ PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK = 0x0080000,
+ PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK = 0x0100000,
+ PHY_CONFIG_TX_PHY_8B10BEN_MASK = 0x0200000,
+};
+
+#define PHY_CONFIG_TX_PHY_LOOPBACK_SHIFT 13
+#define PHY_CONFIG_TX_PHY_LOOPBACK_MASK 0x000E000
+
+enum {
+ PHY_CLOCK_SELECT_162GBPS = 0x1,
+ PHY_CLOCK_SELECT_270GBPS = 0x3,
+ PHY_CLOCK_SELECT_540GBPS = 0x5,
+};
+
+enum {
+ VS_LEVEL_0 = 0x2,
+ VS_LEVEL_1 = 0x5,
+ VS_LEVEL_2 = 0x8,
+ VS_LEVEL_3 = 0xF,
+ VS_LEVEL_OFFSET = 0x4,
+};
+
+enum {
+ PE_LEVEL_0 = 0x00,
+ PE_LEVEL_1 = 0x0E,
+ PE_LEVEL_2 = 0x14,
+ PE_LEVEL_3 = 0x1B,
+};
+
+enum {
+ PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT = 2,
+ PHY_STATUS_TX_ERROR_LANE_0_SHIFT = 18,
+ PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT = 20,
+ PHY_STATUS_TX_ERROR_LANE_1_SHIFT = 22,
+ PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT = 16,
+ PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT = 24,
+ PHY_STATUS_TX_ERROR_LANE_2_SHIFT = 26,
+ PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT = 28,
+ PHY_STATUS_TX_ERROR_LANE_3_SHIFT = 30,
+};
+
+enum {
+ PHY_STATUS_RESET_LANE_0_DONE_MASK = 0x00000001,
+ PHY_STATUS_RESET_LANE_1_DONE_MASK = 0x00000002,
+ PHY_STATUS_RESET_LANE_2_3_DONE_MASK = 0x0000000C,
+ PHY_STATUS_PLL_LANE0_1_LOCK_MASK = 0x00000010,
+ PHY_STATUS_PLL_LANE2_3_LOCK_MASK = 0x00000020,
+ PHY_STATUS_PLL_FABRIC_LOCK_MASK = 0x00000040,
+ PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK = 0x00030000,
+ PHY_STATUS_TX_ERROR_LANE_0_MASK = 0x000C0000,
+ PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK = 0x00300000,
+ PHY_STATUS_TX_ERROR_LANE_1_MASK = 0x00C00000,
+ PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK = 0x03000000,
+ PHY_STATUS_TX_ERROR_LANE_2_MASK = 0x0C000000,
+ PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK = 0x30000000,
+ PHY_STATUS_TX_ERROR_LANE_3_MASK = 0xC0000000,
+};
+
+#define PHY_STATUS_LANE_0_READY_MASK \
+ (PHY_STATUS_RESET_LANE_0_DONE_MASK | \
+ PHY_STATUS_PLL_LANE0_1_LOCK_MASK)
+#define PHY_STATUS_LANES_0_1_READY_MASK \
+ (PHY_STATUS_LANE_0_READY_MASK | \
+ PHY_STATUS_RESET_LANE_1_DONE_MASK)
+/*
+ * PHY_STATUS_ALL_LANES_READY_MASK seems to be missing lanes 0 and 1 in
+ * Xilinx dp_v3_0 implementation
+ */
+#define PHY_STATUS_ALL_LANES_READY_MASK \
+ (PHY_STATUS_LANES_0_1_READY_MASK | \
+ PHY_STATUS_RESET_LANE_2_3_DONE_MASK | \
+ PHY_STATUS_PLL_LANE2_3_LOCK_MASK)
+
+/**
+ * phy_status_lanes_ready_mask() - Generate phy status ready mask
+ * @lane_count: Number of lanes for which to generate a mask
+ *
+ * Return: The generated phy status ready mask
+ */
+static inline u32 phy_status_lanes_ready_mask(u8 lane_count)
+{
+ if (lane_count > 2)
+ return PHY_STATUS_ALL_LANES_READY_MASK;
+
+ if (lane_count == 2)
+ return PHY_STATUS_LANES_0_1_READY_MASK;
+
+ return PHY_STATUS_LANE_0_READY_MASK;
+}
+
+#define GT_DRP_COMMAND_DRP_ADDR_MASK 0x000F
+#define GT_DRP_COMMAND_DRP_RW_CMD_MASK 0x0080
+#define GT_DRP_COMMAND_DRP_W_DATA_SHIFT 16
+#define GT_DRP_COMMAND_DRP_W_DATA_MASK 0xFF00
+
+#define HDCP_ENABLE_BYPASS_DISABLE_MASK 0x0001
+
+#endif /* __GDSYS_LOGICORE_DP_TX_REGIF_H__ */
continue;
printf("Loading Environment from %s... ", drv->name);
+ /*
+ * In error case, the error message must be printed during
+ * drv->load() in some underlying API, and it must be exactly
+ * one message.
+ */
ret = drv->load();
- if (ret)
- printf("Failed (%d)\n", ret);
- else
+ if (ret) {
+ debug("Failed (%d)\n", ret);
+ } else {
printf("OK\n");
-
- if (!ret)
return 0;
+ }
}
/*
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017, 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#ifndef _AXI_H_
+#define _AXI_H_
+
+/**
+ * enum axi_size_t - Determine size of AXI transfer
+ * @AXI_SIZE_8: AXI sransfer is 8-bit wide
+ * @AXI_SIZE_16: AXI sransfer is 16-bit wide
+ * @AXI_SIZE_32: AXI sransfer is 32-bit wide
+ */
+enum axi_size_t {
+ AXI_SIZE_8,
+ AXI_SIZE_16,
+ AXI_SIZE_32,
+};
+
+struct axi_ops {
+ /**
+ * read() - Read a single value from a specified address on a AXI bus
+ * @dev: AXI bus to read from.
+ * @address: The address to read from.
+ * @data: Pointer to a variable that takes the data value read
+ * from the address on the AXI bus.
+ * @size: The size of the data to be read.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+ int (*read)(struct udevice *dev, ulong address, void *data,
+ enum axi_size_t size);
+
+ /**
+ * write() - Write a single value to a specified address on a AXI bus
+ * @dev: AXI bus to write to.
+ * @address: The address to write to.
+ * @data: Pointer to the data value to be written to the address
+ * on the AXI bus.
+ * @size: The size of the data to write.
+ *
+ * Return 0 if OK, -ve on error.
+ */
+ int (*write)(struct udevice *dev, ulong address, void *data,
+ enum axi_size_t size);
+};
+
+#define axi_get_ops(dev) ((struct axi_ops *)(dev)->driver->ops)
+
+/**
+ * axi_read() - Read a single value from a specified address on a AXI bus
+ * @dev: AXI bus to read from.
+ * @address: The address to read from.
+ * @data: Pointer to a variable that takes the data value read from the
+ * address on the AXI bus.
+ * @size: The size of the data to write.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+int axi_read(struct udevice *dev, ulong address, void *data,
+ enum axi_size_t size);
+
+/**
+ * axi_write() - Write a single value to a specified address on a AXI bus
+ * @dev: AXI bus to write to.
+ * @address: The address to write to.
+ * @data: Pointer to the data value to be written to the address on the
+ * AXI bus.
+ * @size: The size of the data to write.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+int axi_write(struct udevice *dev, ulong address, void *data,
+ enum axi_size_t size);
+
+struct axi_emul_ops {
+ /**
+ * read() - Read a single value from a specified address on a AXI bus
+ * @dev: AXI bus to read from.
+ * @address: The address to read from.
+ * @data: Pointer to a variable that takes the data value read
+ * from the address on the AXI bus.
+ * @size: The size of the data to be read.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+ int (*read)(struct udevice *dev, ulong address, void *data,
+ enum axi_size_t size);
+
+ /**
+ * write() - Write a single value to a specified address on a AXI bus
+ * @dev: AXI bus to write to.
+ * @address: The address to write to.
+ * @data: Pointer to the data value to be written to the address
+ * on the AXI bus.
+ * @size: The size of the data to write.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+ int (*write)(struct udevice *dev, ulong address, void *data,
+ enum axi_size_t size);
+
+ /**
+ * get_store() - Get address of internal storage of a emulated AXI
+ * device
+ * @dev: Emulated AXI device to get the pointer of the internal
+ * storage for.
+ * @storep: Pointer to the internal storage of the emulated AXI
+ * device.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+ int (*get_store)(struct udevice *dev, u8 **storep);
+};
+
+#endif
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#endif /* CONFIG_CMD_NET */
-/*
- * Time settings
- */
-#define CONFIG_RTC_MV
-
#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */
#endif /* _CONFIG_SBX81LIFKW_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Allied Telesis <www.alliedtelesis.co.nz>
+ */
+
+#ifndef _CONFIG_SBX81LIFXCAT_H
+#define _CONFIG_SBX81LIFXCAT_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
+#define CONFIG_KW88F6281 1 /* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
+#define CONFIG_BUILD_TARGET "u-boot.kwb"
+
+/* additions for new ARM relocation support */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
+#define CONFIG_KIRKWOOD_GPIO 1
+
+#define CONFIG_MISC_INIT_R /* call misc_init_r */
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
+
+#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)"
+#define MTDPARTS_MTDOOPS "errlog"
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */
+#define CONFIG_ENV_SIZE 0x02000
+#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here - 768K */
+
+/*
+ * U-Boot bootcode configuration
+ */
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */
+#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
+
+/* size in bytes reserved for initial data */
+
+#include <asm/arch/config.h>
+/* There is no PHY directly connected so don't ask it for link status */
+#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#define CONFIG_NR_DRAM_BANKS 4
+#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
+#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* specify more that one ports available */
+#define CONFIG_MII /* expose smi over miiphy interface */
+#define CONFIG_MVGBE /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */
+#define CONFIG_PHY_BASE_ADR 0x01
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#endif /* CONFIG_CMD_NET */
+
+#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */
+
+#endif /* _CONFIG_SBX81LIFXCAT_H */
/*
* Board NAND Info.
*/
-#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access */
/* nand at CS0 */
/* Board NAND Info. */
#ifdef CONFIG_NAND
-#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6838_H
+#define __CONFIG_BMIPS_BCM6838_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ 160000000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM6838_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6838.h>
+
+#define CONFIG_ENV_SIZE (8 * 1024)
"initrd_high=0x10000000\0"
/* SPL */
-/*
- * Select the boot device here
- *
- * Currently supported are:
- * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
- * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
- */
-#define SPL_BOOT_SPI_NOR_FLASH 1
-#define SPL_BOOT_SDIO_MMC_CARD 2
-#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD
/* Defines for SPL */
#define CONFIG_SPL_SIZE (140 << 10)
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
-#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
+#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI)
/* SPL related SPI defines */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
-#endif
-
-#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
+#elif defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC)
/* SPL related MMC defines */
#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
/*
* Board NAND Info.
*/
-#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
/*
* Board NAND Info.
*/
-#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-/*
- * This file contains the configuration parameters for the dbau1x00 board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
-
-#ifdef CONFIG_DBAU1000
-/* Also known as Merlot */
-#define CONFIG_SOC_AU1000 1
-#else
-#ifdef CONFIG_DBAU1100
-#define CONFIG_SOC_AU1100 1
-#else
-#ifdef CONFIG_DBAU1500
-#define CONFIG_SOC_AU1500 1
-#else
-#ifdef CONFIG_DBAU1550
-/* Cabernet */
-#define CONFIG_SOC_AU1550 1
-#else
-#error "No valid board set"
-#endif
-#endif
-#endif
-#endif
-
-/* valid baudrates */
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "addmisc=setenv bootargs ${bootargs} " \
- "console=ttyS0,${baudrate} " \
- "panic=1\0" \
- "bootfile=/tftpboot/vmlinux.srec\0" \
- "load=tftp 80500000 ${u-boot}\0" \
- ""
-
-#ifdef CONFIG_DBAU1550
-/* Boot from flash by default, revert to bootp */
-#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
-#else /* CONFIG_DBAU1550 */
-#define CONFIG_BOOTCOMMAND "bootp;bootm"
-#endif /* CONFIG_DBAU1550 */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * Command line configuration.
- */
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_MALLOC_LEN 128*1024
-
-#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
-
-#define CONFIG_SYS_MHZ 396
-
-#if (CONFIG_SYS_MHZ % 12) != 0
-#error "Invalid CPU frequency - must be multiple of 12!"
-#endif
-
-#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
-
-#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
-
-#define CONFIG_SYS_MEMTEST_START 0x80100000
-#define CONFIG_SYS_MEMTEST_END 0x80800000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#ifdef CONFIG_DBAU1550
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
-
-#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
-
-#else /* CONFIG_DBAU1550 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
-
-#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
-#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
-
-#endif /* CONFIG_DBAU1550 */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
-
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_FLASH_CFI_DRIVER 1
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 << 10)
-
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-
-/* We boot from this flash, selected with dip switch */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-/* Address and size of Primary Environment Sector */
-#define CONFIG_ENV_ADDR 0xB0030000
-#define CONFIG_ENV_SIZE 0x10000
-
-#define CONFIG_FLASH_16BIT
-
-#define CONFIG_NR_DRAM_BANKS 2
-
-#ifdef CONFIG_DBAU1550
-#define MEM_SIZE 192
-#else
-#define MEM_SIZE 64
-#endif
-
-#define CONFIG_MEMSIZE_IN_BYTES
-
-#ifndef CONFIG_DBAU1550
-/*---ATA PCMCIA ------------------------------------*/
-#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
-#define CONFIG_PCMCIA_SLOT_A
-
-#define CONFIG_ATAPI 1
-
-/* We run CF in "true ide" mode or a harddrive via pcmcia */
-#define CONFIG_IDE_PCMCIA 1
-
-/* We only support one slot for now */
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET 8
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET 0
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-#endif /* CONFIG_DBAU1550 */
-
-#endif /* __CONFIG_H */
#define CONFIG_TWL4030_LED 1
/* Board NAND Info */
-
-#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
#endif
/*
- * RTC driver configuration
- */
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_MV
-#endif
-
-/*
* Enable GPI0 support
*/
#define CONFIG_KIRKWOOD_GPIO
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
+ func(MMC, mmc, 2) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#endif /*CONFIG_MVSATA_IDE*/
-/*
- * * RTC driver configuration
- * */
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_MV
-#endif /* CONFIG_CMD_DATE */
-
#endif /* _CONFIG_GOFLEXHOME_H */
/*
* Board NAND Info.
*/
-#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access */
/* nand at CS0 */
*/
#include "mv-common.h"
-/*
- * RTC driver configuration
- */
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_MV
-#endif /* CONFIG_CMD_DATE */
-
#endif /* _CONFIG_MARVELL_PLUG_H */
#define CONFIG_SF_DEFAULT_SPEED 1000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
/* Environment in SPI NOR flash */
#define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */
* EFI partition
*/
-/*
- * Date Time
- */
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_MV
-#endif /* CONFIG_CMD_DATE */
-
#define CONFIG_KIRKWOOD_GPIO
#endif /* _CONFIG_NAS220_H */
/* Console configuration */
-#define CONFIG_BOOTCOMMAND "run autoboot"
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd ; run autoboot"
#define CONFIG_DEFAULT_CONSOLE "ttySAC1,115200n8"
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
-#define CONFIG_ENV_SIZE 4096
+#define CONFIG_ENV_SIZE SZ_16K
#define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */
#define CONFIG_ENV_OVERWRITE
"bl2 raw 0x1f 0x1d;" \
"tzsw raw 0x83f 0x138\0"
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0)
+
+#include <config_distro_bootcmd.h>
+
/*
* Bootable media layout:
* dev: SD eMMC(part boot)
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadbootscript=load mmc ${mmcbootdev}:${mmcbootpart} ${scriptaddr} " \
"boot.scr\0" \
- "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \
+ "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kernel_addr_r} " \
"${kernelname}\0" \
- "loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \
+ "loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${ramdisk_addr_r} " \
"${initrdname}\0" \
- "loaddtb=load mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \
+ "loaddtb=load mmc ${mmcbootdev}:${mmcbootpart} ${fdt_addr_r} " \
"${fdtfile}\0" \
"check_ramdisk=" \
"if run loadinitrd; then " \
- "setenv initrd_addr ${initrdaddr};" \
+ "setenv initrd_addr ${ramdisk_addr_r};" \
"else " \
"setenv initrd_addr -;" \
"fi;\0" \
"check_dtb=" \
"if run loaddtb; then " \
- "setenv fdt_addr ${fdtaddr};" \
+ "setenv fdt_addr ${fdt_addr_r};" \
"else " \
"setenv fdt_addr;" \
"fi;\0" \
"run loadbootscript;" \
"source ${scriptaddr}\0" \
"boot_fit=" \
- "setenv kerneladdr 0x42000000;" \
"setenv kernelname Image.itb;" \
"run loadkernel;" \
"run kernel_args;" \
- "bootm ${kerneladdr}#${boardname}\0" \
+ "bootm ${kernel_addr_r}#${boardname}\0" \
"boot_uimg=" \
- "setenv kerneladdr 0x40007FC0;" \
"setenv kernelname uImage;" \
"run check_dtb;" \
"run check_ramdisk;" \
"run loadkernel;" \
"run kernel_args;" \
- "bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \
+ "bootm ${kernel_addr_r} ${initrd_addr} ${fdt_addr};\0" \
"boot_zimg=" \
- "setenv kerneladdr 0x40007FC0;" \
"setenv kernelname zImage;" \
"run check_dtb;" \
"run check_ramdisk;" \
"run loadkernel;" \
"run kernel_args;" \
- "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \
+ "bootz ${kernel_addr_r} ${initrd_addr} ${fdt_addr};\0" \
"autoboot=" \
"if test -e mmc 0 boot.scr; then; " \
"run boot_script; " \
"mmcbootpart=1\0" \
"mmcrootdev=0\0" \
"mmcrootpart=2\0" \
- "bootdelay=0\0" \
"dfu_alt_system="CONFIG_DFU_ALT \
"dfu_alt_info=Please reset the board\0" \
"consoleon=set console console=ttySAC1,115200n8; save; reset\0" \
"consoleoff=set console console=ram; save; reset\0" \
"initrdname=uInitrd\0" \
- "initrdaddr=42000000\0" \
+ "ramdisk_addr_r=0x42000000\0" \
"scriptaddr=0x42000000\0" \
- "fdtaddr=40800000\0"
+ "fdt_addr_r=0x40800000\0" \
+ "kernel_addr_r=0x41000000\0" \
+ BOOTENV
/* GPT */
/* Board NAND Info. */
#ifdef CONFIG_NAND
-#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#endif /* CONFIG_NAND */
/* Board NAND Info. */
-#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
/*
* Board NAND Info.
*/
-#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
/*
* Board NAND Info.
*/
-#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-/*
- * This file contains the configuration parameters for the dbau1x00 board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
-
-#ifdef CONFIG_PB1000
-#define CONFIG_SOC_AU1000 1
-#else
-#ifdef CONFIG_PB1100
-#define CONFIG_SOC_AU1100 1
-#else
-#ifdef CONFIG_PB1500
-#define CONFIG_SOC_AU1500 1
-#else
-#error "No valid board set"
-#endif
-#endif
-#endif
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "addmisc=setenv bootargs ${bootargs} " \
- "console=ttyS0,${baudrate} " \
- "panic=1\0" \
- "bootfile=/vmlinux.img\0" \
- "load=tftp 80500000 ${u-boot}\0" \
- ""
-/* Boot from NFS root */
-#define CONFIG_BOOTCOMMAND "bootp; setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; bootm"
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_MALLOC_LEN 128*1024
-
-#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
-
-#define CONFIG_SYS_MIPS_TIMER_FREQ 396000000
-
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
-
-#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
-
-#define CONFIG_SYS_MEMTEST_START 0x80100000
-#undef CONFIG_SYS_MEMTEST_START
-#define CONFIG_SYS_MEMTEST_START 0x80200000
-#define CONFIG_SYS_MEMTEST_END 0x83800000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
-
-#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
-#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 << 10)
-
-#define CONFIG_SYS_INIT_SP_OFFSET 0x4000000
-
-/* We boot from this flash, selected with dip switch */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-/* Address and size of Primary Environment Sector */
-#define CONFIG_ENV_ADDR 0xB0030000
-#define CONFIG_ENV_SIZE 0x10000
-
-#define CONFIG_FLASH_16BIT
-
-#define CONFIG_NR_DRAM_BANKS 2
-
-#define CONFIG_MEMSIZE_IN_BYTES
-
-/*---USB -------------------------------------------*/
-#if 0
-#define CONFIG_USB_OHCI
-#endif
-
-/*---ATA PCMCIA ------------------------------------*/
-#if 0
-#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
-#define CONFIG_PCMCIA_SLOT_A
-
-#define CONFIG_ATAPI 1
-
-/* We run CF in "true ide" mode or a harddrive via pcmcia */
-#define CONFIG_IDE_PCMCIA 1
-
-/* We only support one slot for now */
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET 8
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET 0
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * Command line configuration.
- */
-
-#endif /* __CONFIG_H */
#ifndef __CONFIG_SNOW_H
#define __CONFIG_SNOW_H
+#define EXYNOS_FDTFILE_SETTING \
+ "fdtfile=exynos5250-snow.dtb\0"
+
#include <configs/exynos5250-common.h>
#include <configs/exynos5-dt-common.h>
#include <configs/exynos5-common.h>
#define CONFIG_SF_DEFAULT_SPEED 50000000
#define CONFIG_SERIAL_FLASH
#define CONFIG_HARD_SPI
-#define CONFIG_SPI_FLASH_ISSI
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 1
/*
* Board NAND Info.
*/
-#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#undef CONFIG_SPI_FLASH_WINBOND
-#undef CONFIG_SPI_FLASH_ISSI
/* Setup proper boot sequences for Miami boards */
#define CONFIG_TWL4030_LED
/* Board NAND Info */
-
-#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#ifdef CONFIG_TURRIS_OMNIA_SPL_BOOT_DEVICE_SPI
+#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI
/* SPL related SPI defines */
# define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
# define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif
-#ifdef CONFIG_TURRIS_OMNIA_SPL_BOOT_DEVICE_MMC
+#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC
/* SPL related MMC defines */
# define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
# define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
#undef CONFIG_BOOTP_MAY_FAIL
#undef CONFIG_NR_DRAM_BANKS
+#define CONFIG_NR_DRAM_BANKS 1
#endif /* __CONFIG_ZYNQMP_MINI_H */
#include <configs/xilinx_zynqmp_mini.h>
#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x800000
#include <configs/xilinx_zynqmp_mini.h>
#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_SIZE 0x1000000
#define CONFIG_SYS_SDRAM_BASE 0x0
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x40000)
#include <configs/xilinx_zynqmp_mini.h>
#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000)
#define CONFIG_SYS_MALLOC_LEN 0x2000
/* QSPI */
#ifdef CONFIG_ZYNQ_QSPI
# define CONFIG_SF_DEFAULT_SPEED 30000000
-# define CONFIG_SPI_FLASH_ISSI
#endif
/* NOR */
#define CONFIG_SYS_MEMTEST_START 0
#define CONFIG_SYS_MEMTEST_END 0x1000
-#define CONFIG_SYS_MALLOC_LEN 0x1400000
-
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
#define CONFIG_SPL_BSS_START_ADDR 0x20000
#define CONFIG_SPL_BSS_MAX_SIZE 0x8000
-#undef CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SYS_MALLOC_LEN 0x1000
-
#endif /* __CONFIG_ZYNQ_CSE_H */
const char *propname, struct fdt_pci_addr *addr);
/**
+ * ofnode_read_pci_vendev() - look up PCI vendor and device id
+ *
+ * Look at the compatible property of a device node that represents a PCI
+ * device and extract pci vendor id and device id from it.
+ *
+ * @param node node to examine
+ * @param vendor vendor id of the pci device
+ * @param device device id of the pci device
+ * @return 0 if ok, negative on error
+ */
+int ofnode_read_pci_vendev(ofnode node, u16 *vendor, u16 *device);
+
+/**
* ofnode_read_addr_cells() - Get the number of address cells for a node
*
* This walks back up the tree to find the closest #address-cells property
UCLASS_I2C_EMUL, /* sandbox I2C device emulator */
UCLASS_PCI_EMUL, /* sandbox PCI device emulator */
UCLASS_USB_EMUL, /* sandbox USB bus device emulator */
+ UCLASS_AXI_EMUL, /* sandbox AXI bus device emulator */
UCLASS_SIMPLE_BUS, /* bus with child devices */
/* U-Boot uclasses start here - in alphabetical order */
UCLASS_I2C_GENERIC, /* Generic I2C device */
UCLASS_I2C_MUX, /* I2C multiplexer */
UCLASS_IDE, /* IDE device */
+ UCLASS_AXI, /* AXI bus */
UCLASS_IRQ, /* Interrupt controller */
UCLASS_KEYBOARD, /* Keyboard input device */
UCLASS_LED, /* Light-emitting diode (LED) */
int uclass_next_device(struct udevice **devp);
/**
- * uclass_first_device() - Get the first device in a uclass
+ * uclass_first_device_check() - Get the first device in a uclass
*
* The device returned is probed if necessary, and ready for use
*
int uclass_first_device_check(enum uclass_id id, struct udevice **devp);
/**
- * uclass_next_device() - Get the next device in a uclass
+ * uclass_next_device_check() - Get the next device in a uclass
*
* The device returned is probed if necessary, and ready for use
*
/* Values for Elf32/64_Ehdr.e_flags */
#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */
+#define EF_PPC64_ELFV1_ABI 0x00000001
+#define EF_PPC64_ELFV2_ABI 0x00000002
+
/* Cygnus local bits below */
#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/
#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib
*/
int led_set_period(struct udevice *dev, int period_ms);
+/**
+ * led_default_state() - set the default state for all the LED
+ *
+ * This enables all leds which have default state.
+ * see Documentation/devicetree/bindings/leds/common.txt
+ *
+ */
+int led_default_state(void);
+
#endif
#ifndef _MISC_H_
#define _MISC_H_
-/*
- * Read the device to buffer, optional.
- *
+/**
+ * misc_read() - Read the device to buffer, optional.
* @dev: the device
* @offset: offset to read the device
* @buf: pointer to data buffer
* @size: data size in bytes to read the device
- * @return: 0 if OK, -ve on error
+ *
+ * Return: 0 if OK, -ve on error
*/
int misc_read(struct udevice *dev, int offset, void *buf, int size);
-/*
- * Write buffer to the device, optional.
- *
+
+/**
+ * misc_write() - Write buffer to the device, optional.
* @dev: the device
* @offset: offset to write the device
* @buf: pointer to data buffer
* @size: data size in bytes to write the device
- * @return: 0 if OK, -ve on error
+ *
+ * Return: 0 if OK, -ve on error
*/
int misc_write(struct udevice *dev, int offset, void *buf, int size);
-/*
- * Assert command to the device, optional.
- *
+
+/**
+ * misc_ioctl() - Assert command to the device, optional.
* @dev: the device
* @request: command to be sent to the device
* @buf: pointer to buffer related to the request
- * @return: 0 if OK, -ve on error
+ *
+ * Return: 0 if OK, -ve on error
*/
int misc_ioctl(struct udevice *dev, unsigned long request, void *buf);
-/*
- * Send a message to the device and wait for a response.
+/**
+ * misc_call() - Send a message to the device and wait for a response.
+ * @dev: the device.
+ * @msgid: the message ID/number to send.
+ * @tx_msg: the request/transmit message payload.
+ * @tx_size: the size of the buffer pointed at by tx_msg.
+ * @rx_msg: the buffer to receive the response message payload. May be NULL if
+ * the caller only cares about the error code.
+ * @rx_size: the size of the buffer pointed at by rx_msg.
*
* The caller provides the message type/ID and payload to be sent.
* The callee constructs any message header required, transmits it to the
* strips any message header from the response, and returns the error code
* (or a parsed version of it) and the response message payload.
*
- * @dev: the device.
- * @msgid: the message ID/number to send.
- * tx_msg: the request/transmit message payload.
- * tx_size: the size of the buffer pointed at by tx_msg.
- * rx_msg: the buffer to receive the response message payload. May be NULL if
- * the caller only cares about the error code.
- * rx_size: the size of the buffer pointed at by rx_msg.
- * @return the response message size if OK, -ve on error
+ * Return: the response message size if OK, -ve on error
*/
int misc_call(struct udevice *dev, int msgid, void *tx_msg, int tx_size,
void *rx_msg, int rx_size);
+/**
+ * misc_set_enabled() - Enable or disable a device.
+ * @dev: the device to enable or disable.
+ * @val: the flag that tells the driver to either enable or disable the device.
+ *
+ * The semantics of "disable" and "enable" should be understood here as
+ * activating or deactivating the device's primary function, hence a "disabled"
+ * device should be dormant, but still answer to commands and queries.
+ *
+ * A probed device may start in a disabled or enabled state, depending on the
+ * driver and hardware.
+ *
+ * Return: -ve on error, 0 if the previous state was "disabled", 1 if the
+ * previous state was "enabled"
+ */
+int misc_set_enabled(struct udevice *dev, bool val);
+
/*
* struct misc_ops - Driver model Misc operations
*
* use driver model.
*/
struct misc_ops {
- /*
+ /**
* Read the device to buffer, optional.
- *
* @dev: the device
* @offset: offset to read the device
* @buf: pointer to data buffer
* @size: data size in bytes to read the device
- * @return: 0 if OK, -ve on error
+ *
+ * Return: 0 if OK, -ve on error
*/
int (*read)(struct udevice *dev, int offset, void *buf, int size);
- /*
+
+ /**
* Write buffer to the device, optional.
- *
* @dev: the device
* @offset: offset to write the device
* @buf: pointer to data buffer
* @size: data size in bytes to write the device
- * @return: 0 if OK, -ve on error
+ *
+ * Return: 0 if OK, -ve on error
*/
int (*write)(struct udevice *dev, int offset, const void *buf,
int size);
- /*
+ /**
* Assert command to the device, optional.
- *
* @dev: the device
* @request: command to be sent to the device
* @buf: pointer to buffer related to the request
- * @return: 0 if OK, -ve on error
+ *
+ * Return: 0 if OK, -ve on error
*/
int (*ioctl)(struct udevice *dev, unsigned long request, void *buf);
- /*
+
+ /**
* Send a message to the device and wait for a response.
- *
* @dev: the device
* @msgid: the message ID/number to send
- * tx_msg: the request/transmit message payload
- * tx_size: the size of the buffer pointed at by tx_msg
- * rx_msg: the buffer to receive the response message payload. May be
- * NULL if the caller only cares about the error code.
- * rx_size: the size of the buffer pointed at by rx_msg
- * @return the response message size if OK, -ve on error
+ * @tx_msg: the request/transmit message payload
+ * @tx_size: the size of the buffer pointed at by tx_msg
+ * @rx_msg: the buffer to receive the response message payload. May be
+ * NULL if the caller only cares about the error code.
+ * @rx_size: the size of the buffer pointed at by rx_msg
+ *
+ * Return: the response message size if OK, -ve on error
*/
int (*call)(struct udevice *dev, int msgid, void *tx_msg, int tx_size,
void *rx_msg, int rx_size);
+ /**
+ * Enable or disable a device, optional.
+ * @dev: the device to enable.
+ * @val: the flag that tells the driver to either enable or disable the
+ * device.
+ *
+ * Return: -ve on error, 0 if the previous state was "disabled", 1 if
+ * the previous state was "enabled"
+ */
+ int (*set_enabled)(struct udevice *dev, bool val);
};
#endif /* _MISC_H_ */
/* Driver initialization prototypes */
int at91emac_register(bd_t *bis, unsigned long iobase);
-int au1x00_enet_initialize(bd_t*);
int ax88180_initialize(bd_t *bis);
int bcm_sf2_eth_register(bd_t *bis, u8 dev_num);
int bfin_EMAC_initialize(bd_t *bis);
* Under PCI, each device has 256 bytes of configuration address space,
* of which the first 64 bytes are standardized as follows:
*/
+#define PCI_STD_HEADER_SIZEOF 64
#define PCI_VENDOR_ID 0x00 /* 16 bits */
#define PCI_DEVICE_ID 0x02 /* 16 bits */
#define PCI_COMMAND 0x04 /* 16 bits */
#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
-/* From 440ep */
-#define PCI_ERREN 0x48 /* Error Enable */
-#define PCI_ERRSTS 0x49 /* Error Status */
-#define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */
-#define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */
-#define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */
-#define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */
-#define PCI_CAPID 0x58 /* Capability Identifier */
-#define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */
-#define PCI_PMC 0x5A /* Power Management Capabilities */
-#define PCI_PMCSR 0x5C /* Power Management Control Status */
-#define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */
-#define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */
-#define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */
-
/* Header type 2 (CardBus bridges) */
#define PCI_CB_CAPABILITY_LIST 0x14
/* 0x15 reserved */
#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
-#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
+#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
+#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
+#define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
+#define PCI_CAP_ID_DBG 0x0A /* Debug port */
+#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
+#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
+#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
+#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
+#define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */
+#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
+#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
+#define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */
+#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
+#define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */
+#define PCI_CAP_ID_MAX PCI_CAP_ID_EA
#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
#define PCI_CAP_SIZEOF 4
#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
+#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
+#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
+#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
+#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
/* Include the ID list */
*/
void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
+/**
+ * dm_pci_find_capability() - find a capability
+ *
+ * Tell if a device supports a given PCI capability. Returns the
+ * address of the requested capability structure within the device's
+ * PCI configuration space or 0 in case the device does not support it.
+ *
+ * Possible values for @cap:
+ *
+ * %PCI_CAP_ID_MSI Message Signalled Interrupts
+ * %PCI_CAP_ID_PCIX PCI-X
+ * %PCI_CAP_ID_EXP PCI Express
+ * %PCI_CAP_ID_MSIX MSI-X
+ *
+ * See PCI_CAP_ID_xxx for the complete capability ID codes.
+ *
+ * @dev: PCI device to query
+ * @cap: capability code
+ * @return: capability address or 0 if not supported
+ */
+int dm_pci_find_capability(struct udevice *dev, int cap);
+
+/**
+ * dm_pci_find_ext_capability() - find an extended capability
+ *
+ * Tell if a device supports a given PCI express extended capability.
+ * Returns the address of the requested extended capability structure
+ * within the device's PCI configuration space or 0 in case the device
+ * does not support it.
+ *
+ * Possible values for @cap:
+ *
+ * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
+ * %PCI_EXT_CAP_ID_VC Virtual Channel
+ * %PCI_EXT_CAP_ID_DSN Device Serial Number
+ * %PCI_EXT_CAP_ID_PWR Power Budgeting
+ *
+ * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
+ *
+ * @dev: PCI device to query
+ * @cap: extended capability code
+ * @return: extended capability address or 0 if not supported
+ */
+int dm_pci_find_ext_capability(struct udevice *dev, int cap);
+
#define dm_pci_virt_to_bus(dev, addr, flags) \
dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
#define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
*
* @bus: PCI bus to search
* @find_devfn: PCI device and function address (PCI_DEVFN())
+ * @containerp: Returns container device if found
* @emulp: Returns emulated device if found
* @return 0 if found, -ENODEV if not found
*/
int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,
- struct udevice **emulp);
+ struct udevice **containerp, struct udevice **emulp);
#endif /* CONFIG_DM_PCI */
#define serial_get_ops(dev) ((struct dm_serial_ops *)(dev)->driver->ops)
void atmel_serial_initialize(void);
-void au1x00_serial_initialize(void);
void mcf_serial_initialize(void);
void mpc85xx_serial_initialize(void);
void mpc8xx_serial_initialize(void);
t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
t->product_name = smbios_add_string(t->eos, CONFIG_SMBIOS_PRODUCT_NAME);
if (serial_str) {
- strncpy((char*)t->uuid, serial_str, sizeof(t->uuid));
+ strncpy((char *)t->uuid, serial_str, sizeof(t->uuid));
t->serial_number = smbios_add_string(t->eos, serial_str);
}
/* populate minimum required tables */
for (i = 0; i < ARRAY_SIZE(smbios_write_funcs); i++) {
int tmp = smbios_write_funcs[i]((ulong *)&addr, handle++);
+
max_struct_size = max(max_struct_size, tmp);
len += tmp;
}
CONFIG_ARMADA100_FEC
CONFIG_ARMADA168
CONFIG_ARMADA_39X
-CONFIG_ARMV7_PSCI_0_2
CONFIG_ARMV7_PSCI_1_0
CONFIG_ARMV7_SECURE_BASE
CONFIG_ARMV7_SECURE_MAX_SIZE
CONFIG_ENV_RANGE
CONFIG_ENV_RDADDR
CONFIG_ENV_REFLASH
-CONFIG_ENV_SECT_SIZE
CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS
CONFIG_ENV_SETTINGS_NAND_V1
CONFIG_ENV_SETTINGS_NAND_V2
CONFIG_RTC_FTRTC010
CONFIG_RTC_IMXDI
CONFIG_RTC_M41T11
-CONFIG_RTC_M41T60
CONFIG_RTC_M41T62
CONFIG_RTC_MC13XXX
CONFIG_RTC_MC146818
CONFIG_SPI_BOOTING
CONFIG_SPI_CS_IS_VALID
CONFIG_SPI_DATAFLASH_WRITE_VERIFY
-CONFIG_SPI_FLASH_ISSI
CONFIG_SPI_FLASH_QUAD
CONFIG_SPI_FLASH_SIZE
CONFIG_SPI_HALF_DUPLEX
CONFIG_SYS_GPIO2_DAT
CONFIG_SYS_GPIO2_DIR
CONFIG_SYS_GPIO2_PRELIM
-CONFIG_SYS_GPIO_0_ADDR
CONFIG_SYS_GPIO_EN
CONFIG_SYS_GPIO_FUNC
CONFIG_SYS_GPIO_I2C_SCL
CONFIG_SYS_MACB3_BASE
CONFIG_SYS_MAIN_PWR_ON
CONFIG_SYS_MALLOC_BASE
-CONFIG_SYS_MALLOC_LEN
CONFIG_SYS_MALLOC_SIMPLE
CONFIG_SYS_MAMR
CONFIG_SYS_MAPLE
CONFIG_SYS_NAND_ACTL_CLE
CONFIG_SYS_NAND_ACTL_DELAY
CONFIG_SYS_NAND_ACTL_NCE
-CONFIG_SYS_NAND_ADDR
CONFIG_SYS_NAND_ALE
CONFIG_SYS_NAND_AMASK
CONFIG_SYS_NAND_BAD_BLOCK_POS
CONFIG_SYS_XHCI_USB1_ADDR
CONFIG_SYS_XHCI_USB2_ADDR
CONFIG_SYS_XHCI_USB3_ADDR
-CONFIG_SYS_XILINX_SPI_LIST
CONFIG_SYS_XIMG_LEN
CONFIG_SYS_XWAY_EBU_BOOTCFG
CONFIG_SYS_ZYNQ_QSPI_WAIT
CONFIG_VSC7385_IMAGE_SIZE
CONFIG_VSC9953
CONFIG_VSC_CROSSBAR
-CONFIG_WATCHDOG_BASEADDR
-CONFIG_WATCHDOG_IRQ
CONFIG_WATCHDOG_NOWAYOUT
CONFIG_WATCHDOG_PRESC
CONFIG_WATCHDOG_RC
CONFIG_X86_REFCODE_RUN_ADDR
CONFIG_XGI_XG22_BASE
CONFIG_XILINX_SPI_IDLE_VAL
-CONFIG_XILINX_TB_WATCHDOG
CONFIG_XR16L2751
CONFIG_XSENGINE
CONFIG_XTFPGA
* a struct called fdt_property. That struct causes swig to create a class in
* libfdt.py called fdt_property(), which confuses things.
*/
-static int _fdt_property(void *fdt, const char *name, const char *val, int len)
+static int fdt_property_stub(void *fdt, const char *name, const char *val,
+ int len)
{
return fdt_property(fdt, name, val, len);
}
# Pass this as the 'quiet' parameter to return -ENOTFOUND on NOTFOUND errors,
# instead of raising an exception.
QUIET_NOTFOUND = (NOTFOUND,)
+QUIET_NOSPACE = (NOSPACE,)
class FdtException(Exception):
raise FdtException(val)
return val
+class FdtRo(object):
+ """Class for a read-only device-tree
-class Fdt:
- """Device tree class, supporting all operations
-
- The Fdt object is created is created from a device tree binary file,
- e.g. with something like:
+ This is a base class used by FdtRw (read-write access) and FdtSw
+ (sequential-write access). It implements read-only access to the
+ device tree.
- fdt = Fdt(open("filename.dtb").read())
-
- Operations can then be performed using the methods in this class. Each
- method xxx(args...) corresponds to a libfdt function fdt_xxx(fdt, args...).
+ Here are the three classes and when you should use them:
- All methods raise an FdtException if an error occurs. To avoid this
- behaviour a 'quiet' parameter is provided for some functions. This
- defaults to empty, but you can pass a list of errors that you expect.
- If one of these errors occurs, the function will return an error number
- (e.g. -NOTFOUND).
+ FdtRo - read-only access to an existing FDT
+ FdtRw - read-write access to an existing FDT (most common case)
+ FdtSw - for creating a new FDT, as well as allowing read-only access
"""
def __init__(self, data):
self._fdt = bytearray(data)
Args:
nodeoffset: Node offset of previous node
- depth: On input, the depth of the node at nodeoffset. On output, the
- depth of the returned node
+ depth: The depth of the node at nodeoffset. This is used to
+ calculate the depth of the returned node
quiet: Errors to ignore (empty to raise on all errors)
Returns:
- The offset of the next node, if any
+ Typle:
+ Offset of the next node, if any, else a -ve error
+ Depth of the returned node, if any, else undefined
Raises:
FdtException if no more nodes found or other error occurs
Returns:
Magic word
"""
- return fdt_magic(self._fdt) & 0xffffffff
+ return fdt_magic(self._fdt)
def totalsize(self):
"""Return the total size of the device tree
Returns:
Total tree size in bytes
"""
- return check_err(fdt_totalsize(self._fdt))
+ return fdt_totalsize(self._fdt)
def off_dt_struct(self):
"""Return the start of the device-tree struct area
Returns:
Start offset of struct area
"""
- return check_err(fdt_off_dt_struct(self._fdt))
+ return fdt_off_dt_struct(self._fdt)
def off_dt_strings(self):
"""Return the start of the device-tree string area
Returns:
Start offset of string area
"""
- return check_err(fdt_off_dt_strings(self._fdt))
+ return fdt_off_dt_strings(self._fdt)
def off_mem_rsvmap(self):
"""Return the start of the memory reserve map
Returns:
Start offset of memory reserve map
"""
- return check_err(fdt_off_mem_rsvmap(self._fdt))
+ return fdt_off_mem_rsvmap(self._fdt)
def version(self):
"""Return the version of the device tree
Returns:
Version number of the device tree
"""
- return check_err(fdt_version(self._fdt))
+ return fdt_version(self._fdt)
def last_comp_version(self):
"""Return the last compatible version of the device tree
Returns:
Last compatible version number of the device tree
"""
- return check_err(fdt_last_comp_version(self._fdt))
+ return fdt_last_comp_version(self._fdt)
def boot_cpuid_phys(self):
"""Return the physical boot CPU ID
Returns:
Physical boot CPU ID
"""
- return check_err(fdt_boot_cpuid_phys(self._fdt))
+ return fdt_boot_cpuid_phys(self._fdt)
def size_dt_strings(self):
"""Return the start of the device-tree string area
Returns:
Start offset of string area
"""
- return check_err(fdt_size_dt_strings(self._fdt))
+ return fdt_size_dt_strings(self._fdt)
def size_dt_struct(self):
"""Return the start of the device-tree struct area
Returns:
Start offset of struct area
"""
- return check_err(fdt_size_dt_struct(self._fdt))
+ return fdt_size_dt_struct(self._fdt)
def num_mem_rsv(self, quiet=()):
"""Return the number of memory reserve-map records
return pdata
return Property(pdata[0], pdata[1])
- def get_property(self, nodeoffset, prop_name, quiet=()):
- """Obtains a property by name
+ def getprop(self, nodeoffset, prop_name, quiet=()):
+ """Get a property from a node
Args:
- nodeoffset: Offset to the node to check
+ nodeoffset: Node offset containing property to get
prop_name: Name of property to get
quiet: Errors to ignore (empty to raise on all errors)
Returns:
- Property object, or None if not found
+ Value of property as a Property object (which can be used as a
+ bytearray/string), or -ve error number. On failure, returns an
+ integer error
Raises:
- FdtException on error (e.g. invalid prop_offset or device
- tree format)
+ FdtError if any error occurs (e.g. the property is not found)
"""
- pdata = check_err_null(
- fdt_get_property(self._fdt, nodeoffset, prop_name), quiet)
+ pdata = check_err_null(fdt_getprop(self._fdt, nodeoffset, prop_name),
+ quiet)
if isinstance(pdata, (int)):
return pdata
- return Property(pdata[0], pdata[1])
+ return Property(prop_name, bytearray(pdata[0]))
+
+ def get_phandle(self, nodeoffset):
+ """Get the phandle of a node
+
+ Args:
+ nodeoffset: Node offset to check
+
+ Returns:
+ phandle of node, or 0 if the node has no phandle or another error
+ occurs
+ """
+ return fdt_get_phandle(self._fdt, nodeoffset)
+
+ def parent_offset(self, nodeoffset, quiet=()):
+ """Get the offset of a node's parent
+
+ Args:
+ nodeoffset: Node offset to check
+ quiet: Errors to ignore (empty to raise on all errors)
+
+ Returns:
+ The offset of the parent node, if any
+
+ Raises:
+ FdtException if no parent found or other error occurs
+ """
+ return check_err(fdt_parent_offset(self._fdt, nodeoffset), quiet)
+
+ def node_offset_by_phandle(self, phandle, quiet=()):
+ """Get the offset of a node with the given phandle
+
+ Args:
+ phandle: Phandle to search for
+ quiet: Errors to ignore (empty to raise on all errors)
+
+ Returns:
+ The offset of node with that phandle, if any
+
+ Raises:
+ FdtException if no node found or other error occurs
+ """
+ return check_err(fdt_node_offset_by_phandle(self._fdt, phandle), quiet)
+
+
+class Fdt(FdtRo):
+ """Device tree class, supporting all operations
+
+ The Fdt object is created is created from a device tree binary file,
+ e.g. with something like:
+
+ fdt = Fdt(open("filename.dtb").read())
+
+ Operations can then be performed using the methods in this class. Each
+ method xxx(args...) corresponds to a libfdt function fdt_xxx(fdt, args...).
+
+ All methods raise an FdtException if an error occurs. To avoid this
+ behaviour a 'quiet' parameter is provided for some functions. This
+ defaults to empty, but you can pass a list of errors that you expect.
+ If one of these errors occurs, the function will return an error number
+ (e.g. -NOTFOUND).
+ """
+ def __init__(self, data):
+ FdtRo.__init__(self, data)
@staticmethod
def create_empty_tree(size, quiet=()):
return err
return Fdt(data)
- def open_into(self, size, quiet=()):
+ def resize(self, size, quiet=()):
"""Move the device tree into a larger or smaller space
This creates a new device tree of size @size and moves the existing
device tree contents over to that. It can be used to create more space
- in a device tree.
+ in a device tree. Note that the Fdt object remains the same, but it
+ now has a new bytearray holding the contents.
Args:
size: Required new size of device tree in bytes
"""
fdt = bytearray(size)
- fdt[:len(self._fdt)] = self._fdt
err = check_err(fdt_open_into(self._fdt, fdt, size), quiet)
if err:
return err
Args:
quiet: Errors to ignore (empty to raise on all errors)
+ Returns:
+ Error code, or 0 if OK
+
Raises:
FdtException if any error occurs
"""
del self._fdt[self.totalsize():]
return err
- def getprop(self, nodeoffset, prop_name, quiet=()):
- """Get a property from a node
-
- Args:
- nodeoffset: Node offset containing property to get
- prop_name: Name of property to get
- quiet: Errors to ignore (empty to raise on all errors)
-
- Returns:
- Value of property as a string, or -ve error number
-
- Raises:
- FdtError if any error occurs (e.g. the property is not found)
- """
- pdata = check_err_null(fdt_getprop(self._fdt, nodeoffset, prop_name),
- quiet)
- if isinstance(pdata, (int)):
- return pdata
- return str(pdata[0])
-
- def getprop_obj(self, nodeoffset, prop_name, quiet=()):
- """Get a property from a node as a Property object
-
- Args:
- nodeoffset: Node offset containing property to get
- prop_name: Name of property to get
- quiet: Errors to ignore (empty to raise on all errors)
-
- Returns:
- Property object, or None if not found
-
- Raises:
- FdtError if any error occurs (e.g. the property is not found)
- """
- pdata = check_err_null(fdt_getprop(self._fdt, nodeoffset, prop_name),
- quiet)
- if isinstance(pdata, (int)):
- return None
- return Property(prop_name, bytearray(pdata[0]))
-
- def get_phandle(self, nodeoffset):
- """Get the phandle of a node
-
- Args:
- nodeoffset: Node offset to check
-
- Returns:
- phandle of node, or 0 if the node has no phandle or another error
- occurs
- """
- return fdt_get_phandle(self._fdt, nodeoffset)
-
- def parent_offset(self, nodeoffset, quiet=()):
- """Get the offset of a node's parent
-
- Args:
- nodeoffset: Node offset to check
- quiet: Errors to ignore (empty to raise on all errors)
-
- Returns:
- The offset of the parent node, if any
-
- Raises:
- FdtException if no parent found or other error occurs
- """
- return check_err(fdt_parent_offset(self._fdt, nodeoffset), quiet)
-
def set_name(self, nodeoffset, name, quiet=()):
"""Set the name of a node
Args:
nodeoffset: Node offset of node to update
- name: New node name
+ name: New node name (string without \0)
Returns:
Error code, or 0 if OK
Raises:
FdtException if no parent found or other error occurs
"""
+ if chr(0) in name:
+ raise ValueError('Property contains embedded nul characters')
return check_err(fdt_set_name(self._fdt, nodeoffset, name), quiet)
def setprop(self, nodeoffset, prop_name, val, quiet=()):
Args:
nodeoffset: Node offset containing the property to create/update
prop_name: Name of property
- val: Value to write (string without nul terminator)
+ val: Value to write (string without nul terminator). Unicode is
+ supposed by encoding to UTF-8
quiet: Errors to ignore (empty to raise on all errors)
Returns:
Raises:
FdtException if no parent found or other error occurs
"""
- val += '\0'
+ val = val.encode('utf-8') + '\0'
return check_err(fdt_setprop(self._fdt, nodeoffset, prop_name,
val, len(val)), quiet)
"""
return check_err(fdt_delprop(self._fdt, nodeoffset, prop_name))
- def node_offset_by_phandle(self, phandle, quiet=()):
- """Get the offset of a node with the given phandle
-
- Args:
- phandle: Phandle to search for
- quiet: Errors to ignore (empty to raise on all errors)
-
- Returns:
- The offset of node with that phandle, if any
-
- Raises:
- FdtException if no node found or other error occurs
- """
- return check_err(fdt_node_offset_by_phandle(self._fdt, phandle), quiet)
-
def del_node(self, nodeoffset):
"""Delete a node
return self.as_cell('q')
def as_str(self):
- return self[:-1]
+ """Unicode is supported by decoding from UTF-8"""
+ if self[-1] != 0:
+ raise ValueError('Property lacks nul termination')
+ if 0 in self[:-1]:
+ raise ValueError('Property contains embedded nul characters')
+ return self[:-1].decode('utf-8')
-class FdtSw(object):
+class FdtSw(FdtRo):
"""Software interface to create a device tree from scratch
The methods in this class work by adding to an existing 'partial' device
tree buffer of a fixed size created by instantiating this class. When the
- tree is complete, call finish() to complete the device tree so that it can
- be used.
+ tree is complete, call as_fdt() to obtain a device tree ready to be used.
Similarly with nodes, a new node is started with begin_node() and finished
with end_node().
The context manager functions can be used to make this a bit easier:
# First create the device tree with a node and property:
- with FdtSw(small_size) as sw:
- with sw.AddNode('node'):
- sw.property_u32('reg', 2)
- fdt = sw.AsFdt()
+ sw = FdtSw()
+ with sw.add_node('node'):
+ sw.property_u32('reg', 2)
+ fdt = sw.as_fdt()
# Now we can use it as a real device tree
fdt.setprop_u32(0, 'reg', 3)
+
+ The size hint provides a starting size for the space to be used by the
+ device tree. This will be increased automatically as needed as new items
+ are added to the tree.
"""
- def __init__(self, size, quiet=()):
- fdtrw = bytearray(size)
- err = check_err(fdt_create(fdtrw, size))
- if err:
- return err
- self._fdtrw = fdtrw
+ INC_SIZE = 1024 # Expand size by this much when out of space
- def __enter__(self):
- """Contact manager to use to create a device tree via software"""
- return self
+ def __init__(self, size_hint=None):
+ """Create a new FdtSw object
- def __exit__(self, type, value, traceback):
- check_err(fdt_finish(self._fdtrw))
+ Args:
+ size_hint: A hint as to the initial size to use
+
+ Raises:
+ ValueError if size_hint is negative
- def AsFdt(self):
+ Returns:
+ FdtSw object on success, else integer error code (if not raising)
+ """
+ if not size_hint:
+ size_hint = self.INC_SIZE
+ fdtsw = bytearray(size_hint)
+ err = check_err(fdt_create(fdtsw, size_hint))
+ if err:
+ return err
+ self._fdt = fdtsw
+
+ def as_fdt(self):
"""Convert a FdtSw into an Fdt so it can be accessed as normal
- Note that finish() must be called before this function will work. If
- you are using the context manager (see 'with' code in the FdtSw class
- comment) then this will happen automatically.
+ Creates a new Fdt object from the work-in-progress device tree. This
+ does not call fdt_finish() on the current object, so it is possible to
+ add more nodes/properties and call as_fdt() again to get an updated
+ tree.
Returns:
Fdt object allowing access to the newly created device tree
"""
- return Fdt(self._fdtrw)
+ fdtsw = bytearray(self._fdt)
+ check_err(fdt_finish(fdtsw))
+ return Fdt(fdtsw)
- def resize(self, size, quiet=()):
+ def check_space(self, val):
+ """Check if we need to add more space to the FDT
+
+ This should be called with the error code from an operation. If this is
+ -NOSPACE then the FDT will be expanded to have more space, and True will
+ be returned, indicating that the operation needs to be tried again.
+
+ Args:
+ val: Return value from the operation that was attempted
+
+ Returns:
+ True if the operation must be retried, else False
+ """
+ if check_err(val, QUIET_NOSPACE) < 0:
+ self.resize(len(self._fdt) + self.INC_SIZE)
+ return True
+ return False
+
+ def resize(self, size):
"""Resize the buffer to accommodate a larger tree
Args:
size: New size of tree
- quiet: Errors to ignore (empty to raise on all errors)
Raises:
- FdtException if no node found or other error occurs
+ FdtException on any error
"""
fdt = bytearray(size)
- fdt[:len(self._fdtrw)] = self._fdtrw
- err = check_err(fdt_resize(self._fdtrw, fdt, size), quiet)
- if err:
- return err
- self._fdtrw = fdt
+ err = check_err(fdt_resize(self._fdt, fdt, size))
+ self._fdt = fdt
- def add_reservemap_entry(self, addr, size, quiet=()):
+ def add_reservemap_entry(self, addr, size):
"""Add a new memory reserve map entry
Once finished adding, you must call finish_reservemap().
Args:
addr: 64-bit start address
size: 64-bit size
- quiet: Errors to ignore (empty to raise on all errors)
Raises:
- FdtException if no node found or other error occurs
+ FdtException on any error
"""
- return check_err(fdt_add_reservemap_entry(self._fdtrw, addr, size),
- quiet)
+ while self.check_space(fdt_add_reservemap_entry(self._fdt, addr,
+ size)):
+ pass
- def finish_reservemap(self, quiet=()):
+ def finish_reservemap(self):
"""Indicate that there are no more reserve map entries to add
- Args:
- quiet: Errors to ignore (empty to raise on all errors)
-
Raises:
- FdtException if no node found or other error occurs
+ FdtException on any error
"""
- return check_err(fdt_finish_reservemap(self._fdtrw), quiet)
+ while self.check_space(fdt_finish_reservemap(self._fdt)):
+ pass
- def begin_node(self, name, quiet=()):
+ def begin_node(self, name):
"""Begin a new node
Use this before adding properties to the node. Then call end_node() to
Args:
name: Name of node to begin
- quiet: Errors to ignore (empty to raise on all errors)
Raises:
- FdtException if no node found or other error occurs
+ FdtException on any error
"""
- return check_err(fdt_begin_node(self._fdtrw, name), quiet)
+ while self.check_space(fdt_begin_node(self._fdt, name)):
+ pass
- def property_string(self, name, string, quiet=()):
+ def property_string(self, name, string):
"""Add a property with a string value
The string will be nul-terminated when written to the device tree
Args:
name: Name of property to add
string: String value of property
- quiet: Errors to ignore (empty to raise on all errors)
Raises:
- FdtException if no node found or other error occurs
+ FdtException on any error
"""
- return check_err(fdt_property_string(self._fdtrw, name, string), quiet)
+ while self.check_space(fdt_property_string(self._fdt, name, string)):
+ pass
- def property_u32(self, name, val, quiet=()):
+ def property_u32(self, name, val):
"""Add a property with a 32-bit value
Write a single-cell value to the device tree
Args:
name: Name of property to add
val: Value of property
- quiet: Errors to ignore (empty to raise on all errors)
Raises:
- FdtException if no node found or other error occurs
+ FdtException on any error
"""
- return check_err(fdt_property_u32(self._fdtrw, name, val), quiet)
+ while self.check_space(fdt_property_u32(self._fdt, name, val)):
+ pass
- def property_u64(self, name, val, quiet=()):
+ def property_u64(self, name, val):
"""Add a property with a 64-bit value
Write a double-cell value to the device tree in big-endian format
Args:
name: Name of property to add
val: Value of property
- quiet: Errors to ignore (empty to raise on all errors)
Raises:
- FdtException if no node found or other error occurs
+ FdtException on any error
"""
- return check_err(fdt_property_u64(self._fdtrw, name, val), quiet)
+ while self.check_space(fdt_property_u64(self._fdt, name, val)):
+ pass
- def property_cell(self, name, val, quiet=()):
+ def property_cell(self, name, val):
"""Add a property with a single-cell value
Write a single-cell value to the device tree
quiet: Errors to ignore (empty to raise on all errors)
Raises:
- FdtException if no node found or other error occurs
+ FdtException on any error
"""
- return check_err(fdt_property_cell(self._fdtrw, name, val), quiet)
+ while self.check_space(fdt_property_cell(self._fdt, name, val)):
+ pass
- def property(self, name, val, quiet=()):
+ def property(self, name, val):
"""Add a property
Write a new property with the given value to the device tree. The value
quiet: Errors to ignore (empty to raise on all errors)
Raises:
- FdtException if no node found or other error occurs
+ FdtException on any error
"""
- return check_err(_fdt_property(self._fdtrw, name, val, len(val)), quiet)
+ while self.check_space(fdt_property_stub(self._fdt, name, val,
+ len(val))):
+ pass
- def end_node(self, quiet=()):
+ def end_node(self):
"""End a node
Use this after adding properties to a node to close it off. You can also
quiet: Errors to ignore (empty to raise on all errors)
Raises:
- FdtException if no node found or other error occurs
- """
- return check_err(fdt_end_node(self._fdtrw), quiet)
-
- def finish(self, quiet=()):
- """Finish writing the device tree
-
- This closes off the device tree ready for use
-
- Args:
- quiet: Errors to ignore (empty to raise on all errors)
-
- Raises:
- FdtException if no node found or other error occurs
+ FdtException on any error
"""
- return check_err(fdt_finish(self._fdtrw), quiet)
+ while self.check_space(fdt_end_node(self._fdt)):
+ pass
- def AddNode(self, name):
+ def add_node(self, name):
"""Create a new context for adding a node
When used in a 'with' clause this starts a new node and finishes it
Args:
name: Name of node to add
"""
- return NodeAdder(self._fdtrw, name)
+ return NodeAdder(self, name)
class NodeAdder():
This allows you to add nodes in a more natural way:
- with fdtsw.AddNode('name'):
+ with fdtsw.add_node('name'):
fdtsw.property_string('test', 'value')
The node is automatically completed with a call to end_node() when the
context exits.
"""
- def __init__(self, fdt, name):
- self._fdt = fdt
+ def __init__(self, fdtsw, name):
+ self._fdt = fdtsw
self._name = name
def __enter__(self):
- check_err(fdt_begin_node(self._fdt, self._name))
+ self._fdt.begin_node(self._name)
def __exit__(self, type, value, traceback):
- check_err(fdt_end_node(self._fdt))
+ self._fdt.end_node()
%}
%rename(fdt_property) fdt_property_func;
-typedef int fdt32_t;
+/*
+ * fdt32_t is a big-endian 32-bit value defined to uint32_t in libfdt_env.h
+ * so use the same type here.
+ */
+typedef uint32_t fdt32_t;
%include "libfdt/fdt.h"
%warnfilter(302) fdt_property;
/* These are macros in the header so have to be redefined here */
-int fdt_magic(const void *fdt);
-int fdt_totalsize(const void *fdt);
-int fdt_off_dt_struct(const void *fdt);
-int fdt_off_dt_strings(const void *fdt);
-int fdt_off_mem_rsvmap(const void *fdt);
-int fdt_version(const void *fdt);
-int fdt_last_comp_version(const void *fdt);
-int fdt_boot_cpuid_phys(const void *fdt);
-int fdt_size_dt_strings(const void *fdt);
-int fdt_size_dt_struct(const void *fdt);
+uint32_t fdt_magic(const void *fdt);
+uint32_t fdt_totalsize(const void *fdt);
+uint32_t fdt_off_dt_struct(const void *fdt);
+uint32_t fdt_off_dt_strings(const void *fdt);
+uint32_t fdt_off_mem_rsvmap(const void *fdt);
+uint32_t fdt_version(const void *fdt);
+uint32_t fdt_last_comp_version(const void *fdt);
+uint32_t fdt_boot_cpuid_phys(const void *fdt);
+uint32_t fdt_size_dt_strings(const void *fdt);
+uint32_t fdt_size_dt_struct(const void *fdt);
+
int fdt_property_string(void *fdt, const char *name, const char *val);
int fdt_property_cell(void *fdt, const char *name, uint32_t val);
* This function has a stub since the name fdt_property is used for both a
* function and a struct, which confuses SWIG.
*/
-int _fdt_property(void *fdt, const char *name, const char *val, int len);
+int fdt_property_stub(void *fdt, const char *name, const char *val, int len);
%include <../libfdt/libfdt.h>
obj-$(CONFIG_ADC) += adc.o
obj-$(CONFIG_SPMI) += spmi.o
obj-$(CONFIG_WDT) += wdt.o
+obj-$(CONFIG_AXI) += axi.o
+obj-$(CONFIG_MISC) += misc.o
endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <axi.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <test/ut.h>
+#include <asm/axi.h>
+
+/* Test that sandbox AXI works correctly */
+static int dm_test_axi_base(struct unit_test_state *uts)
+{
+ struct udevice *bus;
+
+ ut_assertok(uclass_get_device(UCLASS_AXI, 0, &bus));
+
+ return 0;
+}
+
+DM_TEST(dm_test_axi_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that sandbox PCI bus numbering works correctly */
+static int dm_test_axi_busnum(struct unit_test_state *uts)
+{
+ struct udevice *bus;
+
+ ut_assertok(uclass_get_device_by_seq(UCLASS_AXI, 0, &bus));
+
+ return 0;
+}
+
+DM_TEST(dm_test_axi_busnum, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that we can use the store device correctly */
+static int dm_test_axi_store(struct unit_test_state *uts)
+{
+ struct udevice *store;
+ u8 tdata1[] = {0x55, 0x66, 0x77, 0x88};
+ u8 tdata2[] = {0xaa, 0xbb, 0xcc, 0xdd};
+ u32 val;
+ u8 *data;
+
+ /* Check that asking for the device automatically fires up AXI */
+ ut_assertok(uclass_get_device(UCLASS_AXI_EMUL, 0, &store));
+ ut_assert(device_active(store));
+
+ axi_get_store(store, &data);
+
+ /* Test reading */
+ memcpy(data, tdata1, ARRAY_SIZE(tdata1));
+ axi_read(store, 0, &val, AXI_SIZE_32);
+ ut_asserteq(0x55667788, val);
+
+ memcpy(data + 3, tdata2, ARRAY_SIZE(tdata2));
+ axi_read(store, 3, &val, AXI_SIZE_32);
+ ut_asserteq(0xaabbccdd, val);
+
+ /* Reset data store */
+ memset(data, 0, 16);
+
+ /* Test writing */
+ val = 0x55667788;
+ axi_write(store, 0, &val, AXI_SIZE_32);
+ ut_asserteq(0, memcmp(data, tdata1, ARRAY_SIZE(tdata1)));
+
+ val = 0xaabbccdd;
+ axi_write(store, 3, &val, AXI_SIZE_32);
+ ut_asserteq(0, memcmp(data + 3, tdata2, ARRAY_SIZE(tdata1)));
+
+ return 0;
+}
+
+DM_TEST(dm_test_axi_store, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
{
struct udevice *dev;
+ /* configure the default state (auto-probe) */
+ led_default_state();
+
/* Check that we handle the default-state property correctly. */
ut_assertok(led_get_by_label("sandbox:default_on", &dev));
ut_asserteq(LEDST_ON, led_get_state(dev));
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <misc.h>
+#include <test/ut.h>
+
+static int dm_test_misc(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ u8 buf[16];
+ int id;
+ ulong last_ioctl;
+ bool enabled;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "misc-test", &dev));
+
+ /* Read / write tests */
+ ut_assertok(misc_write(dev, 0, "TEST", 4));
+ ut_assertok(misc_write(dev, 4, "WRITE", 5));
+ ut_assertok(misc_read(dev, 0, buf, 9));
+
+ ut_assertok(memcmp(buf, "TESTWRITE", 9));
+
+ /* Call tests */
+
+ id = 0;
+ ut_assertok(misc_call(dev, 0, &id, 4, buf, 16));
+ ut_assertok(memcmp(buf, "Zero", 4));
+
+ id = 2;
+ ut_assertok(misc_call(dev, 0, &id, 4, buf, 16));
+ ut_assertok(memcmp(buf, "Two", 3));
+
+ ut_assertok(misc_call(dev, 1, &id, 4, buf, 16));
+ ut_assertok(memcmp(buf, "Forty-two", 9));
+
+ id = 1;
+ ut_assertok(misc_call(dev, 1, &id, 4, buf, 16));
+ ut_assertok(memcmp(buf, "Forty-one", 9));
+
+ /* IOCTL tests */
+
+ ut_assertok(misc_ioctl(dev, 6, NULL));
+ /* Read back last issued ioctl */
+ ut_assertok(misc_call(dev, 2, NULL, 0, &last_ioctl,
+ sizeof(last_ioctl)));
+ ut_asserteq(6, last_ioctl)
+
+ ut_assertok(misc_ioctl(dev, 23, NULL));
+ /* Read back last issued ioctl */
+ ut_assertok(misc_call(dev, 2, NULL, 0, &last_ioctl,
+ sizeof(last_ioctl)));
+ ut_asserteq(23, last_ioctl)
+
+ /* Enable / disable tests */
+
+ /* Read back enable/disable status */
+ ut_assertok(misc_call(dev, 3, NULL, 0, &enabled,
+ sizeof(enabled)));
+ ut_asserteq(true, enabled);
+
+ ut_assertok(misc_set_enabled(dev, false));
+ /* Read back enable/disable status */
+ ut_assertok(misc_call(dev, 3, NULL, 0, &enabled,
+ sizeof(enabled)));
+ ut_asserteq(false, enabled);
+
+ ut_assertok(misc_set_enabled(dev, true));
+ /* Read back enable/disable status */
+ ut_assertok(misc_call(dev, 3, NULL, 0, &enabled,
+ sizeof(enabled)));
+ ut_asserteq(true, enabled);
+
+ return 0;
+}
+
+DM_TEST(dm_test_misc, DM_TESTF_SCAN_FDT);
#include <common.h>
#include <dm.h>
#include <asm/io.h>
+#include <asm/test.h>
#include <dm/test.h>
#include <test/ut.h>
}
DM_TEST(dm_test_pci_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
-/* Test that sandbox PCI bus numbering works correctly */
-static int dm_test_pci_busnum(struct unit_test_state *uts)
+/* Test that sandbox PCI bus numbering and device works correctly */
+static int dm_test_pci_busdev(struct unit_test_state *uts)
{
struct udevice *bus;
+ struct udevice *swap;
+ u16 vendor, device;
+ /* Test bus#0 and its devices */
ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 0, &bus));
+ ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x00, 0), &swap));
+ vendor = 0;
+ ut_assertok(dm_pci_read_config16(swap, PCI_VENDOR_ID, &vendor));
+ ut_asserteq(SANDBOX_PCI_VENDOR_ID, vendor);
+ ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap));
+ device = 0;
+ ut_assertok(dm_pci_read_config16(swap, PCI_DEVICE_ID, &device));
+ ut_asserteq(SANDBOX_PCI_DEVICE_ID, device);
+
+ /* Test bus#1 and its devices */
+ ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 1, &bus));
+
+ ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &swap));
+ vendor = 0;
+ ut_assertok(dm_pci_read_config16(swap, PCI_VENDOR_ID, &vendor));
+ ut_asserteq(SANDBOX_PCI_VENDOR_ID, vendor);
+ ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x0c, 0), &swap));
+ device = 0;
+ ut_assertok(dm_pci_read_config16(swap, PCI_DEVICE_ID, &device));
+ ut_asserteq(SANDBOX_PCI_DEVICE_ID, device);
+
return 0;
}
-DM_TEST(dm_test_pci_busnum, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_busdev, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
/* Test that we can use the swapcase device correctly */
static int dm_test_pci_swapcase(struct unit_test_state *uts)
{
- struct udevice *emul, *swap;
+ struct udevice *swap;
ulong io_addr, mem_addr;
char *ptr;
- /* Check that asking for the device automatically fires up PCI */
- ut_assertok(uclass_get_device(UCLASS_PCI_EMUL, 0, &emul));
+ /* Check that asking for the device 0 automatically fires up PCI */
+ ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x00, 0), &swap));
+
+ /* First test I/O */
+ io_addr = dm_pci_read_bar32(swap, 0);
+ outb(2, io_addr);
+ ut_asserteq(2, inb(io_addr));
+
+ /*
+ * Now test memory mapping - note we must unmap and remap to cause
+ * the swapcase emulation to see our data and response.
+ */
+ mem_addr = dm_pci_read_bar32(swap, 1);
+ ptr = map_sysmem(mem_addr, 20);
+ strcpy(ptr, "This is a TesT");
+ unmap_sysmem(ptr);
+
+ ptr = map_sysmem(mem_addr, 20);
+ ut_asserteq_str("tHIS IS A tESt", ptr);
+ unmap_sysmem(ptr);
+
+ /* Check that asking for the device 1 automatically fires up PCI */
ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap));
- ut_assert(device_active(swap));
/* First test I/O */
io_addr = dm_pci_read_bar32(swap, 0);
return 0;
}
DM_TEST(dm_test_pci_swapcase, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that we can dynamically bind the device driver correctly */
+static int dm_test_pci_drvdata(struct unit_test_state *uts)
+{
+ struct udevice *bus, *swap;
+
+ /* Check that asking for the device automatically fires up PCI */
+ ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 1, &bus));
+
+ ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &swap));
+ ut_asserteq(SWAP_CASE_DRV_DATA, swap->driver_data);
+ ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x0c, 0), &swap));
+ ut_asserteq(SWAP_CASE_DRV_DATA, swap->driver_data);
+
+ return 0;
+}
+DM_TEST(dm_test_pci_drvdata, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that devices on PCI bus#2 can be accessed correctly */
+static int dm_test_pci_mixed(struct unit_test_state *uts)
+{
+ /* PCI bus#2 has both statically and dynamic declared devices */
+ struct udevice *bus, *swap;
+ u16 vendor, device;
+ ulong io_addr, mem_addr;
+ char *ptr;
+
+ ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 2, &bus));
+
+ /* Test the dynamic device */
+ ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(2, 0x08, 0), &swap));
+ vendor = 0;
+ ut_assertok(dm_pci_read_config16(swap, PCI_VENDOR_ID, &vendor));
+ ut_asserteq(SANDBOX_PCI_VENDOR_ID, vendor);
+
+ /* First test I/O */
+ io_addr = dm_pci_read_bar32(swap, 0);
+ outb(2, io_addr);
+ ut_asserteq(2, inb(io_addr));
+
+ /*
+ * Now test memory mapping - note we must unmap and remap to cause
+ * the swapcase emulation to see our data and response.
+ */
+ mem_addr = dm_pci_read_bar32(swap, 1);
+ ptr = map_sysmem(mem_addr, 30);
+ strcpy(ptr, "This is a TesT oN dYNAMIc");
+ unmap_sysmem(ptr);
+
+ ptr = map_sysmem(mem_addr, 30);
+ ut_asserteq_str("tHIS IS A tESt On DynamiC", ptr);
+ unmap_sysmem(ptr);
+
+ /* Test the static device */
+ ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(2, 0x1f, 0), &swap));
+ device = 0;
+ ut_assertok(dm_pci_read_config16(swap, PCI_DEVICE_ID, &device));
+ ut_asserteq(SANDBOX_PCI_DEVICE_ID, device);
+
+ /* First test I/O */
+ io_addr = dm_pci_read_bar32(swap, 0);
+ outb(2, io_addr);
+ ut_asserteq(2, inb(io_addr));
+
+ /*
+ * Now test memory mapping - note we must unmap and remap to cause
+ * the swapcase emulation to see our data and response.
+ */
+ mem_addr = dm_pci_read_bar32(swap, 1);
+ ptr = map_sysmem(mem_addr, 30);
+ strcpy(ptr, "This is a TesT oN sTATIc");
+ unmap_sysmem(ptr);
+
+ ptr = map_sysmem(mem_addr, 30);
+ ut_asserteq_str("tHIS IS A tESt On StatiC", ptr);
+ unmap_sysmem(ptr);
+
+ return 0;
+}
+DM_TEST(dm_test_pci_mixed, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test looking up PCI capability and extended capability */
+static int dm_test_pci_cap(struct unit_test_state *uts)
+{
+ struct udevice *bus, *swap;
+ int cap;
+
+ ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 0, &bus));
+ ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap));
+
+ /* look up PCI_CAP_ID_EXP */
+ cap = dm_pci_find_capability(swap, PCI_CAP_ID_EXP);
+ ut_asserteq(PCI_CAP_ID_EXP_OFFSET, cap);
+
+ /* look up PCI_CAP_ID_PCIX */
+ cap = dm_pci_find_capability(swap, PCI_CAP_ID_PCIX);
+ ut_asserteq(0, cap);
+
+ ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 1, &bus));
+ ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &swap));
+
+ /* look up PCI_EXT_CAP_ID_DSN */
+ cap = dm_pci_find_ext_capability(swap, PCI_EXT_CAP_ID_DSN);
+ ut_asserteq(PCI_EXT_CAP_ID_DSN_OFFSET, cap);
+
+ /* look up PCI_EXT_CAP_ID_SRIOV */
+ cap = dm_pci_find_ext_capability(swap, PCI_EXT_CAP_ID_SRIOV);
+ ut_asserteq(0, cap);
+
+ return 0;
+}
+DM_TEST(dm_test_pci_cap, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
fdt_obj = self._fdt._fdt_obj
if fdt_obj.setprop_u32(self.Offset(), prop_name, 0,
(libfdt.NOSPACE,)) == -libfdt.NOSPACE:
- fdt_obj.open_into(fdt_obj.totalsize() + 1024)
+ fdt_obj.resize(fdt_obj.totalsize() + 1024)
fdt_obj.setprop_u32(self.Offset(), prop_name, 0)
self.props[prop_name] = Prop(self, -1, prop_name, '\0' * 4)
self._fdt.Invalidate()
Return fdt.Prop object for this property
"""
- p = self.fdt.get_property(self.node.Offset(), prop_name)
+ p = self.fdt.getprop(self.node.Offset(), prop_name)
return fdt.Prop(self.node, -1, prop_name, p)
def testMakeProp(self):
}
n = read(fd, buf, len);
- if (n < 0)
+ if (n <= 0)
goto out;
buf = (char *)buf + n;
char _buf[128], *buf = _buf;
nin = read(in, buf, sizeof(buf));
- if (nin < 0)
+ if (nin <= 0)
return -1;
if (quit) {
perror("debugmsg");
goto out;
}
- } else {
+ } else if (bootmsg) {
rc = kwboot_bootmsg(tty, bootmsg);
if (rc) {
perror("bootmsg");
projects / platform / kernel / u-boot.git / commitdiff