Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into next
authorTom Rini <trini@konsulko.com>
Wed, 6 Jan 2021 03:34:43 +0000 (22:34 -0500)
committerTom Rini <trini@konsulko.com>
Wed, 6 Jan 2021 03:34:43 +0000 (22:34 -0500)
Driver model: make some udevice fields private
Driver model: Rename U_BOOT_DEVICE et al.
dtoc: Tidy up and add more tests
ns16550 code clean-up
x86 and sandbox minor fixes for of-platdata
dtoc prepration for adding build-time instantiation

13 files changed:
1  2 
board/freescale/lx2160a/lx2160a.c
board/st/stm32mp1/stm32mp1.c
drivers/core/device-remove.c
drivers/misc/cros_ec_sandbox.c
drivers/mmc/fsl_esdhc_imx.c
drivers/mtd/nand/spi/core.c
drivers/spi/designware_spi.c
drivers/spi/spi-uclass.c
drivers/usb/dwc3/dwc3-generic.c
drivers/usb/dwc3/dwc3-meson-g12a.c
drivers/usb/host/dwc3-sti-glue.c
include/asm-generic/global_data.h
tools/patman/tools.py

Simple merge
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@@@ -230,11 -155,9 +230,11 @@@ static int request_gpio_cs(struct udevi
  
  static int dw_spi_of_to_plat(struct udevice *bus)
  {
-       struct dw_spi_plat *plat = bus->plat;
+       struct dw_spi_plat *plat = dev_get_plat(bus);
  
        plat->regs = dev_read_addr_ptr(bus);
 +      if (!plat->regs)
 +              return -EINVAL;
  
        /* Use 500KHz as a suitable default */
        plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
@@@ -562,110 -476,9 +562,110 @@@ static int dw_spi_xfer(struct udevice *
        return ret;
  }
  
 +/*
 + * This function is necessary for reading SPI flash with the native CS
 + * c.f. https://lkml.org/lkml/2015/12/23/132
 + */
 +static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
 +{
 +      bool read = op->data.dir == SPI_MEM_DATA_IN;
 +      int pos, i, ret = 0;
 +      struct udevice *bus = slave->dev->parent;
 +      struct dw_spi_priv *priv = dev_get_priv(bus);
 +      u8 op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
 +      u8 op_buf[op_len];
 +      u32 cr0;
 +
 +      if (read)
 +              priv->tmode = CTRLR0_TMOD_EPROMREAD;
 +      else
 +              priv->tmode = CTRLR0_TMOD_TO;
 +
 +      cr0 = priv->update_cr0(priv);
 +      dev_dbg(bus, "cr0=%08x buf=%p len=%u [bytes]\n", cr0, op->data.buf.in,
 +              op->data.nbytes);
 +
 +      dw_write(priv, DW_SPI_SSIENR, 0);
 +      dw_write(priv, DW_SPI_CTRLR0, cr0);
 +      if (read)
 +              dw_write(priv, DW_SPI_CTRLR1, op->data.nbytes - 1);
 +      dw_write(priv, DW_SPI_SSIENR, 1);
 +
 +      /* From spi_mem_exec_op */
 +      pos = 0;
 +      op_buf[pos++] = op->cmd.opcode;
 +      if (op->addr.nbytes) {
 +              for (i = 0; i < op->addr.nbytes; i++)
 +                      op_buf[pos + i] = op->addr.val >>
 +                              (8 * (op->addr.nbytes - i - 1));
 +
 +              pos += op->addr.nbytes;
 +      }
 +      if (op->dummy.nbytes)
 +              memset(op_buf + pos, 0xff, op->dummy.nbytes);
 +
 +      external_cs_manage(slave->dev, false);
 +
 +      priv->tx = &op_buf;
 +      priv->tx_end = priv->tx + op_len;
 +      priv->rx = NULL;
 +      priv->rx_end = NULL;
 +      while (priv->tx != priv->tx_end)
 +              dw_writer(priv);
 +
 +      /*
 +       * XXX: The following are tight loops! Enabling debug messages may cause
 +       * them to fail because we are not reading/writing the fifo fast enough.
 +       */
 +      if (read) {
 +              priv->rx = op->data.buf.in;
 +              priv->rx_end = priv->rx + op->data.nbytes;
 +
 +              dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev));
 +              while (priv->rx != priv->rx_end)
 +                      dw_reader(priv);
 +      } else {
 +              u32 val;
 +
 +              priv->tx = op->data.buf.out;
 +              priv->tx_end = priv->tx + op->data.nbytes;
 +
 +              /* Fill up the write fifo before starting the transfer */
 +              dw_writer(priv);
 +              dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev));
 +              while (priv->tx != priv->tx_end)
 +                      dw_writer(priv);
 +
 +              if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
 +                                     (val & SR_TF_EMPT) && !(val & SR_BUSY),
 +                                     RX_TIMEOUT * 1000)) {
 +                      ret = -ETIMEDOUT;
 +              }
 +      }
 +
 +      dw_write(priv, DW_SPI_SER, 0);
 +      external_cs_manage(slave->dev, true);
 +
 +      dev_dbg(bus, "%u bytes xfered\n", op->data.nbytes);
 +      return ret;
 +}
 +
 +/* The size of ctrl1 limits data transfers to 64K */
 +static int dw_spi_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op)
 +{
 +      op->data.nbytes = min(op->data.nbytes, (unsigned int)SZ_64K);
 +
 +      return 0;
 +}
 +
 +static const struct spi_controller_mem_ops dw_spi_mem_ops = {
 +      .exec_op = dw_spi_exec_op,
 +      .adjust_op_size = dw_spi_adjust_op_size,
 +};
 +
  static int dw_spi_set_speed(struct udevice *bus, uint speed)
  {
-       struct dw_spi_plat *plat = bus->plat;
+       struct dw_spi_plat *plat = dev_get_plat(bus);
        struct dw_spi_priv *priv = dev_get_priv(bus);
        u16 clk_div;
  
Simple merge
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@@@ -194,9 -194,15 +194,15 @@@ struct global_data 
        /**
         * @uclass_root: head of core tree
         */
-       struct list_head uclass_root;
+       struct list_head uclass_root_s;
+       /**
+        * @uclass_root: pointer to head of core tree, if uclasses are in
+        * read-only memory and cannot be adjusted to use @uclass_root as a
+        * list head.
+        */
+       struct list_head *uclass_root;
  # if CONFIG_IS_ENABLED(OF_PLATDATA)
 -        /** Dynamic info about the driver */
 +      /** @dm_driver_rt: Dynamic info about the driver */
        struct driver_rt *dm_driver_rt;
  # endif
  #endif
Simple merge