powerpc: Enable device tree support for T4240RDB

Add device tree for T4240RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index 388a4b2..9002393 100644 (file)
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -2,6 +2,7 @@
 
 dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
 dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb
+dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb
 dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
 dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
 

diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi
new file mode 100644 (file)
index 0000000..4d8fc71
--- /dev/null
+++ b/arch/powerpc/dts/t4240.dtsi
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T4240 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e6500_power_isa.dtsi"
+
+/ {
+       #address-cells = <2>;
+       #size-cells = <2>;
+       interrupt-parent = <&mpic>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu0: PowerPC,e6500@0 {
+                       device_type = "cpu";
+                       reg = <0 1>;
+                       fsl,portid-mapping = <0x80000000>;
+               };
+               cpu1: PowerPC,e6500@2 {
+                       device_type = "cpu";
+                       reg = <2 3>;
+                       fsl,portid-mapping = <0x80000000>;
+               };
+               cpu2: PowerPC,e6500@4 {
+                       device_type = "cpu";
+                       reg = <4 5>;
+                       fsl,portid-mapping = <0x80000000>;
+               };
+               cpu3: PowerPC,e6500@6 {
+                       device_type = "cpu";
+                       reg = <6 7>;
+                       fsl,portid-mapping = <0x80000000>;
+               };
+               cpu4: PowerPC,e6500@8 {
+                       device_type = "cpu";
+                       reg = <8 9>;
+                       fsl,portid-mapping = <0x80000000>;
+               };
+               cpu5: PowerPC,e6500@10 {
+                       device_type = "cpu";
+                       reg = <10 11>;
+                       fsl,portid-mapping = <0x80000000>;
+               };
+               cpu6: PowerPC,e6500@12 {
+                       device_type = "cpu";
+                       reg = <12 13>;
+                       fsl,portid-mapping = <0x80000000>;
+               };
+               cpu7: PowerPC,e6500@14 {
+                       device_type = "cpu";
+                       reg = <14 15>;
+                       fsl,portid-mapping = <0x80000000>;
+               };
+               cpu8: PowerPC,e6500@16 {
+                       device_type = "cpu";
+                       reg = <16 17>;
+                       fsl,portid-mapping = <0x80000000>;
+               };
+               cpu9: PowerPC,e6500@18 {
+                       device_type = "cpu";
+                       reg = <18 19>;
+                       fsl,portid-mapping = <0x80000000>;
+               };
+               cpu10: PowerPC,e6500@20 {
+                       device_type = "cpu";
+                       reg = <20 21>;
+                       fsl,portid-mapping = <0x80000000>;
+               };
+               cpu11: PowerPC,e6500@22 {
+                       device_type = "cpu";
+                       reg = <22 23>;
+                       fsl,portid-mapping = <0x80000000>;
+               };
+       };
+
+       soc: soc@ffe000000 {
+               ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+               reg = <0xf 0xfe000000 0 0x00001000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               device_type = "soc";
+               compatible = "simple-bus";
+
+               mpic: pic@40000 {
+                       interrupt-controller;
+                       #address-cells = <0>;
+                       #interrupt-cells = <4>;
+                       reg = <0x40000 0x40000>;
+                       compatible = "fsl,mpic";
+                       device_type = "open-pic";
+                       clock-frequency = <0x0>;
+               };
+       };
+};

diff --git a/arch/powerpc/dts/t4240rdb.dts b/arch/powerpc/dts/t4240rdb.dts
new file mode 100644 (file)
index 0000000..f67d7ce
--- /dev/null
+++ b/arch/powerpc/dts/t4240rdb.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T4240RDB Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "t4240.dtsi"
+
+/ {
+       model = "fsl,T4240RDB";
+       compatible = "fsl,T4240RDB";
+       #address-cells = <2>;
+       #size-cells = <2>;
+       interrupt-parent = <&mpic>;
+};

diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 9405755..b82de5c 100644 (file)
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -35,6 +35,8 @@ CONFIG_CMD_PING=y
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -57,4 +59,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index 446c141..d8ff848 100644 (file)
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -21,6 +22,8 @@ CONFIG_CMD_PING=y
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -43,4 +46,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y