#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#if !defined(CONFIG_CPU_SH2)
+#include <asm/processor.h>
+
+/* Timer */
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0x8) /* TCNT0 */
+#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
+#endif
+
#endif
#define PYDR 0xA405016A
#define PZDR 0xA405016C
-/* Ether */
-#define EDMR 0xA4600000
-
/* UBC */
/* H-UDI */
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
-#include <sh_tmu.h>
-#define TCR_TPSC 0x07
+#if defined(CONFIG_CPU_SH3)
+#define TSTR 0x2
+#define TCR0 0xc
+#endif /* CONFIG_CPU_SH3 */
-static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE;
+#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE)
+#define TSTR 0x4
+#define TCR0 0x10
+#endif /* CONFIG_CPU_SH4 */
-unsigned long get_tbclk(void)
-{
- u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
- return get_tmu0_clk_rate() >> ((tmu_bit + 1) * 2);
-}
-
-unsigned long timer_read_counter(void)
-{
- return ~readl(&tmu->tcnt0);
-}
-
-static void tmu_timer_start(unsigned int timer)
-{
- if (timer > 2)
- return;
- writeb(readb(&tmu->tstr) | (1 << timer), &tmu->tstr);
-}
-
-static void tmu_timer_stop(unsigned int timer)
-{
- if (timer > 2)
- return;
- writeb(readb(&tmu->tstr) & ~(1 << timer), &tmu->tstr);
-}
+#define TCR_TPSC 0x07
+#define TSTR_STR0 BIT(0)
int timer_init(void)
{
- u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
- writew((readw(&tmu->tcr0) & ~TCR_TPSC) | tmu_bit, &tmu->tcr0);
-
- tmu_timer_stop(0);
- tmu_timer_start(0);
+ writew(readw(TMU_BASE + TCR0) & ~TCR_TPSC, TMU_BASE + TCR0);
+ writeb(readb(TMU_BASE + TSTR) & ~TSTR_STR0, TMU_BASE + TSTR);
+ writeb(readb(TMU_BASE + TSTR) | TSTR_STR0, TMU_BASE + TSTR);
return 0;
}
#define CPLD_DONE_ADR ((vu_char *)0xA4050132)
#define CPLD_DONE_DAT 0x20
-#define HIZCRB ((vu_short *)0xA405015A)
-
/* data */
#define CPLD_NOMAL_START 0xA0A80000
#define CPLD_SAFE_START 0xA0AC0000
if (*CPLD_DONE_ADR & CPLD_DONE_DAT) /* Already DONE */
return;
- *HIZCRB = 0x0000;
+ *((vu_short *)HIZCRB) = 0x0000;
*CPLD_PFC_ADR = 0x7c00; /* FPGA PROG = OUTPUT */
/* write CPLD data from NOR flash to device */
*/
ubi = open_ubi(name, UBI_READONLY);
if (IS_ERR(ubi)) {
- pr_err("UBIFS error (pid: %d): cannot open \"%s\", error %d",
+ pr_err("UBIFS error (pid: %d): cannot open \"%s\", error %d\n",
current->pid, name, (int)PTR_ERR(ubi));
return ERR_CAST(ubi);
}
* UBIFS_BLOCK_SIZE. It is assumed that both are powers of 2.
*/
if (PAGE_CACHE_SIZE < UBIFS_BLOCK_SIZE) {
- pr_err("UBIFS error (pid %d): VFS page cache size is %u bytes, but UBIFS requires at least 4096 bytes",
+ pr_err("UBIFS error (pid %d): VFS page cache size is %u bytes, but UBIFS requires at least 4096 bytes\n",
current->pid, (unsigned int)PAGE_CACHE_SIZE);
return -EINVAL;
}
err = register_filesystem(&ubifs_fs_type);
if (err) {
- pr_err("UBIFS error (pid %d): cannot register file system, error %d",
+ pr_err("UBIFS error (pid %d): cannot register file system, error %d\n",
current->pid, err);
goto out_dbg;
}
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
#endif /* __MIGO_R_H */
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
#endif /* __AP325RXA_H */
#else
#define CONFIG_SYS_CLK_FREQ 44444444
#endif
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#endif /* __AP_SH4A_4A_H */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_TMU_TIMER
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
+#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
#define CONFIG_SYS_DCACHE_OFF
/* STACK */
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 50000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#endif /* __ARMADILLO_800EVA_H */
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
-#define CONFIG_SYS_TMU_CLK_DIV 4
/* ENV setting */
#if !defined(CONFIG_MTD_NOR_FLASH)
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 41666666
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#endif /* __ECOVEC_H */
/* Clock */
#define CONFIG_SYS_CLK_FREQ 66666666
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
/* Ether */
#define CONFIG_SH_ETHER_USE_PORT (1)
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
/* Clocks */
#define CONFIG_SYS_CLK_FREQ 24000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
/* UART */
#define CONFIG_CONS_SCIF0 1
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
/* PCMCIA */
#define CONFIG_IDE_PCMCIA 1
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
#endif /* __MS7722SE_H */
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#endif /* __MS7750SE_H */
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
#else
#define CONFIG_SYS_CLK_FREQ 44444444
#endif
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#endif /* __R0P7734_H */
* SuperH Clock setting
*/
#define CONFIG_SYS_CLK_FREQ 60000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
/*
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
/* PCI Controller */
#if defined(CONFIG_CMD_PCI)
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_TMU_TIMER
#ifndef CONFIG_PINCTRL_PFC
#define CONFIG_SH_GPIO_PFC
#endif
#undef CONFIG_SPI_FLASH_MTD
#endif
+/* Timer */
+#define CONFIG_TMU_TIMER
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
+#define CONFIG_SYS_TIMER_RATE (32500000 / 4) /* CP/4 */
+
#endif /* __RCAR_GEN2_COMMON_H */
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 36000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 66125000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 48000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#endif /* __SH7752EVB_H */
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 48000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#endif /* __SH7753EVB_H */
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 48000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#endif /* __SH7757LCR_H */
/* Clock */
#define CONFIG_SYS_CLK_FREQ 66666666
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
/* Ether */
#define CONFIG_SH_ETHER_USE_PORT (1)
/* Board Clock */
/* The SCIF used external clock. system clock only used timer. */
#define CONFIG_SYS_CLK_FREQ 50000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
#endif /* __SH7785LCR_H */
#else
#define CONFIG_SYS_CLK_FREQ 33333333
#endif /* CONFIG_T_SH7706LSR */
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4
/* Network device */
#define CONFIG_DRIVER_NE2000
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
+++ /dev/null
-/*
- * Copyright (C) 2012 Renesas Solutions Corp.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SH_TMU_H
-#define __SH_TMU_H
-
-#include <asm/types.h>
-
-#if defined(CONFIG_CPU_SH3)
-struct tmu_regs {
- u8 tocr;
- u8 reserved0;
- u8 tstr;
- u8 reserved1;
- u32 tcor0;
- u32 tcnt0;
- u16 tcr0;
- u16 reserved2;
- u32 tcor1;
- u32 tcnt1;
- u16 tcr1;
- u16 reserved3;
- u32 tcor2;
- u32 tcnt2;
- u16 tcr2;
- u16 reserved4;
- u32 tcpr2;
-};
-#endif /* CONFIG_CPU_SH3 */
-
-#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE)
-struct tmu_regs {
- u32 reserved;
- u8 tstr;
- u8 reserved2[3];
- u32 tcor0;
- u32 tcnt0;
- u16 tcr0;
- u16 reserved3;
- u32 tcor1;
- u32 tcnt1;
- u16 tcr1;
- u16 reserved4;
- u32 tcor2;
- u32 tcnt2;
- u16 tcr2;
- u16 reserved5;
-};
-#endif /* CONFIG_CPU_SH4 */
-
-static inline unsigned long get_tmu0_clk_rate(void)
-{
- return CONFIG_SH_TMU_CLK_FREQ;
-}
-
-#endif /* __SH_TMU_H */
CONFIG_SYS_TMRINTR_PRI
CONFIG_SYS_TMRPND_REG
CONFIG_SYS_TMR_BASE
-CONFIG_SYS_TMU_CLK_DIV
CONFIG_SYS_TSEC1
CONFIG_SYS_TSEC1_OFFSET
CONFIG_SYS_TSEC2