#########################################################################
LIST_4xx=" \
- acadia ADCIOP alpr AP1000 \
- AR405 ASH405 bamboo bubinga \
- CANBT CMS700 CPCI2DP CPCI405 \
- CPCI4052 CPCI405AB CPCI405DT CPCI440 \
- CPCIISER4 CRAYL1 csb272 csb472 \
- DASA_SIM DP405 DU405 ebony \
- ERIC EXBITGEN G2000 HH405 \
- HUB405 JSE KAREF katmai \
- luan METROBOX MIP405 MIP405T \
- ML2 ml300 ocotea OCRTC \
- ORSG p3p440 PCI405 pcs440ep \
- PIP405 PLU405 PMC405 PPChameleonEVB \
- sbc405 sc3 sequoia sequoia_nand \
- taishan VOH405 VOM405 W7OLMC \
- W7OLMG walnut WUH405 XPEDITE1K \
- yellowstone yosemite yucca \
+ acadia acadia_nand ADCIOP alpr \
+ AP1000 AR405 ASH405 bamboo \
+ bamboo_nand bubinga CANBT CMS700 \
+ CPCI2DP CPCI405 CPCI4052 CPCI405AB \
+ CPCI405DT CPCI440 CPCIISER4 CRAYL1 \
+ csb272 csb472 DASA_SIM DP405 \
+ DU405 ebony ERIC EXBITGEN \
+ G2000 HH405 HUB405 JSE \
+ KAREF katmai luan lwmon5 \
+ METROBOX MIP405 MIP405T ML2 \
+ ml300 ocotea OCRTC ORSG \
+ p3p440 PCI405 pcs440ep PIP405 \
+ PLU405 PMC405 PPChameleonEVB sbc405 \
+ sc3 sequoia sequoia_nand taishan \
+ VOH405 VOM405 W7OLMC W7OLMG \
+ walnut WUH405 XPEDITE1K yellowstone \
+ yosemite yucca \
"
#########################################################################
"
#########################################################################
+ ## MPC86xx Systems
+ #########################################################################
+
+ LIST_86xx=" \
+ MPC8641HPCN \
+ "
+
+ #########################################################################
## 74xx/7xx Systems
#########################################################################
${LIST_8220} ${LIST_824x} ${LIST_8260} \
${LIST_83xx} \
${LIST_85xx} \
+ ${LIST_86xx} \
${LIST_4xx} \
${LIST_74xx} ${LIST_7xx}"
LIST_ARM7=" \
armadillo B2 ep7312 evb4510 \
impa7 integratorap ap7 ap720t \
- lpc2292sodimm modnet50 \
+ lpc2292sodimm modnet50 SMN42 \
"
#########################################################################
microblaze| \
mips|mips_el| \
nios|nios2| \
- ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \
+ ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \
x86|I486)
for target in `eval echo '$LIST_'${arg}`
do
u_int i;
# ifdef CONFIG_AUTOBOOT_PROMPT
- printf (CONFIG_AUTOBOOT_PROMPT, bootdelay);
+ printf(CONFIG_AUTOBOOT_PROMPT, bootdelay);
# endif
# ifdef CONFIG_AUTOBOOT_DELAY_STR
}
# if DEBUG_BOOTKEYS
if (!abort)
- puts ("key timeout\n");
+ puts("key timeout\n");
# endif
#ifdef CONFIG_SILENT_CONSOLE
# endif
break;
}
- udelay (10000);
+ udelay(10000);
}
- printf ("\b\b\b%2d ", bootdelay);
+ printf("\b\b\b%2d ", bootdelay);
}
- putc ('\n');
+ putc('\n');
#ifdef CONFIG_SILENT_CONSOLE
if (abort)
n = 0;
continue;
- case 0x17: /* ^W - erase word */
+ case 0x17: /* ^W - erase word */
p=delete_char(console_buffer, p, &col, &n, plen);
while ((n > 0) && (*p != ' ')) {
p=delete_char(console_buffer, p, &col, &n, plen);
if (outputcnt)
*output = 0;
+ else
+ *(output - 1) = 0;
#ifdef DEBUG_PARSER
printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n",
/* Did the user stop this? */
if (had_ctrlc ())
- return 0; /* if stopped then not repeatable */
+ return -1; /* if stopped then not repeatable */
}
return rc ? rc : repeatable;
LIB = $(obj)libdrivers.a
- COBJS = 3c589.o 5701rls.o ali512x.o atmel_usart.o \
+ COBJS = 3c589.o 5701rls.o ali512x.o ata_piix.o atmel_usart.o \
bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
- e1000.o eepro100.o \
+ e1000.o eepro100.o enc28j60.o \
i8042.o inca-ip_sw.o keyboard.o \
lan91c96.o macb.o \
natsemi.o ne2000.o netarm_eth.o netconsole.o \
#define CONFIG_MII 1 /* MII PHY management */
- #define CONFIG_MPC86XX_TSEC1 1
- #define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1"
- #define CONFIG_MPC86XX_TSEC2 1
- #define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2"
- #define CONFIG_MPC86XX_TSEC3 1
- #define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3"
- #define CONFIG_MPC86XX_TSEC4 1
- #define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4"
+ #define CONFIG_TSEC1 1
+ #define CONFIG_TSEC1_NAME "eTSEC1"
+ #define CONFIG_TSEC2 1
+ #define CONFIG_TSEC2_NAME "eTSEC2"
+ #define CONFIG_TSEC3 1
+ #define CONFIG_TSEC3_NAME "eTSEC3"
+ #define CONFIG_TSEC4 1
+ #define CONFIG_TSEC4_NAME "eTSEC4"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define CONFIG_HOSTNAME unknown
#define CONFIG_ROOTPATH /opt/nfsroot
#define CONFIG_BOOTFILE uImage
+#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=your.ramdisk.u-boot\0" \
- "dtbaddr=400000\0" \
+ "dtbaddr=c00000\0" \
"dtbfile=mpc8641_hpcn.dtb\0" \
"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
* This address, however, is used to configure a 256M local bus
* window that includes the Config latch below.
*/
-#define CFG_LBC_OPTION_BASE 0xf0000000 /* Localbus Extension */
+#define CFG_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
#define CFG_LBC_OPTION_SIZE 256 /* 256MB */
/* There are various flash options used, we configure for the largest,
* which is 64Mbytes. The CFI works fine and will discover the proper
* sizes.
*/
-#define CFG_FLASH_BASE 0xFC000000 /* start of FLASH 64M */
-#define CFG_BR0_PRELIM 0xFC001801 /* port size 32bit */
-#define CFG_OR0_PRELIM 0xFC000FF7 /* 64 MB Flash */
+#ifdef CONFIG_STXSSA_4M
+#define CFG_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
+#else
+#define CFG_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
+#endif
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x1801) /* port size 32bit */
+#define CFG_OR0_PRELIM (CFG_FLASH_BASE | 0x0FF7)
#define CFG_FLASH_CFI 1
#define CFG_FLASH_CFI_DRIVER 1
/* The configuration latch is Chip Select 1.
* It's an 8-bit latch in the lower 8 bits of the word.
*/
-#define CFG_LBC_CFGLATCH_BASE 0xfb000000 /* Base of config latch */
-#define CFG_BR1_PRELIM 0xfb001801 /* 32-bit port */
-#define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
+#define CFG_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
+#define CFG_BR1_PRELIM 0xFB001801 /* 32-bit port */
+#define CFG_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CONFIG_MII 1 /* MII PHY management */
- #define CONFIG_MPC85XX_TSEC1 1
- #define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
- #define CONFIG_MPC85XX_TSEC2 1
- #define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
+ #define CONFIG_TSEC1 1
+ #define CONFIG_TSEC1_NAME "TSEC0"
+ #define CONFIG_TSEC2 1
+ #define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPS85XX_FEC
#define TSEC1_PHY_ADDR 2
/* Environment - default config is in flash, see below */
#if 0 /* in EEPROM */
-#define CFG_ENV_IS_IN_EEPROM 1
-#define CFG_ENV_OFFSET 0
-#define CFG_ENV_SIZE 2048
+# define CFG_ENV_IS_IN_EEPROM 1
+# define CFG_ENV_OFFSET 0
+# define CFG_ENV_SIZE 2048
#else /* in flash */
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_SECT_SIZE 0x40000
-
-#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE 0x4000
-#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+# define CFG_ENV_IS_IN_FLASH 1
+# ifdef CONFIG_STXSSA_4M
+# define CFG_ENV_SECT_SIZE 0x20000
+# else /* default configuration - 64 MiB flash */
+# define CFG_ENV_SECT_SIZE 0x40000
+# endif
+# define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
+# define CFG_ENV_SIZE 0x4000
+# define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
+# define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
projects / platform / kernel / u-boot.git / commitdiff