- script: |
KSYMLST=`mktemp`
KUSEDLST=`mktemp`
+ RET=0
cat `find . -name "Kconfig*"` | \
sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
-e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
NUM=`comm -123 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} | \
cut -d , -f 3`
if [[ $NUM -ne 0 ]]; then
- echo "Unmigrated symbols found in $CFG"
- exit 1
+ echo "Unmigrated symbols found in $CFG:"
+ comm -12 ${KSYMLST} ${KUSEDLST}
+ RET=1
fi
done
+ exit $RET
- job: cppcheck
displayName: 'Static code analysis with cppcheck'
script:
- KSYMLST=`mktemp`;
KUSEDLST=`mktemp`;
+ RET=0;
cat `find . -name "Kconfig*"` |
sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
-e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
NUM=`comm -123 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} |
cut -d , -f 3`;
if [[ $NUM -ne 0 ]]; then
- echo "Unmigrated symbols found in $CFG";
- exit 1;
+ echo "Unmigrated symbols found in $CFG:";
+ comm -12 ${KSYMLST} ${KUSEDLST};
+ RET=1;
fi;
- done
+ done;
+ exit $RET
# QA jobs for code analytics
# static code analysis with cppcheck (we can add --enable=all later)
config SYS_MALLOC_LEN
hex "Define memory for Dynamic allocation"
+ default 0x4000000 if SANDBOX
default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON
default 0x200000 if ARCH_BMIPS || X86
default 0x120000 if MACH_SUNIV
}
};
+/* Apple M1 Ultra */
+
+static struct mm_region t6002_mem_map[] = {
+ {
+ /* I/O */
+ .virt = 0x280000000,
+ .phys = 0x280000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x380000000,
+ .phys = 0x380000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x580000000,
+ .phys = 0x580000000,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE */
+ .virt = 0x5a0000000,
+ .phys = 0x5a0000000,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE */
+ .virt = 0x5c0000000,
+ .phys = 0x5c0000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x700000000,
+ .phys = 0x700000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0xb00000000,
+ .phys = 0xb00000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0xf00000000,
+ .phys = 0xf00000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x1300000000,
+ .phys = 0x1300000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2280000000,
+ .phys = 0x2280000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2380000000,
+ .phys = 0x2380000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2580000000,
+ .phys = 0x2580000000,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE */
+ .virt = 0x25a0000000,
+ .phys = 0x25a0000000,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE */
+ .virt = 0x25c0000000,
+ .phys = 0x25c0000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2700000000,
+ .phys = 0x2700000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2b00000000,
+ .phys = 0x2b00000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2f00000000,
+ .phys = 0x2f00000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x3300000000,
+ .phys = 0x3300000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* RAM */
+ .virt = 0x10000000000,
+ .phys = 0x10000000000,
+ .size = 16UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* Framebuffer */
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
struct mm_region *mem_map;
int board_init(void)
mem_map = t6000_mem_map;
else if (of_machine_is_compatible("apple,t6001"))
mem_map = t6000_mem_map;
+ else if (of_machine_is_compatible("apple,t6002"))
+ mem_map = t6002_mem_map;
else
panic("Unsupported SoC\n");
fake-host-hwaddr = [00 00 66 44 22 22];
};
+ phy_eth0: phy-test-eth {
+ compatible = "sandbox,eth";
+ reg = <0x10007000 0x1000>;
+ fake-host-hwaddr = [00 00 66 44 22 77];
+ phy-handle = <ðphy1>;
+ phy-mode = "2500base-x";
+ };
+
dsa_eth0: dsa-test-eth {
compatible = "sandbox,eth";
reg = <0x10006000 0x1000>;
mdio: mdio-test {
compatible = "sandbox,mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ };
};
pm-bus-test {
};
/**
+ * sandbox_serial_written() - Get the total number of characters written
+ *
+ * This returns the number of characters written by the sandbox serial
+ * device. It is intended for performing tests of the serial subsystem
+ * where a console buffer cannot be used. The absolute number should not be
+ * relied upon; call this function twice and compare the difference.
+ *
+ * Return: The number of characters written
+ */
+size_t sandbox_serial_written(void);
+
+/**
+ * sandbox_serial_endisable() - Enable or disable serial output
+ * @enabled: Whether serial output should be enabled or not
+ *
+ * This allows tests to enable or disable the sandbox serial output. All
+ * processes relating to writing output (except the actual writing) will be
+ * performed.
+ */
+void sandbox_serial_endisable(bool enabled);
+
+/**
* struct sandbox_serial_priv - Private data for this driver
*
* @buf: holds input characters available to be read by this driver
#define CB_TABLE_ADDR 0x800
/**
- * table_compute_checksum() - Compute a table checksum
- *
- * This computes an 8-bit checksum for the configuration table.
- * All bytes in the configuration table, including checksum itself and
- * reserved bytes must add up to zero.
- *
- * @v: configuration table base address
- * @len: configuration table size
- * @return: the 8-bit checksum
- */
-u8 table_compute_checksum(void *v, int len);
-
-/**
* table_fill_string() - Fill a string with pad in the configuration table
*
* This fills a string in the configuration table. It copies number of bytes
return;
}
- phydev = phy_find_by_mask(bus, BIT(1), PHY_INTERFACE_MODE_RGMII);
+ phydev = phy_find_by_mask(bus, BIT(1));
if (!phydev) {
printf("Cannot get ethernet PHY!\n");
return;
if (!bus)
return -EINVAL;
/* scan phy 4,5,6,7 */
- phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
+ phydev = phy_find_by_mask(bus, (0xf << 4));
if (!phydev) {
ret = -EINVAL;
goto free_bus;
fm_info_set_mdio(i,
miiphy_get_dev_by_name("HYDRA_RGMII_MDIO"));
break;
- case PHY_INTERFACE_MODE_NONE:
+ case PHY_INTERFACE_MODE_NA:
fm_info_set_phy_address(i, 0);
break;
default:
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
break;
- case PHY_INTERFACE_MODE_NONE:
+ case PHY_INTERFACE_MODE_NA:
fm_info_set_phy_address(i, 0);
break;
default:
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
break;
- case PHY_INTERFACE_MODE_NONE:
+ case PHY_INTERFACE_MODE_NA:
fm_info_set_phy_address(i, 0);
break;
default:
case PHY_INTERFACE_MODE_QSGMII:
fm_info_set_phy_address(i, 0);
break;
- case PHY_INTERFACE_MODE_NONE:
+ case PHY_INTERFACE_MODE_NA:
fm_info_set_phy_address(i, 0);
break;
default:
break;
}
if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||
- fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE)
+ fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NA)
fm_info_set_mdio(i, NULL);
else
fm_info_set_mdio(i,
for (k = 0; k < 2; ++k) {
struct phy_device *phydev;
- phydev = phy_find_by_mask(bus, 1 << k,
- PHY_INTERFACE_MODE_SGMII);
+ phydev = phy_find_by_mask(bus, 1 << k);
- if (phydev)
+ if (phydev) {
+ phydev->interface = PHY_INTERFACE_MODE_SGMII;
phy_config(phydev);
+ }
}
}
{
u16 reg;
+ phydev->interface = PHY_INTERFACE_MODE_MII;
phy_config(phydev);
/* enable QSGMII autonegotiation with flow control */
int init_single_phy(struct porttype *porttype, struct mii_dev *bus,
uint bus_idx, uint m, uint phy_idx)
{
- struct phy_device *phydev = phy_find_by_mask(
- bus, 1 << (m * 8 + phy_idx),
- PHY_INTERFACE_MODE_MII);
+ struct phy_device *phydev;
+ phydev = phy_find_by_mask(bus, BIT(m * 8 + phy_idx));
printf(" %u", bus_idx * 32 + m * 8 + phy_idx);
if (!phydev)
int board_init(void)
{
#ifdef CONFIG_ETH_DESIGNWARE
- const char *phy_mode;
- int node;
+ ofnode node;
- node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,stm32-dwmac");
- if (node < 0)
+ node = ofnode_by_compatible(ofnode_null(), "st,stm32-dwmac");
+ if (!ofnode_valid(node))
return -1;
- phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
-
- switch (phy_get_interface_by_name(phy_mode)) {
+ switch (ofnode_read_phy_mode(node)) {
case PHY_INTERFACE_MODE_RMII:
STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
break;
STM32_SYSCFG->pmc &= ~SYSCFG_PMC_MII_RMII_SEL;
break;
default:
- printf("PHY interface %s not supported !\n", phy_mode);
+ printf("Unsupported PHY interface!\n");
}
#endif
struct mtd_info *mtd;
int err = 0;
+ if (ubi && ubi->mtd && !strcmp(ubi->mtd->name, part_name)) {
+ printf("UBI partition '%s' already selected\n", part_name);
+ return 0;
+ }
+
ubi_detach();
mtd_probe_devices();
CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
CONFIG_USE_SYS_MAX_FLASH_BANKS=y
+CONFIG_DRIVER_DM9000=y
CONFIG_MCFUART=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_DRIVER_DM9000=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_DRIVER_DM9000=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_DRIVER_DM9000=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_MMC_HS400_SUPPORT=y
# CONFIG_MMC_VERBOSE is not set
CONFIG_JZ47XX_MMC=y
+CONFIG_DRIVER_DM9000=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_DRIVER_DM9000=y
CONFIG_DM_SERIAL=y
CONFIG_PXA_SERIAL=y
CONFIG_USB=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_DRIVER_DM9000=y
CONFIG_CONS_INDEX=3
CONFIG_JFFS2_NAND=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sandbox64"
CONFIG_SYS_TEXT_BASE=0
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_SYS_TEXT_BASE=0
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_SYS_TEXT_BASE=0x200000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_TEXT_BASE=0x200000
-CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
--- /dev/null
+* Analog Devices ADIN PHY Device Tree binding
+
+Required properties:
+- reg: PHY address
+
+Optional properties:
+- adi,rx-internal-delay-ps: RGMII RX Clock Delay used only when PHY operates
+ in RGMII mode with internal delay (phy-mode is 'rgmii-id' or
+ 'rgmii-rxid') in pico-seconds.
+- adi,tx-internal-delay-ps: RGMII TX Clock Delay used only when PHY operates
+ in RGMII mode with internal delay (phy-mode is 'rgmii-id' or
+ 'rgmii-txid') in pico-seconds.
+- adi,phy-mode-override: Override phy-mode property for adin. This is useful
+ when a single device tree supports an adin PHY (e.g. ADIN1300)
+ or another PHY (e.g. AR8033) at the same address, but they require
+ different phy-modes.
+
+Example:
+
+ ethernet-phy@0 {
+ reg = <0>;
+
+ adi,rx-internal-delay-ps = <1800>;
+ adi,tx-internal-delay-ps = <2200>;
+ adi,phy-mode-override = "rgmii-id";
+ };
return ofnode_read_string(node, prop_name);
}
+
+ofnode ofnode_get_phy_node(ofnode node)
+{
+ /* DT node properties that reference a PHY node */
+ static const char * const phy_handle_str[] = {
+ "phy-handle", "phy", "phy-device",
+ };
+ struct ofnode_phandle_args args = {
+ .node = ofnode_null()
+ };
+ int i;
+
+ assert(ofnode_valid(node));
+
+ for (i = 0; i < ARRAY_SIZE(phy_handle_str); i++)
+ if (!ofnode_parse_phandle_with_args(node, phy_handle_str[i],
+ NULL, 0, 0, &args))
+ break;
+
+ return args.node;
+}
+
+phy_interface_t ofnode_read_phy_mode(ofnode node)
+{
+ const char *mode;
+ int i;
+
+ assert(ofnode_valid(node));
+
+ mode = ofnode_read_string(node, "phy-mode");
+ if (!mode)
+ mode = ofnode_read_string(node, "phy-connection-type");
+
+ if (!mode)
+ return PHY_INTERFACE_MODE_NA;
+
+ for (i = 0; i < PHY_INTERFACE_MODE_MAX; i++)
+ if (!strcmp(mode, phy_interface_strings[i]))
+ return i;
+
+ debug("%s: Invalid PHY interface '%s'\n", __func__, mode);
+
+ return PHY_INTERFACE_MODE_NA;
+}
{
return ofnode_decode_display_timing(dev_ofnode(dev), index, config);
}
+
+ofnode dev_get_phy_node(const struct udevice *dev)
+{
+ return ofnode_get_phy_node(dev_ofnode(dev));
+}
+
+phy_interface_t dev_read_phy_mode(const struct udevice *dev)
+{
+ return ofnode_read_phy_mode(dev_ofnode(dev));
+}
}
#endif
+/* This is superseded by led_post_bind()/led_post_probe() below. */
int led_default_state(void)
{
- struct udevice *dev;
- struct uclass *uc;
+ return 0;
+}
+
+static int led_post_bind(struct udevice *dev)
+{
+ struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
const char *default_state;
- int ret;
- ret = uclass_get(UCLASS_LED, &uc);
- if (ret)
- return ret;
- for (uclass_find_first_device(UCLASS_LED, &dev);
- dev;
- uclass_find_next_device(&dev)) {
- default_state = dev_read_string(dev, "default-state");
- if (!default_state)
- continue;
- ret = device_probe(dev);
- if (ret)
- return ret;
- if (!strncmp(default_state, "on", 2))
- led_set_state(dev, LEDST_ON);
- else if (!strncmp(default_state, "off", 3))
- led_set_state(dev, LEDST_OFF);
- /* default-state = "keep" : device is only probed */
- }
+ uc_plat->label = dev_read_string(dev, "label");
+ if (!uc_plat->label)
+ uc_plat->label = ofnode_get_name(dev_ofnode(dev));
+
+ uc_plat->default_state = LEDST_COUNT;
+
+ default_state = dev_read_string(dev, "default-state");
+ if (!default_state)
+ return 0;
+
+ if (!strncmp(default_state, "on", 2))
+ uc_plat->default_state = LEDST_ON;
+ else if (!strncmp(default_state, "off", 3))
+ uc_plat->default_state = LEDST_OFF;
+ else
+ return 0;
+
+ /*
+ * In case the LED has default-state DT property, trigger
+ * probe() to configure its default state during startup.
+ */
+ return device_probe(dev);
+}
+
+static int led_post_probe(struct udevice *dev)
+{
+ struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+
+ if (uc_plat->default_state == LEDST_ON ||
+ uc_plat->default_state == LEDST_OFF)
+ led_set_state(dev, uc_plat->default_state);
- return ret;
+ return 0;
}
UCLASS_DRIVER(led) = {
.id = UCLASS_LED,
.name = "led",
.per_device_plat_auto = sizeof(struct led_uc_plat),
+ .post_bind = led_post_bind,
+ .post_probe = led_post_probe,
};
ofnode node;
dev_for_each_subnode(node, parent) {
- struct led_uc_plat *uc_plat;
struct udevice *dev;
- const char *label;
int ret;
- label = ofnode_read_string(node, "label");
- if (!label) {
- debug("%s: node %s has no label\n", __func__,
- ofnode_get_name(node));
- return -EINVAL;
- }
-
ret = device_bind_driver_to_node(parent, "bcm6328-led",
ofnode_get_name(node),
node, &dev);
if (ret)
return ret;
-
- uc_plat = dev_get_uclass_plat(dev);
- uc_plat->label = label;
}
return 0;
ofnode node;
dev_for_each_subnode(node, parent) {
- struct led_uc_plat *uc_plat;
struct udevice *dev;
- const char *label;
int ret;
- label = ofnode_read_string(node, "label");
- if (!label) {
- debug("%s: node %s has no label\n", __func__,
- ofnode_get_name(node));
- return -EINVAL;
- }
-
ret = device_bind_driver_to_node(parent, "bcm6358-led",
ofnode_get_name(node),
node, &dev);
if (ret)
return ret;
-
- uc_plat = dev_get_uclass_plat(dev);
- uc_plat->label = label;
}
return 0;
ofnode node;
dev_for_each_subnode(node, parent) {
- struct led_uc_plat *uc_plat;
struct udevice *dev;
- const char *label;
int ret;
- label = ofnode_read_string(node, "label");
- if (!label) {
- debug("%s: node %s has no label\n", __func__,
- ofnode_get_name(node));
- return -EINVAL;
- }
-
ret = device_bind_driver_to_node(parent, "bcm6753-led",
ofnode_get_name(node),
node, &dev);
if (ret)
return ret;
-
- uc_plat = dev_get_uclass_plat(dev);
- uc_plat->label = label;
}
return 0;
ofnode node;
dev_for_each_subnode(node, parent) {
- struct led_uc_plat *uc_plat;
struct udevice *dev;
- const char *label;
int ret;
- label = ofnode_read_string(node, "label");
- if (!label) {
- debug("%s: node %s has no label\n", __func__,
- ofnode_get_name(node));
- return -EINVAL;
- }
-
ret = device_bind_driver_to_node(parent, "bcm6858-led",
ofnode_get_name(node),
node, &dev);
if (ret)
return ret;
-
- uc_plat = dev_get_uclass_plat(dev);
- uc_plat->label = label;
}
return 0;
ofnode node;
dev_for_each_subnode(node, parent) {
- struct led_uc_plat *uc_plat;
struct udevice *dev;
- const char *label;
int ret;
- label = ofnode_read_string(node, "label");
- if (!label) {
- debug("%s: node %s has no label\n", __func__,
- ofnode_get_name(node));
- return -EINVAL;
- }
-
ret = device_bind_driver_to_node(parent, "ca-leds",
ofnode_get_name(node),
node, &dev);
if (ret)
return ret;
- uc_plat = dev_get_uclass_plat(dev);
- uc_plat->label = label;
}
return 0;
int ret;
dev_for_each_subnode(node, parent) {
- struct led_uc_plat *uc_plat;
- const char *label;
-
- label = ofnode_read_string(node, "label");
- if (!label)
- label = ofnode_get_name(node);
ret = device_bind_driver_to_node(parent, "gpio_led",
ofnode_get_name(node),
node, &dev);
if (ret)
return ret;
- uc_plat = dev_get_uclass_plat(dev);
- uc_plat->label = label;
}
return 0;
int ret;
dev_for_each_subnode(node, parent) {
- struct led_uc_plat *uc_plat;
- const char *label;
-
- label = ofnode_read_string(node, "label");
- if (!label)
- label = ofnode_get_name(node);
-
ret = device_bind_driver_to_node(parent, LEDS_PWM_DRIVER_NAME,
ofnode_get_name(node),
node, &dev);
if (ret)
return ret;
-
- uc_plat = dev_get_uclass_plat(dev);
- uc_plat->label = label;
}
return 0;
}
while (len--)
crc = crc16_byte(crc, *buffer++);
- return cpu_to_le16(crc);
+ return crc;
}
static int atsha204a_send(struct udevice *dev, const u8 *buf, u8 len)
#include <dm.h>
#include <misc.h>
#include <tables_csum.h>
-#ifdef CONFIG_GENERATE_ACPI_TABLE
-#include <asm/tables.h>
-#endif
#if defined(CONFIG_GENERATE_ACPI_TABLE) && !defined(CONFIG_SANDBOX)
/*
This driver supports the XGMAC in Calxeda Highbank and Midway
machines.
+config DRIVER_DM9000
+ bool "Davicom DM9000 controller driver"
+ help
+ The Davicom DM9000 parallel bus external ethernet interface chip.
+
config DWC_ETH_QOS
bool "Synopsys DWC Ethernet QOS device support"
depends on DM_ETH
static int ag7xxx_eth_of_to_plat(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
- const char *phy_mode;
int ret;
pdata->iobase = dev_read_addr(dev);
if (ret <= 0)
return ret;
- phy_mode = fdt_getprop(gd->fdt_blob, ret, "phy-mode", NULL);
- if (phy_mode)
- pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- }
return 0;
}
if (priv->phyaddr)
mask = 1 << priv->phyaddr;
- phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
+ phydev = phy_find_by_mask(priv->bus, mask);
if (!phydev)
return -ENODEV;
- phy_connect_dev(phydev, dev);
+ phy_connect_dev(phydev, dev, priv->interface);
phydev->supported &= PHY_GBIT_FEATURES;
phydev->advertising = phydev->supported;
static int altera_tse_of_to_plat(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
- const char *phy_mode;
-
- pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
- NULL);
- if (phy_mode)
- pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- }
return 0;
}
struct eth_pdata *pdata = dev_get_plat(dev);
struct bcm6348_eth_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args phy;
- const char *phy_mode;
int ret, i;
/* get base address */
pdata->iobase = (phys_addr_t) priv->base;
/* get phy mode */
- pdata->phy_interface = PHY_INTERFACE_MODE_NONE;
- phy_mode = dev_read_string(dev, "phy-mode");
- if (phy_mode)
- pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -ENODEV;
/* get phy */
}
phydev->advertising = phydev->supported;
- phy_connect_dev(phydev, dev);
-
priv->phydev = phydev;
phy_config(priv->phydev);
struct eth_pdata *pdata = dev_get_plat(dev);
struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args phy_node;
- const char *phy_mode;
int ret;
pdata->iobase = dev_read_addr(dev);
/* Get phy mode from DT */
- pdata->phy_interface = -1;
- phy_mode = dev_read_string(dev, "phy-mode");
- if (phy_mode)
- pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- }
ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
&phy_node);
struct dw_eth_dev *priv = dev_get_priv(dev);
#endif
struct eth_pdata *pdata = &dw_pdata->eth_pdata;
- const char *phy_mode;
#if CONFIG_IS_ENABLED(DM_GPIO)
int reset_flags = GPIOD_IS_OUT;
#endif
int ret = 0;
pdata->iobase = dev_read_addr(dev);
- pdata->phy_interface = -1;
- phy_mode = dev_read_string(dev, "phy-mode");
- if (phy_mode)
- pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- }
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
// SPDX-License-Identifier: GPL-2.0+
/*
- dm9000.c: Version 1.2 12/15/2003
-
- A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
- Copyright (C) 1997 Sten Wang
-
- (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
-
-V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
- 06/22/2001 Support DM9801 progrmming
- E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
- E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
- R17 = (R17 & 0xfff0) | NF + 3
- E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
- R17 = (R17 & 0xfff0) | NF
-
-v1.00 modify by simon 2001.9.5
- change for kernel 2.4.x
-
-v1.1 11/09/2001 fix force mode bug
-
-v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
- Fixed phy reset.
- Added tx/rx 32 bit mode.
- Cleaned up for kernel merge.
-
---------------------------------------
-
- 12/15/2003 Initial port to u-boot by
- Sascha Hauer <saschahauer@web.de>
-
- 06/03/2008 Remy Bohmer <linux@bohmer.net>
- - Fixed the driver to work with DM9000A.
- (check on ISR receive status bit before reading the
- FIFO as described in DM9000 programming guide and
- application notes)
- - Added autodetect of databus width.
- - Made debug code compile again.
- - Adapt eth_send such that it matches the DM9000*
- application notes. Needed to make it work properly
- for DM9000A.
- - Adapted reset procedure to match DM9000 application
- notes (i.e. double reset)
- - some minor code cleanups
- These changes are tested with DM9000{A,EP,E} together
- with a 200MHz Atmel AT91SAM9261 core
-
-TODO: external MII is not functional, only internal at the moment.
-*/
+ * dm9000.c: Version 1.2 12/15/2003
+ *
+ * A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
+ * Copyright (C) 1997 Sten Wang
+ *
+ * (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
+ *
+ * V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
+ * 06/22/2001 Support DM9801 progrmming
+ * E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
+ * E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
+ * R17 = (R17 & 0xfff0) | NF + 3
+ * E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
+ * R17 = (R17 & 0xfff0) | NF
+ *
+ * v1.00 modify by simon 2001.9.5
+ * change for kernel 2.4.x
+ *
+ * v1.1 11/09/2001 fix force mode bug
+ *
+ * v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
+ * Fixed phy reset.
+ * Added tx/rx 32 bit mode.
+ * Cleaned up for kernel merge.
+ *
+ * --------------------------------------
+ *
+ * 12/15/2003 Initial port to u-boot by
+ * Sascha Hauer <saschahauer@web.de>
+ *
+ * 06/03/2008 Remy Bohmer <linux@bohmer.net>
+ * - Fixed the driver to work with DM9000A.
+ * (check on ISR receive status bit before reading the
+ * FIFO as described in DM9000 programming guide and
+ * application notes)
+ * - Added autodetect of databus width.
+ * - Made debug code compile again.
+ * - Adapt eth_send such that it matches the DM9000*
+ * application notes. Needed to make it work properly
+ * for DM9000A.
+ * - Adapted reset procedure to match DM9000 application
+ * notes (i.e. double reset)
+ * - some minor code cleanups
+ * These changes are tested with DM9000{A,EP,E} together
+ * with a 200MHz Atmel AT91SAM9261 core
+ *
+ * TODO: external MII is not functional, only internal at the moment.
+ */
#include <common.h>
#include <command.h>
+#include <dm.h>
+#include <malloc.h>
#include <net.h>
#include <asm/io.h>
-#include <dm9000.h>
#include <linux/delay.h>
#include "dm9000x.h"
-/* Board/System/Debug information/definition ---------------- */
-
-/* #define CONFIG_DM9000_DEBUG */
-
-#ifdef CONFIG_DM9000_DEBUG
-#define DM9000_DBG(fmt,args...) printf(fmt, ##args)
-#define DM9000_DMP_PACKET(func,packet,length) \
- do { \
- int i; \
- printf("%s: length: %d\n", func, length); \
- for (i = 0; i < length; i++) { \
- if (i % 8 == 0) \
- printf("\n%s: %02x: ", func, i); \
- printf("%02x ", ((unsigned char *) packet)[i]); \
- } printf("\n"); \
- } while(0)
-#else
-#define DM9000_DBG(fmt,args...)
-#define DM9000_DMP_PACKET(func,packet,length)
-#endif
-
/* Structure/enum declaration ------------------------------- */
-typedef struct board_info {
+struct dm9000_priv {
u32 runt_length_counter; /* counter: RX length < 64byte */
u32 long_length_counter; /* counter: RX length > 1514byte */
u32 reset_counter; /* counter: RESET */
u8 phy_addr;
u8 device_wait_reset; /* device state */
unsigned char srom[128];
- void (*outblk)(volatile void *data_ptr, int count);
- void (*inblk)(void *data_ptr, int count);
- void (*rx_status)(u16 *RxStatus, u16 *RxLen);
- struct eth_device netdev;
-} board_info_t;
-static board_info_t dm9000_info;
-
-
-/* function declaration ------------------------------------- */
-static int dm9000_probe(void);
-static u16 dm9000_phy_read(int);
-static void dm9000_phy_write(int, u16);
-static u8 DM9000_ior(int);
-static void DM9000_iow(int reg, u8 value);
+ void (*outblk)(struct dm9000_priv *db, void *data_ptr, int count);
+ void (*inblk)(struct dm9000_priv *db, void *data_ptr, int count);
+ void (*rx_status)(struct dm9000_priv *db, u16 *rxstatus, u16 *rxlen);
+#ifndef CONFIG_DM_ETH
+ struct eth_device dev;
+#endif
+ void __iomem *base_io;
+ void __iomem *base_data;
+};
/* DM9000 network board routine ---------------------------- */
#ifndef CONFIG_DM9000_BYTE_SWAPPED
-#define DM9000_outb(d,r) writeb(d, (volatile u8 *)(r))
-#define DM9000_outw(d,r) writew(d, (volatile u16 *)(r))
-#define DM9000_outl(d,r) writel(d, (volatile u32 *)(r))
-#define DM9000_inb(r) readb((volatile u8 *)(r))
-#define DM9000_inw(r) readw((volatile u16 *)(r))
-#define DM9000_inl(r) readl((volatile u32 *)(r))
+#define dm9000_outb(d, r) writeb((d), (r))
+#define dm9000_outw(d, r) writew((d), (r))
+#define dm9000_outl(d, r) writel((d), (r))
+#define dm9000_inb(r) readb(r)
+#define dm9000_inw(r) readw(r)
+#define dm9000_inl(r) readl(r)
#else
-#define DM9000_outb(d, r) __raw_writeb(d, r)
-#define DM9000_outw(d, r) __raw_writew(d, r)
-#define DM9000_outl(d, r) __raw_writel(d, r)
-#define DM9000_inb(r) __raw_readb(r)
-#define DM9000_inw(r) __raw_readw(r)
-#define DM9000_inl(r) __raw_readl(r)
+#define dm9000_outb(d, r) __raw_writeb(d, r)
+#define dm9000_outw(d, r) __raw_writew(d, r)
+#define dm9000_outl(d, r) __raw_writel(d, r)
+#define dm9000_inb(r) __raw_readb(r)
+#define dm9000_inw(r) __raw_readw(r)
+#define dm9000_inl(r) __raw_readl(r)
#endif
-#ifdef CONFIG_DM9000_DEBUG
-static void
-dump_regs(void)
-{
- DM9000_DBG("\n");
- DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0));
- DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1));
- DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2));
- DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3));
- DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
- DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5));
- DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6));
- DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR));
- DM9000_DBG("\n");
+#ifdef DEBUG
+static void dm9000_dump_packet(const char *func, u8 *packet, int length)
+{
+ int i;
+
+ printf("%s: length: %d\n", func, length);
+
+ for (i = 0; i < length; i++) {
+ if (i % 8 == 0)
+ printf("\n%s: %02x: ", func, i);
+ printf("%02x ", packet[i]);
+ }
+
+ printf("\n");
}
+#else
+static void dm9000_dump_packet(const char *func, u8 *packet, int length) {}
#endif
-static void dm9000_outblk_8bit(volatile void *data_ptr, int count)
+static void dm9000_outblk_8bit(struct dm9000_priv *db, void *data_ptr, int count)
{
int i;
+
for (i = 0; i < count; i++)
- DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA);
+ dm9000_outb((((u8 *)data_ptr)[i] & 0xff), db->base_data);
}
-static void dm9000_outblk_16bit(volatile void *data_ptr, int count)
+static void dm9000_outblk_16bit(struct dm9000_priv *db, void *data_ptr, int count)
{
int i;
u32 tmplen = (count + 1) / 2;
for (i = 0; i < tmplen; i++)
- DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
+ dm9000_outw(((u16 *)data_ptr)[i], db->base_data);
}
-static void dm9000_outblk_32bit(volatile void *data_ptr, int count)
+
+static void dm9000_outblk_32bit(struct dm9000_priv *db, void *data_ptr, int count)
{
int i;
u32 tmplen = (count + 3) / 4;
for (i = 0; i < tmplen; i++)
- DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
+ dm9000_outl(((u32 *)data_ptr)[i], db->base_data);
}
-static void dm9000_inblk_8bit(void *data_ptr, int count)
+static void dm9000_inblk_8bit(struct dm9000_priv *db, void *data_ptr, int count)
{
int i;
+
for (i = 0; i < count; i++)
- ((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA);
+ ((u8 *)data_ptr)[i] = dm9000_inb(db->base_data);
}
-static void dm9000_inblk_16bit(void *data_ptr, int count)
+static void dm9000_inblk_16bit(struct dm9000_priv *db, void *data_ptr, int count)
{
int i;
u32 tmplen = (count + 1) / 2;
for (i = 0; i < tmplen; i++)
- ((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA);
+ ((u16 *)data_ptr)[i] = dm9000_inw(db->base_data);
}
-static void dm9000_inblk_32bit(void *data_ptr, int count)
+
+static void dm9000_inblk_32bit(struct dm9000_priv *db, void *data_ptr, int count)
{
int i;
u32 tmplen = (count + 3) / 4;
for (i = 0; i < tmplen; i++)
- ((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA);
+ ((u32 *)data_ptr)[i] = dm9000_inl(db->base_data);
}
-static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen)
+static void dm9000_rx_status_32bit(struct dm9000_priv *db, u16 *rxstatus, u16 *rxlen)
{
u32 tmpdata;
- DM9000_outb(DM9000_MRCMD, DM9000_IO);
+ dm9000_outb(DM9000_MRCMD, db->base_io);
- tmpdata = DM9000_inl(DM9000_DATA);
- *RxStatus = __le16_to_cpu(tmpdata);
- *RxLen = __le16_to_cpu(tmpdata >> 16);
+ tmpdata = dm9000_inl(db->base_data);
+ *rxstatus = __le16_to_cpu(tmpdata);
+ *rxlen = __le16_to_cpu(tmpdata >> 16);
}
-static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen)
+static void dm9000_rx_status_16bit(struct dm9000_priv *db, u16 *rxstatus, u16 *rxlen)
{
- DM9000_outb(DM9000_MRCMD, DM9000_IO);
+ dm9000_outb(DM9000_MRCMD, db->base_io);
- *RxStatus = __le16_to_cpu(DM9000_inw(DM9000_DATA));
- *RxLen = __le16_to_cpu(DM9000_inw(DM9000_DATA));
+ *rxstatus = __le16_to_cpu(dm9000_inw(db->base_data));
+ *rxlen = __le16_to_cpu(dm9000_inw(db->base_data));
}
-static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen)
+static void dm9000_rx_status_8bit(struct dm9000_priv *db, u16 *rxstatus, u16 *rxlen)
{
- DM9000_outb(DM9000_MRCMD, DM9000_IO);
+ dm9000_outb(DM9000_MRCMD, db->base_io);
+
+ *rxstatus =
+ __le16_to_cpu(dm9000_inb(db->base_data) +
+ (dm9000_inb(db->base_data) << 8));
+ *rxlen =
+ __le16_to_cpu(dm9000_inb(db->base_data) +
+ (dm9000_inb(db->base_data) << 8));
+}
- *RxStatus =
- __le16_to_cpu(DM9000_inb(DM9000_DATA) +
- (DM9000_inb(DM9000_DATA) << 8));
- *RxLen =
- __le16_to_cpu(DM9000_inb(DM9000_DATA) +
- (DM9000_inb(DM9000_DATA) << 8));
+/*
+ * Read a byte from I/O port
+ */
+static u8 dm9000_ior(struct dm9000_priv *db, int reg)
+{
+ dm9000_outb(reg, db->base_io);
+ return dm9000_inb(db->base_data);
+}
+
+/*
+ * Write a byte to I/O port
+ */
+static void dm9000_iow(struct dm9000_priv *db, int reg, u8 value)
+{
+ dm9000_outb(reg, db->base_io);
+ dm9000_outb(value, db->base_data);
+}
+
+/*
+ * Read a word from phyxcer
+ */
+static u16 dm9000_phy_read(struct dm9000_priv *db, int reg)
+{
+ u16 val;
+
+ /* Fill the phyxcer register into REG_0C */
+ dm9000_iow(db, DM9000_EPAR, DM9000_PHY | reg);
+ dm9000_iow(db, DM9000_EPCR, 0xc); /* Issue phyxcer read command */
+ udelay(100); /* Wait read complete */
+ dm9000_iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */
+ val = (dm9000_ior(db, DM9000_EPDRH) << 8) |
+ dm9000_ior(db, DM9000_EPDRL);
+
+ /* The read data keeps on REG_0D & REG_0E */
+ debug("%s(0x%x): 0x%x\n", __func__, reg, val);
+ return val;
}
/*
- Search DM9000 board, allocate space and register it
-*/
-int
-dm9000_probe(void)
+ * Write a word to phyxcer
+ */
+static void dm9000_phy_write(struct dm9000_priv *db, int reg, u16 value)
+{
+ /* Fill the phyxcer register into REG_0C */
+ dm9000_iow(db, DM9000_EPAR, DM9000_PHY | reg);
+
+ /* Fill the written data into REG_0D & REG_0E */
+ dm9000_iow(db, DM9000_EPDRL, (value & 0xff));
+ dm9000_iow(db, DM9000_EPDRH, ((value >> 8) & 0xff));
+ dm9000_iow(db, DM9000_EPCR, 0xa); /* Issue phyxcer write command */
+ udelay(500); /* Wait write complete */
+ dm9000_iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
+ debug("%s(reg:0x%x, value:0x%x)\n", __func__, reg, value);
+}
+
+/*
+ * Search DM9000 board, allocate space and register it
+ */
+static int dm9000_probe(struct dm9000_priv *db)
{
u32 id_val;
- id_val = DM9000_ior(DM9000_VIDL);
- id_val |= DM9000_ior(DM9000_VIDH) << 8;
- id_val |= DM9000_ior(DM9000_PIDL) << 16;
- id_val |= DM9000_ior(DM9000_PIDH) << 24;
- if (id_val == DM9000_ID) {
- printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
- id_val);
- return 0;
- } else {
- printf("dm9000 not found at 0x%08x id: 0x%08x\n",
- CONFIG_DM9000_BASE, id_val);
+
+ id_val = dm9000_ior(db, DM9000_VIDL);
+ id_val |= dm9000_ior(db, DM9000_VIDH) << 8;
+ id_val |= dm9000_ior(db, DM9000_PIDL) << 16;
+ id_val |= dm9000_ior(db, DM9000_PIDH) << 24;
+ if (id_val != DM9000_ID) {
+ printf("dm9000 not found at 0x%p id: 0x%08x\n",
+ db->base_io, id_val);
return -1;
}
+
+ printf("dm9000 i/o: 0x%p, id: 0x%x\n", db->base_io, id_val);
+ return 0;
}
/* General Purpose dm9000 reset routine */
-static void
-dm9000_reset(void)
+static void dm9000_reset(struct dm9000_priv *db)
{
- DM9000_DBG("resetting DM9000\n");
+ debug("resetting DM9000\n");
- /* Reset DM9000,
- see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */
+ /*
+ * Reset DM9000,
+ * see DM9000 Application Notes V1.22 Jun 11, 2004 page 29
+ */
/* DEBUG: Make all GPIO0 outputs, all others inputs */
- DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT);
+ dm9000_iow(db, DM9000_GPCR, GPCR_GPIO0_OUT);
/* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
- DM9000_iow(DM9000_GPR, 0);
+ dm9000_iow(db, DM9000_GPR, 0);
/* Step 2: Software reset */
- DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));
+ dm9000_iow(db, DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));
do {
- DM9000_DBG("resetting the DM9000, 1st reset\n");
+ debug("resetting the DM9000, 1st reset\n");
udelay(25); /* Wait at least 20 us */
- } while (DM9000_ior(DM9000_NCR) & 1);
+ } while (dm9000_ior(db, DM9000_NCR) & 1);
- DM9000_iow(DM9000_NCR, 0);
- DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */
+ dm9000_iow(db, DM9000_NCR, 0);
+ dm9000_iow(db, DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */
do {
- DM9000_DBG("resetting the DM9000, 2nd reset\n");
+ debug("resetting the DM9000, 2nd reset\n");
udelay(25); /* Wait at least 20 us */
- } while (DM9000_ior(DM9000_NCR) & 1);
+ } while (dm9000_ior(db, DM9000_NCR) & 1);
/* Check whether the ethernet controller is present */
- if ((DM9000_ior(DM9000_PIDL) != 0x0) ||
- (DM9000_ior(DM9000_PIDH) != 0x90))
+ if ((dm9000_ior(db, DM9000_PIDL) != 0x0) ||
+ (dm9000_ior(db, DM9000_PIDH) != 0x90))
printf("ERROR: resetting DM9000 -> not responding\n");
}
-/* Initialize dm9000 board
-*/
-static int dm9000_init(struct eth_device *dev, struct bd_info *bd)
+/* Initialize dm9000 board */
+static int dm9000_init_common(struct dm9000_priv *db, u8 enetaddr[6])
{
int i, oft, lnk;
u8 io_mode;
- struct board_info *db = &dm9000_info;
-
- DM9000_DBG("%s\n", __func__);
/* RESET device */
- dm9000_reset();
+ dm9000_reset(db);
- if (dm9000_probe() < 0)
+ if (dm9000_probe(db) < 0)
return -1;
/* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
- io_mode = DM9000_ior(DM9000_ISR) >> 6;
+ io_mode = dm9000_ior(db, DM9000_ISR) >> 6;
switch (io_mode) {
case 0x0: /* 16-bit mode */
}
/* Program operating register, only internal phy supported */
- DM9000_iow(DM9000_NCR, 0x0);
+ dm9000_iow(db, DM9000_NCR, 0x0);
/* TX Polling clear */
- DM9000_iow(DM9000_TCR, 0);
+ dm9000_iow(db, DM9000_TCR, 0);
/* Less 3Kb, 200us */
- DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US);
+ dm9000_iow(db, DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US);
/* Flow Control : High/Low Water */
- DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
+ dm9000_iow(db, DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
/* SH FIXME: This looks strange! Flow Control */
- DM9000_iow(DM9000_FCR, 0x0);
+ dm9000_iow(db, DM9000_FCR, 0x0);
/* Special Mode */
- DM9000_iow(DM9000_SMCR, 0);
+ dm9000_iow(db, DM9000_SMCR, 0);
/* clear TX status */
- DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
+ dm9000_iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
/* Clear interrupt status */
- DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
+ dm9000_iow(db, DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
- printf("MAC: %pM\n", dev->enetaddr);
- if (!is_valid_ethaddr(dev->enetaddr)) {
+ printf("MAC: %pM\n", enetaddr);
+ if (!is_valid_ethaddr(enetaddr))
printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n");
- }
/* fill device MAC address registers */
for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
- DM9000_iow(oft, dev->enetaddr[i]);
+ dm9000_iow(db, oft, enetaddr[i]);
for (i = 0, oft = 0x16; i < 8; i++, oft++)
- DM9000_iow(oft, 0xff);
+ dm9000_iow(db, oft, 0xff);
/* read back mac, just to be sure */
for (i = 0, oft = 0x10; i < 6; i++, oft++)
- DM9000_DBG("%02x:", DM9000_ior(oft));
- DM9000_DBG("\n");
+ debug("%02x:", dm9000_ior(db, oft));
+ debug("\n");
/* Activate DM9000 */
/* RX enable */
- DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
+ dm9000_iow(db, DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
/* Enable TX/RX interrupt mask */
- DM9000_iow(DM9000_IMR, IMR_PAR);
+ dm9000_iow(db, DM9000_IMR, IMR_PAR);
i = 0;
- while (!(dm9000_phy_read(1) & 0x20)) { /* autonegation complete bit */
+ while (!(dm9000_phy_read(db, 1) & 0x20)) { /* autonegation complete bit */
udelay(1000);
i++;
if (i == 10000) {
}
/* see what we've got */
- lnk = dm9000_phy_read(17) >> 12;
+ lnk = dm9000_phy_read(db, 17) >> 12;
printf("operating at ");
switch (lnk) {
case 1:
}
/*
- Hardware start transmission.
- Send a packet to media from the upper layer.
-*/
-static int dm9000_send(struct eth_device *netdev, void *packet, int length)
+ * Hardware start transmission.
+ * Send a packet to media from the upper layer.
+ */
+static int dm9000_send_common(struct dm9000_priv *db, void *packet, int length)
{
int tmo;
- struct board_info *db = &dm9000_info;
- DM9000_DMP_PACKET(__func__ , packet, length);
+ dm9000_dump_packet(__func__, packet, length);
- DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
+ dm9000_iow(db, DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
/* Move data to DM9000 TX RAM */
- DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */
+ dm9000_outb(DM9000_MWCMD, db->base_io); /* Prepare for TX-data */
/* push the data to the TX-fifo */
- (db->outblk)(packet, length);
+ db->outblk(db, packet, length);
/* Set TX length to DM9000 */
- DM9000_iow(DM9000_TXPLL, length & 0xff);
- DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
+ dm9000_iow(db, DM9000_TXPLL, length & 0xff);
+ dm9000_iow(db, DM9000_TXPLH, (length >> 8) & 0xff);
/* Issue TX polling command */
- DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
+ dm9000_iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
/* wait for end of transmission */
tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
- while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
- !(DM9000_ior(DM9000_ISR) & IMR_PTM) ) {
+ while (!(dm9000_ior(db, DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
+ !(dm9000_ior(db, DM9000_ISR) & IMR_PTM)) {
if (get_timer(0) >= tmo) {
printf("transmission timeout\n");
break;
}
}
- DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
+ dm9000_iow(db, DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
- DM9000_DBG("transmit done\n\n");
+ debug("transmit done\n\n");
return 0;
}
/*
- Stop the interface.
- The interface is stopped when it is brought.
-*/
-static void dm9000_halt(struct eth_device *netdev)
+ * Stop the interface.
+ * The interface is stopped when it is brought.
+ */
+static void dm9000_halt_common(struct dm9000_priv *db)
{
- DM9000_DBG("%s\n", __func__);
-
- /* RESET devie */
- dm9000_phy_write(0, 0x8000); /* PHY RESET */
- DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */
- DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */
- DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */
+ /* RESET device */
+ dm9000_phy_write(db, 0, 0x8000); /* PHY RESET */
+ dm9000_iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */
+ dm9000_iow(db, DM9000_IMR, 0x80); /* Disable all interrupt */
+ dm9000_iow(db, DM9000_RCR, 0x00); /* Disable RX */
}
/*
- Received a packet and pass to upper layer
-*/
-static int dm9000_rx(struct eth_device *netdev)
+ * Received a packet and pass to upper layer
+ */
+static int dm9000_recv_common(struct dm9000_priv *db, uchar *rdptr)
{
u8 rxbyte;
- u8 *rdptr = (u8 *)net_rx_packets[0];
- u16 RxStatus, RxLen = 0;
- struct board_info *db = &dm9000_info;
+ u16 rxstatus, rxlen = 0;
- /* Check packet ready or not, we must check
- the ISR status first for DM9000A */
- if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */
+ /*
+ * Check packet ready or not, we must check
+ * the ISR status first for DM9000A
+ */
+ if (!(dm9000_ior(db, DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */
return 0;
- DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */
+ dm9000_iow(db, DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */
/* There is _at least_ 1 package in the fifo, read them all */
- for (;;) {
- DM9000_ior(DM9000_MRCMDX); /* Dummy read */
-
- /* Get most updated data,
- only look at bits 0:1, See application notes DM9000 */
- rxbyte = DM9000_inb(DM9000_DATA) & 0x03;
-
- /* Status check: this byte must be 0 or 1 */
- if (rxbyte > DM9000_PKT_RDY) {
- DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */
- DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
- printf("DM9000 error: status check fail: 0x%x\n",
- rxbyte);
- return 0;
- }
+ dm9000_ior(db, DM9000_MRCMDX); /* Dummy read */
+
+ /*
+ * Get most updated data,
+ * only look at bits 0:1, See application notes DM9000
+ */
+ rxbyte = dm9000_inb(db->base_data) & 0x03;
+
+ /* Status check: this byte must be 0 or 1 */
+ if (rxbyte > DM9000_PKT_RDY) {
+ dm9000_iow(db, DM9000_RCR, 0x00); /* Stop Device */
+ dm9000_iow(db, DM9000_ISR, 0x80); /* Stop INT request */
+ printf("DM9000 error: status check fail: 0x%x\n",
+ rxbyte);
+ return -EINVAL;
+ }
+
+ if (rxbyte != DM9000_PKT_RDY)
+ return 0; /* No packet received, ignore */
+
+ debug("receiving packet\n");
- if (rxbyte != DM9000_PKT_RDY)
- return 0; /* No packet received, ignore */
-
- DM9000_DBG("receiving packet\n");
-
- /* A packet ready now & Get status/length */
- (db->rx_status)(&RxStatus, &RxLen);
-
- DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
-
- /* Move data from DM9000 */
- /* Read received packet from RX SRAM */
- (db->inblk)(rdptr, RxLen);
-
- if ((RxStatus & 0xbf00) || (RxLen < 0x40)
- || (RxLen > DM9000_PKT_MAX)) {
- if (RxStatus & 0x100) {
- printf("rx fifo error\n");
- }
- if (RxStatus & 0x200) {
- printf("rx crc error\n");
- }
- if (RxStatus & 0x8000) {
- printf("rx length error\n");
- }
- if (RxLen > DM9000_PKT_MAX) {
- printf("rx length too big\n");
- dm9000_reset();
- }
- } else {
- DM9000_DMP_PACKET(__func__ , rdptr, RxLen);
-
- DM9000_DBG("passing packet to upper layer\n");
- net_process_received_packet(net_rx_packets[0], RxLen);
+ /* A packet ready now & Get status/length */
+ db->rx_status(db, &rxstatus, &rxlen);
+
+ debug("rx status: 0x%04x rx len: %d\n", rxstatus, rxlen);
+
+ /* Move data from DM9000 */
+ /* Read received packet from RX SRAM */
+ db->inblk(db, rdptr, rxlen);
+
+ if (rxstatus & 0xbf00 || rxlen < 0x40 || rxlen > DM9000_PKT_MAX) {
+ if (rxstatus & 0x100)
+ printf("rx fifo error\n");
+ if (rxstatus & 0x200)
+ printf("rx crc error\n");
+ if (rxstatus & 0x8000)
+ printf("rx length error\n");
+ if (rxlen > DM9000_PKT_MAX) {
+ printf("rx length too big\n");
+ dm9000_reset(db);
}
+ return -EINVAL;
}
- return 0;
+
+ return rxlen;
}
/*
- Read a word data from SROM
-*/
+ * Read a word data from SROM
+ */
#if !defined(CONFIG_DM9000_NO_SROM)
-void dm9000_read_srom_word(int offset, u8 *to)
-{
- DM9000_iow(DM9000_EPAR, offset);
- DM9000_iow(DM9000_EPCR, 0x4);
- udelay(8000);
- DM9000_iow(DM9000_EPCR, 0x0);
- to[0] = DM9000_ior(DM9000_EPDRL);
- to[1] = DM9000_ior(DM9000_EPDRH);
-}
-
-void dm9000_write_srom_word(int offset, u16 val)
+static void dm9000_read_srom_word(struct dm9000_priv *db, int offset, u8 *to)
{
- DM9000_iow(DM9000_EPAR, offset);
- DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
- DM9000_iow(DM9000_EPDRL, (val & 0xff));
- DM9000_iow(DM9000_EPCR, 0x12);
- udelay(8000);
- DM9000_iow(DM9000_EPCR, 0);
+ dm9000_iow(db, DM9000_EPAR, offset);
+ dm9000_iow(db, DM9000_EPCR, 0x4);
+ mdelay(8);
+ dm9000_iow(db, DM9000_EPCR, 0x0);
+ to[0] = dm9000_ior(db, DM9000_EPDRL);
+ to[1] = dm9000_ior(db, DM9000_EPDRH);
}
-#endif
-static void dm9000_get_enetaddr(struct eth_device *dev)
+static void dm9000_get_enetaddr(struct dm9000_priv *db, u8 *enetaddr)
{
-#if !defined(CONFIG_DM9000_NO_SROM)
int i;
+
for (i = 0; i < 3; i++)
- dm9000_read_srom_word(i, dev->enetaddr + (2 * i));
-#endif
+ dm9000_read_srom_word(db, i, enetaddr + (2 * i));
}
+#else
+static void dm9000_get_enetaddr(struct dm9000_priv *db, u8 *enetaddr) {}
+#endif
-/*
- Read a byte from I/O port
-*/
-static u8
-DM9000_ior(int reg)
+#ifndef CONFIG_DM_ETH
+static int dm9000_init(struct eth_device *dev, struct bd_info *bd)
{
- DM9000_outb(reg, DM9000_IO);
- return DM9000_inb(DM9000_DATA);
+ struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev);
+
+ return dm9000_init_common(db, dev->enetaddr);
}
-/*
- Write a byte to I/O port
-*/
-static void
-DM9000_iow(int reg, u8 value)
+static void dm9000_halt(struct eth_device *dev)
{
- DM9000_outb(reg, DM9000_IO);
- DM9000_outb(value, DM9000_DATA);
+ struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev);
+
+ dm9000_halt_common(db);
}
-/*
- Read a word from phyxcer
-*/
-static u16
-dm9000_phy_read(int reg)
+static int dm9000_send(struct eth_device *dev, void *packet, int length)
{
- u16 val;
+ struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev);
- /* Fill the phyxcer register into REG_0C */
- DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
- DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
- udelay(100); /* Wait read complete */
- DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
- val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
-
- /* The read data keeps on REG_0D & REG_0E */
- DM9000_DBG("dm9000_phy_read(0x%x): 0x%x\n", reg, val);
- return val;
+ return dm9000_send_common(db, packet, length);
}
-/*
- Write a word to phyxcer
-*/
-static void
-dm9000_phy_write(int reg, u16 value)
+static int dm9000_recv(struct eth_device *dev)
{
+ struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev);
+ int ret;
- /* Fill the phyxcer register into REG_0C */
- DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
+ ret = dm9000_recv_common(db, net_rx_packets[0]);
+ if (ret > 0)
+ net_process_received_packet(net_rx_packets[0], ret);
- /* Fill the written data into REG_0D & REG_0E */
- DM9000_iow(DM9000_EPDRL, (value & 0xff));
- DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
- DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
- udelay(500); /* Wait write complete */
- DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
- DM9000_DBG("dm9000_phy_write(reg:0x%x, value:0x%x)\n", reg, value);
+ return ret;
}
int dm9000_initialize(struct bd_info *bis)
{
- struct eth_device *dev = &(dm9000_info.netdev);
+ struct dm9000_priv *priv;
+ struct eth_device *dev;
+
+ priv = calloc(1, sizeof(*priv));
+ if (!priv)
+ return -ENOMEM;
+
+ dev = &priv->dev;
+
+ priv->base_io = (void __iomem *)DM9000_IO;
+ priv->base_data = (void __iomem *)DM9000_DATA;
/* Load MAC address from EEPROM */
- dm9000_get_enetaddr(dev);
+ dm9000_get_enetaddr(priv, dev->enetaddr);
dev->init = dm9000_init;
dev->halt = dm9000_halt;
dev->send = dm9000_send;
- dev->recv = dm9000_rx;
+ dev->recv = dm9000_recv;
strcpy(dev->name, "dm9000");
- eth_register(dev);
+ eth_register(&priv->dev);
+
+ return 0;
+}
+#else /* ifdef CONFIG_DM_ETH */
+static int dm9000_start(struct udevice *dev)
+{
+ struct dm9000_priv *db = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+
+ return dm9000_init_common(db, pdata->enetaddr);
+}
+
+static void dm9000_stop(struct udevice *dev)
+{
+ struct dm9000_priv *db = dev_get_priv(dev);
+
+ dm9000_halt_common(db);
+}
+
+static int dm9000_send(struct udevice *dev, void *packet, int length)
+{
+ struct dm9000_priv *db = dev_get_priv(dev);
+ int ret;
+
+ ret = dm9000_send_common(db, packet, length);
+
+ return ret ? 0 : -ETIMEDOUT;
+}
+
+static int dm9000_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct dm9000_priv *db = dev_get_priv(dev);
+ uchar *data = net_rx_packets[0];
+ int ret;
+
+ ret = dm9000_recv_common(db, data);
+ if (ret)
+ *packetp = (void *)data;
+
+ return ret ? ret : -EAGAIN;
+}
+
+static int dm9000_write_hwaddr(struct udevice *dev)
+{
+ struct dm9000_priv *db = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ int i, oft;
+
+ /* fill device MAC address registers */
+ for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
+ dm9000_iow(db, oft, pdata->enetaddr[i]);
+
+ for (i = 0, oft = 0x16; i < 8; i++, oft++)
+ dm9000_iow(db, oft, 0xff);
+
+ /* read back mac, just to be sure */
+ for (i = 0, oft = 0x10; i < 6; i++, oft++)
+ debug("%02x:", dm9000_ior(db, oft));
+
+ debug("\n");
return 0;
}
+
+static int dm9000_read_rom_hwaddr(struct udevice *dev)
+{
+ struct dm9000_priv *db = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+
+ dm9000_get_enetaddr(db, pdata->enetaddr);
+
+ return !is_valid_ethaddr(pdata->enetaddr);
+}
+
+static int dm9000_bind(struct udevice *dev)
+{
+ return device_set_name(dev, dev->name);
+}
+
+static int dm9000_of_to_plat(struct udevice *dev)
+{
+ struct dm9000_priv *db = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+
+ pdata->iobase = dev_read_addr_index(dev, 0);
+ db->base_io = (void __iomem *)pdata->iobase;
+ db->base_data = (void __iomem *)dev_read_addr_index(dev, 1);
+
+ return 0;
+}
+
+static const struct eth_ops dm9000_ops = {
+ .start = dm9000_start,
+ .stop = dm9000_stop,
+ .send = dm9000_send,
+ .recv = dm9000_recv,
+ .write_hwaddr = dm9000_write_hwaddr,
+ .read_rom_hwaddr = dm9000_read_rom_hwaddr,
+};
+
+static const struct udevice_id dm9000_ids[] = {
+ { .compatible = "davicom,dm9000" },
+ { }
+};
+
+U_BOOT_DRIVER(dm9000) = {
+ .name = "eth_dm9000",
+ .id = UCLASS_ETH,
+ .of_match = dm9000_ids,
+ .bind = dm9000_bind,
+ .of_to_plat = dm9000_of_to_plat,
+ .ops = &dm9000_ops,
+ .priv_auto = sizeof(struct dm9000_priv),
+ .plat_auto = sizeof(struct eth_pdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif
int config_mac;
int config_mac_mdio;
unsigned int axi_bus_width;
- phy_interface_t (*interface)(struct udevice *dev);
+ phy_interface_t (*interface)(const struct udevice *dev);
struct eqos_ops *ops;
};
interface = eqos->config->interface(dev);
- if (interface == PHY_INTERFACE_MODE_NONE) {
+ if (interface == PHY_INTERFACE_MODE_NA) {
pr_err("Invalid PHY interface\n");
return -EINVAL;
}
return ret;
}
-static phy_interface_t eqos_get_interface_stm32(struct udevice *dev)
-{
- const char *phy_mode;
- phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
-
- debug("%s(dev=%p):\n", __func__, dev);
-
- phy_mode = dev_read_prop(dev, "phy-mode", NULL);
- if (phy_mode)
- interface = phy_get_interface_by_name(phy_mode);
-
- return interface;
-}
-
-static phy_interface_t eqos_get_interface_tegra186(struct udevice *dev)
+static phy_interface_t eqos_get_interface_tegra186(const struct udevice *dev)
{
return PHY_INTERFACE_MODE_MII;
}
interface = eqos->config->interface(dev);
- if (interface == PHY_INTERFACE_MODE_NONE) {
+ if (interface == PHY_INTERFACE_MODE_NA) {
pr_err("Invalid PHY interface\n");
return -EINVAL;
}
return 0;
}
-static phy_interface_t eqos_get_interface_imx(struct udevice *dev)
-{
- const char *phy_mode;
- phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
-
- debug("%s(dev=%p):\n", __func__, dev);
-
- phy_mode = dev_read_prop(dev, "phy-mode", NULL);
- if (phy_mode)
- interface = phy_get_interface_by_name(phy_mode);
-
- return interface;
-}
-
static int eqos_remove_resources_tegra186(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
.axi_bus_width = EQOS_AXI_WIDTH_64,
- .interface = eqos_get_interface_stm32,
+ .interface = dev_read_phy_mode,
.ops = &eqos_stm32_ops
};
.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
.axi_bus_width = EQOS_AXI_WIDTH_64,
- .interface = eqos_get_interface_imx,
+ .interface = dev_read_phy_mode,
.ops = &eqos_imx_ops
};
/* search "reset-gpios" in phy node */
ret = gpio_request_by_name(dev, "reset-gpios", 0,
&uc_priv->reset_gpio,
- GPIOD_IS_OUT);
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
if (ret && ret != -ENOENT)
return ret;
mask = 1 << CONFIG_PHY_ADDR;
#endif
- phydev = phy_find_by_mask(priv->bus, mask, PHY_INTERFACE_MODE_MII);
+ phydev = phy_find_by_mask(priv->bus, mask);
if (!phydev)
return -ENODEV;
- phy_connect_dev(phydev, dev);
+ phy_connect_dev(phydev, dev, PHY_INTERFACE_MODE_MII);
phydev->supported &= PHY_BASIC_FEATURES;
phydev->advertising = phydev->supported;
int ret = 0;
struct eth_pdata *pdata = dev_get_plat(dev);
struct fec_priv *priv = dev_get_priv(dev);
- const char *phy_mode;
pdata->iobase = dev_read_addr(dev);
priv->eth = (struct ethernet_regs *)pdata->iobase;
- pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
- NULL);
- if (phy_mode)
- pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- }
#ifdef CONFIG_DM_REGULATOR
device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
#if CONFIG_IS_ENABLED(DM_GPIO)
ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
- &priv->phy_reset_gpio, GPIOD_IS_OUT);
+ &priv->phy_reset_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
if (ret < 0)
return 0; /* property is optional, don't return error! */
#endif
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
/*B4860 has two 10Gig Mac*/
if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
(port == FM1_DTSEC2) ||
(port == FM1_DTSEC3) ||
(port == FM1_DTSEC4))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
}
}
return PHY_INTERFACE_MODE_SGMII;
break;
default:
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
return 0;
}
#else /* CONFIG_DM_ETH */
-#ifdef CONFIG_PHYLIB
-phy_interface_t fman_read_sys_if(struct udevice *dev)
-{
- const char *if_str;
-
- if_str = ofnode_read_string(dev_ofnode(dev), "phy-connection-type");
- debug("MAC system interface mode %s\n", if_str);
-
- return phy_get_interface_by_name(if_str);
-}
-#endif
static int fm_eth_bind(struct udevice *dev)
{
reg = (void *)(uintptr_t)dev_read_addr(dev);
fm_eth->mac_type = dev_get_driver_data(dev);
#ifdef CONFIG_PHYLIB
- fm_eth->enet_if = fman_read_sys_if(dev);
+ fm_eth->enet_if = dev_read_phy_mode(dev);
#else
fm_eth->enet_if = PHY_INTERFACE_MODE_SGMII;
printf("%s: warning - unable to determine interface type\n", __func__);
/*
* Determine if an interface is actually active based on HW config
- * we expect fman_port_enet_if() to report PHY_INTERFACE_MODE_NONE if
+ * we expect fman_port_enet_if() to report PHY_INTERFACE_MODE_NA if
* the interface is not active based on HW cfg of the SoC
*/
void fman_enet_init(void)
phy_interface_t enet_if;
enet_if = fman_port_enet_if(fm_info[i].port);
- if (enet_if != PHY_INTERFACE_MODE_NONE) {
+ if (enet_if != PHY_INTERFACE_MODE_NA) {
fm_info[i].enabled = 1;
fm_info[i].enet_if = enet_if;
} else {
int i = fm_port_to_index(port);
if (i == -1)
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if (fm_info[i].enabled)
return fm_info[i].enet_if;
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
static void
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if (port == FM1_DTSEC3)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
break;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC2) && (is_serdes_configured(XFI_FM1_MAC10)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM1_DTSEC10) && (is_serdes_configured(XFI_FM1_MAC10)))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if (port == FM1_DTSEC3)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
break;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
u32 pordevsr = in_be32(&gur->pordevsr);
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
/* DTSEC1 can be SGMII, RGMII or RMII */
if (port == FM1_DTSEC1) {
return PHY_INTERFACE_MODE_RGMII;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
return PHY_INTERFACE_MODE_XGMII;
return PHY_INTERFACE_MODE_SGMII;
break;
default:
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
return PHY_INTERFACE_MODE_XGMII;
return PHY_INTERFACE_MODE_SGMII;
break;
default:
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
return PHY_INTERFACE_MODE_XGMII;
return PHY_INTERFACE_MODE_SGMII;
break;
default:
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1)))
return PHY_INTERFACE_MODE_XGMII;
break;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
return PHY_INTERFACE_MODE_SGMII;
break;
default:
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
((is_serdes_configured(XAUI_FM1_MAC9)) ||
return PHY_INTERFACE_MODE_SGMII;
break;
default:
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
((is_serdes_configured(XAUI_FM1_MAC9)) ||
if ((port == FM1_DTSEC9 || port == FM1_DTSEC10) &&
((is_serdes_configured(XFI_FM1_MAC9)) ||
(is_serdes_configured(XFI_FM1_MAC10))))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM2_10GEC1 || port == FM2_10GEC2) &&
((is_serdes_configured(XAUI_FM2_MAC9)) ||
break;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
static void enetc_start_pcs(struct udevice *dev)
{
struct enetc_priv *priv = dev_get_priv(dev);
- const char *if_str;
-
- priv->if_type = PHY_INTERFACE_MODE_NONE;
/* register internal MDIO for debug purposes */
if (enetc_read_port(priv, ENETC_PCAPR0) & ENETC_PCAPRO_MDIO) {
return;
}
- if_str = ofnode_read_string(dev_ofnode(dev), "phy-mode");
- if (if_str)
- priv->if_type = phy_get_interface_by_name(if_str);
- else
+ priv->if_type = dev_read_phy_mode(dev);
+ if (priv->if_type == PHY_INTERFACE_MODE_NA) {
enetc_dbg(dev,
"phy-mode property not found, defaulting to SGMII\n");
- if (priv->if_type < 0)
- priv->if_type = PHY_INTERFACE_MODE_NONE;
+ priv->if_type = PHY_INTERFACE_MODE_SGMII;
+ }
switch (priv->if_type) {
case PHY_INTERFACE_MODE_SGMII:
{
struct eth_pdata *pdata = dev_get_plat(dev);
struct ftgmac100_data *priv = dev_get_priv(dev);
- const char *phy_mode;
pdata->iobase = dev_read_addr(dev);
- pdata->phy_interface = -1;
- phy_mode = dev_read_string(dev, "phy-mode");
- if (phy_mode)
- pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
+
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- }
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
static int higmac_of_to_plat(struct udevice *dev)
{
struct higmac_priv *priv = dev_get_priv(dev);
- int phyintf = PHY_INTERFACE_MODE_NONE;
- const char *phy_mode;
ofnode phy_node;
priv->base = dev_remap_addr_index(dev, 0);
priv->macif_ctrl = dev_remap_addr_index(dev, 1);
- phy_mode = dev_read_string(dev, "phy-mode");
- if (phy_mode)
- phyintf = phy_get_interface_by_name(phy_mode);
- if (phyintf == PHY_INTERFACE_MODE_NONE)
+ priv->phyintf = dev_read_phy_mode(dev);
+ if (priv->phyintf == PHY_INTERFACE_MODE_NA)
return -ENODEV;
- priv->phyintf = phyintf;
phy_node = dev_read_subnode(dev, "phy");
if (!ofnode_valid(phy_node)) {
return fdtdec_get_uint(gd->fdt_blob, port_node, "reg", -1);
}
-static const char *ldpaa_eth_get_phy_mode_str(struct udevice *dev)
-{
- int port_node = dev_of_offset(dev);
- const char *phy_mode_str;
-
- phy_mode_str = fdt_getprop(gd->fdt_blob, port_node,
- "phy-connection-type", NULL);
- if (phy_mode_str)
- return phy_mode_str;
-
- phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
- return phy_mode_str;
-}
-
static int ldpaa_eth_bind(struct udevice *dev)
{
- const char *phy_mode_str = NULL;
uint32_t dpmac_id;
char eth_name[16];
int phy_mode = -1;
- phy_mode_str = ldpaa_eth_get_phy_mode_str(dev);
- if (phy_mode_str)
- phy_mode = phy_get_interface_by_name(phy_mode_str);
- if (phy_mode == -1) {
+ phy_mode = dev_read_phy_mode(dev);
+ if (phy_mode == PHY_INTERFACE_MODE_NA) {
dev_err(dev, "incorrect phy mode\n");
return -EINVAL;
}
return -EINVAL;
}
- sprintf(eth_name, "DPMAC%d@%s", dpmac_id, phy_mode_str);
+ sprintf(eth_name, "DPMAC%d@%s", dpmac_id,
+ phy_string_for_interface(phy_mode));
device_set_name(dev, eth_name);
return 0;
static int ldpaa_eth_of_to_plat(struct udevice *dev)
{
struct ldpaa_eth_priv *priv = dev_get_priv(dev);
- const char *phy_mode_str;
priv->dpmac_id = ldpaa_eth_get_dpmac_id(dev);
- phy_mode_str = ldpaa_eth_get_phy_mode_str(dev);
- priv->phy_mode = phy_get_interface_by_name(phy_mode_str);
+ priv->phy_mode = dev_read_phy_mode(dev);
return 0;
}
__weak phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtc)
{
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl)
dpmac_info[dpmac_id].enabled = 0;
dpmac_info[dpmac_id].id = 0;
- dpmac_info[dpmac_id].enet_if = PHY_INTERFACE_MODE_NONE;
+ dpmac_info[dpmac_id].enet_if = PHY_INTERFACE_MODE_NA;
enet_if = wriop_dpmac_enet_if(dpmac_id, lane_prtcl);
- if (enet_if != PHY_INTERFACE_MODE_NONE) {
+ if (enet_if != PHY_INTERFACE_MODE_NA) {
dpmac_info[dpmac_id].enabled = 1;
dpmac_info[dpmac_id].id = dpmac_id;
dpmac_info[dpmac_id].enet_if = enet_if;
int i = wriop_dpmac_to_index(dpmac_id);
if (i == -1)
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if (dpmac_info[i].enabled)
return dpmac_info[i].enet_if;
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
enum srds_prtcl;
if (is_device_disabled(dpmac_id + 1))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
switch (lane_prtcl) {
case SGMII1:
if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_B)
return PHY_INTERFACE_MODE_QSGMII;
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
enum srds_prtcl;
if (is_device_disabled(dpmac_id + 1))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII16)
return PHY_INTERFACE_MODE_SGMII;
if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_D)
return PHY_INTERFACE_MODE_QSGMII;
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
enum srds_prtcl;
if (is_device_disabled(dpmac_id))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
return PHY_INTERFACE_MODE_SGMII;
if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
return PHY_INTERFACE_MODE_CAUI4;
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
#ifdef CONFIG_SYS_FSL_HAS_RGMII
struct eth_pdata *pdata = dev_get_plat(dev);
struct macb_device *macb = dev_get_priv(dev);
struct ofnode_phandle_args phandle_args;
- const char *phy_mode;
int ret;
- phy_mode = dev_read_prop(dev, "phy-mode", NULL);
-
- if (phy_mode)
- macb->phy_interface = phy_get_interface_by_name(phy_mode);
- if (macb->phy_interface == -1) {
- debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ macb->phy_interface = dev_read_phy_mode(dev);
+ if (macb->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- }
/* Read phyaddr from DT */
if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
static int mdio_mux_sandbox_mark_selection(struct udevice *dev, int sel)
{
struct udevice *mdio;
- struct mdio_ops *ops;
int err;
/*
err = uclass_get_device_by_name(UCLASS_MDIO, "mdio-test", &mdio);
if (err)
return err;
- ops = mdio_get_ops(mdio);
- return ops->write(mdio, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
- SANDBOX_PHY_REG_CNT - 1, (u16)sel);
+ return dm_mdio_write(mdio, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
+ SANDBOX_PHY_REG_CNT - 1, (u16)sel);
}
static int mdio_mux_sandbox_select(struct udevice *dev, int cur, int sel)
phy = phy_connect(priv->ports[i].bus,
priv->ports[i].phy_addr, dev,
- PHY_INTERFACE_MODE_NONE);
+ PHY_INTERFACE_MODE_NA);
if (phy)
board_phy_config(phy);
}
phy = phy_connect(priv->ports[i].bus,
priv->ports[i].phy_addr, dev,
- PHY_INTERFACE_MODE_NONE);
+ PHY_INTERFACE_MODE_NA);
if (phy && i >= MAX_INT_PORT)
board_phy_config(phy);
}
phy = phy_connect(priv->ports[i].bus,
priv->ports[i].phy_addr, dev,
- PHY_INTERFACE_MODE_NONE);
+ PHY_INTERFACE_MODE_NA);
if (phy && external_bus(priv, i))
board_phy_config(phy);
}
phy = phy_connect(priv->ports[i].bus,
priv->ports[i].phy_addr, dev,
- PHY_INTERFACE_MODE_NONE);
+ PHY_INTERFACE_MODE_NA);
if (phy)
board_phy_config(phy);
}
continue;
phy_connect(priv->ports[i].bus, priv->ports[i].phy_addr, dev,
- PHY_INTERFACE_MODE_NONE);
+ PHY_INTERFACE_MODE_NA);
}
return 0;
case PHY_INTERFACE_MODE_RGMII:
ge_mode = MT7620_SYSC_GE_RGMII;
break;
- case PHY_INTERFACE_MODE_NONE:
+ case PHY_INTERFACE_MODE_NA:
if (gmac == 2)
ge_mode = MT7620_SYSC_GE_ESW_PHY;
else
{
u32 pmcr;
- if (port_cfg->mode == PHY_INTERFACE_MODE_NONE) {
+ if (port_cfg->mode == PHY_INTERFACE_MODE_NA) {
if (port == 5) {
gsw_write(priv, GSW_PMCR(port), FORCE_MODE);
return;
{
int phy_addr_st, phy_addr_end;
- if (priv->port_cfg[0].mode == PHY_INTERFACE_MODE_NONE)
+ if (priv->port_cfg[0].mode == PHY_INTERFACE_MODE_NA)
priv->ephy_num = NUM_FE_PHYS;
else
priv->ephy_num = NUM_FE_PHYS - 1;
ofnode node)
{
ofnode subnode;
- const char *str;
- int mode, speed, ret;
+ int speed, ret;
u32 phy_addr;
- str = ofnode_read_string(node, "phy-mode");
- if (str) {
- mode = phy_get_interface_by_name(str);
- if (mode < 0) {
- dev_err(priv->dev, "mt7620_eth: invalid phy-mode\n");
- return -EINVAL;
- }
-
- switch (mode) {
- case PHY_INTERFACE_MODE_MII:
- case PHY_INTERFACE_MODE_RMII:
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_NONE:
- break;
- default:
- dev_err(priv->dev,
- "mt7620_eth: unsupported phy-mode\n");
- return -ENOTSUPP;
- }
+ priv->port_cfg[idx].mode = ofnode_read_phy_mode(node);
- priv->port_cfg[idx].mode = mode;
- } else {
- priv->port_cfg[idx].mode = PHY_INTERFACE_MODE_NONE;
+ switch (priv->port_cfg[idx].mode) {
+ case PHY_INTERFACE_MODE_MII:
+ case PHY_INTERFACE_MODE_RMII:
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_NA:
+ break;
+ default:
+ dev_err(priv->dev, "mt7620_eth: unsupported phy-mode\n");
+ return -ENOTSUPP;
}
subnode = ofnode_find_subnode(node, "fixed-link");
if (ret)
return ret;
} else {
- priv->port_cfg[0].mode = PHY_INTERFACE_MODE_NONE;
+ priv->port_cfg[0].mode = PHY_INTERFACE_MODE_NA;
}
subnode = ofnode_find_subnode(dev_ofnode(dev), "port5");
if (ofnode_valid(subnode))
return mt7620_eth_parse_gsw_port(priv, 1, subnode);
- priv->port_cfg[1].mode = PHY_INTERFACE_MODE_NONE;
+ priv->port_cfg[1].mode = PHY_INTERFACE_MODE_NA;
return 0;
}
priv->gmac_id = dev_read_u32_default(dev, "mediatek,gmac-id", 0);
/* Interface mode is required */
- str = dev_read_string(dev, "phy-mode");
- if (str) {
- pdata->phy_interface = phy_get_interface_by_name(str);
- priv->phy_interface = pdata->phy_interface;
- } else {
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ priv->phy_interface = pdata->phy_interface;
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) {
printf("error: phy-mode is not set\n");
return -EINVAL;
}
struct mvgbe_device *dmvgbe = dev_get_priv(dev);
void *blob = (void *)gd->fdt_blob;
int node = dev_of_offset(dev);
- const char *phy_mode;
int fl_node;
int pnode;
unsigned long addr;
"marvell,kirkwood-eth-port");
/* Get phy-mode / phy_interface from DT */
- phy_mode = fdt_getprop(gd->fdt_blob, pnode, "phy-mode", NULL);
- if (phy_mode)
- pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- else
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
pdata->phy_interface = PHY_INTERFACE_MODE_GMII;
dmvgbe->phy_interface = pdata->phy_interface;
static int mvneta_of_to_plat(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
- const char *phy_mode;
pdata->iobase = dev_read_addr(dev);
/* Get phy-mode / phy_interface from DT */
- pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
- NULL);
- if (phy_mode)
- pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- }
return 0;
}
static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
{
int port_node = dev_of_offset(dev);
- const char *phy_mode_str;
int phy_node;
u32 id;
u32 phyaddr = 0;
- int phy_mode = -1;
int fixed_link = 0;
int ret;
phyaddr = PHY_MAX_ADDR;
}
- phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
- if (phy_mode_str)
- phy_mode = phy_get_interface_by_name(phy_mode_str);
- if (phy_mode == -1) {
+ port->phy_interface = dev_read_phy_mode(dev);
+ if (port->phy_interface == PHY_INTERFACE_MODE_NA) {
dev_err(dev, "incorrect phy mode\n");
return -EINVAL;
}
port->first_rxq = port->id * rxq_number;
else
port->first_rxq = port->id * port->priv->max_port_rxqs;
- port->phy_interface = phy_mode;
port->phyaddr = phyaddr;
return 0;
struct phy_device *phydev;
int mask = 0xffffffff;
- phydev = phy_find_by_mask(priv->bus, mask, plat->phy_interface);
+ phydev = phy_find_by_mask(priv->bus, mask);
if (!phydev) {
printf("pch_gbe: cannot find the phy\n");
return -1;
}
- phy_connect_dev(phydev, dev);
+ phy_connect_dev(phydev, dev, plat->phy_interface);
phydev->supported &= PHY_GBIT_FEATURES;
phydev->advertising = phydev->supported;
config PHYLIB_10G
bool "Generic 10G PHY support"
+config PHY_ADIN
+ bool "Analog Devices Industrial Ethernet PHYs"
+ help
+ Add support for configuring RGMII on Analog Devices ADIN PHYs.
+
menuconfig PHY_AQUANTIA
bool "Aquantia Ethernet PHYs support"
select PHY_GIGE
obj-$(CONFIG_PHYLIB) += phy.o
obj-$(CONFIG_PHYLIB_10G) += generic_10g.o
+obj-$(CONFIG_PHY_ADIN) += adin.o
obj-$(CONFIG_PHY_AQUANTIA) += aquantia.o
obj-$(CONFIG_PHY_ATHEROS) += atheros.o
obj-$(CONFIG_PHY_BROADCOM) += broadcom.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/**
+ * Driver for Analog Devices Industrial Ethernet PHYs
+ *
+ * Copyright 2019 Analog Devices Inc.
+ * Copyright 2022 Variscite Ltd.
+ */
+#include <common.h>
+#include <phy.h>
+#include <linux/bitops.h>
+#include <linux/bitfield.h>
+
+#define PHY_ID_ADIN1300 0x0283bc30
+#define ADIN1300_EXT_REG_PTR 0x10
+#define ADIN1300_EXT_REG_DATA 0x11
+#define ADIN1300_GE_RGMII_CFG 0xff23
+#define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6)
+#define ADIN1300_GE_RGMII_RX_SEL(x) \
+ FIELD_PREP(ADIN1300_GE_RGMII_RX_MSK, x)
+#define ADIN1300_GE_RGMII_GTX_MSK GENMASK(5, 3)
+#define ADIN1300_GE_RGMII_GTX_SEL(x) \
+ FIELD_PREP(ADIN1300_GE_RGMII_GTX_MSK, x)
+#define ADIN1300_GE_RGMII_RXID_EN BIT(2)
+#define ADIN1300_GE_RGMII_TXID_EN BIT(1)
+#define ADIN1300_GE_RGMII_EN BIT(0)
+
+/* RGMII internal delay settings for rx and tx for ADIN1300 */
+#define ADIN1300_RGMII_1_60_NS 0x0001
+#define ADIN1300_RGMII_1_80_NS 0x0002
+#define ADIN1300_RGMII_2_00_NS 0x0000
+#define ADIN1300_RGMII_2_20_NS 0x0006
+#define ADIN1300_RGMII_2_40_NS 0x0007
+
+/**
+ * struct adin_cfg_reg_map - map a config value to aregister value
+ * @cfg value in device configuration
+ * @reg value in the register
+ */
+struct adin_cfg_reg_map {
+ int cfg;
+ int reg;
+};
+
+static const struct adin_cfg_reg_map adin_rgmii_delays[] = {
+ { 1600, ADIN1300_RGMII_1_60_NS },
+ { 1800, ADIN1300_RGMII_1_80_NS },
+ { 2000, ADIN1300_RGMII_2_00_NS },
+ { 2200, ADIN1300_RGMII_2_20_NS },
+ { 2400, ADIN1300_RGMII_2_40_NS },
+ { },
+};
+
+static int adin_lookup_reg_value(const struct adin_cfg_reg_map *tbl, int cfg)
+{
+ size_t i;
+
+ for (i = 0; tbl[i].cfg; i++) {
+ if (tbl[i].cfg == cfg)
+ return tbl[i].reg;
+ }
+
+ return -EINVAL;
+}
+
+static u32 adin_get_reg_value(struct phy_device *phydev,
+ const char *prop_name,
+ const struct adin_cfg_reg_map *tbl,
+ u32 dflt)
+{
+ u32 val;
+ int rc;
+
+ ofnode node = phy_get_ofnode(phydev);
+ if (!ofnode_valid(node)) {
+ printf("%s: failed to get node\n", __func__);
+ return -EINVAL;
+ }
+
+ if (ofnode_read_u32(node, prop_name, &val)) {
+ printf("%s: failed to find %s, using default %d\n",
+ __func__, prop_name, dflt);
+ return dflt;
+ }
+
+ debug("%s: %s = '%d'\n", __func__, prop_name, val);
+
+ rc = adin_lookup_reg_value(tbl, val);
+ if (rc < 0) {
+ printf("%s: Unsupported value %u for %s using default (%u)\n",
+ __func__, val, prop_name, dflt);
+ return dflt;
+ }
+
+ return rc;
+}
+
+/**
+ * adin_get_phy_mode_override - Get phy-mode override for adin PHY
+ *
+ * The function gets phy-mode string from property 'adi,phy-mode-override'
+ * and return its index in phy_interface_strings table, or -1 in error case.
+ */
+int adin_get_phy_mode_override(struct phy_device *phydev)
+{
+ ofnode node = phy_get_ofnode(phydev);
+ const char *phy_mode_override;
+ const char *prop_phy_mode_override = "adi,phy-mode-override";
+ int override_interface;
+
+ phy_mode_override = ofnode_read_string(node, prop_phy_mode_override);
+ if (!phy_mode_override)
+ return -ENODEV;
+
+ debug("%s: %s = '%s'\n",
+ __func__, prop_phy_mode_override, phy_mode_override);
+
+ override_interface = phy_get_interface_by_name(phy_mode_override);
+
+ if (override_interface < 0)
+ printf("%s: %s = '%s' is not valid\n",
+ __func__, prop_phy_mode_override, phy_mode_override);
+
+ return override_interface;
+}
+
+static u16 adin_ext_read(struct phy_device *phydev, const u32 regnum)
+{
+ u16 val;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, ADIN1300_EXT_REG_PTR, regnum);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, ADIN1300_EXT_REG_DATA);
+
+ debug("%s: adin@0x%x 0x%x=0x%x\n", __func__, phydev->addr, regnum, val);
+
+ return val;
+}
+
+static int adin_ext_write(struct phy_device *phydev, const u32 regnum, const u16 val)
+{
+ debug("%s: adin@0x%x 0x%x=0x%x\n", __func__, phydev->addr, regnum, val);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, ADIN1300_EXT_REG_PTR, regnum);
+
+ return phy_write(phydev, MDIO_DEVAD_NONE, ADIN1300_EXT_REG_DATA, val);
+}
+
+static int adin_config_rgmii_mode(struct phy_device *phydev)
+{
+ u16 reg_val;
+ u32 val;
+ int phy_mode_override = adin_get_phy_mode_override(phydev);
+
+ if (phy_mode_override >= 0) {
+ phydev->interface = (phy_interface_t) phy_mode_override;
+ }
+
+ reg_val = adin_ext_read(phydev, ADIN1300_GE_RGMII_CFG);
+
+ if (!phy_interface_is_rgmii(phydev)) {
+ /* Disable RGMII */
+ reg_val &= ~ADIN1300_GE_RGMII_EN;
+ return adin_ext_write(phydev, ADIN1300_GE_RGMII_CFG, reg_val);
+ }
+
+ /* Enable RGMII */
+ reg_val |= ADIN1300_GE_RGMII_EN;
+
+ /* Enable / Disable RGMII RX Delay */
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
+ reg_val |= ADIN1300_GE_RGMII_RXID_EN;
+
+ val = adin_get_reg_value(phydev, "adi,rx-internal-delay-ps",
+ adin_rgmii_delays,
+ ADIN1300_RGMII_2_00_NS);
+ reg_val &= ~ADIN1300_GE_RGMII_RX_MSK;
+ reg_val |= ADIN1300_GE_RGMII_RX_SEL(val);
+ } else {
+ reg_val &= ~ADIN1300_GE_RGMII_RXID_EN;
+ }
+
+ /* Enable / Disable RGMII RX Delay */
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
+ reg_val |= ADIN1300_GE_RGMII_TXID_EN;
+
+ val = adin_get_reg_value(phydev, "adi,tx-internal-delay-ps",
+ adin_rgmii_delays,
+ ADIN1300_RGMII_2_00_NS);
+ reg_val &= ~ADIN1300_GE_RGMII_GTX_MSK;
+ reg_val |= ADIN1300_GE_RGMII_GTX_SEL(val);
+ } else {
+ reg_val &= ~ADIN1300_GE_RGMII_TXID_EN;
+ }
+
+ return adin_ext_write(phydev, ADIN1300_GE_RGMII_CFG, reg_val);
+}
+
+static int adin1300_config(struct phy_device *phydev)
+{
+ int ret;
+
+ printf("ADIN1300 PHY detected at addr %d\n", phydev->addr);
+
+ ret = adin_config_rgmii_mode(phydev);
+
+ if (ret < 0)
+ return ret;
+
+ return genphy_config(phydev);
+}
+
+static struct phy_driver ADIN1300_driver = {
+ .name = "ADIN1300",
+ .uid = PHY_ID_ADIN1300,
+ .mask = 0xffffffff,
+ .features = PHY_GBIT_FEATURES,
+ .config = adin1300_config,
+ .startup = genphy_startup,
+ .shutdown = genphy_shutdown,
+};
+
+int phy_adin_init(void)
+{
+ phy_register(&ADIN1300_driver);
+
+ return 0;
+}
u16 syscfg;
int cnt;
u16 start_rate;
-} aquantia_syscfg[PHY_INTERFACE_MODE_COUNT] = {
+} aquantia_syscfg[PHY_INTERFACE_MODE_MAX] = {
[PHY_INTERFACE_MODE_SGMII] = {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
AQUANTIA_VND1_GSTART_RATE_1G},
[PHY_INTERFACE_MODE_2500BASEX] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
node = phy_get_ofnode(phydev);
if (!ofnode_valid(node))
- return -EINVAL;
+ return 0;
priv = malloc(sizeof(*priv));
if (!priv)
node = phy_get_ofnode(phydev);
if (!ofnode_valid(node))
- return -EINVAL;
+ return 0;
/* Optional configuration */
ret = ofnode_read_u32(node, "ti,clk-output-sel",
static int dp83867_config(struct phy_device *phydev)
{
struct dp83867_private *dp83867;
- unsigned int val, delay, cfg2;
+ int val, delay, cfg2;
int ret, bs;
dp83867 = (struct dp83867_private *)phydev->priv;
if (phy_interface_is_rgmii(phydev)) {
val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
- if (val < 0)
+ if (val < 0) {
+ ret = val;
goto err_out;
+ }
+
val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
#include <asm/gpio.h>
struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev,
- int phyaddr, phy_interface_t interface)
+ int phyaddr)
{
struct phy_device *phydev;
struct ofnode_phandle_args phandle_args;
}
id = vendor << 16 | device;
- phydev = phy_device_create(bus, phyaddr, id, false, interface);
+ phydev = phy_device_create(bus, phyaddr, id, false);
if (phydev)
phydev->node = node;
#ifdef CONFIG_MV88E61XX_SWITCH
phy_mv88e61xx_init();
#endif
+#ifdef CONFIG_PHY_ADIN
+ phy_adin_init();
+#endif
#ifdef CONFIG_PHY_AQUANTIA
phy_aquantia_init();
#endif
return err;
}
-static struct phy_driver *generic_for_interface(phy_interface_t interface)
+static struct phy_driver *generic_for_phy(struct phy_device *phydev)
{
#ifdef CONFIG_PHYLIB_10G
- if (is_10g_interface(interface))
+ if (phydev->is_c45)
return &gen10g_driver;
#endif
return &genphy_driver;
}
-static struct phy_driver *get_phy_driver(struct phy_device *phydev,
- phy_interface_t interface)
+static struct phy_driver *get_phy_driver(struct phy_device *phydev)
{
struct list_head *entry;
int phy_id = phydev->phy_id;
}
/* If we made it here, there's no driver for this PHY */
- return generic_for_interface(interface);
+ return generic_for_phy(phydev);
}
struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
- u32 phy_id, bool is_c45,
- phy_interface_t interface)
+ u32 phy_id, bool is_c45)
{
struct phy_device *dev;
dev->duplex = -1;
dev->link = 0;
- dev->interface = interface;
+ dev->interface = PHY_INTERFACE_MODE_NA;
#ifdef CONFIG_DM_ETH
dev->node = ofnode_null();
dev->is_c45 = is_c45;
dev->bus = bus;
- dev->drv = get_phy_driver(dev, interface);
+ dev->drv = get_phy_driver(dev);
if (phy_probe(dev)) {
printf("%s, PHY probe failed\n", __func__);
}
static struct phy_device *create_phy_by_mask(struct mii_dev *bus,
- uint phy_mask, int devad,
- phy_interface_t interface)
+ uint phy_mask, int devad)
{
u32 phy_id = 0xffffffff;
bool is_c45;
/* If the PHY ID is mostly f's, we didn't find anything */
if (r == 0 && (phy_id & 0x1fffffff) != 0x1fffffff) {
is_c45 = (devad == MDIO_DEVAD_NONE) ? false : true;
- return phy_device_create(bus, addr, phy_id, is_c45,
- interface);
+ return phy_device_create(bus, addr, phy_id, is_c45);
}
next:
phy_mask &= ~(1 << addr);
}
static struct phy_device *search_for_existing_phy(struct mii_dev *bus,
- uint phy_mask,
- phy_interface_t interface)
+ uint phy_mask)
{
/* If we have one, return the existing device, with new interface */
while (phy_mask) {
int addr = ffs(phy_mask) - 1;
- if (bus->phymap[addr]) {
- bus->phymap[addr]->interface = interface;
+ if (bus->phymap[addr])
return bus->phymap[addr];
- }
+
phy_mask &= ~(1 << addr);
}
return NULL;
}
static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus,
- uint phy_mask,
- phy_interface_t interface)
+ uint phy_mask)
{
struct phy_device *phydev;
int devad[] = {
int i, devad_cnt;
devad_cnt = sizeof(devad)/sizeof(int);
- phydev = search_for_existing_phy(bus, phy_mask, interface);
+ phydev = search_for_existing_phy(bus, phy_mask);
if (phydev)
return phydev;
/* try different access clauses */
for (i = 0; i < devad_cnt; i++) {
- phydev = create_phy_by_mask(bus, phy_mask,
- devad[i], interface);
+ phydev = create_phy_by_mask(bus, phy_mask, devad[i]);
if (IS_ERR(phydev))
return NULL;
if (phydev)
* Description: Reads the ID registers of the PHY at @addr on the
* @bus, then allocates and returns the phy_device to represent it.
*/
-static struct phy_device *get_phy_device(struct mii_dev *bus, int addr,
- phy_interface_t interface)
+static struct phy_device *get_phy_device(struct mii_dev *bus, int addr)
{
- return get_phy_device_by_mask(bus, 1 << addr, interface);
+ return get_phy_device_by_mask(bus, 1 << addr);
}
int phy_reset(struct phy_device *phydev)
#ifdef CONFIG_PHYLIB_10G
/* If it's 10G, we need to issue reset through one of the MMDs */
- if (is_10g_interface(phydev->interface)) {
+ if (phydev->is_c45) {
if (!phydev->mmds)
gen10g_discover_mmds(phydev);
struct mii_dev *bus = miiphy_get_dev_by_name(devname);
struct phy_device *phydev;
- /*
- * miiphy_reset was only used on standard PHYs, so we'll fake it here.
- * If later code tries to connect with the right interface, this will
- * be corrected by get_phy_device in phy_connect()
- */
- phydev = get_phy_device(bus, addr, PHY_INTERFACE_MODE_MII);
+ phydev = get_phy_device(bus, addr);
return phy_reset(phydev);
}
-struct phy_device *phy_find_by_mask(struct mii_dev *bus, uint phy_mask,
- phy_interface_t interface)
+struct phy_device *phy_find_by_mask(struct mii_dev *bus, uint phy_mask)
{
/* Reset the bus */
if (bus->reset) {
mdelay(15);
}
- return get_phy_device_by_mask(bus, phy_mask, interface);
+ return get_phy_device_by_mask(bus, phy_mask);
}
#ifdef CONFIG_DM_ETH
-void phy_connect_dev(struct phy_device *phydev, struct udevice *dev)
+void phy_connect_dev(struct phy_device *phydev, struct udevice *dev,
+ phy_interface_t interface)
#else
-void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev)
+void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev,
+ phy_interface_t interface)
#endif
{
/* Soft Reset the PHY */
phydev->dev->name, dev->name);
}
phydev->dev = dev;
- debug("%s connected to %s\n", dev->name, phydev->drv->name);
+ phydev->interface = interface;
+ debug("%s connected to %s mode %s\n", dev->name, phydev->drv->name,
+ phy_string_for_interface(interface));
}
#ifdef CONFIG_PHY_XILINX_GMII2RGMII
static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
- struct udevice *dev,
- phy_interface_t interface)
+ struct udevice *dev)
{
struct phy_device *phydev = NULL;
ofnode node;
node = ofnode_by_compatible(node, "xlnx,gmii-to-rgmii-1.0");
if (ofnode_valid(node)) {
phydev = phy_device_create(bus, 0,
- PHY_GMII2RGMII_ID, false,
- interface);
+ PHY_GMII2RGMII_ID, false);
if (phydev)
phydev->node = node;
break;
*/
struct phy_device *fixed_phy_create(ofnode node)
{
- phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
struct phy_device *phydev;
- const char *if_str;
ofnode subnode;
- if_str = ofnode_read_string(node, "phy-mode");
- if (!if_str) {
- if_str = ofnode_read_string(node, "phy-interface-type");
- }
- if (if_str) {
- interface = phy_get_interface_by_name(if_str);
- }
-
subnode = ofnode_find_subnode(node, "fixed-link");
if (!ofnode_valid(subnode)) {
return NULL;
}
- phydev = phy_device_create(NULL, 0, PHY_FIXED_ID, false, interface);
+ phydev = phy_device_create(NULL, 0, PHY_FIXED_ID, false);
if (phydev)
phydev->node = subnode;
+ phydev->interface = ofnode_read_phy_mode(node);
+
return phydev;
}
static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
- struct udevice *dev,
- phy_interface_t interface)
+ struct udevice *dev)
{
ofnode node = dev_ofnode(dev), subnode;
struct phy_device *phydev = NULL;
if (ofnode_phy_is_fixed_link(node, &subnode)) {
- phydev = phy_device_create(bus, 0, PHY_FIXED_ID,
- false, interface);
+ phydev = phy_device_create(bus, 0, PHY_FIXED_ID, false);
if (phydev)
phydev->node = subnode;
}
uint mask = (addr >= 0) ? (1 << addr) : 0xffffffff;
#ifdef CONFIG_PHY_FIXED
- phydev = phy_connect_fixed(bus, dev, interface);
+ phydev = phy_connect_fixed(bus, dev);
#endif
#ifdef CONFIG_PHY_NCSI
if (!phydev)
- phydev = phy_device_create(bus, 0, PHY_NCSI_ID, false, interface);
+ phydev = phy_device_create(bus, 0, PHY_NCSI_ID, false);
#endif
#ifdef CONFIG_PHY_ETHERNET_ID
if (!phydev)
- phydev = phy_connect_phy_id(bus, dev, addr, interface);
+ phydev = phy_connect_phy_id(bus, dev, addr);
#endif
#ifdef CONFIG_PHY_XILINX_GMII2RGMII
if (!phydev)
- phydev = phy_connect_gmii2rgmii(bus, dev, interface);
+ phydev = phy_connect_gmii2rgmii(bus, dev);
#endif
if (!phydev)
- phydev = phy_find_by_mask(bus, mask, interface);
+ phydev = phy_find_by_mask(bus, mask);
if (phydev)
- phy_connect_dev(phydev, dev);
+ phy_connect_dev(phydev, dev, interface);
else
printf("Could not get PHY for %s: addr %d\n", bus->name, addr);
return phydev;
return 0;
}
-int phy_get_interface_by_name(const char *str)
-{
- int i;
-
- for (i = 0; i < PHY_INTERFACE_MODE_COUNT; i++) {
- if (!strcmp(str, phy_interface_strings[i]))
- return i;
- }
-
- return -1;
-}
-
/**
* phy_modify - Convenience function for modifying a given PHY register
* @phydev: the phy_device struct
debug("%s\n", __func__);
+ if (phydev->interface != PHY_INTERFACE_MODE_GMII) {
+ printf("Incorrect interface type\n");
+ return -EINVAL;
+ }
+
if (!ofnode_valid(node))
return -EINVAL;
ext_phyaddr = ofnode_read_u32_default(phandle.node, "reg", -1);
ext_phydev = phy_find_by_mask(phydev->bus,
- 1 << ext_phyaddr,
- PHY_INTERFACE_MODE_RGMII);
+ 1 << ext_phyaddr);
if (!ext_phydev) {
printf("%s, No external phy device found\n", __func__);
return -EINVAL;
}
+ ext_phydev->interface = PHY_INTERFACE_MODE_RGMII;
ext_phydev->node = phandle.node;
phydev->priv = ext_phydev;
{
debug("%s\n", __func__);
- if (phydev->interface != PHY_INTERFACE_MODE_GMII) {
- printf("Incorrect interface type\n");
- return -EINVAL;
- }
-
phydev->flags |= PHY_FLAG_BROKEN_RESET;
return 0;
{
struct eth_pdata *pdata = dev_get_plat(dev);
struct pic32eth_dev *priv = dev_get_priv(dev);
- const char *phy_mode;
void __iomem *iobase;
fdt_addr_t addr;
fdt_size_t size;
pdata->iobase = (phys_addr_t)addr;
/* get phy mode */
- pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
- NULL);
- if (phy_mode)
- pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- }
/* get phy addr */
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
static int qe_uec_of_to_plat(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
- const char *phy_mode;
pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
- pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
- "phy-connection-type", NULL);
- if (phy_mode)
- pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- }
return 0;
}
mdelay(1);
}
- phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
+ phydev = phy_find_by_mask(eth->bus, mask);
if (!phydev)
return -ENODEV;
- phy_connect_dev(phydev, dev);
+ phy_connect_dev(phydev, dev, pdata->phy_interface);
eth->phydev = phydev;
int ravb_of_to_plat(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
- const char *phy_mode;
const fdt32_t *cell;
- int ret = 0;
pdata->iobase = dev_read_addr(dev);
- pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
- NULL);
- if (phy_mode)
- pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- }
pdata->max_speed = 1000;
cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
sprintf(bb_miiphy_buses[0].name, dev->name);
- return ret;
+ return 0;
}
static const struct udevice_id ravb_ids[] = {
struct phy_device *phydev;
int mask = 0xffffffff;
- phydev = phy_find_by_mask(priv->bus, mask, pdata->phy_interface);
+ phydev = phy_find_by_mask(priv->bus, mask);
if (!phydev)
return -ENODEV;
- phy_connect_dev(phydev, dev);
+ phy_connect_dev(phydev, dev, pdata->phy_interface);
port_info->phydev = phydev;
phy_config(phydev);
int sh_ether_of_to_plat(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
- const char *phy_mode;
const fdt32_t *cell;
- int ret = 0;
pdata->iobase = dev_read_addr(dev);
- pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
- NULL);
- if (phy_mode)
- pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- }
pdata->max_speed = 1000;
cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
sprintf(bb_miiphy_buses[0].name, dev->name);
- return ret;
+ return 0;
}
static const struct udevice_id sh_ether_ids[] = {
struct phy_device *phydev;
int mask = GENMASK(31, 0), ret;
- phydev = phy_find_by_mask(priv->bus, mask, priv->phy_mode);
+ phydev = phy_find_by_mask(priv->bus, mask);
if (!phydev)
return -ENODEV;
- phy_connect_dev(phydev, dev);
+ phy_connect_dev(phydev, dev, priv->phy_mode);
phydev->supported &= PHY_GBIT_FEATURES;
if (priv->max_speed) {
struct eth_pdata *pdata = dev_get_plat(dev);
struct ave_private *priv = dev_get_priv(dev);
struct ofnode_phandle_args args;
- const char *phy_mode;
const u32 *valp;
int ret, nc, nr;
const char *name;
return -EINVAL;
pdata->iobase = dev_read_addr(dev);
- pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
- NULL);
- if (phy_mode)
- pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
+
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- }
pdata->max_speed = 0;
valp = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed",
struct eth_pdata *pdata = dev_get_plat(dev);
struct netsec_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args phandle_args;
- const char *phy_mode;
pdata->iobase = dev_read_addr_index(dev, 0);
priv->eeprom_base = dev_read_addr_index(dev, 1) - EERPROM_MAP_OFFSET;
- pdata->phy_interface = -1;
- phy_mode = dev_read_prop(dev, "phy-mode", NULL);
- if (phy_mode)
- pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- pr_err("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- }
if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
&phandle_args))
if (!phydev)
return -ENODEV;
- phy_connect_dev(phydev, dev);
-
priv->phydev = phydev;
phy_config(priv->phydev);
struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
struct emac_eth_dev *priv = dev_get_priv(dev);
- const char *phy_mode;
const fdt32_t *reg;
int node = dev_of_offset(dev);
int offset = 0;
}
priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
- phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
-
- if (phy_mode)
- pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+ pdata->phy_interface = dev_read_phy_mode(dev);
printf("phy interface%d\n", pdata->phy_interface);
-
- if (pdata->phy_interface == -1) {
- debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- }
if (priv->variant == H3_EMAC) {
ret = sun8i_handle_internal_phy(dev, priv);
if (ret)
return ret;
- priv->phydev = phy_find_by_mask(priv->bus, mask,
- PHY_INTERFACE_MODE_MII);
+ priv->phydev = phy_find_by_mask(priv->bus, mask);
if (!priv->phydev)
return -ENODEV;
- phy_connect_dev(priv->phydev, dev);
+ phy_connect_dev(priv->phydev, dev, PHY_INTERFACE_MODE_MII);
phy_config(priv->phydev);
return 0;
struct eth_pdata *pdata = dev_get_plat(dev);
struct am65_cpsw_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args out_args;
- const char *phy_mode;
int ret = 0;
dev_read_u32(dev, "reg", &priv->port_id);
- phy_mode = dev_read_string(dev, "phy-mode");
- if (phy_mode) {
- pdata->phy_interface =
- phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- dev_err(dev, "Invalid PHY mode '%s', port %u\n",
- phy_mode, priv->port_id);
- ret = -EINVAL;
- goto out;
- }
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) {
+ dev_err(dev, "Invalid PHY mode, port %u\n", priv->port_id);
+ return -EINVAL;
}
dev_read_u32(dev, "max-speed", (u32 *)&pdata->max_speed);
{
struct ofnode_phandle_args out_args;
struct cpsw_slave_data *slave_data;
- const char *phy_mode;
u32 phy_id[2];
int ret;
slave_data = &data->slave_data[slave_index];
- phy_mode = ofnode_read_string(subnode, "phy-mode");
- if (phy_mode)
- slave_data->phy_if = phy_get_interface_by_name(phy_mode);
+ slave_data->phy_if = ofnode_read_phy_mode(subnode);
ret = ofnode_parse_phandle_with_args(subnode, "phy-handle",
NULL, 0, 0, &out_args);
}
pdata->phy_interface = data->slave_data[data->active_slave].phy_if;
- if (pdata->phy_interface == -1) {
- debug("%s: Invalid PHY interface '%s'\n", __func__,
- phy_string_for_interface(pdata->phy_interface));
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- }
return 0;
}
#include <asm/ti-common/keystone_net.h>
#include <asm/ti-common/keystone_serdes.h>
#include <asm/arch/psc_defs.h>
-#include <linux/libfdt.h>
#include "cpsw_mdio.h"
struct mii_dev *mdio_bus;
int phy_addr;
phy_interface_t phy_if;
- int phy_of_handle;
+ ofnode phy_ofnode;
int sgmii_link_type;
- void *mdio_base;
+ phys_addr_t mdio_base;
struct rx_buff_desc net_rx_buffs;
struct pktdma_cfg *netcp_pktdma;
void *hd;
* to re-use the same
*/
mdio_bus = cpsw_mdio_init("ethernet-mdio",
- (u32)priv->mdio_base,
+ priv->mdio_base,
EMAC_MDIO_CLOCK_FREQ,
EMAC_MDIO_BUS_FREQ);
if (!mdio_bus) {
priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr,
dev, priv->phy_if);
#ifdef CONFIG_DM_ETH
- if (priv->phy_of_handle)
- priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
+ if (ofnode_valid(priv->phy_ofnode))
+ priv->phydev->node = priv->phy_ofnode;
#endif
phy_config(priv->phydev);
}
.write_hwaddr = ks2_eth_write_hwaddr,
};
-static int ks2_eth_bind_slaves(struct udevice *dev, int gbe, int *gbe_0)
+static int ks2_bind_one_slave(struct udevice *dev, ofnode slave, ofnode *gbe_0)
{
- const void *fdt = gd->fdt_blob;
- struct udevice *sl_dev;
- int interfaces;
- int sec_slave;
- int slave;
- int ret;
char *slave_name;
+ u32 slave_no;
+ int ret;
- interfaces = fdt_subnode_offset(fdt, gbe, "interfaces");
- fdt_for_each_subnode(slave, fdt, interfaces) {
- int slave_no;
-
- slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
- if (slave_no == -ENOENT)
- continue;
-
- if (slave_no == 0) {
- /* This is the current eth device */
- *gbe_0 = slave;
- } else {
- /* Slave devices to be registered */
- slave_name = malloc(20);
- snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
- ret = device_bind_driver_to_node(dev, "eth_ks2_sl",
- slave_name, offset_to_ofnode(slave),
- &sl_dev);
- if (ret) {
- pr_err("ks2_net - not able to bind slave interfaces\n");
- return ret;
- }
- }
+ if (ofnode_read_u32(slave, "slave-port", &slave_no))
+ return 0;
+
+ if (gbe_0 && slave_no == 0) {
+ /* This is the current eth device */
+ *gbe_0 = slave;
+ return 0;
+ }
+
+ /* Slave devices to be registered */
+ slave_name = malloc(20);
+ snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
+ ret = device_bind_driver_to_node(dev, "eth_ks2_sl", slave_name, slave,
+ NULL);
+ if (ret)
+ pr_err("ks2_net - not able to bind slave interfaces\n");
+
+ return ret;
+}
+
+static int ks2_eth_bind_slaves(struct udevice *dev, ofnode gbe, ofnode *gbe_0)
+{
+ ofnode interfaces, sec_slave, slave;
+ int ret;
+
+ interfaces = ofnode_find_subnode(gbe, "interfaces");
+ ofnode_for_each_subnode(slave, interfaces) {
+ ret = ks2_bind_one_slave(dev, slave, gbe_0);
+ if (ret)
+ return ret;
}
- sec_slave = fdt_subnode_offset(fdt, gbe, "secondary-slave-ports");
- fdt_for_each_subnode(slave, fdt, sec_slave) {
- int slave_no;
-
- slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
- if (slave_no == -ENOENT)
- continue;
-
- /* Slave devices to be registered */
- slave_name = malloc(20);
- snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
- ret = device_bind_driver_to_node(dev, "eth_ks2_sl", slave_name,
- offset_to_ofnode(slave), &sl_dev);
- if (ret) {
- pr_err("ks2_net - not able to bind slave interfaces\n");
+ sec_slave = ofnode_find_subnode(gbe, "secondary-slave-ports");
+ ofnode_for_each_subnode(slave, sec_slave) {
+ ret = ks2_bind_one_slave(dev, slave, NULL);
+ if (ret)
return ret;
- }
}
return 0;
}
-static int ks2_eth_parse_slave_interface(int netcp, int slave,
+static int ks2_eth_parse_slave_interface(ofnode netcp, ofnode slave,
struct ks2_eth_priv *priv,
struct eth_pdata *pdata)
{
- const void *fdt = gd->fdt_blob;
- int mdio;
- int phy;
+ struct ofnode_phandle_args dma_args;
+ ofnode phy, mdio;
int dma_count;
- u32 dma_channel[8];
- const char *phy_mode;
- priv->slave_port = fdtdec_get_int(fdt, slave, "slave-port", -1);
+ priv->slave_port = ofnode_read_s32_default(slave, "slave-port", -1);
priv->net_rx_buffs.rx_flow = priv->slave_port * 8;
/* U-Boot slave port number starts with 1 instead of 0 */
priv->slave_port += 1;
- dma_count = fdtdec_get_int_array_count(fdt, netcp,
- "ti,navigator-dmas",
- dma_channel, 8);
-
- if (dma_count > (2 * priv->slave_port)) {
- int dma_idx;
-
- dma_idx = priv->slave_port * 2 - 1;
- priv->net_rx_buffs.rx_flow = dma_channel[dma_idx];
- }
+ dma_count = ofnode_count_phandle_with_args(netcp, "ti,navigator-dmas",
+ NULL, 1);
+ if (priv->slave_port < dma_count &&
+ !ofnode_parse_phandle_with_args(netcp, "ti,navigator-dmas", NULL, 1,
+ priv->slave_port - 1, &dma_args))
+ priv->net_rx_buffs.rx_flow = dma_args.args[0];
- priv->link_type = fdtdec_get_int(fdt, slave, "link-interface", -1);
+ priv->link_type = ofnode_read_s32_default(slave, "link-interface", -1);
- phy = fdtdec_lookup_phandle(fdt, slave, "phy-handle");
+ phy = ofnode_get_phy_node(slave);
+ priv->phy_ofnode = phy;
+ if (ofnode_valid(phy)) {
+ priv->phy_addr = ofnode_read_s32_default(phy, "reg", -1);
- if (phy >= 0) {
- priv->phy_of_handle = phy;
- priv->phy_addr = fdtdec_get_int(fdt, phy, "reg", -1);
-
- mdio = fdt_parent_offset(fdt, phy);
- if (mdio < 0) {
+ mdio = ofnode_get_parent(phy);
+ if (!ofnode_valid(mdio)) {
pr_err("mdio dt not found\n");
return -ENODEV;
}
- priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg");
+ priv->mdio_base = ofnode_get_addr(mdio);
}
if (priv->link_type == LINK_TYPE_SGMII_MAC_TO_PHY_MODE) {
priv->sgmii_link_type = SGMII_LINK_MAC_PHY;
priv->has_mdio = true;
} else if (priv->link_type == LINK_TYPE_RGMII_LINK_MAC_PHY) {
- phy_mode = fdt_getprop(fdt, slave, "phy-mode", NULL);
- if (phy_mode) {
- priv->phy_if = phy_get_interface_by_name(phy_mode);
- if (priv->phy_if != PHY_INTERFACE_MODE_RGMII &&
- priv->phy_if != PHY_INTERFACE_MODE_RGMII_ID &&
- priv->phy_if != PHY_INTERFACE_MODE_RGMII_RXID &&
- priv->phy_if != PHY_INTERFACE_MODE_RGMII_TXID) {
- pr_err("invalid phy-mode\n");
- return -EINVAL;
- }
- } else {
+ priv->phy_if = ofnode_read_phy_mode(slave);
+ if (priv->phy_if == PHY_INTERFACE_MODE_NA)
priv->phy_if = PHY_INTERFACE_MODE_RGMII;
- }
pdata->phy_interface = priv->phy_if;
+
+ if (priv->phy_if != PHY_INTERFACE_MODE_RGMII &&
+ priv->phy_if != PHY_INTERFACE_MODE_RGMII_ID &&
+ priv->phy_if != PHY_INTERFACE_MODE_RGMII_RXID &&
+ priv->phy_if != PHY_INTERFACE_MODE_RGMII_TXID) {
+ pr_err("invalid phy-mode\n");
+ return -EINVAL;
+ }
+
priv->has_mdio = true;
}
static int ks2_sl_eth_of_to_plat(struct udevice *dev)
{
+ ofnode slave, interfaces, gbe, netcp_devices, netcp;
struct ks2_eth_priv *priv = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_plat(dev);
- const void *fdt = gd->fdt_blob;
- int slave = dev_of_offset(dev);
- int interfaces;
- int gbe;
- int netcp_devices;
- int netcp;
-
- interfaces = fdt_parent_offset(fdt, slave);
- gbe = fdt_parent_offset(fdt, interfaces);
- netcp_devices = fdt_parent_offset(fdt, gbe);
- netcp = fdt_parent_offset(fdt, netcp_devices);
+
+ slave = dev_ofnode(dev);
+ interfaces = ofnode_get_parent(slave);
+ gbe = ofnode_get_parent(interfaces);
+ netcp_devices = ofnode_get_parent(gbe);
+ netcp = ofnode_get_parent(netcp_devices);
ks2_eth_parse_slave_interface(netcp, slave, priv, pdata);
- pdata->iobase = fdtdec_get_addr(fdt, netcp, "reg");
+ pdata->iobase = ofnode_get_addr(netcp);
return 0;
}
{
struct ks2_eth_priv *priv = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_plat(dev);
- const void *fdt = gd->fdt_blob;
- int gbe_0 = -ENODEV;
- int netcp_devices;
- int gbe;
+ ofnode netcp_devices, gbe, gbe_0;
- netcp_devices = fdt_subnode_offset(fdt, dev_of_offset(dev),
- "netcp-devices");
- gbe = fdt_subnode_offset(fdt, netcp_devices, "gbe");
+ netcp_devices = dev_read_subnode(dev, "netcp-devices");
+ gbe = ofnode_find_subnode(netcp_devices, "gbe");
+ gbe_0 = ofnode_null();
ks2_eth_bind_slaves(dev, gbe, &gbe_0);
- ks2_eth_parse_slave_interface(dev_of_offset(dev), gbe_0, priv, pdata);
+ ks2_eth_parse_slave_interface(dev_ofnode(dev), gbe_0, priv, pdata);
pdata->iobase = dev_read_addr(dev);
struct ofnode_phandle_args phandle_args;
u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
struct tsec_data *data;
- const char *phy_mode;
ofnode parent, child;
fdt_addr_t reg;
u32 max_speed;
priv->tbiaddr = tbiaddr;
- phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
- if (!phy_mode)
- phy_mode = dev_read_prop(dev, "phy-mode", NULL);
- if (phy_mode)
- pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1)
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
pdata->phy_interface = tsec_get_interface(priv);
priv->interface = pdata->phy_interface;
struct eth_pdata *pdata = &plat->eth_pdata;
int node = dev_of_offset(dev);
int offset = 0;
- const char *phy_mode;
pdata->iobase = dev_read_addr(dev);
plat->mactype = dev_get_driver_data(dev);
plat->phy_of_handle = offset;
}
- phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
- if (phy_mode)
- pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- printf("%s: Invalid PHY interface '%s'\n", __func__,
- phy_mode);
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- }
plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
"xlnx,eth-hasnobuf");
struct eth_pdata *pdata = dev_get_plat(dev);
struct zynq_gem_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args phandle_args;
- const char *phy_mode;
pdata->iobase = (phys_addr_t)dev_read_addr(dev);
priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
}
}
- phy_mode = dev_read_prop(dev, "phy-mode", NULL);
- if (phy_mode)
- pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ pdata->phy_interface = dev_read_phy_mode(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- }
priv->interface = pdata->phy_interface;
priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
#include <linux/iopoll.h>
#define PSC_PTCMD 0x120
+#define PSC_PTCMD_H 0x124
#define PSC_PTSTAT 0x128
+#define PSC_PTSTAT_H 0x12C
#define PSC_PDSTAT 0x200
#define PSC_PDCTL 0x300
#define PSC_MDSTAT 0x800
static int ti_pd_wait(struct ti_pd *pd)
{
u32 ptstat;
+ u32 pdoffset = 0;
+ u32 ptstatreg = PSC_PTSTAT;
int ret;
- ret = readl_poll_timeout(pd->psc->base + PSC_PTSTAT, ptstat,
- !(ptstat & BIT(pd->id)), PD_TIMEOUT);
+ if (pd->id > 31) {
+ pdoffset = 32;
+ ptstatreg = PSC_PTSTAT_H;
+ }
+
+ ret = readl_poll_timeout(pd->psc->base + ptstatreg, ptstat,
+ !(ptstat & BIT(pd->id - pdoffset)), PD_TIMEOUT);
if (ret)
printf("%s: psc%d, pd%d failed to transition.\n", __func__,
static void ti_pd_transition(struct ti_pd *pd)
{
- psc_write(BIT(pd->id), pd->psc, PSC_PTCMD);
+ u32 pdoffset = 0;
+ u32 ptcmdreg = PSC_PTCMD;
+
+ if (pd->id > 31) {
+ pdoffset = 32;
+ ptcmdreg = PSC_PTCMD_H;
+ }
+
+ psc_write(BIT(pd->id - pdoffset), pd->psc, ptcmdreg);
}
u8 ti_pd_state(struct ti_pd *pd)
config SANDBOX_SERIAL
bool "Sandbox UART support"
depends on SANDBOX
+ imply SERIAL_PUTS
help
Select this to enable a seral UART for sandbox. This is required to
operate correctly, otherwise you will see no serial output from
config SEMIHOSTING_SERIAL
bool "Semihosting UART support"
depends on SEMIHOSTING && !SERIAL_RX_BUFFER
+ imply SERIAL_PUTS
help
Select this to enable a serial UART using semihosting. Special halt
instructions will be issued which an external debugger (such as a
DECLARE_GLOBAL_DATA_PTR;
+static size_t _sandbox_serial_written = 1;
+static bool sandbox_serial_enabled = true;
+
+size_t sandbox_serial_written(void)
+{
+ return _sandbox_serial_written;
+}
+
+void sandbox_serial_endisable(bool enabled)
+{
+ sandbox_serial_enabled = enabled;
+}
+
/**
* output_ansi_colour() - Output an ANSI colour code
*
return 0;
}
-static int sandbox_serial_putc(struct udevice *dev, const char ch)
+static void sandbox_print_color(struct udevice *dev)
{
struct sandbox_serial_priv *priv = dev_get_priv(dev);
struct sandbox_serial_plat *plat = dev_get_plat(dev);
priv->start_of_line = false;
output_ansi_colour(plat->colour);
}
+}
+
+static int sandbox_serial_putc(struct udevice *dev, const char ch)
+{
+ struct sandbox_serial_priv *priv = dev_get_priv(dev);
- os_write(1, &ch, 1);
if (ch == '\n')
priv->start_of_line = true;
+ if (sandbox_serial_enabled) {
+ sandbox_print_color(dev);
+ os_write(1, &ch, 1);
+ }
+ _sandbox_serial_written += 1;
return 0;
}
+static ssize_t sandbox_serial_puts(struct udevice *dev, const char *s,
+ size_t len)
+{
+ struct sandbox_serial_priv *priv = dev_get_priv(dev);
+ ssize_t ret;
+
+ if (s[len - 1] == '\n')
+ priv->start_of_line = true;
+
+ if (sandbox_serial_enabled) {
+ sandbox_print_color(dev);
+ ret = os_write(1, s, len);
+ if (ret < 0)
+ return ret;
+ } else {
+ ret = len;
+ }
+ _sandbox_serial_written += ret;
+ return ret;
+}
+
static int sandbox_serial_pending(struct udevice *dev, bool input)
{
struct sandbox_serial_priv *priv = dev_get_priv(dev);
static const struct dm_serial_ops sandbox_serial_ops = {
.putc = sandbox_serial_putc,
+ .puts = sandbox_serial_puts,
.pending = sandbox_serial_pending,
.getc = sandbox_serial_getc,
.getconfig = sandbox_serial_getconfig,
} while (err == -EAGAIN);
}
+static int __serial_puts(struct udevice *dev, const char *str, size_t len)
+{
+ struct dm_serial_ops *ops = serial_get_ops(dev);
+
+ do {
+ ssize_t written = ops->puts(dev, str, len);
+
+ if (written < 0)
+ return written;
+ str += written;
+ len -= written;
+ } while (len);
+
+ return 0;
+}
+
static void _serial_puts(struct udevice *dev, const char *str)
{
struct dm_serial_ops *ops = serial_get_ops(dev);
do {
const char *newline = strchrnul(str, '\n');
- size_t len = newline - str + !!*newline;
+ size_t len = newline - str;
- do {
- ssize_t written = ops->puts(dev, str, len);
+ if (__serial_puts(dev, str, len))
+ return;
- if (written < 0)
- return;
- str += written;
- len -= written;
- } while (len);
+ if (*newline && __serial_puts(dev, "\r\n", 2))
+ return;
- if (*newline)
- _serial_putc(dev, '\r');
+ str += len + !!*newline;
} while (*str);
}
#include <common.h>
#include <dm.h>
+#include <malloc.h>
#include <serial.h>
#include <semihosting.h>
/**
* struct smh_serial_priv - Semihosting serial private data
* @infd: stdin file descriptor (or error)
+ * @outfd: stdout file descriptor (or error)
*/
struct smh_serial_priv {
int infd;
return 0;
}
+static ssize_t smh_serial_puts(struct udevice *dev, const char *s, size_t len)
+{
+ int ret;
+ struct smh_serial_priv *priv = dev_get_priv(dev);
+ unsigned long written;
+
+ if (priv->outfd < 0) {
+ char *buf;
+
+ /* Try and avoid a copy if we can */
+ if (!s[len + 1]) {
+ smh_puts(s);
+ return len;
+ }
+
+ buf = strndup(s, len);
+ smh_puts(buf);
+ free(buf);
+ return len;
+ }
+
+ ret = smh_write(priv->outfd, s, len, &written);
+ if (written)
+ return written;
+ return ret;
+}
+
static const struct dm_serial_ops smh_serial_ops = {
.putc = smh_serial_putc,
+ .puts = smh_serial_puts,
.getc = smh_serial_getc,
};
struct smh_serial_priv *priv = dev_get_priv(dev);
priv->infd = smh_open(":tt", MODE_READ);
+ priv->outfd = smh_open(":tt", MODE_WRITE);
return 0;
}
};
static struct fstype_info fstypes[] = {
-#ifdef CONFIG_FS_FAT
+#if CONFIG_IS_ENABLED(FS_FAT)
{
.fstype = FS_TYPE_FAT,
.name = "fat",
.ln = fs_ln_unsupported,
},
#endif
+#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_CMD_UBIFS
{
.fstype = FS_TYPE_UBIFS,
.ln = fs_ln_unsupported,
},
#endif
+#endif
#ifdef CONFIG_FS_BTRFS
{
.fstype = FS_TYPE_BTRFS,
EXPORT_FUNC(mdio_get_current_dev, struct mii_dev *,
mdio_get_current_dev, void)
EXPORT_FUNC(phy_find_by_mask, struct phy_device *, phy_find_by_mask,
- struct mii_dev *bus, unsigned phy_mask,
- phy_interface_t interface)
+ struct mii_dev *bus, unsigned phy_mask)
EXPORT_FUNC(mdio_phydev_for_ethname, struct phy_device *,
mdio_phydev_for_ethname, const char *ethname)
EXPORT_FUNC(miiphy_set_current_dev, int, miiphy_set_current_dev,
# undef CONFIG_LBA48
#endif
-#define CONFIG_DRIVER_DM9000
#ifdef CONFIG_DRIVER_DM9000
# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
# define DM9000_IO CONFIG_DM9000_BASE
#endif
/* Ethernet */
-#define CONFIG_DRIVER_DM9000
#define CONFIG_DM9000_BASE 0x30000000
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
#define CONFIG_SYS_NS16550_CLK 48000000
/* Ethernet: davicom DM9000 */
-#define CONFIG_DRIVER_DM9000 1
#define CONFIG_DM9000_BASE 0xb6000000
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
*/
#ifdef CONFIG_CMD_NET
-#define CONFIG_DRIVER_DM9000 1
#define CONFIG_DM9000_BASE 0x08000000
#define DM9000_IO (CONFIG_DM9000_BASE)
#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
/* Hardware drivers */
/* DM9000 */
-#define CONFIG_DRIVER_DM9000 1
#define CONFIG_DM9000_BASE 0x2c000000
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
#include <dm/of.h>
#include <dm/of_access.h>
#include <log.h>
+#include <phy_interface.h>
/* Enable checks to protect against invalid calls */
#undef OF_CHECKS
*/
const char *ofnode_conf_read_str(const char *prop_name);
+/**
+ * ofnode_get_phy_node() - Get PHY node for a MAC (if not fixed-link)
+ *
+ * This function parses PHY handle from the Ethernet controller's ofnode
+ * (trying all possible PHY handle property names), and returns the PHY ofnode.
+ *
+ * Before this is used, ofnode_phy_is_fixed_link() should be checked first, and
+ * if the result to that is true, this function should not be called.
+ *
+ * @eth_node: ofnode belonging to the Ethernet controller
+ * Return: ofnode of the PHY, if it exists, otherwise an invalid ofnode
+ */
+ofnode ofnode_get_phy_node(ofnode eth_node);
+
+/**
+ * ofnode_read_phy_mode() - Read PHY connection type from a MAC node
+ *
+ * This function parses the "phy-mode" / "phy-connection-type" property and
+ * returns the corresponding PHY interface type.
+ *
+ * @mac_node: ofnode containing the property
+ * Return: one of PHY_INTERFACE_MODE_* constants, PHY_INTERFACE_MODE_NA on
+ * error
+ */
+phy_interface_t ofnode_read_phy_mode(ofnode mac_node);
+
#endif
int dev_decode_display_timing(const struct udevice *dev, int index,
struct display_timing *config);
+/**
+ * dev_get_phy_node() - Get PHY node for a MAC (if not fixed-link)
+ *
+ * This function parses PHY handle from the Ethernet controller's ofnode
+ * (trying all possible PHY handle property names), and returns the PHY ofnode.
+ *
+ * Before this is used, ofnode_phy_is_fixed_link() should be checked first, and
+ * if the result to that is true, this function should not be called.
+ *
+ * @dev: device representing the MAC
+ * Return: ofnode of the PHY, if it exists, otherwise an invalid ofnode
+ */
+ofnode dev_get_phy_node(const struct udevice *dev);
+
+/**
+ * dev_read_phy_mode() - Read PHY connection type from a MAC
+ *
+ * This function parses the "phy-mode" / "phy-connection-type" property and
+ * returns the corresponding PHY interface type.
+ *
+ * @dev: device representing the MAC
+ * Return: one of PHY_INTERFACE_MODE_* constants, PHY_INTERFACE_MODE_NA on
+ * error
+ */
+phy_interface_t dev_read_phy_mode(const struct udevice *dev);
+
#else /* CONFIG_DM_DEV_READ_INLINE is enabled */
#include <asm/global_data.h>
return ofnode_decode_display_timing(dev_ofnode(dev), index, config);
}
+static inline ofnode dev_get_phy_node(const struct udevice *dev)
+{
+ return ofnode_get_phy_node(dev_ofnode(dev));
+}
+
+static inline phy_interface_t dev_read_phy_mode(const struct udevice *dev)
+{
+ return ofnode_read_phy_mode(dev_ofnode(dev));
+}
+
#endif /* CONFIG_DM_DEV_READ_INLINE */
/**
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * NOTE: DAVICOM DM9000 ethernet driver interface
- *
- * Authors: Remy Bohmer <linux@bohmer.net>
- */
-#ifndef __DM9000_H__
-#define __DM9000_H__
-
-/****************** function prototypes **********************/
-#if !defined(CONFIG_DM9000_NO_SROM)
-void dm9000_write_srom_word(int offset, u16 val);
-void dm9000_read_srom_word(int offset, u8 *to);
-#endif
-
-#endif /* __DM9000_H__ */
#endif
#ifdef CONFIG_PHY_AQUANTIA
struct mii_dev *mdio_get_current_dev(void);
-struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
- phy_interface_t interface);
+struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask);
struct phy_device *mdio_phydev_for_ethname(const char *ethname);
int miiphy_set_current_dev(const char *devname);
#endif
#define FM_ETH_INFO_INITIALIZER(idx, pregs) \
.fm = idx, \
.phy_regs = (void *)pregs, \
- .enet_if = PHY_INTERFACE_MODE_NONE, \
+ .enet_if = PHY_INTERFACE_MODE_NA, \
#ifdef CONFIG_SYS_FMAN_V3
#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
struct udevice;
+enum led_state_t {
+ LEDST_OFF = 0,
+ LEDST_ON = 1,
+ LEDST_TOGGLE,
+#ifdef CONFIG_LED_BLINK
+ LEDST_BLINK,
+#endif
+
+ LEDST_COUNT,
+};
+
/**
* struct led_uc_plat - Platform data the uclass stores about each device
*
* @label: LED label
+ * @default_state: LED default state
*/
struct led_uc_plat {
const char *label;
+ enum led_state_t default_state;
};
/**
int period_ms;
};
-enum led_state_t {
- LEDST_OFF = 0,
- LEDST_ON = 1,
- LEDST_TOGGLE,
-#ifdef CONFIG_LED_BLINK
- LEDST_BLINK,
-#endif
-
- LEDST_COUNT,
-};
-
struct led_ops {
/**
* set_state() - set the state of an LED
void dm_mdio_probe_devices(void);
/**
+ * dm_mdio_read - Wrapper over .read() operation for DM MDIO
+ *
+ * @mdiodev: mdio device
+ * @addr: PHY address on MDIO bus
+ * @devad: device address on PHY if C45; should be MDIO_DEVAD_NONE if C22
+ * @reg: register address
+ * Return: register value if non-negative, -error code otherwise
+ */
+int dm_mdio_read(struct udevice *mdio_dev, int addr, int devad, int reg);
+
+/**
+ * dm_mdio_write - Wrapper over .write() operation for DM MDIO
+ *
+ * @mdiodev: mdio device
+ * @addr: PHY address on MDIO bus
+ * @devad: device address on PHY if C45; should be MDIO_DEVAD_NONE if C22
+ * @reg: register address
+ * @val: value to write
+ * Return: 0 on success, -error code otherwise
+ */
+int dm_mdio_write(struct udevice *mdio_dev, int addr, int devad, int reg, u16 val);
+
+/**
+ * dm_mdio_reset - Wrapper over .reset() operation for DM MDIO
+ *
+ * @mdiodev: mdio device
+ * Return: 0 on success, -error code otherwise
+ */
+int dm_mdio_reset(struct udevice *mdio_dev);
+
+/**
* dm_mdio_phy_connect - Wrapper over phy_connect for DM MDIO
*
* @mdiodev: mdio device the PHY is accesible on
#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;
-
-/*
- * List all 10G interfaces here, the assumption being that PHYs on these
- * interfaces are C45
- */
-static inline int is_10g_interface(phy_interface_t interface)
-{
- return interface == PHY_INTERFACE_MODE_XGMII ||
- interface == PHY_INTERFACE_MODE_USXGMII ||
- interface == PHY_INTERFACE_MODE_10GBASER;
-}
-
#endif
/**
*
* @bus: MII/MDIO bus to scan
* @phy_mask: bitmap of PYH addresses to scan
- * @interface: type of MAC-PHY interface
* @return: pointer to phy_device if a PHY is found, or NULL otherwise
*/
-struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
- phy_interface_t interface);
+struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask);
#ifdef CONFIG_PHY_FIXED
* phy_connect_dev() - Associates the given pair of PHY and Ethernet devices
* @phydev: PHY device
* @dev: Ethernet device
+ * @interface: type of MAC-PHY interface
*/
-void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
+void phy_connect_dev(struct phy_device *phydev, struct udevice *dev,
+ phy_interface_t interface);
/**
* phy_connect() - Creates a PHY device for the Ethernet interface
* @addr: PHY address on MDIO bus
* @phy_id: where to store the ID retrieved
* @is_c45: Device Identifiers if is_c45
- * @interface: interface between the MAC and PHY
* @return: pointer to phy_device if a PHY is found, or NULL otherwise
*/
struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
- u32 phy_id, bool is_c45,
- phy_interface_t interface);
+ u32 phy_id, bool is_c45);
/**
* phy_connect_phy_id() - Connect to phy device by reading PHY id
*
* @bus: MII/MDIO bus that hosts the PHY
* @dev: Ethernet device to associate to the PHY
- * @interface: Interface between the MAC and PHY
* @return: pointer to phy_device if a PHY is found,
* or NULL otherwise
*/
struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev,
- int phyaddr, phy_interface_t interface);
+ int phyaddr);
static inline ofnode phy_get_ofnode(struct phy_device *phydev)
{
* phy_connect_dev() - Associates the given pair of PHY and Ethernet devices
* @phydev: PHY device
* @dev: Ethernet device
+ * @interface: type of MAC-PHY interface
*/
-void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
+void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev,
+ phy_interface_t interface);
/**
* phy_connect() - Creates a PHY device for the Ethernet interface
int phy_b53_init(void);
int phy_mv88e61xx_init(void);
+int phy_adin_init(void);
int phy_aquantia_init(void);
int phy_atheros_init(void);
int phy_broadcom_init(void);
int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
/**
- * phy_get_interface_by_name() - Look up a PHY interface name
- *
- * @str: PHY interface name, e.g. "mii"
- * @return: PHY_INTERFACE_MODE_... value, or -1 if not found
- */
-int phy_get_interface_by_name(const char *str);
-
-/**
* phy_interface_is_rgmii - Convenience function for testing if a PHY interface
* is RGMII (all variants)
* @phydev: the phy_device struct
#include <string.h>
typedef enum {
+ PHY_INTERFACE_MODE_NA, /* don't touch */
PHY_INTERFACE_MODE_MII,
PHY_INTERFACE_MODE_GMII,
PHY_INTERFACE_MODE_SGMII,
PHY_INTERFACE_MODE_NCSI,
PHY_INTERFACE_MODE_10GBASER,
PHY_INTERFACE_MODE_USXGMII,
- PHY_INTERFACE_MODE_NONE, /* Must be last */
-
- PHY_INTERFACE_MODE_COUNT,
+ PHY_INTERFACE_MODE_MAX,
} phy_interface_t;
static const char * const phy_interface_strings[] = {
+ [PHY_INTERFACE_MODE_NA] = "",
[PHY_INTERFACE_MODE_MII] = "mii",
[PHY_INTERFACE_MODE_GMII] = "gmii",
[PHY_INTERFACE_MODE_SGMII] = "sgmii",
[PHY_INTERFACE_MODE_NCSI] = "NC-SI",
[PHY_INTERFACE_MODE_10GBASER] = "10gbase-r",
[PHY_INTERFACE_MODE_USXGMII] = "usxgmii",
- [PHY_INTERFACE_MODE_NONE] = "",
};
/* Backplane modes:
static inline const char *phy_string_for_interface(phy_interface_t i)
{
/* Default to unknown */
- if (i > PHY_INTERFACE_MODE_NONE)
- i = PHY_INTERFACE_MODE_NONE;
+ if (i > PHY_INTERFACE_MODE_NA)
+ i = PHY_INTERFACE_MODE_NA;
return phy_interface_strings[i];
}
#ifndef _TABLES_CSUM_H_
#define _TABLES_CSUM_H_
-static inline u8 table_compute_checksum(void *v, int len)
-{
- u8 *bytes = v;
- u8 checksum = 0;
- int i;
-
- for (i = 0; i < len; i++)
- checksum -= bytes[i];
-
- return checksum;
-}
+/**
+ * table_compute_checksum() - Compute a table checksum
+ *
+ * This computes an 8-bit checksum for the configuration table.
+ * All bytes in the configuration table, including checksum itself and
+ * reserved bytes must add up to zero.
+ *
+ * @v: configuration table base address
+ * @len: configuration table size
+ * @return: the 8-bit checksum
+ */
+u8 table_compute_checksum(void *v, int len);
#endif
.phyaddr = 0, \
.index = idx, \
.phy_regs = NULL, \
- .enet_if = PHY_INTERFACE_MODE_NONE, \
+ .enet_if = PHY_INTERFACE_MODE_NA, \
.bus = NULL, \
.phydev = NULL, \
}
return pdata->mdio_parent;
}
-static struct mdio_ops *mmux_get_mdio_parent_ops(struct udevice *mux)
-{
- return mdio_get_ops(mmux_get_parent_mdio(mux));
-}
-
/* call driver select function before performing MDIO r/w */
static int mmux_change_sel(struct udevice *ch, bool sel)
{
{
struct udevice *mux = ch->parent;
struct udevice *parent_mdio = mmux_get_parent_mdio(mux);
- struct mdio_ops *parent_ops = mmux_get_mdio_parent_ops(mux);
int err;
err = mmux_change_sel(ch, true);
if (err)
return err;
- err = parent_ops->read(parent_mdio, addr, devad, reg);
+ err = dm_mdio_read(parent_mdio, addr, devad, reg);
mmux_change_sel(ch, false);
return err;
{
struct udevice *mux = ch->parent;
struct udevice *parent_mdio = mmux_get_parent_mdio(mux);
- struct mdio_ops *parent_ops = mmux_get_mdio_parent_ops(mux);
int err;
err = mmux_change_sel(ch, true);
if (err)
return err;
- err = parent_ops->write(parent_mdio, addr, devad, reg, val);
+ err = dm_mdio_write(parent_mdio, addr, devad, reg, val);
mmux_change_sel(ch, false);
return err;
{
struct udevice *mux = ch->parent;
struct udevice *parent_mdio = mmux_get_parent_mdio(mux);
- struct mdio_ops *parent_ops = mmux_get_mdio_parent_ops(mux);
int err;
/* reset is optional, if it's not implemented just exit */
- if (!parent_ops->reset)
+ if (!mdio_get_ops(parent_mdio)->reset)
return 0;
err = mmux_change_sel(ch, true);
if (err)
return err;
- err = parent_ops->reset(parent_mdio);
+ err = dm_mdio_reset(parent_mdio);
mmux_change_sel(ch, false);
return err;
#include <dm/uclass-internal.h>
#include <linux/compat.h>
-/* DT node properties for MAC-PHY interface */
-#define PHY_MODE_STR_CNT 2
-static const char *phy_mode_str[PHY_MODE_STR_CNT] = { "phy-mode",
- "phy-connection-type" };
-/* DT node properties that reference a PHY node */
-#define PHY_HANDLE_STR_CNT 3
-const char *phy_handle_str[PHY_HANDLE_STR_CNT] = { "phy-handle",
- "phy",
- "phy-device" };
-
void dm_mdio_probe_devices(void)
{
struct udevice *it;
return 0;
}
+int dm_mdio_read(struct udevice *mdio_dev, int addr, int devad, int reg)
+{
+ struct mdio_ops *ops = mdio_get_ops(mdio_dev);
+
+ if (!ops->read)
+ return -ENOSYS;
+
+ return ops->read(mdio_dev, addr, devad, reg);
+}
+
+int dm_mdio_write(struct udevice *mdio_dev, int addr, int devad, int reg,
+ u16 val)
+{
+ struct mdio_ops *ops = mdio_get_ops(mdio_dev);
+
+ if (!ops->write)
+ return -ENOSYS;
+
+ return ops->write(mdio_dev, addr, devad, reg, val);
+}
+
+int dm_mdio_reset(struct udevice *mdio_dev)
+{
+ struct mdio_ops *ops = mdio_get_ops(mdio_dev);
+
+ if (!ops->reset)
+ return 0;
+
+ return ops->reset(mdio_dev);
+}
+
/*
* Following read/write/reset functions are registered with legacy MII code.
* These are called for PHY operations by upper layers and we further call the
*/
static int mdio_read(struct mii_dev *mii_bus, int addr, int devad, int reg)
{
- struct udevice *dev = mii_bus->priv;
-
- return mdio_get_ops(dev)->read(dev, addr, devad, reg);
+ return dm_mdio_read(mii_bus->priv, addr, devad, reg);
}
static int mdio_write(struct mii_dev *mii_bus, int addr, int devad, int reg,
u16 val)
{
- struct udevice *dev = mii_bus->priv;
-
- return mdio_get_ops(dev)->write(dev, addr, devad, reg, val);
+ return dm_mdio_write(mii_bus->priv, addr, devad, reg, val);
}
static int mdio_reset(struct mii_dev *mii_bus)
{
- struct udevice *dev = mii_bus->priv;
-
- if (mdio_get_ops(dev)->reset)
- return mdio_get_ops(dev)->reset(dev);
- else
- return 0;
+ return dm_mdio_reset(mii_bus->priv);
}
static int dm_mdio_post_probe(struct udevice *dev)
static int dm_mdio_pre_remove(struct udevice *dev)
{
struct mdio_perdev_priv *pdata = dev_get_uclass_priv(dev);
- struct mdio_ops *ops = mdio_get_ops(dev);
- if (ops->reset)
- ops->reset(dev);
+ dm_mdio_reset(dev);
mdio_unregister(pdata->mii_bus);
mdio_free(pdata->mii_bus);
u32 phy_addr;
struct udevice *mdiodev;
struct phy_device *phy;
- struct ofnode_phandle_args phandle = {.node = ofnode_null()};
ofnode phynode;
- int i;
if (CONFIG_IS_ENABLED(PHY_FIXED) &&
ofnode_phy_is_fixed_link(dev_ofnode(ethdev), &phynode)) {
phy = phy_connect(NULL, 0, ethdev, interface);
- phandle.node = phynode;
goto out;
}
- for (i = 0; i < PHY_HANDLE_STR_CNT; i++)
- if (!dev_read_phandle_with_args(ethdev, phy_handle_str[i], NULL,
- 0, 0, &phandle))
- break;
-
- if (!ofnode_valid(phandle.node)) {
+ phynode = dev_get_phy_node(ethdev);
+ if (!ofnode_valid(phynode)) {
dev_dbg(ethdev, "can't find PHY node\n");
return NULL;
}
* reading 'reg' directly should be fine. This is a PHY node, the
* address is always size 1 and requires no translation
*/
- if (ofnode_read_u32(phandle.node, "reg", &phy_addr)) {
+ if (ofnode_read_u32(phynode, "reg", &phy_addr)) {
dev_dbg(ethdev, "missing reg property in phy node\n");
return NULL;
}
if (uclass_get_device_by_ofnode(UCLASS_MDIO,
- ofnode_get_parent(phandle.node),
+ ofnode_get_parent(phynode),
&mdiodev)) {
dev_dbg(ethdev, "can't find MDIO bus for node %s\n",
- ofnode_get_name(ofnode_get_parent(phandle.node)));
+ ofnode_get_name(ofnode_get_parent(phynode)));
return NULL;
}
out:
if (phy)
- phy->node = phandle.node;
+ phy->node = phynode;
return phy;
}
/* Connect to a PHY linked in eth DT node */
struct phy_device *dm_eth_phy_connect(struct udevice *ethdev)
{
- const char *if_str;
phy_interface_t interface;
struct phy_device *phy;
- int i;
if (!dev_has_ofnode(ethdev)) {
debug("%s: supplied eth dev has no DT node!\n", ethdev->name);
return NULL;
}
- interface = PHY_INTERFACE_MODE_NONE;
- for (i = 0; i < PHY_MODE_STR_CNT; i++) {
- if_str = dev_read_string(ethdev, phy_mode_str[i]);
- if (if_str) {
- interface = phy_get_interface_by_name(if_str);
- break;
- }
- }
- if (interface < 0)
- interface = PHY_INTERFACE_MODE_NONE;
- if (interface == PHY_INTERFACE_MODE_NONE)
- dev_dbg(ethdev, "can't find interface mode, default to NONE\n");
+ interface = dev_read_phy_mode(ethdev);
+ if (interface == PHY_INTERFACE_MODE_NA)
+ dev_dbg(ethdev, "can't find interface mode, default to NA\n");
phy = dm_eth_connect_phy_handle(ethdev, interface);
tftp_block_size = TFTP_BLOCK_SIZE;
tftp_cur_block = 0;
tftp_our_port = WELL_KNOWN_PORT;
+ tftp_windowsize = 1;
+ tftp_next_ack = tftp_windowsize;
#ifdef CONFIG_TFTP_TSIZE
tftp_tsize = 0;
CONFIG_DM9000_NO_SROM
CONFIG_DM9000_USE_16BIT
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR
-CONFIG_DRIVER_DM9000
CONFIG_DSP_CLUSTER_START
CONFIG_DWC_AHSATA_BASE_ADDR
CONFIG_DWC_AHSATA_PORT_ID
/* Test that 'pinmux status <pinname>' displays the selected pin. */
console_record_reset();
run_command("pinmux status a5", 0);
- ut_assert_nextlinen("a5 : gpio input .");
+ ut_assert_nextlinen("a5 : gpio output .");
ut_assert_console_end();
console_record_reset();
ut_assertnonnull(ops->read);
ut_assertnonnull(ops->write);
- ut_assertok(ops->write(dev, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
- SANDBOX_PHY_REG, TEST_REG_VALUE));
- reg = ops->read(dev, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
- SANDBOX_PHY_REG);
+ ut_assertok(dm_mdio_write(dev, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
+ SANDBOX_PHY_REG, TEST_REG_VALUE));
+ reg = dm_mdio_read(dev, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
+ SANDBOX_PHY_REG);
ut_asserteq(reg, TEST_REG_VALUE);
- ut_assert(ops->read(dev, SANDBOX_PHY_ADDR + 1, MDIO_DEVAD_NONE,
- SANDBOX_PHY_REG) != 0);
+ ut_assert(dm_mdio_read(dev, SANDBOX_PHY_ADDR + 1, MDIO_DEVAD_NONE,
+ SANDBOX_PHY_REG) != 0);
- ut_assertok(ops->reset(dev));
- reg = ops->read(dev, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
- SANDBOX_PHY_REG);
+ ut_assertok(dm_mdio_reset(dev));
+ reg = dm_mdio_read(dev, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
+ SANDBOX_PHY_REG);
ut_asserteq(reg, 0);
return 0;
* is selected to the selection #. Just reading that register from
* either of the child buses should return the id of the child bus
*/
- reg = ops->read(mdio_ch0, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
- SANDBOX_PHY_REG_CNT - 1);
+ reg = dm_mdio_read(mdio_ch0, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
+ SANDBOX_PHY_REG_CNT - 1);
ut_asserteq(reg, 0);
- reg = ops->read(mdio_ch1, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
- SANDBOX_PHY_REG_CNT - 1);
+ reg = dm_mdio_read(mdio_ch1, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
+ SANDBOX_PHY_REG_CNT - 1);
ut_asserteq(reg, 1);
mmops->select(mux, MDIO_MUX_SELECT_NONE, 5);
- reg = ops_parent->read(mdio, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
- SANDBOX_PHY_REG_CNT - 1);
+ reg = dm_mdio_read(mdio, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
+ SANDBOX_PHY_REG_CNT - 1);
ut_asserteq(reg, 5);
mmops->deselect(mux, 5);
- reg = ops_parent->read(mdio, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
- SANDBOX_PHY_REG_CNT - 1);
+ reg = dm_mdio_read(mdio, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
+ SANDBOX_PHY_REG_CNT - 1);
ut_asserteq(reg, (u16)MDIO_MUX_SELECT_NONE);
return 0;
return 0;
}
DM_TEST(dm_test_ofnode_string_err, UT_TESTF_LIVE_TREE);
+
+static int dm_test_ofnode_get_phy(struct unit_test_state *uts)
+{
+ ofnode eth_node, phy_node;
+ phy_interface_t mode;
+ u32 reg;
+
+ eth_node = ofnode_path("/phy-test-eth");
+ ut_assert(ofnode_valid(eth_node));
+
+ mode = ofnode_read_phy_mode(eth_node);
+ ut_assert(mode == PHY_INTERFACE_MODE_2500BASEX);
+
+ phy_node = ofnode_get_phy_node(eth_node);
+ ut_assert(ofnode_valid(phy_node));
+
+ reg = ofnode_read_u32_default(phy_node, "reg", -1U);
+ ut_asserteq_64(0x1, reg);
+
+ return 0;
+}
+DM_TEST(dm_test_ofnode_get_phy, 0);
#include <log.h>
#include <serial.h>
#include <dm.h>
+#include <asm/serial.h>
#include <dm/test.h>
#include <test/test.h>
#include <test/ut.h>
+static const char test_message[] =
+ "This is a test message\n"
+ "consisting of multiple lines\n";
+
static int dm_test_serial(struct unit_test_state *uts)
{
+ int i;
struct serial_device_info info_serial = {0};
struct udevice *dev_serial;
+ size_t start, putc_written;
+
uint value_serial;
ut_assertok(uclass_get_device_by_name(UCLASS_SERIAL, "serial",
SERIAL_8_BITS,
SERIAL_TWO_STOP)));
+ /* Verify that putc and puts print the same number of characters */
+ sandbox_serial_endisable(false);
+ start = sandbox_serial_written();
+ for (i = 0; i < sizeof(test_message) - 1; i++)
+ serial_putc(test_message[i]);
+ putc_written = sandbox_serial_written();
+ serial_puts(test_message);
+ sandbox_serial_endisable(true);
+ ut_asserteq(putc_written - start,
+ sandbox_serial_written() - putc_written);
+
return 0;
}
projects / platform / kernel / u-boot.git / commitdiff