S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git
F: drivers/watchdog/sp805_wdt.c
+F: drivers/watchdog/sbsa_gwdt.c
I2C
M: Heiko Schocher <hs@denx.de>
config ARCH_LS1028A
bool
select ARMV8_SET_SMPEN
+ select FSL_LAYERSCAPE
select FSL_LSCH3
select NXP_LSCH3_2
select SYS_FSL_HAS_CCI400
select SYS_FSL_ERRATUM_A009660 if !TFABOOT
select SYS_FSL_ERRATUM_A009663 if !TFABOOT
select SYS_FSL_ERRATUM_A009798
- select SYS_FSL_ERRATUM_A009929
select SYS_FSL_ERRATUM_A009942 if !TFABOOT
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
- select SYS_I2C_MXC if !DM_I2C
+ select SYS_I2C_MXC
select SYS_I2C_MXC_I2C1 if !DM_I2C
select SYS_I2C_MXC_I2C2 if !DM_I2C
select SYS_I2C_MXC_I2C3 if !DM_I2C
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
- select SYS_I2C_MXC if !DM_I2C
+ select SYS_I2C_MXC
select SYS_I2C_MXC_I2C1 if !DM_I2C
select SYS_I2C_MXC_I2C2 if !DM_I2C
select SYS_I2C_MXC_I2C3 if !DM_I2C
config SYS_FSL_ERRATUM_A009660
bool
-config SYS_FSL_ERRATUM_A009929
- bool
-
config SYS_FSL_ERRATUM_A050382
bool
obj-y += lowlevel.o
obj-y += soc.o
ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_MP) += mp.o
+obj-$(CONFIG_MP) += mp.o spintable.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
endif
obj-$(CONFIG_SPL) += spl.o
fdt32_t *reg;
int addr_cells;
u64 val, core_id;
- size_t *boot_code_size = &(__secondary_boot_code_size);
u32 mask = cpu_pos_mask();
int off_prev = -1;
"cpu", 4);
}
- fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code,
- *boot_code_size);
+ fdt_add_mem_rsv(blob, (uintptr_t)secondary_boot_code_start,
+ secondary_boot_code_size);
#if CONFIG_IS_ENABLED(EFI_LOADER)
- efi_add_memory_map((uintptr_t)&secondary_boot_code, *boot_code_size,
- EFI_RESERVED_MEMORY_TYPE);
+ efi_add_memory_map((uintptr_t)secondary_boot_code_start,
+ secondary_boot_code_size, EFI_RESERVED_MEMORY_TYPE);
#endif
}
#endif
#include <asm/gic.h>
#include <asm/macro.h>
#include <asm/arch-fsl-layerscape/soc.h>
-#ifdef CONFIG_MP
-#include <asm/arch/mp.h>
-#endif
#ifdef CONFIG_FSL_LSCH3
#include <asm/arch-fsl-layerscape/immap_lsch3.h>
#endif
#include <asm/u-boot.h>
+ .align 3
+ .weak secondary_boot_addr
+secondary_boot_addr:
+ .quad 0
+
/* Get GIC offset
* For LS1043a rev1.0, GIC base address align with 4k.
* For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
branch_if_master x0, x1, 2f
#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
- ldr x0, =secondary_boot_func
- blr x0
+ /*
+ * Formerly, here was a jump to secondary_boot_func, but we just
+ * return early here and let the generic code in start.S handle
+ * the jump to secondary_boot_func.
+ */
+ mov lr, x29 /* Restore LR */
+ ret
#endif
2:
ret
ENDPROC(__asm_flush_l3_dcache)
#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
-
-#ifdef CONFIG_MP
- /* Keep literals not used by the secondary boot code outside it */
- .ltorg
-
- /* Using 64 bit alignment since the spin table is accessed as data */
- .align 4
- .global secondary_boot_code
- /* Secondary Boot Code starts here */
-secondary_boot_code:
- .global __spin_table
-__spin_table:
- .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
-
- .align 2
-ENTRY(secondary_boot_func)
- /*
- * MPIDR_EL1 Fields:
- * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
- * MPIDR[7:2] = AFF0_RES
- * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
- * MPIDR[23:16] = AFF2_CLUSTERID
- * MPIDR[24] = MT
- * MPIDR[29:25] = RES0
- * MPIDR[30] = U
- * MPIDR[31] = ME
- * MPIDR[39:32] = AFF3
- *
- * Linear Processor ID (LPID) calculation from MPIDR_EL1:
- * (We only use AFF0_CPUID and AFF1_CLUSTERID for now
- * until AFF2_CLUSTERID and AFF3 have non-zero values)
- *
- * LPID = MPIDR[15:8] | MPIDR[1:0]
- */
- mrs x0, mpidr_el1
- ubfm x1, x0, #8, #15
- ubfm x2, x0, #0, #1
- orr x10, x2, x1, lsl #2 /* x10 has LPID */
- ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
- /*
- * offset of the spin table element for this core from start of spin
- * table (each elem is padded to 64 bytes)
- */
- lsl x1, x10, #6
- ldr x0, =__spin_table
- /* physical address of this cpus spin table element */
- add x11, x1, x0
-
- ldr x0, =__real_cntfrq
- ldr x0, [x0]
- msr cntfrq_el0, x0 /* set with real frequency */
- str x9, [x11, #16] /* LPID */
- mov x4, #1
- str x4, [x11, #8] /* STATUS */
- dsb sy
-#if defined(CONFIG_GICV3)
- gic_wait_for_interrupt_m x0
-#elif defined(CONFIG_GICV2)
- bl get_gic_offset
- mov x0, x1
- gic_wait_for_interrupt_m x0, w1
-#endif
-
-slave_cpu:
- wfe
- ldr x0, [x11]
- cbz x0, slave_cpu
-#ifndef CONFIG_ARMV8_SWITCH_TO_EL1
- mrs x1, sctlr_el2
-#else
- mrs x1, sctlr_el1
-#endif
- tbz x1, #25, cpu_is_le
- rev x0, x0 /* BE to LE conversion */
-cpu_is_le:
- ldr x5, [x11, #24]
- cbz x5, 1f
-
-#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
- adr x4, secondary_switch_to_el1
- ldr x5, =ES_TO_AARCH64
-#else
- ldr x4, [x11]
- ldr x5, =ES_TO_AARCH32
-#endif
- bl secondary_switch_to_el2
-
-1:
-#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
- adr x4, secondary_switch_to_el1
-#else
- ldr x4, [x11]
-#endif
- ldr x5, =ES_TO_AARCH64
- bl secondary_switch_to_el2
-
-ENDPROC(secondary_boot_func)
-
-ENTRY(secondary_switch_to_el2)
- switch_el x6, 1f, 0f, 0f
-0: ret
-1: armv8_switch_to_el2_m x4, x5, x6
-ENDPROC(secondary_switch_to_el2)
-
-ENTRY(secondary_switch_to_el1)
- mrs x0, mpidr_el1
- ubfm x1, x0, #8, #15
- ubfm x2, x0, #0, #1
- orr x10, x2, x1, lsl #2 /* x10 has LPID */
-
- lsl x1, x10, #6
- ldr x0, =__spin_table
- /* physical address of this cpus spin table element */
- add x11, x1, x0
-
- ldr x4, [x11]
-
- ldr x5, [x11, #24]
- cbz x5, 2f
-
- ldr x5, =ES_TO_AARCH32
- bl switch_to_el1
-
-2: ldr x5, =ES_TO_AARCH64
-
-switch_to_el1:
- switch_el x6, 0f, 1f, 0f
-0: ret
-1: armv8_switch_to_el1_m x4, x5, x6
-ENDPROC(secondary_switch_to_el1)
-
- /* Ensure that the literals used by the secondary boot code are
- * assembled within it (this is required so that we can protect
- * this area with a single memreserve region
- */
- .ltorg
-
- /* 64 bit alignment for elements accessed as data */
- .align 4
- .global __real_cntfrq
-__real_cntfrq:
- .quad COUNTER_FREQUENCY
- .globl __secondary_boot_code_size
- .type __secondary_boot_code_size, %object
- /* Secondary Boot Code ends here */
-__secondary_boot_code_size:
- .quad .-secondary_boot_code
-#endif
#include <common.h>
#include <cpu_func.h>
#include <image.h>
+#include <log.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/system.h>
#include <linux/delay.h>
#include "cpu.h"
#include <asm/arch-fsl-layerscape/soc.h>
+#include <efi_loader.h>
DECLARE_GLOBAL_DATA_PTR;
void *get_spin_tbl_addr(void)
{
- return &__spin_table;
-}
-
-phys_addr_t determine_mp_bootpg(void)
-{
- return (phys_addr_t)&secondary_boot_code;
+ /* the spin table is at the beginning */
+ return secondary_boot_code_start;
}
void update_os_arch_secondary_cores(uint8_t os_arch)
}
#ifdef CONFIG_FSL_LSCH3
-void wake_secondary_core_n(int cluster, int core, int cluster_cores)
+static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
#endif
u32 cores, cpu_up_mask = 1;
int i, timeout = 10;
- u64 *table = get_spin_tbl_addr();
+ u64 *table;
+#ifdef CONFIG_EFI_LOADER
+ u64 reloc_addr = U32_MAX;
+ efi_status_t ret;
+#endif
#ifdef COUNTER_FREQUENCY_REAL
/* update for secondary cores */
(unsigned long)&__real_cntfrq + 8);
#endif
+#ifdef CONFIG_EFI_LOADER
+ /*
+ * EFI will reserve 64kb for its runtime services. This will probably
+ * overlap with our spin table code, which is why we have to relocate
+ * it.
+ * Keep this after the __real_cntfrq update, so we have it when we
+ * copy the complete section here.
+ */
+ ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
+ EFI_RESERVED_MEMORY_TYPE,
+ efi_size_in_pages(secondary_boot_code_size),
+ &reloc_addr);
+ if (ret == EFI_SUCCESS) {
+ debug("Relocating spin table from %llx to %llx (size %lx)\n",
+ (u64)secondary_boot_code_start, reloc_addr,
+ secondary_boot_code_size);
+ memcpy((void *)reloc_addr, secondary_boot_code_start,
+ secondary_boot_code_size);
+ flush_dcache_range(reloc_addr,
+ reloc_addr + secondary_boot_code_size);
+
+ /* set new entry point for secondary cores */
+ secondary_boot_addr += (void *)reloc_addr -
+ secondary_boot_code_start;
+ flush_dcache_range((unsigned long)&secondary_boot_addr,
+ (unsigned long)&secondary_boot_addr + 8);
+
+ /* this will be used to reserve the memory */
+ secondary_boot_code_start = (void *)reloc_addr;
+ }
+#endif
+
cores = cpu_mask();
/* Clear spin table so that secondary processors
* observe the correct value after waking up from wfe.
*/
+ table = get_spin_tbl_addr();
memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE);
flush_dcache_range((unsigned long)table,
(unsigned long)table +
(CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
- printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
+ debug("Waking secondary cores to start from %lx\n", gd->relocaddr);
#ifdef CONFIG_FSL_LSCH3
gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
udelay(10);
}
if (timeout <= 0) {
- printf("Not all cores (0x%x) are up (0x%x)\n",
- cores, cpu_up_mask);
+ printf("CPU: Failed to bring up some cores (mask 0x%x)\n",
+ cores ^ cpu_up_mask);
return 1;
}
- printf("All (%d) cores are up.\n", hweight32(cores));
+ printf("CPU: %d cores online\n", hweight32(cores));
return 0;
}
int is_core_online(u64 cpu_id)
{
- u64 *table;
+ u64 *table = get_spin_tbl_addr();
int pos = id_to_core(cpu_id);
- table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY;
+ table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
}
int cpu_status(u32 nr)
{
- u64 *table;
+ u64 *table = get_spin_tbl_addr();
int pos;
if (nr == 0) {
- table = (u64 *)get_spin_tbl_addr();
printf("table base @ 0x%p\n", table);
} else {
pos = core_to_pos(nr);
if (pos < 0)
return -1;
- table = (u64 *)get_spin_tbl_addr() + pos *
- WORDS_PER_SPIN_TABLE_ENTRY;
+ table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
printf("table @ 0x%p\n", table);
printf(" addr - 0x%016llx\n",
table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]);
int cpu_release(u32 nr, int argc, char *const argv[])
{
u64 boot_addr;
- u64 *table = (u64 *)get_spin_tbl_addr();
+ u64 *table = get_spin_tbl_addr();
int pos;
pos = core_to_pos(nr);
flush_dcache_range((unsigned long)table,
(unsigned long)table + SPIN_TABLE_ELEM_SIZE);
asm volatile("dsb st");
- smp_kick_all_cpus(); /* only those with entry addr set will run */
+
/*
- * When the first release command runs, all cores are set to go. Those
- * without a valid entry address will be trapped by "wfe". "sev" kicks
- * them off to check the address again. When set, they continue to run.
+ * The secondary CPUs polling the spin-table above for a non-zero
+ * value. To save power "wfe" is called. Thus call "sev" here to
+ * wake the CPUs and let them check the spin-table again (see
+ * slave_cpu loop in lowlevel.S)
*/
asm volatile("sev");
}
#elif defined(CONFIG_FSL_LSCH2)
-
-static void erratum_a009929(void)
-{
-#ifdef CONFIG_SYS_FSL_ERRATUM_A009929
- struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
- u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
- u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
-
- rstrqmr1 |= 0x00000400;
- gur_out32(&gur->rstrqmr1, rstrqmr1);
- writel(0x01000000, dcsr_cop_ccp);
-#endif
-}
-
/*
* This erratum requires setting a value to eddrtqcr1 to optimal
* the DDR performance. The eddrtqcr1 register is in SCFG space
#endif
/* Erratum */
erratum_a008850_early(); /* part 1 of 2 */
- erratum_a009929();
erratum_a009660();
erratum_a010539();
erratum_a009008();
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014-2015 Freescale Semiconductor
+ * Copyright 2019 NXP
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+#include <asm/system.h>
+#include <asm/arch/mp.h>
+
+.align 3
+.global secondary_boot_addr
+secondary_boot_addr:
+ .quad __secondary_boot_func
+
+.global secondary_boot_code_start
+secondary_boot_code_start:
+ .quad __secondary_boot_code_start
+
+.global secondary_boot_code_size
+secondary_boot_code_size:
+ .quad __secondary_boot_code_end - __secondary_boot_code_start
+
+ /* Using 64 bit alignment since the spin table is accessed as data */
+ .align 3
+ /* Secondary Boot Code starts here */
+__secondary_boot_code_start:
+__spin_table:
+ .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
+
+ .align 2
+__secondary_boot_func:
+ /*
+ * MPIDR_EL1 Fields:
+ * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
+ * MPIDR[7:2] = AFF0_RES
+ * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
+ * MPIDR[23:16] = AFF2_CLUSTERID
+ * MPIDR[24] = MT
+ * MPIDR[29:25] = RES0
+ * MPIDR[30] = U
+ * MPIDR[31] = ME
+ * MPIDR[39:32] = AFF3
+ *
+ * Linear Processor ID (LPID) calculation from MPIDR_EL1:
+ * (We only use AFF0_CPUID and AFF1_CLUSTERID for now
+ * until AFF2_CLUSTERID and AFF3 have non-zero values)
+ *
+ * LPID = MPIDR[15:8] | MPIDR[1:0]
+ */
+ mrs x0, mpidr_el1
+ ubfm x1, x0, #8, #15
+ ubfm x2, x0, #0, #1
+ orr x10, x2, x1, lsl #2 /* x10 has LPID */
+ ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
+ /*
+ * offset of the spin table element for this core from start of spin
+ * table (each elem is padded to 64 bytes)
+ */
+ lsl x1, x10, #6
+ adr x0, __spin_table
+ /* physical address of this cpus spin table element */
+ add x11, x1, x0
+
+ adr x0, __real_cntfrq
+ ldr x0, [x0]
+ msr cntfrq_el0, x0 /* set with real frequency */
+ str x9, [x11, #16] /* LPID */
+ mov x4, #1
+ str x4, [x11, #8] /* STATUS */
+ dsb sy
+
+1:
+ wfe
+ ldr x4, [x11]
+ cbz x4, 1b
+ mrs x1, sctlr_el2
+ tbz x1, #25, 2f
+ rev x4, x4 /* BE to LE conversion */
+2:
+ ldr x6, =ES_TO_AARCH64
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+ adr x5, 3f
+ switch_el x7, 0f, _dead_loop, _dead_loop
+0: armv8_switch_to_el2_m x5, x6, x7
+#endif
+3:
+ ldr x7, [x11, #24] /* ARCH_COMP */
+ cbz x7, 4f
+ ldr x6, =ES_TO_AARCH32
+4:
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+ switch_el x7, _dead_loop, 0f, _dead_loop
+0: armv8_switch_to_el1_m x4, x6, x7
+#else
+ switch_el x7, 0f, _dead_loop, _dead_loop
+0: armv8_switch_to_el2_m x4, x6, x7
+#endif
+
+_dead_loop:
+ wfe
+ b _dead_loop
+
+ /* Ensure that the literals used by the secondary boot code are
+ * assembled within it (this is required so that we can protect
+ * this area with a single memreserve region
+ */
+ .ltorg
+
+ /* 64 bit alignment for elements accessed as data */
+ .align 3
+ .global __real_cntfrq
+__real_cntfrq:
+ .quad COUNTER_FREQUENCY
+ /* Secondary Boot Code ends here */
+__secondary_boot_code_end:
compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
aliases {
spi0 = &fspi;
+ spi1 = &dspi0;
+ spi2 = &dspi1;
+ spi3 = &dspi2;
};
};
&dspi0 {
+ bus-num = <0>;
status = "okay";
+
+ dflash0: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+
+ dflash1: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ };
+ dflash2: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ };
};
&dspi1 {
+ bus-num = <0>;
status = "okay";
+
+ dflash3: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+
+ dflash4: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ };
+ dflash5: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ };
};
&dspi2 {
+ bus-num = <0>;
status = "okay";
+
+ dflash8: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
};
&esdhc0 {
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
+ pcie_ep@3400000 {
+ compatible = "fsl,ls-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x80000
+ 0x00 0x034c0000 0x0 0x40000
+ 0x40 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "ctrl", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ big-endian;
+ };
+
pcie@3500000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
+ pcie_ep@3500000 {
+ compatible = "fsl,ls-pcie-ep";
+ reg = <0x00 0x03500000 0x0 0x80000
+ 0x00 0x035c0000 0x0 0x40000
+ 0x48 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "ctrl", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ big-endian;
+ };
+
pcie@3600000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
+ pcie_ep@3600000 {
+ compatible = "fsl,ls-pcie-ep";
+ reg = <0x00 0x03600000 0x0 0x80000
+ 0x00 0x036c0000 0x0 0x40000
+ 0x50 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "ctrl", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ big-endian;
+ };
+
sata: sata@3200000 {
compatible = "fsl,ls1046a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
phy-connection-type = "rgmii-id";
};
+&dspi0 {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash0: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+ dflash1: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ };
+ dflash2: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ };
+};
+
+&dspi1 {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash3: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+ dflash4: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ };
+ dflash5: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ };
+};
+
+&dspi2 {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash6: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+ dflash7: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ };
+ dflash8: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ };
+};
+
&emdio1 {
status = "okay";
};
#interrupt-cells = <2>;
};
+ watchdog@23a0000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x0 0x23a0000 0 0x1000>,
+ <0x0 0x2390000 0 0x1000>;
+ timeout-sec = <30>;
+ };
+
usb0: usb3@3100000 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */
0x00 0x03480000 0x0 0x40000 /* LUT registers */
0x00 0x034c0000 0x0 0x40000 /* PF control registers */
- 0x80 0x00000000 0x0 0x1000>; /* configuration space */
+ 0x80 0x00000000 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */
0x00 0x03580000 0x0 0x40000 /* LUT registers */
0x00 0x035c0000 0x0 0x40000 /* PF control registers */
- 0x88 0x00000000 0x0 0x1000>; /* configuration space */
+ 0x88 0x00000000 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */
0x00 0x03680000 0x0 0x40000 /* LUT registers */
0x00 0x036c0000 0x0 0x40000 /* PF control registers */
- 0x90 0x00000000 0x0 0x1000>; /* configuration space */
+ 0x90 0x00000000 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */
0x00 0x03780000 0x0 0x40000 /* LUT registers */
0x00 0x037c0000 0x0 0x40000 /* PF control registers */
- 0x98 0x00000000 0x0 0x1000>; /* configuration space */
+ 0x98 0x00000000 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */
0x00 0x03880000 0x0 0x40000 /* LUT registers */
0x00 0x038c0000 0x0 0x40000 /* PF control registers */
- 0xa0 0x00000000 0x0 0x1000>; /* configuration space */
+ 0xa0 0x00000000 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */
0x00 0x03980000 0x0 0x40000 /* LUT registers */
0x00 0x039c0000 0x0 0x40000 /* PF control registers */
- 0xa8 0x00000000 0x0 0x1000>; /* configuration space */
+ 0xa8 0x00000000 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+/*
+ * Dummy header file to enable CONFIG_OF_CONTROL.
+ * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
+ * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
+ * OF_CONTROL must have arch/gpio.h.
+ */
+
+#ifndef __ASM_ARCH_MX85XX_GPIO_H
+#define __ASM_ARCH_MX85XX_GPIO_H
+
+struct mpc8xxx_gpio_plat {
+ ulong addr;
+ ulong size;
+ uint ngpios;
+};
+
+#endif
#define id_to_core(x) ((x & 3) | (x >> 6))
#ifndef __ASSEMBLY__
-extern u64 __spin_table[];
extern u64 __real_cntfrq;
-extern u64 *secondary_boot_code;
-extern size_t __secondary_boot_code_size;
+extern void *secondary_boot_addr;
+extern void *secondary_boot_code_start;
+extern size_t secondary_boot_code_size;
#ifdef CONFIG_MP
int fsl_layerscape_wake_seconday_cores(void);
#else
static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; }
#endif
void *get_spin_tbl_addr(void);
-phys_addr_t determine_mp_bootpg(void);
-void secondary_boot_func(void);
int is_core_online(u64 cpu_id);
u32 cpu_pos_mask(void);
#endif
#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \
!defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM68360) && \
!defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \
- !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_LX2160A) && \
- !defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \
- !defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \
- !defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_LS1043A) && \
- !defined(CONFIG_ARCH_LS1046A) && !defined(CONFIG_ARCH_U8500) && \
- !defined(CONFIG_CORTINA_PLATFORM)
+ !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \
+ !defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM)
#include <asm/arch/gpio.h>
#endif
#include <asm-generic/gpio.h>
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2002-2010
+ * Copyright 2020 NXP
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
u32 sdhc_per_clk;
-#if defined(CONFIG_FSL_ESDHC_ADAPTER_IDENT)
- u8 sdhc_adapter;
-#endif
#endif
#if defined(CONFIG_MPC8xx)
unsigned long brg_clk;
#else
printf("Not implemented\n");
#endif
+ } else if (strcmp(argv[1], "xspi") == 0) {
+#ifdef QIXIS_LBMAP_XSPI
+ QIXIS_WRITE(rst_ctl, 0x30);
+ QIXIS_WRITE(rcfg_ctl, 0);
+ set_lbmap(QIXIS_LBMAP_XSPI);
+ set_rcw_src(QIXIS_RCW_SRC_XSPI);
+ qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+ QIXIS_RCFG_CTL_RECONFIG_IDLE);
+ qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+ QIXIS_RCFG_CTL_RECONFIG_START);
+#else
+ printf("Not implemented\n");
+#endif
} else if (strcmp(argv[1], "watchdog") == 0) {
static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
"1min", "2min", "4min", "8min"};
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2011 Freescale Semiconductor
+ * Copyright 2020 NXP
* Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
*
* This file provides support for the QIXIS of some Freescale reference boards.
u8 gdc;
u8 gdd; /* DCM Debug Data Register,0x17 */
u8 dmack;
- u8 res1[6];
+ u8 res1;
+ u8 sdhc1;
+ u8 sdhc2;
+ u8 stat_pres3;
+ u8 los_stat;
+ u8 usb_ctl;
u8 watch; /* Watchdog Register,0x1F */
u8 pwr_ctl[2]; /* Power Control Register,0x20 */
u8 res2[2];
#endif
/* Use for SDHC adapter card type identification and operation */
-#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
#define QIXIS_SDID_MASK 0x07
+
#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC45 0x1 /* eMMC Card Rev4.5 */
#define QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY 0x2 /* SD/MMC Legacy Card */
#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC44 0x3 /* eMMC Card Rev4.4 */
#define QIXIS_ESDHC_ADAPTER_TYPE_SD 0x6 /* SD Card Rev2.0 3.0 */
#define QIXIS_ESDHC_NO_ADAPTER 0x7 /* No Card is Present*/
+#define QIXIS_SDHC1_S1V3 0x80 /* SDHC1: SDHC1 3.3V power control */
+#define QIXIS_SDHC1_VS 0x30 /* BRDCFG11: route to SDHC1_VS */
+
#define QIXIS_SDCLKIN 0x08
#define QIXIS_SDCLKOUT 0x02
#define QIXIS_DAT5_6_7 0X02
#define QIXIS_DAT4 0X01
#define QIXIS_EVDD_BY_SDHC_VS 0x0c
-#endif
#endif
/* MAC2 */
pfe_set_phy_address_mode(priv->gemac_port,
CONFIG_PFE_EMAC2_PHY_ADDR,
- PHY_INTERFACE_MODE_RGMII_TXID);
+ PHY_INTERFACE_MODE_RGMII_ID);
}
break;
case 0x2208:
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
*/
#include <common.h>
#define CFG_UART_MUX_SHIFT 1
#define CFG_LPUART_EN 0x1
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+void i2c_early_init_f(void);
+#endif
+
#ifdef CONFIG_TFABOOT
struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
int board_early_init_f(void)
{
+ u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
#ifdef CONFIG_HAS_FSL_XHCI_USB
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
u8 uart;
#endif
-#ifdef CONFIG_SYS_I2C
+ /*
+ * Enable secure system counter for timer
+ */
+ out_le32(cntcr, 0x1);
+
#ifdef CONFIG_SYS_I2C_EARLY_INIT
i2c_early_init_f();
#endif
-#endif
fsl_lsch2_early_init_f();
#ifdef CONFIG_HAS_FSL_XHCI_USB
F: board/freescale/ls1046afrwy/ls1046afrwy.c
F: include/configs/ls1046afrwy.h
F: configs/ls1046afrwy_tfa_defconfig
+
+LS1046AFRWY_SECURE_BOOT BOARD
+M: Manish Tomar <manish.tomar@nxp.com>
+S: Maintained
+F: configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
*/
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+void i2c_early_init_f(void);
+#endif
+
#ifdef CONFIG_TFABOOT
struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
int board_early_init_f(void)
{
+ u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
#ifdef CONFIG_HAS_FSL_XHCI_USB
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
u8 uart;
#endif
-#ifdef CONFIG_SYS_I2C
+ /*
+ * Enable secure system counter for timer
+ */
+ out_le32(cntcr, 0x1);
+
#ifdef CONFIG_SYS_I2C_EARLY_INIT
i2c_early_init_f();
#endif
-#endif
fsl_lsch2_early_init_f();
#ifdef CONFIG_HAS_FSL_XHCI_USB
#include <fdt_support.h>
#include <linux/bitops.h>
#include <linux/libfdt.h>
+#include <linux/delay.h>
#include <fsl-mc/fsl_mc.h>
#include <env_internal.h>
#include <efi_loader.h>
*/
u8 qixis_esdhc_detect_quirk(void)
{
- /* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
+ /*
* SDHC1 Card ID:
* Specifies the type of card installed in the SDHC1 adapter slot.
* 000= (reserved)
* 110= SDCard V2/V3 adapter installed.
* 111= no adapter is installed.
*/
- return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
+ return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
QIXIS_ESDHC_NO_ADAPTER);
}
+static void esdhc_adapter_card_ident(void)
+{
+ u8 card_id, val;
+
+ val = QIXIS_READ(sdhc1);
+ card_id = val & QIXIS_SDID_MASK;
+
+ switch (card_id) {
+ case QIXIS_ESDHC_ADAPTER_TYPE_SD:
+ /* Power cycle to card */
+ val &= ~QIXIS_SDHC1_S1V3;
+ QIXIS_WRITE(sdhc1, val);
+ mdelay(1);
+ val |= QIXIS_SDHC1_S1V3;
+ QIXIS_WRITE(sdhc1, val);
+ /* Route to SDHC1_VS */
+ val = QIXIS_READ(brdcfg[11]);
+ val |= QIXIS_SDHC1_VS;
+ QIXIS_WRITE(brdcfg[11], val);
+ break;
+ default:
+ break;
+ }
+}
+
int config_board_mux(void)
{
u8 reg11, reg5, reg13;
return 0;
}
+
+int board_early_init_r(void)
+{
+ esdhc_adapter_card_ident();
+ return 0;
+}
#elif defined(CONFIG_TARGET_LX2160ARDB)
int config_board_mux(void)
{
return 0;
}
+static void esdhc_adapter_card_ident(void)
+{
+ u8 card_id, value;
+
+ card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
+
+ switch (card_id) {
+ case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
+ value = QIXIS_READ(brdcfg[5]);
+ value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
+ QIXIS_WRITE(brdcfg[5], value);
+ break;
+ case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
+ value = QIXIS_READ(pwr_ctl[1]);
+ value |= QIXIS_EVDD_BY_SDHC_VS;
+ QIXIS_WRITE(pwr_ctl[1], value);
+ break;
+ case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
+ value = QIXIS_READ(brdcfg[5]);
+ value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
+ QIXIS_WRITE(brdcfg[5], value);
+ break;
+ default:
+ break;
+ }
+}
+
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
brd_mux_lane_to_slot();
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
-
+ esdhc_adapter_card_ident();
return 0;
}
}
#endif
+#ifdef CONFIG_PCI_ENDPOINT
+static int initr_pci_ep(void)
+{
+ pci_ep_init();
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_PCI
static int initr_pci(void)
{
#ifdef CONFIG_BITBANGMII
initr_bbmii,
#endif
+#ifdef CONFIG_PCI_ENDPOINT
+ initr_pci_ep,
+#endif
#ifdef CONFIG_CMD_NET
INIT_FUNC_WATCHDOG_RESET
initr_net,
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046AFRWY=y
+CONFIG_TFABOOT=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x500000
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy"
+CONFIG_ENV_ADDR=0x40500000
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_SATA_CEVA=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
+CONFIG_MTD_RAW_NAND=y
+# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_VITESSE=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_SECURE_BOOT=y
+CONFIG_RSA=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_CMD_SETEXPR=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x20500000
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_ADDR=0x580500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_RC_GEN4=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_RC_GEN4=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
+CONFIG_FSL_DSPI=y
CONFIG_DM_SPI=y
CONFIG_NXP_FSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_WDT=y
+CONFIG_WDT_SBSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_RC_GEN4=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_RC_GEN4=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_WDT=y
+CONFIG_WDT_SBSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_RC_GEN4=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
Freescale esdhc-specific options
- - CONFIG_FSL_ESDHC_ADAPTER_IDENT
- Support Freescale adapter card type identification. This is implemented by
- operating Qixis FPGA relevant registers. The STAT_PRES1 register has SDHC
- Card ID[0:2] bits showing the type of card installed in the SDHC Adapter Slot.
-
- SDHC Card ID[0:2] Adapter Card Type
- 0b000 reserved
- 0b001 eMMC Card Rev4.5
- 0b010 SD/MMC Legacy Card
- 0b011 eMMC Card Rev4.4
- 0b100 reserved
- 0b101 MMC Card
- 0b110 SD Card Rev2.0/3.0
- 0b111 No card is present
- CONFIG_SYS_FSL_ESDHC_LE
ESDHC IP is in little-endian mode. Accessing ESDHC registers can be
determined by ESDHC IP's endian mode or processor's endian mode.
- ctar-params: CTAR0 to 7 register configuration, as an array
of 8 integer fields for each register, where each register
is defined as: <fmsz, pcssck, pasc, pdt, cssck, asc, dt, br>.
+- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
+ select and the start of clock signal, at the start of a transfer.
+- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
+ signal and deactivating chip select, at the end of a transfer.
Example:
config SYS_FSL_SEC_LE
bool "Little-endian access to Freescale Secure Boot"
+
+if FSL_CAAM
+
+config FSL_CAAM_RNG
+ bool "Enable Random Number Generator support"
+ depends on DM_RNG
+ default y
+ help
+ Enable support for the hardware based random number generator
+ module of the CAAM. The random data is fetched from the DRGB
+ using the prediction resistance flag which means the DRGB is
+ reseeded from the TRNG every time random data is generated.
+
+endif
obj-$(CONFIG_CMD_BLOB) += fsl_blob.o
obj-$(CONFIG_CMD_DEKBLOB) += fsl_blob.o
obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o
+obj-$(CONFIG_FSL_CAAM_RNG) += rng.o
#define OP_ALG_ICV_OFF (0 << OP_ALG_ICV_SHIFT)
#define OP_ALG_ICV_ON (1 << OP_ALG_ICV_SHIFT)
+#define OP_ALG_PR_ON 0x02
+
#define OP_ALG_DIR_SHIFT 0
#define OP_ALG_DIR_MASK 1
#define OP_ALG_DECRYPT 0
(LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
#ifdef CONFIG_PHYS_64BIT
-union ptr_addr_t {
- u64 m_whole;
- struct {
+struct ptr_addr_t {
#ifdef CONFIG_SYS_FSL_SEC_LE
- u32 low;
- u32 high;
+ u32 low;
+ u32 high;
#elif defined(CONFIG_SYS_FSL_SEC_BE)
- u32 high;
- u32 low;
+ u32 high;
+ u32 low;
#else
#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
#endif
- } m_halfs;
};
#endif
#ifdef CONFIG_PHYS_64BIT
/* The Position of low and high part of 64 bit address
* will depend on the endianness of CAAM Block */
- union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset;
- ptr_addr->m_halfs.high = (u32)(ptr >> 32);
- ptr_addr->m_halfs.low = (u32)ptr;
+ struct ptr_addr_t *ptr_addr = (struct ptr_addr_t *)offset;
+
+ ptr_addr->high = (u32)(ptr >> 32);
+ ptr_addr->low = (u32)ptr;
#else
*offset = ptr;
#endif
#ifdef CONFIG_PHYS_64BIT
/* The Position of low and high part of 64 bit address
* will depend on the endianness of CAAM Block */
- union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset;
- ptr_addr->m_halfs.high = (u32)(ptr >> 32);
- ptr_addr->m_halfs.low = (u32)ptr;
+ struct ptr_addr_t *ptr_addr = (struct ptr_addr_t *)offset;
+
+ ptr_addr->high = (u32)(ptr >> 32);
+ ptr_addr->low = (u32)ptr;
#else
*offset = ptr;
#endif
unsigned int size, int is_last,
enum caam_hash_algos caam_algo)
{
- uint32_t final = 0;
+ uint32_t final;
phys_addr_t addr = virt_to_phys((void *)buf);
struct sha_ctx *ctx = hash_ctx;
/* if the page is not owned => problem */
if ((temp_reg & SMCSJR_PO) != PAGE_OWNED) {
- printf("Allocation of page %d in partition %d failed 0x%X\n",
- temp_reg, page_num, partition_num);
+ printf("Allocation of page %u in partition %u failed 0x%X\n",
+ page_num, partition_num, temp_reg);
return ERROR_IN_PAGE_ALLOC;
}
* Descriptor to instantiate RNG State Handle 0 in normal mode and
* load the JDKEK, TDKEK and TDSK registers
*/
-void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc, int handle)
+void inline_cnstr_jobdesc_rng_instantiation(u32 *desc, int handle, int do_sk)
{
u32 *jump_cmd;
/* INIT RNG in non-test mode */
append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
- (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT);
+ (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT |
+ OP_ALG_PR_ON);
/* For SH0, Secure Keys must be generated as well */
- if (handle == 0) {
+ if (!handle && do_sk) {
/* wait for done */
jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
set_jump_tgt_here(desc, jump_cmd);
}
}
+/* Descriptor for deinstantiation of the RNG block. */
+void inline_cnstr_jobdesc_rng_deinstantiation(u32 *desc, int handle)
+{
+ init_job_desc(desc, 0);
+
+ append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
+ (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
+}
+
+void inline_cnstr_jobdesc_rng(u32 *desc, void *data_out, u32 size)
+{
+ dma_addr_t dma_data_out = virt_to_phys(data_out);
+
+ init_job_desc(desc, 0);
+ append_operation(desc, OP_ALG_ALGSEL_RNG | OP_TYPE_CLASS1_ALG |
+ OP_ALG_PR_ON);
+ append_fifo_store(desc, dma_data_out, size, FIFOST_TYPE_RNGSTORE);
+}
+
/* Change key size to bytes form bits in calling function*/
void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc,
struct pk_in_params *pkin, uint8_t *out,
uint8_t *enc_blob, uint8_t *plain_txt,
uint32_t out_sz);
-void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc, int handle);
+void inline_cnstr_jobdesc_rng_instantiation(u32 *desc, int handle, int do_sk);
+
+void inline_cnstr_jobdesc_rng_deinstantiation(u32 *desc, int handle);
+
+void inline_cnstr_jobdesc_rng(u32 *desc, void *data_out, u32 size);
void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc,
struct pk_in_params *pkin, uint8_t *out,
uint32_t out_siz);
+
#endif
#include <common.h>
#include <cpu_func.h>
+#include <linux/kernel.h>
#include <log.h>
#include <malloc.h>
#include "fsl_sec.h"
#include <asm/cache.h>
#include <asm/fsl_pamu.h>
#endif
+#include <dm/lists.h>
#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
return sec_reset_idx(0);
}
#ifndef CONFIG_SPL_BUILD
-static int instantiate_rng(uint8_t sec_idx)
+static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
+{
+ u32 *desc;
+ int sh_idx, ret = 0;
+ int desc_size = ALIGN(sizeof(u32) * 2, ARCH_DMA_MINALIGN);
+
+ desc = memalign(ARCH_DMA_MINALIGN, desc_size);
+ if (!desc) {
+ debug("cannot allocate RNG init descriptor memory\n");
+ return -ENOMEM;
+ }
+
+ for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
+ /*
+ * If the corresponding bit is set, then it means the state
+ * handle was initialized by us, and thus it needs to be
+ * deinitialized as well
+ */
+
+ if (state_handle_mask & RDSTA_IF(sh_idx)) {
+ /*
+ * Create the descriptor for deinstantating this state
+ * handle.
+ */
+ inline_cnstr_jobdesc_rng_deinstantiation(desc, sh_idx);
+ flush_dcache_range((unsigned long)desc,
+ (unsigned long)desc + desc_size);
+
+ ret = run_descriptor_jr_idx(desc, sec_idx);
+ if (ret) {
+ printf("SEC%u: RNG4 SH%d deinstantiation failed with error 0x%x\n",
+ sec_idx, sh_idx, ret);
+ ret = -EIO;
+ break;
+ }
+
+ printf("SEC%u: Deinstantiated RNG4 SH%d\n",
+ sec_idx, sh_idx);
+ }
+ }
+
+ free(desc);
+ return ret;
+}
+
+static int instantiate_rng(u8 sec_idx, int gen_sk)
{
u32 *desc;
u32 rdsta_val;
* If the corresponding bit is set, this state handle
* was initialized by somebody else, so it's left alone.
*/
- rdsta_val = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK;
- if (rdsta_val & (1 << sh_idx))
- continue;
+ rdsta_val = sec_in32(&rng->rdsta);
+ if (rdsta_val & (RDSTA_IF(sh_idx))) {
+ if (rdsta_val & RDSTA_PR(sh_idx))
+ continue;
+
+ printf("SEC%u: RNG4 SH%d was instantiated w/o prediction resistance. Tearing it down\n",
+ sec_idx, sh_idx);
- inline_cnstr_jobdesc_rng_instantiation(desc, sh_idx);
+ ret = deinstantiate_rng(sec_idx, RDSTA_IF(sh_idx));
+ if (ret)
+ break;
+ }
+
+ inline_cnstr_jobdesc_rng_instantiation(desc, sh_idx, gen_sk);
size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
flush_dcache_range((unsigned long)desc,
(unsigned long)desc + size);
ret = run_descriptor_jr_idx(desc, sec_idx);
if (ret)
- printf("RNG: Instantiation failed with error 0x%x\n",
- ret);
+ printf("SEC%u: RNG4 SH%d instantiation failed with error 0x%x\n",
+ sec_idx, sh_idx, ret);
- rdsta_val = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK;
- if (!(rdsta_val & (1 << sh_idx))) {
+ rdsta_val = sec_in32(&rng->rdsta);
+ if (!(rdsta_val & RDSTA_IF(sh_idx))) {
free(desc);
return -1;
}
static u8 get_rng_vid(uint8_t sec_idx)
{
ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
- u32 cha_vid = sec_in32(&sec->chavid_ls);
+ u8 vid;
+
+ if (caam_get_era() < 10) {
+ vid = (sec_in32(&sec->chavid_ls) & SEC_CHAVID_RNG_LS_MASK)
+ >> SEC_CHAVID_LS_RNG_SHIFT;
+ } else {
+ vid = (sec_in32(&sec->vreg.rng) & CHA_VER_VID_MASK)
+ >> CHA_VER_VID_SHIFT;
+ }
- return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
+ return vid;
}
/*
static int rng_init(uint8_t sec_idx)
{
- int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
+ int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
u32 inst_handles;
+ gen_sk = !(sec_in32(&rng->rdsta) & RDSTA_SKVN);
do {
- inst_handles = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK;
+ inst_handles = sec_in32(&rng->rdsta) & RDSTA_MASK;
/*
* If either of the SH's were instantiated by somebody else
* interval, leading to a sucessful initialization of
* the RNG.
*/
- ret = instantiate_rng(sec_idx);
+ ret = instantiate_rng(sec_idx, gen_sk);
} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
if (ret) {
- printf("RNG: Failed to instantiate RNG\n");
+ printf("SEC%u: Failed to instantiate RNG\n", sec_idx);
return ret;
}
#endif
if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) {
- printf("SEC initialization failed\n");
+ printf("SEC%u: initialization failed\n", sec_idx);
return -1;
}
ret = jr_init(sec_idx);
if (ret < 0) {
- printf("SEC initialization failed\n");
+ printf("SEC%u: initialization failed\n", sec_idx);
return -1;
}
#ifndef CONFIG_SPL_BUILD
if (get_rng_vid(sec_idx) >= 4) {
if (rng_init(sec_idx) < 0) {
- printf("SEC%u: RNG instantiation failed\n", sec_idx);
+ printf("SEC%u: RNG instantiation failed\n", sec_idx);
return -1;
}
- printf("SEC%u: RNG instantiated\n", sec_idx);
+
+ if (IS_ENABLED(CONFIG_DM_RNG)) {
+ ret = device_bind_driver(NULL, "caam-rng", "caam-rng",
+ NULL);
+ if (ret)
+ printf("Couldn't bind rng driver (%d)\n", ret);
+ }
+
+ printf("SEC%u: RNG instantiated\n", sec_idx);
}
#endif
return ret;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 Michael Walle <michael@walle.cc>
+ *
+ * Driver for Freescale Cryptographic Accelerator and Assurance
+ * Module (CAAM) hardware random number generator.
+ */
+
+#include <asm/cache.h>
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <rng.h>
+#include <linux/kernel.h>
+#include "desc_constr.h"
+#include "jobdesc.h"
+#include "jr.h"
+
+#define CAAM_RNG_MAX_FIFO_STORE_SIZE 16
+#define CAAM_RNG_DESC_LEN (3 * CAAM_CMD_SZ + CAAM_PTR_SZ)
+
+struct caam_rng_priv {
+ u32 desc[CAAM_RNG_DESC_LEN / 4];
+ u8 data[CAAM_RNG_MAX_FIFO_STORE_SIZE] __aligned(ARCH_DMA_MINALIGN);
+};
+
+static int caam_rng_read_one(struct caam_rng_priv *priv)
+{
+ int size = ALIGN(CAAM_RNG_MAX_FIFO_STORE_SIZE, ARCH_DMA_MINALIGN);
+ int ret;
+
+ ret = run_descriptor_jr(priv->desc);
+ if (ret < 0)
+ return -EIO;
+
+ invalidate_dcache_range((unsigned long)priv->data,
+ (unsigned long)priv->data + size);
+
+ return 0;
+}
+
+static int caam_rng_read(struct udevice *dev, void *data, size_t len)
+{
+ struct caam_rng_priv *priv = dev_get_priv(dev);
+ u8 *buffer = data;
+ size_t size;
+ int ret;
+
+ while (len) {
+ ret = caam_rng_read_one(priv);
+ if (ret)
+ return ret;
+
+ size = min(len, (size_t)CAAM_RNG_MAX_FIFO_STORE_SIZE);
+
+ memcpy(buffer, priv->data, size);
+ buffer += size;
+ len -= size;
+ }
+
+ return 0;
+}
+
+static int caam_rng_probe(struct udevice *dev)
+{
+ struct caam_rng_priv *priv = dev_get_priv(dev);
+ ulong size = ALIGN(CAAM_RNG_DESC_LEN, ARCH_DMA_MINALIGN);
+
+ inline_cnstr_jobdesc_rng(priv->desc, priv->data,
+ CAAM_RNG_MAX_FIFO_STORE_SIZE);
+ flush_dcache_range((unsigned long)priv->desc,
+ (unsigned long)priv->desc + size);
+
+ return 0;
+}
+
+static const struct dm_rng_ops caam_rng_ops = {
+ .read = caam_rng_read,
+};
+
+U_BOOT_DRIVER(caam_rng) = {
+ .name = "caam-rng",
+ .id = UCLASS_RNG,
+ .ops = &caam_rng_ops,
+ .probe = caam_rng_probe,
+ .priv_auto_alloc_size = sizeof(struct caam_rng_priv),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
fdt_strerror(err));
}
#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* SEC4 */
-static u8 caam_get_era(void)
+/**
+ * caam_get_era() - fetch the CAAM's era
+ *
+ * The SEC module povides an "Era" which can be used to differentiate
+ * between different revisions.
+ *
+ * Return: era of the SEC.
+ */
+u8 caam_get_era(void)
{
static const struct {
u16 ip_id;
*
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
* (c) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright 2020 NXP
*
* Based on i2c-imx.c from linux kernel:
* Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
return 0;
}
+#if !defined(I2C2_BASE_ADDR)
+#define I2C2_BASE_ADDR 0
+#endif
+
+#if !defined(I2C3_BASE_ADDR)
+#define I2C3_BASE_ADDR 0
+#endif
+
+#if !defined(I2C4_BASE_ADDR)
+#define I2C4_BASE_ADDR 0
+#endif
+
+#if !defined(I2C5_BASE_ADDR)
+#define I2C5_BASE_ADDR 0
+#endif
+
+#if !defined(I2C6_BASE_ADDR)
+#define I2C6_BASE_ADDR 0
+#endif
+
+#if !defined(I2C7_BASE_ADDR)
+#define I2C7_BASE_ADDR 0
+#endif
+
+#if !defined(I2C8_BASE_ADDR)
+#define I2C8_BASE_ADDR 0
+#endif
+
+static struct mxc_i2c_bus mxc_i2c_buses[] = {
+#if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
+ defined(CONFIG_FSL_LAYERSCAPE)
+ { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
+ { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
+ { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
+ { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
+ { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
+ { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
+ { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
+ { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
+#else
+ { 0, I2C1_BASE_ADDR, 0 },
+ { 1, I2C2_BASE_ADDR, 0 },
+ { 2, I2C3_BASE_ADDR, 0 },
+ { 3, I2C4_BASE_ADDR, 0 },
+ { 4, I2C5_BASE_ADDR, 0 },
+ { 5, I2C6_BASE_ADDR, 0 },
+ { 6, I2C7_BASE_ADDR, 0 },
+ { 7, I2C8_BASE_ADDR, 0 },
+#endif
+};
+
#ifndef CONFIG_DM_I2C
int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
{
return ret;
}
#endif
+/*
+ * Early init I2C for prepare read the clk through I2C.
+ */
+void i2c_early_init_f(void)
+{
+ ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
+ bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
+ & I2C_QUIRK_FLAG ? true : false;
+ int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
+
+ /* Set I2C divider value */
+ writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
+ /* Reset module */
+ writeb(I2CR_IDIS, base + (I2CR << reg_shift));
+ writeb(0, base + (I2SR << reg_shift));
+ /* Enable I2C */
+ writeb(I2CR_IEN, base + (I2CR << reg_shift));
+}
static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
u32 addr, int alen)
return ret;
}
-#if !defined(I2C2_BASE_ADDR)
-#define I2C2_BASE_ADDR 0
-#endif
-
-#if !defined(I2C3_BASE_ADDR)
-#define I2C3_BASE_ADDR 0
-#endif
-
-#if !defined(I2C4_BASE_ADDR)
-#define I2C4_BASE_ADDR 0
-#endif
-
-#if !defined(I2C5_BASE_ADDR)
-#define I2C5_BASE_ADDR 0
-#endif
-
-#if !defined(I2C6_BASE_ADDR)
-#define I2C6_BASE_ADDR 0
-#endif
-
-#if !defined(I2C7_BASE_ADDR)
-#define I2C7_BASE_ADDR 0
-#endif
-
-#if !defined(I2C8_BASE_ADDR)
-#define I2C8_BASE_ADDR 0
-#endif
-
-static struct mxc_i2c_bus mxc_i2c_buses[] = {
-#if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
- defined(CONFIG_FSL_LAYERSCAPE)
- { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
- { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
- { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
- { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
- { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
- { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
- { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
- { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
-#else
- { 0, I2C1_BASE_ADDR, 0 },
- { 1, I2C2_BASE_ADDR, 0 },
- { 2, I2C3_BASE_ADDR, 0 },
- { 3, I2C4_BASE_ADDR, 0 },
- { 4, I2C5_BASE_ADDR, 0 },
- { 5, I2C6_BASE_ADDR, 0 },
- { 6, I2C7_BASE_ADDR, 0 },
- { 7, I2C8_BASE_ADDR, 0 },
-#endif
-};
-
struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
{
return &mxc_i2c_buses[adap->hwadapnr];
bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
}
-/*
- * Early init I2C for prepare read the clk through I2C.
- */
-void i2c_early_init_f(void)
-{
- ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
- bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
- & I2C_QUIRK_FLAG ? true : false;
- int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
- /* Set I2C divider value */
- writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
- /* Reset module */
- writeb(I2CR_IDIS, base + (I2CR << reg_shift));
- writeb(0, base + (I2SR << reg_shift));
- /* Enable I2C */
- writeb(I2CR_IEN, base + (I2CR << reg_shift));
-}
/*
* Init I2C Bus
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
}
-#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
-void mmc_adapter_card_type_ident(void)
-{
- u8 card_id;
- u8 value;
-
- card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
- gd->arch.sdhc_adapter = card_id;
-
- switch (card_id) {
- case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
- value = QIXIS_READ(brdcfg[5]);
- value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
- QIXIS_WRITE(brdcfg[5], value);
- break;
- case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
- value = QIXIS_READ(pwr_ctl[1]);
- value |= QIXIS_EVDD_BY_SDHC_VS;
- QIXIS_WRITE(pwr_ctl[1], value);
- break;
- case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
- value = QIXIS_READ(brdcfg[5]);
- value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
- QIXIS_WRITE(brdcfg[5], value);
- break;
- case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
- break;
- case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
- break;
- case QIXIS_ESDHC_ADAPTER_TYPE_SD:
- break;
- case QIXIS_ESDHC_NO_ADAPTER:
- break;
- default:
- break;
- }
-}
-#endif
-
#ifdef CONFIG_OF_LIBFDT
__weak int esdhc_status_fixup(void *blob, const char *compat)
{
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Google, Inc
+ * Copyright 2020 NXP
* Written by Simon Glass <sjg@chromium.org>
*/
if (!m)
continue;
-#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
- mmc_set_preinit(m, 1);
-#endif
if (m->preinit)
mmc_start_init(m);
}
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2008, Freescale Semiconductor, Inc
+ * Copyright 2020 NXP
* Andy Fleming
*
* Based vaguely on the Linux code
if (mmc->has_init)
return 0;
-#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
- mmc_adapter_card_type_ident();
-#endif
err = mmc_power_init(mmc);
if (err)
return err;
m = mmc_get_mmc_dev(dev);
if (!m)
return 0;
-#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
- mmc_set_preinit(m, 1);
-#endif
if (m->preinit)
mmc_start_init(m);
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Google, Inc
+ * Copyright 2020 NXP
* Written by Simon Glass <sjg@chromium.org>
*/
void mmc_do_preinit(void)
{
struct mmc *m = &mmc_static;
-#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
- mmc_set_preinit(m, 1);
-#endif
if (m->preinit)
mmc_start_init(m);
}
list_for_each(entry, &mmc_devices) {
m = list_entry(entry, struct mmc, link);
-#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
- mmc_set_preinit(m, 1);
-#endif
if (m->preinit)
mmc_start_init(m);
}
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2008,2010 Freescale Semiconductor, Inc
+ * Copyright 2020 NXP
* Andy Fleming
*
* Based (loosely) on the Linux code
int mmc_poll_for_busy(struct mmc *mmc, int timeout);
int mmc_set_blocklen(struct mmc *mmc, int len);
-#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
-void mmc_adapter_card_type_ident(void);
-#endif
#if CONFIG_IS_ENABLED(BLK)
ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
/* phy iface */
.phy_address = CONFIG_PFE_EMAC2_PHY_ADDR,
- .phy_mode = PHY_INTERFACE_MODE_RGMII_TXID,
+ .phy_mode = PHY_INTERFACE_MODE_RGMII_ID,
},
};
#include <linux/bitops.h>
#include <net/pfe_eth/pfe_eth.h>
#include <net/pfe_eth/pfe_firmware.h>
+#include <spi_flash.h>
#ifdef CONFIG_CHAIN_OF_TRUST
#include <fsl_validate.h>
#endif
#define PFE_FIRMWARE_FIT_CNF_NAME "config@1"
-static const void *pfe_fit_addr = (void *)CONFIG_SYS_LS_PFE_FW_ADDR;
+static const void *pfe_fit_addr;
/*
* PFE elf firmware loader.
return ret;
}
+int pfe_spi_flash_init(void)
+{
+ struct spi_flash *pfe_flash;
+ int ret = 0;
+ void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+
+#ifdef CONFIG_DM_SPI_FLASH
+ struct udevice *new;
+
+ /* speed and mode will be read from DT */
+ ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS,
+ CONFIG_ENV_SPI_CS, 0, 0, &new);
+
+ pfe_flash = dev_get_uclass_priv(new);
+#else
+ pfe_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
+ CONFIG_ENV_SPI_CS,
+ CONFIG_ENV_SPI_MAX_HZ,
+ CONFIG_ENV_SPI_MODE);
+#endif
+ if (!pfe_flash) {
+ printf("SF: probe for pfe failed\n");
+ return -ENODEV;
+ }
+
+ ret = spi_flash_read(pfe_flash,
+ CONFIG_SYS_LS_PFE_FW_ADDR,
+ CONFIG_SYS_QE_FMAN_FW_LENGTH,
+ addr);
+ if (ret)
+ printf("SF: read for pfe failed\n");
+
+ pfe_fit_addr = addr;
+ spi_flash_free(pfe_flash);
+
+ return ret;
+}
+
/*
* PFE firmware initialization.
* Loads different firmware files from FIT image.
int ret = 0;
int fw_count;
+ ret = pfe_spi_flash_init();
+ if (ret)
+ goto err;
+
ret = pfe_fit_check();
if (ret)
goto err;
which can be used on some generations of Xilinx FPGAs.
config PCIE_LAYERSCAPE
- bool "Layerscape PCIe support"
+ bool
+ default n
+
+config PCIE_LAYERSCAPE_RC
+ bool "Layerscape PCIe Root Complex mode support"
+ depends on DM_PCI
+ select PCIE_LAYERSCAPE
+ help
+ Enable Layerscape PCIe Root Complex mode driver support. The Layerscape
+ SoC may have one or several PCIe controllers. Each controller can be
+ configured to Root Complex mode by clearing the corresponding bit of
+ RCW[HOST_AGT_PEX].
+
+config PCIE_LAYERSCAPE_EP
+ bool "Layerscape PCIe Endpoint mode support"
depends on DM_PCI
+ select PCIE_LAYERSCAPE
+ select PCI_ENDPOINT
help
- Support Layerscape PCIe. The Layerscape SoC may have one or several
- PCIe controllers. The PCIe may works in RC or EP mode according to
- RCW[HOST_AGT_PEX] setting.
+ Enable Layerscape PCIe Endpoint mode driver support. The Layerscape
+ SoC may have one or several PCIe controllers. Each controller can be
+ configured to Endpoint mode by setting the corresponding bit of
+ RCW[HOST_AGT_PEX].
config PCIE_LAYERSCAPE_GEN4
bool "Layerscape Gen4 PCIe support"
config FSL_PCIE_COMPAT
string "PCIe compatible of Kernel DT"
- depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
+ depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4
default "fsl,ls1012a-pcie" if ARCH_LS1012A
default "fsl,ls1028a-pcie" if ARCH_LS1028A
default "fsl,ls1043a-pcie" if ARCH_LS1043A
config FSL_PCIE_EP_COMPAT
string "PCIe EP compatible of Kernel DT"
- depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
+ depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4
default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A
default "fsl,ls-pcie-ep"
help
obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
obj-$(CONFIG_PCIE_FSL) += pcie_fsl.o pcie_fsl_fixup.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
-obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o pcie_layerscape_fixup_common.o
+obj-$(CONFIG_PCIE_LAYERSCAPE_RC) += pcie_layerscape_rc.o \
+ pcie_layerscape_fixup.o \
+ pcie_layerscape_fixup_common.o
+obj-$(CONFIG_PCIE_LAYERSCAPE_EP) += pcie_layerscape_ep.o
obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
pcie_layerscape_gen4_fixup.o \
pcie_layerscape_fixup_common.o
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Layerscape PCIe driver
*/
#include <common.h>
#include <log.h>
-#include <asm/arch/fsl_serdes.h>
-#include <pci.h>
#include <asm/io.h>
#include <errno.h>
#include <malloc.h>
-#include <dm.h>
#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
defined(CONFIG_ARM)
#include <asm/arch/clock.h>
LIST_HEAD(ls_pcie_list);
-static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
+unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
{
return in_le32(pcie->dbi + offset);
}
-static void dbi_writel(struct ls_pcie *pcie, unsigned int value,
- unsigned int offset)
+void dbi_writel(struct ls_pcie *pcie, unsigned int value, unsigned int offset)
{
out_le32(pcie->dbi + offset, value);
}
-static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
+unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
{
if (pcie->big_endian)
return in_be32(pcie->ctrl + offset);
return in_le32(pcie->ctrl + offset);
}
-static void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
- unsigned int offset)
+void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
+ unsigned int offset)
{
if (pcie->big_endian)
out_be32(pcie->ctrl + offset, value);
out_le32(pcie->ctrl + offset, value);
}
+void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie)
+{
+ u32 reg, val;
+
+ reg = PCIE_MISC_CONTROL_1_OFF;
+ val = dbi_readl(pcie, reg);
+ val |= PCIE_DBI_RO_WR_EN;
+ dbi_writel(pcie, val, reg);
+}
+
+void ls_pcie_dbi_ro_wr_dis(struct ls_pcie *pcie)
+{
+ u32 reg, val;
+
+ reg = PCIE_MISC_CONTROL_1_OFF;
+ val = dbi_readl(pcie, reg);
+ val &= ~PCIE_DBI_RO_WR_EN;
+ dbi_writel(pcie, val, reg);
+}
+
static int ls_pcie_ltssm(struct ls_pcie *pcie)
{
u32 state;
return state;
}
-static int ls_pcie_link_up(struct ls_pcie *pcie)
+int ls_pcie_link_up(struct ls_pcie *pcie)
{
int ltssm;
return 1;
}
-static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
-{
- dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_VIEWPORT);
- dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
-}
-
-static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
-{
- dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
- PCIE_ATU_VIEWPORT);
- dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
-}
-
-static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
- u64 phys, u64 bus_addr, pci_size_t size)
+void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
+ u64 phys, u64 bus_addr, u64 size)
{
dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT);
dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE);
}
/* Use bar match mode and MEM type as default */
-static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx,
- int bar, u64 phys)
+void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
+ int type, int idx, int bar, u64 phys)
{
dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
- dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
+ dbi_writel(pcie, type | PCIE_ATU_FUNC_NUM(pf), PCIE_ATU_CR1);
dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
+ (vf_flag ? PCIE_ATU_FUNC_NUM_MATCH_EN : 0) |
+ (vf_flag ? PCIE_ATU_VFBAR_MATCH_MODE_EN : 0) |
PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
}
-static void ls_pcie_dump_atu(struct ls_pcie *pcie)
+void ls_pcie_dump_atu(struct ls_pcie *pcie, u32 win_num, u32 type)
{
- int i;
+ int win_idx;
- for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
- dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
- PCIE_ATU_VIEWPORT);
- debug("iATU%d:\n", i);
+ for (win_idx = 0; win_idx < win_num; win_idx++) {
+ dbi_writel(pcie, type | win_idx, PCIE_ATU_VIEWPORT);
+ debug("iATU%d:\n", win_idx);
debug("\tLOWER PHYS 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
debug("\tUPPER PHYS 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
- debug("\tLOWER BUS 0x%08x\n",
- dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
- debug("\tUPPER BUS 0x%08x\n",
- dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
- debug("\tLIMIT 0x%08x\n",
- readl(pcie->dbi + PCIE_ATU_LIMIT));
+ if (type == PCIE_ATU_REGION_OUTBOUND) {
+ debug("\tLOWER BUS 0x%08x\n",
+ dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
+ debug("\tUPPER BUS 0x%08x\n",
+ dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
+ debug("\tLIMIT 0x%08x\n",
+ dbi_readl(pcie, PCIE_ATU_LIMIT));
+ }
debug("\tCR1 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_CR1));
debug("\tCR2 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_CR2));
}
}
-
-static void ls_pcie_setup_atu(struct ls_pcie *pcie)
-{
- struct pci_region *io, *mem, *pref;
- unsigned long long offset = 0;
- int idx = 0;
- uint svr;
-
- svr = get_svr();
- if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
- offset = LS1021_PCIE_SPACE_OFFSET +
- LS1021_PCIE_SPACE_SIZE * pcie->idx;
- }
-
- /* ATU 0 : OUTBOUND : CFG0 */
- ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_TYPE_CFG0,
- pcie->cfg_res.start + offset,
- 0,
- fdt_resource_size(&pcie->cfg_res) / 2);
- /* ATU 1 : OUTBOUND : CFG1 */
- ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
- PCIE_ATU_TYPE_CFG1,
- pcie->cfg_res.start + offset +
- fdt_resource_size(&pcie->cfg_res) / 2,
- 0,
- fdt_resource_size(&pcie->cfg_res) / 2);
-
- pci_get_regions(pcie->bus, &io, &mem, &pref);
- idx = PCIE_ATU_REGION_INDEX1 + 1;
-
- /* Fix the pcie memory map for LS2088A series SoCs */
- svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
- if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
- svr == SVR_LS2048A || svr == SVR_LS2044A ||
- svr == SVR_LS2081A || svr == SVR_LS2041A) {
- if (io)
- io->phys_start = (io->phys_start &
- (PCIE_PHYS_SIZE - 1)) +
- LS2088A_PCIE1_PHYS_ADDR +
- LS2088A_PCIE_PHYS_SIZE * pcie->idx;
- if (mem)
- mem->phys_start = (mem->phys_start &
- (PCIE_PHYS_SIZE - 1)) +
- LS2088A_PCIE1_PHYS_ADDR +
- LS2088A_PCIE_PHYS_SIZE * pcie->idx;
- if (pref)
- pref->phys_start = (pref->phys_start &
- (PCIE_PHYS_SIZE - 1)) +
- LS2088A_PCIE1_PHYS_ADDR +
- LS2088A_PCIE_PHYS_SIZE * pcie->idx;
- }
-
- if (io)
- /* ATU : OUTBOUND : IO */
- ls_pcie_atu_outbound_set(pcie, idx++,
- PCIE_ATU_TYPE_IO,
- io->phys_start + offset,
- io->bus_start,
- io->size);
-
- if (mem)
- /* ATU : OUTBOUND : MEM */
- ls_pcie_atu_outbound_set(pcie, idx++,
- PCIE_ATU_TYPE_MEM,
- mem->phys_start + offset,
- mem->bus_start,
- mem->size);
-
- if (pref)
- /* ATU : OUTBOUND : pref */
- ls_pcie_atu_outbound_set(pcie, idx++,
- PCIE_ATU_TYPE_MEM,
- pref->phys_start + offset,
- pref->bus_start,
- pref->size);
-
- ls_pcie_dump_atu(pcie);
-}
-
-/* Return 0 if the address is valid, -errno if not valid */
-static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf)
-{
- struct udevice *bus = pcie->bus;
-
- if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
- return -ENODEV;
-
- if (!pcie->enabled)
- return -ENXIO;
-
- if (PCI_BUS(bdf) < bus->seq)
- return -EINVAL;
-
- if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie)))
- return -EINVAL;
-
- if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
- return -EINVAL;
-
- return 0;
-}
-
-int ls_pcie_conf_address(const struct udevice *bus, pci_dev_t bdf,
- uint offset, void **paddress)
-{
- struct ls_pcie *pcie = dev_get_priv(bus);
- u32 busdev;
-
- if (ls_pcie_addr_valid(pcie, bdf))
- return -EINVAL;
-
- if (PCI_BUS(bdf) == bus->seq) {
- *paddress = pcie->dbi + offset;
- return 0;
- }
-
- busdev = PCIE_ATU_BUS(PCI_BUS(bdf) - bus->seq) |
- PCIE_ATU_DEV(PCI_DEV(bdf)) |
- PCIE_ATU_FUNC(PCI_FUNC(bdf));
-
- if (PCI_BUS(bdf) == bus->seq + 1) {
- ls_pcie_cfg0_set_busdev(pcie, busdev);
- *paddress = pcie->cfg0 + offset;
- } else {
- ls_pcie_cfg1_set_busdev(pcie, busdev);
- *paddress = pcie->cfg1 + offset;
- }
- return 0;
-}
-
-static int ls_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
- uint offset, ulong *valuep,
- enum pci_size_t size)
-{
- return pci_generic_mmap_read_config(bus, ls_pcie_conf_address,
- bdf, offset, valuep, size);
-}
-
-static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
- uint offset, ulong value,
- enum pci_size_t size)
-{
- return pci_generic_mmap_write_config(bus, ls_pcie_conf_address,
- bdf, offset, value, size);
-}
-
-/* Clear multi-function bit */
-static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
-{
- writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
-}
-
-/* Fix class value */
-static void ls_pcie_fix_class(struct ls_pcie *pcie)
-{
- writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
-}
-
-/* Drop MSG TLP except for Vendor MSG */
-static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
-{
- u32 val;
-
- val = dbi_readl(pcie, PCIE_STRFMR1);
- val &= 0xDFFFFFFF;
- dbi_writel(pcie, val, PCIE_STRFMR1);
-}
-
-/* Disable all bars in RC mode */
-static void ls_pcie_disable_bars(struct ls_pcie *pcie)
-{
- dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
- dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
- dbi_writel(pcie, 0xfffffffe, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
-}
-
-static void ls_pcie_setup_ctrl(struct ls_pcie *pcie)
-{
- ls_pcie_setup_atu(pcie);
-
- dbi_writel(pcie, 1, PCIE_DBI_RO_WR_EN);
- ls_pcie_fix_class(pcie);
- ls_pcie_clear_multifunction(pcie);
- ls_pcie_drop_msg_tlp(pcie);
- dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN);
-
- ls_pcie_disable_bars(pcie);
- pcie->stream_id_cur = 0;
-}
-
-static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie)
-{
- u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
-
- /* ATU 0 : INBOUND : map BAR0 */
- ls_pcie_atu_inbound_set(pcie, 0, 0, phys);
- /* ATU 1 : INBOUND : map BAR1 */
- phys += PCIE_BAR1_SIZE;
- ls_pcie_atu_inbound_set(pcie, 1, 1, phys);
- /* ATU 2 : INBOUND : map BAR2 */
- phys += PCIE_BAR2_SIZE;
- ls_pcie_atu_inbound_set(pcie, 2, 2, phys);
- /* ATU 3 : INBOUND : map BAR4 */
- phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
- ls_pcie_atu_inbound_set(pcie, 3, 4, phys);
-
- /* ATU 0 : OUTBOUND : map MEM */
- ls_pcie_atu_outbound_set(pcie, 0,
- PCIE_ATU_TYPE_MEM,
- pcie->cfg_res.start,
- 0,
- CONFIG_SYS_PCI_MEMORY_SIZE);
-}
-
-/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
-static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
-{
- /* The least inbound window is 4KiB */
- if (size < 4 * 1024)
- return;
-
- switch (bar) {
- case 0:
- writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
- break;
- case 1:
- writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
- break;
- case 2:
- writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
- writel(0, bar_base + PCI_BASE_ADDRESS_3);
- break;
- case 4:
- writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
- writel(0, bar_base + PCI_BASE_ADDRESS_5);
- break;
- default:
- break;
- }
-}
-
-static void ls_pcie_ep_setup_bars(void *bar_base)
-{
- /* BAR0 - 32bit - 4K configuration */
- ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
- /* BAR1 - 32bit - 8K MSIX*/
- ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
- /* BAR2 - 64bit - 4K MEM desciptor */
- ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
- /* BAR4 - 64bit - 1M MEM*/
- ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
-}
-
-static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
-{
- u32 config;
-
- config = ctrl_readl(pcie, PCIE_PF_CONFIG);
- config |= PCIE_CONFIG_READY;
- ctrl_writel(pcie, config, PCIE_PF_CONFIG);
-}
-
-static void ls_pcie_setup_ep(struct ls_pcie *pcie)
-{
- u32 sriov;
-
- sriov = readl(pcie->dbi + PCIE_SRIOV);
- if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
- int pf, vf;
-
- for (pf = 0; pf < PCIE_PF_NUM; pf++) {
- for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
- ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf),
- PCIE_PF_VF_CTRL);
-
- ls_pcie_ep_setup_bars(pcie->dbi);
- ls_pcie_ep_setup_atu(pcie);
- }
- }
- /* Disable CFG2 */
- ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
- } else {
- ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
- ls_pcie_ep_setup_atu(pcie);
- }
-
- ls_pcie_ep_enable_cfg(pcie);
-}
-
-static int ls_pcie_probe(struct udevice *dev)
-{
- struct ls_pcie *pcie = dev_get_priv(dev);
- const void *fdt = gd->fdt_blob;
- int node = dev_of_offset(dev);
- u16 link_sta;
- uint svr;
- int ret;
- fdt_size_t cfg_size;
-
- pcie->bus = dev;
-
- ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
- "dbi", &pcie->dbi_res);
- if (ret) {
- printf("ls-pcie: resource \"dbi\" not found\n");
- return ret;
- }
-
- pcie->idx = (pcie->dbi_res.start - PCIE_SYS_BASE_ADDR) / PCIE_CCSR_SIZE;
-
- list_add(&pcie->list, &ls_pcie_list);
-
- pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
- if (!pcie->enabled) {
- printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
- return 0;
- }
-
- pcie->dbi = map_physmem(pcie->dbi_res.start,
- fdt_resource_size(&pcie->dbi_res),
- MAP_NOCACHE);
-
- ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
- "lut", &pcie->lut_res);
- if (!ret)
- pcie->lut = map_physmem(pcie->lut_res.start,
- fdt_resource_size(&pcie->lut_res),
- MAP_NOCACHE);
-
- ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
- "ctrl", &pcie->ctrl_res);
- if (!ret)
- pcie->ctrl = map_physmem(pcie->ctrl_res.start,
- fdt_resource_size(&pcie->ctrl_res),
- MAP_NOCACHE);
- if (!pcie->ctrl)
- pcie->ctrl = pcie->lut;
-
- if (!pcie->ctrl) {
- printf("%s: NOT find CTRL\n", dev->name);
- return -1;
- }
-
- ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
- "config", &pcie->cfg_res);
- if (ret) {
- printf("%s: resource \"config\" not found\n", dev->name);
- return ret;
- }
-
- /*
- * Fix the pcie memory map address and PF control registers address
- * for LS2088A series SoCs
- */
- svr = get_svr();
- svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
- if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
- svr == SVR_LS2048A || svr == SVR_LS2044A ||
- svr == SVR_LS2081A || svr == SVR_LS2041A) {
- cfg_size = fdt_resource_size(&pcie->cfg_res);
- pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
- LS2088A_PCIE_PHYS_SIZE * pcie->idx;
- pcie->cfg_res.end = pcie->cfg_res.start + cfg_size;
- pcie->ctrl = pcie->lut + 0x40000;
- }
-
- pcie->cfg0 = map_physmem(pcie->cfg_res.start,
- fdt_resource_size(&pcie->cfg_res),
- MAP_NOCACHE);
- pcie->cfg1 = pcie->cfg0 + fdt_resource_size(&pcie->cfg_res) / 2;
-
- pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
-
- debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
- dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
- (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0,
- pcie->big_endian);
-
- pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
-
- if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
- printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
- ls_pcie_setup_ep(pcie);
- } else {
- printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
- ls_pcie_setup_ctrl(pcie);
- }
-
- if (!ls_pcie_link_up(pcie)) {
- /* Let the user know there's no PCIe link */
- printf(": no link\n");
- return 0;
- }
-
- /* Print the negotiated PCIe link width */
- link_sta = readw(pcie->dbi + PCIE_LINK_STA);
- printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4,
- link_sta & PCIE_LINK_SPEED_MASK);
-
- return 0;
-}
-
-static const struct dm_pci_ops ls_pcie_ops = {
- .read_config = ls_pcie_read_config,
- .write_config = ls_pcie_write_config,
-};
-
-static const struct udevice_id ls_pcie_ids[] = {
- { .compatible = "fsl,ls-pcie" },
- { }
-};
-
-U_BOOT_DRIVER(pci_layerscape) = {
- .name = "pci_layerscape",
- .id = UCLASS_PCI,
- .of_match = ls_pcie_ids,
- .ops = &ls_pcie_ops,
- .probe = ls_pcie_probe,
- .priv_auto_alloc_size = sizeof(struct ls_pcie),
-};
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Layerscape PCIe driver
*/
#define _PCIE_LAYERSCAPE_H_
#include <pci.h>
#include <dm.h>
+#include <linux/sizes.h>
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
#endif
#ifndef CONFIG_SYS_PCI_MEMORY_SIZE
-#define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */
+#define CONFIG_SYS_PCI_MEMORY_SIZE SZ_4G
#endif
#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
#define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
#define PCIE_ATU_REGION_NUM 6
+#define PCIE_ATU_REGION_NUM_SRIOV 24
#define PCIE_ATU_CR1 0x904
#define PCIE_ATU_TYPE_MEM (0x0 << 0)
#define PCIE_ATU_TYPE_IO (0x2 << 0)
#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
+#define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)
#define PCIE_ATU_CR2 0x908
#define PCIE_ATU_ENABLE (0x1 << 31)
#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
+#define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
+#define PCIE_ATU_VFBAR_MATCH_MODE_EN BIT(26)
#define PCIE_ATU_BAR_NUM(bar) ((bar) << 8)
#define PCIE_ATU_LOWER_BASE 0x90C
#define PCIE_ATU_UPPER_BASE 0x910
/* DBI registers */
#define PCIE_SRIOV 0x178
#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
-#define PCIE_DBI_RO_WR_EN 0x8bc
+#define PCIE_DBI_RO_WR_EN BIT(0)
+#define PCIE_MISC_CONTROL_1_OFF 0x8BC
#define PCIE_LINK_CAP 0x7c
#define PCIE_LINK_SPEED_MASK 0xf
PCIE_LCTRL0_CFG2_ENABLE)
#define PCIE_NO_SRIOV_BAR_BASE 0x1000
-
+#define FSL_PCIE_EP_MIN_APERTURE 4096 /* 4 Kbytes */
#define PCIE_PF_NUM 2
#define PCIE_VF_NUM 64
+#define BAR_NUM 8
+
+#define PCIE_BAR0_SIZE SZ_4K
+#define PCIE_BAR1_SIZE SZ_8K
+#define PCIE_BAR2_SIZE SZ_4K
+#define PCIE_BAR4_SIZE SZ_1M
+
+#define PCIE_SRIOV_VFBAR0 0x19C
-#define PCIE_BAR0_SIZE (4 * 1024) /* 4K */
-#define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */
-#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
-#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
+#define PCIE_MASK_OFFSET(flag, pf, off) ((flag) ? 0 : (0x1000 + (off) * (pf)))
/* LUT registers */
#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
#define LS1021_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
#define LS1021_LTSSM_STATE_SHIFT 20
+/* LX2160a PF1 offset */
+#define LX2160_PCIE_PF1_OFFSET 0x8000
+
+/* layerscape PF1 offset */
+#define LS_PCIE_PF1_OFFSET 0x20000
+
struct ls_pcie {
+ void __iomem *dbi;
+ void __iomem *lut;
+ void __iomem *ctrl;
int idx;
+ bool big_endian;
+ int mode;
+};
+
+struct ls_pcie_rc {
+ struct ls_pcie *pcie;
struct list_head list;
struct udevice *bus;
struct fdt_resource dbi_res;
struct fdt_resource lut_res;
struct fdt_resource ctrl_res;
struct fdt_resource cfg_res;
- void __iomem *dbi;
- void __iomem *lut;
- void __iomem *ctrl;
void __iomem *cfg0;
void __iomem *cfg1;
- bool big_endian;
bool enabled;
int next_lut_index;
int stream_id_cur;
- int mode;
+};
+
+struct ls_pcie_ep {
+ struct fdt_resource addr_res;
+ struct ls_pcie *pcie;
+ struct udevice *bus;
+ void __iomem *addr;
+ u32 cfg2_flag;
+ u32 sriov_flag;
+ u32 pf1_offset;
+ u32 num_ib_wins;
+ u32 num_ob_wins;
+ u8 max_functions;
};
extern struct list_head ls_pcie_list;
+unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset);
+void dbi_writel(struct ls_pcie *pcie, unsigned int value, unsigned int offset);
+unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset);
+void ctrl_writel(struct ls_pcie *pcie, unsigned int value, unsigned int offset);
+void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
+ u64 phys, u64 bus_addr, u64 size);
+void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
+ int type, int idx, int bar, u64 phys);
+void ls_pcie_dump_atu(struct ls_pcie *pcie, u32 win_num, u32 type);
+int ls_pcie_link_up(struct ls_pcie *pcie);
+void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie);
+void ls_pcie_dbi_ro_wr_dis(struct ls_pcie *pcie);
+
#endif /* _PCIE_LAYERSCAPE_H_ */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ * Layerscape PCIe EP driver
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/devres.h>
+#include <errno.h>
+#include <pci_ep.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <linux/log2.h>
+#include "pcie_layerscape.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void ls_pcie_ep_enable_cfg(struct ls_pcie_ep *pcie_ep)
+{
+ struct ls_pcie *pcie = pcie_ep->pcie;
+ u32 config;
+
+ config = ctrl_readl(pcie, PCIE_PF_CONFIG);
+ config |= PCIE_CONFIG_READY;
+ ctrl_writel(pcie, config, PCIE_PF_CONFIG);
+}
+
+static int ls_ep_set_bar(struct udevice *dev, uint fn, struct pci_bar *ep_bar)
+{
+ struct ls_pcie_ep *pcie_ep = dev_get_priv(dev);
+ struct ls_pcie *pcie = pcie_ep->pcie;
+ dma_addr_t bar_phys = ep_bar->phys_addr;
+ enum pci_barno bar = ep_bar->barno;
+ u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
+ int flags = ep_bar->flags;
+ int type, idx;
+ u64 size;
+
+ idx = bar;
+ /* BAR size is 2^(aperture + 11) */
+ size = max_t(size_t, ep_bar->size, FSL_PCIE_EP_MIN_APERTURE);
+
+ if (!(flags & PCI_BASE_ADDRESS_SPACE))
+ type = PCIE_ATU_TYPE_MEM;
+ else
+ type = PCIE_ATU_TYPE_IO;
+
+ ls_pcie_atu_inbound_set(pcie, fn, 0, type, idx, bar, bar_phys);
+
+ dbi_writel(pcie, lower_32_bits(size - 1), reg + PCIE_NO_SRIOV_BAR_BASE);
+ dbi_writel(pcie, flags, reg);
+
+ if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
+ dbi_writel(pcie, upper_32_bits(size - 1),
+ reg + 4 + PCIE_NO_SRIOV_BAR_BASE);
+ dbi_writel(pcie, 0, reg + 4);
+ }
+
+ return 0;
+}
+
+static struct pci_ep_ops ls_pcie_ep_ops = {
+ .set_bar = ls_ep_set_bar,
+};
+
+static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep, u32 pf)
+{
+ struct ls_pcie *pcie = pcie_ep->pcie;
+ u32 vf_flag = 0;
+ u64 phys = 0;
+
+ phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M;
+
+ phys = ALIGN(phys, PCIE_BAR0_SIZE);
+ /* ATU 0 : INBOUND : map BAR0 */
+ ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+ 0 + pf * BAR_NUM, 0, phys);
+ /* ATU 1 : INBOUND : map BAR1 */
+ phys = ALIGN(phys + PCIE_BAR0_SIZE, PCIE_BAR1_SIZE);
+ ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+ 1 + pf * BAR_NUM, 1, phys);
+ /* ATU 2 : INBOUND : map BAR2 */
+ phys = ALIGN(phys + PCIE_BAR1_SIZE, PCIE_BAR2_SIZE);
+ ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+ 2 + pf * BAR_NUM, 2, phys);
+ /* ATU 3 : INBOUND : map BAR2 */
+ phys = ALIGN(phys + PCIE_BAR2_SIZE, PCIE_BAR4_SIZE);
+ ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+ 3 + pf * BAR_NUM, 4, phys);
+
+ if (pcie_ep->sriov_flag) {
+ vf_flag = 1;
+ /* ATU 4 : INBOUND : map BAR0 */
+ phys = ALIGN(phys + PCIE_BAR4_SIZE, PCIE_BAR0_SIZE);
+ ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+ 4 + pf * BAR_NUM, 0, phys);
+ /* ATU 5 : INBOUND : map BAR1 */
+ phys = ALIGN(phys + PCIE_BAR0_SIZE * PCIE_VF_NUM,
+ PCIE_BAR1_SIZE);
+ ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+ 5 + pf * BAR_NUM, 1, phys);
+ /* ATU 6 : INBOUND : map BAR2 */
+ phys = ALIGN(phys + PCIE_BAR1_SIZE * PCIE_VF_NUM,
+ PCIE_BAR2_SIZE);
+ ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+ 6 + pf * BAR_NUM, 2, phys);
+ /* ATU 7 : INBOUND : map BAR4 */
+ phys = ALIGN(phys + PCIE_BAR2_SIZE * PCIE_VF_NUM,
+ PCIE_BAR4_SIZE);
+ ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
+ 7 + pf * BAR_NUM, 4, phys);
+ }
+
+ /* ATU: OUTBOUND : map MEM */
+ ls_pcie_atu_outbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
+ (u64)pcie_ep->addr_res.start +
+ pf * CONFIG_SYS_PCI_MEMORY_SIZE,
+ 0, CONFIG_SYS_PCI_MEMORY_SIZE);
+}
+
+/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
+static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
+{
+ u32 mask;
+
+ /* The least inbound window is 4KiB */
+ if (size < SZ_4K)
+ mask = 0;
+ else
+ mask = size - 1;
+
+ switch (bar) {
+ case 0:
+ writel(mask, bar_base + PCI_BASE_ADDRESS_0);
+ break;
+ case 1:
+ writel(mask, bar_base + PCI_BASE_ADDRESS_1);
+ break;
+ case 2:
+ writel(mask, bar_base + PCI_BASE_ADDRESS_2);
+ writel(0, bar_base + PCI_BASE_ADDRESS_3);
+ break;
+ case 4:
+ writel(mask, bar_base + PCI_BASE_ADDRESS_4);
+ writel(0, bar_base + PCI_BASE_ADDRESS_5);
+ break;
+ default:
+ break;
+ }
+}
+
+static void ls_pcie_ep_setup_bars(void *bar_base)
+{
+ /* BAR0 - 32bit - MEM */
+ ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
+ /* BAR1 - 32bit - MEM*/
+ ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
+ /* BAR2 - 64bit - MEM */
+ ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
+ /* BAR4 - 64bit - MEM */
+ ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
+}
+
+static void ls_pcie_ep_setup_vf_bars(void *bar_base)
+{
+ /* VF BAR0 MASK register at offset 0x19c*/
+ bar_base += PCIE_SRIOV_VFBAR0 - PCI_BASE_ADDRESS_0;
+
+ /* VF-BAR0 - 32bit - MEM */
+ ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
+ /* VF-BAR1 - 32bit - MEM*/
+ ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
+ /* VF-BAR2 - 64bit - MEM */
+ ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
+ /* VF-BAR4 - 64bit - MEM */
+ ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
+}
+
+static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
+{
+ u32 sriov;
+ u32 pf, vf;
+ void *bar_base = NULL;
+ struct ls_pcie *pcie = pcie_ep->pcie;
+
+ sriov = readl(pcie->dbi + PCIE_SRIOV);
+ if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
+ pcie_ep->sriov_flag = 1;
+ for (pf = 0; pf < PCIE_PF_NUM; pf++) {
+ /*
+ * The VF_BARn_REG register's Prefetchable and Type bit
+ * fields are overwritten by a write to VF's BAR Mask
+ * register. Before writing to the VF_BARn_MASK_REG
+ * register, write 0b to the PCIE_MISC_CONTROL_1_OFF
+ * register.
+ */
+ writel(0, pcie->dbi + PCIE_MISC_CONTROL_1_OFF);
+
+ bar_base = pcie->dbi +
+ PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf,
+ pcie_ep->pf1_offset);
+
+ if (pcie_ep->cfg2_flag) {
+ ctrl_writel(pcie,
+ PCIE_LCTRL0_VAL(pf, 0),
+ PCIE_PF_VF_CTRL);
+ ls_pcie_ep_setup_bars(bar_base);
+
+ for (vf = 1; vf <= PCIE_VF_NUM; vf++) {
+ ctrl_writel(pcie,
+ PCIE_LCTRL0_VAL(pf, vf),
+ PCIE_PF_VF_CTRL);
+ ls_pcie_ep_setup_vf_bars(bar_base);
+ }
+ } else {
+ ls_pcie_ep_setup_bars(bar_base);
+ ls_pcie_ep_setup_vf_bars(bar_base);
+ }
+
+ ls_pcie_ep_setup_atu(pcie_ep, pf);
+ }
+
+ if (pcie_ep->cfg2_flag) /* Disable CFG2 */
+ ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
+ } else {
+ ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
+ ls_pcie_ep_setup_atu(pcie_ep, 0);
+ }
+
+ ls_pcie_dump_atu(pcie, PCIE_ATU_REGION_NUM_SRIOV,
+ PCIE_ATU_REGION_INBOUND);
+
+ ls_pcie_ep_enable_cfg(pcie_ep);
+}
+
+static int ls_pcie_ep_probe(struct udevice *dev)
+{
+ struct ls_pcie_ep *pcie_ep = dev_get_priv(dev);
+ struct ls_pcie *pcie;
+ u16 link_sta;
+ int ret;
+ u32 svr;
+
+ pcie = devm_kmalloc(dev, sizeof(*pcie), GFP_KERNEL);
+ if (!pcie)
+ return -ENOMEM;
+
+ pcie_ep->pcie = pcie;
+
+ pcie->dbi = (void __iomem *)devfdt_get_addr_index(dev, 0);
+ if (!pcie->dbi)
+ return -ENOMEM;
+
+ pcie->ctrl = (void __iomem *)devfdt_get_addr_index(dev, 1);
+ if (!pcie->ctrl)
+ return -ENOMEM;
+
+ ret = fdt_get_named_resource(gd->fdt_blob, dev_of_offset(dev),
+ "reg", "reg-names",
+ "addr_space", &pcie_ep->addr_res);
+ if (ret) {
+ printf("%s: resource \"addr_space\" not found\n", dev->name);
+ return ret;
+ }
+
+ pcie->idx = ((unsigned long)pcie->dbi - PCIE_SYS_BASE_ADDR) /
+ PCIE_CCSR_SIZE;
+
+ pcie->big_endian = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
+ "big-endian");
+
+ svr = SVR_SOC_VER(get_svr());
+
+ if (svr == SVR_LX2160A)
+ pcie_ep->pf1_offset = LX2160_PCIE_PF1_OFFSET;
+ else
+ pcie_ep->pf1_offset = LS_PCIE_PF1_OFFSET;
+
+ if (svr == SVR_LS2080A || svr == SVR_LS2085A)
+ pcie_ep->cfg2_flag = 1;
+ else
+ pcie_ep->cfg2_flag = 0;
+
+ pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
+ if (pcie->mode != PCI_HEADER_TYPE_NORMAL)
+ return 0;
+
+ pcie_ep->max_functions = fdtdec_get_int(gd->fdt_blob,
+ dev_of_offset(dev),
+ "max-functions", 1);
+ pcie_ep->num_ib_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "num-ib-windows", 8);
+ pcie_ep->num_ob_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "num-ob-windows", 8);
+
+ printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+ ls_pcie_setup_ep(pcie_ep);
+
+ if (!ls_pcie_link_up(pcie)) {
+ /* Let the user know there's no PCIe link */
+ printf(": no link\n");
+ return 0;
+ }
+
+ /* Print the negotiated PCIe link width */
+ link_sta = readw(pcie->dbi + PCIE_LINK_STA);
+ printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4,
+ link_sta & PCIE_LINK_SPEED_MASK);
+
+ return 0;
+}
+
+static int ls_pcie_ep_remove(struct udevice *dev)
+{
+ return 0;
+}
+
+const struct udevice_id ls_pcie_ep_ids[] = {
+ { .compatible = "fsl,ls-pcie-ep" },
+ { }
+};
+
+U_BOOT_DRIVER(pci_layerscape_ep) = {
+ .name = "pci_layerscape_ep",
+ .id = UCLASS_PCI_EP,
+ .of_match = ls_pcie_ep_ids,
+ .ops = &ls_pcie_ep_ops,
+ .probe = ls_pcie_ep_probe,
+ .remove = ls_pcie_ep_remove,
+ .priv_auto_alloc_size = sizeof(struct ls_pcie_ep),
+};
/*
* Return next available LUT index.
*/
-static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
+static int ls_pcie_next_lut_index(struct ls_pcie_rc *pcie_rc)
{
- if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
- return pcie->next_lut_index++;
+ if (pcie_rc->next_lut_index < PCIE_LUT_ENTRY_COUNT)
+ return pcie_rc->next_lut_index++;
else
return -ENOSPC; /* LUT is full */
}
-static void lut_writel(struct ls_pcie *pcie, unsigned int value,
+static void lut_writel(struct ls_pcie_rc *pcie_rc, unsigned int value,
unsigned int offset)
{
+ struct ls_pcie *pcie = pcie_rc->pcie;
+
if (pcie->big_endian)
out_be32(pcie->lut + offset, value);
else
/*
* Program a single LUT entry
*/
-static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
- u32 streamid)
+static void ls_pcie_lut_set_mapping(struct ls_pcie_rc *pcie_rc, int index,
+ u32 devid, u32 streamid)
{
/* leave mask as all zeroes, want to match all bits */
- lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
- lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
+ lut_writel(pcie_rc, devid << 16, PCIE_LUT_UDR(index));
+ lut_writel(pcie_rc, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
}
/*
* msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
* [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
*/
-static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
+static void fdt_pcie_set_msi_map_entry_ls(void *blob,
+ struct ls_pcie_rc *pcie_rc,
u32 devid, u32 streamid)
{
u32 *prop;
int nodeoffset;
uint svr;
char *compat = NULL;
+ struct ls_pcie *pcie = pcie_rc->pcie;
/* find pci controller node */
nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
- pcie->dbi_res.start);
+ pcie_rc->dbi_res.start);
if (nodeoffset < 0) {
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
compat = CONFIG_FSL_PCIE_COMPAT;
if (compat)
nodeoffset = fdt_node_offset_by_compat_reg(blob,
- compat, pcie->dbi_res.start);
+ compat, pcie_rc->dbi_res.start);
#endif
if (nodeoffset < 0)
return;
* iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
* [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
*/
-static void fdt_pcie_set_iommu_map_entry_ls(void *blob, struct ls_pcie *pcie,
+static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
+ struct ls_pcie_rc *pcie_rc,
u32 devid, u32 streamid)
{
u32 *prop;
int lenp;
uint svr;
char *compat = NULL;
+ struct ls_pcie *pcie = pcie_rc->pcie;
/* find pci controller node */
nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
- pcie->dbi_res.start);
+ pcie_rc->dbi_res.start);
if (nodeoffset < 0) {
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
if (compat)
nodeoffset = fdt_node_offset_by_compat_reg(blob,
- compat, pcie->dbi_res.start);
+ compat, pcie_rc->dbi_res.start);
#endif
if (nodeoffset < 0)
return;
static void fdt_fixup_pcie_ls(void *blob)
{
struct udevice *dev, *bus;
- struct ls_pcie *pcie;
+ struct ls_pcie_rc *pcie_rc;
int streamid;
int index;
pci_dev_t bdf;
pci_find_next_device(&dev)) {
for (bus = dev; device_is_on_pci_bus(bus);)
bus = bus->parent;
- pcie = dev_get_priv(bus);
+ pcie_rc = dev_get_priv(bus);
- streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
+ streamid = pcie_next_streamid(pcie_rc->stream_id_cur,
+ pcie_rc->pcie->idx);
if (streamid < 0) {
debug("ERROR: no stream ids free\n");
continue;
} else {
- pcie->stream_id_cur++;
+ pcie_rc->stream_id_cur++;
}
- index = ls_pcie_next_lut_index(pcie);
+ index = ls_pcie_next_lut_index(pcie_rc);
if (index < 0) {
debug("ERROR: no LUT indexes free\n");
continue;
/* the DT fixup must be relative to the hose first_busno */
bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
/* map PCI b.d.f to streamID in LUT */
- ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
+ ls_pcie_lut_set_mapping(pcie_rc, index, bdf >> 8,
streamid);
/* update msi-map in device tree */
- fdt_pcie_set_msi_map_entry_ls(blob, pcie, bdf >> 8,
+ fdt_pcie_set_msi_map_entry_ls(blob, pcie_rc, bdf >> 8,
streamid);
/* update iommu-map in device tree */
- fdt_pcie_set_iommu_map_entry_ls(blob, pcie, bdf >> 8,
+ fdt_pcie_set_iommu_map_entry_ls(blob, pcie_rc, bdf >> 8,
streamid);
}
pcie_board_fix_fdt(blob);
}
#endif
-static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
+static void ft_pcie_rc_fix(void *blob, struct ls_pcie_rc *pcie_rc)
{
int off;
uint svr;
char *compat = NULL;
+ struct ls_pcie *pcie = pcie_rc->pcie;
off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
- pcie->dbi_res.start);
+ pcie_rc->dbi_res.start);
if (off < 0) {
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
compat = CONFIG_FSL_PCIE_COMPAT;
if (compat)
off = fdt_node_offset_by_compat_reg(blob,
- compat, pcie->dbi_res.start);
+ compat, pcie_rc->dbi_res.start);
#endif
if (off < 0)
return;
}
- if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
+ if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
else
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
}
-static void ft_pcie_ep_fix(void *blob, struct ls_pcie *pcie)
+static void ft_pcie_ep_fix(void *blob, struct ls_pcie_rc *pcie_rc)
{
int off;
+ struct ls_pcie *pcie = pcie_rc->pcie;
off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
- pcie->dbi_res.start);
+ pcie_rc->dbi_res.start);
if (off < 0)
return;
- if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
+ if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
else
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
}
-static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
+static void ft_pcie_ls_setup(void *blob, struct ls_pcie_rc *pcie_rc)
{
- ft_pcie_ep_fix(blob, pcie);
- ft_pcie_rc_fix(blob, pcie);
+ ft_pcie_ep_fix(blob, pcie_rc);
+ ft_pcie_rc_fix(blob, pcie_rc);
}
/* Fixup Kernel DT for PCIe */
void ft_pci_setup_ls(void *blob, struct bd_info *bd)
{
- struct ls_pcie *pcie;
+ struct ls_pcie_rc *pcie_rc;
- list_for_each_entry(pcie, &ls_pcie_list, list)
- ft_pcie_ls_setup(blob, pcie);
+ list_for_each_entry(pcie_rc, &ls_pcie_list, list)
+ ft_pcie_ls_setup(blob, pcie_rc);
#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
fdt_fixup_pcie_ls(blob);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ * Layerscape PCIe driver
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <malloc.h>
+#include <dm.h>
+#include <dm/devres.h>
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
+ defined(CONFIG_ARM)
+#include <asm/arch/clock.h>
+#endif
+#include "pcie_layerscape.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void ls_pcie_cfg0_set_busdev(struct ls_pcie_rc *pcie_rc, u32 busdev)
+{
+ struct ls_pcie *pcie = pcie_rc->pcie;
+
+ dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_VIEWPORT);
+ dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
+}
+
+static void ls_pcie_cfg1_set_busdev(struct ls_pcie_rc *pcie_rc, u32 busdev)
+{
+ struct ls_pcie *pcie = pcie_rc->pcie;
+
+ dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_VIEWPORT);
+ dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
+}
+
+static void ls_pcie_setup_atu(struct ls_pcie_rc *pcie_rc)
+{
+ struct pci_region *io, *mem, *pref;
+ unsigned long long offset = 0;
+ struct ls_pcie *pcie = pcie_rc->pcie;
+ int idx = 0;
+ uint svr;
+
+ svr = get_svr();
+ if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
+ offset = LS1021_PCIE_SPACE_OFFSET +
+ LS1021_PCIE_SPACE_SIZE * pcie->idx;
+ }
+
+ /* ATU 0 : OUTBOUND : CFG0 */
+ ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_CFG0,
+ pcie_rc->cfg_res.start + offset,
+ 0,
+ fdt_resource_size(&pcie_rc->cfg_res) / 2);
+ /* ATU 1 : OUTBOUND : CFG1 */
+ ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_TYPE_CFG1,
+ pcie_rc->cfg_res.start + offset +
+ fdt_resource_size(&pcie_rc->cfg_res) / 2,
+ 0,
+ fdt_resource_size(&pcie_rc->cfg_res) / 2);
+
+ pci_get_regions(pcie_rc->bus, &io, &mem, &pref);
+ idx = PCIE_ATU_REGION_INDEX1 + 1;
+
+ /* Fix the pcie memory map for LS2088A series SoCs */
+ svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
+ if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+ svr == SVR_LS2048A || svr == SVR_LS2044A ||
+ svr == SVR_LS2081A || svr == SVR_LS2041A) {
+ if (io)
+ io->phys_start = (io->phys_start &
+ (PCIE_PHYS_SIZE - 1)) +
+ LS2088A_PCIE1_PHYS_ADDR +
+ LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+ if (mem)
+ mem->phys_start = (mem->phys_start &
+ (PCIE_PHYS_SIZE - 1)) +
+ LS2088A_PCIE1_PHYS_ADDR +
+ LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+ if (pref)
+ pref->phys_start = (pref->phys_start &
+ (PCIE_PHYS_SIZE - 1)) +
+ LS2088A_PCIE1_PHYS_ADDR +
+ LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+ }
+
+ if (io)
+ /* ATU : OUTBOUND : IO */
+ ls_pcie_atu_outbound_set(pcie, idx++,
+ PCIE_ATU_TYPE_IO,
+ io->phys_start + offset,
+ io->bus_start,
+ io->size);
+
+ if (mem)
+ /* ATU : OUTBOUND : MEM */
+ ls_pcie_atu_outbound_set(pcie, idx++,
+ PCIE_ATU_TYPE_MEM,
+ mem->phys_start + offset,
+ mem->bus_start,
+ mem->size);
+
+ if (pref)
+ /* ATU : OUTBOUND : pref */
+ ls_pcie_atu_outbound_set(pcie, idx++,
+ PCIE_ATU_TYPE_MEM,
+ pref->phys_start + offset,
+ pref->bus_start,
+ pref->size);
+
+ ls_pcie_dump_atu(pcie, PCIE_ATU_REGION_NUM, PCIE_ATU_REGION_OUTBOUND);
+}
+
+/* Return 0 if the address is valid, -errno if not valid */
+static int ls_pcie_addr_valid(struct ls_pcie_rc *pcie_rc, pci_dev_t bdf)
+{
+ struct udevice *bus = pcie_rc->bus;
+ struct ls_pcie *pcie = pcie_rc->pcie;
+
+ if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
+ return -ENODEV;
+
+ if (!pcie_rc->enabled)
+ return -ENXIO;
+
+ if (PCI_BUS(bdf) < bus->seq)
+ return -EINVAL;
+
+ if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie)))
+ return -EINVAL;
+
+ if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
+ return -EINVAL;
+
+ return 0;
+}
+
+int ls_pcie_conf_address(const struct udevice *bus, pci_dev_t bdf,
+ uint offset, void **paddress)
+{
+ struct ls_pcie_rc *pcie_rc = dev_get_priv(bus);
+ struct ls_pcie *pcie = pcie_rc->pcie;
+ u32 busdev;
+
+ if (ls_pcie_addr_valid(pcie_rc, bdf))
+ return -EINVAL;
+
+ if (PCI_BUS(bdf) == bus->seq) {
+ *paddress = pcie->dbi + offset;
+ return 0;
+ }
+
+ busdev = PCIE_ATU_BUS(PCI_BUS(bdf) - bus->seq) |
+ PCIE_ATU_DEV(PCI_DEV(bdf)) |
+ PCIE_ATU_FUNC(PCI_FUNC(bdf));
+
+ if (PCI_BUS(bdf) == bus->seq + 1) {
+ ls_pcie_cfg0_set_busdev(pcie_rc, busdev);
+ *paddress = pcie_rc->cfg0 + offset;
+ } else {
+ ls_pcie_cfg1_set_busdev(pcie_rc, busdev);
+ *paddress = pcie_rc->cfg1 + offset;
+ }
+ return 0;
+}
+
+static int ls_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ return pci_generic_mmap_read_config(bus, ls_pcie_conf_address,
+ bdf, offset, valuep, size);
+}
+
+static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ return pci_generic_mmap_write_config(bus, ls_pcie_conf_address,
+ bdf, offset, value, size);
+}
+
+/* Clear multi-function bit */
+static void ls_pcie_clear_multifunction(struct ls_pcie_rc *pcie_rc)
+{
+ struct ls_pcie *pcie = pcie_rc->pcie;
+
+ writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
+}
+
+/* Fix class value */
+static void ls_pcie_fix_class(struct ls_pcie_rc *pcie_rc)
+{
+ struct ls_pcie *pcie = pcie_rc->pcie;
+
+ writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
+}
+
+/* Drop MSG TLP except for Vendor MSG */
+static void ls_pcie_drop_msg_tlp(struct ls_pcie_rc *pcie_rc)
+{
+ struct ls_pcie *pcie = pcie_rc->pcie;
+ u32 val;
+
+ val = dbi_readl(pcie, PCIE_STRFMR1);
+ val &= 0xDFFFFFFF;
+ dbi_writel(pcie, val, PCIE_STRFMR1);
+}
+
+/* Disable all bars in RC mode */
+static void ls_pcie_disable_bars(struct ls_pcie_rc *pcie_rc)
+{
+ struct ls_pcie *pcie = pcie_rc->pcie;
+
+ dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
+ dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
+ dbi_writel(pcie, 0xfffffffe, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
+}
+
+static void ls_pcie_setup_ctrl(struct ls_pcie_rc *pcie_rc)
+{
+ struct ls_pcie *pcie = pcie_rc->pcie;
+
+ ls_pcie_setup_atu(pcie_rc);
+
+ ls_pcie_dbi_ro_wr_en(pcie);
+ ls_pcie_fix_class(pcie_rc);
+ ls_pcie_clear_multifunction(pcie_rc);
+ ls_pcie_drop_msg_tlp(pcie_rc);
+ ls_pcie_dbi_ro_wr_dis(pcie);
+
+ ls_pcie_disable_bars(pcie_rc);
+ pcie_rc->stream_id_cur = 0;
+}
+
+static int ls_pcie_probe(struct udevice *dev)
+{
+ struct ls_pcie_rc *pcie_rc = dev_get_priv(dev);
+ const void *fdt = gd->fdt_blob;
+ int node = dev_of_offset(dev);
+ struct ls_pcie *pcie;
+ u16 link_sta;
+ uint svr;
+ int ret;
+ fdt_size_t cfg_size;
+
+ pcie_rc->bus = dev;
+
+ pcie = devm_kmalloc(dev, sizeof(*pcie), GFP_KERNEL);
+ if (!pcie)
+ return -ENOMEM;
+
+ pcie_rc->pcie = pcie;
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "dbi", &pcie_rc->dbi_res);
+ if (ret) {
+ printf("ls-pcie: resource \"dbi\" not found\n");
+ return ret;
+ }
+
+ pcie->idx = (pcie_rc->dbi_res.start - PCIE_SYS_BASE_ADDR) /
+ PCIE_CCSR_SIZE;
+
+ list_add(&pcie_rc->list, &ls_pcie_list);
+
+ pcie_rc->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
+ if (!pcie_rc->enabled) {
+ printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+ return 0;
+ }
+
+ pcie->dbi = map_physmem(pcie_rc->dbi_res.start,
+ fdt_resource_size(&pcie_rc->dbi_res),
+ MAP_NOCACHE);
+
+ pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
+ if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
+ return 0;
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "lut", &pcie_rc->lut_res);
+ if (!ret)
+ pcie->lut = map_physmem(pcie_rc->lut_res.start,
+ fdt_resource_size(&pcie_rc->lut_res),
+ MAP_NOCACHE);
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "ctrl", &pcie_rc->ctrl_res);
+ if (!ret)
+ pcie->ctrl = map_physmem(pcie_rc->ctrl_res.start,
+ fdt_resource_size(&pcie_rc->ctrl_res),
+ MAP_NOCACHE);
+ if (!pcie->ctrl)
+ pcie->ctrl = pcie->lut;
+
+ if (!pcie->ctrl) {
+ printf("%s: NOT find CTRL\n", dev->name);
+ return -1;
+ }
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "config", &pcie_rc->cfg_res);
+ if (ret) {
+ printf("%s: resource \"config\" not found\n", dev->name);
+ return ret;
+ }
+
+ /*
+ * Fix the pcie memory map address and PF control registers address
+ * for LS2088A series SoCs
+ */
+ svr = get_svr();
+ svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
+ if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+ svr == SVR_LS2048A || svr == SVR_LS2044A ||
+ svr == SVR_LS2081A || svr == SVR_LS2041A) {
+ cfg_size = fdt_resource_size(&pcie_rc->cfg_res);
+ pcie_rc->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
+ LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+ pcie_rc->cfg_res.end = pcie_rc->cfg_res.start + cfg_size;
+ pcie->ctrl = pcie->lut + 0x40000;
+ }
+
+ pcie_rc->cfg0 = map_physmem(pcie_rc->cfg_res.start,
+ fdt_resource_size(&pcie_rc->cfg_res),
+ MAP_NOCACHE);
+ pcie_rc->cfg1 = pcie_rc->cfg0 +
+ fdt_resource_size(&pcie_rc->cfg_res) / 2;
+
+ pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
+
+ debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
+ dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
+ (unsigned long)pcie->ctrl, (unsigned long)pcie_rc->cfg0,
+ pcie->big_endian);
+
+ printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+ ls_pcie_setup_ctrl(pcie_rc);
+
+ if (!ls_pcie_link_up(pcie)) {
+ /* Let the user know there's no PCIe link */
+ printf(": no link\n");
+ return 0;
+ }
+
+ /* Print the negotiated PCIe link width */
+ link_sta = readw(pcie->dbi + PCIE_LINK_STA);
+ printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4,
+ link_sta & PCIE_LINK_SPEED_MASK);
+
+ return 0;
+}
+
+static const struct dm_pci_ops ls_pcie_ops = {
+ .read_config = ls_pcie_read_config,
+ .write_config = ls_pcie_write_config,
+};
+
+static const struct udevice_id ls_pcie_ids[] = {
+ { .compatible = "fsl,ls-pcie" },
+ { }
+};
+
+U_BOOT_DRIVER(pci_layerscape) = {
+ .name = "pci_layerscape",
+ .id = UCLASS_PCI,
+ .of_match = ls_pcie_ids,
+ .ops = &ls_pcie_ops,
+ .probe = ls_pcie_probe,
+ .priv_auto_alloc_size = sizeof(struct ls_pcie_rc),
+};
.name = "pci_ep",
.flags = DM_UC_FLAG_SEQ_ALIAS,
};
+
+void pci_ep_init(void)
+{
+ struct udevice *dev;
+
+ for (uclass_first_device_check(UCLASS_PCI_EP, &dev);
+ dev;
+ uclass_next_device_check(&dev)) {
+ ;
+ }
+}
* Haikun Wang (B53464@freescale.com)
*/
+#include <linux/math64.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+/* linux/include/time.h */
+#define NSEC_PER_SEC 1000000000L
+
DECLARE_GLOBAL_DATA_PTR;
/* fsl_dspi_platdata flags */
return -EINVAL;
}
+static void ns_delay_scale(unsigned char *psc, unsigned char *sc, int delay_ns,
+ unsigned long clkrate)
+{
+ int scale_needed, scale, minscale = INT_MAX;
+ int pscale_tbl[4] = {1, 3, 5, 7};
+ u32 remainder;
+ int i, j;
+
+ scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
+ &remainder);
+ if (remainder)
+ scale_needed++;
+
+ for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
+ for (j = 0; j <= DSPI_CTAR_SCALE_BITS; j++) {
+ scale = pscale_tbl[i] * (2 << j);
+ if (scale >= scale_needed) {
+ if (scale < minscale) {
+ minscale = scale;
+ *psc = i;
+ *sc = j;
+ }
+ break;
+ }
+ }
+
+ if (minscale == INT_MAX) {
+ pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
+ delay_ns, clkrate);
+ *psc = ARRAY_SIZE(pscale_tbl) - 1;
+ *sc = DSPI_CTAR_SCALE_BITS;
+ }
+}
+
static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed)
{
int ret;
{
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
+ u32 cs_sck_delay = 0, sck_cs_delay = 0;
+ unsigned char pcssck = 0, cssck = 0;
+ unsigned char pasc = 0, asc = 0;
if (slave_plat->cs >= priv->num_chipselect) {
debug("DSPI invalid chipselect number %d(max %d)!\n",
return -EINVAL;
}
- priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE;
+ ofnode_read_u32(dev->node, "fsl,spi-cs-sck-delay", &cs_sck_delay);
+ ofnode_read_u32(dev->node, "fsl,spi-sck-cs-delay", &sck_cs_delay);
+
+ /* Set PCS to SCK delay scale values */
+ ns_delay_scale(&pcssck, &cssck, cs_sck_delay, priv->bus_clk);
+
+ /* Set After SCK delay scale values */
+ ns_delay_scale(&pasc, &asc, sck_cs_delay, priv->bus_clk);
+
+ priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE |
+ DSPI_CTAR_PCSSCK(pcssck) |
+ DSPI_CTAR_PASC(pasc);
debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n",
slave_plat->cs, slave_plat->max_hz, slave_plat->mode);
can be probed and supports all of the methods of WDT, but does not
really do anything.
+config WDT_SBSA
+ bool "SBSA watchdog timer support"
+ depends on WDT
+ help
+ Select this to enable SBSA watchdog timer.
+ This driver can operate ARM SBSA Generic Watchdog as a single stage.
+ In the single stage mode, when the timeout is reached, your system
+ will be reset by WS1. The first signal (WS0) is ignored.
+
config WDT_SP805
bool "SP805 watchdog timer support"
depends on WDT
obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
+obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o
obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Watchdog driver for SBSA
+ *
+ * Copyright 2020 NXP
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm/device.h>
+#include <dm/fdtaddr.h>
+#include <dm/read.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <watchdog.h>
+#include <wdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* SBSA Generic Watchdog register definitions */
+/* refresh frame */
+#define SBSA_GWDT_WRR 0x000
+
+/* control frame */
+#define SBSA_GWDT_WCS 0x000
+#define SBSA_GWDT_WOR 0x008
+#define SBSA_GWDT_WCV 0x010
+
+/* refresh/control frame */
+#define SBSA_GWDT_W_IIDR 0xfcc
+#define SBSA_GWDT_IDR 0xfd0
+
+/* Watchdog Control and Status Register */
+#define SBSA_GWDT_WCS_EN BIT(0)
+#define SBSA_GWDT_WCS_WS0 BIT(1)
+#define SBSA_GWDT_WCS_WS1 BIT(2)
+
+struct sbsa_gwdt_priv {
+ void __iomem *reg_refresh;
+ void __iomem *reg_control;
+};
+
+static int sbsa_gwdt_reset(struct udevice *dev)
+{
+ struct sbsa_gwdt_priv *priv = dev_get_priv(dev);
+
+ writel(0, priv->reg_refresh + SBSA_GWDT_WRR);
+
+ return 0;
+}
+
+static int sbsa_gwdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ struct sbsa_gwdt_priv *priv = dev_get_priv(dev);
+ u32 clk;
+
+ /*
+ * it work in the single stage mode in u-boot,
+ * The first signal (WS0) is ignored,
+ * the timeout is (WOR * 2), so the WOR should be configured
+ * to half value of timeout.
+ */
+ clk = get_tbclk();
+ writel(clk / 2 * timeout,
+ priv->reg_control + SBSA_GWDT_WOR);
+
+ /* writing WCS will cause an explicit watchdog refresh */
+ writel(SBSA_GWDT_WCS_EN, priv->reg_control + SBSA_GWDT_WCS);
+
+ return 0;
+}
+
+static int sbsa_gwdt_stop(struct udevice *dev)
+{
+ struct sbsa_gwdt_priv *priv = dev_get_priv(dev);
+
+ writel(0, priv->reg_control + SBSA_GWDT_WCS);
+
+ return 0;
+}
+
+static int sbsa_gwdt_expire_now(struct udevice *dev, ulong flags)
+{
+ sbsa_gwdt_start(dev, 0, flags);
+
+ return 0;
+}
+
+static int sbsa_gwdt_probe(struct udevice *dev)
+{
+ debug("%s: Probing wdt%u (sbsa-gwdt)\n", __func__, dev->seq);
+
+ return 0;
+}
+
+static int sbsa_gwdt_ofdata_to_platdata(struct udevice *dev)
+{
+ struct sbsa_gwdt_priv *priv = dev_get_priv(dev);
+
+ priv->reg_control = (void __iomem *)dev_read_addr_index(dev, 0);
+ if (IS_ERR(priv->reg_control))
+ return PTR_ERR(priv->reg_control);
+
+ priv->reg_refresh = (void __iomem *)dev_read_addr_index(dev, 1);
+ if (IS_ERR(priv->reg_refresh))
+ return PTR_ERR(priv->reg_refresh);
+
+ return 0;
+}
+
+static const struct wdt_ops sbsa_gwdt_ops = {
+ .start = sbsa_gwdt_start,
+ .reset = sbsa_gwdt_reset,
+ .stop = sbsa_gwdt_stop,
+ .expire_now = sbsa_gwdt_expire_now,
+};
+
+static const struct udevice_id sbsa_gwdt_ids[] = {
+ { .compatible = "arm,sbsa-gwdt" },
+ {}
+};
+
+U_BOOT_DRIVER(sbsa_gwdt) = {
+ .name = "sbsa_gwdt",
+ .id = UCLASS_WDT,
+ .of_match = sbsa_gwdt_ids,
+ .probe = sbsa_gwdt_probe,
+ .priv_auto_alloc_size = sizeof(struct sbsa_gwdt_priv),
+ .ofdata_to_platdata = sbsa_gwdt_ofdata_to_platdata,
+ .ops = &sbsa_gwdt_ops,
+};
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
#endif
/*
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=no\0" \
- "fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"load_addr=0xa0000000\0" \
"kernel_size=0x2800000\0" \
"kernelheader_size=0x40000\0" \
+ "bootm_size=0x10000000\0" \
"console=ttyS0,115200\0" \
BOOTENV \
"boot_scripts=ls1012ardb_boot.scr\0" \
#include <asm/arch/config.h>
#include <asm/arch/stream_id_lsch2.h>
+#include <linux/sizes.h>
#define CONFIG_SYS_CLK_FREQ 125000000
#define CONFIG_LAYERSCAPE_NS_ACCESS
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (5 * SZ_1M)
-/*SPI device */
+/* PFE */
#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x300000
+
+/*SPI device */
#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
/* SATA */
"verify=no\0" \
"loadaddr=0x80100000\0" \
"kernel_addr=0x100000\0" \
- "fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"kernel_start=0x1000000\0" \
"kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \
+ "bootm_size=0x10000000\0" \
#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=no\0" \
"fdt_high=0xffffffffffffffff\0" \
- "initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"scriptaddr=0x80000000\0" \
"fdt_addr_r=0x90000000\0" \
"load_addr=0x96000000\0" \
"kernel_size=0x2800000\0" \
+ "bootm_size=0x10000000\0" \
"console=ttyS0,115200\0" \
BOOTENV \
"boot_scripts=ls1012afrdm_boot.scr\0" \
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=no\0" \
- "fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"load_addr=0x92000000\0" \
"kernel_size=0x2800000\0" \
"kernelheader_size=0x40000\0" \
+ "bootm_size=0x10000000\0" \
"console=ttyS0,115200\0" \
"BOARD=ls1012afrwy\0" \
BOOTENV \
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=no\0" \
- "fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"load_addr=0xa0000000\0" \
"kernel_size=0x2800000\0" \
"kernelheader_size=0x40000\0" \
+ "bootm_size=0x10000000\0" \
"console=ttyS0,115200\0" \
BOOTENV \
"boot_scripts=ls1012ardb_boot.scr\0" \
#define __L1028A_COMMON_H
#define CONFIG_REMAKE_ELF
-#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_MP
#include <asm/arch/stream_id_lsch3.h>
/*
* SMP Definitinos
*/
-#define CPU_RELEASE_ADDR secondary_boot_func
+#define CPU_RELEASE_ADDR secondary_boot_addr
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
#define QIXIS_LBMAP_ALTBANK 0x00
#define QIXIS_LBMAP_SD 0x00
#define QIXIS_LBMAP_EMMC 0x00
-#define QIXIS_LBMAP_QSPI 0x00
+#define QIXIS_LBMAP_XSPI 0x00
#define QIXIS_RCW_SRC_SD 0xf8
#define QIXIS_RCW_SRC_EMMC 0xf9
-#define QIXIS_RCW_SRC_QSPI 0xff
+#define QIXIS_RCW_SRC_XSPI 0xff
#define QIXIS_RST_CTL_RESET 0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x10
#define QIXIS_RCFG_CTL_RECONFIG_START 0x11
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2015 Freescale Semiconductor
- * Copyright (C) 2019 NXP
+ * Copyright 2019-2020 NXP
*/
#ifndef __LS1043A_COMMON_H
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
-#define CPU_RELEASE_ADDR secondary_boot_func
+#define CPU_RELEASE_ADDR secondary_boot_addr
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
-#define CPU_RELEASE_ADDR secondary_boot_func
+#define CPU_RELEASE_ADDR secondary_boot_addr
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
/*
* SMP Definitinos
*/
-#define CPU_RELEASE_ADDR secondary_boot_func
+#define CPU_RELEASE_ADDR secondary_boot_addr
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
func(SCSI, scsi, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
/*
* SMP Definitinos
*/
-#define CPU_RELEASE_ADDR secondary_boot_func
+#define CPU_RELEASE_ADDR secondary_boot_addr
#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
/* SMP Definitinos */
-#define CPU_RELEASE_ADDR secondary_boot_func
+#define CPU_RELEASE_ADDR secondary_boot_addr
/* Generic Timer Definitions */
/*
#define DSPI_CTAR_ASC(x) (((x) & 0x0F) << 8)
#define DSPI_CTAR_DT(x) (((x) & 0x0F) << 4)
#define DSPI_CTAR_BR(x) ((x) & 0x0F)
+#define DSPI_CTAR_SCALE_BITS 0xf
/* Status */
#define DSPI_SR_TCF 0x80000000
/* needed for the mmc_cfg definition */
#include <mmc.h>
-#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
-#include "../board/freescale/common/qixis.h"
-#endif
-
/* FSL eSDHC-specific constants */
#define SYSCTL 0x0002e02c
#define SYSCTL_INITA 0x08000000
u32 rtfreqcnt; /* PRGM=0: freq. count register */
};
u32 rsvd1[40];
-#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
-#define RNG_STATE1_HANDLE_INSTANTIATED 0x00000002
-#define RNG_STATE_HANDLE_MASK \
- (RNG_STATE0_HANDLE_INSTANTIATED | RNG_STATE1_HANDLE_INSTANTIATED)
+#define RDSTA_IF(idx) (0x00000001 << (idx))
+#define RDSTA_PR(idx) (0x00000010 << (idx))
+#define RDSTA_MASK (RDSTA_PR(1) | RDSTA_PR(0) | RDSTA_IF(1) | RDSTA_IF(0))
+#define RDSTA_SKVN 0x40000000
u32 rdsta; /*RNG DRNG Status Register*/
u32 rsvd2[15];
};
+/* Version registers (Era 10+) */
+struct version_regs {
+ u32 crca; /* CRCA_VERSION */
+ u32 afha; /* AFHA_VERSION */
+ u32 kfha; /* KFHA_VERSION */
+ u32 pkha; /* PKHA_VERSION */
+ u32 aesa; /* AESA_VERSION */
+ u32 mdha; /* MDHA_VERSION */
+ u32 desa; /* DESA_VERSION */
+ u32 snw8a; /* SNW8A_VERSION */
+ u32 snw9a; /* SNW9A_VERSION */
+ u32 zuce; /* ZUCE_VERSION */
+ u32 zuca; /* ZUCA_VERSION */
+ u32 ccha; /* CCHA_VERSION */
+ u32 ptha; /* PTHA_VERSION */
+ u32 rng; /* RNG_VERSION */
+ u32 trng; /* TRNG_VERSION */
+ u32 aaha; /* AAHA_VERSION */
+ u32 rsvd[10];
+ u32 sr; /* SR_VERSION */
+ u32 dma; /* DMA_VERSION */
+ u32 ai; /* AI_VERSION */
+ u32 qi; /* QI_VERSION */
+ u32 jr; /* JR_VERSION */
+ u32 deco; /* DECO_VERSION */
+};
+
+#define CHA_VER_NUM_MASK 0x000000ff
+#define CHA_VER_MISC_SHIFT 8
+#define CHA_VER_MISC_MASK 0x0000ff00
+#define CHA_VER_REV_SHIFT 16
+#define CHA_VER_REV_MASK 0x00ff0000
+#define CHA_VER_VID_SHIFT 24
+#define CHA_VER_VID_MASK 0xff000000
+
typedef struct ccsr_sec {
u32 res0;
u32 mcfgr; /* Master CFG Register */
u32 drr; /* DECO Reset Register */
u8 res5[0x4d8];
struct rng4tst rng; /* RNG Registers */
- u8 res6[0x8a0];
+ u8 res6[0x780];
+ struct version_regs vreg; /* version registers since era 10 */
+ u8 res7[0xa0];
u32 crnr_ms; /* CHA Revision Number Register, MS */
u32 crnr_ls; /* CHA Revision Number Register, LS */
u32 ctpr_ms; /* Compile Time Parameters Register, MS */
u32 ctpr_ls; /* Compile Time Parameters Register, LS */
- u8 res7[0x10];
+ u8 res8[0x10];
u32 far_ms; /* Fault Address Register, MS */
u32 far_ls; /* Fault Address Register, LS */
u32 falr; /* Fault Address LIODN Register */
u32 fadr; /* Fault Address Detail Register */
- u8 res8[0x4];
+ u8 res9[0x4];
u32 csta; /* CAAM Status Register */
u32 smpart; /* Secure Memory Partition Parameters */
u32 smvid; /* Secure Memory Version ID */
u32 secvid_ms; /* SEC Version ID Register, MS */
u32 secvid_ls; /* SEC Version ID Register, LS */
#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
- u8 res9[0x6f020];
+ u8 res10[0x6f020];
#else
- u8 res9[0x6020];
+ u8 res10[0x6020];
#endif
u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
- u8 res10[0x8ffd8];
+ u8 res11[0x8ffd8];
#else
- u8 res10[0x8fd8];
+ u8 res11[0x8fd8];
#endif
} ccsr_sec_t;
int sec_init_idx(uint8_t);
#endif
int sec_init(void);
+
+u8 caam_get_era(void);
#endif
#endif /* __FSL_SEC_H */
int update_flash_size(int flash_size);
int arch_early_init_r(void);
void pci_init(void);
+void pci_ep_init(void);
int misc_init_r(void);
#if defined(CONFIG_VID)
int init_func_vid(void);
CONFIG_FSL_DIU_FB
CONFIG_FSL_DMA
CONFIG_FSL_DSPI1
-CONFIG_FSL_ESDHC_ADAPTER_IDENT
CONFIG_FSL_ESDHC_PIN_MUX
CONFIG_FSL_FIXED_MMC_LOCATION
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
projects / platform / kernel / u-boot.git / commitdiff