- Add various STM32MP1 fixes for serial, env, clk, board, i2c ...
- Add STM32MP1 DDR driver update:
These update introduce the DDR interactive mode described in:
https://wiki.st.com/stm32mpu/index.php/U-Boot_SPL:_DDR_interactive_mode
This mode is used by the CubeMX: DDR tuning tool.
https://wiki.st.com/stm32mpu/index.php/STM32CubeMX
The DDR interactive mode is NOT activated by default because
it increase the SPL size and slow down the boot time
(200ms wait added).
select HAVE_PRIVATE_LIBGCC
select SYS_BOOT_GET_CMDLINE
select SYS_BOOT_GET_KBD
+ select SUPPORT_OF_CONTROL
config MICROBLAZE
bool "MicroBlaze architecture"
# processor family
config MCF520x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF52x2
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF523x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF530x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF5301x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF532x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF537x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF5441x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF5445x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF5227x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF547x_8x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
# processor type
# ccflags-y += -DET_DEBUG
extra-y = start.o
-obj-y = cpu.o speed.o cpu_init.o interrupts.o
+obj-y = cpu.o speed.o cpu_init.o interrupts.o dspi.o
#include <asm/rtc.h>
#include <linux/compiler.h>
+void cfspi_port_conf(void)
+{
+ gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+ out_8(&gpio->par_dspi,
+ GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+ GPIO_PAR_DSPI_SCK_SCK);
+}
+
/*
* Breath some life into the CPU...
*
#endif
icache_enable();
+
+ cfspi_port_conf();
}
/*
break;
}
}
-
-#ifdef CONFIG_CF_DSPI
-void cfspi_port_conf(void)
-{
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- out_8(&gpio->par_dspi,
- GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
- GPIO_PAR_DSPI_SCK_SCK);
-}
-
-int cfspi_claim_bus(uint bus, uint cs)
-{
- dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
- return -1;
-
- /* Clear FIFO and resume transfer */
- clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 2:
- clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
- setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
- break;
- }
-
- return 0;
-}
-
-void cfspi_release_bus(uint bus, uint cs)
-{
- dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- /* Clear FIFO */
- clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 2:
- clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
- break;
- }
-}
-#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Angelo Dureghello <angleo@sysam.it>
+ *
+ * CPU specific dspi routines
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_CF_DSPI
+void dspi_chip_select(int cs)
+{
+ struct gpio *gpio = (struct gpio *)MMAP_GPIO;
+
+ switch (cs) {
+ case 0:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+ break;
+ case 2:
+ clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
+ setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
+ break;
+ }
+}
+
+void dspi_chip_unselect(int cs)
+{
+ struct gpio *gpio = (struct gpio *)MMAP_GPIO;
+
+ switch (cs) {
+ case 0:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+ break;
+ case 2:
+ clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
+ break;
+ }
+}
+#endif /* CONFIG_CF_DSPI */
clr.l %sp@-
/* run low-level board init code (from flash) */
- bsr board_init_f
+ move.l #board_init_f, %a1
+ jsr (%a1)
/* board_init_f() does not return */
# ccflags-y += -DET_DEBUG
extra-y = start.o
-obj-y = cpu.o speed.o cpu_init.o interrupts.o pci.o
+obj-y = cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o
#endif
}
+#ifdef CONFIG_CF_DSPI
+void cfspi_port_conf(void)
+{
+ gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+#ifdef CONFIG_MCF5445x
+ out_8(&gpio->par_dspi,
+ GPIO_PAR_DSPI_SIN_SIN |
+ GPIO_PAR_DSPI_SOUT_SOUT |
+ GPIO_PAR_DSPI_SCK_SCK);
+#endif
+
+#ifdef CONFIG_MCF5441x
+ pm_t *pm = (pm_t *)MMAP_PM;
+
+ out_8(&gpio->par_dspi0,
+ GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
+ GPIO_PAR_DSPI0_SCK_DSPI0SCK);
+ out_8(&gpio->srcr_dspiow, 3);
+
+ /* DSPI0 */
+ out_8(&pm->pmcr0, 23);
+#endif
+}
+#endif
+
/*
* Breath some life into the CPU...
*
GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
+#ifdef CONFIG_CF_SPI
+ cfspi_port_conf();
+#endif
+
#ifdef CONFIG_SYS_FSL_I2C
out_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
}
#endif
-#ifdef CONFIG_CF_DSPI
-void cfspi_port_conf(void)
-{
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-#ifdef CONFIG_MCF5445x
- out_8(&gpio->par_dspi,
- GPIO_PAR_DSPI_SIN_SIN |
- GPIO_PAR_DSPI_SOUT_SOUT |
- GPIO_PAR_DSPI_SCK_SCK);
-#endif
-
-#ifdef CONFIG_MCF5441x
- pm_t *pm = (pm_t *) MMAP_PM;
-
- out_8(&gpio->par_dspi0,
- GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
- GPIO_PAR_DSPI0_SCK_DSPI0SCK);
- out_8(&gpio->srcr_dspiow, 3);
-
- /* DSPI0 */
- out_8(&pm->pmcr0, 23);
-#endif
-}
-
-int cfspi_claim_bus(uint bus, uint cs)
-{
- dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
- return -1;
-
- /* Clear FIFO and resume transfer */
- clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
-#ifdef CONFIG_MCF5445x
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 1:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
- break;
- case 2:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
- break;
- case 3:
- clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
- setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
- break;
- case 5:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
- break;
- }
-#endif
-
-#ifdef CONFIG_MCF5441x
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
- setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
- break;
- case 1:
- clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
- setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
- break;
- }
-#endif
-
- return 0;
-}
-
-void cfspi_release_bus(uint bus, uint cs)
-{
- dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- /* Clear FIFO */
- clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
-#ifdef CONFIG_MCF5445x
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 1:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
- break;
- case 2:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
- break;
- case 3:
- clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
- break;
- case 5:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
- break;
- }
-#endif
-
-#ifdef CONFIG_MCF5441x
- if (cs == 1)
- clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
-#endif
-}
-
-#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Angelo Dureghello <angleo@sysam.it>
+ *
+ * CPU specific dspi routines
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_CF_DSPI
+void dspi_chip_select(int cs)
+{
+ struct gpio *gpio = (struct gpio *)MMAP_GPIO;
+
+#ifdef CONFIG_MCF5445x
+ switch (cs) {
+ case 0:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+ break;
+ case 1:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
+ break;
+ case 2:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
+ break;
+ case 3:
+ clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
+ setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
+ break;
+ case 5:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
+ break;
+ }
+#endif
+#ifdef CONFIG_MCF5441x
+ switch (cs) {
+ case 0:
+ clrbits_8(&gpio->par_dspi0,
+ ~GPIO_PAR_DSPI0_PCS0_MASK);
+ setbits_8(&gpio->par_dspi0,
+ GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
+ break;
+ case 1:
+ clrbits_8(&gpio->par_dspiow,
+ GPIO_PAR_DSPIOW_DSPI0PSC1);
+ setbits_8(&gpio->par_dspiow,
+ GPIO_PAR_DSPIOW_DSPI0PSC1);
+ break;
+ }
+#endif
+}
+
+void dspi_chip_unselect(int cs)
+{
+ struct gpio *gpio = (struct gpio *)MMAP_GPIO;
+
+#ifdef CONFIG_MCF5445x
+ switch (cs) {
+ case 0:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+ break;
+ case 1:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
+ break;
+ case 2:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
+ break;
+ case 3:
+ clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
+ break;
+ case 5:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
+ break;
+ }
+#endif
+#ifdef CONFIG_MCF5441x
+ if (cs == 1)
+ clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+#endif
+}
+#endif /* CONFIG_CF_DSPI */
* then (and always) gd struct space will be reserved
*/
move.l %sp, -(%sp)
- bsr board_init_f_alloc_reserve
+ move.l #board_init_f_alloc_reserve, %a1
+ jsr (%a1)
/* update stack and frame-pointers */
move.l %d0, %sp
/* initialize reserved area */
move.l %d0, -(%sp)
- bsr board_init_f_init_reserve
+ move.l #board_init_f_init_reserve, %a1
+ jsr (%a1)
/* run low-level CPU init code (from flash) */
jbsr cpu_init_f
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
- . = ALIGN(256);
+ . = ALIGN(4);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
- . = ALIGN(256);
+ . = ALIGN(4);
__init_end = .;
+ _end = .;
+
__bss_start = .;
.bss (NOLOAD) :
{
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5208.dtsi"
+
+/ {
+ model = "Freescale M5208EVBE";
+ compatible = "fsl,M5208EVBE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5227x.dtsi"
+
+/ {
+ model = "Freescale M52277EVB";
+ compatible = "fsl,M52277EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5227x.dtsi"
+
+/ {
+ model = "Freescale M52277_stmicro";
+ compatible = "fsl,M52277_stmicro";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf523x.dtsi"
+
+/ {
+ model = "Freescale M5235EVB";
+ compatible = "fsl,M5235EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf523x.dtsi"
+
+/ {
+ model = "Freescale M5235EVB_Flash32";
+ compatible = "fsl,M5235EVB_Flash32";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5249.dtsi"
+
+/ {
+ model = "Freescale M5249EVB";
+ compatible = "fsl,M5249EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5253.dtsi"
+
+/ {
+ model = "Freescale M5253DEMO";
+ compatible = "fsl,M5253DEMO";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5272.dtsi"
+
+/ {
+ model = "Freescale M5272C3";
+ compatible = "fsl,M5272C3";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5275.dtsi"
+
+/ {
+ model = "Freescale M5275EVB";
+ compatible = "fsl,M5275EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5282.dtsi"
+
+/ {
+ model = "Freescale M5282EVB";
+ compatible = "fsl,M5282EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5301x.dtsi"
+
+/ {
+ model = "Freescale M53017EVB";
+ compatible = "fsl,M53017EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5329.dtsi"
+
+/ {
+ model = "Freescale M5329AFEE";
+ compatible = "fsl,M5329AFEE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5329.dtsi"
+
+/ {
+ model = "Freescale M5329BFEE";
+ compatible = "fsl,M5329BFEE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf537x.dtsi"
+
+/ {
+ model = "Freescale M5373EVB";
+ compatible = "fsl,M5373EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Freescale M54418TWR";
+ compatible = "fsl,M54418TWR";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Freescale M54418TWR_nand_mii";
+ compatible = "fsl,M54418TWR_nand_mii";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Freescale M54418TWR_nand_rmii";
+ compatible = "fsl,M54418TWR_nand_rmii";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Freescale M54418TWR_nand_rmii_lowfreq";
+ compatible = "fsl,M54418TWR_nand_rmii_lowfreq";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Freescale M54418TWR_serial_mii";
+ compatible = "fsl,M54418TWR_serial_mii";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Freescale M54418TWR_serial_rmii";
+ compatible = "fsl,M54418TWR_serial_rmii";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54451EVB";
+ compatible = "fsl,M54451EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54451EVB_stmicro";
+ compatible = "fsl,M54451EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54455EVB";
+ compatible = "fsl,M54455EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54455EVB_a66";
+ compatible = "fsl,M54455EVB_a66";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54455EVB_i66";
+ compatible = "fsl,M54455EVB_i66";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54455EVB_intel";
+ compatible = "fsl,M5275EVB_intel";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54455EVB_stm33";
+ compatible = "fsl,M5275EVB_stm33";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475AFE";
+ compatible = "fsl,M5475AFE";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475BFE";
+ compatible = "fsl,M5475BFE";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475CFE";
+ compatible = "fsl,M5475CFE";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475DFE";
+ compatible = "fsl,M5475DFE";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475EFE";
+ compatible = "fsl,M5475EFE";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475FFE";
+ compatible = "fsl,M5475FFE";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475GFE";
+ compatible = "fsl,M5475GFE";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485AFE";
+ compatible = "fsl,M5485AFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485BFE";
+ compatible = "fsl,M5485BFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485CFE";
+ compatible = "fsl,M5485CFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485DFE";
+ compatible = "fsl,M5485DFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485EFE";
+ compatible = "fsl,M5485EFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485FFE";
+ compatible = "fsl,M5485FFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485GFE";
+ compatible = "fsl,M5485GFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485HFE";
+ compatible = "fsl,M5485HFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+dtb-$(CONFIG_TARGET_M52277EVB) += M52277EVB.dtb \
+ M52277EVB_stmicro.dtb
+dtb-$(CONFIG_TARGET_M5235EVB) += M5235EVB.dtb \
+ M5235EVB_Flash32.dtb
+dtb-$(CONFIG_TARGET_COBRA5272) += cobra5272.dtb
+dtb-$(CONFIG_TARGET_EB_CPU5282) += eb_cpu5282.dtb \
+ eb_cpu5282_internal.dtb
+dtb-$(CONFIG_TARGET_M5208EVBE) += M5208EVBE.dtb
+dtb-$(CONFIG_TARGET_M5249EVB) += M5249EVB.dtb
+dtb-$(CONFIG_TARGET_M5253DEMO) += M5253DEMO.dtb
+dtb-$(CONFIG_TARGET_M5272C3) += M5272C3.dtb
+dtb-$(CONFIG_TARGET_M5275EVB) += M5275EVB.dtb
+dtb-$(CONFIG_TARGET_M5282EVB) += M5282EVB.dtb
+dtb-$(CONFIG_TARGET_ASTRO_MCF5373L) += astro_mcf5373l.dtb
+dtb-$(CONFIG_TARGET_M53017EVB) += M53017EVB.dtb
+dtb-$(CONFIG_TARGET_M5329EVB) += M5329AFEE.dtb M5329BFEE.dtb
+dtb-$(CONFIG_TARGET_M5373EVB) += M5373EVB.dtb
+dtb-$(CONFIG_TARGET_M54418TWR) += M54418TWR.dtb \
+ M54418TWR_nand_mii.dtb \
+ M54418TWR_nand_rmii.dtb \
+ M54418TWR_serial_mii.dtb \
+ M54418TWR_serial_rmii.dtb \
+ M54418TWR_nand_rmii_lowfreq.dtb
+dtb-$(CONFIG_TARGET_M54451EVB) += M54451EVB.dtb \
+ M54451EVB_stmicro.dtb
+dtb-$(CONFIG_TARGET_M54455EVB) += M54455EVB.dtb \
+ M54455EVB_intel.dtb \
+ M54455EVB_stm33.dtb \
+ M54455EVB_a66.dtb \
+ M54455EVB_i66.dtb
+dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb
+dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb
+dtb-$(CONFIG_TARGET_M5475EVB) += M5475AFE.dtb \
+ M5475BFE.dtb \
+ M5475CFE.dtb \
+ M5475DFE.dtb \
+ M5475EFE.dtb \
+ M5475FFE.dtb \
+ M5475GFE.dtb
+dtb-$(CONFIG_TARGET_M5485EVB) += M5485AFE.dtb \
+ M5485BFE.dtb \
+ M5485CFE.dtb \
+ M5485DFE.dtb \
+ M5485EFE.dtb \
+ M5485FFE.dtb \
+ M5485GFE.dtb \
+ M5485HFE.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := *.dtb
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5307.dtsi"
+
+/ {
+ model = "Sysam AMCORE";
+ compatible = "sysam,AMCORE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf537x.dtsi"
+
+/ {
+ model = "Astro mcf5373l";
+ compatible = "astro,mcf5373l";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5272.dtsi"
+
+/ {
+ model = "Cobra 5272";
+ compatible = "cobra,M5272";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5282.dtsi"
+
+/ {
+ model = "BuS eb_cpuM5282";
+ compatible = "bus,eb_cpuM5282";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5282.dtsi"
+
+/ {
+ model = "BuS eb_cpu5282_internals";
+ compatible = "bus,eb_cpu5282_internals";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5208";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart@fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5227x";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &dspi0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart@fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+
+ dspi0: dspi@fc05c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfc05c000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf523x";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ipsbar: ipsbar@4000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x40000000 0x40000000>;
+ reg = <0x40000000 0x40000000>;
+
+ uart0: uart@200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@240 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x240 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@280 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x280 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5249";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mbar: mbar@10000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x10000000 0x10000>;
+ reg = <0x10000000 0x10000>;
+
+ uart0: uart@1c0 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x1c0 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5253";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mbar: mbar@10000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x10000000 0x10000>;
+ reg = <0x10000000 0x10000>;
+
+ uart0: uart@1c0 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x1c0 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+
+ uart3: uart@c00 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xc00 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5271";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ipsbar: ipsbar@4000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x40000000 0x40000000>;
+ reg = <0x40000000 0x40000000>;
+
+ uart0: uart@200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@240 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x240 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@280 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x280 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5272";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mbar: mbar@10000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x10000000 0x10000>;
+ reg = <0x10000000 0x10000>;
+
+ uart0: uart@100 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x100 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@140 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x140 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5275";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ipsbar: ipsbar@4000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x40000000 0x40000000>;
+ reg = <0x40000000 0x40000000>;
+
+ uart0: uart@200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@240 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x240 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@280 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x280 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5282";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ipsbar: ipsbar@4000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x40000000 0x40000000>;
+ reg = <0x40000000 0x40000000>;
+
+ uart0: uart@200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@240 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x240 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@280 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x280 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5301x";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &dspi0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart@fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+
+ dspi0: dspi@fc05c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfc05c000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5307";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* MBAR */
+ mbar: mbar@10000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x10000000 0x10000>;
+ reg = <0x10000000 0x10000>;
+
+ uart0: uart@1c0 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x1c0 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5329";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart@fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5329";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart@fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5441x";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &dspi0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart@fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+
+ uart3: uart@fc06c000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc06c000 0x40>;
+ status = "disabled";
+ };
+
+ dspi0: dspi@fc05c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfc05c000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+
+ dspi1: dspi@fc03c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfc03c000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+
+ dspi2: dspi@ec038000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xec038000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+
+ dspi3: dspi@ec03c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xec03c00 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5445x";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &dspi0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart@fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+
+ dspi0: dspi@fc05c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfc05c000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf54x5";
+
+ aliases {
+ /* TO DO, clarify on serial, this SoC seems to have SPC and
+ * no UARTS.
+ */
+ spi0 = &dspi0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mbar: mbar@80000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x80000000 0x10000>;
+ reg = <0x80000000 0x10000>;
+
+ dspi0: dspi@8a00 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x8a00 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Sysam stmark2";
+ compatible = "sysam,stmark2";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ spi-mode = <3>;
+ status = "okay";
+
+ flash: is25lp128@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <60000000>;
+ reg = <1>;
+ };
+};
/* Bit definitions and macros for DRFDR group */
#define DSPI_RFDR_RXDATA(x) (((x)&0x0000FFFF))
+/* Architecture-related operations */
+void dspi_chip_select(int cs);
+void dspi_chip_unselect(int cs);
+
#endif /* __DSPI_H__ */
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
select FSL_DDR_INTERACTIVE
- imply CMD_SATA
config TARGET_T2080RDB
bool "Support T2080RDB"
select SUPPORT_SPL
select PHYS_64BIT
imply CMD_SATA
+ imply FSL_SATA
imply PANIC_HANG
config TARGET_T2081QDS
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
select FSL_IFC
- imply CMD_SATA
imply CMD_NAND
imply CMD_REGINFO
- imply FSL_SATA
config ARCH_T2081
bool
device_type = "open-pic";
clock-frequency = <0x0>;
};
+
+ esdhc: esdhc@114000 {
+ compatible = "fsl,esdhc";
+ reg = <0x114000 0x1000>;
+ interrupts = <48 2 0 0>;
+ clock-frequency = <0>;
+ sdhci,auto-cmd12;
+ bus-width = <4>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ };
+
+ usb0: usb@210000 {
+ compatible = "fsl-usb2-mph";
+ reg = <0x210000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <44 0x2 0 0>;
+ phy_type = "utmi";
+ };
+
+ usb1: usb@211000 {
+ compatible = "fsl-usb2-dr";
+ reg = <0x211000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <45 0x2 0 0>;
+ dr_mode = "host";
+ phy_type = "utmi";
+ };
+
+ sata0: sata@220000 {
+ compatible = "fsl,pq-sata-v2";
+ reg = <0x220000 0x1000>;
+ interrupts = <68 0x2 0 0>;
+ sata-number = <0x0>;
+ sata-fpdma = <0x0>;
+ };
+
+ sata1: sata@221000 {
+ compatible = "fsl,pq-sata-v2";
+ reg = <0x221000 0x1000>;
+ interrupts = <69 0x2 0 0>;
+ sata-number = <0x0>;
+ sata-fpdma = <0x0>;
+ };
};
};
#include <jffs2/load_kernel.h>
#include <mtd_node.h>
-struct reg_cell {
- unsigned int r0;
- unsigned int r1;
-};
-
static int fdt_del_subnodes(const void *blob, int parent_offset)
{
int off, ndepth;
{
struct list_head *pentry;
struct part_info *part;
- struct reg_cell cell;
int off, ndepth = 0;
int part_num, ret;
+ int sizecell;
char buf[64];
ret = fdt_del_partitions(blob, parent_offset);
return ret;
/*
+ * Check if size/address is 1 or 2 cells.
+ * We assume #address-cells and #size-cells have same value.
+ */
+ sizecell = fdt_getprop_u32_default_node(blob, parent_offset,
+ 0, "#size-cells", 1);
+
+ /*
* Check if it is nand {}; subnode, adjust
* the offset in this case
*/
goto err_prop;
}
- cell.r0 = cpu_to_fdt32(part->offset);
- cell.r1 = cpu_to_fdt32(part->size);
add_reg:
- ret = fdt_setprop(blob, newoff, "reg", &cell, sizeof(cell));
+ if (sizecell == 2) {
+ ret = fdt_setprop_u64(blob, newoff,
+ "reg", part->offset);
+ if (!ret)
+ ret = fdt_appendprop_u64(blob, newoff,
+ "reg", part->size);
+ } else {
+ ret = fdt_setprop_u32(blob, newoff,
+ "reg", part->offset);
+ if (!ret)
+ ret = fdt_appendprop_u32(blob, newoff,
+ "reg", part->size);
+ }
+
if (ret == -FDT_ERR_NOSPACE) {
ret = fdt_increase_size(blob, 512);
if (!ret)
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_TARGET_M5208EVBE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5208EVBE"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_TARGET_M52277EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M52277EVB"
CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_TARGET_M52277EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M52277EVB_stmicro"
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFC00000
CONFIG_TARGET_M5235EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5235EVB_Flash32"
CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_TARGET_M5235EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5235EVB"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_TARGET_M5249EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5249EVB"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5253DEMO=y
+CONFIG_DEFAULT_DEVICE_TREE="M5253DEMO"
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_TARGET_M5272C3=y
+CONFIG_DEFAULT_DEVICE_TREE="M5272C3"
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_TARGET_M5275EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5275EVB"
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_TARGET_M5282EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5282EVB"
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_TARGET_M53017EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M53017EVB"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock3 rw rootfstype=jffs2"
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_TARGET_M5329EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5329AFEE"
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_TARGET_M5329EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5329BFEE"
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_TARGET_M5373EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5373EVB"
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54418TWR=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR"
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2 ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200"
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_CF_SPI=y
+CONFIG_DM_SPI=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54418TWR=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_mii"
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=25000000"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro,-(jffs2) console=ttyS0,115200"
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54418TWR=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_rmii"
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=50000000"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro,-(jffs2) console=ttyS0,115200"
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54418TWR=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_rmii_lowfreq"
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_INPUT_CLKSRC=50000000"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro,-(jffs2) console=ttyS0,115200"
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54418TWR=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_serial_mii"
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=25000000"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2 ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200"
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54418TWR=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_serial_rmii"
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2 ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200"
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_TARGET_M54451EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M54451EVB"
CONFIG_SYS_EXTRA_OPTIONS="SYS_INPUT_CLKSRC=24000000"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54451EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M54451EVB_stmicro"
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_INPUT_CLKSRC=24000000"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_TARGET_M54455EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_a66"
CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=66666666"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_TARGET_M54455EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB"
CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=33333333"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_TARGET_M54455EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_i66"
CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=66666666"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_TARGET_M54455EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_intel"
CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=33333333"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x4FE00000
CONFIG_TARGET_M54455EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_stm33"
CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_INPUT_CLKSRC=33333333"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5475EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475AFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5475EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475BFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5475EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475CFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5475EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475DFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5475EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475EFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5475EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475FFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5475EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475GFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5485EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485AFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5485EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485BFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5485EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485CFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5485EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485DFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5485EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485EFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5485EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485FFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5485EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485GFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5485EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485HFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
+CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
+CONFIG_FSL_AHCI=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_MII=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
+CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
+CONFIG_FSL_AHCI=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_MII=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_DM=y
+CONFIG_FSL_AHCI=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_MII=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
+CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
+CONFIG_FSL_AHCI=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_MII=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_IS_IN_REMOTE=y
+CONFIG_DM=y
+CONFIG_FSL_AHCI=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_MII=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_DM=y
+CONFIG_FSL_AHCI=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_MII=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_TEXT_BASE=0xFFC00000
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_TARGET_AMCORE=y
+CONFIG_DEFAULT_DEVICE_TREE="amcore"
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_TARGET_ASTRO_MCF5373L=y
+CONFIG_DEFAULT_DEVICE_TREE="astro_mcf5373l"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS=" console=ttyS2,115200 rootfstype=romfs loaderversion=$loaderversion"
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_TARGET_COBRA5272=y
+CONFIG_DEFAULT_DEVICE_TREE="cobra5272"
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF000000
CONFIG_TARGET_EB_CPU5282=y
+CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282"
CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xFF000400"
CONFIG_BOOTDELAY=5
# CONFIG_CONSOLE_MUX is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xF0000000
CONFIG_TARGET_EB_CPU5282=y
+CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282_internal"
CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xF0000418"
CONFIG_BOOTDELAY=5
# CONFIG_CONSOLE_MUX is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_STMARK2=y
+CONFIG_DEFAULT_DEVICE_TREE="stmark2"
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=30000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_CF_SPI=y
CONFIG_REGEX=y
--- /dev/null
+Freescale ColdFire UART
+
+Required properties:
+- compatible : should be "fsl,mcf-uart"
+- reg: start address and size of the registers
+
+Example:
+
+soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart@fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+};
--- /dev/null
+Freescale ColdFire DSPI controller
+
+Required properties:
+- compatible : "fsl,mcf-dspi"
+- #address-cells: <1>, as required by generic SPI binding
+- #size-cells: <0>, also as required by generic SPI binding
+- reg : offset and length of the register set for the device
+
+Optional properties:
+- spi-max-frequency : max supported spi frequency
+- num-cs : the number of the chipselect signals
+- spi-mode: spi motorola mode, 0 to 3
+- ctar-params: CTAR0 to 7 register configuration, as an array
+ of 8 integer fields for each register, where each register
+ is defined as: <fmsz, pcssck, pasc, pdt, cssck, asc, dt, br>.
+
+Example:
+
+dspi0: dspi@fc05c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfc05c000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ ctar-fields = <7, 0, 0, 0, 0, 0, 1, 6>,
+ <7, 0, 0, 0, 0, 0, 1, 6>,
+ <7, 0, 0, 0, 0, 0, 1, 6>;
+};
Enable this driver to support Sata devices through
Synopsys DWC AHCI module.
+config FSL_AHCI
+ bool "Enable Freescale AHCI driver support"
+ select SCSI_AHCI
+ depends on AHCI
+ depends on DM_SCSI
+ help
+ Enable this driver to support Sata devices found in
+ some Freescale PowerPC SoCs.
+
+
config DWC_AHSATA
bool "Enable DWC AHSATA driver support"
select LIBATA
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-$(CONFIG_DWC_AHCI) += dwc_ahci.o
+obj-$(CONFIG_FSL_AHCI) += fsl_ahci.o
obj-$(CONFIG_AHCI) += ahci-uclass.o
obj-$(CONFIG_AHCI_PCI) += ahci-pci.o
obj-$(CONFIG_SCSI_AHCI) += ahci.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * NXP PPC SATA platform driver
+ *
+ * (C) Copyright 2019 NXP, Inc.
+ *
+ */
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <dm/lists.h>
+#include <dm.h>
+#include <ahci.h>
+#include <scsi.h>
+#include <libata.h>
+#include <sata.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <fis.h>
+
+#include "fsl_sata.h"
+
+struct fsl_ahci_priv {
+ u32 base;
+ u32 flag;
+ u32 number;
+ fsl_sata_t *fsl_sata;
+};
+
+static int fsl_ahci_bind(struct udevice *dev)
+{
+ return device_bind_driver(dev, "fsl_ahci_scsi", "fsl_ahci_scsi", NULL);
+}
+
+static int fsl_ahci_ofdata_to_platdata(struct udevice *dev)
+{
+ struct fsl_ahci_priv *priv = dev_get_priv(dev);
+
+ priv->number = dev_read_u32_default(dev, "sata-number", -1);
+ priv->flag = dev_read_u32_default(dev, "sata-fpdma", -1);
+
+ priv->base = dev_read_addr(dev);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int ata_wait_register(unsigned __iomem *addr, u32 mask,
+ u32 val, u32 timeout_msec)
+{
+ int i;
+
+ for (i = 0; ((in_le32(addr) & mask) != val) && i < timeout_msec; i++)
+ mdelay(1);
+
+ return (i < timeout_msec) ? 0 : -1;
+}
+
+static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
+{
+ printf("Status FIS dump:\n\r");
+ printf("fis_type: %02x\n\r", s->fis_type);
+ printf("pm_port_i: %02x\n\r", s->pm_port_i);
+ printf("status: %02x\n\r", s->status);
+ printf("error: %02x\n\r", s->error);
+ printf("lba_low: %02x\n\r", s->lba_low);
+ printf("lba_mid: %02x\n\r", s->lba_mid);
+ printf("lba_high: %02x\n\r", s->lba_high);
+ printf("device: %02x\n\r", s->device);
+ printf("lba_low_exp: %02x\n\r", s->lba_low_exp);
+ printf("lba_mid_exp: %02x\n\r", s->lba_mid_exp);
+ printf("lba_high_exp: %02x\n\r", s->lba_high_exp);
+ printf("res1: %02x\n\r", s->res1);
+ printf("sector_count: %02x\n\r", s->sector_count);
+ printf("sector_count_exp: %02x\n\r", s->sector_count_exp);
+}
+
+static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg)
+{
+ printf("\n\rSATA: %08x\n\r", (u32)reg);
+ printf("CQR: %08x\n\r", in_le32(®->cqr));
+ printf("CAR: %08x\n\r", in_le32(®->car));
+ printf("CCR: %08x\n\r", in_le32(®->ccr));
+ printf("CER: %08x\n\r", in_le32(®->cer));
+ printf("CQR: %08x\n\r", in_le32(®->cqr));
+ printf("DER: %08x\n\r", in_le32(®->der));
+ printf("CHBA: %08x\n\r", in_le32(®->chba));
+ printf("HStatus: %08x\n\r", in_le32(®->hstatus));
+ printf("HControl: %08x\n\r", in_le32(®->hcontrol));
+ printf("CQPMP: %08x\n\r", in_le32(®->cqpmp));
+ printf("SIG: %08x\n\r", in_le32(®->sig));
+ printf("ICC: %08x\n\r", in_le32(®->icc));
+ printf("SStatus: %08x\n\r", in_le32(®->sstatus));
+ printf("SError: %08x\n\r", in_le32(®->serror));
+ printf("SControl: %08x\n\r", in_le32(®->scontrol));
+ printf("SNotification: %08x\n\r", in_le32(®->snotification));
+ printf("TransCfg: %08x\n\r", in_le32(®->transcfg));
+ printf("TransStatus: %08x\n\r", in_le32(®->transstatus));
+ printf("LinkCfg: %08x\n\r", in_le32(®->linkcfg));
+ printf("LinkCfg1: %08x\n\r", in_le32(®->linkcfg1));
+ printf("LinkCfg2: %08x\n\r", in_le32(®->linkcfg2));
+ printf("LinkStatus: %08x\n\r", in_le32(®->linkstatus));
+ printf("LinkStatus1: %08x\n\r", in_le32(®->linkstatus1));
+ printf("PhyCtrlCfg: %08x\n\r", in_le32(®->phyctrlcfg));
+ printf("SYSPR: %08x\n\r", in_be32(®->syspr));
+}
+
+static int init_sata(struct fsl_ahci_priv *priv)
+{
+ int i;
+ u32 cda;
+ u32 val32;
+ u32 sig;
+ fsl_sata_t *sata;
+ u32 length, align;
+ cmd_hdr_tbl_t *cmd_hdr;
+ fsl_sata_reg_t __iomem *reg;
+
+ int dev = priv->number;
+
+ if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
+ printf("the sata index %d is out of ranges\n\r", dev);
+ return -EINVAL;
+ }
+
+#ifdef CONFIG_MPC85xx
+ if (dev == 0 && (!is_serdes_configured(SATA1))) {
+ printf("SATA%d [dev = %d] is not enabled\n", dev + 1, dev);
+ return -EINVAL;
+ }
+ if (dev == 1 && (!is_serdes_configured(SATA2))) {
+ printf("SATA%d [dev = %d] is not enabled\n", dev + 1, dev);
+ return -EINVAL;
+ }
+#endif
+
+ /* Allocate SATA device driver struct */
+ sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t));
+ if (!sata) {
+ printf("alloc the sata device struct failed\n\r");
+ return -ENOMEM;
+ }
+ /* Zero all of the device driver struct */
+ memset((void *)sata, 0, sizeof(fsl_sata_t));
+
+ sata->dma_flag = priv->flag;
+ snprintf(sata->name, 12, "SATA%d", dev);
+
+ /* Set the controller register base address to device struct */
+ reg = (fsl_sata_reg_t *)priv->base;
+ sata->reg_base = reg;
+
+ /* Allocate the command header table, 4 bytes aligned */
+ length = sizeof(struct cmd_hdr_tbl);
+ align = SATA_HC_CMD_HDR_TBL_ALIGN;
+ sata->cmd_hdr_tbl_offset = (void *)malloc(length + align);
+ if (!sata->cmd_hdr_tbl_offset) {
+ printf("alloc the command header failed\n\r");
+ return -ENOMEM;
+ }
+
+ cmd_hdr = (cmd_hdr_tbl_t *)(((u32)sata->cmd_hdr_tbl_offset + align)
+ & ~(align - 1));
+ sata->cmd_hdr = cmd_hdr;
+
+ /* Zero all of the command header table */
+ memset((void *)sata->cmd_hdr_tbl_offset, 0, length + align);
+
+ /* Allocate command descriptor for all command */
+ length = sizeof(struct cmd_desc) * SATA_HC_MAX_CMD;
+ align = SATA_HC_CMD_DESC_ALIGN;
+ sata->cmd_desc_offset = (void *)malloc(length + align);
+ if (!sata->cmd_desc_offset) {
+ printf("alloc the command descriptor failed\n\r");
+ return -ENOMEM;
+ }
+ sata->cmd_desc = (cmd_desc_t *)(((u32)sata->cmd_desc_offset + align)
+ & ~(align - 1));
+ /* Zero all of command descriptor */
+ memset((void *)sata->cmd_desc_offset, 0, length + align);
+
+ /* Link the command descriptor to command header */
+ for (i = 0; i < SATA_HC_MAX_CMD; i++) {
+ cda = ((u32)sata->cmd_desc + SATA_HC_CMD_DESC_SIZE * i)
+ & ~(CMD_HDR_CDA_ALIGN - 1);
+ cmd_hdr->cmd_slot[i].cda = cpu_to_le32(cda);
+ }
+
+ /* To have safe state, force the controller offline */
+ val32 = in_le32(®->hcontrol);
+ val32 &= ~HCONTROL_ONOFF;
+ val32 |= HCONTROL_FORCE_OFFLINE;
+ out_le32(®->hcontrol, val32);
+
+ /* Wait the controller offline */
+ ata_wait_register(®->hstatus, HSTATUS_ONOFF, 0, 1000);
+
+ /* Set the command header base address to CHBA register to tell DMA */
+ out_le32(®->chba, (u32)cmd_hdr & ~0x3);
+
+ /* Snoop for the command header */
+ val32 = in_le32(®->hcontrol);
+ val32 |= HCONTROL_HDR_SNOOP;
+ out_le32(®->hcontrol, val32);
+
+ /* Disable all of interrupts */
+ val32 = in_le32(®->hcontrol);
+ val32 &= ~HCONTROL_INT_EN_ALL;
+ out_le32(®->hcontrol, val32);
+
+ /* Clear all of interrupts */
+ val32 = in_le32(®->hstatus);
+ out_le32(®->hstatus, val32);
+
+ /* Set the ICC, no interrupt coalescing */
+ out_le32(®->icc, 0x01000000);
+
+ /* No PM attatched, the SATA device direct connect */
+ out_le32(®->cqpmp, 0);
+
+ /* Clear SError register */
+ val32 = in_le32(®->serror);
+ out_le32(®->serror, val32);
+
+ /* Clear CER register */
+ val32 = in_le32(®->cer);
+ out_le32(®->cer, val32);
+
+ /* Clear DER register */
+ val32 = in_le32(®->der);
+ out_le32(®->der, val32);
+
+ /* No device detection or initialization action requested */
+ out_le32(®->scontrol, 0x00000300);
+
+ /* Configure the transport layer, default value */
+ out_le32(®->transcfg, 0x08000016);
+
+ /* Configure the link layer, default value */
+ out_le32(®->linkcfg, 0x0000ff34);
+
+ /* Bring the controller online */
+ val32 = in_le32(®->hcontrol);
+ val32 |= HCONTROL_ONOFF;
+ out_le32(®->hcontrol, val32);
+
+ mdelay(100);
+
+ /* print sata device name */
+ printf("%s ", sata->name);
+
+ /* Wait PHY RDY signal changed for 500ms */
+ ata_wait_register(®->hstatus, HSTATUS_PHY_RDY,
+ HSTATUS_PHY_RDY, 500);
+
+ /* Check PHYRDY */
+ val32 = in_le32(®->hstatus);
+ if (val32 & HSTATUS_PHY_RDY) {
+ sata->link = 1;
+ } else {
+ sata->link = 0;
+ printf("(No RDY)\n\r");
+ return -EINVAL;
+ }
+
+ /* Wait for signature updated, which is 1st D2H */
+ ata_wait_register(®->hstatus, HSTATUS_SIGNATURE,
+ HSTATUS_SIGNATURE, 10000);
+
+ if (val32 & HSTATUS_SIGNATURE) {
+ sig = in_le32(®->sig);
+ debug("Signature updated, the sig =%08x\n\r", sig);
+ sata->ata_device_type = ata_dev_classify(sig);
+ }
+
+ /* Check the speed */
+ val32 = in_le32(®->sstatus);
+ if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN1)
+ printf("(1.5 Gbps)\n\r");
+ else if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN2)
+ printf("(3 Gbps)\n\r");
+
+ priv->fsl_sata = sata;
+
+ return 0;
+}
+
+static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata,
+ struct sata_fis_h2d *cfis,
+ int is_ncq, int tag,
+ u8 *buffer, u32 len)
+{
+ cmd_hdr_entry_t *cmd_hdr;
+ cmd_desc_t *cmd_desc;
+ sata_fis_h2d_t *h2d;
+ prd_entry_t *prde;
+ u32 ext_c_ddc;
+ u32 prde_count;
+ u32 val32;
+ u32 ttl;
+ u32 der;
+ int i;
+
+ fsl_sata_reg_t *reg = sata->reg_base;
+
+ /* Check xfer length */
+ if (len > SATA_HC_MAX_XFER_LEN) {
+ printf("max transfer length is 64MB\n\r");
+ return 0;
+ }
+
+ /* Setup the command descriptor */
+ cmd_desc = sata->cmd_desc + tag;
+
+ /* Get the pointer cfis of command descriptor */
+ h2d = (sata_fis_h2d_t *)cmd_desc->cfis;
+
+ /* Zero the cfis of command descriptor */
+ memset((void *)h2d, 0, SATA_HC_CMD_DESC_CFIS_SIZE);
+
+ /* Copy the cfis from user to command descriptor */
+ h2d->fis_type = cfis->fis_type;
+ h2d->pm_port_c = cfis->pm_port_c;
+ h2d->command = cfis->command;
+
+ h2d->features = cfis->features;
+ h2d->features_exp = cfis->features_exp;
+
+ h2d->lba_low = cfis->lba_low;
+ h2d->lba_mid = cfis->lba_mid;
+ h2d->lba_high = cfis->lba_high;
+ h2d->lba_low_exp = cfis->lba_low_exp;
+ h2d->lba_mid_exp = cfis->lba_mid_exp;
+ h2d->lba_high_exp = cfis->lba_high_exp;
+
+ if (!is_ncq) {
+ h2d->sector_count = cfis->sector_count;
+ h2d->sector_count_exp = cfis->sector_count_exp;
+ } else { /* NCQ */
+ h2d->sector_count = (u8)(tag << 3);
+ }
+
+ h2d->device = cfis->device;
+ h2d->control = cfis->control;
+
+ /* Setup the PRD table */
+ prde = (prd_entry_t *)cmd_desc->prdt;
+ memset((void *)prde, 0, sizeof(struct prdt));
+
+ prde_count = 0;
+ ttl = len;
+ for (i = 0; i < SATA_HC_MAX_PRD_DIRECT; i++) {
+ if (!len)
+ break;
+ prde->dba = cpu_to_le32((u32)buffer & ~0x3);
+ debug("dba = %08x\n\r", (u32)buffer);
+
+ if (len < PRD_ENTRY_MAX_XFER_SZ) {
+ ext_c_ddc = PRD_ENTRY_DATA_SNOOP | len;
+ debug("ext_c_ddc1 = %08x, len = %08x\n\r",
+ ext_c_ddc, len);
+ prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
+ prde_count++;
+ prde++;
+ } else {
+ ext_c_ddc = PRD_ENTRY_DATA_SNOOP; /* 4M bytes */
+ debug("ext_c_ddc2 = %08x, len = %08x\n\r",
+ ext_c_ddc, len);
+ prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
+ buffer += PRD_ENTRY_MAX_XFER_SZ;
+ len -= PRD_ENTRY_MAX_XFER_SZ;
+ prde_count++;
+ prde++;
+ }
+ }
+
+ /* Setup the command slot of cmd hdr */
+ cmd_hdr = (cmd_hdr_entry_t *)&sata->cmd_hdr->cmd_slot[tag];
+
+ cmd_hdr->cda = cpu_to_le32((u32)cmd_desc & ~0x3);
+
+ val32 = prde_count << CMD_HDR_PRD_ENTRY_SHIFT;
+ val32 |= sizeof(sata_fis_h2d_t);
+ cmd_hdr->prde_fis_len = cpu_to_le32(val32);
+
+ cmd_hdr->ttl = cpu_to_le32(ttl);
+
+ if (!is_ncq)
+ val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP;
+ else
+ val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP |
+ CMD_HDR_ATTR_FPDMA;
+
+ tag &= CMD_HDR_ATTR_TAG;
+ val32 |= tag;
+
+ debug("attribute = %08x\n\r", val32);
+ cmd_hdr->attribute = cpu_to_le32(val32);
+
+ /* Make sure cmd desc and cmd slot valid before command issue */
+ sync();
+
+ /* PMP*/
+ val32 = (u32)(h2d->pm_port_c & 0x0f);
+ out_le32(®->cqpmp, val32);
+
+ /* Wait no active */
+ if (ata_wait_register(®->car, (1 << tag), 0, 10000))
+ printf("Wait no active time out\n\r");
+
+ /* Issue command */
+ if (!(in_le32(®->cqr) & (1 << tag))) {
+ val32 = 1 << tag;
+ out_le32(®->cqr, val32);
+ }
+
+ /* Wait command completed for 10s */
+ if (ata_wait_register(®->ccr, (1 << tag), (1 << tag), 10000)) {
+ if (!is_ncq)
+ printf("Non-NCQ command time out\n\r");
+ else
+ printf("NCQ command time out\n\r");
+ }
+
+ val32 = in_le32(®->cer);
+
+ if (val32) {
+ fsl_sata_dump_sfis((struct sata_fis_d2h *)cmd_desc->sfis);
+ printf("CE at device\n\r");
+ fsl_sata_dump_regs(reg);
+ der = in_le32(®->der);
+ out_le32(®->cer, val32);
+ out_le32(®->der, der);
+ }
+
+ /* Clear complete flags */
+ val32 = in_le32(®->ccr);
+ out_le32(®->ccr, val32);
+
+ return len;
+}
+
+static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
+ enum cmd_type command_type, int tag, u8 *buffer,
+ u32 len)
+{
+ int rc;
+
+ if (tag > SATA_HC_MAX_CMD || tag < 0) {
+ printf("tag is out of range, tag=%d\n\r", tag);
+ return -1;
+ }
+
+ switch (command_type) {
+ case CMD_ATA:
+ rc = fsl_ata_exec_ata_cmd(sata, cfis, 0, tag, buffer, len);
+ return rc;
+ case CMD_NCQ:
+ rc = fsl_ata_exec_ata_cmd(sata, cfis, 1, tag, buffer, len);
+ return rc;
+ case CMD_ATAPI:
+ case CMD_VENDOR_BIST:
+ case CMD_BIST:
+ printf("not support now\n\r");
+ return -1;
+ default:
+ break;
+ }
+
+ return -1;
+}
+
+static void fsl_sata_identify(fsl_sata_t *sata, u16 *id)
+{
+ struct sata_fis_h2d h2d, *cfis = &h2d;
+
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis->pm_port_c = 0x80; /* is command */
+ cfis->command = ATA_CMD_ID_ATA;
+
+ fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, (u8 *)id, ATA_ID_WORDS * 2);
+ ata_swap_buf_le16(id, ATA_ID_WORDS);
+}
+
+static void fsl_sata_xfer_mode(fsl_sata_t *sata, u16 *id)
+{
+ sata->pio = id[ATA_ID_PIO_MODES];
+ sata->mwdma = id[ATA_ID_MWDMA_MODES];
+ sata->udma = id[ATA_ID_UDMA_MODES];
+ debug("pio %04x, mwdma %04x, udma %04x\n\r", sata->pio,
+ sata->mwdma, sata->udma);
+}
+
+static void fsl_sata_init_wcache(fsl_sata_t *sata, u16 *id)
+{
+ if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
+ sata->wcache = 1;
+ if (ata_id_has_flush(id))
+ sata->flush = 1;
+ if (ata_id_has_flush_ext(id))
+ sata->flush_ext = 1;
+}
+
+static void fsl_sata_set_features(fsl_sata_t *sata)
+{
+ struct sata_fis_h2d h2d, *cfis = &h2d;
+ u8 udma_cap;
+
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis->pm_port_c = 0x80; /* is command */
+ cfis->command = ATA_CMD_SET_FEATURES;
+ cfis->features = SETFEATURES_XFER;
+
+ /* First check the device capablity */
+ udma_cap = (u8)(sata->udma & 0xff);
+ debug("udma_cap %02x\n\r", udma_cap);
+
+ if (udma_cap == ATA_UDMA6)
+ cfis->sector_count = XFER_UDMA_6;
+ if (udma_cap == ATA_UDMA5)
+ cfis->sector_count = XFER_UDMA_5;
+ if (udma_cap == ATA_UDMA4)
+ cfis->sector_count = XFER_UDMA_4;
+ if (udma_cap == ATA_UDMA3)
+ cfis->sector_count = XFER_UDMA_3;
+
+ fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
+}
+
+static u32 fsl_sata_rw_cmd(fsl_sata_t *sata, u32 start, u32 blkcnt,
+ u8 *buffer, int is_write)
+{
+ struct sata_fis_h2d h2d, *cfis = &h2d;
+ u32 block;
+
+ block = start;
+
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis->pm_port_c = 0x80; /* is command */
+ cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
+ cfis->device = ATA_LBA;
+
+ cfis->device |= (block >> 24) & 0xf;
+ cfis->lba_high = (block >> 16) & 0xff;
+ cfis->lba_mid = (block >> 8) & 0xff;
+ cfis->lba_low = block & 0xff;
+ cfis->sector_count = (u8)(blkcnt & 0xff);
+
+ fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer,
+ ATA_SECT_SIZE * blkcnt);
+ return blkcnt;
+}
+
+static void fsl_sata_flush_cache(fsl_sata_t *sata)
+{
+ struct sata_fis_h2d h2d, *cfis = &h2d;
+
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis->pm_port_c = 0x80; /* is command */
+ cfis->command = ATA_CMD_FLUSH;
+
+ fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
+}
+
+static u32 fsl_sata_rw_cmd_ext(fsl_sata_t *sata, u32 start,
+ u32 blkcnt, u8 *buffer, int is_write)
+{
+ struct sata_fis_h2d h2d, *cfis = &h2d;
+ u64 block;
+
+ block = (u64)start;
+
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis->pm_port_c = 0x80; /* is command */
+
+ cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
+ : ATA_CMD_READ_EXT;
+
+ cfis->lba_high_exp = (block >> 40) & 0xff;
+ cfis->lba_mid_exp = (block >> 32) & 0xff;
+ cfis->lba_low_exp = (block >> 24) & 0xff;
+ cfis->lba_high = (block >> 16) & 0xff;
+ cfis->lba_mid = (block >> 8) & 0xff;
+ cfis->lba_low = block & 0xff;
+ cfis->device = ATA_LBA;
+ cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
+ cfis->sector_count = blkcnt & 0xff;
+
+ fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer,
+ ATA_SECT_SIZE * blkcnt);
+ return blkcnt;
+}
+
+static u32 fsl_sata_rw_ncq_cmd(fsl_sata_t *sata, u32 start, u32 blkcnt,
+ u8 *buffer,
+ int is_write)
+{
+ struct sata_fis_h2d h2d, *cfis = &h2d;
+ int ncq_channel;
+ u64 block;
+
+ if (sata->lba48 != 1) {
+ printf("execute FPDMA command on non-LBA48 hard disk\n\r");
+ return -1;
+ }
+
+ block = (u64)start;
+
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis->pm_port_c = 0x80; /* is command */
+
+ cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
+ : ATA_CMD_FPDMA_READ;
+
+ cfis->lba_high_exp = (block >> 40) & 0xff;
+ cfis->lba_mid_exp = (block >> 32) & 0xff;
+ cfis->lba_low_exp = (block >> 24) & 0xff;
+ cfis->lba_high = (block >> 16) & 0xff;
+ cfis->lba_mid = (block >> 8) & 0xff;
+ cfis->lba_low = block & 0xff;
+
+ cfis->device = ATA_LBA;
+ cfis->features_exp = (blkcnt >> 8) & 0xff;
+ cfis->features = blkcnt & 0xff;
+
+ if (sata->queue_depth >= SATA_HC_MAX_CMD)
+ ncq_channel = SATA_HC_MAX_CMD - 1;
+ else
+ ncq_channel = sata->queue_depth - 1;
+
+ /* Use the latest queue */
+ fsl_sata_exec_cmd(sata, cfis, CMD_NCQ, ncq_channel, buffer,
+ ATA_SECT_SIZE * blkcnt);
+ return blkcnt;
+}
+
+static void fsl_sata_flush_cache_ext(fsl_sata_t *sata)
+{
+ struct sata_fis_h2d h2d, *cfis = &h2d;
+
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis->pm_port_c = 0x80; /* is command */
+ cfis->command = ATA_CMD_FLUSH_EXT;
+
+ fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
+}
+
+static u32 ata_low_level_rw_lba48(fsl_sata_t *sata, u32 blknr, lbaint_t blkcnt,
+ const void *buffer, int is_write)
+{
+ u32 start, blks;
+ u8 *addr;
+ int max_blks;
+
+ start = blknr;
+ blks = blkcnt;
+ addr = (u8 *)buffer;
+
+ max_blks = ATA_MAX_SECTORS_LBA48;
+ do {
+ if (blks > max_blks) {
+ if (sata->dma_flag != FLAGS_FPDMA)
+ fsl_sata_rw_cmd_ext(sata, start, max_blks,
+ addr, is_write);
+ else
+ fsl_sata_rw_ncq_cmd(sata, start, max_blks,
+ addr, is_write);
+ start += max_blks;
+ blks -= max_blks;
+ addr += ATA_SECT_SIZE * max_blks;
+ } else {
+ if (sata->dma_flag != FLAGS_FPDMA)
+ fsl_sata_rw_cmd_ext(sata, start, blks,
+ addr, is_write);
+ else
+ fsl_sata_rw_ncq_cmd(sata, start, blks,
+ addr, is_write);
+ start += blks;
+ blks = 0;
+ addr += ATA_SECT_SIZE * blks;
+ }
+ } while (blks != 0);
+
+ return blks;
+}
+
+static u32 ata_low_level_rw_lba28(fsl_sata_t *sata, u32 blknr, u32 blkcnt,
+ const void *buffer, int is_write)
+{
+ u32 start, blks;
+ u8 *addr;
+ int max_blks;
+
+ start = blknr;
+ blks = blkcnt;
+ addr = (u8 *)buffer;
+
+ max_blks = ATA_MAX_SECTORS;
+ do {
+ if (blks > max_blks) {
+ fsl_sata_rw_cmd(sata, start, max_blks, addr, is_write);
+ start += max_blks;
+ blks -= max_blks;
+ addr += ATA_SECT_SIZE * max_blks;
+ } else {
+ fsl_sata_rw_cmd(sata, start, blks, addr, is_write);
+ start += blks;
+ blks = 0;
+ addr += ATA_SECT_SIZE * blks;
+ }
+ } while (blks != 0);
+
+ return blks;
+}
+
+/*
+ * SATA interface between low level driver and command layer
+ */
+static int sata_read(fsl_sata_t *sata, ulong blknr, lbaint_t blkcnt,
+ void *buffer)
+{
+ u32 rc;
+
+ if (sata->lba48)
+ rc = ata_low_level_rw_lba48(sata, blknr, blkcnt, buffer,
+ READ_CMD);
+ else
+ rc = ata_low_level_rw_lba28(sata, blknr, blkcnt, buffer,
+ READ_CMD);
+ return rc;
+}
+
+static int sata_write(fsl_sata_t *sata, ulong blknr, lbaint_t blkcnt,
+ const void *buffer)
+{
+ u32 rc;
+
+ if (sata->lba48) {
+ rc = ata_low_level_rw_lba48(sata, blknr, blkcnt, buffer,
+ WRITE_CMD);
+ if (sata->wcache && sata->flush_ext)
+ fsl_sata_flush_cache_ext(sata);
+ } else {
+ rc = ata_low_level_rw_lba28(sata, blknr, blkcnt, buffer,
+ WRITE_CMD);
+ if (sata->wcache && sata->flush)
+ fsl_sata_flush_cache(sata);
+ }
+
+ return rc;
+}
+
+int sata_getinfo(fsl_sata_t *sata, u16 *id)
+{
+ /* if no detected link */
+ if (!sata->link)
+ return -EINVAL;
+
+#ifdef CONFIG_LBA48
+ /* Check if support LBA48 */
+ if (ata_id_has_lba48(id)) {
+ sata->lba48 = 1;
+ debug("Device support LBA48\n\r");
+ } else {
+ debug("Device supports LBA28\n\r");
+ }
+#endif
+
+ /* Get the NCQ queue depth from device */
+ sata->queue_depth = ata_id_queue_depth(id);
+
+ /* Get the xfer mode from device */
+ fsl_sata_xfer_mode(sata, id);
+
+ /* Get the write cache status from device */
+ fsl_sata_init_wcache(sata, id);
+
+ /* Set the xfer mode to highest speed */
+ fsl_sata_set_features(sata);
+
+ return 0;
+}
+
+static int fsl_scsi_exec(fsl_sata_t *sata, struct scsi_cmd *pccb,
+ bool is_write)
+{
+ int ret;
+ u32 temp;
+ u16 blocks = 0;
+ lbaint_t start = 0;
+ u8 *buffer = pccb->pdata;
+
+ /* Retrieve the base LBA number from the ccb structure. */
+ if (pccb->cmd[0] == SCSI_READ16) {
+ memcpy(&start, pccb->cmd + 2, 8);
+ start = be64_to_cpu(start);
+ } else {
+ memcpy(&temp, pccb->cmd + 2, 4);
+ start = be32_to_cpu(temp);
+ }
+
+ if (pccb->cmd[0] == SCSI_READ16)
+ blocks = (((u16)pccb->cmd[13]) << 8) | ((u16)pccb->cmd[14]);
+ else
+ blocks = (((u16)pccb->cmd[7]) << 8) | ((u16)pccb->cmd[8]);
+
+ debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
+ is_write ? "write" : "read", blocks, start);
+
+ if (is_write)
+ ret = sata_write(sata, start, blocks, buffer);
+ else
+ ret = sata_read(sata, start, blocks, buffer);
+
+ return ret;
+}
+
+static char *fsl_ata_id_strcpy(u16 *target, u16 *src, int len)
+{
+ int i;
+
+ for (i = 0; i < len / 2; i++)
+ target[i] = src[i];
+
+ return (char *)target;
+}
+
+static int fsl_ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
+ struct scsi_cmd *pccb,
+ fsl_sata_t *sata)
+{
+ u8 port;
+ u16 *idbuf;
+
+ ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
+
+ /* Clean ccb data buffer */
+ memset(pccb->pdata, 0, pccb->datalen);
+
+ if (pccb->datalen <= 35)
+ return 0;
+
+ /* Read id from sata */
+ port = pccb->target;
+
+ fsl_sata_identify(sata, (u16 *)tmpid);
+
+ if (!uc_priv->ataid[port]) {
+ uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
+ if (!uc_priv->ataid[port]) {
+ printf("%s: No memory for ataid[port]\n", __func__);
+ return -ENOMEM;
+ }
+ }
+
+ idbuf = uc_priv->ataid[port];
+
+ memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
+
+ memcpy(&pccb->pdata[8], "ATA ", 8);
+ fsl_ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
+ fsl_ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
+
+ sata_getinfo(sata, (u16 *)idbuf);
+#ifdef DEBUG
+ ata_dump_id(idbuf);
+#endif
+ return 0;
+}
+
+/*
+ * SCSI READ CAPACITY10 command operation.
+ */
+static int fsl_ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
+ struct scsi_cmd *pccb)
+{
+ u32 cap;
+ u64 cap64;
+ u32 block_size;
+
+ if (!uc_priv->ataid[pccb->target]) {
+ printf("scsi_ahci: SCSI READ CAPACITY10 command failure.");
+ printf("\tNo ATA info!\n");
+ printf("\tPlease run SCSI command INQUIRY first!\n");
+ return -EPERM;
+ }
+
+ cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
+ if (cap64 > 0x100000000ULL)
+ cap64 = 0xffffffff;
+
+ cap = cpu_to_be32(cap64);
+ memcpy(pccb->pdata, &cap, sizeof(cap));
+
+ block_size = cpu_to_be32((u32)512);
+ memcpy(&pccb->pdata[4], &block_size, 4);
+
+ return 0;
+}
+
+/*
+ * SCSI READ CAPACITY16 command operation.
+ */
+static int fsl_ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
+ struct scsi_cmd *pccb)
+{
+ u64 cap;
+ u64 block_size;
+
+ if (!uc_priv->ataid[pccb->target]) {
+ printf("scsi_ahci: SCSI READ CAPACITY16 command failure.");
+ printf("\tNo ATA info!\n");
+ printf("\tPlease run SCSI command INQUIRY first!\n");
+ return -EPERM;
+ }
+
+ cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
+ cap = cpu_to_be64(cap);
+ memcpy(pccb->pdata, &cap, sizeof(cap));
+
+ block_size = cpu_to_be64((u64)512);
+ memcpy(&pccb->pdata[8], &block_size, 8);
+
+ return 0;
+}
+
+/*
+ * SCSI TEST UNIT READY command operation.
+ */
+static int fsl_ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
+ struct scsi_cmd *pccb)
+{
+ return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
+}
+
+static int fsl_ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
+{
+ struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev->parent);
+ struct fsl_ahci_priv *priv = dev_get_priv(dev->parent);
+ fsl_sata_t *sata = priv->fsl_sata;
+ int ret;
+
+ switch (pccb->cmd[0]) {
+ case SCSI_READ16:
+ case SCSI_READ10:
+ ret = fsl_scsi_exec(sata, pccb, 0);
+ break;
+ case SCSI_WRITE10:
+ ret = fsl_scsi_exec(sata, pccb, 1);
+ break;
+ case SCSI_RD_CAPAC10:
+ ret = fsl_ata_scsiop_read_capacity10(uc_priv, pccb);
+ break;
+ case SCSI_RD_CAPAC16:
+ ret = fsl_ata_scsiop_read_capacity16(uc_priv, pccb);
+ break;
+ case SCSI_TST_U_RDY:
+ ret = fsl_ata_scsiop_test_unit_ready(uc_priv, pccb);
+ break;
+ case SCSI_INQUIRY:
+ ret = fsl_ata_scsiop_inquiry(uc_priv, pccb, sata);
+ break;
+ default:
+ printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
+ return -ENOTSUPP;
+ }
+
+ if (ret) {
+ debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int fsl_ahci_probe(struct udevice *dev)
+{
+ struct fsl_ahci_priv *priv = dev_get_priv(dev);
+ struct udevice *child_dev;
+ struct scsi_platdata *uc_plat;
+
+ device_find_first_child(dev, &child_dev);
+ if (!child_dev)
+ return -ENODEV;
+ uc_plat = dev_get_uclass_platdata(child_dev);
+ uc_plat->base = priv->base;
+ uc_plat->max_lun = 1;
+ uc_plat->max_id = 1;
+
+ return init_sata(priv);
+}
+
+struct scsi_ops fsl_scsi_ops = {
+ .exec = fsl_ahci_scsi_exec,
+};
+
+static const struct udevice_id fsl_ahci_ids[] = {
+ { .compatible = "fsl,pq-sata-v2" },
+ { }
+};
+
+U_BOOT_DRIVER(fsl_ahci_scsi) = {
+ .name = "fsl_ahci_scsi",
+ .id = UCLASS_SCSI,
+ .ops = &fsl_scsi_ops,
+};
+
+U_BOOT_DRIVER(fsl_ahci) = {
+ .name = "fsl_ahci",
+ .id = UCLASS_AHCI,
+ .of_match = fsl_ahci_ids,
+ .bind = fsl_ahci_bind,
+ .ofdata_to_platdata = fsl_ahci_ofdata_to_platdata,
+ .probe = fsl_ahci_probe,
+ .priv_auto_alloc_size = sizeof(struct fsl_ahci_priv),
+};
int wcache;
int flush;
int flush_ext;
+ u32 dma_flag;
} fsl_sata_t;
#define READ_CMD 0
return 0;
}
-int ofnode_read_u32_default(ofnode node, const char *propname, u32 def)
+u32 ofnode_read_u32_default(ofnode node, const char *propname, u32 def)
{
assert(ofnode_valid(node));
ofnode_read_u32(node, propname, &def);
return -EINVAL;
}
-fdt_addr_t ofnode_get_addr_index(ofnode node, int index)
+fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, fdt_size_t *size)
{
int na, ns;
uint flags;
prop_val = of_get_address(ofnode_to_np(node), index,
- NULL, &flags);
+ (u64 *)size, &flags);
if (!prop_val)
return FDT_ADDR_T_NONE;
ns = ofnode_read_simple_size_cells(ofnode_get_parent(node));
return fdtdec_get_addr_size_fixed(gd->fdt_blob,
ofnode_to_offset(node), "reg",
- index, na, ns, NULL, true);
+ index, na, ns, size, true);
}
return FDT_ADDR_T_NONE;
}
+fdt_addr_t ofnode_get_addr_index(ofnode node, int index)
+{
+ fdt_size_t size;
+
+ return ofnode_get_addr_size_index(node, index, &size);
+}
+
fdt_addr_t ofnode_get_addr(ofnode node)
{
return ofnode_get_addr_index(node, 0);
{
int ret;
- ret = dm_scan_fdt(gd->fdt_blob, pre_reloc_only);
+ ret = dm_scan_fdt(blob, pre_reloc_only);
if (ret) {
debug("dm_scan_fdt() failed: %d\n", ret);
return ret;
set of generic read, write and ioctl methods may be used to
access the device.
+config SPL_MISC
+ bool "Enable Driver Model for Misc drivers in SPL"
+ depends on SPL_DM
+ help
+ Enable driver model for miscellaneous devices. This class is
+ used only for those do not fit other more general classes. A
+ set of generic read, write and ioctl methods may be used to
+ access the device.
+
+config TPL_MISC
+ bool "Enable Driver Model for Misc drivers in TPL"
+ depends on TPL_DM
+ help
+ Enable driver model for miscellaneous devices. This class is
+ used only for those do not fit other more general classes. A
+ set of generic read, write and ioctl methods may be used to
+ access the device.
+
config ALTERA_SYSID
bool "Altera Sysid support"
depends on MISC
control access to the battery and main PMIC depending on the
device. You can use the 'crosec' command to access it.
+config SPL_CROS_EC
+ bool "Enable Chrome OS EC in SPL"
+ help
+ Enable access to the Chrome OS EC in SPL. This is a separate
+ microcontroller typically available on a SPI bus on Chromebooks. It
+ provides access to the keyboard, some internal storage and may
+ control access to the battery and main PMIC depending on the
+ device. You can use the 'crosec' command to access it.
+
+config TPL_CROS_EC
+ bool "Enable Chrome OS EC in TPL"
+ help
+ Enable access to the Chrome OS EC in TPL. This is a separate
+ microcontroller typically available on a SPI bus on Chromebooks. It
+ provides access to the keyboard, some internal storage and may
+ control access to the battery and main PMIC depending on the
+ device. You can use the 'crosec' command to access it.
+
config CROS_EC_I2C
bool "Enable Chrome OS EC I2C driver"
depends on CROS_EC
through a legacy port interface, so on x86 machines the main
function of the EC is power and thermal management.
+config SPL_CROS_EC_LPC
+ bool "Enable Chrome OS EC LPC driver in SPL"
+ depends on CROS_EC
+ help
+ Enable I2C access to the Chrome OS EC. This is used on x86
+ Chromebooks such as link and falco. The keyboard is provided
+ through a legacy port interface, so on x86 machines the main
+ function of the EC is power and thermal management.
+
+config TPL_CROS_EC_LPC
+ bool "Enable Chrome OS EC LPC driver in TPL"
+ depends on CROS_EC
+ help
+ Enable I2C access to the Chrome OS EC. This is used on x86
+ Chromebooks such as link and falco. The keyboard is provided
+ through a legacy port interface, so on x86 machines the main
+ function of the EC is power and thermal management.
+
config CROS_EC_SANDBOX
bool "Enable Chrome OS EC sandbox driver"
depends on CROS_EC && SANDBOX
EC flash read/write/erase support and a few other things. It is
enough to perform a Chrome OS verified boot on sandbox.
+config SPL_CROS_EC_SANDBOX
+ bool "Enable Chrome OS EC sandbox driver in SPL"
+ depends on SPL_CROS_EC && SANDBOX
+ help
+ Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
+ keyboard (use the -l flag to enable the LCD), verified boot context,
+ EC flash read/write/erase support and a few other things. It is
+ enough to perform a Chrome OS verified boot on sandbox.
+
+config TPL_CROS_EC_SANDBOX
+ bool "Enable Chrome OS EC sandbox driver in TPL"
+ depends on TPL_CROS_EC && SANDBOX
+ help
+ Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
+ keyboard (use the -l flag to enable the LCD), verified boot context,
+ EC flash read/write/erase support and a few other things. It is
+ enough to perform a Chrome OS verified boot on sandbox.
+
config CROS_EC_SPI
bool "Enable Chrome OS EC SPI driver"
depends on CROS_EC
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-$(CONFIG_MISC) += misc-uclass.o
+
+obj-$(CONFIG_$(SPL_TPL_)CROS_EC) += cros_ec.o
+obj-$(CONFIG_$(SPL_TPL_)CROS_EC_SANDBOX) += cros_ec_sandbox.o
+obj-$(CONFIG_$(SPL_TPL_)CROS_EC_LPC) += cros_ec_lpc.o
+
ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_CROS_EC) += cros_ec.o
-obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o
obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
-obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o
obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
endif
#endif
#if CONFIG_IS_ENABLED(DM_MMC)
+#ifndef CONFIG_PPC
#include <asm/arch/clock.h>
+#endif
__weak void init_clk_usdhc(u32 index)
{
}
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
-
+#ifdef CONFIG_PPC
+ priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
+#else
priv->esdhc_regs = (struct fsl_esdhc *)addr;
+#endif
priv->dev = dev;
priv->mode = -1;
if (data) {
priv->sdhc_clk = clk_get_rate(&priv->per_clk);
} else {
+#ifndef CONFIG_PPC
priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
+#else
+ priv->sdhc_clk = gd->arch.sdhc_clk;
+#endif
if (priv->sdhc_clk <= 0) {
dev_err(dev, "Unable to get clk for %s\n", dev->name);
return -EINVAL;
Choose this option to add support for UART driver on the Marvell
Armada 3700 SoC. The base address is configured via DT.
+config MCFUART
+ bool "Freescale ColdFire UART support"
+ help
+ Choose this option to add support for UART driver on the ColdFire
+ SoC's family. The serial communication channel provides a full-duplex
+ asynchronous/synchronous receiver and transmitter deriving an
+ operating frequency from the internal bus clock or an external clock.
+
config MXC_UART
bool "IMX serial port support"
depends on MX5 || MX6
*
* Modified to add device model (DM) support
* (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
+ *
+ * Modified to add DM and fdt support, removed non DM code
+ * (C) Copyright 2018 Angelo Dureghello <angelo@sysam.it>
*/
/*
writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
}
-#ifndef CONFIG_DM_SERIAL
-
-static int mcf_serial_init(void)
-{
- uart_t *uart_base;
- int port_idx;
-
- uart_base = (uart_t *)CONFIG_SYS_UART_BASE;
- port_idx = CONFIG_SYS_UART_PORT;
-
- return mcf_serial_init_common(uart_base, port_idx, gd->baudrate);
-}
-
-static void mcf_serial_putc(const char c)
-{
- uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
-
- if (c == '\n')
- serial_putc('\r');
-
- /* Wait for last character to go. */
- while (!(readb(&uart->usr) & UART_USR_TXRDY))
- ;
-
- writeb(c, &uart->utb);
-}
-
-static int mcf_serial_getc(void)
-{
- uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
-
- /* Wait for a character to arrive. */
- while (!(readb(&uart->usr) & UART_USR_RXRDY))
- ;
-
- return readb(&uart->urb);
-}
-
-static void mcf_serial_setbrg(void)
-{
- uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
-
- mcf_serial_setbrg_common(uart, gd->baudrate);
-}
-
-static int mcf_serial_tstc(void)
-{
- uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
-
- return readb(&uart->usr) & UART_USR_RXRDY;
-}
-
-static struct serial_device mcf_serial_drv = {
- .name = "mcf_serial",
- .start = mcf_serial_init,
- .stop = NULL,
- .setbrg = mcf_serial_setbrg,
- .putc = mcf_serial_putc,
- .puts = default_serial_puts,
- .getc = mcf_serial_getc,
- .tstc = mcf_serial_tstc,
-};
-
-void mcf_serial_initialize(void)
-{
- serial_register(&mcf_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &mcf_serial_drv;
-}
-
-#endif
-
-#ifdef CONFIG_DM_SERIAL
-
static int coldfire_serial_probe(struct udevice *dev)
{
struct coldfire_serial_platdata *plat = dev->platdata;
return 0;
}
+static int coldfire_ofdata_to_platdata(struct udevice *dev)
+{
+ struct coldfire_serial_platdata *plat = dev_get_platdata(dev);
+ fdt_addr_t addr_base;
+
+ addr_base = devfdt_get_addr(dev);
+ if (addr_base == FDT_ADDR_T_NONE)
+ return -ENODEV;
+
+ plat->base = (uint32_t)addr_base;
+
+ plat->port = dev->seq;
+ plat->baudrate = gd->baudrate;
+
+ return 0;
+}
+
static const struct dm_serial_ops coldfire_serial_ops = {
.putc = coldfire_serial_putc,
.pending = coldfire_serial_pending,
.setbrg = coldfire_serial_setbrg,
};
+static const struct udevice_id coldfire_serial_ids[] = {
+ { .compatible = "fsl,mcf-uart" },
+ { }
+};
+
U_BOOT_DRIVER(serial_coldfire) = {
.name = "serial_coldfire",
.id = UCLASS_SERIAL,
+ .of_match = coldfire_serial_ids,
+ .ofdata_to_platdata = coldfire_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct coldfire_serial_platdata),
.probe = coldfire_serial_probe,
.ops = &coldfire_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
};
-#endif
used to access the SPI NOR flash on platforms embedding this
Cadence IP core.
+config CF_SPI
+ bool "ColdFire SPI driver"
+ help
+ Enable the ColdFire SPI driver. This driver can be used on
+ some m68k SoCs.
+
config DESIGNWARE_SPI
bool "Designware SPI driver"
help
*
* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * Support for DM and DT, non-DM code removed.
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ *
+ * TODO: fsl_dspi.c should work as a driver for the DSPI module.
*/
#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/spi_coldfire.h>
#include <spi.h>
#include <malloc.h>
-#include <asm/immap.h>
+#include <asm/coldfire/dspi.h>
+#include <asm/io.h>
-struct cf_spi_slave {
- struct spi_slave slave;
+struct coldfire_spi_priv {
+ struct dspi *regs;
uint baudrate;
+ int mode;
int charbit;
};
-extern void cfspi_port_conf(void);
-extern int cfspi_claim_bus(uint bus, uint cs);
-extern void cfspi_release_bus(uint bus, uint cs);
-
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SPI_IDLE_VAL
#endif
#endif
-#if defined(CONFIG_CF_DSPI)
-/* DSPI specific mode */
-#define SPI_MODE_MOD 0x00200000
-#define SPI_DBLRATE 0x00100000
-
-static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
+/*
+ * DSPI specific mode
+ *
+ * bit 31 - 28: Transfer size 3 to 16 bits
+ * 27 - 26: PCS to SCK delay prescaler
+ * 25 - 24: After SCK delay prescaler
+ * 23 - 22: Delay after transfer prescaler
+ * 21 : Allow overwrite for bit 31-22 and bit 20-8
+ * 20 : Double baud rate
+ * 19 - 16: PCS to SCK delay scaler
+ * 15 - 12: After SCK delay scaler
+ * 11 - 8: Delay after transfer scaler
+ * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
+ */
+#define SPI_MODE_MOD 0x00200000
+#define SPI_MODE_DBLRATE 0x00100000
+
+#define SPI_MODE_XFER_SZ_MASK 0xf0000000
+#define SPI_MODE_DLY_PRE_MASK 0x0fc00000
+#define SPI_MODE_DLY_SCA_MASK 0x000fff00
+
+#define MCF_FRM_SZ_16BIT DSPI_CTAR_TRSZ(0xf)
+#define MCF_DSPI_SPEED_BESTMATCH 0x7FFFFFFF
+#define MCF_DSPI_MAX_CTAR_REGS 8
+
+/* Default values */
+#define MCF_DSPI_DEFAULT_SCK_FREQ 10000000
+#define MCF_DSPI_DEFAULT_MAX_CS 4
+#define MCF_DSPI_DEFAULT_MODE 0
+
+#define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \
+ DSPI_CTAR_PCSSCK_1CLK | \
+ DSPI_CTAR_PASC(0) | \
+ DSPI_CTAR_PDT(0) | \
+ DSPI_CTAR_CSSCK(0) | \
+ DSPI_CTAR_ASC(0) | \
+ DSPI_CTAR_DT(1) | \
+ DSPI_CTAR_BR(6))
+
+#define MCF_CTAR_MODE_MASK (MCF_FRM_SZ_16BIT | \
+ DSPI_CTAR_PCSSCK(3) | \
+ DSPI_CTAR_PASC_7CLK | \
+ DSPI_CTAR_PDT(3) | \
+ DSPI_CTAR_CSSCK(0x0f) | \
+ DSPI_CTAR_ASC(0x0f) | \
+ DSPI_CTAR_DT(0x0f))
+
+#define setup_ctrl(ctrl, cs) ((ctrl & 0xFF000000) | ((1 << cs) << 16))
+
+static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
+ u32 ctrl, u16 data)
{
- return container_of(slave, struct cf_spi_slave, slave);
+ /*
+ * Need to check fifo level here
+ */
+ while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
+ ;
+
+ writel(ctrl | data, &cfspi->regs->tfr);
}
-static void cfspi_init(void)
+static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
{
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- cfspi_port_conf(); /* port configuration */
-
- dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
- DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
- DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
- DSPI_MCR_CRXF | DSPI_MCR_CTXF;
+ while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
+ ;
- /* Default setting in platform configuration */
-#ifdef CONFIG_SYS_DSPI_CTAR0
- dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR1
- dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR2
- dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR3
- dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR4
- dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR5
- dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR6
- dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR7
- dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7;
-#endif
+ return readw(&cfspi->regs->rfr);
}
-static void cfspi_tx(u32 ctrl, u16 data)
+static int coldfire_spi_claim_bus(struct udevice *dev)
{
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+ struct udevice *bus = dev->parent;
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+ struct dspi *dspi = cfspi->regs;
+ struct dm_spi_slave_platdata *slave_plat =
+ dev_get_parent_platdata(dev);
- while ((dspi->sr & 0x0000F000) >= 4) ;
+ if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
+ return -1;
- dspi->tfr = (ctrl | data);
+ /* Clear FIFO and resume transfer */
+ clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+
+ dspi_chip_select(slave_plat->cs);
+
+ return 0;
}
-static u16 cfspi_rx(void)
+static int coldfire_spi_release_bus(struct udevice *dev)
{
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+ struct udevice *bus = dev->parent;
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+ struct dspi *dspi = cfspi->regs;
+ struct dm_spi_slave_platdata *slave_plat =
+ dev_get_parent_platdata(dev);
- while ((dspi->sr & 0x000000F0) == 0) ;
+ /* Clear FIFO */
+ clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
- return (dspi->rfr & 0xFFFF);
+ dspi_chip_unselect(slave_plat->cs);
+
+ return 0;
}
-static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
- void *din, ulong flags)
+static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din,
+ unsigned long flags)
{
- struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
+ struct udevice *bus = dev_get_parent(dev);
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
u8 *spi_rd = NULL, *spi_wr = NULL;
- static u32 ctrl = 0;
+ static u32 ctrl;
uint len = bitlen >> 3;
- if (cfslave->charbit == 16) {
+ if (cfspi->charbit == 16) {
bitlen >>= 1;
- spi_wr16 = (u16 *) dout;
- spi_rd16 = (u16 *) din;
+ spi_wr16 = (u16 *)dout;
+ spi_rd16 = (u16 *)din;
} else {
- spi_wr = (u8 *) dout;
- spi_rd = (u8 *) din;
+ spi_wr = (u8 *)dout;
+ spi_rd = (u8 *)din;
}
if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
ctrl |= DSPI_TFR_CONT;
- ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16);
+ ctrl = setup_ctrl(ctrl, slave_plat->cs);
if (len > 1) {
int tmp_len = len - 1;
+
while (tmp_len--) {
- if (dout != NULL) {
- if (cfslave->charbit == 16)
- cfspi_tx(ctrl, *spi_wr16++);
+ if (dout) {
+ if (cfspi->charbit == 16)
+ cfspi_tx(cfspi, ctrl, *spi_wr16++);
else
- cfspi_tx(ctrl, *spi_wr++);
- cfspi_rx();
+ cfspi_tx(cfspi, ctrl, *spi_wr++);
+ cfspi_rx(cfspi);
}
- if (din != NULL) {
- cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
- if (cfslave->charbit == 16)
- *spi_rd16++ = cfspi_rx();
+ if (din) {
+ cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
+ if (cfspi->charbit == 16)
+ *spi_rd16++ = cfspi_rx(cfspi);
else
- *spi_rd++ = cfspi_rx();
+ *spi_rd++ = cfspi_rx(cfspi);
}
}
len = 1; /* remaining byte */
}
- if ((flags & SPI_XFER_END) == SPI_XFER_END)
+ if (flags & SPI_XFER_END)
ctrl &= ~DSPI_TFR_CONT;
if (len) {
- if (dout != NULL) {
- if (cfslave->charbit == 16)
- cfspi_tx(ctrl, *spi_wr16);
+ if (dout) {
+ if (cfspi->charbit == 16)
+ cfspi_tx(cfspi, ctrl, *spi_wr16);
else
- cfspi_tx(ctrl, *spi_wr);
- cfspi_rx();
+ cfspi_tx(cfspi, ctrl, *spi_wr);
+ cfspi_rx(cfspi);
}
- if (din != NULL) {
- cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
- if (cfslave->charbit == 16)
- *spi_rd16 = cfspi_rx();
+ if (din) {
+ cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
+ if (cfspi->charbit == 16)
+ *spi_rd16 = cfspi_rx(cfspi);
else
- *spi_rd = cfspi_rx();
+ *spi_rd = cfspi_rx(cfspi);
}
} else {
/* dummy read */
- cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
- cfspi_rx();
+ cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
+ cfspi_rx(cfspi);
}
return 0;
}
-static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
- uint mode)
+static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
{
- /*
- * bit definition for mode:
- * bit 31 - 28: Transfer size 3 to 16 bits
- * 27 - 26: PCS to SCK delay prescaler
- * 25 - 24: After SCK delay prescaler
- * 23 - 22: Delay after transfer prescaler
- * 21 : Allow overwrite for bit 31-22 and bit 20-8
- * 20 : Double baud rate
- * 19 - 16: PCS to SCK delay scaler
- * 15 - 12: After SCK delay scaler
- * 11 - 8: Delay after transfer scaler
- * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
- */
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+ struct dspi *dspi = cfspi->regs;
int prescaler[] = { 2, 3, 5, 7 };
int scaler[] = {
2, 4, 6, 8,
4096, 8192, 16384, 32768
};
int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
- int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
- u32 bus_setup = 0;
+ int best_i, best_j, bestmatch = MCF_DSPI_SPEED_BESTMATCH, baud_speed;
+ u32 bus_setup;
+
+ cfspi->baudrate = max_hz;
+
+ /* Read current setup */
+ bus_setup = readl(&dspi->ctar[bus->seq]);
tmp = (prescaler[3] * scaler[15]);
/* Maximum and minimum baudrate it can handle */
- if ((cfslave->baudrate > (gd->bus_clk >> 1)) ||
- (cfslave->baudrate < (gd->bus_clk / tmp))) {
+ if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
+ (cfspi->baudrate < (gd->bus_clk / tmp))) {
printf("Exceed baudrate limitation: Max %d - Min %d\n",
(int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
- return NULL;
+ return -1;
}
/* Activate Double Baud when it exceed 1/4 the bus clk */
- if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) ||
- (cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
+ if ((bus_setup & DSPI_CTAR_DBR) ||
+ (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
bus_setup |= DSPI_CTAR_DBR;
dbr = 1;
}
- if (mode & SPI_CPOL)
- bus_setup |= DSPI_CTAR_CPOL;
- if (mode & SPI_CPHA)
- bus_setup |= DSPI_CTAR_CPHA;
- if (mode & SPI_LSB_FIRST)
- bus_setup |= DSPI_CTAR_LSBFE;
-
/* Overwrite default value set in platform configuration file */
- if (mode & SPI_MODE_MOD) {
-
- if ((mode & 0xF0000000) == 0)
- bus_setup |=
- dspi->ctar[cfslave->slave.bus] & 0x78000000;
- else
- bus_setup |= ((mode & 0xF0000000) >> 1);
-
+ if (cfspi->mode & SPI_MODE_MOD) {
/*
* Check to see if it is enabled by default in platform
* config, or manual setting passed by mode parameter
*/
- if (mode & SPI_DBLRATE) {
+ if (cfspi->mode & SPI_MODE_DBLRATE) {
bus_setup |= DSPI_CTAR_DBR;
dbr = 1;
}
- bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */
- bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */
- } else
- bus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0);
-
- cfslave->charbit =
- ((dspi->ctar[cfslave->slave.bus] & 0x78000000) ==
- 0x78000000) ? 16 : 8;
+ }
pbrcnt = sizeof(prescaler) / sizeof(int);
brcnt = sizeof(scaler) / sizeof(int);
for (j = 0; j < brcnt; j++) {
tmp = (baud_speed / scaler[j]) * (1 + dbr);
- if (tmp > cfslave->baudrate)
- diff = tmp - cfslave->baudrate;
+ if (tmp > cfspi->baudrate)
+ diff = tmp - cfspi->baudrate;
else
- diff = cfslave->baudrate - tmp;
+ diff = cfspi->baudrate - tmp;
if (diff < bestmatch) {
bestmatch = diff;
}
}
}
+
+ bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
- dspi->ctar[cfslave->slave.bus] = bus_setup;
+ writel(bus_setup, &dspi->ctar[bus->seq]);
- return &cfslave->slave;
+ return 0;
}
-#endif /* CONFIG_CF_DSPI */
-#ifdef CONFIG_CMD_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
{
- if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
- return 1;
- else
- return 0;
-}
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+ struct dspi *dspi = cfspi->regs;
+ u32 bus_setup = 0;
-void spi_init(void)
-{
- cfspi_init();
-}
+ cfspi->mode = mode;
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct cf_spi_slave *cfslave;
+ if (cfspi->mode & SPI_CPOL)
+ bus_setup |= DSPI_CTAR_CPOL;
+ if (cfspi->mode & SPI_CPHA)
+ bus_setup |= DSPI_CTAR_CPHA;
+ if (cfspi->mode & SPI_LSB_FIRST)
+ bus_setup |= DSPI_CTAR_LSBFE;
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
+ /* Overwrite default value set in platform configuration file */
+ if (cfspi->mode & SPI_MODE_MOD) {
+ if ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) == 0)
+ bus_setup |=
+ readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT;
+ else
+ bus_setup |=
+ ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) >> 1);
- cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs);
- if (!cfslave)
- return NULL;
+ /* PSCSCK, PASC, PDT */
+ bus_setup |= (cfspi->mode & SPI_MODE_DLY_PRE_MASK) >> 4;
+ /* CSSCK, ASC, DT */
+ bus_setup |= (cfspi->mode & SPI_MODE_DLY_SCA_MASK) >> 4;
+ } else {
+ bus_setup |=
+ (readl(&dspi->ctar[bus->seq]) & MCF_CTAR_MODE_MASK);
+ }
+
+ cfspi->charbit =
+ ((readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT) ==
+ MCF_FRM_SZ_16BIT) ? 16 : 8;
- cfslave->baudrate = max_hz;
+ setbits_be32(&dspi->ctar[bus->seq], bus_setup);
- /* specific setup */
- return cfspi_setup_slave(cfslave, mode);
+ return 0;
}
-void spi_free_slave(struct spi_slave *slave)
+static int coldfire_spi_probe(struct udevice *bus)
{
- struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
+ struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+ struct dspi *dspi = cfspi->regs;
+ int i;
- free(cfslave);
-}
+ cfspi->regs = (struct dspi *)plat->regs_addr;
-int spi_claim_bus(struct spi_slave *slave)
-{
- return cfspi_claim_bus(slave->bus, slave->cs);
+ cfspi->baudrate = plat->speed_hz;
+ cfspi->mode = plat->mode;
+
+ for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
+ unsigned int ctar = 0;
+
+ if (plat->ctar[i][0] == 0)
+ break;
+
+ ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |
+ DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |
+ DSPI_CTAR_PASC(plat->ctar[i][2]) |
+ DSPI_CTAR_PDT(plat->ctar[i][3]) |
+ DSPI_CTAR_CSSCK(plat->ctar[i][4]) |
+ DSPI_CTAR_ASC(plat->ctar[i][5]) |
+ DSPI_CTAR_DT(plat->ctar[i][6]) |
+ DSPI_CTAR_BR(plat->ctar[i][7]);
+
+ writel(ctar, &cfspi->regs->ctar[i]);
+ }
+
+ /* Default CTARs */
+ for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
+ writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);
+
+ dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
+ DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
+ DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
+ DSPI_MCR_CRXF | DSPI_MCR_CTXF;
+
+ return 0;
}
-void spi_release_bus(struct spi_slave *slave)
+void spi_init(void)
{
- cfspi_release_bus(slave->bus, slave->cs);
}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus)
{
- return cfspi_xfer(slave, bitlen, dout, din, flags);
+ fdt_addr_t addr;
+ struct coldfire_spi_platdata *plat = bus->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(bus);
+ int *ctar, len;
+
+ addr = devfdt_get_addr(bus);
+ if (addr == FDT_ADDR_T_NONE)
+ return -ENOMEM;
+
+ plat->regs_addr = addr;
+
+ plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
+ MCF_DSPI_DEFAULT_MAX_CS);
+
+ plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
+ MCF_DSPI_DEFAULT_SCK_FREQ);
+
+ plat->mode = fdtdec_get_int(blob, node, "spi-mode",
+ MCF_DSPI_DEFAULT_MODE);
+
+ memset(plat->ctar, 0, sizeof(plat->ctar));
+
+ ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);
+
+ if (ctar && len) {
+ int i, q, ctar_regs;
+
+ ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;
+
+ if (ctar_regs > MAX_CTAR_REGS)
+ ctar_regs = MAX_CTAR_REGS;
+
+ for (i = 0; i < ctar_regs; i++) {
+ for (q = 0; q < MAX_CTAR_FIELDS; q++)
+ plat->ctar[i][q] = *ctar++;
+ }
+ }
+
+ debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
+ (void *)plat->regs_addr,
+ plat->speed_hz, plat->num_cs, plat->mode);
+
+ return 0;
}
-#endif /* CONFIG_CMD_SPI */
+
+static const struct udevice_id coldfire_spi_ids[] = {
+ { .compatible = "fsl,mcf-dspi" },
+ { }
+};
+#endif
+
+static const struct dm_spi_ops coldfire_spi_ops = {
+ .claim_bus = coldfire_spi_claim_bus,
+ .release_bus = coldfire_spi_release_bus,
+ .xfer = coldfire_spi_xfer,
+ .set_speed = coldfire_spi_set_speed,
+ .set_mode = coldfire_spi_set_mode,
+};
+
+U_BOOT_DRIVER(coldfire_spi) = {
+ .name = "spi_coldfire",
+ .id = UCLASS_SPI,
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .of_match = coldfire_spi_ids,
+ .ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),
+#endif
+ .probe = coldfire_spi_probe,
+ .ops = &coldfire_spi_ops,
+ .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),
+};
struct usb_ehci *ehci = NULL;
struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv,
ehci);
-
+#ifdef CONFIG_PPC
+ ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
+#else
ehci = (struct usb_ehci *)priv->hcd_base;
+#endif
+
if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0)
return -ENXIO;
debug("Can't get the EHCI register base address\n");
return -ENXIO;
}
+#ifdef CONFIG_PPC
+ ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
+#else
ehci = (struct usb_ehci *)priv->hcd_base;
+#endif
hccr = (struct ehci_hccr *)(&ehci->caplength);
hcor = (struct ehci_hcor *)
((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
/* DSPI and Serial Flash */
#define CONFIG_CF_DSPI
#define CONFIG_SYS_SBFHDR_SIZE 0x7
-#ifdef CONFIG_CMD_SPI
-# define CONFIG_SYS_DSPI_CS2
-
-# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
- DSPI_CTAR_PCSSCK_1CLK | \
- DSPI_CTAR_PASC(0) | \
- DSPI_CTAR_PDT(0) | \
- DSPI_CTAR_CSSCK(0) | \
- DSPI_CTAR_ASC(0) | \
- DSPI_CTAR_DT(1))
-#endif
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK
#define CONFIG_CF_DSPI
#define CONFIG_SERIAL_FLASH
#define CONFIG_SYS_SBFHDR_SIZE 0x7
-#ifdef CONFIG_CMD_SPI
-
-# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
- DSPI_CTAR_PCSSCK_1CLK | \
- DSPI_CTAR_PASC(0) | \
- DSPI_CTAR_PDT(0) | \
- DSPI_CTAR_CSSCK(0) | \
- DSPI_CTAR_ASC(0) | \
- DSPI_CTAR_DT(1))
-# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
-# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
-#endif
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK
#define CONFIG_CF_DSPI
#define CONFIG_SERIAL_FLASH
#define CONFIG_SYS_SBFHDR_SIZE 0x7
-#ifdef CONFIG_CMD_SPI
-
-# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
- DSPI_CTAR_PCSSCK_1CLK | \
- DSPI_CTAR_PASC(0) | \
- DSPI_CTAR_PDT(0) | \
- DSPI_CTAR_CSSCK(0) | \
- DSPI_CTAR_ASC(0) | \
- DSPI_CTAR_DT(1))
-# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
-# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
-#endif
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK
/* DSPI and Serial Flash */
#define CONFIG_CF_DSPI
#define CONFIG_SYS_SBFHDR_SIZE 0x13
-#ifdef CONFIG_CMD_SPI
-
-# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
- DSPI_CTAR_PCSSCK_1CLK | \
- DSPI_CTAR_PASC(0) | \
- DSPI_CTAR_PDT(0) | \
- DSPI_CTAR_CSSCK(0) | \
- DSPI_CTAR_ASC(0) | \
- DSPI_CTAR_DT(1))
-#endif
/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_SYS_SBFHDR_SIZE 0x7
-#define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
- DSPI_CTAR_PCSSCK_1CLK | \
- DSPI_CTAR_PASC(0) | \
- DSPI_CTAR_PDT(0) | \
- DSPI_CTAR_CSSCK(0) | \
- DSPI_CTAR_ASC(0) | \
- DSPI_CTAR_DT(1) | \
- DSPI_CTAR_BR(6))
-#define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
-#define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
-
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK
* @def: default value to return if the property has no value
* @return property value, or @def if not found
*/
-int ofnode_read_u32_default(ofnode ref, const char *propname, u32 def);
+u32 ofnode_read_u32_default(ofnode ref, const char *propname, u32 def);
/**
* ofnode_read_s32_default() - Read a 32-bit integer from a property
int ofnode_read_size(ofnode node, const char *propname);
/**
+ * ofnode_get_addr_size_index() - get an address/size from a node
+ * based on index
+ *
+ * This reads the register address/size from a node based on index
+ *
+ * @node: node to read from
+ * @index: Index of address to read (0 for first)
+ * @size: Pointer to size of the address
+ * @return address, or FDT_ADDR_T_NONE if not present or invalid
+ */
+phys_addr_t ofnode_get_addr_size_index(ofnode node, int index,
+ fdt_size_t *size);
+
+/**
* ofnode_get_addr_index() - get an address from a node
*
* This reads the register address from a node
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+#ifndef __spi_coldfire_h
+#define __spi_coldfire_h
+
+#define MAX_CTAR_REGS 8
+#define MAX_CTAR_FIELDS 8
+
+/*
+ * struct coldfire_spi_platdata - information about a coldfire spi module
+ *
+ * @regs_addr: base address for module registers
+ * @speed_hz: default SCK frequency
+ * @mode: default SPI mode
+ * @num_cs: number of DSPI chipselect signals
+ */
+struct coldfire_spi_platdata {
+ fdt_addr_t regs_addr;
+ uint speed_hz;
+ uint mode;
+ uint num_cs;
+ uint ctar[MAX_CTAR_REGS][MAX_CTAR_FIELDS];
+};
+
+#endif /* __spi_coldfire_h */
+
typedef phys_addr_t fdt_addr_t;
typedef phys_size_t fdt_size_t;
-static inline fdt32_t fdt_addr_unpack(fdt_addr_t addr, fdt32_t *upper)
-{
- if (upper)
-#ifdef CONFIG_PHYS_64BIT
- *upper = addr >> 32;
-#else
- *upper = 0;
-#endif
-
- return addr;
-}
-
-static inline fdt32_t fdt_size_unpack(fdt_size_t size, fdt32_t *upper)
-{
- if (upper)
-#ifdef CONFIG_PHYS_64BIT
- *upper = size >> 32;
-#else
- *upper = 0;
-#endif
-
- return size;
-}
-
#ifdef CONFIG_PHYS_64BIT
#define FDT_ADDR_T_NONE (-1U)
#define fdt_addr_to_cpu(reg) be64_to_cpu(reg)
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Dummy file to allow libraries linked with U-Boot to include stdint.h without
+ * getting the system version.
+ *
+ * U-Boot uses linux types (linux/types.h) so does not make use of stdint.h
+ */
fdt32_t cells[4] = {}, *ptr = cells;
uint32_t upper, lower, phandle;
int parent, node, na, ns, err;
+ fdt_size_t size;
char name[64];
/* create an empty /reserved-memory node if one doesn't exist */
* Unpack the start address and generate the name of the new node
* base on the basename and the unit-address.
*/
- lower = fdt_addr_unpack(carveout->start, &upper);
+ upper = upper_32_bits(carveout->start);
+ lower = lower_32_bits(carveout->start);
if (na > 1 && upper > 0)
snprintf(name, sizeof(name), "%s@%x,%x", basename, upper,
*ptr++ = cpu_to_fdt32(lower);
/* store one or two size cells */
- lower = fdt_size_unpack(carveout->end - carveout->start + 1, &upper);
+ size = carveout->end - carveout->start + 1;
+ upper = upper_32_bits(size);
+ lower = lower_32_bits(size);
if (ns > 1)
*ptr++ = cpu_to_fdt32(upper);
};
fdt32_t cells[4], *ptr = cells;
uint32_t upper, lower;
+ fdt_size_t size;
char name[32];
int offset;
/* store one or two address cells */
- lower = fdt_addr_unpack(carveout.start, &upper);
+ upper = upper_32_bits(carveout.start);
+ lower = lower_32_bits(carveout.start);
if (na > 1 && upper > 0)
snprintf(name, sizeof(name), "%s@%x,%x", basename, upper,
*ptr++ = cpu_to_fdt32(lower);
/* store one or two size cells */
- lower = fdt_size_unpack(carveout.end - carveout.start + 1, &upper);
+ size = carveout.end - carveout.start + 1;
+ upper = upper_32_bits(size);
+ lower = lower_32_bits(size);
if (ns > 1)
*ptr++ = cpu_to_fdt32(upper);
environment = {}
if os.path.exists(done_file):
with open(done_file, 'r') as fd:
- return_code = int(fd.readline())
+ try:
+ return_code = int(fd.readline())
+ except ValueError:
+ # The file may be empty due to running out of disk space.
+ # Try a rebuild
+ return_code = 1
err_lines = []
err_file = self.GetErrFile(commit_upto, target)
if os.path.exists(err_file):
projects / platform / kernel / u-boot.git / commitdiff