--- /dev/null
+*.orig
+*.a
+*.o
+*.depend
+System.map
+/u-boot
+/u-boot.map
+/u-boot.bin
+/u-boot.srec
+/LOG
+/errlog
+/reloc_off
+
+commit f30ad49b16bf998b03c1a5228b6c86369d61c258
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Mon Nov 19 10:02:13 2007 -0500
+
+ Move CONFIG_QE out of CONFIG_PCI wrap for MPC8568MDS
+
+ CONFIG_QE shouldn't be in the wrap of CONFIG_PCI, fix it.
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit f8c320609366176b31104d9bf5e295232e1c7f1d
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date: Mon Nov 19 11:14:16 2007 +0900
+
+ [MIPS] board/gth2/lowlevel_init.S: Fix a build warning
+
+ lowlevel_init.S: Assembler messages:
+ lowlevel_init.S:413: Warning: Pretending global symbol used as branch target is local.
+
+ Looking at codes, the `memtest' and `clearmem' are intentional mixed
+ use of `global symbols' and `label' for debugging purpose. To make it
+ build, just disable global-symbols-use for now. As a result `memtest'
+ still remains as unused, but leave it be...
+
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+
+commit e8da58f2bc092891e8cc92b927ed5c4bd0cb0cab
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Nov 19 12:59:14 2007 +0100
+
+ Fix build problems with mp2usb board
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 6bf4c686afca1e86e1c384d59218f914605713bf
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Nov 18 18:36:11 2007 +0100
+
+ s3c24x0: Fix usb_ohci.c missing in Makefile
+ and usb_ohci.c warning differ in signedness
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 6073f61e078da5ddb521b56256bcc36508589883
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Nov 18 12:55:02 2007 +0100
+
+ pb1x00 board: Fix u16 status declaration when PCMCIA is defined
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 8412d814ce8bf5570a2b747f1e7fd321097fe987
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Nov 18 17:11:09 2007 +0100
+
+ Fix compiler warnings for ARM systems.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 409ecdc0bb47dd28b0af6c25ffd658d22cc36b37
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Nov 18 16:36:27 2007 +0100
+
+ Fix compiler warnings for PPC systems. Update CHANGELOG.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 079c2c4fa71c0d1ebef394508df9088df8a308d3
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Nov 17 11:31:10 2007 +0100
+
+ Fix warning differ in signedness in net/net.c and net/nfs.c
+
+commit 7e14fc65368cbd2861b1207453da55a4fc7b3f81
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Nov 17 20:42:45 2007 +0900
+
+ gth2.c: Fix a warning on gth2 build.
+
+ gth2.c: In function 'misc_init_r':
+ gth2.c:434: warning: pointer targets in passing argument 2 of 'setenv' differ in signedness
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 2309c130aa4c84b91bd874a41269c923eb61b555
+Author: Stefan Roese <sr@denx.de>
+Date: Sat Nov 17 07:58:25 2007 +0100
+
+ Fix warning differ in signedness in common/cmd_scsi.c
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 7e1d884b7cb602007329c517ec1c453e3a6a5d9c
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Nov 17 20:05:26 2007 +0900
+
+ [MIPS] cpu/mips/config.mk: Fix GNU assembler minor version picker
+
+ Current trick to pick up GNU assembler minor version does not work with the
+ latest binutils (2007-03-01 or later) due to ${PKGVERSION} now default to
+ "(GNU Binutils) ".
+
+ $ sde-as --version |grep "GNU assembler"
+ GNU assembler 2.15.94 mipssde-6.02.02-20050602
+ $ sde-as --version |grep "GNU assembler" |awk '{print $3}'
+ 2.15.94
+ $ sde-as --version |grep "GNU assembler" |awk '{print $3}' |awk -F. '{print $2}'
+ 15
+ $
+
+ $ mips-linux-as --version |grep "GNU assembler"
+ GNU assembler (GNU Binutils) 2.18
+ $ mips-linux-as --version |grep "GNU assembler" |awk '{print $3}'
+ (GNU
+ $ mips-linux-as --version |grep "GNU assembler" |awk '{print $3}' |awk -F. '{print $2}'
+ (no output)
+ $
+
+ As a result of above, you'll see many noises with such binutils:
+
+ make -C cpu/mips/
+ /bin/sh: line 0: [: : integer expression expected
+ /bin/sh: line 0: [: : integer expression expected
+ make[1]: Entering directory `/home/skuribay/devel/u-boot.git/cpu/mips'
+ mips-linux-gcc -D__ASSEMBLY__ -g -Os -D__KERNEL__ -DTEXT_BASE=0xB0000000 -I/home/skuribay/devel/u-boot.git/include -fno-builtin -ffreestanding -nostdinc -isystem /home/skuribay/devel/buildroot/build_mips/staging_dir/usr/bin/../lib/gcc/mips-linux-uclibc/4.2.1/include -pipe -DCONFIG_MIPS -D__MIPS__ -G 0 -mabicalls -fpic -pipe -msoft-float -march=4kc -mtune=4kc -EB -c -o incaip_wdt.o incaip_wdt.S
+ /bin/sh: line 0: [: : integer expression expected
+ mips-linux-gcc -D__ASSEMBLY__ -g -Os -D__KERNEL__ -DTEXT_BASE=0xB0000000 -I/home/skuribay/devel/u-boot.git/include -fno-builtin -ffreestanding -nostdinc -isystem /home/skuribay/devel/buildroot/build_mips/staging_dir/usr/bin/../lib/gcc/mips-linux-uclibc/4.2.1/include -pipe -DCONFIG_MIPS -D__MIPS__ -G 0 -mabicalls -fpic -pipe -msoft-float -march=4kc -mtune=4kc -EB -c -o cache.o cache.S
+ /bin/sh: line 0: [: : integer expression expected
+ mips-linux-gcc -g -Os -D__KERNEL__ -DTEXT_BASE=0xB0000000 -I/home/skuribay/devel/u-boot.git/include -fno-builtin -ffreestanding -nostdinc -isystem /home/skuribay/devel/buildroot/build_mips/staging_dir/usr/bin/../lib/gcc/mips-linux-uclibc/4.2.1/include -pipe -DCONFIG_MIPS -D__MIPS__ -G 0 -mabicalls -fpic -pipe -msoft-float -march=4kc -mtune=4kc -EB -Wall -Wstrict-prototypes -c -o asc_serial.o asc_serial.c
+ /bin/sh: line 0: [: : integer expression expected
+
+ This patch simplifies the trick and makes it work with both versions of gas.
+ I also replace an expensive `awk (or gawk)' with `cut'.
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 16664f72850846e645616da1c0fa5afcd6d15f15
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Nov 17 20:05:26 2007 +0900
+
+ [MIPS] Remove useless instructions for initializing $gp.
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 03c031d5660ea946c39af6e2e16267da857c609f
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Oct 27 15:27:06 2007 +0900
+
+ [MIPS] MIPS 4K core: Coding style cleanups
+
+ No logical changes.
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit f5e429d3860bba4c6ae8bead8f78349fa24491b2
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Nov 17 20:05:20 2007 +0900
+
+ [MIPS] gth2.c: Fix a warning on gth2 build.
+
+ gth2.c: In function 'misc_init_r':
+ gth2.c:434: warning: pointer targets in passing argument 2 of 'setenv' differ in signedness
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 4fbd0741b2b6441da10be93e10267122581b7079
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Oct 27 15:22:33 2007 +0900
+
+ [MIPS] au1x00_eth.c: Fixed a warning on pb1000 build.
+
+ au1x00_eth.c: In function 'au1x00_miiphy_write':
+ au1x00_eth.c:139: warning: 'return' with no value, in function returning non-void
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit f01320459736f156707425cf8112f98606301aa4
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Oct 27 15:00:25 2007 +0900
+
+ [MIPS] au1x00_eth.c: Fix au1x00_miiphy_{read,write} build error
+
+ au1x00_eth.c: In function 'au1x00_enet_initialize':
+ au1x00_eth.c:246: error: 'au1x00_miiphy_read' undeclared (first use in this function)
+ au1x00_eth.c:246: error: (Each undeclared identifier is reported only once
+ au1x00_eth.c:246: error: for each function it appears in.)
+ au1x00_eth.c:246: error: 'au1x00_miiphy_write' undeclared (first use in this function)
+ au1x00_eth.c: In function 'au1x00_miiphy_write':
+ au1x00_eth.c:298: warning: 'return' with no value, in function returning non-void
+ make[1]: *** [au1x00_eth.o] Error 1
+
+ Fixed by moving these two functions forward.
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit b09258c5393edd1087c5f39ae68338f16b49f8b3
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Oct 27 15:00:25 2007 +0900
+
+ MAKEALL: Added missing pb1000 board
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 2e4a6e3667a1e39c0e6e99498686b15d2718b369
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Oct 27 15:00:24 2007 +0900
+
+ [MIPS] pb1000: Replace obsolete memsetup.S with lowlevel_init.S
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 662e5cb397249c3ea88a4c3255e9ccfc40b98d82
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Oct 27 15:00:24 2007 +0900
+
+ [MIPS] u-boot.lds: Cleanup __u_boot_cmd_{start,end}
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 5947f6999aafa7c54c1390983d264a8463dfea8e
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Nov 17 02:34:38 2007 +0100
+
+ Update CHANGELOIG, prepare for -rc4
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit fd329e6f05bbdfe6bd71b0e09f0c76d3b0a025a5
+Author: Luotao Fu <l.fu@pengutronix.de>
+Date: Wed Nov 14 18:58:33 2007 +0100
+
+ Fix the i2c frequency and default address in rsdproto board
+
+ rsdproto board support has wrong I2C frequency and wrong return value
+ handling.
+
+ Signed-off-by: Luotao Fu <l.fu@pengutronix.de>
+
+commit 429c180edad038f91c989cb14b478228092e7054
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Nov 17 01:45:38 2007 +0100
+
+ powerpc: Backout relocation changes for MPC5121, too.
+
+ Apply Grant Likely's backout to MPC5121 code, too.
+
+ Pointed out by Rafal Jaworowski <raj@semihalf.com>
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 1c3dd43338a077165e7e0309cb3994e65d2bdbf8
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Tue Nov 13 22:18:33 2007 -0700
+
+ powerpc: Backout relocation changes.
+
+ Ugh. I *hate* to back this change out, but these compiler flags don't
+ work for relocation on all versions of GCC. I've not been able to
+ reproduce the environment in my setup (and hence, not been able to
+ find a combination that *does* work), so I've got no choice but to go
+ back to the old gcc flags and linker script.
+
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 5c15010efad980ad5498cc565fc1ed70df2f52b4
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Tue Nov 13 09:11:05 2007 +0100
+
+ Fixed mips_io_port_base build errors.
+
+ This patch has been sent on:
+ - 29 Sep 2007
+
+ Although mips_io_port_base is currently a part of IDE command, it is quite
+ fundamental for MIPS I/O port access such as in[bwl] and out[bwl]. So move
+ it to MIPS general part, and introduce `set_io_port_base()' from Linux.
+
+ This patch is triggered by multiple definition of `mips_io_port_base' build
+ error on gth2 (and tb0229 also needs this fix.)
+
+ board/gth2/libgth2.a(gth2.o): In function `log_serial_char':
+ /home/skuribay/devel/u-boot.git/board/gth2/gth2.c:47: multiple definition of `mips_io_port_base'
+ common/libcommon.a(cmd_ide.o):/home/skuribay/devel/u-boot.git/common/cmd_ide.c:712: first defined here
+ make: *** [u-boot] Error 1
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 6ecbb7a3fa9b0940ed33e490d195d4b6830b2422
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Nov 17 01:30:40 2007 +0100
+
+ Fix a bug in the slave serial programming mode for the Xilinx
+ Spartan2/3 FPGAs. The old code used "< 0" on a "char" type to test if
+ the most significant bit was set, which did not work on any
+ architecture where "char" defaulted to be an unsigned type.
+
+ Based on a patch by Angelos Manousaridis <amanous@inaccessnetworks.com>
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit d08b7233bc252faad8339e7ca0ddfd62fa79903c
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Nov 1 12:23:29 2007 -0500
+
+ 86xx: Fix broken variable reference when #def DEBUGing.
+
+ Sometimes you can't reference the DDR2 controller variables.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit f9d9164d9c6b5a7f0393fd8d7e246b8a0326bc19
+Author: Jason Jin <Jason.jin@freescale.com>
+Date: Fri Oct 26 18:32:00 2007 +0800
+
+ make 8610 board use pixis reset
+
+ Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+
+commit db74b3c1c9481a6bffbf8cd445e5bcbf6908e836
+Author: Jason Jin <Jason.jin@freescale.com>
+Date: Mon Oct 29 19:26:21 2007 +0800
+
+ Unify pixis_reset altbank across board families
+
+ Basically, refactor the CFG_PIXIS_VBOOT_MASK values
+ into the separate board config files.
+
+ Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 64bf555465c7926be13e1046ac0d0f05ac72829c
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Wed Nov 7 08:19:21 2007 +0100
+
+ Fix warning: pointer targets in assignment differ in signedness
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 7a60ee7c6248a958c5757d3660a1702723a2786d
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Wed Nov 7 08:19:19 2007 +0100
+
+ Fix warning differ in signedness in common/cmd_ide.c
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 955413f35f054a82e40042f1dbcf501c6a05719b
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Thu Nov 15 08:27:52 2007 -0700
+
+ Revert "Correct relocation fixup for mpc5xx"
+
+ This reverts commit 3649cd99ba815b6601868735765602f00ef3692b.
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit e15633888a058aacb31a62d2cf1278e1e4c236ab
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Thu Nov 15 08:24:32 2007 -0700
+
+ Revert "Correct fixup relocation for MPC5xxx"
+
+ This reverts commit 6f7576b20ecf0d040c3ac3b032b5cbc860e38a90.
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 139365fbe566d0fc619a1ed04452ec5388f0cef8
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Thu Nov 15 08:21:04 2007 -0700
+
+ Revert "Correct fixup relocation for mpc8220"
+
+ This reverts commit a85dd254c0577fca13627c46e93fc2ad4c4f1f00.
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 70922342369e5e39b286fe21e768a239ca07a514
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Thu Nov 15 08:20:57 2007 -0700
+
+ Revert "Correct fixup relocation for mpc824x"
+
+ This reverts commit f3a52fe05923935db86985daf9438e2f70ac39aa.
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 96279ab4cad60cb5972aa934fbe4845ac02cc75a
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Thu Nov 15 08:20:50 2007 -0700
+
+ Revert "Correct fixup relocation for mpc8260"
+
+ This reverts commit 5af61b2f4b838a05f79be274f3e5a66edd2d9c96.
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 928fe33b24cdf382a8dc8687fed24b1961cdb5d6
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Thu Nov 15 08:20:43 2007 -0700
+
+ Revert "Correct fixup relocation for mpc83xx"
+
+ This reverts commit 057004f4a4863554d56cc56268bfa7c7d9738e27.
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit c93945e8f9e300860d2bf73a2549ce5794f8bd00
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Thu Nov 15 08:20:25 2007 -0700
+
+ Revert "[MPC512x] Correct fixup relocation"
+
+ This reverts commit 8d17979d0359492a822a0a409d26e3a3549b4cd4.
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 54fd6c93c28a0a45352fff5dd92673401ff563f2
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Nov 13 08:18:20 2007 +0100
+
+ ppc4xx: lwmon5: Change PHY reset sequence for PHY MDIO address latching
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 1ce55151c85d068f70317a8d65c61058b891afb4
+Author: Heiko Schocher <hs@denx.de>
+Date: Tue Nov 13 07:50:29 2007 +0100
+
+ [UC101] SRAM now with 2 MB working.
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 8d737a28152ec12873f8544cca1fb39a49e5e693
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Nov 8 12:50:18 2007 -0600
+
+ ColdFire: MCF5329 - Remove reset registers from CCM
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 7d7cdea769a60b0a6e4c18bef7f9d648fd14b8d7
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Nov 8 12:31:11 2007 -0600
+
+ ColdFire: MCF5329 - Add Reset structure to immap_5329.h
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 09b26cf00d76d75fdf7fdc4b13e4dd929743bc21
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Nov 8 12:19:01 2007 -0600
+
+ ColdFire: MCF5329 - revert include/asm-m68k/m5329.h file mode
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 225a24b5e062ad94627424508ae814f51dbe1a34
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Wed Nov 7 18:00:54 2007 -0600
+
+ ColdFire: MCF5445x - Update correct RAMBAR and missing linker files
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 248c7c14835f34d5d910b45e5600050e58ca6cab
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Wed Nov 7 17:56:15 2007 -0600
+
+ ColdFire: MCF532x - Update do_reset() using core reset
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit d9240a5f827eb3b476a6ba2938d01f1a9e7688f4
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Wed Nov 7 17:51:00 2007 -0600
+
+ ColdFire: Update cpu flag for 4.2-xx compiler
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 1f103105a3746ab12279b63b8c1d372c0ce2cc58
+Author: Roy Zang <tie-fei.zang@freescale.com>
+Date: Mon Nov 5 17:39:24 2007 +0800
+
+ Implement general ULi 526x Ethernet driver support in U-boot
+
+ This patch implements general ULi 526x Ethernet driver.
+ Until now, it is the only native Ethernet port on
+ MPC8610HPCD board, but it could be used on other boards
+ with ULi 526x Ethernet port as well.
+
+ Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
+ Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
+ Acked-by: Jon Loeliger <jdl@freescale.com>
+ Signed-off-by: Ben Warren <bwarren@qstreams.com>
+
+commit 71bc6e6474fea8ef481b9b45d1edd7ad1f6dfbbd
+Author: Larry Johnson <lrj@arlinx.com>
+Date: Thu Nov 1 08:46:50 2007 -0500
+
+ NET: Add Ethernet 1000BASE-X support for PPC4xx
+
+ This patch adds support for 1000BASE-X to functions "miiphy_speed ()" and
+ "miiphy_duplex()". It also adds function "miiphy_is_1000base_x ()", which
+ returns non-zero iff the PHY registers are configured for 1000BASE-X. The
+ "mii info" command is modified to distinguish between 1000BASE-T and -X.
+
+ Signed-off-by: Larry Johnson <lrj@acm.org>
+ Signed-off-by: Ben Warren <bwarren@qstreams.com>
+
+commit 298035df4948b113d29ac0e694717d34b95bc5dc
+Author: Larry Johnson <lrj@arlinx.com>
+Date: Wed Oct 31 11:21:29 2007 -0500
+
+ NET: Cosmetic changes
+
+ Signed-off-by: Larry Johnson <lrj@acm.org>
+ Signed-off-by: Ben Warren <bwarren@qstreams.com>
+
+commit 992742a5b09d9040adbd156fb90756af66ade310
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Nov 3 23:09:27 2007 +0100
+
+ Cleanup coding style; update CHANGELOG
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit e881cb563e32f45832b7b6db77bdcd017adcbb41
+Author: Bruce Adler <bruce.adler@ccpu.com>
+Date: Fri Nov 2 13:15:42 2007 -0700
+
+ fix wording in README
+
+ Changed the wording to properly describe the shadowing
+ of the environment from ROM to RAM
+
+ Signed-off-by: Bruce Adler <bruce.adler@acm.org>
+
+commit ad845beef06245426c57b53dcdc01b7dc70e0d45
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Wed Oct 31 02:18:15 2007 +0900
+
+ blackfin: Move `-D__BLACKFIN__' to $(ARCH)_config.mk
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit ec22755799466c8a103664bb3a5e647bf9c238f4
+Author: Vlad Lungu <vlad@comsys.ro>
+Date: Thu Oct 25 16:08:14 2007 +0300
+
+ Trimmed some variables in ne2000.c
+
+ Signed-off-by: Vlad Lungu <vlad@comsys.ro>
+
+commit eb6f214d3644b2a77968c176ed36dcf858cfe7e0
+Author: Zhang Wei <wei.zhang@freescale.com>
+Date: Thu Oct 25 17:51:27 2007 +0800
+
+ Fix the issue of usb_kbd driver missing the scan code of key 'z'.
+
+ The scan code of the key 'z' is 0x1d, which should be handled.
+
+ The change has be tested on NOVATEK USB keyboard and ULI PCI OHCI
+ controller.
+
+ Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
+
+commit bbf4796f6498fbade56d56eff3a0a49b299d93e5
+Author: Zhang Wei <wei.zhang@freescale.com>
+Date: Thu Oct 25 17:30:04 2007 +0800
+
+ Fix USB support issue for MPC8641HPCN board.
+
+ The configuration file has already enabled USB, but it
+ missed definition of CFG_OHCI_SWAP_REG_ACCESS, the USB
+ on MPC8641HPCN can not work because of the wrong USB
+ register endian.
+
+ And add the USB command to U-Boot commands list.
+
+ Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
+
+commit 4e62041023dc3de9d98d977bb080235bc6d035e0
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Wed Oct 24 18:16:01 2007 +0200
+
+ Use config_cmd_default.h instead of config_cmd_all.h
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 56622f87857439b1c221e9deef11a9d5bb5d4308
+Author: Marian Balakowicz <m8@semihalf.com>
+Date: Wed Oct 24 01:37:36 2007 +0200
+
+ TQM5200: Call usb_cpu_init() during board init
+
+ usb_cpu_init() configures GPS USB pins, clocks, etc. and
+ is required for proper operation of kernel USB subsystem.
+ This setup was previously done in the kernel by the fixup
+ code which is being removed, thus low level init must be
+ done by U-boot now.
+
+ Signed-off-by: Marian Balakowicz <m8@semihalf.com>
+
+commit 29c29c0267fe857e72014ce90c5d35b2ef6302bd
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date: Tue Oct 23 16:25:50 2007 +0200
+
+ Fix typo in nfs.c
+
+ An obvious typo. Originally fixed in linkstation u-boot port.
+
+ Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+
+commit 59543fe00a4ce720ef9f5aa7fb387c6daf1c7d78
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date: Tue Oct 23 14:35:05 2007 +0200
+
+ Fix a typo in cpu/mpc824x/interrupts.c
+
+ Since December 2003 the timer_interrupt_cpu() function in
+ cpu/mpc824x/interrupts.c contains what seems to be a superfluous
+ parameter. Remove it.
+
+ Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+
+commit c9e7b9b9a1700fe009678d1f9b41e6364ac5df2d
+Author: Sergej Stepanov <Sergej.Stepanov@ids.de>
+Date: Wed Oct 17 11:13:51 2007 +0200
+
+ add ft_cpu_setup(..) on mpc8260
+
+ Add ft_cpu_setup(..)-function to adapt it for use with libfdt
+ based on code from mpc5xxx
+
+ Sigend-off-by: Sergej Stepanov <Sergej.Stepanov@ids.de>
+ --
+
+commit 6abd82e19ae93c0b4d104e50165e235915ec0875
+Author: Sergej Stepanov <Sergej.Stepanov@ids.de>
+Date: Wed Oct 17 11:18:42 2007 +0200
+
+ changes for IDS8247 board support
+
+ To get the IDS8247 board working following are done:
+ - FCC2 is deactivated
+ - FCC1 is activated
+ - I2C is activated
+ - CFI driver is activated
+ - Adapted for use with LIBFDT
+
+ Signed-off-by: Sergej Stepanov <Sergej.Stepanov@ids.de>
+ --
+
+commit 8b6684a698500be9c142ec2c9f46cfc348e17f0c
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Wed Oct 24 15:48:37 2007 +0200
+
+ ATSTK1002: Remove default ethernet addresses
+
+ Wolfgang is right: It's not a good idea to set up default initial
+ ethernet addresses for a board, even though they belong to the local
+ range.
+
+ This will change the failure mode from "IT manager screams at you for
+ using duplicate ethernet addresses" to a nice error message explaining
+ that the ethernet address hasn't been set properly.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit e5c794e491a57d829b6d8733e2ed8368a2269abf
+Author: Justin Flammia <jflammia@savantav.com>
+Date: Mon Oct 29 17:40:35 2007 -0400
+
+ DHCP Client Fix
+
+ This is a multi-part message in MIME format.
+
+ commit e6e505eae94ed721e123e177489291fc4544b7b8
+ Author: Justin Flammia <jflammia@savantav.com>
+ Date: Mon Oct 29 17:19:03 2007 -0400
+
+ Found a bug in the way the DHCP Request packet is built, where the IP address
+ that is offered by the server is bound to prematurely. This patch is a fix of
+ that bug where the IP address offered by the DHCP server is not used until
+ after the DHCP ACK from the server is received.
+
+ Signed-off-by: Justin Flammia <jflammia@savantav.com>
+ Signed-off-by: Ben Warren <bwarren@qstreams.com>
+
+commit 31548249decf18a6b877a18436b6139dd483fe4a
+Author: Justin Flammia <jflammia@savantav.com>
+Date: Mon Oct 29 17:40:35 2007 -0400
+
+ DHCP Client Fix
+
+ This is a multi-part message in MIME format.
+
+ commit e6e505eae94ed721e123e177489291fc4544b7b8
+ Author: Justin Flammia <jflammia@savantav.com>
+ Date: Mon Oct 29 17:19:03 2007 -0400
+
+ Found a bug in the way the DHCP Request packet is built, where the IP address
+ that is offered by the server is bound to prematurely. This patch is a fix of
+ that bug where the IP address offered by the DHCP server is not used until
+ after the DHCP ACK from the server is received.
+
+ Signed-off-by: Justin Flammia <jflammia@savantav.com>
+ Signed-off-by: Ben Warren <bwarren@qstreams.com>
+
+commit e8ee8f3ade2a06c1893dd5e68f223070d650c7ed
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Oct 25 17:16:22 2007 -0500
+
+ ColdFire 54455: Fix correct boot location for atmel and intel
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 688e8eb414ac111cca7ce60bdf30e805ab9a7bcb
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Oct 25 17:14:00 2007 -0500
+
+ ColdFire: Fix build error when CONFIG_WATCHDOG is defined
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit c67e12e705b204cfe914e3e3e693d69a445dcabf
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Oct 25 17:12:36 2007 -0500
+
+ ColdFire 5329: Assign correct SDRAM size and fix cache
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 95e9f2c212a65610b2e59a5c00d0113383a4da0b
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Oct 25 17:10:23 2007 -0500
+
+ ColdFire 5253: Assign correct SDRAM size
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 2acefa72ee0026f862ab65597ca687428f63a973
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Oct 25 17:09:17 2007 -0500
+
+ ColdFire 5282: Fix external flash boot and return dramsize
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit d78791ae914d4e7c5edca1cdad73b3dc81a4eb82
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Thu Oct 25 17:20:01 2007 +0200
+
+ TQM5200: increase kernel_addr_r and fdt_addr_r (hinted by Wolfgang Denk).
+
+ Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit 1a0ce20aa4cb4e3068da04e7290ee9986fd0b834
+Author: Martin Krause <martin.krause@tqs.de>
+Date: Wed Oct 24 08:42:25 2007 +0200
+
+ TQM5200: fix spurious characters on second serial interface
+
+ With this patch PSC3 is configured as UART. This is done, because if
+ the pins of PSC3 are not configured at all (-> all pins are GPI),
+ due to crosstalk, spurious characters may be send over the RX232_2_TXD
+ signal line.
+
+ Signed-off-by: Martin Krause <martin.krause@tqs.de>
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit be4a87f11e297a5cededbf7dd71c0248f3874acd
+Author: Martin Krause <martin.krause@tqs.de>
+Date: Wed Oct 24 08:41:27 2007 +0200
+
+ TQM5200S: fix commands for STK52xx base board because of missing SM501 grafic controller
+
+ Some commands for the STK52xx base board try to access the SM501 grafic
+ controller. But the TQM5200S has no grafic controller (only the TQM5200
+ and the TQM5200B have). This patch deactivates the commands accessing
+ the SM501 for the TQM5200S.
+
+ Signed-off-by: Martin Krause <martin.krause@tqs.de>
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit b31f64343ead9482cd439b1adbe4c34026a641b1
+Author: Martin Krause <martin.krause@tqs.de>
+Date: Mon Oct 22 16:45:53 2007 +0200
+
+ TQM5200: fix spurious characters on second serial interface
+
+ With this patch PSC3 is configured as UART. This is done, because if
+ the pins of PSC3 are not configured at all (-> all pins are GPI),
+ due to crosstalk, spurious characters may be send over the RX232_2_TXD
+ signal line.
+
+ Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit 0fc0f91b20ffa802f5a66534ca5c2844910583f6
+Author: Martin Krause <martin.krause@tqs.de>
+Date: Mon Oct 22 16:40:06 2007 +0200
+
+ TQM5200S: fix commands for STK52xx base board because of missing SM501 grafic controller
+
+ Some commands for the STK52xx base board try to access the SM501 grafic
+ controller. But the TQM5200S has no grafic controller (only the TQM5200
+ and the TQM5200B have). This patch deactivates the commands accessing
+ the SM501 for the TQM5200S.
+
+ Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit 7b0a42219f30277f71f4405cbaf8a269f6d2d227
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Oct 21 09:14:28 2007 +0200
+
+ Mips: Fix string functions differ prototype declaration
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit cb8250fe4b3c4ed549b270e8a20bc22060e7e1d2
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Fri Oct 19 17:51:40 2007 -0500
+
+ fsl_pci_init enable COMMAND_MEMORY if inbound window
+
+ Patch 16e23c3f removed PCSRBAR allocation. But passing zero windows
+ to pciauto_setup_device has the side effect of not getting
+ COMMAND_MEMORY set.
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit e9d0d527992566ebef9826962ff1745b2f082b92
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri Oct 19 10:55:24 2007 +0200
+
+ delta: Fix OHCI_REGS_BASE undeclared and wait_ms implicit declaration
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 9c4884f54da982ce990c7d1760ac81b0704d3c64
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri Oct 19 08:10:15 2007 +0200
+
+ fix warning: no return statement in function returning non-void
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit e78220f6e514206757acfe247297fc9a328a881f
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri Oct 19 06:33:45 2007 +0200
+
+ xsengine: Fix no partition type specified, use DOS as default
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 10cdb8dbd67a818823ab9ec88b68fc348903db59
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri Oct 19 00:24:59 2007 +0200
+
+ lubbock: Fix no partition type specified, use DOS as default
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 41b4d282d38fa7231c315c5f6cfff5bdd24e0191
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Oct 23 16:50:03 2007 +0200
+
+ Coding style: keep lists sorted; update CHANGELOG
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 58b74b05c621e2835ecf4e2d3243042cf4186777
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri Oct 19 00:09:05 2007 +0200
+
+ Fix missing drivers makefile entries ds1722.c mw_eeprom.c
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 96455bfebc9887837095c9051d216f53c61b5f10
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri Oct 19 00:07:39 2007 +0200
+
+ Fix warning differ in signedness in board/innokom/innokom.c
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 2a4741d9a14ec475f50e9856d2c0a67e8b4271bd
+Author: Marcel Ziswiler <marcel@ziswiler.com>
+Date: Fri Oct 19 00:25:33 2007 +0200
+
+ fix pxa255_idp board
+
+ The pxa255_idp being an old unmaintained board showed several issues:
+ 1. CONFIG_INIT_CRITICAL was still defined.
+ 2. Neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION was defined.
+ 3. Symbol flash_addr was undeclared.
+ 4. The boards lowlevel_init function was still called memsetup.
+ 5. The TEXT_BASE was still 0xa3000000 rather than 0xa3080000.
+ 6. Using -march=armv5 instead of -march=armv5te resulted in lots of
+ 'target CPU does not support interworking' warnings on recent compilers.
+ 7. The PXA's serial driver redefined FFUART, BTUART and STUART used as
+ indexes rather than the register definitions from the pxa-regs header
+ file. Renamed them to FFUART_INDEX, BTUART_INDEX and STUART_INDEX to
+ avoid any ambiguities.
+ 8. There were several redefinition warnings concerning ICMR, OSMR3,
+ OSCR, OWER, OIER, RCSR and CCCR in the PXA's assembly start file.
+ 9. The board configuration file was rather outdated.
+ 10. The part header file defined the vendor, product and revision arrays
+ as unsigned chars instead of just chars in the block_dev_desc_t
+ structure.
+
+ Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
+
+commit 298cd4cafe81ff8a6c87be8fbc440a20720d3ed6
+Author: Rune Torgersen <runet@innovsys.com>
+Date: Wed Oct 17 11:56:31 2007 -0500
+
+ Make MPC8266ADS command selection more robust
+
+ Fix MPC8266 command line definition so it won't break when new commands
+ are added to u-boot.
+ Signed-off-by Rune Torgersen <runet@innovsys.com>
+
+commit d3afa1ee19345a31fd1eaad3e98b97d13ca47315
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Tue Oct 23 13:14:10 2007 +0200
+
+ Motion-PRO: Update configuration to accomodate next generation board.
+
+ New board has faster oscillator and a different Flash chip. This affects:
+ - CFG_MPC5XXX_CLKIN
+ - SDRAM timings
+ - Flash CS configuration (timings)
+ - Flash sector size, and thus MTD partition layout
+ - malloc() arena size (due to bigger Flash sectors)
+ - smaller memory test range (due to bigger malloc() arena)
+
+ This patch also enables more extensive memory testing via "mtest".
+
+ Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit eff501904df2bf1724a750062628ba2c51dbb1f8
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Tue Oct 23 11:36:07 2007 +0200
+
+ Motion-PRO: Add setting of SDelay reg. to SDRAM controller configuration.
+
+ Per AN3221 (MPC5200B SDRAM Initialization and Configuration), the SDelay
+ register must be written a value of 0x00000004 as the first step of the
+ SDRAM contorller configuration.
+
+ Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit 7a9348728ebda63cdbaacffd83099aa71d9d4c54
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Oct 23 10:22:16 2007 +0100
+
+ Move PL01* serial drivers to drivers/serial and adjust Makefiles.
+
+commit 20d500d531a6b971ce6cc1bf191cb0092cdc0afc
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Oct 23 10:17:42 2007 +0200
+
+ ppc4xx: lwmon5: Some further GPIO config changes
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit de9a738faa7c2f47286119c3bfebc3dfbfe7d86d
+Author: Vlad Lungu <vlad@comsys.ro>
+Date: Sun Oct 21 22:10:10 2007 +0900
+
+ [MIPS] Fix UNCACHED_SDRAM
+
+ PHYSADDR is for physical address, KSEG1ADDR is for uncached.
+
+ Signed-off-by: Vlad Lungu <vlad@comsys.ro>
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+
+commit 00101dd7a32d12f698150123e47e4b3420279f86
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date: Sun Oct 21 21:30:42 2007 +0900
+
+ [MIPS] Add PIC-related switches to PLATFORM_{CPP,LD}FLAGS and cleanup
+
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+
+commit eb700636db017d310edaeb559b13d82588560674
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date: Sun Oct 21 10:55:37 2007 +0900
+
+ [MIPS] u-boot.lds: Define _gp in a standard manner
+
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+
+commit 22069215eb7adf5a3888bf7c7784ea9d70a72cd0
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date: Sun Oct 21 10:55:36 2007 +0900
+
+ [MIPS] Fix $gp usage
+
+ Now we load $gp with _GLOBAL_OFFSET_TABLE_, but this is incorrect use.
+ As a general principle, we should use _gp for $gp.
+
+ Thanks to linker script's help we fortunately have _gp which equals to
+ _GLOBAL_OFFSET_TABLE_. But once _gp gets out of alignment, we will not
+ be able to access to GOT entires, global variables and procedure entry
+ points. The right thing to do is to use _gp.
+
+ This patch also introduce a new symbol `.gpword _GLOBAL_OFFSET_TABLE_'
+ which holds the offset from _gp. When updating GOT entries, we use this
+ offset and _gp to calculate the final _GLOBAL_OFFSET_TABLE_.
+
+ This patch is originally submitted by Vlad Lungu <vlad@comsys.ro>, then
+ I made some change to leave over num_got_entries.
+
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+ Cc: Vlad Lungu <vlad@comsys.ro>
+
+commit cbf2323b5b8285ea01acba7bbb905a3162d9b021
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date: Sun Oct 21 10:55:36 2007 +0900
+
+ [MIPS] u-boot.lds: Fix __got_start and __got_end
+
+ Ensure that __got_start points to top of the `.got', and __got_end points
+ to bottom as well, so that we never fail to count num_got_entries.
+
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+
+commit e5f325fec5b48ae705c89522923ba5a2e37cd5c7
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date: Sun Oct 21 10:55:36 2007 +0900
+
+ [MIPS] u-boot.lds: Remove duplicated .sdata section
+
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+
+commit 05bf4919c1ce49cdedadacd564d0786a8ed796a1
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Oct 21 01:01:17 2007 +0200
+
+ Minor coding style cleanup; update CHANGELOG
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit ff285ca07eda1ea4a8909848cc1cc604ec8fec9c
+Author: Vlad Lungu <vlad@comsys.ro>
+Date: Thu Oct 4 20:47:10 2007 +0300
+
+ Fix NE2000 driver:
+
+ Fixed typo in ne2000.h, thinko re n2k_inb() usage, don't try
+ to do anything in eth_stop() if eth_init() was not called.
+ Simplified RX path in order to avoid timeouts on really really
+ fast NE2000 cards (read: qemu with internal tftp), NetLoop() is
+ clever enough to cope with 1 packet per eth_rx().
+
+ Signed-off-by: Vlad Lungu <vlad@comsys.ro>
+
+commit df90968b48fb34fa9072fab150db2ac89678f537
+Author: urwithsughosh@gmail.com <urwithsughosh@gmail.com>
+Date: Mon Sep 24 13:32:13 2007 -0400
+
+ Setting MSR[DE] in do_reset
+
+ Hello,
+ This patch ensures the soft reset of the board for the 85xx boards
+ by setting the MSR[DE] in the do_reset function.
+
+ Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
+
+commit 1e701e701304b3c3a3768ca83dd2ab7b9e88c77d
+Author: urwithsughosh@gmail.com <urwithsughosh@gmail.com>
+Date: Mon Sep 24 13:36:01 2007 -0400
+
+ MSR overwrite fix
+
+ Hello,
+ This patch fixes the MSR overwrite in the start.S when moving out of
+ the last 4K page.
+
+ Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
+
+commit 5c7ea64bb74a850a2b2303f853a8270695ad8602
+Author: Dan Wilson <dwilson@fulcrummicro.com>
+Date: Fri Oct 19 11:33:48 2007 -0500
+
+ tsec driver should clear RHALT on startup
+
+ This was causing problems for some people.
+
+ Signed-off-by: Alain Gravel <agravel@fulcrummicro.com>
+ Signed-off-by: Dan Wilson <dwilson@fulcrummicro.com>
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 7600d47b8f6a10019e537dc9a62aa1498df58d25
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Oct 11 00:29:18 2007 -0500
+
+ Improve handling of PCI interrupt device tree fixup on MPC85xx CDS
+
+ On the MPC85xx CDS we have two issues:
+
+ 1. The device tree fixup code did not check to see if the property we are
+ trying to update is actually found. Its possible that it would update
+ random memory starting at 0.
+
+ 2. Newer Linux kernel's have moved the location of the PCI nodes to be
+ sibilings of the soc node and not children. The explicit PATH to the PCI
+ node would not be found for these device trees. Add the ability to handle
+ both paths. In the future we shouldn't handle such fixups by explicit path.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit a3063eec775719b7e91023bbec3f64b3118791df
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Oct 11 00:18:48 2007 -0500
+
+ Set OF_STDOUT_PATH to match the default console on MPC8568 MDS
+
+ On the MPC8568 MDS we use ttyS0, UART0, etc. as the standard configured
+ console. Make it so we match that config what we tell Linux as the early
+ STDOUT console.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit e1ce3cb617bb06f91f82f98915391175addf3e82
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Tue Oct 2 11:12:27 2007 -0500
+
+ Remove magic numbers from cache related operations for mpc85xx
+
+ The mpc85xx start code uses some magic numbers that we actually
+ have #defines for in <config.h> so use those instead.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 5441f61a3d8b7034f19fc1361183e936198e6dbb
+Author: Detlev Zundel <dzu@denx.de>
+Date: Fri Oct 19 16:47:26 2007 +0200
+
+ Fix two typos.
+
+ Signed-off-by: Detlev Zundel <dzu@denx.de>
+
+commit 281df457c1aa50d2752165d0c5c3282d4027b974
+Author: Tony Li <tony.li@freescale.com>
+Date: Thu Oct 18 17:47:19 2007 +0800
+
+ mpc83xx: Add configure entry for MPC83xx ATM support
+
+ Add MPC8360EMDS_ATM_config and MPC832XEMDS_ATM_config into
+ Makfile and MAKEALL
+
+ Signed-off-by: Tony Li <tony.li@freescale.com>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit d2646554f529a9577515eceb0ec5eceee18244ba
+Author: Tony Li <tony.li@freescale.com>
+Date: Thu Oct 18 17:44:38 2007 +0800
+
+ mpc83xx: pq-mds-pib.c typo error
+
+ Correct to val8 from val.
+
+ Signed-off-by: Tony Li <tony.li@freescale.com>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 3e11ae80fec1ee12194940955431186abf6009c2
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Oct 17 15:40:19 2007 +0200
+
+ ppc4xx: Add 667/133 (CPU/PLB) frequency setup to Sequoia bootstrap command
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 7ee6ba1a056e4061ab4cfde30127e332e7957afd
+Author: runet@innovsys.com <runet@innovsys.com>
+Date: Tue Oct 16 14:50:40 2007 -0500
+
+ Make MPC8266ADS board compile again.
+
+ Signed-off-by: Runet Torgersen <runet@innovsys.com>
+
+commit 2491167c245d8ebe6f2dbd8c4287aaa0d14fe93a
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Mon Aug 27 12:41:03 2007 -0500
+
+ 86xx: Allow for fewer DDR slots per memory controller.
+
+ As a direct correlation exists between DDR DIMM slots
+ and SPD EEPROM addresses used to configure them, use
+ the individually defined SPD_EEPROM_ADDRESS* values to
+ determine if a DDR DIMM slot should have its SPD
+ configuration read or not.
+
+ Effectively, this now allows for 1 or 2 DIMM slots
+ per memory controller.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 4d4a945e189a2f384c66432316da2788a0ac1607
+Author: Rodolfo Giometti <giometti@enneenne.com>
+Date: Mon Oct 15 11:59:17 2007 +0200
+
+ PXA USB OHCI: "usb stop" implementation.
+
+ Some USB keys need to be switched off before loading the kernel
+ otherwise they can remain in an undefined status which prevents them
+ to be correctly recognized by the kernel.
+
+ Signed-off-by: Rodolfo Giometti <giometti@linux.it>
+
+commit e2e93442e558cf1500e92861f99713b2f045ea22
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Oct 15 11:39:00 2007 +0200
+
+ ppc4xx: Fix bug in I2C bootstrap values for Sequoia/Rainier
+
+ The I2C bootstrap values that can be setup via the "bootstrap" command,
+ were setup incorrect regarding the generation of the internal sync PCI
+ clock. The values for PLB clock == 133MHz were slighly incorrect and the
+ values for PLB clock == 166MHz were totally incorrect. This could
+ lead to a hangup upon booting while PCI configuration scan.
+
+ This patch fixes this issue and configures valid PCI divisor values
+ for the sync PCI clock, with respect to the provided external async
+ PCI frequency.
+
+ Here the values of the formula in the chapter 14.2 "PCI clocking"
+ from the 440EPx users manual:
+
+ AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz
+
+ 33MHz async PCI frequency:
+ PLB = 133:
+ => 32 <= 44.3 <= 65 (div = 3)
+
+ PLB = 166:
+ => 32 <= 55.3 <= 65 (div = 3)
+
+ 66MHz async PCI frequency:
+ PLB = 133:
+ => 65 <= 66.5 <= 132 (div = 2)
+
+ PLB = 166:
+ => 65 <= 83 <= 132 (div = 2)
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 5a5958b7de70ae99f0e7cbd5c97ec1346e051587
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Oct 15 11:29:33 2007 +0200
+
+ ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & Yosemite
+
+ The BCSR status bit for the 66MHz PCI operation was correctly
+ addressed (MSB/LSB problem). Now the correct currently setup
+ PCI frequency is displayed upon bootup.
+
+ This patch also fixes this problem on Rainier & Yellowstone, since these
+ boards use the same souce code as Sequoia & Yosemite do.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit da3aad55cbde80ab6e301aafa82a2c411aa53eff
+Author: Martin Krause <martin.krause@tqs.de>
+Date: Wed Sep 26 17:55:56 2007 +0200
+
+ TQM860M: adjust for doubled flash sector size.
+
+ Adjust flash map to support the new S29GLxxN (N-Type) Flashes with
+ doubled sector size.
+
+ Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit 9d29250e2e62f4bf20c7a20b4173d84c48f11f5d
+Author: Jens Gehrlein <jens.gehrlein@tqs.de>
+Date: Wed Sep 26 17:55:54 2007 +0200
+
+ TQM8xx: Fix CAN timing.
+
+ Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit d43e489baf02afae49077791fb22332d240d8656
+Author: Martin Krause <martin.krause@tqs.de>
+Date: Thu Sep 27 14:54:36 2007 +0200
+
+ TQM866M: fix SDRAM refresh
+
+ At 133 MHz the current SDRAM refresh rate is too fast
+ (measured 4 * 1.17 us).
+ CFG_MAMR_PTA changes from 39 to 97. This result
+ in a refresh rate of 4 * 7.8 us at the default clock
+ 50 MHz. At 133 MHz the value will be then 4 * 2.9 us.
+ This is a compromise until a new method is found to
+ adjust the refresh rate.
+
+ Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit 9ef57bbee1c67cc01da2026c242c4692db32be36
+Author: Martin Krause <martin.krause@tqs.de>
+Date: Wed Sep 26 17:55:55 2007 +0200
+
+ TQM866M: adjust for doubled flash sector size.
+
+ Adjust flash map to support the new S29GLxxN (N-Type) Flashes with
+ doubled sector size.
+
+ Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit f8bf90461d9bad2e6fed31fcebaf235f60dd6763
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sun Oct 14 16:12:29 2007 +0200
+
+ [FIX] XUPV2P change command handling
+ and remove code violation
+
+commit 636400198228d96983c06657b17f760f5989958e
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Oct 14 00:13:19 2007 +0200
+
+ Prepare for 1.3.0-rc3 release
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 68f14f77ca5fe5f9cc025c8cae101671f628309f
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Sep 29 13:41:37 2007 +0200
+
+ Fix warning differ in signedness in cpu/pxa/mmc.c
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit fc19e36f741e8bc727c0a330170b3b5db90399ef
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Oct 13 23:51:14 2007 +0200
+
+ Fix warning differ in signedness in board/mpl/vcma9/vcma9.c
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit de74b9eeacccaf0a42e5ecc9ae79a88f7a311296
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Oct 13 21:15:39 2007 +0200
+
+ Coding Style cleanup.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit e1893815b0999410d7a327589611c7b38e95299e
+Author: Wolfgang Denk <wd@denx.de>
+Date: Fri Oct 12 15:49:39 2007 +0200
+
+ GP3 SSA: enable RTC
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 8002012041f1ff9f997a5727abe5015f70cd2e46
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Tue Oct 9 13:58:24 2007 +0200
+
+ [ads5121] EEPROM support added.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 7b624ad254b97e5a25dca2304a398b64aeedaffe
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Sat Oct 6 18:55:35 2007 +0200
+
+ AVR32: Initialize bi_flash* in board_init_r
+
+ The ATSTK1000-specific flash driver intializes bi_flashstart,
+ bi_flashsize and bi_flashoffset, but other flash drivers, like the CFI
+ driver, don't.
+
+ Initialize these in board_init_r instead so that things will still be
+ set up correctly when we switch to the CFI driver.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 2b2a587d6d3076387d22ac740f44044bf46e2cb8
+Author: Marian Balakowicz <m8@semihalf.com>
+Date: Fri Oct 5 10:40:54 2007 +0200
+
+ tqm5200: Fix CONFIG_CMD_PCI typo in board config file.
+
+ Signed-off-by: Marian Balakowicz <m8@semihalf.com>
+
+commit 92869195ef8210758d2176230c0a36897afd50ed
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Fri Oct 5 09:46:06 2007 +0200
+
+ CM5200: Fix missing null-termination in hostname manipulation code
+
+ Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit 9add9884b1fddc34ca186e00a2f868ccd5d02d87
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Tue Oct 2 19:09:01 2007 +0200
+
+ Fix memtest breakage
+
+ CFG_MEMTEST_START uses weird magic involving gd, which fails to
+ compile. Use hardcoded values instead (we actually know how much RAM
+ we have on board.)
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 738815c0cc44aa329097f868dc1efc49ede9c5ba
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Oct 2 11:44:46 2007 +0200
+
+ ppc4xx: Coding style cleanup
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 87c1833a39e944db66385286fd5e28f9b3fcdd50
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Oct 2 11:44:19 2007 +0200
+
+ ppc4xx: lwmon5: Remove watchdog for now, since not fully tested yet
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2db64784061bfc34f4ba70ef1d2fbe7133b55670
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Mon Oct 1 09:51:50 2007 +0200
+
+ Program EPLD to force full duplex mode for PHY.
+
+ EPLD forces modes of PHY operation. By default full duplex is turned off.
+ This fix turns it on.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 785c13477b77dcd2e6c5128fffcdb4e1943f4818
+Author: Timo Ketola <timo.ketola@exertus.fi>
+Date: Mon Sep 24 14:50:32 2007 +0300
+
+ Bugfix: Use only one PTD for one endpoint
+
+ Original isp116x-hcd code prepared multiple PTDs for longer than 16
+ byte transfers for one endpoint. That is unnecessary because the
+ ISP116x is able to split long data from one PTD into multiple
+ transactions based on the buffer size of the endpoint. It also caused
+ serious problems if the endpoint NAKed some of the transactions. In
+ that case ISP116x wouldn't notice that the other PTDs were for the same
+ endpoint and would try the other PTDs possibly out of order. That would
+ break the whole transfer.
+
+ This patch makes isp116x_submit_job to use one PTD for one transfer.
+
+ Signed-off-by: Timo Ketola <timo.ketola@exertus.fi>
+ Signed-off-by: Markus Klotzbuecher <mk@denx.de>
+
+commit 86ec86c04326c3913178a7679aa910de071da75d
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Thu Sep 27 23:27:47 2007 +0200
+
+ Fix missing DECLARE_GLOBAL_DATA_PTR on CONFIG_LPC2292 in serial
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 3e954beb614b5b190d7f4f4c3b641437a0132e35
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Sep 11 14:12:55 2007 +0200
+
+ ppc4xx: lwmon5: Change GPIO 58 to default to low (watchdog test)
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 1487adbdcf9594bb2eb686325a6f9540dad1b70a
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Wed Sep 26 16:35:54 2007 -0500
+
+ 85xx io out functions need sync after write.
+
+ This fixes the mc146818 rtc_read/write functions for 85xx.
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit 0d38effc6e359e6b1b0c78d66e8bc1a4dc15a2ae
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Tue Sep 25 15:48:05 2007 -0600
+
+ Fpga: fix incorrect test of CFG_FPGA_XILINX macro
+
+ CFG_FPGA_XILINX is a bit value used to test against the value in
+ CONFIG_FPGA. Testing for a value will always return TRUE. I don't
+ think that is the intention in this code.
+
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 853643d8cf2ca80cb2e25c53ad5dc580abafe166
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Sep 24 00:41:30 2007 +0200
+
+ [FIX] change command handling and removing code violation
+
+commit f240356507038e5ce55e8a24cb2607e9eae6d10c
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Sep 24 00:36:06 2007 +0200
+
+ [FIX] change sets of commands
+ because changing of command handling brings
+ compilation problems
+
+commit cb1bc63b75a232571eb69aa2c8aa919321655845
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Sep 24 00:30:42 2007 +0200
+
+ [FIX] Email reparation & Copyright
+ Both codes are written by myself without any
+ support from CTU
+
+commit 0731cbae6c2feab93b244d83fd6a43f5cc9bf852
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Sep 24 00:25:11 2007 +0200
+
+ [PATCH] Change macro name for UartLite
+ because PowerPC 405 can use UartLite as console
+
+commit 1c1100d2fcf46b9d11dcf78d6e5aea75e2e8b716
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Sep 24 00:21:19 2007 +0200
+
+ [PATCH] Add support for design without interrupt controller
+ Polling timer
+
+commit 0731933ec8ec45d02ba89b52df673d526873cdde
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Sep 24 00:19:48 2007 +0200
+
+ [FIX] resolve problem with cpu without barrel shifter
+
+commit db14d77995ce515b728b178b63f82babe60e3d56
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Sep 24 00:18:46 2007 +0200
+
+ [FIX] repair email address
+
+commit 481d4328618804add1f818a6c96296121cd0528e
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Sep 24 00:17:42 2007 +0200
+
+ [FIX] repair MFSL commands
+
+commit b90c045f035c3cc9b5d2edaed6048dfb74e40763
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Sep 24 00:08:37 2007 +0200
+
+ synchronizition with mainline
+
+commit 66dcad3a9a53e0766d90e0084123bd8529522fb0
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu Sep 20 00:04:14 2007 +0200
+
+ v1.3.0-rc2
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
commit 135e19bc2773ebca487e9a8371f67e1ba202313a
Author: Wolfgang Denk <wd@denx.de>
Date: Tue Sep 18 21:36:35 2007 +0200
Signed-off-by: Wolfgang Denk <wd@denx.de>
+commit bd86220f58b99d6896198c385fda132f0c980915
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Sep 18 13:07:54 2007 +0100
+
+ Move coloured led API to status_led.h
+ Improve indentation in drivers/at45.c
+
+commit e80e585b00fbbab7ad1bf71619741f2c5b029ab7
+Author: Eirik Aanonsen <eaa@wprmedical.com>
+Date: Tue Sep 18 08:47:20 2007 +0200
+
+ Update atstk1002 bootargs.
+
+ Updates to atstk1002 U-Boot header file:
+ - Changed bootargs:
+ * Set the bootargs for at1002 to point to the SD-card partition instead
+ * ... of the boot flash.
+ * Removing the rootfstype since that argument are not needed.
+
+ Signed-off-by: Eirik Aanonsen <eaa@wprmedical.com>
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit a4f3aab6dfbed6c29367c688bfb8a47eef62c225
+Author: Eirik Aanonsen <eaa@wprmedical.com>
+Date: Wed Sep 12 13:32:37 2007 +0200
+
+ Add some comments to clocks in atstk1002.h
+
+ This patch applies some clarifying comments to how the different
+ clocks are setup according to atstk1002.h Some of the previous
+ comments where stating wrongful information.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 97213f32416ead885deafea86774e912ffd60ad0
+Author: David Saada <David.Saada@ecitele.com>
+Date: Mon Sep 17 17:04:47 2007 +0200
+
+ Description: Add NEC's PCI OHCI module ID to the USB OHCI driver
+
+ Signed-off-by: David Saada <david.saada@ecitele.com>
+
+commit 30363e98fa470fbecea5e8bc0f1443352754f303
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Sep 17 08:20:47 2007 +0200
+
+ Small whitespace cleanup of OneNAND patch
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit d7e8ce101a4a45ed6ed45739fc2de5f87b13f7f1
+Author: Kyungmin Park <kmpark@infradead.org>
+Date: Mon Sep 10 17:15:14 2007 +0900
+
+ OneNAND support (take #2)
+
+ [PATCH 3/3] OneNAND support (take #2)
+
+ OneNAND support at U-Boot
+
+ Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit 17aa2800457df0c06b41516f46f126712c196219
+Author: Kyungmin Park <kmpark@infradead.org>
+Date: Mon Sep 10 17:14:34 2007 +0900
+
+ OneNAND support (take #2)
+
+ [PATCH 2/3] OneNAND support (take #2)
+
+ OneNAND support at U-Boot
+
+ Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit 916527f4809a7bcd811f1f1daf34af184e31dd8c
+Author: Kyungmin Park <kmpark@infradead.org>
+Date: Mon Sep 10 17:13:49 2007 +0900
+
+ OneNAND support (take #2)
+
+ [PATCH 1/3] OneNAND support (take #2)
+
+ OneNAND support at U-Boot
+
+ Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit b49c90df6e7cfcfb8b862b8bbf8448dff5eed9a5
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sun Sep 16 20:51:57 2007 +0200
+
+ [FIX] remove files form repository
+
commit 67c31036acaaaa992fc346cc89db0909a7e733c4
Author: Wolfgang Denk <wd@denx.de>
Date: Sun Sep 16 17:10:04 2007 +0200
[1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/31805
+commit 991b089d1ce5ad945725e3657a8f106dfa02a38e
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sat Sep 15 00:03:35 2007 +0200
+
+ Synchronize with U-BOOT mainline
+
+commit d7fee32b7e61fe11c64e371cde79faa4768e8350
+Author: Sam Sparks <SSparks@twacs.com>
+Date: Fri Sep 14 11:14:42 2007 -0600
+
+ Update MPC8349ITX*_config to place config.tmp in right place.
+
+ MPC834ITX*_config does not store config.tmp at the correct locatation,
+ causing MPC8349ITXGP to have the wrong TEXT_BASE.
+
+ Signed-off-by: Sam Sparks <SSparks@twacs.com>
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
commit 6e7b7b6ea1b6d04dbe96242eb6a0c1c664c98e8c
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Thu Sep 13 18:21:48 2007 +0200
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
+commit e1f601b572db5de9aa81a0b77c68a86994fe24c4
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Thu Sep 13 16:33:59 2007 +0200
+
+ tqm5200: Restore customary env. variable boot commands for powerpc kernels
+
+ - update default definitions of kernel_addr and fdt_addr env. variables
+ - make arch/powerpc booting the default scenario
+ - update MTD partition layout to match the above
+
+ Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
commit f34024d4a328e6edd906456da98d2c537155c4f7
Author: Wolfgang Denk <wd@denx.de>
Date: Wed Sep 12 00:48:57 2007 +0200
Signed-off-by: Wolfgang Denk <wd@denx.de>
+commit d94c79e47011af5e8dd10ed6163c09b4cfc743cc
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Sep 11 15:35:01 2007 +0100
+
+ Final tidy
+
commit 38ad82da0c1180ecdeb212a8f4245e945bcc546e
Author: Grzegorz Bernacki <gjb@semihalf.com>
Date: Tue Sep 11 15:42:11 2007 +0200
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+commit d45963854eff39d575124d859419bb4953ce2c87
+Author: Michal Simek <monstr@monstr.eu>
+Date: Tue Sep 11 00:37:04 2007 +0200
+
+ [FIX] Microblaze ML401 - repare FLASH handling
+
commit 38c1ef728d19950414a8ab1ccfc53767848fa346
Author: Sean MCGOOGAN <sean.mcgoogan@st.com>
Date: Mon Sep 10 16:55:59 2007 +0100
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+commit 80767a6cead9990d9e77e62be947843c2c72f469
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Wed Sep 5 16:04:41 2007 +0100
+
+ Changed API name to coloured_led.h
+ Removed code using deprecated ifdef CONFIG_BOOTBINFUNC
+ Tidied other cpu/arm920t/start.S code
+
commit 56a9270521baaa00e12639a978302a67f61ef060
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Thu Aug 30 16:18:18 2007 -0500
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+commit 9f5c3d3720e777a572dcdc8af2008b44c7243885
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Sep 4 16:18:38 2007 +0100
+
+ Add coloured led interface for ARM boards.
+ Use it in cpu/arm920t/start.S to indicate U-Boot code has been entered.
+
+commit 7462fe0d5a9d40cde083fb1a3cd73911996b5ecb
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Sep 4 14:49:28 2007 +0100
+
+ Move include/led.h to board/at91rm9200dk
+
+commit 6e4bf9b24e57c15abc6542e685d06380bc64af27
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Sep 4 14:25:51 2007 +0100
+
+ Ran Lindent on drivers/at45.c
+
+commit 557ab89d294f08dd532f21d19861b40093200a33
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Sep 4 14:23:50 2007 +0100
+
+ Rename CONFIG_CMD_MUX to CONFIG_CMD_AT91_SPIMUX
+
commit 81b73dec16fd1227369a191e725e10044a9d56b8
Author: Gary Jennejohn <garyj@denx.de>
Date: Fri Aug 31 15:21:46 2007 +0200
Signed-off-by: Wolfgang Denk <wd@denx.de>
+commit 696dd1307cd8e73a10e9bb3c51731bfd6f837bee
+Author: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
+Date: Thu Aug 30 15:03:05 2007 +0200
+
+ Reduce BOOTDELAY variable to 1 second by default for STK1002
+
+ Signed-off-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit c88b6e1cbf9a8ae2a34fb602f78a1bf4e6692b6a
+Author: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
+Date: Thu Aug 30 15:03:04 2007 +0200
+
+ Remove double quotation marks around MAC address for STK1002
+
+ Signed-off-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
commit ff13ac8c7bbebb238e339592de765c546dba1073
Author: Wolfgang Denk <wd@denx.de>
Date: Thu Aug 30 14:42:15 2007 +0200
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+commit 04625764cc93ce8a61625ac19d7fe2a2ceee8143
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Aug 29 16:31:18 2007 +0200
+
+ ppc4xx: Change lwmon5 default environment to support Linux RTC
+
+ The Linux PCF8563 RTC driver doesn't do autoprobing, so we need
+ to supply the RTC I2C address as bootline parameter. This patch
+ adds support for this rtc probing parameter to the bootargs:
+
+ "rtc-pcf8563.probe=0,0x51"
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
commit 2602a5c40ae37ab965a4e240854fdaffb51328a4
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Wed Aug 29 09:06:05 2007 -0500
Signed-off-by: Heiko Schocher <hs@denx.de>
+commit 2c05fd125744981e5f2828d24e66ccc20a77d25d
+Author: Semih Hazar <semih.hazar@indefia.com>
+Date: Mon Aug 20 19:00:01 2007 +0300
+
+ AVR32: Change prototype of memset
+
+ Signed-off-by: Semih Hazar <semih.hazar@indefia.com>
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
commit 9c02defc29b57945b600714cf61ddfd02b02fb14
Author: Yuri Tikhonov <yur@emcraft.com>
Date: Sat Aug 25 05:07:16 2007 +0200
Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
+commit 78cff50edba6b1508eb15c2f53ce966ac891eb9e
+Author: Michal Simek <monstr@monstr.eu>
+Date: Thu Aug 16 10:46:28 2007 +0200
+
+ [FIX] Changes for bios_emulator code for others architecture
+
+commit 6e0e2253f039344f8ebd2787285fdba90e6714e8
+Author: Michal Simek <monstr@monstr.eu>
+Date: Thu Aug 16 10:45:09 2007 +0200
+
+ [FIX] Remove unused include file
+
commit 9de469bd960cc1870bb40d6672ed42726b8b50d7
Author: Stefan Roese <sr@denx.de>
Date: Thu Aug 16 10:18:33 2007 +0200
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+commit 5b4de9309d7a03aa1db2e5391ab696363391f460
+Author: Michal Simek <monstr@monstr.eu>
+Date: Wed Aug 15 21:15:05 2007 +0200
+
+ [FIX] Resolve problem with warnings
+ microblaze toolchain don't support PRAGMA PACK.
+
+commit d1ed28cf36ab6b1d4c479809de7252bf53d2f2d4
+Author: Michal Simek <monstr@monstr.eu>
+Date: Wed Aug 15 21:05:07 2007 +0200
+
+ [FIX] Correction command setting for Microblaze boards
+
+commit 7aa63d8cd30ab20ac2fd1ab86e60471de8b1f1e5
+Author: Michal Simek <monstr@monstr.eu>
+Date: Wed Aug 15 21:03:41 2007 +0200
+
+ [FIX] Correction command definition
+
commit 30b52df9e906bf0e465916c2c6bb5192b438e0b8
Author: Jon Loeliger <jdl@freescale.com>
Date: Wed Aug 15 11:55:35 2007 -0500
Signed-off-by: Wolfgang Denk <wd@denx.de>
+commit 706714d97a0d08d59eda4de2268c39f504688329
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Aug 6 23:41:53 2007 +0200
+
+ [FIX] remove cute code
+
+commit f500d9fdeb576288656dac427052ad2c5ca0ad1a
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Aug 6 23:35:26 2007 +0200
+
+ [FIX] Fix romfs code
+
+commit ab4b956d3143f8f8174089053f5dfabbb04762b0
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Aug 6 23:31:49 2007 +0200
+
+ [FIX] Coding style cleanup - Wolfgang's suggestions
+
commit 6c33c78557ca6f8da68c01ce33e278695197d3f4
Author: Wolfgang Denk <wd@denx.de>
Date: Mon Aug 6 23:21:05 2007 +0200
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
+commit a274ca4f6d68830e7c916f897561cff8c4101c38
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sun Aug 5 22:33:05 2007 +0200
+
+ [FIX] Coding style cleanup
+
+commit af8377d4eb3a0ac5a831830d5ce63fbf65fecb7f
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sun Aug 5 16:13:31 2007 +0200
+
+ [FIX] Xilinx Uartlite driver
+ Because PPC405 can use UARTLITE serial interface and
+ Microblaze can use Uart16550 serial interface not only Uartlite.
+
+commit 98889edd50aadf862071eb5664747ad0d568a20e
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sun Aug 5 15:54:53 2007 +0200
+
+ [FIX] Change configuration for XUPV2P Microblaze board
+
+commit 537091b4eed9302865d03fef3f7212b4fe5cf28f
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sun Aug 5 15:53:50 2007 +0200
+
+ [PATCH] Added support for Xilinx Emac community driver
+
commit 86b116b1b1e165ca4840daefed36d2e3b8460173
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Fri Aug 3 12:08:16 2007 +0200
Signed-off-by: Stefan Roese <sr@denx.de>
+commit 0c0a9cda1bde37106520476ed486bd67eb8d30ae
+Author: Michal Simek <monstr@monstr.eu>
+Date: Mon Jul 16 00:31:07 2007 +0200
+
+ [PATCH] Support for Xilinx EmacLite controller
+
commit 3a6cab844cf74f76639d795e0be8717e02c86af7
Author: Wolfgang Denk <wd@denx.de>
Date: Sat Jul 14 22:51:02 2007 +0200
Signed-off-by: Wolfgang Denk <wd@denx.de>
+commit 5280f352c8da33b1d7fbf448768717d9e16ff9a1
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sat Jul 14 13:11:28 2007 +0200
+
+ [FIX] support for simply measuring time
+
+commit 91bb4ca665d2e0cf7f60c4b5b370990250ec0c43
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sat Jul 14 12:41:23 2007 +0200
+
+ [FS] Added support for ROMFS
+
commit 011595307731a7a67a7445d107c279d031e8ab97
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Sat Jul 14 01:06:58 2007 +0200
[PCS440EP] - fix compile error, if BUILD_DIR is used
+commit 5a2f1098d81ad58b309e5e558d0492643166a799
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sat Jul 14 00:18:48 2007 +0200
+
+ [PATCH] Support time without timer
+
+commit a476ca2ac2217ddd05a2bf0c514075814b10a3c0
+Author: Michal Simek <monstr@monstr.eu>
+Date: Fri Jul 13 21:43:55 2007 +0200
+
+ [PATCH] Remove problem with disabled BARREL SHIFTER
+
+commit 55e26ad62107d2f14f757de3ae0b14b9aa7aed94
+Author: Michal Simek <monstr@monstr.eu>
+Date: Fri Jul 13 21:41:44 2007 +0200
+
+ [FIX] correct help for rspr
+
commit fad63407154f46246ce80d53a9c669a44362ac67
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Fri Jul 13 09:54:17 2007 +0200
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+commit 093172f08d6afb3f34d8a2f26ee0ee874261cf27
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sun Jun 17 19:04:11 2007 +0200
+
+ [fix] email reparation
+
+commit 3666afffe7baf859c6ae0ce2bebbc8ab7e512ddc
+Author: Michal Simek <monstr@monstr.eu>
+Date: Sun Jun 17 19:03:21 2007 +0200
+
+ [FIX] fix microblaze file permitission
+
commit e73846b7cf1e29ae635bf9bb5570269663df2ee5
Author: Stefan Roese <sr@denx.de>
Date: Fri Jun 15 11:33:41 2007 +0200
MPC8313ERDB_66 \
MPC8323ERDB \
MPC832XEMDS \
+ MPC832XEMDS_ATM \
MPC8349EMDS \
MPC8349ITX \
MPC8349ITXGP \
MPC8360EMDS \
+ MPC8360EMDS_ATM \
sbc8349 \
TQM834x \
"
LIST_au1xx0_el=" \
dbau1550_el \
+ pb1000 \
"
LIST_mips_el=" \
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
VERSION = 1
PATCHLEVEL = 3
SUBLEVEL = 0
-EXTRAVERSION = -rc2
+EXTRAVERSION =
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
VERSION_FILE = $(obj)include/version_autogenerated.h
LIBS += drivers/bios_emulator/libatibiosemu.a
LIBS += drivers/nand/libnand.a
LIBS += drivers/nand_legacy/libnand_legacy.a
+LIBS += drivers/onenand/libonenand.a
LIBS += drivers/net/libnet.a
ifeq ($(CPU),mpc83xx)
LIBS += drivers/qe/qe.a
cpci5200_config: unconfig
@$(MKCONFIG) -a cpci5200 ppc mpc5xxx cpci5200 esd
-hmi1001_config: unconfig
+hmi1001_config: unconfig
@$(MKCONFIG) hmi1001 ppc mpc5xxx hmi1001
Lite5200_config \
}
@$(MKCONFIG) -a IceCube ppc mpc5xxx icecube
-jupiter_config: unconfig
+jupiter_config: unconfig
@$(MKCONFIG) jupiter ppc mpc5xxx jupiter
v38b_config: unconfig
{ echo "TEXT_BASE = 0xFFF00000" >$(obj)board/tqm5200/config.tmp ; \
}
@$(MKCONFIG) -n $@ -a TQM5200 ppc mpc5xxx tqm5200
-uc101_config: unconfig
+uc101_config: unconfig
@$(MKCONFIG) uc101 ppc mpc5xxx uc101
-motionpro_config: unconfig
+motionpro_config: unconfig
@$(MKCONFIG) motionpro ppc mpc5xxx motionpro
RPXlite_DW_NVRAM_64_config \
RPXlite_DW_NVRAM_LCD_config \
RPXlite_DW_NVRAM_64_LCD_config \
-RPXlite_DW_config: unconfig
+RPXlite_DW_config: unconfig
@mkdir -p $(obj)include
@ >$(obj)include/config.h
@[ -z "$(findstring _64,$@)" ] || \
>include/config.h ; \
if [ "$${FLASH}" == "INTEL" ] ; then \
echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
+ echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
+ cp $(obj)board/freescale/m54455evb/u-boot.int $(obj)board/freescale/m54455evb/u-boot.lds ; \
echo "... with INTEL boot..." ; \
else \
echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
+ echo "TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
+ cp $(obj)board/freescale/m54455evb/u-boot.atm $(obj)board/freescale/m54455evb/u-boot.lds ; \
echo "... with ATMEL boot..." ; \
fi; \
echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
MPC832XEMDS_config \
MPC832XEMDS_HOST_33_config \
MPC832XEMDS_HOST_66_config \
-MPC832XEMDS_SLAVE_config: unconfig
+MPC832XEMDS_SLAVE_config \
+MPC832XEMDS_ATM_config: unconfig
@mkdir -p $(obj)include
@echo "" >$(obj)include/config.h ; \
if [ "$(findstring _HOST_,$@)" ] ; then \
if [ "$(findstring _33_,$@)" ] ; then \
echo -n "...33M ..." ; \
echo "#define PCI_33M" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _66_,$@)" ] ; then \
echo -n "...66M..." ; \
echo "#define PCI_66M" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
+ fi ; \
+ if [ "$(findstring _ATM_,$@)" ] ; then \
+ echo -n "...ATM..." ; \
+ echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \
fi ;
@$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds freescale
MPC8360EMDS_config \
MPC8360EMDS_HOST_33_config \
MPC8360EMDS_HOST_66_config \
-MPC8360EMDS_SLAVE_config: unconfig
+MPC8360EMDS_SLAVE_config \
+MPC8360EMDS_ATM_config: unconfig
@mkdir -p $(obj)include
@echo "" >$(obj)include/config.h ; \
if [ "$(findstring _HOST_,$@)" ] ; then \
if [ "$(findstring _33_,$@)" ] ; then \
echo -n "...33M ..." ; \
echo "#define PCI_33M" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _66_,$@)" ] ; then \
echo -n "...66M..." ; \
echo "#define PCI_66M" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
+ fi ; \
+ if [ "$(findstring _ATM_,$@)" ] ; then \
+ echo -n "...ATM..." ; \
+ echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \
fi ;
@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale
BAB7xx_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx bab7xx eltec
-CPCI750_config: unconfig
+CPCI750_config: unconfig
@$(MKCONFIG) CPCI750 ppc 74xx_7xx cpci750 esd
-DB64360_config: unconfig
+DB64360_config: unconfig
@$(MKCONFIG) DB64360 ppc 74xx_7xx db64360 Marvell
-DB64460_config: unconfig
+DB64460_config: unconfig
@$(MKCONFIG) DB64460 ppc 74xx_7xx db64460 Marvell
ELPPC_config: unconfig
to be a good choice since it makes it far enough from the
start of the data area as well as from the stack pointer.
-Please note that the environment is read-only as long as the monitor
+Please note that the environment is read-only until the monitor
has been relocated to RAM and a RAM copy of the environment has been
created; also, when using EEPROM you will have to use getenv_r()
until then to read environment variables.
# MA 02111-1307 USA
#
-PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
+PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -D__BLACKFIN__
{
cpu/mpc512x/start.o (.text)
*(.text)
+ *(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
************************************************************************/
int board_early_init_f(void)
{
- volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
-
mtebc( pb0ap, 0x03800000 ); /* set chip selects */
mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
mtebc( pb1ap, 0x03800000 );
mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
mtdcr( uic0sr, 0xffffffff );
- x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */
-
return 0;
}
int misc_init_r(void)
{
volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
- x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */
+
+ /* set modes of operation */
+ x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
+ EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
+ /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
+ x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
+
+ /* put Ethernet+PHY in reset */
+ x->ethuart &= ~EPLD2_RESET_ETH_N;
+ udelay(10000);
+ /* take Ethernet+PHY out of reset */
+ x->ethuart |= EPLD2_RESET_ETH_N;
return 0;
}
#include <common.h>
#include <command.h>
#include <i2c.h>
+#include <asm/io.h>
/*
* There are 2 versions of production Sequoia & Rainier platforms.
* All Sequoias & Rainiers select from two possible EEPROMs in Boot
* Config F. One for 33MHz PCI, one for 66MHz PCI. The following
* values are for the 33MHz PCI configuration. Byte 5 (0 base) is
- * the only value affected for a 66MHz PCI and simply needs a +0x10.
+ * the only value affected for a 33MHz PCI and simply needs a | 0x08.
*/
#define NAND_COMPATIBLE 0x01
"CPU: 416 PLB: 166 OPB: 83 EBC: 55",
"CPU: 500 PLB: 166 OPB: 83 EBC: 55",
"CPU: 533 PLB: 133 OPB: 66 EBC: 66",
+ "CPU: 667 PLB: 133 OPB: 66 EBC: 66",
"CPU: 667 PLB: 166 OPB: 83 EBC: 55",
NULL
};
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
+ (NOR_COMPATIBLE),
+ 0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30, 0x40,
+ 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ },
+ {
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
/* check CPLD register +5 for PCI 66MHz flag */
- if (in8(CFG_BCSR_BASE + 5) & 0x01)
- buf[5] += 0x10;
+ if ((in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN) == 0)
+ /*
+ * PLB-to-PCI divisor = 3 for 33MHz sync PCI
+ * instead of 2 for 66MHz systems
+ */
+ buf[5] |= 0x08;
if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
/*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <ppc440.h>
DECLARE_GLOBAL_DATA_PTR;
printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
#endif
- rev = in8(CFG_BCSR_BASE + 0);
- val = in8(CFG_BCSR_BASE + 5) & 0x01;
+ rev = in_8((void *)(CFG_BCSR_BASE + 0));
+ val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
if (s != NULL) {
/*
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <spd_sdram.h>
DECLARE_GLOBAL_DATA_PTR;
printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
#endif
- rev = *(u8 *)(CFG_CPLD + 0);
- val = *(u8 *)(CFG_CPLD + 5) & 0x01;
+ rev = in_8((void *)(CFG_BCSR_BASE + 0));
+ val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
if (s != NULL) {
}
-void LED_init (void)
+void coloured_LED_init (void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
AT91PS_PMC PMC = AT91C_BASE_PMC;
unsigned long addr;
unsigned int i;
- gd->bd->bi_flashstart = CFG_FLASH_BASE;
- gd->bd->bi_flashsize = CFG_FLASH_SIZE;
- gd->bd->bi_flashoffset = _edata - _text;
-
flash_info[0].size = CFG_FLASH_SIZE;
flash_info[0].sector_count = 135;
map = ft_get_prop(blob, "/" OF_SOC "/pci@8000/interrupt-map", &len);
- len /= sizeof(u32);
+ if (!map)
+ map = ft_get_prop(blob, "/" OF_PCI "/interrupt-map", &len);
- slot = get_pci_slot();
+ if (map) {
+ len /= sizeof(u32);
- for (i=0;i<len;i+=7) {
- /* We rotate the interrupt pins so that the mapping
- * changes depending on the slot the carrier card is in.
- */
- map[3] = ((map[3] + slot - 2) % 4) + 1;
+ slot = get_pci_slot();
- map+=7;
+ for (i=0;i<len;i+=7) {
+ /* We rotate the interrupt pins so that the mapping
+ * changes depending on the slot the carrier card is in.
+ */
+ map[3] = ((map[3] + slot - 2) % 4) + 1;
+
+ map+=7;
+ }
+ } else {
+ printf("*** Warning - No PCI node found\n");
}
}
#endif
"operational\n");
/* set the hostname appropriate to the module we're running on */
+ hostname[0] = 0x00;
compose_hostname(hw_id, hostname);
setenv("hostname", hostname);
{
*(.text)
common/environment.o(.text)
+ *(.fixup)
*(.got1)
}
_etext = .;
#include <command.h>
#include <asm/au1x00.h>
#include <asm/mipsregs.h>
+#include <asm/io.h>
long int initdram(int board_type)
{
default:
printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
}
+
+ set_io_port_base(0);
+
#ifdef CONFIG_IDE_PCMCIA
/* Enable 3.3 V on slot 0 ( VCC )
No 5V */
. = ALIGN(4);
.data : { *(.data) }
- . = ALIGN(4);
- .sdata : { *(.sdata) }
-
- _gp = ALIGN(16);
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
- __got_start = .;
- .got : { *(.got) }
- __got_end = .;
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
.sdata : { *(.sdata) }
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_cmd : {
+ __u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ __u_boot_cmd_end = .;
+ }
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
}
+#ifndef CFG_PIXIS_VBOOT_MASK
+#define CFG_PIXIS_VBOOT_MASK 0x40
+#endif
void set_altbank(void)
{
u8 tmp;
tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
- tmp ^= 0x40;
+ tmp ^= CFG_PIXIS_VBOOT_MASK;
out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
}
printf("QOC3 ATM card on PMC0\n");
#elif defined(CONFIG_MPC832XEMDS)
- val = 0;
- i2c_write(0x26, 0x7, 1, &val, 1);
- val = 0xf7;
- i2c_write(0x26, 0x3, 1, &val, 1);
-
- val = 0;
- i2c_write(0x21, 0x6, 1, &val, 1);
- i2c_write(0x21, 0x7, 1, &val, 1);
-
- val = 0xdf;
- i2c_write(0x21, 0x2, 1, &val, 1);
- val = 0xef;
- i2c_write(0x21, 0x3, 1, &val, 1);
+ val8 = 0;
+ i2c_write(0x26, 0x7, 1, &val8, 1);
+ val8 = 0xf7;
+ i2c_write(0x26, 0x3, 1, &val8, 1);
+
+ val8 = 0;
+ i2c_write(0x21, 0x6, 1, &val8, 1);
+ i2c_write(0x21, 0x7, 1, &val8, 1);
+
+ val8 = 0xdf;
+ i2c_write(0x21, 0x2, 1, &val8, 1);
+ val8 = 0xef;
+ i2c_write(0x21, 0x3, 1, &val8, 1);
eieio();
# MA 02111-1307 USA
#
-TEXT_BASE = 0
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mcf5445x/start.o (.text)
+ lib_m68k/traps.o (.text)
+ lib_m68k/interrupts.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/zlib.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ _sbss = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mcf5445x/start.o (.text)
+ lib_m68k/traps.o (.text)
+ lib_m68k/interrupts.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/zlib.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ _sbss = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
*/
- in_be32(CFG_PCIE3_MEM_BASE);
+ in_be32((u32 *)CFG_PCIE3_MEM_BASE);
} else {
printf (" PCIE3: disabled\n");
}
#include <asm/au1x00.h>
#include <asm/addrspace.h>
#include <asm/mipsregs.h>
+#include <asm/io.h>
#include <watchdog.h>
#include "ee_access.h"
static int wdi_status = 0;
-unsigned long mips_io_port_base = 0;
-
#define SDRAM_SIZE ((64*1024*1024)-(12*4096))
default:
printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
}
+
+ set_io_port_base(0);
+
#ifdef CONFIG_IDE_PCMCIA
/* PCMCIA is on a 36 bit physical address.
We need to map it into a 32 bit addresses */
(Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) {
printf ("*** ethernet addr invalid, using default ***\n");
} else {
- setenv ("ethaddr", Rx);
+ setenv ("ethaddr", (char *)Rx);
}
return (0);
}
j clearmem
nop
+#if 0
.globl memtest
+#endif
memtest:
/* Fill memory with address */
li t0, 0x80000000
bne t1, zero, mt1
nop
nop
+#if 0
.globl clearmem
+#endif
clearmem:
/* Clear memory */
li t0, 0x80000000
. = ALIGN(4);
.data : { *(.data) }
- . = ALIGN(4);
- .sdata : { *(.sdata) }
-
- _gp = ALIGN(16);
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
- __got_start = .;
- .got : { *(.got) }
- __got_end = .;
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
.sdata : { *(.sdata) }
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_cmd : {
+ __u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ __u_boot_cmd_end = .;
+ }
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
common/environment.o(.text)
*(.text)
+ *(.fixup)
*(.got1)
}
_etext = .;
#include <ioports.h>
#include <mpc8260.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <libfdt_env.h>
+#include <fdt_support.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
/*
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 COL */
- /* PA30 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
- /* PA29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
- /* PA28 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
- /* PA27 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
- /* PA26 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
+ /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
+ /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
+ /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
+ /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
+ /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
+ /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
/* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */
#if defined(CONFIG_SOFT_I2C)
/* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */
/* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
#endif
/* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */
- /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
- /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
- /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
- /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
- /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
- /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */
- /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
- /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
+ /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
+ /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
+ /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
+ /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
+ /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
+ /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */
+ /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
+ /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
/* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */
/* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */
/* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
+ /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
/* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
/* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* MII_MDIO */
+ /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* MII_MDIO */
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
* mapped by the controller. That means, that the initial mapping has
* to be (at least) twice as large as the maximum expected size.
*/
- maxsize = (1 + (~orx | 0x7fff)) / 2;
+ maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
sdmr_ptr = &memctl->memc_psdmr;
orx_ptr = &memctl->memc_or2;
printf ("%4lu MB\n", totlen >>20);
}
-#endif
+#endif /* CFG_CMD_NAND */
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+/*
+ * update "memory" property in the blob
+ */
+void ft_blob_update(void *blob, bd_t *bd)
+{
+ int ret, nodeoffset = 0;
+ ulong memory_data[2] = {0};
+
+ memory_data[0] = cpu_to_be32(bd->bi_memstart);
+ memory_data[1] = cpu_to_be32(bd->bi_memsize);
+
+ nodeoffset = fdt_find_node_by_path (blob, "/memory");
+ if (nodeoffset >= 0) {
+ ret = fdt_setprop(blob, nodeoffset, "reg", memory_data,
+ sizeof(memory_data));
+ if (ret < 0)
+ printf("ft_blob_update): cannot set /memory/reg "
+ "property err:%s\n", fdt_strerror(ret));
+ }
+ else {
+ /* memory node is required in dts */
+ printf("ft_blob_update(): cannot find /memory node "
+ "err:%s\n", fdt_strerror(nodeoffset));
+ }
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup( blob, bd);
+ ft_blob_update(blob, bd);
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
#include <command.h>
#include <asm/addrspace.h>
#include <asm/inca-ip.h>
-
+#include <asm/io.h>
extern uint incaip_get_cpuclk(void);
int checkboard (void)
{
-
unsigned long chipid = *INCA_IP_WDT_CHIPID;
int part_num;
printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000);
+ set_io_port_base(0);
+
return 0;
}
. = ALIGN(4);
.data : { *(.data) }
- . = ALIGN(4);
- .sdata : { *(.sdata) }
-
- _gp = ALIGN(16);
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
- __got_start = .;
- .got : { *(.got) }
- __got_end = .;
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
.sdata : { *(.sdata) }
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_cmd : {
+ __u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ __u_boot_cmd_end = .;
+ }
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
int misc_init_r(void)
{
- uchar *str;
+ char *str;
/* determine if the software update key is pressed during startup */
if (GPLR0 & 0x00000800) {
gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
+ /*
+ * Reset PHY's:
+ * The PHY's need a 2nd reset pulse, since the MDIO address is latched
+ * upon reset, and with the first reset upon powerup, the addresses are
+ * not latched reliable, since the IRQ line is multiplexed with an
+ * MDIO address. A 2nd reset at this time will make sure, that the
+ * correct address is latched.
+ */
+ gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
+ gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
+ udelay(1000);
+ gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
+ gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
+ udelay(1000);
+ gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
+ gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
+
return 0;
}
out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
/*
- * Reset PHY's
- */
- gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
- gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
- udelay(100);
- gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
- gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
-
- /*
* Init display controller
*/
/* Setup dot clock (internal PLL, division rate 1/16) */
/* Write to the SDRAM Mode Register */
*(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
}
+ return dramsize;
}
#ifndef CFG_RAMBOOT
ulong test1, test2;
+ /* According to AN3221 (MPC5200B SDRAM Initialization and
+ * Configuration), the SDelay register must be written a value of
+ * 0x00000004 as the first step of the SDRAM contorller configuration.
+ */
+ *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+
/* configure SDRAM start/end for detection */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
+ *(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
* Copy memory to flash
*/
-volatile static int write_hword (flash_info_t * info, ulong dest, ushort data)
+static int write_hword (flash_info_t * info, ulong dest, ushort data)
{
vu_short *addr = (vu_short *) dest;
ushort result;
int checkboard(void)
{
- unsigned char s[50];
+ char s[50];
int i;
backup_t *b = (backup_t *) s;
************************************************************************/
void print_vcma9_info(void)
{
- unsigned char s[50];
+ char s[50];
int i;
if ((i = getenv_r("serial#", s, 32)) < 0) {
} /*__attribute__((__packed__))*/ VCMA9_PLD;
#define VCMA9_PLD_BASE 0x2C000100
-static inline VCMA9_PLD * const VCMA9_GetBase_PLD(void)
+static inline VCMA9_PLD * VCMA9_GetBase_PLD(void)
{
return (VCMA9_PLD * const)VCMA9_PLD_BASE;
}
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o
-SOBJS = memsetup.o
+SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
.set noreorder
.set mips32
- .globl memsetup
-memsetup:
+ .globl lowlevel_init
+lowlevel_init:
/*
* Step 1) Establish CPU endian mode.
* NOTE: A fair amount of code is necessary on the Pb1000 to
#include <command.h>
#include <asm/au1x00.h>
#include <asm/mipsregs.h>
+#include <asm/io.h>
long int initdram(int board_type)
{
int checkboard (void)
{
+#if defined(CONFIG_IDE_PCMCIA) && 0
u16 status;
+#endif
/* volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); */
volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
u32 proc_id;
default:
printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
}
+
+ set_io_port_base(0);
+
#if defined(CONFIG_IDE_PCMCIA) && 0
/* Enable 3.3 V on slot 0 ( VCC )
No 5V */
. = ALIGN(4);
.data : { *(.data) }
- . = ALIGN(4);
- .sdata : { *(.sdata) }
-
- _gp = ALIGN(16);
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
- __got_start = .;
- .got : { *(.got) }
- __got_end = .;
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
.sdata : { *(.sdata) }
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_cmd : {
+ __u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ __u_boot_cmd_end = .;
+ }
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
int i;
uchar *boottype;
uchar *bootletter;
- uchar *fmt;
+ char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";
int i;
uchar *boottype;
uchar *bootletter;
- uchar *fmt;
+ char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";
#include <asm/inca-ip.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
+#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
printf("CPU Speed %d MHz\n", CPU_CLOCK_RATE/1000000);
+ set_io_port_base(0);
+
return 0;
}
. = ALIGN(4);
.data : { *(.data) }
- . = ALIGN(4);
- .sdata : { *(.sdata) }
-
- _gp = ALIGN(16);
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
- __got_start = .;
- .got : { *(.got) }
- __got_end = .;
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
.sdata : { *(.sdata) }
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_cmd : {
+ __u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ __u_boot_cmd_end = .;
+ }
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
LIB = $(obj)lib$(BOARD).a
COBJS := pxa_idp.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
#TEXT_BASE = 0xa1700000
-TEXT_BASE = 0xa3000000
+TEXT_BASE = 0xa3080000
#TEXT_BASE = 0
*
* NOTE: I haven't clean this up considerably, just enough to get it
* running. See hal_platform_setup.h for the source. See
- * board/cradle/memsetup.S for another PXA250 setup that is
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
* much cleaner.
*
* See file CREDITS for list of people who contributed to this
/*
* Memory setup
*/
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
mov r10, lr
/* Save SDRAM size */
ldr r1, =DRAM_SIZE
- str r8, [r1]
+ str r8, [r1]
/* Interrupt init: Mask all interrupts */
ldr r0, =ICMR /* enable no sources */
bl blink
#endif
-endmemsetup:
+endlowlevel_init:
mov pc, r10
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
- if (i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) {
+ if (! i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) {
timedate->tm_sec = BCD_TO_BIN (buffer[0]);
timedate->tm_min = BCD_TO_BIN (buffer[1]);
timedate->tm_hour = BCD_TO_BIN (buffer[2]);
unsigned char buffer[8];
/*int rc;*/
- if (i2c_read (address, 0, 1, buffer, 1)) {
+ if (! i2c_read (address, 0, 1, buffer, 1)) {
return (int) buffer[0];
} else {
/*printf("i2c error %02x\n", rc); */
{
cpu/mpc8260/start.o (.text)
*(.text)
+ *(.fixup)
*(.got1)
/*. = env_offset; */
}
* Copy memory to flash
*/
-volatile static int write_hword (flash_info_t * info, ulong dest, ushort data)
+static int write_hword (flash_info_t * info, ulong dest, ushort data)
{
vu_short *addr = (vu_short *) dest;
ushort result;
* Copy memory to flash
*/
-volatile static int write_hword (flash_info_t * info, ulong dest, ushort data)
+static int write_hword (flash_info_t * info, ulong dest, ushort data)
{
vu_short *addr = (vu_short *) dest;
ushort result;
#include <command.h>
#include <asm/addrspace.h>
#include <asm/inca-ip.h>
+#include <asm/io.h>
#include <pci.h>
-unsigned long mips_io_port_base = 0;
-
#if defined(CONFIG_PCI)
static struct pci_controller hose;
}
#endif
-
long int initdram(int board_type)
{
return get_ram_size (CFG_SDRAM_BASE, 0x8000000);
}
-
int checkboard (void)
{
printf("Board: TANBAC TB0229 ");
printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000);
+ set_io_port_base(0);
+
return 0;
}
. = ALIGN(4);
.data : { *(.data) }
- . = ALIGN(4);
- .sdata : { *(.sdata) }
-
- _gp = ALIGN(16);
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
- __got_start = .;
- .got : { *(.got) }
- __got_end = .;
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
.sdata : { *(.sdata) }
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_cmd : {
+ __u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ __u_boot_cmd_end = .;
+ }
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
gpt->gpt6.emsr |= 0x00000024;
gpt->gpt7.emsr |= 0x00000024;
-
+#ifndef CONFIG_TQM5200S
/* enable SM501 GPIO control (in both power modes) */
*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
POWER_MODE_GATE_GPIO_PWM_I2C;
/* configure SM501 gpio pins 48-51 as output */
*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= (0xF << 16);
+#endif /* !CONFIG_TQM5200S */
}
/*
gpt->gpt7.emsr &= ~(1 << 4);
}
break;
-
+#ifndef CONFIG_TQM5200S
case 24:
if (strcmp (argv[3], "on") == 0) {
*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
~(0x1 << 19);
}
break;
-
+#endif /* !CONFIG_TQM5200S */
default:
printf ("%s: invalid led number %s\n", __FUNCTION__, argv[2]);
return 1;
return error_status;
}
-#ifndef CONFIG_FO300
+#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S)
static void sm501_backlight (unsigned int state)
{
if (state == BL_ON) {
*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
~((1 << 26) | (1 << 27));
}
-#endif
+#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */
int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
else
printf ("Error\n");
return rcode;
-#ifndef CONFIG_FO300
+#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S)
} else if (strncmp (argv[1], "backlight", 4) == 0) {
if (strncmp (argv[2], "on", 2) == 0) {
sm501_backlight (BL_ON);
sm501_backlight (BL_OFF);
return 0;
}
-#endif
+#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */
}
break;
" - loopback plug for X83 required\n"
"fkt rs232 number\n"
" - loopback plug(s) for X2 required\n"
+#ifndef CONFIG_TQM5200S
"fkt backlight on/off\n"
" - switch backlight on or off\n"
+#endif /* !CONFIG_TQM5200S */
);
#elif defined(CONFIG_FO300)
U_BOOT_CMD(
}
#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
-#ifdef CONFIG_PS2MULT
#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
+ extern int usb_cpu_init(void);
+
+#ifdef CONFIG_PS2MULT
ps2mult_early_init();
+#endif /* CONFIG_PS2MULT */
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
+ /* Low level USB init, required for proper kernel operation */
+ usb_cpu_init();
+#endif
+
return (0);
}
#endif
-#endif /* CONFIG_PS2MULT */
#ifdef CONFIG_FO300
int silent_boot (void)
__asm__ volatile ("sync");
}
+#ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */
/*
* Check for Grafic Controller
*/
disable_ctrlc(1);
}
#endif
+#endif /* !CONFIG_TQM5200S */
return 0;
}
udelay (10000);
#ifdef CONFIG_CAN_DRIVER
+ /* UPM initialization for CAN @ CLKOUT <= 66 MHz */
+
/* Initialize OR3 / BR3 */
memctl->memc_or3 = CFG_OR3_CAN;
memctl->memc_br3 = CFG_BR3_CAN;
memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
/* Initialize UPMB for CAN: single read */
- memctl->memc_mdr = 0xFFFFC004;
+ memctl->memc_mdr = 0xFFFFCC04;
memctl->memc_mcr = 0x0100 | UPMB;
memctl->memc_mdr = 0x0FFFD004;
memctl->memc_mdr = 0x3FFFC004;
memctl->memc_mcr = 0x0103 | UPMB;
- memctl->memc_mdr = 0xFFFFDC05;
+ memctl->memc_mdr = 0xFFFFDC07;
memctl->memc_mcr = 0x0104 | UPMB;
/* Initialize UPMB for CAN: single write */
- memctl->memc_mdr = 0xFFFCC004;
+ memctl->memc_mdr = 0xFFFCCC04;
memctl->memc_mcr = 0x0118 | UPMB;
- memctl->memc_mdr = 0xCFFCD004;
+ memctl->memc_mdr = 0xCFFCDC04;
memctl->memc_mcr = 0x0119 | UPMB;
- memctl->memc_mdr = 0x0FFCC000;
+ memctl->memc_mdr = 0x3FFCC000;
memctl->memc_mcr = 0x011A | UPMB;
- memctl->memc_mdr = 0x7FFCC004;
+ memctl->memc_mdr = 0xFFFCC004;
memctl->memc_mcr = 0x011B | UPMB;
- memctl->memc_mdr = 0xFFFDCC05;
+ memctl->memc_mdr = 0xFFFDC405;
memctl->memc_mcr = 0x011C | UPMB;
#endif /* CONFIG_CAN_DRIVER */
#if ( WEP_FLASH_BUS_WIDTH == 1 )
# define FLASH_BUS vu_char
+# define FLASH_BUS_RET u_char
# if ( WEP_FLASH_INTERLEAVE == 1 )
# define FLASH_CMD( x ) x
# else
#elif ( WEP_FLASH_BUS_WIDTH == 2 )
# define FLASH_BUS vu_short
+# define FLASH_BUS_RET u_short
# if ( WEP_FLASH_INTERLEAVE == 1 )
# define FLASH_CMD( x ) x
# elif ( WEP_FLASH_INTERLEAVE == 2 )
#elif ( WEP_FLASH_BUS_WIDTH == 4 )
# define FLASH_BUS vu_long
+# define FLASH_BUS_RET u_long
# if ( WEP_FLASH_INTERLEAVE == 1 )
# define FLASH_CMD( x ) x
# elif ( WEP_FLASH_INTERLEAVE == 2 )
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
-static FLASH_BUS flash_status_reg (void)
+static FLASH_BUS_RET flash_status_reg (void)
{
FLASH_BUS *addr = (FLASH_BUS *) 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
switch (i) {
case 0:
- flash_get_size ((long *) PHYS_FLASH_1, &flash_info[i]);
+ flash_get_size ((vu_long *) PHYS_FLASH_1, &flash_info[i]);
flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
break;
case 1:
- flash_get_size ((long *) PHYS_FLASH_2, &flash_info[i]);
+ flash_get_size ((vu_long *) PHYS_FLASH_2, &flash_info[i]);
flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
break;
default:
AOBJS =
-COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \
- cmd_bdinfo.o cmd_bedbug.o cmd_bmp.o cmd_boot.o cmd_bootm.o \
- cmd_cache.o cmd_console.o \
- cmd_date.o cmd_dcr.o cmd_diag.o cmd_display.o cmd_doc.o cmd_dtt.o \
- cmd_eeprom.o cmd_elf.o cmd_ext2.o \
- cmd_fat.o cmd_fdc.o cmd_fdt.o cmd_fdos.o cmd_flash.o cmd_fpga.o \
- cmd_i2c.o cmd_ide.o cmd_immap.o cmd_itest.o cmd_jffs2.o \
- cmd_load.o cmd_log.o \
- cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
- cmd_nand.o cmd_net.o cmd_nvedit.o \
- cmd_pci.o cmd_pcmcia.o cmd_portio.o \
- cmd_reginfo.o cmd_reiser.o cmd_sata.o cmd_scsi.o cmd_spi.o \
- cmd_universe.o cmd_usb.o cmd_vfd.o \
- command.o console.o cyclon2.o devices.o dlmalloc.o docecc.o \
- environment.o env_common.o \
- env_nand.o env_dataflash.o env_flash.o env_eeprom.o \
- env_nvram.o env_nowhere.o \
- exports.o \
- fdt_support.o flash.o fpga.o ft_build.o \
- hush.o kgdb.o lcd.o lists.o lynxkdi.o \
- memsize.o miiphybb.o miiphyutil.o \
- s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \
- usb.o usb_kbd.o usb_storage.o \
- virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o cmd_mfsl.o
+COBJS-y += main.o
+COBJS-y += ACEX1K.o
+COBJS-y += altera.o
+COBJS-y += bedbug.o
+COBJS-y += circbuf.o
+COBJS-y += cmd_autoscript.o
+COBJS-y += cmd_bdinfo.o
+COBJS-y += cmd_bedbug.o
+COBJS-y += cmd_bmp.o
+COBJS-y += cmd_boot.o
+COBJS-y += cmd_bootm.o
+COBJS-y += cmd_cache.o
+COBJS-y += cmd_console.o
+COBJS-y += cmd_date.o
+COBJS-y += cmd_dcr.o
+COBJS-y += cmd_diag.o
+COBJS-y += cmd_display.o
+COBJS-y += cmd_doc.o
+COBJS-y += cmd_dtt.o
+COBJS-y += cmd_eeprom.o
+COBJS-y += cmd_elf.o
+COBJS-y += cmd_ext2.o
+COBJS-y += cmd_fat.o
+COBJS-y += cmd_fdc.o
+COBJS-y += cmd_fdt.o
+COBJS-y += cmd_fdos.o
+COBJS-y += cmd_flash.o
+COBJS-y += cmd_fpga.o
+COBJS-y += cmd_i2c.o
+COBJS-y += cmd_ide.o
+COBJS-y += cmd_immap.o
+COBJS-y += cmd_itest.o
+COBJS-y += cmd_jffs2.o
+COBJS-y += cmd_load.o
+COBJS-y += cmd_log.o
+COBJS-y += cmd_mem.o
+COBJS-y += cmd_mii.o
+COBJS-y += cmd_misc.o
+COBJS-y += cmd_mmc.o
+COBJS-y += cmd_nand.o
+COBJS-y += cmd_net.o
+COBJS-y += cmd_nvedit.o
+COBJS-y += cmd_onenand.o
+COBJS-y += cmd_pci.o
+COBJS-y += cmd_pcmcia.o
+COBJS-y += cmd_portio.o
+COBJS-y += cmd_reginfo.o
+COBJS-y += cmd_reiser.o
+COBJS-y += cmd_sata.o
+COBJS-y += cmd_scsi.o
+COBJS-y += cmd_spi.o
+COBJS-y += cmd_universe.o
+COBJS-y += cmd_usb.o
+COBJS-y += cmd_vfd.o
+COBJS-y += command.o
+COBJS-y += console.o
+COBJS-y += cyclon2.o
+COBJS-y += devices.o
+COBJS-y += dlmalloc.o
+COBJS-y += docecc.o
+COBJS-y += environment.o
+COBJS-y += env_common.o
+COBJS-y += env_nand.o
+COBJS-y += env_dataflash.o
+COBJS-y += env_flash.o
+COBJS-y += env_eeprom.o
+COBJS-y += env_onenand.o
+COBJS-y += env_nvram.o
+COBJS-y += env_nowhere.o
+COBJS-y += exports.o
+COBJS-y += fdt_support.o
+COBJS-y += flash.o
+COBJS-y += fpga.o
+COBJS-y += ft_build.o
+COBJS-y += hush.o
+COBJS-y += kgdb.o
+COBJS-y += lcd.o
+COBJS-y += lists.o
+COBJS-y += lynxkdi.o
+COBJS-y += memsize.o
+COBJS-y += miiphybb.o
+COBJS-y += miiphyutil.o
+COBJS-y += s_record.o
+COBJS-y += serial.o
+COBJS-y += soft_i2c.o
+COBJS-y += soft_spi.o
+COBJS-y += spartan2.o
+COBJS-y += spartan3.o
+COBJS-y += usb.o
+COBJS-y += usb_kbd.o
+COBJS-y += usb_storage.o
+COBJS-y += virtex2.o
+COBJS-y += xilinx.o
+COBJS-y += crc16.o
+COBJS-y += xyzModem.o
+COBJS-y += cmd_mac.o
+COBJS-y += cmd_mfsl.o
+COBJS := $(COBJS-y)
SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))
"\t'arg' can be the address of an initrd image\n"
#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
"\tWhen booting a Linux kernel which requires a flat device-tree\n"
- "\ta third argument is required which is the address of the of the\n"
+ "\ta third argument is required which is the address of the\n"
"\tdevice-tree blob. To boot that kernel without an initrd image,\n"
"\tuse a '-' for the second argument. If you do not pass a third\n"
"\ta bd_info struct will be passed instead\n"
U_BOOT_CMD(
dtt, 1, 1, do_dtt,
- "dtt - Digital Thermometer and Themostat\n",
+ "dtt - Digital Thermometer and Thermostat\n",
" - Read temperature from digital thermometer and thermostat.\n"
);
/* Convert bitstream data and load into the fpga */
int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
{
+#if (CONFIG_FPGA & CFG_FPGA_XILINX)
unsigned int length;
unsigned char* swapdata;
unsigned int swapsize;
dataptr = (unsigned char *)fpgadata;
-#if CFG_FPGA_XILINX
/* skip the first bytes of the bitsteam, their meaning is unknown */
length = (*dataptr << 8) + *(dataptr+1);
dataptr+=2;
#ifndef __PPC__
#include <asm/io.h>
-#ifdef __MIPS__
-/* Macros depend on this variable */
-unsigned long mips_io_port_base = 0;
-#endif
#endif
#ifdef CONFIG_IDE_8xx_DIRECT
input_swap_data (device, iobuf, ATA_SECTORWORDS);
- ident_cpy (dev_desc->revision, iop->fw_rev, sizeof(dev_desc->revision));
- ident_cpy (dev_desc->vendor, iop->model, sizeof(dev_desc->vendor));
- ident_cpy (dev_desc->product, iop->serial_no, sizeof(dev_desc->product));
+ ident_cpy ((unsigned char*)dev_desc->revision, iop->fw_rev, sizeof(dev_desc->revision));
+ ident_cpy ((unsigned char*)dev_desc->vendor, iop->model, sizeof(dev_desc->vendor));
+ ident_cpy ((unsigned char*)dev_desc->product, iop->serial_no, sizeof(dev_desc->product));
#ifdef __LITTLE_ENDIAN
/*
* firmware revision and model number have Big Endian Byte
return;
/* copy device ident strings */
- ident_cpy(dev_desc->vendor,&iobuf[8],8);
- ident_cpy(dev_desc->product,&iobuf[16],16);
- ident_cpy(dev_desc->revision,&iobuf[32],5);
+ ident_cpy((unsigned char*)dev_desc->vendor,&iobuf[8],8);
+ ident_cpy((unsigned char*)dev_desc->product,&iobuf[16],16);
+ ident_cpy((unsigned char*)dev_desc->revision,&iobuf[32],5);
dev_desc->lun=0;
dev_desc->lba=0;
unsigned int reg = 0;
unsigned int val = 0;
- reg = (unsigned int)simple_strtoul (argv[1], NULL, 16);
- val = (unsigned int)simple_strtoul (argv[2], NULL, 16);
- if (argc < 1) {
+ if (argc < 2) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
+ reg = (unsigned int)simple_strtoul (argv[1], NULL, 16);
+ val = (unsigned int)simple_strtoul (argv[2], NULL, 16);
switch (reg) {
case 0x1:
if (argc > 2) {
MTS (val, rmsr);
NOP;
MFS (val, rmsr);
-
} else {
MFS (val, rmsr);
}
puts ("ESR");
break;
default:
+ puts ("Unsupported register\n");
return 1;
}
printf (": 0x%08lx\n", val);
" 3 - blocking control write\n");
U_BOOT_CMD (rspr, 3, 1, do_rspr,
- "rmsr - read/write special purpose register\n",
+ "rspr - read/write special purpose register\n",
"- reg_num [write value] read/write special purpose register\n"
- " 0 - MSR - Machine status register\n"
- " 1 - EAR - Exception address register\n"
- " 2 - ESR - Exception status register\n");
+ " 1 - MSR - Machine status register\n"
+ " 3 - EAR - Exception address register\n"
+ " 5 - ESR - Exception status register\n");
#endif
"OUI = 0x%04X, "
"Model = 0x%02X, "
"Rev = 0x%02X, "
- "%3dbaseT, %s\n",
+ "%3dbase%s, %s\n",
j, oui, model, rev,
miiphy_speed (devname, j),
+ miiphy_is_1000base_x (devname, j)
+ ? "X" : "T",
(miiphy_duplex (devname, j) == FULL)
? "FDX" : "HDX");
}
"OUI = 0x%04X, "
"Model = 0x%02X, "
"Rev = 0x%02X, "
- "%3dbaseT, %s\n",
+ "%3dbase%s, %s\n",
j, oui, model, rev,
miiphy_speed (devname, j),
+ miiphy_is_1000base_x (devname, j)
+ ? "X" : "T",
(miiphy_duplex (devname, j) == FULL)
? "FDX" : "HDX");
}
!defined(CFG_ENV_IS_IN_FLASH) && \
!defined(CFG_ENV_IS_IN_DATAFLASH) && \
!defined(CFG_ENV_IS_IN_NAND) && \
+ !defined(CFG_ENV_IS_IN_ONENAND) && \
!defined(CFG_ENV_IS_NOWHERE)
-# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|NOWHERE}
+# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|ONENAND|NOWHERE}
#endif
#define XMK_STR(x) #x
#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \
- || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND))
+ || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) \
+ || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))
int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
extern char * env_name_spec;
#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \
|| (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \
- || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND))
+ || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) \
+ || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))
U_BOOT_CMD(
saveenv, 1, 0, do_saveenv,
"saveenv - save environment variables to persistent storage\n",
--- /dev/null
+/*
+ * U-Boot command for OneNAND support
+ *
+ * Copyright (C) 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <command.h>
+
+#ifdef CONFIG_CMD_ONENAND
+
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+
+#include <asm/io.h>
+
+extern struct mtd_info onenand_mtd;
+extern struct onenand_chip onenand_chip;
+
+int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ int ret = 0;
+
+ switch (argc) {
+ case 0:
+ case 1:
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+
+ case 2:
+ if (strncmp(argv[1], "open", 4) == 0) {
+ onenand_init();
+ return 0;
+ }
+ onenand_print_device_info(onenand_chip.device_id, 1);
+ return 0;
+
+ default:
+ /* At least 4 args */
+ if (strncmp(argv[1], "erase", 5) == 0) {
+ struct erase_info instr;
+ ulong start, end;
+ ulong block;
+
+ start = simple_strtoul(argv[2], NULL, 10);
+ end = simple_strtoul(argv[3], NULL, 10);
+ start -= (unsigned long)onenand_chip.base;
+ end -= (unsigned long)onenand_chip.base;
+
+ if (!end || end < 0)
+ end = start;
+
+ printf("Erase block from %d to %d\n", start, end);
+
+ for (block = start; block <= end; block++) {
+ instr.addr = block << onenand_chip.erase_shift;
+ instr.len = 1 << onenand_chip.erase_shift;
+ ret = onenand_erase(&onenand_mtd, &instr);
+ if (ret) {
+ printf("erase failed %d\n", block);
+ break;
+ }
+ }
+
+ return 0;
+ }
+
+ if (strncmp(argv[1], "read", 4) == 0) {
+ ulong addr = simple_strtoul(argv[2], NULL, 16);
+ ulong ofs = simple_strtoul(argv[3], NULL, 16);
+ size_t len = simple_strtoul(argv[4], NULL, 16);
+ size_t retlen = 0;
+ int oob = strncmp(argv[1], "read.oob", 8) ? 0 : 1;
+
+ ofs -= (unsigned long)onenand_chip.base;
+
+ if (oob)
+ onenand_read_oob(&onenand_mtd, ofs, len,
+ &retlen, (u_char *) addr);
+ else
+ onenand_read(&onenand_mtd, ofs, len, &retlen,
+ (u_char *) addr);
+ printf("Done\n");
+
+ return 0;
+ }
+
+ if (strncmp(argv[1], "write", 5) == 0) {
+ ulong addr = simple_strtoul(argv[2], NULL, 16);
+ ulong ofs = simple_strtoul(argv[3], NULL, 16);
+ size_t len = simple_strtoul(argv[4], NULL, 16);
+ size_t retlen = 0;
+
+ ofs -= (unsigned long)onenand_chip.base;
+
+ onenand_write(&onenand_mtd, ofs, len, &retlen,
+ (u_char *) addr);
+ printf("Done\n");
+
+ return 0;
+ }
+
+ if (strncmp(argv[1], "block", 5) == 0) {
+ ulong addr = simple_strtoul(argv[2], NULL, 16);
+ ulong block = simple_strtoul(argv[3], NULL, 10);
+ ulong page = simple_strtoul(argv[4], NULL, 10);
+ size_t len = simple_strtol(argv[5], NULL, 10);
+ size_t retlen = 0;
+ ulong ofs;
+ int oob = strncmp(argv[1], "block.oob", 9) ? 0 : 1;
+
+ ofs = block << onenand_chip.erase_shift;
+ if (page)
+ ofs += page << onenand_chip.page_shift;
+
+ if (!len) {
+ if (oob)
+ len = 64;
+ else
+ len = 512;
+ }
+
+ if (oob)
+ onenand_read_oob(&onenand_mtd, ofs, len,
+ &retlen, (u_char *) addr);
+ else
+ onenand_read(&onenand_mtd, ofs, len, &retlen,
+ (u_char *) addr);
+ return 0;
+ }
+
+ break;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ onenand, 6, 1, do_onenand,
+ "onenand - OneNAND sub-system\n",
+ "info - show available OneNAND devices\n"
+ "onenand read[.oob] addr ofs len - read data at ofs with len to addr\n"
+ "onenand write addr ofs len - write data at ofs with len from addr\n"
+ "onenand erase saddr eaddr - erase block start addr to end addr\n"
+ "onenand block[.oob] addr block [page] [len] - "
+ "read data with (block [, page]) to addr"
+);
+
+#endif /* CONFIG_CMD_ONENAND */
if((modi&0x80)==0x80) /* drive is removable */
scsi_dev_desc[scsi_max_devs].removable=TRUE;
/* get info for this device */
- scsi_ident_cpy(&scsi_dev_desc[scsi_max_devs].vendor[0],&tempbuff[8],8);
- scsi_ident_cpy(&scsi_dev_desc[scsi_max_devs].product[0],&tempbuff[16],16);
- scsi_ident_cpy(&scsi_dev_desc[scsi_max_devs].revision[0],&tempbuff[32],4);
+ scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].vendor[0],
+ &tempbuff[8], 8);
+ scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].product[0],
+ &tempbuff[16], 16);
+ scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].revision[0],
+ &tempbuff[32], 4);
scsi_dev_desc[scsi_max_devs].target=pccb->target;
scsi_dev_desc[scsi_max_devs].lun=pccb->lun;
--- /dev/null
+/*
+ * (C) Copyright 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CFG_ENV_IS_IN_ONENAND) /* Environment is in OneNAND */
+
+#include <command.h>
+#include <environment.h>
+#include <linux/stddef.h>
+#include <malloc.h>
+
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+
+extern struct mtd_info onenand_mtd;
+extern struct onenand_chip onenand_chip;
+
+/* References to names in env_common.c */
+extern uchar default_environment[];
+
+#define ONENAND_ENV_SIZE(mtd) (mtd.oobblock - ENV_HEADER_SIZE)
+
+char *env_name_spec = "OneNAND";
+
+#ifdef ENV_IS_EMBEDDED
+extern uchar environment[];
+env_t *env_ptr = (env_t *) (&environment[0]);
+#else /* ! ENV_IS_EMBEDDED */
+static unsigned char onenand_env[MAX_ONENAND_PAGESIZE];
+env_t *env_ptr = (env_t *) onenand_env;
+#endif /* ENV_IS_EMBEDDED */
+
+uchar env_get_char_spec(int index)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ return (*((uchar *) (gd->env_addr + index)));
+}
+
+void env_relocate_spec(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ unsigned long env_addr;
+ int use_default = 0;
+ int retlen;
+
+ env_addr = CFG_ENV_ADDR;
+ env_addr -= (unsigned long)onenand_chip.base;
+
+ /* Check OneNAND exist */
+ if (onenand_mtd.oobblock)
+ /* Ignore read fail */
+ onenand_read(&onenand_mtd, env_addr, onenand_mtd.oobblock,
+ &retlen, (u_char *) env_ptr);
+ else
+ onenand_mtd.oobblock = MAX_ONENAND_PAGESIZE;
+
+ if (crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd)) !=
+ env_ptr->crc)
+ use_default = 1;
+
+ if (use_default) {
+ memcpy(env_ptr->data, default_environment,
+ ONENAND_ENV_SIZE(onenand_mtd));
+ env_ptr->crc =
+ crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd));
+ }
+
+ gd->env_addr = (ulong) & env_ptr->data;
+ gd->env_valid = 1;
+}
+
+int saveenv(void)
+{
+ unsigned long env_addr = CFG_ENV_ADDR;
+ struct erase_info instr;
+ int retlen;
+
+ instr.len = CFG_ENV_SIZE;
+ instr.addr = env_addr;
+ instr.addr -= (unsigned long)onenand_chip.base;
+ if (onenand_erase(&onenand_mtd, &instr)) {
+ printf("OneNAND: erase failed at 0x%08x\n", env_addr);
+ return 1;
+ }
+
+ /* update crc */
+ env_ptr->crc =
+ crc32(0, env_ptr->data, onenand_mtd.oobblock - ENV_HEADER_SIZE);
+
+ env_addr -= (unsigned long)onenand_chip.base;
+ if (onenand_write(&onenand_mtd, env_addr, onenand_mtd.oobblock, &retlen,
+ (u_char *) env_ptr)) {
+ printf("OneNAND: write failed at 0x%08x\n", instr.addr);
+ return 2;
+ }
+
+ return 0;
+}
+
+int env_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /* use default */
+ gd->env_addr = (ulong) & default_environment[0];
+ gd->env_valid = 1;
+
+ return 0;
+}
+
+#endif /* CFG_ENV_IS_IN_ONENAND */
struct mii_dev {
struct list_head link;
char *name;
- int (* read)(char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value);
- int (* write)(char *devname, unsigned char addr,
- unsigned char reg, unsigned short value);
+ int (*read) (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value);
+ int (*write) (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
};
static struct list_head mii_devs;
*
* Initialize global data. Need to be called before any other miiphy routine.
*/
-void miiphy_init()
+void miiphy_init ()
{
- INIT_LIST_HEAD(&mii_devs);
- current_mii = NULL;
+ INIT_LIST_HEAD (&mii_devs);
+ current_mii = NULL;
}
/*****************************************************************************
*
* Register read and write MII access routines for the device <name>.
*/
-void miiphy_register(char *name,
- int (* read)(char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value),
- int (* write)(char *devname, unsigned char addr,
- unsigned char reg, unsigned short value))
+void miiphy_register (char *name,
+ int (*read) (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value),
+ int (*write) (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value))
{
struct list_head *entry;
struct mii_dev *new_dev;
unsigned int name_len;
/* check if we have unique name */
- list_for_each(entry, &mii_devs) {
- miidev = list_entry(entry, struct mii_dev, link);
- if (strcmp(miidev->name, name) == 0) {
- printf("miiphy_register: non unique device name '%s'\n",
- name);
+ list_for_each (entry, &mii_devs) {
+ miidev = list_entry (entry, struct mii_dev, link);
+ if (strcmp (miidev->name, name) == 0) {
+ printf ("miiphy_register: non unique device name "
+ "'%s'\n", name);
return;
}
}
/* allocate memory */
- name_len = strlen(name);
- new_dev = (struct mii_dev *)malloc(sizeof(struct mii_dev) + name_len + 1);
+ name_len = strlen (name);
+ new_dev =
+ (struct mii_dev *)malloc (sizeof (struct mii_dev) + name_len + 1);
- if(new_dev == NULL) {
- printf("miiphy_register: cannot allocate memory for '%s'\n",
- name);
+ if (new_dev == NULL) {
+ printf ("miiphy_register: cannot allocate memory for '%s'\n",
+ name);
return;
}
- memset(new_dev, 0, sizeof(struct mii_dev) + name_len);
+ memset (new_dev, 0, sizeof (struct mii_dev) + name_len);
/* initalize mii_dev struct fields */
- INIT_LIST_HEAD(&new_dev->link);
+ INIT_LIST_HEAD (&new_dev->link);
new_dev->read = read;
new_dev->write = write;
new_dev->name = (char *)(new_dev + 1);
- strncpy(new_dev->name, name, name_len);
+ strncpy (new_dev->name, name, name_len);
new_dev->name[name_len] = '\0';
- debug("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n",
- new_dev->name, new_dev->read, new_dev->write);
+ debug ("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n",
+ new_dev->name, new_dev->read, new_dev->write);
/* add it to the list */
- list_add_tail(&new_dev->link, &mii_devs);
+ list_add_tail (&new_dev->link, &mii_devs);
if (!current_mii)
current_mii = new_dev;
}
-int miiphy_set_current_dev(char *devname)
+int miiphy_set_current_dev (char *devname)
{
struct list_head *entry;
struct mii_dev *dev;
- list_for_each(entry, &mii_devs) {
- dev = list_entry(entry, struct mii_dev, link);
+ list_for_each (entry, &mii_devs) {
+ dev = list_entry (entry, struct mii_dev, link);
- if (strcmp(devname, dev->name) == 0) {
+ if (strcmp (devname, dev->name) == 0) {
current_mii = dev;
return 0;
}
}
- printf("No such device: %s\n", devname);
+ printf ("No such device: %s\n", devname);
return 1;
}
-char *miiphy_get_current_dev()
+char *miiphy_get_current_dev ()
{
if (current_mii)
return current_mii->name;
* Returns:
* 0 on success
*/
-int miiphy_read(char *devname, unsigned char addr, unsigned char reg,
- unsigned short *value)
+int miiphy_read (char *devname, unsigned char addr, unsigned char reg,
+ unsigned short *value)
{
struct list_head *entry;
struct mii_dev *dev;
int read_ret = 0;
if (!devname) {
- printf("NULL device name!\n");
+ printf ("NULL device name!\n");
return 1;
}
- list_for_each(entry, &mii_devs) {
- dev = list_entry(entry, struct mii_dev, link);
+ list_for_each (entry, &mii_devs) {
+ dev = list_entry (entry, struct mii_dev, link);
- if (strcmp(devname, dev->name) == 0) {
+ if (strcmp (devname, dev->name) == 0) {
found_dev = 1;
- read_ret = dev->read(devname, addr, reg, value);
+ read_ret = dev->read (devname, addr, reg, value);
break;
}
}
if (found_dev == 0)
- printf("No such device: %s\n", devname);
+ printf ("No such device: %s\n", devname);
return ((found_dev) ? read_ret : 1);
}
* Returns:
* 0 on success
*/
-int miiphy_write(char *devname, unsigned char addr, unsigned char reg,
- unsigned short value)
+int miiphy_write (char *devname, unsigned char addr, unsigned char reg,
+ unsigned short value)
{
struct list_head *entry;
struct mii_dev *dev;
int write_ret = 0;
if (!devname) {
- printf("NULL device name!\n");
+ printf ("NULL device name!\n");
return 1;
}
- list_for_each(entry, &mii_devs) {
- dev = list_entry(entry, struct mii_dev, link);
+ list_for_each (entry, &mii_devs) {
+ dev = list_entry (entry, struct mii_dev, link);
- if (strcmp(devname, dev->name) == 0) {
+ if (strcmp (devname, dev->name) == 0) {
found_dev = 1;
- write_ret = dev->write(devname, addr, reg, value);
+ write_ret = dev->write (devname, addr, reg, value);
break;
}
}
if (found_dev == 0)
- printf("No such device: %s\n", devname);
+ printf ("No such device: %s\n", devname);
return ((found_dev) ? write_ret : 1);
}
*
* Print out list of registered MII capable devices.
*/
-void miiphy_listdev(void)
+void miiphy_listdev (void)
{
struct list_head *entry;
struct mii_dev *dev;
- puts("MII devices: ");
- list_for_each(entry, &mii_devs) {
- dev = list_entry(entry, struct mii_dev, link);
- printf("'%s' ", dev->name);
+ puts ("MII devices: ");
+ list_for_each (entry, &mii_devs) {
+ dev = list_entry (entry, struct mii_dev, link);
+ printf ("'%s' ", dev->name);
}
- puts("\n");
+ puts ("\n");
if (current_mii)
- printf("Current device: '%s'\n", current_mii->name);
+ printf ("Current device: '%s'\n", current_mii->name);
}
-
/*****************************************************************************
*
* Read the OUI, manufacture's model number, and revision number.
* Returns:
* 0 on success
*/
-int miiphy_info (char *devname,
- unsigned char addr,
- unsigned int *oui,
+int miiphy_info (char *devname, unsigned char addr, unsigned int *oui,
unsigned char *model, unsigned char *rev)
{
unsigned int reg = 0;
#ifdef DEBUG
printf ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
#endif
- *oui = ( reg >> 10);
- *model = (unsigned char) ((reg >> 4) & 0x0000003F);
- *rev = (unsigned char) ( reg & 0x0000000F);
+ *oui = (reg >> 10);
+ *model = (unsigned char)((reg >> 4) & 0x0000003F);
+ *rev = (unsigned char)(reg & 0x0000000F);
return (0);
}
-
/*****************************************************************************
*
* Reset the PHY.
return (0);
}
-
/*****************************************************************************
*
- * Determine the ethernet speed (10/100).
+ * Determine the ethernet speed (10/100/1000). Return 10 on error.
*/
int miiphy_speed (char *devname, unsigned char addr)
{
- unsigned short reg;
+ u16 bmcr, anlpar;
#if defined(CONFIG_PHY_GIGE)
- if (miiphy_read (devname, addr, PHY_1000BTSR, ®)) {
- printf ("PHY 1000BT Status read failed\n");
- } else {
- if (reg != 0xFFFF) {
- if ((reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) !=0) {
- return (_1000BASET);
- }
- }
+ u16 btsr;
+
+ /*
+ * Check for 1000BASE-X. If it is supported, then assume that the speed
+ * is 1000.
+ */
+ if (miiphy_is_1000base_x (devname, addr)) {
+ return _1000BASET;
+ }
+ /*
+ * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
+ */
+ /* Check for 1000BASE-T. */
+ if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) {
+ printf ("PHY 1000BT status");
+ goto miiphy_read_failed;
+ }
+ if (btsr != 0xFFFF &&
+ (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD))) {
+ return _1000BASET;
}
#endif /* CONFIG_PHY_GIGE */
/* Check Basic Management Control Register first. */
- if (miiphy_read (devname, addr, PHY_BMCR, ®)) {
- puts ("PHY speed read failed, assuming 10bT\n");
- return (_10BASET);
+ if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) {
+ printf ("PHY speed");
+ goto miiphy_read_failed;
}
/* Check if auto-negotiation is on. */
- if ((reg & PHY_BMCR_AUTON) != 0) {
+ if (bmcr & PHY_BMCR_AUTON) {
/* Get auto-negotiation results. */
- if (miiphy_read (devname, addr, PHY_ANLPAR, ®)) {
- puts ("PHY AN speed read failed, assuming 10bT\n");
- return (_10BASET);
- }
- if ((reg & PHY_ANLPAR_100) != 0) {
- return (_100BASET);
- } else {
- return (_10BASET);
+ if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
+ printf ("PHY AN speed");
+ goto miiphy_read_failed;
}
+ return (anlpar & PHY_ANLPAR_100) ? _100BASET : _10BASET;
}
/* Get speed from basic control settings. */
- else if (reg & PHY_BMCR_100MB) {
- return (_100BASET);
- } else {
- return (_10BASET);
- }
+ return (bmcr & PHY_BMCR_100MB) ? _100BASET : _10BASET;
+ miiphy_read_failed:
+ printf (" read failed, assuming 10BASE-T\n");
+ return _10BASET;
}
-
/*****************************************************************************
*
- * Determine full/half duplex.
+ * Determine full/half duplex. Return half on error.
*/
int miiphy_duplex (char *devname, unsigned char addr)
{
- unsigned short reg;
+ u16 bmcr, anlpar;
#if defined(CONFIG_PHY_GIGE)
- if (miiphy_read (devname, addr, PHY_1000BTSR, ®)) {
- printf ("PHY 1000BT Status read failed\n");
- } else {
- if ( (reg != 0xFFFF) &&
- (reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) ) {
- if ((reg & PHY_1000BTSR_1000FD) !=0) {
- return (FULL);
- } else {
- return (HALF);
- }
+ u16 btsr;
+
+ /* Check for 1000BASE-X. */
+ if (miiphy_is_1000base_x (devname, addr)) {
+ /* 1000BASE-X */
+ if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
+ printf ("1000BASE-X PHY AN duplex");
+ goto miiphy_read_failed;
+ }
+ }
+ /*
+ * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
+ */
+ /* Check for 1000BASE-T. */
+ if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) {
+ printf ("PHY 1000BT status");
+ goto miiphy_read_failed;
+ }
+ if (btsr != 0xFFFF) {
+ if (btsr & PHY_1000BTSR_1000FD) {
+ return FULL;
+ } else if (btsr & PHY_1000BTSR_1000HD) {
+ return HALF;
}
}
#endif /* CONFIG_PHY_GIGE */
/* Check Basic Management Control Register first. */
- if (miiphy_read (devname, addr, PHY_BMCR, ®)) {
- puts ("PHY duplex read failed, assuming half duplex\n");
- return (HALF);
+ if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) {
+ puts ("PHY duplex");
+ goto miiphy_read_failed;
}
/* Check if auto-negotiation is on. */
- if ((reg & PHY_BMCR_AUTON) != 0) {
+ if (bmcr & PHY_BMCR_AUTON) {
/* Get auto-negotiation results. */
- if (miiphy_read (devname, addr, PHY_ANLPAR, ®)) {
- puts ("PHY AN duplex read failed, assuming half duplex\n");
- return (HALF);
- }
-
- if ((reg & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) != 0) {
- return (FULL);
- } else {
- return (HALF);
+ if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
+ puts ("PHY AN duplex");
+ goto miiphy_read_failed;
}
+ return (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) ?
+ FULL : HALF;
}
/* Get speed from basic control settings. */
- else if (reg & PHY_BMCR_DPLX) {
- return (FULL);
- } else {
- return (HALF);
- }
+ return (bmcr & PHY_BMCR_DPLX) ? FULL : HALF;
+
+ miiphy_read_failed:
+ printf (" read failed, assuming half duplex\n");
+ return HALF;
+}
+/*****************************************************************************
+ *
+ * Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/
+ * 1000BASE-T, or on error.
+ */
+int miiphy_is_1000base_x (char *devname, unsigned char addr)
+{
+#if defined(CONFIG_PHY_GIGE)
+ u16 exsr;
+
+ if (miiphy_read (devname, addr, PHY_EXSR, &exsr)) {
+ printf ("PHY extended status read failed, assuming no "
+ "1000BASE-X\n");
+ return 0;
+ }
+ return 0 != (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH));
+#else
+ return 0;
+#endif
}
#ifdef CFG_FAULT_ECHO_LINK_DOWN
unsigned short reg;
/* dummy read; needed to latch some phys */
- (void)miiphy_read(devname, addr, PHY_BMSR, ®);
+ (void)miiphy_read (devname, addr, PHY_BMSR, ®);
if (miiphy_read (devname, addr, PHY_BMSR, ®)) {
puts ("PHY_BMSR read failed, assuming no link\n");
return (0);
}
}
#endif
-
#endif /* CONFIG_MII */
(*fn->clk) (FALSE, TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Write data */
- (*fn->wr) ((val < 0), TRUE, cookie);
+ (*fn->wr) ((val & 0x80), TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Assert the clock */
(*fn->clk) (TRUE, TRUE, cookie);
(*fn->clk) (FALSE, TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Write data */
- (*fn->wr) ((val < 0), TRUE, cookie);
+ (*fn->wr) ((val & 0x80), TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Assert the clock */
(*fn->clk) (TRUE, TRUE, cookie);
repeat_delay=REPEAT_DELAY;
}
keycode=0;
- if((scancode>3) && (scancode<0x1d)) { /* alpha numeric values */
+ if((scancode>3) && (scancode<=0x1d)) { /* alpha numeric values */
keycode=scancode-4 + 0x61;
if(caps_lock)
keycode&=~CAPITAL_MASK; /* switch to capital Letters */
dev_desc->product[16] = 0;
dev_desc->revision[4] = 0;
#ifdef CONFIG_USB_BIN_FIXUP
- usb_bin_fixup(dev->descriptor, dev_desc->vendor, dev_desc->product);
+ usb_bin_fixup(dev->descriptor, (uchar *)dev_desc->vendor, (uchar *)dev_desc->product);
#endif /* CONFIG_USB_BIN_FIXUP */
USB_STOR_PRINTF("ISO Vers %X, Response Data %X\n",usb_stor_buf[2],usb_stor_buf[3]);
if(usb_test_unit_ready(pccb,ss)) {
endif
endif
-ifeq ($(ARCH),blackfin)
-PLATFORM_CPPFLAGS+= -D__BLACKFIN__
-endif
-
ifdef ARCH
sinclude $(TOPDIR)/$(ARCH)_config.mk # include architecture dependend rules
endif
#elif defined(CONFIG_LPC2292)
+DECLARE_GLOBAL_DATA_PTR;
+
#include <asm/arch/hardware.h>
void serial_setbrg (void)
#include <asm/arch/hardware.h>
-int usb_cpu_init()
+int usb_cpu_init(void)
{
/* Enable USB host clock. */
*AT91C_PMC_SCER = AT91C_PMC_UHP; /* 48MHz clock enabled for UHP */
return 0;
}
-int usb_cpu_stop()
+int usb_cpu_stop(void)
{
/* Initialization failed */
*AT91C_PMC_PCDR = 1 << AT91C_ID_UHP; /* Peripheral Clock Disable Register */
return 0;
}
-int usb_cpu_init_fail()
+int usb_cpu_init_fail(void)
{
- usb_cpu_stop();
+ return usb_cpu_stop();
}
# endif /* CONFIG_AT91RM9200 */
LIB = $(obj)lib$(SOC).a
COBJS = i2c.o interrupts.o serial.o speed.o \
- usb.o
+ usb.o usb_ohci.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
if (ohci->ed_controltail == NULL) {
writel (ed, &ohci->regs->ed_controlhead);
} else {
- ohci->ed_controltail->hwNextED = m32_swap (ed);
+ ohci->ed_controltail->hwNextED = (__u32)m32_swap (ed);
}
ed->ed_prev = ohci->ed_controltail;
if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
if (ohci->ed_bulktail == NULL) {
writel (ed, &ohci->regs->ed_bulkhead);
} else {
- ohci->ed_bulktail->hwNextED = m32_swap (ed);
+ ohci->ed_bulktail->hwNextED = (__u32)m32_swap (ed);
}
ed->ed_prev = ohci->ed_bulktail;
if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
/* dummy td; end of td list for ed */
td = td_alloc (usb_dev);
- ed->hwTailP = m32_swap (td);
+ ed->hwTailP = (__u32)m32_swap (td);
ed->hwHeadP = ed->hwTailP;
ed->state = ED_UNLINK;
ed->type = usb_pipetype (pipe);
if (!len)
data = 0;
- td->hwINFO = m32_swap (info);
- td->hwCBP = m32_swap (data);
+ td->hwINFO = (__u32)m32_swap (info);
+ td->hwCBP = (__u32)m32_swap (data);
if (data)
- td->hwBE = m32_swap (data + len - 1);
+ td->hwBE = (__u32)m32_swap (data + len - 1);
else
td->hwBE = 0;
- td->hwNextTD = m32_swap (td_pt);
+ td->hwNextTD = (__u32)m32_swap (td_pt);
/* append to queue */
td->ed->hwTailP = td->hwNextTD;
#include <config.h>
#include <version.h>
-#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
-#include <led.h>
-#endif
+#include <status_led.h>
/*
*************************************************************************
.globl _start
-_start: b reset
+_start: b start_code
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
/*
*************************************************************************
*
- * Startup Code (reset vector)
+ * Startup Code (called from the ARM reset exception vector)
*
* do important init only if we don't start from memory!
* relocate armboot to ram
/*
- * the actual reset code
+ * the actual start code
*/
-reset:
+start_code:
/*
* set the cpu to SVC32 mode
*/
orr r0,r0,#0xd3
msr cpsr,r0
-#if CONFIG_AT91RM9200
-#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
- bl LED_init
+ bl coloured_LED_init
bl red_LED_on
-#endif
-#ifdef CONFIG_BOOTBINFUNC
-/* code based on entry.S from ATMEL */
-#define AT91C_BASE_CKGR 0xFFFFFC20
-#define CKGR_MOR 0
- /* Get the CKGR Base Address */
- ldr r1, =AT91C_BASE_CKGR
-
-/* Main oscillator Enable register APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF */
-/* ldr r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT */
- ldr r0, =0x0000FF01
- str r0, [r1, #CKGR_MOR]
- /* Add loop to compensate Main Oscillator startup time */
- ldr r0, =0x00000010
-LoopOsc:
- subs r0, r0, #1
- bhi LoopOsc
- /* scratch stack */
- ldr r1, =0x00204000
- /* Insure word alignment */
- bic r1, r1, #3
- /* Init stack SYS */
- mov sp, r1
- /*
- * This does a lot more than just set up the memory, which
- * is why it's called lowlevelinit
- */
- bl lowlevelinit /* in memsetup.S */
- bl icache_enable;
- /* ------------------------------------
- * Read/modify/write CP15 control register
- * -------------------------------------
- * read cp15 control register (cp15 r1) in r0
- * ------------------------------------
- */
- mrc p15, 0, r0, c1, c0, 0
- /* Reset bit :Little Endian end fast bus mode */
- ldr r3, =0xC0000080
- /* Set bit :Asynchronous clock mode, Not Fast Bus */
- ldr r4, =0xC0000000
- bic r0, r0, r3
- orr r0, r0, r4
- /* write r0 in cp15 control register (cp15 r1) */
- mcr p15, 0, r0, c1, c0, 0
-#endif /* CONFIG_BOOTBINFUNC */
+#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
/*
- * relocate exeception table
+ * relocate exception table
*/
ldr r0, =_start
ldr r1, =0x0
bne copyex
#endif
-/* turn off the watchdog */
-#if defined(CONFIG_S3C2400)
-# define pWTCON 0x15300000
-# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
-# define CLKDIVN 0x14800014 /* clock divisor register */
-#elif defined(CONFIG_S3C2410)
-# define pWTCON 0x53000000
-# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
-# define INTSUBMSK 0x4A00001C
-# define CLKDIVN 0x4C000014 /* clock divisor register */
-#endif
-
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
+ /* turn off the watchdog */
+
+# if defined(CONFIG_S3C2400)
+# define pWTCON 0x15300000
+# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
+# define CLKDIVN 0x14800014 /* clock divisor register */
+#else
+# define pWTCON 0x53000000
+# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
+# define INTSUBMSK 0x4A00001C
+# define CLKDIVN 0x4C000014 /* clock divisor register */
+# endif
+
ldr r0, =pWTCON
mov r1, #0x0
str r1, [r0]
#endif
#ifdef CONFIG_AT91RM9200
-#ifdef CONFIG_BOOTBINFUNC
-relocate: /* relocate U-Boot to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
-#endif /* CONFIG_BOOTBINFUNC */
-#else
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
cmp r0, r1
ble clbss_l
-#if 0
- /* try doing this stuff after the relocation */
- ldr r0, =pWTCON
- mov r1, #0x0
- str r1, [r0]
-
- /*
- * mask all IRQs by setting all bits in the INTMR - default
- */
- mov r1, #0xffffffff
- ldr r0, =INTMR
- str r1, [r0]
-
- /* FCLK:HCLK:PCLK = 1:2:4 */
- /* default FCLK is 120 MHz ! */
- ldr r0, =CLKDIVN
- mov r1, #3
- str r1, [r0]
- /* END stuff after relocation */
-#endif
-
ldr pc, _start_armboot
_start_armboot: .word start_armboot
#
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
+PLATFORM_CPPFLAGS += -mcpu=5235 -fPIC
+else
PLATFORM_CPPFLAGS += -m5307 -fPIC
+endif
#
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+
+cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is5249=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg))
+is5253=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
+is5271=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
+is5272=$(shell grep CONFIG_M5272 $(TOPDIR)/include/$(cfg))
+is5282=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
+
+
+ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
+
+ifneq (,$(findstring CONFIG_M5249,$(is5249)))
+PLATFORM_CPPFLAGS += -mcpu=5249
+endif
+ifneq (,$(findstring CONFIG_M5253,$(is5253)))
+PLATFORM_CPPFLAGS += -mcpu=5253
+endif
+ifneq (,$(findstring CONFIG_M5271,$(is5271)))
+PLATFORM_CPPFLAGS += -mcpu=5271
+endif
+ifneq (,$(findstring CONFIG_M5272,$(is5272)))
+PLATFORM_CPPFLAGS += -mcpu=5272
+endif
+ifneq (,$(findstring CONFIG_M5282,$(is5282)))
+PLATFORM_CPPFLAGS += -mcpu=5282
+endif
+
+else
PLATFORM_CPPFLAGS += -m5307
+endif
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
#if defined(CONFIG_R5200)
.long 0x400
-#elif defined(CONFIG_M5282)
+#elif defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
.long _start - TEXT_BASE
#else
.long _START
* therefore no VBR to set
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
+ move.l #CFG_INT_FLASH_BASE, %d0
+#else
move.l #CFG_FLASH_BASE, %d0
+#endif
movec %d0, %VBR
#endif
#
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
+PLATFORM_CPPFLAGS += -mcpu=5329 -fPIC
+else
PLATFORM_CPPFLAGS += -m5307 -fPIC
+endif
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
- volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+ volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
- wdp->cr = 0;
udelay(1000);
-
- /* enable watchdog, set timeout to 0 and wait */
- wdp->cr = WTM_WCR_EN;
- while (1) ;
+ rcm->rcr |= RCM_RCR_SOFTRST;
/* we don't return! */
return 0;
movec %d0, %VBR
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
- movec %d0, %RAMBAR0
+ movec %d0, %RAMBAR1
/* invalidate and disable cache */
move.l #0x01000000, %d0 /* Invalidate cache cmd */
icache_enable:
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
- move.l #(CFG_SDRAM_BASE + 0xc000 + ((CFG_SDRAM_SIZE & 0x1fe0) << 11)), %d0
+ move.l #(CFG_SDRAM_BASE + 0x1c000), %d0
movec %d0, %ACR0 /* Enable cache */
move.l #0x80000200, %d0 /* Setup cache mask */
#
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
+PLATFORM_CPPFLAGS += -mcpu=54455 -fPIC
+else
PLATFORM_CPPFLAGS += -m5407 -fPIC
+endif
movec %d0, %VBR
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
- movec %d0, %RAMBAR0
+ movec %d0, %RAMBAR1
/* initialize general use internal ram */
move.l #0, %d0
/*
* (C) Copyright 2007 Michal Simek
*
- * Michal SIMEK <moonstr@monstr.eu>
+ * Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
addi r1, r0, CFG_INIT_SP_OFFSET
addi r1, r1, -4 /* Decrement SP to top of memory */
/* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
- addi r6, r0, 0xb000 /* hex b000 opcode imm */
- bslli r6, r6, 16 /* shift */
+ addi r6, r0, 0xb0000000 /* hex b000 opcode imm */
swi r6, r0, 0x0 /* reset address */
swi r6, r0, 0x8 /* user vector exception */
swi r6, r0, 0x10 /* interrupt */
swi r6, r0, 0x20 /* hardware exception */
- addi r6, r0, 0xb808 /* hew b808 opcode brai*/
- bslli r6, r6, 16
+ addi r6, r0, 0xb8080000 /* hew b808 opcode brai*/
swi r6, r0, 0x4 /* reset address */
swi r6, r0, 0xC /* user vector exception */
swi r6, r0, 0x14 /* interrupt */
timestamp = 0;
}
+#ifdef CFG_TIMER_0
ulong get_timer (ulong base)
{
return (timestamp - base);
}
+#else
+ulong get_timer (ulong base)
+{
+ return (timestamp++ - base);
+}
+#endif
void set_timer (ulong t)
{
#define MAX_WAIT 1000
+#if defined(CONFIG_CMD_MII)
+int au1x00_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short * value)
+{
+ volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
+ volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
+ u32 mii_control;
+ unsigned int timedout = 20;
+
+ while (*mii_control_reg & MAC_MII_BUSY) {
+ udelay(1000);
+ if (--timedout == 0) {
+ printf("au1x00_eth: miiphy_read busy timeout!!\n");
+ return -1;
+ }
+ }
+
+ mii_control = MAC_SET_MII_SELECT_REG(reg) |
+ MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
+
+ *mii_control_reg = mii_control;
+
+ timedout = 20;
+ while (*mii_control_reg & MAC_MII_BUSY) {
+ udelay(1000);
+ if (--timedout == 0) {
+ printf("au1x00_eth: miiphy_read busy timeout!!\n");
+ return -1;
+ }
+ }
+ *value = *mii_data_reg;
+ return 0;
+}
+
+int au1x00_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
+{
+ volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
+ volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
+ u32 mii_control;
+ unsigned int timedout = 20;
+
+ while (*mii_control_reg & MAC_MII_BUSY) {
+ udelay(1000);
+ if (--timedout == 0) {
+ printf("au1x00_eth: miiphy_write busy timeout!!\n");
+ return -1;
+ }
+ }
+
+ mii_control = MAC_SET_MII_SELECT_REG(reg) |
+ MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
+
+ *mii_data_reg = value;
+ *mii_control_reg = mii_control;
+ return 0;
+}
+#endif
+
static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
volatile mac_fifo_t *fifo_tx =
(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
return 1;
}
-#if defined(CONFIG_CMD_MII)
-int au1x00_miiphy_read(char *devname, unsigned char addr,
- unsigned char reg, unsigned short * value)
-{
- volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
- volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
- u32 mii_control;
- unsigned int timedout = 20;
-
- while (*mii_control_reg & MAC_MII_BUSY) {
- udelay(1000);
- if (--timedout == 0) {
- printf("au1x00_eth: miiphy_read busy timeout!!\n");
- return -1;
- }
- }
-
- mii_control = MAC_SET_MII_SELECT_REG(reg) |
- MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
-
- *mii_control_reg = mii_control;
-
- timedout = 20;
- while (*mii_control_reg & MAC_MII_BUSY) {
- udelay(1000);
- if (--timedout == 0) {
- printf("au1x00_eth: miiphy_read busy timeout!!\n");
- return -1;
- }
- }
- *value = *mii_data_reg;
- return 0;
-}
-
-int au1x00_miiphy_write(char *devname, unsigned char addr,
- unsigned char reg, unsigned short value)
-{
- volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
- volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
- u32 mii_control;
- unsigned int timedout = 20;
-
- while (*mii_control_reg & MAC_MII_BUSY) {
- udelay(1000);
- if (--timedout == 0) {
- printf("au1x00_eth: miiphy_write busy timeout!!\n");
- return;
- }
- }
-
- mii_control = MAC_SET_MII_SELECT_REG(reg) |
- MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
-
- *mii_data_reg = value;
- *mii_control_reg = mii_control;
- return 0;
-}
-#endif
-
#endif /* CONFIG_AU1X00 */
* MA 02111-1307 USA
*/
-
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
-
/* 16KB is the maximum size of instruction and data caches on
* MIPS 4K.
*/
#define MIPS_MAX_CACHE_SIZE 0x4000
-
/*
* cacheop macro to automate cache operations
* first some helpers...
li t4, CFG_CACHELINE_SIZE
move t5, t4
-
li v0, MIPS_MAX_CACHE_SIZE
/* Now clear that much memory starting from zero.
li a0, KSEG1
addu a1, a0, v0
-
-2: sw zero, 0(a0)
+2:
+ sw zero, 0(a0)
sw zero, 4(a0)
sw zero, 8(a0)
sw zero, 12(a0)
mtc0 zero, CP0_TAGLO
- /*
- * The caches are probably in an indeterminate state,
- * so we force good parity into them by doing an
- * invalidate, load/fill, invalidate for each line.
- */
+ /*
+ * The caches are probably in an indeterminate state,
+ * so we force good parity into them by doing an
+ * invalidate, load/fill, invalidate for each line.
+ */
/* Assume bottom of RAM will generate good parity for the cache.
*/
move a1, a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
- j ra
- .end mips_cache_reset
+ j ra
+ .end mips_cache_reset
/*******************************************************************************
*
andi v0, v0, 1
j ra
- .end dcache_status
+ .end dcache_status
/*******************************************************************************
*
li t1, -8
and t0, t0, t1
ori t0, t0, CONF_CM_UNCACHED
- mtc0 t0, CP0_CONFIG
+ mtc0 t0, CP0_CONFIG
j ra
- .end dcache_disable
-
+ .end dcache_disable
/*******************************************************************************
*
icacheop(a0,a1,a2,a3,0x1d)
j ra
+
.end mips_cache_lock
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-v=$(shell \
-$(CROSS_COMPILE)as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}')
+v=$(shell $(AS) --version |grep "GNU assembler" |cut -d. -f2)
MIPSFLAGS=$(shell \
if [ "$v" -lt "14" ]; then \
echo "-mcpu=4kc"; \
ENDIANNESS = -EB
endif
-MIPSFLAGS += $(ENDIANNESS) -mabicalls
+MIPSFLAGS += $(ENDIANNESS)
PLATFORM_CPPFLAGS += $(MIPSFLAGS)
return 0;
}
-void flush_cache (ulong start_addr, ulong size)
+void flush_cache(ulong start_addr, ulong size)
{
-
}
-void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ){
+void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
+{
write_32bit_cp0_register(CP0_ENTRYLO0, low0);
write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
write_32bit_cp0_register(CP0_ENTRYLO1, low1);
* MA 02111-1307 USA
*/
-
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
-
#define RVECENT(f,n) \
b f; nop
#define XVECENT(f,bev) \
.word 0x00000000
.word 0x03e00008
.word 0x00000000
- .word 0x00000000
+ .word 0x00000000
/* 0xbfc00428 */
.word 0xdc870000
.word 0xfca70000
.word 0x00000000
.word 0x03e00008
.word 0x00000000
- .word 0x00000000
+ .word 0x00000000
#endif /* CONFIG_PURPLE */
.align 4
reset:
li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
- /* Initialize GOT pointer.
- */
- bal 1f
+ /* Initialize $gp.
+ */
+ bal 1f
nop
- .word _GLOBAL_OFFSET_TABLE_
- 1:
- move gp, ra
- lw t1, 0(ra)
- move gp, t1
+ .word _gp
+1:
+ lw gp, 0(ra)
#ifdef CONFIG_INCA_IP
/* Disable INCA-IP Watchdog.
*/
- la t9, disable_incaip_wdt
- jalr t9
+ la t9, disable_incaip_wdt
+ jalr t9
nop
#endif
/* Initialize any external memory.
*/
- la t9, lowlevel_init
- jalr t9
+ la t9, lowlevel_init
+ jalr t9
nop
/* Initialize caches...
*/
- la t9, mips_cache_reset
- jalr t9
+ la t9, mips_cache_reset
+ jalr t9
nop
/* ... and enable them.
li t0, CONF_CM_CACHABLE_NONCOHERENT
mtc0 t0, CP0_CONFIG
-
/* Set up temporary stack.
*/
li a0, CFG_INIT_SP_OFFSET
- la t9, mips_cache_lock
- jalr t9
+ la t9, mips_cache_lock
+ jalr t9
nop
li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
j t9
nop
-
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
.globl relocate_code
.ent relocate_code
relocate_code:
- move sp, a0 /* Set new stack pointer */
+ move sp, a0 /* Set new stack pointer */
li t0, CFG_MONITOR_BASE
la t3, in_ram
move t1, a2
/*
- * Fix GOT pointer:
+ * Fix $gp:
*
- * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ * New $gp = (Old $gp - CFG_MONITOR_BASE) + Destination Address
*/
move t6, gp
sub gp, CFG_MONITOR_BASE
- add gp, a2 /* gp now adjusted */
- sub t6, gp, t6 /* t6 <-- relocation offset */
+ add gp, a2 /* gp now adjusted */
+ sub t6, gp, t6 /* t6 <-- relocation offset */
/*
* t0 = source address
sw t3, 0(t1)
addu t0, 4
ble t0, t2, 1b
- addu t1, 4 /* delay slot */
+ addu t1, 4 /* delay slot */
#endif
/* If caches were enabled, we would have to flush them here.
j t0
nop
+ .gpword _GLOBAL_OFFSET_TABLE_ /* _GLOBAL_OFFSET_TABLE_ - _gp */
.word uboot_end_data
.word uboot_end
.word num_got_entries
in_ram:
- /* Now we want to update GOT.
+ /*
+ * Now we want to update GOT.
+ *
+ * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+ * generated by GNU ld. Skip these reserved entries from relocation.
*/
lw t3, -4(t0) /* t3 <-- num_got_entries */
- addi t4, gp, 8 /* Skipping first two entries. */
+ lw t4, -16(t0) /* t4 <-- (_GLOBAL_OFFSET_TABLE_ - _gp) */
+ add t4, t4, gp /* t4 now holds _GLOBAL_OFFSET_TABLE_ */
+ addi t4, t4, 8 /* Skipping first two entries. */
li t2, 2
1:
lw t1, 0(t4)
add t2, t6
sub t1, 4
-1: addi t1, 4
+1:
+ addi t1, 4
bltl t1, t2, 1b
sw zero, 0(t1) /* delay slot */
.end relocate_code
-
/* Exception handlers.
*/
romReserved:
- b romReserved
+ b romReserved
romExcHandle:
- b romExcHandle
+ b romExcHandle
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \
-ffixed-r2 -ffixed-r29 -msoft-float -mcpu=603e
#
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -ffixed-r29 -mpowerpc -msoft-float
cpu/mpc5xx/start.o (.text)
*(.text)
+ *(.fixup)
*(.got1)
}
_etext = .;
# MA 02111-1307 USA
#
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 -ffixed-r29 \
-mstring -mcpu=603e -mmultiple
common/environment.o (.ppcenv)
*(.text)
+ *(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
{
cpu/mpc5xxx/start.o (.text)
*(.text)
+ *(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
# MA 02111-1307 USA
#
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 -ffixed-r29 \
-mstring -mcpu=603e -mmultiple
{
cpu/mpc8220/start.o (.text)
*(.text)
+ *(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
# MA 02111-1307 USA
#
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing -mrelocatable
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -msoft-float
vga?
*/
-void timer_interrupt_cpu (struct pt_regs *regs, ulong timestamp)
+void timer_interrupt_cpu (struct pt_regs *regs)
{
/* nothing to do here */
return;
{
cpu/mpc824x/start.o (.text)
*(.text)
+ *(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
# MA 02111-1307 USA
#
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 -ffixed-r29 \
-mstring -mcpu=603e -mmultiple
#include <asm/processor.h>
#include <asm/cpm_8260.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <libfdt_env.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_GET_CPU_STR_F)
#endif /* CONFIG_WATCHDOG */
/* ------------------------------------------------------------------------- */
+#if defined(CONFIG_OF_LIBFDT)
+static void do_fixup(void *fdt, const char *node, const char *prop,
+ const void *val, int len, int create)
+{
+#if defined(DEBUG)
+ int i;
+ debug("Updating property '%s/%s' = ", node, prop);
+ for (i = 0; i < len; i++)
+ debug(" %.2x", *(u8*)(val+i));
+ debug("\n");
+#endif
+ int rc = fdt_find_and_setprop(fdt, node, prop, val, len, create);
+ if (rc)
+ printf("Unable to update property %s:%s, err=%s\n",
+ node, prop, fdt_strerror(rc));
+}
+
+static void do_fixup_u32(void *fdt, const char *node, const char *prop,
+ u32 val, int create)
+{
+ val = cpu_to_fdt32(val);
+ do_fixup(fdt, node, prop, &val, sizeof(val), create);
+}
+
+void ft_cpu_setup (void *blob, bd_t *bd)
+{
+ char * cpu_path = "/cpus/" OF_CPU;
+
+ do_fixup_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
+ do_fixup_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
+ do_fixup_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
+}
+#endif /* CONFIG_OF_LIBFDT */
{
cpu/mpc8260/start.o (.text)
*(.text)
+ *(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
# MA 02111-1307 USA
#
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_CPPFLAGS += -DCONFIG_MPC83XX -DCONFIG_E300 \
-ffixed-r2 -ffixed-r29 -msoft-float
{
cpu/mpc83xx/start.o (.text)
*(.text)
+ *(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
* Initiate hard reset in debug control register DBCR0
* Make sure MSR[DE] = 1
*/
- unsigned long val;
+ unsigned long val, msr;
+
+ msr = mfmsr ();
+ msr |= MSR_DE;
+ mtmsr (msr);
+
val = mfspr(DBCR0);
val |= 0x70000000;
mtspr(DBCR0,val);
bdnz 0b
/* Clear and set up some registers. */
+ li r0,0
+ mtmsr r0
li r0,0x0000
lis r1,0xffff
mtspr DEC,r0 /* prevent dec exceptions */
*/
lis r3,CFG_INIT_RAM_ADDR@h
ori r3,r3,CFG_INIT_RAM_ADDR@l
- li r2,512 /* 512*32=16K */
+ li r2,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE))
mtctr r2
li r0,0
1:
dcbz r0,r3
dcbtls 0,r0,r3
- addi r3,r3,32
+ addi r3,r3,CFG_CACHELINE_SIZE
bdnz 1b
/* Jump out the last 4K page and continue to 'normal' start */
#ifdef CFG_RAMBOOT
- bl 3f
b _start_cont
#else
/* Calculate absolute address in FLASH and jump there */
ori r3,r3,CFG_MONITOR_BASE@l
addi r3,r3,_start_cont - _start + _START_OFFSET
mtlr r3
+ blr
#endif
-3: li r0,0
- mtspr SRR1,r0 /* Keep things disabled for now */
- mflr r1
- mtspr SRR0,r1
- rfi
- isync
-
.text
.globl _start
_start:
.globl out8
out8:
stb r4,0x0000(r3)
+ sync
blr
/*------------------------------------------------------------------------------- */
.globl out16
out16:
sth r4,0x0000(r3)
+ sync
blr
/*------------------------------------------------------------------------------- */
.globl out16r
out16r:
sthbrx r4,r0,r3
+ sync
blr
/*------------------------------------------------------------------------------- */
.globl out32
out32:
stw r4,0x0000(r3)
+ sync
blr
/*------------------------------------------------------------------------------- */
.globl out32r
out32r:
stwbrx r4,r0,r3
+ sync
blr
/*------------------------------------------------------------------------------- */
/* invalidate the INIT_RAM section */
lis r3,(CFG_INIT_RAM_ADDR & ~31)@h
ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l
- li r4,512
+ li r4,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE))
mtctr r4
1: icbi r0,r3
dcbi r0,r3
- addi r3,r3,32
+ addi r3,r3,CFG_CACHELINE_SIZE
bdnz 1b
sync /* Wait for all icbi to complete on bus */
isync
static inline void
soft_restart(unsigned long addr)
{
-#ifndef CONFIG_MPC8641HPCN
+#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
/*
* SRR0 has system reset vector, SRR1 has default MSR value
void
do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
-#ifndef CONFIG_MPC8641HPCN
+#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
#ifdef CFG_RESET_ADDRESS
ulong addr = CFG_RESET_ADDRESS;
* Read both dimm slots and decide whether
* or not to enable this controller.
*/
- memset((void *)&spd1,0,sizeof(spd1));
- memset((void *)&spd2,0,sizeof(spd2));
+ memset((void *)&spd1, 0, sizeof(spd1));
+ memset((void *)&spd2, 0, sizeof(spd2));
if (ddr_num == 1) {
CFG_READ_SPD(SPD_EEPROM_ADDRESS1,
0, 1, (uchar *) &spd1, sizeof(spd1));
+#if defined(SPD_EEPROM_ADDRESS2)
CFG_READ_SPD(SPD_EEPROM_ADDRESS2,
0, 1, (uchar *) &spd2, sizeof(spd2));
+#endif
} else {
+#if defined(SPD_EEPROM_ADDRESS3)
CFG_READ_SPD(SPD_EEPROM_ADDRESS3,
0, 1, (uchar *) &spd1, sizeof(spd1));
+#endif
+#if defined(SPD_EEPROM_ADDRESS4)
CFG_READ_SPD(SPD_EEPROM_ADDRESS4,
0, 1, (uchar *) &spd2, sizeof(spd2));
+#endif
}
/*
{
int memsize_ddr1_dimm1 = 0;
int memsize_ddr1_dimm2 = 0;
+ int memsize_ddr1 = 0;
+ unsigned int law_size_ddr1;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+#ifdef CONFIG_DDR_INTERLEAVE
+ volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
+#endif
+
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
int memsize_ddr2_dimm1 = 0;
int memsize_ddr2_dimm2 = 0;
- int memsize_total = 0;
- int memsize_ddr1 = 0;
int memsize_ddr2 = 0;
+ unsigned int law_size_ddr2;
+#endif
+
unsigned int ddr1_enabled = 0;
unsigned int ddr2_enabled = 0;
- unsigned int law_size_ddr1;
- unsigned int law_size_ddr2;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+ int memsize_total = 0;
#ifdef CONFIG_DDR_INTERLEAVE
unsigned int law_size_interleaved;
- volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2;
memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
(unsigned int)memsize_total * 1024*1024);
memsize_total += memsize_ddr1_dimm1;
+#if defined(SPD_EEPROM_ADDRESS2)
memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2,
1, 2,
(unsigned int)memsize_total * 1024*1024);
+#endif
memsize_total += memsize_ddr1_dimm2;
/*
debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
}
+
+ debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2);
+
#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
- debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n",
- memsize_ddr1, memsize_ddr2);
+ debug("\nMemory size of DDR1 = 0x%08lx\n", memsize_ddr1);
/*
* If neither DDR controller is enabled return 0.
DECLARE_GLOBAL_DATA_PTR;
+/* used in some defintiions of CONFIG_SYS_CLK_FREQ */
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+
void get_sys_info(sys_info_t *sysInfo)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
return 0;
-
+
address = pcie_get_base(hose, devfn);
offset += devfn << 4;
int offset, int len, u32 val) {
u8 *address;
-
+
/*
* Bus numbers are relative to hose->first_busno
*/
devfn -= PCI_BDF(hose->first_busno, 0, 0);
-
+
/*
* Same constraints as in pcie_read_config().
*/
if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
return 0;
-
+
address = pcie_get_base(hose, devfn);
offset += devfn << 4;
in_le16((u16 *)(mbase + PCI_COMMAND)) |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
printf("PCIE:%d successfully set as rootpoint\n",port);
-
+
/* Set Device and Vendor Id */
switch (port) {
case 0:
#define BI_PHYMODE_MII 7
#endif
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || \
+ defined(CONFIG_440GRX) || defined(CONFIG_440SP)
#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
#endif
int ethgroup = -1;
#endif
#endif
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
unsigned long mfr;
#endif
__asm__ volatile ("eieio");
/* reset emac so we have access to the phy */
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/* provide clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
if (failsafe <= 0)
printf("\nProblem resetting EMAC!\n");
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/* remove clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
/* set speed */
if (speed == _1000BASET) {
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
unsigned long pfc1;
mfsdr (sdr_pfc1, pfc1);
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
-msoft-float
-#PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100
-PLATFORM_CPPFLAGS += -march=armv5 -mtune=xscale
+PLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale
# =========================================================================
#
# Supply options according to compiler version
uchar i2c_reg_read (uchar chip, uchar reg)
{
- char buf;
+ uchar buf;
PRINTD(("i2c_reg_read(chip=0x%02x, reg=0x%02x)\n",chip,reg));
i2c_read(chip, reg, 1, &buf, 1);
/* FIXME fill in the correct size (is set to 32MByte) */
mmc_dev.blksz = 512;
mmc_dev.lba = 0x10000;
- sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x",
+ sprintf((char*)mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x",
cid->id[0], cid->id[1], cid->id[2],
cid->sn[0], cid->sn[1], cid->sn[2]);
- sprintf(mmc_dev.product,"%s",cid->name);
- sprintf(mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev);
+ sprintf((char*)mmc_dev.product,"%s",cid->name);
+ sprintf((char*)mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev);
mmc_dev.removable = 0;
mmc_dev.block_read = mmc_bread;
DECLARE_GLOBAL_DATA_PTR;
-#define FFUART 0
-#define BTUART 1
-#define STUART 2
+#define FFUART_INDEX 0
+#define BTUART_INDEX 1
+#define STUART_INDEX 2
#ifndef CONFIG_SERIAL_MULTI
#if defined (CONFIG_FFUART)
-#define UART_INDEX FFUART
+#define UART_INDEX FFUART_INDEX
#elif defined (CONFIG_BTUART)
-#define UART_INDEX BTUART
+#define UART_INDEX BTUART_INDEX
#elif defined (CONFIG_STUART)
-#define UART_INDEX STUART
+#define UART_INDEX STUART_INDEX
#else
#error "Bad: you didn't configure serial ..."
#endif
hang ();
switch (uart_index) {
- case FFUART:
+ case FFUART_INDEX:
#ifdef CONFIG_CPU_MONAHANS
CKENA |= CKENA_22_FFUART;
#else
FFIER = IER_UUE; /* Enable FFUART */
break;
- case BTUART:
+ case BTUART_INDEX:
#ifdef CONFIG_CPU_MONAHANS
CKENA |= CKENA_21_BTUART;
#else
break;
- case STUART:
+ case STUART_INDEX:
#ifdef CONFIG_CPU_MONAHANS
CKENA |= CKENA_23_STUART;
#else
void pxa_putc_dev (unsigned int uart_index,const char c)
{
switch (uart_index) {
- case FFUART:
+ case FFUART_INDEX:
/* wait for room in the tx FIFO on FFUART */
while ((FFLSR & LSR_TEMT) == 0)
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
FFTHR = c;
break;
- case BTUART:
+ case BTUART_INDEX:
while ((BTLSR & LSR_TEMT ) == 0 )
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
BTTHR = c;
break;
- case STUART:
+ case STUART_INDEX:
while ((STLSR & LSR_TEMT ) == 0 )
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
STTHR = c;
int pxa_tstc_dev (unsigned int uart_index)
{
switch (uart_index) {
- case FFUART:
+ case FFUART_INDEX:
return FFLSR & LSR_DR;
- case BTUART:
+ case BTUART_INDEX:
return BTLSR & LSR_DR;
- case STUART:
+ case STUART_INDEX:
return STLSR & LSR_DR;
}
return -1;
int pxa_getc_dev (unsigned int uart_index)
{
switch (uart_index) {
- case FFUART:
+ case FFUART_INDEX:
while (!(FFLSR & LSR_DR))
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
return (char) FFRBR & 0xff;
- case BTUART:
+ case BTUART_INDEX:
while (!(BTLSR & LSR_DR))
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
return (char) BTRBR & 0xff;
- case STUART:
+ case STUART_INDEX:
while (!(STLSR & LSR_DR))
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
return (char) STRBR & 0xff;
#if defined (CONFIG_FFUART)
static int ffuart_init(void)
{
- return pxa_init_dev(FFUART);
+ return pxa_init_dev(FFUART_INDEX);
}
static void ffuart_setbrg(void)
{
- return pxa_setbrg_dev(FFUART);
+ return pxa_setbrg_dev(FFUART_INDEX);
}
static void ffuart_putc(const char c)
{
- return pxa_putc_dev(FFUART,c);
+ return pxa_putc_dev(FFUART_INDEX,c);
}
static void ffuart_puts(const char *s)
{
- return pxa_puts_dev(FFUART,s);
+ return pxa_puts_dev(FFUART_INDEX,s);
}
static int ffuart_getc(void)
{
- return pxa_getc_dev(FFUART);
+ return pxa_getc_dev(FFUART_INDEX);
}
static int ffuart_tstc(void)
{
- return pxa_tstc_dev(FFUART);
+ return pxa_tstc_dev(FFUART_INDEX);
}
struct serial_device serial_ffuart_device =
#if defined (CONFIG_BTUART)
static int btuart_init(void)
{
- return pxa_init_dev(BTUART);
+ return pxa_init_dev(BTUART_INDEX);
}
static void btuart_setbrg(void)
{
- return pxa_setbrg_dev(BTUART);
+ return pxa_setbrg_dev(BTUART_INDEX);
}
static void btuart_putc(const char c)
{
- return pxa_putc_dev(BTUART,c);
+ return pxa_putc_dev(BTUART_INDEX,c);
}
static void btuart_puts(const char *s)
{
- return pxa_puts_dev(BTUART,s);
+ return pxa_puts_dev(BTUART_INDEX,s);
}
static int btuart_getc(void)
{
- return pxa_getc_dev(BTUART);
+ return pxa_getc_dev(BTUART_INDEX);
}
static int btuart_tstc(void)
{
- return pxa_tstc_dev(BTUART);
+ return pxa_tstc_dev(BTUART_INDEX);
}
struct serial_device serial_btuart_device =
#if defined (CONFIG_STUART)
static int stuart_init(void)
{
- return pxa_init_dev(STUART);
+ return pxa_init_dev(STUART_INDEX);
}
static void stuart_setbrg(void)
{
- return pxa_setbrg_dev(STUART);
+ return pxa_setbrg_dev(STUART_INDEX);
}
static void stuart_putc(const char c)
{
- return pxa_putc_dev(STUART,c);
+ return pxa_putc_dev(STUART_INDEX,c);
}
static void stuart_puts(const char *s)
{
- return pxa_puts_dev(STUART,s);
+ return pxa_puts_dev(STUART_INDEX,s);
}
static int stuart_getc(void)
{
- return pxa_getc_dev(STUART);
+ return pxa_getc_dev(STUART_INDEX);
}
static int stuart_tstc(void)
{
- return pxa_tstc_dev(STUART);
+ return pxa_tstc_dev(STUART_INDEX);
}
struct serial_device serial_stuart_device =
/* */
/****************************************************************************/
/* mk@tbd: Fix this! */
-#ifdef CONFIG_CPU_MONAHANS
+#if defined(CONFIG_PXA250) || defined(CONFIG_CPU_MONAHANS)
#undef ICMR
#undef OSMR3
#undef OSCR
#undef OWER
#undef OIER
#endif
+#ifdef CONFIG_PXA250
+#undef RCSR
+#undef CCCR
+#endif
/* Interrupt-Controller base address */
IC_BASE: .word 0x40d00000
# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
#include <asm/arch/pxa-regs.h>
+#include <usb.h>
-int usb_cpu_init()
+int usb_cpu_init(void)
{
#if defined(CONFIG_CPU_MONAHANS)
/* Enable USB host clock. */
return 0;
}
-int usb_cpu_stop()
+int usb_cpu_stop(void)
{
+ UHCHR |= UHCHR_FHR;
+ udelay(11);
+ UHCHR &= ~UHCHR_FHR;
+
+ UHCCOMS |= 1;
+ udelay(10);
+
+#if defined(CONFIG_CPU_MONAHANS)
+ UHCHR |= UHCHR_SSEP0;
+#endif
+#if defined(CONFIG_PXA27X)
+ UHCHR |= UHCHR_SSEP2;
+#endif
+ UHCHR |= UHCHR_SSEP1;
+ UHCHR |= UHCHR_SSE;
+
return 0;
}
-int usb_cpu_init_fail()
+int usb_cpu_init_fail(void)
{
return 0;
}
LIB = $(obj)libdisk.a
-COBJS = part.o part_mac.o part_dos.o part_iso.o part_amiga.o
+COBJS-y += part.o
+COBJS-y += part_mac.o
+COBJS-y += part_dos.o
+COBJS-y += part_iso.o
+COBJS-y += part_amiga.o
+COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
LIB = $(obj)libdrivers.a
-COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o atmel_usart.o \
- bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
- cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
- e1000.o eepro100.o enc28j60.o \
- i8042.o inca-ip_sw.o isp116x-hcd.o keyboard.o \
- lan91c96.o macb.o \
- natsemi.o ne2000.o netarm_eth.o netconsole.o \
- ns16550.o ns8382x.o ns87308.o ns7520_eth.o omap1510_i2c.o \
- omap24xx_i2c.o pci.o pci_auto.o pci_indirect.o \
- pcnet.o plb2800_eth.o \
- ps2ser.o ps2mult.o pc_keyb.o \
- rtl8019.o rtl8139.o rtl8169.o \
- s3c4510b_eth.o s3c4510b_uart.o \
- sed13806.o sed156x.o \
- serial.o serial_max3100.o serial_sh.o \
- serial_pl010.o serial_pl011.o serial_xuartlite.o \
- sil680.o sl811_usb.o sm501.o smc91111.o smiLynxEM.o \
- status_led.o sym53c8xx.o systemace.o ahci.o \
- ti_pci1410a.o tigon3.o tsec.o \
- tsi108_eth.o tsi108_i2c.o tsi108_pci.o \
- usb_ohci.o \
- usbdcore.o usbdcore_ep0.o usbdcore_mpc8xx.o usbdcore_omap1510.o \
- usbtty.o \
- videomodes.o w83c553f.o \
- ks8695eth.o \
- pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \
- rpx_pcmcia.o \
- fsl_i2c.o fsl_pci_init.o ati_radeon_fb.o
+COBJS-y += ali512x.o
+COBJS-y += ds1722.o
+COBJS-y += ns87308.o
+COBJS-y += status_led.o
+#
+# Block and Flash Drivers
+#
+COBJS-y += ahci.o
+COBJS-y += at45.o
+COBJS-y += ata_piix.o
+COBJS-y += cfi_flash.o
+COBJS-y += dataflash.o
+COBJS-y += mw_eeprom.o
+COBJS-y += sil680.o
+COBJS-y += sym53c8xx.o
+COBJS-y += systemace.o
+
+#
+# Console Drivers
+#
+COBJS-y += ati_radeon_fb.o
+COBJS-y += atmel_usart.o
+COBJS-y += cfb_console.o
+COBJS-y += ct69000.o
+COBJS-y += i8042.o
+COBJS-y += keyboard.o
+COBJS-y += netconsole.o
+COBJS-y += ns16550.o
+COBJS-y += pc_keyb.o
+COBJS-y += ps2ser.o
+COBJS-y += ps2mult.o
+COBJS-y += s3c4510b_uart.o
+COBJS-y += sed13806.o
+COBJS-y += sed156x.o
+COBJS-y += serial.o
+COBJS-y += serial_max3100.o
+COBJS-y += serial_xuartlite.o
+COBJS-y += sm501.o
+COBJS-y += smiLynxEM.o
+COBJS-y += usbtty.o
+COBJS-y += videomodes.o
+
+#
+# I2C Drivers
+#
+COBJS-y += omap1510_i2c.o
+COBJS-y += omap24xx_i2c.o
+COBJS-y += tsi108_i2c.o
+COBJS-y += fsl_i2c.o
+
+#
+# Network Drivers
+#
+COBJS-y += 3c589.o
+COBJS-y += bcm570x.o bcm570x_autoneg.o 5701rls.o
+COBJS-y += cs8900.o
+COBJS-y += dc2114x.o
+COBJS-y += dm9000x.o
+COBJS-y += e1000.o
+COBJS-y += eepro100.o
+COBJS-y += enc28j60.o
+COBJS-y += inca-ip_sw.o
+COBJS-y += ks8695eth.o
+COBJS-y += lan91c96.o
+COBJS-y += macb.o
+COBJS-y += natsemi.o
+COBJS-y += ne2000.o
+COBJS-y += netarm_eth.o
+COBJS-y += ns7520_eth.o
+COBJS-y += ns8382x.o
+COBJS-y += pcnet.o
+COBJS-y += plb2800_eth.o
+COBJS-y += rtl8019.o
+COBJS-y += rtl8139.o
+COBJS-y += rtl8169.o
+COBJS-y += s3c4510b_eth.o
+COBJS-y += smc91111.o
+COBJS-y += tigon3.o
+COBJS-y += tsec.o
+COBJS-y += tsi108_eth.o
+COBJS-y += uli526x.o
+
+#
+# PCI/PCMCIA device drivers
+#
+COBJS-y += fsl_pci_init.o
+COBJS-y += mpc8xx_pcmcia.o
+COBJS-y += pci.o
+COBJS-y += pci_auto.o
+COBJS-y += pci_indirect.o
+COBJS-y += pxa_pcmcia.o
+COBJS-y += rpx_pcmcia.o
+COBJS-y += ti_pci1410a.o
+COBJS-y += tqm8xx_pcmcia.o
+COBJS-y += tsi108_pci.o
+COBJS-y += w83c553f.o
+
+#
+# USB Drivers
+#
+COBJS-y += isp116x-hcd.o
+COBJS-y += sl811_usb.o
+COBJS-y += usb_ohci.o
+COBJS-y += usbdcore.o
+COBJS-y += usbdcore_ep0.o
+COBJS-y += usbdcore_mpc8xx.o
+COBJS-y += usbdcore_omap1510.o
+
+#
+# Miscellaneous Drivers
+#
+COBJS-y += ali512x.o
+COBJS-y += ns87308.o
+COBJS-y += status_led.o
+
+COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
/*
* spi.c API
*/
-extern unsigned int AT91F_SpiWrite (AT91PS_DataflashDesc pDesc);
-extern void AT91F_SpiEnable(int cs);
+extern unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc);
+extern void AT91F_SpiEnable(int cs);
#define AT91C_TIMEOUT_WRDY 200000
-
/*----------------------------------------------------------------------*/
/* \fn AT91F_DataFlashSendCommand */
/* \brief Generic function to send a command to the dataflash */
/*----------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
- AT91PS_DataFlash pDataFlash,
- unsigned char OpCode,
- unsigned int CmdSize,
- unsigned int DataflashAddress)
+AT91S_DataFlashStatus AT91F_DataFlashSendCommand(AT91PS_DataFlash pDataFlash,
+ unsigned char OpCode,
+ unsigned int CmdSize,
+ unsigned int DataflashAddress)
{
unsigned int adr;
- if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
+ if ((pDataFlash->pDataFlashDesc->state) != IDLE)
return DATAFLASH_BUSY;
/* process the address to obtain page address and byte address */
adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) <<
- pDataFlash->pDevice->page_offset) + (DataflashAddress %
- (pDataFlash->pDevice->pages_size));
+ pDataFlash->pDevice->page_offset) +
+ (DataflashAddress % (pDataFlash->pDevice->pages_size));
- /* fill the command buffer */
+ /* fill the command buffer */
pDataFlash->pDataFlashDesc->command[0] = OpCode;
if (pDataFlash->pDevice->pages_number >= 16384) {
pDataFlash->pDataFlashDesc->command[1] =
pDataFlash->pDataFlashDesc->command[7] = 0;
/* Initialize the SpiData structure for the spi write fuction */
- pDataFlash->pDataFlashDesc->tx_cmd_pt =
+ pDataFlash->pDataFlashDesc->tx_cmd_pt =
pDataFlash->pDataFlashDesc->command;
- pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize;
- pDataFlash->pDataFlashDesc->rx_cmd_pt =
+ pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize;
+ pDataFlash->pDataFlashDesc->rx_cmd_pt =
pDataFlash->pDataFlashDesc->command;
- pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize;
+ pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize;
/* send the command and read the data */
- return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); }
-
+ return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
+}
/*----------------------------------------------------------------------*/
/* \fn AT91F_DataFlashGetStatus */
AT91S_DataFlashStatus status;
/* if a transfert is in progress ==> return 0 */
- if( (pDesc->state) != IDLE)
+ if ((pDesc->state) != IDLE)
return DATAFLASH_BUSY;
/* first send the read status command (D7H) */
pDesc->command[0] = DB_STATUS;
pDesc->command[1] = 0;
- pDesc->DataFlash_state = GET_STATUS;
- pDesc->tx_data_size = 0; /* Transmit the command */
- /* and receive response */
- pDesc->tx_cmd_pt = pDesc->command;
- pDesc->rx_cmd_pt = pDesc->command;
- pDesc->rx_cmd_size = 2;
- pDesc->tx_cmd_size = 2;
- status = AT91F_SpiWrite (pDesc);
+ pDesc->DataFlash_state = GET_STATUS;
+ pDesc->tx_data_size = 0; /* Transmit the command */
+ /* and receive response */
+ pDesc->tx_cmd_pt = pDesc->command;
+ pDesc->rx_cmd_pt = pDesc->command;
+ pDesc->rx_cmd_size = 2;
+ pDesc->tx_cmd_size = 2;
+ status = AT91F_SpiWrite(pDesc);
- pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
+ pDesc->DataFlash_state = *((unsigned char *)(pDesc->rx_cmd_pt) + 1);
return status;
}
-
/*----------------------------------------------------------------------*/
/* \fn AT91F_DataFlashWaitReady */
/* \brief wait for dataflash ready (bit7 of the status register == 1) */
/*----------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc
-pDataFlashDesc, unsigned int timeout)
+ pDataFlashDesc,
+ unsigned int timeout)
{
pDataFlashDesc->DataFlash_state = IDLE;
do {
AT91F_DataFlashGetStatus(pDataFlashDesc);
timeout--;
- } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) &&
- (timeout > 0) );
+ } while (((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) &&
+ (timeout > 0));
- if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
+ if ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
return DATAFLASH_ERROR;
return DATAFLASH_OK;
}
-
/*--------------------------------------------------------------------------*/
/* Function Name : AT91F_DataFlashContinuousRead */
/* Object : Continuous stream Read */
/* : <sizeToRead> = data buffer size */
/* Return value : State of the dataflash */
/*--------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
- AT91PS_DataFlash pDataFlash,
- int src,
- unsigned char *dataBuffer,
- int sizeToRead )
+AT91S_DataFlashStatus AT91F_DataFlashContinuousRead(
+ AT91PS_DataFlash pDataFlash,
+ int src,
+ unsigned char *dataBuffer,
+ int sizeToRead)
{
AT91S_DataFlashStatus status;
/* Test the size to read in the device */
- if ( (src + sizeToRead) >
- (pDataFlash->pDevice->pages_size *
- (pDataFlash->pDevice->pages_number)))
+ if ((src + sizeToRead) >
+ (pDataFlash->pDevice->pages_size *
+ (pDataFlash->pDevice->pages_number)))
return DATAFLASH_MEMORY_OVERFLOW;
pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;
- status = AT91F_DataFlashSendCommand
- (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
+ status = AT91F_DataFlashSendCommand(
+ pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
/* Send the command to the dataflash */
- return(status);
+ return (status);
}
-
/*---------------------------------------------------------------------------*/
/* Function Name : AT91F_DataFlashPagePgmBuf */
/* Object : Main memory page program thru buffer 1 or buffer 2 */
/* : <SizeToWrite> = data buffer size */
/* Return value : State of the dataflash */
/*---------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
- AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- unsigned int dest,
- unsigned int SizeToWrite)
+AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ unsigned int dest,
+ unsigned int SizeToWrite)
{
int cmdsize;
pDataFlash->pDataFlashDesc->tx_data_pt = src;
/* Send the command to the dataflash */
if (pDataFlash->pDevice->pages_number >= 16384)
cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1,
-cmdsize, dest)); }
-
+ return (AT91F_DataFlashSendCommand(
+ pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest));
+}
/*---------------------------------------------------------------------------*/
/* Function Name : AT91F_MainMemoryToBufferTransfert */
/* Return value : State of the dataflash */
/*---------------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
- AT91PS_DataFlash pDataFlash,
- unsigned char BufferCommand,
- unsigned int page)
+ AT91PS_DataFlash
+ pDataFlash,
+ unsigned char
+ BufferCommand,
+ unsigned int page)
{
int cmdsize;
/* Test if the buffer command is legal */
- if ((BufferCommand != DB_PAGE_2_BUF1_TRF)
- && (BufferCommand != DB_PAGE_2_BUF2_TRF))
+ if ((BufferCommand != DB_PAGE_2_BUF1_TRF) &&
+ (BufferCommand != DB_PAGE_2_BUF2_TRF)) {
return DATAFLASH_BAD_COMMAND;
+ }
/* no data to transmit or receive */
pDataFlash->pDataFlashDesc->tx_data_size = 0;
cmdsize = 4;
if (pDataFlash->pDevice->pages_number >= 16384)
cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize,
-page*pDataFlash->pDevice->pages_size));
+ return (AT91F_DataFlashSendCommand(
+ pDataFlash, BufferCommand, cmdsize,
+ page * pDataFlash->pDevice->pages_size));
}
-
/*-------------------------------------------------------------------------- */
/* Function Name : AT91F_DataFlashWriteBuffer */
/* Object : Write data to the internal sram buffer 1 or 2 */
/* : <SizeToWrite> = data buffer size */
/* Return value : State of the dataflash */
/*---------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
- AT91PS_DataFlash pDataFlash,
- unsigned char BufferCommand,
- unsigned char *dataBuffer,
- unsigned int bufferAddress,
- int SizeToWrite )
+AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char BufferCommand,
+ unsigned char *dataBuffer,
+ unsigned int bufferAddress,
+ int SizeToWrite)
{
int cmdsize;
/* Test if the buffer command is legal */
- if ((BufferCommand != DB_BUF1_WRITE)
- && (BufferCommand != DB_BUF2_WRITE))
+ if ((BufferCommand != DB_BUF1_WRITE) &&
+ (BufferCommand != DB_BUF2_WRITE)) {
return DATAFLASH_BAD_COMMAND;
+ }
/* buffer address must be lower than page size */
if (bufferAddress > pDataFlash->pDevice->pages_size)
return DATAFLASH_BAD_ADDRESS;
- if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
+ if ((pDataFlash->pDataFlashDesc->state) != IDLE)
return DATAFLASH_BUSY;
/* Send first Write Command */
pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
pDataFlash->pDataFlashDesc->command[1] = 0;
if (pDataFlash->pDevice->pages_number >= 16384) {
- pDataFlash->pDataFlashDesc->command[2] = 0;
- pDataFlash->pDataFlashDesc->command[3] =
+ pDataFlash->pDataFlashDesc->command[2] = 0;
+ pDataFlash->pDataFlashDesc->command[3] =
(unsigned char)(((unsigned int)(bufferAddress &
- pDataFlash->pDevice->byte_mask)) >> 8);
- pDataFlash->pDataFlashDesc->command[4] =
- (unsigned char)((unsigned int)bufferAddress & 0x00FF);
+ pDataFlash->pDevice->
+ byte_mask)) >> 8);
+ pDataFlash->pDataFlashDesc->command[4] =
+ (unsigned char)((unsigned int)bufferAddress & 0x00FF);
cmdsize = 5;
} else {
- pDataFlash->pDataFlashDesc->command[2] =
+ pDataFlash->pDataFlashDesc->command[2] =
(unsigned char)(((unsigned int)(bufferAddress &
- pDataFlash->pDevice->byte_mask)) >> 8);
- pDataFlash->pDataFlashDesc->command[3] =
- (unsigned char)((unsigned int)bufferAddress & 0x00FF);
- pDataFlash->pDataFlashDesc->command[4] = 0;
+ pDataFlash->pDevice->
+ byte_mask)) >> 8);
+ pDataFlash->pDataFlashDesc->command[3] =
+ (unsigned char)((unsigned int)bufferAddress & 0x00FF);
+ pDataFlash->pDataFlashDesc->command[4] = 0;
cmdsize = 4;
}
- pDataFlash->pDataFlashDesc->tx_cmd_pt =
+ pDataFlash->pDataFlashDesc->tx_cmd_pt =
pDataFlash->pDataFlashDesc->command;
pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize;
- pDataFlash->pDataFlashDesc->rx_cmd_pt =
+ pDataFlash->pDataFlashDesc->rx_cmd_pt =
pDataFlash->pDataFlashDesc->command;
pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize;
- pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
- pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
- pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
- pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite;
+ pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
+ pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
+ pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
+ pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite;
return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
}
/* Return value : State of the dataflash */
/*---------------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_PageErase(
- AT91PS_DataFlash pDataFlash,
- unsigned int page)
+ AT91PS_DataFlash pDataFlash,
+ unsigned int page)
{
int cmdsize;
/* Test if the buffer command is legal */
/* no data to transmit or receive */
- pDataFlash->pDataFlashDesc->tx_data_size = 0;
+ pDataFlash->pDataFlashDesc->tx_data_size = 0;
cmdsize = 4;
if (pDataFlash->pDevice->pages_number >= 16384)
cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize,
-page*pDataFlash->pDevice->pages_size));
+ return (AT91F_DataFlashSendCommand(pDataFlash,
+ DB_PAGE_ERASE, cmdsize,
+ page * pDataFlash->pDevice->pages_size));
}
-
/*---------------------------------------------------------------------------*/
/* Function Name : AT91F_BlockErase */
/* Object : Erase a Block */
/* Return value : State of the dataflash */
/*---------------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_BlockErase(
- AT91PS_DataFlash pDataFlash,
- unsigned int block)
+ AT91PS_DataFlash pDataFlash,
+ unsigned int block)
{
int cmdsize;
/* Test if the buffer command is legal */
/* no data to transmit or receive */
- pDataFlash->pDataFlashDesc->tx_data_size = 0;
+ pDataFlash->pDataFlashDesc->tx_data_size = 0;
cmdsize = 4;
if (pDataFlash->pDevice->pages_number >= 16384)
cmdsize = 5;
- return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize,
-block*8*pDataFlash->pDevice->pages_size));
+ return (AT91F_DataFlashSendCommand(pDataFlash, DB_BLOCK_ERASE, cmdsize,
+ block * 8 *
+ pDataFlash->pDevice->pages_size));
}
/*---------------------------------------------------------------------------*/
/* : <dest> = main memory address */
/* Return value : State of the dataflash */
/*---------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_WriteBufferToMain (
- AT91PS_DataFlash pDataFlash,
- unsigned char BufferCommand,
- unsigned int dest )
+AT91S_DataFlashStatus AT91F_WriteBufferToMain(AT91PS_DataFlash pDataFlash,
+ unsigned char BufferCommand,
+ unsigned int dest)
{
int cmdsize;
/* Test if the buffer command is correct */
if ((BufferCommand != DB_BUF1_PAGE_PGM) &&
- (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
- (BufferCommand != DB_BUF2_PAGE_PGM) &&
- (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )
+ (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
+ (BufferCommand != DB_BUF2_PAGE_PGM) &&
+ (BufferCommand != DB_BUF2_PAGE_ERASE_PGM))
return DATAFLASH_BAD_COMMAND;
/* no data to transmit or receive */
if (pDataFlash->pDevice->pages_number >= 16384)
cmdsize = 5;
/* Send the command to the dataflash */
- return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize,
- dest)); }
-
+ return (AT91F_DataFlashSendCommand(pDataFlash, BufferCommand,
+ cmdsize, dest));
+}
/*---------------------------------------------------------------------------*/
/* Function Name : AT91F_PartialPageWrite */
/* : <AdrInpage> = adr to begin the fading */
/* : <length> = Number of bytes to erase */
/*---------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_PartialPageWrite (
- AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- unsigned int dest,
- unsigned int size)
+AT91S_DataFlashStatus AT91F_PartialPageWrite(AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ unsigned int dest,
+ unsigned int size)
{
unsigned int page;
unsigned int AdrInPage;
AdrInPage = dest % (pDataFlash->pDevice->pages_size);
/* Read the contents of the page in the Sram Buffer */
- AT91F_MainMemoryToBufferTransfert(pDataFlash,
- DB_PAGE_2_BUF1_TRF, page);
+ AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page);
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
- AT91C_TIMEOUT_WRDY);
+ AT91C_TIMEOUT_WRDY);
/*Update the SRAM buffer */
AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src,
AdrInPage, size);
AT91F_PageErase(pDataFlash, page);
/* Rewrite the modified Sram Buffer in the main memory */
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
- AT91C_TIMEOUT_WRDY);
+ AT91C_TIMEOUT_WRDY);
}
/* Rewrite the modified Sram Buffer in the main memory */
- return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM,
- (page*pDataFlash->pDevice->pages_size)));
+ return (AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM,
+ (page *
+ pDataFlash->pDevice->pages_size)));
}
/*---------------------------------------------------------------------------*/
/* : <dest> = dataflash adress */
/* : <size> = data buffer size */
/*---------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWrite(
- AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- int dest,
- int size )
+AT91S_DataFlashStatus AT91F_DataFlashWrite(AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ int dest, int size)
{
unsigned int length;
unsigned int page;
AT91F_SpiEnable(pDataFlash->pDevice->cs);
- if ( (dest + size) > (pDataFlash->pDevice->pages_size *
- (pDataFlash->pDevice->pages_number)))
+ if ((dest + size) > (pDataFlash->pDevice->pages_size *
+ (pDataFlash->pDevice->pages_number)))
return DATAFLASH_MEMORY_OVERFLOW;
/* If destination does not fit a page start address */
- if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 )
- {
- length = pDataFlash->pDevice->pages_size -
- (dest %
- ((unsigned int)
- (pDataFlash->pDevice->pages_size)));
+ if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0) {
+ length =
+ pDataFlash->pDevice->pages_size -
+ (dest % ((unsigned int)(pDataFlash->pDevice->pages_size)));
if (size < length)
length = size;
- if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))
+ if (!AT91F_PartialPageWrite(pDataFlash, src, dest, length))
return DATAFLASH_ERROR;
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
- AT91C_TIMEOUT_WRDY);
+ AT91C_TIMEOUT_WRDY);
/* Update size, source and destination pointers */
size -= length;
src += length;
}
- while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
+ while ((size - pDataFlash->pDevice->pages_size) >= 0) {
/* program dataflash page */
page = (unsigned int)dest / (pDataFlash->pDevice->pages_size);
status = AT91F_DataFlashWriteBuffer(pDataFlash,
- DB_BUF1_WRITE, src, 0,
- pDataFlash->pDevice->pages_size);
+ DB_BUF1_WRITE, src, 0,
+ pDataFlash->pDevice->
+ pages_size);
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
- AT91C_TIMEOUT_WRDY);
+ AT91C_TIMEOUT_WRDY);
status = AT91F_PageErase(pDataFlash, page);
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
- AT91C_TIMEOUT_WRDY);
+ AT91C_TIMEOUT_WRDY);
if (!status)
return DATAFLASH_ERROR;
- status = AT91F_WriteBufferToMain (pDataFlash,
- DB_BUF1_PAGE_PGM, dest);
- if(!status)
+ status = AT91F_WriteBufferToMain(pDataFlash,
+ DB_BUF1_PAGE_PGM, dest);
+ if (!status)
return DATAFLASH_ERROR;
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
- AT91C_TIMEOUT_WRDY);
+ AT91C_TIMEOUT_WRDY);
/* Update size, source and destination pointers */
size -= pDataFlash->pDevice->pages_size;
dest += pDataFlash->pDevice->pages_size;
- src += pDataFlash->pDevice->pages_size;
+ src += pDataFlash->pDevice->pages_size;
}
/* If still some bytes to read */
- if ( size > 0 ) {
+ if (size > 0) {
/* program dataflash page */
- if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
+ if (!AT91F_PartialPageWrite(pDataFlash, src, dest, size))
return DATAFLASH_ERROR;
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
- AT91C_TIMEOUT_WRDY);
+ AT91C_TIMEOUT_WRDY);
}
return DATAFLASH_OK;
}
-
/*---------------------------------------------------------------------------*/
/* Function Name : AT91F_DataFlashRead */
/* Object : Read a block in dataflash */
/* Input Parameters : */
/* Return value : */
/*---------------------------------------------------------------------------*/
-int AT91F_DataFlashRead(
- AT91PS_DataFlash pDataFlash,
- unsigned long addr,
- unsigned long size,
- char *buffer)
+int AT91F_DataFlashRead(AT91PS_DataFlash pDataFlash,
+ unsigned long addr, unsigned long size, char *buffer)
{
unsigned long SizeToRead;
AT91F_SpiEnable(pDataFlash->pDevice->cs);
- if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
return -1;
while (size) {
- SizeToRead = (size < 0x8000)? size:0x8000;
+ SizeToRead = (size < 0x8000) ? size : 0x8000;
if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
- AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
+ AT91C_TIMEOUT_WRDY) !=
+ DATAFLASH_OK)
return -1;
- if (AT91F_DataFlashContinuousRead (pDataFlash, addr,
- (uchar *) buffer, SizeToRead) != DATAFLASH_OK)
+ if (AT91F_DataFlashContinuousRead(pDataFlash, addr,
+ (uchar *) buffer,
+ SizeToRead) != DATAFLASH_OK)
return -1;
size -= SizeToRead;
/* Input Parameters : */
/* Return value : Dataflash status register */
/*---------------------------------------------------------------------------*/
-int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) {
+int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
+{
AT91F_SpiEnable(cs);
AT91F_DataFlashGetStatus(pDesc);
- return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
+ return ((pDesc->command[1] == 0xFF) ? 0 : pDesc->command[1] & 0x3C);
}
#endif
u32 val;
} reg_val;
-
+#if 0 /* unused ? -> scheduled for removal */
/* these common regs are cleared before mode setting so they do not
* interfere with anything
*/
{ CAP0_TRIG_CNTL, 0 },
{ CAP1_TRIG_CNTL, 0 },
};
-
+#endif /* 0 */
void radeon_setmode(void)
{
- int i;
struct radeon_regs *mode = malloc(sizeof(struct radeon_regs));
mode->crtc_gen_cntl = 0x03000200;
radeon_write_pll_regs(rinfo, mode);
}
+#include "bios_emulator/include/biosemu.h"
+extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp);
+
int radeon_probe(struct radeonfb_info *rinfo)
{
pci_dev_t pdev;
else if (addr >= 0xFFFF5 && addr < 0xFFFFE) {
/* Return a faked BIOS date string for non-x86 machines */
DB(printf("BE_memaddr - Returning BIOS date\n");)
- return BE_biosDate + addr - 0xFFFF5;
+ return (u8 *)(BE_biosDate + addr - 0xFFFF5);
} else if (addr == 0xFFFFE) {
/* Return system model identifier for non-x86 machines */
DB(printf("BE_memaddr - Returning model\n");)
return 0;
}
- M.mem_base = (unsigned long)malloc(memSize);
+ M.mem_base = malloc(memSize);
if (M.mem_base == NULL){
printf("Biosemu:Out of memory!");
_BE_env.emulateVGA = 0;
_BE_env.busmem_base = (unsigned long)malloc(128 * 1024);
- if (_BE_env.busmem_base == NULL){
+ if ((void *)_BE_env.busmem_base == NULL){
printf("Biosemu:Out of memory!");
return 0;
}
void X86API BE_exit(void)
{
free(M.mem_base);
- free(_BE_env.busmem_base);
+ free((void *)_BE_env.busmem_base);
}
/****************************************************************************
#include <common.h>
-#include <ssi.h>
-
#ifdef CONFIG_DS1722
+#include <ssi.h>
+
static void ds1722_select(int dev)
{
ssi_set_interface(4096, 0, 0, 0);
u8 temp8;
int r;
int bridge;
+ int inbound = 0;
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr;
pci_dev_t dev = PCI_BDF(busno,0,0);
PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP |
(__ilog2(hose->regions[r].size) - 1);
pi++;
+ inbound = hose->regions[r].size > 0;
} else { /* Outbound */
po->powbar = (hose->regions[r].phys_start >> 12) & 0x000fffff;
po->potar = (hose->regions[r].bus_start >> 12) & 0x000fffff;
pciauto_setup_device(hose, dev, 0, hose->pci_mem,
hose->pci_prefetch, hose->pci_io);
+ if (inbound) {
+ pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND,
+ temp16 | PCI_COMMAND_MEMORY);
+ }
+
#ifndef CONFIG_PCI_NOSCAN
printf (" Scanning PCI bus %02x\n", hose->current_busno);
hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno);
struct isp116x isp116x_dev;
struct isp116x_platform_data isp116x_board;
-int got_rhsc = 0; /* root hub status change */
+static int got_rhsc; /* root hub status change */
struct usb_device *devgone; /* device which was disconnected */
-int rh_devnum = 0; /* address of Root Hub endpoint */
+static int rh_devnum; /* address of Root Hub endpoint */
/* ------------------------------------------------------------------------- */
done += PTD_GET_LEN(&ptd[i]);
cc = PTD_GET_CC(&ptd[i]);
- if (cc == TD_DATAUNDERRUN) { /* underrun is no error... */
- DBG("allowed data underrun");
- cc = TD_CC_NOERROR;
- }
- if (cc != TD_CC_NOERROR && ret == TD_CC_NOERROR)
+
+ /* Data underrun means basically that we had more buffer space than
+ * the function had data. It is perfectly normal but upper levels have
+ * to know how much we actually transferred.
+ */
+ if (cc == TD_NOTACCESSED ||
+ (cc != TD_CC_NOERROR && (ret == TD_CC_NOERROR || ret == TD_DATAUNDERRUN)))
ret = cc;
}
return ret;
}
-#define PTD_NUM 64 /* it should be enougth... */
-struct ptd ptd[PTD_NUM];
+/* With one PTD we can transfer almost 1K in one go;
+ * HC does the splitting into endpoint digestible transactions
+ */
+struct ptd ptd[1];
+
static inline int max_transfer_len(struct usb_device *dev, unsigned long pipe)
{
- return min(PTD_NUM * usb_maxpacket(dev, pipe), PTD_NUM * 16);
+ unsigned mpck = usb_maxpacket(dev, pipe);
+
+ /* One PTD can transfer 1023 bytes but try to always
+ * transfer multiples of endpoint buffer size
+ */
+ return 1023 / mpck * mpck;
}
/* Do an USB transfer
int max = usb_maxpacket(dev, pipe);
int dir_out = usb_pipeout(pipe);
int speed_low = usb_pipeslow(pipe);
- int i, done, stat, timeout, cc;
- int retries = 10;
+ int i, done = 0, stat, timeout, cc;
+
+ /* 500 frames or 0.5s timeout when function is busy and NAKs transactions for a while */
+ int retries = 500;
DBG("------------------------------------------------");
dump_msg(dev, pipe, buffer, len, "SUBMIT");
DBG("------------------------------------------------");
+ if (len >= 1024) {
+ ERR("Too big job");
+ dev->status = USB_ST_CRC_ERR;
+ return -1;
+ }
+
if (isp116x->disabled) {
ERR("EPIPE");
dev->status = USB_ST_CRC_ERR;
isp116x_write_reg32(isp116x, HCINTSTAT, 0xff);
/* Prepare the PTD data */
- done = 0;
- i = 0;
- do {
- ptd[i].count = PTD_CC_MSK | PTD_ACTIVE_MSK |
- PTD_TOGGLE(usb_gettoggle(dev, epnum, dir_out));
- ptd[i].mps = PTD_MPS(max) | PTD_SPD(speed_low) | PTD_EP(epnum);
- ptd[i].len = PTD_LEN(max > len - done ? len - done : max) |
- PTD_DIR(dir);
- ptd[i].faddr = PTD_FA(usb_pipedevice(pipe));
-
- usb_dotoggle(dev, epnum, dir_out);
- done += PTD_GET_LEN(&ptd[i]);
- i++;
- if (i >= PTD_NUM) {
- ERR("****** Cannot pack buffer! ******");
- dev->status = USB_ST_BUF_ERR;
- return -1;
- }
- } while (done < len);
- ptd[i - 1].mps |= PTD_LAST_MSK;
+ ptd->count = PTD_CC_MSK | PTD_ACTIVE_MSK |
+ PTD_TOGGLE(usb_gettoggle(dev, epnum, dir_out));
+ ptd->mps = PTD_MPS(max) | PTD_SPD(speed_low) | PTD_EP(epnum) | PTD_LAST_MSK;
+ ptd->len = PTD_LEN(len) | PTD_DIR(dir);
+ ptd->faddr = PTD_FA(usb_pipedevice(pipe));
+retry_same:
/* Pack data into FIFO ram */
- pack_fifo(isp116x, dev, pipe, ptd, i, buffer, len);
+ pack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len);
#ifdef EXTRA_DELAY
wait_ms(EXTRA_DELAY);
#endif
}
/* Unpack data from FIFO ram */
- cc = unpack_fifo(isp116x, dev, pipe, ptd, i, buffer, len);
+ cc = unpack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len);
+
+ i = PTD_GET_COUNT(ptd);
+ done += i;
+ buffer += i;
+ len -= i;
- /* Mmm... sometime we get 0x0f as cc which is a non sense!
- * Just retry the transfer...
+ /* There was some kind of real problem; Prepare the PTD again
+ * and retry from the failed transaction on
*/
- if (cc == 0x0f && retries-- > 0) {
- usb_dotoggle(dev, epnum, dir_out);
- goto retry;
+ if (cc && cc != TD_NOTACCESSED && cc != TD_DATAUNDERRUN) {
+ if (retries >= 100) {
+ retries -= 100;
+ /* The chip will have toggled the toggle bit for the failed
+ * transaction too. We have to toggle it back.
+ */
+ usb_settoggle(dev, epnum, dir_out, !PTD_GET_TOGGLE(ptd));
+ goto retry;
+ }
+ }
+ /* "Normal" errors; TD_NOTACCESSED would mean in effect that the function have NAKed
+ * the transactions from the first on for the whole frame. It may be busy and we retry
+ * with the same PTD. PTD_ACTIVE (and not TD_NOTACCESSED) would mean that some of the
+ * PTD didn't make it because the function was busy or the frame ended before the PTD
+ * finished. We prepare the rest of the data and try again.
+ */
+ else if (cc == TD_NOTACCESSED || PTD_GET_ACTIVE(ptd) || (cc != TD_DATAUNDERRUN && PTD_GET_COUNT(ptd) < PTD_GET_LEN(ptd))) {
+ if (retries) {
+ --retries;
+ if (cc == TD_NOTACCESSED && PTD_GET_ACTIVE(ptd) && !PTD_GET_COUNT(ptd)) goto retry_same;
+ usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd));
+ goto retry;
+ }
}
- if (cc != TD_CC_NOERROR) {
+ if (cc != TD_CC_NOERROR && cc != TD_DATAUNDERRUN) {
DBG("****** completition code error %x ******", cc);
switch (cc) {
case TD_CC_BITSTUFFING:
}
return -cc;
}
+ else usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd));
dump_msg(dev, pipe, buffer, len, "SUBMIT(ret)");
DBG("");
+ got_rhsc = rh_devnum = 0;
+
/* Init device registers addr */
isp116x->addr_reg = (u16 *) ISP116X_HCD_ADDR;
isp116x->data_reg = (u16 *) ISP116X_HCD_DATA;
/* Three-wire (MicroWire) serial eeprom driver (for 93C46 and compatibles) */
#include <common.h>
-#include <ssi.h>
-
#ifdef CONFIG_MW_EEPROM
+#include <ssi.h>
+
/*
* Serial EEPROM opcodes, including start bit
*/
LIB := $(obj)libnand.a
-COBJS := nand.o nand_base.o nand_ids.o nand_ecc.o nand_bbt.o nand_util.o
-
+COBJS-y += nand.o
+COBJS-y += nand_base.o
+COBJS-y += nand_ids.o
+COBJS-y += nand_ecc.o
+COBJS-y += nand_bbt.o
+COBJS-y += nand_util.o
+
+COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
{ /* SuperSocket RE450T */ 0x0110, 0x00, 0xe0, 0x98, 0 },
{ /* Volktek NPL-402CT */ 0x0060, 0x00, 0x40, 0x05, 0 },
{ /* NEC PC-9801N-J12 */ 0x0ff0, 0x00, 0x00, 0x4c, 0 },
- { /* PCMCIA Technology OEM */ 0x01c8, 0x00, 0xa0, 0x0c, 0 }
+ { /* PCMCIA Technology OEM */ 0x01c8, 0x00, 0xa0, 0x0c, 0 },
+ { /* Qemu */ 0x0, 0x52, 0x54, 0x00, 0 }
};
#define NR_INFO (sizeof(hw_info)/sizeof(hw_info_t))
PRINTK("nic base is %lx\n", nic_base);
-#if 1
n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD);
PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
-#endif
n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
- n2k_outb(n2k_inb(nic_base + PCNET_RESET), PCNET_RESET);
+ n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET);
for (i = 0; i < 100; i++) {
if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0)
/* U-boot specific routines */
-#define NB 5
static unsigned char *pbuf = NULL;
-static int plen[NB];
-static int nrx = 0;
static int pkey = -1;
+static int initialized=0;
void uboot_push_packet_len(int len) {
- PRINTK("pushed len = %d, nrx = %d\n", len, nrx);
+ PRINTK("pushed len = %d\n", len);
if (len>=2000) {
printf("NE2000: packet too big\n");
return;
}
- if (nrx >= NB) {
- printf("losing packets in rx\n");
- return;
- }
- plen[nrx] = len;
- dp83902a_recv(&pbuf[nrx*2000], len);
- nrx++;
+ dp83902a_recv(&pbuf[0], len);
+
+ /*Just pass it to the upper layer*/
+ NetReceive(&pbuf[0], len);
}
void uboot_push_tx_done(int key, int val) {
PRINTK("### eth_init\n");
if (!pbuf) {
- pbuf = malloc(NB*2000);
+ pbuf = malloc(2000);
if (!pbuf) {
- printf("Cannot allocate rx buffers\n");
+ printf("Cannot allocate rx buffer\n");
return -1;
}
}
if (dp83902a_init() == false)
return -1;
dp83902a_start(dev_addr);
+ initialized=1;
return 0;
}
void eth_halt() {
PRINTK("### eth_halt\n");
-
- dp83902a_stop();
+ if(initialized)
+ dp83902a_stop();
+ initialized=0;
}
int eth_rx() {
- int j, tmo;
-
- PRINTK("### eth_rx\n");
-
- tmo = get_timer (0) + TOUT * CFG_HZ;
- while(1) {
- dp83902a_poll();
- if (nrx > 0) {
- for(j=0; j<nrx; j++) {
- NetReceive(&pbuf[j*2000], plen[j]);
- }
- nrx = 0;
- return 1;
- }
- if (get_timer (0) >= tmo) {
- printf("timeout during rx\n");
- return 0;
- }
- }
- return 0;
+dp83902a_poll();
+return 1;
}
int eth_send(volatile void *packet, int length) {
}
return 0;
}
-
#endif
this file might be covered by the GNU General Public License.
Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
- at http://sources.redhat.com/ecos/ecos-license/ */
+ at http://sources.redhat.com/ecos/ecos-license/
-------------------------------------------
####ECOSGPLCOPYRIGHTEND####
####BSDCOPYRIGHTBEGIN####
--- /dev/null
+#
+# Copyright (C) 2005-2007 Samsung Electronics.
+# Kyungmin Park <kyungmin.park@samsung.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)libonenand.a
+
+COBJS := onenand_base.o onenand_bbt.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * linux/drivers/mtd/onenand/onenand_base.c
+ *
+ * Copyright (C) 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_CMD_ONENAND
+
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+
+#include <asm/io.h>
+#include <asm/errno.h>
+
+static const unsigned char ffchars[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 32 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */
+};
+
+/**
+ * onenand_readw - [OneNAND Interface] Read OneNAND register
+ * @param addr address to read
+ *
+ * Read OneNAND register
+ */
+static unsigned short onenand_readw(void __iomem * addr)
+{
+ return readw(addr);
+}
+
+/**
+ * onenand_writew - [OneNAND Interface] Write OneNAND register with value
+ * @param value value to write
+ * @param addr address to write
+ *
+ * Write OneNAND register with value
+ */
+static void onenand_writew(unsigned short value, void __iomem * addr)
+{
+ writew(value, addr);
+}
+
+/**
+ * onenand_block_address - [DEFAULT] Get block address
+ * @param device the device id
+ * @param block the block
+ * @return translated block address if DDP, otherwise same
+ *
+ * Setup Start Address 1 Register (F100h)
+ */
+static int onenand_block_address(int device, int block)
+{
+ if (device & ONENAND_DEVICE_IS_DDP) {
+ /* Device Flash Core select, NAND Flash Block Address */
+ int dfs = 0, density, mask;
+
+ density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
+ mask = (1 << (density + 6));
+
+ if (block & mask)
+ dfs = 1;
+
+ return (dfs << ONENAND_DDP_SHIFT) | (block & (mask - 1));
+ }
+
+ return block;
+}
+
+/**
+ * onenand_bufferram_address - [DEFAULT] Get bufferram address
+ * @param device the device id
+ * @param block the block
+ * @return set DBS value if DDP, otherwise 0
+ *
+ * Setup Start Address 2 Register (F101h) for DDP
+ */
+static int onenand_bufferram_address(int device, int block)
+{
+ if (device & ONENAND_DEVICE_IS_DDP) {
+ /* Device BufferRAM Select */
+ int dbs = 0, density, mask;
+
+ density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
+ mask = (1 << (density + 6));
+
+ if (block & mask)
+ dbs = 1;
+
+ return (dbs << ONENAND_DDP_SHIFT);
+ }
+
+ return 0;
+}
+
+/**
+ * onenand_page_address - [DEFAULT] Get page address
+ * @param page the page address
+ * @param sector the sector address
+ * @return combined page and sector address
+ *
+ * Setup Start Address 8 Register (F107h)
+ */
+static int onenand_page_address(int page, int sector)
+{
+ /* Flash Page Address, Flash Sector Address */
+ int fpa, fsa;
+
+ fpa = page & ONENAND_FPA_MASK;
+ fsa = sector & ONENAND_FSA_MASK;
+
+ return ((fpa << ONENAND_FPA_SHIFT) | fsa);
+}
+
+/**
+ * onenand_buffer_address - [DEFAULT] Get buffer address
+ * @param dataram1 DataRAM index
+ * @param sectors the sector address
+ * @param count the number of sectors
+ * @return the start buffer value
+ *
+ * Setup Start Buffer Register (F200h)
+ */
+static int onenand_buffer_address(int dataram1, int sectors, int count)
+{
+ int bsa, bsc;
+
+ /* BufferRAM Sector Address */
+ bsa = sectors & ONENAND_BSA_MASK;
+
+ if (dataram1)
+ bsa |= ONENAND_BSA_DATARAM1; /* DataRAM1 */
+ else
+ bsa |= ONENAND_BSA_DATARAM0; /* DataRAM0 */
+
+ /* BufferRAM Sector Count */
+ bsc = count & ONENAND_BSC_MASK;
+
+ return ((bsa << ONENAND_BSA_SHIFT) | bsc);
+}
+
+/**
+ * onenand_command - [DEFAULT] Send command to OneNAND device
+ * @param mtd MTD device structure
+ * @param cmd the command to be sent
+ * @param addr offset to read from or write to
+ * @param len number of bytes to read or write
+ *
+ * Send command to OneNAND device. This function is used for middle/large page
+ * devices (1KB/2KB Bytes per page)
+ */
+static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr,
+ size_t len)
+{
+ struct onenand_chip *this = mtd->priv;
+ int value, readcmd = 0;
+ int block, page;
+ /* Now we use page size operation */
+ int sectors = 4, count = 4;
+
+ /* Address translation */
+ switch (cmd) {
+ case ONENAND_CMD_UNLOCK:
+ case ONENAND_CMD_LOCK:
+ case ONENAND_CMD_LOCK_TIGHT:
+ block = -1;
+ page = -1;
+ break;
+
+ case ONENAND_CMD_ERASE:
+ case ONENAND_CMD_BUFFERRAM:
+ block = (int)(addr >> this->erase_shift);
+ page = -1;
+ break;
+
+ default:
+ block = (int)(addr >> this->erase_shift);
+ page = (int)(addr >> this->page_shift);
+ page &= this->page_mask;
+ break;
+ }
+
+ /* NOTE: The setting order of the registers is very important! */
+ if (cmd == ONENAND_CMD_BUFFERRAM) {
+ /* Select DataRAM for DDP */
+ value = onenand_bufferram_address(this->device_id, block);
+ this->write_word(value,
+ this->base + ONENAND_REG_START_ADDRESS2);
+
+ /* Switch to the next data buffer */
+ ONENAND_SET_NEXT_BUFFERRAM(this);
+
+ return 0;
+ }
+
+ if (block != -1) {
+ /* Write 'DFS, FBA' of Flash */
+ value = onenand_block_address(this->device_id, block);
+ this->write_word(value,
+ this->base + ONENAND_REG_START_ADDRESS1);
+ }
+
+ if (page != -1) {
+ int dataram;
+
+ switch (cmd) {
+ case ONENAND_CMD_READ:
+ case ONENAND_CMD_READOOB:
+ dataram = ONENAND_SET_NEXT_BUFFERRAM(this);
+ readcmd = 1;
+ break;
+
+ default:
+ dataram = ONENAND_CURRENT_BUFFERRAM(this);
+ break;
+ }
+
+ /* Write 'FPA, FSA' of Flash */
+ value = onenand_page_address(page, sectors);
+ this->write_word(value,
+ this->base + ONENAND_REG_START_ADDRESS8);
+
+ /* Write 'BSA, BSC' of DataRAM */
+ value = onenand_buffer_address(dataram, sectors, count);
+ this->write_word(value, this->base + ONENAND_REG_START_BUFFER);
+
+ if (readcmd) {
+ /* Select DataRAM for DDP */
+ value =
+ onenand_bufferram_address(this->device_id, block);
+ this->write_word(value,
+ this->base +
+ ONENAND_REG_START_ADDRESS2);
+ }
+ }
+
+ /* Interrupt clear */
+ this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT);
+ /* Write command */
+ this->write_word(cmd, this->base + ONENAND_REG_COMMAND);
+
+ return 0;
+}
+
+/**
+ * onenand_wait - [DEFAULT] wait until the command is done
+ * @param mtd MTD device structure
+ * @param state state to select the max. timeout value
+ *
+ * Wait for command done. This applies to all OneNAND command
+ * Read can take up to 30us, erase up to 2ms and program up to 350us
+ * according to general OneNAND specs
+ */
+static int onenand_wait(struct mtd_info *mtd, int state)
+{
+ struct onenand_chip *this = mtd->priv;
+ unsigned int flags = ONENAND_INT_MASTER;
+ unsigned int interrupt = 0;
+ unsigned int ctrl, ecc;
+
+ while (1) {
+ interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
+ if (interrupt & flags)
+ break;
+ }
+
+ ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
+
+ if (ctrl & ONENAND_CTRL_ERROR) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_wait: controller error = 0x%04x\n", ctrl);
+ return -EAGAIN;
+ }
+
+ if (ctrl & ONENAND_CTRL_LOCK) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_wait: it's locked error = 0x%04x\n", ctrl);
+ return -EIO;
+ }
+
+ if (interrupt & ONENAND_INT_READ) {
+ ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS);
+ if (ecc & ONENAND_ECC_2BIT_ALL) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_wait: ECC error = 0x%04x\n", ecc);
+ return -EBADMSG;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * onenand_bufferram_offset - [DEFAULT] BufferRAM offset
+ * @param mtd MTD data structure
+ * @param area BufferRAM area
+ * @return offset given area
+ *
+ * Return BufferRAM offset given area
+ */
+static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area)
+{
+ struct onenand_chip *this = mtd->priv;
+
+ if (ONENAND_CURRENT_BUFFERRAM(this)) {
+ if (area == ONENAND_DATARAM)
+ return mtd->oobblock;
+ if (area == ONENAND_SPARERAM)
+ return mtd->oobsize;
+ }
+
+ return 0;
+}
+
+/**
+ * onenand_read_bufferram - [OneNAND Interface] Read the bufferram area
+ * @param mtd MTD data structure
+ * @param area BufferRAM area
+ * @param buffer the databuffer to put/get data
+ * @param offset offset to read from or write to
+ * @param count number of bytes to read/write
+ *
+ * Read the BufferRAM area
+ */
+static int onenand_read_bufferram(struct mtd_info *mtd, int area,
+ unsigned char *buffer, int offset,
+ size_t count)
+{
+ struct onenand_chip *this = mtd->priv;
+ void __iomem *bufferram;
+
+ bufferram = this->base + area;
+ bufferram += onenand_bufferram_offset(mtd, area);
+
+ memcpy(buffer, bufferram + offset, count);
+
+ return 0;
+}
+
+/**
+ * onenand_sync_read_bufferram - [OneNAND Interface] Read the bufferram area with Sync. Burst mode
+ * @param mtd MTD data structure
+ * @param area BufferRAM area
+ * @param buffer the databuffer to put/get data
+ * @param offset offset to read from or write to
+ * @param count number of bytes to read/write
+ *
+ * Read the BufferRAM area with Sync. Burst Mode
+ */
+static int onenand_sync_read_bufferram(struct mtd_info *mtd, int area,
+ unsigned char *buffer, int offset,
+ size_t count)
+{
+ struct onenand_chip *this = mtd->priv;
+ void __iomem *bufferram;
+
+ bufferram = this->base + area;
+ bufferram += onenand_bufferram_offset(mtd, area);
+
+ this->mmcontrol(mtd, ONENAND_SYS_CFG1_SYNC_READ);
+
+ memcpy(buffer, bufferram + offset, count);
+
+ this->mmcontrol(mtd, 0);
+
+ return 0;
+}
+
+/**
+ * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area
+ * @param mtd MTD data structure
+ * @param area BufferRAM area
+ * @param buffer the databuffer to put/get data
+ * @param offset offset to read from or write to
+ * @param count number of bytes to read/write
+ *
+ * Write the BufferRAM area
+ */
+static int onenand_write_bufferram(struct mtd_info *mtd, int area,
+ const unsigned char *buffer, int offset,
+ size_t count)
+{
+ struct onenand_chip *this = mtd->priv;
+ void __iomem *bufferram;
+
+ bufferram = this->base + area;
+ bufferram += onenand_bufferram_offset(mtd, area);
+
+ memcpy(bufferram + offset, buffer, count);
+
+ return 0;
+}
+
+/**
+ * onenand_check_bufferram - [GENERIC] Check BufferRAM information
+ * @param mtd MTD data structure
+ * @param addr address to check
+ * @return 1 if there are valid data, otherwise 0
+ *
+ * Check bufferram if there is data we required
+ */
+static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr)
+{
+ struct onenand_chip *this = mtd->priv;
+ int block, page;
+ int i;
+
+ block = (int)(addr >> this->erase_shift);
+ page = (int)(addr >> this->page_shift);
+ page &= this->page_mask;
+
+ i = ONENAND_CURRENT_BUFFERRAM(this);
+
+ /* Is there valid data? */
+ if (this->bufferram[i].block == block &&
+ this->bufferram[i].page == page && this->bufferram[i].valid)
+ return 1;
+
+ return 0;
+}
+
+/**
+ * onenand_update_bufferram - [GENERIC] Update BufferRAM information
+ * @param mtd MTD data structure
+ * @param addr address to update
+ * @param valid valid flag
+ *
+ * Update BufferRAM information
+ */
+static int onenand_update_bufferram(struct mtd_info *mtd, loff_t addr,
+ int valid)
+{
+ struct onenand_chip *this = mtd->priv;
+ int block, page;
+ int i;
+
+ block = (int)(addr >> this->erase_shift);
+ page = (int)(addr >> this->page_shift);
+ page &= this->page_mask;
+
+ /* Invalidate BufferRAM */
+ for (i = 0; i < MAX_BUFFERRAM; i++) {
+ if (this->bufferram[i].block == block &&
+ this->bufferram[i].page == page)
+ this->bufferram[i].valid = 0;
+ }
+
+ /* Update BufferRAM */
+ i = ONENAND_CURRENT_BUFFERRAM(this);
+ this->bufferram[i].block = block;
+ this->bufferram[i].page = page;
+ this->bufferram[i].valid = valid;
+
+ return 0;
+}
+
+/**
+ * onenand_get_device - [GENERIC] Get chip for selected access
+ * @param mtd MTD device structure
+ * @param new_state the state which is requested
+ *
+ * Get the device and lock it for exclusive access
+ */
+static void onenand_get_device(struct mtd_info *mtd, int new_state)
+{
+ /* Do nothing */
+}
+
+/**
+ * onenand_release_device - [GENERIC] release chip
+ * @param mtd MTD device structure
+ *
+ * Deselect, release chip lock and wake up anyone waiting on the device
+ */
+static void onenand_release_device(struct mtd_info *mtd)
+{
+ /* Do nothing */
+}
+
+/**
+ * onenand_read_ecc - [MTD Interface] Read data with ECC
+ * @param mtd MTD device structure
+ * @param from offset to read from
+ * @param len number of bytes to read
+ * @param retlen pointer to variable to store the number of read bytes
+ * @param buf the databuffer to put data
+ * @param oob_buf filesystem supplied oob data buffer
+ * @param oobsel oob selection structure
+ *
+ * OneNAND read with ECC
+ */
+static int onenand_read_ecc(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t * retlen, u_char * buf,
+ u_char * oob_buf, struct nand_oobinfo *oobsel)
+{
+ struct onenand_chip *this = mtd->priv;
+ int read = 0, column;
+ int thislen;
+ int ret = 0;
+
+ DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_ecc: from = 0x%08x, len = %i\n",
+ (unsigned int)from, (int)len);
+
+ /* Do not allow reads past end of device */
+ if ((from + len) > mtd->size) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_read_ecc: Attempt read beyond end of device\n");
+ *retlen = 0;
+ return -EINVAL;
+ }
+
+ /* Grab the lock and see if the device is available */
+ onenand_get_device(mtd, FL_READING);
+
+ while (read < len) {
+ thislen = min_t(int, mtd->oobblock, len - read);
+
+ column = from & (mtd->oobblock - 1);
+ if (column + thislen > mtd->oobblock)
+ thislen = mtd->oobblock - column;
+
+ if (!onenand_check_bufferram(mtd, from)) {
+ this->command(mtd, ONENAND_CMD_READ, from,
+ mtd->oobblock);
+ ret = this->wait(mtd, FL_READING);
+ /* First copy data and check return value for ECC handling */
+ onenand_update_bufferram(mtd, from, 1);
+ }
+
+ this->read_bufferram(mtd, ONENAND_DATARAM, buf, column,
+ thislen);
+
+ read += thislen;
+ if (read == len)
+ break;
+
+ if (ret) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_read_ecc: read failed = %d\n", ret);
+ break;
+ }
+
+ from += thislen;
+ buf += thislen;
+ }
+
+ /* Deselect and wake up anyone waiting on the device */
+ onenand_release_device(mtd);
+
+ /*
+ * Return success, if no ECC failures, else -EBADMSG
+ * fs driver will take care of that, because
+ * retlen == desired len and result == -EBADMSG
+ */
+ *retlen = read;
+ return ret;
+}
+
+/**
+ * onenand_read - [MTD Interface] MTD compability function for onenand_read_ecc
+ * @param mtd MTD device structure
+ * @param from offset to read from
+ * @param len number of bytes to read
+ * @param retlen pointer to variable to store the number of read bytes
+ * @param buf the databuffer to put data
+ *
+ * This function simply calls onenand_read_ecc with oob buffer and oobsel = NULL
+*/
+int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t * retlen, u_char * buf)
+{
+ return onenand_read_ecc(mtd, from, len, retlen, buf, NULL, NULL);
+}
+
+/**
+ * onenand_read_oob - [MTD Interface] OneNAND read out-of-band
+ * @param mtd MTD device structure
+ * @param from offset to read from
+ * @param len number of bytes to read
+ * @param retlen pointer to variable to store the number of read bytes
+ * @param buf the databuffer to put data
+ *
+ * OneNAND read out-of-band data from the spare area
+ */
+int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t * retlen, u_char * buf)
+{
+ struct onenand_chip *this = mtd->priv;
+ int read = 0, thislen, column;
+ int ret = 0;
+
+ DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob: from = 0x%08x, len = %i\n",
+ (unsigned int)from, (int)len);
+
+ /* Initialize return length value */
+ *retlen = 0;
+
+ /* Do not allow reads past end of device */
+ if (unlikely((from + len) > mtd->size)) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_read_oob: Attempt read beyond end of device\n");
+ return -EINVAL;
+ }
+
+ /* Grab the lock and see if the device is available */
+ onenand_get_device(mtd, FL_READING);
+
+ column = from & (mtd->oobsize - 1);
+
+ while (read < len) {
+ thislen = mtd->oobsize - column;
+ thislen = min_t(int, thislen, len);
+
+ this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize);
+
+ onenand_update_bufferram(mtd, from, 0);
+
+ ret = this->wait(mtd, FL_READING);
+ /* First copy data and check return value for ECC handling */
+
+ this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column,
+ thislen);
+
+ read += thislen;
+ if (read == len)
+ break;
+
+ if (ret) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_read_oob: read failed = %d\n", ret);
+ break;
+ }
+
+ buf += thislen;
+ /* Read more? */
+ if (read < len) {
+ /* Page size */
+ from += mtd->oobblock;
+ column = 0;
+ }
+ }
+
+ /* Deselect and wake up anyone waiting on the device */
+ onenand_release_device(mtd);
+
+ *retlen = read;
+ return ret;
+}
+
+#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
+/**
+ * onenand_verify_page - [GENERIC] verify the chip contents after a write
+ * @param mtd MTD device structure
+ * @param buf the databuffer to verify
+ * @param block block address
+ * @param page page address
+ *
+ * Check DataRAM area directly
+ */
+static int onenand_verify_page(struct mtd_info *mtd, u_char * buf,
+ loff_t addr, int block, int page)
+{
+ struct onenand_chip *this = mtd->priv;
+ void __iomem *dataram0, *dataram1;
+ int ret = 0;
+
+ this->command(mtd, ONENAND_CMD_READ, addr, mtd->oobblock);
+
+ ret = this->wait(mtd, FL_READING);
+ if (ret)
+ return ret;
+
+ onenand_update_bufferram(mtd, addr, 1);
+
+ /* Check, if the two dataram areas are same */
+ dataram0 = this->base + ONENAND_DATARAM;
+ dataram1 = dataram0 + mtd->oobblock;
+
+ if (memcmp(dataram0, dataram1, mtd->oobblock))
+ return -EBADMSG;
+
+ return 0;
+}
+#else
+#define onenand_verify_page(...) (0)
+#endif
+
+#define NOTALIGNED(x) ((x & (mtd->oobblock - 1)) != 0)
+
+/**
+ * onenand_write_ecc - [MTD Interface] OneNAND write with ECC
+ * @param mtd MTD device structure
+ * @param to offset to write to
+ * @param len number of bytes to write
+ * @param retlen pointer to variable to store the number of written bytes
+ * @param buf the data to write
+ * @param eccbuf filesystem supplied oob data buffer
+ * @param oobsel oob selection structure
+ *
+ * OneNAND write with ECC
+ */
+static int onenand_write_ecc(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t * retlen, const u_char * buf,
+ u_char * eccbuf, struct nand_oobinfo *oobsel)
+{
+ struct onenand_chip *this = mtd->priv;
+ int written = 0;
+ int ret = 0;
+
+ DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_ecc: to = 0x%08x, len = %i\n",
+ (unsigned int)to, (int)len);
+
+ /* Initialize retlen, in case of early exit */
+ *retlen = 0;
+
+ /* Do not allow writes past end of device */
+ if (unlikely((to + len) > mtd->size)) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_write_ecc: Attempt write to past end of device\n");
+ return -EINVAL;
+ }
+
+ /* Reject writes, which are not page aligned */
+ if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(len))) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_write_ecc: Attempt to write not page aligned data\n");
+ return -EINVAL;
+ }
+
+ /* Grab the lock and see if the device is available */
+ onenand_get_device(mtd, FL_WRITING);
+
+ /* Loop until all data write */
+ while (written < len) {
+ int thislen = min_t(int, mtd->oobblock, len - written);
+
+ this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobblock);
+
+ this->write_bufferram(mtd, ONENAND_DATARAM, buf, 0, thislen);
+ this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0,
+ mtd->oobsize);
+
+ this->command(mtd, ONENAND_CMD_PROG, to, mtd->oobblock);
+
+ onenand_update_bufferram(mtd, to, 1);
+
+ ret = this->wait(mtd, FL_WRITING);
+ if (ret) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_write_ecc: write filaed %d\n", ret);
+ break;
+ }
+
+ written += thislen;
+
+ /* Only check verify write turn on */
+ ret = onenand_verify_page(mtd, (u_char *) buf, to, block, page);
+ if (ret) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_write_ecc: verify failed %d\n", ret);
+ break;
+ }
+
+ if (written == len)
+ break;
+
+ to += thislen;
+ buf += thislen;
+ }
+
+ /* Deselect and wake up anyone waiting on the device */
+ onenand_release_device(mtd);
+
+ *retlen = written;
+
+ return ret;
+}
+
+/**
+ * onenand_write - [MTD Interface] compability function for onenand_write_ecc
+ * @param mtd MTD device structure
+ * @param to offset to write to
+ * @param len number of bytes to write
+ * @param retlen pointer to variable to store the number of written bytes
+ * @param buf the data to write
+ *
+ * This function simply calls onenand_write_ecc
+ * with oob buffer and oobsel = NULL
+ */
+int onenand_write(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t * retlen, const u_char * buf)
+{
+ return onenand_write_ecc(mtd, to, len, retlen, buf, NULL, NULL);
+}
+
+/**
+ * onenand_write_oob - [MTD Interface] OneNAND write out-of-band
+ * @param mtd MTD device structure
+ * @param to offset to write to
+ * @param len number of bytes to write
+ * @param retlen pointer to variable to store the number of written bytes
+ * @param buf the data to write
+ *
+ * OneNAND write out-of-band
+ */
+int onenand_write_oob(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t * retlen, const u_char * buf)
+{
+ struct onenand_chip *this = mtd->priv;
+ int column, status;
+ int written = 0;
+
+ DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob: to = 0x%08x, len = %i\n",
+ (unsigned int)to, (int)len);
+
+ /* Initialize retlen, in case of early exit */
+ *retlen = 0;
+
+ /* Do not allow writes past end of device */
+ if (unlikely((to + len) > mtd->size)) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_write_oob: Attempt write to past end of device\n");
+ return -EINVAL;
+ }
+
+ /* Grab the lock and see if the device is available */
+ onenand_get_device(mtd, FL_WRITING);
+
+ /* Loop until all data write */
+ while (written < len) {
+ int thislen = min_t(int, mtd->oobsize, len - written);
+
+ column = to & (mtd->oobsize - 1);
+
+ this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobsize);
+
+ this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0,
+ mtd->oobsize);
+ this->write_bufferram(mtd, ONENAND_SPARERAM, buf, column,
+ thislen);
+
+ this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize);
+
+ onenand_update_bufferram(mtd, to, 0);
+
+ status = this->wait(mtd, FL_WRITING);
+ if (status)
+ break;
+
+ written += thislen;
+ if (written == len)
+ break;
+
+ to += thislen;
+ buf += thislen;
+ }
+
+ /* Deselect and wake up anyone waiting on the device */
+ onenand_release_device(mtd);
+
+ *retlen = written;
+
+ return 0;
+}
+
+/**
+ * onenand_erase - [MTD Interface] erase block(s)
+ * @param mtd MTD device structure
+ * @param instr erase instruction
+ *
+ * Erase one ore more blocks
+ */
+int onenand_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+ struct onenand_chip *this = mtd->priv;
+ unsigned int block_size;
+ loff_t addr;
+ int len;
+ int ret = 0;
+
+ DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n",
+ (unsigned int)instr->addr, (unsigned int)instr->len);
+
+ block_size = (1 << this->erase_shift);
+
+ /* Start address must align on block boundary */
+ if (unlikely(instr->addr & (block_size - 1))) {
+ DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Unaligned address\n");
+ return -EINVAL;
+ }
+
+ /* Length must align on block boundary */
+ if (unlikely(instr->len & (block_size - 1))) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_erase: Length not block aligned\n");
+ return -EINVAL;
+ }
+
+ /* Do not allow erase past end of device */
+ if (unlikely((instr->len + instr->addr) > mtd->size)) {
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_erase: Erase past end of device\n");
+ return -EINVAL;
+ }
+
+ instr->fail_addr = 0xffffffff;
+
+ /* Grab the lock and see if the device is available */
+ onenand_get_device(mtd, FL_ERASING);
+
+ /* Loop throught the pages */
+ len = instr->len;
+ addr = instr->addr;
+
+ instr->state = MTD_ERASING;
+
+ while (len) {
+
+ /* TODO Check badblock */
+
+ this->command(mtd, ONENAND_CMD_ERASE, addr, block_size);
+
+ ret = this->wait(mtd, FL_ERASING);
+ /* Check, if it is write protected */
+ if (ret) {
+ if (ret == -EPERM)
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_erase: Device is write protected!!!\n");
+ else
+ DEBUG(MTD_DEBUG_LEVEL0,
+ "onenand_erase: Failed erase, block %d\n",
+ (unsigned)(addr >> this->erase_shift));
+ instr->state = MTD_ERASE_FAILED;
+ instr->fail_addr = addr;
+ goto erase_exit;
+ }
+
+ len -= block_size;
+ addr += block_size;
+ }
+
+ instr->state = MTD_ERASE_DONE;
+
+ erase_exit:
+
+ ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
+ /* Do call back function */
+ if (!ret)
+ mtd_erase_callback(instr);
+
+ /* Deselect and wake up anyone waiting on the device */
+ onenand_release_device(mtd);
+
+ return ret;
+}
+
+/**
+ * onenand_sync - [MTD Interface] sync
+ * @param mtd MTD device structure
+ *
+ * Sync is actually a wait for chip ready function
+ */
+void onenand_sync(struct mtd_info *mtd)
+{
+ DEBUG(MTD_DEBUG_LEVEL3, "onenand_sync: called\n");
+
+ /* Grab the lock and see if the device is available */
+ onenand_get_device(mtd, FL_SYNCING);
+
+ /* Release it and go back */
+ onenand_release_device(mtd);
+}
+
+/**
+ * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad
+ * @param mtd MTD device structure
+ * @param ofs offset relative to mtd start
+ */
+int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs)
+{
+ /*
+ * TODO
+ * 1. Bad block table (BBT)
+ * -> using NAND BBT to support JFFS2
+ * 2. Bad block management (BBM)
+ * -> bad block replace scheme
+ *
+ * Currently we do nothing
+ */
+ return 0;
+}
+
+/**
+ * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad
+ * @param mtd MTD device structure
+ * @param ofs offset relative to mtd start
+ */
+int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+ /* see above */
+ return 0;
+}
+
+/**
+ * onenand_unlock - [MTD Interface] Unlock block(s)
+ * @param mtd MTD device structure
+ * @param ofs offset relative to mtd start
+ * @param len number of bytes to unlock
+ *
+ * Unlock one or more blocks
+ */
+int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len)
+{
+ struct onenand_chip *this = mtd->priv;
+ int start, end, block, value, status;
+
+ start = ofs >> this->erase_shift;
+ end = len >> this->erase_shift;
+
+ /* Continuous lock scheme */
+ if (this->options & ONENAND_CONT_LOCK) {
+ /* Set start block address */
+ this->write_word(start,
+ this->base + ONENAND_REG_START_BLOCK_ADDRESS);
+ /* Set end block address */
+ this->write_word(end - 1,
+ this->base + ONENAND_REG_END_BLOCK_ADDRESS);
+ /* Write unlock command */
+ this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0);
+
+ /* There's no return value */
+ this->wait(mtd, FL_UNLOCKING);
+
+ /* Sanity check */
+ while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
+ & ONENAND_CTRL_ONGO)
+ continue;
+
+ /* Check lock status */
+ status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
+ if (!(status & ONENAND_WP_US))
+ printk(KERN_ERR "wp status = 0x%x\n", status);
+
+ return 0;
+ }
+
+ /* Block lock scheme */
+ for (block = start; block < end; block++) {
+ /* Set start block address */
+ this->write_word(block,
+ this->base + ONENAND_REG_START_BLOCK_ADDRESS);
+ /* Write unlock command */
+ this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0);
+
+ /* There's no return value */
+ this->wait(mtd, FL_UNLOCKING);
+
+ /* Sanity check */
+ while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
+ & ONENAND_CTRL_ONGO)
+ continue;
+
+ /* Set block address for read block status */
+ value = onenand_block_address(this->device_id, block);
+ this->write_word(value,
+ this->base + ONENAND_REG_START_ADDRESS1);
+
+ /* Check lock status */
+ status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
+ if (!(status & ONENAND_WP_US))
+ printk(KERN_ERR "block = %d, wp status = 0x%x\n",
+ block, status);
+ }
+
+ return 0;
+}
+
+/**
+ * onenand_print_device_info - Print device ID
+ * @param device device ID
+ *
+ * Print device ID
+ */
+void onenand_print_device_info(int device, int verbose)
+{
+ int vcc, demuxed, ddp, density;
+
+ if (!verbose)
+ return;
+
+ vcc = device & ONENAND_DEVICE_VCC_MASK;
+ demuxed = device & ONENAND_DEVICE_IS_DEMUX;
+ ddp = device & ONENAND_DEVICE_IS_DDP;
+ density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
+ printk(KERN_INFO "%sOneNAND%s %dMB %sV 16-bit (0x%02x)\n",
+ demuxed ? "" : "Muxed ",
+ ddp ? "(DDP)" : "",
+ (16 << density), vcc ? "2.65/3.3" : "1.8", device);
+}
+
+static const struct onenand_manufacturers onenand_manuf_ids[] = {
+ {ONENAND_MFR_SAMSUNG, "Samsung"},
+ {ONENAND_MFR_UNKNOWN, "Unknown"}
+};
+
+/**
+ * onenand_check_maf - Check manufacturer ID
+ * @param manuf manufacturer ID
+ *
+ * Check manufacturer ID
+ */
+static int onenand_check_maf(int manuf)
+{
+ int i;
+
+ for (i = 0; onenand_manuf_ids[i].id; i++) {
+ if (manuf == onenand_manuf_ids[i].id)
+ break;
+ }
+
+#ifdef ONENAND_DEBUG
+ printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n",
+ onenand_manuf_ids[i].name, manuf);
+#endif
+
+ return (i != ONENAND_MFR_UNKNOWN);
+}
+
+/**
+ * onenand_probe - [OneNAND Interface] Probe the OneNAND device
+ * @param mtd MTD device structure
+ *
+ * OneNAND detection method:
+ * Compare the the values from command with ones from register
+ */
+static int onenand_probe(struct mtd_info *mtd)
+{
+ struct onenand_chip *this = mtd->priv;
+ int bram_maf_id, bram_dev_id, maf_id, dev_id;
+ int version_id;
+ int density;
+
+ /* Send the command for reading device ID from BootRAM */
+ this->write_word(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM);
+
+ /* Read manufacturer and device IDs from BootRAM */
+ bram_maf_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x0);
+ bram_dev_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x2);
+
+ /* Check manufacturer ID */
+ if (onenand_check_maf(bram_maf_id))
+ return -ENXIO;
+
+ /* Reset OneNAND to read default register values */
+ this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM);
+
+ {
+ int i;
+ for (i = 0; i < 10000; i++) ;
+ }
+
+ /* Read manufacturer and device IDs from Register */
+ maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID);
+ dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID);
+
+ /* Check OneNAND device */
+ if (maf_id != bram_maf_id || dev_id != bram_dev_id)
+ return -ENXIO;
+
+ /* Flash device information */
+ onenand_print_device_info(dev_id, 0);
+ this->device_id = dev_id;
+
+ density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT;
+ this->chipsize = (16 << density) << 20;
+
+ /* OneNAND page size & block size */
+ /* The data buffer size is equal to page size */
+ mtd->oobblock =
+ this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE);
+ mtd->oobsize = mtd->oobblock >> 5;
+ /* Pagers per block is always 64 in OneNAND */
+ mtd->erasesize = mtd->oobblock << 6;
+
+ this->erase_shift = ffs(mtd->erasesize) - 1;
+ this->page_shift = ffs(mtd->oobblock) - 1;
+ this->ppb_shift = (this->erase_shift - this->page_shift);
+ this->page_mask = (mtd->erasesize / mtd->oobblock) - 1;
+
+ /* REVIST: Multichip handling */
+
+ mtd->size = this->chipsize;
+
+ /* Version ID */
+ version_id = this->read_word(this->base + ONENAND_REG_VERSION_ID);
+#ifdef ONENAND_DEBUG
+ printk(KERN_DEBUG "OneNAND version = 0x%04x\n", version_id);
+#endif
+
+ /* Lock scheme */
+ if (density <= ONENAND_DEVICE_DENSITY_512Mb &&
+ !(version_id >> ONENAND_VERSION_PROCESS_SHIFT)) {
+ printk(KERN_INFO "Lock scheme is Continues Lock\n");
+ this->options |= ONENAND_CONT_LOCK;
+ }
+
+ return 0;
+}
+
+/**
+ * onenand_scan - [OneNAND Interface] Scan for the OneNAND device
+ * @param mtd MTD device structure
+ * @param maxchips Number of chips to scan for
+ *
+ * This fills out all the not initialized function pointers
+ * with the defaults.
+ * The flash ID is read and the mtd/chip structures are
+ * filled with the appropriate values.
+ */
+int onenand_scan(struct mtd_info *mtd, int maxchips)
+{
+ struct onenand_chip *this = mtd->priv;
+
+ if (!this->read_word)
+ this->read_word = onenand_readw;
+ if (!this->write_word)
+ this->write_word = onenand_writew;
+
+ if (!this->command)
+ this->command = onenand_command;
+ if (!this->wait)
+ this->wait = onenand_wait;
+
+ if (!this->read_bufferram)
+ this->read_bufferram = onenand_read_bufferram;
+ if (!this->write_bufferram)
+ this->write_bufferram = onenand_write_bufferram;
+
+ if (onenand_probe(mtd))
+ return -ENXIO;
+
+ /* Set Sync. Burst Read after probing */
+ if (this->mmcontrol) {
+ printk(KERN_INFO "OneNAND Sync. Burst Read support\n");
+ this->read_bufferram = onenand_sync_read_bufferram;
+ }
+
+ onenand_unlock(mtd, 0, mtd->size);
+
+ return onenand_default_bbt(mtd);
+}
+
+/**
+ * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device
+ * @param mtd MTD device structure
+ */
+void onenand_release(struct mtd_info *mtd)
+{
+}
+
+/*
+ * OneNAND initialization at U-Boot
+ */
+struct mtd_info onenand_mtd;
+struct onenand_chip onenand_chip;
+
+void onenand_init(void)
+{
+ memset(&onenand_mtd, 0, sizeof(struct mtd_info));
+ memset(&onenand_chip, 0, sizeof(struct onenand_chip));
+
+ onenand_chip.base = (void *)CFG_ONENAND_BASE;
+ onenand_mtd.priv = &onenand_chip;
+
+ onenand_scan(&onenand_mtd, 1);
+
+ puts("OneNAND: ");
+ print_size(onenand_mtd.size, "\n");
+}
+
+#endif /* CONFIG_CMD_ONENAND */
--- /dev/null
+/*
+ * linux/drivers/mtd/onenand/onenand_bbt.c
+ *
+ * Bad Block Table support for the OneNAND driver
+ *
+ * Copyright(c) 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * TODO:
+ * Split BBT core and chip specific BBT.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_CMD_ONENAND
+
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <malloc.h>
+
+#include <asm/errno.h>
+
+/**
+ * check_short_pattern - [GENERIC] check if a pattern is in the buffer
+ * @param buf the buffer to search
+ * @param len the length of buffer to search
+ * @param paglen the pagelength
+ * @param td search pattern descriptor
+ *
+ * Check for a pattern at the given place. Used to search bad block
+ * tables and good / bad block identifiers. Same as check_pattern, but
+ * no optional empty check and the pattern is expected to start
+ * at offset 0.
+ */
+static int check_short_pattern(uint8_t * buf, int len, int paglen,
+ struct nand_bbt_descr *td)
+{
+ int i;
+ uint8_t *p = buf;
+
+ /* Compare the pattern */
+ for (i = 0; i < td->len; i++) {
+ if (p[i] != td->pattern[i])
+ return -1;
+ }
+ return 0;
+}
+
+/**
+ * create_bbt - [GENERIC] Create a bad block table by scanning the device
+ * @param mtd MTD device structure
+ * @param buf temporary buffer
+ * @param bd descriptor for the good/bad block search pattern
+ * @param chip create the table for a specific chip, -1 read all chips.
+ * Applies only if NAND_BBT_PERCHIP option is set
+ *
+ * Create a bad block table by scanning the device
+ * for the given good/bad block identify pattern
+ */
+static int create_bbt(struct mtd_info *mtd, uint8_t * buf,
+ struct nand_bbt_descr *bd, int chip)
+{
+ struct onenand_chip *this = mtd->priv;
+ struct bbm_info *bbm = this->bbm;
+ int i, j, numblocks, len, scanlen;
+ int startblock;
+ loff_t from;
+ size_t readlen, ooblen;
+
+ printk(KERN_INFO "Scanning device for bad blocks\n");
+
+ len = 1;
+
+ /* We need only read few bytes from the OOB area */
+ scanlen = ooblen = 0;
+ readlen = bd->len;
+
+ /* chip == -1 case only */
+ /* Note that numblocks is 2 * (real numblocks) here;
+ * see i += 2 below as it makses shifting and masking less painful
+ */
+ numblocks = mtd->size >> (bbm->bbt_erase_shift - 1);
+ startblock = 0;
+ from = 0;
+
+ for (i = startblock; i < numblocks;) {
+ int ret;
+
+ for (j = 0; j < len; j++) {
+ size_t retlen;
+
+ /* No need to read pages fully,
+ * just read required OOB bytes */
+ ret = onenand_read_oob(mtd,
+ from + j * mtd->oobblock +
+ bd->offs, readlen, &retlen,
+ &buf[0]);
+
+ if (ret && ret != -EAGAIN) {
+ printk("ret = %d\n", ret);
+ return ret;
+ }
+
+ if (check_short_pattern
+ (&buf[j * scanlen], scanlen, mtd->oobblock, bd)) {
+ bbm->bbt[i >> 3] |= 0x03 << (i & 0x6);
+ printk(KERN_WARNING
+ "Bad eraseblock %d at 0x%08x\n", i >> 1,
+ (unsigned int)from);
+ break;
+ }
+ }
+ i += 2;
+ from += (1 << bbm->bbt_erase_shift);
+ }
+
+ return 0;
+}
+
+/**
+ * onenand_memory_bbt - [GENERIC] create a memory based bad block table
+ * @param mtd MTD device structure
+ * @param bd descriptor for the good/bad block search pattern
+ *
+ * The function creates a memory based bbt by scanning the device
+ * for manufacturer / software marked good / bad blocks
+ */
+static inline int onenand_memory_bbt(struct mtd_info *mtd,
+ struct nand_bbt_descr *bd)
+{
+ unsigned char data_buf[MAX_ONENAND_PAGESIZE];
+
+ bd->options &= ~NAND_BBT_SCANEMPTY;
+ return create_bbt(mtd, data_buf, bd, -1);
+}
+
+/**
+ * onenand_isbad_bbt - [OneNAND Interface] Check if a block is bad
+ * @param mtd MTD device structure
+ * @param offs offset in the device
+ * @param allowbbt allow access to bad block table region
+ */
+static int onenand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt)
+{
+ struct onenand_chip *this = mtd->priv;
+ struct bbm_info *bbm = this->bbm;
+ int block;
+ uint8_t res;
+
+ /* Get block number * 2 */
+ block = (int)(offs >> (bbm->bbt_erase_shift - 1));
+ res = (bbm->bbt[block >> 3] >> (block & 0x06)) & 0x03;
+
+ DEBUG(MTD_DEBUG_LEVEL2,
+ "onenand_isbad_bbt: bbt info for offs 0x%08x: (block %d) 0x%02x\n",
+ (unsigned int)offs, block >> 1, res);
+
+ switch ((int)res) {
+ case 0x00:
+ return 0;
+ case 0x01:
+ return 1;
+ case 0x02:
+ return allowbbt ? 0 : 1;
+ }
+
+ return 1;
+}
+
+/**
+ * onenand_scan_bbt - [OneNAND Interface] scan, find, read and maybe create bad block table(s)
+ * @param mtd MTD device structure
+ * @param bd descriptor for the good/bad block search pattern
+ *
+ * The function checks, if a bad block table(s) is/are already
+ * available. If not it scans the device for manufacturer
+ * marked good / bad blocks and writes the bad block table(s) to
+ * the selected place.
+ *
+ * The bad block table memory is allocated here. It must be freed
+ * by calling the onenand_free_bbt function.
+ *
+ */
+int onenand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
+{
+ struct onenand_chip *this = mtd->priv;
+ struct bbm_info *bbm = this->bbm;
+ int len, ret = 0;
+
+ len = mtd->size >> (this->erase_shift + 2);
+ /* Allocate memory (2bit per block) */
+ bbm->bbt = malloc(len);
+ if (!bbm->bbt) {
+ printk(KERN_ERR "onenand_scan_bbt: Out of memory\n");
+ return -ENOMEM;
+ }
+ /* Clear the memory bad block table */
+ memset(bbm->bbt, 0x00, len);
+
+ /* Set the bad block position */
+ bbm->badblockpos = ONENAND_BADBLOCK_POS;
+
+ /* Set erase shift */
+ bbm->bbt_erase_shift = this->erase_shift;
+
+ if (!bbm->isbad_bbt)
+ bbm->isbad_bbt = onenand_isbad_bbt;
+
+ /* Scan the device to build a memory based bad block table */
+ if ((ret = onenand_memory_bbt(mtd, bd))) {
+ printk(KERN_ERR
+ "onenand_scan_bbt: Can't scan flash and build the RAM-based BBT\n");
+ free(bbm->bbt);
+ bbm->bbt = NULL;
+ }
+
+ return ret;
+}
+
+/*
+ * Define some generic bad / good block scan pattern which are used
+ * while scanning a device for factory marked good / bad blocks.
+ */
+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
+
+static struct nand_bbt_descr largepage_memorybased = {
+ .options = 0,
+ .offs = 0,
+ .len = 2,
+ .pattern = scan_ff_pattern,
+};
+
+/**
+ * onenand_default_bbt - [OneNAND Interface] Select a default bad block table for the device
+ * @param mtd MTD device structure
+ *
+ * This function selects the default bad block table
+ * support for the device and calls the onenand_scan_bbt function
+ */
+int onenand_default_bbt(struct mtd_info *mtd)
+{
+ struct onenand_chip *this = mtd->priv;
+ struct bbm_info *bbm;
+
+ this->bbm = malloc(sizeof(struct bbm_info));
+ if (!this->bbm)
+ return -ENOMEM;
+
+ bbm = this->bbm;
+
+ memset(bbm, 0, sizeof(struct bbm_info));
+
+ /* 1KB page has same configuration as 2KB page */
+ if (!bbm->badblock_pattern)
+ bbm->badblock_pattern = &largepage_memorybased;
+
+ return onenand_scan_bbt(mtd, bbm->badblock_pattern);
+}
+
+#endif /* CFG_CMD_ONENAND */
}
/* copy user data into frame data pointer */
- memcpy((void *)(eth->m_curTX_FD->m_frameDataPtr.bf.dataPtr),
+ memcpy((void *)((u32)(eth->m_curTX_FD->m_frameDataPtr.bf.dataPtr)),
(void *)packet,
length);
LIB := $(obj)libserial.a
-COBJS := mcfuart.o
+COBJS := mcfuart.o serial_pl010.o serial_pl011.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
#include <config.h>
-#ifdef CONFIG_MICROBLAZE
+#ifdef CONFIG_XILINX_UARTLITE
#include <asm/serial_xuartlite.h>
LIB := $(obj)libsk98lin.a
-COBJS := skge.o skaddr.o skgehwt.o skgeinit.o skgepnmi.o skgesirq.o \
- ski2c.o sklm80.o skqueue.o skrlmt.o sktimer.o skvpd.o \
- skxmac2.o skcsum.o #skproc.o
-
-COBJS += uboot_skb.o uboot_drv.o
-
+COBJS-y += skge.o
+COBJS-y += skaddr.o
+COBJS-y += skgehwt.o
+COBJS-y += skgeinit.o
+COBJS-y += skgepnmi.o
+COBJS-y += skgesirq.o
+COBJS-y += ski2c.o
+COBJS-y += sklm80.o
+COBJS-y += skqueue.o
+COBJS-y += skrlmt.o
+COBJS-y += sktimer.o
+COBJS-y += skvpd.o
+COBJS-y += skxmac2.o
+COBJS-y += skcsum.o
+#COBJS-y += skproc.o
+
+COBJS-y += uboot_skb.o
+COBJS-y += uboot_drv.o
+
+COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
static void adjust_link(struct eth_device *dev);
static void relocate_cmds(void);
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
+ && !defined(BITBANGMII)
static int tsec_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
static int tsec_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
+#endif
#ifdef CONFIG_MCAST_TFTP
static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
#endif
/* Tell the DMA it is clear to go */
regs->dmactrl |= DMACTRL_INIT_SETTINGS;
regs->tstat = TSTAT_CLEAR_THALT;
+ regs->rstat = RSTAT_CLEAR_RHALT;
regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
}
* The Tsi108 HW doesn't support sending just the chip address
* and checkong for an <ACK> back.
*/
- return i2c_read (chip, 0, 1, (char *)&tmp, 1);
+ return i2c_read (chip, 0, 1, (uchar *)&tmp, 1);
}
#endif
#include <pci.h>
#include <asm/io.h>
#include <tsi108.h>
+#ifdef CONFIG_OF_FLAT_TREE
+#include <ft_build.h>
+#endif
struct pci_controller local_hose;
--- /dev/null
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: Roy Zang <tie-fei.zang@freescale.com>, Sep, 2007
+ *
+ * Description:
+ * ULI 526x Ethernet port driver.
+ * Based on the Linux driver: drivers/net/tulip/uli526x.c
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <miiphy.h>
+
+/* some kernel function compatible define */
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
+ defined(CONFIG_ULI526X)
+
+#undef DEBUG
+
+/* Board/System/Debug information/definition */
+#define ULI_VENDOR_ID 0x10B9
+#define ULI5261_DEVICE_ID 0x5261
+#define ULI5263_DEVICE_ID 0x5263
+/* ULi M5261 ID*/
+#define PCI_ULI5261_ID ULI5261_DEVICE_ID << 16 | ULI_VENDOR_ID
+/* ULi M5263 ID*/
+#define PCI_ULI5263_ID ULI5263_DEVICE_ID << 16 | ULI_VENDOR_ID
+
+#define ULI526X_IO_SIZE 0x100
+#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
+#define RX_DESC_CNT PKTBUFSRX /* Allocated Rx descriptors */
+#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
+#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
+#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
+#define TX_BUF_ALLOC 0x300
+#define RX_ALLOC_SIZE PKTSIZE
+#define ULI526X_RESET 1
+#define CR0_DEFAULT 0
+#define CR6_DEFAULT 0x22200000
+#define CR7_DEFAULT 0x180c1
+#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
+#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
+#define MAX_PACKET_SIZE 1514
+#define ULI5261_MAX_MULTICAST 14
+#define RX_COPY_SIZE 100
+#define MAX_CHECK_PACKET 0x8000
+
+#define ULI526X_10MHF 0
+#define ULI526X_100MHF 1
+#define ULI526X_10MFD 4
+#define ULI526X_100MFD 5
+#define ULI526X_AUTO 8
+
+#define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
+#define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
+#define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
+#define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
+#define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
+#define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
+
+/* CR9 definition: SROM/MII */
+#define CR9_SROM_READ 0x4800
+#define CR9_SRCS 0x1
+#define CR9_SRCLK 0x2
+#define CR9_CRDOUT 0x8
+#define SROM_DATA_0 0x0
+#define SROM_DATA_1 0x4
+#define PHY_DATA_1 0x20000
+#define PHY_DATA_0 0x00000
+#define MDCLKH 0x10000
+
+#define PHY_POWER_DOWN 0x800
+
+#define SROM_V41_CODE 0x14
+
+#define SROM_CLK_WRITE(data, ioaddr) do { \
+ outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
+ udelay(5); \
+ outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr); \
+ udelay(5); \
+ outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
+ udelay(5); \
+ } while (0)
+
+/* Structure/enum declaration */
+
+struct tx_desc {
+ u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
+ char *tx_buf_ptr; /* Data for us */
+ struct tx_desc *next_tx_desc;
+};
+
+struct rx_desc {
+ u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
+ char *rx_buf_ptr; /* Data for us */
+ struct rx_desc *next_rx_desc;
+};
+
+struct uli526x_board_info {
+ u32 chip_id; /* Chip vendor/Device ID */
+ pci_dev_t pdev;
+
+ long ioaddr; /* I/O base address */
+ u32 cr0_data;
+ u32 cr5_data;
+ u32 cr6_data;
+ u32 cr7_data;
+ u32 cr15_data;
+
+ /* pointer for memory physical address */
+ dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
+ dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
+ dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
+ dma_addr_t first_tx_desc_dma;
+ dma_addr_t first_rx_desc_dma;
+
+ /* descriptor pointer */
+ unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
+ unsigned char *buf_pool_start; /* Tx buffer pool align dword */
+ unsigned char *desc_pool_ptr; /* descriptor pool memory */
+ struct tx_desc *first_tx_desc;
+ struct tx_desc *tx_insert_ptr;
+ struct tx_desc *tx_remove_ptr;
+ struct rx_desc *first_rx_desc;
+ struct rx_desc *rx_ready_ptr; /* packet come pointer */
+ unsigned long tx_packet_cnt; /* transmitted packet count */
+
+ u16 PHY_reg4; /* Saved Phyxcer register 4 value */
+
+ u8 media_mode; /* user specify media mode */
+ u8 op_mode; /* real work dedia mode */
+ u8 phy_addr;
+
+ /* NIC SROM data */
+ unsigned char srom[128];
+};
+
+enum uli526x_offsets {
+ DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
+ DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
+ DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
+ DCR15 = 0x78
+};
+
+enum uli526x_CR6_bits {
+ CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
+ CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
+ CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
+};
+
+/* Global variable declaration -- */
+
+static unsigned char uli526x_media_mode = ULI526X_AUTO;
+
+static struct tx_desc desc_pool_array[DESC_ALL_CNT + 0x20]
+ __attribute__ ((aligned(32)));
+static char buf_pool[TX_BUF_ALLOC * TX_DESC_CNT + 4];
+
+/* For module input parameter */
+static int mode = 8;
+
+/* function declaration -- */
+static int uli526x_start_xmit(struct eth_device *dev,
+ volatile void *packet, int length);
+static const struct ethtool_ops netdev_ethtool_ops;
+static u16 read_srom_word(long, int);
+static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
+static void allocate_rx_buffer(struct uli526x_board_info *);
+static void update_cr6(u32, unsigned long);
+static u16 phy_read(unsigned long, u8, u8, u32);
+static u16 phy_readby_cr10(unsigned long, u8, u8);
+static void phy_write(unsigned long, u8, u8, u16, u32);
+static void phy_writeby_cr10(unsigned long, u8, u8, u16);
+static void phy_write_1bit(unsigned long, u32, u32);
+static u16 phy_read_1bit(unsigned long, u32);
+static int uli526x_rx_packet(struct eth_device *);
+static void uli526x_free_tx_pkt(struct eth_device *,
+ struct uli526x_board_info *);
+static void uli526x_reuse_buf(struct rx_desc *);
+static void uli526x_init(struct eth_device *);
+static void uli526x_set_phyxcer(struct uli526x_board_info *);
+
+
+static int uli526x_init_one(struct eth_device *, bd_t *);
+static void uli526x_disable(struct eth_device *);
+static void set_mac_addr(struct eth_device *);
+
+static struct pci_device_id uli526x_pci_tbl[] = {
+ { ULI_VENDOR_ID, ULI5261_DEVICE_ID}, /* 5261 device */
+ { ULI_VENDOR_ID, ULI5263_DEVICE_ID}, /* 5263 device */
+ {}
+};
+
+/* ULI526X network board routine */
+
+/*
+ * Search ULI526X board, register it
+ */
+
+int uli526x_initialize(bd_t *bis)
+{
+ pci_dev_t devno;
+ int card_number = 0;
+ struct eth_device *dev;
+ struct uli526x_board_info *db; /* board information structure */
+
+ u32 iobase;
+ int idx = 0;
+
+ while (1) {
+ /* Find PCI device */
+ devno = pci_find_devices(uli526x_pci_tbl, idx++);
+ if (devno < 0)
+ break;
+
+ pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
+ iobase &= ~0xf;
+
+ dev = (struct eth_device *)malloc(sizeof *dev);
+ sprintf(dev->name, "uli526x#%d\n", card_number);
+ db = (struct uli526x_board_info *)
+ malloc(sizeof(struct uli526x_board_info));
+
+ dev->priv = db;
+ db->pdev = devno;
+ dev->iobase = iobase;
+
+ dev->init = uli526x_init_one;
+ dev->halt = uli526x_disable;
+ dev->send = uli526x_start_xmit;
+ dev->recv = uli526x_rx_packet;
+
+ /* init db */
+ db->ioaddr = dev->iobase;
+ /* get chip id */
+
+ pci_read_config_dword(devno, PCI_VENDOR_ID, &db->chip_id);
+#ifdef DEBUG
+ printf("uli526x: uli526x @0x%x\n", iobase);
+ printf("uli526x: chip_id%x\n", db->chip_id);
+#endif
+ eth_register(dev);
+ card_number++;
+ pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
+ udelay(10 * 1000);
+ }
+ return card_number;
+}
+
+static int uli526x_init_one(struct eth_device *dev, bd_t *bis)
+{
+
+ struct uli526x_board_info *db = dev->priv;
+ int i;
+
+ switch (mode) {
+ case ULI526X_10MHF:
+ case ULI526X_100MHF:
+ case ULI526X_10MFD:
+ case ULI526X_100MFD:
+ uli526x_media_mode = mode;
+ break;
+ default:
+ uli526x_media_mode = ULI526X_AUTO;
+ break;
+ }
+
+ /* Allocate Tx/Rx descriptor memory */
+ db->desc_pool_ptr = (uchar *)&desc_pool_array[0];
+ db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0];
+ if (db->desc_pool_ptr == NULL)
+ return 0;
+
+ db->buf_pool_ptr = &buf_pool[0];
+ db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0];
+ if (db->buf_pool_ptr == NULL)
+ return 0;
+
+ db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
+ db->first_tx_desc_dma = db->desc_pool_dma_ptr;
+
+ db->buf_pool_start = db->buf_pool_ptr;
+ db->buf_pool_dma_start = db->buf_pool_dma_ptr;
+
+#ifdef DEBUG
+ printf("%s(): db->ioaddr= 0x%x\n",
+ __FUNCTION__, db->ioaddr);
+ printf("%s(): media_mode= 0x%x\n",
+ __FUNCTION__, uli526x_media_mode);
+ printf("%s(): db->desc_pool_ptr= 0x%x\n",
+ __FUNCTION__, db->desc_pool_ptr);
+ printf("%s(): db->desc_pool_dma_ptr= 0x%x\n",
+ __FUNCTION__, db->desc_pool_dma_ptr);
+ printf("%s(): db->buf_pool_ptr= 0x%x\n",
+ __FUNCTION__, db->buf_pool_ptr);
+ printf("%s(): db->buf_pool_dma_ptr= 0x%x\n",
+ __FUNCTION__, db->buf_pool_dma_ptr);
+#endif
+
+ /* read 64 word srom data */
+ for (i = 0; i < 64; i++)
+ ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr,
+ i));
+
+ /* Set Node address */
+ if (((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0)
+ /* SROM absent, so write MAC address to ID Table */
+ set_mac_addr(dev);
+ else { /*Exist SROM*/
+ for (i = 0; i < 6; i++)
+ dev->enetaddr[i] = db->srom[20 + i];
+ }
+#ifdef DEBUG
+ for (i = 0; i < 6; i++)
+ printf("%c%02x", i ? ':' : ' ', dev->enetaddr[i]);
+#endif
+ db->PHY_reg4 = 0x1e0;
+
+ /* system variable init */
+ db->cr6_data = CR6_DEFAULT ;
+ db->cr6_data |= ULI526X_TXTH_256;
+ db->cr0_data = CR0_DEFAULT;
+ uli526x_init(dev);
+ return 1;
+}
+
+static void uli526x_disable(struct eth_device *dev)
+{
+#ifdef DEBUG
+ printf("uli526x_disable\n");
+#endif
+ struct uli526x_board_info *db = dev->priv;
+
+ if (!((inl(db->ioaddr + DCR12)) & 0x8)) {
+ /* Reset & stop ULI526X board */
+ outl(ULI526X_RESET, db->ioaddr + DCR0);
+ udelay(5);
+ phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
+
+ /* reset the board */
+ db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
+ update_cr6(db->cr6_data, dev->iobase);
+ outl(0, dev->iobase + DCR7); /* Disable Interrupt */
+ outl(inl(dev->iobase + DCR5), dev->iobase + DCR5);
+ }
+}
+
+/* Initialize ULI526X board
+ * Reset ULI526X board
+ * Initialize TX/Rx descriptor chain structure
+ * Send the set-up frame
+ * Enable Tx/Rx machine
+ */
+
+static void uli526x_init(struct eth_device *dev)
+{
+
+ struct uli526x_board_info *db = dev->priv;
+ u8 phy_tmp;
+ u16 phy_value;
+ u16 phy_reg_reset;
+
+ /* Reset M526x MAC controller */
+ outl(ULI526X_RESET, db->ioaddr + DCR0); /* RESET MAC */
+ udelay(100);
+ outl(db->cr0_data, db->ioaddr + DCR0);
+ udelay(5);
+
+ /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
+ db->phy_addr = 1;
+ db->tx_packet_cnt = 0;
+ for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
+ /* peer add */
+ phy_value = phy_read(db->ioaddr, phy_tmp, 3, db->chip_id);
+ if (phy_value != 0xffff && phy_value != 0) {
+ db->phy_addr = phy_tmp;
+ break;
+ }
+ }
+
+#ifdef DEBUG
+ printf("%s(): db->ioaddr= 0x%x\n", __FUNCTION__, db->ioaddr);
+ printf("%s(): db->phy_addr= 0x%x\n", __FUNCTION__, db->phy_addr);
+#endif
+ if (phy_tmp == 32)
+ printf("Can not find the phy address!!!");
+
+ /* Parser SROM and media mode */
+ db->media_mode = uli526x_media_mode;
+
+ if (!(inl(db->ioaddr + DCR12) & 0x8)) {
+ /* Phyxcer capability setting */
+ phy_reg_reset = phy_read(db->ioaddr,
+ db->phy_addr, 0, db->chip_id);
+ phy_reg_reset = (phy_reg_reset | 0x8000);
+ phy_write(db->ioaddr, db->phy_addr, 0,
+ phy_reg_reset, db->chip_id);
+ udelay(500);
+
+ /* Process Phyxcer Media Mode */
+ uli526x_set_phyxcer(db);
+ }
+ /* Media Mode Process */
+ if (!(db->media_mode & ULI526X_AUTO))
+ db->op_mode = db->media_mode; /* Force Mode */
+
+ /* Initialize Transmit/Receive decriptor and CR3/4 */
+ uli526x_descriptor_init(db, db->ioaddr);
+
+ /* Init CR6 to program M526X operation */
+ update_cr6(db->cr6_data, db->ioaddr);
+
+ /* Init CR7, interrupt active bit */
+ db->cr7_data = CR7_DEFAULT;
+ outl(db->cr7_data, db->ioaddr + DCR7);
+
+ /* Init CR15, Tx jabber and Rx watchdog timer */
+ outl(db->cr15_data, db->ioaddr + DCR15);
+
+ /* Enable ULI526X Tx/Rx function */
+ db->cr6_data |= CR6_RXSC | CR6_TXSC;
+ update_cr6(db->cr6_data, db->ioaddr);
+ while (!(inl(db->ioaddr + DCR12) & 0x8))
+ udelay(10);
+}
+
+/*
+ * Hardware start transmission.
+ * Send a packet to media from the upper layer.
+ */
+
+static int uli526x_start_xmit(struct eth_device *dev,
+ volatile void *packet, int length)
+{
+ struct uli526x_board_info *db = dev->priv;
+ struct tx_desc *txptr;
+ unsigned int len = length;
+ /* Too large packet check */
+ if (len > MAX_PACKET_SIZE) {
+ printf(": big packet = %d\n", len);
+ return 0;
+ }
+
+ /* No Tx resource check, it never happen nromally */
+ if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
+ printf("No Tx resource %ld\n", db->tx_packet_cnt);
+ return 0;
+ }
+
+ /* Disable NIC interrupt */
+ outl(0, dev->iobase + DCR7);
+
+ /* transmit this packet */
+ txptr = db->tx_insert_ptr;
+ memcpy((char *)txptr->tx_buf_ptr, (char *)packet, (int)length);
+ txptr->tdes1 = cpu_to_le32(0xe1000000 | length);
+
+ /* Point to next transmit free descriptor */
+ db->tx_insert_ptr = txptr->next_tx_desc;
+
+ /* Transmit Packet Process */
+ if ((db->tx_packet_cnt < TX_DESC_CNT)) {
+ txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
+ db->tx_packet_cnt++; /* Ready to send */
+ outl(0x1, dev->iobase + DCR1); /* Issue Tx polling */
+ }
+
+ /* Got ULI526X status */
+ db->cr5_data = inl(db->ioaddr + DCR5);
+ outl(db->cr5_data, db->ioaddr + DCR5);
+
+#ifdef TX_DEBUG
+ printf("%s(): length = 0x%x\n", __FUNCTION__, length);
+ printf("%s(): cr5_data=%x\n", __FUNCTION__, db->cr5_data);
+#endif
+
+ outl(db->cr7_data, dev->iobase + DCR7);
+ uli526x_free_tx_pkt(dev, db);
+
+ return length;
+}
+
+/*
+ * Free TX resource after TX complete
+ */
+
+static void uli526x_free_tx_pkt(struct eth_device *dev,
+ struct uli526x_board_info *db)
+{
+ struct tx_desc *txptr;
+ u32 tdes0;
+
+ txptr = db->tx_remove_ptr;
+ while (db->tx_packet_cnt) {
+ tdes0 = le32_to_cpu(txptr->tdes0);
+ /* printf(DRV_NAME ": tdes0=%x\n", tdes0); */
+ if (tdes0 & 0x80000000)
+ break;
+
+ /* A packet sent completed */
+ db->tx_packet_cnt--;
+
+ if (tdes0 != 0x7fffffff) {
+#ifdef TX_DEBUG
+ printf("%s()tdes0=%x\n", __FUNCTION__, tdes0);
+#endif
+ if (tdes0 & TDES0_ERR_MASK) {
+ if (tdes0 & 0x0002) { /* UnderRun */
+ if (!(db->cr6_data & CR6_SFT)) {
+ db->cr6_data = db->cr6_data |
+ CR6_SFT;
+ update_cr6(db->cr6_data,
+ db->ioaddr);
+ }
+ }
+ }
+ }
+
+ txptr = txptr->next_tx_desc;
+ }/* End of while */
+
+ /* Update TX remove pointer to next */
+ db->tx_remove_ptr = txptr;
+}
+
+
+/*
+ * Receive the come packet and pass to upper layer
+ */
+
+static int uli526x_rx_packet(struct eth_device *dev)
+{
+ struct uli526x_board_info *db = dev->priv;
+ struct rx_desc *rxptr;
+ int rxlen = 0;
+ u32 rdes0;
+
+ rxptr = db->rx_ready_ptr;
+
+ rdes0 = le32_to_cpu(rxptr->rdes0);
+#ifdef RX_DEBUG
+ printf("%s(): rxptr->rdes0=%x:%x\n", __FUNCTION__, rxptr->rdes0);
+#endif
+ if (!(rdes0 & 0x80000000)) { /* packet owner check */
+ if ((rdes0 & 0x300) != 0x300) {
+ /* A packet without First/Last flag */
+ /* reuse this buf */
+ printf("A packet without First/Last flag");
+ uli526x_reuse_buf(rxptr);
+ } else {
+ /* A packet with First/Last flag */
+ rxlen = ((rdes0 >> 16) & 0x3fff) - 4;
+#ifdef RX_DEBUG
+ printf("%s(): rxlen =%x\n", __FUNCTION__, rxlen);
+#endif
+ /* error summary bit check */
+ if (rdes0 & 0x8000) {
+ /* This is a error packet */
+ printf("Eroor: rdes0: %lx\n", rdes0);
+ }
+
+ if (!(rdes0 & 0x8000) ||
+ ((db->cr6_data & CR6_PM) && (rxlen > 6))) {
+
+#ifdef RX_DEBUG
+ printf("%s(): rx_skb_ptr =%x\n",
+ __FUNCTION__, rxptr->rx_buf_ptr);
+ printf("%s(): rxlen =%x\n",
+ __FUNCTION__, rxlen);
+
+ printf("%s(): buf addr =%x\n",
+ __FUNCTION__, rxptr->rx_buf_ptr);
+ printf("%s(): rxlen =%x\n",
+ __FUNCTION__, rxlen);
+ int i;
+ for (i = 0; i < 0x20; i++)
+ printf("%s(): data[%x] =%x\n",
+ __FUNCTION__, i, rxptr->rx_buf_ptr[i]);
+#endif
+
+ NetReceive(rxptr->rx_buf_ptr, rxlen);
+ uli526x_reuse_buf(rxptr);
+
+ } else {
+ /* Reuse SKB buffer when the packet is error */
+ printf("Reuse buffer, rdes0");
+ uli526x_reuse_buf(rxptr);
+ }
+ }
+
+ rxptr = rxptr->next_rx_desc;
+ }
+
+ db->rx_ready_ptr = rxptr;
+ return rxlen;
+}
+
+/*
+ * Reuse the RX buffer
+ */
+
+static void uli526x_reuse_buf(struct rx_desc *rxptr)
+{
+
+ if (!(rxptr->rdes0 & cpu_to_le32(0x80000000)))
+ rxptr->rdes0 = cpu_to_le32(0x80000000);
+ else
+ printf("Buffer reuse method error");
+}
+/*
+ * Initialize transmit/Receive descriptor
+ * Using Chain structure, and allocate Tx/Rx buffer
+ */
+
+static void uli526x_descriptor_init(struct uli526x_board_info *db,
+ unsigned long ioaddr)
+{
+ struct tx_desc *tmp_tx;
+ struct rx_desc *tmp_rx;
+ unsigned char *tmp_buf;
+ dma_addr_t tmp_tx_dma, tmp_rx_dma;
+ dma_addr_t tmp_buf_dma;
+ int i;
+ /* tx descriptor start pointer */
+ db->tx_insert_ptr = db->first_tx_desc;
+ db->tx_remove_ptr = db->first_tx_desc;
+
+ outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
+
+ /* rx descriptor start pointer */
+ db->first_rx_desc = (void *)db->first_tx_desc +
+ sizeof(struct tx_desc) * TX_DESC_CNT;
+ db->first_rx_desc_dma = db->first_tx_desc_dma +
+ sizeof(struct tx_desc) * TX_DESC_CNT;
+ db->rx_ready_ptr = db->first_rx_desc;
+ outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
+#ifdef DEBUG
+ printf("%s(): db->first_tx_desc= 0x%x\n",
+ __FUNCTION__, db->first_tx_desc);
+ printf("%s(): db->first_rx_desc_dma= 0x%x\n",
+ __FUNCTION__, db->first_rx_desc_dma);
+#endif
+ /* Init Transmit chain */
+ tmp_buf = db->buf_pool_start;
+ tmp_buf_dma = db->buf_pool_dma_start;
+ tmp_tx_dma = db->first_tx_desc_dma;
+ for (tmp_tx = db->first_tx_desc, i = 0;
+ i < TX_DESC_CNT; i++, tmp_tx++) {
+ tmp_tx->tx_buf_ptr = tmp_buf;
+ tmp_tx->tdes0 = cpu_to_le32(0);
+ tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
+ tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
+ tmp_tx_dma += sizeof(struct tx_desc);
+ tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
+ tmp_tx->next_tx_desc = tmp_tx + 1;
+ tmp_buf = tmp_buf + TX_BUF_ALLOC;
+ tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
+ }
+ (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
+ tmp_tx->next_tx_desc = db->first_tx_desc;
+
+ /* Init Receive descriptor chain */
+ tmp_rx_dma = db->first_rx_desc_dma;
+ for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT;
+ i++, tmp_rx++) {
+ tmp_rx->rdes0 = cpu_to_le32(0);
+ tmp_rx->rdes1 = cpu_to_le32(0x01000600);
+ tmp_rx_dma += sizeof(struct rx_desc);
+ tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
+ tmp_rx->next_rx_desc = tmp_rx + 1;
+ }
+ (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
+ tmp_rx->next_rx_desc = db->first_rx_desc;
+
+ /* pre-allocate Rx buffer */
+ allocate_rx_buffer(db);
+}
+
+/*
+ * Update CR6 value
+ * Firstly stop ULI526X, then written value and start
+ */
+
+static void update_cr6(u32 cr6_data, unsigned long ioaddr)
+{
+
+ outl(cr6_data, ioaddr + DCR6);
+ udelay(5);
+}
+
+/*
+ * Allocate rx buffer,
+ */
+
+static void allocate_rx_buffer(struct uli526x_board_info *db)
+{
+ int index;
+ struct rx_desc *rxptr;
+ rxptr = db->first_rx_desc;
+ u32 addr;
+
+ for (index = 0; index < RX_DESC_CNT; index++) {
+ addr = (u32)NetRxPackets[index];
+ addr += (16 - (addr & 15));
+ rxptr->rx_buf_ptr = (char *) addr;
+ rxptr->rdes2 = cpu_to_le32(addr);
+ rxptr->rdes0 = cpu_to_le32(0x80000000);
+#ifdef DEBUG
+ printf("%s(): Number 0x%x:\n", __FUNCTION__, index);
+ printf("%s(): addr 0x%x:\n", __FUNCTION__, addr);
+ printf("%s(): rxptr address = 0x%x\n", __FUNCTION__, rxptr);
+ printf("%s(): rxptr buf address = 0x%x\n", \
+ __FUNCTION__, rxptr->rx_buf_ptr);
+ printf("%s(): rdes2 = 0x%x\n", __FUNCTION__, rxptr->rdes2);
+#endif
+ rxptr = rxptr->next_rx_desc;
+ }
+}
+
+/*
+ * Read one word data from the serial ROM
+ */
+
+static u16 read_srom_word(long ioaddr, int offset)
+{
+ int i;
+ u16 srom_data = 0;
+ long cr9_ioaddr = ioaddr + DCR9;
+
+ outl(CR9_SROM_READ, cr9_ioaddr);
+ outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
+
+ /* Send the Read Command 110b */
+ SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
+ SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
+ SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
+
+ /* Send the offset */
+ for (i = 5; i >= 0; i--) {
+ srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
+ SROM_CLK_WRITE(srom_data, cr9_ioaddr);
+ }
+
+ outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
+
+ for (i = 16; i > 0; i--) {
+ outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
+ udelay(5);
+ srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT)
+ ? 1 : 0);
+ outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
+ udelay(5);
+ }
+
+ outl(CR9_SROM_READ, cr9_ioaddr);
+ return srom_data;
+}
+
+/*
+ * Set 10/100 phyxcer capability
+ * AUTO mode : phyxcer register4 is NIC capability
+ * Force mode: phyxcer register4 is the force media
+ */
+
+static void uli526x_set_phyxcer(struct uli526x_board_info *db)
+{
+ u16 phy_reg;
+
+ /* Phyxcer capability setting */
+ phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
+
+ if (db->media_mode & ULI526X_AUTO) {
+ /* AUTO Mode */
+ phy_reg |= db->PHY_reg4;
+ } else {
+ /* Force Mode */
+ switch (db->media_mode) {
+ case ULI526X_10MHF: phy_reg |= 0x20; break;
+ case ULI526X_10MFD: phy_reg |= 0x40; break;
+ case ULI526X_100MHF: phy_reg |= 0x80; break;
+ case ULI526X_100MFD: phy_reg |= 0x100; break;
+ }
+
+ }
+
+ /* Write new capability to Phyxcer Reg4 */
+ if (!(phy_reg & 0x01e0)) {
+ phy_reg |= db->PHY_reg4;
+ db->media_mode |= ULI526X_AUTO;
+ }
+ phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
+
+ /* Restart Auto-Negotiation */
+ phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
+ udelay(50);
+}
+
+/*
+ * Write a word to Phy register
+ */
+
+static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
+ u16 phy_data, u32 chip_id)
+{
+ u16 i;
+ unsigned long ioaddr;
+
+ if (chip_id == PCI_ULI5263_ID) {
+ phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
+ return;
+ }
+ /* M5261/M5263 Chip */
+ ioaddr = iobase + DCR9;
+
+ /* Send 33 synchronization clock to Phy controller */
+ for (i = 0; i < 35; i++)
+ phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
+
+ /* Send start command(01) to Phy */
+ phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
+ phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
+
+ /* Send write command(01) to Phy */
+ phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
+ phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
+
+ /* Send Phy address */
+ for (i = 0x10; i > 0; i = i >> 1)
+ phy_write_1bit(ioaddr, phy_addr & i ?
+ PHY_DATA_1 : PHY_DATA_0, chip_id);
+
+ /* Send register address */
+ for (i = 0x10; i > 0; i = i >> 1)
+ phy_write_1bit(ioaddr, offset & i ?
+ PHY_DATA_1 : PHY_DATA_0, chip_id);
+
+ /* written trasnition */
+ phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
+ phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
+
+ /* Write a word data to PHY controller */
+ for (i = 0x8000; i > 0; i >>= 1)
+ phy_write_1bit(ioaddr, phy_data & i ?
+ PHY_DATA_1 : PHY_DATA_0, chip_id);
+}
+
+/*
+ * Read a word data from phy register
+ */
+
+static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
+{
+ int i;
+ u16 phy_data;
+ unsigned long ioaddr;
+
+ if (chip_id == PCI_ULI5263_ID)
+ return phy_readby_cr10(iobase, phy_addr, offset);
+ /* M5261/M5263 Chip */
+ ioaddr = iobase + DCR9;
+
+ /* Send 33 synchronization clock to Phy controller */
+ for (i = 0; i < 35; i++)
+ phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
+
+ /* Send start command(01) to Phy */
+ phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
+ phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
+
+ /* Send read command(10) to Phy */
+ phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
+ phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
+
+ /* Send Phy address */
+ for (i = 0x10; i > 0; i = i >> 1)
+ phy_write_1bit(ioaddr, phy_addr & i ?
+ PHY_DATA_1 : PHY_DATA_0, chip_id);
+
+ /* Send register address */
+ for (i = 0x10; i > 0; i = i >> 1)
+ phy_write_1bit(ioaddr, offset & i ?
+ PHY_DATA_1 : PHY_DATA_0, chip_id);
+
+ /* Skip transition state */
+ phy_read_1bit(ioaddr, chip_id);
+
+ /* read 16bit data */
+ for (phy_data = 0, i = 0; i < 16; i++) {
+ phy_data <<= 1;
+ phy_data |= phy_read_1bit(ioaddr, chip_id);
+ }
+
+ return phy_data;
+}
+
+static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
+{
+ unsigned long ioaddr, cr10_value;
+
+ ioaddr = iobase + DCR10;
+ cr10_value = phy_addr;
+ cr10_value = (cr10_value<<5) + offset;
+ cr10_value = (cr10_value<<16) + 0x08000000;
+ outl(cr10_value, ioaddr);
+ udelay(1);
+ while (1) {
+ cr10_value = inl(ioaddr);
+ if (cr10_value & 0x10000000)
+ break;
+ }
+ return (cr10_value&0x0ffff);
+}
+
+static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr,
+ u8 offset, u16 phy_data)
+{
+ unsigned long ioaddr, cr10_value;
+
+ ioaddr = iobase + DCR10;
+ cr10_value = phy_addr;
+ cr10_value = (cr10_value<<5) + offset;
+ cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
+ outl(cr10_value, ioaddr);
+ udelay(1);
+}
+/*
+ * Write one bit data to Phy Controller
+ */
+
+static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
+{
+ outl(phy_data , ioaddr); /* MII Clock Low */
+ udelay(1);
+ outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
+ udelay(1);
+ outl(phy_data , ioaddr); /* MII Clock Low */
+ udelay(1);
+}
+
+/*
+ * Read one bit phy data from PHY controller
+ */
+
+static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
+{
+ u16 phy_data;
+
+ outl(0x50000 , ioaddr);
+ udelay(1);
+ phy_data = (inl(ioaddr) >> 19) & 0x1;
+ outl(0x40000 , ioaddr);
+ udelay(1);
+
+ return phy_data;
+}
+
+/*
+ * Set MAC address to ID Table
+ */
+
+static void set_mac_addr(struct eth_device *dev)
+{
+ int i;
+ u16 addr;
+ struct uli526x_board_info *db = dev->priv;
+ outl(0x10000, db->ioaddr + DCR0); /* Diagnosis mode */
+ /* Reset dianostic pointer port */
+ outl(0x1c0, db->ioaddr + DCR13);
+ outl(0, db->ioaddr + DCR14); /* Clear reset port */
+ outl(0x10, db->ioaddr + DCR14); /* Reset ID Table pointer */
+ outl(0, db->ioaddr + DCR14); /* Clear reset port */
+ outl(0, db->ioaddr + DCR13); /* Clear CR13 */
+ /* Select ID Table access port */
+ outl(0x1b0, db->ioaddr + DCR13);
+ /* Read MAC address from CR14 */
+ for (i = 0; i < 3; i++) {
+ addr = dev->enetaddr[2 * i] | (dev->enetaddr[2 * i + 1] << 8);
+ outl(addr, db->ioaddr + DCR14);
+ }
+ /* write end */
+ outl(0, db->ioaddr + DCR13); /* Clear CR13 */
+ outl(0, db->ioaddr + DCR0); /* Clear CR0 */
+ udelay(10);
+ return;
+}
+#endif
#include <usb.h>
#include "usb_ohci.h"
+#ifdef CONFIG_AT91RM9200
+#include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */
+#endif
+
#if defined(CONFIG_ARM920T) || \
defined(CONFIG_S3C2400) || \
defined(CONFIG_S3C2410) || \
#ifdef CONFIG_PCI_OHCI
static struct pci_device_id ohci_pci_ids[] = {
{0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */
+ {0x1033, 0x0035}, /* NEC PCI OHCI module ids */
/* Please add supported PCI OHCI controller ids here */
{0, 0}
};
LIB = $(obj)libdtt.a
-COBJS = lm75.o ds1621.o adm1021.o lm81.o ds1775.o
+COBJS-y += lm75.o
+COBJS-y += ds1621.o
+COBJS-y += adm1021.o
+COBJS-y += lm81.o
+COBJS-y += ds1775.o
+COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
--- /dev/null
+/hello_world
+/interrupt
+/sched
+*.bin
+*.srec
. = ALIGN(4);
.data : { *(.data) }
- . = ALIGN(4);
- .sdata : { *(.sdata) }
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
- _gp = ALIGN(16);
-
- __got_start = .;
- .got : { *(.got) }
- __got_end = .;
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
.sdata : { *(.sdata) }
LIB = $(obj)libjffs2.a
AOBJS =
-COBJS = jffs2_1pass.o compr_rtime.o compr_rubin.o compr_zlib.o mini_inflate.o
-COBJS += compr_lzo.o compr_lzari.o
-
+COBJS-y += jffs2_1pass.o
+COBJS-y += compr_rtime.o
+COBJS-y += compr_rubin.o
+COBJS-y += compr_zlib.o
+COBJS-y += mini_inflate.o
+COBJS-y += compr_lzo.o
+COBJS-y += compr_lzari.o
+
+COBJS := $(COBJS-y)
SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))
--- /dev/null
+/asm
+/asm-ppc/arch
+/bmp_logo.h
+/config.h
+/config.mk
+/version_autogenerated.h
#ifndef __ASSEMBLY__
#include "AT91RM9200.h"
-#else
-#include "AT91RM9200_inc.h"
#endif
/* Virtual and Physical base address for system peripherals */
#define __ASM_AVR32_STRING_H
#define __HAVE_ARCH_MEMSET
-extern void *memset(void *s, int c, size_t n);
+extern void *memset(void *s, int c, __kernel_size_t n);
#endif /* __ASM_AVR32_STRING_H */
#define MMAP_PWM 0xFC090000
#define MMAP_EPORT 0xFC094000
#define MMAP_WDOG 0xFC098000
-#define MMAP_CCM 0xFC0A0000
+#define MMAP_RCM 0xFC0A0000
+#define MMAP_CCM 0xFC0A0004
#define MMAP_GPIO 0xFC0A4000
#define MMAP_RTC 0xFC0A8000
#define MMAP_LCDC 0xFC0AC000
/*Chip configuration module registers */
typedef struct ccm_ctrl {
- u8 rstctrl; /* 0x00 Reset Controller register */
- u8 rststat; /* 0x01 Reset Status register */
- u16 res1; /* 0x02 - 0x03 */
- u16 ccr; /* 0x04 Chip configuration register */
- u16 res2; /* 0x06 */
- u16 rcon; /* 0x08 Rreset configuration register */
- u16 cir; /* 0x0A Chip identification register */
- u32 res3; /* 0x0C */
- u16 misccr; /* 0x10 Miscellaneous control register */
- u16 cdr; /* 0x12 Clock divider register */
- u16 uhcsr; /* 0x14 USB Host controller status register */
- u16 uocsr; /* 0x16 USB On-the-Go Controller Status Register */
+ u16 ccr; /* 0x00 Chip configuration register */
+ u16 res2; /* 0x02 */
+ u16 rcon; /* 0x04 Rreset configuration register */
+ u16 cir; /* 0x06 Chip identification register */
+ u32 res3; /* 0x08 */
+ u16 misccr; /* 0x0A Miscellaneous control register */
+ u16 cdr; /* 0x0C Clock divider register */
+ u16 uhcsr; /* 0x10 USB Host controller status register */
+ u16 uocsr; /* 0x12 USB On-the-Go Controller Status Reg */
} ccm_t;
+typedef struct rcm {
+ u8 rcr;
+ u8 rsr;
+} rcm_t;
+
/* GPIO port registers */
typedef struct gpio_ctrl {
/* Port Output Data Registers */
#define CSCR_BSTW (0x00000008)
/*********************************************************************
+* Reset Controller Module (RCM)
+*********************************************************************/
+
+/* Bit definitions and macros for RCR */
+#define RCM_RCR_FRCRSTOUT (0x40)
+#define RCM_RCR_SOFTRST (0x80)
+
+/* Bit definitions and macros for RSR */
+#define RCM_RSR_LOL (0x01)
+#define RCM_RSR_WDR_CORE (0x02)
+#define RCM_RSR_EXT (0x04)
+#define RCM_RSR_POR (0x08)
+#define RCM_RSR_SOFT (0x20)
+
+/*********************************************************************
* FlexCAN Module (CAN)
*********************************************************************/
/* Bit definitions and macros for CAN_CANMCR */
#define GPIO_PAR_FEC_FEC0_MASK (0xF8)
#define GPIO_PAR_FEC_FEC0_MII (0x07)
#define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03)
-#define GPIO_PAR_FEC_FEC0_RMII_ATA (0x02)
-#define GPIO_PAR_FEC_FEC0_ATA (0x01)
+#define GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02)
+#define GPIO_PAR_FEC_FEC0_ULPI (0x01)
#define GPIO_PAR_FEC_FEC0_GPIO (0x00)
/* Bit definitions and macros for PAR_DMA */
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
#else /* !CONFIG_AU1X00 */
-#define UNCACHED_SDRAM(a) PHYSADDR(a)
+#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
#endif /* CONFIG_AU1X00 */
#endif /* __ASSEMBLY__ */
/*
* instruction, so the lower 16 bits must be zero. Should be true on
* on any sane architecture; generic code does not use this assumption.
*/
-extern unsigned long mips_io_port_base;
+extern const unsigned long mips_io_port_base;
+
+/*
+ * Gcc will generate code to load the value of mips_io_port_base after each
+ * function call which may be fairly wasteful in some cases. So we don't
+ * play quite by the book. We tell gcc mips_io_port_base is a long variable
+ * which solves the code generation issue. Now we need to violate the
+ * aliasing rules a little to make initialization possible and finally we
+ * will need the barrier() to fight side effects of the aliasing chat.
+ * This trickery will eventually collapse under gcc's optimizer. Oh well.
+ */
+static inline void set_io_port_base(unsigned long base)
+{
+ * (unsigned long *) &mips_io_port_base = base;
+}
/*
* Thanks to James van Artsdalen for a better timing-fix than
extern char *strcpy(char *__dest, __const__ char *__src);
#undef __HAVE_ARCH_STRNCPY
-extern char *strncpy(char *__dest, __const__ char *__src, size_t __n);
+extern char *strncpy(char *__dest, __const__ char *__src, __kernel_size_t __n);
#undef __HAVE_ARCH_STRCMP
extern int strcmp(__const__ char *__cs, __const__ char *__ct);
#undef __HAVE_ARCH_STRNCMP
-extern int strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count);
+extern int strncmp(__const__ char *__cs, __const__ char *__ct, __kernel_size_t __count);
#undef __HAVE_ARCH_MEMSET
-extern void *memset(void *__s, int __c, size_t __count);
+extern void *memset(void *__s, int __c, __kernel_size_t __count);
#undef __HAVE_ARCH_MEMCPY
-extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
+extern void *memcpy(void *__to, __const__ void *__from, __kernel_size_t __n);
#undef __HAVE_ARCH_MEMMOVE
-extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
+extern void *memmove(void *__dest, __const__ void *__src, __kernel_size_t __n);
#endif /* _ASM_STRING_H */
#endif
#elif defined(CONFIG_5xx)
#include <asm/5xx_immap.h>
-#define CONFIG_RELOC_FIXUP_WORKS
#elif defined(CONFIG_MPC5xxx)
#include <mpc5xxx.h>
-#define CONFIG_RELOC_FIXUP_WORKS
#elif defined(CONFIG_MPC512X)
#include <mpc512x.h>
#include <asm/immap_512x.h>
-#define CONFIG_RELOC_FIXUP_WORKS
#elif defined(CONFIG_MPC8220)
#include <asm/immap_8220.h>
-#define CONFIG_RELOC_FIXUP_WORKS
-#elif defined(CONFIG_824X)
-#define CONFIG_RELOC_FIXUP_WORKS
#elif defined(CONFIG_8260)
#if defined(CONFIG_MPC8247) \
|| defined(CONFIG_MPC8248) \
#define CONFIG_MPC8260 1
#endif
#include <asm/immap_8260.h>
-#define CONFIG_RELOC_FIXUP_WORKS
#endif
#ifdef CONFIG_MPC86xx
#include <mpc86xx.h>
#ifdef CONFIG_MPC83XX
#include <mpc83xx.h>
#include <asm/immap_83xx.h>
-#define CONFIG_RELOC_FIXUP_WORKS
#endif
#ifdef CONFIG_4xx
#include <ppc4xx.h>
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_ONENAND /* OneNAND support */
#define CONFIG_CMD_PCI /* pciinfo */
#define CONFIG_CMD_PCMCIA /* PCMCIA support */
#define CONFIG_CMD_PING /* ping support */
#define CONFIG_CMD_USB /* USB Support */
#define CONFIG_CMD_VFD /* VFD support (TRAB) */
#define CONFIG_CMD_XIMG /* Load part of Multi Image */
-#define CONFIG_CMD_MUX /* AT91 MMC/SPI Mux Support */
+#define CONFIG_CMD_AT91_SPIMUX /* AT91 MMC/SPI Mux Support */
#endif /* _CONFIG_CMD_ALL_H */
/*
* Command line configuration.
*/
-#include <config_cmd_all.h>
-
-#undef CONFIG_CMD_ASKENV
-#undef CONFIG_CMD_BEDBUG
-#undef CONFIG_CMD_BMP
-#undef CONFIG_CMD_CACHE
-#undef CONFIG_CMD_DOC
-#undef CONFIG_CMD_DTT
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_ELF
-#undef CONFIG_CMD_FAT
-#undef CONFIG_CMD_FDC
-#undef CONFIG_CMD_FDOS
-#undef CONFIG_CMD_HWFLOW
-#undef CONFIG_CMD_IDE
-#undef CONFIG_CMD_I2C
-#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_KGDB
-#undef CONFIG_CMD_NAND
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DISPLAY
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_REISER
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_MMC
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_PCI
-#undef CONFIG_CMD_PCMCIA
-#undef CONFIG_CMD_SCSI
-#undef CONFIG_CMD_VFD
-#undef CONFIG_CMD_USB
#undef CONFIG_CMD_XIMG
-#if (CFG_NIOS_CPU_SPI_NUMS != 1)
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_DATE
+#if (CFG_NIOS_CPU_SPI_NUMS == 1)
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_SPI
#endif
/*------------------------------------------------------------------------
/*
* Command line configuration.
*/
-#include <config_cmd_all.h>
-
-#undef CONFIG_CMD_ASKENV
-#undef CONFIG_CMD_BEDBUG
-#undef CONFIG_CMD_BMP
-#undef CONFIG_CMD_BSP
-#undef CONFIG_CMD_CACHE
-#undef CONFIG_CMD_DATE
-#undef CONFIG_CMD_DOC
-#undef CONFIG_CMD_DTT
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_ELF
-#undef CONFIG_CMD_FDC
-#undef CONFIG_CMD_FDOS
-#undef CONFIG_CMD_HWFLOW
-#undef CONFIG_CMD_I2C
-#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_KGDB
-#undef CONFIG_CMD_NAND
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DISPLAY
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_MMC
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_PCI
-#undef CONFIG_CMD_PCMCIA
-#undef CONFIG_CMD_REISER
-#undef CONFIG_CMD_SCSI
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_VFD
-#undef CONFIG_CMD_USB
#undef CONFIG_CMD_XIMG
-
/*------------------------------------------------------------------------
* COMPACT FLASH
*----------------------------------------------------------------------*/
/*
* Command line configuration.
*/
-#include <config_cmd_all.h>
-
-#undef CONFIG_CMD_ASKENV
-#undef COND_CMD_BEDBUG
-#undef COND_CMD_BMP
-#undef COND_CMD_BSP
-#undef COND_CMD_CACHE
-#undef COND_CMD_DATE
-#undef COND_CMD_DOC
-#undef COND_CMD_DTT
-#undef COND_CMD_EEPROM
-#undef COND_CMD_ELF
-#undef COND_CMD_FAT
-#undef COND_CMD_FDC
-#undef COND_CMD_FDOS
-#undef COND_CMD_HWFLOW
-#undef COND_CMD_IDE
-#undef COND_CMD_I2C
-#undef COND_CMD_JFFS2
-#undef COND_CMD_KGDB
-#undef COND_CMD_NAND
-#undef COND_CMD_NFS
-#undef COND_CMD_MMC
-#undef COND_CMD_MII
-#undef COND_CMD_PCI
-#undef COND_CMD_PCMCIA
-#undef COND_CMD_SCSI
-#undef COND_CMD_SPI
-#undef COND_CMD_VFD
-#undef COND_CMD_USB
-#undef COND_CMD_XIMG
-
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DISPLAY
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_REISER
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_XIMG
/*------------------------------------------------------------------------
* KGDB
#define CFG_NS16550_COM1 (CFG_UART_BASE + 0x8000)
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_CPU "PowerPC,8247@0"
+#define OF_SOC "soc@f0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000"
+
+
/*
* select ethernet configuration
*
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
#undef CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
+#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
+#define CONFIG_ETHER_ON_FCC1
+#define FCC_ENET
/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
+ * - Rx-CLK is CLK10
+ * - Tx-CLK is CLK9
* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
* - Enable Full Duplex in FSMR
*/
-# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
# define CFG_CPMFCR_RAMTYPE 0
# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR 0x51
/*
* Command line configuration.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CFG_FLASH_BANKS_LIST { 0xFF800000 }
+#define CFG_MAX_FLASH_BANKS_DETECT 1
/* What should the base address of the main FLASH be and how big is
* it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk
* The main FLASH is whichever is connected to *CS0.
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CFG_MAX_FLASH_SECT 64 /* max num of sects on one chip */
+#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
*/
#define CFG_OR2 ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A10 |\
+ ORxS_ROWST_PBI0_A9 |\
ORxS_NUMR_12)
-#define CFG_PSDMR (PSDMR_SDAM_A13_IS_A5 |\
+#define CFG_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
PSDMR_BSMA_A15_A17 |\
- PSDMR_SDA10_PBI0_A11 |\
+ PSDMR_SDA10_PBI0_A10 |\
PSDMR_RFRC_5_CLK |\
PSDMR_PRETOACT_2W |\
PSDMR_ACTTORW_2W |\
/*
* Command line configuration.
*/
-#include <config_cmd_all.h>
-
-#undef CONFIG_CMD_BEDBUG
-#undef CONFIG_CMD_BMP
-#undef CONFIG_CMD_BSP
-#undef CONFIG_CMD_DISPLAY
-#undef CONFIG_CMD_DOC
-#undef CONFIG_CMD_DTT
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_ELF
-#undef CONFIG_CMD_EXT2
-#undef CONFIG_CMD_FDC
-#undef CONFIG_CMD_FDOS
-#undef CONFIG_CMD_HWFLOW
-#undef CONFIG_CMD_I2C
-#undef CONFIG_CMD_IDE
-#undef CONFIG_CMD_IRQ
-#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_KGDB
-#undef CONFIG_CMD_MFSL
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_MMC
-#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_PCI
-#undef CONFIG_CMD_PCMCIA
-#undef CONFIG_CMD_REISER
-#undef CONFIG_CMD_SCSI
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_UNIVERSE
-#undef CONFIG_CMD_USB
-#undef CONFIG_CMD_VFD
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#undef CONFIG_CMD_XIMG
#if !(CONFIG_LANTEC >= 2)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */
#ifdef CONFIG_MONITOR_IS_IN_RAM
#define CFG_MONITOR_BASE 0x20000
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_FLASH_BASE 0xffe00000
#define CFG_INT_FLASH_BASE 0xf0000000
#define CFG_INT_FLASH_ENABLE 0x21
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x40000000
-#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CFG_SDRAM_CFG1 0x53722730
#define CFG_SDRAM_CFG2 0x56670000
#define CFG_SDRAM_CTRL 0xE1092000
* board/config.h - configuration options, board specific
*/
-#ifndef _JAMICA54455_H
-#define _JAMICA54455_H
+#ifndef _M54455EVB_H
+#define _M54455EVB_H
/*
* High Level Configuration Options
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
+#undef CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
- "prog=prot off 0 2ffff;" \
- "era 0 2ffff;" \
+ "prog=prot off 4000000 402ffff;" \
+ "era 4000000 402ffff;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \
""
#define CFG_IMMR CFG_MBAR
/* PCI */
+#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI 1
#define CFG_PCI_MEM_BUS 0xA0000000
#define CFG_PCI_CFG_BUS 0xB0000000
#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS
#define CFG_PCI_CFG_SIZE 0x01000000
+#endif
/* FPGA - Spartan 2 */
/* experiment
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
-#define CFG_ENV_OFFSET 0x4000
-#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OVERWRITE 1
#undef CFG_ENV_IS_EMBEDDED
* FLASH organization
*/
#ifdef CFG_ATMEL_BOOT
-# define CFG_FLASH_BASE 0
+# define CFG_FLASH_BASE CFG_CS0_BASE
# define CFG_FLASH0_BASE CFG_CS0_BASE
# define CFG_FLASH1_BASE CFG_CS1_BASE
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000)
+# define CFG_ENV_SECT_SIZE 0x2000
#else
# define CFG_FLASH_BASE CFG_FLASH0_BASE
# define CFG_FLASH0_BASE CFG_CS1_BASE
# define CFG_FLASH1_BASE CFG_CS0_BASE
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000)
+# define CFG_ENV_SECT_SIZE 0x20000
#endif
/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
*/
#ifdef CFG_ATMEL_BOOT
-# define CONFIG_JFFS2_DEV "nor0"
+# define CONFIG_JFFS2_DEV "nor1"
# define CONFIG_JFFS2_PART_SIZE 0x01000000
-# define CONFIG_JFFS2_PART_OFFSET CFG_FLASH1_BASE
+# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH1_BASE + 0x500000)
#else
# define CONFIG_JFFS2_DEV "nor0"
# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
#ifdef CFG_ATMEL_BOOT
/* Atmel Flash */
-#define CFG_CS0_BASE 0
+#define CFG_CS0_BASE 0x04000000
#define CFG_CS0_MASK 0x00070001
#define CFG_CS0_CTRL 0x00001140
/* Intel Flash */
-#define CFG_CS1_BASE 0x04000000
+#define CFG_CS1_BASE 0x00000000
#define CFG_CS1_MASK 0x01FF0001
-#define CFG_CS1_CTRL 0x003F3D60
+#define CFG_CS1_CTRL 0x00000D60
#define CFG_ATMEL_BASE CFG_CS0_BASE
#else
/* Intel Flash */
-#define CFG_CS0_BASE 0
+#define CFG_CS0_BASE 0x00000000
#define CFG_CS0_MASK 0x01FF0001
-#define CFG_CS0_CTRL 0x003F3D60
+#define CFG_CS0_CTRL 0x00000D60
/* Atmel Flash */
#define CFG_CS1_BASE 0x04000000
#define CFG_CS1_MASK 0x00070001
#define CFG_CS3_MASK 0x00070001
#define CFG_CS3_CTRL 0x00000020
-#endif /* _JAMICA54455_H */
+#endif /* _M54455EVB_H */
/*
* Command line configuration.
*/
-#include <config_cmd_all.h>
-
-#undef CONFIG_CMD_BEDBUG
-#undef CONFIG_CMD_BMP
-#undef CONFIG_CMD_BSP
-#undef CONFIG_CMD_DATE
-#undef CONFIG_CMD_DISPLAY
-#undef CONFIG_CMD_DOC
-#undef CONFIG_CMD_DTT
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_ELF
-#undef CONFIG_CMD_EXT2
-#undef CONFIG_CMD_FAT
-#undef CONFIG_CMD_FDC
-#undef CONFIG_CMD_FDOS
-#undef CONFIG_CMD_HWFLOW
-#undef CONFIG_CMD_IDE
-#undef CONFIG_CMD_KGDB
-#undef CONFIG_CMD_MFSL
-#undef CONFIG_CMD_MMC
-#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_PCMCIA
-#undef CONFIG_CMD_REISER
-#undef CONFIG_CMD_SCSI
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_SNTP
-#undef CONFIG_CMD_UNIVERSE
-#undef CONFIG_CMD_USB
-#undef CONFIG_CMD_VFD
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+
#undef CONFIG_CMD_XIMG
#if CONFIG_ADSTYPE == CFG_8272ADS
/*
* Command line configuration.
*/
-#include <config_cmd_all.h>
-
-#undef CONFIG_CMD_BEDBUG
-#undef CONFIG_CMD_BMP
-#undef CONFIG_CMD_BSP
-#undef CONFIG_CMD_DATE
-#undef CONFIG_CMD_DHCP
-#undef CONFIG_CMD_DISPLAY
-#undef CONFIG_CMD_DOC
-#undef CONFIG_CMD_DTT
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_ELF
-#undef CONFIG_CMD_EXT2
-#undef CONFIG_CMD_FDC
-#undef CONFIG_CMD_FDOS
-#undef CONFIG_CMD_HWFLOW
-#undef CONFIG_CMD_IDE
-#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_KGDB
-#undef CONFIG_CMD_MFSL
-#undef CONFIG_CMD_MMC
-#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_PCMCIA
-#undef CONFIG_CMD_REISER
-#undef CONFIG_CMD_SCSI
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_SNTP
-#undef CONFIG_CMD_VFD
-#undef CONFIG_CMD_UNIVERSE
-#undef CONFIG_CMD_USB
-#undef CONFIG_CMD_XIMG
+#include <config_cmd_default.h>
+
+/* Commands we want, that are not part of default set */
+#define CONFIG_CMD_ASKENV /* ask for env variable */
+#define CONFIG_CMD_CACHE /* icache, dcache */
+#define CONFIG_CMD_DHCP /* DHCP Support */
+#define CONFIG_CMD_DIAG /* Diagnostics */
+#define CONFIG_CMD_IMMAP /* IMMR dump support */
+#define CONFIG_CMD_IRQ /* irqinfo */
+#define CONFIG_CMD_MII /* MII support */
+#define CONFIG_CMD_PCI /* pciinfo */
+#define CONFIG_CMD_PING /* ping support */
+#define CONFIG_CMD_PORTIO /* Port I/O */
+#define CONFIG_CMD_REGINFO /* Register dump */
+#define CONFIG_CMD_SAVES /* save S record dump */
+#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
+
+/* Commands from default set we don't need */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
/* Define a command string that is automatically executed when no character
* is read on the console interface withing "Boot Delay" after reset.
#define OF_SOC "soc8541@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600"
+#define OF_PCI "pci@e0008000"
/*
* I2C
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
+#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
/* define to use L1 as initial stack */
#define OF_SOC "soc8548@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600"
+#define OF_PCI "pci@e0008000"
/*
* I2C
#define OF_SOC "soc8555@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600"
+#define OF_PCI "pci@e0008000"
/*
* I2C
#define OF_SOC "soc8568@e0000000"
#define OF_QE "qe@e0080000"
#define OF_TBCLK (bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600"
+#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4500"
/*
* I2C
#define CFG_SRIO_MEM_BASE 0xc0000000
-#if defined(CONFIG_PCI)
-
-#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#ifdef CONFIG_QE
/*
* QE UEC ethernet configuration
#endif
#endif /* CONFIG_QE */
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
+#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
#define CFG_USB_EVENT_POLL 1
#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+#define CFG_OHCI_SWAP_REG_ACCESS 1
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_EXT2
+ #define CONFIG_CMD_USB
#endif
/*
* Command line configuration.
*/
-#include <config_cmd_all.h>
-
-#undef CONFIG_CMD_BSP
-#undef CONFIG_CMD_DATE
-#undef CONFIG_CMD_DISPLAY
-#undef CONFIG_CMD_DTT
-#undef CONFIG_CMD_EXT2
-#undef CONFIG_CMD_FDC
-#undef CONFIG_CMD_FDOS
-#undef CONFIG_CMD_HWFLOW
-#undef CONFIG_CMD_IDE
-#undef CONFIG_CMD_IRQ
-#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_MFSL
-#undef CONFIG_CMD_MMC
-#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_PCI
-#undef CONFIG_CMD_PCMCIA
-#undef CONFIG_CMD_REISER
-#undef CONFIG_CMD_SCSI
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_KGDB
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+
#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_SNTP
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_UNIVERSE
-#undef CONFIG_CMD_USB
-#undef CONFIG_CMD_VFD
#undef CONFIG_CMD_XIMG
-
/*
* Miscellaneous configurable options
*/
#endif
#ifdef CONFIG_PCI
-#define CONFIG_CMD_CMD_PCI
+#define CONFIG_CMD_PCI
#endif
#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
"protect on FC000000 +${filesize}\0"
#endif
-#ifndef CONFIG_CAM5200
+#if defined(CONFIG_TQM5200)
#define CUSTOM_ENV_SETTINGS \
+ "hostname=tqm5200\0" \
"bootfile=/tftpboot/tqm5200/uImage\0" \
- "bootfile_fdt=/tftpboot/tqm5200/uImage_fdt\0" \
"fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0"
-#else
+#elif defined(CONFIG_CAM5200)
#define CUSTOM_ENV_SETTINGS \
"bootfile=cam5200/uImage\0" \
"u-boot=cam5200/u-boot.bin\0" \
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=ttyS0\0" \
- "kernel_addr=200000\0" \
- "fdt_addr=400000\0" \
- "hostname=tqm5200\0" \
"netdev=eth0\0" \
+ "console=ttyPSC0\0" \
+ "fdt_addr=FC0A0000\0" \
+ "kernel_addr=FC0C0000\0" \
+ "ramdisk_addr=FC300000\0" \
+ "kernel_addr_r=400000\0" \
+ "fdt_addr_r=600000\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
":${hostname}:${netdev}:off panic=1\0" \
"addcons=setenv bootargs ${bootargs} " \
"console=${console},${baudrate}\0" \
- "flash_self=run ramargs addip addcons;" \
+ "flash_self_old=sete console ttyS0; run ramargs addip addcons;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip addcons;" \
+ "flash_self=run ramargs addip addcons;" \
+ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
+ "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \
"bootm ${kernel_addr}\0" \
- "net_nfs=tftp ${kernel_addr} ${bootfile};" \
- "run nfsargs addip addcons;bootm\0" \
- "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt};" \
- "tftp ${fdt_addr} ${fdt_file};setenv console ttyPSC0;" \
- "run nfsargs addip addcons;" \
+ "flash_nfs=run nfsargs addip addcons;" \
"bootm ${kernel_addr} - ${fdt_addr}\0" \
+ "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
+ "sete console ttyS0; run nfsargs addip addcons;bootm\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "tftp ${fdt_addr_r} ${fdt_file}; " \
+ "run nfsargs addip addcons; " \
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
CUSTOM_ENV_SETTINGS \
"load=tftp 200000 ${u-boot}\0" \
ENV_UPDT \
# endif /* CFG_LOWBOOT */
# else /* !CONFIG_TQM5200_B */
# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
- "1408k(kernel)," \
+ "128k(dtb)," \
+ "2304k(kernel)," \
"2m(initrd)," \
"4m(small-fs)," \
"8m(misc)," \
- "16m(big-fs)"
+ "15m(big-fs)"
# endif /* CONFIG_TQM5200_B */
#elif defined (CONFIG_CAM5200)
# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
# if defined (CONFIG_TQM5200_REV100)
# error TQM5200 REV100 not supported on STK52XX REV200 or above
# else/* TQM5200 REV200 and above */
-# define CFG_GPS_PORT_CONFIG 0x91500004
+# define CFG_GPS_PORT_CONFIG 0x91500404
# endif
# endif
#elif defined (CONFIG_FO300)
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM860M/uImage\0" \
- "fdt_addr=40080000\0" \
- "kernel_addr=400A0000\0" \
+ "fdt_addr=400C0000\0" \
+ "kernel_addr=40100000\0" \
"ramdisk_addr=40280000\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=protect off 40000000 +${filesize};" \
+ "erase 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "protect on 40000000 +${filesize}\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CFG_FLASH_BASE 0x40000000
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
/*
* For booting Linux, the board info and command line data
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM866M/uImage\0" \
- "fdt_addr=40080000\0" \
- "kernel_addr=400A0000\0" \
+ "fdt_addr=400C0000\0" \
+ "kernel_addr=40100000\0" \
"ramdisk_addr=40280000\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=protect off 40000000 +${filesize};" \
+ "erase 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "protect on 40000000 +${filesize}\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CFG_FLASH_BASE 0x40000000
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
/*
* For booting Linux, the board info and command line data
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
/*
- * Memory Periodic Timer Prescaler
- * Periodic timer for refresh, start with refresh rate for 40 MHz clock
- * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
+ * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
+ *
+ * CPUclock(MHz) * 31.2
+ * CFG_MAMR_PTA = ----------------------------------- with DFBRG = 0
+ * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
+ *
+ * CPU clock = 15 MHz: CFG_MAMR_PTA = 29 -> 4 * 7.73 us
+ * CPU clock = 50 MHz: CFG_MAMR_PTA = 97 -> 4 * 7.76 us
+ * CPU clock = 66 MHz: CFG_MAMR_PTA = 128 -> 4 * 7.75 us
+ * CPU clock = 133 MHz: CFG_MAMR_PTA = 255 -> 4 * 7.67 us
+ *
+ * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
+ * be met also in the default configuration, i.e. if environment variable
+ * 'cpuclk' is not set.
*/
-#define CFG_MAMR_PTA 39
+#define CFG_MAMR_PTA 97
/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
- * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
+ * Memory Periodic Timer Prescaler Register (MPTPR) values.
*/
-#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
+/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
+#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16
+/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
+#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8
/*
* MAMR settings for SDRAM
#endif
/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
+#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
+
+/*
* Ethernet configuration
*/
#define CONFIG_MPC512x_FEC 1
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_EEPROM
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#define CFG_HZ 1000
/*
- * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL
- * frequency and the peripherals to run at 1/4 the PLL frequency.
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
+ * PLL frequency.
+ * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
*/
#define CONFIG_PLL 1
#define CFG_POWER_MANAGER 1
#define CFG_PLL0_DIV 1
#define CFG_PLL0_MUL 7
#define CFG_PLL0_SUPPRESS_CYCLES 16
+/*
+ * Set the CPU running at:
+ * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
+ */
#define CFG_CLKDIV_CPU 0
+/*
+ * Set the HSB running at:
+ * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
+ */
#define CFG_CLKDIV_HSB 1
+/*
+ * Set the PBA running at:
+ * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
+ */
#define CFG_CLKDIV_PBA 2
+/*
+ * Set the PBB running at:
+ * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
+ */
#define CFG_CLKDIV_PBB 1
/*
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS \
- "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2 fbmem=600k"
+ "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1"
#define CONFIG_BOOTCOMMAND \
"fsload; bootm $(fileaddr)"
* Only interrupt autoboot if <space> is pressed. Otherwise, garbage
* data on the serial line may interrupt the boot sequence.
*/
-#define CONFIG_BOOTDELAY 2
+#define CONFIG_BOOTDELAY 1
#define CONFIG_AUTOBOOT 1
#define CONFIG_AUTOBOOT_KEYED 1
#define CONFIG_AUTOBOOT_PROMPT \
#define CONFIG_AUTOBOOT_STOP_STR " "
/*
- * These are "locally administered ethernet addresses" generated by
- * ./tools/gen_eth_addr
- *
- * After booting the board for the first time, new addresses should be
- * generated and assigned to the environment variables "ethaddr" and
- * "eth1addr".
+ * After booting the board for the first time, new ethernet addresses
+ * should be generated and assigned to the environment variables
+ * "ethaddr" and "eth1addr". This is normally done during production.
*/
-#define CONFIG_ETHADDR "6a:87:71:14:cd:cb"
-#define CONFIG_ETH1ADDR "ca:f8:15:e6:3e:e6"
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
#define CONFIG_NET_MULTI 1
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP 1
-#define CFG_MEMTEST_START \
- ({ gd->bd->bi_dram[0].start; })
-#define CFG_MEMTEST_END \
- ({ \
- gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \
- })
+#define CFG_MEMTEST_START CFG_SDRAM_BASE
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000)
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
#endif /* __CONFIG_H */
#define CONFIG_USB_STORAGE 1
#define CONFIG_DOS_PARTITION 1
+#include <asm/arch/pxa-regs.h> /* for OHCI_REGS_BASE */
+
#undef CFG_USB_OHCI_BOARD_INIT
#define CFG_USB_OHCI_CPU_INIT 1
#define CFG_USB_OHCI_REGS_BASE OHCI_REGS_BASE
/*
* Command line configuration.
*/
-#include <config_cmd_all.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
-#undef CONFIG_CMD_BMP
-#undef CONFIG_CMD_BSP
#undef CONFIG_CMD_DCR
-#undef CONFIG_CMD_DHCP
-#undef CONFIG_CMD_DISPLAY
-#undef CONFIG_CMD_DOC
-#undef CONFIG_CMD_DTT
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_EXT2
-#undef CONFIG_CMD_FDC
-#undef CONFIG_CMD_FDOS
-#undef CONFIG_CMD_HWFLOW
-#undef CONFIG_CMD_IDE
-#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_KGDB
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_MFSL
-#undef CONFIG_CMD_MMC
-#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_PCI
-#undef CONFIG_CMD_PCMCIA
-#undef CONFIG_CMD_REISER
-#undef CONFIG_CMD_SCSI
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_UNIVERSE
-#undef CONFIG_CMD_USB
-#undef CONFIG_CMD_VFD
#undef CONFIG_CMD_XIMG
-
/* Where do the internal registers live? */
#define CFG_IMMR 0xF0000000
#define CFG_DEFAULT_IMMR 0x00010000
/*
* Command line configuration.
*/
-#include <config_cmd_all.h>
-
-#undef CONFIG_CMD_BEDBUG
-#undef CONFIG_CMD_BMP
-#undef CONFIG_CMD_DISPLAY
-#undef CONFIG_CMD_DOC
-#undef CONFIG_CMD_EXT2
-#undef CONFIG_CMD_FDC
-#undef CONFIG_CMD_FDOS
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_KGDB
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_HWFLOW
-#undef CONFIG_CMD_IDE
-#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_MFSL
-#undef CONFIG_CMD_MMC
-#undef CONFIG_CMD_PCMCIA
-#undef CONFIG_CMD_PCI
-#undef CONFIG_CMD_USB
-#undef CONFIG_CMD_REISER
-#undef CONFIG_CMD_SCSI
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_UNIVERSE
-#undef CONFIG_CMD_VFD
#undef CONFIG_CMD_XIMG
-
#ifdef DEBUG
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#endif
#define CONFIG_MMC 1
#define BOARD_LATE_INIT 1
+#define CONFIG_DOS_PARTITION
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
+ "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
+ "flash_nfs=run nfsargs addip addtty addmisc;" \
"bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
+ "flash_self=run ramargs addip addtty addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
+ "net_nfs=tftp 200000 ${bootfile};" \
+ "run nfsargs addip addtty addmisc;bootm\0" \
"rootpath=/opt/eldk/ppc_4xxFP\0" \
"bootfile=/tftpboot/lwmon5/uImage\0" \
"kernel_addr=FC000000\0" \
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
+#if 0
+/*
+ * ToDo: Watchdog is not test fully, so exclude it for now
+ */
#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
+#endif
/*
* For booting Linux, the board info and command line data
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO58 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
/*
- * (C) Copyright 2007 Czech Technical University.
+ * (C) Copyright 2007 Michal Simek
*
- * Michal SIMEK <monstr@seznam.cz>
+ * Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
#define CONFIG_ML401 1 /* ML401 Board */
/* uart */
+#define CONFIG_XILINX_UARTLITE
#define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR
#define CONFIG_BAUDRATE XILINX_UART_BAUDRATE
#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
#define FREQUENCE XILINX_CLOCK_FREQ
#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
+#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
/* FSL */
#define CFG_FSL_2
* 0x11FB_F000 CFG_MONITOR_BASE
* MONITOR_CODE 256kB Env
* 0x13FF_F000 CFG_GBL_DATA_OFFSET
- * GLOBAL_DATA 4kB bd, gd
+ * GLOBAL_DATA 4kB bd, gd
* 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
*/
/* global pointer */
#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
/* start of global data */
-#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
+#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
/* monitor code */
#define SIZE 0x40000
#define CFG_FLASH_PROTECTION /* hardware flash protection */
#endif /* !FLASH */
+/* system ace */
+#ifdef XILINX_SYSACE_BASEADDR
+ #define CONFIG_SYSTEMACE
+ /* #define DEBUG_SYSTEMACE */
+ #define SYSTEMACE_CONFIG_FPGA
+ #define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
+ #define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
+ #define CONFIG_DOS_PARTITION
+#endif
+
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_AUTOSCRIPT
-#define CONFIG_CMD_BDI
#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_IMI
#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
#define CONFIG_CMD_MFSL
-#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
-#define CONFIG_CMD_RUN
+
+#if defined(CONFIG_SYSTEMACE)
+ #define CONFIG_CMD_EXT2
+ #define CONFIG_CMD_FAT
+#endif
#if defined(FLASH)
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVES
#endif
+#else
+ #undef CONFIG_CMD_FLASH
#endif
#if defined(CONFIG_CMD_JFFS2)
#define CONFIG_BOOTDELAY 30
#define CONFIG_BOOTARGS "root=romfs"
#define CONFIG_HOSTNAME "ml401"
-#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
+#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
#define CONFIG_IPADDR 192.168.0.3
-#define CONFIG_SERVERIP 192.168.0.5
-#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.5
+#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
/* architecture dependent code */
#define CFG_USR_EXCEP /* user exception */
#define CFG_HZ 1000
-/* system ace */
-#define CONFIG_SYSTEMACE
-/* #define DEBUG_SYSTEMACE */
-#define SYSTEMACE_CONFIG_FPGA
-#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
-#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo"
#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\
/*
- * Clock configuration: SYS_XTALIN = 25MHz
+ * Clock configuration: SYS_XTALIN = 33MHz
*/
-#define CFG_MPC5XXX_CLKIN 25000000
+#define CFG_MPC5XXX_CLKIN 33000000
/*
#endif
#define CFG_MONITOR_LEN (256 << 10) /* 256 kB for Monitor */
-#define CFG_MALLOC_LEN (128 << 10) /* 128 kB for malloc() */
+#define CFG_MALLOC_LEN (1024 << 10) /* 1 MiB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */
/* Boot Chipselect */
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG 0x03035D00
+#define CFG_BOOTCS_CFG 0x00045D00
/* Flash memory addressing */
#define CFG_CS0_START CFG_FLASH_BASE
/*
* SDRAM configuration
*/
-/* 2 x MT48LC16M16A2BG-75 IT:D, CASL 2, 32 bit data bus */
-#define SDRAM_CONFIG1 0x52222600
-#define SDRAM_CONFIG2 0x88b70000
-#define SDRAM_CONTROL 0x50570000
-#define SDRAM_MODE 0x008d0000
+/* 2 x MT48LC16M16A2BG-75 IT:D, CASL 3, 32 bit data bus */
+#define SDRAM_CONFIG1 0x62322900
+#define SDRAM_CONFIG2 0x88c70000
+#define SDRAM_CONTROL 0x504f0000
+#define SDRAM_MODE 0x00cd0000
/*
#define CFG_FLASH_SIZE 0x01000000
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
-#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
+#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
#define CONFIG_FLASH_16BIT /* Flash is 16-bit */
/*
#define MTDIDS_DEFAULT "nor0=motionpro-0"
#define MTDPARTS_DEFAULT "mtdparts=motionpro-0:" \
"13m(fs),2m(kernel),256k(uboot)," \
- "64k(env),64k(redund_env),64k(dtb)," \
- "-(user_data)"
+ "128k(env),128k(redund_env)," \
+ "128k(dtb),-(user_data)"
/*
* IDE/ATA configuration
/* This has to be a multiple of the Flash sector size */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_ENV_SIZE 0x1000
-#define CFG_ENV_SECT_SIZE 0x10000
+#define CFG_ENV_SECT_SIZE 0x20000
/* Configuration of redundant environment */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
-#define CFG_MEMTEST_END 0x03f00000 /* 1 ... 64 MiB in DRAM */
+#define CFG_MEMTEST_END 0x03e00000 /* 1 ... 62 MiB in DRAM */
+#define CFG_ALT_MEMTEST
#define CFG_LOAD_ADDR 0x200000 /* default kernel load addr */
#include <asm/arch/pxa-regs.h>
/*
- * If we are developing, we might want to start armboot from ram
+ * If we are developing, we might want to start U-Boot from RAM
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */
+#undef CONFIG_SKIP_RELOCATE_UBOOT /* define for developing */
/*
* define the following to enable debug blinks. A debug blink function
#endif
#define CONFIG_MMC 1
+#define CONFIG_DOS_PARTITION 1
#define BOARD_LATE_INIT 1
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMD_FAT
#define CONFIG_CMD_DHCP
-
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTCOMMAND "bootm 40000"
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
#define CFG_FLASH_CFI_DRIVER 1
#define CFG_MONITOR_BASE 0
-#define CFG_MONITOR_LEN 0x40000
+#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
/* Addr of Environment Sector */
#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
-#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE 0x40000
+#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE (PHYS_FLASH_SECT_SIZE / 16)
#endif /* __CONFIG_H */
/* enable I2C */
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x30
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#define CFG_EBC_PB2AP 0x24814580
#define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x38000)
+#define CFG_BCSR5_PCI66EN 0x80
+
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
+/*
+ * I2C
+ */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
-#if 0
-#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */
-#else
-/* I did the 'if 0' so we could keep the syntax above if ever needed. */
#undef CFG_I2C_NOPROBES
-#endif
#define CFG_I2C_OFFSET 0x3000
+/* I2C RTC */
+#define CONFIG_RTC_DS1337 /* This is really a DS1339 RTC */
+#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+
/* I2C EEPROM. AT24C32, we keep our environment in here.
*/
#define CFG_I2C_EEPROM_ADDR 0x51 /* 1010001x */
*/
#include <config_cmd_default.h>
-#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - (1024 * 1024))
+#define CONFIG_XILINX_UARTLITE
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 115200 }
#define MICROBLAZE_SYSREG_BASE_ADDR 0xFFFFA000
#define MICROBLAZE_SYSREG_RECONFIGURE (1 << 0)
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_MEMORY
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_MISC
#define CFG_UART1_BASE (0xFFFF2000)
#define CONFIG_SERIAL_BASE CFG_UART1_BASE
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define XILINX_CLOCK_FREQ 50000000
+#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
+
#endif /* __CONFIG_H */
/* 8Mbit SRAM @0x80100000 */
#define CFG_CS1_START CFG_SRAM_BASE
-#define CFG_CS1_SIZE 0x00100000
+#define CFG_CS1_SIZE 0x00200000
#define CFG_CS1_CFG 0x21D00
/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
#define CONFIG_XSENGINE 1
#define CONFIG_MMC 1
+#define CONFIG_DOS_PARTITION 1
#define BOARD_POST_INIT 1
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
/*
- * (C) Copyright 2007 Czech Technical University.
+ * (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
#define CONFIG_XUPV2P 1
/* uart */
+#define CONFIG_XILINX_UARTLITE
#define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR
#define CONFIG_BAUDRATE XILINX_UART_BAUDRATE
#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
* U-BOOT auto-relocate to TEXT_BASE. After RESET command Microblaze
* jump to CFG_RESET_ADDRESS where is the original U-BOOT code.
*/
-#define CFG_RESET_ADDRESS 0x36000000
+/* #define CFG_RESET_ADDRESS 0x36000000 */
/* gpio */
+#ifdef XILINX_GPIO_BASEADDR
#define CFG_GPIO_0 1
#define CFG_GPIO_0_ADDR XILINX_GPIO_BASEADDR
+#endif
/* interrupt controller */
#define CFG_INTC_0 1
#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
#define FREQUENCE XILINX_CLOCK_FREQ
#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
+#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
/*
* memory layout - Example
#define CFG_ENV_SIZE 0x1000
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+
#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_MISC
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PING
+#ifdef XILINX_SYSACE_BASEADDR
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#endif
/* Miscellaneous configurable options */
#define CFG_PROMPT "U-Boot-mONStR> "
#define CONFIG_BOOTDELAY 30
#define CONFIG_BOOTARGS "root=romfs"
-#define CONFIG_HOSTNAME "ml401"
+#define CONFIG_HOSTNAME "xupv2p"
#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
#define CONFIG_IPADDR 192.168.0.3
#define CONFIG_SERVERIP 192.168.0.5
"echo"
/* system ace */
+#ifdef XILINX_SYSACE_BASEADDR
#define CONFIG_SYSTEMACE
/* #define DEBUG_SYSTEMACE */
#define SYSTEMACE_CONFIG_FPGA
#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
#define CONFIG_DOS_PARTITION
+#endif
#endif /* __CONFIG_H */
#define CFG_EBC_PB2AP 0x04814500
#define CFG_EBC_PB2CR (CFG_CPLD | 0x18000)
+#define CFG_BCSR5_PCI66EN 0x80
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Atmel Nordic AB <www.atmel.com>
- * Ulf Samuelsson <ulf@atmel.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __LED_H
-#define __LED_H
-
-#ifndef __ASSEMBLY__
-extern void LED_init (void);
-extern void red_LED_on(void);
-extern void red_LED_off(void);
-extern void green_LED_on(void);
-extern void green_LED_off(void);
-extern void yellow_LED_on(void);
-extern void yellow_LED_off(void);
-#else
- .extern LED_init
- .extern red_LED_on
- .extern red_LED_off
- .extern yellow_LED_on
- .extern yellow_LED_off
- .extern green_LED_on
- .extern green_LED_off
-#endif
-#endif
--- /dev/null
+/*
+ * linux/include/linux/mtd/bbm.h
+ *
+ * NAND family Bad Block Management (BBM) header file
+ * - Bad Block Table (BBT) implementation
+ *
+ * Copyright (c) 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Copyright (c) 2000-2005
+ * Thomas Gleixner <tglx@linuxtronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_MTD_BBM_H
+#define __LINUX_MTD_BBM_H
+
+/* The maximum number of NAND chips in an array */
+#ifndef NAND_MAX_CHIPS
+#define NAND_MAX_CHIPS 8
+#endif
+
+/**
+ * struct nand_bbt_descr - bad block table descriptor
+ * @param options options for this descriptor
+ * @param pages the page(s) where we find the bbt, used with
+ * option BBT_ABSPAGE when bbt is searched,
+ * then we store the found bbts pages here.
+ * Its an array and supports up to 8 chips now
+ * @param offs offset of the pattern in the oob area of the page
+ * @param veroffs offset of the bbt version counter in the oob are of the page
+ * @param version version read from the bbt page during scan
+ * @param len length of the pattern, if 0 no pattern check is performed
+ * @param maxblocks maximum number of blocks to search for a bbt. This number of
+ * blocks is reserved at the end of the device
+ * where the tables are written.
+ * @param reserved_block_code if non-0, this pattern denotes a reserved
+ * (rather than bad) block in the stored bbt
+ * @param pattern pattern to identify bad block table or factory marked
+ * good / bad blocks, can be NULL, if len = 0
+ *
+ * Descriptor for the bad block table marker and the descriptor for the
+ * pattern which identifies good and bad blocks. The assumption is made
+ * that the pattern and the version count are always located in the oob area
+ * of the first block.
+ */
+struct nand_bbt_descr {
+ int options;
+ int pages[NAND_MAX_CHIPS];
+ int offs;
+ int veroffs;
+ uint8_t version[NAND_MAX_CHIPS];
+ int len;
+ int maxblocks;
+ int reserved_block_code;
+ uint8_t *pattern;
+};
+
+/* Options for the bad block table descriptors */
+
+/* The number of bits used per block in the bbt on the device */
+#define NAND_BBT_NRBITS_MSK 0x0000000F
+#define NAND_BBT_1BIT 0x00000001
+#define NAND_BBT_2BIT 0x00000002
+#define NAND_BBT_4BIT 0x00000004
+#define NAND_BBT_8BIT 0x00000008
+/* The bad block table is in the last good block of the device */
+#define NAND_BBT_LASTBLOCK 0x00000010
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_ABSPAGE 0x00000020
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_SEARCH 0x00000040
+/* bbt is stored per chip on multichip devices */
+#define NAND_BBT_PERCHIP 0x00000080
+/* bbt has a version counter at offset veroffs */
+#define NAND_BBT_VERSION 0x00000100
+/* Create a bbt if none axists */
+#define NAND_BBT_CREATE 0x00000200
+/* Search good / bad pattern through all pages of a block */
+#define NAND_BBT_SCANALLPAGES 0x00000400
+/* Scan block empty during good / bad block scan */
+#define NAND_BBT_SCANEMPTY 0x00000800
+/* Write bbt if neccecary */
+#define NAND_BBT_WRITE 0x00001000
+/* Read and write back block contents when writing bbt */
+#define NAND_BBT_SAVECONTENT 0x00002000
+/* Search good / bad pattern on the first and the second page */
+#define NAND_BBT_SCAN2NDPAGE 0x00004000
+
+/* The maximum number of blocks to scan for a bbt */
+#define NAND_BBT_SCAN_MAXBLOCKS 4
+
+/*
+ * Constants for oob configuration
+ */
+#define ONENAND_BADBLOCK_POS 0
+
+/**
+ * struct bbt_info - [GENERIC] Bad Block Table data structure
+ * @param bbt_erase_shift [INTERN] number of address bits in a bbt entry
+ * @param badblockpos [INTERN] position of the bad block marker in the oob area
+ * @param bbt [INTERN] bad block table pointer
+ * @param badblock_pattern [REPLACEABLE] bad block scan pattern used for initial bad block scan
+ * @param priv [OPTIONAL] pointer to private bbm date
+ */
+struct bbm_info {
+ int bbt_erase_shift;
+ int badblockpos;
+ int options;
+
+ uint8_t *bbt;
+
+ int (*isbad_bbt) (struct mtd_info * mtd, loff_t ofs, int allowbbt);
+
+ /* TODO Add more NAND specific fileds */
+ struct nand_bbt_descr *badblock_pattern;
+
+ void *priv;
+};
+
+/* OneNAND BBT interface */
+extern int onenand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
+extern int onenand_default_bbt (struct mtd_info *mtd);
+
+#endif /* __LINUX_MTD_BBM_H */
--- /dev/null
+/*
+ * linux/include/linux/mtd/onenand.h
+ *
+ * Copyright (C) 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_MTD_ONENAND_H
+#define __LINUX_MTD_ONENAND_H
+
+#include <linux/mtd/onenand_regs.h>
+
+/* Note: The header order is impoertant */
+#include <onenand_uboot.h>
+
+#include <linux/mtd/bbm.h>
+
+#define MAX_BUFFERRAM 2
+#define MAX_ONENAND_PAGESIZE (2048 + 64)
+
+/* Scan and identify a OneNAND device */
+extern int onenand_scan (struct mtd_info *mtd, int max_chips);
+/* Free resources held by the OneNAND device */
+extern void onenand_release (struct mtd_info *mtd);
+
+/**
+ * onenand_state_t - chip states
+ * Enumeration for OneNAND flash chip state
+ */
+typedef enum {
+ FL_READY,
+ FL_READING,
+ FL_WRITING,
+ FL_ERASING,
+ FL_SYNCING,
+ FL_UNLOCKING,
+ FL_LOCKING,
+} onenand_state_t;
+
+/**
+ * struct onenand_bufferram - OneNAND BufferRAM Data
+ * @param block block address in BufferRAM
+ * @param page page address in BufferRAM
+ * @param valid valid flag
+ */
+struct onenand_bufferram {
+ int block;
+ int page;
+ int valid;
+};
+
+/**
+ * struct onenand_chip - OneNAND Private Flash Chip Data
+ * @param base [BOARDSPECIFIC] address to access OneNAND
+ * @param chipsize [INTERN] the size of one chip for multichip arrays
+ * @param device_id [INTERN] device ID
+ * @param verstion_id [INTERN] version ID
+ * @param options [BOARDSPECIFIC] various chip options. They can partly be set to inform onenand_scan about
+ * @param erase_shift [INTERN] number of address bits in a block
+ * @param page_shift [INTERN] number of address bits in a page
+ * @param ppb_shift [INTERN] number of address bits in a pages per block
+ * @param page_mask [INTERN] a page per block mask
+ * @param bufferam_index [INTERN] BufferRAM index
+ * @param bufferam [INTERN] BufferRAM info
+ * @param readw [REPLACEABLE] hardware specific function for read short
+ * @param writew [REPLACEABLE] hardware specific function for write short
+ * @param command [REPLACEABLE] hardware specific function for writing commands to the chip
+ * @param wait [REPLACEABLE] hardware specific function for wait on ready
+ * @param read_bufferram [REPLACEABLE] hardware specific function for BufferRAM Area
+ * @param write_bufferram [REPLACEABLE] hardware specific function for BufferRAM Area
+ * @param chip_lock [INTERN] spinlock used to protect access to this structure and the chip
+ * @param wq [INTERN] wait queue to sleep on if a OneNAND operation is in progress
+ * @param state [INTERN] the current state of the OneNAND device
+ * @param autooob [REPLACEABLE] the default (auto)placement scheme
+ * @param priv [OPTIONAL] pointer to private chip date
+ */
+struct onenand_chip {
+ void __iomem *base;
+ unsigned int chipsize;
+ unsigned int device_id;
+ unsigned int options;
+
+ unsigned int erase_shift;
+ unsigned int page_shift;
+ unsigned int ppb_shift; /* Pages per block shift */
+ unsigned int page_mask;
+
+ unsigned int bufferram_index;
+ struct onenand_bufferram bufferram[MAX_BUFFERRAM];
+
+ int (*command) (struct mtd_info * mtd, int cmd, loff_t address,
+ size_t len);
+ int (*wait) (struct mtd_info * mtd, int state);
+ int (*read_bufferram) (struct mtd_info * mtd, int area,
+ unsigned char *buffer, int offset, size_t count);
+ int (*write_bufferram) (struct mtd_info * mtd, int area,
+ const unsigned char *buffer, int offset,
+ size_t count);
+ unsigned short (*read_word) (void __iomem * addr);
+ void (*write_word) (unsigned short value, void __iomem * addr);
+ void (*mmcontrol) (struct mtd_info * mtd, int sync_read);
+
+ spinlock_t chip_lock;
+ wait_queue_head_t wq;
+ onenand_state_t state;
+
+ struct nand_oobinfo *autooob;
+
+ void *bbm;
+
+ void *priv;
+};
+
+#define ONENAND_CURRENT_BUFFERRAM(this) (this->bufferram_index)
+#define ONENAND_NEXT_BUFFERRAM(this) (this->bufferram_index ^ 1)
+#define ONENAND_SET_NEXT_BUFFERRAM(this) (this->bufferram_index ^= 1)
+
+/*
+ * Options bits
+ */
+#define ONENAND_CONT_LOCK (0x0001)
+
+/*
+ * OneNAND Flash Manufacturer ID Codes
+ */
+#define ONENAND_MFR_SAMSUNG 0xec
+#define ONENAND_MFR_UNKNOWN 0x00
+
+/**
+ * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
+ * @param name: Manufacturer name
+ * @param id: manufacturer ID code of device.
+*/
+struct onenand_manufacturers {
+ int id;
+ char *name;
+};
+
+#endif /* __LINUX_MTD_ONENAND_H */
--- /dev/null
+/*
+ * linux/include/linux/mtd/onenand_regs.h
+ *
+ * OneNAND Register header file
+ *
+ * Copyright (C) 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ONENAND_REG_H
+#define __ONENAND_REG_H
+
+/* Memory Address Map Translation (Word order) */
+#define ONENAND_MEMORY_MAP(x) ((x) << 1)
+
+/*
+ * External BufferRAM area
+ */
+#define ONENAND_BOOTRAM ONENAND_MEMORY_MAP(0x0000)
+#define ONENAND_DATARAM ONENAND_MEMORY_MAP(0x0200)
+#define ONENAND_SPARERAM ONENAND_MEMORY_MAP(0x8010)
+
+/*
+ * OneNAND Registers
+ */
+#define ONENAND_REG_MANUFACTURER_ID ONENAND_MEMORY_MAP(0xF000)
+#define ONENAND_REG_DEVICE_ID ONENAND_MEMORY_MAP(0xF001)
+#define ONENAND_REG_VERSION_ID ONENAND_MEMORY_MAP(0xF002)
+#define ONENAND_REG_DATA_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF003)
+#define ONENAND_REG_BOOT_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF004)
+#define ONENAND_REG_NUM_BUFFERS ONENAND_MEMORY_MAP(0xF005)
+#define ONENAND_REG_TECHNOLOGY ONENAND_MEMORY_MAP(0xF006)
+
+#define ONENAND_REG_START_ADDRESS1 ONENAND_MEMORY_MAP(0xF100)
+#define ONENAND_REG_START_ADDRESS2 ONENAND_MEMORY_MAP(0xF101)
+#define ONENAND_REG_START_ADDRESS3 ONENAND_MEMORY_MAP(0xF102)
+#define ONENAND_REG_START_ADDRESS4 ONENAND_MEMORY_MAP(0xF103)
+#define ONENAND_REG_START_ADDRESS5 ONENAND_MEMORY_MAP(0xF104)
+#define ONENAND_REG_START_ADDRESS6 ONENAND_MEMORY_MAP(0xF105)
+#define ONENAND_REG_START_ADDRESS7 ONENAND_MEMORY_MAP(0xF106)
+#define ONENAND_REG_START_ADDRESS8 ONENAND_MEMORY_MAP(0xF107)
+
+#define ONENAND_REG_START_BUFFER ONENAND_MEMORY_MAP(0xF200)
+#define ONENAND_REG_COMMAND ONENAND_MEMORY_MAP(0xF220)
+#define ONENAND_REG_SYS_CFG1 ONENAND_MEMORY_MAP(0xF221)
+#define ONENAND_REG_SYS_CFG2 ONENAND_MEMORY_MAP(0xF222)
+#define ONENAND_REG_CTRL_STATUS ONENAND_MEMORY_MAP(0xF240)
+#define ONENAND_REG_INTERRUPT ONENAND_MEMORY_MAP(0xF241)
+#define ONENAND_REG_START_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24C)
+#define ONENAND_REG_END_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24D)
+#define ONENAND_REG_WP_STATUS ONENAND_MEMORY_MAP(0xF24E)
+
+#define ONENAND_REG_ECC_STATUS ONENAND_MEMORY_MAP(0xFF00)
+#define ONENAND_REG_ECC_M0 ONENAND_MEMORY_MAP(0xFF01)
+#define ONENAND_REG_ECC_S0 ONENAND_MEMORY_MAP(0xFF02)
+#define ONENAND_REG_ECC_M1 ONENAND_MEMORY_MAP(0xFF03)
+#define ONENAND_REG_ECC_S1 ONENAND_MEMORY_MAP(0xFF04)
+#define ONENAND_REG_ECC_M2 ONENAND_MEMORY_MAP(0xFF05)
+#define ONENAND_REG_ECC_S2 ONENAND_MEMORY_MAP(0xFF06)
+#define ONENAND_REG_ECC_M3 ONENAND_MEMORY_MAP(0xFF07)
+#define ONENAND_REG_ECC_S3 ONENAND_MEMORY_MAP(0xFF08)
+
+/*
+ * Device ID Register F001h (R)
+ */
+#define ONENAND_DEVICE_DENSITY_SHIFT (4)
+#define ONENAND_DEVICE_IS_DDP (1 << 3)
+#define ONENAND_DEVICE_IS_DEMUX (1 << 2)
+#define ONENAND_DEVICE_VCC_MASK (0x3)
+
+#define ONENAND_DEVICE_DENSITY_512Mb (0x002)
+
+/*
+ * Version ID Register F002h (R)
+ */
+#define ONENAND_VERSION_PROCESS_SHIFT (8)
+
+/*
+ * Start Address 1 F100h (R/W)
+ */
+#define ONENAND_DDP_SHIFT (15)
+
+/*
+ * Start Address 8 F107h (R/W)
+ */
+#define ONENAND_FPA_MASK (0x3f)
+#define ONENAND_FPA_SHIFT (2)
+#define ONENAND_FSA_MASK (0x03)
+
+/*
+ * Start Buffer Register F200h (R/W)
+ */
+#define ONENAND_BSA_MASK (0x03)
+#define ONENAND_BSA_SHIFT (8)
+#define ONENAND_BSA_BOOTRAM (0 << 2)
+#define ONENAND_BSA_DATARAM0 (2 << 2)
+#define ONENAND_BSA_DATARAM1 (3 << 2)
+#define ONENAND_BSC_MASK (0x03)
+
+/*
+ * Command Register F220h (R/W)
+ */
+#define ONENAND_CMD_READ (0x00)
+#define ONENAND_CMD_READOOB (0x13)
+#define ONENAND_CMD_PROG (0x80)
+#define ONENAND_CMD_PROGOOB (0x1A)
+#define ONENAND_CMD_UNLOCK (0x23)
+#define ONENAND_CMD_LOCK (0x2A)
+#define ONENAND_CMD_LOCK_TIGHT (0x2C)
+#define ONENAND_CMD_ERASE (0x94)
+#define ONENAND_CMD_RESET (0xF0)
+#define ONENAND_CMD_READID (0x90)
+
+/* NOTE: Those are not *REAL* commands */
+#define ONENAND_CMD_BUFFERRAM (0x1978)
+
+/*
+ * System Configuration 1 Register F221h (R, R/W)
+ */
+#define ONENAND_SYS_CFG1_SYNC_READ (1 << 15)
+#define ONENAND_SYS_CFG1_BRL_7 (7 << 12)
+#define ONENAND_SYS_CFG1_BRL_6 (6 << 12)
+#define ONENAND_SYS_CFG1_BRL_5 (5 << 12)
+#define ONENAND_SYS_CFG1_BRL_4 (4 << 12)
+#define ONENAND_SYS_CFG1_BRL_3 (3 << 12)
+#define ONENAND_SYS_CFG1_BRL_10 (2 << 12)
+#define ONENAND_SYS_CFG1_BRL_9 (1 << 12)
+#define ONENAND_SYS_CFG1_BRL_8 (0 << 12)
+#define ONENAND_SYS_CFG1_BRL_SHIFT (12)
+#define ONENAND_SYS_CFG1_BL_32 (4 << 9)
+#define ONENAND_SYS_CFG1_BL_16 (3 << 9)
+#define ONENAND_SYS_CFG1_BL_8 (2 << 9)
+#define ONENAND_SYS_CFG1_BL_4 (1 << 9)
+#define ONENAND_SYS_CFG1_BL_CONT (0 << 9)
+#define ONENAND_SYS_CFG1_BL_SHIFT (9)
+#define ONENAND_SYS_CFG1_NO_ECC (1 << 8)
+#define ONENAND_SYS_CFG1_RDY (1 << 7)
+#define ONENAND_SYS_CFG1_INT (1 << 6)
+#define ONENAND_SYS_CFG1_IOBE (1 << 5)
+#define ONENAND_SYS_CFG1_RDY_CONF (1 << 4)
+
+/*
+ * Controller Status Register F240h (R)
+ */
+#define ONENAND_CTRL_ONGO (1 << 15)
+#define ONENAND_CTRL_LOCK (1 << 14)
+#define ONENAND_CTRL_LOAD (1 << 13)
+#define ONENAND_CTRL_PROGRAM (1 << 12)
+#define ONENAND_CTRL_ERASE (1 << 11)
+#define ONENAND_CTRL_ERROR (1 << 10)
+#define ONENAND_CTRL_RSTB (1 << 7)
+
+/*
+ * Interrupt Status Register F241h (R)
+ */
+#define ONENAND_INT_MASTER (1 << 15)
+#define ONENAND_INT_READ (1 << 7)
+#define ONENAND_INT_WRITE (1 << 6)
+#define ONENAND_INT_ERASE (1 << 5)
+#define ONENAND_INT_RESET (1 << 4)
+#define ONENAND_INT_CLEAR (0 << 0)
+
+/*
+ * NAND Flash Write Protection Status Register F24Eh (R)
+ */
+#define ONENAND_WP_US (1 << 2)
+#define ONENAND_WP_LS (1 << 1)
+#define ONENAND_WP_LTS (1 << 0)
+
+/*
+ * ECC Status Reigser FF00h (R)
+ */
+#define ONENAND_ECC_1BIT (1 << 0)
+#define ONENAND_ECC_2BIT (1 << 1)
+#define ONENAND_ECC_2BIT_ALL (0xAAAA)
+
+#endif /* __ONENAND_REG_H */
|
| Author: Mark Wisner
|
-| Change Activity-
-|
-| Date Description of Change BY
-| --------- --------------------- ---
-| 04-May-99 Created MKW
-| 07-Jul-99 Added full duplex support MKW
-| 08-Sep-01 Tweaks gvb
-|
+----------------------------------------------------------------------------*/
#ifndef _miiphy_h_
#define _miiphy_h_
#include <net.h>
-int miiphy_read(char *devname, unsigned char addr, unsigned char reg,
- unsigned short *value);
-int miiphy_write(char *devname, unsigned char addr, unsigned char reg,
- unsigned short value);
-int miiphy_info(char *devname, unsigned char addr, unsigned int *oui,
- unsigned char *model, unsigned char *rev);
-int miiphy_reset(char *devname, unsigned char addr);
-int miiphy_speed(char *devname, unsigned char addr);
-int miiphy_duplex(char *devname, unsigned char addr);
+int miiphy_read (char *devname, unsigned char addr, unsigned char reg,
+ unsigned short *value);
+int miiphy_write (char *devname, unsigned char addr, unsigned char reg,
+ unsigned short value);
+int miiphy_info (char *devname, unsigned char addr, unsigned int *oui,
+ unsigned char *model, unsigned char *rev);
+int miiphy_reset (char *devname, unsigned char addr);
+int miiphy_speed (char *devname, unsigned char addr);
+int miiphy_duplex (char *devname, unsigned char addr);
+int miiphy_is_1000base_x (char *devname, unsigned char addr);
#ifdef CFG_FAULT_ECHO_LINK_DOWN
-int miiphy_link(char *devname, unsigned char addr);
+int miiphy_link (char *devname, unsigned char addr);
#endif
-void miiphy_init(void);
+void miiphy_init (void);
-void miiphy_register(char *devname,
- int (* read)(char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value),
- int (* write)(char *devname, unsigned char addr,
- unsigned char reg, unsigned short value));
+void miiphy_register (char *devname,
+ int (*read) (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value),
+ int (*write) (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value));
-int miiphy_set_current_dev(char *devname);
-char *miiphy_get_current_dev(void);
+int miiphy_set_current_dev (char *devname);
+char *miiphy_get_current_dev (void);
-void miiphy_listdev(void);
+void miiphy_listdev (void);
#define BB_MII_DEVNAME "bbmii"
int bb_miiphy_read (char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value);
+ unsigned char reg, unsigned short *value);
int bb_miiphy_write (char *devname, unsigned char addr,
- unsigned char reg, unsigned short value);
+ unsigned char reg, unsigned short value);
/* phy seed setup */
#define AUTO 99
-#define _1000BASET 1000
+#define _1000BASET 1000
#define _100BASET 100
#define _10BASET 10
#define HALF 22
#define PHY_ANLPAR 0x05
#define PHY_ANER 0x06
#define PHY_ANNPTR 0x07
-#define PHY_ANLPNP 0x08
-#define PHY_1000BTCR 0x09
-#define PHY_1000BTSR 0x0A
+#define PHY_ANLPNP 0x08
+#define PHY_1000BTCR 0x09
+#define PHY_1000BTSR 0x0A
+#define PHY_EXSR 0x0F
#define PHY_PHYSTS 0x10
#define PHY_MIPSCR 0x11
#define PHY_MIPGSR 0x12
#define PHY_BMCR_DPLX 0x0100
#define PHY_BMCR_COL_TST 0x0080
-#define PHY_BMCR_SPEED_MASK 0x2040
-#define PHY_BMCR_1000_MBPS 0x0040
-#define PHY_BMCR_100_MBPS 0x2000
-#define PHY_BMCR_10_MBPS 0x0000
+#define PHY_BMCR_SPEED_MASK 0x2040
+#define PHY_BMCR_1000_MBPS 0x0040
+#define PHY_BMCR_100_MBPS 0x2000
+#define PHY_BMCR_10_MBPS 0x0000
/* phy BMSR */
#define PHY_BMSR_100T4 0x8000
#define PHY_BMSR_100TXH 0x2000
#define PHY_BMSR_10TF 0x1000
#define PHY_BMSR_10TH 0x0800
+#define PHY_BMSR_EXT_STAT 0x0100
#define PHY_BMSR_PRE_SUP 0x0040
#define PHY_BMSR_AUTN_COMP 0x0020
#define PHY_BMSR_RF 0x0010
#define PHY_ANLPAR_NP 0x8000
#define PHY_ANLPAR_ACK 0x4000
#define PHY_ANLPAR_RF 0x2000
+#define PHY_ANLPAR_ASYMP 0x0800
+#define PHY_ANLPAR_PAUSE 0x0400
#define PHY_ANLPAR_T4 0x0200
#define PHY_ANLPAR_TXFD 0x0100
#define PHY_ANLPAR_TX 0x0080
#define PHY_ANLPAR_10FD 0x0040
#define PHY_ANLPAR_10 0x0020
-#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */
-
-#define PHY_ANLPAR_PSB_MASK 0x001f
-#define PHY_ANLPAR_PSB_802_3 0x0001
-#define PHY_ANLPAR_PSB_802_9 0x0002
-
-/* PHY_1000BTSR */
-#define PHY_1000BTSR_MSCF 0x8000
-#define PHY_1000BTSR_MSCR 0x4000
-#define PHY_1000BTSR_LRS 0x2000
-#define PHY_1000BTSR_RRS 0x1000
-#define PHY_1000BTSR_1000FD 0x0800
-#define PHY_1000BTSR_1000HD 0x0400
+#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */
+/* phy ANLPAR 1000BASE-X */
+#define PHY_X_ANLPAR_NP 0x8000
+#define PHY_X_ANLPAR_ACK 0x4000
+#define PHY_X_ANLPAR_RF_MASK 0x3000
+#define PHY_X_ANLPAR_PAUSE_MASK 0x0180
+#define PHY_X_ANLPAR_HD 0x0040
+#define PHY_X_ANLPAR_FD 0x0020
+
+#define PHY_ANLPAR_PSB_MASK 0x001f
+#define PHY_ANLPAR_PSB_802_3 0x0001
+#define PHY_ANLPAR_PSB_802_9 0x0002
+
+/* phy 1000BTCR */
+#define PHY_1000BTCR_1000FD 0x0200
+#define PHY_1000BTCR_1000HD 0x0100
+
+/* phy 1000BTSR */
+#define PHY_1000BTSR_MSCF 0x8000
+#define PHY_1000BTSR_MSCR 0x4000
+#define PHY_1000BTSR_LRS 0x2000
+#define PHY_1000BTSR_RRS 0x1000
+#define PHY_1000BTSR_1000FD 0x0800
+#define PHY_1000BTSR_1000HD 0x0400
+
+/* phy EXSR */
+#define PHY_EXSR_1000XF 0x8000
+#define PHY_EXSR_1000XH 0x4000
+#define PHY_EXSR_1000TF 0x2000
+#define PHY_EXSR_1000TH 0x1000
#endif
--- /dev/null
+/*
+ * Header file for OneNAND support for U-Boot
+ *
+ * Adaptation from kernel to U-Boot
+ *
+ * Copyright (C) 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __UBOOT_ONENAND_H
+#define __UBOOT_ONENAND_H
+
+struct kvec {
+ void *iov_base;
+ size_t iov_len;
+};
+
+typedef int spinlock_t;
+typedef int wait_queue_head_t;
+
+/* Functions */
+extern void onenand_init(void);
+extern int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t * retlen, u_char * buf);
+extern int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t * retlen, u_char * buf);
+extern int onenand_write(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t * retlen, const u_char * buf);
+extern int onenand_erase(struct mtd_info *mtd, struct erase_info *instr);
+
+extern int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len);
+
+extern void onenand_print_device_info(int device, int verbose);
+
+#endif /* __UBOOT_ONENAND_H */
#endif
lbaint_t lba; /* number of blocks */
unsigned long blksz; /* block size */
- unsigned char vendor [40+1]; /* IDE model, SCSI Vendor */
- unsigned char product[20+1]; /* IDE Serial no, SCSI product */
- unsigned char revision[8+1]; /* firmware revision */
+ char vendor [40+1]; /* IDE model, SCSI Vendor */
+ char product[20+1]; /* IDE Serial no, SCSI product */
+ char revision[8+1]; /* firmware revision */
unsigned long (*block_read)(int dev,
unsigned long start,
lbaint_t blkcnt,
# include <asm/status_led.h>
#endif
+/*
+ * Coloured LEDs API
+ */
+#ifndef __ASSEMBLY__
+extern void coloured_LED_init (void);
+extern void red_LED_on(void);
+extern void red_LED_off(void);
+extern void green_LED_on(void);
+extern void green_LED_off(void);
+extern void yellow_LED_on(void);
+extern void yellow_LED_off(void);
+#else
+ .extern LED_init
+ .extern red_LED_on
+ .extern red_LED_off
+ .extern yellow_LED_on
+ .extern yellow_LED_off
+ .extern green_LED_on
+ .extern green_LED_off
+#endif
+
#endif /* CONFIG_STATUS_LED */
#endif /* _STATUS_LED_H_ */
void nand_init (void);
#endif
+#if defined(CONFIG_CMD_ONENAND)
+void onenand_init(void);
+#endif
+
ulong monitor_flash_len;
#ifdef CONFIG_HAS_DATAFLASH
}
/************************************************************************
+ * Coloured LED functionality
+ ************************************************************************
+ * May be supplied by boards if desired
+ */
+void inline __coloured_LED_init (void) {}
+void inline coloured_LED_init (void) __attribute__((weak, alias("__coloured_LED_init")));
+void inline __red_LED_on (void) {}
+void inline red_LED_on (void) __attribute__((weak, alias("__red_LED_on")));
+void inline __red_LED_off(void) {}
+void inline red_LED_off(void) __attribute__((weak, alias("__red_LED_off")));
+void inline __green_LED_on(void) {}
+void inline green_LED_on(void) __attribute__((weak, alias("__green_LED_on")));
+void inline __green_LED_off(void) {}
+void inline green_LED_off(void)__attribute__((weak, alias("__green_LED_off")));
+void inline __yellow_LED_on(void) {}
+void inline yellow_LED_on(void)__attribute__((weak, alias("__yellow_LED_on")));
+void inline __yellow_LED_off(void) {}
+void inline yellow_LED_off(void)__attribute__((weak, alias("__yellow_LED_off")));
+
+/************************************************************************
* Init Utilities *
************************************************************************
* Some of this code should be moved into the core functions,
}
#endif /* CFG_NO_FLASH */
-
/*
* Breathe some life into the board...
*
nand_init(); /* go init the NAND */
#endif
+#if defined(CONFIG_CMD_ONENAND)
+ onenand_init();
+#endif
+
#ifdef CONFIG_HAS_DATAFLASH
AT91F_DataflashInit();
dataflash_print_info();
malloc_bin_reloc();
dma_alloc_init();
board_init_info();
- flash_init();
+
+ bd->bi_flashstart = 0;
+ bd->bi_flashsize = 0;
+ bd->bi_flashoffset = 0;
+
+#ifndef CFG_NO_FLASH
+ bd->bi_flashstart = CFG_FLASH_BASE;
+ bd->bi_flashsize = flash_init();
+ bd->bi_flashoffset = (unsigned long)_edata - (unsigned long)_text;
if (bd->bi_flashsize)
display_flash_config();
+#endif
+
if (bd->bi_dram[0].size)
display_dram_config();
LIB = $(obj)libgeneric.a
-COBJS = bzlib.o bzlib_crctable.o bzlib_decompress.o \
- bzlib_randtable.o bzlib_huffman.o \
- crc32.o ctype.o display_options.o div64.o ldiv.o sha1.o \
- string.o vsprintf.o zlib.o
-
+COBJS-y += bzlib.o
+COBJS-y += bzlib_crctable.o
+COBJS-y += bzlib_decompress.o
+COBJS-y += bzlib_randtable.o
+COBJS-y += bzlib_huffman.o
+COBJS-y += crc32.o
+COBJS-y += ctype.o
+COBJS-y += display_options.o
+COBJS-y += div64.o
+COBJS-y += ldiv.o
+COBJS-y += sha1.o
+COBJS-y += string.o
+COBJS-y += vsprintf.o
+COBJS-y += zlib.o
+
+COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
#include <image.h>
#include <zlib.h>
#include <bzlib.h>
+#include <watchdog.h>
#include <environment.h>
#include <asm/byteorder.h>
#define LINUX_MAX_ENVS 256
#define LINUX_MAX_ARGS 256
+#define CHUNKSZ (64 * 1024)
+
#ifdef CONFIG_SHOW_BOOT_PROGRESS
# include <status_led.h>
# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
#include <common.h>
+#ifdef CFG_TIMER_0
void udelay (unsigned long usec)
{
int i;
i = get_timer (0);
while ((get_timer (0) - i) < (usec / 1000)) ;
}
+#else
+void udelay (unsigned long usec)
+{
+ unsigned int i;
+ for (i = 0; i < (usec * CONFIG_XILINX_CLOCK_FREQ / 10000000); i++);
+}
+#endif
static ulong mem_malloc_end;
static ulong mem_malloc_brk;
+/*
+ * mips_io_port_base is the begin of the address space to which x86 style
+ * I/O ports are mapped.
+ */
+unsigned long mips_io_port_base = -1;
/*
* The Malloc area is immediately below the monitor copy in DRAM
SOBJS =
-COBJS = fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o
-
+COBJS-y += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
#
PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
+
+#
+# From Linux arch/mips/Makefile
+#
+# GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel
+# code since it only slows down the whole thing. At some point we might make
+# use of global pointer optimizations but their use of $28 conflicts with
+# the current pointer optimization.
+#
+# The DECStation requires an ECOFF kernel for remote booting, other MIPS
+# machines may also. Since BFD is incredibly buggy with respect to
+# crossformat linking we rely on the elf2ecoff tool for format conversion.
+#
+# cflags-y += -G 0 -mno-abicalls -fno-pic -pipe
+# cflags-y += -msoft-float
+# LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
+# MODFLAGS += -mlong-calls
+#
+
+#
+# Meanwhile, U-Boot rely on PIC. We add proper switches explicitly.
+#
+PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic -pipe
+PLATFORM_CPPFLAGS += -msoft-float
+PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib
LIB = $(obj)libnet.a
-COBJS = net.o tftp.o bootp.o rarp.o eth.o nfs.o sntp.o
-
+COBJS-y += net.o
+COBJS-y += tftp.o
+COBJS-y += bootp.o
+COBJS-y += rarp.o
+COBJS-y += eth.o
+COBJS-y += nfs.o
+COBJS-y += sntp.o
+
+COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
#if defined(CONFIG_CMD_NET)
-#define TIMEOUT 5 /* Seconds before trying BOOTP again */
+#define TIMEOUT 5UL /* Seconds before trying BOOTP again */
#ifndef CONFIG_NET_RETRY_COUNT
# define TIMEOUT_COUNT 5 /* # of timeouts before giving up */
#else
bp->bp_hlen = HWL_ETHER;
bp->bp_hops = 0;
bp->bp_secs = htons(get_timer(0) / CFG_HZ);
- NetCopyIP(&bp->bp_ciaddr, &bp_offer->bp_ciaddr); /* both in network byte order */
- NetCopyIP(&bp->bp_yiaddr, &bp_offer->bp_yiaddr);
- NetCopyIP(&bp->bp_siaddr, &bp_offer->bp_siaddr);
+ /* Do not set the client IP, your IP, or server IP yet, since it hasn't been ACK'ed by
+ * the server yet */
+
/*
* RFC3046 requires Relay Agents to discard packets with
* nonzero and offered giaddr
/*
* Copy options from OFFER packet if present
*/
- NetCopyIP(&OfferedIP, &bp->bp_yiaddr);
+
+ /* Copy offered IP into the parameters request list */
+ NetCopyIP(&OfferedIP, &bp_offer->bp_yiaddr);
extlen = DhcpExtended((u8 *)bp->bp_vend, DHCP_REQUEST, NetDHCPServerIP, OfferedIP);
pktlen = BOOTP_SIZE - sizeof(bp->bp_vend) + extlen;
{
BootpRequest();
}
-#endif
+#endif /* CONFIG_CMD_DHCP */
-#endif
+#endif /* CONFIG_CMD_NET */
#define DHCP_NAK 6
#define DHCP_RELEASE 7
-#define SELECT_TIMEOUT 3 /* Seconds to wait for offers */
+#define SELECT_TIMEOUT 3UL /* Seconds to wait for offers */
/**********************************************************************/
extern int scc_initialize(bd_t*);
extern int skge_initialize(bd_t*);
extern int tsi108_eth_initialize(bd_t*);
+extern int uli526x_initialize(bd_t *);
extern int tsec_initialize(bd_t*, int, char *);
extern int npe_initialize(bd_t *);
extern int uec_initialize(int);
#if defined(CONFIG_TSI108_ETH)
tsi108_eth_initialize(bis);
#endif
+#if defined(CONFIG_ULI526X)
+ uli526x_initialize(bis);
+#endif
#if defined(CONFIG_RTL8139)
rtl8139_initialize(bis);
#endif
DECLARE_GLOBAL_DATA_PTR;
-#define ARP_TIMEOUT 5 /* Seconds before trying ARP again */
+#define ARP_TIMEOUT 5UL /* Seconds before trying ARP again */
#ifndef CONFIG_NET_RETRY_COUNT
# define ARP_TIMEOUT_COUNT 5 /* # of timeouts before giving up */
#else
return;
}
#ifndef CONFIG_NET_MULTI
- NetSetTimeout (10 * CFG_HZ, startAgainTimeout);
+ NetSetTimeout (10UL * CFG_HZ, startAgainTimeout);
NetSetHandler (startAgainHandler);
#else /* !CONFIG_NET_MULTI*/
eth_halt ();
if (NetRestartWrap) {
NetRestartWrap = 0;
if (NetDevExists && !once) {
- NetSetTimeout (10 * CFG_HZ, startAgainTimeout);
+ NetSetTimeout (10UL * CFG_HZ, startAgainTimeout);
NetSetHandler (startAgainHandler);
} else {
NetState = NETLOOP_FAIL;
#if defined(CONFIG_NET_MULTI)
printf ("Using %s device\n", eth_get_name());
#endif /* CONFIG_NET_MULTI */
- NetSetTimeout (10 * CFG_HZ, PingTimeout);
+ NetSetTimeout (10UL * CFG_HZ, PingTimeout);
NetSetHandler (PingHandler);
PingSend();
#if defined(CONFIG_CMD_NET) && defined(CONFIG_CMD_NFS)
#define HASHES_PER_LINE 65 /* Number of "loading" hashes per line */
-#define NFS_TIMEOUT 60
+#define NFS_TIMEOUT 60UL
static int fs_mounted = 0;
static unsigned long rpc_id = 0;
if (rpc_pkt.u.reply.rstatus ||
rpc_pkt.u.reply.verifier ||
- rpc_pkt.u.reply.astatus ||
rpc_pkt.u.reply.astatus) {
return -1;
}
#if defined(CONFIG_CMD_NET)
-#define TIMEOUT 5 /* Seconds before trying BOOTP again */
+#define TIMEOUT 5UL /* Seconds before trying BOOTP again */
#ifndef CONFIG_NET_RETRY_COUNT
# define TIMEOUT_COUNT 5 /* # of timeouts before giving up */
#else
#if defined(CONFIG_CMD_NET)
#define WELL_KNOWN_PORT 69 /* Well known TFTP port # */
-#define TIMEOUT 5 /* Seconds to timeout for a lost pkt */
+#define TIMEOUT 5UL /* Seconds to timeout for a lost pkt */
#ifndef CONFIG_NET_RETRY_COUNT
# define TIMEOUT_COUNT 10 /* # of timeouts before giving up */
#else
LIB = $(obj)librtc.a
-COBJS = date.o \
- bf5xx_rtc.o ds12887.o ds1302.o ds1306.o ds1307.o \
- ds1337.o ds1374.o ds1556.o ds164x.o ds174x.o ds3231.o \
- m41t11.o max6900.o m48t35ax.o mc146818.o mk48t59.o \
- mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o \
- mcfrtc.o
+COBJS-y += date.o
+COBJS-y += bf5xx_rtc.o
+COBJS-y += ds12887.o
+COBJS-y += ds1302.o
+COBJS-y += ds1306.o
+COBJS-y += ds1307.o
+COBJS-y += ds1337.o
+COBJS-y += ds1374.o
+COBJS-y += ds1556.o
+COBJS-y += ds164x.o
+COBJS-y += ds174x.o
+COBJS-y += ds3231.o
+COBJS-y += m41t11.o
+COBJS-y += max6900.o
+COBJS-y += m48t35ax.o
+COBJS-y += mc146818.o
+COBJS-y += mk48t59.o
+COBJS-y += mpc5xxx.o
+COBJS-y += mpc8xx.o
+COBJS-y += pcf8563.o
+COBJS-y += s3c24x0_rtc.o
+COBJS-y += rs5c372.o
+COBJS-y += mcfrtc.o
+COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
--- /dev/null
+/bmp_logo
+/crc32.c
+/envcrc
+/environment.c
+/gen_eth_addr
+/img2srec
+/mkimage
+/sha1.c
+/ubsha1
projects / platform / kernel / u-boot.git / commitdiff