windows_vm: vs2017-win2016
ubuntu_vm: ubuntu-18.04
macos_vm: macOS-10.15
- ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210827-30Sep2021
+ ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210921-05Oct2021
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.
TEST_PY_BD: "sandbox"
sandbox_clang:
TEST_PY_BD: "sandbox"
- OVERRIDE: "-O clang-12"
+ OVERRIDE: "-O clang-13"
sandbox_spl:
TEST_PY_BD: "sandbox_spl"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
# Grab our configured image. The source for this is found at:
# https://source.denx.de/u-boot/gitlab-ci-runner
-image: trini/u-boot-gitlab-ci-runner:focal-20210827-30Sep2021
+image: trini/u-boot-gitlab-ci-runner:focal-20210921-05Oct2021
# We run some tests in different order, to catch some failures quicker.
stages:
sandbox with clang test.py:
variables:
TEST_PY_BD: "sandbox"
- OVERRIDE: "-O clang-12"
+ OVERRIDE: "-O clang-13"
<<: *buildman_and_testpy_dfn
sandbox_spl test.py:
F: include/linux/libfdt*
F: cmd/fdt.c
F: common/fdt_support.c
+F: scripts/dtc-version.sh
FREEBSD
M: Rafal Jaworowski <raj@semihalf.com>
F: arch/riscv/
F: cmd/riscv/
F: doc/usage/sbi.rst
+F: drivers/sysreset/sysreset_sbi.c
F: drivers/timer/andes_plmt_timer.c
F: drivers/timer/sifive_clint_timer.c
F: tools/prelink-riscv.c
# have older compilers as their default, so we make it explicit for
# these that our host tools are GNU11 (i.e. C11 w/ GNU extensions).
CSTD_FLAG := -std=gnu11
-ifeq ($(HOSTOS),linux)
KBUILD_HOSTCFLAGS += $(CSTD_FLAG)
-endif
ifeq ($(HOSTOS),cygwin)
KBUILD_HOSTCFLAGS += -ansi
PYTHON ?= python
PYTHON2 = python2
PYTHON3 ?= python3
-DTC ?= $(objtree)/scripts/dtc/dtc
+
+# The devicetree compiler and pylibfdt are automatically built unless DTC is
+# provided. If DTC is provided, it is assumed the pylibfdt is available too.
+DTC_INTREE := $(objtree)/scripts/dtc/dtc
+DTC ?= $(DTC_INTREE)
+DTC_MIN_VERSION := 010406
+
CHECK = sparse
CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
endif
+# Check dtc and pylibfdt, if DTC is provided, else build them
PHONY += scripts_dtc
scripts_dtc: scripts_basic
- $(Q)$(MAKE) $(build)=scripts/dtc
+ $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \
+ $(MAKE) $(build)=scripts/dtc; \
+ else \
+ if ! $(DTC) -v >/dev/null; then \
+ echo '*** Failed to check dtc version: $(DTC)'; \
+ false; \
+ else \
+ if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \
+ echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \
+ false; \
+ else \
+ if [ -n "$(CONFIG_PYLIBFDT)" ]; then \
+ if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \
+ echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \
+ false; \
+ fi; \
+ fi; \
+ fi; \
+ fi; \
+ fi
# ---------------------------------------------------------------------------
quiet_cmd_cpp_lds = LDS $@
"(fake run for tracing)" : "");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
r0 = 2;
r2 = (unsigned int)images->ft_addr;
} else {
select DM
select GPIO_EXTRA_HEADER
select OF_CONTROL
- select OF_PRIOR_STAGE
imply CMD_DM
help
This enables support for Broadcom ARM-based set-top box
select DM
select DM_ETH
select DM_GPIO
+ select DM_I2C if I2C
select DM_KEYBOARD
select DM_MMC if MMC
select DM_SCSI if SCSI
(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
-#define GPT_RESOLUTION (CONFIG_STV0991_HZ_CLOCK / CONFIG_STV0991_HZ)
+#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR;
{
ulong tmo;
ulong start = get_timer_masked();
- ulong tenudelcnt = CONFIG_STV0991_HZ_CLOCK / (1000 * 100);
+ ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100);
ulong rndoff;
rndoff = (usec % 10) ? 1 : 0;
*/
ulong get_tbclk(void)
{
- return CONFIG_STV0991_HZ;
+ return CONFIG_SYS_HZ;
}
lpi_base.start = addr;
lpi_base.end = addr + size - 1;
- ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL, false);
+ ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL,
+ 0, NULL, 0);
if (ret) {
debug("%s: failed to add reserved memory\n", __func__);
return ret;
s5p4418-nanopi2.dtb
dtb-$(CONFIG_ARCH_MESON) += \
+ meson-axg-s400.dtb \
+ meson-axg-jethome-jethub-j100.dtb \
meson-gxbb-nanopi-k2.dtb \
meson-gxbb-odroidc2.dtb \
meson-gxbb-nanopi-k2.dtb \
meson-gxbb-p200.dtb \
meson-gxbb-p201.dtb \
- meson-gxl-s905x-p212.dtb \
meson-gxl-s805x-libretech-ac.dtb \
+ meson-gxl-s905d-libretech-pc.dtb \
+ meson-gxl-s905w-jethome-jethub-j80.dtb \
+ meson-gxl-s905x-khadas-vim.dtb \
meson-gxl-s905x-libretech-cc.dtb \
meson-gxl-s905x-libretech-cc-v2.dtb \
- meson-gxl-s905x-khadas-vim.dtb \
- meson-gxl-s905d-libretech-pc.dtb \
+ meson-gxl-s905x-p212.dtb \
meson-gxm-khadas-vim2.dtb \
meson-gxm-s912-libretech-pc.dtb \
meson-gxm-wetek-core2.dtb \
- meson-axg-s400.dtb \
- meson-g12a-u200.dtb \
+ meson-g12a-radxa-zero.dtb \
meson-g12a-sei510.dtb \
+ meson-g12a-u200.dtb \
+ meson-g12b-a311d-khadas-vim3.dtb \
meson-g12b-gtking.dtb \
meson-g12b-gtking-pro.dtb \
+ meson-g12b-gsking-x.dtb \
meson-g12b-odroid-n2.dtb \
meson-g12b-odroid-n2-plus.dtb \
- meson-g12b-a311d-khadas-vim3.dtb \
+ meson-sm1-bananapi-m5.dtb \
meson-sm1-khadas-vim3l.dtb \
meson-sm1-odroid-c4.dtb \
+ meson-sm1-odroid-hc4.dtb \
meson-sm1-sei610.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
sun50i-h5-libretech-all-h5-cc.dtb \
sun50i-h5-nanopi-neo2.dtb \
sun50i-h5-nanopi-neo-plus2.dtb \
+ sun50i-h5-nanopi-r1s-h5.dtb \
sun50i-h5-orangepi-zero-plus.dtb \
sun50i-h5-orangepi-pc2.dtb \
sun50i-h5-orangepi-prime.dtb \
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x0490>, <0x045c>, <0x0468>;
+ reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
};
dpll_core_x2_ck: dpll_core_x2_ck {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x0488>, <0x0420>, <0x042c>;
+ reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x0494>, <0x0434>, <0x0440>;
+ reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x0498>, <0x0448>, <0x0454>;
+ reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
};
dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-j-type-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x048c>, <0x0470>, <0x049c>;
+ reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
};
dpll_per_m2_ck: dpll_per_m2_ck@4ac {
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2d20>, <0x2d24>, <0x2d2c>;
+ reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>;
};
dpll_core_x2_ck: dpll_core_x2_ck {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2d60>, <0x2d64>, <0x2d6c>;
+ reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2da0>, <0x2da4>, <0x2dac>;
+ reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2e20>, <0x2e24>, <0x2e2c>;
+ reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>;
};
dpll_disp_m2_ck: dpll_disp_m2_ck {
#clock-cells = <0>;
compatible = "ti,am3-dpll-j-type-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2de0>, <0x2de4>, <0x2dec>;
+ reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>;
};
dpll_per_m2_ck: dpll_per_m2_ck {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2e60>, <0x2e64>, <0x2e6c>;
+ reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>;
};
dpll_extdev_m2_ck: dpll_extdev_m2_ck {
/*
* The 128 MiB address range [0xe8000000-0xf0000000] is
* dedicated for PCIe and can be assigned to 8 windows
- * with size a power of two. Use one 64 KiB window for
+ * with size a power of two. Use one 1 MiB window for
* IO at the end and the remaining seven windows
* (totaling 127 MiB) for MEM.
*/
ranges = <0x82000000 0 0xe8000000
0 0xe8000000 0 0x7f00000 /* Port 0 MEM */
- 0x81000000 0 0xefff0000
- 0 0xefff0000 0 0x10000>; /* Port 0 IO*/
+ 0x81000000 0 0xeff00000
+ 0 0xeff00000 0 0x100000>; /* Port 0 IO*/
};
};
};
&cp1_mdio {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_smi_pins>;
+
cp1_ge_phy0: ethernet-phy@3 {
reg = <1>;
};
/*
* MPP Bus:
* [0-5] TDM
- * [6,7] CP1_UART 0
- * [8] CP1 10G SFP LOS
- * [9] CP1 10G PHY RESET
- * [10] CP1 10G SFP TX Disable
- * [11] CP1 10G SFP Mode
- * [12] SPI1 CS1n
- * [13] SPI1 MISO (TDM and SPI ROM shared)
- * [14] SPI1 CS0n
- * [15] SPI1 MOSI (TDM and SPI ROM shared)
- * [16] SPI1 CLK (TDM and SPI ROM shared)
- * [24] CP1 2.5G SFP TX Disable
- * [26] CP0 10G SFP TX Fault
- * [27] CP0 10G SFP Mode
- * [28] CP0 10G SFP LOS
- * [29] CP0 10G SFP TX Disable
- * [30] USB Over current indication
- * [31] 10G Port 0 phy reset
+ * [27-28] SMI
+ * [29-30] CP1 MSS I2C
+ * [6-26, 31] GPIO
* [32-62] = 0xff: Keep default CP1_shared_pins:
*/
/* 0 1 2 3 4 5 6 7 8 9 */
- pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x8 0x8 0x0 0x0
- 0x0 0x0 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff
- 0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x0 0x0 0x0
- 0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x8 0x8 0x8
+ 0x8 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff>;
+
+ cp1_smi_pins: cp1-smi-pins {
+ marvell,pins = < 27 28 >;
+ marvell,function = <8>;
+ };
};
&ap_spi0 {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2018-2021
+ *
+ * Authors:
+ * Chao Zeng <chao.zeng@siemens.com>
+ *
+ * U-Boot bits of the IOT2050 Advanced PG2 variants
+ * (downgrade of usb0 to USB 2.0 mode)
+ */
+
+&serdes0 {
+ status = "disabled";
+};
+
+&dwc3_0 {
+ assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
+ <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
+ /delete-property/ phys;
+ /delete-property/ phy-names;
+};
+
+&usb0 {
+ maximum-speed = "high-speed";
+ /delete-property/ snps,dis-u1-entry-quirk;
+ /delete-property/ snps,dis-u2-entry-quirk;
+};
phy-names = "usb3-phy";
};
-&usb0_phy {
+&usb0 {
maximum-speed = "super-speed";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
};
+
+#include "k3-am65-iot2050-common-pg2-u-boot.dtsi"
&cbass_main {
u-boot,dm-spl;
- main-navss {
+ main_navss: bus@30800000 {
u-boot,dm-spl;
};
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Vyacheslav Bocharov <adeep@lexina.in>
+ * Copyright (c) 2020 JetHome
+ * Author: Aleksandr Kazantsev <ak@tvip.ru>
+ * Author: Alexey Shevelkin <ash@tvip.ru>
+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
+ */
+
+/dts-v1/;
+
+#include "meson-axg.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "jethome,jethub-j100", "amlogic,a113d", "amlogic,meson-axg";
+ model = "JetHome JetHub J100";
+ aliases {
+ serial0 = &uart_AO; /* Console */
+ serial1 = &uart_AO_B; /* External UART (Wireless Module) */
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ /* 1024MB RAM */
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ reserved-memory {
+ linux,cma {
+ size = <0x0 0x400000>;
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_5v: regulator-vcc_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_5v>;
+ regulator-always-on;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ usb_pwr: regulator-usb_pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_PWR";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+ regulator-always-on;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&scpi_sensors 0>;
+ trips {
+ cpu_passive: cpu-passive {
+ temperature = <70000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+
+ cpu_hot: cpu-hot {
+ temperature = <80000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "hot";
+ };
+
+ cpu_critical: cpu-critical {
+ temperature = <100000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ cpu_cooling_maps: cooling-maps {
+ map0 {
+ trip = <&cpu_passive>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+
+ map1 {
+ trip = <&cpu_hot>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ onewire {
+ compatible = "w1-gpio";
+ gpios = <&gpio GPIOA_14 GPIO_ACTIVE_HIGH>;
+ #gpio-cells = <1>;
+ };
+};
+
+&efuse {
+ sn: sn@32 {
+ reg = <0x32 0x20>;
+ };
+
+ eth_mac: eth_mac@0 {
+ reg = <0x0 0x6>;
+ };
+
+ bt_mac: bt_mac@6 {
+ reg = <0x6 0x6>;
+ };
+
+ wifi_mac: wifi_mac@c {
+ reg = <0xc 0x6>;
+ };
+
+ bid: bid@12 {
+ reg = <0x12 0x20>;
+ };
+};
+
+ðmac {
+ status = "okay";
+ pinctrl-0 = <ð_rmii_x_pins>;
+ pinctrl-names = "default";
+ phy-handle = <ð_phy0>;
+ phy-mode = "rmii";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* ICPlus IP101A/G Ethernet PHY (vendor_id=0x0243, model_id=0x0c54) */
+ eth_phy0: ethernet-phy@0 {
+ /* compatible = "ethernet-phy-id0243.0c54";*/
+ max-speed = <100>;
+ reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
+ reset-gpios = <&gpio GPIOZ_5 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+/* Internal I2C bus (on CPU module) */
+&i2c1 {
+ status = "okay";
+ pinctrl-0 = <&i2c1_z_pins>;
+ pinctrl-names = "default";
+
+ /* RTC */
+ pcf8563: pcf8563@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ status = "okay";
+ };
+};
+
+/* Peripheral I2C bus (on motherboard) */
+&i2c_AO {
+ status = "okay";
+ pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_ab {
+ status = "okay";
+ pinctrl-0 = <&pwm_a_x20_pins>;
+ pinctrl-names = "default";
+};
+
+/* wifi module */
+&sd_emmc_b {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr104;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* emmc storage */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* UART Bluetooth */
+&uart_B {
+ status = "okay";
+ pinctrl-0 = <&uart_b_z_pins>, <&uart_b_z_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* UART Console */
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+/* UART Wireless module */
+&uart_AO_B {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_b_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+ phy-supply = <&usb_pwr>;
+};
+
+&spicc1 {
+ status = "okay";
+ pinctrl-0 = <&spi1_x_pins>, <&spi1_ss0_x_pins>;
+ pinctrl-names = "default";
+};
+
+&gpio {
+ gpio-line-names =
+ "", "", "", "", "", // 0 - 4
+ "", "", "", "", "", // 5 - 9
+ "UserButton", "", "", "", "", // 10 - 14
+ "", "", "", "", "", // 15 - 19
+ "", "", "", "", "", // 20 - 24
+ "", "LedRed", "LedGreen", "Output3", "Output2", // 25 - 29
+ "Output1", "", "", "", "", // 30 - 34
+ "", "ZigBeeBOOT", "", "", "", // 35 - 39
+ "", "ZigBeeRESET", "", "Input4", "Input3", // 40 - 44
+ "Input2", "Input1", "", "", "", // 45 - 49
+ "", "", "", "", "", // 50 - 54
+ "", "", "", "", "", // 55 - 59
+ "", "", "", "", "", // 60 - 64
+ "", "", "", "", "", // 65 - 69
+ "", "", "", "", "", // 70 - 74
+ "", "", "", "", "", // 75 - 79
+ "", "", "", "", "", // 80 - 84
+ "", ""; // 85-86
+};
+
+&cpu0 {
+ #cooling-cells = <2>;
+};
+
+&cpu1 {
+ #cooling-cells = <2>;
+};
+
+&cpu2 {
+ #cooling-cells = <2>;
+};
+
+&cpu3 {
+ #cooling-cells = <2>;
+};
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
*/
-#include "meson-axg-u-boot.dtsi"
-
/* wifi module */
&sd_emmc_b {
status = "disabled";
status = "okay";
};
-&usb {
- status = "okay";
- dr_mode = "otg";
- vbus-supply = <&usb_pwr>;
-};
-
&usb2_phy1 {
phy-supply = <&vcc_5v>;
};
status = "okay";
};
+&pcieA {
+ reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcieB {
+ reset-gpios = <&gpio GPIOZ_10 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
&pwm_ab {
status = "okay";
pinctrl-0 = <&pwm_a_x20_pins>;
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
+
+&usb {
+ status = "okay";
+ dr_mode = "otg";
+ vbus-supply = <&usb_pwr>;
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-/ {
- soc {
- usb: usb@ffe09080 {
- compatible = "amlogic,meson-gxl-usb-ctrl";
- reg = <0x0 0xffe09080 0x0 0x20>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
- clock-names = "usb_ctrl", "ddr";
- resets = <&reset RESET_USB_OTG>;
-
- dr_mode = "otg";
-
- phys = <&usb2_phy1>;
- phy-names = "usb2-phy1";
-
- dwc2: usb@ff400000 {
- compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
- reg = <0x0 0xff400000 0x0 0x40000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clkc CLKID_USB1>;
- clock-names = "otg";
- phys = <&usb2_phy1>;
- dr_mode = "peripheral";
- g-rx-fifo-size = <192>;
- g-np-tx-fifo-size = <128>;
- g-tx-fifo-size = <128 128 16 16 16>;
- };
-
- dwc3: usb@ff500000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xff500000 0x0 0x100000>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- maximum-speed = "high-speed";
- snps,dis_u2_susphy_quirk;
- };
- };
- };
-};
-
-&apb {
- usb2_phy1: phy@9020 {
- compatible = "amlogic,meson-gxl-usb2-phy";
- #phy-cells = <0>;
- reg = <0x0 0x9020 0x0 0x20>;
- clocks = <&clkc CLKID_USB>;
- clock-names = "phy";
- resets = <&reset RESET_USB_OTG>;
- reset-names = "phy";
- status = "okay";
- };
-};
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
+#include <dt-bindings/power/meson-axg-power.h>
/ {
compatible = "amlogic,meson-axg";
#size-cells = <2>;
ranges;
+ pcieA: pcie@f9800000 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf9800000 0x0 0x400000>,
+ <0x0 0xff646000 0x0 0x2000>,
+ <0x0 0xf9f00000 0x0 0x100000>;
+ reg-names = "elbi", "cfg", "config";
+ interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>;
+
+ clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>;
+ clock-names = "general", "pclk", "port";
+ resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>;
+ reset-names = "port", "apb";
+ num-lanes = <1>;
+ phys = <&pcie_phy>;
+ phy-names = "pcie";
+ status = "disabled";
+ };
+
+ pcieB: pcie@fa000000 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xfa000000 0x0 0x400000>,
+ <0x0 0xff648000 0x0 0x2000>,
+ <0x0 0xfa400000 0x0 0x100000>;
+ reg-names = "elbi", "cfg", "config";
+ interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>;
+
+ clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>;
+ clock-names = "general", "pclk", "port";
+ resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>;
+ reset-names = "port", "apb";
+ num-lanes = <1>;
+ phys = <&pcie_phy>;
+ phy-names = "pcie";
+ status = "disabled";
+ };
+
+ usb: usb@ffe09080 {
+ compatible = "amlogic,meson-axg-usb-ctrl";
+ reg = <0x0 0xffe09080 0x0 0x20>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
+ clock-names = "usb_ctrl", "ddr";
+ resets = <&reset RESET_USB_OTG>;
+
+ dr_mode = "otg";
+
+ phys = <&usb2_phy1>;
+ phy-names = "usb2-phy1";
+
+ dwc2: usb@ff400000 {
+ compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
+ reg = <0x0 0xff400000 0x0 0x40000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLKID_USB1>;
+ clock-names = "otg";
+ phys = <&usb2_phy1>;
+ dr_mode = "peripheral";
+ g-rx-fifo-size = <192>;
+ g-np-tx-fifo-size = <128>;
+ g-tx-fifo-size = <128 128 16 16 16>;
+ };
+
+ dwc3: usb@ff500000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff500000 0x0 0x100000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+ snps,dis_u2_susphy_quirk;
+ };
+ };
+
ethmac: ethernet@ff3f0000 {
compatible = "amlogic,meson-axg-dwmac",
"snps,dwmac-3.70a",
"timing-adjustment";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
+ power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>;
status = "disabled";
};
+ pcie_phy: phy@ff644000 {
+ compatible = "amlogic,axg-pcie-phy";
+ reg = <0x0 0xff644000 0x0 0x1c>;
+ resets = <&reset RESET_PCIE_PHY>;
+ phys = <&mipi_pcie_analog_dphy>;
+ phy-names = "analog";
+ #phy-cells = <0>;
+ };
+
pdm: audio-controller@ff632000 {
compatible = "amlogic,axg-pdm";
reg = <0x0 0xff632000 0x0 0x34>;
clocks = <&xtal>;
clock-names = "xtal";
};
+
+ pwrc: power-controller {
+ compatible = "amlogic,meson-axg-pwrc";
+ #power-domain-cells = <1>;
+ amlogic,ao-sysctrl = <&sysctrl_AO>;
+ resets = <&reset RESET_VIU>,
+ <&reset RESET_VENC>,
+ <&reset RESET_VCBUS>,
+ <&reset RESET_VENCL>,
+ <&reset RESET_VID_LOCK>;
+ reset-names = "viu", "venc", "vcbus",
+ "vencl", "vid_lock";
+ clocks = <&clkc CLKID_VPU>,
+ <&clkc CLKID_VAPB>;
+ clock-names = "vpu", "vapb";
+ /*
+ * VPU clocking is provided by two identical clock paths
+ * VPU_0 and VPU_1 muxed to a single clock by a glitch
+ * free mux to safely change frequency while running.
+ * Same for VAPB but with a final gate after the glitch free mux.
+ */
+ assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
+ <&clkc CLKID_VPU_0>,
+ <&clkc CLKID_VPU>, /* Glitch free mux */
+ <&clkc CLKID_VAPB_0_SEL>,
+ <&clkc CLKID_VAPB_0>,
+ <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>,
+ <0>, /* Do Nothing */
+ <&clkc CLKID_VPU_0>,
+ <&clkc CLKID_FCLK_DIV4>,
+ <0>, /* Do Nothing */
+ <&clkc CLKID_VAPB_0>;
+ assigned-clock-rates = <0>, /* Do Nothing */
+ <250000000>,
+ <0>, /* Do Nothing */
+ <0>, /* Do Nothing */
+ <250000000>,
+ <0>; /* Do Nothing */
+ };
+
+ mipi_pcie_analog_dphy: phy {
+ compatible = "amlogic,axg-mipi-pcie-analog-phy";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
};
};
#mbox-cells = <1>;
};
+ mipi_dphy: phy@ff640000 {
+ compatible = "amlogic,axg-mipi-dphy";
+ reg = <0x0 0xff640000 0x0 0x100>;
+ clocks = <&clkc CLKID_MIPI_DSI_PHY>;
+ clock-names = "pclk";
+ resets = <&reset RESET_MIPI_PHY>;
+ reset-names = "phy";
+ phys = <&mipi_pcie_analog_dphy>;
+ phy-names = "analog";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
audio: bus@ff642000 {
compatible = "simple-bus";
reg = <0x0 0xff642000 0x0 0x2000>;
};
};
+ ge2d: ge2d@ff940000 {
+ compatible = "amlogic,axg-ge2d";
+ reg = <0x0 0xff940000 0x0 0x10000>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc CLKID_VAPB>;
+ resets = <&reset RESET_GE2D>;
+ };
+
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
reg = <0x0 0xffc01000 0 0x1000>,
status = "disabled";
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
+ fifo-size = <128>;
};
};
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
};
+
+ usb2_phy1: phy@9020 {
+ compatible = "amlogic,meson-gxl-usb2-phy";
+ #phy-cells = <0>;
+ reg = <0x0 0x9020 0x0 0x20>;
+ clocks = <&clkc CLKID_USB>;
+ clock-names = "phy";
+ resets = <&reset RESET_USB_OTG>;
+ reset-names = "phy";
+ };
};
sram: sram@fffc0000 {
*/
/ {
+ /* Keep HW order from U-boot */
+ aliases {
+ /delete-property/ mmc0;
+ /delete-property/ mmc1;
+ /delete-property/ mmc2;
+ };
+
soc {
u-boot,dm-pre-reloc;
};
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ mmc0 = &sd_emmc_b; /* SD card */
+ mmc1 = &sd_emmc_c; /* eMMC */
+ mmc2 = &sd_emmc_a; /* SDIO */
+ };
+
chosen {
#address-cells = <2>;
#size-cells = <2>;
pcie: pcie@fc000000 {
compatible = "amlogic,g12a-pcie", "snps,dw-pcie";
- reg = <0x0 0xfc000000 0x0 0x400000
- 0x0 0xff648000 0x0 0x2000
- 0x0 0xfc400000 0x0 0x200000>;
+ reg = <0x0 0xfc000000 0x0 0x400000>,
+ <0x0 0xff648000 0x0 0x2000>,
+ <0x0 0xfc400000 0x0 0x200000>;
reg-names = "elbi", "cfg", "config";
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000
- 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
+ ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000>,
+ <0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
clocks = <&clkc CLKID_PCIE_PHY
&clkc CLKID_PCIE_COMB
};
ethmac: ethernet@ff3f0000 {
- compatible = "amlogic,meson-axg-dwmac",
+ compatible = "amlogic,meson-g12a-dwmac",
"snps,dwmac-3.70a",
"snps,dwmac";
reg = <0x0 0xff3f0000 0x0 0x10000>,
hwrng: rng@218 {
compatible = "amlogic,meson-rng";
reg = <0x0 0x218 0x0 0x4>;
+ clocks = <&clkc CLKID_RNG0>;
+ clock-names = "core";
};
};
};
};
- vrtc: rtc@0a8 {
+ vrtc: rtc@a8 {
compatible = "amlogic,meson-vrtc";
reg = <0x0 0x000a8 0x0 0x4>;
};
amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
};
+ watchdog: watchdog@f0d0 {
+ compatible = "amlogic,meson-gxbb-wdt";
+ reg = <0x0 0xf0d0 0x0 0x10>;
+ clocks = <&xtal>;
+ };
+
spicc0: spi@13000 {
compatible = "amlogic,meson-g12a-spicc";
reg = <0x0 0x13000 0x0 0x44>;
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
+ fifo-size = <128>;
};
};
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,dis_u2_susphy_quirk;
- snps,quirk-frame-length-adjustment;
+ snps,quirk-frame-length-adjustment = <0x20>;
snps,parkmode-disable-ss-quirk;
};
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-g12-common-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 BayLibre SAS. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-g12a.dtsi"
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "radxa,zero", "amlogic,g12a";
+ model = "Radxa Zero";
+
+ aliases {
+ serial0 = &uart_AO;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ cvbs-connector {
+ status = "disabled";
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ ao_5v: regulator-ao_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "AO_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vcc_1v8: regulator-vcc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ hdmi_pw: regulator-hdmi_pw {
+ compatible = "regulator-fixed";
+ regulator-name = "HDMI_PW";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&ao_5v>;
+ regulator-always-on;
+ };
+
+ vddao_1v8: regulator-vddao_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&ao_5v>;
+ regulator-always-on;
+ };
+
+ vddcpu: regulator-vddcpu {
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU";
+ regulator-min-microvolt = <721000>;
+ regulator-max-microvolt = <1022000>;
+
+ vin-supply = <&ao_5v>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "RADXA-ZERO";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&cec_AO {
+ pinctrl-0 = <&cec_ao_a_h_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+ pinctrl-0 = <&cec_ao_b_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu2 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu3 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&hdmi_pw>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "disabled";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin0";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+/* SDIO */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr50;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+
+ /* WiFi firmware requires power to be kept while in suspend */
+ keep-power-in-suspend;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_1v8>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ clocks = <&wifi32k>;
+ clock-names = "lpo";
+ };
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
+};
sound {
compatible = "amlogic,axg-sound-card";
- model = "G12A-SEI510";
+ model = "SEI510";
audio-aux-devs = <&tdmout_a>, <&tdmout_b>,
<&tdmin_a>, <&tdmin_b>;
audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-g12-common-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-w400.dtsi"
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "azw,gsking-x", "amlogic,s922x", "amlogic,g12b";
+ model = "Beelink GS-King X";
+
+ aliases {
+ rtc0 = &rtc;
+ rtc1 = &vrtc;
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <100>;
+
+ power-button {
+ label = "power";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "GSKING-X";
+ audio-aux-devs = <&tdmout_a>;
+ audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_A IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_A IN 2", "FRDDR_C OUT 1",
+ "TDM_A Playback", "TDMOUT_A OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_a>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
+ };
+ };
+
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+ pinctrl-names = "default";
+
+ rtc: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ wakeup-source;
+ };
+};
+
+&tdmif_a {
+ status = "okay";
+};
+
+&tdmout_a {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ {
- compatible = "azw,gtking", "amlogic,g12b";
+ compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b";
model = "Beelink GT-King Pro";
+ aliases {
+ rtc0 = &rtc;
+ rtc1 = &vrtc;
+ };
+
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
leds {
compatible = "gpio-leds";
- white {
+ led-white {
label = "power:white";
gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
default-state = "on";
sound {
compatible = "amlogic,axg-sound-card";
- model = "G12B-GTKING-PRO";
+ model = "GTKING-PRO";
audio-aux-devs = <&tdmout_b>;
audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
"TDMOUT_B IN 1", "FRDDR_B OUT 1",
status = "okay";
};
+&i2c3 {
+ status = "okay";
+ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+ pinctrl-names = "default";
+
+ rtc: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ wakeup-source;
+ };
+};
+
&tdmif_b {
status = "okay";
};
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ {
- compatible = "azw,gtking", "amlogic,g12b";
+ compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b";
model = "Beelink GT-King";
+ aliases {
+ rtc0 = &rtc;
+ rtc1 = &vrtc;
+ };
+
spdif_dit: audio-codec-1 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
sound {
compatible = "amlogic,axg-sound-card";
- model = "G12B-GTKING";
+ model = "GTKING";
audio-aux-devs = <&tdmout_b>;
audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
"TDMOUT_B IN 1", "FRDDR_B OUT 1",
status = "okay";
};
+
+&i2c3 {
+ status = "okay";
+ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+ pinctrl-names = "default";
+
+ rtc: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ wakeup-source;
+ };
+};
+
&spdifout {
pinctrl-0 = <&spdif_out_h_pins>;
pinctrl-names = "default";
regulator-min-microvolt = <680000>;
regulator-max-microvolt = <1040000>;
- pwms = <&pwm_AO_cd 1 1500 0>;
+ pwms = <&pwm_ab 0 1500 0>;
};
&vddcpu_b {
aliases {
serial0 = &uart_AO;
ethernet0 = ðmac;
+ rtc0 = &rtc;
+ rtc1 = &vrtc;
};
dioo2133: audio-amplifier-0 {
leds {
compatible = "gpio-leds";
- blue {
+ led-blue {
label = "n2:blue";
gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
sound {
compatible = "amlogic,axg-sound-card";
- model = "G12B-ODROID-N2";
+ model = "ODROID-N2";
audio-widgets = "Line", "Lineout";
audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>,
<&tdmin_b>, <&tdmin_c>, <&tdmin_lb>,
&ext_mdio {
external_phy: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
+ /* Realtek RTL8211F (0x001cc916) */
reg = <0>;
max-speed = <1000>;
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
interrupt-parent = <&gpio_intc>;
};
&gpio {
+ gpio-line-names =
+ /* GPIOZ */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* GPIOH */
+ "", "", "", "", "", "", "", "",
+ "",
+ /* BOOT */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* GPIOC */
+ "", "", "", "", "", "", "", "",
+ /* GPIOA */
+ "PIN_44", /* GPIOA_0 */
+ "PIN_46", /* GPIOA_1 */
+ "PIN_45", /* GPIOA_2 */
+ "PIN_47", /* GPIOA_3 */
+ "PIN_26", /* GPIOA_4 */
+ "", "", "", "", "", "",
+ "PIN_42", /* GPIOA_11 */
+ "PIN_32", /* GPIOA_12 */
+ "PIN_7", /* GPIOA_13 */
+ "PIN_27", /* GPIOA_14 */
+ "PIN_28", /* GPIOA_15 */
+ /* GPIOX */
+ "PIN_16", /* GPIOX_0 */
+ "PIN_18", /* GPIOX_1 */
+ "PIN_22", /* GPIOX_2 */
+ "PIN_11", /* GPIOX_3 */
+ "PIN_13", /* GPIOX_4 */
+ "PIN_33", /* GPIOX_5 */
+ "PIN_35", /* GPIOX_6 */
+ "PIN_15", /* GPIOX_7 */
+ "PIN_19", /* GPIOX_8 */
+ "PIN_21", /* GPIOX_9 */
+ "PIN_24", /* GPIOX_10 */
+ "PIN_23", /* GPIOX_11 */
+ "PIN_8", /* GPIOX_12 */
+ "PIN_10", /* GPIOX_13 */
+ "PIN_29", /* GPIOX_14 */
+ "PIN_31", /* GPIOX_15 */
+ "PIN_12", /* GPIOX_16 */
+ "PIN_3", /* GPIOX_17 */
+ "PIN_5", /* GPIOX_18 */
+ "PIN_36"; /* GPIOX_19 */
/*
* WARNING: The USB Hub on the Odroid-N2 needs a reset signal
* to be turned high in order to be detected by the USB Controller
* This signal should be handled by a USB specific power sequence
* in order to reset the Hub when USB bus is powered down.
*/
- usb-hub {
+ hog-0 {
gpio-hog;
gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
output-high;
linux,rc-map-name = "rc-odroid";
};
+&i2c3 {
+ status = "okay";
+ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+ pinctrl-names = "default";
+
+ rtc: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ wakeup-source;
+ };
+};
+
&pwm_ab {
pinctrl-0 = <&pwm_a_e_pins>;
pinctrl-names = "default";
status = "okay";
};
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
/* SD card */
&sd_emmc_b {
status = "okay";
max-speed = <1000>;
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
interrupt-parent = <&gpio_intc>;
};
};
};
+
+&mali {
+ dma-coherent;
+};
sound {
compatible = "amlogic,gx-sound-card";
- model = "GXL-LIBRETECH-S9XX-PC";
+ model = "LIBRETECH-PC";
audio-aux-devs = <&dio2133>;
audio-widgets = "Speaker", "7J4-14 LEFT",
"Speaker", "7J4-11 RIGHT";
sound {
compatible = "amlogic,gx-sound-card";
- model = "GX-P230-Q200";
+ model = "P230-Q200";
audio-aux-devs = <&dio2133>;
audio-widgets = "Line", "Lineout";
audio-routing = "AU2 INL", "ACODEC LOLP",
*/
/ {
+ /* Keep HW order from U-boot */
+ aliases {
+ /delete-property/ mmc0;
+ /delete-property/ mmc1;
+ /delete-property/ mmc2;
+ };
+
soc {
u-boot,dm-pre-reloc;
};
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ mmc0 = &sd_emmc_b; /* SD card */
+ mmc1 = &sd_emmc_c; /* eMMC */
+ mmc2 = &sd_emmc_a; /* SDIO */
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
reg = <0x0 0x84c0 0x0 0x18>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
+ fifo-size = <128>;
};
uart_B: serial@84dc {
#include "meson-gxbb.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/meson-aiu.h>
/ {
compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
};
};
};
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "NANOPI-K2";
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&aiu {
+ status = "okay";
};
&cec_AO {
reg = <0>;
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
#include "meson-gxbb.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/meson-aiu.h>
/ {
compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
};
};
};
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "ODROID-C2";
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&aiu {
+ status = "okay";
};
&cec_AO {
reg = <0>;
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
* This signal should be handled by a USB specific power sequence
* in order to reset the Hub when USB bus is powered down.
*/
- usb-hub {
+ hog-0 {
gpio-hog;
gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
output-high;
sound {
compatible = "amlogic,gx-sound-card";
- model = "GXL-LIBRETECH-S805X-AC";
+ model = "LIBRETECH-AC";
audio-widgets = "Speaker", "9J5-3 LEFT",
"Speaker", "9J5-2 RIGHT";
audio-routing = "9J5-3 LEFT", "ACODEC LOLN",
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Vyacheslav Bocharov <adeep@lexina.in>
+ * Copyright (c) 2020 JetHome
+ * Author: Aleksandr Kazantsev <ak@tvip.ru>
+ * Author: Alexey Shevelkin <ash@tvip.ru>
+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
+ */
+
+/dts-v1/;
+
+#include "meson-gxl.dtsi"
+
+/ {
+ compatible = "jethome,jethub-j80", "amlogic,s905w", "amlogic,meson-gxl";
+ model = "JetHome JetHub J80";
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ reserved-memory {
+ linux,cma {
+ size = <0x0 0x1000000>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart_AO; /* Console */
+ serial1 = &uart_A; /* Bluetooth */
+ serial2 = &uart_AO_B; /* Wireless module 1 */
+ serial3 = &uart_C; /* Wireless module 2 */
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+&efuse {
+ bt_mac: bt_mac@6 {
+ reg = <0x6 0x6>;
+ };
+
+ wifi_mac: wifi_mac@C {
+ reg = <0xc 0x6>;
+ };
+};
+
+&sn {
+ reg = <0x32 0x20>;
+};
+
+ð_mac {
+ reg = <0x0 0x6>;
+};
+
+&bid {
+ reg = <0x12 0x20>;
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+
+ non-removable;
+ disable-wp;
+
+ /* WiFi firmware requires power to be kept while in suspend */
+ keep-power-in-suspend;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* Console UART */
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+/* S905W only has access to its internal PHY */
+ðmac {
+ status = "okay";
+ phy-mode = "rmii";
+ phy-handle = <&internal_phy>;
+};
+
+&internal_phy {
+ status = "okay";
+ pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>;
+ pinctrl-names = "default";
+};
+
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+};
+
+&uart_C {
+ status = "okay";
+ pinctrl-0 = <&uart_c_pins>;
+ pinctrl-names = "default";
+};
+
+&uart_AO_B {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_b_pins>, <&uart_ao_b_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+};
+
+&i2c_B {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_b_pins>;
+
+ pcf8563: pcf8563@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ status = "okay";
+ };
+};
/dts-v1/;
-#include <dt-bindings/input/input.h>
-
#include "meson-gxl-s905x-p212.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/sound/meson-aiu.h>
/ {
compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl";
};
};
- pwmleds {
+ led-controller {
compatible = "pwm-leds";
- power {
+ led-1 {
label = "vim:red:power";
pwms = <&pwm_AO_ab 1 7812500 0>;
max-brightness = <255>;
};
};
};
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "KHADAS-VIM";
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&aiu {
+ status = "okay";
};
&cec_AO {
pinctrl-names = "default";
rtc: rtc@51 {
- /* has to be enabled manually when a battery is connected: */
- status = "disabled";
+ status = "okay";
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
regulator-always-on;
};
-
vcck: regulator-vcck {
compatible = "regulator-fixed";
regulator-name = "VCCK";
regulator-always-on;
};
-
vddio_card: regulator-vddio-card {
compatible = "regulator-gpio";
regulator-name = "VDDIO_CARD";
sound {
compatible = "amlogic,gx-sound-card";
- model = "GXL-LIBRETECH-S905X-CC-V2";
+ model = "LIBRETECH-CC-V2";
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
};
};
-
&aiu {
status = "okay";
};
hdmi-phandle = <&hdmi_tx>;
};
-
ðmac {
status = "okay";
};
sound {
compatible = "amlogic,gx-sound-card";
- model = "GXL-LIBRETECH-S905X-CC";
+ model = "LIBRETECH-CC";
audio-aux-devs = <&dio2133>;
audio-widgets = "Line", "Lineout";
audio-routing = "AU2 INL", "ACODEC LOLN",
/dts-v1/;
-#include <dt-bindings/input/input.h>
-
#include "meson-gxm.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/sound/meson-aiu.h>
/ {
compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
};
};
- pwmleds {
+ led-controller {
compatible = "pwm-leds";
- power {
+ led-1 {
label = "vim:red:power";
pwms = <&pwm_AO_ab 1 7812500 0>;
max-brightness = <255>;
clock-frequency = <32768>;
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
};
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "KHADAS-VIM2";
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&aiu {
+ status = "okay";
};
&cec_AO {
hdmi-phandle = <&hdmi_tx>;
};
-
&cpu_cooling_maps {
map0 {
cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>;
reg = <0>;
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
pinctrl-names = "default";
rtc: rtc@51 {
- /* has to be enabled manually when a battery is connected: */
- status = "disabled";
+ status = "okay";
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
#size-cells = <1>;
compatible = "winbond,w25q16", "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <3000000>;
+ spi-max-frequency = <104000000>;
};
};
leds {
compatible = "gpio-leds";
- blue {
+ led-blue {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
};
};
+ cpu0: cpu@0 {
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu1: cpu@1 {
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu2: cpu@2 {
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu3: cpu@3 {
+ capacity-dmips-mhz = <1024>;
+ };
+
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
compatible = "arm,cortex-a53";
reg = <0x0 0x102>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
compatible = "arm,cortex-a53";
reg = <0x0 0x103>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
*/
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/meson-g12a-gpio.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
aliases {
serial0 = &uart_AO;
ethernet0 = ðmac;
+ rtc0 = &rtc;
+ rtc1 = &vrtc;
};
chosen {
compatible = "gpio-leds";
led-white {
- label = "vim3:white:sys";
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_STATUS;
gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
led-red {
- label = "vim3:red";
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
gpios = <&gpio_expander 5 GPIO_ACTIVE_HIGH>;
};
};
sound {
compatible = "amlogic,axg-sound-card";
- model = "G12B-KHADAS-VIM3";
- audio-aux-devs = <&tdmout_a>;
+ model = "KHADAS-VIM3";
+ audio-aux-devs = <&tdmin_a>, <&tdmout_a>;
audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
"TDMOUT_A IN 1", "FRDDR_B OUT 0",
"TDMOUT_A IN 2", "FRDDR_C OUT 0",
- "TDM_A Playback", "TDMOUT_A OUT";
+ "TDM_A Playback", "TDMOUT_A OUT",
+ "TDMIN_A IN 0", "TDM_A Capture",
+ "TDMIN_A IN 3", "TDM_A Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT";
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
sound-dai = <&frddr_c>;
};
- /* 8ch hdmi interface */
dai-link-3 {
+ sound-dai = <&toddr_a>;
+ };
+
+ dai-link-4 {
+ sound-dai = <&toddr_b>;
+ };
+
+ dai-link-5 {
+ sound-dai = <&toddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-6 {
sound-dai = <&tdmif_a>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
};
/* hdmi glue */
- dai-link-4 {
+ dai-link-7 {
sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
codec {
};
ðmac {
- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
- pinctrl-names = "default";
- status = "okay";
- phy-mode = "rgmii";
- phy-handle = <&external_phy>;
- amlogic,tx-delay-ns = <2>;
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&external_phy>;
+ amlogic,tx-delay-ns = <2>;
};
&frddr_a {
#gpio-cells = <2>;
};
- rtc@51 {
+ rtc: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
};
&pwm_ef {
- status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
};
&saradc {
};
};
-
&tdmif_a {
status = "okay";
};
+&tdmin_a {
+ status = "okay";
+};
+
&tdmout_a {
status = "okay";
};
+&toddr_a {
+ status = "okay";
+};
+
+&toddr_b {
+ status = "okay";
+};
+
+&toddr_c {
+ status = "okay";
+};
+
&tohdmitx {
status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-sm1-u-boot.dtsi"
+
+ðmac {
+ snps,reset-gpio = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1.dtsi"
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-toacodec.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "bananapi,bpi-m5", "amlogic,sm1";
+ model = "Banana Pi BPI-M5";
+
+ adc_keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 2>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+
+ key {
+ label = "SW3";
+ linux,code = <BTN_3>;
+ press-threshold-microvolt = <1700000>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ /* TOFIX: handle CVBS_DET on SARADC channel 0 */
+ cvbs-connector {
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key {
+ label = "SW1";
+ linux,code = <BTN_1>;
+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio_intc>;
+ interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+ };
+
+ blue {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ emmc_1v8: regulator-emmc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "EMMC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ dc_in: regulator-dc_in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vddio_c: regulator-vddio_c {
+ compatible = "regulator-gpio";
+ regulator-name = "VDDIO_C";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+
+ gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>;
+ gpios-states = <1>;
+
+ states = <1800000 0>,
+ <3300000 1>;
+ };
+
+ tflash_vdd: regulator-tflash_vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "TFLASH_VDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ vddao_1v8: regulator-vddao_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ vddcpu: regulator-vddcpu {
+ /*
+ * SY8120B1ABC DC/DC Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU";
+ regulator-min-microvolt = <690000>;
+ regulator-max-microvolt = <1050000>;
+
+ vin-supply = <&dc_in>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* USB Hub Power Enable */
+ vl_pwr_en: regulator-vl_pwr_en {
+ compatible = "regulator-fixed";
+ regulator-name = "VL_PWR_EN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_in>;
+
+ gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "BPI-M5";
+ audio-widgets = "Line", "Lineout";
+ audio-aux-devs = <&tdmout_b>, <&tdmout_c>,
+ <&tdmin_a>, <&tdmin_b>, <&tdmin_c>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT",
+ "TDMOUT_C IN 0", "FRDDR_A OUT 2",
+ "TDMOUT_C IN 1", "FRDDR_B OUT 2",
+ "TDMOUT_C IN 2", "FRDDR_C OUT 2",
+ "TDM_C Playback", "TDMOUT_C OUT",
+ "TDMIN_A IN 4", "TDM_B Loopback",
+ "TDMIN_B IN 4", "TDM_B Loopback",
+ "TDMIN_C IN 4", "TDM_B Loopback",
+ "TDMIN_A IN 5", "TDM_C Loopback",
+ "TDMIN_B IN 5", "TDM_C Loopback",
+ "TDMIN_C IN 5", "TDM_C Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT",
+ "TODDR_A IN 1", "TDMIN_B OUT",
+ "TODDR_B IN 1", "TDMIN_B OUT",
+ "TODDR_C IN 1", "TDMIN_B OUT",
+ "TODDR_A IN 2", "TDMIN_C OUT",
+ "TODDR_B IN 2", "TDMIN_C OUT",
+ "TODDR_C IN 2", "TDMIN_C OUT",
+ "Lineout", "ACODEC LOLP",
+ "Lineout", "ACODEC LORP";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ dai-link-3 {
+ sound-dai = <&toddr_a>;
+ };
+
+ dai-link-4 {
+ sound-dai = <&toddr_b>;
+ };
+
+ dai-link-5 {
+ sound-dai = <&toddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-6 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+
+ codec-1 {
+ sound-dai = <&toacodec TOACODEC_IN_B>;
+ };
+ };
+
+ /* i2s jack output interface */
+ dai-link-7 {
+ sound-dai = <&tdmif_c>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>;
+ };
+
+ codec-1 {
+ sound-dai = <&toacodec TOACODEC_IN_C>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-8 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+
+ /* acodec glue */
+ dai-link-9 {
+ sound-dai = <&toacodec TOACODEC_OUT>;
+
+ codec {
+ sound-dai = <&acodec>;
+ };
+ };
+ };
+};
+
+&acodec {
+ AVDD-supply = <&vddao_1v8>;
+ status = "okay";
+};
+
+&arb {
+ status = "okay";
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU1_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu2 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU2_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu3 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU3_CLK>;
+ clock-latency = <50000>;
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+&ext_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_14 */
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+ðmac {
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy-mode = "rgmii-txid";
+ phy-handle = <&external_phy>;
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&gpio {
+ gpio-line-names =
+ /* GPIOZ */
+ "ETH_MDIO", /* GPIOZ_0 */
+ "ETH_MDC", /* GPIOZ_1 */
+ "ETH_RXCLK", /* GPIOZ_2 */
+ "ETH_RX_DV", /* GPIOZ_3 */
+ "ETH_RXD0", /* GPIOZ_4 */
+ "ETH_RXD1", /* GPIOZ_5 */
+ "ETH_RXD2", /* GPIOZ_6 */
+ "ETH_RXD3", /* GPIOZ_7 */
+ "ETH_TXCLK", /* GPIOZ_8 */
+ "ETH_TXEN", /* GPIOZ_9 */
+ "ETH_TXD0", /* GPIOZ_10 */
+ "ETH_TXD1", /* GPIOZ_11 */
+ "ETH_TXD2", /* GPIOZ_12 */
+ "ETH_TXD3", /* GPIOZ_13 */
+ "ETH_INTR", /* GPIOZ_14 */
+ "ETH_NRST", /* GPIOZ_15 */
+ /* GPIOH */
+ "HDMI_SDA", /* GPIOH_0 */
+ "HDMI_SCL", /* GPIOH_1 */
+ "HDMI_HPD", /* GPIOH_2 */
+ "HDMI_CEC", /* GPIOH_3 */
+ "VL-RST_N", /* GPIOH_4 */
+ "CON1-P36", /* GPIOH_5 */
+ "VL-PWREN", /* GPIOH_6 */
+ "WiFi_3V3_1V8", /* GPIOH_7 */
+ "TFLASH_VDD_EN", /* GPIOH_8 */
+ /* BOOT */
+ "eMMC_D0", /* BOOT_0 */
+ "eMMC_D1", /* BOOT_1 */
+ "eMMC_D2", /* BOOT_2 */
+ "eMMC_D3", /* BOOT_3 */
+ "eMMC_D4", /* BOOT_4 */
+ "eMMC_D5", /* BOOT_5 */
+ "eMMC_D6", /* BOOT_6 */
+ "eMMC_D7", /* BOOT_7 */
+ "eMMC_CLK", /* BOOT_8 */
+ "",
+ "eMMC_CMD", /* BOOT_10 */
+ "",
+ "eMMC_RST#", /* BOOT_12 */
+ "eMMC_DS", /* BOOT_13 */
+ /* GPIOC */
+ "SD_D0_B", /* GPIOC_0 */
+ "SD_D1_B", /* GPIOC_1 */
+ "SD_D2_B", /* GPIOC_2 */
+ "SD_D3_B", /* GPIOC_3 */
+ "SD_CLK_B", /* GPIOC_4 */
+ "SD_CMD_B", /* GPIOC_5 */
+ "CARD_EN_DET", /* GPIOC_6 */
+ "",
+ /* GPIOA */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "",
+ "CON1-P27", /* GPIOA_14 */
+ "CON1-P28", /* GPIOA_15 */
+ /* GPIOX */
+ "CON1-P16", /* GPIOX_0 */
+ "CON1-P18", /* GPIOX_1 */
+ "CON1-P22", /* GPIOX_2 */
+ "CON1-P11", /* GPIOX_3 */
+ "CON1-P13", /* GPIOX_4 */
+ "CON1-P07", /* GPIOX_5 */
+ "CON1-P33", /* GPIOX_6 */
+ "CON1-P15", /* GPIOX_7 */
+ "CON1-P19", /* GPIOX_8 */
+ "CON1-P21", /* GPIOX_9 */
+ "CON1-P24", /* GPIOX_10 */
+ "CON1-P23", /* GPIOX_11 */
+ "CON1-P08", /* GPIOX_12 */
+ "CON1-P10", /* GPIOX_13 */
+ "CON1-P29", /* GPIOX_14 */
+ "CON1-P31", /* GPIOX_15 */
+ "CON1-P26", /* GPIOX_16 */
+ "CON1-P03", /* GPIOX_17 */
+ "CON1-P05", /* GPIOX_18 */
+ "CON1-P32"; /* GPIOX_19 */
+
+ /*
+ * WARNING: The USB Hub on the BPI-M5 needs a reset signal
+ * to be turned high in order to be detected by the USB Controller
+ * This signal should be handled by a USB specific power sequence
+ * in order to reset the Hub when USB bus is powered down.
+ */
+ usb-hub {
+ gpio-hog;
+ gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-hub-reset";
+ };
+};
+
+&gpio_ao {
+ gpio-line-names =
+ /* GPIOAO */
+ "DEBUG TX", /* GPIOAO_0 */
+ "DEBUG RX", /* GPIOAO_1 */
+ "SYS_LED2", /* GPIOAO_2 */
+ "UPDATE_KEY", /* GPIOAO_3 */
+ "CON1-P40", /* GPIOAO_4 */
+ "IR_IN", /* GPIOAO_5 */
+ "TF_3V3N_1V8_EN", /* GPIOAO_6 */
+ "CON1-P35", /* GPIOAO_7 */
+ "CON1-P12", /* GPIOAO_8 */
+ "CON1-P37", /* GPIOAO_9 */
+ "CON1-P38", /* GPIOAO_10 */
+ "SYS_LED", /* GPIOAO_11 */
+ /* GPIOE */
+ "VDDEE_PWM", /* GPIOE_0 */
+ "VDDCPU_PWM", /* GPIOE_1 */
+ "TF_PWR_EN"; /* GPIOE_2 */
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&dc_in>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ /* TOFIX: SD card is barely usable in SDR modes */
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&tflash_vdd>;
+ vqmmc-supply = <&vddio_c>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&emmc_1v8>;
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmif_c {
+ status = "okay";
+};
+
+&tdmin_a {
+ status = "okay";
+};
+
+&tdmin_b {
+ status = "okay";
+};
+
+&tdmin_c {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tdmout_c {
+ status = "okay";
+};
+
+&toacodec {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&toddr_a {
+ status = "okay";
+};
+
+&toddr_b {
+ status = "okay";
+};
+
+&toddr_c {
+ status = "okay";
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb2_phy0 {
+ phy-supply = <&dc_in>;
+};
+
+&usb2_phy1 {
+ /* Enable the hub which is connected to this port */
+ phy-supply = <&vl_pwr_en>;
+};
regulator-boot-on;
regulator-always-on;
};
+
+ sound {
+ model = "G12B-KHADAS-VIM3L";
+ audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
+ "TDMOUT_A IN 1", "FRDDR_B OUT 0",
+ "TDMOUT_A IN 2", "FRDDR_C OUT 0",
+ "TDM_A Playback", "TDMOUT_A OUT",
+ "TDMIN_A IN 0", "TDM_A Capture",
+ "TDMIN_A IN 13", "TDM_A Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT";
+ };
};
&cpu0 {
status = "okay";
};
-&sd_emmc_a {
- sd-uhs-sdr50;
-};
-
&usb {
phys = <&usb2_phy0>, <&usb2_phy1>;
phy-names = "usb2-phy0", "usb2-phy1";
};
*/
+&sd_emmc_a {
+ sd-uhs-sdr50;
+};
/dts-v1/;
-#include "meson-sm1.dtsi"
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+#include "meson-sm1-odroid.dtsi"
/ {
compatible = "hardkernel,odroid-c4", "amlogic,sm1";
model = "Hardkernel ODROID-C4";
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
leds {
compatible = "gpio-leds";
};
};
- tflash_vdd: regulator-tflash_vdd {
- compatible = "regulator-fixed";
-
- regulator-name = "TFLASH_VDD";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- };
-
- tf_io: gpio-regulator-tf_io {
- compatible = "regulator-gpio";
-
- regulator-name = "TF_IO";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>;
- gpios-states = <0>;
-
- states = <3300000 0>,
- <1800000 1>;
- };
-
- flash_1v8: regulator-flash_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "FLASH_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- main_12v: regulator-main_12v {
- compatible = "regulator-fixed";
- regulator-name = "12V";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- };
-
- vcc_5v: regulator-vcc_5v {
- compatible = "regulator-fixed";
- regulator-name = "5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- vin-supply = <&main_12v>;
- };
-
- vcc_1v8: regulator-vcc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- /* FIXME: actually controlled by VDDCPU_B_EN */
- };
-
- vddcpu: regulator-vddcpu {
- /*
- * MP8756GD Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU";
- regulator-min-microvolt = <721000>;
- regulator-max-microvolt = <1022000>;
-
- vin-supply = <&main_12v>;
-
- pwms = <&pwm_AO_cd 1 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- hub_5v: regulator-hub_5v {
- compatible = "regulator-fixed";
- regulator-name = "HUB_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- /* Connected to the Hub CHIPENABLE, LOW sets low power state */
- gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- usb_pwr_en: regulator-usb_pwr_en {
- compatible = "regulator-fixed";
- regulator-name = "USB_PWR_EN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- /* Connected to the microUSB port power enable */
- gpio = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vddao_1v8: regulator-vddao_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&main_12v>;
- regulator-always-on;
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
sound {
- compatible = "amlogic,axg-sound-card";
- model = "SM1-ODROID-C4";
- audio-aux-devs = <&tdmout_b>;
- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
- "TDMOUT_B IN 1", "FRDDR_B OUT 1",
- "TDMOUT_B IN 2", "FRDDR_C OUT 1",
- "TDM_B Playback", "TDMOUT_B OUT";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- /* 8ch hdmi interface */
- dai-link-3 {
- sound-dai = <&tdmif_b>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
- };
- };
-
- /* hdmi glue */
- dai-link-4 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-};
-
-&arb {
- status = "okay";
-};
-
-&clkc_audio {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU1_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu2 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU2_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu3 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU3_CLK>;
- clock-latency = <50000>;
-};
-
-&ext_mdio {
- external_phy: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
- reg = <0>;
- max-speed = <1000>;
-
- interrupt-parent = <&gpio_intc>;
- /* MAC_INTR on GPIOZ_14 */
- interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ model = "ODROID-C4";
};
};
-ðmac {
- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
- pinctrl-names = "default";
- status = "okay";
- phy-mode = "rgmii";
- phy-handle = <&external_phy>;
- amlogic,tx-delay-ns = <2>;
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
&gpio {
- gpio-line-names =
- /* GPIOZ */
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- /* GPIOH */
- "", "", "", "", "",
- "PIN_36", /* GPIOH_5 */
- "PIN_26", /* GPIOH_6 */
- "PIN_32", /* GPIOH_7 */
- "",
- /* BOOT */
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- /* GPIOC */
- "", "", "", "", "", "", "", "",
- /* GPIOA */
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "",
- "PIN_27", /* GPIOA_14 */
- "PIN_28", /* GPIOA_15 */
- /* GPIOX */
- "PIN_16", /* GPIOX_0 */
- "PIN_18", /* GPIOX_1 */
- "PIN_22", /* GPIOX_2 */
- "PIN_11", /* GPIOX_3 */
- "PIN_13", /* GPIOX_4 */
- "PIN_7", /* GPIOX_5 */
- "PIN_33", /* GPIOX_6 */
- "PIN_15", /* GPIOX_7 */
- "PIN_19", /* GPIOX_8 */
- "PIN_21", /* GPIOX_9 */
- "PIN_24", /* GPIOX_10 */
- "PIN_23", /* GPIOX_11 */
- "PIN_8", /* GPIOX_12 */
- "PIN_10", /* GPIOX_13 */
- "PIN_29", /* GPIOX_14 */
- "PIN_31", /* GPIOX_15 */
- "PIN_12", /* GPIOX_16 */
- "PIN_3", /* GPIOX_17 */
- "PIN_5", /* GPIOX_18 */
- "PIN_35"; /* GPIOX_19 */
-
/*
* WARNING: The USB Hub on the Odroid-C4 needs a reset signal
* to be turned high in order to be detected by the USB Controller
* This signal should be handled by a USB specific power sequence
* in order to reset the Hub when USB bus is powered down.
*/
- usb-hub {
+ hog-0 {
gpio-hog;
gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
output-high;
};
};
-&gpio_ao {
- gpio-line-names =
- /* GPIOAO */
- "", "", "", "",
- "PIN_47", /* GPIOAO_4 */
- "", "",
- "PIN_45", /* GPIOAO_7 */
- "PIN_46", /* GPIOAO_8 */
- "PIN_44", /* GPIOAO_9 */
- "PIN_42", /* GPIOAO_10 */
- "",
- /* GPIOE */
- "", "", "";
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&vcc_5v>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
linux,rc-map-name = "rc-odroid";
};
-
-&pwm_AO_cd {
- pinctrl-0 = <&pwm_ao_d_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin1";
- status = "okay";
-};
-
-&saradc {
- status = "okay";
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <200000000>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&tflash_vdd>;
- vqmmc-supply = <&tf_io>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&flash_1v8>;
-};
-
-&tdmif_b {
- status = "okay";
-};
-
-&tdmout_b {
- status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
- vbus-supply = <&usb_pwr_en>;
-};
-
-&usb2_phy0 {
- phy-supply = <&vcc_5v>;
-};
-
-&usb2_phy1 {
- /* Enable the hub which is connected to this port */
- phy-supply = <&hub_5v>;
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-sm1-u-boot.dtsi"
+
+ðmac {
+ snps,reset-gpio = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+};
+
+/* SARADC is needed for proper board variant detection */
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+&tflash_vdd {
+ gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Dongjin Kim <tobetter@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-odroid.dtsi"
+
+/ {
+ compatible = "hardkernel,odroid-hc4", "amlogic,sm1";
+ model = "Hardkernel ODROID-HC4";
+
+ aliases {
+ rtc0 = &rtc;
+ rtc1 = &vrtc;
+ };
+
+ fan0: pwm-fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+ cooling-min-state = <0>;
+ cooling-max-state = <3>;
+ cooling-levels = <0 120 170 220>;
+ pwms = <&pwm_cd 1 40000 0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ panic-indicator;
+ };
+
+ led-red {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ /* Powers the SATA Disk 0 regulator, which is enabled when a disk load is detected */
+ p12v_0: regulator-p12v_0 {
+ compatible = "regulator-fixed";
+ regulator-name = "P12V_0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <&main_12v>;
+
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ /* Powers the SATA Disk 1 regulator, which is enabled when a disk load is detected */
+ p12v_1: regulator-p12v_1 {
+ compatible = "regulator-fixed";
+ regulator-name = "P12V_1";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <&main_12v>;
+
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ sound {
+ model = "ODROID-HC4";
+ };
+};
+
+&cpu_thermal {
+ cooling-maps {
+ map {
+ trip = <&cpu_passive>;
+ cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&ir {
+ linux,rc-map-name = "rc-odroid";
+};
+
+&i2c2 {
+ status = "okay";
+ pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>;
+ pinctrl-names = "default";
+
+ rtc: rtc@51 {
+ status = "okay";
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ wakeup-source;
+ };
+};
+
+&pcie {
+ status = "okay";
+ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
+};
+
+&pwm_cd {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_d_x6_pins>;
+};
+
+&sd_emmc_c {
+ status = "disabled";
+};
+
+&spifc {
+ status = "okay";
+ pinctrl-0 = <&nor_pins>;
+ pinctrl-names = "default";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ };
+};
+
+&usb {
+ phys = <&usb2_phy1>;
+ phy-names = "usb2-phy1";
+};
+
+&usb2_phy0 {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Dongjin Kim <tobetter@gmail.com>
+ */
+
+#include "meson-sm1.dtsi"
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ tflash_vdd: regulator-tflash_vdd {
+ compatible = "regulator-fixed";
+
+ regulator-name = "TFLASH_VDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ tf_io: gpio-regulator-tf_io {
+ compatible = "regulator-gpio";
+
+ regulator-name = "TF_IO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_5v>;
+
+ enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+
+ gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE>;
+ gpios-states = <0>;
+
+ states = <3300000 0>,
+ <1800000 1>;
+ };
+
+ flash_1v8: regulator-flash_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "FLASH_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ main_12v: regulator-main_12v {
+ compatible = "regulator-fixed";
+ regulator-name = "12V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ };
+
+ vcc_5v: regulator-vcc_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ vin-supply = <&main_12v>;
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ };
+
+ vcc_1v8: regulator-vcc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ /* FIXME: actually controlled by VDDCPU_B_EN */
+ };
+
+ vddcpu: regulator-vddcpu {
+ /*
+ * MP8756GD Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU";
+ regulator-min-microvolt = <721000>;
+ regulator-max-microvolt = <1022000>;
+
+ vin-supply = <&main_12v>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ usb_pwr_en: regulator-usb_pwr_en {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_PWR_EN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+
+ /* Connected to the microUSB port power enable */
+ gpio = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vddao_1v8: regulator-vddao_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&main_12v>;
+ regulator-always-on;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU1_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu2 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU2_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu3 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU3_CLK>;
+ clock-latency = <50000>;
+};
+
+&ext_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_14 */
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+ðmac {
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&external_phy>;
+ amlogic,tx-delay-ns = <2>;
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&gpio {
+ gpio-line-names =
+ /* GPIOZ */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* GPIOH */
+ "", "", "", "", "",
+ "PIN_36", /* GPIOH_5 */
+ "PIN_26", /* GPIOH_6 */
+ "PIN_32", /* GPIOH_7 */
+ "",
+ /* BOOT */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* GPIOC */
+ "", "", "", "", "", "", "", "",
+ /* GPIOA */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "",
+ "PIN_27", /* GPIOA_14 */
+ "PIN_28", /* GPIOA_15 */
+ /* GPIOX */
+ "PIN_16", /* GPIOX_0 */
+ "PIN_18", /* GPIOX_1 */
+ "PIN_22", /* GPIOX_2 */
+ "PIN_11", /* GPIOX_3 */
+ "PIN_13", /* GPIOX_4 */
+ "PIN_7", /* GPIOX_5 */
+ "PIN_33", /* GPIOX_6 */
+ "PIN_15", /* GPIOX_7 */
+ "PIN_19", /* GPIOX_8 */
+ "PIN_21", /* GPIOX_9 */
+ "PIN_24", /* GPIOX_10 */
+ "PIN_23", /* GPIOX_11 */
+ "PIN_8", /* GPIOX_12 */
+ "PIN_10", /* GPIOX_13 */
+ "PIN_29", /* GPIOX_14 */
+ "PIN_31", /* GPIOX_15 */
+ "PIN_12", /* GPIOX_16 */
+ "PIN_3", /* GPIOX_17 */
+ "PIN_5", /* GPIOX_18 */
+ "PIN_35"; /* GPIOX_19 */
+};
+
+&gpio_ao {
+ gpio-line-names =
+ /* GPIOAO */
+ "", "", "", "",
+ "PIN_47", /* GPIOAO_4 */
+ "", "",
+ "PIN_45", /* GPIOAO_7 */
+ "PIN_46", /* GPIOAO_8 */
+ "PIN_44", /* GPIOAO_9 */
+ "PIN_42", /* GPIOAO_10 */
+ "",
+ /* GPIOE */
+ "", "", "";
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&vcc_5v>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <200000000>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&tflash_vdd>;
+ vqmmc-supply = <&tf_io>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&flash_1v8>;
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+ vbus-supply = <&usb_pwr_en>;
+};
+
+&usb2_phy0 {
+ phy-supply = <&vcc_5v>;
+};
+
};
};
- leds {
+ led-controller-1 {
compatible = "gpio-leds";
- led-bluetooth {
+ led-1 {
label = "sei610:blue:bt";
gpios = <&gpio GPIOC_7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
default-state = "off";
};
};
- pwmleds {
+ led-controller-2 {
compatible = "pwm-leds";
- power {
+ led-2 {
label = "sei610:red:power";
pwms = <&pwm_AO_ab 0 30518 0>;
max-brightness = <255>;
sound {
compatible = "amlogic,axg-sound-card";
- model = "SM1-SEI610";
+ model = "SEI610";
audio-aux-devs = <&tdmout_a>, <&tdmout_b>,
<&tdmin_a>, <&tdmin_b>;
audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
opp-microvolt = <790000>;
};
- opp-1512000000 {
+ opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <800000>;
};
status = "disabled";
};
+ toacodec: audio-controller@740 {
+ compatible = "amlogic,sm1-toacodec",
+ "amlogic,g12a-toacodec";
+ reg = <0x0 0x740 0x0 0x4>;
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "TOACODEC";
+ resets = <&clkc_audio AUD_RESET_TOACODEC>;
+ status = "disabled";
+ };
+
tohdmitx: audio-controller@744 {
compatible = "amlogic,sm1-tohdmitx",
"amlogic,g12a-tohdmitx";
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
clock-names = "clk_sfc", "hclk_sfc";
pinctrl-names = "default";
- pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus4>;
+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
power-domains = <&power PX30_PD_MMC_NAND>;
status = "disabled";
};
<1 RK_PA1 3 &pcfg_pull_none>;
};
- sfc_cs: sfc-cs {
+ sfc_cs0: sfc-cs0 {
rockchip,pins =
<1 RK_PA4 3 &pcfg_pull_none>;
};
};
};
+/* U-Boot clk driver for px30 cannot set GPU_CLK */
&cru {
u-boot,dm-pre-reloc;
+ assigned-clocks = <&cru PLL_NPLL>,
+ <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+ <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
+ <&cru PCLK_BUS_PRE>, <&cru PLL_CPLL>;
+
+ assigned-clock-rates = <1188000000>,
+ <200000000>, <200000000>,
+ <150000000>, <150000000>,
+ <100000000>, <17000000>;
};
&dmc {
u-boot,dm-pre-reloc;
};
-&spi_flash {
+&{/sfc@ff3a0000/flash@0} {
u-boot,dm-pre-reloc;
};
};
&sfc {
+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
+ pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
status = "okay";
- spi_flash: xt25f128b@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <108000000>;
spi-rx-bus-width = <2>;
- spi-tx-bus-width = <2>;
+ spi-tx-bus-width = <1>;
};
};
status = "disabled";
};
+ pwm0: pwm@f802c000 {
+ compatible = "atmel,sama5d2-pwm";
+ reg = <0xf802c000 0x4000>;
+ clocks = <&pwm_clk>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
rstc@f8048000 {
compatible = "atmel,sama5d3-rstc";
reg = <0xf8048000 0x10>;
clocks = <&rcc 1 CLK_I2C1>;
#address-cells = <1>;
#size-cells = <0>;
+ i2c-analog-filter;
status = "disabled";
};
clocks = <&rcc 1 CLK_I2C2>;
#address-cells = <1>;
#size-cells = <0>;
+ i2c-analog-filter;
status = "disabled";
};
clocks = <&rcc 1 CLK_I2C3>;
#address-cells = <1>;
#size-cells = <0>;
+ i2c-analog-filter;
status = "disabled";
};
clocks = <&rcc 1 CLK_I2C4>;
#address-cells = <1>;
#size-cells = <0>;
+ i2c-analog-filter;
status = "disabled";
};
<32>;
resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
clocks = <&rcc I2C1_CK>;
+ i2c-analog-filter;
status = "disabled";
};
<34>;
resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
clocks = <&rcc I2C2_CK>;
+ i2c-analog-filter;
status = "disabled";
};
<73>;
resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
clocks = <&rcc I2C3_CK>;
+ i2c-analog-filter;
status = "disabled";
};
<96>;
resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
clocks = <&rcc I2C4_CK>;
+ i2c-analog-filter;
status = "disabled";
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Chukun Pan <amadeus@jmu.edu.cn>
+ *
+ * Based on sun50i-h5-nanopi-neo-plus2.dts, which is:
+ * Copyright (C) 2017 Antony Antony <antony@phenome.org>
+ * Copyright (C) 2016 ARM Ltd.
+ */
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "FriendlyARM NanoPi R1S H5";
+ compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5";
+
+ aliases {
+ ethernet0 = &emac;
+ ethernet1 = &rtl8189etv;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-2 {
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ r-gpio-keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_usb0_vbus: usb0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+ status = "okay";
+ };
+
+ vdd_cpux: gpio-regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-cpux";
+ regulator-type = "voltage";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <50>; /* 4ms */
+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0x1>;
+ states = <1100000 0x0>, <1300000 0x1>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpux>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "microchip,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ vqmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ rtl8189etv: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ /* USB Type-A port's VBUS is always on */
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ status = "okay";
+};
#define CM_CLKSEL_DPLL_N_SHIFT 0
#define CM_CLKSEL_DPLL_N_MASK 0x7F
+/* CM_SSC_DELTAM_DPLL */
+#define CM_SSC_DELTAM_DPLL_FRAC_SHIFT 0
+#define CM_SSC_DELTAM_DPLL_FRAC_MASK GENMASK(17, 0)
+#define CM_SSC_DELTAM_DPLL_INT_SHIFT 18
+#define CM_SSC_DELTAM_DPLL_INT_MASK GENMASK(19, 18)
+
+/* CM_SSC_MODFREQ_DPLL */
+#define CM_SSC_MODFREQ_DPLL_MANT_SHIFT 0
+#define CM_SSC_MODFREQ_DPLL_MANT_MASK GENMASK(6, 0)
+#define CM_SSC_MODFREQ_DPLL_EXP_SHIFT 7
+#define CM_SSC_MODFREQ_DPLL_EXP_MASK GENMASK(10, 8)
+
struct dpll_params {
u32 m;
u32 n;
#include <asm/arch/sys_proto.h>
-/* CONFIG_REG_0 */
+/* CFG REG_0 */
#define CFG_REG_0_OFFSET 0xC
#define CFG_REG_ROM_READ_SHIFT 1
#define CFG_REG_ROM_READ_MASK (1 << 1)
#define CFG_REG_ROM_READ_START (1 << 1)
#define CFG_REG_ROM_READ_END (0 << 1)
-/* CONFIG_REG_2 */
+/* CFG REG_2 */
#define CFG_REG_2_OFFSET 0x14
#define CFG_REG_REFCLK_PERIOD_SHIFT 0
#define CFG_REG_REFCLK_PERIOD_MASK (0xFFFF << 0)
#define CFG_REG_REFCLK_PERIOD 0x2EF
-/* CONFIG_REG_8 */
+/* CFG REG_8 */
#define CFG_REG_8_OFFSET 0x2C
#define CFG_IODELAY_UNLOCK_KEY 0x0000AAAA
#define CFG_IODELAY_LOCK_KEY 0x0000AAAB
-/* CONFIG_REG_3/4 */
+/* CFG REG_3/4 */
#define CFG_REG_3_OFFSET 0x18
#define CFG_REG_4_OFFSET 0x1C
#define CFG_REG_DLY_CNT_SHIFT 16
#define APLL_HZ (816 * MHz)
#define GPLL_HZ (1188 * MHz)
#define CPLL_HZ (1000 * MHz)
-#define PPLL_HZ (100 * MHz)
+#define PPLL_HZ (200 * MHz)
/* RK3568 pll id */
enum rk3568_pll_id {
#define GPT_FREE_RUNNING 0xFFFF
/* Timer, HZ specific defines */
-#define CONFIG_STV0991_HZ 1000
-#define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128)
#endif
#define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
/* GPIO bank sizes */
-#define SUNXI_GPIO_A_NR 32
-#define SUNXI_GPIO_B_NR 32
-#define SUNXI_GPIO_C_NR 32
-#define SUNXI_GPIO_D_NR 32
-#define SUNXI_GPIO_E_NR 32
-#define SUNXI_GPIO_F_NR 32
-#define SUNXI_GPIO_G_NR 32
-#define SUNXI_GPIO_H_NR 32
-#define SUNXI_GPIO_I_NR 32
-#define SUNXI_GPIO_L_NR 32
-#define SUNXI_GPIO_M_NR 32
+#define SUNXI_GPIOS_PER_BANK 32
#define SUNXI_GPIO_NEXT(__gpio) \
- ((__gpio##_START) + (__gpio##_NR) + 0)
+ ((__gpio##_START) + SUNXI_GPIOS_PER_BANK)
enum sunxi_gpio_number {
SUNXI_GPIO_A_START = 0,
#define SUNXI_GPA_EMAC 2
#define SUN6I_GPA_GMAC 2
#define SUN7I_GPA_GMAC 5
-#define SUN6I_GPA_SDC2 5
-#define SUN6I_GPA_SDC3 4
#define SUN8I_H3_GPA_UART0 2
#define SUN4I_GPB_PWM 2
#define SUN6I_GPC_SDC3 4
#define SUN50I_GPC_SPI0 4
-#define SUN8I_GPD_SDC1 3
#define SUNXI_GPD_LCD0 2
#define SUNXI_GPD_LVDS0 3
#define SUNXI_GPD_PWM 2
-#define SUN5I_GPE_SDC2 3
#define SUN8I_GPE_TWI2 3
#define SUN50I_GPE_TWI2 3
int sunxi_gpio_get_cfgpin(u32 pin);
int sunxi_gpio_set_drv(u32 pin, u32 val);
int sunxi_gpio_set_pull(u32 pin, u32 val);
-int sunxi_name_to_gpio_bank(const char *name);
int sunxi_name_to_gpio(const char *name);
-#define name_to_gpio(name) sunxi_name_to_gpio(name)
#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
int axp_gpio_init(void);
void pin_mux_mmc(void); /* overridable mmc pinmux setup */
void pin_mux_display(void); /* overridable DISPLAY pinmux setup */
+/*
+ * Helpers for various standard DT update mechanisms.
+ */
+
+#if defined(CONFIG_ARM64)
+void ft_mac_address_setup(void *fdt);
+void ft_carveout_setup(void *fdt, const char *const *nodes,
+ unsigned int count);
+#endif
+
#endif
{
char *commandline = env_get("bootargs");
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_OF_LIBFDT
debug("using: FDT\n");
if (image_setup_linux(images)) {
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
announce_and_cleanup(fake);
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len)
r2 = (unsigned long)images->ft_addr;
else
r2 = gd->bd->bi_boot_params;
return (image_get_image_size((image_header_t *)img_addr)
+ 0x1000 - 1) & ~(0x1000 - 1);
#endif
-#if IMAGE_ENABLE_FIT
+#if CONFIG_IS_ENABLED(FIT)
case IMAGE_FORMAT_FIT:
return (fit_get_size(buf) + 0x1000 - 1) & ~(0x1000 - 1);
#endif
#endif /* CONFIG_CMD_NET */
/*
- * USB/EHCI
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_EHCI_IS_TDI
-#endif /* CONFIG_CMD_USB */
-
-/*
* IDE Support on SATA ports
*/
#ifdef CONFIG_IDE
{ "A113X", 0x25, 0x37, 0xff },
{ "A113D", 0x25, 0x22, 0xff },
{ "S905D2", 0x28, 0x10, 0xf0 },
+ { "S905Y2", 0x28, 0x30, 0xf0 },
{ "S905X2", 0x28, 0x40, 0xf0 },
{ "A311D", 0x29, 0x10, 0xf0 },
{ "S922X", 0x29, 0x40, 0xf0 },
select SPL_DM if SPL
select SPL_DM_SEQ_ALIAS if SPL
select SPL_OF_CONTROL if SPL
+ select SPL_SKIP_LOWLEVEL_INIT
select SPL_SIMPLE_BUS if SPL
select SUPPORT_SPL
select TRANSLATION_OFFSET
int hws_pex_config(const struct serdes_map *serdes_map, u8 count)
{
- u32 pex_idx, tmp, next_busno, first_busno, temp_pex_reg,
- temp_reg, addr, dev_id, ctrl_mode;
enum serdes_type serdes_type;
- u32 idx;
+ u32 idx, tmp;
DEBUG_INIT_FULL_S("\n### hws_pex_config ###\n");
- for (idx = 0; idx < count; idx++) {
- serdes_type = serdes_map[idx].serdes_type;
- /* configuration for PEX only */
- if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
- (serdes_type != PEX2) && (serdes_type != PEX3))
- continue;
-
- if ((serdes_type != PEX0) &&
- ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
- (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
- /* for PEX by4 - relevant for the first port only */
- continue;
- }
-
- pex_idx = serdes_type - PEX0;
- tmp = reg_read(PEX_CAPABILITIES_REG(pex_idx));
- tmp &= ~(0xf << 20);
- tmp |= (0x4 << 20);
- reg_write(PEX_CAPABILITIES_REG(pex_idx), tmp);
- }
-
- tmp = reg_read(SOC_CTRL_REG);
+ tmp = reg_read(SOC_CONTROL_REG1);
tmp &= ~0x03;
for (idx = 0; idx < count; idx++) {
}
}
- reg_write(SOC_CTRL_REG, tmp);
-
- /* Support gen1/gen2 */
- DEBUG_INIT_FULL_S("Support gen1/gen2\n");
+ reg_write(SOC_CONTROL_REG1, tmp);
board_pex_config();
- next_busno = 0;
- mdelay(150);
-
- for (idx = 0; idx < count; idx++) {
- serdes_type = serdes_map[idx].serdes_type;
- DEBUG_INIT_FULL_S(" serdes_type=0x");
- DEBUG_INIT_FULL_D(serdes_type, 8);
- DEBUG_INIT_FULL_S("\n");
- DEBUG_INIT_FULL_S(" idx=0x");
- DEBUG_INIT_FULL_D(idx, 8);
- DEBUG_INIT_FULL_S("\n");
-
- /* Configuration for PEX only */
- if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
- (serdes_type != PEX2) && (serdes_type != PEX3))
- continue;
-
- if ((serdes_type != PEX0) &&
- ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
- (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
- /* for PEX by4 - relevant for the first port only */
- continue;
- }
-
- pex_idx = serdes_type - PEX0;
- tmp = reg_read(PEX_DBG_STATUS_REG(pex_idx));
-
- first_busno = next_busno;
- if ((tmp & 0x7f) != 0x7e) {
- DEBUG_INIT_S("PCIe, Idx ");
- DEBUG_INIT_D(pex_idx, 1);
- DEBUG_INIT_S(": detected no link\n");
- continue;
- }
-
- next_busno++;
- temp_pex_reg = reg_read((PEX_CFG_DIRECT_ACCESS
- (pex_idx, PEX_LINK_CAPABILITY_REG)));
- temp_pex_reg &= 0xf;
- if (temp_pex_reg != 0x2)
- continue;
-
- temp_reg = (reg_read(PEX_CFG_DIRECT_ACCESS(
- pex_idx,
- PEX_LINK_CTRL_STAT_REG)) &
- 0xf0000) >> 16;
-
- /* Check if the link established is GEN1 */
- DEBUG_INIT_FULL_S
- ("Checking if the link established is gen1\n");
- if (temp_reg != 0x1)
- continue;
-
- pex_local_bus_num_set(pex_idx, first_busno);
- pex_local_dev_num_set(pex_idx, 1);
- DEBUG_INIT_FULL_S("PCIe, Idx ");
- DEBUG_INIT_FULL_D(pex_idx, 1);
-
- DEBUG_INIT_S(":** Link is Gen1, check the EP capability\n");
- /* link is Gen1, check the EP capability */
- addr = pex_config_read(pex_idx, first_busno, 0, 0, 0x34) & 0xff;
- DEBUG_INIT_FULL_C("pex_config_read: return addr=0x%x", addr, 4);
- if (addr == 0xff) {
- DEBUG_INIT_FULL_C
- ("pex_config_read: return 0xff -->PCIe (%d): Detected No Link.",
- pex_idx, 1);
- continue;
- }
-
- while ((pex_config_read(pex_idx, first_busno, 0, 0, addr)
- & 0xff) != 0x10) {
- addr = (pex_config_read(pex_idx, first_busno, 0,
- 0, addr) & 0xff00) >> 8;
- }
-
- /* Check for Gen2 and above */
- if ((pex_config_read(pex_idx, first_busno, 0, 0,
- addr + 0xc) & 0xf) < 0x2) {
- DEBUG_INIT_S("PCIe, Idx ");
- DEBUG_INIT_D(pex_idx, 1);
- DEBUG_INIT_S(": remains Gen1\n");
- continue;
- }
-
- tmp = reg_read(PEX_LINK_CTRL_STATUS2_REG(pex_idx));
- DEBUG_RD_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
- tmp &= ~(BIT(0) | BIT(1));
- tmp |= BIT(1);
- tmp |= BIT(6); /* Select Deemphasize (-3.5d_b) */
- reg_write(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
- DEBUG_WR_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
-
- tmp = reg_read(PEX_CTRL_REG(pex_idx));
- DEBUG_RD_REG(PEX_CTRL_REG(pex_idx), tmp);
- tmp |= BIT(10);
- reg_write(PEX_CTRL_REG(pex_idx), tmp);
- DEBUG_WR_REG(PEX_CTRL_REG(pex_idx), tmp);
-
- /*
- * We need to wait 10ms before reading the PEX_DBG_STATUS_REG
- * in order not to read the status of the former state
- */
- mdelay(10);
-
- DEBUG_INIT_S("PCIe, Idx ");
- DEBUG_INIT_D(pex_idx, 1);
- DEBUG_INIT_S
- (": Link upgraded to Gen2 based on client capabilities\n");
- }
-
- /* Update pex DEVICE ID */
- ctrl_mode = sys_env_model_get();
-
- for (idx = 0; idx < count; idx++) {
- serdes_type = serdes_map[idx].serdes_type;
- /* configuration for PEX only */
- if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
- (serdes_type != PEX2) && (serdes_type != PEX3))
- continue;
-
- if ((serdes_type != PEX0) &&
- ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
- (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
- /* for PEX by4 - relevant for the first port only */
- continue;
- }
-
- pex_idx = serdes_type - PEX0;
- dev_id = reg_read(PEX_CFG_DIRECT_ACCESS
- (pex_idx, PEX_DEVICE_AND_VENDOR_ID));
- dev_id &= 0xffff;
- dev_id |= ((ctrl_mode << 16) & 0xffff0000);
- reg_write(PEX_CFG_DIRECT_ACCESS
- (pex_idx, PEX_DEVICE_AND_VENDOR_ID), dev_id);
- }
- DEBUG_INIT_FULL_C("Update PEX Device ID ", ctrl_mode, 4);
-
return MV_OK;
}
-
-int pex_local_bus_num_set(u32 pex_if, u32 bus_num)
-{
- u32 pex_status;
-
- DEBUG_INIT_FULL_S("\n### pex_local_bus_num_set ###\n");
-
- if (bus_num >= MAX_PEX_BUSSES) {
- DEBUG_INIT_C("pex_local_bus_num_set: Illegal bus number %d\n",
- bus_num, 4);
- return MV_BAD_PARAM;
- }
-
- pex_status = reg_read(PEX_STATUS_REG(pex_if));
- pex_status &= ~PXSR_PEX_BUS_NUM_MASK;
- pex_status |=
- (bus_num << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK;
- reg_write(PEX_STATUS_REG(pex_if), pex_status);
-
- return MV_OK;
-}
-
-int pex_local_dev_num_set(u32 pex_if, u32 dev_num)
-{
- u32 pex_status;
-
- DEBUG_INIT_FULL_S("\n### pex_local_dev_num_set ###\n");
-
- pex_status = reg_read(PEX_STATUS_REG(pex_if));
- pex_status &= ~PXSR_PEX_DEV_NUM_MASK;
- pex_status |=
- (dev_num << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK;
- reg_write(PEX_STATUS_REG(pex_if), pex_status);
-
- return MV_OK;
-}
-
-/*
- * pex_config_read - Read from configuration space
- *
- * DESCRIPTION:
- * This function performs a 32 bit read from PEX configuration space.
- * It supports both type 0 and type 1 of Configuration Transactions
- * (local and over bridge). In order to read from local bus segment, use
- * bus number retrieved from pex_local_bus_num_get(). Other bus numbers
- * will result configuration transaction of type 1 (over bridge).
- *
- * INPUT:
- * pex_if - PEX interface number.
- * bus - PEX segment bus number.
- * dev - PEX device number.
- * func - Function number.
- * reg_offs - Register offset.
- *
- * OUTPUT:
- * None.
- *
- * RETURN:
- * 32bit register data, 0xffffffff on error
- */
-u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off)
-{
- u32 pex_data = 0;
- u32 local_dev, local_bus;
- u32 pex_status;
-
- pex_status = reg_read(PEX_STATUS_REG(pex_if));
- local_dev =
- ((pex_status & PXSR_PEX_DEV_NUM_MASK) >> PXSR_PEX_DEV_NUM_OFFS);
- local_bus =
- ((pex_status & PXSR_PEX_BUS_NUM_MASK) >> PXSR_PEX_BUS_NUM_OFFS);
-
- /*
- * In PCI Express we have only one device number
- * and this number is the first number we encounter
- * else that the local_dev
- * spec pex define return on config read/write on any device
- */
- if (bus == local_bus) {
- if (local_dev == 0) {
- /*
- * if local dev is 0 then the first number we encounter
- * after 0 is 1
- */
- if ((dev != 1) && (dev != local_dev))
- return MV_ERROR;
- } else {
- /*
- * if local dev is not 0 then the first number we
- * encounter is 0
- */
- if ((dev != 0) && (dev != local_dev))
- return MV_ERROR;
- }
- }
-
- /* Creating PEX address to be passed */
- pex_data = (bus << PXCAR_BUS_NUM_OFFS);
- pex_data |= (dev << PXCAR_DEVICE_NUM_OFFS);
- pex_data |= (func << PXCAR_FUNC_NUM_OFFS);
- /* Legacy register space */
- pex_data |= (reg_off & PXCAR_REG_NUM_MASK);
- /* Extended register space */
- pex_data |= (((reg_off & PXCAR_REAL_EXT_REG_NUM_MASK) >>
- PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS);
- pex_data |= PXCAR_CONFIG_EN;
-
- /* Write the address to the PEX configuration address register */
- reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data);
-
- /*
- * In order to let the PEX controller absorbed the address
- * of the read transaction we perform a validity check that
- * the address was written
- */
- if (pex_data != reg_read(PEX_CFG_ADDR_REG(pex_if)))
- return MV_ERROR;
-
- /* Cleaning Master Abort */
- reg_bit_set(PEX_CFG_DIRECT_ACCESS(pex_if, PEX_STATUS_AND_COMMAND),
- PXSAC_MABORT);
- /* Read the Data returned in the PEX Data register */
- pex_data = reg_read(PEX_CFG_DATA_REG(pex_if));
-
- DEBUG_INIT_FULL_C(" --> ", pex_data, 4);
-
- return pex_data;
-}
#ifndef _CTRL_PEX_H
#define _CTRL_PEX_H
+#include <pci.h>
#include "high_speed_env_spec.h"
-/* Sample at Reset */
-#define MPP_SAMPLE_AT_RESET(id) (0xe4200 + (id * 4))
+/* Direct access to PEX0 Root Port's PCIe Capability structure */
+#define PEX0_RP_PCIE_CFG_OFFSET (0x00080000 + 0x60)
-/* PCI Express Control and Status Registers */
-#define MAX_PEX_BUSSES 256
-
-#define MISC_REGS_OFFSET 0x18200
-#define MV_MISC_REGS_BASE MISC_REGS_OFFSET
-#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4)
-
-#define PEX_IF_REGS_OFFSET(if) ((if) > 0 ? \
- (0x40000 + ((if) - 1) * 0x4000) : \
- 0x80000)
-#define PEX_IF_REGS_BASE(if) (PEX_IF_REGS_OFFSET(if))
-#define PEX_CAPABILITIES_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x60)
-#define PEX_LINK_CTRL_STATUS2_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x90)
-#define PEX_CTRL_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a00)
-#define PEX_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a04)
-#define PEX_DBG_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a64)
-#define PEX_LINK_CAPABILITY_REG 0x6c
-#define PEX_LINK_CTRL_STAT_REG 0x70
-#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */
-#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS)
-#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */
-#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS)
-
-/* PEX_CAPABILITIES_REG fields */
+/* SOC_CONTROL_REG1 fields */
#define PCIE0_ENABLE_OFFS 0
#define PCIE0_ENABLE_MASK (0x1 << PCIE0_ENABLE_OFFS)
#define PCIE1_ENABLE_OFFS 1
#define PCIE3_ENABLE_OFFS 3
#define PCIE4_ENABLE_MASK (0x1 << PCIE3_ENABLE_OFFS)
-/* Controller revision info */
-#define PEX_DEVICE_AND_VENDOR_ID 0x000
-#define PEX_CFG_DIRECT_ACCESS(if, reg) (PEX_IF_REGS_BASE(if) + (reg))
-
-/* PCI Express Configuration Address Register */
-#define PXCAR_REG_NUM_OFFS 2
-#define PXCAR_REG_NUM_MAX 0x3f
-#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << \
- PXCAR_REG_NUM_OFFS)
-#define PXCAR_FUNC_NUM_OFFS 8
-#define PXCAR_FUNC_NUM_MAX 0x7
-#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << \
- PXCAR_FUNC_NUM_OFFS)
-#define PXCAR_DEVICE_NUM_OFFS 11
-#define PXCAR_DEVICE_NUM_MAX 0x1f
-#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << \
- PXCAR_DEVICE_NUM_OFFS)
-#define PXCAR_BUS_NUM_OFFS 16
-#define PXCAR_BUS_NUM_MAX 0xff
-#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << \
- PXCAR_BUS_NUM_OFFS)
-#define PXCAR_EXT_REG_NUM_OFFS 24
-#define PXCAR_EXT_REG_NUM_MAX 0xf
-
-#define PEX_CFG_ADDR_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18f8)
-#define PEX_CFG_DATA_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18fc)
-
-#define PXCAR_REAL_EXT_REG_NUM_OFFS 8
-#define PXCAR_REAL_EXT_REG_NUM_MASK (0xf << PXCAR_REAL_EXT_REG_NUM_OFFS)
-
-#define PXCAR_CONFIG_EN BIT(31)
-#define PEX_STATUS_AND_COMMAND 0x004
-#define PXSAC_MABORT BIT(29) /* Recieved Master Abort */
-
int hws_pex_config(const struct serdes_map *serdes_map, u8 count);
-int pex_local_bus_num_set(u32 pex_if, u32 bus_num);
-int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
-u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off);
-
void board_pex_config(void);
#endif
(serdes_mode == PEX_END_POINT_X1);
pex_idx = serdes_type - PEX0;
- if ((is_pex_by1 == 1) || (serdes_type == PEX0)) {
+ if (serdes_type == PEX0) {
/* For PEX by 4, init only the PEX 0 */
reg_data = reg_read(SOC_CONTROL_REG1);
if (is_pex_by1 == 1)
reg_data &= ~0x4000;
reg_write(SOC_CONTROL_REG1, reg_data);
- reg_data =
- reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
- 0x6c));
- reg_data &= ~0x3f0;
- if (is_pex_by1 == 1)
- reg_data |= 0x10;
- else
- reg_data |= 0x40;
- reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
- reg_data);
-
- reg_data =
- reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
- 0x6c));
- reg_data &= ~0xf;
- reg_data |= 0x2;
- reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
- reg_data);
-
- reg_data =
- reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
- 0x70));
- reg_data &= ~0x40;
- reg_data |= 0x40;
- reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x70),
- reg_data);
+ /*
+ * Set Maximum Link Width to X1 or X4 in Root
+ * Port's PCIe Link Capability register.
+ * This register is read-only but if is not set
+ * correctly then access to PCI config space of
+ * endpoint card behind this Root Port does not
+ * work.
+ */
+ reg_data = reg_read(PEX0_RP_PCIE_CFG_OFFSET +
+ PCI_EXP_LNKCAP);
+ reg_data &= ~PCI_EXP_LNKCAP_MLW;
+ reg_data |= (is_pex_by1 ? 1 : 4) << 4;
+ reg_write(PEX0_RP_PCIE_CFG_OFFSET +
+ PCI_EXP_LNKCAP, reg_data);
}
CHECK_STATUS(mv_seq_exec(serdes_num, PEX_POWER_UP_SEQ));
feature.
endif
-config SUN6I_P2WI
- bool "Allwinner sun6i internal P2WI controller"
- help
- If you say yes to this option, support will be included for the
- P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
- SOCs.
- The P2WI looks like an SMBus controller (which supports only byte
- accesses), except that it only supports one slave device.
- This interface is used to connect to specific PMIC devices (like the
- AXP221).
-
config SUN6I_PRCM
bool
help
in A31 SoC.
config AXP_PMIC_BUS
- bool "Sunxi AXP PMIC bus access helpers"
+ bool
+ select DM_PMIC if DM_I2C
+ select PMIC_AXP if DM_I2C
help
Select this PMIC bus access helpers for Sunxi platform PRCM or other
AXP family PMIC devices.
-config SUN8I_RSB
- bool "Allwinner sunXi Reduced Serial Bus Driver"
- help
- Say y here to enable support for Allwinner's Reduced Serial Bus
- (RSB) support. This controller is responsible for communicating
- with various RSB based devices, such as AXP223, AXP8XX PMICs,
- and AC100/AC200 ICs.
-
config SUNXI_SRAM_ADDRESS
hex
default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
config MACH_SUNXI_H3_H5
bool
- select DM_I2C
select PHY_SUN4I_USB
select SUNXI_DE2
select SUNXI_DRAM_DW
select ARCH_SUPPORT_PSCI
select DRAM_SUN6I
select PHY_SUN4I_USB
- select SUN6I_P2WI
+ select SPL_I2C
select SUN6I_PRCM
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+ select SYS_I2C_SUN6I_P2WI
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
config MACH_SUN7I
select ARCH_SUPPORT_PSCI
select DRAM_SUN8I_A23
select PHY_SUN4I_USB
+ select SPL_I2C
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+ select SYS_I2C_SUN8I_RSB
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
imply CONS_INDEX_5 if !DM_SERIAL
select ARCH_SUPPORT_PSCI
select DRAM_SUN8I_A33
select PHY_SUN4I_USB
+ select SPL_I2C
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+ select SYS_I2C_SUN8I_RSB
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
imply CONS_INDEX_5 if !DM_SERIAL
select CPU_V7A
select DRAM_SUN8I_A83T
select PHY_SUN4I_USB
+ select SPL_I2C
select SUNXI_GEN_SUN6I
select MMC_SUNXI_HAS_NEW_MODE
select MMC_SUNXI_HAS_MODE_SWITCH
select SUPPORT_SPL
+ select SYS_I2C_SUN8I_RSB
config MACH_SUN8I_H3
bool "sun8i (Allwinner H3)"
bool "sun9i (Allwinner A80)"
select CPU_V7A
select DRAM_SUN9I
+ select SPL_I2C
select SUN6I_PRCM
select SUNXI_GEN_SUN6I
- select SUN8I_RSB
select SUPPORT_SPL
config MACH_SUN50I
bool "sun50i (Allwinner A64)"
select ARM64
select SPI
- select DM_I2C
select DM_SPI if SPI
select DM_SPI_FLASH
select PHY_SUN4I_USB
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
config MACH_SUN8I
bool
- select SUN8I_RSB
select SUN6I_PRCM
default y if MACH_SUN8I_A23
default y if MACH_SUN8I_A33
---help---
See MMC0_CD_PIN help text.
-config MMC1_PINS
- string "Pins for mmc1"
- default ""
+config MMC1_PINS_PH
+ bool "Pins for mmc1 are on Port H"
+ depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40
---help---
- Set the pins used for mmc1, when applicable. This takes a string in the
- format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
-
-config MMC2_PINS
- string "Pins for mmc2"
- default ""
- ---help---
- See MMC1_PINS help text.
-
-config MMC3_PINS
- string "Pins for mmc3"
- default ""
- ---help---
- See MMC1_PINS help text.
+ Select this option for boards where mmc1 uses the Port H pinmux.
config MMC_SUNXI_SLOT_EXTRA
int "mmc extra slot number"
config AXP_GPIO
bool "Enable support for gpio-s on axp PMICs"
+ depends on AXP_PMIC_BUS
---help---
Say Y here to enable support for the gpio pins of the axp PMIC ICs.
config VIDEO_LCD_PANEL_I2C
bool "LCD panel needs to be configured via i2c"
depends on VIDEO_SUNXI
- select CMD_I2C
+ select DM_I2C_GPIO
---help---
Say y here if the LCD panel needs to be configured via i2c. This
will add a bitbang i2c controller using gpios to talk to the LCD.
-config VIDEO_LCD_PANEL_I2C_SDA
- string "LCD panel i2c interface SDA pin"
+config VIDEO_LCD_PANEL_I2C_NAME
+ string "LCD panel i2c interface node name"
depends on VIDEO_LCD_PANEL_I2C
- default "PG12"
+ default "i2c@0"
---help---
- Set the SDA pin for the LCD i2c interface. This takes a string in the
- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config VIDEO_LCD_PANEL_I2C_SCL
- string "LCD panel i2c interface SCL pin"
- depends on VIDEO_LCD_PANEL_I2C
- default "PG10"
- ---help---
- Set the SCL pin for the LCD i2c interface. This takes a string in the
- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
+ Set the device tree node name for the LCD i2c interface.
# Note only one of these may be selected at a time! But hidden choices are
# not supported by Kconfig
obj-y += cpu_info.o
obj-y += dram_helpers.o
obj-y += pinmux.o
-obj-$(CONFIG_SUN6I_P2WI) += p2wi.o
obj-$(CONFIG_SUN6I_PRCM) += prcm.o
obj-$(CONFIG_AXP_PMIC_BUS) += pmic_bus.o
-obj-$(CONFIG_SUN8I_RSB) += rsb.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/spl.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
spl_init();
preloader_console_init();
-#ifdef CONFIG_SPL_I2C
+#if CONFIG_IS_ENABLED(I2C) && CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
/* Needed early by sunxi_board_init if PMU is enabled */
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/prcm.h>
#include <asm/arch/gtbus.h>
#include <asm/arch/sys_proto.h>
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/sys_proto.h>
#ifdef CONFIG_SPL_BUILD
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Sunxi A31 Power Management Unit
- *
- * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
- * http://linux-sunxi.org
- *
- * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work
- *
- * (C) Copyright 2006-2013
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Berg Xing <bergxing@allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- */
-
-#include <common.h>
-#include <errno.h>
-#include <time.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/p2wi.h>
-#include <asm/arch/prcm.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-
-void p2wi_init(void)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
-
- /* Enable p2wi and PIO clk, and de-assert their resets */
- prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
-
- sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
- sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
-
- /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
- writel(P2WI_CTRL_RESET, &p2wi->ctrl);
- sdelay(0x100);
- writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
- &p2wi->cc);
-}
-
-int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
- unsigned long tmo = timer_get_us() + 1000000;
-
- writel(P2WI_PM_DEV_ADDR(slave_addr) |
- P2WI_PM_CTRL_ADDR(ctrl_reg) |
- P2WI_PM_INIT_DATA(init_data) |
- P2WI_PM_INIT_SEND,
- &p2wi->pm);
-
- while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) {
- if (timer_get_us() > tmo)
- return -ETIME;
- }
-
- return 0;
-}
-
-static int p2wi_await_trans(void)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
- unsigned long tmo = timer_get_us() + 1000000;
- int ret;
- u8 reg;
-
- while (1) {
- reg = readl(&p2wi->status);
- if (reg & P2WI_STAT_TRANS_ERR) {
- ret = -EIO;
- break;
- }
- if (reg & P2WI_STAT_TRANS_DONE) {
- ret = 0;
- break;
- }
- if (timer_get_us() > tmo) {
- ret = -ETIME;
- break;
- }
- }
- writel(reg, &p2wi->status); /* Clear status bits */
- return ret;
-}
-
-int p2wi_read(const u8 addr, u8 *data)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
- int ret;
-
- writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
- writel(P2WI_DATA_NUM_BYTES(1) |
- P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes);
- writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
- writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
-
- ret = p2wi_await_trans();
-
- *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK;
- return ret;
-}
-
-int p2wi_write(const u8 addr, u8 data)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
-
- writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
- writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
- writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes);
- writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
- writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
-
- return p2wi_await_trans();
-}
* axp223 uses the rsb bus, these functions abstract this.
*/
+#include <axp_pmic.h>
#include <common.h>
+#include <dm.h>
#include <asm/arch/p2wi.h>
#include <asm/arch/rsb.h>
#include <i2c.h>
+#include <power/pmic.h>
#include <asm/arch/pmic_bus.h>
#define AXP152_I2C_ADDR 0x30
#define AXP305_I2C_ADDR 0x36
#define AXP221_CHIP_ADDR 0x68
-#define AXP221_CTRL_ADDR 0x3e
-#define AXP221_INIT_DATA 0x3e
-/* AXP818 device and runtime addresses are same as AXP223 */
-#define AXP223_DEVICE_ADDR 0x3a3
-#define AXP223_RUNTIME_ADDR 0x2d
+#if CONFIG_IS_ENABLED(PMIC_AXP)
+static struct udevice *pmic;
+#else
+static int pmic_i2c_address(void)
+{
+ if (IS_ENABLED(CONFIG_AXP152_POWER))
+ return AXP152_I2C_ADDR;
+ if (IS_ENABLED(CONFIG_AXP305_POWER))
+ return AXP305_I2C_ADDR;
+
+ /* Other AXP2xx and AXP8xx variants */
+ return AXP209_I2C_ADDR;
+}
+#endif
int pmic_bus_init(void)
{
/* This cannot be 0 because it is used in SPL before BSS is ready */
static int needs_init = 1;
- __maybe_unused int ret;
+ int ret = 0;
if (!needs_init)
return 0;
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
-# ifdef CONFIG_MACH_SUN6I
- p2wi_init();
- ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
- AXP221_INIT_DATA);
-# elif defined CONFIG_MACH_SUN8I_R40
- /* Nothing. R40 uses the AXP221s in I2C mode */
- ret = 0;
-# else
- ret = rsb_init();
- if (ret)
- return ret;
-
- ret = rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR);
-# endif
- if (ret)
- return ret;
+#if CONFIG_IS_ENABLED(PMIC_AXP)
+ ret = uclass_get_device_by_driver(UCLASS_PMIC, DM_DRIVER_GET(axp_pmic),
+ &pmic);
+#else
+ if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI)) {
+ p2wi_init();
+ ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR,
+ AXP_PMIC_MODE_REG,
+ AXP_PMIC_MODE_P2WI);
+ } else if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB)) {
+ ret = rsb_init();
+ if (ret)
+ return ret;
+
+ ret = rsb_set_device_address(AXP_PMIC_PRI_DEVICE_ADDR,
+ AXP_PMIC_PRI_RUNTIME_ADDR);
+ }
#endif
- needs_init = 0;
- return 0;
+ needs_init = ret;
+
+ return ret;
}
int pmic_bus_read(u8 reg, u8 *data)
{
-#ifdef CONFIG_AXP152_POWER
- return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP209_POWER
- return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP305_POWER
- return i2c_read(AXP305_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
-# ifdef CONFIG_MACH_SUN6I
- return p2wi_read(reg, data);
-# elif defined CONFIG_MACH_SUN8I_R40
- return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
-# else
- return rsb_read(AXP223_RUNTIME_ADDR, reg, data);
-# endif
+#if CONFIG_IS_ENABLED(PMIC_AXP)
+ return pmic_read(pmic, reg, data, 1);
+#else
+ if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI))
+ return p2wi_read(reg, data);
+ if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB))
+ return rsb_read(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data);
+
+ return i2c_read(pmic_i2c_address(), reg, 1, data, 1);
#endif
}
int pmic_bus_write(u8 reg, u8 data)
{
-#ifdef CONFIG_AXP152_POWER
- return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1);
-#elif defined CONFIG_AXP209_POWER
- return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
-#elif defined CONFIG_AXP305_POWER
- return i2c_write(AXP305_I2C_ADDR, reg, 1, &data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
-# ifdef CONFIG_MACH_SUN6I
- return p2wi_write(reg, data);
-# elif defined CONFIG_MACH_SUN8I_R40
- return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
-# else
- return rsb_write(AXP223_RUNTIME_ADDR, reg, data);
-# endif
+#if CONFIG_IS_ENABLED(PMIC_AXP)
+ return pmic_write(pmic, reg, &data, 1);
+#else
+ if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI))
+ return p2wi_write(reg, data);
+ if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB))
+ return rsb_write(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data);
+
+ return i2c_write(pmic_i2c_address(), reg, 1, &data, 1);
#endif
}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
- *
- * Based on allwinner u-boot sources rsb code which is:
- * (C) Copyright 2007-2013
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * lixiang <lixiang@allwinnertech.com>
- */
-
-#include <common.h>
-#include <errno.h>
-#include <time.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/prcm.h>
-#include <asm/arch/rsb.h>
-
-static int rsb_set_device_mode(void);
-
-static void rsb_cfg_io(void)
-{
-#ifdef CONFIG_MACH_SUN8I
- sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
- sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
- sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
- sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
- sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
- sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
-#elif defined CONFIG_MACH_SUN9I
- sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
- sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
- sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
- sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
- sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
- sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
-#else
-#error unsupported MACH_SUNXI
-#endif
-}
-
-static void rsb_set_clk(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
- u32 div = 0;
- u32 cd_odly = 0;
-
- /* Source is Hosc24M, set RSB clk to 3Mhz */
- div = 24000000 / 3000000 / 2 - 1;
- cd_odly = div >> 1;
- if (!cd_odly)
- cd_odly = 1;
-
- writel((cd_odly << 8) | div, &rsb->ccr);
-}
-
-int rsb_init(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
-
- /* Enable RSB and PIO clk, and de-assert their resets */
- prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
-
- /* Setup external pins */
- rsb_cfg_io();
-
- writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
- rsb_set_clk();
-
- return rsb_set_device_mode();
-}
-
-static int rsb_await_trans(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
- unsigned long tmo = timer_get_us() + 1000000;
- u32 stat;
- int ret;
-
- while (1) {
- stat = readl(&rsb->stat);
- if (stat & RSB_STAT_LBSY_INT) {
- ret = -EBUSY;
- break;
- }
- if (stat & RSB_STAT_TERR_INT) {
- ret = -EIO;
- break;
- }
- if (stat & RSB_STAT_TOVER_INT) {
- ret = 0;
- break;
- }
- if (timer_get_us() > tmo) {
- ret = -ETIME;
- break;
- }
- }
- writel(stat, &rsb->stat); /* Clear status bits */
-
- return ret;
-}
-
-static int rsb_set_device_mode(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
- unsigned long tmo = timer_get_us() + 1000000;
-
- writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
- &rsb->dmcr);
-
- while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
- if (timer_get_us() > tmo)
- return -ETIME;
- }
-
- return rsb_await_trans();
-}
-
-static int rsb_do_trans(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
-
- setbits_le32(&rsb->ctrl, RSB_CTRL_START_TRANS);
- return rsb_await_trans();
-}
-
-int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
-
- writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) |
- RSB_DEVADDR_DEVICE_ADDR(device_addr), &rsb->devaddr);
- writel(RSB_CMD_SET_RTSADDR, &rsb->cmd);
-
- return rsb_do_trans();
-}
-
-int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
-
- writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
- writel(reg_addr, &rsb->addr);
- writel(data, &rsb->data);
- writel(RSB_CMD_BYTE_WRITE, &rsb->cmd);
-
- return rsb_do_trans();
-}
-
-int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
- int ret;
-
- writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
- writel(reg_addr, &rsb->addr);
- writel(RSB_CMD_BYTE_READ, &rsb->cmd);
-
- ret = rsb_do_trans();
- if (ret)
- return ret;
-
- *data = readl(&rsb->data) & 0xff;
-
- return 0;
-}
*/
#include <common.h>
+#include <fdtdec.h>
+#include <stdlib.h>
+#include <asm/arch-tegra/cboot.h>
#include <asm/arch-tegra/gpu.h>
/*
return 0;
}
+
+#if defined(CONFIG_ARM64)
+void ft_mac_address_setup(void *fdt)
+{
+ const void *cboot_fdt = (const void *)cboot_boot_x0;
+ uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
+ const char *path;
+ int offset, err;
+
+ err = cboot_get_ethaddr(cboot_fdt, local_mac);
+ if (err < 0)
+ memset(local_mac, 0, ETH_ALEN);
+
+ path = fdt_get_alias(fdt, "ethernet");
+ if (!path)
+ return;
+
+ debug("ethernet alias found: %s\n", path);
+
+ offset = fdt_path_offset(fdt, path);
+ if (offset < 0) {
+ printf("ethernet alias points to absent node %s\n", path);
+ return;
+ }
+
+ if (is_valid_ethaddr(local_mac)) {
+ err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
+ ETH_ALEN);
+ if (!err)
+ debug("Local MAC address set: %pM\n", local_mac);
+ }
+
+ if (eth_env_get_enetaddr("ethaddr", mac)) {
+ if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
+ err = fdt_setprop(fdt, offset, "mac-address", mac,
+ ETH_ALEN);
+ if (!err)
+ debug("MAC address set: %pM\n", mac);
+ }
+ }
+}
+
+static int ft_copy_carveout(void *dst, const void *src, const char *node)
+{
+ const char *names = "memory-region-names";
+ struct fdt_memory carveout;
+ unsigned int index = 0;
+ int err, offset, len;
+ const void *prop;
+
+ while (true) {
+ const char **compatibles = NULL;
+ unsigned int num_compatibles;
+ unsigned long flags;
+ char *copy = NULL;
+ const char *name;
+
+ err = fdtdec_get_carveout(src, node, "memory-region", index,
+ &carveout, &name, &compatibles,
+ &num_compatibles, &flags);
+ if (err < 0) {
+ if (err != -FDT_ERR_NOTFOUND)
+ printf("failed to get carveout for %s: %d\n",
+ node, err);
+ else
+ break;
+
+ return err;
+ }
+
+ if (name) {
+ const char *ptr = strchr(name, '@');
+
+ if (ptr) {
+ copy = strndup(name, ptr - name);
+ name = copy;
+ }
+ } else {
+ name = "carveout";
+ }
+
+ err = fdtdec_set_carveout(dst, node, "memory-region", index,
+ &carveout, name, compatibles,
+ num_compatibles, flags);
+ if (err < 0) {
+ printf("failed to set carveout for %s: %d\n", node,
+ err);
+ return err;
+ }
+
+ if (copy)
+ free(copy);
+
+ index++;
+ }
+
+ offset = fdt_path_offset(src, node);
+ if (offset < 0) {
+ debug("failed to find source offset for %s: %s\n", node,
+ fdt_strerror(err));
+ return err;
+ }
+
+ prop = fdt_getprop(src, offset, names, &len);
+ if (prop) {
+ offset = fdt_path_offset(dst, node);
+ if (offset < 0) {
+ debug("failed to find destination offset for %s: %s\n",
+ node, fdt_strerror(err));
+ return err;
+ }
+
+ err = fdt_setprop(dst, offset, "memory-region-names", prop,
+ len);
+ if (err < 0) {
+ debug("failed to copy \"%s\" property: %s\n", names,
+ fdt_strerror(err));
+ return err;
+ }
+ }
+
+ return 0;
+}
+
+void ft_carveout_setup(void *fdt, const char * const *nodes, unsigned int count)
+{
+ const void *cboot_fdt = (const void *)cboot_boot_x0;
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < count; i++) {
+ printf("copying carveout for %s...\n", nodes[i]);
+
+ err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
+ if (err < 0) {
+ if (err != -FDT_ERR_NOTFOUND)
+ printf("failed to copy carveout for %s: %d\n",
+ nodes[i], err);
+
+ continue;
+ }
+ }
+}
+#endif
static void boot_prep_linux(bootm_headers_t *images)
{
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
debug("using: FDT\n");
if (image_setup_linux(images)) {
printf("FDT creation failed! hanging...");
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
+ select USB_EHCI_IS_TDI if USB_EHCI_HCD
help
This supports QCA/Atheros ar934x family SOCs.
debug("## Transferring control to Linux (at address %08lx) ...\n",
(ulong)theKernel);
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_OF_LIBFDT
debug("using: FDT\n");
if (image_setup_linux(images)) {
#endif
}
cleanup_before_linux();
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len)
theKernel(0, machid, (unsigned long)images->ft_addr);
else
theKernel(0, machid, bd->bi_boot_params);
#include <cpu_func.h>
#include <irq_func.h>
#include <asm/cache.h>
+#include <asm/csr.h>
+
+#define CSR_MCACHE_CTL 0x7ca
+#define CSR_MMISC_CTL 0x7d0
+#define CSR_MARCHID 0xf12
+
+#define V5_MCACHE_CTL_IC_EN_OFFSET 0
+#define V5_MCACHE_CTL_DC_EN_OFFSET 1
+#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19
+#define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20
+
+#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET)
+#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET)
+#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET)
+#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)
+
/*
* cleanup_before_linux() is called just before we call linux
return 0;
}
+
+void harts_early_init(void)
+{
+ if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
+ unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+
+ if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN))
+ mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN;
+ if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN))
+ mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;
+ if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))
+ mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;
+ csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
+
+ /*
+ * Check DC_COHEN_EN, if cannot write to mcache_ctl,
+ * we assume this bitmap not support L2 CM
+ */
+ mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+ if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) {
+ /* Wait for DC_COHSTA bit be set */
+ while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN))
+ mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+ }
+ }
+}
#include <common.h>
#include <cpu.h>
#include <dm.h>
+#include <dm/lists.h>
#include <init.h>
#include <log.h>
#include <asm/encoding.h>
* The variables here must be stored in the data section since they are used
* before the bss section is available.
*/
-#ifdef CONFIG_OF_PRIOR_STAGE
-phys_addr_t prior_stage_fdt_address __section(".data");
-#endif
#ifndef CONFIG_XIP
u32 hart_lottery __section(".data") = 0;
int arch_early_init_r(void)
{
- return riscv_cpu_probe();
+ int ret;
+
+ ret = riscv_cpu_probe();
+ if (ret)
+ return ret;
+
+ if (IS_ENABLED(CONFIG_SYSRESET_SBI))
+ device_bind_driver(gd->dm_root, "sbi-sysreset",
+ "sbi-sysreset", NULL);
+
+ return 0;
}
/**
bnez tp, secondary_hart_loop
#endif
-#ifdef CONFIG_OF_PRIOR_STAGE
- la t0, prior_stage_fdt_address
- SREG s1, 0(t0)
-#endif
-
jal board_init_f_init_reserve
SREG s1, GD_FIRMWARE_FDT_ADDR(gp)
};
};
-#ifndef CONFIG_OF_PRIOR_STAGE
+#ifndef CONFIG_OF_BOARD
@fdt-SEQ {
description = "NAME";
type = "flat_dt";
configurations {
default = "conf-1";
-#ifndef CONFIG_OF_PRIOR_STAGE
+#ifndef CONFIG_OF_BOARD
@conf-SEQ {
#else
conf-1 {
description = "NAME";
firmware = "opensbi";
loadables = "uboot";
-#ifndef CONFIG_OF_PRIOR_STAGE
+#ifndef CONFIG_OF_BOARD
fdt = "fdt-SEQ";
#endif
};
* read/writes. We define __arch_*[bl] here, and leave __arch_*w
* to the architecture specific code.
*/
-#define __arch_getb(a) (*(unsigned char *)(a))
-#define __arch_getw(a) (*(unsigned short *)(a))
-#define __arch_getl(a) (*(unsigned int *)(a))
-#define __arch_getq(a) (*(unsigned long long *)(a))
-
-#define __arch_putb(v, a) (*(unsigned char *)(a) = (v))
-#define __arch_putw(v, a) (*(unsigned short *)(a) = (v))
-#define __arch_putl(v, a) (*(unsigned int *)(a) = (v))
-#define __arch_putq(v, a) (*(unsigned long long *)(a) = (v))
+#define __arch_getb(a) (*(volatile unsigned char *)(a))
+#define __arch_getw(a) (*(volatile unsigned short *)(a))
+#define __arch_getl(a) (*(volatile unsigned int *)(a))
+#define __arch_getq(a) (*(volatile unsigned long long *)(a))
+
+#define __arch_putb(v, a) (*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v, a) (*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v, a) (*(volatile unsigned int *)(a) = (v))
+#define __arch_putq(v, a) (*(volatile unsigned long long *)(a) = (v))
#define __raw_writeb(v, a) __arch_putb(v, a)
#define __raw_writew(v, a) __arch_putw(v, a)
#include <linux/types.h>
enum sbi_ext_id {
-#ifdef CONFIG_SBI_V01
SBI_EXT_0_1_SET_TIMER = 0x0,
SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
SBI_EXT_0_1_SHUTDOWN = 0x8,
-#endif
SBI_EXT_BASE = 0x10,
SBI_EXT_TIME = 0x54494D45,
SBI_EXT_IPI = 0x735049,
SBI_EXT_RFENCE = 0x52464E43,
+ SBI_EXT_HSM = 0x48534D,
+ SBI_EXT_SRST = 0x53525354,
};
enum sbi_ext_base_fid {
SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
+};
+
+enum sbi_ext_hsm_fid {
+ SBI_EXT_HSM_HART_START = 0,
+ SBI_EXT_HSM_HART_STOP,
+ SBI_EXT_HSM_HART_STATUS,
+ SBI_EXT_HSM_HART_SUSPEND,
+};
+
+enum sbi_hsm_hart_status {
+ SBI_HSM_HART_STATUS_STARTED = 0,
+ SBI_HSM_HART_STATUS_STOPPED,
+ SBI_HSM_HART_STATUS_START_PENDING,
+ SBI_HSM_HART_STATUS_STOP_PENDING,
+ SBI_HSM_HART_STATUS_SUSPEND_PENDING,
+ SBI_HSM_HART_STATUS_RESUME_PENDING,
+};
+
+enum sbi_ext_srst_fid {
+ SBI_EXT_SRST_RESET = 0,
+};
+
+enum sbi_srst_reset_type {
+ SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
+ SBI_SRST_RESET_TYPE_COLD_REBOOT,
+ SBI_SRST_RESET_TYPE_WARM_REBOOT,
+};
+
+enum sbi_srst_reset_reason {
+ SBI_SRST_RESET_REASON_NONE = 0,
+ SBI_SRST_RESET_REASON_SYS_FAILURE,
};
#ifdef CONFIG_SBI_V01
long sbi_get_spec_version(void);
int sbi_get_impl_id(void);
int sbi_probe_extension(int ext);
+void sbi_srst_reset(unsigned long type, unsigned long reason);
#endif
static void boot_prep_linux(bootm_headers_t *images)
{
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_OF_LIBFDT
debug("using: FDT\n");
if (image_setup_linux(images)) {
announce_and_cleanup(fake);
if (!fake) {
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_SMP
ret = smp_call_function(images->ep,
(ulong)images->ft_addr, 0, 0);
fdt_addr_t addr;
fdt_size_t size;
int offset, node, err, rmem_offset;
- bool nomap = true;
char basename[32] = {0};
int bname_len;
int max_len = sizeof(basename);
pmp_mem.start = addr;
pmp_mem.end = addr + size - 1;
err = fdtdec_add_reserved_memory(dst, basename, &pmp_mem,
- &phandle, false);
+ NULL, 0, &phandle, 0);
if (err < 0 && err != -FDT_ERR_EXISTS) {
log_err("failed to add reserved memory: %d\n", err);
return err;
}
- if (!fdt_getprop(src, node, "no-map", NULL))
- nomap = false;
- if (nomap) {
+ if (fdt_getprop(src, node, "no-map", NULL)) {
rmem_offset = fdt_node_offset_by_phandle(dst, phandle);
fdt_setprop_empty(dst, rmem_offset, "no-map");
}
return -ENOTSUPP;
}
+/**
+ * sbi_srst_reset() - invoke system reset extension
+ *
+ * @type: type of reset
+ * @reason: reason for reset
+ */
+void sbi_srst_reset(unsigned long type, unsigned long reason)
+{
+ sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason,
+ 0, 0, 0, 0);
+}
+
#ifdef CONFIG_SBI_V01
/**
DECLARE_GLOBAL_DATA_PTR;
-extern phys_addr_t prior_stage_fdt_address;
/*
* Miscellaneous platform dependent initializations
*/
void *board_fdt_blob_setup(void)
{
+#if CONFIG_IS_ENABLED(OF_BOARD)
+ return (void *)(ulong)gd->arch.firmware_fdt_addr;
+#elif CONFIG_IS_ENABLED(OF_SEPARATE)
return (void *)CONFIG_SYS_FDT_BASE;
+#else
+ return NULL;
+#endif
}
int smc_init(void)
#define I2C_IO_REG_CL ((1 << I2C_IO_REG_0_USB_H0_CL) | \
(1 << I2C_IO_REG_0_USB_H1_CL))
-/*
- * Information specific to the iEi Puzzle-M801 board.
- */
-
-/* Internal configuration registers */
-#define CP1_CONF_REG_BASE 0xf4440000
-#define CONF_REG_MPP0 0x0
-#define CONF_REG_MPP1 0x4
-#define CONF_REG_MPP2 0x8
-#define CONF_REG_MPP3 0xC
-
static int usb_enabled = 0;
/* Board specific xHCI dis-/enable code */
int board_early_init_f(void)
{
- /* Initialize some platform specific memory locations */
- if (of_machine_is_compatible("marvell,armada8040-puzzle-m801")) {
- /* MPP setup */
- writel(0x00444444, CP1_CONF_REG_BASE + CONF_REG_MPP0);
- writel(0x00000000, CP1_CONF_REG_BASE + CONF_REG_MPP1);
- writel(0x00000000, CP1_CONF_REG_BASE + CONF_REG_MPP2);
- writel(0x08888000, CP1_CONF_REG_BASE + CONF_REG_MPP3);
- }
+ /* Nothing to do yet */
return 0;
}
+++ /dev/null
-#
-# Copyright (C) 2017 Allied Telesis Labs
-#
-
-# Armada XP uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
F: board/amlogic/beelink-s922x/
F: configs/beelink-gtking_defconfig
F: configs/beelink-gtkingpro_defconfig
+F: configs/beelink-gsking-x_defconfig
F: doc/board/amlogic/beelink-gtking.rst
F: doc/board/amlogic/beelink-gtkingpro.rst
--- /dev/null
+JetHome JetHub
+M: Vyacheslav Bocharov <adeep@lexina.in>
+S: Maintained
+L: u-boot-amlogic@groups.io
+F: board/amlogic/jethub-j80/
+F: configs/jethub_j80_defconfig
+F: configs/jethub_j100_defconfig
+F: doc/board/amlogic/jethub-j80.rst
+F: doc/board/amlogic/jethub-j100.rst
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2021 Vyacheslav Bocharov
+# Author: Vyacheslav Bocharov <adeep@lexina.in>
+
+obj-y := jethub-j80.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Vyacheslav Bocharov
+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <adc.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/gx.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
+
+#define EFUSE_SN_OFFSET 50
+#define EFUSE_SN_SIZE 32
+#define EFUSE_MAC_OFFSET 0
+#define EFUSE_MAC_SIZE 6
+#define EFUSE_USID_OFFSET 18
+#define EFUSE_USID_SIZE 32
+
+int misc_init_r(void)
+{
+ u8 mac_addr[EFUSE_MAC_SIZE];
+ char serial[EFUSE_SN_SIZE];
+ char usid[EFUSE_USID_SIZE];
+ ssize_t len;
+ unsigned int adcval;
+ int ret;
+
+ if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+ len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+ mac_addr, EFUSE_MAC_SIZE);
+ if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+ else
+ meson_generate_serial_ethaddr();
+ }
+
+ if (!env_get("serial")) {
+ len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
+ EFUSE_SN_SIZE);
+ if (len == EFUSE_SN_SIZE)
+ env_set("serial", serial);
+ }
+
+ if (!env_get("usid")) {
+ len = meson_sm_read_efuse(EFUSE_USID_OFFSET, usid,
+ EFUSE_USID_SIZE);
+ if (len == EFUSE_USID_SIZE)
+ env_set("usid", usid);
+ }
+
+ ret = adc_channel_single_shot("adc@8680", 0, &adcval);
+ if (adcval < 3000)
+ env_set("userbutton", "true");
+ else
+ env_set("userbutton", "false");
+
+ return 0;
+}
F: board/amlogic/odroid-n2/
F: configs/odroid-n2_defconfig
F: configs/odroid-c4_defconfig
+F: configs/odroid-hc4_defconfig
F: doc/board/amlogic/odroid-n2.rst
F: doc/board/amlogic/odroid-c4.rst
L: u-boot-amlogic@groups.io
F: board/amlogic/u200/
F: configs/u200_defconfig
+F: configs/bananapi-m5_defconfig
+F: configs/radxa-zero_defconfig
F: doc/board/amlogic/u200.rst
+F: doc/board/amlogic/radxa-zero.rst
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
return 0;
}
return 0;
}
+
+void *board_fdt_blob_setup(void)
+{
+ /* Stored the DTB address there during our init */
+ return (void *)prior_stage_fdt_address;
+}
offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd");
while (offset != -FDT_ERR_NOTFOUND) {
lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
- NULL, true);
+ NULL, NULL, true);
offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
"nxp,imx8-pd");
}
/* board dependent setup after realloc */
int board_init(void)
{
- /* address of boot parameters */
- gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
-
- if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
- gpio_hog_probe_all();
-
board_key_check();
#ifdef CONFIG_DM_REGULATOR
#include <virtio_types.h>
#include <virtio.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int board_init(void)
{
/*
return 0;
}
#endif
+
+void *board_fdt_blob_setup(void)
+{
+ /* Stored the DTB address there during our init */
+ return (void *)(ulong)gd->arch.firmware_fdt_addr;
+}
/* board dependent setup after realloc */
int board_init(void)
{
- /* address of boot parameters */
- gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
-
if (IS_ENABLED(CONFIG_DM_REGULATOR))
regulators_enable_boot_on(_DEBUG);
KM83XX BOARD
-M: Holger Brunck <holger.brunck@hitachi-powergrids.com>
+M: Holger Brunck <holger.brunck@hitachienergy.com>
M: Heiko Schocher <hs@denx.de>
S: Maintained
F: board/keymile/km83xx/
KM_ARM BOARD
-M: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
+M: Holger Brunck <holger.brunck@hitachienergy.com>
S: Maintained
F: board/keymile/km_arm/
F: include/configs/km_kirkwood.h
Hitachi Power Grids LS102XA BOARD
-M: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
-M: Rainer Boschung <rainer.boschung@hitachi-powergrids.com>
-M: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com>
+M: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
+M: Rainer Boschung <rainer.boschung@hitachienergy.com>
S: Maintained
F: board/keymile/pg-wcom-ls102xa/
F: include/configs/km/pg-wcom-ls102xa.h
Hitachi Power Grids SECU1 BOARD
-M: Holger Brunck <holger.brunck@hitachi-powergrids.com>
+M: Holger Brunck <holger.brunck@hitachienergy.com>
S: Maintained
F: include/configs/socfpga_arria5_secu1.h
F: configs/socfpga_secu1_defconfig
*/
void set_muxconf_regs(void)
{
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)); /*SDRC_CKE1*/
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*SDRC_CKE0*/
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)) /*SDRC_CKE1*/
- MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
- MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
- MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
- MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
- MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
- MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
- MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /*GPMC_nCS1*/
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /*GPMC_nCS2*/
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /*GPMC_nCS3*/
- MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)); /*GPMC_nCS5*/
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M0)); /*GPMC_nCS6*/
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)); /*GPMC_nCS7*/
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)); /*GPMC_CLK*/
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*GPMC_nADV_ALE*/
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*GPMC_nOE*/
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*GPMC_nWE*/
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*GPMC_nBE0_CLE*/
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)); /*GPMC_nBE1*/
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*GPMC_nWP*/
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*GPMC_WAIT0*/
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /*GPMC_WAIT1*/
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /*GPIO_64*/
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); /*GPMC_WAIT3*/
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) /*GPMC_nCS4*/
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M0)) /*GPMC_nCS6*/
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) /*GPMC_nBE0_CLE*/
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) /*GPMC_nBE1*/
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /*UART1_TX*/
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /*UART1_RTS*/
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /*UART1_CTS*/
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /*UART1_RX*/
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
- MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
- MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /*JTAG_EMU0*/
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /*JTAG_EMU1*/
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)); /*ETK_CLK*/
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); /*ETK_CTL*/
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)); /*ETK_D0*/
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)); /*ETK_D1*/
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)); /*ETK_D2*/
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)); /*ETK_D3*/
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)); /*ETK_D4*/
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)); /*ETK_D5*/
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)); /*ETK_D6*/
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); /*ETK_D7*/
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); /*ETK_D8*/
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); /*ETK_D9*/
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) /*ETK_CLK*/
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) /*ETK_CTL*/
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) /*ETK_D0*/
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) /*ETK_D1*/
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) /*ETK_D2*/
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) /*ETK_D3*/
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) /*ETK_D4*/
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) /*ETK_D5*/
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) /*ETK_D6*/
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) /*ETK_D7*/
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) /*ETK_D8*/
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) /*ETK_D9*/
#ifndef CONFIG_USB_EHCI_OMAP /* Torpedo does not use EHCI_OMAP */
- MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); /*ETK_D10*/
- MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); /*ETK_D11*/
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); /*ETK_D12*/
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); /*ETK_D13*/
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); /*ETK_D14*/
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); /*ETK_D15*/
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) /*ETK_D10*/
+ MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) /*ETK_D11*/
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) /*ETK_D12*/
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) /*ETK_D13*/
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) /*ETK_D14*/
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) /*ETK_D15*/
#endif
- MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /*d2d_mcad1*/
- MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /*d2d_mcad2*/
- MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /*d2d_mcad3*/
- MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /*d2d_mcad4*/
- MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /*d2d_mcad5*/
- MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /*d2d_mcad6*/
- MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /*d2d_mcad7*/
- MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /*d2d_mcad8*/
- MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /*d2d_mcad9*/
- MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /*d2d_mcad10*/
- MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /*d2d_mcad11*/
- MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /*d2d_mcad12*/
- MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /*d2d_mcad13*/
- MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /*d2d_mcad14*/
- MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /*d2d_mcad15*/
- MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /*d2d_mcad16*/
- MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /*d2d_mcad17*/
- MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /*d2d_mcad18*/
- MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /*d2d_mcad19*/
- MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /*d2d_mcad20*/
- MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /*d2d_mcad21*/
- MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /*d2d_mcad22*/
- MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /*d2d_mcad23*/
- MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /*d2d_mcad24*/
- MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /*d2d_mcad25*/
- MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /*d2d_mcad26*/
- MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /*d2d_mcad27*/
- MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /*d2d_mcad28*/
- MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /*d2d_mcad29*/
- MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /*d2d_mcad30*/
- MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /*d2d_mcad31*/
- MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /*d2d_mcad32*/
- MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /*d2d_mcad33*/
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /*d2d_mcad34*/
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /*d2d_mcad35*/
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /*d2d_mcad36*/
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)); /*d2d_clk26mi*/
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)); /*d2d_nrespwron*/
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)); /*d2d_nreswarm */
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)); /*d2d_arm9nirq */
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)); /*d2d_uma2p6fiq*/
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)); /*d2d_spint*/
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)); /*d2d_frint*/
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)); /*d2d_dmareq0*/
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)); /*d2d_dmareq1*/
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)); /*d2d_dmareq2*/
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)); /*d2d_dmareq3*/
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)); /*d2d_n3gtrst*/
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)); /*d2d_n3gtdi*/
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)); /*d2d_n3gtdo*/
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)); /*d2d_n3gtms*/
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)); /*d2d_n3gtck*/
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)); /*d2d_n3grtck*/
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)); /*d2d_mstdby*/
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)); /*d2d_swakeup*/
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)); /*d2d_idlereq*/
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)); /*d2d_idleack*/
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)); /*d2d_mwrite*/
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)); /*d2d_swrite*/
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)); /*d2d_mread*/
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); /*d2d_sread*/
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_mbusflag*/
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_sbusflag*/
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/
#ifdef CONFIG_USB_EHCI_OMAP /* SOM-LV Uses EHCI-OMAP */
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_DATA0*/
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_DATA1*/
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)); /*HSUSB2_DATA2*/
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)); /*HSUSB2_DATA3*/
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA4*/
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA5*/
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); /*HSUSB2_DATA6*/
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA7*/
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */
- MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_CLK*/
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)); /*HSUSB2_DIR*/
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_NXT*/
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA0*/
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA1*/
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*HSUSB2_DATA2*/
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*HSUSB2_DATA3*/
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA4*/
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA5*/
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*HSUSB2_DATA6*/
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA7*/
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_NXT*/
#endif
}
#include <i2c.h>
#include <log.h>
#include <net.h>
+#include <stdlib.h>
#include <linux/bitops.h>
#include <linux/libfdt.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch-tegra/cboot.h>
+#include <asm/arch-tegra/board.h>
#include "../p2571/max77620_init.h"
void pin_mux_mmc(void)
}
#endif /* PCI */
-static void ft_mac_address_setup(void *fdt)
-{
- const void *cboot_fdt = (const void *)cboot_boot_x0;
- uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
- const char *path;
- int offset, err;
-
- err = cboot_get_ethaddr(cboot_fdt, local_mac);
- if (err < 0)
- memset(local_mac, 0, ETH_ALEN);
-
- path = fdt_get_alias(fdt, "ethernet");
- if (!path)
- return;
-
- debug("ethernet alias found: %s\n", path);
-
- offset = fdt_path_offset(fdt, path);
- if (offset < 0) {
- printf("ethernet alias points to absent node %s\n", path);
- return;
- }
-
- if (is_valid_ethaddr(local_mac)) {
- err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
- ETH_ALEN);
- if (!err)
- debug("Local MAC address set: %pM\n", local_mac);
- }
-
- if (eth_env_get_enetaddr("ethaddr", mac)) {
- if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
- err = fdt_setprop(fdt, offset, "mac-address", mac,
- ETH_ALEN);
- if (!err)
- debug("MAC address set: %pM\n", mac);
- }
- }
-}
-
-static int ft_copy_carveout(void *dst, const void *src, const char *node)
-{
- struct fdt_memory fb;
- int err;
-
- err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
- if (err < 0) {
- if (err != -FDT_ERR_NOTFOUND)
- printf("failed to get carveout for %s: %d\n", node,
- err);
-
- return err;
- }
-
- err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
- &fb);
- if (err < 0) {
- printf("failed to set carveout for %s: %d\n", node, err);
- return err;
- }
-
- return 0;
-}
-
-static void ft_carveout_setup(void *fdt)
-{
- const void *cboot_fdt = (const void *)cboot_boot_x0;
- static const char * const nodes[] = {
- "/host1x@50000000/dc@54200000",
- "/host1x@50000000/dc@54240000",
- };
- unsigned int i;
- int err;
-
- for (i = 0; i < ARRAY_SIZE(nodes); i++) {
- err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
- if (err < 0) {
- if (err != -FDT_ERR_NOTFOUND)
- printf("failed to copy carveout for %s: %d\n",
- nodes[i], err);
- continue;
- }
- }
-}
+static const char * const nodes[] = {
+ "/host1x@50000000/dc@54200000",
+ "/host1x@50000000/dc@54240000",
+ "/external-memory-controller@7001b000",
+};
int ft_board_setup(void *fdt, struct bd_info *bd)
{
ft_mac_address_setup(fdt);
- ft_carveout_setup(fdt);
+ ft_carveout_setup(fdt, nodes, ARRAY_SIZE(nodes));
return 0;
}
#include <i2c.h>
#include <log.h>
#include <net.h>
+#include <stdlib.h>
#include <linux/libfdt.h>
-#include <asm/arch-tegra/cboot.h>
+#include <asm/arch-tegra/board.h>
#include "../p2571/max77620_init.h"
void pin_mux_mmc(void)
}
#endif
-static void ft_mac_address_setup(void *fdt)
-{
- const void *cboot_fdt = (const void *)cboot_boot_x0;
- uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
- const char *path;
- int offset, err;
-
- err = cboot_get_ethaddr(cboot_fdt, local_mac);
- if (err < 0)
- memset(local_mac, 0, ETH_ALEN);
-
- path = fdt_get_alias(fdt, "ethernet");
- if (!path)
- return;
-
- debug("ethernet alias found: %s\n", path);
-
- offset = fdt_path_offset(fdt, path);
- if (offset < 0) {
- printf("ethernet alias points to absent node %s\n", path);
- return;
- }
-
- if (is_valid_ethaddr(local_mac)) {
- err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
- ETH_ALEN);
- if (!err)
- debug("Local MAC address set: %pM\n", local_mac);
- }
-
- if (eth_env_get_enetaddr("ethaddr", mac)) {
- if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
- err = fdt_setprop(fdt, offset, "mac-address", mac,
- ETH_ALEN);
- if (!err)
- debug("MAC address set: %pM\n", mac);
- }
- }
-}
-
-static int ft_copy_carveout(void *dst, const void *src, const char *node)
-{
- struct fdt_memory fb;
- int err;
-
- err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
- if (err < 0) {
- if (err != -FDT_ERR_NOTFOUND)
- printf("failed to get carveout for %s: %d\n", node,
- err);
-
- return err;
- }
-
- err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
- &fb);
- if (err < 0) {
- printf("failed to set carveout for %s: %d\n", node, err);
- return err;
- }
-
- return 0;
-}
-
-static void ft_carveout_setup(void *fdt)
-{
- const void *cboot_fdt = (const void *)cboot_boot_x0;
- static const char * const nodes[] = {
- "/host1x@13e00000/display-hub@15200000/display@15200000",
- "/host1x@13e00000/display-hub@15200000/display@15210000",
- "/host1x@13e00000/display-hub@15200000/display@15220000",
- };
- unsigned int i;
- int err;
-
- for (i = 0; i < ARRAY_SIZE(nodes); i++) {
- printf("copying carveout for %s...\n", nodes[i]);
-
- err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
- if (err < 0) {
- if (err != -FDT_ERR_NOTFOUND)
- printf("failed to copy carveout for %s: %d\n",
- nodes[i], err);
-
- continue;
- }
- }
-}
+static const char * const nodes[] = {
+ "/host1x@13e00000/display-hub@15200000/display@15200000",
+ "/host1x@13e00000/display-hub@15200000/display@15210000",
+ "/host1x@13e00000/display-hub@15200000/display@15220000",
+};
int ft_board_setup(void *fdt, struct bd_info *bd)
{
ft_mac_address_setup(fdt);
- ft_carveout_setup(fdt);
+ ft_carveout_setup(fdt, nodes, ARRAY_SIZE(nodes));
return 0;
}
#include <linux/bitops.h>
#include <linux/libfdt.h>
#include <pca953x.h>
-#include <asm/arch-tegra/cboot.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/board.h>
#include "../p2571/max77620_init.h"
void pin_mux_mmc(void)
}
#endif /* PCI */
-static void ft_mac_address_setup(void *fdt)
-{
- const void *cboot_fdt = (const void *)cboot_boot_x0;
- uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
- const char *path;
- int offset, err;
-
- err = cboot_get_ethaddr(cboot_fdt, local_mac);
- if (err < 0)
- memset(local_mac, 0, ETH_ALEN);
-
- path = fdt_get_alias(fdt, "ethernet");
- if (!path)
- return;
-
- debug("ethernet alias found: %s\n", path);
-
- offset = fdt_path_offset(fdt, path);
- if (offset < 0) {
- printf("ethernet alias points to absent node %s\n", path);
- return;
- }
-
- if (is_valid_ethaddr(local_mac)) {
- err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
- ETH_ALEN);
- if (!err)
- debug("Local MAC address set: %pM\n", local_mac);
- }
-
- if (eth_env_get_enetaddr("ethaddr", mac)) {
- if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
- err = fdt_setprop(fdt, offset, "mac-address", mac,
- ETH_ALEN);
- if (!err)
- debug("MAC address set: %pM\n", mac);
- }
- }
-}
-
-static int ft_copy_carveout(void *dst, const void *src, const char *node)
-{
- struct fdt_memory fb;
- int err;
-
- err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
- if (err < 0) {
- if (err != -FDT_ERR_NOTFOUND)
- printf("failed to get carveout for %s: %d\n", node,
- err);
-
- return err;
- }
-
- err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
- &fb);
- if (err < 0) {
- printf("failed to set carveout for %s: %d\n", node, err);
- return err;
- }
-
- return 0;
-}
-
-static void ft_carveout_setup(void *fdt)
-{
- const void *cboot_fdt = (const void *)cboot_boot_x0;
- static const char * const nodes[] = {
- "/host1x@50000000/dc@54200000",
- "/host1x@50000000/dc@54240000",
- };
- unsigned int i;
- int err;
-
- for (i = 0; i < ARRAY_SIZE(nodes); i++) {
- printf("copying carveout for %s...\n", nodes[i]);
-
- err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
- if (err < 0) {
- if (err != -FDT_ERR_NOTFOUND)
- printf("failed to copy carveout for %s: %d\n",
- nodes[i], err);
-
- continue;
- }
- }
-}
+static const char * const nodes[] = {
+ "/host1x@50000000/dc@54200000",
+ "/host1x@50000000/dc@54240000",
+ "/external-memory-controller@7001b000",
+};
int ft_board_setup(void *fdt, struct bd_info *bd)
{
ft_mac_address_setup(fdt);
- ft_carveout_setup(fdt);
+ ft_carveout_setup(fdt, nodes, ARRAY_SIZE(nodes));
return 0;
}
{
if (IS_ENABLED(CONFIG_OF_SEPARATE)) {
if (gd->arch.firmware_fdt_addr)
- return (ulong *)gd->arch.firmware_fdt_addr;
- else
- return (ulong *)&_end;
+ return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
}
+
+ return (ulong *)&_end;
}
int board_init(void)
{
if (IS_ENABLED(CONFIG_OF_SEPARATE)) {
if (gd->arch.firmware_fdt_addr)
- return (ulong *)gd->arch.firmware_fdt_addr;
- else
- return (ulong *)&_end;
+ return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
}
+
+ return (ulong *)&_end;
}
int board_init(void)
int board_init(void)
{
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
-
return 0;
}
int board_init(void)
{
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
-
return 0;
}
int board_init(void)
{
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
-
return 0;
}
int board_init(void)
{
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
-
#ifdef CONFIG_ETH_DESIGNWARE
const char *phy_mode;
int node;
int board_init(void)
{
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
return 0;
}
int board_init(void)
{
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
return 0;
}
int board_init(void)
{
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
return 0;
}
/* board dependent setup after realloc */
int board_init(void)
{
- /* address of boot parameters */
- gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
-
- if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
- gpio_hog_probe_all();
-
board_key_check();
if (board_is_ev1())
S: Maintained
F: configs/nanopi_neo_air_defconfig
+NANOPI-R1S-H5 BOARD
+M: Chukun Pan <amadeus@jmu.edu.cn>
+S: Maintained
+F: configs/nanopi_r1s_h5_defconfig
+
NANOPI-A64 BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
S: Maintained
F: configs/pinephone_defconfig
+PINETAB BOARD
+M: Arnaud Ferraris <arnaud.ferraris@collabora.com>
+S: Maintained
+F: configs/pinetab_defconfig
+
R16 EVB PARROT BOARD
M: Quentin Schulz <quentin.schulz@free-electrons.com>
S: Maintained
#include <asm/arch/cpu.h>
#include <asm/arch/display.h>
#include <asm/arch/dram.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/prcm.h>
#include <asm/arch/spl.h>
#include <spl.h>
#include <sy8106a.h>
#include <asm/setup.h>
-
-#if defined(CONFIG_VIDEO_LCD_PANEL_I2C)
-/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
-int soft_i2c_gpio_sda;
-int soft_i2c_gpio_scl;
-
-static int soft_i2c_board_init(void)
-{
- int ret;
-
- soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
- if (soft_i2c_gpio_sda < 0) {
- printf("Error invalid soft i2c sda pin: '%s', err %d\n",
- CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
- return soft_i2c_gpio_sda;
- }
- ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
- if (ret) {
- printf("Error requesting soft i2c sda pin: '%s', err %d\n",
- CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
- return ret;
- }
-
- soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
- if (soft_i2c_gpio_scl < 0) {
- printf("Error invalid soft i2c scl pin: '%s', err %d\n",
- CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
- return soft_i2c_gpio_scl;
- }
- ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
- if (ret) {
- printf("Error requesting soft i2c scl pin: '%s', err %d\n",
- CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
- return ret;
- }
-
- return 0;
-}
-#else
-static int soft_i2c_board_init(void) { return 0; }
-#endif
+#include <status_led.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
#endif /* CONFIG_DM_MMC */
- /* Uses dm gpio code so do this here and not in i2c_init_board() */
- return soft_i2c_board_init();
+ return 0;
}
/*
static void mmc_pinmux_setup(int sdc)
{
unsigned int pin;
- __maybe_unused int pins;
switch (sdc) {
case 0:
break;
case 1:
- pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
-
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40)
- if (pins == SUNXI_GPIO_H) {
+ if (IS_ENABLED(CONFIG_MMC1_PINS_PH)) {
/* SDC1: PH22-PH-27 */
for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
sunxi_gpio_set_drv(pin, 2);
}
#elif defined(CONFIG_MACH_SUN8I)
- if (pins == SUNXI_GPIO_D) {
- /* SDC1: PD2-PD7 */
- for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
- } else {
- /* SDC1: PG0-PG5 */
- for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
+ /* SDC1: PG0-PG5 */
+ for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
}
#endif
break;
case 2:
- pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
-
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
/* SDC2: PC6-PC11 */
for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
sunxi_gpio_set_drv(pin, 2);
}
#elif defined(CONFIG_MACH_SUN5I)
- if (pins == SUNXI_GPIO_E) {
- /* SDC2: PE4-PE9 */
- for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
- } else {
- /* SDC2: PC6-PC15 */
- for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
+ /* SDC2: PC6-PC15 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
}
#elif defined(CONFIG_MACH_SUN6I)
- if (pins == SUNXI_GPIO_A) {
- /* SDC2: PA9-PA14 */
- for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
- } else {
- /* SDC2: PC6-PC15, PC24 */
- for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
-
- sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
- sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
+ /* SDC2: PC6-PC15, PC24 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
}
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
#elif defined(CONFIG_MACH_SUN8I_R40)
/* SDC2: PC6-PC15, PC24 */
for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
break;
case 3:
- pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
-
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40)
/* SDC3: PI4-PI9 */
sunxi_gpio_set_drv(pin, 2);
}
#elif defined(CONFIG_MACH_SUN6I)
- if (pins == SUNXI_GPIO_A) {
- /* SDC3: PA9-PA14 */
- for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
- } else {
- /* SDC3: PC6-PC15, PC24 */
- for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
-
- sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
- sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
+ /* SDC3: PC6-PC15, PC24 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
}
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
+ sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
#endif
break;
{
int power_failed = 0;
+#ifdef CONFIG_LED_STATUS
+ if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC))
+ status_led_init();
+#endif
+
#ifdef CONFIG_SY8106A_POWER
power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
#endif
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
void eth_init_board(void)
{
if (env_common.core_mask.val == ALL_CPU_MASK)
return 0;
- if (!IMAGE_ENABLE_OF_LIBFDT || !images->ft_len) {
+ if (!CONFIG_IS_ENABLED(OF_LIBFDT) || !images->ft_len) {
pr_err("WARN: core_mask setup will work properly only with external DTB!\n");
return 0;
}
}
ofnode = ofnode_path(path);
- ret = lists_bind_fdt(parent, ofnode, &dev, false);
+ ret = lists_bind_fdt(parent, ofnode, &dev, drv, false);
if (!dev || ret) {
printf("Unable to bind. err:%d\n", ret);
int prefetchable;
dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
+ header_type &= 0x7f;
if (header_type == PCI_HEADER_TYPE_CARDBUS) {
printf("CardBus doesn't support BARs\n");
return -ENOSYS;
+ } else if (header_type != PCI_HEADER_TYPE_NORMAL &&
+ header_type != PCI_HEADER_TYPE_BRIDGE) {
+ printf("unknown header type\n");
+ return -ENOSYS;
}
bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2;
pci_class_str(class));
pci_show_regs(dev, regs_rest);
- switch (header_type & 0x03) {
+ switch (header_type & 0x7f) {
case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
pci_show_regs(dev, regs_normal);
break;
};
static struct sbi_ext extensions[] = {
- { 0x00000000, "sbi_set_timer" },
- { 0x00000001, "sbi_console_putchar" },
- { 0x00000002, "sbi_console_getchar" },
- { 0x00000003, "sbi_clear_ipi" },
- { 0x00000004, "sbi_send_ipi" },
- { 0x00000005, "sbi_remote_fence_i" },
- { 0x00000006, "sbi_remote_sfence_vma" },
- { 0x00000007, "sbi_remote_sfence_vma_asid" },
- { 0x00000008, "sbi_shutdown" },
- { 0x00000010, "SBI Base Functionality" },
- { 0x54494D45, "Timer Extension" },
- { 0x00735049, "IPI Extension" },
- { 0x52464E43, "RFENCE Extension" },
- { 0x0048534D, "Hart State Management Extension" },
- { 0x53525354, "System Reset Extension" },
+ { SBI_EXT_0_1_SET_TIMER, "sbi_set_timer" },
+ { SBI_EXT_0_1_CONSOLE_PUTCHAR, "sbi_console_putchar" },
+ { SBI_EXT_0_1_CONSOLE_GETCHAR, "sbi_console_getchar" },
+ { SBI_EXT_0_1_CLEAR_IPI, "sbi_clear_ipi" },
+ { SBI_EXT_0_1_SEND_IPI, "sbi_send_ipi" },
+ { SBI_EXT_0_1_REMOTE_FENCE_I, "sbi_remote_fence_i" },
+ { SBI_EXT_0_1_REMOTE_SFENCE_VMA, "sbi_remote_sfence_vma" },
+ { SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, "sbi_remote_sfence_vma_asid" },
+ { SBI_EXT_0_1_SHUTDOWN, "sbi_shutdown" },
+ { SBI_EXT_BASE, "SBI Base Functionality" },
+ { SBI_EXT_TIME, "Timer Extension" },
+ { SBI_EXT_IPI, "IPI Extension" },
+ { SBI_EXT_RFENCE, "RFENCE Extension" },
+ { SBI_EXT_HSM, "Hart State Management Extension" },
+ { SBI_EXT_SRST, "System Reset Extension" },
};
static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
#include <common.h>
#include <command.h>
#include <env.h>
-#include <lz4.h>
+#include <u-boot/lz4.h>
static int do_unlz4(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
default y if CONSOLE_MUX
help
This allows multiple input/output devices to be set at boot time.
- For example, if stdout is set to "serial,video" then output will
- be sent to both the serial and video devices on boot. The
+ For example, if stdout is set to "serial,vidconsole" then output
+ will be sent to both the serial and video devices on boot. The
environment variables can be updated after boot to change the
input/output devices.
select SPL_IMAGE_SIGN_INFO
select SPL_FIT_FULL_CHECK
+config SPL_FIT_SIGNATURE_MAX_SIZE
+ hex "Max size of signed FIT structures in SPL"
+ depends on SPL_FIT_SIGNATURE
+ default 0x10000000
+ help
+ This option sets a max size in bytes for verified FIT uImages.
+ A sane value of 256MB protects corrupted DTB structures from overlapping
+ device memory. Assure this size does not extend past expected storage
+ space.
+
config SPL_LOAD_FIT
bool "Enable SPL loading U-Boot as a FIT (basic fitImage features)"
select SPL_FIT
endif
endif
-obj-y += image.o
+obj-y += image.o image-board.o
obj-$(CONFIG_$(SPL_TPL_)HASH) += hash.o
obj-$(CONFIG_ANDROID_AB) += android_ab.o
obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o image-android-dt.o
images.os.arch = image_get_arch(os_hdr);
break;
#endif
-#if IMAGE_ENABLE_FIT
+#if CONFIG_IS_ENABLED(FIT)
case IMAGE_FORMAT_FIT:
if (fit_image_get_type(images.fit_hdr_os,
images.fit_noffset_os,
/* Kernel entry point is the setup.bin */
} else if (images.legacy_hdr_valid) {
images.ep = image_get_ep(&images.legacy_hdr_os_copy);
-#if IMAGE_ENABLE_FIT
+#if CONFIG_IS_ENABLED(FIT)
} else if (images.fit_uname_os) {
int ret;
return 1;
}
-#if IMAGE_ENABLE_OF_LIBFDT
+#if CONFIG_IS_ENABLED(OF_LIBFDT)
/* find flattened device tree */
ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, &images,
&images.ft_addr, &images.ft_len);
set_working_fdt_addr(map_to_sysmem(images.ft_addr));
#endif
-#if IMAGE_ENABLE_FIT
-#if defined(CONFIG_FPGA)
- /* find bitstreams */
- ret = boot_get_fpga(argc, argv, &images, IH_ARCH_DEFAULT,
- NULL, NULL);
- if (ret) {
- printf("FPGA image is corrupted or invalid\n");
- return 1;
+#if CONFIG_IS_ENABLED(FIT)
+ if (IS_ENABLED(CONFIG_FPGA)) {
+ /* find bitstreams */
+ ret = boot_get_fpga(argc, argv, &images, IH_ARCH_DEFAULT,
+ NULL, NULL);
+ if (ret) {
+ printf("FPGA image is corrupted or invalid\n");
+ return 1;
+ }
}
-#endif
/* find all of the loadables */
ret = boot_get_loadable(argc, argv, &images, IH_ARCH_DEFAULT,
}
}
#endif
-#if IMAGE_ENABLE_OF_LIBFDT && defined(CONFIG_LMB)
+#if CONFIG_IS_ENABLED(OF_LIBFDT) && defined(CONFIG_LMB)
if (!ret && (states & BOOTM_STATE_FDT)) {
boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr);
ret = boot_relocate_fdt(&images->lmb, &images->ft_addr,
const void *buf;
const char *fit_uname_config = NULL;
const char *fit_uname_kernel = NULL;
-#if IMAGE_ENABLE_FIT
+#if CONFIG_IS_ENABLED(FIT)
int os_noffset;
#endif
bootstage_mark(BOOTSTAGE_ID_DECOMP_IMAGE);
break;
#endif
-#if IMAGE_ENABLE_FIT
+#if CONFIG_IS_ENABLED(FIT)
case IMAGE_FORMAT_FIT:
os_noffset = fit_image_load(images, img_addr,
&fit_uname_kernel, &fit_uname_config,
}
#endif
+static void __maybe_unused fit_unsupported_reset(const char *msg)
+{
+ if (CONFIG_IS_ENABLED(FIT_VERBOSE)) {
+ printf("! FIT images not supported for '%s' - must reset board to recover!\n",
+ msg);
+ }
+}
+
#ifdef CONFIG_BOOTM_NETBSD
static int do_bootm_netbsd(int flag, int argc, char *const argv[],
bootm_headers_t *images)
#include <u-boot/crc.h>
#else
#include "mkimage.h"
+#include <linux/compiler_attributes.h>
#include <time.h>
+#include <linux/kconfig.h>
#endif /* !USE_HOSTCC*/
#include <hash.h>
static void reloc_update(void);
-#if defined(CONFIG_SHA1) && !defined(CONFIG_SHA_PROG_HW_ACCEL)
-static int hash_init_sha1(struct hash_algo *algo, void **ctxp)
+static int __maybe_unused hash_init_sha1(struct hash_algo *algo, void **ctxp)
{
sha1_context *ctx = malloc(sizeof(sha1_context));
sha1_starts(ctx);
return 0;
}
-static int hash_update_sha1(struct hash_algo *algo, void *ctx, const void *buf,
- unsigned int size, int is_last)
+static int __maybe_unused hash_update_sha1(struct hash_algo *algo, void *ctx,
+ const void *buf, unsigned int size,
+ int is_last)
{
sha1_update((sha1_context *)ctx, buf, size);
return 0;
}
-static int hash_finish_sha1(struct hash_algo *algo, void *ctx, void *dest_buf,
- int size)
+static int __maybe_unused hash_finish_sha1(struct hash_algo *algo, void *ctx,
+ void *dest_buf, int size)
{
if (size < algo->digest_size)
return -1;
free(ctx);
return 0;
}
-#endif
-#if defined(CONFIG_SHA256) && !defined(CONFIG_SHA_PROG_HW_ACCEL)
-static int hash_init_sha256(struct hash_algo *algo, void **ctxp)
+static int __maybe_unused hash_init_sha256(struct hash_algo *algo, void **ctxp)
{
sha256_context *ctx = malloc(sizeof(sha256_context));
sha256_starts(ctx);
return 0;
}
-static int hash_update_sha256(struct hash_algo *algo, void *ctx,
- const void *buf, unsigned int size, int is_last)
+static int __maybe_unused hash_update_sha256(struct hash_algo *algo, void *ctx,
+ const void *buf, uint size,
+ int is_last)
{
sha256_update((sha256_context *)ctx, buf, size);
return 0;
}
-static int hash_finish_sha256(struct hash_algo *algo, void *ctx, void
- *dest_buf, int size)
+static int __maybe_unused hash_finish_sha256(struct hash_algo *algo, void *ctx,
+ void *dest_buf, int size)
{
if (size < algo->digest_size)
return -1;
free(ctx);
return 0;
}
-#endif
-#if defined(CONFIG_SHA384) && !defined(CONFIG_SHA_PROG_HW_ACCEL)
-static int hash_init_sha384(struct hash_algo *algo, void **ctxp)
+static int __maybe_unused hash_init_sha384(struct hash_algo *algo, void **ctxp)
{
sha512_context *ctx = malloc(sizeof(sha512_context));
sha384_starts(ctx);
return 0;
}
-static int hash_update_sha384(struct hash_algo *algo, void *ctx,
- const void *buf, unsigned int size, int is_last)
+static int __maybe_unused hash_update_sha384(struct hash_algo *algo, void *ctx,
+ const void *buf, uint size,
+ int is_last)
{
sha384_update((sha512_context *)ctx, buf, size);
return 0;
}
-static int hash_finish_sha384(struct hash_algo *algo, void *ctx, void
- *dest_buf, int size)
+static int __maybe_unused hash_finish_sha384(struct hash_algo *algo, void *ctx,
+ void *dest_buf, int size)
{
if (size < algo->digest_size)
return -1;
free(ctx);
return 0;
}
-#endif
-#if defined(CONFIG_SHA512) && !defined(CONFIG_SHA_PROG_HW_ACCEL)
-static int hash_init_sha512(struct hash_algo *algo, void **ctxp)
+static int __maybe_unused hash_init_sha512(struct hash_algo *algo, void **ctxp)
{
sha512_context *ctx = malloc(sizeof(sha512_context));
sha512_starts(ctx);
return 0;
}
-static int hash_update_sha512(struct hash_algo *algo, void *ctx,
- const void *buf, unsigned int size, int is_last)
+static int __maybe_unused hash_update_sha512(struct hash_algo *algo, void *ctx,
+ const void *buf, uint size,
+ int is_last)
{
sha512_update((sha512_context *)ctx, buf, size);
return 0;
}
-static int hash_finish_sha512(struct hash_algo *algo, void *ctx, void
- *dest_buf, int size)
+static int __maybe_unused hash_finish_sha512(struct hash_algo *algo, void *ctx,
+ void *dest_buf, int size)
{
if (size < algo->digest_size)
return -1;
free(ctx);
return 0;
}
-#endif
-
static int hash_init_crc16_ccitt(struct hash_algo *algo, void **ctxp)
{
return 0;
}
-static int hash_init_crc32(struct hash_algo *algo, void **ctxp)
+static int __maybe_unused hash_init_crc32(struct hash_algo *algo, void **ctxp)
{
uint32_t *ctx = malloc(sizeof(uint32_t));
*ctx = 0;
return 0;
}
-static int hash_update_crc32(struct hash_algo *algo, void *ctx,
- const void *buf, unsigned int size, int is_last)
+static int __maybe_unused hash_update_crc32(struct hash_algo *algo, void *ctx,
+ const void *buf, unsigned int size,
+ int is_last)
{
*((uint32_t *)ctx) = crc32(*((uint32_t *)ctx), buf, size);
return 0;
}
-static int hash_finish_crc32(struct hash_algo *algo, void *ctx, void *dest_buf,
- int size)
+static int __maybe_unused hash_finish_crc32(struct hash_algo *algo, void *ctx,
+ void *dest_buf, int size)
{
if (size < algo->digest_size)
return -1;
return 0;
}
-#ifdef USE_HOSTCC
-# define I_WANT_MD5 1
-#else
-# define I_WANT_MD5 CONFIG_IS_ENABLED(MD5)
-#endif
/*
* These are the hash algorithms we support. If we have hardware acceleration
* is enable we will use that, otherwise a software version of the algorithm.
* Note that algorithm names must be in lower case.
*/
static struct hash_algo hash_algo[] = {
-#if I_WANT_MD5
+#if CONFIG_IS_ENABLED(MD5)
{
.name = "md5",
.digest_size = MD5_SUM_LEN,
.hash_func_ws = md5_wd,
},
#endif
-#ifdef CONFIG_SHA1
+#if CONFIG_IS_ENABLED(SHA1)
{
.name = "sha1",
.digest_size = SHA1_SUM_LEN,
.chunk_size = CHUNKSZ_SHA1,
-#ifdef CONFIG_SHA_HW_ACCEL
+#if CONFIG_IS_ENABLED(SHA_HW_ACCEL)
.hash_func_ws = hw_sha1,
#else
.hash_func_ws = sha1_csum_wd,
#endif
-#ifdef CONFIG_SHA_PROG_HW_ACCEL
+#if CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL)
.hash_init = hw_sha_init,
.hash_update = hw_sha_update,
.hash_finish = hw_sha_finish,
#endif
},
#endif
-#ifdef CONFIG_SHA256
+#if CONFIG_IS_ENABLED(SHA256)
{
.name = "sha256",
.digest_size = SHA256_SUM_LEN,
.chunk_size = CHUNKSZ_SHA256,
-#ifdef CONFIG_SHA_HW_ACCEL
+#if CONFIG_IS_ENABLED(SHA_HW_ACCEL)
.hash_func_ws = hw_sha256,
#else
.hash_func_ws = sha256_csum_wd,
#endif
-#ifdef CONFIG_SHA_PROG_HW_ACCEL
+#if CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL)
.hash_init = hw_sha_init,
.hash_update = hw_sha_update,
.hash_finish = hw_sha_finish,
#endif
},
#endif
-#ifdef CONFIG_SHA384
+#if CONFIG_IS_ENABLED(SHA384)
{
.name = "sha384",
.digest_size = SHA384_SUM_LEN,
.chunk_size = CHUNKSZ_SHA384,
-#ifdef CONFIG_SHA512_HW_ACCEL
+#if CONFIG_IS_ENABLED(SHA512_HW_ACCEL)
.hash_func_ws = hw_sha384,
#else
.hash_func_ws = sha384_csum_wd,
#endif
-#if defined(CONFIG_SHA512_HW_ACCEL) && defined(CONFIG_SHA_PROG_HW_ACCEL)
+#if CONFIG_IS_ENABLED(SHA512_HW_ACCEL) && CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL)
.hash_init = hw_sha_init,
.hash_update = hw_sha_update,
.hash_finish = hw_sha_finish,
#endif
},
#endif
-#ifdef CONFIG_SHA512
+#if CONFIG_IS_ENABLED(SHA512)
{
.name = "sha512",
.digest_size = SHA512_SUM_LEN,
.chunk_size = CHUNKSZ_SHA512,
-#ifdef CONFIG_SHA512_HW_ACCEL
+#if CONFIG_IS_ENABLED(SHA512_HW_ACCEL)
.hash_func_ws = hw_sha512,
#else
.hash_func_ws = sha512_csum_wd,
#endif
-#if defined(CONFIG_SHA512_HW_ACCEL) && defined(CONFIG_SHA_PROG_HW_ACCEL)
+#if CONFIG_IS_ENABLED(SHA512_HW_ACCEL) && CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL)
.hash_init = hw_sha_init,
.hash_update = hw_sha_update,
.hash_finish = hw_sha_finish,
.hash_update = hash_update_crc16_ccitt,
.hash_finish = hash_finish_crc16_ccitt,
},
+#if CONFIG_IS_ENABLED(CRC32)
{
.name = "crc32",
.digest_size = 4,
.hash_update = hash_update_crc32,
.hash_finish = hash_finish_crc32,
},
+#endif
};
/* Try to minimize code size for boards that don't want much hashing */
-#if defined(CONFIG_SHA256) || defined(CONFIG_CMD_SHA1SUM) || \
- defined(CONFIG_CRC32_VERIFY) || defined(CONFIG_CMD_HASH) || \
- defined(CONFIG_SHA384) || defined(CONFIG_SHA512)
+#if CONFIG_IS_ENABLED(SHA256) || CONFIG_IS_ENABLED(CMD_SHA1SUM) || \
+ CONFIG_IS_ENABLED(CRC32_VERIFY) || CONFIG_IS_ENABLED(CMD_HASH) || \
+ CONFIG_IS_ENABLED(SHA384) || CONFIG_IS_ENABLED(SHA512)
#define multi_hash() 1
#else
#define multi_hash() 0
return 0;
}
-#if defined(CONFIG_CMD_HASH) || defined(CONFIG_CMD_SHA1SUM) || defined(CONFIG_CMD_CRC32)
+#if !defined(CONFIG_SPL_BUILD) && (defined(CONFIG_CMD_HASH) || \
+ defined(CONFIG_CMD_SHA1SUM) || defined(CONFIG_CMD_CRC32))
/**
* store_result: Store the resulting sum to an address or variable
*
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Image code used by boards (and not host tools)
+ *
+ * (C) Copyright 2008 Semihalf
+ *
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <bootstage.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <fpga.h>
+#include <image.h>
+#include <mapmem.h>
+#include <rtc.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+
+#ifndef CONFIG_SYS_BARGSIZE
+#define CONFIG_SYS_BARGSIZE 512
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * image_get_ramdisk - get and verify ramdisk image
+ * @rd_addr: ramdisk image start address
+ * @arch: expected ramdisk architecture
+ * @verify: checksum verification flag
+ *
+ * image_get_ramdisk() returns a pointer to the verified ramdisk image
+ * header. Routine receives image start address and expected architecture
+ * flag. Verification done covers data and header integrity and os/type/arch
+ * fields checking.
+ *
+ * returns:
+ * pointer to a ramdisk image header, if image was found and valid
+ * otherwise, return NULL
+ */
+static const image_header_t *image_get_ramdisk(ulong rd_addr, u8 arch,
+ int verify)
+{
+ const image_header_t *rd_hdr = (const image_header_t *)rd_addr;
+
+ if (!image_check_magic(rd_hdr)) {
+ puts("Bad Magic Number\n");
+ bootstage_error(BOOTSTAGE_ID_RD_MAGIC);
+ return NULL;
+ }
+
+ if (!image_check_hcrc(rd_hdr)) {
+ puts("Bad Header Checksum\n");
+ bootstage_error(BOOTSTAGE_ID_RD_HDR_CHECKSUM);
+ return NULL;
+ }
+
+ bootstage_mark(BOOTSTAGE_ID_RD_MAGIC);
+ image_print_contents(rd_hdr);
+
+ if (verify) {
+ puts(" Verifying Checksum ... ");
+ if (!image_check_dcrc(rd_hdr)) {
+ puts("Bad Data CRC\n");
+ bootstage_error(BOOTSTAGE_ID_RD_CHECKSUM);
+ return NULL;
+ }
+ puts("OK\n");
+ }
+
+ bootstage_mark(BOOTSTAGE_ID_RD_HDR_CHECKSUM);
+
+ if (!image_check_os(rd_hdr, IH_OS_LINUX) ||
+ !image_check_arch(rd_hdr, arch) ||
+ !image_check_type(rd_hdr, IH_TYPE_RAMDISK)) {
+ printf("No Linux %s Ramdisk Image\n",
+ genimg_get_arch_name(arch));
+ bootstage_error(BOOTSTAGE_ID_RAMDISK);
+ return NULL;
+ }
+
+ return rd_hdr;
+}
+
+/*****************************************************************************/
+/* Shared dual-format routines */
+/*****************************************************************************/
+ulong image_load_addr = CONFIG_SYS_LOAD_ADDR; /* Default Load Address */
+ulong image_save_addr; /* Default Save Address */
+ulong image_save_size; /* Default Save Size (in bytes) */
+
+static int on_loadaddr(const char *name, const char *value, enum env_op op,
+ int flags)
+{
+ switch (op) {
+ case env_op_create:
+ case env_op_overwrite:
+ image_load_addr = hextoul(value, NULL);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+U_BOOT_ENV_CALLBACK(loadaddr, on_loadaddr);
+
+ulong env_get_bootm_low(void)
+{
+ char *s = env_get("bootm_low");
+
+ if (s) {
+ ulong tmp = hextoul(s, NULL);
+ return tmp;
+ }
+
+#if defined(CONFIG_SYS_SDRAM_BASE)
+ return CONFIG_SYS_SDRAM_BASE;
+#elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV)
+ return gd->bd->bi_dram[0].start;
+#else
+ return 0;
+#endif
+}
+
+phys_size_t env_get_bootm_size(void)
+{
+ phys_size_t tmp, size;
+ phys_addr_t start;
+ char *s = env_get("bootm_size");
+
+ if (s) {
+ tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
+ return tmp;
+ }
+
+ start = gd->ram_base;
+ size = gd->ram_size;
+
+ if (start + size > gd->ram_top)
+ size = gd->ram_top - start;
+
+ s = env_get("bootm_low");
+ if (s)
+ tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
+ else
+ tmp = start;
+
+ return size - (tmp - start);
+}
+
+phys_size_t env_get_bootm_mapsize(void)
+{
+ phys_size_t tmp;
+ char *s = env_get("bootm_mapsize");
+
+ if (s) {
+ tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
+ return tmp;
+ }
+
+#if defined(CONFIG_SYS_BOOTMAPSZ)
+ return CONFIG_SYS_BOOTMAPSZ;
+#else
+ return env_get_bootm_size();
+#endif
+}
+
+void memmove_wd(void *to, void *from, size_t len, ulong chunksz)
+{
+ if (to == from)
+ return;
+
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ if (to > from) {
+ from += len;
+ to += len;
+ }
+ while (len > 0) {
+ size_t tail = (len > chunksz) ? chunksz : len;
+
+ WATCHDOG_RESET();
+ if (to > from) {
+ to -= tail;
+ from -= tail;
+ }
+ memmove(to, from, tail);
+ if (to < from) {
+ to += tail;
+ from += tail;
+ }
+ len -= tail;
+ }
+#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */
+ memmove(to, from, len);
+#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
+}
+
+/**
+ * genimg_get_kernel_addr_fit - get the real kernel address and return 2
+ * FIT strings
+ * @img_addr: a string might contain real image address
+ * @fit_uname_config: double pointer to a char, will hold pointer to a
+ * configuration unit name
+ * @fit_uname_kernel: double pointer to a char, will hold pointer to a subimage
+ * name
+ *
+ * genimg_get_kernel_addr_fit get the real kernel start address from a string
+ * which is normally the first argv of bootm/bootz
+ *
+ * returns:
+ * kernel start address
+ */
+ulong genimg_get_kernel_addr_fit(char * const img_addr,
+ const char **fit_uname_config,
+ const char **fit_uname_kernel)
+{
+ ulong kernel_addr;
+
+ /* find out kernel image address */
+ if (!img_addr) {
+ kernel_addr = image_load_addr;
+ debug("* kernel: default image load address = 0x%08lx\n",
+ image_load_addr);
+ } else if (CONFIG_IS_ENABLED(FIT) &&
+ fit_parse_conf(img_addr, image_load_addr, &kernel_addr,
+ fit_uname_config)) {
+ debug("* kernel: config '%s' from image at 0x%08lx\n",
+ *fit_uname_config, kernel_addr);
+ } else if (CONFIG_IS_ENABLED(FIT) &&
+ fit_parse_subimage(img_addr, image_load_addr, &kernel_addr,
+ fit_uname_kernel)) {
+ debug("* kernel: subimage '%s' from image at 0x%08lx\n",
+ *fit_uname_kernel, kernel_addr);
+ } else {
+ kernel_addr = hextoul(img_addr, NULL);
+ debug("* kernel: cmdline image address = 0x%08lx\n",
+ kernel_addr);
+ }
+
+ return kernel_addr;
+}
+
+/**
+ * genimg_get_kernel_addr() is the simple version of
+ * genimg_get_kernel_addr_fit(). It ignores those return FIT strings
+ */
+ulong genimg_get_kernel_addr(char * const img_addr)
+{
+ const char *fit_uname_config = NULL;
+ const char *fit_uname_kernel = NULL;
+
+ return genimg_get_kernel_addr_fit(img_addr, &fit_uname_config,
+ &fit_uname_kernel);
+}
+
+/**
+ * genimg_get_format - get image format type
+ * @img_addr: image start address
+ *
+ * genimg_get_format() checks whether provided address points to a valid
+ * legacy or FIT image.
+ *
+ * New uImage format and FDT blob are based on a libfdt. FDT blob
+ * may be passed directly or embedded in a FIT image. In both situations
+ * genimg_get_format() must be able to dectect libfdt header.
+ *
+ * returns:
+ * image format type or IMAGE_FORMAT_INVALID if no image is present
+ */
+int genimg_get_format(const void *img_addr)
+{
+ if (CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)) {
+ const image_header_t *hdr;
+
+ hdr = (const image_header_t *)img_addr;
+ if (image_check_magic(hdr))
+ return IMAGE_FORMAT_LEGACY;
+ }
+ if (CONFIG_IS_ENABLED(FIT) || CONFIG_IS_ENABLED(OF_LIBFDT)) {
+ if (!fdt_check_header(img_addr))
+ return IMAGE_FORMAT_FIT;
+ }
+ if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE) &&
+ !android_image_check_header(img_addr))
+ return IMAGE_FORMAT_ANDROID;
+
+ return IMAGE_FORMAT_INVALID;
+}
+
+/**
+ * fit_has_config - check if there is a valid FIT configuration
+ * @images: pointer to the bootm command headers structure
+ *
+ * fit_has_config() checks if there is a FIT configuration in use
+ * (if FTI support is present).
+ *
+ * returns:
+ * 0, no FIT support or no configuration found
+ * 1, configuration found
+ */
+int genimg_has_config(bootm_headers_t *images)
+{
+ if (CONFIG_IS_ENABLED(FIT) && images->fit_uname_cfg)
+ return 1;
+
+ return 0;
+}
+
+/**
+ * select_ramdisk() - Select and locate the ramdisk to use
+ *
+ * @images: pointer to the bootm images structure
+ * @select: name of ramdisk to select, or NULL for any
+ * @arch: expected ramdisk architecture
+ * @rd_datap: pointer to a ulong variable, will hold ramdisk pointer
+ * @rd_lenp: pointer to a ulong variable, will hold ramdisk length
+ * @return 0 if OK, -ENOPKG if no ramdisk (but an error should not be reported),
+ * other -ve value on other error
+ */
+static int select_ramdisk(bootm_headers_t *images, const char *select, u8 arch,
+ ulong *rd_datap, ulong *rd_lenp)
+{
+ ulong rd_addr = 0;
+ char *buf;
+ const char *fit_uname_config = images->fit_uname_cfg;
+ const char *fit_uname_ramdisk = NULL;
+ bool processed;
+ int rd_noffset;
+
+ if (select) {
+ ulong default_addr;
+ bool done = true;
+
+ if (CONFIG_IS_ENABLED(FIT)) {
+ /*
+ * If the init ramdisk comes from the FIT image and
+ * the FIT image address is omitted in the command
+ * line argument, try to use os FIT image address or
+ * default load address.
+ */
+ if (images->fit_uname_os)
+ default_addr = (ulong)images->fit_hdr_os;
+ else
+ default_addr = image_load_addr;
+
+ if (fit_parse_conf(select, default_addr, &rd_addr,
+ &fit_uname_config)) {
+ debug("* ramdisk: config '%s' from image at 0x%08lx\n",
+ fit_uname_config, rd_addr);
+ } else if (fit_parse_subimage(select, default_addr,
+ &rd_addr,
+ &fit_uname_ramdisk)) {
+ debug("* ramdisk: subimage '%s' from image at 0x%08lx\n",
+ fit_uname_ramdisk, rd_addr);
+ } else {
+ done = false;
+ }
+ }
+ if (!done) {
+ rd_addr = hextoul(select, NULL);
+ debug("* ramdisk: cmdline image address = 0x%08lx\n",
+ rd_addr);
+ }
+ } else if (CONFIG_IS_ENABLED(FIT)) {
+ /* use FIT configuration provided in first bootm
+ * command argument. If the property is not defined,
+ * quit silently (with -ENOPKG )
+ */
+ rd_addr = map_to_sysmem(images->fit_hdr_os);
+ rd_noffset = fit_get_node_from_config(images, FIT_RAMDISK_PROP,
+ rd_addr);
+ if (rd_noffset == -ENOENT)
+ return -ENOPKG;
+ else if (rd_noffset < 0)
+ return rd_noffset;
+ }
+
+ /*
+ * Check if there is an initrd image at the
+ * address provided in the second bootm argument
+ * check image type, for FIT images get FIT node.
+ */
+ buf = map_sysmem(rd_addr, 0);
+ processed = false;
+ switch (genimg_get_format(buf)) {
+ case IMAGE_FORMAT_LEGACY:
+ if (CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)) {
+ const image_header_t *rd_hdr;
+
+ printf("## Loading init Ramdisk from Legacy Image at %08lx ...\n",
+ rd_addr);
+
+ bootstage_mark(BOOTSTAGE_ID_CHECK_RAMDISK);
+ rd_hdr = image_get_ramdisk(rd_addr, arch, images->verify);
+ if (!rd_hdr)
+ return -ENOENT;
+
+ *rd_datap = image_get_data(rd_hdr);
+ *rd_lenp = image_get_data_size(rd_hdr);
+ processed = true;
+ }
+ break;
+ case IMAGE_FORMAT_FIT:
+ if (CONFIG_IS_ENABLED(FIT)) {
+ rd_noffset = fit_image_load(images, rd_addr,
+ &fit_uname_ramdisk,
+ &fit_uname_config, arch,
+ IH_TYPE_RAMDISK,
+ BOOTSTAGE_ID_FIT_RD_START,
+ FIT_LOAD_OPTIONAL_NON_ZERO,
+ rd_datap, rd_lenp);
+ if (rd_noffset < 0)
+ return rd_noffset;
+
+ images->fit_hdr_rd = map_sysmem(rd_addr, 0);
+ images->fit_uname_rd = fit_uname_ramdisk;
+ images->fit_noffset_rd = rd_noffset;
+ processed = true;
+ }
+ break;
+ case IMAGE_FORMAT_ANDROID:
+ if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) {
+ android_image_get_ramdisk((void *)images->os.start,
+ rd_datap, rd_lenp);
+ processed = true;
+ }
+ break;
+ }
+
+ if (!processed) {
+ if (IS_ENABLED(CONFIG_SUPPORT_RAW_INITRD)) {
+ char *end = NULL;
+
+ if (select)
+ end = strchr(select, ':');
+ if (end) {
+ *rd_lenp = hextoul(++end, NULL);
+ *rd_datap = rd_addr;
+ processed = true;
+ }
+ }
+
+ if (!processed) {
+ puts("Wrong Ramdisk Image Format\n");
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * boot_get_ramdisk - main ramdisk handling routine
+ * @argc: command argument count
+ * @argv: command argument list
+ * @images: pointer to the bootm images structure
+ * @arch: expected ramdisk architecture
+ * @rd_start: pointer to a ulong variable, will hold ramdisk start address
+ * @rd_end: pointer to a ulong variable, will hold ramdisk end
+ *
+ * boot_get_ramdisk() is responsible for finding a valid ramdisk image.
+ * Currently supported are the following ramdisk sources:
+ * - multicomponent kernel/ramdisk image,
+ * - commandline provided address of decicated ramdisk image.
+ *
+ * returns:
+ * 0, if ramdisk image was found and valid, or skiped
+ * rd_start and rd_end are set to ramdisk start/end addresses if
+ * ramdisk image is found and valid
+ *
+ * 1, if ramdisk image is found but corrupted, or invalid
+ * rd_start and rd_end are set to 0 if no ramdisk exists
+ */
+int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images,
+ u8 arch, ulong *rd_start, ulong *rd_end)
+{
+ ulong rd_data, rd_len;
+ const char *select = NULL;
+
+ *rd_start = 0;
+ *rd_end = 0;
+
+ if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) {
+ char *buf;
+
+ /* Look for an Android boot image */
+ buf = map_sysmem(images->os.start, 0);
+ if (buf && genimg_get_format(buf) == IMAGE_FORMAT_ANDROID)
+ select = (argc == 0) ? env_get("loadaddr") : argv[0];
+ }
+
+ if (argc >= 2)
+ select = argv[1];
+
+ /*
+ * Look for a '-' which indicates to ignore the
+ * ramdisk argument
+ */
+ if (select && strcmp(select, "-") == 0) {
+ debug("## Skipping init Ramdisk\n");
+ rd_len = 0;
+ rd_data = 0;
+ } else if (select || genimg_has_config(images)) {
+ int ret;
+
+ ret = select_ramdisk(images, select, arch, &rd_data, &rd_len);
+ if (ret == -ENOPKG)
+ return 0;
+ else if (ret)
+ return ret;
+ } else if (images->legacy_hdr_valid &&
+ image_check_type(&images->legacy_hdr_os_copy,
+ IH_TYPE_MULTI)) {
+ /*
+ * Now check if we have a legacy mult-component image,
+ * get second entry data start address and len.
+ */
+ bootstage_mark(BOOTSTAGE_ID_RAMDISK);
+ printf("## Loading init Ramdisk from multi component Legacy Image at %08lx ...\n",
+ (ulong)images->legacy_hdr_os);
+
+ image_multi_getimg(images->legacy_hdr_os, 1, &rd_data, &rd_len);
+ } else {
+ /*
+ * no initrd image
+ */
+ bootstage_mark(BOOTSTAGE_ID_NO_RAMDISK);
+ rd_len = 0;
+ rd_data = 0;
+ }
+
+ if (!rd_data) {
+ debug("## No init Ramdisk\n");
+ } else {
+ *rd_start = rd_data;
+ *rd_end = rd_data + rd_len;
+ }
+ debug(" ramdisk start = 0x%08lx, ramdisk end = 0x%08lx\n",
+ *rd_start, *rd_end);
+
+ return 0;
+}
+
+/**
+ * boot_ramdisk_high - relocate init ramdisk
+ * @lmb: pointer to lmb handle, will be used for memory mgmt
+ * @rd_data: ramdisk data start address
+ * @rd_len: ramdisk data length
+ * @initrd_start: pointer to a ulong variable, will hold final init ramdisk
+ * start address (after possible relocation)
+ * @initrd_end: pointer to a ulong variable, will hold final init ramdisk
+ * end address (after possible relocation)
+ *
+ * boot_ramdisk_high() takes a relocation hint from "initrd_high" environment
+ * variable and if requested ramdisk data is moved to a specified location.
+ *
+ * Initrd_start and initrd_end are set to final (after relocation) ramdisk
+ * start/end addresses if ramdisk image start and len were provided,
+ * otherwise set initrd_start and initrd_end set to zeros.
+ *
+ * returns:
+ * 0 - success
+ * -1 - failure
+ */
+int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len,
+ ulong *initrd_start, ulong *initrd_end)
+{
+ char *s;
+ ulong initrd_high;
+ int initrd_copy_to_ram = 1;
+
+ s = env_get("initrd_high");
+ if (s) {
+ /* a value of "no" or a similar string will act like 0,
+ * turning the "load high" feature off. This is intentional.
+ */
+ initrd_high = hextoul(s, NULL);
+ if (initrd_high == ~0)
+ initrd_copy_to_ram = 0;
+ } else {
+ initrd_high = env_get_bootm_mapsize() + env_get_bootm_low();
+ }
+
+ debug("## initrd_high = 0x%08lx, copy_to_ram = %d\n",
+ initrd_high, initrd_copy_to_ram);
+
+ if (rd_data) {
+ if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */
+ debug(" in-place initrd\n");
+ *initrd_start = rd_data;
+ *initrd_end = rd_data + rd_len;
+ lmb_reserve(lmb, rd_data, rd_len);
+ } else {
+ if (initrd_high)
+ *initrd_start = (ulong)lmb_alloc_base(lmb,
+ rd_len, 0x1000, initrd_high);
+ else
+ *initrd_start = (ulong)lmb_alloc(lmb, rd_len,
+ 0x1000);
+
+ if (*initrd_start == 0) {
+ puts("ramdisk - allocation error\n");
+ goto error;
+ }
+ bootstage_mark(BOOTSTAGE_ID_COPY_RAMDISK);
+
+ *initrd_end = *initrd_start + rd_len;
+ printf(" Loading Ramdisk to %08lx, end %08lx ... ",
+ *initrd_start, *initrd_end);
+
+ memmove_wd((void *)*initrd_start,
+ (void *)rd_data, rd_len, CHUNKSZ);
+
+ /*
+ * Ensure the image is flushed to memory to handle
+ * AMP boot scenarios in which we might not be
+ * HW cache coherent
+ */
+ if (IS_ENABLED(CONFIG_MP)) {
+ flush_cache((unsigned long)*initrd_start,
+ ALIGN(rd_len, ARCH_DMA_MINALIGN));
+ }
+ puts("OK\n");
+ }
+ } else {
+ *initrd_start = 0;
+ *initrd_end = 0;
+ }
+ debug(" ramdisk load start = 0x%08lx, ramdisk load end = 0x%08lx\n",
+ *initrd_start, *initrd_end);
+
+ return 0;
+
+error:
+ return -1;
+}
+
+int boot_get_setup(bootm_headers_t *images, u8 arch,
+ ulong *setup_start, ulong *setup_len)
+{
+ if (!CONFIG_IS_ENABLED(FIT))
+ return -ENOENT;
+
+ return boot_get_setup_fit(images, arch, setup_start, setup_len);
+}
+
+int boot_get_fpga(int argc, char *const argv[], bootm_headers_t *images,
+ u8 arch, const ulong *ld_start, ulong * const ld_len)
+{
+ ulong tmp_img_addr, img_data, img_len;
+ void *buf;
+ int conf_noffset;
+ int fit_img_result;
+ const char *uname, *name;
+ int err;
+ int devnum = 0; /* TODO support multi fpga platforms */
+
+ if (!IS_ENABLED(CONFIG_FPGA))
+ return -ENOSYS;
+
+ /* Check to see if the images struct has a FIT configuration */
+ if (!genimg_has_config(images)) {
+ debug("## FIT configuration was not specified\n");
+ return 0;
+ }
+
+ /*
+ * Obtain the os FIT header from the images struct
+ */
+ tmp_img_addr = map_to_sysmem(images->fit_hdr_os);
+ buf = map_sysmem(tmp_img_addr, 0);
+ /*
+ * Check image type. For FIT images get FIT node
+ * and attempt to locate a generic binary.
+ */
+ switch (genimg_get_format(buf)) {
+ case IMAGE_FORMAT_FIT:
+ conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg);
+
+ uname = fdt_stringlist_get(buf, conf_noffset, FIT_FPGA_PROP, 0,
+ NULL);
+ if (!uname) {
+ debug("## FPGA image is not specified\n");
+ return 0;
+ }
+ fit_img_result = fit_image_load(images,
+ tmp_img_addr,
+ (const char **)&uname,
+ &images->fit_uname_cfg,
+ arch,
+ IH_TYPE_FPGA,
+ BOOTSTAGE_ID_FPGA_INIT,
+ FIT_LOAD_OPTIONAL_NON_ZERO,
+ &img_data, &img_len);
+
+ debug("FPGA image (%s) loaded to 0x%lx/size 0x%lx\n",
+ uname, img_data, img_len);
+
+ if (fit_img_result < 0) {
+ /* Something went wrong! */
+ return fit_img_result;
+ }
+
+ if (!fpga_is_partial_data(devnum, img_len)) {
+ name = "full";
+ err = fpga_loadbitstream(devnum, (char *)img_data,
+ img_len, BIT_FULL);
+ if (err)
+ err = fpga_load(devnum, (const void *)img_data,
+ img_len, BIT_FULL);
+ } else {
+ name = "partial";
+ err = fpga_loadbitstream(devnum, (char *)img_data,
+ img_len, BIT_PARTIAL);
+ if (err)
+ err = fpga_load(devnum, (const void *)img_data,
+ img_len, BIT_PARTIAL);
+ }
+
+ if (err)
+ return err;
+
+ printf(" Programming %s bitstream... OK\n", name);
+ break;
+ default:
+ printf("The given image format is not supported (corrupt?)\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+static void fit_loadable_process(u8 img_type,
+ ulong img_data,
+ ulong img_len)
+{
+ int i;
+ const unsigned int count =
+ ll_entry_count(struct fit_loadable_tbl, fit_loadable);
+ struct fit_loadable_tbl *fit_loadable_handler =
+ ll_entry_start(struct fit_loadable_tbl, fit_loadable);
+ /* For each loadable handler */
+ for (i = 0; i < count; i++, fit_loadable_handler++)
+ /* matching this type */
+ if (fit_loadable_handler->type == img_type)
+ /* call that handler with this image data */
+ fit_loadable_handler->handler(img_data, img_len);
+}
+
+int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images,
+ u8 arch, const ulong *ld_start, ulong * const ld_len)
+{
+ /*
+ * These variables are used to hold the current image location
+ * in system memory.
+ */
+ ulong tmp_img_addr;
+ /*
+ * These two variables are requirements for fit_image_load, but
+ * their values are not used
+ */
+ ulong img_data, img_len;
+ void *buf;
+ int loadables_index;
+ int conf_noffset;
+ int fit_img_result;
+ const char *uname;
+ u8 img_type;
+
+ /* Check to see if the images struct has a FIT configuration */
+ if (!genimg_has_config(images)) {
+ debug("## FIT configuration was not specified\n");
+ return 0;
+ }
+
+ /*
+ * Obtain the os FIT header from the images struct
+ */
+ tmp_img_addr = map_to_sysmem(images->fit_hdr_os);
+ buf = map_sysmem(tmp_img_addr, 0);
+ /*
+ * Check image type. For FIT images get FIT node
+ * and attempt to locate a generic binary.
+ */
+ switch (genimg_get_format(buf)) {
+ case IMAGE_FORMAT_FIT:
+ conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg);
+
+ for (loadables_index = 0;
+ uname = fdt_stringlist_get(buf, conf_noffset,
+ FIT_LOADABLE_PROP,
+ loadables_index, NULL), uname;
+ loadables_index++) {
+ fit_img_result = fit_image_load(images, tmp_img_addr,
+ &uname,
+ &images->fit_uname_cfg,
+ arch, IH_TYPE_LOADABLE,
+ BOOTSTAGE_ID_FIT_LOADABLE_START,
+ FIT_LOAD_OPTIONAL_NON_ZERO,
+ &img_data, &img_len);
+ if (fit_img_result < 0) {
+ /* Something went wrong! */
+ return fit_img_result;
+ }
+
+ fit_img_result = fit_image_get_node(buf, uname);
+ if (fit_img_result < 0) {
+ /* Something went wrong! */
+ return fit_img_result;
+ }
+ fit_img_result = fit_image_get_type(buf,
+ fit_img_result,
+ &img_type);
+ if (fit_img_result < 0) {
+ /* Something went wrong! */
+ return fit_img_result;
+ }
+
+ fit_loadable_process(img_type, img_data, img_len);
+ }
+ break;
+ default:
+ printf("The given image format is not supported (corrupt?)\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+/**
+ * boot_get_cmdline - allocate and initialize kernel cmdline
+ * @lmb: pointer to lmb handle, will be used for memory mgmt
+ * @cmd_start: pointer to a ulong variable, will hold cmdline start
+ * @cmd_end: pointer to a ulong variable, will hold cmdline end
+ *
+ * boot_get_cmdline() allocates space for kernel command line below
+ * BOOTMAPSZ + env_get_bootm_low() address. If "bootargs" U-Boot environment
+ * variable is present its contents is copied to allocated kernel
+ * command line.
+ *
+ * returns:
+ * 0 - success
+ * -1 - failure
+ */
+int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end)
+{
+ char *cmdline;
+ char *s;
+
+ cmdline = (char *)(ulong)lmb_alloc_base(lmb, CONFIG_SYS_BARGSIZE, 0xf,
+ env_get_bootm_mapsize() + env_get_bootm_low());
+ if (!cmdline)
+ return -1;
+
+ s = env_get("bootargs");
+ if (!s)
+ s = "";
+
+ strcpy(cmdline, s);
+
+ *cmd_start = (ulong)cmdline;
+ *cmd_end = *cmd_start + strlen(cmdline);
+
+ debug("## cmdline at 0x%08lx ... 0x%08lx\n", *cmd_start, *cmd_end);
+
+ return 0;
+}
+
+/**
+ * boot_get_kbd - allocate and initialize kernel copy of board info
+ * @lmb: pointer to lmb handle, will be used for memory mgmt
+ * @kbd: double pointer to board info data
+ *
+ * boot_get_kbd() allocates space for kernel copy of board info data below
+ * BOOTMAPSZ + env_get_bootm_low() address and kernel board info is initialized
+ * with the current u-boot board info data.
+ *
+ * returns:
+ * 0 - success
+ * -1 - failure
+ */
+int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd)
+{
+ *kbd = (struct bd_info *)(ulong)lmb_alloc_base(lmb,
+ sizeof(struct bd_info),
+ 0xf,
+ env_get_bootm_mapsize() +
+ env_get_bootm_low());
+ if (!*kbd)
+ return -1;
+
+ **kbd = *gd->bd;
+
+ debug("## kernel board info at 0x%08lx\n", (ulong)*kbd);
+
+#if defined(DEBUG)
+ if (IS_ENABLED(CONFIG_CMD_BDI)
+ do_bdinfo(NULL, 0, 0, NULL);
+#endif
+
+ return 0;
+}
+
+int image_setup_linux(bootm_headers_t *images)
+{
+ ulong of_size = images->ft_len;
+ char **of_flat_tree = &images->ft_addr;
+ struct lmb *lmb = &images->lmb;
+ int ret;
+
+ if (CONFIG_IS_ENABLED(OF_LIBFDT))
+ boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree);
+
+ if (IS_ENABLED(CONFIG_SYS_BOOT_GET_CMDLINE)) {
+ ret = boot_get_cmdline(lmb, &images->cmdline_start,
+ &images->cmdline_end);
+ if (ret) {
+ puts("ERROR with allocation of cmdline\n");
+ return ret;
+ }
+ }
+
+ if (CONFIG_IS_ENABLED(OF_LIBFDT)) {
+ ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size);
+ if (ret)
+ return ret;
+ }
+
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && of_size) {
+ ret = image_setup_libfdt(images, *of_flat_tree, of_size, lmb);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+void genimg_print_size(uint32_t size)
+{
+ printf("%d Bytes = ", size);
+ print_size(size, "\n");
+}
+
+void genimg_print_time(time_t timestamp)
+{
+ struct rtc_time tm;
+
+ rtc_to_tm(timestamp, &tm);
+ printf("%4d-%02d-%02d %2d:%02d:%02d UTC\n",
+ tm.tm_year, tm.tm_mon, tm.tm_mday,
+ tm.tm_hour, tm.tm_min, tm.tm_sec);
+}
}
/**
- * boot_get_fdt - main fdt handling routine
- * @argc: command argument count
- * @argv: command argument list
- * @arch: architecture (IH_ARCH_...)
- * @images: pointer to the bootm images structure
- * @of_flat_tree: pointer to a char* variable, will hold fdt start address
- * @of_size: pointer to a ulong variable, will hold fdt length
- *
- * boot_get_fdt() is responsible for finding a valid flat device tree image.
- * Curently supported are the following ramdisk sources:
- * - multicomponent kernel/ramdisk image,
- * - commandline provided address of decicated ramdisk image.
- *
- * returns:
- * 0, if fdt image was found and valid, or skipped
- * of_flat_tree and of_size are set to fdt start address and length if
- * fdt image is found and valid
+ * select_fdt() - Select and locate the FDT to use
*
- * 1, if fdt image is found but corrupted
- * of_flat_tree and of_size are set to 0 if no fdt exists
+ * @images: pointer to the bootm images structure
+ * @select: name of FDT to select, or NULL for any
+ * @arch: expected FDT architecture
+ * @fdt_addrp: pointer to a ulong variable, will hold FDT pointer
+ * @return 0 if OK, -ENOPKG if no FDT (but an error should not be reported),
+ * other -ve value on other error
*/
-int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch,
- bootm_headers_t *images, char **of_flat_tree, ulong *of_size)
-{
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
- const image_header_t *fdt_hdr;
- ulong load, load_end;
- ulong image_start, image_data, image_end;
-#endif
- ulong img_addr;
- ulong fdt_addr;
- char *fdt_blob = NULL;
- void *buf;
-#if CONFIG_IS_ENABLED(FIT)
- const char *fit_uname_config = images->fit_uname_cfg;
- const char *fit_uname_fdt = NULL;
- ulong default_addr;
- int fdt_noffset;
-#endif
- const char *select = NULL;
- *of_flat_tree = NULL;
- *of_size = 0;
-
- img_addr = (argc == 0) ? image_load_addr :
- hextoul(argv[0], NULL);
- buf = map_sysmem(img_addr, 0);
+static int select_fdt(bootm_headers_t *images, const char *select, u8 arch,
+ ulong *fdt_addrp)
+{
+ const char *buf;
+ ulong fdt_addr;
- if (argc > 2)
- select = argv[2];
- if (select || genimg_has_config(images)) {
#if CONFIG_IS_ENABLED(FIT)
- if (select) {
+ const char *fit_uname_config = images->fit_uname_cfg;
+ const char *fit_uname_fdt = NULL;
+ ulong default_addr;
+ int fdt_noffset;
+
+ if (select) {
/*
* If the FDT blob comes from the FIT image and the
* FIT image address is omitted in the command line
else
default_addr = image_load_addr;
- if (fit_parse_conf(select, default_addr,
- &fdt_addr, &fit_uname_config)) {
+ if (fit_parse_conf(select, default_addr, &fdt_addr,
+ &fit_uname_config)) {
debug("* fdt: config '%s' from image at 0x%08lx\n",
fit_uname_config, fdt_addr);
- } else if (fit_parse_subimage(select, default_addr,
- &fdt_addr, &fit_uname_fdt)) {
+ } else if (fit_parse_subimage(select, default_addr, &fdt_addr,
+ &fit_uname_fdt)) {
debug("* fdt: subimage '%s' from image at 0x%08lx\n",
fit_uname_fdt, fdt_addr);
} else
#endif
- {
- fdt_addr = hextoul(select, NULL);
- debug("* fdt: cmdline image address = 0x%08lx\n",
- fdt_addr);
- }
-#if CONFIG_IS_ENABLED(FIT)
- } else {
- /* use FIT configuration provided in first bootm
- * command argument
- */
- fdt_addr = map_to_sysmem(images->fit_hdr_os);
- fdt_noffset = fit_get_node_from_config(images,
- FIT_FDT_PROP,
- fdt_addr);
- if (fdt_noffset == -ENOENT)
- return 0;
- else if (fdt_noffset < 0)
- return 1;
+ {
+ fdt_addr = hextoul(select, NULL);
+ debug("* fdt: cmdline image address = 0x%08lx\n",
+ fdt_addr);
}
-#endif
- debug("## Checking for 'FDT'/'FDT Image' at %08lx\n",
- fdt_addr);
-
- /*
- * Check if there is an FDT image at the
- * address provided in the second bootm argument
- * check image type, for FIT images get a FIT node.
+#if CONFIG_IS_ENABLED(FIT)
+ } else {
+ /* use FIT configuration provided in first bootm
+ * command argument
*/
- buf = map_sysmem(fdt_addr, 0);
- switch (genimg_get_format(buf)) {
+ fdt_addr = map_to_sysmem(images->fit_hdr_os);
+ fdt_noffset = fit_get_node_from_config(images, FIT_FDT_PROP,
+ fdt_addr);
+ if (fdt_noffset == -ENOENT)
+ return -ENOPKG;
+ else if (fdt_noffset < 0)
+ return fdt_noffset;
+ }
+#endif
+ debug("## Checking for 'FDT'/'FDT Image' at %08lx\n",
+ fdt_addr);
+
+ /*
+ * Check if there is an FDT image at the
+ * address provided in the second bootm argument
+ * check image type, for FIT images get a FIT node.
+ */
+ buf = map_sysmem(fdt_addr, 0);
+ switch (genimg_get_format(buf)) {
#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
- case IMAGE_FORMAT_LEGACY:
+ case IMAGE_FORMAT_LEGACY: {
+ const image_header_t *fdt_hdr;
+ ulong load, load_end;
+ ulong image_start, image_data, image_end;
+
/* verify fdt_addr points to a valid image header */
printf("## Flattened Device Tree from Legacy Image at %08lx\n",
fdt_addr);
fdt_hdr = image_get_fdt(fdt_addr);
if (!fdt_hdr)
- goto no_fdt;
+ return -ENOPKG;
/*
* move image data to the load address,
if ((load < image_end) && (load_end > image_start)) {
fdt_error("fdt overwritten");
- goto error;
+ return -EFAULT;
}
debug(" Loading FDT from 0x%08lx to 0x%08lx\n",
fdt_addr = load;
break;
+ }
#endif
- case IMAGE_FORMAT_FIT:
- /*
- * This case will catch both: new uImage format
- * (libfdt based) and raw FDT blob (also libfdt
- * based).
- */
+ case IMAGE_FORMAT_FIT:
+ /*
+ * This case will catch both: new uImage format
+ * (libfdt based) and raw FDT blob (also libfdt
+ * based).
+ */
#if CONFIG_IS_ENABLED(FIT)
/* check FDT blob vs FIT blob */
if (!fit_check_format(buf, IMAGE_SIZE_INVAL)) {
ulong load, len;
- fdt_noffset = boot_get_fdt_fit(images,
- fdt_addr, &fit_uname_fdt,
- &fit_uname_config,
- arch, &load, &len);
+ fdt_noffset = boot_get_fdt_fit(images, fdt_addr,
+ &fit_uname_fdt,
+ &fit_uname_config,
+ arch, &load, &len);
if (fdt_noffset < 0)
- goto error;
+ return -ENOENT;
images->fit_hdr_fdt = map_sysmem(fdt_addr, 0);
images->fit_uname_fdt = fit_uname_fdt;
fdt_addr = load;
break;
- } else
+ } else
#endif
- {
- /*
- * FDT blob
- */
- debug("* fdt: raw FDT blob\n");
- printf("## Flattened Device Tree blob at %08lx\n",
- (long)fdt_addr);
- }
- break;
- default:
- puts("ERROR: Did not find a cmdline Flattened Device Tree\n");
- goto error;
+ {
+ /*
+ * FDT blob
+ */
+ debug("* fdt: raw FDT blob\n");
+ printf("## Flattened Device Tree blob at %08lx\n",
+ (long)fdt_addr);
}
+ break;
+ default:
+ puts("ERROR: Did not find a cmdline Flattened Device Tree\n");
+ return -ENOENT;
+ }
+ *fdt_addrp = fdt_addr;
+
+ return 0;
+}
+
+/**
+ * boot_get_fdt - main fdt handling routine
+ * @argc: command argument count
+ * @argv: command argument list
+ * @arch: architecture (IH_ARCH_...)
+ * @images: pointer to the bootm images structure
+ * @of_flat_tree: pointer to a char* variable, will hold fdt start address
+ * @of_size: pointer to a ulong variable, will hold fdt length
+ *
+ * boot_get_fdt() is responsible for finding a valid flat device tree image.
+ * Currently supported are the following ramdisk sources:
+ * - multicomponent kernel/ramdisk image,
+ * - commandline provided address of decicated ramdisk image.
+ *
+ * returns:
+ * 0, if fdt image was found and valid, or skipped
+ * of_flat_tree and of_size are set to fdt start address and length if
+ * fdt image is found and valid
+ *
+ * 1, if fdt image is found but corrupted
+ * of_flat_tree and of_size are set to 0 if no fdt exists
+ */
+int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch,
+ bootm_headers_t *images, char **of_flat_tree, ulong *of_size)
+{
+ ulong img_addr;
+ ulong fdt_addr;
+ char *fdt_blob = NULL;
+ void *buf;
+ const char *select = NULL;
+ *of_flat_tree = NULL;
+ *of_size = 0;
+
+ img_addr = (argc == 0) ? image_load_addr : hextoul(argv[0], NULL);
+ buf = map_sysmem(img_addr, 0);
+
+ if (argc > 2)
+ select = argv[2];
+ if (select || genimg_has_config(images)) {
+ int ret;
+
+ ret = select_fdt(images, select, arch, &fdt_addr);
+ if (ret == -ENOPKG)
+ goto no_fdt;
+ else if (ret)
+ return 1;
printf(" Booting using the fdt blob at %#08lx\n", fdt_addr);
fdt_blob = map_sysmem(fdt_addr, 0);
} else if (images->legacy_hdr_valid &&
/* Append PStore configuration */
fdt_fixup_pstore(blob);
#endif
- if (IMAGE_OF_BOARD_SETUP) {
+ if (IS_ENABLED(CONFIG_OF_BOARD_SETUP)) {
const char *skip_board_fixup;
skip_board_fixup = env_get("skip_board_fixup");
}
}
}
- if (IMAGE_OF_SYSTEM_SETUP) {
+ if (IS_ENABLED(CONFIG_OF_SYSTEM_SETUP)) {
fdt_ret = ft_system_setup(blob, gd->bd);
if (fdt_ret) {
printf("ERROR: system-specific fdt fixup failed: %s\n",
goto err;
#if defined(CONFIG_ARCH_KEYSTONE)
- if (IMAGE_OF_BOARD_SETUP)
+ if (IS_ENABLED(CONFIG_OF_BOARD_SETUP))
ft_board_setup_ex(blob, gd->bd);
#endif
* Use malloc() except in SPL (to save code size). In SPL the caller
* must allocate the array.
*/
-#ifndef CONFIG_SPL_BUILD
- if (!region)
+ if (!IS_ENABLED(CONFIG_SPL_BUILD) && !region)
region = calloc(sizeof(*region), count);
-#endif
if (!region)
return NULL;
for (i = 0; i < count; i++) {
char *algo_name;
const char *padding_name;
- if (fdt_totalsize(fit) > CONFIG_FIT_SIGNATURE_MAX_SIZE) {
+ if (fdt_totalsize(fit) > CONFIG_VAL(FIT_SIGNATURE_MAX_SIZE)) {
*err_msgp = "Total size too large";
return 1;
}
-
if (fit_image_hash_get_algo(fit, noffset, &algo_name)) {
*err_msgp = "Can't get hash algo property";
return -1;
return count;
}
-#if CONFIG_IS_ENABLED(FIT_PRINT) || CONFIG_IS_ENABLED(SPL_FIT_PRINT)
/**
* fit_image_print_data() - prints out the hash node details
* @fit: pointer to the FIT format image header
const char *p;
time_t timestamp;
+ if (!CONFIG_IS_ENABLED(FIT_PRINT))
+ return;
+
/* Indent string is defined in header image.h */
p = IMAGE_INDENT_STRING;
int ndepth;
int ret;
+ if (!CONFIG_IS_ENABLED(FIT_PRINT))
+ return;
+
/* Mandatory properties */
ret = fit_get_desc(fit, image_noffset, &desc);
printf("%s Description: ", p);
ret = fit_image_get_data_and_size(fit, image_noffset, &data, &size);
- if (!host_build()) {
+ if (!tools_build()) {
printf("%s Data Start: ", p);
if (ret) {
printf("unavailable\n");
}
}
}
-#else
-void fit_print_contents(const void *fit) { }
-void fit_image_print(const void *fit, int image_noffset, const char *p) { }
-#endif /* CONFIG_IS_ENABLED(FIR_PRINT) || CONFIG_IS_ENABLED(SPL_FIT_PRINT) */
/**
* fit_get_desc - get node description property
}
printf("%s", algo);
- if (IMAGE_ENABLE_IGNORE) {
+ if (!tools_build()) {
fit_image_hash_get_ignore(fit, noffset, &ignore);
if (ignore) {
printf("-skipped ");
if (conf_uname == NULL) {
/* get configuration unit name from the default property */
debug("No configuration specified, trying default...\n");
- if (!host_build() && IS_ENABLED(CONFIG_MULTI_DTB_FIT)) {
+ if (!tools_build() && IS_ENABLED(CONFIG_MULTI_DTB_FIT)) {
noffset = fit_find_config_node(fit);
if (noffset < 0)
return noffset;
int type_ok, os_ok;
ulong load, load_end, data, len;
uint8_t os, comp;
-#ifndef USE_HOSTCC
- uint8_t os_arch;
-#endif
const char *prop_name;
int ret;
}
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ARCH);
- if (!host_build() && IS_ENABLED(CONFIG_SANDBOX)) {
+ if (!tools_build() && IS_ENABLED(CONFIG_SANDBOX)) {
if (!fit_image_check_target_arch(fit, noffset)) {
puts("Unsupported Architecture\n");
bootstage_error(bootstage_id + BOOTSTAGE_SUB_CHECK_ARCH);
}
#ifndef USE_HOSTCC
+ {
+ uint8_t os_arch;
+
fit_image_get_arch(fit, noffset, &os_arch);
images->os.arch = os_arch;
+ }
#endif
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ALL);
}
/* perform any post-processing on the image data */
- if (!host_build() && IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS))
+ if (!tools_build() && IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS))
board_fit_image_post_process(fit, noffset, &buf, &size);
len = (ulong)size;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Image code used by host tools (and not boards)
+ *
+ * (C) Copyright 2008 Semihalf
+ *
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <time.h>
+
+void memmove_wd(void *to, void *from, size_t len, ulong chunksz)
+{
+ memmove(to, from, len);
+}
+
+void genimg_print_size(uint32_t size)
+{
+ printf("%d Bytes = %.2f KiB = %.2f MiB\n", size, (double)size / 1.024e3,
+ (double)size / 1.048576e6);
+}
+
+void genimg_print_time(time_t timestamp)
+{
+ printf("%s", ctime(×tamp));
+}
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <image.h>
+#include <relocate.h>
#include <u-boot/ecdsa.h>
#include <u-boot/rsa.h>
#include <u-boot/hash-checksum.h>
int i;
const char *name;
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- static bool done;
+ if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC)) {
+ static bool done;
- if (!done) {
- done = true;
- for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) {
- checksum_algos[i].name += gd->reloc_off;
- checksum_algos[i].calculate += gd->reloc_off;
+ if (!done) {
+ done = true;
+ for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) {
+ struct checksum_algo *algo = &checksum_algos[i];
+
+ MANUAL_RELOC(algo->name);
+ MANUAL_RELOC(algo->calculate);
+ }
}
}
-#endif
for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) {
name = checksum_algos[i].name;
struct crypto_algo *crypto, *end;
const char *name;
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- static bool done;
-
- if (!done) {
- crypto = ll_entry_start(struct crypto_algo, cryptos);
- end = ll_entry_end(struct crypto_algo, cryptos);
- for (; crypto < end; crypto++) {
- crypto->name += gd->reloc_off;
- crypto->verify += gd->reloc_off;
+ if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC)) {
+ static bool done;
+
+ if (!done) {
+ done = true;
+ crypto = ll_entry_start(struct crypto_algo, cryptos);
+ end = ll_entry_end(struct crypto_algo, cryptos);
+ for (; crypto < end; crypto++) {
+ MANUAL_RELOC(crypto->name);
+ MANUAL_RELOC(crypto->verify);
+ }
}
}
-#endif
/* Move name to after the comma */
name = strchr(full_name, ',');
#ifndef USE_HOSTCC
#include <common.h>
-#include <bootstage.h>
-#include <cpu_func.h>
#include <env.h>
#include <lmb.h>
#include <log.h>
#include <malloc.h>
-#include <asm/cache.h>
#include <u-boot/crc.h>
-#include <watchdog.h>
#ifdef CONFIG_SHOW_BOOT_PROGRESS
#include <status_led.h>
#endif
-#include <rtc.h>
-
-#include <gzip.h>
-#include <image.h>
-#include <lz4.h>
-#include <mapmem.h>
-
-#if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT
+#if CONFIG_IS_ENABLED(FIT) || CONFIG_IS_ENABLED(OF_LIBFDT)
#include <linux/libfdt.h>
#include <fdt_support.h>
-#include <fpga.h>
-#include <xilinx.h>
#endif
#include <asm/global_data.h>
#include <linux/errno.h>
#include <asm/io.h>
-#include <bzlib.h>
-#include <linux/lzo.h>
-#include <lzma/LzmaTypes.h>
-#include <lzma/LzmaDec.h>
-#include <lzma/LzmaTools.h>
-#include <linux/zstd.h>
-
#ifdef CONFIG_CMD_BDI
extern int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[]);
DECLARE_GLOBAL_DATA_PTR;
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
-static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch,
- int verify);
-#endif
+/* Set this if we have less than 4 MB of malloc() space */
+#if CONFIG_SYS_MALLOC_LEN < (4096 * 1024)
+#define CONSERVE_MEMORY true
#else
+#define CONSERVE_MEMORY false
+#endif
+
+#else /* USE_HOSTCC */
#include "mkimage.h"
#include <u-boot/md5.h>
#include <time.h>
-#include <image.h>
#ifndef __maybe_unused
# define __maybe_unused /* unimplemented */
#endif
+
+#define CONSERVE_MEMORY false
+
#endif /* !USE_HOSTCC*/
-#include <u-boot/crc.h>
+#include <abuf.h>
+#include <bzlib.h>
+#include <display_options.h>
+#include <gzip.h>
+#include <image.h>
#include <imximage.h>
-
-#ifndef CONFIG_SYS_BARGSIZE
-#define CONFIG_SYS_BARGSIZE 512
-#endif
+#include <relocate.h>
+#include <linux/lzo.h>
+#include <linux/zstd.h>
+#include <linux/kconfig.h>
+#include <lzma/LzmaTypes.h>
+#include <lzma/LzmaDec.h>
+#include <lzma/LzmaTools.h>
+#include <u-boot/crc.h>
+#include <u-boot/lz4.h>
static const table_entry_t uimage_arch[] = {
{ IH_ARCH_INVALID, "invalid", "Invalid ARCH", },
void *load_buf, void *image_buf, ulong image_len,
uint unc_len, ulong *load_end)
{
- int ret = 0;
+ int ret = -ENOSYS;
*load_end = load;
print_decomp_msg(comp, type, load == image_start);
*/
switch (comp) {
case IH_COMP_NONE:
+ ret = 0;
if (load == image_start)
break;
if (image_len <= unc_len)
else
ret = -ENOSPC;
break;
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(GZIP)
- case IH_COMP_GZIP: {
- ret = gunzip(load_buf, unc_len, image_buf, &image_len);
- break;
- }
-#endif /* CONFIG_GZIP */
-#endif
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(BZIP2)
- case IH_COMP_BZIP2: {
- uint size = unc_len;
-
- /*
- * If we've got less than 4 MB of malloc() space,
- * use slower decompression algorithm which requires
- * at most 2300 KB of memory.
- */
- ret = BZ2_bzBuffToBuffDecompress(load_buf, &size,
- image_buf, image_len,
- CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0);
- image_len = size;
+ case IH_COMP_GZIP:
+ if (!tools_build() && CONFIG_IS_ENABLED(GZIP))
+ ret = gunzip(load_buf, unc_len, image_buf, &image_len);
break;
- }
-#endif /* CONFIG_BZIP2 */
-#endif
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(LZMA)
- case IH_COMP_LZMA: {
- SizeT lzma_len = unc_len;
+ case IH_COMP_BZIP2:
+ if (!tools_build() && CONFIG_IS_ENABLED(BZIP2)) {
+ uint size = unc_len;
- ret = lzmaBuffToBuffDecompress(load_buf, &lzma_len,
- image_buf, image_len);
- image_len = lzma_len;
+ /*
+ * If we've got less than 4 MB of malloc() space,
+ * use slower decompression algorithm which requires
+ * at most 2300 KB of memory.
+ */
+ ret = BZ2_bzBuffToBuffDecompress(load_buf, &size,
+ image_buf, image_len, CONSERVE_MEMORY, 0);
+ image_len = size;
+ }
break;
- }
-#endif /* CONFIG_LZMA */
-#endif
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(LZO)
- case IH_COMP_LZO: {
- size_t size = unc_len;
+ case IH_COMP_LZMA:
+ if (!tools_build() && CONFIG_IS_ENABLED(LZMA)) {
+ SizeT lzma_len = unc_len;
- ret = lzop_decompress(image_buf, image_len, load_buf, &size);
- image_len = size;
+ ret = lzmaBuffToBuffDecompress(load_buf, &lzma_len,
+ image_buf, image_len);
+ image_len = lzma_len;
+ }
break;
- }
-#endif /* CONFIG_LZO */
-#endif
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(LZ4)
- case IH_COMP_LZ4: {
- size_t size = unc_len;
+ case IH_COMP_LZO:
+ if (!tools_build() && CONFIG_IS_ENABLED(LZO)) {
+ size_t size = unc_len;
- ret = ulz4fn(image_buf, image_len, load_buf, &size);
- image_len = size;
- break;
- }
-#endif /* CONFIG_LZ4 */
-#endif
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(ZSTD)
- case IH_COMP_ZSTD: {
- size_t size = unc_len;
- ZSTD_DStream *dstream;
- ZSTD_inBuffer in_buf;
- ZSTD_outBuffer out_buf;
- void *workspace;
- size_t wsize;
-
- wsize = ZSTD_DStreamWorkspaceBound(image_len);
- workspace = malloc(wsize);
- if (!workspace) {
- debug("%s: cannot allocate workspace of size %zu\n", __func__,
- wsize);
- return -1;
+ ret = lzop_decompress(image_buf, image_len, load_buf, &size);
+ image_len = size;
}
+ break;
+ case IH_COMP_LZ4:
+ if (!tools_build() && CONFIG_IS_ENABLED(LZ4)) {
+ size_t size = unc_len;
- dstream = ZSTD_initDStream(image_len, workspace, wsize);
- if (!dstream) {
- printf("%s: ZSTD_initDStream failed\n", __func__);
- return ZSTD_getErrorCode(ret);
+ ret = ulz4fn(image_buf, image_len, load_buf, &size);
+ image_len = size;
}
-
- in_buf.src = image_buf;
- in_buf.pos = 0;
- in_buf.size = image_len;
-
- out_buf.dst = load_buf;
- out_buf.pos = 0;
- out_buf.size = size;
-
- while (1) {
- size_t ret;
-
- ret = ZSTD_decompressStream(dstream, &out_buf, &in_buf);
- if (ZSTD_isError(ret)) {
- printf("%s: ZSTD_decompressStream error %d\n", __func__,
- ZSTD_getErrorCode(ret));
- return ZSTD_getErrorCode(ret);
+ break;
+ case IH_COMP_ZSTD:
+ if (!tools_build() && CONFIG_IS_ENABLED(ZSTD)) {
+ struct abuf in, out;
+
+ abuf_init_set(&in, image_buf, image_len);
+ abuf_init_set(&in, load_buf, unc_len);
+ ret = zstd_decompress(&in, &out);
+ if (ret >= 0) {
+ image_len = ret;
+ ret = 0;
}
-
- if (in_buf.pos >= image_len || !ret)
- break;
}
-
- image_len = out_buf.pos;
-
break;
}
-#endif /* CONFIG_ZSTD */
-#endif
- default:
+ if (ret == -ENOSYS) {
printf("Unimplemented compression type %d\n", comp);
- return -ENOSYS;
+ return ret;
}
+ if (ret)
+ return ret;
*load_end = load + image_len;
- return ret;
-}
-
-
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
-/**
- * image_get_ramdisk - get and verify ramdisk image
- * @rd_addr: ramdisk image start address
- * @arch: expected ramdisk architecture
- * @verify: checksum verification flag
- *
- * image_get_ramdisk() returns a pointer to the verified ramdisk image
- * header. Routine receives image start address and expected architecture
- * flag. Verification done covers data and header integrity and os/type/arch
- * fields checking.
- *
- * returns:
- * pointer to a ramdisk image header, if image was found and valid
- * otherwise, return NULL
- */
-static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch,
- int verify)
-{
- const image_header_t *rd_hdr = (const image_header_t *)rd_addr;
-
- if (!image_check_magic(rd_hdr)) {
- puts("Bad Magic Number\n");
- bootstage_error(BOOTSTAGE_ID_RD_MAGIC);
- return NULL;
- }
-
- if (!image_check_hcrc(rd_hdr)) {
- puts("Bad Header Checksum\n");
- bootstage_error(BOOTSTAGE_ID_RD_HDR_CHECKSUM);
- return NULL;
- }
-
- bootstage_mark(BOOTSTAGE_ID_RD_MAGIC);
- image_print_contents(rd_hdr);
-
- if (verify) {
- puts(" Verifying Checksum ... ");
- if (!image_check_dcrc(rd_hdr)) {
- puts("Bad Data CRC\n");
- bootstage_error(BOOTSTAGE_ID_RD_CHECKSUM);
- return NULL;
- }
- puts("OK\n");
- }
-
- bootstage_mark(BOOTSTAGE_ID_RD_HDR_CHECKSUM);
-
- if (!image_check_os(rd_hdr, IH_OS_LINUX) ||
- !image_check_arch(rd_hdr, arch) ||
- !image_check_type(rd_hdr, IH_TYPE_RAMDISK)) {
- printf("No Linux %s Ramdisk Image\n",
- genimg_get_arch_name(arch));
- bootstage_error(BOOTSTAGE_ID_RAMDISK);
- return NULL;
- }
-
- return rd_hdr;
-}
-#endif
-#endif /* !USE_HOSTCC */
-
-/*****************************************************************************/
-/* Shared dual-format routines */
-/*****************************************************************************/
-#ifndef USE_HOSTCC
-ulong image_load_addr = CONFIG_SYS_LOAD_ADDR; /* Default Load Address */
-ulong image_save_addr; /* Default Save Address */
-ulong image_save_size; /* Default Save Size (in bytes) */
-
-static int on_loadaddr(const char *name, const char *value, enum env_op op,
- int flags)
-{
- switch (op) {
- case env_op_create:
- case env_op_overwrite:
- image_load_addr = hextoul(value, NULL);
- break;
- default:
- break;
- }
-
- return 0;
-}
-U_BOOT_ENV_CALLBACK(loadaddr, on_loadaddr);
-
-ulong env_get_bootm_low(void)
-{
- char *s = env_get("bootm_low");
- if (s) {
- ulong tmp = hextoul(s, NULL);
- return tmp;
- }
-
-#if defined(CONFIG_SYS_SDRAM_BASE)
- return CONFIG_SYS_SDRAM_BASE;
-#elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE)
- return gd->bd->bi_dram[0].start;
-#else
return 0;
-#endif
-}
-
-phys_size_t env_get_bootm_size(void)
-{
- phys_size_t tmp, size;
- phys_addr_t start;
- char *s = env_get("bootm_size");
- if (s) {
- tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
- return tmp;
- }
-
- start = gd->ram_base;
- size = gd->ram_size;
-
- if (start + size > gd->ram_top)
- size = gd->ram_top - start;
-
- s = env_get("bootm_low");
- if (s)
- tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
- else
- tmp = start;
-
- return size - (tmp - start);
-}
-
-phys_size_t env_get_bootm_mapsize(void)
-{
- phys_size_t tmp;
- char *s = env_get("bootm_mapsize");
- if (s) {
- tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
- return tmp;
- }
-
-#if defined(CONFIG_SYS_BOOTMAPSZ)
- return CONFIG_SYS_BOOTMAPSZ;
-#else
- return env_get_bootm_size();
-#endif
-}
-
-void memmove_wd(void *to, void *from, size_t len, ulong chunksz)
-{
- if (to == from)
- return;
-
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
- if (to > from) {
- from += len;
- to += len;
- }
- while (len > 0) {
- size_t tail = (len > chunksz) ? chunksz : len;
- WATCHDOG_RESET();
- if (to > from) {
- to -= tail;
- from -= tail;
- }
- memmove(to, from, tail);
- if (to < from) {
- to += tail;
- from += tail;
- }
- len -= tail;
- }
-#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */
- memmove(to, from, len);
-#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
-}
-#else /* USE_HOSTCC */
-void memmove_wd(void *to, void *from, size_t len, ulong chunksz)
-{
- memmove(to, from, len);
-}
-#endif /* !USE_HOSTCC */
-
-void genimg_print_size(uint32_t size)
-{
-#ifndef USE_HOSTCC
- printf("%d Bytes = ", size);
- print_size(size, "\n");
-#else
- printf("%d Bytes = %.2f KiB = %.2f MiB\n",
- size, (double)size / 1.024e3,
- (double)size / 1.048576e6);
-#endif
-}
-
-#if IMAGE_ENABLE_TIMESTAMP
-void genimg_print_time(time_t timestamp)
-{
-#ifndef USE_HOSTCC
- struct rtc_time tm;
-
- rtc_to_tm(timestamp, &tm);
- printf("%4d-%02d-%02d %2d:%02d:%02d UTC\n",
- tm.tm_year, tm.tm_mon, tm.tm_mday,
- tm.tm_hour, tm.tm_min, tm.tm_sec);
-#else
- printf("%s", ctime(×tamp));
-#endif
}
-#endif
const table_entry_t *get_table_entry(const table_entry_t *table, int id)
{
entry = get_table_entry(table_info[category].table, id);
if (!entry)
return unknown_msg(category);
-#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC)
- return entry->lname;
-#else
- return entry->lname + gd->reloc_off;
-#endif
+ return manual_reloc(entry->lname);
}
/**
entry = get_table_entry(table_info[category].table, id);
if (!entry)
return unknown_msg(category);
-#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC)
- return entry->sname;
-#else
- return entry->sname + gd->reloc_off;
-#endif
+ return manual_reloc(entry->sname);
}
int genimg_get_cat_count(enum ih_category category)
table = get_table_entry(table, id);
if (!table)
return msg;
-#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC)
- return table->lname;
-#else
- return table->lname + gd->reloc_off;
-#endif
+ return manual_reloc(table->lname);
}
const char *genimg_get_os_name(uint8_t os)
table = get_table_entry(table, val);
if (!table)
return "unknown";
-#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC)
- return table->sname;
-#else
- return table->sname + gd->reloc_off;
-#endif
+ return manual_reloc(table->sname);
}
const char *genimg_get_type_short_name(uint8_t type)
const table_entry_t *t;
for (t = table; t->id >= 0; ++t) {
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- if (t->sname && strcasecmp(t->sname + gd->reloc_off, name) == 0)
-#else
- if (t->sname && strcasecmp(t->sname, name) == 0)
-#endif
- return (t->id);
+ if (t->sname && !strcasecmp(manual_reloc(t->sname), name))
+ return t->id;
}
debug("Invalid %s Type: %s\n", table_name, name);
{
return (get_table_entry_id(uimage_comp, "Compression", name));
}
-
-#ifndef USE_HOSTCC
-/**
- * genimg_get_kernel_addr_fit - get the real kernel address and return 2
- * FIT strings
- * @img_addr: a string might contain real image address
- * @fit_uname_config: double pointer to a char, will hold pointer to a
- * configuration unit name
- * @fit_uname_kernel: double pointer to a char, will hold pointer to a subimage
- * name
- *
- * genimg_get_kernel_addr_fit get the real kernel start address from a string
- * which is normally the first argv of bootm/bootz
- *
- * returns:
- * kernel start address
- */
-ulong genimg_get_kernel_addr_fit(char * const img_addr,
- const char **fit_uname_config,
- const char **fit_uname_kernel)
-{
- ulong kernel_addr;
-
- /* find out kernel image address */
- if (!img_addr) {
- kernel_addr = image_load_addr;
- debug("* kernel: default image load address = 0x%08lx\n",
- image_load_addr);
-#if CONFIG_IS_ENABLED(FIT)
- } else if (fit_parse_conf(img_addr, image_load_addr, &kernel_addr,
- fit_uname_config)) {
- debug("* kernel: config '%s' from image at 0x%08lx\n",
- *fit_uname_config, kernel_addr);
- } else if (fit_parse_subimage(img_addr, image_load_addr, &kernel_addr,
- fit_uname_kernel)) {
- debug("* kernel: subimage '%s' from image at 0x%08lx\n",
- *fit_uname_kernel, kernel_addr);
-#endif
- } else {
- kernel_addr = hextoul(img_addr, NULL);
- debug("* kernel: cmdline image address = 0x%08lx\n",
- kernel_addr);
- }
-
- return kernel_addr;
-}
-
-/**
- * genimg_get_kernel_addr() is the simple version of
- * genimg_get_kernel_addr_fit(). It ignores those return FIT strings
- */
-ulong genimg_get_kernel_addr(char * const img_addr)
-{
- const char *fit_uname_config = NULL;
- const char *fit_uname_kernel = NULL;
-
- return genimg_get_kernel_addr_fit(img_addr, &fit_uname_config,
- &fit_uname_kernel);
-}
-
-/**
- * genimg_get_format - get image format type
- * @img_addr: image start address
- *
- * genimg_get_format() checks whether provided address points to a valid
- * legacy or FIT image.
- *
- * New uImage format and FDT blob are based on a libfdt. FDT blob
- * may be passed directly or embedded in a FIT image. In both situations
- * genimg_get_format() must be able to dectect libfdt header.
- *
- * returns:
- * image format type or IMAGE_FORMAT_INVALID if no image is present
- */
-int genimg_get_format(const void *img_addr)
-{
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
- const image_header_t *hdr;
-
- hdr = (const image_header_t *)img_addr;
- if (image_check_magic(hdr))
- return IMAGE_FORMAT_LEGACY;
-#endif
-#if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT
- if (fdt_check_header(img_addr) == 0)
- return IMAGE_FORMAT_FIT;
-#endif
-#ifdef CONFIG_ANDROID_BOOT_IMAGE
- if (android_image_check_header(img_addr) == 0)
- return IMAGE_FORMAT_ANDROID;
-#endif
-
- return IMAGE_FORMAT_INVALID;
-}
-
-/**
- * fit_has_config - check if there is a valid FIT configuration
- * @images: pointer to the bootm command headers structure
- *
- * fit_has_config() checks if there is a FIT configuration in use
- * (if FTI support is present).
- *
- * returns:
- * 0, no FIT support or no configuration found
- * 1, configuration found
- */
-int genimg_has_config(bootm_headers_t *images)
-{
-#if IMAGE_ENABLE_FIT
- if (images->fit_uname_cfg)
- return 1;
-#endif
- return 0;
-}
-
-/**
- * boot_get_ramdisk - main ramdisk handling routine
- * @argc: command argument count
- * @argv: command argument list
- * @images: pointer to the bootm images structure
- * @arch: expected ramdisk architecture
- * @rd_start: pointer to a ulong variable, will hold ramdisk start address
- * @rd_end: pointer to a ulong variable, will hold ramdisk end
- *
- * boot_get_ramdisk() is responsible for finding a valid ramdisk image.
- * Curently supported are the following ramdisk sources:
- * - multicomponent kernel/ramdisk image,
- * - commandline provided address of decicated ramdisk image.
- *
- * returns:
- * 0, if ramdisk image was found and valid, or skiped
- * rd_start and rd_end are set to ramdisk start/end addresses if
- * ramdisk image is found and valid
- *
- * 1, if ramdisk image is found but corrupted, or invalid
- * rd_start and rd_end are set to 0 if no ramdisk exists
- */
-int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images,
- uint8_t arch, ulong *rd_start, ulong *rd_end)
-{
- ulong rd_addr, rd_load;
- ulong rd_data, rd_len;
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
- const image_header_t *rd_hdr;
-#endif
- void *buf;
-#ifdef CONFIG_SUPPORT_RAW_INITRD
- char *end;
-#endif
-#if IMAGE_ENABLE_FIT
- const char *fit_uname_config = images->fit_uname_cfg;
- const char *fit_uname_ramdisk = NULL;
- ulong default_addr;
- int rd_noffset;
-#endif
- const char *select = NULL;
-
- *rd_start = 0;
- *rd_end = 0;
-
-#ifdef CONFIG_ANDROID_BOOT_IMAGE
- /*
- * Look for an Android boot image.
- */
- buf = map_sysmem(images->os.start, 0);
- if (buf && genimg_get_format(buf) == IMAGE_FORMAT_ANDROID)
- select = (argc == 0) ? env_get("loadaddr") : argv[0];
-#endif
-
- if (argc >= 2)
- select = argv[1];
-
- /*
- * Look for a '-' which indicates to ignore the
- * ramdisk argument
- */
- if (select && strcmp(select, "-") == 0) {
- debug("## Skipping init Ramdisk\n");
- rd_len = rd_data = 0;
- } else if (select || genimg_has_config(images)) {
-#if IMAGE_ENABLE_FIT
- if (select) {
- /*
- * If the init ramdisk comes from the FIT image and
- * the FIT image address is omitted in the command
- * line argument, try to use os FIT image address or
- * default load address.
- */
- if (images->fit_uname_os)
- default_addr = (ulong)images->fit_hdr_os;
- else
- default_addr = image_load_addr;
-
- if (fit_parse_conf(select, default_addr,
- &rd_addr, &fit_uname_config)) {
- debug("* ramdisk: config '%s' from image at "
- "0x%08lx\n",
- fit_uname_config, rd_addr);
- } else if (fit_parse_subimage(select, default_addr,
- &rd_addr, &fit_uname_ramdisk)) {
- debug("* ramdisk: subimage '%s' from image at "
- "0x%08lx\n",
- fit_uname_ramdisk, rd_addr);
- } else
-#endif
- {
- rd_addr = hextoul(select, NULL);
- debug("* ramdisk: cmdline image address = "
- "0x%08lx\n",
- rd_addr);
- }
-#if IMAGE_ENABLE_FIT
- } else {
- /* use FIT configuration provided in first bootm
- * command argument. If the property is not defined,
- * quit silently.
- */
- rd_addr = map_to_sysmem(images->fit_hdr_os);
- rd_noffset = fit_get_node_from_config(images,
- FIT_RAMDISK_PROP, rd_addr);
- if (rd_noffset == -ENOENT)
- return 0;
- else if (rd_noffset < 0)
- return 1;
- }
-#endif
-
- /*
- * Check if there is an initrd image at the
- * address provided in the second bootm argument
- * check image type, for FIT images get FIT node.
- */
- buf = map_sysmem(rd_addr, 0);
- switch (genimg_get_format(buf)) {
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
- case IMAGE_FORMAT_LEGACY:
- printf("## Loading init Ramdisk from Legacy "
- "Image at %08lx ...\n", rd_addr);
-
- bootstage_mark(BOOTSTAGE_ID_CHECK_RAMDISK);
- rd_hdr = image_get_ramdisk(rd_addr, arch,
- images->verify);
-
- if (rd_hdr == NULL)
- return 1;
-
- rd_data = image_get_data(rd_hdr);
- rd_len = image_get_data_size(rd_hdr);
- rd_load = image_get_load(rd_hdr);
- break;
-#endif
-#if IMAGE_ENABLE_FIT
- case IMAGE_FORMAT_FIT:
- rd_noffset = fit_image_load(images,
- rd_addr, &fit_uname_ramdisk,
- &fit_uname_config, arch,
- IH_TYPE_RAMDISK,
- BOOTSTAGE_ID_FIT_RD_START,
- FIT_LOAD_OPTIONAL_NON_ZERO,
- &rd_data, &rd_len);
- if (rd_noffset < 0)
- return 1;
-
- images->fit_hdr_rd = map_sysmem(rd_addr, 0);
- images->fit_uname_rd = fit_uname_ramdisk;
- images->fit_noffset_rd = rd_noffset;
- break;
-#endif
-#ifdef CONFIG_ANDROID_BOOT_IMAGE
- case IMAGE_FORMAT_ANDROID:
- android_image_get_ramdisk((void *)images->os.start,
- &rd_data, &rd_len);
- break;
-#endif
- default:
-#ifdef CONFIG_SUPPORT_RAW_INITRD
- end = NULL;
- if (select)
- end = strchr(select, ':');
- if (end) {
- rd_len = hextoul(++end, NULL);
- rd_data = rd_addr;
- } else
-#endif
- {
- puts("Wrong Ramdisk Image Format\n");
- rd_data = rd_len = rd_load = 0;
- return 1;
- }
- }
- } else if (images->legacy_hdr_valid &&
- image_check_type(&images->legacy_hdr_os_copy,
- IH_TYPE_MULTI)) {
-
- /*
- * Now check if we have a legacy mult-component image,
- * get second entry data start address and len.
- */
- bootstage_mark(BOOTSTAGE_ID_RAMDISK);
- printf("## Loading init Ramdisk from multi component "
- "Legacy Image at %08lx ...\n",
- (ulong)images->legacy_hdr_os);
-
- image_multi_getimg(images->legacy_hdr_os, 1, &rd_data, &rd_len);
- } else {
- /*
- * no initrd image
- */
- bootstage_mark(BOOTSTAGE_ID_NO_RAMDISK);
- rd_len = rd_data = 0;
- }
-
- if (!rd_data) {
- debug("## No init Ramdisk\n");
- } else {
- *rd_start = rd_data;
- *rd_end = rd_data + rd_len;
- }
- debug(" ramdisk start = 0x%08lx, ramdisk end = 0x%08lx\n",
- *rd_start, *rd_end);
-
- return 0;
-}
-
-#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
-/**
- * boot_ramdisk_high - relocate init ramdisk
- * @lmb: pointer to lmb handle, will be used for memory mgmt
- * @rd_data: ramdisk data start address
- * @rd_len: ramdisk data length
- * @initrd_start: pointer to a ulong variable, will hold final init ramdisk
- * start address (after possible relocation)
- * @initrd_end: pointer to a ulong variable, will hold final init ramdisk
- * end address (after possible relocation)
- *
- * boot_ramdisk_high() takes a relocation hint from "initrd_high" environment
- * variable and if requested ramdisk data is moved to a specified location.
- *
- * Initrd_start and initrd_end are set to final (after relocation) ramdisk
- * start/end addresses if ramdisk image start and len were provided,
- * otherwise set initrd_start and initrd_end set to zeros.
- *
- * returns:
- * 0 - success
- * -1 - failure
- */
-int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len,
- ulong *initrd_start, ulong *initrd_end)
-{
- char *s;
- ulong initrd_high;
- int initrd_copy_to_ram = 1;
-
- s = env_get("initrd_high");
- if (s) {
- /* a value of "no" or a similar string will act like 0,
- * turning the "load high" feature off. This is intentional.
- */
- initrd_high = hextoul(s, NULL);
- if (initrd_high == ~0)
- initrd_copy_to_ram = 0;
- } else {
- initrd_high = env_get_bootm_mapsize() + env_get_bootm_low();
- }
-
-
- debug("## initrd_high = 0x%08lx, copy_to_ram = %d\n",
- initrd_high, initrd_copy_to_ram);
-
- if (rd_data) {
- if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */
- debug(" in-place initrd\n");
- *initrd_start = rd_data;
- *initrd_end = rd_data + rd_len;
- lmb_reserve(lmb, rd_data, rd_len);
- } else {
- if (initrd_high)
- *initrd_start = (ulong)lmb_alloc_base(lmb,
- rd_len, 0x1000, initrd_high);
- else
- *initrd_start = (ulong)lmb_alloc(lmb, rd_len,
- 0x1000);
-
- if (*initrd_start == 0) {
- puts("ramdisk - allocation error\n");
- goto error;
- }
- bootstage_mark(BOOTSTAGE_ID_COPY_RAMDISK);
-
- *initrd_end = *initrd_start + rd_len;
- printf(" Loading Ramdisk to %08lx, end %08lx ... ",
- *initrd_start, *initrd_end);
-
- memmove_wd((void *)*initrd_start,
- (void *)rd_data, rd_len, CHUNKSZ);
-
-#ifdef CONFIG_MP
- /*
- * Ensure the image is flushed to memory to handle
- * AMP boot scenarios in which we might not be
- * HW cache coherent
- */
- flush_cache((unsigned long)*initrd_start,
- ALIGN(rd_len, ARCH_DMA_MINALIGN));
-#endif
- puts("OK\n");
- }
- } else {
- *initrd_start = 0;
- *initrd_end = 0;
- }
- debug(" ramdisk load start = 0x%08lx, ramdisk load end = 0x%08lx\n",
- *initrd_start, *initrd_end);
-
- return 0;
-
-error:
- return -1;
-}
-#endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */
-
-int boot_get_setup(bootm_headers_t *images, uint8_t arch,
- ulong *setup_start, ulong *setup_len)
-{
-#if IMAGE_ENABLE_FIT
- return boot_get_setup_fit(images, arch, setup_start, setup_len);
-#else
- return -ENOENT;
-#endif
-}
-
-#if IMAGE_ENABLE_FIT
-#if defined(CONFIG_FPGA)
-int boot_get_fpga(int argc, char *const argv[], bootm_headers_t *images,
- uint8_t arch, const ulong *ld_start, ulong * const ld_len)
-{
- ulong tmp_img_addr, img_data, img_len;
- void *buf;
- int conf_noffset;
- int fit_img_result;
- const char *uname, *name;
- int err;
- int devnum = 0; /* TODO support multi fpga platforms */
-
- /* Check to see if the images struct has a FIT configuration */
- if (!genimg_has_config(images)) {
- debug("## FIT configuration was not specified\n");
- return 0;
- }
-
- /*
- * Obtain the os FIT header from the images struct
- */
- tmp_img_addr = map_to_sysmem(images->fit_hdr_os);
- buf = map_sysmem(tmp_img_addr, 0);
- /*
- * Check image type. For FIT images get FIT node
- * and attempt to locate a generic binary.
- */
- switch (genimg_get_format(buf)) {
- case IMAGE_FORMAT_FIT:
- conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg);
-
- uname = fdt_stringlist_get(buf, conf_noffset, FIT_FPGA_PROP, 0,
- NULL);
- if (!uname) {
- debug("## FPGA image is not specified\n");
- return 0;
- }
- fit_img_result = fit_image_load(images,
- tmp_img_addr,
- (const char **)&uname,
- &(images->fit_uname_cfg),
- arch,
- IH_TYPE_FPGA,
- BOOTSTAGE_ID_FPGA_INIT,
- FIT_LOAD_OPTIONAL_NON_ZERO,
- &img_data, &img_len);
-
- debug("FPGA image (%s) loaded to 0x%lx/size 0x%lx\n",
- uname, img_data, img_len);
-
- if (fit_img_result < 0) {
- /* Something went wrong! */
- return fit_img_result;
- }
-
- if (!fpga_is_partial_data(devnum, img_len)) {
- name = "full";
- err = fpga_loadbitstream(devnum, (char *)img_data,
- img_len, BIT_FULL);
- if (err)
- err = fpga_load(devnum, (const void *)img_data,
- img_len, BIT_FULL);
- } else {
- name = "partial";
- err = fpga_loadbitstream(devnum, (char *)img_data,
- img_len, BIT_PARTIAL);
- if (err)
- err = fpga_load(devnum, (const void *)img_data,
- img_len, BIT_PARTIAL);
- }
-
- if (err)
- return err;
-
- printf(" Programming %s bitstream... OK\n", name);
- break;
- default:
- printf("The given image format is not supported (corrupt?)\n");
- return 1;
- }
-
- return 0;
-}
-#endif
-
-static void fit_loadable_process(uint8_t img_type,
- ulong img_data,
- ulong img_len)
-{
- int i;
- const unsigned int count =
- ll_entry_count(struct fit_loadable_tbl, fit_loadable);
- struct fit_loadable_tbl *fit_loadable_handler =
- ll_entry_start(struct fit_loadable_tbl, fit_loadable);
- /* For each loadable handler */
- for (i = 0; i < count; i++, fit_loadable_handler++)
- /* matching this type */
- if (fit_loadable_handler->type == img_type)
- /* call that handler with this image data */
- fit_loadable_handler->handler(img_data, img_len);
-}
-
-int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images,
- uint8_t arch, const ulong *ld_start, ulong * const ld_len)
-{
- /*
- * These variables are used to hold the current image location
- * in system memory.
- */
- ulong tmp_img_addr;
- /*
- * These two variables are requirements for fit_image_load, but
- * their values are not used
- */
- ulong img_data, img_len;
- void *buf;
- int loadables_index;
- int conf_noffset;
- int fit_img_result;
- const char *uname;
- uint8_t img_type;
-
- /* Check to see if the images struct has a FIT configuration */
- if (!genimg_has_config(images)) {
- debug("## FIT configuration was not specified\n");
- return 0;
- }
-
- /*
- * Obtain the os FIT header from the images struct
- */
- tmp_img_addr = map_to_sysmem(images->fit_hdr_os);
- buf = map_sysmem(tmp_img_addr, 0);
- /*
- * Check image type. For FIT images get FIT node
- * and attempt to locate a generic binary.
- */
- switch (genimg_get_format(buf)) {
- case IMAGE_FORMAT_FIT:
- conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg);
-
- for (loadables_index = 0;
- uname = fdt_stringlist_get(buf, conf_noffset,
- FIT_LOADABLE_PROP, loadables_index,
- NULL), uname;
- loadables_index++)
- {
- fit_img_result = fit_image_load(images,
- tmp_img_addr,
- &uname,
- &(images->fit_uname_cfg), arch,
- IH_TYPE_LOADABLE,
- BOOTSTAGE_ID_FIT_LOADABLE_START,
- FIT_LOAD_OPTIONAL_NON_ZERO,
- &img_data, &img_len);
- if (fit_img_result < 0) {
- /* Something went wrong! */
- return fit_img_result;
- }
-
- fit_img_result = fit_image_get_node(buf, uname);
- if (fit_img_result < 0) {
- /* Something went wrong! */
- return fit_img_result;
- }
- fit_img_result = fit_image_get_type(buf,
- fit_img_result,
- &img_type);
- if (fit_img_result < 0) {
- /* Something went wrong! */
- return fit_img_result;
- }
-
- fit_loadable_process(img_type, img_data, img_len);
- }
- break;
- default:
- printf("The given image format is not supported (corrupt?)\n");
- return 1;
- }
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
-/**
- * boot_get_cmdline - allocate and initialize kernel cmdline
- * @lmb: pointer to lmb handle, will be used for memory mgmt
- * @cmd_start: pointer to a ulong variable, will hold cmdline start
- * @cmd_end: pointer to a ulong variable, will hold cmdline end
- *
- * boot_get_cmdline() allocates space for kernel command line below
- * BOOTMAPSZ + env_get_bootm_low() address. If "bootargs" U-Boot environment
- * variable is present its contents is copied to allocated kernel
- * command line.
- *
- * returns:
- * 0 - success
- * -1 - failure
- */
-int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end)
-{
- char *cmdline;
- char *s;
-
- cmdline = (char *)(ulong)lmb_alloc_base(lmb, CONFIG_SYS_BARGSIZE, 0xf,
- env_get_bootm_mapsize() + env_get_bootm_low());
-
- if (cmdline == NULL)
- return -1;
-
- s = env_get("bootargs");
- if (!s)
- s = "";
-
- strcpy(cmdline, s);
-
- *cmd_start = (ulong) & cmdline[0];
- *cmd_end = *cmd_start + strlen(cmdline);
-
- debug("## cmdline at 0x%08lx ... 0x%08lx\n", *cmd_start, *cmd_end);
-
- return 0;
-}
-#endif /* CONFIG_SYS_BOOT_GET_CMDLINE */
-
-#ifdef CONFIG_SYS_BOOT_GET_KBD
-/**
- * boot_get_kbd - allocate and initialize kernel copy of board info
- * @lmb: pointer to lmb handle, will be used for memory mgmt
- * @kbd: double pointer to board info data
- *
- * boot_get_kbd() allocates space for kernel copy of board info data below
- * BOOTMAPSZ + env_get_bootm_low() address and kernel board info is initialized
- * with the current u-boot board info data.
- *
- * returns:
- * 0 - success
- * -1 - failure
- */
-int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd)
-{
- *kbd = (struct bd_info *)(ulong)lmb_alloc_base(lmb,
- sizeof(struct bd_info),
- 0xf,
- env_get_bootm_mapsize() + env_get_bootm_low());
- if (*kbd == NULL)
- return -1;
-
- **kbd = *(gd->bd);
-
- debug("## kernel board info at 0x%08lx\n", (ulong)*kbd);
-
-#if defined(DEBUG) && defined(CONFIG_CMD_BDI)
- do_bdinfo(NULL, 0, 0, NULL);
-#endif
-
- return 0;
-}
-#endif /* CONFIG_SYS_BOOT_GET_KBD */
-
-#ifdef CONFIG_LMB
-int image_setup_linux(bootm_headers_t *images)
-{
- ulong of_size = images->ft_len;
- char **of_flat_tree = &images->ft_addr;
- struct lmb *lmb = &images->lmb;
- int ret;
-
- if (IMAGE_ENABLE_OF_LIBFDT)
- boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree);
-
- if (IMAGE_BOOT_GET_CMDLINE) {
- ret = boot_get_cmdline(lmb, &images->cmdline_start,
- &images->cmdline_end);
- if (ret) {
- puts("ERROR with allocation of cmdline\n");
- return ret;
- }
- }
-
- if (IMAGE_ENABLE_OF_LIBFDT) {
- ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size);
- if (ret)
- return ret;
- }
-
- if (IMAGE_ENABLE_OF_LIBFDT && of_size) {
- ret = image_setup_libfdt(images, *of_flat_tree, of_size, lmb);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif /* CONFIG_LMB */
-#endif /* !USE_HOSTCC */
config SPL_CRC32
bool "Support CRC32"
- default y if SPL_LEGACY_IMAGE_SUPPORT
+ default y if SPL_LEGACY_IMAGE_SUPPORT || SPL_EFI_PARTITION
+ default y if SPL_ENV_SUPPORT || TPL_BLOBLIST
help
Enable this to support CRC32 in uImages or FIT images within SPL.
This is a 32-bit checksum value that can be used to verify images.
BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the
boot device list, if not implemented for a given board)
+config TPL_CRC32
+ bool "Support CRC32 in TPL"
+ default y if TPL_ENV_SUPPORT || TPL_BLOBLIST
+ help
+ Enable this to support CRC32 in uImages or FIT images within SPL.
+ This is a 32-bit checksum value that can be used to verify images.
+ For FIT images, this is the least secure type of checksum, suitable
+ for detected accidental image corruption. For secure applications you
+ should consider SHA1 or SHA256.
+
config TPL_DRIVERS_MISC
bool "Support misc drivers in TPL"
help
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC3_CD_PIN="PH0"
-CONFIG_MMC3_PINS="PH"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_USB0_VBUS_DET="PH5"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
-CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
CONFIG_VIDEO_LCD_POWER="PH27"
CONFIG_VIDEO_LCD_BL_EN="PM1"
CONFIG_VIDEO_LCD_BL_PWM="PH13"
-CONFIG_VIDEO_LCD_PANEL_I2C_SDA="PA23"
-CONFIG_VIDEO_LCD_PANEL_I2C_SCL="PA24"
CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_SOFT=y
-CONFIG_SYS_I2C_SOFT_SPEED=50000
-CONFIG_SYS_I2C_SOFT_SLAVE=0x00
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
CONFIG_USB1_VBUS_PIN="PH14"
CONFIG_USB3_VBUS_PIN="PH15"
CONFIG_AXP_GPIO=y
+CONFIG_SYS_I2C_SUN8I_RSB=y
CONFIG_AXP809_POWER=y
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
-CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_USB1_VBUS_PIN="PH4"
CONFIG_USB3_VBUS_PIN="PH5"
CONFIG_AXP_GPIO=y
+CONFIG_SYS_I2C_SUN8I_RSB=y
CONFIG_AXP809_POWER=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_NAND_FSL_ELBC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_NAND_FSL_ELBC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_NAND_FSL_ELBC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_NAND_FSL_ELBC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_NAND_FSL_ELBC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_ELBC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_ELBC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_ELBC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=251
CONFIG_MMC0_CD_PIN="PA4"
-CONFIG_MMC3_PINS="PC"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_VIDEO_LCD_TL059WV5C0=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
-CONFIG_SYS_I2C_SOFT=y
-CONFIG_SYS_I2C_SOFT_SPEED=50000
-CONFIG_SYS_I2C_SOFT_SLAVE=0x00
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
CONFIG_DRAM_CLK=408
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC1_CD_PIN="PH2"
-CONFIG_MMC1_PINS="PH"
+CONFIG_MMC1_PINS_PH=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTP_SEND_HOSTNAME=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_CLK=y
CONFIG_CLK_CDCE9XX=y
+CONFIG_CLK_TI_CTRL=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_MMC=y
CONFIG_DFU_NAND=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MICREL=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MICREL=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_TI_DP83867=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PINCTRL=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_DA9063=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_DA9063=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_DA9063=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_DA9063=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-bananapi-m5"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING="bpi-m5"
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
-CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_BOARD="beelink-s922x"
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-gsking-x"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" beelink"
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_SPL_DM=y
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_ARM=y
-CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MVEBU=y
CONFIG_MISC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_XENON=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NAND_MXS=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_ARM=y
-CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_ARM=y
-CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_ARM=y
-CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_USB=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="dh"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x140000
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_TI_DP83867=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x140000
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_TI_DP83867=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
# CONFIG_TPL_BANNER_PRINT is not set
-CONFIG_SPL_CRC32=y
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
# CONFIG_TPL_BANNER_PRINT is not set
-CONFIG_SPL_CRC32=y
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
# CONFIG_CMD_BOOTD is not set
CONFIG_MTD=y
CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
-CONFIG_MTD_UBI_FASTMAP=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
+CONFIG_MTD_UBI_FASTMAP=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_LED_GPIO=y
CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ARM=y
-CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MVEBU=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHYLIB=y
CONFIG_DM_VIDEO=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_K3=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am6528-iot2050-basic"
CONFIG_SPL_TEXT_BASE=0x80080000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_ENV_OFFSET_REDUND=0x6a0000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="jethub"
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-axg-jethome-jethub-j100"
+CONFIG_MESON_AXG=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" jethubj100"
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPIO=y
+CONFIG_RANDOM_UUID=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD_UBI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MESON_GXL_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_AXG=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF8563=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_GXL=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_BOARD="jethub-j80"
+CONFIG_SYS_CONFIG_NAME="jethub"
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905w-jethome-jethub-j80"
+CONFIG_MESON_GXL=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" jethubj80"
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_RANDOM_UUID=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SARADC_MESON=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD_UBI=y
+CONFIG_PHY_MESON_GXL=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MMIOREG=y
+CONFIG_MESON_GXL_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXL=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF8563=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_GXL=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX5=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_MC34708=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
CONFIG_IMX_WATCHDOG=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MISC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_XENON=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_PXA3XX=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_MISC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_XENON=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MISC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_XENON=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHY_MARVELL=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_NAND_MXS=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_NAND_MXS=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_CI_UDC=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PINCTRL=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_MXC_UART=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-r1s-h5"
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881977
+# CONFIG_DRAM_ODT_EN is not set
+CONFIG_MACPWR="PD6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
# CONFIG_TPL_BANNER_PRINT is not set
-CONFIG_SPL_CRC32=y
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_SOUND=y
CONFIG_SYSRESET=y
-CONFIG_OPTEE_LIB=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
+CONFIG_OPTEE_LIB=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_BOARD="odroid-n2"
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-odroid-hc4"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" odroid-hc4"
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SATA=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_MESON=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MESON_SPIFC=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_SPL=y
+CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_SPL=y
+CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_SPL=y
+CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_VIDEO_BPP8 is not set
# CONFIG_VIDEO_BPP32 is not set
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_SPLASH_SOURCE=y
CONFIG_R_I2C_ENABLE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
-CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_RTL8169=y
CONFIG_DRAM_CLK=600
CONFIG_DRAM_ZQ=15291
CONFIG_MMC0_CD_PIN="PD14"
-CONFIG_MMC2_PINS="PC"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_ID_DET="PD10"
CONFIG_USB1_VBUS_PIN="PD12"
CONFIG_NAND_MXS_DT=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_MXC_UART=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_MXC_UART=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
CONFIG_CI_UDC=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
CONFIG_DRAM_ODT_EN=y
CONFIG_I2C0_ENABLE=y
CONFIG_SPL_I2C=y
-CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinephone-1.2"
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MACH_SUN50I=y
CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
CONFIG_PINEPHONE_DT_SELECTION=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.2"
+CONFIG_LED_STATUS=y
+CONFIG_LED_STATUS_GPIO=y
+CONFIG_LED_STATUS0=y
+CONFIG_LED_STATUS_BIT=114
+CONFIG_LED_STATUS_STATE=2
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinetab"
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I=y
+CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=3881949
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
# CONFIG_TPL_BANNER_PRINT is not set
-CONFIG_SPL_CRC32=y
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
# CONFIG_TPL_BANNER_PRINT is not set
-CONFIG_SPL_CRC32=y
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
+CONFIG_SYSRESET_SBI=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_CMD_SBI=y
# CONFIG_CMD_MII is not set
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
+CONFIG_SYSRESET_SBI=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
+CONFIG_SYSRESET_SBI=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_CMD_SBI=y
# CONFIG_CMD_MII is not set
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
+CONFIG_SYSRESET_SBI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-radxa-zero"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" radxa-zero"
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_KEYBOARD=y
# CONFIG_USB_KEYBOARD_FN_KEYS is not set
CONFIG_USB_GADGET=y
CONFIG_DEBUG_UART_CLOCK=83000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_BOOT_GET_CMDLINE=y
CONFIG_SYS_BOOT_GET_KBD=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
CONFIG_QSPI_BOOT=y
CONFIG_CMD_MEM_SEARCH=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
CONFIG_CMD_BIND=y
CONFIG_CMD_DEMO=y
CONFIG_CMD_GPIO=y
CONFIG_USB=y
CONFIG_USB_EMUL=y
CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_COPY=y
CONFIG_CONSOLE_ROTATION=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_RISCV=y
+# CONFIG_SPL_USE_ARCH_MEMMOVE is not set
CONFIG_SPL_GPIO=y
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_NR_DRAM_BANKS=1
CONFIG_TARGET_SIFIVE_UNMATCHED=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
-# CONFIG_SPL_USE_ARCH_MEMMOVE is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
CONFIG_USB_GADGET_VENDOR_NUM=0x483
# CONFIG_NET is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
+CONFIG_STM32_FLASH=y
# CONFIG_NET is not set
CONFIG_ARM_PL180_MMCI=y
CONFIG_MTD_NOR_FLASH=y
+CONFIG_STM32_FLASH=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
+CONFIG_STM32_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_PINCTRL_FULL is not set
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
+CONFIG_STM32_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
+CONFIG_STM32_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_MALLOC_LEN=0x14000
CONFIG_DEFAULT_DEVICE_TREE="stv0991"
CONFIG_SYS_LOAD_ADDR=0x0
-CONFIG_SYS_EXTRA_OPTIONS="STV0991"
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_IGNORE_OSINDICATIONS=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
-CONFIG_EFI_SECURE_BOOT=y
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_SPL_DM=y
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=108000000
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=108000000
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=108000000
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_USDHC=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_USDHC=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_USDHC=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_USDHC=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_USDHC=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_USDHC=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_PCI=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ARM=y
-CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_SPL_SYS_THUMB_BUILD=y
CONFIG_ARCH_MVEBU=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_MXC_UART=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_AT91_GPIO=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_PHY_SMSC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
-CONFIG_OPTEE=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ETH_CDC=y
CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_OPTEE_TZDRAM_SIZE=0x02000000
CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7s-warp"
+CONFIG_OPTEE_TZDRAM_SIZE=0x3000000
CONFIG_TARGET_WARP7=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
-CONFIG_OPTEE=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
-CONFIG_OPTEE_TZDRAM_SIZE=0x3000000
CONFIG_BOOTM_OPTEE=y
CONFIG_ARM=y
-CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
-CONFIG_EFI_SECURE_BOOT=y
This matrix concerns the actual source code version.
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| | S905 | S905X | S912 | A113X | S905X2 | S922X | S905X3 |
-| | | S805X | S905D | | S905D2 | A311D | S905D3 |
-| | | | | | S905Y2 | | |
-+===============================+===========+=================+==============+============+============+=============+==============+
-| Boards | Odroid-C2 | P212 | Khadas VIM2 | S400 | U200 | Odroid-N2 | SEI610 |
-| | Nanopi-K2 | Khadas-VIM | Libretech-PC | | SEI510 | Khadas-VIM3 | Khadas-VIM3L |
-| | P200 | LibreTech-CC v1 | WeTek Core2 | | | GT-King/Pro | Odroid-C4 |
-| | P201 | LibreTech-AC v2 | | | | | |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| UART | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| Pinctrl/GPIO | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| Clock Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| PWM | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| Reset Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| Infrared Decoder | No | No | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| Ethernet | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| Multi-core | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| Fuse access | **Yes** | **Yes** |**Yes** |**Yes** |**Yes** |**Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| SPI (FC) | **Yes** | **Yes** | **Yes** | **Yes** |**Yes** | **Yes** | No |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| SPI (CC) | No | No | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| I2C | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| USB | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| USB OTG | No | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| eMMC | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| SDCard | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| NAND | No | No | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| ADC | **Yes** | **Yes** | **Yes** | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| CVBS Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| HDMI Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| CEC | No | No | No | *N/A* | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| Thermal Sensor | No | No | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| LCD/LVDS Output | No | *N/A* | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| MIPI DSI Output | *N/A* | *N/A* | *N/A* | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| SoC (version) information | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
-| PCIe (+NVMe) | *N/A* | *N/A* | *N/A* | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| | S905 | S905X | S912 | A113X | S905X2 | S922X | S905X3 |
+| | | S805X | S905D | | S905D2 | A311D | S905D3 |
+| | | S905W | | | S905Y2 | | |
++===============================+===========+=================+==============+=============+============+=============+==============+
+| Boards | Odroid-C2 | P212 | Khadas VIM2 | S400 | U200 | Odroid-N2 | SEI610 |
+| | Nanopi-K2 | Khadas-VIM | Libretech-PC | JetHub J100 | SEI510 | Khadas-VIM3 | Khadas-VIM3L |
+| | P200 | LibreTech-CC v1 | WeTek Core2 | | Radxa Zero | GT-King/Pro | Odroid-C4 |
+| | P201 | LibreTech-AC v2 | | | | GSKing-X | Odroid-HC4 |
+| | | JetHub J80 | | | | | BananaPi-M5 |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| UART | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| Pinctrl/GPIO | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| Clock Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| PWM | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| Reset Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| Infrared Decoder | No | No | No | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| Ethernet | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| Multi-core | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| Fuse access | **Yes** | **Yes** |**Yes** |**Yes** |**Yes** |**Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| SPI (FC) | **Yes** | **Yes** | **Yes** | **Yes** |**Yes** | **Yes** | No |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| SPI (CC) | No | No | No | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| I2C | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| USB | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| USB OTG | No | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| eMMC | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| SDCard | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| NAND | No | No | No | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| ADC | **Yes** | **Yes** | **Yes** | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| CVBS Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| HDMI Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| CEC | No | No | No | *N/A* | No | No | No |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| Thermal Sensor | No | No | No | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| LCD/LVDS Output | No | *N/A* | No | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| MIPI DSI Output | *N/A* | *N/A* | *N/A* | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| SoC (version) information | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
+| PCIe (+NVMe) | *N/A* | *N/A* | *N/A* | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
Board Documentation
-------------------
beelink-gtking
beelink-gtkingpro
+ jethub-j100
+ jethub-j80
khadas-vim2
khadas-vim3l
khadas-vim3
p201
p212
q200
+ radxa-zero
s400
sei510
sei610
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for JetHub J100
+=======================
+
+JetHome Jethub D1 (http://jethome.ru/jethub-d1) is a home automation
+controller manufactured by JetHome with the following specifications:
+
+ - Amlogic A113X (ARM Cortex-A53) quad-core up to 1.5GHz
+ - no video out
+ - 512Mb/1GB DDR3
+ - 8/16GB eMMC flash
+ - 1 x USB 2.0
+ - 1 x 10/100Mbps ethernet
+ - WiFi / Bluetooth AMPAK AP6255 (Broadcom BCM43455) IEEE
+ 802.11a/b/g/n/ac, Bluetooth 4.2.
+ - TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output
+ power and Zigbee 3.0 support.
+ - 2 x gpio LEDS
+ - GPIO user Button
+ - 1 x 1-Wire
+ - 2 x RS-485
+ - 4 x dry contact digital GPIO inputs
+ - 3 x relay GPIO outputs
+ - DC source with a voltage of 9 to 56 V / Passive POE
+ - DIN Rail Mounting case
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make jethub_j100_defconfig
+ $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain binaries
+from the git tree published by the board vendor:
+
+.. code-block:: bash
+
+ $ git clone https://github.com/jethome-ru/jethub-aml-tools jethub-u-boot
+ $ cd jethub-u-boot
+ $ export FIPDIR=$PWD
+
+Go back to mainline U-boot source tree then :
+
+.. code-block:: bash
+
+ $ mkdir fip
+
+ $ cp $FIPDIR/j100/bl2.bin fip/
+ $ cp $FIPDIR/j100/acs.bin fip/
+ $ cp $FIPDIR/j100/bl21.bin fip/
+ $ cp $FIPDIR/j100/bl30.bin fip/
+ $ cp $FIPDIR/j100/bl301.bin fip/
+ $ cp $FIPDIR/j100/bl31.img fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ $FIPDIR/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+ $ $FIPDIR/blx_fix.sh \
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ $ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ $ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
+ $ $FIPDIR/j100/aml_encrypt_axg --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ $ $FIPDIR/j100/aml_encrypt_axg --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc --level v3
+
+and then write the image to eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/your_emmc_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for JetHub J80
+======================
+
+JetHome Jethub H1 (http://jethome.ru/jethub-h1) is a home automation
+controller manufactured by JetHome with the following specifications:
+
+ - Amlogic S905W (ARM Cortex-A53) quad-core up to 1.5GHz
+ - No video out
+ - 1GB DDR3
+ - 8/16GB eMMC flash
+ - 2 x USB 2.0
+ - 1 x 10/100Mbps ethernet
+ - SDIO WiFi / Bluetooth RTL8822CS IEEE 802.11a/b/g/n/ac, Bluetooth 5.0.
+ - TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output
+ power and Zigbee 3.0 support.
+ - MicroSD 2.x/3.x/4.x DS/HS cards.
+ - 1 x gpio LED
+ - ADC user Button
+ - DC source 5V microUSB
+ - Square plastic case
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make jethub_j80_defconfig
+ $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain binaries
+from the git tree published by the board vendor:
+
+.. code-block:: bash
+
+ $ git clone https://github.com/jethome-ru/jethub-aml-tools jethub-u-boot
+ $ cd jethub-u-boot
+ $ export FIPDIR=$PWD
+
+Go back to mainline U-Boot source tree then :
+
+.. code-block:: bash
+
+ $ mkdir fip
+
+ $ cp $FIPDIR/j80/bl2.bin fip/
+ $ cp $FIPDIR/j80/acs.bin fip/
+ $ cp $FIPDIR/j80/bl21.bin fip/
+ $ cp $FIPDIR/j80/bl30.bin fip/
+ $ cp $FIPDIR/j80/bl301.bin fip/
+ $ cp $FIPDIR/j80/bl31.img fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ $FIPDIR/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+ $ $FIPDIR/blx_fix.sh \
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $FIPDIR/j80/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+ $ $FIPDIR/j80/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+ $ $FIPDIR/j80/aml_encrypt_gxl --bl3enc --input fip/bl33.bin --compress lz4
+ $ $FIPDIR/j80/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+ $ $FIPDIR/j80/aml_encrypt_gxl --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
+
+and then write the image to SD/eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/your_sd_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
- UART serial
- Infrared receiver
+The ODROID-HC4 is a variant with a PCIe-SATA controller, the same commands
+applies for HC4.
+
Schematics are available on the manufacturer website.
U-Boot compilation
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Radxa Zero
+=====================
+
+Radxa Zero is a small form factor SBC based on the Amlogic S905Y2
+chipset that ships in a number of RAM/eMMC configurations:
+
+Boards with 512MB/1GB LPDDR4 RAM have no eMMC storage and BCM43436
+wireless (2.4GHz b/g/n) while 2GB/4GB boards have 8/16/32/64/128GB
+eMMC storage and BCM4345 wireless (2.4/5GHz a/b/g/n/ac).
+
+- Amlogic S905Y2 quad-core Cortex-A53
+- Mali G31-MP2 GPU
+- HDMI 2.1 output (micro)
+- 1x USB 2.0 port - Type C (OTG)
+- 1x USB 3.0 port - Type C (Host)
+- 1x micro SD Card slot
+- 40 Pin GPIO header
+
+Schematics are available on the manufacturer website:
+
+https://dl.radxa.com/zero/docs/hw/RADAX_ZERO_V13_SCH_20210309.pdf
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make radxa-zero_defconfig
+ $ make
+
+Image creation
+--------------
+
+Amlogic does not provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+git trees published by the board vendor:
+
+.. code-block:: bash
+
+ $ git clone -b radxa-zero-v2021.07 https://github.com/radxa/u-boot.git
+ $ git clone https://github.com/radxa/fip.git
+
+ $ sudo apt-get install -y gcc-aarch64-linux-gnu device-tree-compiler libncurses5 libncurses5-dev
+ $ sudo apt-get install -y bc python dosfstools flex build-essential libssl-dev mtools
+
+ $ wget https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz
+ $ sudo tar xvf gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz -C /opt
+
+ $ export CROSS_COMPILE=/opt/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf/bin/aarch64-none-elf-
+ $ export ARCH=arm
+ $ cd u-boot
+ $ make radxa-zero_defconfig
+ $ make
+
+ $ cp u-boot.bin ../fip/radxa-zero/bl33.bin
+ $ cd ../fip/radxa-zero
+ $ make
+
+This will generate:
+
+.. code-block:: bash
+
+ $ u-boot.bin u-boot.bin.sd.bin u-boot.bin.usb.bl2 u-boot.bin.usb.tpl
+
+Then write the image to SD with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/your_sd_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
Rockchip is SoC solutions provider for tablets & PCs, streaming media
TV boxes, AI audio & vision, IoT hardware.
-A wide range of Rockchip SoCs with associated boardsare supported in
+A wide range of Rockchip SoCs with associated boards are supported in
mainline U-Boot.
-List of mainline supported rockchip boards:
+List of mainline supported Rockchip boards:
* rk3036
- Rockchip Evb-RK3036 (evb-rk3036)
- Kylin (kylin_rk3036)
* rk3128
- Rockchip Evb-RK3128 (evb-rk3128)
+* rk3188
+ - Radxa Rock (rock)
* rk3229
- Rockchip Evb-RK3229 (evb-rk3229)
* rk3288
* rv1108
- Rockchip Evb-rv1108 (evb-rv1108)
- Elgin-R1 (elgin-rv1108)
-* rv3188
- - Radxa Rock (rock)
Building
--------
make realclean
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399
-Specify the PLAT= with desired rockchip platform to build TF-A for.
+Specify the PLAT= with desired Rockchip platform to build TF-A for.
U-Boot
^^^^^^
SD Card
^^^^^^^
-All rockchip platforms, except rk3128 (which doesn't use SPL) are now
+All Rockchip platforms, except rk3128 (which doesn't use SPL) are now
supporting single boot image using binman and pad_cat.
To write an image that boots from an SD card (assumed to be /dev/sda)::
eMMC
^^^^
-eMMC flash would probe on mmc0 in most of the rockchip platforms.
+eMMC flash would probe on mmc0 in most of the Rockchip platforms.
Create GPT partition layout as defined in configurations::
sudo fastboot -i 0x2207 flash loader1 idbloader.img
sudo fastboot -i 0x2207 flash loader2 u-boot.itb
-Note: for rockchip 32-bit platforms the U-Boot proper image
+Note: for Rockchip 32-bit platforms the U-Boot proper image
is u-boot-dtb.img
SPI
TODO
----
-- Add rockchip idbloader image building
-- Add rockchip TPL image building
+- Add Rockchip idbloader image building
+- Add Rockchip TPL image building
- Document SPI flash boot
- Add missing SoC's with it boards list
* O=<dir> - generate all output files in directory <dir>, including .config
* V=1 - verbose build
+Devicetree compiler
+~~~~~~~~~~~~~~~~~~~
+
+Boards that use `CONFIG_OF_CONTROL` (i.e. almost all of them) need the
+devicetree compiler (dtc). Those with `CONFIG_PYLIBFDT` need pylibfdt, a Python
+library for accessing devicetree data. Suitable versions of these are included
+in the U-Boot tree in `scripts/dtc` and built automatically as needed.
+
+To use the system versions of these, use the DTC parameter, for example
+
+.. code-block:: bash
+
+ DTC=/usr/bin/dtc make
+
+In this case, dtc and pylibfdt are not built. The build checks that the version
+of dtc is new enough. It also makes sure that pylibfdt is present, if needed
+(see `scripts_dtc` in the Makefile).
+
+Note that the :doc:`tools` are always built with the included version of libfdt
+so it is not possible to build U-Boot tools with a system libfdt, at present.
+
Other build targets
~~~~~~~~~~~~~~~~~~~
browser, but may be read directly as plain text, perhaps with the aid of the
`html2text` utility.
+If sandbox crashes (e.g. with a segfault) you will see message like this::
+
+
+ test/py/u_boot_spawn.py:171: in expect
+ c = os.read(self.fd, 1024).decode(errors='replace')
+ E ValueError: U-Boot exited with signal 11 (Signals.SIGSEGV)
+
+
+Controlling output
+~~~~~~~~~~~~~~~~~~
+
+By default a short backtrace is reported. If you would like a longer one,
+pass ``--tb=long`` when running the test. See the pytest documentation for
+more options.
+
Running tests in parallel
~~~~~~~~~~~~~~~~~~~~~~~~~
--- /dev/null
+* MAX7320 I/O expanders
+
+The original maxim 7320 i/o expander offers 8 bit push/pull outputs.
+There exists some clones which offers 16 bit.
+
+Required Properties:
+
+ - compatible: should be one of the following.
+ - "maxim,max7320"
+
+ - reg: I2C slave address.
+
+ - gpio-controller: Marks the device node as a gpio controller.
+ - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
+ cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
+ GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
+
+Optional Properties:
+
+ - ngpios: tell the driver how many gpios the device offers.
+ if the property is omitted, 8bit (original maxim) is assumed.
+
+Please refer to gpio.txt in this directory for details of the common GPIO
+bindings used by client devices.
+
+Example: MAX7320 I/O expander node
+
+ ledgpio: max7320@5d {
+ status = "okay";
+ compatible = "maxim,max7320";
+ reg = <0x5d>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <16>;
+ };
+
--- /dev/null
+Microchip AT91 PWM controller for SAMA5D2
+
+Required properties:
+ - compatible: Should be "atmel,sama5d2-pwm"
+ - reg: Physical base address and length of the controller's registers.
+ - clocks: Should contain a clock identifier for the PWM's parent clock.
+ - #pwm-cells: Should be 3.
+
+Example:
+
+pwm0: pwm@f802c000 {
+ compatible = "atmel,sama5d2-pwm";
+ reg = <0xf802c000 0x4000>;
+ clocks = <&pwm_clk>;
+ #pwm-cells = <3>;
+};
{
struct sifive_ccache *priv = dev_get_priv(dev);
- info->base = (phys_addr_t)priv->base;
+ info->base = (uintptr_t)priv->base;
return 0;
}
const struct clk_ops clk_fixed_rate_ops = {
.get_rate = clk_fixed_rate_get_rate,
.enable = dummy_enable,
+ .disable = dummy_enable,
};
void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev,
* Whether we swapped r and od while enforcing frequency limits
*/
bool swapped = false;
+ /*
+ * Whether the intermediate frequencies are out-of-spec
+ */
+ bool out_of_spec;
u64 last_od = od;
u64 last_r = r;
* aren't in spec, try swapping r and od. If everything is
* in-spec, calculate the relative error.
*/
- while (true) {
+again:
+ out_of_spec = false;
+ if (r > max_r) {
+ out_of_spec = true;
+ } else {
/*
- * Whether the intermediate frequencies are out-of-spec
+ * There is no way to only divide once; we need
+ * to examine the frequency with and without the
+ * effect of od.
*/
- bool out_of_spec = false;
+ u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r);
- if (r > max_r) {
+ if (vco > 1750000000 || vco < 340000000)
out_of_spec = true;
- } else {
- /*
- * There is no way to only divide once; we need
- * to examine the frequency with and without the
- * effect of od.
- */
- u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r);
+ }
+
+ if (out_of_spec) {
+ u64 new_r, new_od;
+
+ if (!swapped) {
+ u64 tmp = r;
- if (vco > 1750000000 || vco < 340000000)
- out_of_spec = true;
+ r = od;
+ od = tmp;
+ swapped = true;
+ goto again;
}
- if (out_of_spec) {
- if (!swapped) {
- u64 tmp = r;
-
- r = od;
- od = tmp;
- swapped = true;
- continue;
- } else {
- /*
- * Try looking ahead to see if there are
- * additional factors for the same
- * product.
- */
- if (i + 1 < ARRAY_SIZE(factors)) {
- u64 new_r, new_od;
-
- i++;
- new_r = UNPACK_R(factors[i]);
- new_od = UNPACK_OD(factors[i]);
- if (r * od == new_r * new_od) {
- r = new_r;
- od = new_od;
- swapped = false;
- continue;
- }
- i--;
+ /*
+ * Try looking ahead to see if there are additional
+ * factors for the same product.
+ */
+ if (i + 1 < ARRAY_SIZE(factors)) {
+ i++;
+ new_r = UNPACK_R(factors[i]);
+ new_od = UNPACK_OD(factors[i]);
+ if (r * od == new_r * new_od) {
+ r = new_r;
+ od = new_od;
+ swapped = false;
+ goto again;
+ }
+ i--;
+ }
+
+ /*
+ * Try looking back to see if there is a worse ratio
+ * that we could try anyway
+ */
+ while (i > 0) {
+ i--;
+ new_r = UNPACK_R(factors[i]);
+ new_od = UNPACK_OD(factors[i]);
+ /*
+ * Don't loop over factors for the same product
+ * to avoid getting stuck because of the above
+ * clause
+ */
+ if (r * od != new_r * new_od) {
+ if (new_r * new_od > last_r * last_od) {
+ r = new_r;
+ od = new_od;
+ swapped = false;
+ goto again;
}
break;
}
}
- error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od);
- /* The lower 16 bits are spurious */
- error = abs((error - BIT(32))) >> 16;
+ /* We ran out of things to try */
+ continue;
+ }
- if (error < best_error) {
- best->r = r;
- best->f = f;
- best->od = od;
- best_error = error;
- }
- break;
+ error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od);
+ /* The lower 16 bits are spurious */
+ error = abs((error - BIT(32))) >> 16;
+
+ if (error < best_error) {
+ best->r = r;
+ best->f = f;
+ best->od = od;
+ best_error = error;
}
} while (f < 64 && i + 1 < ARRAY_SIZE(factors) && error != 0);
+ log_debug("best error %lld\n", best_error);
if (best_error == S64_MAX)
return -EINVAL;
- log_debug("best error %lld\n", best_error);
return 0;
}
u32 reg;
ulong calc_rate;
- if (rate_in < 0)
- return rate_in;
-
err = k210_pll_calc_config(rate, rate_in, &config);
if (err)
return err;
u64 r, f, od;
u32 reg = readl(priv->base + k210_plls[id].off);
- if (rate_in < 0 || (reg & K210_PLL_BYPASS))
+ if (reg & K210_PLL_BYPASS)
return rate_in;
if (!(reg & K210_PLL_PWRD))
parent = k210_clk_get_parent(priv, id);
parent_rate = do_k210_clk_get_rate(priv, parent);
+ if (IS_ERR_VALUE(parent_rate))
+ return parent_rate;
if (k210_clks[id].flags & K210_CLKF_PLL)
return k210_pll_get_rate(priv, k210_clks[id].pll, parent_rate);
parent = k210_clk_get_parent(priv, clk->id);
rate_in = do_k210_clk_get_rate(priv, parent);
+ if (IS_ERR_VALUE(rate_in))
+ return rate_in;
log_debug("id=%ld rate=%lu rate_in=%lu\n", clk->id, rate, rate_in);
case PLL_NPLL:
ret = px30_clk_set_pll_rate(priv, NPLL, rate);
break;
+ case PLL_CPLL:
+ ret = px30_clk_set_pll_rate(priv, CPLL, rate);
+ break;
case ARMCLK:
ret = px30_armclk_set_clk(priv, rate);
break;
switch (rate) {
case OSC_HZ:
+ case 26 * MHz:
src_clk = CLK_SDMMC_SEL_24M;
break;
case 400 * MHz:
case SCLK_SFC_SEL_125M:
return 125 * MHz;
case SCLK_SFC_SEL_150M:
- return 150 * KHz;
+ return 150 * MHz;
default:
return -ENOENT;
}
case 125 * MHz:
src_clk = SCLK_SFC_SEL_125M;
break;
- case 150 * KHz:
+ case 150 * MHz:
src_clk = SCLK_SFC_SEL_150M;
break;
default:
case BCLK_EMMC:
rate = rk3568_emmc_get_bclk(priv);
break;
+ case TCLK_EMMC:
+ rate = OSC_HZ;
+ break;
#ifndef CONFIG_SPL_BUILD
case ACLK_VOP:
rate = rk3568_aclk_vop_get_clk(priv);
case BCLK_EMMC:
ret = rk3568_emmc_set_bclk(priv, rate);
break;
+ case TCLK_EMMC:
+ ret = OSC_HZ;
+ break;
#ifndef CONFIG_SPL_BUILD
case ACLK_VOP:
ret = rk3568_aclk_vop_set_clk(priv, rate);
struct prci_clk_desc *data =
(struct prci_clk_desc *)dev_get_driver_data(dev);
- pd->va = (void *)dev_read_addr(dev);
- if (IS_ERR(pd->va))
- return PTR_ERR(pd->va);
+ pd->va = dev_read_addr_ptr(dev);
+ if (!pd->va)
+ return -EINVAL;
err = clk_get_by_index(dev, 0, &pd->parent_hfclk);
if (err)
This enables common clock driver support for platforms based
on Allwinner A31/A31s SoC.
+config CLK_SUN6I_A31_R
+ bool "Clock driver for Allwinner A31 generation PRCM"
+ default SUNXI_GEN_SUN6I
+ help
+ This enables common clock driver support for the PRCM
+ in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs.
+
config CLK_SUN8I_A23
bool "Clock driver for Allwinner A23/A33"
default MACH_SUN8I_A23 || MACH_SUN8I_A33
This enables common clock driver support for platforms based
on Allwinner H6 SoC.
+config CLK_SUN50I_H6_R
+ bool "Clock driver for Allwinner H6 generation PRCM"
+ default SUN50I_GEN_H6
+ help
+ This enables common clock driver support for the PRCM
+ in Allwinner H6/H616 SoCs.
+
config CLK_SUN50I_H616
bool "Clock driver for Allwinner H616"
default MACH_SUN50I_H616
obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
+obj-$(CONFIG_CLK_SUN6I_A31_R) += clk_a31_r.o
obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
+obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun4i-a10-ccu.h>
#include <dt-bindings/reset/sun4i-a10-ccu.h>
#include <linux/bitops.h>
[CLK_AHB_GMAC] = GATE(0x064, BIT(17)),
+ [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
+ [CLK_APB1_I2C3] = GATE(0x06c, BIT(3)),
+ [CLK_APB1_I2C4] = GATE(0x06c, BIT(15)),
[CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
[CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
[CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun5i-ccu.h>
#include <dt-bindings/reset/sun5i-ccu.h>
#include <linux/bitops.h>
[CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
[CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
+ [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
[CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
[CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
[CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
#include <linux/bitops.h>
[CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
[CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
[RST_BUS_EHCI] = RESET(0x2c0, BIT(26)),
[RST_BUS_OHCI] = RESET(0x2c0, BIT(29)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun6i-a31-ccu.h>
#include <dt-bindings/reset/sun6i-a31-ccu.h>
#include <linux/bitops.h>
[CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)),
[CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)),
+ [CLK_APB2_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_APB2_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_APB2_I2C2] = GATE(0x06c, BIT(2)),
+ [CLK_APB2_I2C3] = GATE(0x06c, BIT(3)),
[CLK_APB2_UART0] = GATE(0x06c, BIT(16)),
[CLK_APB2_UART1] = GATE(0x06c, BIT(17)),
[CLK_APB2_UART2] = GATE(0x06c, BIT(18)),
[RST_AHB1_OHCI1] = RESET(0x2c0, BIT(30)),
[RST_AHB1_OHCI2] = RESET(0x2c0, BIT(31)),
+ [RST_APB2_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_APB2_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_APB2_I2C2] = RESET(0x2d8, BIT(2)),
+ [RST_APB2_I2C3] = RESET(0x2d8, BIT(3)),
[RST_APB2_UART0] = RESET(0x2d8, BIT(16)),
[RST_APB2_UART1] = RESET(0x2d8, BIT(17)),
[RST_APB2_UART2] = RESET(0x2d8, BIT(18)),
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) Samuel Holland <samuel@sholland.org>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <clk/sunxi.h>
+#include <dt-bindings/clock/sun8i-r-ccu.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate a31_r_gates[] = {
+ [CLK_APB0_PIO] = GATE(0x028, BIT(0)),
+ [CLK_APB0_IR] = GATE(0x028, BIT(1)),
+ [CLK_APB0_TIMER] = GATE(0x028, BIT(2)),
+ [CLK_APB0_RSB] = GATE(0x028, BIT(3)),
+ [CLK_APB0_UART] = GATE(0x028, BIT(4)),
+ [CLK_APB0_I2C] = GATE(0x028, BIT(6)),
+ [CLK_APB0_TWD] = GATE(0x028, BIT(7)),
+};
+
+static struct ccu_reset a31_r_resets[] = {
+ [RST_APB0_IR] = RESET(0x0b0, BIT(1)),
+ [RST_APB0_TIMER] = RESET(0x0b0, BIT(2)),
+ [RST_APB0_RSB] = RESET(0x0b0, BIT(3)),
+ [RST_APB0_UART] = RESET(0x0b0, BIT(4)),
+ [RST_APB0_I2C] = RESET(0x0b0, BIT(6)),
+};
+
+static const struct ccu_desc a31_r_ccu_desc = {
+ .gates = a31_r_gates,
+ .resets = a31_r_resets,
+};
+
+static int a31_r_clk_bind(struct udevice *dev)
+{
+ return sunxi_reset_bind(dev, ARRAY_SIZE(a31_r_resets));
+}
+
+static const struct udevice_id a31_r_clk_ids[] = {
+ { .compatible = "allwinner,sun8i-a83t-r-ccu",
+ .data = (ulong)&a31_r_ccu_desc },
+ { .compatible = "allwinner,sun8i-h3-r-ccu",
+ .data = (ulong)&a31_r_ccu_desc },
+ { .compatible = "allwinner,sun50i-a64-r-ccu",
+ .data = (ulong)&a31_r_ccu_desc },
+ { }
+};
+
+U_BOOT_DRIVER(clk_sun6i_a31_r) = {
+ .name = "sun6i_a31_r_ccu",
+ .id = UCLASS_CLK,
+ .of_match = a31_r_clk_ids,
+ .priv_auto = sizeof(struct ccu_priv),
+ .ops = &sunxi_clk_ops,
+ .probe = sunxi_clk_probe,
+ .bind = a31_r_clk_bind,
+};
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun50i-a64-ccu.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>
#include <linux/bitops.h>
[CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
[CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
[RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
[RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun9i-a80-ccu.h>
#include <dt-bindings/reset/sun9i-a80-ccu.h>
#include <linux/bitops.h>
[CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
[CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
+ [CLK_BUS_I2C0] = GATE(0x594, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x594, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x594, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x594, BIT(3)),
+ [CLK_BUS_I2C4] = GATE(0x594, BIT(4)),
[CLK_BUS_UART0] = GATE(0x594, BIT(16)),
[CLK_BUS_UART1] = GATE(0x594, BIT(17)),
[CLK_BUS_UART2] = GATE(0x594, BIT(18)),
[RST_BUS_SPI2] = RESET(0x5a0, BIT(22)),
[RST_BUS_SPI3] = RESET(0x5a0, BIT(23)),
+ [RST_BUS_I2C0] = RESET(0x5b4, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x5b4, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x5b4, BIT(2)),
+ [RST_BUS_I2C3] = RESET(0x5b4, BIT(3)),
+ [RST_BUS_I2C4] = RESET(0x5b4, BIT(4)),
[RST_BUS_UART0] = RESET(0x5b4, BIT(16)),
[RST_BUS_UART1] = RESET(0x5b4, BIT(17)),
[RST_BUS_UART2] = RESET(0x5b4, BIT(18)),
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun8i-a83t-ccu.h>
#include <dt-bindings/reset/sun8i-a83t-ccu.h>
#include <linux/bitops.h>
[CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
[CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
[RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
[RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun8i-h3-ccu.h>
#include <dt-bindings/reset/sun8i-h3-ccu.h>
#include <linux/bitops.h>
[CLK_BUS_OHCI2] = GATE(0x060, BIT(30)),
[CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
[RST_BUS_EPHY] = RESET(0x2c8, BIT(2)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun50i-h6-ccu.h>
#include <dt-bindings/reset/sun50i-h6-ccu.h>
#include <linux/bitops.h>
[CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
[CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
+ [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
+
[CLK_SPI0] = GATE(0x940, BIT(31)),
[CLK_SPI1] = GATE(0x944, BIT(31)),
[RST_BUS_UART2] = RESET(0x90c, BIT(18)),
[RST_BUS_UART3] = RESET(0x90c, BIT(19)),
+ [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
+ [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
+ [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
+ [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
+
[RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
[RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun50i-h616-ccu.h>
#include <dt-bindings/reset/sun50i-h616-ccu.h>
#include <linux/bitops.h>
[CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
[CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
+ [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
+ [CLK_BUS_I2C4] = GATE(0x91c, BIT(4)),
+
[CLK_SPI0] = GATE(0x940, BIT(31)),
[CLK_SPI1] = GATE(0x944, BIT(31)),
[RST_BUS_UART4] = RESET(0x90c, BIT(20)),
[RST_BUS_UART5] = RESET(0x90c, BIT(21)),
+ [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
+ [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
+ [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
+ [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
+ [RST_BUS_I2C4] = RESET(0x91c, BIT(20)),
+
[RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
[RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) Samuel Holland <samuel@sholland.org>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <clk/sunxi.h>
+#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
+#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate h6_r_gates[] = {
+ [CLK_R_APB1_TIMER] = GATE(0x11c, BIT(0)),
+ [CLK_R_APB1_TWD] = GATE(0x12c, BIT(0)),
+ [CLK_R_APB1_PWM] = GATE(0x13c, BIT(0)),
+ [CLK_R_APB2_UART] = GATE(0x18c, BIT(0)),
+ [CLK_R_APB2_I2C] = GATE(0x19c, BIT(0)),
+ [CLK_R_APB2_RSB] = GATE(0x1bc, BIT(0)),
+ [CLK_R_APB1_IR] = GATE(0x1cc, BIT(0)),
+ [CLK_R_APB1_W1] = GATE(0x1ec, BIT(0)),
+};
+
+static struct ccu_reset h6_r_resets[] = {
+ [RST_R_APB1_TIMER] = RESET(0x11c, BIT(16)),
+ [RST_R_APB1_TWD] = RESET(0x12c, BIT(16)),
+ [RST_R_APB1_PWM] = RESET(0x13c, BIT(16)),
+ [RST_R_APB2_UART] = RESET(0x18c, BIT(16)),
+ [RST_R_APB2_I2C] = RESET(0x19c, BIT(16)),
+ [RST_R_APB2_RSB] = RESET(0x1bc, BIT(16)),
+ [RST_R_APB1_IR] = RESET(0x1cc, BIT(16)),
+ [RST_R_APB1_W1] = RESET(0x1ec, BIT(16)),
+};
+
+static const struct ccu_desc h6_r_ccu_desc = {
+ .gates = h6_r_gates,
+ .resets = h6_r_resets,
+};
+
+static int h6_r_clk_bind(struct udevice *dev)
+{
+ return sunxi_reset_bind(dev, ARRAY_SIZE(h6_r_resets));
+}
+
+static const struct udevice_id h6_r_clk_ids[] = {
+ { .compatible = "allwinner,sun50i-h6-r-ccu",
+ .data = (ulong)&h6_r_ccu_desc },
+ { .compatible = "allwinner,sun50i-h616-r-ccu",
+ .data = (ulong)&h6_r_ccu_desc },
+ { }
+};
+
+U_BOOT_DRIVER(clk_sun6i_h6_r) = {
+ .name = "sun6i_h6_r_ccu",
+ .id = UCLASS_CLK,
+ .of_match = h6_r_clk_ids,
+ .priv_auto = sizeof(struct ccu_priv),
+ .ops = &sunxi_clk_ops,
+ .probe = sunxi_clk_probe,
+ .bind = h6_r_clk_bind,
+};
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun8i-r40-ccu.h>
#include <dt-bindings/reset/sun8i-r40-ccu.h>
#include <linux/bitops.h>
[CLK_BUS_GMAC] = GATE(0x064, BIT(17)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x06c, BIT(3)),
+ [CLK_BUS_I2C4] = GATE(0x06c, BIT(15)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
[RST_BUS_GMAC] = RESET(0x2c4, BIT(17)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
+ [RST_BUS_I2C3] = RESET(0x2d8, BIT(3)),
+ [RST_BUS_I2C4] = RESET(0x2d8, BIT(15)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
#include <log.h>
#include <reset.h>
#include <asm/io.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <linux/bitops.h>
#include <linux/log2.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun8i-v3s-ccu.h>
#include <dt-bindings/reset/sun8i-v3s-ccu.h>
#include <linux/bitops.h>
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_OTG] = GATE(0x060, BIT(24)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
struct clk_ti_reg clkmode_reg;
struct clk_ti_reg idlest_reg;
struct clk_ti_reg clksel_reg;
+ struct clk_ti_reg ssc_deltam_reg;
+ struct clk_ti_reg ssc_modfreq_reg;
struct clk clk_bypass;
struct clk clk_ref;
u16 last_rounded_mult;
u8 last_rounded_div;
+ u8 min_div;
ulong max_rate;
+ u32 ssc_modfreq;
+ u32 ssc_deltam;
+ bool ssc_downspread;
};
static ulong clk_ti_am3_dpll_round_rate(struct clk *clk, ulong rate)
err = rate;
err_min = rate;
ref_rate = clk_get_rate(&priv->clk_ref);
- for (d = 1; err_min && d <= 128; d++) {
+ for (d = priv->min_div; err_min && d <= 128; d++) {
for (m = 2; m <= 2047; m++) {
r = (ref_rate * m) / d;
err = abs(r - rate);
priv->last_rounded_mult = mult;
priv->last_rounded_div = div;
- dev_dbg(clk->dev, "rate=%ld, best_rate=%ld, mult=%d, div=%d\n", rate,
- ret, mult, div);
+ dev_dbg(clk->dev, "rate=%ld, min-div: %d, best_rate=%ld, mult=%d, div=%d\n",
+ rate, priv->min_div, ret, mult, div);
return ret;
}
return 0;
}
+/**
+ * clk_ti_am3_dpll_ssc_program - set spread-spectrum clocking registers
+ * @clk: struct clk * of DPLL to set
+ *
+ * Enable the DPLL spread spectrum clocking if frequency modulation and
+ * frequency spreading have been set, otherwise disable it.
+ */
+static void clk_ti_am3_dpll_ssc_program(struct clk *clk)
+{
+ struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
+ unsigned long ref_rate;
+ u32 v, ctrl, mod_freq_divider, exponent, mantissa;
+ u32 deltam_step, deltam_ceil;
+
+ ctrl = clk_ti_readl(&priv->clkmode_reg);
+
+ if (priv->ssc_modfreq && priv->ssc_deltam) {
+ ctrl |= CM_CLKMODE_DPLL_SSC_EN_MASK;
+
+ if (priv->ssc_downspread)
+ ctrl |= CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK;
+ else
+ ctrl &= ~CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK;
+
+ ref_rate = clk_get_rate(&priv->clk_ref);
+ mod_freq_divider =
+ (ref_rate / priv->last_rounded_div) / (4 * priv->ssc_modfreq);
+ if (priv->ssc_modfreq > (ref_rate / 70))
+ dev_warn(clk->dev,
+ "clock: SSC modulation frequency of DPLL %s greater than %ld\n",
+ clk->dev->name, ref_rate / 70);
+
+ exponent = 0;
+ mantissa = mod_freq_divider;
+ while ((mantissa > 127) && (exponent < 7)) {
+ exponent++;
+ mantissa /= 2;
+ }
+ if (mantissa > 127)
+ mantissa = 127;
+
+ v = clk_ti_readl(&priv->ssc_modfreq_reg);
+ v &= ~(CM_SSC_MODFREQ_DPLL_MANT_MASK | CM_SSC_MODFREQ_DPLL_EXP_MASK);
+ v |= mantissa << __ffs(CM_SSC_MODFREQ_DPLL_MANT_MASK);
+ v |= exponent << __ffs(CM_SSC_MODFREQ_DPLL_EXP_MASK);
+ clk_ti_writel(v, &priv->ssc_modfreq_reg);
+ dev_dbg(clk->dev,
+ "mod_freq_divider: %u, exponent: %u, mantissa: %u, modfreq_reg: 0x%x\n",
+ mod_freq_divider, exponent, mantissa, v);
+
+ deltam_step = priv->last_rounded_mult * priv->ssc_deltam;
+ deltam_step /= 10;
+ if (priv->ssc_downspread)
+ deltam_step /= 2;
+
+ deltam_step <<= __ffs(CM_SSC_DELTAM_DPLL_INT_MASK);
+ deltam_step /= 100;
+ deltam_step /= mod_freq_divider;
+ if (deltam_step > 0xFFFFF)
+ deltam_step = 0xFFFFF;
+
+ deltam_ceil = (deltam_step & CM_SSC_DELTAM_DPLL_INT_MASK) >>
+ __ffs(CM_SSC_DELTAM_DPLL_INT_MASK);
+ if (deltam_step & CM_SSC_DELTAM_DPLL_FRAC_MASK)
+ deltam_ceil++;
+
+ if ((priv->ssc_downspread &&
+ ((priv->last_rounded_mult - (2 * deltam_ceil)) < 20 ||
+ priv->last_rounded_mult > 2045)) ||
+ ((priv->last_rounded_mult - deltam_ceil) < 20 ||
+ (priv->last_rounded_mult + deltam_ceil) > 2045))
+ dev_warn(clk->dev,
+ "clock: SSC multiplier of DPLL %s is out of range\n",
+ clk->dev->name);
+
+ v = clk_ti_readl(&priv->ssc_deltam_reg);
+ v &= ~(CM_SSC_DELTAM_DPLL_INT_MASK | CM_SSC_DELTAM_DPLL_FRAC_MASK);
+ v |= deltam_step << __ffs(CM_SSC_DELTAM_DPLL_INT_MASK |
+ CM_SSC_DELTAM_DPLL_FRAC_MASK);
+ clk_ti_writel(v, &priv->ssc_deltam_reg);
+ dev_dbg(clk->dev,
+ "deltam_step: %u, deltam_ceil: %u, deltam_reg: 0x%x\n",
+ deltam_step, deltam_ceil, v);
+ } else {
+ ctrl &= ~CM_CLKMODE_DPLL_SSC_EN_MASK;
+ }
+
+ clk_ti_writel(ctrl, &priv->clkmode_reg);
+}
+
static ulong clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate)
{
struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
clk_ti_writel(v, &priv->clksel_reg);
+ clk_ti_am3_dpll_ssc_program(clk);
+
/* lock dpll */
clk_ti_am3_dpll_clken(priv, DPLL_EN_LOCK);
struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev);
struct clk_ti_am3_dpll_drv_data *data =
(struct clk_ti_am3_dpll_drv_data *)dev_get_driver_data(dev);
+ u32 min_div;
int err;
priv->max_rate = data->max_rate;
return err;
}
+ err = clk_ti_get_reg_addr(dev, 3, &priv->ssc_deltam_reg);
+ if (err) {
+ dev_err(dev, "failed to get SSC deltam register\n");
+ return err;
+ }
+
+ err = clk_ti_get_reg_addr(dev, 4, &priv->ssc_modfreq_reg);
+ if (err) {
+ dev_err(dev, "failed to get SSC modfreq register\n");
+ return err;
+ }
+
+ if (dev_read_u32(dev, "ti,ssc-modfreq-hz", &priv->ssc_modfreq))
+ priv->ssc_modfreq = 0;
+
+ if (dev_read_u32(dev, "ti,ssc-deltam", &priv->ssc_deltam))
+ priv->ssc_deltam = 0;
+
+ priv->ssc_downspread = dev_read_bool(dev, "ti,ssc-downspread");
+
+ if (dev_read_u32(dev, "ti,min-div", &min_div) || min_div == 0 ||
+ min_div > 128)
+ priv->min_div = 1;
+ else
+ priv->min_div = min_div;
+
return 0;
}
if (ret)
return ret;
- return lists_bind_fdt(parent, node, NULL, false);
+ return lists_bind_fdt(parent, node, NULL, NULL, false);
}
#endif
#endif
}
+void *devfdt_get_addr_index_ptr(const struct udevice *dev, int index)
+{
+ fdt_addr_t addr = devfdt_get_addr_index(dev, index);
+
+ return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr;
+}
+
fdt_addr_t devfdt_get_addr_size_index(const struct udevice *dev, int index,
fdt_size_t *size)
{
void *devfdt_get_addr_ptr(const struct udevice *dev)
{
- fdt_addr_t addr = devfdt_get_addr_index(dev, 0);
-
- return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr;
+ return devfdt_get_addr_index_ptr(dev, 0);
}
void *devfdt_remap_addr_index(const struct udevice *dev, int index)
}
int lists_bind_fdt(struct udevice *parent, ofnode node, struct udevice **devp,
- bool pre_reloc_only)
+ struct driver *drv, bool pre_reloc_only)
{
struct driver *driver = ll_entry_start(struct driver, driver);
const int n_ents = ll_entry_count(struct driver, driver);
for (entry = driver; entry != driver + n_ents; entry++) {
ret = driver_check_compatible(entry->of_match, &id,
compat);
+ if ((drv) && (drv == entry))
+ break;
if (!ret)
break;
}
pr_debug(" - ignoring disabled device\n");
continue;
}
- err = lists_bind_fdt(parent, node, NULL, pre_reloc_only);
+ err = lists_bind_fdt(parent, node, NULL, NULL, pre_reloc_only);
if (err && !ret) {
ret = err;
debug("%s: ret=%d\n", node_name, ret);
/* check for raw partition descriptor */
strcpy(env_desc_name, "fastboot_raw_partition_");
- strlcat(env_desc_name, name, PART_NAME_LEN);
+ strlcat(env_desc_name, name, sizeof(env_desc_name));
raw_part_desc = strdup(env_get(env_desc_name));
if (raw_part_desc == NULL)
return -ENODEV;
/* check for alias */
strcpy(env_alias_name, "fastboot_partition_alias_");
- strlcat(env_alias_name, name, PART_NAME_LEN);
+ strlcat(env_alias_name, name, sizeof(env_alias_name));
aliased_part_name = env_get(env_alias_name);
if (aliased_part_name != NULL)
ret = do_get_part_info(dev_desc, aliased_part_name,
help
Support for the LPC32XX GPIO driver.
+config MAX7320_GPIO
+ bool "MAX7320 I2C GPIO Expander driver"
+ depends on DM_GPIO && DM_I2C
+ help
+ Support for MAX7320 I2C 8/16-bit GPIO expander.
+ original maxim device has 8 push/pull outputs,
+ some clones offers 16bit.
+
config MCP230XX_GPIO
bool "MCP230XX GPIO driver"
depends on DM
obj-$(CONFIG_NX_GPIO) += nx_gpio.o
obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o
obj-$(CONFIG_NOMADIK_GPIO) += nmk_gpio.o
+obj-$(CONFIG_MAX7320_GPIO) += max7320_gpio.o
*/
#include <common.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/pmic_bus.h>
#include <asm/gpio.h>
#include <axp_pmic.h>
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * max7320 I2C GPIO EXPANDER DRIVER
+ *
+ * Copyright (C) 2021 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <asm-generic/gpio.h>
+#include <linux/bitops.h>
+
+struct max7320_chip {
+ u32 outreg;
+};
+
+static int max7320_direction_output(struct udevice *dev,
+ unsigned int offset, int value)
+{
+ struct max7320_chip *plat = dev_get_plat(dev);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
+
+ int ret;
+
+ if (value)
+ plat->outreg |= BIT(offset);
+ else
+ plat->outreg &= ~BIT(offset);
+
+ ret = dm_i2c_write(dev,
+ plat->outreg & 0xff,
+ (uint8_t *)&plat->outreg + 1,
+ uc_priv->gpio_count > 8 ? 1 : 0);
+ if (ret)
+ printf("%s i2c write failed to addr %x\n", __func__,
+ chip->chip_addr);
+
+ return ret;
+}
+
+static int max7320_get_value(struct udevice *dev, unsigned int offset)
+{
+ struct max7320_chip *plat = dev_get_plat(dev);
+
+ return (plat->outreg >> offset) & 0x1;
+}
+
+static int max7320_set_value(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ return max7320_direction_output(dev, offset, value);
+}
+
+static int max7320_get_function(struct udevice *dev, unsigned int offset)
+{
+ return GPIOF_OUTPUT;
+}
+
+static int max7320_ofdata_plat(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", 8);
+ if (uc_priv->gpio_count > 16) {
+ printf("%s: max7320 doesn't support more than 16 gpios!",
+ __func__);
+ return -EINVAL;
+ }
+
+ uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
+ "gpio-bank-name", NULL);
+ if (!uc_priv->bank_name)
+ uc_priv->bank_name = fdt_get_name(gd->fdt_blob,
+ dev_of_offset(dev), NULL);
+
+ return 0;
+}
+
+static int max7320_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ debug("%s GPIO controller with %d gpios probed\n",
+ uc_priv->bank_name, uc_priv->gpio_count);
+
+ return 0;
+}
+
+static const struct dm_gpio_ops max7320_gpio_ops = {
+ .direction_output = max7320_direction_output,
+ .set_value = max7320_set_value,
+ .get_value = max7320_get_value,
+ .get_function = max7320_get_function,
+};
+
+static const struct udevice_id max7320_gpio_ids[] = {
+ { .compatible = "maxim,max7320" },
+ { }
+};
+
+U_BOOT_DRIVER(gpio_max7320) = {
+ .name = "gpio_max7320",
+ .id = UCLASS_GPIO,
+ .ops = &max7320_gpio_ops,
+ .of_match = max7320_gpio_ids,
+ .of_to_plat = max7320_ofdata_plat,
+ .probe = max7320_gpio_probe,
+ .plat_auto = sizeof(struct max7320_chip),
+};
static int sifive_gpio_of_to_plat(struct udevice *dev)
{
struct sifive_gpio_plat *plat = dev_get_plat(dev);
- fdt_addr_t addr;
- addr = dev_read_addr(dev);
- if (addr == FDT_ADDR_T_NONE)
+ plat->base = dev_read_addr_ptr(dev);
+ if (!plat->base)
return -EINVAL;
- plat->base = (void *)addr;
return 0;
}
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
-#include <asm/arch/gpio.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm/device-internal.h>
#include <dt-bindings/gpio/gpio.h>
-#define SUNXI_GPIOS_PER_BANK SUNXI_GPIO_A_NR
-
struct sunxi_gpio_plat {
struct sunxi_gpio *regs;
const char *bank_name; /* Name of bank, e.g. "B" */
}
#endif /* DM_GPIO */
-int sunxi_name_to_gpio_bank(const char *name)
-{
- int group = 0;
-
- if (*name == 'P' || *name == 'p')
- name++;
- if (*name >= 'A') {
- group = *name - (*name > 'a' ? 'a' : 'A');
- return group;
- }
-
- return -1;
-}
-
#if CONFIG_IS_ENABLED(DM_GPIO)
/* TODO(sjg@chromium.org): Remove this function and use device tree */
int sunxi_name_to_gpio(const char *name)
_ Optional clock stretching
_ Software reset
+config SYS_I2C_SUN6I_P2WI
+ bool "Allwinner sun6i P2WI controller"
+ depends on ARCH_SUNXI
+ help
+ Support for the P2WI (Push/Pull 2 Wire Interface) controller embedded
+ in the Allwinner A31 and A31s SOCs. This interface is used to connect
+ to specific devices like the X-Powers AXP221 PMIC.
+
+config SYS_I2C_SUN8I_RSB
+ bool "Allwinner sun8i Reduced Serial Bus controller"
+ depends on ARCH_SUNXI
+ help
+ Support for Allwinner's Reduced Serial Bus (RSB) controller. This
+ controller is responsible for communicating with various RSB based
+ devices, such as X-Powers AXPxxx PMICs and AC100/AC200 CODEC ICs.
+
config SYS_I2C_SYNQUACER
bool "Socionext SynQuacer I2C controller"
depends on ARCH_SYNQUACER && DM_I2C
obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o
+obj-$(CONFIG_SYS_I2C_SUN6I_P2WI) += sun6i_p2wi.o
+obj-$(CONFIG_SYS_I2C_SUN8I_RSB) += sun8i_rsb.o
obj-$(CONFIG_SYS_I2C_SYNQUACER) += synquacer_i2c.o
obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
u32 clock_frequency_khz;
int ret;
- bus->base = (void __iomem *)devfdt_get_addr(dev);
+ bus->base = dev_read_addr_ptr(dev);
if (dev_read_u32(dev, "reg-shift", &bus->reg_shift)) {
/* no 'reg-shift', check for deprecated 'regstep' */
/* STM32 I2C control 1 */
#define STM32_I2C_CR1_ANFOFF BIT(12)
+#define STM32_I2C_CR1_DNF_MASK GENMASK(11, 8)
+#define STM32_I2C_CR1_DNF(n) (((n) & 0xf) << 8)
#define STM32_I2C_CR1_ERRIE BIT(7)
#define STM32_I2C_CR1_TCIE BIT(6)
#define STM32_I2C_CR1_STOPIE BIT(5)
#define STM32_I2C_MAX_LEN 0xff
-#define STM32_I2C_DNF_DEFAULT 0
-#define STM32_I2C_DNF_MAX 16
+#define STM32_I2C_DNF_MAX 15
-#define STM32_I2C_ANALOG_FILTER_ENABLE 1
#define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
#define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
* @clock_src: I2C clock source frequency (Hz)
* @rise_time: Rise time (ns)
* @fall_time: Fall time (ns)
- * @dnf: Digital filter coefficient (0-16)
+ * @dnf: value of digital filter to apply
* @analog_filter: Analog filter delay (On/Off)
- * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
*/
struct stm32_i2c_setup {
u32 speed_freq;
u32 fall_time;
u8 dnf;
bool analog_filter;
+};
+
+/**
+ * struct stm32_i2c_data - driver data for I2C configuration by compatible
+ * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
+ */
+struct stm32_i2c_data {
u32 fmp_clr_offset;
};
* @regmap_sreg: register address for setting Fast Mode Plus bits
* @regmap_creg: register address for clearing Fast Mode Plus bits
* @regmap_mask: mask for Fast Mode Plus bits
+ * @dnf_dt: value of digital filter requested via dt
*/
struct stm32_i2c_priv {
struct stm32_i2c_regs *regs;
struct clk clk;
- struct stm32_i2c_setup *setup;
+ struct stm32_i2c_setup setup;
u32 speed;
struct regmap *regmap;
u32 regmap_sreg;
u32 regmap_creg;
u32 regmap_mask;
+ u32 dnf_dt;
};
static const struct stm32_i2c_spec i2c_specs[] = {
},
};
-static const struct stm32_i2c_setup stm32f7_setup = {
- .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
- .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
- .dnf = STM32_I2C_DNF_DEFAULT,
- .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
+static const struct stm32_i2c_data stm32f7_data = {
+ .fmp_clr_offset = 0x00,
};
-static const struct stm32_i2c_setup stm32mp15_setup = {
- .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
- .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
- .dnf = STM32_I2C_DNF_DEFAULT,
- .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
+static const struct stm32_i2c_data stm32mp15_data = {
.fmp_clr_offset = 0x40,
};
return 0;
}
-static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
+static int stm32_i2c_compute_solutions(u32 i2cclk,
+ struct stm32_i2c_setup *setup,
const struct stm32_i2c_spec *specs,
struct list_head *solutions)
{
struct stm32_i2c_timings *v;
u32 p_prev = STM32_PRESC_MAX;
- u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
- setup->clock_src);
u32 af_delay_min, af_delay_max;
u16 p, l, a;
int sdadel_min, sdadel_max, scldel_min;
return ret;
}
-static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
+static int stm32_i2c_choose_solution(u32 i2cclk,
+ struct stm32_i2c_setup *setup,
const struct stm32_i2c_spec *specs,
struct list_head *solutions,
struct stm32_i2c_timings *s)
u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
setup->speed_freq);
u32 clk_error_prev = i2cbus;
- u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
- setup->clock_src);
u32 clk_min, clk_max;
u32 af_delay_min;
u32 dnf_delay;
}
static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
- struct stm32_i2c_setup *setup,
struct stm32_i2c_timings *output)
{
+ struct stm32_i2c_setup *setup = &i2c_priv->setup;
const struct stm32_i2c_spec *specs;
struct stm32_i2c_timings *v, *_v;
struct list_head solutions;
+ u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, setup->clock_src);
int ret;
specs = get_specs(setup->speed_freq);
return -EINVAL;
}
+ /* Analog and Digital Filters */
+ setup->dnf = DIV_ROUND_CLOSEST(i2c_priv->dnf_dt, i2cclk);
if (setup->dnf > STM32_I2C_DNF_MAX) {
log_err("DNF out of bound %d/%d\n",
setup->dnf, STM32_I2C_DNF_MAX);
}
INIT_LIST_HEAD(&solutions);
- ret = stm32_i2c_compute_solutions(setup, specs, &solutions);
+ ret = stm32_i2c_compute_solutions(i2cclk, setup, specs, &solutions);
if (ret)
goto exit;
- ret = stm32_i2c_choose_solution(setup, specs, &solutions, output);
+ ret = stm32_i2c_choose_solution(i2cclk, setup, specs, &solutions, output);
if (ret)
goto exit;
static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
struct stm32_i2c_timings *timing)
{
- struct stm32_i2c_setup *setup = i2c_priv->setup;
+ struct stm32_i2c_setup *setup = &i2c_priv->setup;
int ret = 0;
setup->speed_freq = i2c_priv->speed;
}
do {
- ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
+ ret = stm32_i2c_compute_timing(i2c_priv, timing);
if (ret) {
log_debug("failed to compute I2C timings.\n");
if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) {
writel(timing, ®s->timingr);
/* Enable I2C */
- if (i2c_priv->setup->analog_filter)
+ if (i2c_priv->setup.analog_filter)
clrbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF);
else
setbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF);
+
+ /* Program the Digital Filter */
+ clrsetbits_le32(®s->cr1, STM32_I2C_CR1_DNF_MASK,
+ STM32_I2C_CR1_DNF(i2c_priv->setup.dnf));
+
setbits_le32(®s->cr1, STM32_I2C_CR1_PE);
return 0;
static int stm32_of_to_plat(struct udevice *dev)
{
+ const struct stm32_i2c_data *data;
struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
u32 rise_time, fall_time;
int ret;
- i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev);
- if (!i2c_priv->setup)
+ data = (const struct stm32_i2c_data *)dev_get_driver_data(dev);
+ if (!data)
return -EINVAL;
- rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0);
- if (rise_time)
- i2c_priv->setup->rise_time = rise_time;
+ rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns",
+ STM32_I2C_RISE_TIME_DEFAULT);
+
+ fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns",
+ STM32_I2C_FALL_TIME_DEFAULT);
+
+ i2c_priv->dnf_dt = dev_read_u32_default(dev, "i2c-digital-filter-width-ns", 0);
+ if (!dev_read_bool(dev, "i2c-digital-filter"))
+ i2c_priv->dnf_dt = 0;
- fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0);
- if (fall_time)
- i2c_priv->setup->fall_time = fall_time;
+ i2c_priv->setup.analog_filter = dev_read_bool(dev, "i2c-analog-filter");
/* Optional */
i2c_priv->regmap = syscon_regmap_lookup_by_phandle(dev,
return ret;
i2c_priv->regmap_sreg = fmp[1];
- i2c_priv->regmap_creg = fmp[1] +
- i2c_priv->setup->fmp_clr_offset;
+ i2c_priv->regmap_creg = fmp[1] + data->fmp_clr_offset;
i2c_priv->regmap_mask = fmp[2];
}
};
static const struct udevice_id stm32_i2c_of_match[] = {
- { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup },
- { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_setup },
+ { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_data },
+ { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_data },
{}
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ */
+
+#include <axp_pmic.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <i2c.h>
+#include <time.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/p2wi.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+static int sun6i_p2wi_await_trans(struct sunxi_p2wi_reg *base)
+{
+ unsigned long tmo = timer_get_us() + 1000000;
+ int ret;
+ u8 reg;
+
+ while (1) {
+ reg = readl(&base->status);
+ if (reg & P2WI_STAT_TRANS_ERR) {
+ ret = -EIO;
+ break;
+ }
+ if (reg & P2WI_STAT_TRANS_DONE) {
+ ret = 0;
+ break;
+ }
+ if (timer_get_us() > tmo) {
+ ret = -ETIME;
+ break;
+ }
+ }
+ writel(reg, &base->status); /* Clear status bits */
+
+ return ret;
+}
+
+static int sun6i_p2wi_read(struct sunxi_p2wi_reg *base, const u8 addr, u8 *data)
+{
+ int ret;
+
+ writel(P2WI_DATADDR_BYTE_1(addr), &base->dataddr0);
+ writel(P2WI_DATA_NUM_BYTES(1) |
+ P2WI_DATA_NUM_BYTES_READ, &base->numbytes);
+ writel(P2WI_STAT_TRANS_DONE, &base->status);
+ writel(P2WI_CTRL_TRANS_START, &base->ctrl);
+
+ ret = sun6i_p2wi_await_trans(base);
+
+ *data = readl(&base->data0) & P2WI_DATA_BYTE_1_MASK;
+
+ return ret;
+}
+
+static int sun6i_p2wi_write(struct sunxi_p2wi_reg *base, const u8 addr, u8 data)
+{
+ writel(P2WI_DATADDR_BYTE_1(addr), &base->dataddr0);
+ writel(P2WI_DATA_BYTE_1(data), &base->data0);
+ writel(P2WI_DATA_NUM_BYTES(1), &base->numbytes);
+ writel(P2WI_STAT_TRANS_DONE, &base->status);
+ writel(P2WI_CTRL_TRANS_START, &base->ctrl);
+
+ return sun6i_p2wi_await_trans(base);
+}
+
+static int sun6i_p2wi_change_to_p2wi_mode(struct sunxi_p2wi_reg *base,
+ u8 slave_addr, u8 ctrl_reg,
+ u8 init_data)
+{
+ unsigned long tmo = timer_get_us() + 1000000;
+
+ writel(P2WI_PM_DEV_ADDR(slave_addr) |
+ P2WI_PM_CTRL_ADDR(ctrl_reg) |
+ P2WI_PM_INIT_DATA(init_data) |
+ P2WI_PM_INIT_SEND,
+ &base->pm);
+
+ while ((readl(&base->pm) & P2WI_PM_INIT_SEND)) {
+ if (timer_get_us() > tmo)
+ return -ETIME;
+ }
+
+ return 0;
+}
+
+static void sun6i_p2wi_init(struct sunxi_p2wi_reg *base)
+{
+ /* Enable p2wi and PIO clk, and de-assert their resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
+
+ /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
+ writel(P2WI_CTRL_RESET, &base->ctrl);
+ sdelay(0x100);
+ writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
+ &base->cc);
+}
+
+#if IS_ENABLED(CONFIG_AXP_PMIC_BUS)
+int p2wi_read(const u8 addr, u8 *data)
+{
+ struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
+
+ return sun6i_p2wi_read(base, addr, data);
+}
+
+int p2wi_write(const u8 addr, u8 data)
+{
+ struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
+
+ return sun6i_p2wi_write(base, addr, data);
+}
+
+int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
+{
+ struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
+
+ return sun6i_p2wi_change_to_p2wi_mode(base, slave_addr, ctrl_reg,
+ init_data);
+}
+
+void p2wi_init(void)
+{
+ struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
+
+ sun6i_p2wi_init(base);
+}
+#endif
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+struct sun6i_p2wi_priv {
+ struct sunxi_p2wi_reg *base;
+};
+
+static int sun6i_p2wi_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+ struct sun6i_p2wi_priv *priv = dev_get_priv(bus);
+
+ /* The hardware only supports SMBus-style transfers. */
+ if (nmsgs == 2 && msg[1].flags == I2C_M_RD && msg[1].len == 1)
+ return sun6i_p2wi_read(priv->base,
+ msg[0].buf[0], &msg[1].buf[0]);
+
+ if (nmsgs == 1 && msg[0].len == 2)
+ return sun6i_p2wi_write(priv->base,
+ msg[0].buf[0], msg[0].buf[1]);
+
+ return -EINVAL;
+}
+
+static int sun6i_p2wi_probe_chip(struct udevice *bus, uint chip_addr,
+ uint chip_flags)
+{
+ struct sun6i_p2wi_priv *priv = dev_get_priv(bus);
+
+ return sun6i_p2wi_change_to_p2wi_mode(priv->base, chip_addr,
+ AXP_PMIC_MODE_REG,
+ AXP_PMIC_MODE_P2WI);
+}
+
+static int sun6i_p2wi_probe(struct udevice *bus)
+{
+ struct sun6i_p2wi_priv *priv = dev_get_priv(bus);
+
+ priv->base = dev_read_addr_ptr(bus);
+
+ sun6i_p2wi_init(priv->base);
+
+ return 0;
+}
+
+static int sun6i_p2wi_child_pre_probe(struct udevice *child)
+{
+ struct dm_i2c_chip *chip = dev_get_parent_plat(child);
+
+ /* Ensure each transfer is for a single register. */
+ chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS;
+
+ return 0;
+}
+
+static const struct dm_i2c_ops sun6i_p2wi_ops = {
+ .xfer = sun6i_p2wi_xfer,
+ .probe_chip = sun6i_p2wi_probe_chip,
+};
+
+static const struct udevice_id sun6i_p2wi_ids[] = {
+ { .compatible = "allwinner,sun6i-a31-p2wi" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sun6i_p2wi) = {
+ .name = "sun6i_p2wi",
+ .id = UCLASS_I2C,
+ .of_match = sun6i_p2wi_ids,
+ .probe = sun6i_p2wi_probe,
+ .child_pre_probe = sun6i_p2wi_child_pre_probe,
+ .priv_auto = sizeof(struct sun6i_p2wi_priv),
+ .ops = &sun6i_p2wi_ops,
+};
+#endif /* CONFIG_IS_ENABLED(DM_I2C) */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Based on allwinner u-boot sources rsb code which is:
+ * (C) Copyright 2007-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * lixiang <lixiang@allwinnertech.com>
+ */
+
+#include <axp_pmic.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <i2c.h>
+#include <time.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/rsb.h>
+
+static int sun8i_rsb_await_trans(struct sunxi_rsb_reg *base)
+{
+ unsigned long tmo = timer_get_us() + 1000000;
+ u32 stat;
+ int ret;
+
+ while (1) {
+ stat = readl(&base->stat);
+ if (stat & RSB_STAT_LBSY_INT) {
+ ret = -EBUSY;
+ break;
+ }
+ if (stat & RSB_STAT_TERR_INT) {
+ ret = -EIO;
+ break;
+ }
+ if (stat & RSB_STAT_TOVER_INT) {
+ ret = 0;
+ break;
+ }
+ if (timer_get_us() > tmo) {
+ ret = -ETIME;
+ break;
+ }
+ }
+ writel(stat, &base->stat); /* Clear status bits */
+
+ return ret;
+}
+
+static int sun8i_rsb_do_trans(struct sunxi_rsb_reg *base)
+{
+ setbits_le32(&base->ctrl, RSB_CTRL_START_TRANS);
+
+ return sun8i_rsb_await_trans(base);
+}
+
+static int sun8i_rsb_read(struct sunxi_rsb_reg *base, u16 runtime_addr,
+ u8 reg_addr, u8 *data)
+{
+ int ret;
+
+ writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr);
+ writel(reg_addr, &base->addr);
+ writel(RSB_CMD_BYTE_READ, &base->cmd);
+
+ ret = sun8i_rsb_do_trans(base);
+ if (ret)
+ return ret;
+
+ *data = readl(&base->data) & 0xff;
+
+ return 0;
+}
+
+static int sun8i_rsb_write(struct sunxi_rsb_reg *base, u16 runtime_addr,
+ u8 reg_addr, u8 data)
+{
+ writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr);
+ writel(reg_addr, &base->addr);
+ writel(data, &base->data);
+ writel(RSB_CMD_BYTE_WRITE, &base->cmd);
+
+ return sun8i_rsb_do_trans(base);
+}
+
+static int sun8i_rsb_set_device_address(struct sunxi_rsb_reg *base,
+ u16 device_addr, u16 runtime_addr)
+{
+ writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) |
+ RSB_DEVADDR_DEVICE_ADDR(device_addr), &base->devaddr);
+ writel(RSB_CMD_SET_RTSADDR, &base->cmd);
+
+ return sun8i_rsb_do_trans(base);
+}
+
+static void sun8i_rsb_cfg_io(void)
+{
+#ifdef CONFIG_MACH_SUN8I
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
+ sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
+ sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
+ sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
+ sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
+#elif defined CONFIG_MACH_SUN9I
+ sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
+ sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
+ sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
+ sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
+ sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
+ sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
+#else
+#error unsupported MACH_SUNXI
+#endif
+}
+
+static void sun8i_rsb_set_clk(struct sunxi_rsb_reg *base)
+{
+ u32 div = 0;
+ u32 cd_odly = 0;
+
+ /* Source is Hosc24M, set RSB clk to 3Mhz */
+ div = 24000000 / 3000000 / 2 - 1;
+ cd_odly = div >> 1;
+ if (!cd_odly)
+ cd_odly = 1;
+
+ writel((cd_odly << 8) | div, &base->ccr);
+}
+
+static int sun8i_rsb_set_device_mode(struct sunxi_rsb_reg *base)
+{
+ unsigned long tmo = timer_get_us() + 1000000;
+
+ writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
+ &base->dmcr);
+
+ while (readl(&base->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
+ if (timer_get_us() > tmo)
+ return -ETIME;
+ }
+
+ return sun8i_rsb_await_trans(base);
+}
+
+static int sun8i_rsb_init(struct sunxi_rsb_reg *base)
+{
+ /* Enable RSB and PIO clk, and de-assert their resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
+
+ /* Setup external pins */
+ sun8i_rsb_cfg_io();
+
+ writel(RSB_CTRL_SOFT_RST, &base->ctrl);
+ sun8i_rsb_set_clk(base);
+
+ return sun8i_rsb_set_device_mode(base);
+}
+
+#if IS_ENABLED(CONFIG_AXP_PMIC_BUS)
+int rsb_read(const u16 runtime_addr, const u8 reg_addr, u8 *data)
+{
+ struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ return sun8i_rsb_read(base, runtime_addr, reg_addr, data);
+}
+
+int rsb_write(const u16 runtime_addr, const u8 reg_addr, u8 data)
+{
+ struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ return sun8i_rsb_write(base, runtime_addr, reg_addr, data);
+}
+
+int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
+{
+ struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ return sun8i_rsb_set_device_address(base, device_addr, runtime_addr);
+}
+
+int rsb_init(void)
+{
+ struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ return sun8i_rsb_init(base);
+}
+#endif
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+struct sun8i_rsb_priv {
+ struct sunxi_rsb_reg *base;
+};
+
+/*
+ * The mapping from hardware address to runtime address is fixed, and shared
+ * among all RSB drivers. See the comment in drivers/bus/sunxi-rsb.c in Linux.
+ */
+static int sun8i_rsb_get_runtime_address(u16 device_addr)
+{
+ if (device_addr == AXP_PMIC_PRI_DEVICE_ADDR)
+ return AXP_PMIC_PRI_RUNTIME_ADDR;
+ if (device_addr == AXP_PMIC_SEC_DEVICE_ADDR)
+ return AXP_PMIC_SEC_RUNTIME_ADDR;
+
+ return -ENXIO;
+}
+
+static int sun8i_rsb_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+ int runtime_addr = sun8i_rsb_get_runtime_address(msg->addr);
+ struct sun8i_rsb_priv *priv = dev_get_priv(bus);
+
+ if (runtime_addr < 0)
+ return runtime_addr;
+
+ /* The hardware only supports SMBus-style transfers. */
+ if (nmsgs == 2 && msg[1].flags == I2C_M_RD && msg[1].len == 1)
+ return sun8i_rsb_read(priv->base, runtime_addr,
+ msg[0].buf[0], &msg[1].buf[0]);
+
+ if (nmsgs == 1 && msg[0].len == 2)
+ return sun8i_rsb_write(priv->base, runtime_addr,
+ msg[0].buf[0], msg[0].buf[1]);
+
+ return -EINVAL;
+}
+
+static int sun8i_rsb_probe_chip(struct udevice *bus, uint chip_addr,
+ uint chip_flags)
+{
+ int runtime_addr = sun8i_rsb_get_runtime_address(chip_addr);
+ struct sun8i_rsb_priv *priv = dev_get_priv(bus);
+
+ if (runtime_addr < 0)
+ return runtime_addr;
+
+ return sun8i_rsb_set_device_address(priv->base, chip_addr, runtime_addr);
+}
+
+static int sun8i_rsb_probe(struct udevice *bus)
+{
+ struct sun8i_rsb_priv *priv = dev_get_priv(bus);
+
+ priv->base = dev_read_addr_ptr(bus);
+
+ return sun8i_rsb_init(priv->base);
+}
+
+static int sun8i_rsb_child_pre_probe(struct udevice *child)
+{
+ struct dm_i2c_chip *chip = dev_get_parent_plat(child);
+
+ /* Ensure each transfer is for a single register. */
+ chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS;
+
+ return 0;
+}
+
+static const struct dm_i2c_ops sun8i_rsb_ops = {
+ .xfer = sun8i_rsb_xfer,
+ .probe_chip = sun8i_rsb_probe_chip,
+};
+
+static const struct udevice_id sun8i_rsb_ids[] = {
+ { .compatible = "allwinner,sun8i-a23-rsb" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sun8i_rsb) = {
+ .name = "sun8i_rsb",
+ .id = UCLASS_I2C,
+ .of_match = sun8i_rsb_ids,
+ .probe = sun8i_rsb_probe,
+ .child_pre_probe = sun8i_rsb_child_pre_probe,
+ .priv_auto = sizeof(struct sun8i_rsb_priv),
+ .ops = &sun8i_rsb_ops,
+};
+#endif /* CONFIG_IS_ENABLED(DM_I2C) */
debug("%s(dev=%p)\n", __func__, dev);
ofnode_for_each_subnode(node, dev_ofnode(dev)) {
- ret = lists_bind_fdt(dev, node, &child, true);
+ ret = lists_bind_fdt(dev, node, &child, NULL, true);
if (ret)
return ret;
debug("bind child dev %s\n", child->name);
writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]);
writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]);
+ /* REN Enable on STRB Line for HS400 */
+ writel(RK_CLRSETBITS(0, 1 << 9), &phy->emmcphy_con[2]);
+
read_poll_timeout(readl, &phy->emmcphy_status, dllrdy,
PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1, 5000);
}
#include <mmc.h>
#include <clk.h>
#include <reset.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
-#include <asm-generic/gpio.h>
#include <linux/delay.h>
#ifndef CCM_MMC_CTRL_MODE_SEL_NEW
This is the driver for HyperBus controller on TI's AM65x and
other SoCs
+config STM32_FLASH
+ bool "STM32 MCU Flash driver"
+ depends on ARCH_STM32
+ help
+ This is the driver of embedded flash for some STMicroelectronics
+ STM32 MCU.
+
source "drivers/mtd/nand/Kconfig"
config SYS_NAND_MAX_CHIPS
endif
+config NAND_MXIC
+ bool "Macronix raw NAND controller"
+ select SYS_NAND_SELF_INIT
+ help
+ This selects the Macronix raw NAND controller driver.
+
config NAND_ZYNQ
bool "Support for Zynq Nand controller"
select SYS_NAND_SELF_INIT
obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
obj-$(CONFIG_NAND_PLAT) += nand_plat.o
obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o
+obj-$(CONFIG_NAND_MXIC) += mxic_nand.o
obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
obj-$(CONFIG_NAND_STM32_FMC2) += stm32_fmc2_nand.o
obj-$(CONFIG_CORTINA_NAND) += cortina_nand.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Macronix International Co., Ltd.
+ *
+ * Author:
+ * Zhengxun Li <zhengxunli@mxic.com.tw>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <malloc.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <dm/device_compat.h>
+#include <linux/bug.h>
+#include <linux/errno.h>
+#include <linux/iopoll.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/delay.h>
+
+#define HC_CFG 0x0
+#define HC_CFG_IF_CFG(x) ((x) << 27)
+#define HC_CFG_DUAL_SLAVE BIT(31)
+#define HC_CFG_INDIVIDUAL BIT(30)
+#define HC_CFG_NIO(x) (((x) / 4) << 27)
+#define HC_CFG_TYPE(s, t) ((t) << (23 + ((s) * 2)))
+#define HC_CFG_TYPE_SPI_NOR 0
+#define HC_CFG_TYPE_SPI_NAND 1
+#define HC_CFG_TYPE_SPI_RAM 2
+#define HC_CFG_TYPE_RAW_NAND 3
+#define HC_CFG_SLV_ACT(x) ((x) << 21)
+#define HC_CFG_CLK_PH_EN BIT(20)
+#define HC_CFG_CLK_POL_INV BIT(19)
+#define HC_CFG_BIG_ENDIAN BIT(18)
+#define HC_CFG_DATA_PASS BIT(17)
+#define HC_CFG_IDLE_SIO_LVL(x) ((x) << 16)
+#define HC_CFG_MAN_START_EN BIT(3)
+#define HC_CFG_MAN_START BIT(2)
+#define HC_CFG_MAN_CS_EN BIT(1)
+#define HC_CFG_MAN_CS_ASSERT BIT(0)
+
+#define INT_STS 0x4
+#define INT_STS_EN 0x8
+#define INT_SIG_EN 0xc
+#define INT_STS_ALL GENMASK(31, 0)
+#define INT_RDY_PIN BIT(26)
+#define INT_RDY_SR BIT(25)
+#define INT_LNR_SUSP BIT(24)
+#define INT_ECC_ERR BIT(17)
+#define INT_CRC_ERR BIT(16)
+#define INT_LWR_DIS BIT(12)
+#define INT_LRD_DIS BIT(11)
+#define INT_SDMA_INT BIT(10)
+#define INT_DMA_FINISH BIT(9)
+#define INT_RX_NOT_FULL BIT(3)
+#define INT_RX_NOT_EMPTY BIT(2)
+#define INT_TX_NOT_FULL BIT(1)
+#define INT_TX_EMPTY BIT(0)
+
+#define HC_EN 0x10
+#define HC_EN_BIT BIT(0)
+
+#define TXD(x) (0x14 + ((x) * 4))
+#define RXD 0x24
+
+#define SS_CTRL(s) (0x30 + ((s) * 4))
+#define LRD_CFG 0x44
+#define LWR_CFG 0x80
+#define RWW_CFG 0x70
+#define OP_READ BIT(23)
+#define OP_DUMMY_CYC(x) ((x) << 17)
+#define OP_ADDR_BYTES(x) ((x) << 14)
+#define OP_CMD_BYTES(x) (((x) - 1) << 13)
+#define OP_OCTA_CRC_EN BIT(12)
+#define OP_DQS_EN BIT(11)
+#define OP_ENHC_EN BIT(10)
+#define OP_PREAMBLE_EN BIT(9)
+#define OP_DATA_DDR BIT(8)
+#define OP_DATA_BUSW(x) ((x) << 6)
+#define OP_ADDR_DDR BIT(5)
+#define OP_ADDR_BUSW(x) ((x) << 3)
+#define OP_CMD_DDR BIT(2)
+#define OP_CMD_BUSW(x) (x)
+#define OP_BUSW_1 0
+#define OP_BUSW_2 1
+#define OP_BUSW_4 2
+#define OP_BUSW_8 3
+
+#define OCTA_CRC 0x38
+#define OCTA_CRC_IN_EN(s) BIT(3 + ((s) * 16))
+#define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16)))
+#define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16))
+
+#define ONFI_DIN_CNT(s) (0x3c + (s))
+
+#define LRD_CTRL 0x48
+#define RWW_CTRL 0x74
+#define LWR_CTRL 0x84
+#define LMODE_EN BIT(31)
+#define LMODE_SLV_ACT(x) ((x) << 21)
+#define LMODE_CMD1(x) ((x) << 8)
+#define LMODE_CMD0(x) (x)
+
+#define LRD_ADDR 0x4c
+#define LWR_ADDR 0x88
+#define LRD_RANGE 0x50
+#define LWR_RANGE 0x8c
+
+#define AXI_SLV_ADDR 0x54
+
+#define DMAC_RD_CFG 0x58
+#define DMAC_WR_CFG 0x94
+#define DMAC_CFG_PERIPH_EN BIT(31)
+#define DMAC_CFG_ALLFLUSH_EN BIT(30)
+#define DMAC_CFG_LASTFLUSH_EN BIT(29)
+#define DMAC_CFG_QE(x) (((x) + 1) << 16)
+#define DMAC_CFG_BURST_LEN(x) (((x) + 1) << 12)
+#define DMAC_CFG_BURST_SZ(x) ((x) << 8)
+#define DMAC_CFG_DIR_READ BIT(1)
+#define DMAC_CFG_START BIT(0)
+
+#define DMAC_RD_CNT 0x5c
+#define DMAC_WR_CNT 0x98
+
+#define SDMA_ADDR 0x60
+
+#define DMAM_CFG 0x64
+#define DMAM_CFG_START BIT(31)
+#define DMAM_CFG_CONT BIT(30)
+#define DMAM_CFG_SDMA_GAP(x) (fls((x) / 8192) << 2)
+#define DMAM_CFG_DIR_READ BIT(1)
+#define DMAM_CFG_EN BIT(0)
+
+#define DMAM_CNT 0x68
+
+#define LNR_TIMER_TH 0x6c
+
+#define RDM_CFG0 0x78
+#define RDM_CFG0_POLY(x) (x)
+
+#define RDM_CFG1 0x7c
+#define RDM_CFG1_RDM_EN BIT(31)
+#define RDM_CFG1_SEED(x) (x)
+
+#define LWR_SUSP_CTRL 0x90
+#define LWR_SUSP_CTRL_EN BIT(31)
+
+#define DMAS_CTRL 0x9c
+#define DMAS_CTRL_EN BIT(31)
+#define DMAS_CTRL_DIR_READ BIT(30)
+
+#define DATA_STROB 0xa0
+#define DATA_STROB_EDO_EN BIT(2)
+#define DATA_STROB_INV_POL BIT(1)
+#define DATA_STROB_DELAY_2CYC BIT(0)
+
+#define IDLY_CODE(x) (0xa4 + ((x) * 4))
+#define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8))
+
+#define GPIO 0xc4
+#define GPIO_PT(x) BIT(3 + ((x) * 16))
+#define GPIO_RESET(x) BIT(2 + ((x) * 16))
+#define GPIO_HOLDB(x) BIT(1 + ((x) * 16))
+#define GPIO_WPB(x) BIT((x) * 16)
+
+#define HC_VER 0xd0
+
+#define HW_TEST(x) (0xe0 + ((x) * 4))
+
+#define MXIC_NFC_MAX_CLK_HZ 50000000
+#define IRQ_TIMEOUT 1000
+
+struct mxic_nand_ctrl {
+ struct clk *send_clk;
+ struct clk *send_dly_clk;
+ void __iomem *regs;
+ struct nand_chip nand_chip;
+};
+
+/*
+ * struct mxic_nfc_command_format - Defines NAND flash command format
+ * @start_cmd: First cycle command (Start command)
+ * @end_cmd: Second cycle command (Last command)
+ * @addr_len: Number of address cycles required to send the address
+ * @read: Direction of command
+ */
+
+struct mxic_nfc_command_format {
+ int start_cmd;
+ int end_cmd;
+ u8 addr_len;
+ bool read;
+};
+
+/* The NAND flash operations command format */
+static const struct mxic_nfc_command_format mxic_nand_commands[] = {
+ {NAND_CMD_READ0, NAND_CMD_READSTART, 5, 1 },
+ {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, 1 },
+ {NAND_CMD_READID, NAND_CMD_NONE, 1, 1 },
+ {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 1 },
+ {NAND_CMD_SEQIN, NAND_CMD_NONE, 5, 0 },
+ {NAND_CMD_PAGEPROG, NAND_CMD_NONE, 0, 0 },
+ {NAND_CMD_CACHEDPROG, NAND_CMD_NONE, 0, 0 },
+ {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0 },
+ {NAND_CMD_ERASE1, NAND_CMD_NONE, 3, 0 },
+ {NAND_CMD_ERASE2, NAND_CMD_NONE, 0, 0 },
+ {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0 },
+ {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 1 },
+ {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 1 },
+ {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0 },
+ {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0 },
+};
+
+static int mxic_nfc_clk_enable(struct mxic_nand_ctrl *nfc)
+{
+ int ret;
+
+ ret = clk_prepare_enable(nfc->send_clk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(nfc->send_dly_clk);
+ if (ret)
+ goto err_send_dly_clk;
+
+ return ret;
+
+err_send_dly_clk:
+ clk_disable_unprepare(nfc->send_clk);
+
+ return ret;
+}
+
+static void mxic_nfc_clk_disable(struct mxic_nand_ctrl *nfc)
+{
+ clk_disable_unprepare(nfc->send_clk);
+ clk_disable_unprepare(nfc->send_dly_clk);
+}
+
+static void mxic_nfc_set_input_delay(struct mxic_nand_ctrl *nfc, u8 idly_code)
+{
+ writel(IDLY_CODE_VAL(0, idly_code) |
+ IDLY_CODE_VAL(1, idly_code) |
+ IDLY_CODE_VAL(2, idly_code) |
+ IDLY_CODE_VAL(3, idly_code),
+ nfc->regs + IDLY_CODE(0));
+ writel(IDLY_CODE_VAL(4, idly_code) |
+ IDLY_CODE_VAL(5, idly_code) |
+ IDLY_CODE_VAL(6, idly_code) |
+ IDLY_CODE_VAL(7, idly_code),
+ nfc->regs + IDLY_CODE(1));
+}
+
+static int mxic_nfc_clk_setup(struct mxic_nand_ctrl *nfc, unsigned long freq)
+{
+ int ret;
+
+ ret = clk_set_rate(nfc->send_clk, freq);
+ if (ret)
+ return ret;
+
+ ret = clk_set_rate(nfc->send_dly_clk, freq);
+ if (ret)
+ return ret;
+
+ /*
+ * A constant delay range from 0x0 ~ 0x1F for input delay,
+ * the unit is 78 ps, the max input delay is 2.418 ns.
+ */
+ mxic_nfc_set_input_delay(nfc, 0xf);
+
+ return 0;
+}
+
+static int mxic_nfc_set_freq(struct mxic_nand_ctrl *nfc, unsigned long freq)
+{
+ int ret;
+
+ if (freq > MXIC_NFC_MAX_CLK_HZ)
+ freq = MXIC_NFC_MAX_CLK_HZ;
+
+ mxic_nfc_clk_disable(nfc);
+ ret = mxic_nfc_clk_setup(nfc, freq);
+ if (ret)
+ return ret;
+
+ ret = mxic_nfc_clk_enable(nfc);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void mxic_nfc_hw_init(struct mxic_nand_ctrl *nfc)
+{
+ writel(HC_CFG_NIO(8) | HC_CFG_TYPE(1, HC_CFG_TYPE_RAW_NAND) |
+ HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN |
+ HC_CFG_IDLE_SIO_LVL(1), nfc->regs + HC_CFG);
+ writel(INT_STS_ALL, nfc->regs + INT_STS_EN);
+ writel(INT_RDY_PIN, nfc->regs + INT_SIG_EN);
+ writel(0x0, nfc->regs + ONFI_DIN_CNT(0));
+ writel(0, nfc->regs + LRD_CFG);
+ writel(0, nfc->regs + LRD_CTRL);
+ writel(0x0, nfc->regs + HC_EN);
+}
+
+static void mxic_nfc_cs_enable(struct mxic_nand_ctrl *nfc)
+{
+ writel(readl(nfc->regs + HC_CFG) | HC_CFG_MAN_CS_EN,
+ nfc->regs + HC_CFG);
+ writel(HC_CFG_MAN_CS_ASSERT | readl(nfc->regs + HC_CFG),
+ nfc->regs + HC_CFG);
+}
+
+static void mxic_nfc_cs_disable(struct mxic_nand_ctrl *nfc)
+{
+ writel(~HC_CFG_MAN_CS_ASSERT & readl(nfc->regs + HC_CFG),
+ nfc->regs + HC_CFG);
+}
+
+static int mxic_nfc_data_xfer(struct mxic_nand_ctrl *nfc, const void *txbuf,
+ void *rxbuf, unsigned int len)
+{
+ unsigned int pos = 0;
+
+ while (pos < len) {
+ unsigned int nbytes = len - pos;
+ u32 data = 0xffffffff;
+ u32 sts;
+ int ret;
+
+ if (nbytes > 4)
+ nbytes = 4;
+
+ if (txbuf)
+ memcpy(&data, txbuf + pos, nbytes);
+
+ ret = readl_poll_timeout(nfc->regs + INT_STS, sts,
+ sts & INT_TX_EMPTY, 1000000);
+ if (ret)
+ return ret;
+
+ writel(data, nfc->regs + TXD(nbytes % 4));
+
+ ret = readl_poll_timeout(nfc->regs + INT_STS, sts,
+ sts & INT_TX_EMPTY, 1000000);
+ if (ret)
+ return ret;
+
+ ret = readl_poll_timeout(nfc->regs + INT_STS, sts,
+ sts & INT_RX_NOT_EMPTY, 1000000);
+ if (ret)
+ return ret;
+
+ data = readl(nfc->regs + RXD);
+ if (rxbuf) {
+ data >>= (8 * (4 - nbytes));
+ memcpy(rxbuf + pos, &data, nbytes);
+ }
+
+ WARN_ON(readl(nfc->regs + INT_STS) & INT_RX_NOT_EMPTY);
+
+ pos += nbytes;
+ }
+
+ return 0;
+}
+
+static uint8_t mxic_nfc_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
+ u8 data;
+
+ writel(0x0, nfc->regs + ONFI_DIN_CNT(0));
+ writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
+ OP_READ, nfc->regs + SS_CTRL(0));
+
+ mxic_nfc_data_xfer(nfc, NULL, &data, 1);
+
+ return data;
+}
+
+static void mxic_nfc_read_buf(struct mtd_info *mtd, uint8_t *rxbuf, int rlen)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
+
+ writel(0x0, nfc->regs + ONFI_DIN_CNT(0));
+ writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
+ OP_READ, nfc->regs + SS_CTRL(0));
+
+ mxic_nfc_data_xfer(nfc, NULL, rxbuf, rlen);
+}
+
+static void mxic_nfc_write_buf(struct mtd_info *mtd, const uint8_t *txbuf,
+ int wlen)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
+
+ writel(wlen, nfc->regs + ONFI_DIN_CNT(0));
+ writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F),
+ nfc->regs + SS_CTRL(0));
+
+ mxic_nfc_data_xfer(nfc, txbuf, NULL, wlen);
+}
+
+static void mxic_nfc_cmd_function(struct mtd_info *mtd, unsigned int command,
+ int column, int page_addr)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
+ const struct mxic_nfc_command_format *cmd = NULL;
+ u32 sts;
+ u8 index, addr[5];
+
+ /* Emulate NAND_CMD_READOOB */
+ if (command == NAND_CMD_READOOB) {
+ column += mtd->writesize;
+ command = NAND_CMD_READ0;
+ }
+
+ /* Get the command format */
+ for (index = 0; index < ARRAY_SIZE(mxic_nand_commands); index++)
+ if (command == mxic_nand_commands[index].start_cmd)
+ break;
+
+ cmd = &mxic_nand_commands[index];
+
+ if (!(command == NAND_CMD_PAGEPROG ||
+ command == NAND_CMD_CACHEDPROG ||
+ command == NAND_CMD_ERASE2))
+ mxic_nfc_cs_disable(nfc);
+
+ mxic_nfc_cs_enable(nfc);
+
+ if (column != -1) {
+ addr[0] = column;
+ addr[1] = column >> 8;
+
+ if (page_addr != -1) {
+ addr[2] = page_addr;
+ addr[3] = page_addr >> 8;
+ addr[4] = page_addr >> 16;
+ }
+ } else if (page_addr != -1) {
+ addr[0] = page_addr;
+ addr[1] = page_addr >> 8;
+ addr[2] = page_addr >> 16;
+ }
+
+ writel(0, nfc->regs + HC_EN);
+ writel(HC_EN_BIT, nfc->regs + HC_EN);
+ writel(OP_CMD_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) | OP_CMD_BYTES(0),
+ nfc->regs + SS_CTRL(0));
+
+ mxic_nfc_data_xfer(nfc, &cmd->start_cmd, NULL, 1);
+
+ if (cmd->addr_len) {
+ writel(OP_ADDR_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
+ OP_ADDR_BYTES(cmd->addr_len), nfc->regs + SS_CTRL(0));
+
+ mxic_nfc_data_xfer(nfc, &addr, NULL, cmd->addr_len);
+ }
+
+ if (cmd->end_cmd != NAND_CMD_NONE) {
+ writel(0, nfc->regs + HC_EN);
+ writel(HC_EN_BIT, nfc->regs + HC_EN);
+ writel(OP_CMD_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
+ OP_CMD_BYTES(0), nfc->regs + SS_CTRL(0));
+
+ mxic_nfc_data_xfer(nfc, &cmd->end_cmd, NULL, 1);
+ }
+
+ readl_poll_timeout(nfc->regs + INT_STS, sts, sts & INT_RDY_PIN,
+ 1000000);
+
+ if (command == NAND_CMD_PAGEPROG ||
+ command == NAND_CMD_CACHEDPROG ||
+ command == NAND_CMD_ERASE2 ||
+ command == NAND_CMD_RESET) {
+ mxic_nfc_cs_disable(nfc);
+ }
+}
+
+static int mxic_nfc_setup_data_interface(struct mtd_info *mtd, int chipnr,
+ const struct nand_data_interface *conf)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
+ const struct nand_sdr_timings *sdr;
+ unsigned long freq;
+ int ret;
+
+ sdr = nand_get_sdr_timings(conf);
+ if (IS_ERR(sdr))
+ return PTR_ERR(sdr);
+
+ if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
+ return 0;
+
+ freq = 1000000000 / (sdr->tRC_min / 1000);
+
+ ret = mxic_nfc_set_freq(nfc, freq);
+ if (ret)
+ WARN_ON("Set freq failed\n");
+
+ if (sdr->tRC_min < 30000)
+ writel(DATA_STROB_EDO_EN, nfc->regs + DATA_STROB);
+
+ return 0;
+}
+
+/* Dummy implementation: we don't support multiple chips */
+static void mxic_nfc_select_chip(struct mtd_info *mtd, int chipnr)
+{
+ switch (chipnr) {
+ case -1:
+ case 0:
+ break;
+
+ default:
+ BUG();
+ }
+}
+
+static int mxic_nfc_probe(struct udevice *dev)
+{
+ struct mxic_nand_ctrl *nfc = dev_get_priv(dev);
+ struct nand_chip *nand_chip = &nfc->nand_chip;
+ struct mtd_info *mtd;
+ ofnode child;
+ int err;
+
+ nfc->regs = (void *)dev_read_addr(dev);
+
+ nfc->send_clk = devm_clk_get(dev, "send");
+ if (IS_ERR(nfc->send_clk))
+ return PTR_ERR(nfc->send_clk);
+
+ nfc->send_dly_clk = devm_clk_get(dev, "send_dly");
+ if (IS_ERR(nfc->send_dly_clk))
+ return PTR_ERR(nfc->send_dly_clk);
+
+ mtd = nand_to_mtd(nand_chip);
+
+ ofnode_for_each_subnode(child, dev_ofnode(dev))
+ nand_set_flash_node(nand_chip, child);
+
+ nand_set_controller_data(nand_chip, nfc);
+
+ nand_chip->select_chip = mxic_nfc_select_chip;
+ nand_chip->setup_data_interface = mxic_nfc_setup_data_interface;
+ nand_chip->cmdfunc = mxic_nfc_cmd_function;
+ nand_chip->read_byte = mxic_nfc_read_byte;
+ nand_chip->read_buf = mxic_nfc_read_buf;
+ nand_chip->write_buf = mxic_nfc_write_buf;
+
+ mxic_nfc_hw_init(nfc);
+
+ err = nand_scan(mtd, 1);
+ if (err)
+ return err;
+
+ err = nand_register(0, mtd);
+ if (err) {
+ dev_err(dev, "Failed to register MTD: %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id mxic_nfc_of_ids[] = {
+ { .compatible = "mxic,multi-itfc-v009-nand-controller" },
+ { /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(mxic_nfc) = {
+ .name = "mxic_nfc",
+ .id = UCLASS_MTD,
+ .of_match = mxic_nfc_of_ids,
+ .probe = mxic_nfc_probe,
+ .priv_auto = sizeof(struct mxic_nand_ctrl),
+};
+
+void board_nand_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MTD,
+ DM_DRIVER_GET(mxic_nfc), &dev);
+ if (ret && ret != -ENODEV)
+ pr_err("Failed to initialize %s. (error %d)\n", dev->name,
+ ret);
+}
#ifdef CONFIG_DM_ETH
static int macb_sifive_clk_init(struct udevice *dev, ulong rate)
{
- fdt_addr_t addr;
void *gemgxl_regs;
- addr = dev_read_addr_index(dev, 1);
- if (addr == FDT_ADDR_T_NONE)
- return -ENODEV;
-
- gemgxl_regs = (void __iomem *)addr;
+ gemgxl_regs = dev_read_addr_index_ptr(dev, 1);
if (!gemgxl_regs)
return -ENODEV;
macb->phy_addr = ofnode_read_u32_default(phandle_args.node,
"reg", -1);
- macb->regs = (void *)pdata->iobase;
+ macb->regs = (void *)(uintptr_t)pdata->iobase;
macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
{
struct eth_pdata *pdata = dev_get_plat(dev);
- pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
+ pdata->iobase = (uintptr_t)dev_remap_addr(dev);
if (!pdata->iobase)
return -EINVAL;
#include <log.h>
#include <asm/cache.h>
#include <asm/global_data.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <reset.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <wait_bit.h>
-#if CONFIG_IS_ENABLED(DM_GPIO)
-#include <asm-generic/gpio.h>
-#endif
#define MDIO_CMD_MII_BUSY BIT(0)
#define MDIO_CMD_MII_WRITE BIT(1)
u64 prp2;
u64 total_len = blkcnt << desc->log2blksz;
u64 temp_len = total_len;
+ uintptr_t temp_buffer = (uintptr_t)buffer;
u64 slba = blknr;
u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift);
}
if (nvme_setup_prps(dev, &prp2,
- lbas << ns->lba_shift, (ulong)buffer))
+ lbas << ns->lba_shift, temp_buffer))
return -EIO;
c.rw.slba = cpu_to_le64(slba);
slba += lbas;
c.rw.length = cpu_to_le16(lbas - 1);
- c.rw.prp1 = cpu_to_le64((ulong)buffer);
+ c.rw.prp1 = cpu_to_le64(temp_buffer);
c.rw.prp2 = cpu_to_le64(prp2);
status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q],
&c, NULL, IO_TIMEOUT);
if (status)
break;
temp_len -= (u32)lbas << ns->lba_shift;
- buffer += lbas << ns->lba_shift;
+ temp_buffer += lbas << ns->lba_shift;
}
if (read)
#define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
#define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
#define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
+#define PCIE_CORE_DEV_REV_REG 0x8
+#define PCIE_CORE_EXP_ROM_BAR_REG 0x30
+#define PCIE_CORE_PCIEXP_CAP_OFF 0xc0
#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
#define LTSSM_SHIFT 24
#define LTSSM_MASK 0x3f
#define LTSSM_L0 0x10
+#define LTSSM_DISABLED 0x20
#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
/* PCIe core controller registers */
#define PCIE_CONFIG_WR_TYPE1 0xb
/* PCI_BDF shifts 8bit, so we need extra 4bit shift */
-#define PCIE_BDF(dev) (dev << 4)
+#define PCIE_BDF(b, d, f) (PCI_BDF(b, d, f) << 4)
#define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
#define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
#define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
/**
* struct pcie_advk - Advk PCIe controller state
*
- * @reg_base: The base address of the register space.
- * @first_busno: This driver supports multiple PCIe controllers.
- * first_busno stores the bus number of the PCIe root-port
- * number which may vary depending on the PCIe setup
- * (PEX switches etc).
- * @device: The pointer to PCI uclass device.
+ * @base: The base address of the register space.
+ * @first_busno: Bus number of the PCIe root-port.
+ * This may vary depending on the PCIe setup.
+ * @sec_busno: Bus number for the device behind the PCIe root-port.
+ * @dev: The pointer to PCI uclass device.
+ * @reset_gpio: GPIO descriptor for PERST.
+ * @cfgcache: Buffer for emulation of PCIe Root Port's PCI Bridge registers
+ * that are not available on Aardvark.
+ * @cfgcrssve: For CRSSVE emulation.
*/
struct pcie_advk {
- void *base;
- int first_busno;
- struct udevice *dev;
- struct gpio_desc reset_gpio;
+ void *base;
+ int first_busno;
+ int sec_busno;
+ struct udevice *dev;
+ struct gpio_desc reset_gpio;
+ u32 cfgcache[0x34 - 0x10];
+ bool cfgcrssve;
};
static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
/**
* pcie_advk_addr_valid() - Check for valid bus address
*
+ * @pcie: Pointer to the PCI bus
+ * @busno: Bus number of PCI device
+ * @dev: Device number of PCI device
+ * @func: Function number of PCI device
* @bdf: The PCI device to access
- * @first_busno: Bus number of the PCIe controller root complex
*
- * Return: 1 on valid, 0 on invalid
+ * Return: true on valid, false on invalid
*/
-static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
+static bool pcie_advk_addr_valid(struct pcie_advk *pcie,
+ int busno, u8 dev, u8 func)
{
+ /* On the primary (local) bus there is only one PCI Bridge */
+ if (busno == pcie->first_busno && (dev != 0 || func != 0))
+ return false;
+
/*
- * In PCIE-E only a single device (0) can exist
- * on the local bus. Beyound the local bus, there might be
- * a Switch and everything is possible.
+ * In PCI-E only a single device (0) can exist on the secondary bus.
+ * Beyond the secondary bus, there might be a Switch and anything is
+ * possible.
*/
- if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
- return 0;
+ if (busno == pcie->sec_busno && dev != 0)
+ return false;
- return 1;
+ return true;
}
/**
enum pci_size_t size)
{
struct pcie_advk *pcie = dev_get_priv(bus);
+ int busno = PCI_BUS(bdf) - dev_seq(bus);
int retry_count;
bool allow_crs;
+ ulong data;
uint reg;
int ret;
dev_dbg(pcie->dev, "PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
- if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
+ if (!pcie_advk_addr_valid(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) {
dev_dbg(pcie->dev, "- out of range\n");
*valuep = pci_get_ff(size);
return 0;
}
/*
+ * The configuration space of the PCI Bridge on primary (local) bus is
+ * not accessible via PIO transfers like all other PCIe devices. PCI
+ * Bridge config registers are available directly in Aardvark memory
+ * space starting at offset zero. Moreover PCI Bridge registers in the
+ * range 0x10 - 0x34 are not available and register 0x38 (Expansion ROM
+ * Base Address) is at offset 0x30.
+ * We therefore read configuration space content of the primary PCI
+ * Bridge from our virtual cache.
+ */
+ if (busno == pcie->first_busno) {
+ if (offset >= 0x10 && offset < 0x34)
+ data = pcie->cfgcache[(offset - 0x10) / 4];
+ else if ((offset & ~3) == PCI_ROM_ADDRESS1)
+ data = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG);
+ else
+ data = advk_readl(pcie, offset & ~3);
+
+ if ((offset & ~3) == (PCI_HEADER_TYPE & ~3)) {
+ /*
+ * Change Header Type of PCI Bridge device to Type 1
+ * (0x01, used by PCI Bridges) because hardwired value
+ * is Type 0 (0x00, used by Endpoint devices).
+ */
+ data &= ~0x007f0000;
+ data |= PCI_HEADER_TYPE_BRIDGE << 16;
+ }
+
+ if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL) {
+ /* CRSSVE bit is stored only in cache */
+ if (pcie->cfgcrssve)
+ data |= PCI_EXP_RTCTL_CRSSVE;
+ }
+
+ if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF +
+ (PCI_EXP_RTCAP & ~3)) {
+ /* CRS is emulated below, so set CRSVIS capability */
+ data |= PCI_EXP_RTCAP_CRSVIS << 16;
+ }
+
+ *valuep = pci_conv_32_to_size(data, offset, size);
+
+ return 0;
+ }
+
+ /*
* Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to
* OS is allowed only for 4-byte PCI_VENDOR_ID config read request and
* only when CRSSVE bit in Root Port PCIe device is enabled. In all
* other error PCIe Root Complex must return all-ones.
- * Aardvark HW does not have Root Port PCIe device and U-Boot does not
- * implement emulation of this device.
+ *
* U-Boot currently does not support handling of CRS return value for
* PCI_VENDOR_ID config read request and also does not set CRSSVE bit.
- * Therefore disable returning CRS response for now.
+ * So it means that pcie->cfgcrssve is false. But the code is prepared
+ * for returning CRS, so that if U-Boot does support CRS in the future,
+ * it will work for Aardvark.
*/
- allow_crs = false;
+ allow_crs = pcie->cfgcrssve;
if (advk_readl(pcie, PIO_START)) {
dev_err(pcie->dev,
/* Program the control register */
reg = advk_readl(pcie, PIO_CTRL);
reg &= ~PIO_CTRL_TYPE_MASK;
- if (PCI_BUS(bdf) == pcie->first_busno)
+ if (busno == pcie->sec_busno)
reg |= PCIE_CONFIG_RD_TYPE0;
else
reg |= PCIE_CONFIG_RD_TYPE1;
advk_writel(pcie, reg, PIO_CTRL);
/* Program the address registers */
- reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
+ reg = PCIE_BDF(busno, PCI_DEV(bdf), PCI_FUNC(bdf)) | PCIE_CONF_REG(offset);
advk_writel(pcie, reg, PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS);
enum pci_size_t size)
{
struct pcie_advk *pcie = dev_get_priv(bus);
+ int busno = PCI_BUS(bdf) - dev_seq(bus);
int retry_count;
+ ulong data;
uint reg;
int ret;
dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
offset, size, value);
- if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
+ if (!pcie_advk_addr_valid(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) {
dev_dbg(pcie->dev, "- out of range\n");
return 0;
}
+ /*
+ * As explained in pcie_advk_read_config(), for the configuration
+ * space of the primary PCI Bridge, we write the content into virtual
+ * cache.
+ */
+ if (busno == pcie->first_busno) {
+ if (offset >= 0x10 && offset < 0x34) {
+ data = pcie->cfgcache[(offset - 0x10) / 4];
+ data = pci_conv_size_to_32(data, value, offset, size);
+ pcie->cfgcache[(offset - 0x10) / 4] = data;
+ } else if ((offset & ~3) == PCI_ROM_ADDRESS1) {
+ data = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG);
+ data = pci_conv_size_to_32(data, value, offset, size);
+ advk_writel(pcie, data, PCIE_CORE_EXP_ROM_BAR_REG);
+ } else {
+ data = advk_readl(pcie, offset & ~3);
+ data = pci_conv_size_to_32(data, value, offset, size);
+ advk_writel(pcie, data, offset & ~3);
+ }
+
+ if (offset == PCI_PRIMARY_BUS)
+ pcie->first_busno = data & 0xff;
+
+ if (offset == PCI_SECONDARY_BUS ||
+ (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))
+ pcie->sec_busno = (data >> 8) & 0xff;
+
+ if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL)
+ pcie->cfgcrssve = data & PCI_EXP_RTCTL_CRSSVE;
+
+ return 0;
+ }
+
if (advk_readl(pcie, PIO_START)) {
dev_err(pcie->dev,
"Previous PIO read/write transfer is still running\n");
/* Program the control register */
reg = advk_readl(pcie, PIO_CTRL);
reg &= ~PIO_CTRL_TYPE_MASK;
- if (PCI_BUS(bdf) == pcie->first_busno)
+ if (busno == pcie->sec_busno)
reg |= PCIE_CONFIG_WR_TYPE0;
else
reg |= PCIE_CONFIG_WR_TYPE1;
advk_writel(pcie, reg, PIO_CTRL);
/* Program the address registers */
- reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
+ reg = PCIE_BDF(busno, PCI_DEV(bdf), PCI_FUNC(bdf)) | PCIE_CONF_REG(offset);
advk_writel(pcie, reg, PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS);
dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
val = advk_readl(pcie, CFG_REG);
ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
- return ltssm_state >= LTSSM_L0;
+ return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED;
}
/**
/* check if the link is up or not */
for (retries = 0; retries < LINK_MAX_RETRIES; retries++) {
if (pcie_advk_link_up(pcie)) {
- printf("PCIE-%d: Link up\n", pcie->first_busno);
+ printf("PCIe: Link up\n");
return 0;
}
udelay(LINK_WAIT_TIMEOUT);
}
- printf("PCIE-%d: Link down\n", pcie->first_busno);
+ printf("PCIe: Link down\n");
return -ETIMEDOUT;
}
*/
advk_writel(pcie, 0x11ab11ab, VENDOR_ID_REG);
+ /*
+ * Change Class Code of PCI Bridge device to PCI Bridge (0x600400),
+ * because default value is Mass Storage Controller (0x010400), causing
+ * U-Boot to fail to recognize it as P2P Bridge.
+ *
+ * Note that this Aardvark PCI Bridge does not have a compliant Type 1
+ * Configuration Space and it even cannot be accessed via Aardvark's
+ * PCI config space access method. Something like config space is
+ * available in internal Aardvark registers starting at offset 0x0
+ * and is reported as Type 0. In range 0x10 - 0x34 it has totally
+ * different registers. So our driver reports Header Type as Type 1 and
+ * for the above mentioned range redirects access to the virtual
+ * cfgcache[] buffer, which avoids changing internal Aardvark registers.
+ */
+ reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG);
+ reg &= ~0xffffff00;
+ reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
+ advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG);
+
/* Set Advanced Error Capabilities and Control PF0 register */
reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
if (pcie_advk_wait_for_link(pcie))
return -ENXIO;
- reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
- reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
- PCIE_CORE_CMD_IO_ACCESS_EN |
- PCIE_CORE_CMD_MEM_IO_REQ_EN;
- advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
-
return 0;
}
dev_warn(dev, "PCIE Reset on GPIO support is missing\n");
}
- pcie->first_busno = dev_seq(dev);
pcie->dev = pci_get_controller(dev);
+ /* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */
+ pcie->cfgcache[(PCI_IO_BASE - 0x10) / 4] =
+ PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8);
+ pcie->cfgcache[(PCI_PREF_MEMORY_BASE - 0x10) / 4] =
+ PCI_PREF_RANGE_TYPE_64 | (PCI_PREF_RANGE_TYPE_64 << 16);
+
return pcie_advk_setup_hw(pcie);
}
int dm_pci_hose_probe_bus(struct udevice *bus)
{
+ u8 header_type;
int sub_bus;
int ret;
int ea_pos;
debug("%s\n", __func__);
+ dm_pci_read_config8(bus, PCI_HEADER_TYPE, &header_type);
+ header_type &= 0x7f;
+ if (header_type != PCI_HEADER_TYPE_BRIDGE) {
+ debug("%s: Skipping PCI device %d with Non-Bridge Header Type 0x%x\n",
+ __func__, PCI_DEV(dm_pci_get_bdf(bus)), header_type);
+ return log_msg_ret("probe", -EINVAL);
+ }
+
ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA);
if (ea_pos) {
dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8),
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
#endif
-static void dm_pciauto_setup_device(struct udevice *dev, int bars_num,
+static void dm_pciauto_setup_device(struct udevice *dev,
struct pci_region *mem,
struct pci_region *prefetch,
struct pci_region *io)
pci_size_t bar_size;
u16 cmdstat = 0;
int bar, bar_nr = 0;
+ int bars_num;
u8 header_type;
int rom_addr;
pci_addr_t bar_value;
cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
PCI_COMMAND_MASTER;
+ dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
+ header_type &= 0x7f;
+
+ switch (header_type) {
+ case PCI_HEADER_TYPE_NORMAL:
+ bars_num = 6;
+ break;
+ case PCI_HEADER_TYPE_BRIDGE:
+ bars_num = 2;
+ break;
+ case PCI_HEADER_TYPE_CARDBUS:
+ /* CardBus header does not have any BAR */
+ bars_num = 0;
+ break;
+ default:
+ /* Skip configuring BARs for unknown header types */
+ bars_num = 0;
+ break;
+ }
+
for (bar = PCI_BASE_ADDRESS_0;
bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
int ret = 0;
}
/* Configure the expansion ROM address */
- dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
- header_type &= 0x7f;
- if (header_type != PCI_HEADER_TYPE_CARDBUS) {
+ if (header_type == PCI_HEADER_TYPE_NORMAL ||
+ header_type == PCI_HEADER_TYPE_BRIDGE) {
rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
debug("PCI Autoconfig: Found P2P bridge, device %d\n",
PCI_DEV(dm_pci_get_bdf(dev)));
- dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io);
+ dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
ret = dm_pci_hose_probe_bus(dev);
if (ret < 0)
* just do a minimal setup of the bridge,
* let the OS take care of the rest
*/
- dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io);
+ dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
PCI_DEV(dm_pci_get_bdf(dev)));
/* fall through */
default:
- dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io);
+ dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
break;
}
{
pciauto_region_init(region);
debug("PCI Autoconfig: Bus %s region: [%llx-%llx],\n"
- "\t\tPhysical Memory [%llx-%llxx]\n", name,
+ "\t\tPhysical Memory [%llx-%llx]\n", name,
(unsigned long long)region->bus_start,
(unsigned long long)(region->bus_start + region->size - 1),
(unsigned long long)region->phys_start,
pcie_dw_setup_host(&priv->dw);
- ret = meson_pcie_link_up(priv, LINK_SPEED_GEN_2);
- if (ret < 0)
- goto err_link_up;
+ meson_pcie_link_up(priv, LINK_SPEED_GEN_2);
return 0;
-err_link_up:
- clk_disable(&priv->clk_port);
- clk_disable(&priv->clk_general);
- clk_disable(&priv->clk_pclk);
err_deassert_bulk:
reset_assert_bulk(&priv->rsts);
err_power_off_phy:
* 6. Enable the output of 100M/125M/500M clock
*/
reg_set16(phy_addr(PCIE, MISC_REG0),
- 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF);
+ 0xA00D | rb_clk500m_en | rb_txdclk_2x_sel | rb_clk100m_125m_en, 0xFFFF);
/*
* 7. Enable TX
*/
if (invert & COMPHY_POLARITY_TXD_INVERT)
reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0);
+ else
+ reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_txd_inv);
if (invert & COMPHY_POLARITY_RXD_INVERT)
reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);
+ else
+ reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_rxd_inv);
/*
* 11. Release SW reset
*/
if (invert & COMPHY_POLARITY_TXD_INVERT)
usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane);
+ else
+ usb3_reg_set16(SYNC_PATTERN, 0, phy_txd_inv, lane);
if (invert & COMPHY_POLARITY_RXD_INVERT)
usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane);
+ else
+ usb3_reg_set16(SYNC_PATTERN, 0, phy_rxd_inv, lane);
/*
* 10. Set max speed generation to USB3.0 5Gbps
rb_usb2phy_pllcal_done, /* value */
rb_usb2phy_pllcal_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to end USB2 PLL calibration\n");
+ goto out;
+ }
/* Assert impedance calibration done */
ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32),
rb_usb2phy_impcal_done, /* value */
rb_usb2phy_impcal_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to end USB2 impedance calibration\n");
+ goto out;
+ }
/* Assert squetch calibration done */
ret = comphy_poll_reg(USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32),
rb_usb2phy_sqcal_done, /* value */
rb_usb2phy_sqcal_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to end USB2 unknown calibration\n");
+ goto out;
+ }
/* Assert PLL is ready */
ret = comphy_poll_reg(USB2_PHY_PLL_CTRL0_ADDR(usb32),
rb_usb2phy_pll_ready, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to lock USB2 PLL\n");
+ goto out;
+ }
+out:
debug_exit();
return ret;
*/
if (invert & COMPHY_POLARITY_TXD_INVERT)
reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0);
+ else
+ reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), 0, phy_txd_inv);
if (invert & COMPHY_POLARITY_RXD_INVERT)
reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0);
+ else
+ reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), 0, phy_rxd_inv);
/*
* 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1
rb_pll_ready_tx | rb_pll_ready_rx, /* value */
rb_pll_ready_tx | rb_pll_ready_rx, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to lock PLL for SGMII PHY %d\n", lane);
+ goto out;
+ }
/*
* 21. Set COMPHY input port PIN_TX_IDLE=0
rb_rx_init_done, /* value */
rb_rx_init_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to init RX of SGMII PHY %d\n", lane);
+ goto out;
+ }
/*
* Restore saved selector.
*/
reg_set(COMPHY_SEL_ADDR, saved_selector, 0xFFFFFFFF);
+out:
debug_exit();
return ret;
#define MISC_REG0 0x4f
#define rb_clk100m_125m_en BIT(4)
+#define rb_txdclk_2x_sel BIT(6)
#define rb_clk500m_en BIT(7)
#define rb_ref_clk_sel BIT(10)
{
struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
struct reset_ctl reset;
- ofnode node;
- int i, ret;
+ ofnode node, connector;
+ int ret;
usbphyc->base = dev_read_addr(dev);
if (usbphyc->base == FDT_ADDR_T_NONE)
return ret;
}
- /*
- * parse all PHY subnodes in order to populate regulator associated
- * to each PHY port
- */
- node = dev_read_first_subnode(dev);
- for (i = 0; i < MAX_PHYS; i++) {
- struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i;
+ /* parse all PHY subnodes to populate regulator associated to each PHY port */
+ dev_for_each_subnode(node, dev) {
+ fdt_addr_t phy_id;
+ struct stm32_usbphyc_phy *usbphyc_phy;
+ phy_id = ofnode_read_u32_default(node, "reg", FDT_ADDR_T_NONE);
+ if (phy_id >= MAX_PHYS) {
+ dev_err(dev, "invalid reg value %lx for %s\n",
+ phy_id, ofnode_get_name(node));
+ return -ENOENT;
+ }
+ usbphyc_phy = usbphyc->phys + phy_id;
usbphyc_phy->init = false;
usbphyc_phy->powered = false;
ret = stm32_usbphyc_get_regulator(node, "phy-supply",
return ret;
}
- ret = stm32_usbphyc_get_regulator(node, "vbus-supply",
- &usbphyc_phy->vbus);
- if (ret)
- usbphyc_phy->vbus = NULL;
-
- node = dev_read_next_subnode(node);
+ usbphyc_phy->vbus = NULL;
+ connector = ofnode_find_subnode(node, "connector");
+ if (ofnode_valid(connector)) {
+ ret = stm32_usbphyc_get_regulator(connector, "vbus-supply",
+ &usbphyc_phy->vbus);
+ }
}
/* Check if second port has to be used for host controller */
#include <common.h>
#include <command.h>
#include <errno.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/pmic_bus.h>
#include <axp_pmic.h>
#include <common.h>
#include <command.h>
#include <errno.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/pmic_bus.h>
#include <axp_pmic.h>
- 'drivers/power/pmic/pmic-uclass.c'
- 'include/power/pmic.h'
+if DM_PMIC
+
config SPL_DM_PMIC
bool "Enable Driver Model for PMIC drivers (UCLASS_PMIC) in SPL"
depends on SPL_DM
- default y if DM_PMIC
+ default y
---help---
This config enables the driver-model PMIC support in SPL.
UCLASS_PMIC - designed to provide an I/O interface for PMIC devices.
config PMIC_CHILDREN
bool "Allow child devices for PMICs"
- depends on DM_PMIC
default y
---help---
This allows PMICs to support child devices (such as regulators) in
config SPL_PMIC_CHILDREN
bool "Allow child devices for PMICs in SPL"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
default y
---help---
This allows PMICs to support child devices (such as regulators) in
config PMIC_AB8500
bool "Enable driver for ST-Ericsson AB8500 PMIC via PRCMU"
- depends on DM_PMIC
select REGMAP
select SYSCON
help
config PMIC_ACT8846
bool "Enable support for the active-semi 8846 PMIC"
- depends on DM_PMIC && DM_I2C
+ depends on DM_I2C
---help---
This PMIC includes 4 DC/DC step-down buck regulators and 8 low-dropout
regulators (LDOs). It also provides some GPIO, reset and battery
functions. It uses an I2C interface and is designed for use with
tablets and smartphones.
+config PMIC_AXP
+ bool "Enable Driver Model for X-Powers AXP PMICs"
+ depends on DM_I2C
+ help
+ This config enables driver-model PMIC uclass features for
+ X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
+
+config SPL_PMIC_AXP
+ bool "Enable Driver Model for X-Powers AXP PMICs in SPL"
+ depends on SPL_DM_I2C && SPL_DM_PMIC
+ help
+ This config enables driver-model PMIC uclass features in the SPL for
+ X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
+
config DM_PMIC_DA9063
bool "Enable Driver Model for the Dialog DA9063 PMIC"
- depends on DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC DA9063. The driver implements read/write operations.
config SPL_DM_PMIC_DA9063
bool "Enable Driver Model for the Dialog DA9063 PMIC in SPL"
- depends on DM_PMIC && SPL
+ depends on SPL_DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC DA9063. The driver implements read/write operations.
config DM_PMIC_BD71837
bool "Enable Driver Model for PMIC BD71837"
- depends on DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC BD71837. The driver implements read/write operations.
config SPL_DM_PMIC_BD71837
bool "Enable Driver Model for PMIC BD71837 in SPL stage"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
help
This config enables implementation of driver-model pmic uclass
features for PMIC BD71837. The driver implements read/write
config DM_PMIC_FAN53555
bool "Enable support for OnSemi FAN53555"
- depends on DM_PMIC && DM_REGULATOR && DM_I2C
+ depends on DM_REGULATOR && DM_I2C
select DM_REGULATOR_FAN53555
help
This config enables implementation of driver-model PMIC
config DM_PMIC_MP5416
bool "Enable Driver Model for PMIC MP5416"
- depends on DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC MP5416. The driver implements read/write operations.
config SPL_DM_PMIC_MP5416
bool "Enable Driver Model for PMIC MP5416 in SPL stage"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
help
This config enables implementation of driver-model pmic uclass
features for PMIC MP5416. The driver implements read/write
config DM_PMIC_PCA9450
bool "Enable Driver Model for PMIC PCA9450"
- depends on DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC PCA9450. The driver implements read/write operations.
config SPL_DM_PMIC_PCA9450
bool "Enable Driver Model for PMIC PCA9450"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC PCA9450 in SPL. The driver implements read/write operations.
config DM_PMIC_PFUZE100
bool "Enable Driver Model for PMIC PFUZE100"
- depends on DM_PMIC
---help---
This config enables implementation of driver-model pmic uclass features
for PMIC PFUZE100. The driver implements read/write operations.
config SPL_DM_PMIC_PFUZE100
bool "Enable Driver Model for PMIC PFUZE100 in SPL"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
---help---
This config enables implementation of driver-model pmic uclass features
for PMIC PFUZE100 in SPL. The driver implements read/write operations.
config DM_PMIC_MAX77686
bool "Enable Driver Model for PMIC MAX77686"
- depends on DM_PMIC
---help---
This config enables implementation of driver-model pmic uclass features
for PMIC MAX77686. The driver implements read/write operations.
config DM_PMIC_MAX8998
bool "Enable Driver Model for PMIC MAX8998"
- depends on DM_PMIC
---help---
This config enables implementation of driver-model pmic uclass features
for PMIC MAX8998. The driver implements read/write operations.
config DM_PMIC_MC34708
bool "Enable Driver Model for PMIC MC34708"
- depends on DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC MC34708. The driver implements read/write operations.
config PMIC_MAX8997
bool "Enable Driver Model for PMIC MAX8997"
- depends on DM_PMIC
---help---
This config enables implementation of driver-model pmic uclass features
for PMIC MAX8997. The driver implements read/write operations.
config PMIC_PM8916
bool "Enable Driver Model for Qualcomm PM8916 PMIC"
- depends on DM_PMIC
---help---
The PM8916 is a PMIC connected to one (or several) processors
with SPMI bus. It has 2 slaves with several peripherals:
config PMIC_RK8XX
bool "Enable support for Rockchip PMIC RK8XX"
- depends on DM_PMIC
---help---
The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs,
an RTC and two low Rds (resistance (drain to source)) switches. It is
config SPL_PMIC_RK8XX
bool "Enable support for Rockchip PMIC RK8XX"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
---help---
The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs,
an RTC and two low Rds (resistance (drain to source)) switches. It is
config PMIC_S2MPS11
bool "Enable Driver Model for PMIC Samsung S2MPS11"
- depends on DM_PMIC
---help---
The Samsung S2MPS11 PMIC provides:
- 38 adjustable LDO regulators
config DM_PMIC_SANDBOX
bool "Enable Driver Model for emulated Sandbox PMIC"
- depends on DM_PMIC
---help---
Enable the driver for Sandbox PMIC emulation. The emulated PMIC device
depends on two drivers:
config PMIC_S5M8767
bool "Enable Driver Model for the Samsung S5M8767 PMIC"
- depends on DM_PMIC
---help---
The S5M8767 PMIC provides a large array of LDOs and BUCKs for use
as a SoC power controller. It also provides 32KHz clock outputs. This
config PMIC_RN5T567
bool "Enable driver for Ricoh RN5T567 PMIC"
- depends on DM_PMIC
---help---
The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO
regulators Real-Time Clock and 4 GPIOs. This driver provides
config PMIC_TPS65090
bool "Enable driver for Texas Instruments TPS65090 PMIC"
- depends on DM_PMIC
---help---
The TPS65090 is a PMIC containing several LDOs, DC to DC convertors,
FETs and a battery charger. This driver provides register access
config PMIC_PALMAS
bool "Enable driver for Texas Instruments PALMAS PMIC"
- depends on DM_PMIC
---help---
The PALMAS is a PMIC containing several LDOs, SMPS.
This driver binds the pmic children.
config PMIC_LP873X
bool "Enable driver for Texas Instruments LP873X PMIC"
- depends on DM_PMIC
---help---
The LP873X is a PMIC containing couple of LDOs and couple of SMPS.
This driver binds the pmic children.
config PMIC_LP87565
bool "Enable driver for Texas Instruments LP87565 PMIC"
- depends on DM_PMIC
---help---
The LP87565 is a PMIC containing a bunch of SMPS.
This driver binds the pmic children.
-config POWER_MC34VR500
- bool "Enable driver for Freescale MC34VR500 PMIC"
- ---help---
- The MC34VR500 is used in conjunction with the FSL T1 and LS1 series
- SoC. It provides 4 buck DC-DC convertors and 5 LDOs, and it is accessed
- via an I2C interface.
-
config DM_PMIC_TPS65910
bool "Enable driver for Texas Instruments TPS65910 PMIC"
- depends on DM_PMIC
---help---
The TPS65910 is a PMIC containing 3 buck DC-DC converters, one boost
DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO
config PMIC_STPMIC1
bool "Enable support for STMicroelectronics STPMIC1 PMIC"
- depends on DM_PMIC && DM_I2C
+ depends on DM_I2C
select SYSRESET_CMD_POWEROFF if CMD_POWEROFF && !ARM_PSCI_FW
---help---
The STPMIC1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches.
config SPL_PMIC_PALMAS
bool "Enable driver for Texas Instruments PALMAS PMIC"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
help
The PALMAS is a PMIC containing several LDOs, SMPS.
This driver binds the pmic children in SPL.
config SPL_PMIC_LP873X
bool "Enable driver for Texas Instruments LP873X PMIC"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
help
The LP873X is a PMIC containing couple of LDOs and couple of SMPS.
This driver binds the pmic children in SPL.
config SPL_PMIC_LP87565
bool "Enable driver for Texas Instruments LP87565 PMIC"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
help
The LP87565 is a PMIC containing a bunch of SMPS.
This driver binds the pmic children in SPL.
config PMIC_TPS65941
bool "Enable driver for Texas Instruments TPS65941 PMIC"
- depends on DM_PMIC
help
The TPS65941 is a PMIC containing a bunch of SMPS & LDOs.
This driver binds the pmic children.
+
+endif
+
+config POWER_MC34VR500
+ bool "Enable driver for Freescale MC34VR500 PMIC"
+ depends on !DM_PMIC
+ ---help---
+ The MC34VR500 is used in conjunction with the FSL T1 and LS1 series
+ SoC. It provides 4 buck DC-DC convertors and 5 LDOs, and it is accessed
+ via an I2C interface.
obj-$(CONFIG_PMIC_AB8500) += ab8500.o
obj-$(CONFIG_PMIC_ACT8846) += act8846.o
obj-$(CONFIG_PMIC_AS3722) += as3722.o as3722_gpio.o
+obj-$(CONFIG_$(SPL_)PMIC_AXP) += axp.o
obj-$(CONFIG_PMIC_MAX8997) += max8997.o
obj-$(CONFIG_PMIC_PM8916) += pm8916.o
obj-$(CONFIG_$(SPL_TPL_)PMIC_RK8XX) += rk8xx.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+
+static int axp_pmic_reg_count(struct udevice *dev)
+{
+ /* TODO: Get the specific value from driver data. */
+ return 0x100;
+}
+
+static struct dm_pmic_ops axp_pmic_ops = {
+ .reg_count = axp_pmic_reg_count,
+ .read = dm_i2c_read,
+ .write = dm_i2c_write,
+};
+
+static const struct udevice_id axp_pmic_ids[] = {
+ { .compatible = "x-powers,axp152" },
+ { .compatible = "x-powers,axp202" },
+ { .compatible = "x-powers,axp209" },
+ { .compatible = "x-powers,axp221" },
+ { .compatible = "x-powers,axp223" },
+ { .compatible = "x-powers,axp803" },
+ { .compatible = "x-powers,axp806" },
+ { .compatible = "x-powers,axp809" },
+ { .compatible = "x-powers,axp813" },
+ { }
+};
+
+U_BOOT_DRIVER(axp_pmic) = {
+ .name = "axp_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = axp_pmic_ids,
+ .bind = dm_scan_fdt_dev,
+ .ops = &axp_pmic_ops,
+};
frequency/period can be controlled along with the proportion of that
time that the signal is high.
+config PWM_AT91
+ bool "Enable support for PWM found on AT91 SoC's"
+ depends on DM_PWM && ARCH_AT91
+ help
+ Support for PWM hardware on AT91 based SoC.
+
config PWM_CROS_EC
bool "Enable support for the Chrome OS EC PWM"
depends on DM_PWM
obj-$(CONFIG_DM_PWM) += pwm-uclass.o
+obj-$(CONFIG_PWM_AT91) += pwm-at91.o
obj-$(CONFIG_PWM_CROS_EC) += cros_ec_pwm.o
obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o
obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PWM support for Microchip AT91 architectures.
+ *
+ * Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Dan Sneddon <daniel.sneddon@microchip.com>
+ *
+ * Based on drivers/pwm/pwm-atmel.c from Linux.
+ */
+#include <clk.h>
+#include <common.h>
+#include <div64.h>
+#include <dm.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <pwm.h>
+
+#define PERIOD_BITS 16
+#define PWM_MAX_PRES 10
+#define NSEC_PER_SEC 1000000000L
+
+#define PWM_ENA 0x04
+#define PWM_CHANNEL_OFFSET 0x20
+#define PWM_CMR 0x200
+#define PWM_CMR_CPRE_MSK GENMASK(3, 0)
+#define PWM_CMR_CPOL BIT(9)
+#define PWM_CDTY 0x204
+#define PWM_CPRD 0x20C
+
+struct at91_pwm_priv {
+ void __iomem *base;
+ struct clk pclk;
+ u32 clkrate;
+};
+
+static int at91_pwm_calculate_cprd_and_pres(struct udevice *dev,
+ unsigned long clkrate,
+ uint period_ns, uint duty_ns,
+ unsigned long *cprd, u32 *pres)
+{
+ u64 cycles = period_ns;
+ int shift;
+
+ /* Calculate the period cycles and prescale value */
+ cycles *= clkrate;
+ do_div(cycles, NSEC_PER_SEC);
+
+ /*
+ * The register for the period length is period_bits bits wide.
+ * So for each bit the number of clock cycles is wider divide the input
+ * clock frequency by two using pres and shift cprd accordingly.
+ */
+ shift = fls(cycles) - PERIOD_BITS;
+
+ if (shift > PWM_MAX_PRES) {
+ return -EINVAL;
+ } else if (shift > 0) {
+ *pres = shift;
+ cycles >>= *pres;
+ } else {
+ *pres = 0;
+ }
+
+ *cprd = cycles;
+
+ return 0;
+}
+
+static void at91_pwm_calculate_cdty(uint period_ns, uint duty_ns,
+ unsigned long clkrate, unsigned long cprd,
+ u32 pres, unsigned long *cdty)
+{
+ u64 cycles = duty_ns;
+
+ cycles *= clkrate;
+ do_div(cycles, NSEC_PER_SEC);
+ cycles >>= pres;
+ *cdty = cprd - cycles;
+}
+
+/**
+ * Returns: channel status after set operation
+ */
+static bool at91_pwm_set(void __iomem *base, uint channel, bool enable)
+{
+ u32 val, cur_status;
+
+ val = ioread32(base + PWM_ENA);
+ cur_status = !!(val & BIT(channel));
+
+ /* if channel is already in that state, do nothing */
+ if (!(enable ^ cur_status))
+ return cur_status;
+
+ if (enable)
+ val |= BIT(channel);
+ else
+ val &= ~(BIT(channel));
+
+ iowrite32(val, base + PWM_ENA);
+
+ return cur_status;
+}
+
+static int at91_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
+{
+ struct at91_pwm_priv *priv = dev_get_priv(dev);
+
+ at91_pwm_set(priv->base, channel, enable);
+
+ return 0;
+}
+
+static int at91_pwm_set_config(struct udevice *dev, uint channel,
+ uint period_ns, uint duty_ns)
+{
+ struct at91_pwm_priv *priv = dev_get_priv(dev);
+ unsigned long cprd, cdty;
+ u32 pres, val;
+ int channel_enabled;
+ int ret;
+
+ ret = at91_pwm_calculate_cprd_and_pres(dev, priv->clkrate, period_ns,
+ duty_ns, &cprd, &pres);
+ if (ret)
+ return ret;
+
+ at91_pwm_calculate_cdty(period_ns, duty_ns, priv->clkrate, cprd, pres, &cdty);
+
+ /* disable the channel */
+ channel_enabled = at91_pwm_set(priv->base, channel, false);
+
+ /* It is necessary to preserve CPOL, inside CMR */
+ val = ioread32(priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
+ val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
+ iowrite32(val, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
+
+ iowrite32(cprd, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CPRD);
+
+ iowrite32(cdty, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CDTY);
+
+ /* renable the channel if needed */
+ if (channel_enabled)
+ at91_pwm_set(priv->base, channel, true);
+
+ return 0;
+}
+
+static int at91_pwm_set_invert(struct udevice *dev, uint channel,
+ bool polarity)
+{
+ struct at91_pwm_priv *priv = dev_get_priv(dev);
+ u32 val;
+
+ val = ioread32(priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
+ if (polarity)
+ val |= PWM_CMR_CPOL;
+ else
+ val &= ~PWM_CMR_CPOL;
+ iowrite32(val, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
+
+ return 0;
+}
+
+static int at91_pwm_probe(struct udevice *dev)
+{
+ struct at91_pwm_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -EINVAL;
+
+ ret = clk_get_by_index(dev, 0, &priv->pclk);
+ if (ret)
+ return ret;
+
+ /* clocks aren't ref-counted so just enabled them once here */
+ ret = clk_enable(&priv->pclk);
+ if (ret)
+ return ret;
+
+ priv->clkrate = clk_get_rate(&priv->pclk);
+
+ return ret;
+}
+
+static const struct pwm_ops at91_pwm_ops = {
+ .set_config = at91_pwm_set_config,
+ .set_enable = at91_pwm_set_enable,
+ .set_invert = at91_pwm_set_invert,
+};
+
+static const struct udevice_id at91_pwm_of_match[] = {
+ { .compatible = "atmel,sama5d2-pwm" },
+ { }
+};
+
+U_BOOT_DRIVER(at91_pwm) = {
+ .name = "at91_pwm",
+ .id = UCLASS_PWM,
+ .of_match = at91_pwm_of_match,
+ .probe = at91_pwm_probe,
+ .priv_auto = sizeof(struct at91_pwm_priv),
+ .ops = &at91_pwm_ops,
+};
sifive_ddr_phy_fixup(denali_phy);
/* check size */
- priv->info.size = get_ram_size((long *)priv->info.base,
+ priv->info.size = get_ram_size((long *)(uintptr_t)priv->info.base,
ddr_size);
debug("%s : %lx\n", __func__, (uintptr_t)priv->info.size);
return ret;
}
- priv->ctl = (struct sifive_ddrctl *)dev_read_addr_index(dev, 0);
- priv->phy = (struct sifive_ddrphy *)dev_read_addr_index(dev, 1);
- priv->physical_filter_ctrl = (u32 *)dev_read_addr_index(dev, 2);
+ priv->ctl = (struct sifive_ddrctl *)dev_read_addr_index_ptr(dev, 0);
+ priv->phy = (struct sifive_ddrphy *)dev_read_addr_index_ptr(dev, 1);
+ priv->physical_filter_ctrl = (u32 *)dev_read_addr_index_ptr(dev, 2);
return sifive_ddr_setup(dev);
#endif
#include <malloc.h>
#include <reset-uclass.h>
#include <asm/io.h>
+#include <clk/sunxi.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <linux/bitops.h>
#include <linux/log2.h>
-#include <asm/arch/ccu.h>
struct sunxi_reset_priv {
void *base;
#define RTC_YR_REG_ADDR 0x06
#define RTC_CTL_REG_ADDR 0x07
+#define DS1337_CTL_REG_ADDR 0x0e
+#define DS1337_STAT_REG_ADDR 0x0f
+#define DS1340_STAT_REG_ADDR 0x09
+
+#define RTC_STAT_BIT_OSF 0x80
+
#define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */
/* DS1307-specific bits */
if (ret < 0)
return ret;
+ if (type == ds_1337) {
+ /* Ensure oscillator is enabled */
+ dm_i2c_reg_write(dev, DS1337_CTL_REG_ADDR, 0);
+ }
+
return 0;
}
uchar buf[7];
enum ds_type type = dev_get_driver_data(dev);
-read_rtc:
ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
if (ret < 0)
return ret;
- if (type == ds_1307) {
- if (buf[RTC_SEC_REG_ADDR] & RTC_SEC_BIT_CH) {
- printf("### Warning: RTC oscillator has stopped\n");
- /* clear the CH flag */
- buf[RTC_SEC_REG_ADDR] &= ~RTC_SEC_BIT_CH;
- dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
- buf[RTC_SEC_REG_ADDR]);
- return -1;
- }
- } else if (type == ds_1337) {
- if (buf[RTC_CTL_REG_ADDR] & DS1337_CTL_BIT_EOSC) {
- printf("### Warning: RTC oscillator has stopped\n");
- /* clear the not oscillator enable (~EOSC) flag */
- buf[RTC_CTL_REG_ADDR] &= ~DS1337_CTL_BIT_EOSC;
- dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR,
- buf[RTC_CTL_REG_ADDR]);
- return -1;
- }
- } else if (type == ds_1340) {
- if (buf[RTC_SEC_REG_ADDR] & DS1340_SEC_BIT_EOSC) {
- printf("### Warning: RTC oscillator has stopped\n");
- /* clear the not oscillator enable (~EOSC) flag */
- buf[RTC_SEC_REG_ADDR] &= ~DS1340_SEC_BIT_EOSC;
- dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
- buf[RTC_SEC_REG_ADDR]);
- return -1;
- }
- } else if (type == m41t11) {
- /* clock halted? turn it on, so clock can tick. */
- if (buf[RTC_SEC_REG_ADDR] & RTC_SEC_BIT_CH) {
- buf[RTC_SEC_REG_ADDR] &= ~RTC_SEC_BIT_CH;
- dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
- MCP7941X_BIT_ST);
- dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
- buf[RTC_SEC_REG_ADDR]);
- goto read_rtc;
- }
- } else if (type == mcp794xx) {
- /* make sure that the backup battery is enabled */
- if (!(buf[RTC_DAY_REG_ADDR] & MCP7941X_BIT_VBATEN)) {
- dm_i2c_reg_write(dev, RTC_DAY_REG_ADDR,
- buf[RTC_DAY_REG_ADDR] |
- MCP7941X_BIT_VBATEN);
- }
+ if (type == ds_1337 || type == ds_1340) {
+ uint reg = (type == ds_1337) ? DS1337_STAT_REG_ADDR :
+ DS1340_STAT_REG_ADDR;
+ int status = dm_i2c_reg_read(dev, reg);
- /* clock halted? turn it on, so clock can tick. */
- if (!(buf[RTC_SEC_REG_ADDR] & MCP7941X_BIT_ST)) {
- dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
- MCP7941X_BIT_ST);
- printf("Started RTC\n");
- goto read_rtc;
+ if (status >= 0 && (status & RTC_STAT_BIT_OSF)) {
+ printf("### Warning: RTC oscillator has stopped\n");
+ /* clear the OSF flag */
+ dm_i2c_reg_write(dev, reg, status & ~RTC_STAT_BIT_OSF);
}
}
/* Write control register in order to enable oscillator output
* (not EOSC) and set a default rate of 32.768kHz (RS2|RS1).
*/
- ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR,
+ ret = dm_i2c_reg_write(dev, DS1337_CTL_REG_ADDR,
DS1337_CTL_BIT_RS2 | DS1337_CTL_BIT_RS1);
} else if (type == ds_1340 || type == mcp794xx || type == m41t11) {
/* Reset clock calibration, frequency test and output level. */
U-Boot when running on top of EFI (Extensive Firmware Interface).
This is a type of BIOS used by PCs.
+config DEBUG_SBI_CONSOLE
+ bool "SBI"
+ depends on SBI_V01
+ help
+ Select this to enable a debug console which calls back to SBI to
+ output to the console. This can be useful for early debugging of
+ U-Boot when running on top of SBI (Supervisor Binary Interface).
+
config DEBUG_UART_S5P
bool "Samsung S5P"
depends on ARCH_EXYNOS || ARCH_S5PC1XX
config DEBUG_UART_BASE
hex "Base address of UART"
depends on DEBUG_UART
+ default 0 if DEBUG_SBI_CONSOLE
default 0 if DEBUG_UART_SANDBOX
help
This is the base address of your UART for memory-mapped UARTs.
config DEBUG_UART_CLOCK
int "UART input clock"
depends on DEBUG_UART
+ default 0 if DEBUG_SBI_CONSOLE
default 0 if DEBUG_UART_SANDBOX
default 0 if DEBUG_MVEBU_A3700_UART
help
obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o
obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o
obj-$(CONFIG_CORTINA_UART) += serial_cortina.o
+obj-$(CONFIG_DEBUG_SBI_CONSOLE) += serial_sbi.o
obj-$(CONFIG_EFI_APP) += serial_efi.o
obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
obj-$(CONFIG_MCFUART) += serial_mcf.o
* anyway.
*/
if (node > 0 && !lists_bind_fdt(gd->dm_root, offset_to_ofnode(node),
- devp, false)) {
+ devp, NULL, false)) {
if (!device_probe(*devp))
return 0;
}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <debug_uart.h>
+#include <asm/sbi.h>
+
+static inline void _debug_uart_init(void)
+{
+}
+
+static inline void _debug_uart_putc(int c)
+{
+ if (CONFIG_IS_ENABLED(RISCV_SMODE))
+ sbi_console_putchar(c);
+}
+
+DEBUG_UART_FUNCS
/* Master trigger */
#define SFC_DMA_TRIGGER 0x80
+#define SFC_DMA_TRIGGER_START 1
/* Src or Dst addr for master */
#define SFC_DMA_ADDR 0x84
#define SFC_DMA_TRANS_THRETHOLD (0x40)
/* Maximum clock values from datasheet suggest keeping clock value under
- * 150MHz. No minimum or average value is suggested, but the U-boot BSP driver
- * has a minimum of 10MHz and a default of 80MHz which seems reasonable.
+ * 150MHz. No minimum or average value is suggested.
*/
-#define SFC_MIN_SPEED_HZ (10 * 1000 * 1000)
-#define SFC_DEFAULT_SPEED_HZ (80 * 1000 * 1000)
-#define SFC_MAX_SPEED_HZ (150 * 1000 * 1000)
+#define SFC_MAX_SPEED (150 * 1000 * 1000)
struct rockchip_sfc {
+ struct udevice *dev;
void __iomem *regbase;
struct clk hclk;
struct clk clk;
/* Still need to clear the masked interrupt from RISR */
writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
- debug("reset\n");
-
return err;
}
#if CONFIG_IS_ENABLED(CLK)
ret = clk_enable(&sfc->hclk);
if (ret)
- debug("Enable ahb clock fail %s: %d\n", bus->name, ret);
+ dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret);
ret = clk_enable(&sfc->clk);
if (ret)
- debug("Enable clock fail for %s: %d\n", bus->name, ret);
-
- ret = clk_set_rate(&sfc->clk, SFC_DEFAULT_SPEED_HZ);
- if (ret)
- debug("Could not set sfc clock for %s: %d\n", bus->name, ret);
+ dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret);
#endif
ret = rockchip_sfc_init(sfc);
sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc);
sfc->version = rockchip_sfc_get_version(sfc);
- sfc->speed = SFC_DEFAULT_SPEED_HZ;
+ sfc->max_freq = SFC_MAX_SPEED;
+ sfc->dev = bus;
return 0;
return ret;
}
-static inline int rockchip_sfc_get_fifo_level(struct rockchip_sfc *sfc, int wr)
+static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us)
{
- u32 fsr = readl(sfc->regbase + SFC_FSR);
- int level;
+ int ret = 0;
+ u32 status;
- if (wr)
- level = (fsr & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT;
- else
- level = (fsr & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT;
+ ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status,
+ status & SFC_FSR_TXLV_MASK,
+ timeout_us);
+ if (ret) {
+ dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n");
+
+ return -ETIMEDOUT;
+ }
- return level;
+ return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT;
}
-static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int wr, u32 timeout)
+static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us)
{
- unsigned long tbase = get_timer(0);
- int level;
+ int ret = 0;
+ u32 status;
- while (!(level = rockchip_sfc_get_fifo_level(sfc, wr))) {
- if (get_timer(tbase) > timeout) {
- debug("%s fifo timeout\n", wr ? "write" : "read");
- return -ETIMEDOUT;
- }
- udelay(1);
+ ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status,
+ status & SFC_FSR_RXLV_MASK,
+ timeout_us);
+ if (ret) {
+ dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n");
+
+ return -ETIMEDOUT;
}
- return level;
+ return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT;
}
static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op)
ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE;
cmd |= plat->cs << SFC_CMD_CS_SHIFT;
- debug("addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
- op->addr.nbytes, op->addr.buswidth,
- op->dummy.nbytes, op->dummy.buswidth);
- debug("ctrl=%x cmd=%x addr=%llx len=%x\n",
- ctrl, cmd, op->addr.val, len);
+ dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
+ op->addr.nbytes, op->addr.buswidth,
+ op->dummy.nbytes, op->dummy.buswidth);
+ dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n",
+ ctrl, cmd, op->addr.val, len);
writel(ctrl, sfc->regbase + SFC_CTRL);
writel(cmd, sfc->regbase + SFC_CMD);
dwords = len >> 2;
while (dwords) {
- tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000);
+ tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000);
if (tx_level < 0)
return tx_level;
write_words = min_t(u32, tx_level, dwords);
/* write the rest non word aligned bytes */
if (bytes) {
- tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000);
+ tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000);
if (tx_level < 0)
return tx_level;
memcpy(&tmp, buf, bytes);
/* word aligned access only */
dwords = len >> 2;
while (dwords) {
- rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000);
+ rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000);
if (rx_level < 0)
return rx_level;
read_words = min_t(u32, rx_level, dwords);
/* read the rest non word aligned bytes */
if (bytes) {
- rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000);
+ rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000);
if (rx_level < 0)
return rx_level;
tmp = readl(sfc->regbase + SFC_DATA);
{
writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR);
- writel(0x1, sfc->regbase + SFC_DMA_TRIGGER);
+ writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER);
return len;
}
static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc,
const struct spi_mem_op *op, u32 len)
{
- debug("xfer_poll len=%x\n", len);
+ dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len);
if (op->data.dir == SPI_MEM_DATA_OUT)
return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len);
void *dma_buf;
int ret;
- debug("xfer_dma len=%x\n", len);
+ dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len);
if (op->data.dir == SPI_MEM_DATA_OUT) {
dma_buf = (void *)op->data.buf.out;
static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us)
{
- unsigned long tbase = get_timer(0);
int ret = 0;
- u32 timeout = timeout_us;
-
- while (readl(sfc->regbase + SFC_SR) & SFC_SR_IS_BUSY) {
- if (get_timer(tbase) > timeout) {
- printf("wait sfc idle timeout\n");
- rockchip_sfc_reset(sfc);
+ u32 status;
- return -ETIMEDOUT;
- }
+ ret = readl_poll_timeout(sfc->regbase + SFC_SR, status,
+ !(status & SFC_SR_IS_BUSY),
+ timeout_us);
+ if (ret) {
+ dev_err(sfc->dev, "wait sfc idle timeout\n");
+ rockchip_sfc_reset(sfc);
- udelay(1);
+ ret = -EIO;
}
return ret;
u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize);
int ret;
-#if CONFIG_IS_ENABLED(CLK)
- if (unlikely(mem->max_hz != sfc->speed)) {
- ret = clk_set_rate(&sfc->clk, clamp(mem->max_hz, (uint)SFC_MIN_SPEED_HZ,
- (uint)SFC_MAX_SPEED_HZ));
- if (ret < 0) {
- printf("set_freq=%dHz fail, check if it's the cru support level\n",
- mem->max_hz);
- return ret;
- }
-
- sfc->max_freq = mem->max_hz;
- sfc->speed = mem->max_hz;
- debug("set_freq=%dHz real_freq=%dHz\n", sfc->max_freq, sfc->speed);
- }
-#endif
-
rockchip_sfc_adjust_op_work((struct spi_mem_op *)op);
-
rockchip_sfc_xfer_setup(sfc, mem, op, len);
if (len) {
- if (likely(sfc->use_dma) && !(len & 0x3) && len >= SFC_DMA_TRANS_THRETHOLD)
+ if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD)
ret = rockchip_sfc_xfer_data_dma(sfc, op, len);
else
ret = rockchip_sfc_xfer_data_poll(sfc, op, len);
if (ret != len) {
- printf("xfer data failed ret %d dir %d\n", ret, op->data.dir);
+ dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir);
return -EIO;
}
struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent);
op->data.nbytes = min(op->data.nbytes, sfc->max_iosize);
+
return 0;
}
static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
{
- /* We set up speed later for each transmission.
- */
+ struct rockchip_sfc *sfc = dev_get_plat(bus);
+
+ if (speed > sfc->max_freq)
+ speed = sfc->max_freq;
+
+ if (speed == sfc->speed)
+ return 0;
+
+#if CONFIG_IS_ENABLED(CLK)
+ int ret = clk_set_rate(&sfc->clk, speed);
+
+ if (ret < 0) {
+ dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n",
+ speed);
+ return ret;
+ }
+ sfc->speed = speed;
+#else
+ dev_dbg(sfc->dev, "sfc failed, CLK not support\n");
+#endif
return 0;
}
break;
}
- pin = name_to_gpio(pin_name);
+ pin = sunxi_name_to_gpio(pin_name);
if (pin < 0)
break;
#define SPI_SIMPLEX_RX 2
#define SPI_HALF_DUPLEX 3
-struct stm32_spi_priv {
+struct stm32_spi_plat {
void __iomem *base;
struct clk clk;
struct reset_ctl rst_ctl;
struct gpio_desc cs_gpios[MAX_CS_COUNT];
+};
+
+struct stm32_spi_priv {
ulong bus_clk_rate;
unsigned int fifo_size;
unsigned int cur_bpw;
bool cs_high;
};
-static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv)
+static void stm32_spi_write_txfifo(struct udevice *bus)
{
+ struct stm32_spi_priv *priv = dev_get_priv(bus);
+ struct stm32_spi_plat *plat = dev_get_plat(bus);
+ void __iomem *base = plat->base;
+
while ((priv->tx_len > 0) &&
- (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)) {
+ (readl(base + STM32_SPI_SR) & SPI_SR_TXP)) {
u32 offs = priv->cur_xferlen - priv->tx_len;
if (priv->tx_len >= sizeof(u32) &&
IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u32))) {
const u32 *tx_buf32 = (const u32 *)(priv->tx_buf + offs);
- writel(*tx_buf32, priv->base + STM32_SPI_TXDR);
+ writel(*tx_buf32, base + STM32_SPI_TXDR);
priv->tx_len -= sizeof(u32);
} else if (priv->tx_len >= sizeof(u16) &&
IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u16))) {
const u16 *tx_buf16 = (const u16 *)(priv->tx_buf + offs);
- writew(*tx_buf16, priv->base + STM32_SPI_TXDR);
+ writew(*tx_buf16, base + STM32_SPI_TXDR);
priv->tx_len -= sizeof(u16);
} else {
const u8 *tx_buf8 = (const u8 *)(priv->tx_buf + offs);
- writeb(*tx_buf8, priv->base + STM32_SPI_TXDR);
+ writeb(*tx_buf8, base + STM32_SPI_TXDR);
priv->tx_len -= sizeof(u8);
}
}
log_debug("%d bytes left\n", priv->tx_len);
}
-static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv)
+static void stm32_spi_read_rxfifo(struct udevice *bus)
{
- u32 sr = readl(priv->base + STM32_SPI_SR);
+ struct stm32_spi_priv *priv = dev_get_priv(bus);
+ struct stm32_spi_plat *plat = dev_get_plat(bus);
+ void __iomem *base = plat->base;
+ u32 sr = readl(base + STM32_SPI_SR);
u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
while ((priv->rx_len > 0) &&
(priv->rx_len >= sizeof(u32) || (sr & SPI_SR_RXWNE))) {
u32 *rx_buf32 = (u32 *)(priv->rx_buf + offs);
- *rx_buf32 = readl(priv->base + STM32_SPI_RXDR);
+ *rx_buf32 = readl(base + STM32_SPI_RXDR);
priv->rx_len -= sizeof(u32);
} else if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u16)) &&
(priv->rx_len >= sizeof(u16) ||
(rxplvl >= 2 || priv->cur_bpw > 8)))) {
u16 *rx_buf16 = (u16 *)(priv->rx_buf + offs);
- *rx_buf16 = readw(priv->base + STM32_SPI_RXDR);
+ *rx_buf16 = readw(base + STM32_SPI_RXDR);
priv->rx_len -= sizeof(u16);
} else {
u8 *rx_buf8 = (u8 *)(priv->rx_buf + offs);
- *rx_buf8 = readb(priv->base + STM32_SPI_RXDR);
+ *rx_buf8 = readb(base + STM32_SPI_RXDR);
priv->rx_len -= sizeof(u8);
}
- sr = readl(priv->base + STM32_SPI_SR);
+ sr = readl(base + STM32_SPI_SR);
rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
}
log_debug("%d bytes left\n", priv->rx_len);
}
-static int stm32_spi_enable(struct stm32_spi_priv *priv)
+static int stm32_spi_enable(void __iomem *base)
{
log_debug("\n");
/* Enable the SPI hardware */
- setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
+ setbits_le32(base + STM32_SPI_CR1, SPI_CR1_SPE);
return 0;
}
-static int stm32_spi_disable(struct stm32_spi_priv *priv)
+static int stm32_spi_disable(void __iomem *base)
{
log_debug("\n");
/* Disable the SPI hardware */
- clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
+ clrbits_le32(base + STM32_SPI_CR1, SPI_CR1_SPE);
return 0;
}
static int stm32_spi_claim_bus(struct udevice *slave)
{
struct udevice *bus = dev_get_parent(slave);
- struct stm32_spi_priv *priv = dev_get_priv(bus);
+ struct stm32_spi_plat *plat = dev_get_plat(bus);
+ void __iomem *base = plat->base;
dev_dbg(slave, "\n");
/* Enable the SPI hardware */
- return stm32_spi_enable(priv);
+ return stm32_spi_enable(base);
}
static int stm32_spi_release_bus(struct udevice *slave)
{
struct udevice *bus = dev_get_parent(slave);
- struct stm32_spi_priv *priv = dev_get_priv(bus);
+ struct stm32_spi_plat *plat = dev_get_plat(bus);
+ void __iomem *base = plat->base;
dev_dbg(slave, "\n");
/* Disable the SPI hardware */
- return stm32_spi_disable(priv);
+ return stm32_spi_disable(base);
}
static void stm32_spi_stopxfer(struct udevice *dev)
{
- struct stm32_spi_priv *priv = dev_get_priv(dev);
+ struct stm32_spi_plat *plat = dev_get_plat(dev);
+ void __iomem *base = plat->base;
u32 cr1, sr;
int ret;
dev_dbg(dev, "\n");
- cr1 = readl(priv->base + STM32_SPI_CR1);
+ cr1 = readl(base + STM32_SPI_CR1);
if (!(cr1 & SPI_CR1_SPE))
return;
/* Wait on EOT or suspend the flow */
- ret = readl_poll_timeout(priv->base + STM32_SPI_SR, sr,
+ ret = readl_poll_timeout(base + STM32_SPI_SR, sr,
!(sr & SPI_SR_EOT), 100000);
if (ret < 0) {
if (cr1 & SPI_CR1_CSTART) {
- writel(cr1 | SPI_CR1_CSUSP, priv->base + STM32_SPI_CR1);
- if (readl_poll_timeout(priv->base + STM32_SPI_SR,
+ writel(cr1 | SPI_CR1_CSUSP, base + STM32_SPI_CR1);
+ if (readl_poll_timeout(base + STM32_SPI_SR,
sr, !(sr & SPI_SR_SUSP),
100000) < 0)
dev_err(dev, "Suspend request timeout\n");
}
/* clear status flags */
- setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
+ setbits_le32(base + STM32_SPI_IFCR, SPI_IFCR_ALL);
}
static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
{
+ struct stm32_spi_plat *plat = dev_get_plat(dev);
struct stm32_spi_priv *priv = dev_get_priv(dev);
dev_dbg(dev, "cs=%d enable=%d\n", cs, enable);
if (cs >= MAX_CS_COUNT)
return -ENODEV;
- if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
+ if (!dm_gpio_is_valid(&plat->cs_gpios[cs]))
return -EINVAL;
if (priv->cs_high)
enable = !enable;
- return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
+ return dm_gpio_set_value(&plat->cs_gpios[cs], enable ? 1 : 0);
}
static int stm32_spi_set_mode(struct udevice *bus, uint mode)
{
struct stm32_spi_priv *priv = dev_get_priv(bus);
+ struct stm32_spi_plat *plat = dev_get_plat(bus);
+ void __iomem *base = plat->base;
u32 cfg2_clrb = 0, cfg2_setb = 0;
dev_dbg(bus, "mode=%d\n", mode);
cfg2_clrb |= SPI_CFG2_LSBFRST;
if (cfg2_clrb || cfg2_setb)
- clrsetbits_le32(priv->base + STM32_SPI_CFG2,
+ clrsetbits_le32(base + STM32_SPI_CFG2,
cfg2_clrb, cfg2_setb);
if (mode & SPI_CS_HIGH)
static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len)
{
struct stm32_spi_priv *priv = dev_get_priv(dev);
+ struct stm32_spi_plat *plat = dev_get_plat(dev);
+ void __iomem *base = plat->base;
u32 fthlv, half_fifo;
/* data packet should not exceed 1/2 of fifo space */
if (!fthlv)
fthlv = 1;
- clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_FTHLV,
+ clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_FTHLV,
(fthlv - 1) << SPI_CFG1_FTHLV_SHIFT);
return 0;
static int stm32_spi_set_speed(struct udevice *bus, uint hz)
{
struct stm32_spi_priv *priv = dev_get_priv(bus);
+ struct stm32_spi_plat *plat = dev_get_plat(bus);
+ void __iomem *base = plat->base;
u32 mbrdiv;
long div;
if (!mbrdiv)
return -EINVAL;
- clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR,
+ clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_MBR,
(mbrdiv - 1) << SPI_CFG1_MBR_SHIFT);
priv->cur_hz = hz;
struct udevice *bus = dev_get_parent(slave);
struct dm_spi_slave_plat *slave_plat;
struct stm32_spi_priv *priv = dev_get_priv(bus);
+ struct stm32_spi_plat *plat = dev_get_plat(bus);
+ void __iomem *base = plat->base;
u32 sr;
u32 ifcr = 0;
u32 xferlen;
xferlen = bitlen / 8;
if (xferlen <= SPI_CR2_TSIZE)
- writel(xferlen, priv->base + STM32_SPI_CR2);
+ writel(xferlen, base + STM32_SPI_CR2);
else
return -EMSGSIZE;
priv->cur_xferlen = xferlen;
/* Disable the SPI hardware to unlock CFG1/CFG2 registers */
- stm32_spi_disable(priv);
+ stm32_spi_disable(base);
- clrsetbits_le32(priv->base + STM32_SPI_CFG2, SPI_CFG2_COMM,
+ clrsetbits_le32(base + STM32_SPI_CFG2, SPI_CFG2_COMM,
mode << SPI_CFG2_COMM_SHIFT);
stm32_spi_set_fthlv(bus, xferlen);
/* Enable the SPI hardware */
- stm32_spi_enable(priv);
+ stm32_spi_enable(base);
}
dev_dbg(bus, "priv->tx_len=%d priv->rx_len=%d\n",
/* Be sure to have data in fifo before starting data transfer */
if (priv->tx_buf)
- stm32_spi_write_txfifo(priv);
+ stm32_spi_write_txfifo(bus);
- setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_CSTART);
+ setbits_le32(base + STM32_SPI_CR1, SPI_CR1_CSTART);
while (1) {
- sr = readl(priv->base + STM32_SPI_SR);
+ sr = readl(base + STM32_SPI_SR);
if (sr & SPI_SR_OVR) {
dev_err(bus, "Overrun: RX data lost\n");
dev_warn(bus, "System too slow is limiting data throughput\n");
if (priv->rx_buf && priv->rx_len > 0)
- stm32_spi_read_rxfifo(priv);
+ stm32_spi_read_rxfifo(bus);
ifcr |= SPI_SR_SUSP;
}
if (sr & SPI_SR_TXP)
if (priv->tx_buf && priv->tx_len > 0)
- stm32_spi_write_txfifo(priv);
+ stm32_spi_write_txfifo(bus);
if (sr & SPI_SR_RXP)
if (priv->rx_buf && priv->rx_len > 0)
- stm32_spi_read_rxfifo(priv);
+ stm32_spi_read_rxfifo(bus);
if (sr & SPI_SR_EOT) {
if (priv->rx_buf && priv->rx_len > 0)
- stm32_spi_read_rxfifo(priv);
+ stm32_spi_read_rxfifo(bus);
break;
}
- writel(ifcr, priv->base + STM32_SPI_IFCR);
+ writel(ifcr, base + STM32_SPI_IFCR);
}
/* clear status flags */
- setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
+ setbits_le32(base + STM32_SPI_IFCR, SPI_IFCR_ALL);
stm32_spi_stopxfer(bus);
if (flags & SPI_XFER_END)
static int stm32_spi_get_fifo_size(struct udevice *dev)
{
- struct stm32_spi_priv *priv = dev_get_priv(dev);
+ struct stm32_spi_plat *plat = dev_get_plat(dev);
+ void __iomem *base = plat->base;
u32 count = 0;
- stm32_spi_enable(priv);
+ stm32_spi_enable(base);
- while (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)
- writeb(++count, priv->base + STM32_SPI_TXDR);
+ while (readl(base + STM32_SPI_SR) & SPI_SR_TXP)
+ writeb(++count, base + STM32_SPI_TXDR);
- stm32_spi_disable(priv);
+ stm32_spi_disable(base);
dev_dbg(dev, "%d x 8-bit fifo size\n", count);
return count;
}
+static int stm32_spi_of_to_plat(struct udevice *dev)
+{
+ struct stm32_spi_plat *plat = dev_get_plat(dev);
+ int ret;
+
+ plat->base = dev_read_addr_ptr(dev);
+ if (!plat->base) {
+ dev_err(dev, "can't get registers base address\n");
+ return -ENOENT;
+ }
+
+ ret = clk_get_by_index(dev, 0, &plat->clk);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_get_by_index(dev, 0, &plat->rst_ctl);
+ if (ret < 0)
+ goto clk_err;
+
+ ret = gpio_request_list_by_name(dev, "cs-gpios", plat->cs_gpios,
+ ARRAY_SIZE(plat->cs_gpios), 0);
+ if (ret < 0) {
+ dev_err(dev, "Can't get %s cs gpios: %d", dev->name, ret);
+ ret = -ENOENT;
+ goto clk_err;
+ }
+
+ return 0;
+
+clk_err:
+ clk_free(&plat->clk);
+
+ return ret;
+}
+
static int stm32_spi_probe(struct udevice *dev)
{
+ struct stm32_spi_plat *plat = dev_get_plat(dev);
struct stm32_spi_priv *priv = dev_get_priv(dev);
+ void __iomem *base = plat->base;
unsigned long clk_rate;
int ret;
unsigned int i;
- priv->base = dev_remap_addr(dev);
- if (!priv->base)
- return -EINVAL;
-
/* enable clock */
- ret = clk_get_by_index(dev, 0, &priv->clk);
+ ret = clk_enable(&plat->clk);
if (ret < 0)
return ret;
- ret = clk_enable(&priv->clk);
- if (ret < 0)
- return ret;
-
- clk_rate = clk_get_rate(&priv->clk);
+ clk_rate = clk_get_rate(&plat->clk);
if (!clk_rate) {
ret = -EINVAL;
goto clk_err;
priv->bus_clk_rate = clk_rate;
/* perform reset */
- ret = reset_get_by_index(dev, 0, &priv->rst_ctl);
- if (ret < 0)
- goto clk_err;
-
- reset_assert(&priv->rst_ctl);
+ reset_assert(&plat->rst_ctl);
udelay(2);
- reset_deassert(&priv->rst_ctl);
-
- ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
- ARRAY_SIZE(priv->cs_gpios), 0);
- if (ret < 0) {
- dev_err(dev, "Can't get cs gpios: %d", ret);
- goto reset_err;
- }
+ reset_deassert(&plat->rst_ctl);
priv->fifo_size = stm32_spi_get_fifo_size(dev);
-
priv->cur_mode = SPI_FULL_DUPLEX;
priv->cur_xferlen = 0;
priv->cur_bpw = SPI_DEFAULT_WORDLEN;
- clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
+ clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
priv->cur_bpw - 1);
- for (i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
- if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
+ for (i = 0; i < ARRAY_SIZE(plat->cs_gpios); i++) {
+ if (!dm_gpio_is_valid(&plat->cs_gpios[i]))
continue;
- dm_gpio_set_dir_flags(&priv->cs_gpios[i],
+ dm_gpio_set_dir_flags(&plat->cs_gpios[i],
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
}
/* Ensure I2SMOD bit is kept cleared */
- clrbits_le32(priv->base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
+ clrbits_le32(base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
/*
* - SS input value high
* - transmitter half duplex direction
* - automatic communication suspend when RX-Fifo is full
*/
- setbits_le32(priv->base + STM32_SPI_CR1,
+ setbits_le32(base + STM32_SPI_CR1,
SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX);
/*
* SS input value is determined by the SSI bit
* - keep control of all associated GPIOs
*/
- setbits_le32(priv->base + STM32_SPI_CFG2,
+ setbits_le32(base + STM32_SPI_CFG2,
SPI_CFG2_MASTER | SPI_CFG2_SSM | SPI_CFG2_AFCNTR);
return 0;
-reset_err:
- reset_free(&priv->rst_ctl);
-
clk_err:
- clk_disable(&priv->clk);
- clk_free(&priv->clk);
+ clk_disable(&plat->clk);
+ clk_free(&plat->clk);
return ret;
};
static int stm32_spi_remove(struct udevice *dev)
{
- struct stm32_spi_priv *priv = dev_get_priv(dev);
+ struct stm32_spi_plat *plat = dev_get_plat(dev);
+ void __iomem *base = plat->base;
int ret;
stm32_spi_stopxfer(dev);
- stm32_spi_disable(priv);
+ stm32_spi_disable(base);
- ret = reset_assert(&priv->rst_ctl);
+ ret = reset_assert(&plat->rst_ctl);
if (ret < 0)
return ret;
- reset_free(&priv->rst_ctl);
+ reset_free(&plat->rst_ctl);
- ret = clk_disable(&priv->clk);
+ ret = clk_disable(&plat->clk);
if (ret < 0)
return ret;
- clk_free(&priv->clk);
+ clk_free(&plat->clk);
return ret;
};
.id = UCLASS_SPI,
.of_match = stm32_spi_ids,
.ops = &stm32_spi_ops,
- .priv_auto = sizeof(struct stm32_spi_priv),
+ .of_to_plat = stm32_spi_of_to_plat,
+ .plat_auto = sizeof(struct stm32_spi_plat),
+ .priv_auto = sizeof(struct stm32_spi_priv),
.probe = stm32_spi_probe,
.remove = stm32_spi_remove,
};
Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware
must be running on your system.
+config SYSRESET_SBI
+ bool "Enable support for SBI System Reset"
+ depends on RISCV_SMODE && SBI_V02
+ select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
+ help
+ Enable system reset and poweroff via the SBI system reset extension.
+ The extension was introduced in version 0.3 of the SBI specification.
+
+ If the SBI implementation provides the extension, is board specific.
+ The RISC-V platform specification mandates the extension for rich
+ operating system platforms.
+
config SYSRESET_SOCFPGA
bool "Enable support for Intel SOCFPGA family"
depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10)
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
+obj-$(CONFIG_SYSRESET_SBI) += sysreset_sbi.o
obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o
obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <sysreset.h>
+#include <asm/sbi.h>
+
+static enum sbi_srst_reset_type reset_type_map[SYSRESET_COUNT] = {
+ [SYSRESET_WARM] = SBI_SRST_RESET_TYPE_WARM_REBOOT,
+ [SYSRESET_COLD] = SBI_SRST_RESET_TYPE_COLD_REBOOT,
+ [SYSRESET_POWER] = SBI_SRST_RESET_TYPE_COLD_REBOOT,
+ [SYSRESET_POWER_OFF] = SBI_SRST_RESET_TYPE_SHUTDOWN,
+};
+
+static int sbi_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ enum sbi_srst_reset_type reset_type;
+
+ reset_type = reset_type_map[type];
+ sbi_srst_reset(reset_type, SBI_SRST_RESET_REASON_NONE);
+
+ return -EINPROGRESS;
+}
+
+static int sbi_sysreset_probe(struct udevice *dev)
+{
+ long have_reset;
+
+ have_reset = sbi_probe_extension(SBI_EXT_SRST);
+ if (have_reset)
+ return 0;
+
+ log_warning("SBI has no system reset extension\n");
+ return -ENOENT;
+}
+
+static struct sysreset_ops sbi_sysreset_ops = {
+ .request = sbi_sysreset_request,
+};
+
+U_BOOT_DRIVER(sbi_sysreset) = {
+ .name = "sbi-sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &sbi_sysreset_ops,
+ .probe = sbi_sysreset_probe,
+};
* If the timer is not marked to be bound before
* relocation, bind it anyway.
*/
- if (!lists_bind_fdt(dm_root(), node, &dev, false)) {
+ if (!lists_bind_fdt(dm_root(), node, &dev, NULL, false)) {
ret = device_probe(dev);
if (ret)
return ret;
}
static const struct udevice_id dwc3_meson_gxl_ids[] = {
+ { .compatible = "amlogic,meson-axg-usb-ctrl" },
{ .compatible = "amlogic,meson-gxl-usb-ctrl" },
{ .compatible = "amlogic,meson-gxm-usb-ctrl" },
{ }
#define gadget_is_mtu3(g) 0
#endif
+#ifdef CONFIG_USB_GADGET_DWC2_OTG
+#define gadget_is_dwc2(g) (!strcmp("dwc2-udc", (g)->name))
+#else
+#define gadget_is_dwc2(g) 0
+#endif
+
/**
* usb_gadget_controller_number - support bcdDevice id convention
* @gadget: the controller being driven
return 0x25;
else if (gadget_is_mtu3(gadget))
return 0x26;
+ else if (gadget_is_dwc2(gadget))
+ return 0x27;
return -ENOENT;
}
if USB_EHCI_HCD
+config USB_EHCI_IS_TDI
+ bool
+
config USB_EHCI_ATMEL
bool "Support for Atmel on-chip EHCI USB controller"
depends on ARCH_AT91
bool "Support for Marvell on-chip EHCI USB controller"
depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X
default y
+ select USB_EHCI_IS_TDI if !ARM64
---help---
Enables support for the on-chip EHCI controller on MVEBU SoCs.
---help---
Enables support for the on-chip EHCI controller on i.MX7 SoCs.
+config USB_EHCI_MXS
+ bool "Support for i.MX23 EHCI USB controller"
+ depends on ARCH_MX23
+ default y
+ select USB_EHCI_IS_TDI
+ help
+ Enables support for the on-chip EHCI controller on i.MX23 SoCs.
+
config USB_EHCI_OMAP
bool "Support for OMAP3+ on-chip EHCI USB controller"
depends on ARCH_OMAP2PLUS
config USB_EHCI_TEGRA
bool "Support for NVIDIA Tegra on-chip EHCI USB controller"
depends on ARCH_TEGRA
+ select USB_EHCI_IS_TDI
---help---
Enable support for Tegra on-chip EHCI USB controller
config USB_EHCI_ZYNQ
bool "Support for Xilinx Zynq on-chip EHCI USB controller"
default y if ARCH_ZYNQ
+ select USB_EHCI_IS_TDI
---help---
Enable support for Zynq on-chip EHCI USB controller
},
};
-#if defined(CONFIG_EHCI_IS_TDI)
+#if defined(CONFIG_USB_EHCI_IS_TDI)
#define ehci_is_TDI() (1)
#else
#define ehci_is_TDI() (0)
#include <log.h>
#include <usb.h>
#include <dm/root.h>
+#include <linux/usb/gadget.h>
+
+struct sandbox_udc {
+ struct usb_gadget gadget;
+};
+
+struct sandbox_udc *this_controller;
struct sandbox_usb_ctrl {
int rootdev;
return ret;
}
+int usb_gadget_handle_interrupts(int index)
+{
+ return 0;
+}
+
+int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+{
+ struct sandbox_udc *dev = this_controller;
+
+ return driver->bind(&dev->gadget);
+}
+
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+ struct sandbox_udc *dev = this_controller;
+
+ driver->unbind(&dev->gadget);
+
+ return 0;
+}
+
static int sandbox_alloc_device(struct udevice *dev, struct usb_device *udev)
{
struct sandbox_usb_ctrl *ctrl = dev_get_priv(dev);
#include <reset.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm-generic/gpio.h>
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <dm/root.h>
default ""
---help---
The reset pin of SSD2828 chip. This takes a string in the format
- understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
+ understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H.
config VIDEO_LCD_TDO_TL070WSH30
bool "TDO TL070WSH30 DSI LCD panel support"
This is one of the SPI communication pins, involved in setting up a
working LCD configuration. The exact role of SPI may differ for
different hardware setups. The option takes a string in the format
- understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
+ understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H.
config VIDEO_LCD_SPI_SCLK
string "SPI SCLK pin for LCD related config job"
This is one of the SPI communication pins, involved in setting up a
working LCD configuration. The exact role of SPI may differ for
different hardware setups. The option takes a string in the format
- understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
+ understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H.
config VIDEO_LCD_SPI_MOSI
string "SPI MOSI pin for LCD related config job"
This is one of the SPI communication pins, involved in setting up a
working LCD configuration. The exact role of SPI may differ for
different hardware setups. The option takes a string in the format
- understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
+ understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H.
config VIDEO_LCD_SPI_MISO
string "SPI MISO pin for LCD related config job (optional)"
different hardware setups. If wired up, this pin may provide additional
useful functionality. Such as bi-directional communication with the
hardware and LCD panel id retrieval (if the panel can report it). The
- option takes a string in the format understood by 'name_to_gpio'
+ option takes a string in the format understood by 'sunxi_name_to_gpio'
function, e.g. PH1 for pin 1 of port H.
source "drivers/video/meson/Kconfig"
source "drivers/video/imx/Kconfig"
+config VIDEO_MXS
+ bool "Enable video support on i.MX28/i.MX6UL/i.MX7 SoCs"
+ depends on DM_VIDEO
+ help
+ Enable framebuffer driver for i.MX28/i.MX6UL/i.MX7 processors
+
config VIDEO_NX
bool "Enable video support on Nexell SoC"
depends on ARCH_S5P6818 || ARCH_S5P4418
obj-${CONFIG_VIDEO_MESON} += meson/
obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_dsi.o
obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o
-obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
obj-$(CONFIG_VIDEO_NX) += nexell_display.o videomodes.o nexell/
obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
* This function will init an anx9804 parallel lcd to dp bridge chip
* using the passed in parameters.
*
- * @i2c_bus: Number of the i2c bus to which the anx9804 is connected.
+ * @i2c_bus: Device of the i2c bus to which the anx9804 is connected.
* @lanes: Number of displayport lanes to use
* @data_rate: Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G
* @bpp: Bits per pixel, must be 18 or 24
*/
-void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp)
+void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp)
{
- unsigned int orig_i2c_bus = i2c_get_bus_num();
- u8 c, colordepth;
- int i;
+ struct udevice *chip0, *chip1;
+ int c, colordepth, i, ret;
- i2c_set_bus_num(i2c_bus);
+ ret = i2c_get_chip(i2c_bus, 0x38, 1, &chip0);
+ if (ret)
+ return;
+
+ ret = i2c_get_chip(i2c_bus, 0x39, 1, &chip1);
+ if (ret)
+ return;
if (bpp == 18)
colordepth = 0x00; /* 6 bit */
colordepth = 0x10; /* 8 bit */
/* Reset */
- i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 1);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 1);
mdelay(100);
- i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 0);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 0);
/* Write 0 to the powerdown reg (powerup everything) */
- i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, 0);
+ dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, 0);
- c = i2c_reg_read(0x39, ANX9804_DEV_IDH_REG);
+ c = dm_i2c_reg_read(chip1, ANX9804_DEV_IDH_REG);
if (c != 0x98) {
printf("Error anx9804 chipid mismatch\n");
- i2c_set_bus_num(orig_i2c_bus);
return;
}
for (i = 0; i < 100; i++) {
- c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
- i2c_reg_write(0x38, ANX9804_SYS_CTRL2_REG, c);
- c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
+ c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG);
+ dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL2_REG, c);
+ c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG);
if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
break;
if (i == 100)
printf("Error anx9804 clock is not stable\n");
- i2c_reg_write(0x39, ANX9804_VID_CTRL2_REG, colordepth);
+ dm_i2c_reg_write(chip1, ANX9804_VID_CTRL2_REG, colordepth);
/* Set a bunch of analog related register values */
- i2c_reg_write(0x38, ANX9804_PLL_CTRL_REG, 0x07);
- i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL3, 0x19);
- i2c_reg_write(0x39, ANX9804_PLL_CTRL3, 0xd9);
- i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
- i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
- i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG3, 0x99);
- i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL1, 0x7b);
- i2c_reg_write(0x38, ANX9804_LINK_DEBUG_REG, 0x30);
- i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL, 0x06);
+ dm_i2c_reg_write(chip0, ANX9804_PLL_CTRL_REG, 0x07);
+ dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL3, 0x19);
+ dm_i2c_reg_write(chip1, ANX9804_PLL_CTRL3, 0xd9);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
+ dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
+ dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG3, 0x99);
+ dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL1, 0x7b);
+ dm_i2c_reg_write(chip0, ANX9804_LINK_DEBUG_REG, 0x30);
+ dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL, 0x06);
/* Force HPD */
- i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
- ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
+ dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG,
+ ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
/* Power up and configure lanes */
- i2c_reg_write(0x38, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
- i2c_reg_write(0x38, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
- i2c_reg_write(0x38, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
- i2c_reg_write(0x38, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
- i2c_reg_write(0x38, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
/* Reset AUX CH */
- i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
- ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
- i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
- ANX9804_RST_CTRL2_AC_MODE);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG,
+ ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG,
+ ANX9804_RST_CTRL2_AC_MODE);
/* Powerdown audio and some other unused bits */
- i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
- i2c_reg_write(0x38, ANX9804_HDCP_CONTROL_0_REG, 0x00);
- i2c_reg_write(0x38, 0xa7, 0x00);
+ dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
+ dm_i2c_reg_write(chip0, ANX9804_HDCP_CONTROL_0_REG, 0x00);
+ dm_i2c_reg_write(chip0, 0xa7, 0x00);
/* Set data-rate / lanes */
- i2c_reg_write(0x38, ANX9804_LINK_BW_SET_REG, data_rate);
- i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes);
+ dm_i2c_reg_write(chip0, ANX9804_LINK_BW_SET_REG, data_rate);
+ dm_i2c_reg_write(chip0, ANX9804_LANE_COUNT_SET_REG, lanes);
/* Link training */
- i2c_reg_write(0x38, ANX9804_LINK_TRAINING_CTRL_REG,
- ANX9804_LINK_TRAINING_CTRL_EN);
+ dm_i2c_reg_write(chip0, ANX9804_LINK_TRAINING_CTRL_REG,
+ ANX9804_LINK_TRAINING_CTRL_EN);
mdelay(5);
for (i = 0; i < 100; i++) {
- c = i2c_reg_read(0x38, ANX9804_LINK_TRAINING_CTRL_REG);
+ c = dm_i2c_reg_read(chip0, ANX9804_LINK_TRAINING_CTRL_REG);
if ((c & 0x01) == 0)
break;
}
if(i == 100) {
printf("Error anx9804 link training timeout\n");
- i2c_set_bus_num(orig_i2c_bus);
return;
}
/* Enable */
- i2c_reg_write(0x39, ANX9804_VID_CTRL1_REG,
- ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
+ dm_i2c_reg_write(chip1, ANX9804_VID_CTRL1_REG,
+ ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
/* Force stream valid */
- i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
- ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
- ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
-
- i2c_set_bus_num(orig_i2c_bus);
+ dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG,
+ ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
+ ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
}
#define ANX9804_DATA_RATE_2700M 0x0a
#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
-void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp);
+void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp);
#else
-static inline void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate,
+static inline void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate,
int bpp) {}
#endif
+
#endif
#include <dm/ofnode.h>
#include <linux/compiler.h>
-#if defined(CONFIG_VIDEO_MXS)
-#define VIDEO_FB_16BPP_WORD_SWAP
-#endif
-
-/*
- * Defines for the i.MX31 driver (mx3fb.c)
- */
-#if defined(CONFIG_VIDEO_MX3) || defined(CONFIG_VIDEO_IPUV3)
-#define VIDEO_FB_16BPP_WORD_SWAP
-#endif
-
/*
* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc.
*/
};
int i, cs, clk, mosi, ret = 0;
- cs = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS);
- clk = name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK);
- mosi = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI);
+ cs = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS);
+ clk = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK);
+ mosi = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI);
if (cs == -1 || clk == -1 || mosi == 1) {
printf("Error tx18d42vm spi gpio config is invalid\n");
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2009
- * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
- * Copyright (C) 2011
- * HALE electronic GmbH, <helmut.raiger@hale.at>
- */
-#include <common.h>
-#include <env.h>
-#include <log.h>
-#include <malloc.h>
-#include <video_fb.h>
-#include <linux/delay.h>
-
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <linux/errno.h>
-#include <asm/io.h>
-
-#include "videomodes.h"
-
-/* this might need panel specific set-up as-well */
-#define IF_CONF 0
-
-/* -------------- controller specific stuff -------------- */
-
-/* IPU DMA Controller channel definitions. */
-enum ipu_channel {
- IDMAC_IC_0 = 0, /* IC (encoding task) to memory */
- IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */
- IDMAC_ADC_0 = 1,
- IDMAC_IC_2 = 2,
- IDMAC_ADC_1 = 2,
- IDMAC_IC_3 = 3,
- IDMAC_IC_4 = 4,
- IDMAC_IC_5 = 5,
- IDMAC_IC_6 = 6,
- IDMAC_IC_7 = 7, /* IC (sensor data) to memory */
- IDMAC_IC_8 = 8,
- IDMAC_IC_9 = 9,
- IDMAC_IC_10 = 10,
- IDMAC_IC_11 = 11,
- IDMAC_IC_12 = 12,
- IDMAC_IC_13 = 13,
- IDMAC_SDC_0 = 14, /* Background synchronous display data */
- IDMAC_SDC_1 = 15, /* Foreground data (overlay) */
- IDMAC_SDC_2 = 16,
- IDMAC_SDC_3 = 17,
- IDMAC_ADC_2 = 18,
- IDMAC_ADC_3 = 19,
- IDMAC_ADC_4 = 20,
- IDMAC_ADC_5 = 21,
- IDMAC_ADC_6 = 22,
- IDMAC_ADC_7 = 23,
- IDMAC_PF_0 = 24,
- IDMAC_PF_1 = 25,
- IDMAC_PF_2 = 26,
- IDMAC_PF_3 = 27,
- IDMAC_PF_4 = 28,
- IDMAC_PF_5 = 29,
- IDMAC_PF_6 = 30,
- IDMAC_PF_7 = 31,
-};
-
-/* More formats can be copied from the Linux driver if needed */
-enum pixel_fmt {
- /* 2 bytes */
- IPU_PIX_FMT_RGB565,
- IPU_PIX_FMT_RGB666,
- IPU_PIX_FMT_BGR666,
- /* 3 bytes */
- IPU_PIX_FMT_RGB24,
-};
-
-struct pixel_fmt_cfg {
- u32 b0;
- u32 b1;
- u32 b2;
- u32 acc;
-};
-
-static struct pixel_fmt_cfg fmt_cfg[] = {
- [IPU_PIX_FMT_RGB24] = {
- 0x1600AAAA, 0x00E05555, 0x00070000, 3,
- },
- [IPU_PIX_FMT_RGB666] = {
- 0x0005000F, 0x000B000F, 0x0011000F, 1,
- },
- [IPU_PIX_FMT_BGR666] = {
- 0x0011000F, 0x000B000F, 0x0005000F, 1,
- },
- [IPU_PIX_FMT_RGB565] = {
- 0x0004003F, 0x000A000F, 0x000F003F, 1,
- }
-};
-
-enum ipu_panel {
- IPU_PANEL_SHARP_TFT,
- IPU_PANEL_TFT,
-};
-
-/* IPU Common registers */
-/* IPU_CONF and its bits already defined in imx-regs.h */
-#define IPU_CHA_BUF0_RDY (0x04 + IPU_BASE)
-#define IPU_CHA_BUF1_RDY (0x08 + IPU_BASE)
-#define IPU_CHA_DB_MODE_SEL (0x0C + IPU_BASE)
-#define IPU_CHA_CUR_BUF (0x10 + IPU_BASE)
-#define IPU_FS_PROC_FLOW (0x14 + IPU_BASE)
-#define IPU_FS_DISP_FLOW (0x18 + IPU_BASE)
-#define IPU_TASKS_STAT (0x1C + IPU_BASE)
-#define IPU_IMA_ADDR (0x20 + IPU_BASE)
-#define IPU_IMA_DATA (0x24 + IPU_BASE)
-#define IPU_INT_CTRL_1 (0x28 + IPU_BASE)
-#define IPU_INT_CTRL_2 (0x2C + IPU_BASE)
-#define IPU_INT_CTRL_3 (0x30 + IPU_BASE)
-#define IPU_INT_CTRL_4 (0x34 + IPU_BASE)
-#define IPU_INT_CTRL_5 (0x38 + IPU_BASE)
-#define IPU_INT_STAT_1 (0x3C + IPU_BASE)
-#define IPU_INT_STAT_2 (0x40 + IPU_BASE)
-#define IPU_INT_STAT_3 (0x44 + IPU_BASE)
-#define IPU_INT_STAT_4 (0x48 + IPU_BASE)
-#define IPU_INT_STAT_5 (0x4C + IPU_BASE)
-#define IPU_BRK_CTRL_1 (0x50 + IPU_BASE)
-#define IPU_BRK_CTRL_2 (0x54 + IPU_BASE)
-#define IPU_BRK_STAT (0x58 + IPU_BASE)
-#define IPU_DIAGB_CTRL (0x5C + IPU_BASE)
-
-/* Image Converter Registers */
-#define IC_CONF (0x88 + IPU_BASE)
-#define IC_PRP_ENC_RSC (0x8C + IPU_BASE)
-#define IC_PRP_VF_RSC (0x90 + IPU_BASE)
-#define IC_PP_RSC (0x94 + IPU_BASE)
-#define IC_CMBP_1 (0x98 + IPU_BASE)
-#define IC_CMBP_2 (0x9C + IPU_BASE)
-#define PF_CONF (0xA0 + IPU_BASE)
-#define IDMAC_CONF (0xA4 + IPU_BASE)
-#define IDMAC_CHA_EN (0xA8 + IPU_BASE)
-#define IDMAC_CHA_PRI (0xAC + IPU_BASE)
-#define IDMAC_CHA_BUSY (0xB0 + IPU_BASE)
-
-/* Image Converter Register bits */
-#define IC_CONF_PRPENC_EN 0x00000001
-#define IC_CONF_PRPENC_CSC1 0x00000002
-#define IC_CONF_PRPENC_ROT_EN 0x00000004
-#define IC_CONF_PRPVF_EN 0x00000100
-#define IC_CONF_PRPVF_CSC1 0x00000200
-#define IC_CONF_PRPVF_CSC2 0x00000400
-#define IC_CONF_PRPVF_CMB 0x00000800
-#define IC_CONF_PRPVF_ROT_EN 0x00001000
-#define IC_CONF_PP_EN 0x00010000
-#define IC_CONF_PP_CSC1 0x00020000
-#define IC_CONF_PP_CSC2 0x00040000
-#define IC_CONF_PP_CMB 0x00080000
-#define IC_CONF_PP_ROT_EN 0x00100000
-#define IC_CONF_IC_GLB_LOC_A 0x10000000
-#define IC_CONF_KEY_COLOR_EN 0x20000000
-#define IC_CONF_RWS_EN 0x40000000
-#define IC_CONF_CSI_MEM_WR_EN 0x80000000
-
-/* SDC Registers */
-#define SDC_COM_CONF (0xB4 + IPU_BASE)
-#define SDC_GW_CTRL (0xB8 + IPU_BASE)
-#define SDC_FG_POS (0xBC + IPU_BASE)
-#define SDC_BG_POS (0xC0 + IPU_BASE)
-#define SDC_CUR_POS (0xC4 + IPU_BASE)
-#define SDC_PWM_CTRL (0xC8 + IPU_BASE)
-#define SDC_CUR_MAP (0xCC + IPU_BASE)
-#define SDC_HOR_CONF (0xD0 + IPU_BASE)
-#define SDC_VER_CONF (0xD4 + IPU_BASE)
-#define SDC_SHARP_CONF_1 (0xD8 + IPU_BASE)
-#define SDC_SHARP_CONF_2 (0xDC + IPU_BASE)
-
-/* Register bits */
-#define SDC_COM_TFT_COLOR 0x00000001UL
-#define SDC_COM_FG_EN 0x00000010UL
-#define SDC_COM_GWSEL 0x00000020UL
-#define SDC_COM_GLB_A 0x00000040UL
-#define SDC_COM_KEY_COLOR_G 0x00000080UL
-#define SDC_COM_BG_EN 0x00000200UL
-#define SDC_COM_SHARP 0x00001000UL
-
-#define SDC_V_SYNC_WIDTH_L 0x00000001UL
-
-/* Display Interface registers */
-#define DI_DISP_IF_CONF (0x0124 + IPU_BASE)
-#define DI_DISP_SIG_POL (0x0128 + IPU_BASE)
-#define DI_SER_DISP1_CONF (0x012C + IPU_BASE)
-#define DI_SER_DISP2_CONF (0x0130 + IPU_BASE)
-#define DI_HSP_CLK_PER (0x0134 + IPU_BASE)
-#define DI_DISP0_TIME_CONF_1 (0x0138 + IPU_BASE)
-#define DI_DISP0_TIME_CONF_2 (0x013C + IPU_BASE)
-#define DI_DISP0_TIME_CONF_3 (0x0140 + IPU_BASE)
-#define DI_DISP1_TIME_CONF_1 (0x0144 + IPU_BASE)
-#define DI_DISP1_TIME_CONF_2 (0x0148 + IPU_BASE)
-#define DI_DISP1_TIME_CONF_3 (0x014C + IPU_BASE)
-#define DI_DISP2_TIME_CONF_1 (0x0150 + IPU_BASE)
-#define DI_DISP2_TIME_CONF_2 (0x0154 + IPU_BASE)
-#define DI_DISP2_TIME_CONF_3 (0x0158 + IPU_BASE)
-#define DI_DISP3_TIME_CONF (0x015C + IPU_BASE)
-#define DI_DISP0_DB0_MAP (0x0160 + IPU_BASE)
-#define DI_DISP0_DB1_MAP (0x0164 + IPU_BASE)
-#define DI_DISP0_DB2_MAP (0x0168 + IPU_BASE)
-#define DI_DISP0_CB0_MAP (0x016C + IPU_BASE)
-#define DI_DISP0_CB1_MAP (0x0170 + IPU_BASE)
-#define DI_DISP0_CB2_MAP (0x0174 + IPU_BASE)
-#define DI_DISP1_DB0_MAP (0x0178 + IPU_BASE)
-#define DI_DISP1_DB1_MAP (0x017C + IPU_BASE)
-#define DI_DISP1_DB2_MAP (0x0180 + IPU_BASE)
-#define DI_DISP1_CB0_MAP (0x0184 + IPU_BASE)
-#define DI_DISP1_CB1_MAP (0x0188 + IPU_BASE)
-#define DI_DISP1_CB2_MAP (0x018C + IPU_BASE)
-#define DI_DISP2_DB0_MAP (0x0190 + IPU_BASE)
-#define DI_DISP2_DB1_MAP (0x0194 + IPU_BASE)
-#define DI_DISP2_DB2_MAP (0x0198 + IPU_BASE)
-#define DI_DISP2_CB0_MAP (0x019C + IPU_BASE)
-#define DI_DISP2_CB1_MAP (0x01A0 + IPU_BASE)
-#define DI_DISP2_CB2_MAP (0x01A4 + IPU_BASE)
-#define DI_DISP3_B0_MAP (0x01A8 + IPU_BASE)
-#define DI_DISP3_B1_MAP (0x01AC + IPU_BASE)
-#define DI_DISP3_B2_MAP (0x01B0 + IPU_BASE)
-#define DI_DISP_ACC_CC (0x01B4 + IPU_BASE)
-#define DI_DISP_LLA_CONF (0x01B8 + IPU_BASE)
-#define DI_DISP_LLA_DATA (0x01BC + IPU_BASE)
-
-/* DI_DISP_SIG_POL bits */
-#define DI_D3_VSYNC_POL (1 << 28)
-#define DI_D3_HSYNC_POL (1 << 27)
-#define DI_D3_DRDY_SHARP_POL (1 << 26)
-#define DI_D3_CLK_POL (1 << 25)
-#define DI_D3_DATA_POL (1 << 24)
-
-/* DI_DISP_IF_CONF bits */
-#define DI_D3_CLK_IDLE (1 << 26)
-#define DI_D3_CLK_SEL (1 << 25)
-#define DI_D3_DATAMSK (1 << 24)
-
-#define IOMUX_PADNUM_MASK 0x1ff
-#define IOMUX_GPIONUM_SHIFT 9
-#define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT)
-
-#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
-
-#define IOMUX_MODE_L(pin, mode) IOMUX_MODE(((pin) + 0xc) ^ 3, mode)
-
-struct chan_param_mem_planar {
- /* Word 0 */
- u32 xv:10;
- u32 yv:10;
- u32 xb:12;
-
- u32 yb:12;
- u32 res1:2;
- u32 nsb:1;
- u32 lnpb:6;
- u32 ubo_l:11;
-
- u32 ubo_h:15;
- u32 vbo_l:17;
-
- u32 vbo_h:9;
- u32 res2:3;
- u32 fw:12;
- u32 fh_l:8;
-
- u32 fh_h:4;
- u32 res3:28;
-
- /* Word 1 */
- u32 eba0;
-
- u32 eba1;
-
- u32 bpp:3;
- u32 sl:14;
- u32 pfs:3;
- u32 bam:3;
- u32 res4:2;
- u32 npb:6;
- u32 res5:1;
-
- u32 sat:2;
- u32 res6:30;
-} __attribute__ ((packed));
-
-struct chan_param_mem_interleaved {
- /* Word 0 */
- u32 xv:10;
- u32 yv:10;
- u32 xb:12;
-
- u32 yb:12;
- u32 sce:1;
- u32 res1:1;
- u32 nsb:1;
- u32 lnpb:6;
- u32 sx:10;
- u32 sy_l:1;
-
- u32 sy_h:9;
- u32 ns:10;
- u32 sm:10;
- u32 sdx_l:3;
-
- u32 sdx_h:2;
- u32 sdy:5;
- u32 sdrx:1;
- u32 sdry:1;
- u32 sdr1:1;
- u32 res2:2;
- u32 fw:12;
- u32 fh_l:8;
-
- u32 fh_h:4;
- u32 res3:28;
-
- /* Word 1 */
- u32 eba0;
-
- u32 eba1;
-
- u32 bpp:3;
- u32 sl:14;
- u32 pfs:3;
- u32 bam:3;
- u32 res4:2;
- u32 npb:6;
- u32 res5:1;
-
- u32 sat:2;
- u32 scc:1;
- u32 ofs0:5;
- u32 ofs1:5;
- u32 ofs2:5;
- u32 ofs3:5;
- u32 wid0:3;
- u32 wid1:3;
- u32 wid2:3;
-
- u32 wid3:3;
- u32 dec_sel:1;
- u32 res6:28;
-} __attribute__ ((packed));
-
-union chan_param_mem {
- struct chan_param_mem_planar pp;
- struct chan_param_mem_interleaved ip;
-};
-
-/* graphics setup */
-static GraphicDevice panel;
-static struct ctfb_res_modes *mode;
-static struct ctfb_res_modes var_mode;
-
-/*
- * sdc_init_panel() - initialize a synchronous LCD panel.
- * @width: width of panel in pixels.
- * @height: height of panel in pixels.
- * @di_setup: pixel format of the frame buffer
- * @di_panel: either SHARP or normal TFT
- * @return: 0 on success or negative error code on failure.
- */
-static int sdc_init_panel(u16 width, u16 height,
- enum pixel_fmt di_setup, enum ipu_panel di_panel)
-{
- u32 reg, div;
- uint32_t old_conf;
- int clock;
-
- debug("%s(width=%d, height=%d)\n", __func__, width, height);
-
- /* Init clocking, the IPU receives its clock from the hsp divder */
- clock = mxc_get_clock(MXC_IPU_CLK);
- if (clock < 0)
- return -EACCES;
-
- /* Init panel size and blanking periods */
- reg = width + mode->left_margin + mode->right_margin - 1;
- if (reg > 1023) {
- printf("mx3fb: Display width too large, coerced to 1023!");
- reg = 1023;
- }
- reg = ((mode->hsync_len - 1) << 26) | (reg << 16);
- writel(reg, SDC_HOR_CONF);
-
- reg = height + mode->upper_margin + mode->lower_margin - 1;
- if (reg > 1023) {
- printf("mx3fb: Display height too large, coerced to 1023!");
- reg = 1023;
- }
- reg = ((mode->vsync_len - 1) << 26) | SDC_V_SYNC_WIDTH_L | (reg << 16);
- writel(reg, SDC_VER_CONF);
-
- switch (di_panel) {
- case IPU_PANEL_SHARP_TFT:
- writel(0x00FD0102L, SDC_SHARP_CONF_1);
- writel(0x00F500F4L, SDC_SHARP_CONF_2);
- writel(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
- /* TODO: probably IF_CONF must be adapted (see below)! */
- break;
- case IPU_PANEL_TFT:
- writel(SDC_COM_TFT_COLOR, SDC_COM_CONF);
- break;
- default:
- return -EINVAL;
- }
-
- /*
- * Calculate divider: The fractional part is 4 bits so simply
- * multiple by 2^4 to get it.
- *
- * Opposed to the kernel driver mode->pixclock is the time of one
- * pixel in pico seconds, so:
- * pixel_clk = 1e12 / mode->pixclock
- * div = ipu_clk * 16 / pixel_clk
- * leads to:
- * div = ipu_clk * 16 / (1e12 / mode->pixclock)
- * or:
- * div = ipu_clk * 16 * mode->pixclock / 1e12
- *
- * To avoid integer overflows this is split into 2 shifts and
- * one divide with sufficient accuracy:
- * 16*1024*128*476837 = 0.9999996682e12
- */
- div = ((clock/1024) * (mode->pixclock/128)) / 476837;
- debug("hsp_clk is %d, div=%d\n", clock, div);
- /* coerce to not less than 4.0, not more than 255.9375 */
- if (div < 0x40)
- div = 0x40;
- else if (div > 0xFFF)
- div = 0xFFF;
- /* DISP3_IF_CLK_DOWN_WR is half the divider value and 2 less
- * fraction bits. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR
- * based on timing debug DISP3_IF_CLK_UP_WR is 0
- */
- writel((((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
-
- /* DI settings for display 3: clock idle (bit 26) during vsync */
- old_conf = readl(DI_DISP_IF_CONF) & 0x78FFFFFF;
- writel(old_conf | IF_CONF, DI_DISP_IF_CONF);
-
- /* only set display 3 polarity bits */
- old_conf = readl(DI_DISP_SIG_POL) & 0xE0FFFFFF;
- writel(old_conf | mode->sync, DI_DISP_SIG_POL);
-
- writel(fmt_cfg[di_setup].b0, DI_DISP3_B0_MAP);
- writel(fmt_cfg[di_setup].b1, DI_DISP3_B1_MAP);
- writel(fmt_cfg[di_setup].b2, DI_DISP3_B2_MAP);
- writel(readl(DI_DISP_ACC_CC) |
- ((fmt_cfg[di_setup].acc - 1) << 12), DI_DISP_ACC_CC);
-
- debug("DI_DISP_IF_CONF = 0x%08X\n", readl(DI_DISP_IF_CONF));
- debug("DI_DISP_SIG_POL = 0x%08X\n", readl(DI_DISP_SIG_POL));
- debug("DI_DISP3_TIME_CONF = 0x%08X\n", readl(DI_DISP3_TIME_CONF));
- debug("SDC_HOR_CONF = 0x%08X\n", readl(SDC_HOR_CONF));
- debug("SDC_VER_CONF = 0x%08X\n", readl(SDC_VER_CONF));
-
- return 0;
-}
-
-static void ipu_ch_param_set_size(union chan_param_mem *params,
- uint pixelfmt, uint16_t width,
- uint16_t height, uint16_t stride)
-{
- debug("%s(pixelfmt=%d, width=%d, height=%d, stride=%d)\n",
- __func__, pixelfmt, width, height, stride);
-
- params->pp.fw = width - 1;
- params->pp.fh_l = height - 1;
- params->pp.fh_h = (height - 1) >> 8;
- params->pp.sl = stride - 1;
-
- /* See above, for further formats see the Linux driver */
- switch (pixelfmt) {
- case GDF_16BIT_565RGB:
- params->ip.bpp = 2;
- params->ip.pfs = 4;
- params->ip.npb = 7;
- params->ip.sat = 2; /* SAT = 32-bit access */
- params->ip.ofs0 = 0; /* Red bit offset */
- params->ip.ofs1 = 5; /* Green bit offset */
- params->ip.ofs2 = 11; /* Blue bit offset */
- params->ip.ofs3 = 16; /* Alpha bit offset */
- params->ip.wid0 = 4; /* Red bit width - 1 */
- params->ip.wid1 = 5; /* Green bit width - 1 */
- params->ip.wid2 = 4; /* Blue bit width - 1 */
- break;
- case GDF_32BIT_X888RGB:
- params->ip.bpp = 1; /* 24 BPP & RGB PFS */
- params->ip.pfs = 4;
- params->ip.npb = 7;
- params->ip.sat = 2; /* SAT = 32-bit access */
- params->ip.ofs0 = 16; /* Red bit offset */
- params->ip.ofs1 = 8; /* Green bit offset */
- params->ip.ofs2 = 0; /* Blue bit offset */
- params->ip.ofs3 = 24; /* Alpha bit offset */
- params->ip.wid0 = 7; /* Red bit width - 1 */
- params->ip.wid1 = 7; /* Green bit width - 1 */
- params->ip.wid2 = 7; /* Blue bit width - 1 */
- break;
- default:
- printf("mx3fb: Pixel format not supported!\n");
- break;
- }
-
- params->pp.nsb = 1;
-}
-
-static void ipu_ch_param_set_buffer(union chan_param_mem *params,
- void *buf0, void *buf1)
-{
- params->pp.eba0 = (u32)buf0;
- params->pp.eba1 = (u32)buf1;
-}
-
-static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
- uint32_t num_words)
-{
- for (; num_words > 0; num_words--) {
- writel(addr, IPU_IMA_ADDR);
- writel(*data++, IPU_IMA_DATA);
- addr++;
- if ((addr & 0x7) == 5) {
- addr &= ~0x7; /* set to word 0 */
- addr += 8; /* increment to next row */
- }
- }
-}
-
-static uint32_t dma_param_addr(enum ipu_channel channel)
-{
- /* Channel Parameter Memory */
- return 0x10000 | (channel << 4);
-}
-
-static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem)
-{
- union chan_param_mem params = {};
- uint32_t reg;
- uint32_t stride_bytes;
-
- stride_bytes = (panel.plnSizeX * panel.gdfBytesPP + 3) & ~3;
-
- debug("%s(channel=%d, fbmem=%p)\n", __func__, channel, fbmem);
-
- /* Build parameter memory data for DMA channel */
- ipu_ch_param_set_size(¶ms, panel.gdfIndex,
- panel.plnSizeX, panel.plnSizeY, stride_bytes);
- ipu_ch_param_set_buffer(¶ms, fbmem, NULL);
- params.pp.bam = 0;
- /* Some channels (rotation) have restriction on burst length */
-
- switch (channel) {
- case IDMAC_SDC_0:
- /* In original code only IPU_PIX_FMT_RGB565 was setting burst */
- params.pp.npb = 16 - 1;
- break;
- default:
- break;
- }
-
- ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)¶ms, 10);
-
- /* Disable double-buffering */
- reg = readl(IPU_CHA_DB_MODE_SEL);
- reg &= ~(1UL << channel);
- writel(reg, IPU_CHA_DB_MODE_SEL);
-}
-
-static void ipu_channel_set_priority(enum ipu_channel channel,
- int prio)
-{
- u32 reg = readl(IDMAC_CHA_PRI);
-
- if (prio)
- reg |= 1UL << channel;
- else
- reg &= ~(1UL << channel);
-
- writel(reg, IDMAC_CHA_PRI);
-}
-
-/*
- * ipu_enable_channel() - enable an IPU channel.
- * @channel: channel ID.
- * @return: 0 on success or negative error code on failure.
- */
-static int ipu_enable_channel(enum ipu_channel channel)
-{
- uint32_t reg;
-
- /* Reset to buffer 0 */
- writel(1UL << channel, IPU_CHA_CUR_BUF);
-
- switch (channel) {
- case IDMAC_SDC_0:
- ipu_channel_set_priority(channel, 1);
- break;
- default:
- break;
- }
-
- reg = readl(IDMAC_CHA_EN);
- writel(reg | (1UL << channel), IDMAC_CHA_EN);
-
- return 0;
-}
-
-static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf)
-{
- uint32_t reg;
-
- reg = readl(IPU_CHA_BUF0_RDY);
- if (reg & (1UL << channel))
- return -EACCES;
-
- /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
- writel(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR);
- writel((u32)buf, IPU_IMA_DATA);
-
- return 0;
-}
-
-static int idmac_tx_submit(enum ipu_channel channel, void *buf)
-{
- int ret;
-
- ipu_init_channel_buffer(channel, buf);
-
-
- /* ipu_idmac.c::ipu_submit_channel_buffers() */
- ret = ipu_update_channel_buffer(channel, buf);
- if (ret < 0)
- return ret;
-
- /* ipu_idmac.c::ipu_select_buffer() */
- /* Mark buffer 0 as ready. */
- writel(1UL << channel, IPU_CHA_BUF0_RDY);
-
-
- ret = ipu_enable_channel(channel);
- return ret;
-}
-
-static void sdc_enable_channel(void *fbmem)
-{
- int ret;
- u32 reg;
-
- ret = idmac_tx_submit(IDMAC_SDC_0, fbmem);
-
- /* mx3fb.c::sdc_fb_init() */
- if (ret >= 0) {
- reg = readl(SDC_COM_CONF);
- writel(reg | SDC_COM_BG_EN, SDC_COM_CONF);
- }
-
- /*
- * Attention! Without this msleep the channel keeps generating
- * interrupts. Next sdc_set_brightness() is going to be called
- * from mx3fb_blank().
- */
- udelay(2000);
-}
-
-/*
- * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
- * @return: 0 on success or negative error code on failure.
- * TODO: currently only 666 and TFT as DI setup supported
- */
-static int mx3fb_set_par(void)
-{
- int ret;
-
- ret = sdc_init_panel(panel.plnSizeX, panel.plnSizeY,
- IPU_PIX_FMT_RGB666, IPU_PANEL_TFT);
- if (ret < 0)
- return ret;
-
- writel((mode->left_margin << 16) | mode->upper_margin, SDC_BG_POS);
-
- return 0;
-}
-
-static void ll_disp3_enable(void *base)
-{
- u32 reg;
-
- debug("%s(base=0x%x)\n", __func__, (u32) base);
- /* pcm037.c::mxc_board_init() */
-
- /* Display Interface #3 */
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD0, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD1, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD2, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD3, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD4, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD5, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD6, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD7, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD8, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD9, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD10, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD11, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD12, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD13, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD14, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD15, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD16, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD17, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_VSYNC3, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_HSYNC, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_FPSHIFT, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_DRDY0, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_REV, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_CONTRAST, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_SPL, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_CLS, MUX_CTL_FUNC));
-
-
- /* ipu_idmac.c::ipu_probe() */
-
- /* Start the clock */
- __REG(CCM_CGR1) = __REG(CCM_CGR1) | (3 << 22);
-
-
- /* ipu_idmac.c::ipu_idmac_init() */
-
- /* Service request counter to maximum - shouldn't be needed */
- writel(0x00000070, IDMAC_CONF);
-
-
- /* ipu_idmac.c::ipu_init_channel() */
-
- /* Enable IPU sub modules */
- reg = readl(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
- writel(reg, IPU_CONF);
-
-
- /* mx3fb.c::init_fb_chan() */
-
- /* set Display Interface clock period */
- writel(0x00100010L, DI_HSP_CLK_PER);
- /* Might need to trigger HSP clock change - see 44.3.3.8.5 */
-
-
- /* mx3fb.c::sdc_set_brightness() */
-
- /* This might be board-specific */
- writel(0x03000000UL | 255 << 16, SDC_PWM_CTRL);
-
-
- /* mx3fb.c::sdc_set_global_alpha() */
-
- /* Use global - not per-pixel - Alpha-blending */
- reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL;
- writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL);
-
- reg = readl(SDC_COM_CONF);
- writel(reg | SDC_COM_GLB_A, SDC_COM_CONF);
-
-
- /* mx3fb.c::sdc_set_color_key() */
-
- /* Disable colour-keying for background */
- reg = readl(SDC_COM_CONF) &
- ~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G);
- writel(reg, SDC_COM_CONF);
-
-
- mx3fb_set_par();
-
- sdc_enable_channel(base);
-
- /*
- * Linux driver calls sdc_set_brightness() here again,
- * once is enough for us
- */
- debug("%s() done\n", __func__);
-}
-
-/* ------------------------ public part ------------------- */
-ulong calc_fbsize(void)
-{
- return panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP;
-}
-
-/*
- * The current implementation is only tested for GDF_16BIT_565RGB!
- * It was switched from the original CONFIG_LCD setup to CONFIG_VIDEO,
- * because the lcd code seemed loaded with color table stuff, that
- * does not relate to most modern TFTs. cfb_console.c looks more
- * straight forward.
- * This is the environment setting for the original setup
- * "unknown=video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,le:9,ri:17,
- * up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0"
- * "videomode=unknown"
- *
- * Settings for VBEST VGG322403 display:
- * "videomode=video=ctfb:x:320,y:240,depth:16,mode:0,pclk:156000,
- * "le:20,ri:68,up:7,lo:29,hs:30,vs:3,sync:100663296,vmode:0"
- *
- * Settings for COM57H5M10XRC display:
- * "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000,
- * "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296,vmode:0"
- */
-void *video_hw_init(void)
-{
- char *penv;
- u32 memsize;
- unsigned long t1, hsynch, vsynch;
- int bits_per_pixel, i, tmp, videomode;
-
- tmp = 0;
-
- puts("Video: ");
-
- videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE;
- /* get video mode via environment */
- penv = env_get("videomode");
- if (penv) {
- /* decide if it is a string */
- if (penv[0] <= '9') {
- videomode = (int)hextoul(penv, NULL);
- tmp = 1;
- }
- } else {
- tmp = 1;
- }
- if (tmp) {
- /* parameter are vesa modes */
- /* search params */
- for (i = 0; i < VESA_MODES_COUNT; i++) {
- if (vesa_modes[i].vesanr == videomode)
- break;
- }
- if (i == VESA_MODES_COUNT) {
- printf("No VESA Mode found, switching to mode 0x%x ",
- CONFIG_SYS_DEFAULT_VIDEO_MODE);
- i = 0;
- }
- mode = (struct ctfb_res_modes *)
- &res_mode_init[vesa_modes[i].resindex];
- bits_per_pixel = vesa_modes[i].bits_per_pixel;
- } else {
- mode = (struct ctfb_res_modes *) &var_mode;
- bits_per_pixel = video_get_params(mode, penv);
- }
-
- /* calculate hsynch and vsynch freq (info only) */
- t1 = (mode->left_margin + mode->xres +
- mode->right_margin + mode->hsync_len) / 8;
- t1 *= 8;
- t1 *= mode->pixclock;
- t1 /= 1000;
- hsynch = 1000000000L / t1;
- t1 *= (mode->upper_margin + mode->yres +
- mode->lower_margin + mode->vsync_len);
- t1 /= 1000;
- vsynch = 1000000000L / t1;
-
- /* fill in Graphic device struct */
- sprintf(panel.modeIdent, "%dx%dx%d %ldkHz %ldHz",
- mode->xres, mode->yres,
- bits_per_pixel, (hsynch / 1000), (vsynch / 1000));
- printf("%s\n", panel.modeIdent);
- panel.winSizeX = mode->xres;
- panel.winSizeY = mode->yres;
- panel.plnSizeX = mode->xres;
- panel.plnSizeY = mode->yres;
-
- switch (bits_per_pixel) {
- case 24:
- panel.gdfBytesPP = 4;
- panel.gdfIndex = GDF_32BIT_X888RGB;
- break;
- case 16:
- panel.gdfBytesPP = 2;
- panel.gdfIndex = GDF_16BIT_565RGB;
- break;
- default:
- panel.gdfBytesPP = 1;
- panel.gdfIndex = GDF__8BIT_INDEX;
- break;
- }
-
- /* set up Hardware */
- memsize = calc_fbsize();
-
- debug("%s() allocating %d bytes\n", __func__, memsize);
-
- /* fill in missing Graphic device struct */
- panel.frameAdrs = (u32) malloc(memsize);
- if (panel.frameAdrs == 0) {
- printf("%s() malloc(%d) failed\n", __func__, memsize);
- return 0;
- }
- panel.memSize = memsize;
-
- ll_disp3_enable((void *) panel.frameAdrs);
- memset((void *) panel.frameAdrs, 0, memsize);
-
- debug("%s() done, framebuffer at 0x%x, size=%d cleared\n",
- __func__, panel.frameAdrs, memsize);
-
- return (void *) &panel;
-}
if (strcmp(format, "r5g6b5") == 0) {
uc_priv->bpix = VIDEO_BPP16;
- } else if (strcmp(format, "a8b8g8r8") == 0) {
+ } else if (strcmp(format, "a8b8g8r8") == 0 ||
+ strcmp(format, "x8b8g8r8") == 0) {
uc_priv->bpix = VIDEO_BPP32;
+ uc_priv->format = VIDEO_X8B8G8R8;
+ } else if (strcmp(format, "a8r8g8b8") == 0 ||
+ strcmp(format, "x8r8g8b8") == 0) {
+ uc_priv->bpix = VIDEO_BPP32;
+ uc_priv->format = VIDEO_X8R8G8B8;
+ } else if (strcmp(format, "a2r10g10b10") == 0 ||
+ strcmp(format, "x2r10g10b10") == 0) {
+ uc_priv->bpix = VIDEO_BPP32;
+ uc_priv->format = VIDEO_X2R10G10B10;
} else {
printf("%s: invalid format: %s\n", __func__, format);
return -EINVAL;
#include <asm/arch/clock.h>
#include <asm/arch/display.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/lcdc.h>
#include <asm/arch/pwm.h>
#include <asm/arch/tve.h>
static int sunxi_ssd2828_init(const struct ctfb_res_modes *mode)
{
struct ssd2828_config cfg = {
- .csx_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS),
- .sck_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK),
- .sdi_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI),
- .sdo_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO),
- .reset_pin = name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET),
+ .csx_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS),
+ .sck_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK),
+ .sdi_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI),
+ .sdo_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO),
+ .reset_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET),
.ssd2828_tx_clk_khz = CONFIG_VIDEO_LCD_SSD2828_TX_CLK * 1000,
.ssd2828_color_depth = 24,
#ifdef CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
}
#endif /* CONFIG_VIDEO_LCD_SSD2828 */
+#ifdef CONFIG_VIDEO_LCD_PANEL_I2C
+static void sunxi_panel_i2c_init(struct sunxi_display_priv *sunxi_display)
+{
+ const char *name = CONFIG_VIDEO_LCD_PANEL_I2C_NAME;
+ struct udevice *i2c_bus;
+ int ret;
+
+ ret = uclass_get_device_by_name(UCLASS_I2C, name, &i2c_bus);
+ if (ret)
+ return;
+
+ if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) {
+ /*
+ * The anx9804 needs 1.8V from eldo3, we do this here
+ * and not via CONFIG_AXP_ELDO3_VOLT from board_init()
+ * to avoid turning this on when using hdmi output.
+ */
+ axp_set_eldo(3, 1800);
+ anx9804_init(i2c_bus, 4,
+ ANX9804_DATA_RATE_1620M,
+ sunxi_display->depth);
+ }
+ if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) {
+ struct udevice *chip;
+
+ ret = i2c_get_chip(i2c_bus, 0x5c, 1, &chip);
+ if (ret)
+ return;
+
+ dm_i2c_reg_write(chip, 0x04, 0x42); /* Turn on the LCD */
+ }
+}
+#else
+static void sunxi_panel_i2c_init(struct sunxi_display_priv *sunxi_display) {}
+#endif
+
static void sunxi_engines_init(void)
{
sunxi_composer_init();
break;
case sunxi_monitor_lcd:
sunxi_lcdc_panel_enable();
- if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) {
- /*
- * The anx9804 needs 1.8V from eldo3, we do this here
- * and not via CONFIG_AXP_ELDO3_VOLT from board_init()
- * to avoid turning this on when using hdmi output.
- */
- axp_set_eldo(3, 1800);
- anx9804_init(CONFIG_VIDEO_LCD_I2C_BUS, 4,
- ANX9804_DATA_RATE_1620M,
- sunxi_display->depth);
- }
if (IS_ENABLED(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM)) {
mdelay(50); /* Wait for lcd controller power on */
hitachi_tx18d42vm_init();
}
- if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) {
- unsigned int orig_i2c_bus = i2c_get_bus_num();
- i2c_set_bus_num(CONFIG_VIDEO_LCD_I2C_BUS);
- i2c_reg_write(0x5c, 0x04, 0x42); /* Turn on the LCD */
- i2c_set_bus_num(orig_i2c_bus);
- }
+ if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_I2C))
+ sunxi_panel_i2c_init(sunxi_display);
sunxi_composer_mode_set(mode, address, monitor);
sunxi_lcdc_tcon0_mode_set(sunxi_display, mode, false);
sunxi_composer_enable();
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/lcdc.h>
-#include <asm/arch/gpio.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
break;
case VIDEO_BPP32:
if (CONFIG_IS_ENABLED(VIDEO_BPP32)) {
- return (colors[idx].r << 16) |
- (colors[idx].g << 8) |
- (colors[idx].b << 0);
+ if (priv->format == VIDEO_X2R10G10B10)
+ return (colors[idx].r << 22) |
+ (colors[idx].g << 12) |
+ (colors[idx].b << 2);
+ else
+ return (colors[idx].r << 16) |
+ (colors[idx].g << 8) |
+ (colors[idx].b << 0);
}
break;
default:
config SUPPORT_OF_CONTROL
bool
-config DTC
- bool
-
config PYLIBFDT
bool
config BINMAN_STANDALONE_FDT
bool
depends on BINMAN
- default y if OF_BOARD || OF_PRIOR_STAGE
+ default y if OF_BOARD
help
This option tells U-Boot build system that a standalone device tree
source is explicitly required when using binman to package U-Boot.
directory for a specific board. Such device tree sources are built for
OF_SEPARATE or OF_EMBED. However for a scenario like the board device
tree blob is not provided in the U-Boot build tree, but fed to U-Boot
- in the runtime, e.g.: in the OF_PRIOR_STAGE case that it is passed by
+ in the runtime, e.g.: in the OF_BOARD case that it is passed by
a prior stage bootloader. For such scenario, a standalone device tree
blob containing binman node to describe how to package U-Boot should
be provided explicitly.
config OF_CONTROL
bool "Run-time configuration via Device Tree"
- select DTC
select OF_LIBFDT if !OF_PLATDATA
select OF_REAL if !OF_PLATDATA
help
Boards in the mainline U-Boot tree should not use it.
config OF_BOARD
- bool "Provided by the board at runtime"
+ bool "Provided by the board (e.g a previous loader) at runtime"
depends on !SANDBOX
help
If this option is enabled, the device tree will be provided by
This is only useful for Sandbox. Use the -d flag to U-Boot to
specify the file to read.
-config OF_PRIOR_STAGE
- bool "Prior stage bootloader DTB for DT control"
- help
- If this option is enabled, the device tree used for DT
- control will be read from a device tree binary, at a memory
- location passed to U-Boot by the prior stage bootloader.
-
endchoice
config DEFAULT_DEVICE_TREE
*/
#include "btrfs.h"
+#include <abuf.h>
#include <log.h>
#include <malloc.h>
#include <linux/lzo.h>
static u32 decompress_zstd(const u8 *cbuf, u32 clen, u8 *dbuf, u32 dlen)
{
- ZSTD_DStream *dstream;
- ZSTD_inBuffer in_buf;
- ZSTD_outBuffer out_buf;
- void *workspace;
- size_t wsize;
- u32 res = -1;
-
- wsize = ZSTD_DStreamWorkspaceBound(ZSTD_BTRFS_MAX_INPUT);
- workspace = malloc(wsize);
- if (!workspace) {
- debug("%s: cannot allocate workspace of size %zu\n", __func__,
- wsize);
- return -1;
- }
-
- dstream = ZSTD_initDStream(ZSTD_BTRFS_MAX_INPUT, workspace, wsize);
- if (!dstream) {
- printf("%s: ZSTD_initDStream failed\n", __func__);
- goto err_free;
- }
+ struct abuf in, out;
- in_buf.src = cbuf;
- in_buf.pos = 0;
- in_buf.size = clen;
+ abuf_init_set(&in, (u8 *)cbuf, clen);
+ abuf_init_set(&out, dbuf, dlen);
- out_buf.dst = dbuf;
- out_buf.pos = 0;
- out_buf.size = dlen;
-
- while (1) {
- size_t ret;
-
- ret = ZSTD_decompressStream(dstream, &out_buf, &in_buf);
- if (ZSTD_isError(ret)) {
- printf("%s: ZSTD_decompressStream error %d\n", __func__,
- ZSTD_getErrorCode(ret));
- goto err_free;
- }
-
- if (in_buf.pos >= clen || !ret)
- break;
- }
-
- res = out_buf.pos;
-
-err_free:
- free(workspace);
- return res;
+ return zstd_decompress(&in, &out);
}
u32 btrfs_decompress(u8 type, const char *c, u32 clen, char *d, u32 dlen)
buffer += mydata->sect_size;
size -= mydata->sect_size;
}
- } else {
- __u32 idx;
-
- idx = size / mydata->sect_size;
- if (idx == 0)
- ret = 0;
- else
- ret = disk_read(startsect, idx, buffer);
- if (ret != idx) {
+ } else if (size >= mydata->sect_size) {
+ __u32 bytes_read;
+ __u32 sect_count = size / mydata->sect_size;
+
+ ret = disk_read(startsect, sect_count, buffer);
+ if (ret != sect_count) {
debug("Error reading data (got %d)\n", ret);
return -1;
}
- startsect += idx;
- idx *= mydata->sect_size;
- buffer += idx;
- size -= idx;
+ bytes_read = sect_count * mydata->sect_size;
+ startsect += sect_count;
+ buffer += bytes_read;
+ size -= bytes_read;
}
if (size) {
ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size);
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Handles a buffer that can be allocated and freed
+ *
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __ABUF_H
+#define __ABUF_H
+
+#include <linux/types.h>
+
+/**
+ * struct abuf - buffer that can be allocated and freed
+ *
+ * This is useful for a block of data which may be allocated with malloc(), or
+ * not, so that it needs to be freed correctly when finished with.
+ *
+ * For now it has a very simple purpose.
+ *
+ * Using memset() to zero all fields is guaranteed to be equivalent to
+ * abuf_init().
+ *
+ * @data: Pointer to data
+ * @size: Size of data in bytes
+ * @alloced: true if allocated with malloc(), so must be freed after use
+ */
+struct abuf {
+ void *data;
+ size_t size;
+ bool alloced;
+};
+
+static inline void *abuf_data(const struct abuf *abuf)
+{
+ return abuf->data;
+}
+
+static inline size_t abuf_size(const struct abuf *abuf)
+{
+ return abuf->size;
+}
+
+/**
+ * abuf_set() - set the (unallocated) data in a buffer
+ *
+ * This simply makes the abuf point to the supplied data, which must be live
+ * for the lifetime of the abuf. It is not alloced.
+ *
+ * Any existing data in the abuf is freed and the alloced member is set to
+ * false.
+ *
+ * @abuf: abuf to adjust
+ * @data: New contents of abuf
+ * @size: New size of abuf
+ */
+void abuf_set(struct abuf *abuf, void *data, size_t size);
+
+/**
+ * abuf_map_sysmem() - calls map_sysmem() to set up an abuf
+ *
+ * This is equivalent to abuf_set(abuf, map_sysmem(addr, size), size)
+ *
+ * Any existing data in the abuf is freed and the alloced member is set to
+ * false.
+ *
+ * @abuf: abuf to adjust
+ * @addr: Address to set the abuf to
+ * @size: New size of abuf
+ */
+void abuf_map_sysmem(struct abuf *abuf, ulong addr, size_t size);
+
+/**
+ * abuf_realloc() - Change the size of a buffer
+ *
+ * This uses realloc() to change the size of the buffer, with the same semantics
+ * as that function. If the abuf is not currently alloced, then it will alloc
+ * it if the size needs to increase (i.e. set the alloced member to true)
+ *
+ * @abuf: abuf to adjust
+ * @new_size: new size in bytes.
+ * if 0, the abuf is freed
+ * if greater than the current size, the abuf is extended and the new
+ * space is not inited. The alloced member is set to true
+ * if less than the current size, the abuf is contracted and the data at
+ * the end is lost. If @new_size is 0, this sets the alloced member to
+ * false
+ * @return true if OK, false if out of memory
+ */
+bool abuf_realloc(struct abuf *abuf, size_t new_size);
+
+/**
+ * abuf_uninit_move() - Return the allocated contents and uninit the abuf
+ *
+ * This returns the abuf data to the caller, allocating it if necessary, so that
+ * the caller receives data that it can be sure will hang around. The caller is
+ * responsible for freeing the data.
+ *
+ * If the abuf has allocated data, it is returned. If the abuf has data but it
+ * is not allocated, then it is first allocated, then returned.
+ *
+ * If the abuf size is 0, this returns NULL
+ *
+ * The abuf is uninited as part of this, except if the allocation fails, in
+ * which NULL is returned and the abuf remains untouched.
+ *
+ * The abuf must be inited before this can be called.
+ *
+ * @abuf: abuf to uninit
+ * @sizep: if non-NULL, returns the size of the returned data
+ * @return data contents, allocated with malloc(), or NULL if the data could not
+ * be allocated, or the data size is 0
+ */
+void *abuf_uninit_move(struct abuf *abuf, size_t *sizep);
+
+/**
+ * abuf_init_move() - Make abuf take over the management of an allocated region
+ *
+ * After this, @data must not be used. All access must be via the abuf.
+ *
+ * @abuf: abuf to init
+ * @data: Existing allocated buffer to place in the abuf
+ * @size: Size of allocated buffer
+ */
+void abuf_init_move(struct abuf *abuf, void *data, size_t size);
+
+/**
+ * abuf_init_set() - Set up a new abuf
+ *
+ * Inits a new abuf and sets up its (unallocated) data
+ *
+ * @abuf: abuf to set up
+ * @data: New contents of abuf
+ * @size: New size of abuf
+ */
+void abuf_init_set(struct abuf *abuf, void *data, size_t size);
+
+/**
+ * abuf_uninit() - Free any memory used by an abuf
+ *
+ * The buffer must be inited before this can be called.
+ *
+ * @abuf: abuf to uninit
+ */
+void abuf_uninit(struct abuf *abuf);
+
+/**
+ * abuf_init() - Set up a new abuf
+ *
+ * This initially has no data and alloced is set to false. This is equivalent to
+ * setting all fields to 0, e.g. with memset(), so callers can do that instead
+ * if desired.
+ *
+ * @abuf: abuf to set up
+ */
+void abuf_init(struct abuf *abuf);
+
+#endif
*/
#ifndef _AXP_PMIC_H_
+#include <stdbool.h>
+
#ifdef CONFIG_AXP152_POWER
#include <axp152.h>
#endif
#include <axp818.h>
#endif
+#define AXP_PMIC_MODE_REG 0x3e
+#define AXP_PMIC_MODE_I2C 0x00
+#define AXP_PMIC_MODE_P2WI 0x3e
+#define AXP_PMIC_MODE_RSB 0x7c
+
+#define AXP_PMIC_PRI_DEVICE_ADDR 0x3a3
+#define AXP_PMIC_PRI_RUNTIME_ADDR 0x2d
+#define AXP_PMIC_SEC_DEVICE_ADDR 0x745
+#define AXP_PMIC_SEC_RUNTIME_ADDR 0x3a
+
int axp_set_dcdc1(unsigned int mvolt);
int axp_set_dcdc2(unsigned int mvolt);
int axp_set_dcdc3(unsigned int mvolt);
* Author: Jagan Teki <jagan@amarulasolutions.com>
*/
-#ifndef _ASM_ARCH_CCU_H
-#define _ASM_ARCH_CCU_H
+#ifndef _CLK_SUNXI_H
+#define _CLK_SUNXI_H
-#ifndef __ASSEMBLY__
#include <linux/bitops.h>
-#endif
/**
* enum ccu_flags - ccu clock/reset flags
*/
int sunxi_reset_bind(struct udevice *dev, ulong count);
-#endif /* _ASM_ARCH_CCU_H */
+#endif /* _CLK_SUNXI_H */
typedef unsigned int uint;
typedef unsigned long ulong;
+/* Define these on the host so we can build some target code */
+typedef __u32 u32;
+
#define uswap_16(x) \
((((x) & 0xff00) >> 8) | \
(((x) & 0x00ff) << 8))
#define MEM_SUPPORT_64BIT_DATA 0
#endif
-static inline bool host_build(void) {
+/**
+ * tools_build() - check if we are building host tools
+ *
+ * @return true if building for the host, false if for a target
+ */
+static inline bool tools_build(void)
+{
#ifdef USE_HOSTCC
return true;
#else
"fi\0" \
\
"scsi_boot=" \
+ BOOTENV_RUN_PCI_ENUM \
BOOTENV_RUN_SCSI_INIT \
BOOTENV_SHARED_BLKDEV_BODY(scsi)
#define BOOTENV_DEV_SCSI BOOTENV_DEV_BLKDEV
#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+/* this must be included AFTER the definition of CONFIG COMMANDS (if any) */
#define CONFIG_BOOTFILE "u-boot.bin"
#ifdef CONFIG_MCFFEC
# define CONFIG_IPADDR 192.162.1.2
/* Serial Port */
#define CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else */
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
#endif /* CONFIG_NAND_FSL_ELBC */
#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
#define CONFIG_HWCONFIG
/* Bootcount using the RTC block */
#define CONFIG_SYS_BOOTCOUNT_BE
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER)
-/* Remove other SPL modes. */
-/* disable host part of MUSB in SPL */
-#undef CONFIG_MUSB_HOST
-/* disable EFI partitions and partition UUID support */
-#endif
-
/* Network. */
#endif /* ! __CONFIG_AM335X_SL50_H */
* U-Boot into it.
*/
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
#define CONFIG_ENV_MIN_ENTRIES 128
/* Environment in MMC */
/* USB Device Firmware Update support */
#define DFU_DEFAULT_POLL_TIMEOUT 300
-#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
-#define CONFIG_VIDEO_MXS
+#if defined(CONFIG_DM_VIDEO)
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_USBD_HS
-#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
-#define CONFIG_VIDEO_MXS
+#if defined(CONFIG_DM_VIDEO)
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#endif
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
/* Environment in SPI NOR flash */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
#endif /* CONFIG_NAND_FSL_ELBC */
#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_HWCONFIG
#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) /* 64 MB */
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
/* Environment in SPI NOR flash */
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
/* Environment in SPI NOR flash */
* High Level Configuration Options (easy to change)
*/
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
/* Environment in SPI NOR flash */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
/* Environment in SPI NOR flash */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
/* Environment in SPI NOR flash */
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
/* Environment in SPI NOR flash */
/* NAND */
/* USB Configs */
#ifdef CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
#define CONFIG_SYS_MAX_FLASH_SECT 512
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */
-/* #define CONFIG_INIT_IGNORE_ERROR */
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BASE (0x08000000)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_PCI_SCAN_SHOW
#endif
-/* USB/EHCI/XHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
* U-Boot into it.
*/
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
#define CONFIG_ENV_MIN_ENTRIES 128
/* Environment in MMC */
DMAMEM_SZ_ALL)
#ifdef CONFIG_DM_VIDEO
-#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
#define CONFIG_SYS_BOOTM_LEN SZ_64M
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for JetHome devices
+ * Copyright (C) 2021 Vyacheslav Bocharov
+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
+ */
+
+#ifndef __JETHUB_CONFIG_H
+#define __JETHUB_CONFIG_H
+
+#if defined(CONFIG_MESON_AXG)
+#define BOOTENV_DEV_RESCUE(devtypeu, devtypel, instance) \
+ "bootcmd_rescue=" \
+ "if gpio input 10; then " \
+ "run bootcmd_usb0;" \
+ "fi;\0"
+#else
+#define BOOTENV_DEV_RESCUE(devtypeu, devtypel, instance) \
+ "bootcmd_rescue=" \
+ "if test \"${userbutton}\" = \"true\"; then " \
+ "run bootcmd_mmc0; " \
+ "fi;\0"
+#endif
+
+#define BOOTENV_DEV_NAME_RESCUE(devtypeu, devtypel, instance) \
+ "rescue "
+
+#ifndef BOOT_TARGET_DEVICES
+#define BOOT_TARGET_DEVICES(func) \
+ func(RESCUE, rescue, na) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ BOOT_TARGET_DEVICES_USB(func) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+#endif
+
+#include <configs/meson64.h>
+
+#endif /* __JETHUB_CONFIG_H */
/* USB Configs */
#ifdef CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
#define BOOT_TARGET_NVME(func)
#endif
+#ifdef CONFIG_CMD_SCSI
+ #define BOOT_TARGET_SCSI(func) func(SCSI, scsi, 0)
+#else
+ #define BOOT_TARGET_SCSI(func)
+#endif
+
#ifndef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
func(ROMUSB, romusb, na) \
func(MMC, mmc, 2) \
BOOT_TARGET_DEVICES_USB(func) \
BOOT_TARGET_NVME(func) \
+ BOOT_TARGET_SCSI(func) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
#endif
#endif
/* Framebuffer support */
-#ifdef CONFIG_VIDEO
+#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
#endif
#endif
/* Framebuffer support */
-#ifdef CONFIG_VIDEO
+#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
#endif
#define CONFIG_SYS_FSL_CLK
/* USB Configs */
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_USB_ETHER_MCS7830
-#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#endif
#ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_MXS
+#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR
#ifndef CONFIG_SPL_BUILD
#if defined(CONFIG_DM_VIDEO)
-#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#define CONFIG_USBD_HS
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_MXS
+#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#endif
#endif
#endif
-/* LCD */
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_MXS
-#endif
-
/* NAND */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SPI_HALF_DUPLEX
#endif
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI_MXS
-#define CONFIG_EHCI_IS_TDI
-#endif
-
#endif /* __CONFIGS_MXS_H__ */
#endif /* CONFIG_CMD_NET */
/*
- * USB/EHCI
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
-#define CONFIG_EHCI_IS_TDI
-#endif /* CONFIG_CMD_USB */
-
-/*
* File system
*/
#define CONFIG_JFFS2_NAND
#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_VIDEO_MXS
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#endif
#endif
*/
#define CONFIG_BOARD_SIZE_LIMIT 715776
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_MXS
+#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
#ifdef CONFIG_DM_VIDEO
-#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#endif
AT91_WDT_MR_WDDIS | \
AT91_WDT_MR_WDD(0xfff))
-#define CONFIG_USER_LOWLEVEL_INIT 1
-
/*
* Hardware drivers
*/
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_USB_ETHER_MCS7830
-#define CONFIG_USB_ETHER_SMSC95XX
-
/* NET Configs */
#endif /* __CONFIG_H */
#define CONFIG_RED_LED 110
#define CONFIG_GREEN_LED 109
-#define CONFIG_STM32_FLASH
-
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_BOOTCOMMAND \
- "run bootcmd_romfs"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
#define CONFIG_SYS_MAX_FLASH_SECT 12
#define CONFIG_SYS_MAX_FLASH_BANKS 2
-#define CONFIG_STM32_FLASH
-
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_MAX_FLASH_SECT 12
#define CONFIG_SYS_MAX_FLASH_BANKS 2
-#define CONFIG_STM32_FLASH
-
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_MAX_FLASH_SECT 8
#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_STM32_FLASH
-
#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8)
#define CONFIG_DW_ALTDESCRIPTOR
* for serial/usb: execute the stm32prog command
* for mmc boot (eMMC, SD card), boot only on the same device
* for nand or spi-nand boot, boot with on ubifs partition on UBI partition
- * for nor boot, use SD card = mmc0
+ * for nor boot, use the default order
*/
#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \
"echo \"Boot over ${boot_device}${boot_instance}!\";" \
"if test ${boot_device} = nand ||" \
" test ${boot_device} = spi-nand ;" \
"then env set boot_targets ubifs0; fi;" \
- "if test ${boot_device} = nor;" \
- "then env set boot_targets mmc0; fi;" \
"run distro_bootcmd;" \
"fi;\0"
#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */
#endif
-
-/* I2C */
-#if defined(CONFIG_VIDEO_LCD_PANEL_I2C)
-/* We use pin names in Kconfig and sunxi_name_to_gpio() */
-#define CONFIG_SOFT_I2C_GPIO_SDA soft_i2c_gpio_sda
-#define CONFIG_SOFT_I2C_GPIO_SCL soft_i2c_gpio_scl
-#ifndef __ASSEMBLY__
-extern int soft_i2c_gpio_sda;
-extern int soft_i2c_gpio_scl;
-#endif
-#define CONFIG_VIDEO_LCD_I2C_BUS 0 /* The lcd panel soft i2c is bus 0 */
-#define CONFIG_SYS_SPD_BUS_NUM 1 /* And the axp209 i2c bus is bus 1 */
-#else
-#define CONFIG_SYS_SPD_BUS_NUM 0 /* The axp209 i2c bus is bus 0 */
-#define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */
-#endif
-
/* Ethernet support */
#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_SPL_STACK 0x800ffffc
/* For USB EHCI controller */
-#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
#endif /* _TEGRA114_COMMON_H_ */
#define CONFIG_SPL_STACK 0x800ffffc
/* For USB EHCI controller */
-#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
/* GPU needs setup */
* packets depending on the buffer address and size.
*/
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
-#define CONFIG_EHCI_IS_TDI
#define CONFIG_SYS_NAND_SELF_INIT
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"fdtfile=" FDTFILE "\0" \
"fdt_addr_r=0x83000000\0" \
- "ramdisk_addr_r=0x83200000\0"
+ "ramdisk_addr_r=0x83420000\0"
/* For USB EHCI controller */
-#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
/* GPU needs setup */
#define CONFIG_SPL_STACK 0x800ffffc
/* For USB EHCI controller */
-#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
#endif /* _TEGRA30_COMMON_H_ */
#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
/* Environment in SPI NOR flash */
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS 64 /* max command args */
-#define CONFIG_NO_RELOCATION 1
#define PLL_REF_CLK 50000000 /* 50 MHz */
#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK)
#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define PHYS_SDRAM_2 0x8080000000
+#define PHYS_SDRAM_2_SIZE 0x180000000
+
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
#define CONFIG_EXTRA_ENV_SETTINGS \
/* USB, USB storage, USB ethernet */
#define CONFIG_EHCI_MMIO_BIG_ENDIAN
#define CONFIG_EHCI_DESC_BIG_ENDIAN
-#define CONFIG_EHCI_IS_TDI
/*
* Diagnostics
* U-Boot into it.
*/
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
/* Environment in SPI NOR flash */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
/* Additional FS support/configuration */
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
/* Environment in SPI NOR flash */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
#endif
#ifdef CONFIG_USB_EHCI_ZYNQ
-# define CONFIG_EHCI_IS_TDI
-
# define DFU_DEFAULT_POLL_TIMEOUT 300
# define CONFIG_THOR_RESET_OFF
#endif
fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index);
/**
+ * devfdt_get_addr_index_ptr() - Return indexed pointer to the address of the
+ * reg property of a device
+ *
+ * @dev: Pointer to a device
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ * and @index is used to select which one is required
+ *
+ * @return Pointer to addr, or NULL if there is no such property
+ */
+void *devfdt_get_addr_index_ptr(const struct udevice *dev, int index);
+
+/**
* devfdt_get_addr_size_index() - Get the indexed reg property of a device
*
* Returns the address and size specified in the 'reg' property of a device.
* @parent: parent device (root)
* @node: device tree node to bind
* @devp: if non-NULL, returns a pointer to the bound device
+ * @drv: if non-NULL, force this driver to be bound
* @pre_reloc_only: If true, bind only nodes with special devicetree properties,
* or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers.
* @return 0 if device was bound, -EINVAL if the device tree is invalid,
* other -ve value on error
*/
int lists_bind_fdt(struct udevice *parent, ofnode node, struct udevice **devp,
- bool pre_reloc_only);
+ struct driver *drv, bool pre_reloc_only);
/**
* device_bind_driver() - bind a device to a driver
fdt_addr_t dev_read_addr_index(const struct udevice *dev, int index);
/**
+ * dev_read_addr_index_ptr() - Get the indexed reg property of a device
+ * as a pointer
+ *
+ * @dev: Device to read from
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ * and @index is used to select which one is required
+ *
+ * @return pointer or NULL if not found
+ */
+void *dev_read_addr_index_ptr(const struct udevice *dev, int index);
+
+/**
* dev_read_addr_size_index() - Get the indexed reg property of a device
*
* @dev: Device to read from
return devfdt_get_addr_index(dev, index);
}
+static inline void *dev_read_addr_index_ptr(const struct udevice *dev,
+ int index)
+{
+ return devfdt_get_addr_index_ptr(dev, index);
+}
+
static inline fdt_addr_t dev_read_addr_size_index(const struct udevice *dev,
int index,
fdt_size_t *size)
#define CLKID_HIFI_PLL 69
#define CLKID_PCIE_CML_EN0 79
#define CLKID_PCIE_CML_EN1 80
-#define CLKID_MIPI_ENABLE 81
#define CLKID_GEN_CLK 84
+#define CLKID_VPU_0_SEL 92
+#define CLKID_VPU_0 93
+#define CLKID_VPU_1_SEL 95
+#define CLKID_VPU_1 96
+#define CLKID_VPU 97
+#define CLKID_VAPB_0_SEL 99
+#define CLKID_VAPB_0 100
+#define CLKID_VAPB_1_SEL 102
+#define CLKID_VAPB_1 103
+#define CLKID_VAPB_SEL 104
+#define CLKID_VAPB 105
+#define CLKID_VCLK 106
+#define CLKID_VCLK2 107
+#define CLKID_VCLK_DIV1 122
+#define CLKID_VCLK_DIV2 123
+#define CLKID_VCLK_DIV4 124
+#define CLKID_VCLK_DIV6 125
+#define CLKID_VCLK_DIV12 126
+#define CLKID_VCLK2_DIV1 127
+#define CLKID_VCLK2_DIV2 128
+#define CLKID_VCLK2_DIV4 129
+#define CLKID_VCLK2_DIV6 130
+#define CLKID_VCLK2_DIV12 131
+#define CLKID_CTS_ENCL 133
+#define CLKID_VDIN_MEAS 136
#endif /* __AXG_CLKC_H */
#define CLKID_SPICC1_SCLK 261
#define CLKID_NNA_AXI_CLK 264
#define CLKID_NNA_CORE_CLK 267
+#define CLKID_MIPI_DSI_PXCLK_SEL 269
+#define CLKID_MIPI_DSI_PXCLK 270
#endif /* __G12A_CLKC_H */
#ifndef __FDT_SUPPORT_H
#define __FDT_SUPPORT_H
-#ifdef CONFIG_OF_LIBFDT
+#if defined(CONFIG_OF_LIBFDT) && !defined(USE_HOSTCC)
#include <asm/u-boot.h>
#include <linux/libfdt.h>
#define SPL_BUILD 0
#endif
-#ifdef CONFIG_OF_PRIOR_STAGE
-extern phys_addr_t prior_stage_fdt_address;
-#endif
-
/*
* Information about a resource. start is the first address of the resource
* and end is the last address (inclusive). The length of the resource will
return fdt_setprop_u32(blob, node, "phandle", phandle);
}
+/* add "no-map" property */
+#define FDTDEC_RESERVED_MEMORY_NO_MAP (1 << 0)
+
/**
* fdtdec_add_reserved_memory() - add or find a reserved-memory node
*
* };
* uint32_t phandle;
*
- * fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, &phandle, false);
+ * fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, NULL, 0, &phandle,
+ * 0);
*
* This results in the following subnode being added to the top-level
* /reserved-memory node:
* @param blob FDT blob
* @param basename base name of the node to create
* @param carveout information about the carveout region
+ * @param compatibles list of compatible strings for the carveout region
+ * @param count number of compatible strings for the carveout region
* @param phandlep return location for the phandle of the carveout region
* can be NULL if no phandle should be added
- * @param no_map add "no-map" property if true
+ * @param flags bitmask of flags to set for the carveout region
* @return 0 on success or a negative error code on failure
*/
int fdtdec_add_reserved_memory(void *blob, const char *basename,
const struct fdt_memory *carveout,
- uint32_t *phandlep, bool no_map);
+ const char **compatibles, unsigned int count,
+ uint32_t *phandlep, unsigned long flags);
/**
* fdtdec_get_carveout() - reads a carveout from an FDT
*
* @param blob FDT blob
* @param node name of a node
- * @param name name of the property in the given node that contains
+ * @param prop_name name of the property in the given node that contains
* the phandle for the carveout
* @param index index of the phandle for which to read the carveout
* @param carveout return location for the carveout information
+ * @param name return location for the carveout name
+ * @param compatiblesp return location for compatible strings
+ * @param countp return location for the number of compatible strings
+ * @param flags return location for the flags of the carveout
* @return 0 on success or a negative error code on failure
*/
-int fdtdec_get_carveout(const void *blob, const char *node, const char *name,
- unsigned int index, struct fdt_memory *carveout);
+int fdtdec_get_carveout(const void *blob, const char *node,
+ const char *prop_name, unsigned int index,
+ struct fdt_memory *carveout, const char **name,
+ const char ***compatiblesp, unsigned int *countp,
+ unsigned long *flags);
/**
* fdtdec_set_carveout() - sets a carveout region for a given node
* .end = 0x934b2fff,
* };
*
- * fdtdec_set_carveout(fdt, node, "memory-region", 0, "framebuffer", &fb);
+ * fdtdec_set_carveout(fdt, node, "memory-region", 0, "framebuffer", NULL,
+ * 0, &fb, 0);
*
* dc@54200000 is a display controller and was set up by the bootloader to
* scan out the framebuffer specified by "fb". This would cause the following
* @param prop_name name of the property in which to store the phandle of
* the carveout
* @param index index of the phandle to store
- * @param name base name of the reserved-memory node to create
* @param carveout information about the carveout to add
+ * @param name base name of the reserved-memory node to create
+ * @param compatibles compatible strings to set for the carveout
+ * @param count number of compatible strings
+ * @param flags bitmask of flags to set for the carveout
* @return 0 on success or a negative error code on failure
*/
int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name,
- unsigned int index, const char *name,
- const struct fdt_memory *carveout);
+ unsigned int index, const struct fdt_memory *carveout,
+ const char *name, const char **compatibles,
+ unsigned int count, unsigned long flags);
/**
* Set up the device tree ready for use
* gzwrite_progress_finish called at end of loop to
* indicate success (retcode=0) or failure
*/
-void gzwrite_progress_init(u64 expected_size);
+void gzwrite_progress_init(ulong expected_size);
-void gzwrite_progress(int iteration, u64 bytes_written, u64 total_bytes);
+void gzwrite_progress(int iteration, ulong bytes_written, ulong total_bytes);
-void gzwrite_progress_finish(int retcode, u64 totalwritten, u64 totalsize,
+void gzwrite_progress_finish(int retcode, ulong totalwritten, ulong totalsize,
u32 expected_crc, u32 calculated_crc);
/**
* @return 0 if OK, -1 on error
*/
int gzwrite(unsigned char *src, int len, struct blk_desc *dev, ulong szwritebuf,
- u64 startoffs, u64 szexpected);
+ ulong startoffs, ulong szexpected);
/**
* gzip()- Compress data into a buffer using the gzip algorithm
#ifndef _HASH_H
#define _HASH_H
+#ifdef USE_HOSTCC
+#include <linux/kconfig.h>
+#endif
+
struct cmd_tbl;
/*
* Maximum digest size for all algorithms we support. Having this value
* avoids a malloc() or C99 local declaration in common/cmd_hash.c.
*/
-#if defined(CONFIG_SHA384) || defined(CONFIG_SHA512)
+#if CONFIG_IS_ENABLED(SHA384) || CONFIG_IS_ENABLED(SHA512)
#define HASH_MAX_DIGEST_SIZE 64
#else
#define HASH_MAX_DIGEST_SIZE 32
#ifdef USE_HOSTCC
#include <sys/types.h>
+#include <linux/kconfig.h>
-/* new uImage format support enabled on host */
-#define IMAGE_ENABLE_FIT 1
-#define IMAGE_ENABLE_OF_LIBFDT 1
-#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
-#define CONFIG_FIT_RSASSA_PSS 1
-#define CONFIG_MD5
-#define CONFIG_SHA1
-#define CONFIG_SHA256
-#define CONFIG_SHA384
-#define CONFIG_SHA512
-
-#define IMAGE_ENABLE_IGNORE 0
#define IMAGE_INDENT_STRING ""
#else
#include <command.h>
#include <linker_lists.h>
-/* Take notice of the 'ignore' property for hashes */
-#define IMAGE_ENABLE_IGNORE 1
#define IMAGE_INDENT_STRING " "
-#define IMAGE_ENABLE_FIT CONFIG_IS_ENABLED(FIT)
-#define IMAGE_ENABLE_OF_LIBFDT CONFIG_IS_ENABLED(OF_LIBFDT)
-
#endif /* USE_HOSTCC */
-#if IMAGE_ENABLE_FIT
#include <hash.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
-#endif /* IMAGE_ENABLE_FIT */
-
-#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
-# define IMAGE_BOOT_GET_CMDLINE 1
-#else
-# define IMAGE_BOOT_GET_CMDLINE 0
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-# define IMAGE_OF_BOARD_SETUP 1
-#else
-# define IMAGE_OF_BOARD_SETUP 0
-#endif
-
-#ifdef CONFIG_OF_SYSTEM_SETUP
-# define IMAGE_OF_SYSTEM_SETUP 1
-#else
-# define IMAGE_OF_SYSTEM_SETUP 0
-#endif
+#include <u-boot/hash-checksum.h>
extern ulong image_load_addr; /* Default Load Address */
extern ulong image_save_addr; /* Default Save Address */
image_header_t legacy_hdr_os_copy; /* header copy */
ulong legacy_hdr_valid;
-#if IMAGE_ENABLE_FIT
+ /*
+ * The fit_ members are only used with FIT, but it involves a lot of
+ * #ifdefs to avoid compiling that code. Since FIT is the standard
+ * format, even for SPL, this extra data size seems worth it.
+ */
const char *fit_uname_cfg; /* configuration node unit name */
void *fit_hdr_os; /* os FIT image header */
void *fit_hdr_setup; /* x86 setup FIT image header */
const char *fit_uname_setup; /* x86 setup subimage node name */
int fit_noffset_setup;/* x86 setup subimage node offset */
-#endif
#ifndef USE_HOSTCC
image_info_t os; /* os image info */
int genimg_get_comp_id(const char *name);
void genimg_print_size(uint32_t size);
-#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || \
- defined(USE_HOSTCC)
+#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
#define IMAGE_ENABLE_TIMESTAMP 1
#else
#define IMAGE_ENABLE_TIMESTAMP 0
int boot_get_setup(bootm_headers_t *images, uint8_t arch, ulong *setup_start,
ulong *setup_len);
-#ifndef USE_HOSTCC
/* Image format types, returned by _get_format() routine */
#define IMAGE_FORMAT_INVALID 0x00
-#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
#define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */
-#endif
#define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */
#define IMAGE_FORMAT_ANDROID 0x03 /* Android boot image */
*/
int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images,
uint8_t arch, const ulong *ld_start, ulong *const ld_len);
-#endif /* !USE_HOSTCC */
int boot_get_setup_fit(bootm_headers_t *images, uint8_t arch,
ulong *setup_start, ulong *setup_len);
*/
int image_source_script(ulong addr, const char *fit_uname);
-#ifndef USE_HOSTCC
/**
* fit_get_node_from_config() - Look up an image a FIT by type
*
int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len,
ulong *initrd_start, ulong *initrd_end);
int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end);
-#ifdef CONFIG_SYS_BOOT_GET_KBD
int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd);
-#endif /* CONFIG_SYS_BOOT_GET_KBD */
-#endif /* !USE_HOSTCC */
/*******************************************************************/
/* Legacy format specific code (prefixed with image_) */
}
static inline int image_check_arch(const image_header_t *hdr, uint8_t arch)
{
-#ifndef USE_HOSTCC
/* Let's assume that sandbox can load any architecture */
- if (IS_ENABLED(CONFIG_SANDBOX))
+ if (!tools_build() && IS_ENABLED(CONFIG_SANDBOX))
return true;
-#endif
return (image_get_arch(hdr) == arch) ||
(image_get_arch(hdr) == IH_ARCH_ARM && arch == IH_ARCH_ARM64);
}
#define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE
-#if IMAGE_ENABLE_FIT
/* cmdline argument format parsing */
int fit_parse_conf(const char *spec, ulong addr_curr,
ulong *addr, const char **conf_name);
int fit_check_ramdisk(const void *fit, int os_noffset,
uint8_t arch, int verify);
-#endif /* IMAGE_ENABLE_FIT */
int calculate_hash(const void *data, int data_len, const char *algo,
uint8_t *value, int *value_len);
# define FIT_IMAGE_ENABLE_VERIFY CONFIG_IS_ENABLED(FIT_SIGNATURE)
#endif
-#if IMAGE_ENABLE_FIT
#ifdef USE_HOSTCC
void *image_get_host_blob(void);
void image_set_host_blob(void *host_blob);
# define gd_fdt_blob() (gd->fdt_blob)
#endif
-#endif /* IMAGE_ENABLE_FIT */
-
/*
* Information passed to the signing routines
*
int size;
};
-#if FIT_IMAGE_ENABLE_VERIFY
-# include <u-boot/hash-checksum.h>
-#endif
struct checksum_algo {
const char *name;
const int checksum_len;
const EVP_MD *(*calculate_sign)(void);
#endif
int (*calculate)(const char *name,
- const struct image_region region[],
+ const struct image_region *region,
int region_count, uint8_t *checksum);
};
*/
struct padding_algo *image_get_padding_algo(const char *name);
-#if IMAGE_ENABLE_FIT
-
/**
* fit_image_verify_required_sigs() - Verify signatures marked as 'required'
*
struct cipher_algo *image_get_cipher_algo(const char *full_name);
-#ifdef CONFIG_FIT_VERBOSE
-#define fit_unsupported(msg) printf("! %s:%d " \
- "FIT images not supported for '%s'\n", \
- __FILE__, __LINE__, (msg))
-
-#define fit_unsupported_reset(msg) printf("! %s:%d " \
- "FIT images not supported for '%s' " \
- "- must reset board to recover!\n", \
- __FILE__, __LINE__, (msg))
-#else
-#define fit_unsupported(msg)
-#define fit_unsupported_reset(msg)
-#endif /* CONFIG_FIT_VERBOSE */
-#endif /* CONFIG_FIT */
-
-#if !defined(USE_HOSTCC)
-#if defined(CONFIG_ANDROID_BOOT_IMAGE)
struct andr_img_hdr;
int android_image_check_header(const struct andr_img_hdr *hdr);
int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
ulong android_image_get_kload(const struct andr_img_hdr *hdr);
ulong android_image_get_kcomp(const struct andr_img_hdr *hdr);
void android_print_contents(const struct andr_img_hdr *hdr);
-#if !defined(CONFIG_SPL_BUILD)
bool android_image_print_dtb_contents(ulong hdr_addr);
-#endif
-
-#endif /* CONFIG_ANDROID_BOOT_IMAGE */
-#endif /* !USE_HOSTCC */
/**
* board_fit_config_name_match() - Check for a matching board name
(config_enabled(option))
/*
- * U-Boot add-on: Helper macros to reference to different macros
- * (CONFIG_ or CONFIG_SPL_ prefixed), depending on the build context.
+ * U-Boot add-on: Helper macros to reference to different macros (prefixed by
+ * CONFIG_, CONFIG_SPL_, CONFIG_TPL_ or CONFIG_TOOLS_), depending on the build
+ * context.
*/
-#if defined(CONFIG_TPL_BUILD)
+#ifdef USE_HOSTCC
+#define _CONFIG_PREFIX TOOLS_
+#elif defined(CONFIG_TPL_BUILD)
#define _CONFIG_PREFIX TPL_
#elif defined(CONFIG_SPL_BUILD)
#define _CONFIG_PREFIX SPL_
/*
* CONFIG_VAL(FOO) evaluates to the value of
+ * CONFIG_TOOLS_FOO if USE_HOSTCC is defined,
* CONFIG_FOO if CONFIG_SPL_BUILD is undefined,
* CONFIG_SPL_FOO if CONFIG_SPL_BUILD is defined.
* CONFIG_TPL_FOO if CONFIG_TPL_BUILD is defined.
/*
* CONFIG_IS_ENABLED(FOO) expands to
+ * 1 if USE_HOSTCC is defined and CONFIG_TOOLS_FOO is set to 'y',
* 1 if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y',
* 1 if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y',
* 1 if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y',
* 0 otherwise.
*
* CONFIG_IS_ENABLED(FOO, (abc)) expands to
+ * abc if USE_HOSTCC is defined and CONFIG_TOOLS_FOO is set to 'y',
* abc if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y',
* abc if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y',
* abc if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y',
* nothing otherwise.
*
* CONFIG_IS_ENABLED(FOO, (abc), (def)) expands to
+ * abc if USE_HOSTCC is defined and CONFIG_TOOLS_FOO is set to 'y',
* abc if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y',
* abc if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y',
* abc if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y',
void *memchr_inv(const void *, int, size_t);
#endif
+/**
+ * memdup() - allocate a buffer and copy in the contents
+ *
+ * Note that this returns a valid pointer even if @len is 0
+ *
+ * @src: data to copy in
+ * @len: number of bytes to copy
+ * @return allocated buffer with the copied contents, or NULL if not enough
+ * memory is available
+ *
+ */
+char *memdup(const void *src, size_t len);
+
unsigned long ustrtoul(const char *cp, char **endp, unsigned int base);
unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base);
size_t ZSTD_insertBlock(ZSTD_DCtx *dctx, const void *blockStart,
size_t blockSize);
+struct abuf;
+
+/**
+ * zstd_decompress() - Decompress Zstandard data
+ *
+ * @in: Input buffer to decompress
+ * @out: Output buffer to hold the results (must be large enough)
+ * @return size of the decompressed data, or -ve on error
+ */
+int zstd_decompress(struct abuf *in, struct abuf *out);
+
#endif /* ZSTD_H */
#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
+#define PCI_EXP_RTCTL 28 /* Root Control */
+#define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */
+#define PCI_EXP_RTCAP 30 /* Root Capabilities */
+#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */
#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
#define PCI_EXP_DEVCAP2_ARI 0x00000020 /* ARI Forwarding Supported */
#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
#ifndef _RELOCATE_H_
#define _RELOCATE_H_
-#include <common.h>
+#ifndef USE_HOSTCC
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#endif
/**
* copy_uboot_to_ram() - Copy U-Boot to its new relocated position
*/
int do_elf_reloc_fixups(void);
+/**
+ * manual_reloc() - Manually relocate a pointer if needed
+ *
+ * This is a nop in almost all cases, except for the systems with a broken gcc
+ * which need to manually relocate some things.
+ *
+ * @ptr: Pointer to relocate
+ * @return new pointer value
+ */
+static inline void *manual_reloc(void *ptr)
+{
+#ifndef USE_HOSTCC
+ if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC))
+ return ptr + gd->reloc_off;
+#endif
+ return ptr;
+}
+
+#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
+#define MANUAL_RELOC(ptr) (ptr) = manual_reloc(ptr)
+#else
+#define MANUAL_RELOC(ptr) (void)(ptr)
+#endif
+
#endif /* _RELOCATE_H_ */
#define _RSA_CHECKSUM_H
#include <errno.h>
-#include <image.h>
#include <u-boot/sha1.h>
#include <u-boot/sha256.h>
#include <u-boot/sha512.h>
+struct image_region;
+
/**
* hash_calculate() - Calculate hash over the data
*
* @return 0 if OK, < 0 if error
*/
int hash_calculate(const char *name,
- const struct image_region region[], int region_count,
+ const struct image_region *region, int region_count,
uint8_t *checksum);
#endif
uint8_t *msg, int msg_len,
const uint8_t *hash, int hash_len);
-#ifdef CONFIG_FIT_RSASSA_PSS
int padding_pss_verify(struct image_sign_info *info,
uint8_t *msg, int msg_len,
const uint8_t *hash, int hash_len);
-#endif /* CONFIG_FIT_RSASSA_PSS */
#define RSA_DEFAULT_PADDING_NAME "pkcs-1.5"
#define VNBITS(bpix) (1 << (bpix))
+enum video_format {
+ VIDEO_UNKNOWN,
+ VIDEO_X8B8G8R8,
+ VIDEO_X8R8G8B8,
+ VIDEO_X2R10G10B10,
+};
+
/**
* struct video_priv - Device information used by the video uclass
*
* @ysize: Number of pixels rows (e.g.. 768)
* @rot: Display rotation (0=none, 1=90 degrees clockwise, etc.)
* @bpix: Encoded bits per pixel (enum video_log2_bpp)
+ * @format: Pixel format (enum video_format)
* @vidconsole_drv_name: Driver to use for the text console, NULL to
* select automatically
* @font_size: Font size in pixels (0 to use a default value)
ushort ysize;
ushort rot;
enum video_log2_bpp bpix;
+ enum video_format format;
const char *vidconsole_drv_name;
int font_size;
The SHA256 algorithm produces a 256-bit (32-byte) hash value
(digest).
-
config SHA512
bool "Enable SHA512 support"
help
hashing algorithms. This affects the 'hash' command and also the
hash_lookup_algo() function.
+if SPL
+
+config SPL_SHA1
+ bool "Enable SHA1 support in SPL"
+ default y if SHA1
+ help
+ This option enables support of hashing using SHA1 algorithm.
+ The hash is calculated in software.
+ The SHA1 algorithm produces a 160-bit (20-byte) hash value
+ (digest).
+
+config SPL_SHA256
+ bool "Enable SHA256 support in SPL"
+ default y if SHA256
+ help
+ This option enables support of hashing using SHA256 algorithm.
+ The hash is calculated in software.
+ The SHA256 algorithm produces a 256-bit (32-byte) hash value
+ (digest).
+
+config SPL_SHA512
+ bool "Enable SHA512 support in SPL"
+ default y if SHA512
+ help
+ This option enables support of hashing using SHA512 algorithm.
+ The hash is calculated in software.
+ The SHA512 algorithm produces a 512-bit (64-byte) hash value
+ (digest).
+
+config SPL_SHA384
+ bool "Enable SHA384 support in SPL"
+ default y if SHA384
+ select SPL_SHA512
+ help
+ This option enables support of hashing using SHA384 algorithm.
+ The hash is calculated in software. This is also selects SHA512,
+ because these implementations share the bulk of the code..
+ The SHA384 algorithm produces a 384-bit (48-byte) hash value
+ (digest).
+
+config SPL_SHA_HW_ACCEL
+ bool "Enable hardware acceleration for SHA hash functions"
+ default y if SHA_HW_ACCEL
+ help
+ This option enables hardware acceleration for the SHA1 and SHA256
+ hashing algorithms. This affects the 'hash' command and also the
+ hash_lookup_algo() function.
+
+config SPL_SHA_PROG_HW_ACCEL
+ bool "Enable Progressive hashing support using hardware in SPL"
+ depends on SHA_PROG_HW_ACCEL
+ default y
+ help
+ This option enables hardware-acceleration for SHA progressive
+ hashing.
+ Data can be streamed in a block at a time and the hashing is
+ performed in hardware.
+
+endif
+
if SHA_HW_ACCEL
config SHA512_HW_ACCEL
security applications, but it can be useful for providing a quick
checksum of a block of data.
+config CRC32
+ def_bool y
+ help
+ Enables CRC32 support in U-Boot. This is normally required.
+
config CRC32C
bool
CFLAGS_display_options.o := $(if $(BUILD_TAG),-DBUILD_TAG='"$(BUILD_TAG)"')
obj-$(CONFIG_BCH) += bch.o
obj-$(CONFIG_MMC_SPI) += crc7.o
-#ifndef CONFIG_TPL_BUILD
-obj-y += crc32.o
-#endif
+obj-$(CONFIG_$(SPL_TPL_)CRC32) += crc32.o
obj-$(CONFIG_CRC32C) += crc32c.o
obj-y += ctype.o
obj-y += div64.o
obj-$(CONFIG_SSCANF) += sscanf.o
endif
+obj-y += abuf.o
obj-y += date.o
obj-y += rtc-lib.o
obj-$(CONFIG_LIB_ELF) += elf.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Handles a buffer that can be allocated and freed
+ *
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <abuf.h>
+#include <malloc.h>
+#include <mapmem.h>
+#include <string.h>
+
+void abuf_set(struct abuf *abuf, void *data, size_t size)
+{
+ abuf_uninit(abuf);
+ abuf->data = data;
+ abuf->size = size;
+}
+
+void abuf_map_sysmem(struct abuf *abuf, ulong addr, size_t size)
+{
+ abuf_set(abuf, map_sysmem(addr, size), size);
+}
+
+bool abuf_realloc(struct abuf *abuf, size_t new_size)
+{
+ void *ptr;
+
+ if (!new_size) {
+ /* easy case, just need to uninit, freeing any allocation */
+ abuf_uninit(abuf);
+ return true;
+ } else if (abuf->alloced) {
+ /* currently allocated, so need to reallocate */
+ ptr = realloc(abuf->data, new_size);
+ if (!ptr)
+ return false;
+ abuf->data = ptr;
+ abuf->size = new_size;
+ return true;
+ } else if (new_size <= abuf->size) {
+ /*
+ * not currently alloced and new size is no larger. Just update
+ * it. Data is lost off the end if new_size < abuf->size
+ */
+ abuf->size = new_size;
+ return true;
+ } else {
+ /* not currently allocated and new size is larger. Alloc and
+ * copy in data. The new space is not inited.
+ */
+ ptr = memdup(abuf->data, new_size);
+ if (!ptr)
+ return false;
+ abuf->data = ptr;
+ abuf->size = new_size;
+ abuf->alloced = true;
+ return true;
+ }
+}
+
+void *abuf_uninit_move(struct abuf *abuf, size_t *sizep)
+{
+ void *ptr;
+
+ if (sizep)
+ *sizep = abuf->size;
+ if (!abuf->size)
+ return NULL;
+ if (abuf->alloced) {
+ ptr = abuf->data;
+ } else {
+ ptr = memdup(abuf->data, abuf->size);
+ if (!ptr)
+ return NULL;
+ }
+ /* Clear everything out so there is no record of the data */
+ abuf_init(abuf);
+
+ return ptr;
+}
+
+void abuf_init_set(struct abuf *abuf, void *data, size_t size)
+{
+ abuf_init(abuf);
+ abuf_set(abuf, data, size);
+}
+
+void abuf_init_move(struct abuf *abuf, void *data, size_t size)
+{
+ abuf_init_set(abuf, data, size);
+ abuf->alloced = true;
+}
+
+void abuf_uninit(struct abuf *abuf)
+{
+ if (abuf->alloced)
+ free(abuf->data);
+ abuf_init(abuf);
+}
+
+void abuf_init(struct abuf *abuf)
+{
+ abuf->data = NULL;
+ abuf->size = 0;
+ abuf->alloced = false;
+}
config EFI_SECURE_BOOT
bool "Enable EFI secure boot support"
- depends on EFI_LOADER
+ depends on EFI_LOADER && FIT_SIGNATURE
select HASH
select SHA256
select RSA
return EFI_EXIT(ret);
}
+static __always_inline struct efi_gop_pixel efi_vid30_to_blt_col(u32 vid)
+{
+ struct efi_gop_pixel blt = {
+ .reserved = 0,
+ };
+
+ blt.blue = (vid & 0x3ff) >> 2;
+ vid >>= 10;
+ blt.green = (vid & 0x3ff) >> 2;
+ vid >>= 10;
+ blt.red = (vid & 0x3ff) >> 2;
+ return blt;
+}
+
+static __always_inline u32 efi_blt_col_to_vid30(struct efi_gop_pixel *blt)
+{
+ return (u32)(blt->red << 2) << 20 |
+ (u32)(blt->green << 2) << 10 |
+ (u32)(blt->blue << 2);
+}
+
static __always_inline struct efi_gop_pixel efi_vid16_to_blt_col(u16 vid)
{
struct efi_gop_pixel blt = {
if (vid_bpp == 32)
pix = *(struct efi_gop_pixel *)&fb32[
slineoff + j + sx];
+ else if (vid_bpp == 30)
+ pix = efi_vid30_to_blt_col(fb32[
+ slineoff + j + sx]);
else
pix = efi_vid16_to_blt_col(fb16[
slineoff + j + sx]);
case EFI_BLT_VIDEO_TO_VIDEO:
if (vid_bpp == 32)
fb32[dlineoff + j + dx] = *(u32 *)&pix;
+ else if (vid_bpp == 30)
+ fb32[dlineoff + j + dx] =
+ efi_blt_col_to_vid30(&pix);
else
fb16[dlineoff + j + dx] =
efi_blt_col_to_vid16(&pix);
#else
case LCD_COLOR32:
#endif
- vid_bpp = 32;
+ if (gopobj->info.pixel_format == EFI_GOT_BGRA8)
+ vid_bpp = 32;
+ else
+ vid_bpp = 30;
break;
#ifdef CONFIG_DM_VIDEO
case VIDEO_BPP16:
dy, width, height, delta, 16);
}
+static efi_status_t gop_blt_buf_to_vid30(struct efi_gop *this,
+ struct efi_gop_pixel *buffer,
+ u32 foo, efi_uintn_t sx,
+ efi_uintn_t sy, efi_uintn_t dx,
+ efi_uintn_t dy, efi_uintn_t width,
+ efi_uintn_t height, efi_uintn_t delta)
+{
+ return gop_blt_int(this, buffer, EFI_BLT_BUFFER_TO_VIDEO, sx, sy, dx,
+ dy, width, height, delta, 30);
+}
+
static efi_status_t gop_blt_buf_to_vid32(struct efi_gop *this,
struct efi_gop_pixel *buffer,
u32 foo, efi_uintn_t sx,
ret = gop_blt_buf_to_vid32(this, buffer, operation, sx,
sy, dx, dy, width, height,
delta);
+ else if (vid_bpp == 30)
+ ret = gop_blt_buf_to_vid30(this, buffer, operation, sx,
+ sy, dx, dy, width, height,
+ delta);
else
ret = gop_blt_buf_to_vid16(this, buffer, operation, sx,
sy, dx, dy, width, height,
efi_status_t efi_gop_register(void)
{
struct efi_gop_obj *gopobj;
- u32 bpix, col, row;
+ u32 bpix, format, col, row;
u64 fb_base, fb_size;
void *fb;
efi_status_t ret;
priv = dev_get_uclass_priv(vdev);
bpix = priv->bpix;
+ format = priv->format;
col = video_get_xsize(vdev);
row = video_get_ysize(vdev);
fb_base = (uintptr_t)priv->fb;
int line_len;
bpix = panel_info.vl_bpix;
+ format = VIDEO_UNKNOWN;
col = panel_info.vl_col;
row = panel_info.vl_row;
fb_base = gd->fb_base;
if (bpix == LCD_COLOR32)
#endif
{
- gopobj->info.pixel_format = EFI_GOT_BGRA8;
+ if (format == VIDEO_X2R10G10B10) {
+ gopobj->info.pixel_format = EFI_GOT_BITMASK;
+ gopobj->info.pixel_bitmask[0] = 0x3ff00000; /* red */
+ gopobj->info.pixel_bitmask[1] = 0x000ffc00; /* green */
+ gopobj->info.pixel_bitmask[2] = 0x000003ff; /* blue */
+ gopobj->info.pixel_bitmask[3] = 0xc0000000; /* reserved */
+ } else {
+ gopobj->info.pixel_format = EFI_GOT_BGRA8;
+ }
} else {
gopobj->info.pixel_format = EFI_GOT_BITMASK;
gopobj->info.pixel_bitmask[0] = 0xf800; /* red */
int fdtdec_add_reserved_memory(void *blob, const char *basename,
const struct fdt_memory *carveout,
- uint32_t *phandlep, bool no_map)
+ const char **compatibles, unsigned int count,
+ uint32_t *phandlep, unsigned long flags)
{
fdt32_t cells[4] = {}, *ptr = cells;
uint32_t upper, lower, phandle;
if (node < 0)
return node;
+ if (flags & FDTDEC_RESERVED_MEMORY_NO_MAP) {
+ err = fdt_setprop(blob, node, "no-map", NULL, 0);
+ if (err < 0)
+ return err;
+ }
+
if (phandlep) {
err = fdt_generate_phandle(blob, &phandle);
if (err < 0)
if (err < 0)
return err;
- if (no_map) {
- err = fdt_setprop(blob, node, "no-map", NULL, 0);
+ if (compatibles && count > 0) {
+ size_t length = 0, len = 0;
+ unsigned int i;
+ char *buffer;
+
+ for (i = 0; i < count; i++)
+ length += strlen(compatibles[i]) + 1;
+
+ buffer = malloc(length);
+ if (!buffer)
+ return -FDT_ERR_INTERNAL;
+
+ for (i = 0; i < count; i++)
+ len += strlcpy(buffer + len, compatibles[i],
+ length - len) + 1;
+
+ err = fdt_setprop(blob, node, "compatible", buffer, length);
+ free(buffer);
if (err < 0)
return err;
}
return 0;
}
-int fdtdec_get_carveout(const void *blob, const char *node, const char *name,
- unsigned int index, struct fdt_memory *carveout)
+int fdtdec_get_carveout(const void *blob, const char *node,
+ const char *prop_name, unsigned int index,
+ struct fdt_memory *carveout, const char **name,
+ const char ***compatiblesp, unsigned int *countp,
+ unsigned long *flags)
{
const fdt32_t *prop;
uint32_t phandle;
if (offset < 0)
return offset;
- prop = fdt_getprop(blob, offset, name, &len);
+ prop = fdt_getprop(blob, offset, prop_name, &len);
if (!prop) {
- debug("failed to get %s for %s\n", name, node);
+ debug("failed to get %s for %s\n", prop_name, node);
return -FDT_ERR_NOTFOUND;
}
if (len < (sizeof(phandle) * (index + 1))) {
debug("invalid phandle index\n");
- return -FDT_ERR_BADPHANDLE;
+ return -FDT_ERR_NOTFOUND;
}
phandle = fdt32_to_cpu(prop[index]);
return offset;
}
+ if (name)
+ *name = fdt_get_name(blob, offset, NULL);
+
+ if (compatiblesp) {
+ const char **compatibles = NULL;
+ const char *start, *end, *ptr;
+ unsigned int count = 0;
+
+ prop = fdt_getprop(blob, offset, "compatible", &len);
+ if (!prop)
+ goto skip_compat;
+
+ start = ptr = (const char *)prop;
+ end = start + len;
+
+ while (ptr < end) {
+ ptr = strchrnul(ptr, '\0');
+ count++;
+ ptr++;
+ }
+
+ compatibles = malloc(sizeof(ptr) * count);
+ if (!compatibles)
+ return -FDT_ERR_INTERNAL;
+
+ ptr = start;
+ count = 0;
+
+ while (ptr < end) {
+ compatibles[count] = ptr;
+ ptr = strchrnul(ptr, '\0');
+ count++;
+ ptr++;
+ }
+
+skip_compat:
+ *compatiblesp = compatibles;
+
+ if (countp)
+ *countp = count;
+ }
+
carveout->start = fdtdec_get_addr_size_auto_noparent(blob, offset,
"reg", 0, &size,
true);
carveout->end = carveout->start + size - 1;
+ if (flags) {
+ *flags = 0;
+
+ if (fdtdec_get_bool(blob, offset, "no-map"))
+ *flags |= FDTDEC_RESERVED_MEMORY_NO_MAP;
+ }
+
return 0;
}
int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name,
- unsigned int index, const char *name,
- const struct fdt_memory *carveout)
+ unsigned int index, const struct fdt_memory *carveout,
+ const char *name, const char **compatibles,
+ unsigned int count, unsigned long flags)
{
uint32_t phandle;
int err, offset, len;
fdt32_t value;
void *prop;
- err = fdtdec_add_reserved_memory(blob, name, carveout, &phandle, false);
+ err = fdtdec_add_reserved_memory(blob, name, carveout, compatibles,
+ count, &phandle, flags);
if (err < 0) {
debug("failed to add reserved memory: %d\n", err);
return err;
puts("Failed to read control FDT\n");
return -1;
}
-# elif defined(CONFIG_OF_PRIOR_STAGE)
- gd->fdt_blob = (void *)(uintptr_t)prior_stage_fdt_address;
# endif
# ifndef CONFIG_SPL_BUILD
/* Allow the early environment to override the fdt address */
offset = CHECK(fdt_add_subnode(fdt, 0, name + 1));
CHECK(fdt_setprop(fdt, offset, "reg", cells, (na + ns) * sizeof(*cells)));
- return fdtdec_set_carveout(fdt, name, "memory-region", 0,
- "framebuffer", &carveout);
+ return fdtdec_set_carveout(fdt, name, "memory-region", 0, &carveout,
+ "framebuffer", NULL, 0, 0);
}
static int check_fdt_carveout(void *fdt, uint32_t address_cells,
printf("carveout: %pap-%pap na=%u ns=%u: ", &expected.start,
&expected.end, address_cells, size_cells);
- CHECK(fdtdec_get_carveout(fdt, name, "memory-region", 0, &carveout));
+ CHECK(fdtdec_get_carveout(fdt, name, "memory-region", 0, &carveout,
+ NULL, NULL, NULL, NULL));
if ((carveout.start != expected.start) ||
(carveout.end != expected.end)) {
#ifdef CONFIG_CMD_UNZIP
__weak
-void gzwrite_progress_init(u64 expectedsize)
+void gzwrite_progress_init(ulong expectedsize)
{
putc('\n');
}
__weak
void gzwrite_progress(int iteration,
- u64 bytes_written,
- u64 total_bytes)
+ ulong bytes_written,
+ ulong total_bytes)
{
if (0 == (iteration & 3))
- printf("%llu/%llu\r", bytes_written, total_bytes);
+ printf("%lu/%lu\r", bytes_written, total_bytes);
}
__weak
void gzwrite_progress_finish(int returnval,
- u64 bytes_written,
- u64 total_bytes,
+ ulong bytes_written,
+ ulong total_bytes,
u32 expected_crc,
u32 calculated_crc)
{
if (0 == returnval) {
- printf("\n\t%llu bytes, crc 0x%08x\n",
+ printf("\n\t%lu bytes, crc 0x%08x\n",
total_bytes, calculated_crc);
} else {
- printf("\n\tuncompressed %llu of %llu\n"
+ printf("\n\tuncompressed %lu of %lu\n"
"\tcrcs == 0x%08x/0x%08x\n",
bytes_written, total_bytes,
expected_crc, calculated_crc);
int gzwrite(unsigned char *src, int len,
struct blk_desc *dev,
unsigned long szwritebuf,
- u64 startoffs,
- u64 szexpected)
+ ulong startoffs,
+ ulong szexpected)
{
int i, flags;
z_stream s;
int r = 0;
unsigned char *writebuf;
unsigned crc = 0;
- u64 totalfilled = 0;
+ ulong totalfilled = 0;
lbaint_t blksperbuf, outblock;
u32 expected_crc;
u32 payload_size;
}
if (startoffs & (dev->blksz-1)) {
- printf("%s: start offset %llu not a multiple of %lu\n",
+ printf("%s: start offset %lu not a multiple of %lu\n",
__func__, startoffs, dev->blksz);
return -1;
}
if (szexpected == 0) {
szexpected = le32_to_cpu(szuncompressed);
} else if (szuncompressed != (u32)szexpected) {
- printf("size of %llx doesn't match trailer low bits %x\n",
+ printf("size of %lx doesn't match trailer low bits %x\n",
szexpected, szuncompressed);
return -1;
}
if (lldiv(szexpected, dev->blksz) > (dev->lba - outblock)) {
- printf("%s: uncompressed size %llu exceeds device size\n",
+ printf("%s: uncompressed size %lu exceeds device size\n",
__func__, szexpected);
return -1;
}
#include <image.h>
int hash_calculate(const char *name,
- const struct image_region region[],
+ const struct image_region *region,
int region_count, uint8_t *checksum)
{
struct hash_algo *algo;
arch_lmb_reserve(lmb);
board_lmb_reserve(lmb);
- if (IMAGE_ENABLE_OF_LIBFDT && fdt_blob)
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && fdt_blob)
boot_fdt_add_mem_rsv_regions(lmb, fdt_blob);
}
#include <common.h>
#include <compiler.h>
#include <image.h>
-#include <lz4.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/unaligned.h>
+#include <u-boot/lz4.h>
static u16 LZ4_readLE16(const void *src)
{
.start = res.start,
.end = res.end,
};
+ unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
char *oldname, *nodename, *tmp;
oldname = strdup(name);
ret = fdtdec_add_reserved_memory(new_blob,
nodename,
&carveout,
- NULL, true);
+ NULL, 0,
+ NULL, flags);
free(oldname);
if (ret < 0)
goto err_sign;
}
-#ifdef CONFIG_FIT_RSASSA_PSS
- if (padding_algo && !strcmp(padding_algo->name, "pss")) {
+ if (CONFIG_IS_ENABLED(FIT_RSASSA_PSS) && padding_algo &&
+ !strcmp(padding_algo->name, "pss")) {
if (EVP_PKEY_CTX_set_rsa_padding(ckey,
RSA_PKCS1_PSS_PADDING) <= 0) {
ret = rsa_err("Signer padding setup failed");
goto err_sign;
}
}
-#endif /* CONFIG_FIT_RSASSA_PSS */
for (i = 0; i < region_count; i++) {
if (!EVP_DigestSignUpdate(context, region[i].data,
};
#endif
-#ifdef CONFIG_FIT_RSASSA_PSS
+#if CONFIG_IS_ENABLED(FIT_RSASSA_PSS)
static void u32_i2osp(uint32_t val, uint8_t *buf)
{
buf[0] = (uint8_t)((val >> 24) & 0xff);
#endif
-#if CONFIG_IS_ENABLED(FIT_SIGNATURE) || CONFIG_IS_ENABLED(RSA_VERIFY_WITH_PKEY)
/**
* rsa_verify_key() - Verify a signature against some data using RSA Key
*
return 0;
}
-#endif
-#if CONFIG_IS_ENABLED(RSA_VERIFY_WITH_PKEY)
/**
* rsa_verify_with_pkey() - Verify a signature against some data using
* only modulus and exponent as RSA key properties.
struct key_prop *prop;
int ret;
+ if (!CONFIG_IS_ENABLED(RSA_VERIFY_WITH_PKEY))
+ return -EACCES;
+
/* Public key is self-described to fill key_prop */
ret = rsa_gen_key_prop(info->key, info->keylen, &prop);
if (ret) {
return ret;
}
-#else
-int rsa_verify_with_pkey(struct image_sign_info *info,
- const void *hash, uint8_t *sig, uint sig_len)
-{
- return -EACCES;
-}
-#endif
#if CONFIG_IS_ENABLED(FIT_SIGNATURE)
/**
}
#endif
+char *memdup(const void *src, size_t len)
+{
+ char *p;
+
+ p = malloc(len);
+ if (!p)
+ return NULL;
+
+ memcpy(p, src, len);
+
+ return p;
+}
+
#ifndef __HAVE_ARCH_STRSTR
/**
* strstr - Find the first substring in a %NUL terminated string
obj-y += zstd_decompress.o
zstd_decompress-y := huf_decompress.o decompress.o \
- entropy_common.o fse_decompress.o zstd_common.o
+ entropy_common.o fse_decompress.o zstd_common.o zstd.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Google LLC
+ */
+
+#define LOG_CATEGORY LOGC_BOOT
+
+#include <common.h>
+#include <abuf.h>
+#include <log.h>
+#include <malloc.h>
+#include <linux/zstd.h>
+
+int zstd_decompress(struct abuf *in, struct abuf *out)
+{
+ ZSTD_DStream *dstream;
+ ZSTD_inBuffer in_buf;
+ ZSTD_outBuffer out_buf;
+ void *workspace;
+ size_t wsize;
+ int ret;
+
+ wsize = ZSTD_DStreamWorkspaceBound(abuf_size(in));
+ workspace = malloc(wsize);
+ if (!workspace) {
+ debug("%s: cannot allocate workspace of size %zu\n", __func__,
+ wsize);
+ return -ENOMEM;
+ }
+
+ dstream = ZSTD_initDStream(abuf_size(in), workspace, wsize);
+ if (!dstream) {
+ log_err("%s: ZSTD_initDStream failed\n", __func__);
+ ret = -EPERM;
+ goto do_free;
+ }
+
+ in_buf.src = abuf_data(in);
+ in_buf.pos = 0;
+ in_buf.size = abuf_size(in);
+
+ out_buf.dst = abuf_data(out);
+ out_buf.pos = 0;
+ out_buf.size = abuf_size(out);
+
+ while (1) {
+ size_t res;
+
+ res = ZSTD_decompressStream(dstream, &out_buf, &in_buf);
+ if (ZSTD_isError(res)) {
+ ret = ZSTD_getErrorCode(res);
+ log_err("ZSTD_decompressStream error %d\n", ret);
+ goto do_free;
+ }
+
+ if (in_buf.pos >= abuf_size(in) || !res)
+ break;
+ }
+
+ ret = out_buf.pos;
+do_free:
+ free(workspace);
+ return ret;
+}
# added for U-Boot
binutils-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/binutils-version.sh $(AS))
+dtc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/dtc-version.sh $(DTC))
# cc-ldoption
# Usage: ldflags += $(call cc-ldoption, -Wl$(comma)--hash-style=both)
# Let clean descend into subdirs
subdir- += basic kconfig
-subdir-$(CONFIG_DTC) += dtc
CONFIG_BOARD_NAME
CONFIG_BOARD_POSTCLK_INIT
CONFIG_BOARD_SIZE_LIMIT
-CONFIG_BOOGER
CONFIG_BOOTFILE
CONFIG_BOOTMODE
-CONFIG_BOOTP_
CONFIG_BOOTP_BOOTFILESIZE
CONFIG_BOOTP_DHCP_REQUEST_DELAY
CONFIG_BOOTP_ID_CACHE_SIZE
CONFIG_CM_SPD_DETECT
CONFIG_CM_TCRAM
CONFIG_COLDFIRE
-CONFIG_COMMANDS
CONFIG_COMMON_BOOT
CONFIG_COMPAT
CONFIG_CONS_EXTC_PINSEL
CONFIG_CONS_EXTC_RATE
-CONFIG_CONS_NONE
CONFIG_CONS_ON_SCC
CONFIG_CONS_SCIF0
CONFIG_CONS_SCIF1
CONFIG_DP_DDR_CTRL
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR
CONFIG_DP_DDR_NUM_CTRLS
-CONFIG_DRAM_TIMINGS_
CONFIG_DRIVER_DM9000
CONFIG_DSP_CLUSTER_START
CONFIG_DWCDDR21MCTL
CONFIG_EFLASH_PROTSECTORS
CONFIG_EHCI_DESC_BIG_ENDIAN
CONFIG_EHCI_HCD_INIT_AFTER_RESET
-CONFIG_EHCI_IS_TDI
CONFIG_EHCI_MMIO_BIG_ENDIAN
CONFIG_EHCI_MXS_PORT0
CONFIG_EHCI_MXS_PORT1
CONFIG_ENV_FLAGS_LIST_DEFAULT
CONFIG_ENV_FLAGS_LIST_STATIC
CONFIG_ENV_IS_EMBEDDED
-CONFIG_ENV_IS_IN_
CONFIG_ENV_MAX_ENTRIES
CONFIG_ENV_MIN_ENTRIES
CONFIG_ENV_OFFSET_OOB
CONFIG_HITACHI_SX14
CONFIG_HOSTNAME
CONFIG_HOST_MAX_DEVICES
-CONFIG_HOTPLUG
CONFIG_HPS_ALTERAGRP_DBGATCLK
CONFIG_HPS_ALTERAGRP_MAINCLK
CONFIG_HPS_ALTERAGRP_MPUCLK
CONFIG_IMX_HDMI
CONFIG_IMX_VIDEO_SKIP
CONFIG_INETSPACE_V2
-CONFIG_INIT_IGNORE_ERROR
CONFIG_INI_ALLOW_MULTILINE
CONFIG_INI_CASE_INSENSITIVE
CONFIG_INI_MAX_LINE
CONFIG_MTD_UBI_GLUEBI
CONFIG_MTD_UBI_MODULE
CONFIG_MULTI_CS
-CONFIG_MUSB_HOST
CONFIG_MVGBE_PORTS
CONFIG_MVMFP_V2
CONFIG_MVS
CONFIG_NORBOOT
CONFIG_NORFLASH_PS32BIT
CONFIG_NO_ETH
-CONFIG_NO_RELOCATION
CONFIG_NO_WAIT
CONFIG_NS16550_MIN_FUNCTIONS
CONFIG_NS8382X
CONFIG_NUM_PAMU
CONFIG_ODROID_REV_AIN
CONFIG_OFF_PADCONF
-CONFIG_OF_
CONFIG_ORIGEN
CONFIG_OTHBOOTARGS
CONFIG_OVERWRITE_ETHADDR_ONCE
CONFIG_REALMODE_DEBUG
CONFIG_RED_LED
CONFIG_REG
-CONFIG_REG_0
-CONFIG_REG_2
-CONFIG_REG_3
-CONFIG_REG_8
CONFIG_REMAKE_ELF
CONFIG_REQ
CONFIG_RESERVED_01_BASE
CONFIG_SMSTP9_ENA
CONFIG_SOCRATES
CONFIG_SOC_OMAP3430
-CONFIG_SOFT_I2C_GPIO_SCL
-CONFIG_SOFT_I2C_GPIO_SDA
CONFIG_SOFT_I2C_READ_REPEATED_START
CONFIG_SPD_EEPROM
CONFIG_SPIFLASH
CONFIG_SPI_HALF_DUPLEX
CONFIG_SPI_IDLE_VAL
CONFIG_SPI_N25Q256A_RESET
-CONFIG_SPL_
CONFIG_SPL_ATMEL_SIZE
CONFIG_SPL_BOARD_LOAD_IMAGE
CONFIG_SPL_BOOTROM_SAVE
CONFIG_STANDALONE_LOAD_ADDR
CONFIG_STATIC_BOARD_REV
CONFIG_STD_DEVICES_SETTINGS
-CONFIG_STM32_FLASH
-CONFIG_STV0991
-CONFIG_STV0991_HZ
-CONFIG_STV0991_HZ_CLOCK
CONFIG_SXNI855T
CONFIG_SYSFS
CONFIG_SYSMGR_ISWGRP_HANDOFF
CONFIG_SYS_FLASH1_BASE_PHYS
CONFIG_SYS_FLASH1_BASE_PHYS_EARLY
CONFIG_SYS_FLASHBOOT
-CONFIG_SYS_FLASH_AMD_CHECK_DQ7
CONFIG_SYS_FLASH_AUTOPROTECT_LIST
CONFIG_SYS_FLASH_BANKS_LIST
CONFIG_SYS_FLASH_BANKS_SIZES
CONFIG_SYS_MMC_U_BOOT_OFFS
CONFIG_SYS_MMC_U_BOOT_SIZE
CONFIG_SYS_MMC_U_BOOT_START
-CONFIG_SYS_MONITOR_
CONFIG_SYS_MONITOR_BASE
CONFIG_SYS_MONITOR_LEN
CONFIG_SYS_MONITOR_SEC
CONFIG_USB_EHCI_BASE_LIST
CONFIG_USB_EHCI_EXYNOS
CONFIG_USB_EHCI_FARADAY
-CONFIG_USB_EHCI_KIRKWOOD
-CONFIG_USB_EHCI_MXS
CONFIG_USB_EHCI_TXFIFO_THRESH
CONFIG_USB_ETH_QMULT
CONFIG_USB_ETH_SUBSET
CONFIG_USB_TUSB_OMAP_DMA
CONFIG_USB_ULPI_TIMEOUT
CONFIG_USB_XHCI_EXYNOS
-CONFIG_USER_LOWLEVEL_INIT
CONFIG_USE_INTERRUPT
CONFIG_USE_ONENAND_BOARD_INIT
CONFIG_UTBIPAR_INIT_TBIPA
CONFIG_VIDEO_BMP_LOGO
CONFIG_VIDEO_DA8XX
CONFIG_VIDEO_FONT_4X6
-CONFIG_VIDEO_LCD_I2C_BUS
CONFIG_VIDEO_LOGO
-CONFIG_VIDEO_MXS
CONFIG_VIDEO_MXS_MODE_SYSTEM
CONFIG_VIDEO_STD_TIMINGS
CONFIG_VID_FLS_ENV
--- /dev/null
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0+
+#
+# dtc-version dtc-command
+#
+# Prints the dtc version of `dtc-command' in a canonical 6-digit form
+# such as `010404' for dtc 1.4.4
+#
+
+dtc="$*"
+
+if [ ${#dtc} -eq 0 ]; then
+ echo "Error: No dtc command specified"
+ printf "Usage:\n\t$0 <dtc-command>\n"
+ exit 1
+fi
+
+if ! which $dtc >/dev/null ; then
+ echo "Error: Cannot find dtc: $dtc"
+ exit 1
+fi
+
+MAJOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 1)
+MINOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 2)
+PATCH=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 3 | cut -d - -f 1)
+
+printf "%02d%02d%02d\\n" $MAJOR $MINOR $PATCH
#include <gzip.h>
#include <image.h>
#include <log.h>
-#include <lz4.h>
#include <malloc.h>
#include <mapmem.h>
#include <asm/io.h>
+#include <u-boot/lz4.h>
#include <u-boot/zlib.h>
#include <bzlib.h>
resv.start = 0x1000;
resv.end = 0x2000;
- ut_assertok(fdtdec_set_carveout(blob, "/a-test",
- "memory-region", 2, "test_resv1",
- &resv));
+ ut_assertok(fdtdec_set_carveout(blob, "/a-test", "memory-region", 2,
+ &resv, "test_resv1", NULL, 0, 0));
resv.start = 0x10000;
resv.end = 0x20000;
- ut_assertok(fdtdec_set_carveout(blob, "/a-test",
- "memory-region", 1, "test_resv2",
- &resv));
+ ut_assertok(fdtdec_set_carveout(blob, "/a-test", "memory-region", 1,
+ &resv, "test_resv2", NULL, 0, 0));
resv.start = 0x100000;
resv.end = 0x200000;
- ut_assertok(fdtdec_set_carveout(blob, "/a-test",
- "memory-region", 0, "test_resv3",
- &resv));
+ ut_assertok(fdtdec_set_carveout(blob, "/a-test", "memory-region", 0,
+ &resv, "test_resv3", NULL, 0, 0));
offset = fdt_path_offset(blob, "/a-test");
ut_assert(offset > 0);
fdt_addr_t addr;
fdt_size_t size;
void *blob;
+ unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
int blob_sz, parent, subnode;
uint32_t phandle, phandle1;
/* Insert a memory region in /reserved-memory node */
resv.start = 0x1000;
resv.end = 0x1fff;
- ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region",
- &resv, &phandle, false));
+ ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region", &resv,
+ NULL, 0, &phandle, 0));
/* Test /reserve-memory and its subnode should exist */
parent = fdt_path_offset(blob, "/reserved-memory");
resv.start = 0x2000;
resv.end = 0x2fff;
- ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region1",
- &resv, &phandle1, true));
+ ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region1", &resv,
+ NULL, 0, &phandle1, flags));
subnode = fdt_path_offset(blob, "/reserved-memory/rsvd_region1");
ut_assert(subnode > 0);
*/
resv.start = 0x1000;
resv.end = 0x1fff;
- ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region2",
- &resv, &phandle1, false));
+ ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region2", &resv,
+ NULL, 0, &phandle1, 0));
subnode = fdt_path_offset(blob, "/reserved-memory/rsvd_region2");
ut_assert(subnode < 0);
&theirs));
ut_asserteq(-EINVAL, k210_pll_calc_config(1500000000, 20000000,
&theirs));
+ ut_asserteq(-EINVAL, k210_pll_calc_config(1750000000, 13300000,
+ &theirs));
/* Verify we get the same output with brute-force */
- ut_assertok(dm_test_k210_pll_calc_config(390000000, 26000000, &ours));
- ut_assertok(k210_pll_calc_config(390000000, 26000000, &theirs));
- ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
-
- ut_assertok(dm_test_k210_pll_calc_config(26000000, 390000000, &ours));
- ut_assertok(k210_pll_calc_config(26000000, 390000000, &theirs));
- ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
-
- ut_assertok(dm_test_k210_pll_calc_config(400000000, 26000000, &ours));
- ut_assertok(k210_pll_calc_config(400000000, 26000000, &theirs));
- ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
-
- ut_assertok(dm_test_k210_pll_calc_config(27000000, 26000000, &ours));
- ut_assertok(k210_pll_calc_config(27000000, 26000000, &theirs));
- ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
-
- ut_assertok(dm_test_k210_pll_calc_config(26000000, 27000000, &ours));
- ut_assertok(k210_pll_calc_config(26000000, 27000000, &theirs));
- ut_assertok(dm_test_k210_pll_compare(&ours, &theirs));
+#define compare(rate, rate_in) do { \
+ ut_assertok(dm_test_k210_pll_calc_config(rate, rate_in, &ours)); \
+ ut_assertok(k210_pll_calc_config(rate, rate_in, &theirs)); \
+ ut_assertok(dm_test_k210_pll_compare(&ours, &theirs)); \
+} while (0)
+
+ compare(390000000, 26000000);
+ compare(26000000, 390000000);
+ compare(400000000, 26000000);
+ compare(27000000, 26000000);
+ compare(26000000, 27000000);
+ compare(13300000 * 64, 13300000);
+ compare(21250000, 21250000 * 70);
+ compare(21250000, 1750000000);
+ compare(1750000000, 1750000000);
return 0;
}
const char *bind_flag = ofnode_read_string(ofnode, "bind");
if (bind_flag && (strcmp(bind_flag, "True") == 0))
- lists_bind_fdt(parent, ofnode, &dev, false);
+ lists_bind_fdt(parent, ofnode, &dev, NULL, false);
ofnode = dev_read_next_subnode(ofnode);
}
# (C) Copyright 2018
# Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
obj-y += cmd_ut_lib.o
+obj-y += abuf.o
obj-$(CONFIG_EFI_LOADER) += efi_device_path.o
obj-$(CONFIG_EFI_SECURE_BOOT) += efi_image_region.o
obj-y += hexdump.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <abuf.h>
+#include <mapmem.h>
+#include <test/lib.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+static char test_data[] = "1234";
+#define TEST_DATA_LEN sizeof(test_data)
+
+/* Test abuf_set() */
+static int lib_test_abuf_set(struct unit_test_state *uts)
+{
+ struct abuf buf;
+ ulong start;
+
+ start = ut_check_free();
+
+ abuf_init(&buf);
+ abuf_set(&buf, test_data, TEST_DATA_LEN);
+ ut_asserteq_ptr(test_data, buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Force it to allocate */
+ ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN + 1));
+ ut_assertnonnull(buf.data);
+ ut_asserteq(TEST_DATA_LEN + 1, buf.size);
+ ut_asserteq(true, buf.alloced);
+
+ /* Now set it again, to force it to free */
+ abuf_set(&buf, test_data, TEST_DATA_LEN);
+ ut_asserteq_ptr(test_data, buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_set, 0);
+
+/* Test abuf_map_sysmem() */
+static int lib_test_abuf_map_sysmem(struct unit_test_state *uts)
+{
+ struct abuf buf;
+ ulong addr;
+
+ abuf_init(&buf);
+ addr = 0x100;
+ abuf_map_sysmem(&buf, addr, TEST_DATA_LEN);
+
+ ut_asserteq_ptr(map_sysmem(0x100, 0), buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_map_sysmem, 0);
+
+/* Test abuf_realloc() */
+static int lib_test_abuf_realloc(struct unit_test_state *uts)
+{
+ struct abuf buf;
+ ulong start;
+ void *ptr;
+
+ /*
+ * TODO: crashes on sandbox sometimes due to an apparent bug in
+ * realloc().
+ */
+ return 0;
+
+ start = ut_check_free();
+
+ abuf_init(&buf);
+
+ /* Allocate an empty buffer */
+ ut_asserteq(true, abuf_realloc(&buf, 0));
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Allocate a non-empty abuf */
+ ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN));
+ ut_assertnonnull(buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(true, buf.alloced);
+ ptr = buf.data;
+
+ /*
+ * Make it smaller; the pointer should remain the same. Note this relies
+ * on knowledge of how U-Boot's realloc() works
+ */
+ ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN - 1));
+ ut_asserteq(TEST_DATA_LEN - 1, buf.size);
+ ut_asserteq(true, buf.alloced);
+ ut_asserteq_ptr(ptr, buf.data);
+
+ /*
+ * Make it larger, forcing reallocation. Note this relies on knowledge
+ * of how U-Boot's realloc() works
+ */
+ ut_asserteq(true, abuf_realloc(&buf, 0x1000));
+ ut_assert(buf.data != ptr);
+ ut_asserteq(0x1000, buf.size);
+ ut_asserteq(true, buf.alloced);
+
+ /* Free it */
+ ut_asserteq(true, abuf_realloc(&buf, 0));
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_realloc, 0);
+
+/* Test handling of buffers that are too large */
+static int lib_test_abuf_large(struct unit_test_state *uts)
+{
+ struct abuf buf;
+ ulong start;
+ size_t size;
+ int delta;
+ void *ptr;
+
+ /*
+ * This crashes at present due to trying to allocate more memory than
+ * available, which breaks something on sandbox.
+ */
+ return 0;
+
+ start = ut_check_free();
+
+ /* Try an impossible size */
+ abuf_init(&buf);
+ ut_asserteq(false, abuf_realloc(&buf, CONFIG_SYS_MALLOC_LEN));
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ abuf_uninit(&buf);
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Start with a normal size then try to increase it, to check realloc */
+ ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN));
+ ut_assertnonnull(buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(true, buf.alloced);
+ ptr = buf.data;
+ delta = ut_check_delta(start);
+ ut_assert(delta > 0);
+
+ /* try to increase it */
+ ut_asserteq(false, abuf_realloc(&buf, CONFIG_SYS_MALLOC_LEN));
+ ut_asserteq_ptr(ptr, buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(true, buf.alloced);
+ ut_asserteq(delta, ut_check_delta(start));
+
+ /* Check for memory leaks */
+ abuf_uninit(&buf);
+ ut_assertok(ut_check_delta(start));
+
+ /* Start with a huge unallocated buf and try to move it */
+ abuf_init(&buf);
+ abuf_map_sysmem(&buf, 0, CONFIG_SYS_MALLOC_LEN);
+ ut_asserteq(CONFIG_SYS_MALLOC_LEN, buf.size);
+ ut_asserteq(false, buf.alloced);
+ ut_assertnull(abuf_uninit_move(&buf, &size));
+
+ /* Check for memory leaks */
+ abuf_uninit(&buf);
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_large, 0);
+
+/* Test abuf_uninit_move() */
+static int lib_test_abuf_uninit_move(struct unit_test_state *uts)
+{
+ void *ptr, *orig_ptr;
+ struct abuf buf;
+ size_t size;
+ ulong start;
+ int delta;
+
+ start = ut_check_free();
+
+ /*
+ * TODO: crashes on sandbox sometimes due to an apparent bug in
+ * realloc().
+ */
+ return 0;
+
+ /* Move an empty buffer */
+ abuf_init(&buf);
+ ut_assertnull(abuf_uninit_move(&buf, &size));
+ ut_asserteq(0, size);
+ ut_assertnull(abuf_uninit_move(&buf, NULL));
+
+ /* Move an unallocated buffer */
+ abuf_set(&buf, test_data, TEST_DATA_LEN);
+ ut_assertok(ut_check_delta(start));
+ ptr = abuf_uninit_move(&buf, &size);
+ ut_asserteq(TEST_DATA_LEN, size);
+ ut_asserteq_str(ptr, test_data);
+ ut_assertnonnull(ptr);
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Check that freeing it frees the only allocation */
+ delta = ut_check_delta(start);
+ ut_assert(delta > 0);
+ free(ptr);
+ ut_assertok(ut_check_delta(start));
+
+ /* Move an allocated buffer */
+ ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN));
+ orig_ptr = buf.data;
+ strcpy(orig_ptr, test_data);
+
+ delta = ut_check_delta(start);
+ ut_assert(delta > 0);
+ ptr = abuf_uninit_move(&buf, &size);
+ ut_asserteq(TEST_DATA_LEN, size);
+ ut_assertnonnull(ptr);
+ ut_asserteq_ptr(ptr, orig_ptr);
+ ut_asserteq_str(ptr, test_data);
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Check there was no new allocation */
+ ut_asserteq(delta, ut_check_delta(start));
+
+ /* Check that freeing it frees the only allocation */
+ free(ptr);
+ ut_assertok(ut_check_delta(start));
+
+ /* Move an unallocated buffer, without the size */
+ abuf_set(&buf, test_data, TEST_DATA_LEN);
+ ut_assertok(ut_check_delta(start));
+ ptr = abuf_uninit_move(&buf, NULL);
+ ut_asserteq_str(ptr, test_data);
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_uninit_move, 0);
+
+/* Test abuf_uninit() */
+static int lib_test_abuf_uninit(struct unit_test_state *uts)
+{
+ struct abuf buf;
+
+ /* Nothing in the buffer */
+ abuf_init(&buf);
+ abuf_uninit(&buf);
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Not allocated */
+ abuf_set(&buf, test_data, TEST_DATA_LEN);
+ abuf_uninit(&buf);
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_uninit, 0);
+
+/* Test abuf_init_set() */
+static int lib_test_abuf_init_set(struct unit_test_state *uts)
+{
+ struct abuf buf;
+
+ abuf_init_set(&buf, test_data, TEST_DATA_LEN);
+ ut_asserteq_ptr(test_data, buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_init_set, 0);
+
+/* Test abuf_init_move() */
+static int lib_test_abuf_init_move(struct unit_test_state *uts)
+{
+ struct abuf buf;
+ void *ptr;
+
+ /*
+ * TODO: crashes on sandbox sometimes due to an apparent bug in
+ * realloc().
+ */
+ return 0;
+
+ ptr = strdup(test_data);
+ ut_assertnonnull(ptr);
+
+ free(ptr);
+
+ abuf_init_move(&buf, ptr, TEST_DATA_LEN);
+ ut_asserteq_ptr(ptr, abuf_data(&buf));
+ ut_asserteq(TEST_DATA_LEN, abuf_size(&buf));
+ ut_asserteq(true, buf.alloced);
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_init_move, 0);
+
+/* Test abuf_init() */
+static int lib_test_abuf_init(struct unit_test_state *uts)
+{
+ struct abuf buf;
+
+ buf.data = &buf;
+ buf.size = 123;
+ buf.alloced = true;
+ abuf_init(&buf);
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_init, 0);
/* Allow for copying up to 32 bytes */
#define BUFLEN (SWEEP + 33)
+#define TEST_STR "hello"
+
/**
* init_buffer() - initialize buffer
*
}
LIB_TEST(lib_memmove, 0);
+
+/** lib_memdup() - unit test for memdup() */
+static int lib_memdup(struct unit_test_state *uts)
+{
+ char buf[BUFLEN];
+ size_t len;
+ char *p, *q;
+
+ /* Zero size should do nothing */
+ p = memdup(NULL, 0);
+ ut_assertnonnull(p);
+ free(p);
+
+ p = memdup(buf, 0);
+ ut_assertnonnull(p);
+ free(p);
+
+ strcpy(buf, TEST_STR);
+ len = sizeof(TEST_STR);
+ p = memdup(buf, len);
+ ut_asserteq_mem(p, buf, len);
+
+ q = memdup(p, len);
+ ut_asserteq_mem(q, buf, len);
+ free(q);
+ free(p);
+
+ return 0;
+}
+LIB_TEST(lib_memdup, 0);
# argv; py.test test_directory_name user-supplied-arguments
args = [os.path.dirname(__file__) + '/tests']
args.extend(sys.argv)
+
+ # Use short format by default
+ if not [arg for arg in args if '--tb=' in arg]:
+ args.append('--tb=short')
+
sys.exit(pytest.main(args))
assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, False)
assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True)
+ #bind usb_ether driver (which has no compatible) to usb@1 node.
+ ##New entry usb_ether should appear in the dm tree
+ response = u_boot_console.run_command('bind /usb@1 usb_ether')
+ assert response == ''
+ tree = u_boot_console.run_command('dm tree')
+ assert in_tree(tree, 'usb@1', 'ethernet', 'usb_ether', 1, True)
+
#Unbind child #1. No error expected and all devices should be there except for bind-test-child1
response = u_boot_console.run_command('unbind /bind-test/bind-test-child1')
assert response == ''
"""
self.waited = False
+ self.exit_code = 0
+ self.exit_info = ''
self.buf = ''
self.output = ''
self.logfile_read = None
os.kill(self.pid, sig)
- def isalive(self):
+ def checkalive(self):
"""Determine whether the child process is still running.
- Args:
- None.
-
Returns:
- Boolean indicating whether process is alive.
+ tuple:
+ True if process is alive, else False
+ 0 if process is alive, else exit code of process
+ string describing what happened ('' or 'status/signal n')
"""
if self.waited:
- return False
+ return False, self.exit_code, self.exit_info
w = os.waitpid(self.pid, os.WNOHANG)
if w[0] == 0:
- return True
-
+ return True, 0, 'running'
+ status = w[1]
+
+ if os.WIFEXITED(status):
+ self.exit_code = os.WEXITSTATUS(status)
+ self.exit_info = 'status %d' % self.exit_code
+ elif os.WIFSIGNALED(status):
+ signum = os.WTERMSIG(status)
+ self.exit_code = -signum
+ self.exit_info = 'signal %d (%s)' % (signum, signal.Signals(signum))
self.waited = True
- return False
+ return False, self.exit_code, self.exit_info
+
+ def isalive(self):
+ """Determine whether the child process is still running.
+
+ Args:
+ None.
+
+ Returns:
+ Boolean indicating whether process is alive.
+ """
+ return self.checkalive()[0]
def send(self, data):
"""Send data to the sub-process's stdin.
events = self.poll.poll(poll_maxwait)
if not events:
raise Timeout()
- c = os.read(self.fd, 1024).decode(errors='replace')
- if not c:
- raise EOFError()
+ try:
+ c = os.read(self.fd, 1024).decode(errors='replace')
+ except OSError as err:
+ # With sandbox, try to detect when U-Boot exits when it
+ # shouldn't and explain why. This is much more friendly than
+ # just dying with an I/O error
+ if err.errno == 5: # Input/output error
+ alive, exit_code, info = self.checkalive()
+ if alive:
+ raise
+ else:
+ raise ValueError('U-Boot exited with %s' % info)
+ else:
+ raise
if self.logfile_read:
self.logfile_read.write(c)
self.buf += c
some cases the system dtc may not support all required features
and the path to a different version should be given here.
+config TOOLS_CRC32
+ def_bool y
+ help
+ Enable CRC32 support in the tools builds
+
config TOOLS_LIBCRYPTO
bool "Use OpenSSL's libcrypto library for host tools"
default y
This selection does not affect target features, such as runtime FIT
signature verification.
+config TOOLS_FIT
+ def_bool y
+ help
+ Enable FIT support in the tools builds.
+
+config TOOLS_FIT_FULL_CHECK
+ def_bool y
+ help
+ Do a full check of the FIT before using it in the tools builds
+
+config TOOLS_FIT_PRINT
+ def_bool y
+ help
+ Print the content of the FIT verbosely in the tools builds
+
+config TOOLS_FIT_RSASSA_PSS
+ def_bool y
+ help
+ Support the rsassa-pss signature scheme in the tools builds
+
+config TOOLS_FIT_SIGNATURE
+ def_bool y
+ help
+ Enable signature verification of FIT uImages in the tools builds
+
+config TOOLS_FIT_SIGNATURE_MAX_SIZE
+ hex
+ depends on TOOLS_FIT_SIGNATURE
+ default 0x10000000
+
+config TOOLS_FIT_VERBOSE
+ def_bool y
+ help
+ Support verbose FIT output in the tools builds
+
+config TOOLS_MD5
+ def_bool y
+ help
+ Enable MD5 support in the tools builds
+
+config TOOLS_OF_LIBFDT
+ def_bool y
+ help
+ Enable libfdt support in the tools builds
+
+config TOOLS_SHA1
+ def_bool y
+ help
+ Enable SHA1 support in the tools builds
+
+config TOOLS_SHA256
+ def_bool y
+ help
+ Enable SHA256 support in the tools builds
+
+config TOOLS_SHA384
+ def_bool y
+ help
+ Enable SHA384 support in the tools builds
+
+config TOOLS_SHA512
+ def_bool y
+ help
+ Enable SHA512 support in the tools builds
+
endmenu
lib/fdtdec_common.o \
lib/fdtdec.o \
common/image.o \
+ common/image-host.o \
imagetool.o \
imximage.o \
imx8image.o \
-I$(srctree)/tools \
-DUSE_HOSTCC \
-D__KERNEL_STRICT_NAMES \
- -D_GNU_SOURCE \
- -std=gnu99
+ -D_GNU_SOURCE
__build: $(LOGO-y)
inclusion' below.
-Using binman with OF_BOARD or OF_PRIOR_STAGE
+Using binman with OF_BOARD
--------------------------------------------
Normally binman is used with a board configured with OF_SEPARATE or OF_EMBED.
This is a typical scenario where a device tree source that contains the binman
node is provided in the arch/<arch>/dts directory for a specific board.
-However for a board configured with OF_BOARD or OF_PRIOR_STAGE, no device tree
-blob is provided in the U-Boot build phase hence the binman node information
-is not available. In order to support such use case, a new Kconfig option
-BINMAN_STANDALONE_FDT is introduced, to tell the build system that a standalone
-device tree blob containing binman node is explicitly required.
+However for a board configured with OF_BOARD, no device tree blob is provided
+in the U-Boot build phase hence the binman node information is not available.
+In order to support such use case, a new Kconfig option BINMAN_STANDALONE_FDT
+is introduced, to tell the build system that a standalone device tree blob
+containing binman node is explicitly required.
Note there is a Kconfig option BINMAN_FDT which enables U-Boot run time to
access information about binman entries, stored in the device tree in a binman
available as binman is invoked during the build phase, thus this option is not
turned on by default for these OF_CONTROL methods.
-See qemu-riscv64_spl_defconfig for an example of how binman is used with
-OF_PRIOR_STAGE to generate u-boot.itb image.
-
-
Access to binman entry offsets at run time (symbols)
----------------------------------------------------
# This Dockerfile is used to build an image containing basic stuff to be used
# to build U-Boot and run our test suites.
-FROM ubuntu:focal-20210827
+FROM ubuntu:focal-20210921
MAINTAINER Tom Rini <trini@konsulko.com>
LABEL Description=" This image is for building U-Boot inside a container"
# Add LLVM repository
RUN apt-get update && apt-get install -y gnupg2 wget xz-utils && rm -rf /var/lib/apt/lists/*
RUN wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add -
-RUN echo deb http://apt.llvm.org/focal/ llvm-toolchain-focal-12 main | tee /etc/apt/sources.list.d/llvm.list
+RUN echo deb http://apt.llvm.org/focal/ llvm-toolchain-focal-13 main | tee /etc/apt/sources.list.d/llvm.list
# Manually install the kernel.org "Crosstool" based toolchains for gcc-11.1.0
RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ
binutils-dev \
bison \
build-essential \
- clang-12 \
+ clang-13 \
coreutils \
cpio \
cppcheck \
/* Check that we have read all the file */
if (n != sbuf.st_size) {
- printf("Can't read all file %s (read %zd bytes, expexted %lld)\n",
+ printf("Can't read all file %s (read %zd bytes, expected %lld)\n",
filename, n, (long long)sbuf.st_size);
goto err;
}
projects / platform / kernel / u-boot.git / commitdiff