Merge git://git.denx.de/u-boot-mpc85xx

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index bfa63e4..38ea4c1 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -390,6 +390,7 @@ config ARCH_B4860
        select SYS_FSL_ERRATUM_A007075
        select SYS_FSL_ERRATUM_A007186
        select SYS_FSL_ERRATUM_A007212
+       select SYS_FSL_ERRATUM_A007907
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
@@ -855,6 +856,8 @@ config ARCH_T2080
        select SYS_FSL_ERRATUM_A006593
        select SYS_FSL_ERRATUM_A007186
        select SYS_FSL_ERRATUM_A007212
+       select SYS_FSL_ERRATUM_A007815
+       select SYS_FSL_ERRATUM_A007907
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_ESDHC111
        select SYS_FSL_HAS_DDR3
@@ -916,6 +919,8 @@ config ARCH_T4240
        select SYS_FSL_ERRATUM_A006593
        select SYS_FSL_ERRATUM_A007186
        select SYS_FSL_ERRATUM_A007798
+       select SYS_FSL_ERRATUM_A007815
+       select SYS_FSL_ERRATUM_A007907
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_HAS_DDR3
        select SYS_FSL_HAS_SEC
@@ -1103,9 +1108,15 @@ config SYS_FSL_ERRATUM_A007186
 config SYS_FSL_ERRATUM_A007212
        bool
 
+config SYS_FSL_ERRATUM_A007815
+       bool
+
 config SYS_FSL_ERRATUM_A007798
        bool
 
+config SYS_FSL_ERRATUM_A007907
+       bool
+
 config SYS_FSL_ERRATUM_A008044
        bool
 

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 54b5b33..b8be596 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -330,6 +330,12 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
        puts("Work-around for Erratum A009663 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
+       puts("Work-around for Erratum A007907 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
+       puts("Work-around for Erratum A007815 enabled\n");
+#endif
 
        return 0;
 }

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 822844d..f5bf67c 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -777,6 +777,13 @@ int cpu_init_r(void)
                sync();
        }
 #endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
+       flush_dcache();
+       mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
+       sync();
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
        /*
         * A-005812 workaround sets bit 32 of SPR 976 for SoCs running

diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index 8bee8ca..cad341e 100644 (file)
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -79,7 +79,9 @@ typedef struct ccsr_pci {
        u32     pme_msg_dis;    /* 0x024 - PCIE PME & message disable register */
        u32     pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */
        u32     pm_command;     /* 0x02c - PCIE PM Command register */
-       char    res4[3016];     /*     (- #xbf8  #x30)3016 */
+       char    res3[2188];     /*     (0x8bc - 0x30 = 2188) */
+       u32     dbi_ro_wr_en;   /* 0x8bc - DBI read only write enable reg */
+       char    res4[824];      /*     (0xbf8 - 0x8c0 = 824) */
        u32     block_rev1;     /* 0xbf8 - PCIE Block Revision register 1 */
        u32     block_rev2;     /* 0xbfc - PCIE Block Revision register 2 */
 

diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index fbf72bb..81bae6f 100644 (file)
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -501,6 +501,7 @@
 #define   L1CSR1_ICE           0x00000001      /* Instruction Cache Enable */
 #define SPRN_L1CSR2    0x25e   /* L1 Data Cache Control and Status Register 2 */
 #define   L1CSR2_DCWS          0x40000000      /* Data Cache Write Shadow */
+#define   L1CSR2_DCSTASHID  0x000003ff /* Data Cache Stash ID */
 #define SPRN_L2CSR0    0x3f9   /* L2 Data Cache Control and Status Register 0 */
 #define   L2CSR0_L2E           0x80000000      /* L2 Cache Enable */
 #define   L2CSR0_L2PE          0x40000000      /* L2 Cache Parity/ECC Enable */

diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S
index 66cf02d..ad28c7c 100644 (file)
--- a/arch/powerpc/lib/ppccache.S
+++ b/arch/powerpc/lib/ppccache.S
@@ -65,7 +65,7 @@ ppcSync:
  * flush_dcache_range(unsigned long start, unsigned long stop)
  */
 _GLOBAL(flush_dcache_range)
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
        li      r5,L1_CACHE_BYTES-1
        andc    r3,r3,r5
        subf    r4,r3,r4
@@ -89,7 +89,7 @@ _GLOBAL(flush_dcache_range)
  * invalidate_dcache_range(unsigned long start, unsigned long stop)
  */
 _GLOBAL(invalidate_dcache_range)
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
        li      r5,L1_CACHE_BYTES-1
        andc    r3,r3,r5
        subf    r4,r3,r4

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 52792dc..af20cf0 100644 (file)
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -543,6 +543,13 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
                pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
        }
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
+       /* The Read-Only Write Enable bit defaults to 1 instead of 0.
+        * Set to 0 to protect the read-only registers.
+        */
+       clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
+#endif
+
        /* Use generic setup_device to initialize standard pci regs,
         * but do not allocate any windows since any BAR found (such
         * as PCSRBAR) is not in this cpu's memory space.